Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 22:48:35.593170 lava-dispatcher, installed at version: 2024.01
2 22:48:35.593430 start: 0 validate
3 22:48:35.593630 Start time: 2024-05-07 22:48:35.593622+00:00 (UTC)
4 22:48:35.593761 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:48:35.593894 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:48:35.853469 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:48:35.854124 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:49:16.390766 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:49:16.391544 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:49:16.645169 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:49:16.645997 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:49:17.148798 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:49:17.149597 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:49:19.166481 validate duration: 43.57
16 22:49:19.166724 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:49:19.166815 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:49:19.166899 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:49:19.167019 Not decompressing ramdisk as can be used compressed.
20 22:49:19.167099 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 22:49:19.167163 saving as /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/ramdisk/initrd.cpio.gz
22 22:49:19.167223 total size: 5628182 (5 MB)
23 22:49:19.425168 progress 0 % (0 MB)
24 22:49:19.426913 progress 5 % (0 MB)
25 22:49:19.428487 progress 10 % (0 MB)
26 22:49:19.429921 progress 15 % (0 MB)
27 22:49:19.431475 progress 20 % (1 MB)
28 22:49:19.432910 progress 25 % (1 MB)
29 22:49:19.434507 progress 30 % (1 MB)
30 22:49:19.436029 progress 35 % (1 MB)
31 22:49:19.437381 progress 40 % (2 MB)
32 22:49:19.438943 progress 45 % (2 MB)
33 22:49:19.440296 progress 50 % (2 MB)
34 22:49:19.441868 progress 55 % (2 MB)
35 22:49:19.443382 progress 60 % (3 MB)
36 22:49:19.444866 progress 65 % (3 MB)
37 22:49:19.446500 progress 70 % (3 MB)
38 22:49:19.447850 progress 75 % (4 MB)
39 22:49:19.449358 progress 80 % (4 MB)
40 22:49:19.450746 progress 85 % (4 MB)
41 22:49:19.452258 progress 90 % (4 MB)
42 22:49:19.453807 progress 95 % (5 MB)
43 22:49:19.455173 progress 100 % (5 MB)
44 22:49:19.455375 5 MB downloaded in 0.29 s (18.63 MB/s)
45 22:49:19.455529 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:49:19.455761 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:49:19.455845 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:49:19.455927 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:49:19.456063 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:49:19.456129 saving as /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/kernel/Image
52 22:49:19.456190 total size: 54682112 (52 MB)
53 22:49:19.456249 No compression specified
54 22:49:19.457332 progress 0 % (0 MB)
55 22:49:19.471130 progress 5 % (2 MB)
56 22:49:19.484831 progress 10 % (5 MB)
57 22:49:19.498608 progress 15 % (7 MB)
58 22:49:19.512484 progress 20 % (10 MB)
59 22:49:19.526358 progress 25 % (13 MB)
60 22:49:19.540325 progress 30 % (15 MB)
61 22:49:19.554608 progress 35 % (18 MB)
62 22:49:19.568327 progress 40 % (20 MB)
63 22:49:19.582124 progress 45 % (23 MB)
64 22:49:19.595869 progress 50 % (26 MB)
65 22:49:19.609442 progress 55 % (28 MB)
66 22:49:19.623488 progress 60 % (31 MB)
67 22:49:19.637461 progress 65 % (33 MB)
68 22:49:19.651425 progress 70 % (36 MB)
69 22:49:19.665306 progress 75 % (39 MB)
70 22:49:19.679260 progress 80 % (41 MB)
71 22:49:19.692959 progress 85 % (44 MB)
72 22:49:19.706685 progress 90 % (46 MB)
73 22:49:19.720432 progress 95 % (49 MB)
74 22:49:19.734253 progress 100 % (52 MB)
75 22:49:19.734512 52 MB downloaded in 0.28 s (187.37 MB/s)
76 22:49:19.734673 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:49:19.734904 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:49:19.734989 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:49:19.735074 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:49:19.735210 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:49:19.735286 saving as /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/dtb/mt8192-asurada-spherion-r0.dtb
83 22:49:19.735348 total size: 47258 (0 MB)
84 22:49:19.735408 No compression specified
85 22:49:19.736515 progress 69 % (0 MB)
86 22:49:19.736799 progress 100 % (0 MB)
87 22:49:19.736953 0 MB downloaded in 0.00 s (28.12 MB/s)
88 22:49:19.737071 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:49:19.737285 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:49:19.737369 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:49:19.737450 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:49:19.737600 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 22:49:19.737665 saving as /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/nfsrootfs/full.rootfs.tar
95 22:49:19.737723 total size: 107552908 (102 MB)
96 22:49:19.737782 Using unxz to decompress xz
97 22:49:19.741753 progress 0 % (0 MB)
98 22:49:20.020577 progress 5 % (5 MB)
99 22:49:20.334306 progress 10 % (10 MB)
100 22:49:20.645825 progress 15 % (15 MB)
101 22:49:20.984375 progress 20 % (20 MB)
102 22:49:21.253457 progress 25 % (25 MB)
103 22:49:21.543257 progress 30 % (30 MB)
104 22:49:21.858620 progress 35 % (35 MB)
105 22:49:22.024096 progress 40 % (41 MB)
106 22:49:22.218013 progress 45 % (46 MB)
107 22:49:22.537607 progress 50 % (51 MB)
108 22:49:22.870258 progress 55 % (56 MB)
109 22:49:23.212858 progress 60 % (61 MB)
110 22:49:23.541068 progress 65 % (66 MB)
111 22:49:23.877759 progress 70 % (71 MB)
112 22:49:24.202987 progress 75 % (76 MB)
113 22:49:24.512917 progress 80 % (82 MB)
114 22:49:24.820036 progress 85 % (87 MB)
115 22:49:25.122852 progress 90 % (92 MB)
116 22:49:25.423089 progress 95 % (97 MB)
117 22:49:25.756427 progress 100 % (102 MB)
118 22:49:25.761653 102 MB downloaded in 6.02 s (17.03 MB/s)
119 22:49:25.761910 end: 1.4.1 http-download (duration 00:00:06) [common]
121 22:49:25.762182 end: 1.4 download-retry (duration 00:00:06) [common]
122 22:49:25.762270 start: 1.5 download-retry (timeout 00:09:53) [common]
123 22:49:25.762357 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 22:49:25.762502 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:49:25.762571 saving as /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/modules/modules.tar
126 22:49:25.762631 total size: 8594396 (8 MB)
127 22:49:25.762693 Using unxz to decompress xz
128 22:49:25.766840 progress 0 % (0 MB)
129 22:49:25.786870 progress 5 % (0 MB)
130 22:49:25.813620 progress 10 % (0 MB)
131 22:49:25.839053 progress 15 % (1 MB)
132 22:49:25.863630 progress 20 % (1 MB)
133 22:49:25.888493 progress 25 % (2 MB)
134 22:49:25.913344 progress 30 % (2 MB)
135 22:49:25.937523 progress 35 % (2 MB)
136 22:49:25.963254 progress 40 % (3 MB)
137 22:49:25.989100 progress 45 % (3 MB)
138 22:49:26.014291 progress 50 % (4 MB)
139 22:49:26.040492 progress 55 % (4 MB)
140 22:49:26.067662 progress 60 % (4 MB)
141 22:49:26.093133 progress 65 % (5 MB)
142 22:49:26.118661 progress 70 % (5 MB)
143 22:49:26.143620 progress 75 % (6 MB)
144 22:49:26.170793 progress 80 % (6 MB)
145 22:49:26.198050 progress 85 % (6 MB)
146 22:49:26.228047 progress 90 % (7 MB)
147 22:49:26.258341 progress 95 % (7 MB)
148 22:49:26.284406 progress 100 % (8 MB)
149 22:49:26.289514 8 MB downloaded in 0.53 s (15.56 MB/s)
150 22:49:26.289781 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:49:26.290060 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:49:26.290152 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 22:49:26.290247 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 22:49:28.330905 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13683708/extract-nfsrootfs-3ye22qzo
156 22:49:28.331102 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 22:49:28.331203 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 22:49:28.331359 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm
159 22:49:28.331485 makedir: /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin
160 22:49:28.331584 makedir: /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/tests
161 22:49:28.331681 makedir: /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/results
162 22:49:28.331779 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-add-keys
163 22:49:28.331916 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-add-sources
164 22:49:28.332041 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-background-process-start
165 22:49:28.332164 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-background-process-stop
166 22:49:28.332286 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-common-functions
167 22:49:28.332406 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-echo-ipv4
168 22:49:28.332527 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-install-packages
169 22:49:28.332646 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-installed-packages
170 22:49:28.332765 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-os-build
171 22:49:28.332882 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-probe-channel
172 22:49:28.333000 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-probe-ip
173 22:49:28.333118 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-target-ip
174 22:49:28.333236 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-target-mac
175 22:49:28.333354 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-target-storage
176 22:49:28.333475 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-test-case
177 22:49:28.333600 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-test-event
178 22:49:28.333720 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-test-feedback
179 22:49:28.333840 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-test-raise
180 22:49:28.333959 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-test-reference
181 22:49:28.334078 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-test-runner
182 22:49:28.334196 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-test-set
183 22:49:28.334314 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-test-shell
184 22:49:28.334435 Updating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-install-packages (oe)
185 22:49:28.334579 Updating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/bin/lava-installed-packages (oe)
186 22:49:28.334696 Creating /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/environment
187 22:49:28.334788 LAVA metadata
188 22:49:28.334855 - LAVA_JOB_ID=13683708
189 22:49:28.334917 - LAVA_DISPATCHER_IP=192.168.201.1
190 22:49:28.335014 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 22:49:28.335079 skipped lava-vland-overlay
192 22:49:28.335150 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 22:49:28.335228 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 22:49:28.335288 skipped lava-multinode-overlay
195 22:49:28.335357 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 22:49:28.335430 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 22:49:28.335500 Loading test definitions
198 22:49:28.335582 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 22:49:28.335650 Using /lava-13683708 at stage 0
200 22:49:28.335957 uuid=13683708_1.6.2.3.1 testdef=None
201 22:49:28.336045 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 22:49:28.336128 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 22:49:28.336622 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 22:49:28.336834 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 22:49:28.337471 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 22:49:28.337759 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 22:49:28.338383 runner path: /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/0/tests/0_dmesg test_uuid 13683708_1.6.2.3.1
210 22:49:28.338538 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 22:49:28.338735 Creating lava-test-runner.conf files
213 22:49:28.338795 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683708/lava-overlay-6rqjxqjm/lava-13683708/0 for stage 0
214 22:49:28.338881 - 0_dmesg
215 22:49:28.338973 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 22:49:28.339054 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 22:49:28.344778 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 22:49:28.344881 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 22:49:28.344964 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 22:49:28.345048 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 22:49:28.345130 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 22:49:28.511923 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 22:49:28.512352 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 22:49:28.512473 extracting modules file /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683708/extract-nfsrootfs-3ye22qzo
225 22:49:28.724475 extracting modules file /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683708/extract-overlay-ramdisk-8ufauzw2/ramdisk
226 22:49:28.943719 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 22:49:28.943899 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 22:49:28.943991 [common] Applying overlay to NFS
229 22:49:28.944059 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683708/compress-overlay-4p10_wa8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683708/extract-nfsrootfs-3ye22qzo
230 22:49:28.950598 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 22:49:28.950731 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 22:49:28.950841 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 22:49:28.950929 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 22:49:28.951009 Building ramdisk /var/lib/lava/dispatcher/tmp/13683708/extract-overlay-ramdisk-8ufauzw2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683708/extract-overlay-ramdisk-8ufauzw2/ramdisk
235 22:49:29.289802 >> 130327 blocks
236 22:49:31.376898 rename /var/lib/lava/dispatcher/tmp/13683708/extract-overlay-ramdisk-8ufauzw2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/ramdisk/ramdisk.cpio.gz
237 22:49:31.377413 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 22:49:31.377572 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 22:49:31.377682 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 22:49:31.377790 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/kernel/Image'
241 22:49:44.863997 Returned 0 in 13 seconds
242 22:49:44.964751 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/kernel/image.itb
243 22:49:45.340367 output: FIT description: Kernel Image image with one or more FDT blobs
244 22:49:45.340846 output: Created: Tue May 7 23:49:45 2024
245 22:49:45.340958 output: Image 0 (kernel-1)
246 22:49:45.341052 output: Description:
247 22:49:45.341144 output: Created: Tue May 7 23:49:45 2024
248 22:49:45.341238 output: Type: Kernel Image
249 22:49:45.341328 output: Compression: lzma compressed
250 22:49:45.341420 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
251 22:49:45.341522 output: Architecture: AArch64
252 22:49:45.341614 output: OS: Linux
253 22:49:45.341708 output: Load Address: 0x00000000
254 22:49:45.341800 output: Entry Point: 0x00000000
255 22:49:45.341890 output: Hash algo: crc32
256 22:49:45.341975 output: Hash value: 727ee7c6
257 22:49:45.342064 output: Image 1 (fdt-1)
258 22:49:45.342151 output: Description: mt8192-asurada-spherion-r0
259 22:49:45.342237 output: Created: Tue May 7 23:49:45 2024
260 22:49:45.342323 output: Type: Flat Device Tree
261 22:49:45.342410 output: Compression: uncompressed
262 22:49:45.342496 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 22:49:45.342582 output: Architecture: AArch64
264 22:49:45.342667 output: Hash algo: crc32
265 22:49:45.342752 output: Hash value: 0f8e4d2e
266 22:49:45.342835 output: Image 2 (ramdisk-1)
267 22:49:45.342921 output: Description: unavailable
268 22:49:45.343006 output: Created: Tue May 7 23:49:45 2024
269 22:49:45.343092 output: Type: RAMDisk Image
270 22:49:45.343179 output: Compression: Unknown Compression
271 22:49:45.343266 output: Data Size: 18730658 Bytes = 18291.66 KiB = 17.86 MiB
272 22:49:45.343352 output: Architecture: AArch64
273 22:49:45.343436 output: OS: Linux
274 22:49:45.343520 output: Load Address: unavailable
275 22:49:45.343604 output: Entry Point: unavailable
276 22:49:45.343689 output: Hash algo: crc32
277 22:49:45.343774 output: Hash value: 00958b34
278 22:49:45.343858 output: Default Configuration: 'conf-1'
279 22:49:45.343942 output: Configuration 0 (conf-1)
280 22:49:45.344025 output: Description: mt8192-asurada-spherion-r0
281 22:49:45.344109 output: Kernel: kernel-1
282 22:49:45.344193 output: Init Ramdisk: ramdisk-1
283 22:49:45.344278 output: FDT: fdt-1
284 22:49:45.344361 output: Loadables: kernel-1
285 22:49:45.344445 output:
286 22:49:45.344719 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 22:49:45.344857 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 22:49:45.345000 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 22:49:45.345139 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
290 22:49:45.345258 No LXC device requested
291 22:49:45.345376 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 22:49:45.345512 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
293 22:49:45.345631 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 22:49:45.345739 Checking files for TFTP limit of 4294967296 bytes.
295 22:49:45.346431 end: 1 tftp-deploy (duration 00:00:26) [common]
296 22:49:45.346572 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 22:49:45.346698 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 22:49:45.346874 substitutions:
299 22:49:45.346971 - {DTB}: 13683708/tftp-deploy-okay74ba/dtb/mt8192-asurada-spherion-r0.dtb
300 22:49:45.347065 - {INITRD}: 13683708/tftp-deploy-okay74ba/ramdisk/ramdisk.cpio.gz
301 22:49:45.347154 - {KERNEL}: 13683708/tftp-deploy-okay74ba/kernel/Image
302 22:49:45.347242 - {LAVA_MAC}: None
303 22:49:45.347329 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13683708/extract-nfsrootfs-3ye22qzo
304 22:49:45.347416 - {NFS_SERVER_IP}: 192.168.201.1
305 22:49:45.347501 - {PRESEED_CONFIG}: None
306 22:49:45.347587 - {PRESEED_LOCAL}: None
307 22:49:45.347671 - {RAMDISK}: 13683708/tftp-deploy-okay74ba/ramdisk/ramdisk.cpio.gz
308 22:49:45.347756 - {ROOT_PART}: None
309 22:49:45.347843 - {ROOT}: None
310 22:49:45.347928 - {SERVER_IP}: 192.168.201.1
311 22:49:45.348012 - {TEE}: None
312 22:49:45.348098 Parsed boot commands:
313 22:49:45.348181 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 22:49:45.348428 Parsed boot commands: tftpboot 192.168.201.1 13683708/tftp-deploy-okay74ba/kernel/image.itb 13683708/tftp-deploy-okay74ba/kernel/cmdline
315 22:49:45.348553 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 22:49:45.348677 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 22:49:45.348810 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 22:49:45.348938 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 22:49:45.349044 Not connected, no need to disconnect.
320 22:49:45.349153 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 22:49:45.349270 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 22:49:45.349374 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
323 22:49:45.354066 Setting prompt string to ['lava-test: # ']
324 22:49:45.354585 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 22:49:45.354744 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 22:49:45.354912 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 22:49:45.355040 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 22:49:45.355337 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
329 22:49:50.488635 >> Command sent successfully.
330 22:49:50.491138 Returned 0 in 5 seconds
331 22:49:50.591578 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 22:49:50.591929 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 22:49:50.592028 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 22:49:50.592116 Setting prompt string to 'Starting depthcharge on Spherion...'
336 22:49:50.592184 Changing prompt to 'Starting depthcharge on Spherion...'
337 22:49:50.592247 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 22:49:50.592518 [Enter `^Ec?' for help]
339 22:49:50.764055
340 22:49:50.764226
341 22:49:50.764300 F0: 102B 0000
342 22:49:50.764368
343 22:49:50.764429 F3: 1001 0000 [0200]
344 22:49:50.767092
345 22:49:50.767178 F3: 1001 0000
346 22:49:50.767244
347 22:49:50.767305 F7: 102D 0000
348 22:49:50.767364
349 22:49:50.770881 F1: 0000 0000
350 22:49:50.770967
351 22:49:50.771032 V0: 0000 0000 [0001]
352 22:49:50.771097
353 22:49:50.774098 00: 0007 8000
354 22:49:50.774185
355 22:49:50.774249 01: 0000 0000
356 22:49:50.774313
357 22:49:50.777424 BP: 0C00 0209 [0000]
358 22:49:50.777541
359 22:49:50.777610 G0: 1182 0000
360 22:49:50.777671
361 22:49:50.780900 EC: 0000 0021 [4000]
362 22:49:50.780987
363 22:49:50.781053 S7: 0000 0000 [0000]
364 22:49:50.781113
365 22:49:50.785066 CC: 0000 0000 [0001]
366 22:49:50.785161
367 22:49:50.785229 T0: 0000 0040 [010F]
368 22:49:50.785290
369 22:49:50.785348 Jump to BL
370 22:49:50.785405
371 22:49:50.811619
372 22:49:50.811780
373 22:49:50.811853
374 22:49:50.818954 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 22:49:50.822294 ARM64: Exception handlers installed.
376 22:49:50.825996 ARM64: Testing exception
377 22:49:50.829202 ARM64: Done test exception
378 22:49:50.835941 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 22:49:50.845968 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 22:49:50.852594 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 22:49:50.863304 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 22:49:50.869891 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 22:49:50.876351 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 22:49:50.887674 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 22:49:50.894394 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 22:49:50.913868 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 22:49:50.916963 WDT: Last reset was cold boot
388 22:49:50.920500 SPI1(PAD0) initialized at 2873684 Hz
389 22:49:50.923878 SPI5(PAD0) initialized at 992727 Hz
390 22:49:50.927121 VBOOT: Loading verstage.
391 22:49:50.933702 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 22:49:50.937401 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 22:49:50.940511 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 22:49:50.943967 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 22:49:50.951333 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 22:49:50.957980 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 22:49:50.968753 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 22:49:50.968904
399 22:49:50.968974
400 22:49:50.978933 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 22:49:50.982115 ARM64: Exception handlers installed.
402 22:49:50.985690 ARM64: Testing exception
403 22:49:50.985794 ARM64: Done test exception
404 22:49:50.992683 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 22:49:50.995650 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 22:49:51.010254 Probing TPM: . done!
407 22:49:51.010415 TPM ready after 0 ms
408 22:49:51.016366 Connected to device vid:did:rid of 1ae0:0028:00
409 22:49:51.023535 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 22:49:51.064935 Initialized TPM device CR50 revision 0
411 22:49:51.076983 tlcl_send_startup: Startup return code is 0
412 22:49:51.077143 TPM: setup succeeded
413 22:49:51.088061 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 22:49:51.096878 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 22:49:51.108740 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 22:49:51.117823 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 22:49:51.121192 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 22:49:51.124799 in-header: 03 07 00 00 08 00 00 00
419 22:49:51.127851 in-data: aa e4 47 04 13 02 00 00
420 22:49:51.131433 Chrome EC: UHEPI supported
421 22:49:51.138688 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 22:49:51.142263 in-header: 03 9d 00 00 08 00 00 00
423 22:49:51.146192 in-data: 10 20 20 08 00 00 00 00
424 22:49:51.146313 Phase 1
425 22:49:51.149456 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 22:49:51.157093 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 22:49:51.164292 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 22:49:51.164438 Recovery requested (1009000e)
429 22:49:51.173329 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 22:49:51.177884 tlcl_extend: response is 0
431 22:49:51.186133 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 22:49:51.191587 tlcl_extend: response is 0
433 22:49:51.198088 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 22:49:51.219384 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 22:49:51.226779 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 22:49:51.226932
437 22:49:51.227031
438 22:49:51.234269 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 22:49:51.237971 ARM64: Exception handlers installed.
440 22:49:51.241795 ARM64: Testing exception
441 22:49:51.244957 ARM64: Done test exception
442 22:49:51.265130 pmic_efuse_setting: Set efuses in 11 msecs
443 22:49:51.268197 pmwrap_interface_init: Select PMIF_VLD_RDY
444 22:49:51.272285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 22:49:51.279796 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 22:49:51.283906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 22:49:51.287226 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 22:49:51.294227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 22:49:51.298036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 22:49:51.302250 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 22:49:51.305972 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 22:49:51.312306 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 22:49:51.316072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 22:49:51.322359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 22:49:51.325789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 22:49:51.328989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 22:49:51.336203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 22:49:51.342684 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 22:49:51.348966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 22:49:51.352841 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 22:49:51.359077 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 22:49:51.366217 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 22:49:51.370220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 22:49:51.377071 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 22:49:51.381255 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 22:49:51.387786 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 22:49:51.391364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 22:49:51.398201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 22:49:51.404840 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 22:49:51.408685 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 22:49:51.412498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 22:49:51.419426 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 22:49:51.422775 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 22:49:51.430175 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 22:49:51.433780 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 22:49:51.437198 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 22:49:51.444580 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 22:49:51.448160 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 22:49:51.451781 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 22:49:51.458284 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 22:49:51.462070 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 22:49:51.468651 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 22:49:51.471856 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 22:49:51.475277 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 22:49:51.481872 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 22:49:51.485029 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 22:49:51.488235 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 22:49:51.494874 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 22:49:51.498195 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 22:49:51.501909 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 22:49:51.508467 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 22:49:51.511560 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 22:49:51.514734 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 22:49:51.518500 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 22:49:51.528698 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 22:49:51.535195 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 22:49:51.541756 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 22:49:51.548484 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 22:49:51.558187 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 22:49:51.562005 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 22:49:51.565027 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 22:49:51.571490 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 22:49:51.578096 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x35
504 22:49:51.581367 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 22:49:51.588961 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
506 22:49:51.592250 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 22:49:51.601403 [RTC]rtc_get_frequency_meter,154: input=15, output=793
508 22:49:51.604881 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
509 22:49:51.611684 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
510 22:49:51.615342 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
511 22:49:51.618355 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
512 22:49:51.621737 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
513 22:49:51.625072 ADC[4]: Raw value=897780 ID=7
514 22:49:51.628914 ADC[3]: Raw value=213440 ID=1
515 22:49:51.629023 RAM Code: 0x71
516 22:49:51.635120 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
517 22:49:51.638424 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
518 22:49:51.648339 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
519 22:49:51.655780 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
520 22:49:51.659192 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
521 22:49:51.662392 in-header: 03 07 00 00 08 00 00 00
522 22:49:51.665678 in-data: aa e4 47 04 13 02 00 00
523 22:49:51.665761 Chrome EC: UHEPI supported
524 22:49:51.672350 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
525 22:49:51.676346 in-header: 03 d5 00 00 08 00 00 00
526 22:49:51.680348 in-data: 98 20 60 08 00 00 00 00
527 22:49:51.684012 MRC: failed to locate region type 0.
528 22:49:51.691882 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
529 22:49:51.694638 DRAM-K: Running full calibration
530 22:49:51.701283 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
531 22:49:51.701377 header.status = 0x0
532 22:49:51.704736 header.version = 0x6 (expected: 0x6)
533 22:49:51.708091 header.size = 0xd00 (expected: 0xd00)
534 22:49:51.711610 header.flags = 0x0
535 22:49:51.715172 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
536 22:49:51.733455 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
537 22:49:51.740532 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
538 22:49:51.743895 dram_init: ddr_geometry: 2
539 22:49:51.747038 [EMI] MDL number = 2
540 22:49:51.747123 [EMI] Get MDL freq = 0
541 22:49:51.750774 dram_init: ddr_type: 0
542 22:49:51.750858 is_discrete_lpddr4: 1
543 22:49:51.753756 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
544 22:49:51.753839
545 22:49:51.753904
546 22:49:51.757221 [Bian_co] ETT version 0.0.0.1
547 22:49:51.763809 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
548 22:49:51.763898
549 22:49:51.767194 dramc_set_vcore_voltage set vcore to 650000
550 22:49:51.767278 Read voltage for 800, 4
551 22:49:51.770408 Vio18 = 0
552 22:49:51.770491 Vcore = 650000
553 22:49:51.770557 Vdram = 0
554 22:49:51.773633 Vddq = 0
555 22:49:51.773716 Vmddr = 0
556 22:49:51.777240 dram_init: config_dvfs: 1
557 22:49:51.780376 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
558 22:49:51.787388 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
559 22:49:51.790381 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
560 22:49:51.793543 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
561 22:49:51.796757 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
562 22:49:51.800295 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
563 22:49:51.803604 MEM_TYPE=3, freq_sel=18
564 22:49:51.806893 sv_algorithm_assistance_LP4_1600
565 22:49:51.810437 ============ PULL DRAM RESETB DOWN ============
566 22:49:51.813414 ========== PULL DRAM RESETB DOWN end =========
567 22:49:51.820439 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
568 22:49:51.823563 ===================================
569 22:49:51.827032 LPDDR4 DRAM CONFIGURATION
570 22:49:51.830200 ===================================
571 22:49:51.830286 EX_ROW_EN[0] = 0x0
572 22:49:51.833618 EX_ROW_EN[1] = 0x0
573 22:49:51.833703 LP4Y_EN = 0x0
574 22:49:51.836947 WORK_FSP = 0x0
575 22:49:51.837032 WL = 0x2
576 22:49:51.840227 RL = 0x2
577 22:49:51.840310 BL = 0x2
578 22:49:51.843364 RPST = 0x0
579 22:49:51.843447 RD_PRE = 0x0
580 22:49:51.847054 WR_PRE = 0x1
581 22:49:51.847139 WR_PST = 0x0
582 22:49:51.850379 DBI_WR = 0x0
583 22:49:51.850463 DBI_RD = 0x0
584 22:49:51.853681 OTF = 0x1
585 22:49:51.857255 ===================================
586 22:49:51.860287 ===================================
587 22:49:51.860372 ANA top config
588 22:49:51.863616 ===================================
589 22:49:51.866878 DLL_ASYNC_EN = 0
590 22:49:51.870355 ALL_SLAVE_EN = 1
591 22:49:51.873636 NEW_RANK_MODE = 1
592 22:49:51.873721 DLL_IDLE_MODE = 1
593 22:49:51.877049 LP45_APHY_COMB_EN = 1
594 22:49:51.879902 TX_ODT_DIS = 1
595 22:49:51.883792 NEW_8X_MODE = 1
596 22:49:51.886981 ===================================
597 22:49:51.890445 ===================================
598 22:49:51.893470 data_rate = 1600
599 22:49:51.893580 CKR = 1
600 22:49:51.896768 DQ_P2S_RATIO = 8
601 22:49:51.900841 ===================================
602 22:49:51.903604 CA_P2S_RATIO = 8
603 22:49:51.906906 DQ_CA_OPEN = 0
604 22:49:51.910053 DQ_SEMI_OPEN = 0
605 22:49:51.913481 CA_SEMI_OPEN = 0
606 22:49:51.913594 CA_FULL_RATE = 0
607 22:49:51.916732 DQ_CKDIV4_EN = 1
608 22:49:51.920152 CA_CKDIV4_EN = 1
609 22:49:51.923815 CA_PREDIV_EN = 0
610 22:49:51.927487 PH8_DLY = 0
611 22:49:51.927577 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
612 22:49:51.930931 DQ_AAMCK_DIV = 4
613 22:49:51.934424 CA_AAMCK_DIV = 4
614 22:49:51.938201 CA_ADMCK_DIV = 4
615 22:49:51.938291 DQ_TRACK_CA_EN = 0
616 22:49:51.941953 CA_PICK = 800
617 22:49:51.946041 CA_MCKIO = 800
618 22:49:51.949468 MCKIO_SEMI = 0
619 22:49:51.952923 PLL_FREQ = 3068
620 22:49:51.953013 DQ_UI_PI_RATIO = 32
621 22:49:51.956696 CA_UI_PI_RATIO = 0
622 22:49:51.960370 ===================================
623 22:49:51.964085 ===================================
624 22:49:51.967415 memory_type:LPDDR4
625 22:49:51.967501 GP_NUM : 10
626 22:49:51.971215 SRAM_EN : 1
627 22:49:51.971304 MD32_EN : 0
628 22:49:51.974919 ===================================
629 22:49:51.978995 [ANA_INIT] >>>>>>>>>>>>>>
630 22:49:51.982750 <<<<<< [CONFIGURE PHASE]: ANA_TX
631 22:49:51.982846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
632 22:49:51.986303 ===================================
633 22:49:51.990410 data_rate = 1600,PCW = 0X7600
634 22:49:51.994092 ===================================
635 22:49:51.997296 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
636 22:49:52.001118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
637 22:49:52.008968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
638 22:49:52.012345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
639 22:49:52.015620 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
640 22:49:52.019731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
641 22:49:52.022967 [ANA_INIT] flow start
642 22:49:52.023058 [ANA_INIT] PLL >>>>>>>>
643 22:49:52.026672 [ANA_INIT] PLL <<<<<<<<
644 22:49:52.026757 [ANA_INIT] MIDPI >>>>>>>>
645 22:49:52.030821 [ANA_INIT] MIDPI <<<<<<<<
646 22:49:52.034589 [ANA_INIT] DLL >>>>>>>>
647 22:49:52.034682 [ANA_INIT] flow end
648 22:49:52.038840 ============ LP4 DIFF to SE enter ============
649 22:49:52.042094 ============ LP4 DIFF to SE exit ============
650 22:49:52.045433 [ANA_INIT] <<<<<<<<<<<<<
651 22:49:52.049643 [Flow] Enable top DCM control >>>>>
652 22:49:52.053272 [Flow] Enable top DCM control <<<<<
653 22:49:52.053359 Enable DLL master slave shuffle
654 22:49:52.060776 ==============================================================
655 22:49:52.060875 Gating Mode config
656 22:49:52.067348 ==============================================================
657 22:49:52.070507 Config description:
658 22:49:52.081084 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
659 22:49:52.083971 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
660 22:49:52.090665 SELPH_MODE 0: By rank 1: By Phase
661 22:49:52.097539 ==============================================================
662 22:49:52.097649 GAT_TRACK_EN = 1
663 22:49:52.100905 RX_GATING_MODE = 2
664 22:49:52.104432 RX_GATING_TRACK_MODE = 2
665 22:49:52.107488 SELPH_MODE = 1
666 22:49:52.110533 PICG_EARLY_EN = 1
667 22:49:52.114251 VALID_LAT_VALUE = 1
668 22:49:52.120778 ==============================================================
669 22:49:52.124244 Enter into Gating configuration >>>>
670 22:49:52.127272 Exit from Gating configuration <<<<
671 22:49:52.130685 Enter into DVFS_PRE_config >>>>>
672 22:49:52.140699 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
673 22:49:52.144471 Exit from DVFS_PRE_config <<<<<
674 22:49:52.147508 Enter into PICG configuration >>>>
675 22:49:52.151063 Exit from PICG configuration <<<<
676 22:49:52.154266 [RX_INPUT] configuration >>>>>
677 22:49:52.154353 [RX_INPUT] configuration <<<<<
678 22:49:52.160842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
679 22:49:52.167410 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
680 22:49:52.170745 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
681 22:49:52.177441 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
682 22:49:52.184379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
683 22:49:52.190645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
684 22:49:52.194050 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
685 22:49:52.197694 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
686 22:49:52.204339 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
687 22:49:52.207606 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
688 22:49:52.210735 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
689 22:49:52.214032 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
690 22:49:52.217873 ===================================
691 22:49:52.221067 LPDDR4 DRAM CONFIGURATION
692 22:49:52.224102 ===================================
693 22:49:52.227541 EX_ROW_EN[0] = 0x0
694 22:49:52.227630 EX_ROW_EN[1] = 0x0
695 22:49:52.230810 LP4Y_EN = 0x0
696 22:49:52.230894 WORK_FSP = 0x0
697 22:49:52.234752 WL = 0x2
698 22:49:52.234837 RL = 0x2
699 22:49:52.238206 BL = 0x2
700 22:49:52.238290 RPST = 0x0
701 22:49:52.241562 RD_PRE = 0x0
702 22:49:52.241646 WR_PRE = 0x1
703 22:49:52.245254 WR_PST = 0x0
704 22:49:52.245338 DBI_WR = 0x0
705 22:49:52.249444 DBI_RD = 0x0
706 22:49:52.249550 OTF = 0x1
707 22:49:52.252493 ===================================
708 22:49:52.256253 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
709 22:49:52.260460 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
710 22:49:52.264035 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
711 22:49:52.267738 ===================================
712 22:49:52.270808 LPDDR4 DRAM CONFIGURATION
713 22:49:52.274576 ===================================
714 22:49:52.274661 EX_ROW_EN[0] = 0x10
715 22:49:52.277834 EX_ROW_EN[1] = 0x0
716 22:49:52.281450 LP4Y_EN = 0x0
717 22:49:52.281575 WORK_FSP = 0x0
718 22:49:52.281643 WL = 0x2
719 22:49:52.285410 RL = 0x2
720 22:49:52.285493 BL = 0x2
721 22:49:52.288858 RPST = 0x0
722 22:49:52.288941 RD_PRE = 0x0
723 22:49:52.292479 WR_PRE = 0x1
724 22:49:52.292561 WR_PST = 0x0
725 22:49:52.296004 DBI_WR = 0x0
726 22:49:52.296089 DBI_RD = 0x0
727 22:49:52.299905 OTF = 0x1
728 22:49:52.303522 ===================================
729 22:49:52.306925 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
730 22:49:52.312214 nWR fixed to 40
731 22:49:52.316179 [ModeRegInit_LP4] CH0 RK0
732 22:49:52.316268 [ModeRegInit_LP4] CH0 RK1
733 22:49:52.320063 [ModeRegInit_LP4] CH1 RK0
734 22:49:52.320148 [ModeRegInit_LP4] CH1 RK1
735 22:49:52.323589 match AC timing 13
736 22:49:52.327359 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
737 22:49:52.330680 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
738 22:49:52.334592 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
739 22:49:52.342193 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
740 22:49:52.345329 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
741 22:49:52.345416 [EMI DOE] emi_dcm 0
742 22:49:52.353427 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
743 22:49:52.353529 ==
744 22:49:52.353598 Dram Type= 6, Freq= 0, CH_0, rank 0
745 22:49:52.360908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
746 22:49:52.361002 ==
747 22:49:52.364436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
748 22:49:52.371218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
749 22:49:52.380180 [CA 0] Center 38 (7~69) winsize 63
750 22:49:52.383478 [CA 1] Center 38 (7~69) winsize 63
751 22:49:52.387174 [CA 2] Center 35 (5~66) winsize 62
752 22:49:52.391046 [CA 3] Center 35 (5~66) winsize 62
753 22:49:52.394304 [CA 4] Center 34 (4~65) winsize 62
754 22:49:52.397903 [CA 5] Center 34 (3~65) winsize 63
755 22:49:52.397994
756 22:49:52.401642 [CmdBusTrainingLP45] Vref(ca) range 1: 34
757 22:49:52.401730
758 22:49:52.405283 [CATrainingPosCal] consider 1 rank data
759 22:49:52.405374 u2DelayCellTimex100 = 270/100 ps
760 22:49:52.412283 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
761 22:49:52.415697 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
762 22:49:52.419856 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
763 22:49:52.423193 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
764 22:49:52.427102 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
765 22:49:52.430486 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
766 22:49:52.430583
767 22:49:52.434241 CA PerBit enable=1, Macro0, CA PI delay=34
768 22:49:52.434329
769 22:49:52.434394 [CBTSetCACLKResult] CA Dly = 34
770 22:49:52.438341 CS Dly: 6 (0~37)
771 22:49:52.438429 ==
772 22:49:52.441719 Dram Type= 6, Freq= 0, CH_0, rank 1
773 22:49:52.445142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:49:52.445237 ==
775 22:49:52.452106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
776 22:49:52.455946 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
777 22:49:52.466027 [CA 0] Center 38 (7~69) winsize 63
778 22:49:52.469803 [CA 1] Center 38 (7~69) winsize 63
779 22:49:52.473292 [CA 2] Center 35 (5~66) winsize 62
780 22:49:52.476955 [CA 3] Center 35 (5~66) winsize 62
781 22:49:52.480742 [CA 4] Center 34 (4~65) winsize 62
782 22:49:52.484711 [CA 5] Center 34 (4~65) winsize 62
783 22:49:52.484811
784 22:49:52.487766 [CmdBusTrainingLP45] Vref(ca) range 1: 34
785 22:49:52.487869
786 22:49:52.491977 [CATrainingPosCal] consider 2 rank data
787 22:49:52.492141 u2DelayCellTimex100 = 270/100 ps
788 22:49:52.495707 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
789 22:49:52.499363 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
790 22:49:52.503177 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
791 22:49:52.506269 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
792 22:49:52.510531 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
793 22:49:52.513536 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
794 22:49:52.513657
795 22:49:52.517763 CA PerBit enable=1, Macro0, CA PI delay=34
796 22:49:52.517858
797 22:49:52.521495 [CBTSetCACLKResult] CA Dly = 34
798 22:49:52.525448 CS Dly: 6 (0~37)
799 22:49:52.525563
800 22:49:52.529218 ----->DramcWriteLeveling(PI) begin...
801 22:49:52.529311 ==
802 22:49:52.533269 Dram Type= 6, Freq= 0, CH_0, rank 0
803 22:49:52.536399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 22:49:52.536490 ==
805 22:49:52.536557 Write leveling (Byte 0): 33 => 33
806 22:49:52.539879 Write leveling (Byte 1): 28 => 28
807 22:49:52.543377 DramcWriteLeveling(PI) end<-----
808 22:49:52.543475
809 22:49:52.543542 ==
810 22:49:52.546824 Dram Type= 6, Freq= 0, CH_0, rank 0
811 22:49:52.553634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
812 22:49:52.553758 ==
813 22:49:52.553827 [Gating] SW mode calibration
814 22:49:52.563266 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
815 22:49:52.566503 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
816 22:49:52.569903 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
817 22:49:52.576694 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
818 22:49:52.580055 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
819 22:49:52.583553 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
820 22:49:52.590038 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:49:52.593077 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 22:49:52.596625 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:49:52.603472 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:49:52.607004 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:49:52.610564 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:49:52.614187 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:49:52.621225 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:49:52.624446 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 22:49:52.628117 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 22:49:52.631712 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 22:49:52.638757 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 22:49:52.642021 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 22:49:52.645071 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 22:49:52.651878 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
835 22:49:52.655029 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 22:49:52.658959 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 22:49:52.665278 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 22:49:52.669358 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 22:49:52.672286 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 22:49:52.678474 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 22:49:52.682461 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 22:49:52.685383 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 22:49:52.688611 0 9 12 | B1->B0 | 2323 3232 | 1 0 | (1 1) (0 0)
844 22:49:52.695174 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
845 22:49:52.698932 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
846 22:49:52.702061 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
847 22:49:52.708476 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 22:49:52.712083 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 22:49:52.715488 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 22:49:52.721898 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
851 22:49:52.725519 0 10 12 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
852 22:49:52.728632 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 22:49:52.735332 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 22:49:52.739146 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 22:49:52.741874 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 22:49:52.748798 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:49:52.752217 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:49:52.755532 0 11 8 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (0 0)
859 22:49:52.762249 0 11 12 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
860 22:49:52.765436 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
861 22:49:52.768738 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 22:49:52.772141 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 22:49:52.778576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 22:49:52.782381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 22:49:52.785334 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 22:49:52.792061 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
867 22:49:52.795543 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
868 22:49:52.798873 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 22:49:52.805505 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 22:49:52.809118 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 22:49:52.812540 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 22:49:52.818845 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 22:49:52.822042 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 22:49:52.825455 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 22:49:52.832084 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 22:49:52.835471 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 22:49:52.838932 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 22:49:52.845542 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 22:49:52.848744 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 22:49:52.851973 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 22:49:52.858492 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 22:49:52.861746 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 22:49:52.865201 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
884 22:49:52.869748 Total UI for P1: 0, mck2ui 16
885 22:49:52.871860 best dqsien dly found for B0: ( 0, 14, 10)
886 22:49:52.875467 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 22:49:52.878706 Total UI for P1: 0, mck2ui 16
888 22:49:52.882022 best dqsien dly found for B1: ( 0, 14, 12)
889 22:49:52.885113 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
890 22:49:52.891960 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
891 22:49:52.892110
892 22:49:52.895342 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
893 22:49:52.898973 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
894 22:49:52.901923 [Gating] SW calibration Done
895 22:49:52.902040 ==
896 22:49:52.905184 Dram Type= 6, Freq= 0, CH_0, rank 0
897 22:49:52.908938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 22:49:52.909024 ==
899 22:49:52.912024 RX Vref Scan: 0
900 22:49:52.912109
901 22:49:52.912173 RX Vref 0 -> 0, step: 1
902 22:49:52.912234
903 22:49:52.915345 RX Delay -130 -> 252, step: 16
904 22:49:52.918465 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
905 22:49:52.921848 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
906 22:49:52.928976 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
907 22:49:52.931929 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
908 22:49:52.935412 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
909 22:49:52.938878 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
910 22:49:52.942038 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
911 22:49:52.948906 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
912 22:49:52.951865 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
913 22:49:52.955481 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
914 22:49:52.958603 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
915 22:49:52.961986 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
916 22:49:52.968955 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
917 22:49:52.971849 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
918 22:49:52.975537 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
919 22:49:52.978853 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
920 22:49:52.978943 ==
921 22:49:52.981780 Dram Type= 6, Freq= 0, CH_0, rank 0
922 22:49:52.988781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 22:49:52.988970 ==
924 22:49:52.989040 DQS Delay:
925 22:49:52.991674 DQS0 = 0, DQS1 = 0
926 22:49:52.991758 DQM Delay:
927 22:49:52.991823 DQM0 = 81, DQM1 = 70
928 22:49:52.995407 DQ Delay:
929 22:49:52.998844 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
930 22:49:53.002061 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
931 22:49:53.005325 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
932 22:49:53.008448 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
933 22:49:53.008532
934 22:49:53.008597
935 22:49:53.008657 ==
936 22:49:53.012014 Dram Type= 6, Freq= 0, CH_0, rank 0
937 22:49:53.015830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
938 22:49:53.015922 ==
939 22:49:53.015994
940 22:49:53.016055
941 22:49:53.018917 TX Vref Scan disable
942 22:49:53.019002 == TX Byte 0 ==
943 22:49:53.025698 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
944 22:49:53.029273 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
945 22:49:53.029362 == TX Byte 1 ==
946 22:49:53.035531 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
947 22:49:53.038784 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
948 22:49:53.038870 ==
949 22:49:53.042368 Dram Type= 6, Freq= 0, CH_0, rank 0
950 22:49:53.045634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 22:49:53.045719 ==
952 22:49:53.059857 TX Vref=22, minBit 0, minWin=27, winSum=441
953 22:49:53.063036 TX Vref=24, minBit 11, minWin=26, winSum=438
954 22:49:53.066368 TX Vref=26, minBit 11, minWin=26, winSum=442
955 22:49:53.069794 TX Vref=28, minBit 1, minWin=28, winSum=451
956 22:49:53.073160 TX Vref=30, minBit 4, minWin=27, winSum=447
957 22:49:53.080107 TX Vref=32, minBit 5, minWin=27, winSum=446
958 22:49:53.083143 [TxChooseVref] Worse bit 1, Min win 28, Win sum 451, Final Vref 28
959 22:49:53.083233
960 22:49:53.086125 Final TX Range 1 Vref 28
961 22:49:53.086209
962 22:49:53.086275 ==
963 22:49:53.089500 Dram Type= 6, Freq= 0, CH_0, rank 0
964 22:49:53.092967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
965 22:49:53.096077 ==
966 22:49:53.096161
967 22:49:53.096226
968 22:49:53.096286 TX Vref Scan disable
969 22:49:53.099743 == TX Byte 0 ==
970 22:49:53.103436 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
971 22:49:53.109995 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
972 22:49:53.110105 == TX Byte 1 ==
973 22:49:53.113308 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
974 22:49:53.117041 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
975 22:49:53.120108
976 22:49:53.120193 [DATLAT]
977 22:49:53.120259 Freq=800, CH0 RK0
978 22:49:53.120322
979 22:49:53.122994 DATLAT Default: 0xa
980 22:49:53.123078 0, 0xFFFF, sum = 0
981 22:49:53.126378 1, 0xFFFF, sum = 0
982 22:49:53.126467 2, 0xFFFF, sum = 0
983 22:49:53.130238 3, 0xFFFF, sum = 0
984 22:49:53.130323 4, 0xFFFF, sum = 0
985 22:49:53.133484 5, 0xFFFF, sum = 0
986 22:49:53.133605 6, 0xFFFF, sum = 0
987 22:49:53.136815 7, 0xFFFF, sum = 0
988 22:49:53.140206 8, 0xFFFF, sum = 0
989 22:49:53.140290 9, 0x0, sum = 1
990 22:49:53.140357 10, 0x0, sum = 2
991 22:49:53.143502 11, 0x0, sum = 3
992 22:49:53.143586 12, 0x0, sum = 4
993 22:49:53.146575 best_step = 10
994 22:49:53.146658
995 22:49:53.146723 ==
996 22:49:53.149886 Dram Type= 6, Freq= 0, CH_0, rank 0
997 22:49:53.153292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 22:49:53.153379 ==
999 22:49:53.156562 RX Vref Scan: 1
1000 22:49:53.156645
1001 22:49:53.156709 Set Vref Range= 32 -> 127
1002 22:49:53.156770
1003 22:49:53.160165 RX Vref 32 -> 127, step: 1
1004 22:49:53.160250
1005 22:49:53.163302 RX Delay -111 -> 252, step: 8
1006 22:49:53.163384
1007 22:49:53.166885 Set Vref, RX VrefLevel [Byte0]: 32
1008 22:49:53.169950 [Byte1]: 32
1009 22:49:53.170035
1010 22:49:53.173529 Set Vref, RX VrefLevel [Byte0]: 33
1011 22:49:53.176676 [Byte1]: 33
1012 22:49:53.180600
1013 22:49:53.180684 Set Vref, RX VrefLevel [Byte0]: 34
1014 22:49:53.183888 [Byte1]: 34
1015 22:49:53.188087
1016 22:49:53.188173 Set Vref, RX VrefLevel [Byte0]: 35
1017 22:49:53.191267 [Byte1]: 35
1018 22:49:53.195934
1019 22:49:53.196021 Set Vref, RX VrefLevel [Byte0]: 36
1020 22:49:53.199139 [Byte1]: 36
1021 22:49:53.203434
1022 22:49:53.203521 Set Vref, RX VrefLevel [Byte0]: 37
1023 22:49:53.206668 [Byte1]: 37
1024 22:49:53.210948
1025 22:49:53.211051 Set Vref, RX VrefLevel [Byte0]: 38
1026 22:49:53.214989 [Byte1]: 38
1027 22:49:53.218785
1028 22:49:53.218869 Set Vref, RX VrefLevel [Byte0]: 39
1029 22:49:53.222316 [Byte1]: 39
1030 22:49:53.226147
1031 22:49:53.226231 Set Vref, RX VrefLevel [Byte0]: 40
1032 22:49:53.229754 [Byte1]: 40
1033 22:49:53.233722
1034 22:49:53.233806 Set Vref, RX VrefLevel [Byte0]: 41
1035 22:49:53.237369 [Byte1]: 41
1036 22:49:53.241536
1037 22:49:53.241620 Set Vref, RX VrefLevel [Byte0]: 42
1038 22:49:53.245104 [Byte1]: 42
1039 22:49:53.249472
1040 22:49:53.249572 Set Vref, RX VrefLevel [Byte0]: 43
1041 22:49:53.252548 [Byte1]: 43
1042 22:49:53.257132
1043 22:49:53.257214 Set Vref, RX VrefLevel [Byte0]: 44
1044 22:49:53.260649 [Byte1]: 44
1045 22:49:53.264376
1046 22:49:53.264459 Set Vref, RX VrefLevel [Byte0]: 45
1047 22:49:53.268250 [Byte1]: 45
1048 22:49:53.272379
1049 22:49:53.272469 Set Vref, RX VrefLevel [Byte0]: 46
1050 22:49:53.275685 [Byte1]: 46
1051 22:49:53.280129
1052 22:49:53.280221 Set Vref, RX VrefLevel [Byte0]: 47
1053 22:49:53.283373 [Byte1]: 47
1054 22:49:53.287588
1055 22:49:53.287675 Set Vref, RX VrefLevel [Byte0]: 48
1056 22:49:53.291592 [Byte1]: 48
1057 22:49:53.296006
1058 22:49:53.296097 Set Vref, RX VrefLevel [Byte0]: 49
1059 22:49:53.299009 [Byte1]: 49
1060 22:49:53.302680
1061 22:49:53.302770 Set Vref, RX VrefLevel [Byte0]: 50
1062 22:49:53.305943 [Byte1]: 50
1063 22:49:53.310498
1064 22:49:53.310593 Set Vref, RX VrefLevel [Byte0]: 51
1065 22:49:53.313970 [Byte1]: 51
1066 22:49:53.318281
1067 22:49:53.318365 Set Vref, RX VrefLevel [Byte0]: 52
1068 22:49:53.321256 [Byte1]: 52
1069 22:49:53.325928
1070 22:49:53.326016 Set Vref, RX VrefLevel [Byte0]: 53
1071 22:49:53.329167 [Byte1]: 53
1072 22:49:53.333118
1073 22:49:53.333202 Set Vref, RX VrefLevel [Byte0]: 54
1074 22:49:53.336777 [Byte1]: 54
1075 22:49:53.341015
1076 22:49:53.341100 Set Vref, RX VrefLevel [Byte0]: 55
1077 22:49:53.344438 [Byte1]: 55
1078 22:49:53.348614
1079 22:49:53.348698 Set Vref, RX VrefLevel [Byte0]: 56
1080 22:49:53.351932 [Byte1]: 56
1081 22:49:53.355988
1082 22:49:53.356072 Set Vref, RX VrefLevel [Byte0]: 57
1083 22:49:53.359339 [Byte1]: 57
1084 22:49:53.363685
1085 22:49:53.363769 Set Vref, RX VrefLevel [Byte0]: 58
1086 22:49:53.367576 [Byte1]: 58
1087 22:49:53.371564
1088 22:49:53.371648 Set Vref, RX VrefLevel [Byte0]: 59
1089 22:49:53.374699 [Byte1]: 59
1090 22:49:53.378901
1091 22:49:53.378985 Set Vref, RX VrefLevel [Byte0]: 60
1092 22:49:53.382499 [Byte1]: 60
1093 22:49:53.386785
1094 22:49:53.386871 Set Vref, RX VrefLevel [Byte0]: 61
1095 22:49:53.390384 [Byte1]: 61
1096 22:49:53.394466
1097 22:49:53.394573 Set Vref, RX VrefLevel [Byte0]: 62
1098 22:49:53.397912 [Byte1]: 62
1099 22:49:53.401910
1100 22:49:53.401995 Set Vref, RX VrefLevel [Byte0]: 63
1101 22:49:53.405288 [Byte1]: 63
1102 22:49:53.409554
1103 22:49:53.409642 Set Vref, RX VrefLevel [Byte0]: 64
1104 22:49:53.413393 [Byte1]: 64
1105 22:49:53.417284
1106 22:49:53.417374 Set Vref, RX VrefLevel [Byte0]: 65
1107 22:49:53.420680 [Byte1]: 65
1108 22:49:53.424990
1109 22:49:53.425074 Set Vref, RX VrefLevel [Byte0]: 66
1110 22:49:53.428234 [Byte1]: 66
1111 22:49:53.432658
1112 22:49:53.432743 Set Vref, RX VrefLevel [Byte0]: 67
1113 22:49:53.436007 [Byte1]: 67
1114 22:49:53.440510
1115 22:49:53.440594 Set Vref, RX VrefLevel [Byte0]: 68
1116 22:49:53.443574 [Byte1]: 68
1117 22:49:53.448029
1118 22:49:53.448113 Set Vref, RX VrefLevel [Byte0]: 69
1119 22:49:53.451039 [Byte1]: 69
1120 22:49:53.455395
1121 22:49:53.455478 Set Vref, RX VrefLevel [Byte0]: 70
1122 22:49:53.458740 [Byte1]: 70
1123 22:49:53.463308
1124 22:49:53.463393 Set Vref, RX VrefLevel [Byte0]: 71
1125 22:49:53.466643 [Byte1]: 71
1126 22:49:53.470979
1127 22:49:53.471062 Set Vref, RX VrefLevel [Byte0]: 72
1128 22:49:53.474008 [Byte1]: 72
1129 22:49:53.478851
1130 22:49:53.478936 Set Vref, RX VrefLevel [Byte0]: 73
1131 22:49:53.481933 [Byte1]: 73
1132 22:49:53.486193
1133 22:49:53.486278 Set Vref, RX VrefLevel [Byte0]: 74
1134 22:49:53.489666 [Byte1]: 74
1135 22:49:53.494023
1136 22:49:53.494109 Set Vref, RX VrefLevel [Byte0]: 75
1137 22:49:53.497116 [Byte1]: 75
1138 22:49:53.501261
1139 22:49:53.501345 Set Vref, RX VrefLevel [Byte0]: 76
1140 22:49:53.504478 [Byte1]: 76
1141 22:49:53.509043
1142 22:49:53.509153 Set Vref, RX VrefLevel [Byte0]: 77
1143 22:49:53.512576 [Byte1]: 77
1144 22:49:53.516999
1145 22:49:53.517086 Set Vref, RX VrefLevel [Byte0]: 78
1146 22:49:53.520242 [Byte1]: 78
1147 22:49:53.524625
1148 22:49:53.524709 Set Vref, RX VrefLevel [Byte0]: 79
1149 22:49:53.527823 [Byte1]: 79
1150 22:49:53.531957
1151 22:49:53.532060 Final RX Vref Byte 0 = 62 to rank0
1152 22:49:53.535221 Final RX Vref Byte 1 = 51 to rank0
1153 22:49:53.538695 Final RX Vref Byte 0 = 62 to rank1
1154 22:49:53.542181 Final RX Vref Byte 1 = 51 to rank1==
1155 22:49:53.545408 Dram Type= 6, Freq= 0, CH_0, rank 0
1156 22:49:53.551877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 22:49:53.551965 ==
1158 22:49:53.552036 DQS Delay:
1159 22:49:53.552095 DQS0 = 0, DQS1 = 0
1160 22:49:53.555521 DQM Delay:
1161 22:49:53.555627 DQM0 = 82, DQM1 = 68
1162 22:49:53.558673 DQ Delay:
1163 22:49:53.562059 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1164 22:49:53.562140 DQ4 =80, DQ5 =72, DQ6 =88, DQ7 =92
1165 22:49:53.565283 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1166 22:49:53.568572 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =76
1167 22:49:53.572233
1168 22:49:53.572316
1169 22:49:53.578928 [DQSOSCAuto] RK0, (LSB)MR18= 0x2423, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1170 22:49:53.582289 CH0 RK0: MR19=606, MR18=2423
1171 22:49:53.588622 CH0_RK0: MR19=0x606, MR18=0x2423, DQSOSC=400, MR23=63, INC=92, DEC=61
1172 22:49:53.588713
1173 22:49:53.591864 ----->DramcWriteLeveling(PI) begin...
1174 22:49:53.591949 ==
1175 22:49:53.595160 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 22:49:53.598684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 22:49:53.598769 ==
1178 22:49:53.602062 Write leveling (Byte 0): 30 => 30
1179 22:49:53.605024 Write leveling (Byte 1): 30 => 30
1180 22:49:53.608570 DramcWriteLeveling(PI) end<-----
1181 22:49:53.608655
1182 22:49:53.608720 ==
1183 22:49:53.611882 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 22:49:53.615250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 22:49:53.615341 ==
1186 22:49:53.618309 [Gating] SW mode calibration
1187 22:49:53.625233 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1188 22:49:53.631887 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1189 22:49:53.635283 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 22:49:53.638680 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1191 22:49:53.645556 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1192 22:49:53.648901 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1193 22:49:53.652058 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:49:53.658864 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:49:53.661889 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:49:53.665462 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:49:53.672098 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 22:49:53.675447 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 22:49:53.678762 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 22:49:53.685345 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:49:53.688791 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 22:49:53.732929 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 22:49:53.733125 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:49:53.733222 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:49:53.733497 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 22:49:53.733606 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1207 22:49:53.733698 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1208 22:49:53.733815 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 22:49:53.733930 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 22:49:53.734047 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 22:49:53.734136 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 22:49:53.737422 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 22:49:53.740731 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 22:49:53.744275 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 22:49:53.751015 0 9 8 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (1 1)
1216 22:49:53.754113 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1217 22:49:53.757920 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 22:49:53.764360 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 22:49:53.767836 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 22:49:53.771217 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 22:49:53.777665 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 22:49:53.780934 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 1)
1223 22:49:53.784062 0 10 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (0 0)
1224 22:49:53.787691 0 10 12 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
1225 22:49:53.794594 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:49:53.797346 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:49:53.800983 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:49:53.807728 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:49:53.810827 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:49:53.813984 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1231 22:49:53.820882 0 11 8 | B1->B0 | 2e2e 4343 | 0 1 | (0 0) (0 0)
1232 22:49:53.824482 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1233 22:49:53.827611 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 22:49:53.833840 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 22:49:53.837319 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 22:49:53.840879 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 22:49:53.844419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 22:49:53.852313 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1239 22:49:53.855407 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1240 22:49:53.859645 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1241 22:49:53.862856 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 22:49:53.869747 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 22:49:53.872661 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 22:49:53.876669 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 22:49:53.879818 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 22:49:53.886535 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 22:49:53.890216 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 22:49:53.893517 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 22:49:53.899666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 22:49:53.903367 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 22:49:53.906653 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 22:49:53.913434 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 22:49:53.916692 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 22:49:53.919907 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1255 22:49:53.926631 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1256 22:49:53.930035 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 22:49:53.933285 Total UI for P1: 0, mck2ui 16
1258 22:49:53.936287 best dqsien dly found for B0: ( 0, 14, 6)
1259 22:49:53.940204 Total UI for P1: 0, mck2ui 16
1260 22:49:53.943026 best dqsien dly found for B1: ( 0, 14, 8)
1261 22:49:53.946858 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1262 22:49:53.949985 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1263 22:49:53.950067
1264 22:49:53.953353 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1265 22:49:53.956714 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1266 22:49:53.959749 [Gating] SW calibration Done
1267 22:49:53.959831 ==
1268 22:49:53.963304 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 22:49:53.966723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 22:49:53.966807 ==
1271 22:49:53.970376 RX Vref Scan: 0
1272 22:49:53.970458
1273 22:49:53.973137 RX Vref 0 -> 0, step: 1
1274 22:49:53.973218
1275 22:49:53.973282 RX Delay -130 -> 252, step: 16
1276 22:49:53.980008 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1277 22:49:53.982982 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1278 22:49:53.986362 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1279 22:49:53.990255 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1280 22:49:53.993031 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1281 22:49:53.999616 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1282 22:49:54.003396 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1283 22:49:54.006641 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1284 22:49:54.009881 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1285 22:49:54.013245 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1286 22:49:54.019814 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1287 22:49:54.023433 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1288 22:49:54.026587 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1289 22:49:54.029878 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1290 22:49:54.033342 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1291 22:49:54.039722 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1292 22:49:54.039812 ==
1293 22:49:54.043060 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 22:49:54.046185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 22:49:54.046270 ==
1296 22:49:54.046333 DQS Delay:
1297 22:49:54.050001 DQS0 = 0, DQS1 = 0
1298 22:49:54.050136 DQM Delay:
1299 22:49:54.053367 DQM0 = 78, DQM1 = 70
1300 22:49:54.053450 DQ Delay:
1301 22:49:54.056582 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1302 22:49:54.060063 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
1303 22:49:54.063349 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =61
1304 22:49:54.066541 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1305 22:49:54.066623
1306 22:49:54.066688
1307 22:49:54.066747 ==
1308 22:49:54.070018 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 22:49:54.073026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 22:49:54.073109 ==
1311 22:49:54.073173
1312 22:49:54.076686
1313 22:49:54.076768 TX Vref Scan disable
1314 22:49:54.080040 == TX Byte 0 ==
1315 22:49:54.083295 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1316 22:49:54.086513 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1317 22:49:54.089686 == TX Byte 1 ==
1318 22:49:54.093370 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1319 22:49:54.096875 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1320 22:49:54.096959 ==
1321 22:49:54.099706 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 22:49:54.106366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 22:49:54.106452 ==
1324 22:49:54.117851 TX Vref=22, minBit 1, minWin=26, winSum=435
1325 22:49:54.121722 TX Vref=24, minBit 11, minWin=26, winSum=437
1326 22:49:54.124578 TX Vref=26, minBit 12, minWin=26, winSum=436
1327 22:49:54.128057 TX Vref=28, minBit 1, minWin=27, winSum=442
1328 22:49:54.131255 TX Vref=30, minBit 1, minWin=27, winSum=446
1329 22:49:54.138019 TX Vref=32, minBit 7, minWin=27, winSum=441
1330 22:49:54.141359 [TxChooseVref] Worse bit 1, Min win 27, Win sum 446, Final Vref 30
1331 22:49:54.141448
1332 22:49:54.144849 Final TX Range 1 Vref 30
1333 22:49:54.144931
1334 22:49:54.144995 ==
1335 22:49:54.148097 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 22:49:54.151425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 22:49:54.151507 ==
1338 22:49:54.154489
1339 22:49:54.154587
1340 22:49:54.154652 TX Vref Scan disable
1341 22:49:54.158369 == TX Byte 0 ==
1342 22:49:54.161501 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1343 22:49:54.164853 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1344 22:49:54.167859 == TX Byte 1 ==
1345 22:49:54.171409 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1346 22:49:54.174667 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1347 22:49:54.177790
1348 22:49:54.177871 [DATLAT]
1349 22:49:54.177935 Freq=800, CH0 RK1
1350 22:49:54.177995
1351 22:49:54.181188 DATLAT Default: 0xa
1352 22:49:54.181268 0, 0xFFFF, sum = 0
1353 22:49:54.184728 1, 0xFFFF, sum = 0
1354 22:49:54.184810 2, 0xFFFF, sum = 0
1355 22:49:54.188166 3, 0xFFFF, sum = 0
1356 22:49:54.188248 4, 0xFFFF, sum = 0
1357 22:49:54.191678 5, 0xFFFF, sum = 0
1358 22:49:54.194567 6, 0xFFFF, sum = 0
1359 22:49:54.194649 7, 0xFFFF, sum = 0
1360 22:49:54.198047 8, 0xFFFF, sum = 0
1361 22:49:54.198130 9, 0x0, sum = 1
1362 22:49:54.198195 10, 0x0, sum = 2
1363 22:49:54.201482 11, 0x0, sum = 3
1364 22:49:54.201602 12, 0x0, sum = 4
1365 22:49:54.204794 best_step = 10
1366 22:49:54.204874
1367 22:49:54.204937 ==
1368 22:49:54.208011 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 22:49:54.211437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 22:49:54.211520 ==
1371 22:49:54.214738 RX Vref Scan: 0
1372 22:49:54.214818
1373 22:49:54.214881 RX Vref 0 -> 0, step: 1
1374 22:49:54.214941
1375 22:49:54.217935 RX Delay -111 -> 252, step: 8
1376 22:49:54.224590 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1377 22:49:54.228475 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1378 22:49:54.231590 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1379 22:49:54.234731 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1380 22:49:54.237899 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1381 22:49:54.244680 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1382 22:49:54.247993 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1383 22:49:54.251941 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1384 22:49:54.255027 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1385 22:49:54.258023 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1386 22:49:54.264919 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1387 22:49:54.268516 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1388 22:49:54.271583 iDelay=209, Bit 12, Center 76 (-39 ~ 192) 232
1389 22:49:54.274733 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1390 22:49:54.277970 iDelay=209, Bit 14, Center 76 (-39 ~ 192) 232
1391 22:49:54.285033 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1392 22:49:54.285126 ==
1393 22:49:54.288237 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 22:49:54.291299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 22:49:54.291382 ==
1396 22:49:54.291445 DQS Delay:
1397 22:49:54.294557 DQS0 = 0, DQS1 = 0
1398 22:49:54.294652 DQM Delay:
1399 22:49:54.297897 DQM0 = 79, DQM1 = 69
1400 22:49:54.297976 DQ Delay:
1401 22:49:54.301554 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1402 22:49:54.304798 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1403 22:49:54.308435 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1404 22:49:54.311189 DQ12 =76, DQ13 =80, DQ14 =76, DQ15 =76
1405 22:49:54.311270
1406 22:49:54.311334
1407 22:49:54.321343 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1408 22:49:54.321456 CH0 RK1: MR19=606, MR18=4C27
1409 22:49:54.328246 CH0_RK1: MR19=0x606, MR18=0x4C27, DQSOSC=390, MR23=63, INC=97, DEC=64
1410 22:49:54.331209 [RxdqsGatingPostProcess] freq 800
1411 22:49:54.337858 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1412 22:49:54.341413 Pre-setting of DQS Precalculation
1413 22:49:54.344860 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1414 22:49:54.344942 ==
1415 22:49:54.348133 Dram Type= 6, Freq= 0, CH_1, rank 0
1416 22:49:54.351496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 22:49:54.351579 ==
1418 22:49:54.358281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 22:49:54.364485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 22:49:54.373324 [CA 0] Center 36 (6~67) winsize 62
1421 22:49:54.376761 [CA 1] Center 37 (7~67) winsize 61
1422 22:49:54.380003 [CA 2] Center 34 (4~64) winsize 61
1423 22:49:54.383049 [CA 3] Center 34 (4~64) winsize 61
1424 22:49:54.386408 [CA 4] Center 34 (4~65) winsize 62
1425 22:49:54.389787 [CA 5] Center 34 (4~64) winsize 61
1426 22:49:54.389870
1427 22:49:54.393096 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1428 22:49:54.393178
1429 22:49:54.396338 [CATrainingPosCal] consider 1 rank data
1430 22:49:54.399866 u2DelayCellTimex100 = 270/100 ps
1431 22:49:54.403210 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 22:49:54.406311 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1433 22:49:54.413049 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 22:49:54.416638 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1435 22:49:54.419927 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 22:49:54.423190 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1437 22:49:54.423271
1438 22:49:54.426426 CA PerBit enable=1, Macro0, CA PI delay=34
1439 22:49:54.426506
1440 22:49:54.429788 [CBTSetCACLKResult] CA Dly = 34
1441 22:49:54.429868 CS Dly: 5 (0~36)
1442 22:49:54.429931 ==
1443 22:49:54.433299 Dram Type= 6, Freq= 0, CH_1, rank 1
1444 22:49:54.439869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 22:49:54.439954 ==
1446 22:49:54.443127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 22:49:54.449446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 22:49:54.459353 [CA 0] Center 37 (7~67) winsize 61
1449 22:49:54.462641 [CA 1] Center 37 (7~67) winsize 61
1450 22:49:54.466056 [CA 2] Center 35 (5~65) winsize 61
1451 22:49:54.469433 [CA 3] Center 34 (4~65) winsize 62
1452 22:49:54.472847 [CA 4] Center 34 (4~65) winsize 62
1453 22:49:54.475638 [CA 5] Center 33 (3~64) winsize 62
1454 22:49:54.475719
1455 22:49:54.479059 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1456 22:49:54.479140
1457 22:49:54.482338 [CATrainingPosCal] consider 2 rank data
1458 22:49:54.486120 u2DelayCellTimex100 = 270/100 ps
1459 22:49:54.488995 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1460 22:49:54.492289 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1461 22:49:54.498997 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1462 22:49:54.502379 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1463 22:49:54.506166 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 22:49:54.509853 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 22:49:54.509935
1466 22:49:54.513676 CA PerBit enable=1, Macro0, CA PI delay=34
1467 22:49:54.513762
1468 22:49:54.517309 [CBTSetCACLKResult] CA Dly = 34
1469 22:49:54.517391 CS Dly: 6 (0~38)
1470 22:49:54.517454
1471 22:49:54.520856 ----->DramcWriteLeveling(PI) begin...
1472 22:49:54.520937 ==
1473 22:49:54.524562 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 22:49:54.528236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 22:49:54.528319 ==
1476 22:49:54.531438 Write leveling (Byte 0): 27 => 27
1477 22:49:54.535603 Write leveling (Byte 1): 28 => 28
1478 22:49:54.539268 DramcWriteLeveling(PI) end<-----
1479 22:49:54.539352
1480 22:49:54.539415 ==
1481 22:49:54.543246 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 22:49:54.545891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1483 22:49:54.545974 ==
1484 22:49:54.549808 [Gating] SW mode calibration
1485 22:49:54.556022 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1486 22:49:54.559421 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1487 22:49:54.566061 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1488 22:49:54.570036 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1489 22:49:54.573291 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:49:54.579902 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:49:54.582682 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:49:54.586085 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:49:54.593281 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:49:54.596547 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:49:54.599890 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 22:49:54.603153 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 22:49:54.609875 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 22:49:54.612857 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:49:54.616146 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 22:49:54.622972 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 22:49:54.626322 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:49:54.629482 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 22:49:54.635911 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 22:49:54.639381 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 22:49:54.642910 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1506 22:49:54.649777 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 22:49:54.653626 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 22:49:54.656320 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 22:49:54.662332 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 22:49:54.665842 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 22:49:54.669223 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 22:49:54.675674 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 22:49:54.679448 0 9 8 | B1->B0 | 2424 2424 | 1 1 | (1 1) (1 1)
1514 22:49:54.682333 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 22:49:54.689021 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 22:49:54.692233 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 22:49:54.695510 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 22:49:54.702212 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 22:49:54.705690 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 22:49:54.709086 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
1521 22:49:54.715749 0 10 8 | B1->B0 | 2e2e 2d2d | 0 0 | (0 0) (1 0)
1522 22:49:54.719148 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:49:54.722424 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:49:54.728811 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:49:54.732642 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:49:54.735904 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:49:54.742651 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:49:54.745997 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:49:54.749177 0 11 8 | B1->B0 | 3535 3737 | 0 0 | (0 0) (0 0)
1530 22:49:54.752533 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 22:49:54.759087 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 22:49:54.762170 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 22:49:54.765453 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 22:49:54.772241 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 22:49:54.775388 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 22:49:54.779148 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 22:49:54.785462 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1538 22:49:54.789175 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 22:49:54.792446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 22:49:54.799017 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 22:49:54.802441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 22:49:54.805832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 22:49:54.812077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 22:49:54.815425 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 22:49:54.818862 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 22:49:54.825365 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 22:49:54.828660 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 22:49:54.832058 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 22:49:54.838948 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 22:49:54.842022 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 22:49:54.845710 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 22:49:54.852160 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1553 22:49:54.855403 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1554 22:49:54.858709 Total UI for P1: 0, mck2ui 16
1555 22:49:54.862158 best dqsien dly found for B0: ( 0, 14, 4)
1556 22:49:54.865320 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 22:49:54.868623 Total UI for P1: 0, mck2ui 16
1558 22:49:54.872012 best dqsien dly found for B1: ( 0, 14, 8)
1559 22:49:54.875429 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1560 22:49:54.878738 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1561 22:49:54.878824
1562 22:49:54.882363 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1563 22:49:54.885964 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1564 22:49:54.888950 [Gating] SW calibration Done
1565 22:49:54.889037 ==
1566 22:49:54.892466 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 22:49:54.895692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 22:49:54.898986 ==
1569 22:49:54.899074 RX Vref Scan: 0
1570 22:49:54.899139
1571 22:49:54.902455 RX Vref 0 -> 0, step: 1
1572 22:49:54.902539
1573 22:49:54.905838 RX Delay -130 -> 252, step: 16
1574 22:49:54.908770 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1575 22:49:54.912586 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1576 22:49:54.915414 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1577 22:49:54.918874 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1578 22:49:54.925779 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1579 22:49:54.929213 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1580 22:49:54.932220 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1581 22:49:54.935509 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1582 22:49:54.938878 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1583 22:49:54.945405 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1584 22:49:54.949031 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1585 22:49:54.951981 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1586 22:49:54.955321 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1587 22:49:54.959075 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1588 22:49:54.965236 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1589 22:49:54.969073 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1590 22:49:54.969159 ==
1591 22:49:54.972298 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 22:49:54.975741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 22:49:54.975823 ==
1594 22:49:54.979085 DQS Delay:
1595 22:49:54.979167 DQS0 = 0, DQS1 = 0
1596 22:49:54.979229 DQM Delay:
1597 22:49:54.981990 DQM0 = 81, DQM1 = 70
1598 22:49:54.982071 DQ Delay:
1599 22:49:54.985351 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1600 22:49:54.988755 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1601 22:49:54.992120 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1602 22:49:54.995631 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1603 22:49:54.995761
1604 22:49:54.995841
1605 22:49:54.995900 ==
1606 22:49:54.998959 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 22:49:55.005654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 22:49:55.005736 ==
1609 22:49:55.005799
1610 22:49:55.005857
1611 22:49:55.005913 TX Vref Scan disable
1612 22:49:55.009077 == TX Byte 0 ==
1613 22:49:55.012191 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1614 22:49:55.015604 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1615 22:49:55.018479 == TX Byte 1 ==
1616 22:49:55.021970 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1617 22:49:55.028798 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1618 22:49:55.028886 ==
1619 22:49:55.032352 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 22:49:55.035092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 22:49:55.035174 ==
1622 22:49:55.047487 TX Vref=22, minBit 1, minWin=27, winSum=441
1623 22:49:55.050876 TX Vref=24, minBit 1, minWin=27, winSum=443
1624 22:49:55.054645 TX Vref=26, minBit 1, minWin=27, winSum=446
1625 22:49:55.057473 TX Vref=28, minBit 5, minWin=27, winSum=447
1626 22:49:55.060968 TX Vref=30, minBit 6, minWin=27, winSum=450
1627 22:49:55.064584 TX Vref=32, minBit 0, minWin=27, winSum=448
1628 22:49:55.071176 [TxChooseVref] Worse bit 6, Min win 27, Win sum 450, Final Vref 30
1629 22:49:55.071273
1630 22:49:55.074336 Final TX Range 1 Vref 30
1631 22:49:55.074421
1632 22:49:55.074485 ==
1633 22:49:55.077804 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 22:49:55.081060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 22:49:55.081142 ==
1636 22:49:55.081206
1637 22:49:55.084432
1638 22:49:55.084513 TX Vref Scan disable
1639 22:49:55.088310 == TX Byte 0 ==
1640 22:49:55.091688 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1641 22:49:55.095198 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1642 22:49:55.098193 == TX Byte 1 ==
1643 22:49:55.101689 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1644 22:49:55.104966 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1645 22:49:55.105048
1646 22:49:55.108340 [DATLAT]
1647 22:49:55.108425 Freq=800, CH1 RK0
1648 22:49:55.108489
1649 22:49:55.111676 DATLAT Default: 0xa
1650 22:49:55.111757 0, 0xFFFF, sum = 0
1651 22:49:55.114994 1, 0xFFFF, sum = 0
1652 22:49:55.115079 2, 0xFFFF, sum = 0
1653 22:49:55.118313 3, 0xFFFF, sum = 0
1654 22:49:55.118395 4, 0xFFFF, sum = 0
1655 22:49:55.121678 5, 0xFFFF, sum = 0
1656 22:49:55.121760 6, 0xFFFF, sum = 0
1657 22:49:55.124787 7, 0xFFFF, sum = 0
1658 22:49:55.124868 8, 0xFFFF, sum = 0
1659 22:49:55.128317 9, 0x0, sum = 1
1660 22:49:55.128400 10, 0x0, sum = 2
1661 22:49:55.131879 11, 0x0, sum = 3
1662 22:49:55.131962 12, 0x0, sum = 4
1663 22:49:55.134974 best_step = 10
1664 22:49:55.135055
1665 22:49:55.135119 ==
1666 22:49:55.138199 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 22:49:55.141680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 22:49:55.141762 ==
1669 22:49:55.141826 RX Vref Scan: 1
1670 22:49:55.145056
1671 22:49:55.145136 Set Vref Range= 32 -> 127
1672 22:49:55.145199
1673 22:49:55.148647 RX Vref 32 -> 127, step: 1
1674 22:49:55.148728
1675 22:49:55.151503 RX Delay -111 -> 252, step: 8
1676 22:49:55.151585
1677 22:49:55.154877 Set Vref, RX VrefLevel [Byte0]: 32
1678 22:49:55.158421 [Byte1]: 32
1679 22:49:55.158503
1680 22:49:55.161664 Set Vref, RX VrefLevel [Byte0]: 33
1681 22:49:55.164775 [Byte1]: 33
1682 22:49:55.167891
1683 22:49:55.167972 Set Vref, RX VrefLevel [Byte0]: 34
1684 22:49:55.171246 [Byte1]: 34
1685 22:49:55.175594
1686 22:49:55.175675 Set Vref, RX VrefLevel [Byte0]: 35
1687 22:49:55.178909 [Byte1]: 35
1688 22:49:55.183252
1689 22:49:55.183363 Set Vref, RX VrefLevel [Byte0]: 36
1690 22:49:55.186698 [Byte1]: 36
1691 22:49:55.191117
1692 22:49:55.191199 Set Vref, RX VrefLevel [Byte0]: 37
1693 22:49:55.194546 [Byte1]: 37
1694 22:49:55.198506
1695 22:49:55.198588 Set Vref, RX VrefLevel [Byte0]: 38
1696 22:49:55.201933 [Byte1]: 38
1697 22:49:55.206526
1698 22:49:55.206608 Set Vref, RX VrefLevel [Byte0]: 39
1699 22:49:55.209475 [Byte1]: 39
1700 22:49:55.213908
1701 22:49:55.213997 Set Vref, RX VrefLevel [Byte0]: 40
1702 22:49:55.217167 [Byte1]: 40
1703 22:49:55.221661
1704 22:49:55.221744 Set Vref, RX VrefLevel [Byte0]: 41
1705 22:49:55.224890 [Byte1]: 41
1706 22:49:55.229290
1707 22:49:55.229374 Set Vref, RX VrefLevel [Byte0]: 42
1708 22:49:55.232507 [Byte1]: 42
1709 22:49:55.236853
1710 22:49:55.236933 Set Vref, RX VrefLevel [Byte0]: 43
1711 22:49:55.240350 [Byte1]: 43
1712 22:49:55.244585
1713 22:49:55.244667 Set Vref, RX VrefLevel [Byte0]: 44
1714 22:49:55.247846 [Byte1]: 44
1715 22:49:55.251919
1716 22:49:55.252000 Set Vref, RX VrefLevel [Byte0]: 45
1717 22:49:55.255381 [Byte1]: 45
1718 22:49:55.259610
1719 22:49:55.259692 Set Vref, RX VrefLevel [Byte0]: 46
1720 22:49:55.263150 [Byte1]: 46
1721 22:49:55.267554
1722 22:49:55.267635 Set Vref, RX VrefLevel [Byte0]: 47
1723 22:49:55.270533 [Byte1]: 47
1724 22:49:55.275300
1725 22:49:55.275383 Set Vref, RX VrefLevel [Byte0]: 48
1726 22:49:55.278489 [Byte1]: 48
1727 22:49:55.282950
1728 22:49:55.283034 Set Vref, RX VrefLevel [Byte0]: 49
1729 22:49:55.286121 [Byte1]: 49
1730 22:49:55.290551
1731 22:49:55.290633 Set Vref, RX VrefLevel [Byte0]: 50
1732 22:49:55.293920 [Byte1]: 50
1733 22:49:55.298043
1734 22:49:55.298125 Set Vref, RX VrefLevel [Byte0]: 51
1735 22:49:55.301495 [Byte1]: 51
1736 22:49:55.305461
1737 22:49:55.305552 Set Vref, RX VrefLevel [Byte0]: 52
1738 22:49:55.309013 [Byte1]: 52
1739 22:49:55.313488
1740 22:49:55.313638 Set Vref, RX VrefLevel [Byte0]: 53
1741 22:49:55.319952 [Byte1]: 53
1742 22:49:55.320038
1743 22:49:55.323418 Set Vref, RX VrefLevel [Byte0]: 54
1744 22:49:55.326341 [Byte1]: 54
1745 22:49:55.326423
1746 22:49:55.329588 Set Vref, RX VrefLevel [Byte0]: 55
1747 22:49:55.332987 [Byte1]: 55
1748 22:49:55.336397
1749 22:49:55.336478 Set Vref, RX VrefLevel [Byte0]: 56
1750 22:49:55.339720 [Byte1]: 56
1751 22:49:55.344148
1752 22:49:55.344228 Set Vref, RX VrefLevel [Byte0]: 57
1753 22:49:55.347300 [Byte1]: 57
1754 22:49:55.351382
1755 22:49:55.351463 Set Vref, RX VrefLevel [Byte0]: 58
1756 22:49:55.354700 [Byte1]: 58
1757 22:49:55.359309
1758 22:49:55.359390 Set Vref, RX VrefLevel [Byte0]: 59
1759 22:49:55.362563 [Byte1]: 59
1760 22:49:55.366816
1761 22:49:55.366897 Set Vref, RX VrefLevel [Byte0]: 60
1762 22:49:55.370248 [Byte1]: 60
1763 22:49:55.374536
1764 22:49:55.374616 Set Vref, RX VrefLevel [Byte0]: 61
1765 22:49:55.378127 [Byte1]: 61
1766 22:49:55.382403
1767 22:49:55.382484 Set Vref, RX VrefLevel [Byte0]: 62
1768 22:49:55.385544 [Byte1]: 62
1769 22:49:55.390110
1770 22:49:55.390190 Set Vref, RX VrefLevel [Byte0]: 63
1771 22:49:55.392875 [Byte1]: 63
1772 22:49:55.397970
1773 22:49:55.398081 Set Vref, RX VrefLevel [Byte0]: 64
1774 22:49:55.400796 [Byte1]: 64
1775 22:49:55.405299
1776 22:49:55.405379 Set Vref, RX VrefLevel [Byte0]: 65
1777 22:49:55.408595 [Byte1]: 65
1778 22:49:55.412489
1779 22:49:55.412570 Set Vref, RX VrefLevel [Byte0]: 66
1780 22:49:55.415987 [Byte1]: 66
1781 22:49:55.420498
1782 22:49:55.420580 Set Vref, RX VrefLevel [Byte0]: 67
1783 22:49:55.423723 [Byte1]: 67
1784 22:49:55.428057
1785 22:49:55.428140 Set Vref, RX VrefLevel [Byte0]: 68
1786 22:49:55.431623 [Byte1]: 68
1787 22:49:55.436086
1788 22:49:55.436166 Set Vref, RX VrefLevel [Byte0]: 69
1789 22:49:55.438779 [Byte1]: 69
1790 22:49:55.443337
1791 22:49:55.443417 Set Vref, RX VrefLevel [Byte0]: 70
1792 22:49:55.446650 [Byte1]: 70
1793 22:49:55.451234
1794 22:49:55.451315 Set Vref, RX VrefLevel [Byte0]: 71
1795 22:49:55.454517 [Byte1]: 71
1796 22:49:55.458445
1797 22:49:55.458526 Set Vref, RX VrefLevel [Byte0]: 72
1798 22:49:55.462284 [Byte1]: 72
1799 22:49:55.466314
1800 22:49:55.466394 Set Vref, RX VrefLevel [Byte0]: 73
1801 22:49:55.469550 [Byte1]: 73
1802 22:49:55.473928
1803 22:49:55.474009 Set Vref, RX VrefLevel [Byte0]: 74
1804 22:49:55.477176 [Byte1]: 74
1805 22:49:55.481904
1806 22:49:55.481985 Final RX Vref Byte 0 = 58 to rank0
1807 22:49:55.485030 Final RX Vref Byte 1 = 54 to rank0
1808 22:49:55.488177 Final RX Vref Byte 0 = 58 to rank1
1809 22:49:55.491680 Final RX Vref Byte 1 = 54 to rank1==
1810 22:49:55.495186 Dram Type= 6, Freq= 0, CH_1, rank 0
1811 22:49:55.501577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 22:49:55.501659 ==
1813 22:49:55.501724 DQS Delay:
1814 22:49:55.501783 DQS0 = 0, DQS1 = 0
1815 22:49:55.505000 DQM Delay:
1816 22:49:55.505081 DQM0 = 81, DQM1 = 71
1817 22:49:55.508313 DQ Delay:
1818 22:49:55.511903 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1819 22:49:55.511986 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1820 22:49:55.515059 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1821 22:49:55.518393 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =80
1822 22:49:55.518476
1823 22:49:55.521791
1824 22:49:55.528437 [DQSOSCAuto] RK0, (LSB)MR18= 0x1620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1825 22:49:55.531849 CH1 RK0: MR19=606, MR18=1620
1826 22:49:55.538560 CH1_RK0: MR19=0x606, MR18=0x1620, DQSOSC=401, MR23=63, INC=91, DEC=61
1827 22:49:55.538644
1828 22:49:55.541740 ----->DramcWriteLeveling(PI) begin...
1829 22:49:55.541822 ==
1830 22:49:55.545030 Dram Type= 6, Freq= 0, CH_1, rank 1
1831 22:49:55.548461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1832 22:49:55.548542 ==
1833 22:49:55.551823 Write leveling (Byte 0): 30 => 30
1834 22:49:55.555249 Write leveling (Byte 1): 30 => 30
1835 22:49:55.558508 DramcWriteLeveling(PI) end<-----
1836 22:49:55.558588
1837 22:49:55.558651 ==
1838 22:49:55.561669 Dram Type= 6, Freq= 0, CH_1, rank 1
1839 22:49:55.564909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 22:49:55.564990 ==
1841 22:49:55.568340 [Gating] SW mode calibration
1842 22:49:55.574898 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1843 22:49:55.581978 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1844 22:49:55.585277 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1845 22:49:55.588427 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1846 22:49:55.594944 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 22:49:55.598251 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 22:49:55.601415 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 22:49:55.608342 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:49:55.611536 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:49:55.615100 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:49:55.621625 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:49:55.624969 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:49:55.628389 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:49:55.631805 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:49:55.638263 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:49:55.641882 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 22:49:55.645083 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 22:49:55.651578 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 22:49:55.654881 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 22:49:55.658056 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1862 22:49:55.664755 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 22:49:55.668125 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 22:49:55.671762 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 22:49:55.678528 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 22:49:55.681717 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 22:49:55.685141 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 22:49:55.691704 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1869 22:49:55.695130 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
1870 22:49:55.698444 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1871 22:49:55.704655 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 22:49:55.708065 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 22:49:55.711486 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 22:49:55.718130 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 22:49:55.721268 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 22:49:55.724683 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1877 22:49:55.731701 0 10 4 | B1->B0 | 3131 2c2c | 1 0 | (1 1) (0 0)
1878 22:49:55.734776 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1879 22:49:55.738027 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:49:55.744777 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:49:55.748179 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:49:55.751496 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:49:55.754813 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:49:55.761539 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 22:49:55.764909 0 11 4 | B1->B0 | 2929 3a39 | 1 1 | (0 0) (0 0)
1886 22:49:55.768278 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1887 22:49:55.775041 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 22:49:55.778238 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 22:49:55.781351 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 22:49:55.788221 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 22:49:55.791357 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 22:49:55.794649 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 22:49:55.801424 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1894 22:49:55.804861 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 22:49:55.808227 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 22:49:55.814457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 22:49:55.818350 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 22:49:55.821213 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 22:49:55.828088 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 22:49:55.831331 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 22:49:55.834670 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 22:49:55.841455 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 22:49:55.844765 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 22:49:55.848125 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 22:49:55.851361 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 22:49:55.857990 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 22:49:55.861762 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 22:49:55.864597 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 22:49:55.871142 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1910 22:49:55.874981 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 22:49:55.877929 Total UI for P1: 0, mck2ui 16
1912 22:49:55.881476 best dqsien dly found for B0: ( 0, 14, 4)
1913 22:49:55.884608 Total UI for P1: 0, mck2ui 16
1914 22:49:55.887701 best dqsien dly found for B1: ( 0, 14, 4)
1915 22:49:55.891113 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1916 22:49:55.894409 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1917 22:49:55.894490
1918 22:49:55.897937 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1919 22:49:55.901381 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1920 22:49:55.904549 [Gating] SW calibration Done
1921 22:49:55.904669 ==
1922 22:49:55.907875 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 22:49:55.911299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 22:49:55.914648 ==
1925 22:49:55.914803 RX Vref Scan: 0
1926 22:49:55.914911
1927 22:49:55.917894 RX Vref 0 -> 0, step: 1
1928 22:49:55.917976
1929 22:49:55.921377 RX Delay -130 -> 252, step: 16
1930 22:49:55.924741 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1931 22:49:55.927622 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1932 22:49:55.931384 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1933 22:49:55.934235 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1934 22:49:55.941169 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1935 22:49:55.944231 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1936 22:49:55.947803 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1937 22:49:55.950848 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1938 22:49:55.954317 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1939 22:49:55.961101 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1940 22:49:55.964495 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1941 22:49:55.967856 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1942 22:49:55.971155 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1943 22:49:55.974239 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1944 22:49:55.980862 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1945 22:49:55.984741 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1946 22:49:55.984823 ==
1947 22:49:55.987951 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 22:49:55.990963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 22:49:55.991046 ==
1950 22:49:55.994673 DQS Delay:
1951 22:49:55.994755 DQS0 = 0, DQS1 = 0
1952 22:49:55.994819 DQM Delay:
1953 22:49:55.998108 DQM0 = 77, DQM1 = 72
1954 22:49:55.998190 DQ Delay:
1955 22:49:56.001111 DQ0 =77, DQ1 =69, DQ2 =61, DQ3 =77
1956 22:49:56.004251 DQ4 =69, DQ5 =93, DQ6 =93, DQ7 =77
1957 22:49:56.008008 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1958 22:49:56.010856 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1959 22:49:56.010938
1960 22:49:56.011001
1961 22:49:56.011060 ==
1962 22:49:56.014144 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 22:49:56.021320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 22:49:56.021405 ==
1965 22:49:56.021468
1966 22:49:56.021570
1967 22:49:56.021630 TX Vref Scan disable
1968 22:49:56.024263 == TX Byte 0 ==
1969 22:49:56.027739 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1970 22:49:56.034223 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1971 22:49:56.034306 == TX Byte 1 ==
1972 22:49:56.037491 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1973 22:49:56.044211 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1974 22:49:56.044292 ==
1975 22:49:56.047632 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 22:49:56.050706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 22:49:56.050811 ==
1978 22:49:56.063458 TX Vref=22, minBit 3, minWin=27, winSum=446
1979 22:49:56.066663 TX Vref=24, minBit 1, minWin=27, winSum=450
1980 22:49:56.069798 TX Vref=26, minBit 3, minWin=27, winSum=452
1981 22:49:56.072992 TX Vref=28, minBit 5, minWin=27, winSum=456
1982 22:49:56.076362 TX Vref=30, minBit 1, minWin=27, winSum=459
1983 22:49:56.082840 TX Vref=32, minBit 1, minWin=27, winSum=456
1984 22:49:56.086250 [TxChooseVref] Worse bit 1, Min win 27, Win sum 459, Final Vref 30
1985 22:49:56.086357
1986 22:49:56.089973 Final TX Range 1 Vref 30
1987 22:49:56.090056
1988 22:49:56.090120 ==
1989 22:49:56.092730 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 22:49:56.096277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 22:49:56.099391 ==
1992 22:49:56.099476
1993 22:49:56.099540
1994 22:49:56.099599 TX Vref Scan disable
1995 22:49:56.102944 == TX Byte 0 ==
1996 22:49:56.106289 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1997 22:49:56.109607 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1998 22:49:56.113138 == TX Byte 1 ==
1999 22:49:56.116315 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2000 22:49:56.120020 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2001 22:49:56.122929
2002 22:49:56.123009 [DATLAT]
2003 22:49:56.123074 Freq=800, CH1 RK1
2004 22:49:56.123134
2005 22:49:56.126393 DATLAT Default: 0xa
2006 22:49:56.126474 0, 0xFFFF, sum = 0
2007 22:49:56.129685 1, 0xFFFF, sum = 0
2008 22:49:56.129768 2, 0xFFFF, sum = 0
2009 22:49:56.132953 3, 0xFFFF, sum = 0
2010 22:49:56.133036 4, 0xFFFF, sum = 0
2011 22:49:56.136557 5, 0xFFFF, sum = 0
2012 22:49:56.139519 6, 0xFFFF, sum = 0
2013 22:49:56.139627 7, 0xFFFF, sum = 0
2014 22:49:56.142844 8, 0xFFFF, sum = 0
2015 22:49:56.142928 9, 0x0, sum = 1
2016 22:49:56.142994 10, 0x0, sum = 2
2017 22:49:56.146381 11, 0x0, sum = 3
2018 22:49:56.146464 12, 0x0, sum = 4
2019 22:49:56.149588 best_step = 10
2020 22:49:56.149668
2021 22:49:56.149733 ==
2022 22:49:56.153209 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 22:49:56.156429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 22:49:56.156514 ==
2025 22:49:56.159449 RX Vref Scan: 0
2026 22:49:56.159531
2027 22:49:56.159596 RX Vref 0 -> 0, step: 1
2028 22:49:56.159656
2029 22:49:56.162809 RX Delay -111 -> 252, step: 8
2030 22:49:56.170007 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2031 22:49:56.173134 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2032 22:49:56.176719 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2033 22:49:56.179639 iDelay=209, Bit 3, Center 76 (-47 ~ 200) 248
2034 22:49:56.182926 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2035 22:49:56.189591 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2036 22:49:56.192841 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2037 22:49:56.196273 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2038 22:49:56.199786 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2039 22:49:56.203254 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2040 22:49:56.209613 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2041 22:49:56.213053 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2042 22:49:56.216554 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2043 22:49:56.220046 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2044 22:49:56.226432 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2045 22:49:56.229806 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2046 22:49:56.229888 ==
2047 22:49:56.233192 Dram Type= 6, Freq= 0, CH_1, rank 1
2048 22:49:56.236497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2049 22:49:56.236580 ==
2050 22:49:56.236645 DQS Delay:
2051 22:49:56.239859 DQS0 = 0, DQS1 = 0
2052 22:49:56.239966 DQM Delay:
2053 22:49:56.242711 DQM0 = 78, DQM1 = 73
2054 22:49:56.242793 DQ Delay:
2055 22:49:56.246108 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =76
2056 22:49:56.249451 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2057 22:49:56.252910 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =64
2058 22:49:56.256246 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2059 22:49:56.256328
2060 22:49:56.256392
2061 22:49:56.266193 [DQSOSCAuto] RK1, (LSB)MR18= 0x2038, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2062 22:49:56.266279 CH1 RK1: MR19=606, MR18=2038
2063 22:49:56.272802 CH1_RK1: MR19=0x606, MR18=0x2038, DQSOSC=395, MR23=63, INC=94, DEC=63
2064 22:49:56.276099 [RxdqsGatingPostProcess] freq 800
2065 22:49:56.282823 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2066 22:49:56.286181 Pre-setting of DQS Precalculation
2067 22:49:56.289354 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2068 22:49:56.296229 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2069 22:49:56.302720 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2070 22:49:56.302807
2071 22:49:56.305976
2072 22:49:56.306057 [Calibration Summary] 1600 Mbps
2073 22:49:56.309742 CH 0, Rank 0
2074 22:49:56.309847 SW Impedance : PASS
2075 22:49:56.312935 DUTY Scan : NO K
2076 22:49:56.316377 ZQ Calibration : PASS
2077 22:49:56.316461 Jitter Meter : NO K
2078 22:49:56.319899 CBT Training : PASS
2079 22:49:56.322838 Write leveling : PASS
2080 22:49:56.322918 RX DQS gating : PASS
2081 22:49:56.326556 RX DQ/DQS(RDDQC) : PASS
2082 22:49:56.329407 TX DQ/DQS : PASS
2083 22:49:56.329547 RX DATLAT : PASS
2084 22:49:56.333166 RX DQ/DQS(Engine): PASS
2085 22:49:56.333272 TX OE : NO K
2086 22:49:56.336726 All Pass.
2087 22:49:56.336821
2088 22:49:56.336914 CH 0, Rank 1
2089 22:49:56.339738 SW Impedance : PASS
2090 22:49:56.339842 DUTY Scan : NO K
2091 22:49:56.342999 ZQ Calibration : PASS
2092 22:49:56.346536 Jitter Meter : NO K
2093 22:49:56.346617 CBT Training : PASS
2094 22:49:56.349692 Write leveling : PASS
2095 22:49:56.352853 RX DQS gating : PASS
2096 22:49:56.352933 RX DQ/DQS(RDDQC) : PASS
2097 22:49:56.356088 TX DQ/DQS : PASS
2098 22:49:56.359817 RX DATLAT : PASS
2099 22:49:56.359897 RX DQ/DQS(Engine): PASS
2100 22:49:56.363049 TX OE : NO K
2101 22:49:56.363129 All Pass.
2102 22:49:56.363193
2103 22:49:56.366436 CH 1, Rank 0
2104 22:49:56.366515 SW Impedance : PASS
2105 22:49:56.369889 DUTY Scan : NO K
2106 22:49:56.373270 ZQ Calibration : PASS
2107 22:49:56.373350 Jitter Meter : NO K
2108 22:49:56.376295 CBT Training : PASS
2109 22:49:56.376375 Write leveling : PASS
2110 22:49:56.379680 RX DQS gating : PASS
2111 22:49:56.383241 RX DQ/DQS(RDDQC) : PASS
2112 22:49:56.383321 TX DQ/DQS : PASS
2113 22:49:56.386399 RX DATLAT : PASS
2114 22:49:56.389829 RX DQ/DQS(Engine): PASS
2115 22:49:56.389910 TX OE : NO K
2116 22:49:56.393192 All Pass.
2117 22:49:56.393297
2118 22:49:56.393386 CH 1, Rank 1
2119 22:49:56.396606 SW Impedance : PASS
2120 22:49:56.396686 DUTY Scan : NO K
2121 22:49:56.399457 ZQ Calibration : PASS
2122 22:49:56.402798 Jitter Meter : NO K
2123 22:49:56.402879 CBT Training : PASS
2124 22:49:56.406099 Write leveling : PASS
2125 22:49:56.409888 RX DQS gating : PASS
2126 22:49:56.409995 RX DQ/DQS(RDDQC) : PASS
2127 22:49:56.413198 TX DQ/DQS : PASS
2128 22:49:56.416499 RX DATLAT : PASS
2129 22:49:56.416582 RX DQ/DQS(Engine): PASS
2130 22:49:56.419647 TX OE : NO K
2131 22:49:56.419729 All Pass.
2132 22:49:56.419795
2133 22:49:56.423112 DramC Write-DBI off
2134 22:49:56.426297 PER_BANK_REFRESH: Hybrid Mode
2135 22:49:56.426379 TX_TRACKING: ON
2136 22:49:56.429683 [GetDramInforAfterCalByMRR] Vendor 6.
2137 22:49:56.432945 [GetDramInforAfterCalByMRR] Revision 606.
2138 22:49:56.436353 [GetDramInforAfterCalByMRR] Revision 2 0.
2139 22:49:56.439619 MR0 0x3b3b
2140 22:49:56.439699 MR8 0x5151
2141 22:49:56.443021 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2142 22:49:56.443102
2143 22:49:56.443166 MR0 0x3b3b
2144 22:49:56.446403 MR8 0x5151
2145 22:49:56.449851 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2146 22:49:56.449931
2147 22:49:56.456290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2148 22:49:56.462902 [FAST_K] Save calibration result to emmc
2149 22:49:56.466265 [FAST_K] Save calibration result to emmc
2150 22:49:56.466347 dram_init: config_dvfs: 1
2151 22:49:56.469532 dramc_set_vcore_voltage set vcore to 662500
2152 22:49:56.472838 Read voltage for 1200, 2
2153 22:49:56.476184 Vio18 = 0
2154 22:49:56.476265 Vcore = 662500
2155 22:49:56.476328 Vdram = 0
2156 22:49:56.476387 Vddq = 0
2157 22:49:56.479093 Vmddr = 0
2158 22:49:56.482706 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2159 22:49:56.489382 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2160 22:49:56.492465 MEM_TYPE=3, freq_sel=15
2161 22:49:56.492546 sv_algorithm_assistance_LP4_1600
2162 22:49:56.499184 ============ PULL DRAM RESETB DOWN ============
2163 22:49:56.502893 ========== PULL DRAM RESETB DOWN end =========
2164 22:49:56.505770 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2165 22:49:56.509089 ===================================
2166 22:49:56.512313 LPDDR4 DRAM CONFIGURATION
2167 22:49:56.515617 ===================================
2168 22:49:56.519074 EX_ROW_EN[0] = 0x0
2169 22:49:56.519158 EX_ROW_EN[1] = 0x0
2170 22:49:56.522331 LP4Y_EN = 0x0
2171 22:49:56.522414 WORK_FSP = 0x0
2172 22:49:56.525504 WL = 0x4
2173 22:49:56.525626 RL = 0x4
2174 22:49:56.528941 BL = 0x2
2175 22:49:56.529022 RPST = 0x0
2176 22:49:56.532232 RD_PRE = 0x0
2177 22:49:56.532313 WR_PRE = 0x1
2178 22:49:56.535530 WR_PST = 0x0
2179 22:49:56.535611 DBI_WR = 0x0
2180 22:49:56.538955 DBI_RD = 0x0
2181 22:49:56.539037 OTF = 0x1
2182 22:49:56.542294 ===================================
2183 22:49:56.545849 ===================================
2184 22:49:56.549243 ANA top config
2185 22:49:56.552601 ===================================
2186 22:49:56.555914 DLL_ASYNC_EN = 0
2187 22:49:56.555994 ALL_SLAVE_EN = 0
2188 22:49:56.559153 NEW_RANK_MODE = 1
2189 22:49:56.562552 DLL_IDLE_MODE = 1
2190 22:49:56.566517 LP45_APHY_COMB_EN = 1
2191 22:49:56.566598 TX_ODT_DIS = 1
2192 22:49:56.569292 NEW_8X_MODE = 1
2193 22:49:56.572524 ===================================
2194 22:49:56.575834 ===================================
2195 22:49:56.579168 data_rate = 2400
2196 22:49:56.582563 CKR = 1
2197 22:49:56.585782 DQ_P2S_RATIO = 8
2198 22:49:56.589172 ===================================
2199 22:49:56.592536 CA_P2S_RATIO = 8
2200 22:49:56.592618 DQ_CA_OPEN = 0
2201 22:49:56.595898 DQ_SEMI_OPEN = 0
2202 22:49:56.599087 CA_SEMI_OPEN = 0
2203 22:49:56.602778 CA_FULL_RATE = 0
2204 22:49:56.605759 DQ_CKDIV4_EN = 0
2205 22:49:56.605841 CA_CKDIV4_EN = 0
2206 22:49:56.609711 CA_PREDIV_EN = 0
2207 22:49:56.612351 PH8_DLY = 17
2208 22:49:56.616216 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2209 22:49:56.619599 DQ_AAMCK_DIV = 4
2210 22:49:56.622357 CA_AAMCK_DIV = 4
2211 22:49:56.622439 CA_ADMCK_DIV = 4
2212 22:49:56.626301 DQ_TRACK_CA_EN = 0
2213 22:49:56.629423 CA_PICK = 1200
2214 22:49:56.632902 CA_MCKIO = 1200
2215 22:49:56.636227 MCKIO_SEMI = 0
2216 22:49:56.639340 PLL_FREQ = 2366
2217 22:49:56.642405 DQ_UI_PI_RATIO = 32
2218 22:49:56.646260 CA_UI_PI_RATIO = 0
2219 22:49:56.649031 ===================================
2220 22:49:56.652819 ===================================
2221 22:49:56.652900 memory_type:LPDDR4
2222 22:49:56.655650 GP_NUM : 10
2223 22:49:56.655731 SRAM_EN : 1
2224 22:49:56.659080 MD32_EN : 0
2225 22:49:56.662335 ===================================
2226 22:49:56.666203 [ANA_INIT] >>>>>>>>>>>>>>
2227 22:49:56.669039 <<<<<< [CONFIGURE PHASE]: ANA_TX
2228 22:49:56.672375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2229 22:49:56.675670 ===================================
2230 22:49:56.675752 data_rate = 2400,PCW = 0X5b00
2231 22:49:56.678954 ===================================
2232 22:49:56.686059 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2233 22:49:56.689446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 22:49:56.695851 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2235 22:49:56.699197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2236 22:49:56.702582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2237 22:49:56.705669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2238 22:49:56.709276 [ANA_INIT] flow start
2239 22:49:56.712953 [ANA_INIT] PLL >>>>>>>>
2240 22:49:56.713034 [ANA_INIT] PLL <<<<<<<<
2241 22:49:56.715838 [ANA_INIT] MIDPI >>>>>>>>
2242 22:49:56.719535 [ANA_INIT] MIDPI <<<<<<<<
2243 22:49:56.719618 [ANA_INIT] DLL >>>>>>>>
2244 22:49:56.722844 [ANA_INIT] DLL <<<<<<<<
2245 22:49:56.726100 [ANA_INIT] flow end
2246 22:49:56.729007 ============ LP4 DIFF to SE enter ============
2247 22:49:56.732899 ============ LP4 DIFF to SE exit ============
2248 22:49:56.735725 [ANA_INIT] <<<<<<<<<<<<<
2249 22:49:56.739528 [Flow] Enable top DCM control >>>>>
2250 22:49:56.742481 [Flow] Enable top DCM control <<<<<
2251 22:49:56.745770 Enable DLL master slave shuffle
2252 22:49:56.749191 ==============================================================
2253 22:49:56.752582 Gating Mode config
2254 22:49:56.755789 ==============================================================
2255 22:49:56.759318 Config description:
2256 22:49:56.769473 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2257 22:49:56.776230 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2258 22:49:56.779384 SELPH_MODE 0: By rank 1: By Phase
2259 22:49:56.786087 ==============================================================
2260 22:49:56.789359 GAT_TRACK_EN = 1
2261 22:49:56.792737 RX_GATING_MODE = 2
2262 22:49:56.796392 RX_GATING_TRACK_MODE = 2
2263 22:49:56.799472 SELPH_MODE = 1
2264 22:49:56.799553 PICG_EARLY_EN = 1
2265 22:49:56.802640 VALID_LAT_VALUE = 1
2266 22:49:56.809435 ==============================================================
2267 22:49:56.812707 Enter into Gating configuration >>>>
2268 22:49:56.816377 Exit from Gating configuration <<<<
2269 22:49:56.819327 Enter into DVFS_PRE_config >>>>>
2270 22:49:56.829273 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2271 22:49:56.832460 Exit from DVFS_PRE_config <<<<<
2272 22:49:56.836271 Enter into PICG configuration >>>>
2273 22:49:56.839115 Exit from PICG configuration <<<<
2274 22:49:56.842894 [RX_INPUT] configuration >>>>>
2275 22:49:56.845814 [RX_INPUT] configuration <<<<<
2276 22:49:56.849088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2277 22:49:56.855853 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2278 22:49:56.862772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2279 22:49:56.869465 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2280 22:49:56.876277 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2281 22:49:56.879761 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2282 22:49:56.885764 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2283 22:49:56.889569 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2284 22:49:56.892393 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2285 22:49:56.895739 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2286 22:49:56.899530 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2287 22:49:56.905973 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 22:49:56.909366 ===================================
2289 22:49:56.912697 LPDDR4 DRAM CONFIGURATION
2290 22:49:56.915945 ===================================
2291 22:49:56.916028 EX_ROW_EN[0] = 0x0
2292 22:49:56.919304 EX_ROW_EN[1] = 0x0
2293 22:49:56.919388 LP4Y_EN = 0x0
2294 22:49:56.922704 WORK_FSP = 0x0
2295 22:49:56.922787 WL = 0x4
2296 22:49:56.926123 RL = 0x4
2297 22:49:56.926205 BL = 0x2
2298 22:49:56.929237 RPST = 0x0
2299 22:49:56.929343 RD_PRE = 0x0
2300 22:49:56.932852 WR_PRE = 0x1
2301 22:49:56.932934 WR_PST = 0x0
2302 22:49:56.936212 DBI_WR = 0x0
2303 22:49:56.936333 DBI_RD = 0x0
2304 22:49:56.939424 OTF = 0x1
2305 22:49:56.942673 ===================================
2306 22:49:56.946160 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2307 22:49:56.949485 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2308 22:49:56.956313 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2309 22:49:56.959267 ===================================
2310 22:49:56.959350 LPDDR4 DRAM CONFIGURATION
2311 22:49:56.962590 ===================================
2312 22:49:56.965866 EX_ROW_EN[0] = 0x10
2313 22:49:56.969296 EX_ROW_EN[1] = 0x0
2314 22:49:56.969379 LP4Y_EN = 0x0
2315 22:49:56.972948 WORK_FSP = 0x0
2316 22:49:56.973030 WL = 0x4
2317 22:49:56.975891 RL = 0x4
2318 22:49:56.975973 BL = 0x2
2319 22:49:56.979254 RPST = 0x0
2320 22:49:56.979335 RD_PRE = 0x0
2321 22:49:56.982640 WR_PRE = 0x1
2322 22:49:56.982742 WR_PST = 0x0
2323 22:49:56.985986 DBI_WR = 0x0
2324 22:49:56.986081 DBI_RD = 0x0
2325 22:49:56.989350 OTF = 0x1
2326 22:49:56.992560 ===================================
2327 22:49:56.999211 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2328 22:49:56.999297 ==
2329 22:49:57.002599 Dram Type= 6, Freq= 0, CH_0, rank 0
2330 22:49:57.005927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2331 22:49:57.006012 ==
2332 22:49:57.009693 [Duty_Offset_Calibration]
2333 22:49:57.009775 B0:2 B1:0 CA:3
2334 22:49:57.009839
2335 22:49:57.012716 [DutyScan_Calibration_Flow] k_type=0
2336 22:49:57.022856
2337 22:49:57.022953 ==CLK 0==
2338 22:49:57.026094 Final CLK duty delay cell = 0
2339 22:49:57.029468 [0] MAX Duty = 5062%(X100), DQS PI = 20
2340 22:49:57.032636 [0] MIN Duty = 4906%(X100), DQS PI = 54
2341 22:49:57.032717 [0] AVG Duty = 4984%(X100)
2342 22:49:57.032781
2343 22:49:57.035967 CH0 CLK Duty spec in!! Max-Min= 156%
2344 22:49:57.042642 [DutyScan_Calibration_Flow] ====Done====
2345 22:49:57.042730
2346 22:49:57.045694 [DutyScan_Calibration_Flow] k_type=1
2347 22:49:57.061688
2348 22:49:57.061794 ==DQS 0 ==
2349 22:49:57.064932 Final DQS duty delay cell = 0
2350 22:49:57.068296 [0] MAX Duty = 5062%(X100), DQS PI = 12
2351 22:49:57.071684 [0] MIN Duty = 4907%(X100), DQS PI = 0
2352 22:49:57.071766 [0] AVG Duty = 4984%(X100)
2353 22:49:57.074987
2354 22:49:57.075068 ==DQS 1 ==
2355 22:49:57.078207 Final DQS duty delay cell = 0
2356 22:49:57.081631 [0] MAX Duty = 5125%(X100), DQS PI = 34
2357 22:49:57.085284 [0] MIN Duty = 5031%(X100), DQS PI = 0
2358 22:49:57.085367 [0] AVG Duty = 5078%(X100)
2359 22:49:57.088472
2360 22:49:57.091564 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2361 22:49:57.091646
2362 22:49:57.095052 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2363 22:49:57.098326 [DutyScan_Calibration_Flow] ====Done====
2364 22:49:57.098408
2365 22:49:57.101765 [DutyScan_Calibration_Flow] k_type=3
2366 22:49:57.118935
2367 22:49:57.119051 ==DQM 0 ==
2368 22:49:57.122197 Final DQM duty delay cell = 0
2369 22:49:57.125518 [0] MAX Duty = 5124%(X100), DQS PI = 28
2370 22:49:57.128948 [0] MIN Duty = 4876%(X100), DQS PI = 48
2371 22:49:57.132328 [0] AVG Duty = 5000%(X100)
2372 22:49:57.132409
2373 22:49:57.132475 ==DQM 1 ==
2374 22:49:57.135688 Final DQM duty delay cell = 4
2375 22:49:57.138897 [4] MAX Duty = 5124%(X100), DQS PI = 0
2376 22:49:57.142051 [4] MIN Duty = 5000%(X100), DQS PI = 14
2377 22:49:57.142134 [4] AVG Duty = 5062%(X100)
2378 22:49:57.145428
2379 22:49:57.148925 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2380 22:49:57.149006
2381 22:49:57.152239 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2382 22:49:57.155396 [DutyScan_Calibration_Flow] ====Done====
2383 22:49:57.155478
2384 22:49:57.158573 [DutyScan_Calibration_Flow] k_type=2
2385 22:49:57.173837
2386 22:49:57.173923 ==DQ 0 ==
2387 22:49:57.176836 Final DQ duty delay cell = -4
2388 22:49:57.180531 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2389 22:49:57.183813 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2390 22:49:57.187112 [-4] AVG Duty = 4969%(X100)
2391 22:49:57.187193
2392 22:49:57.187256 ==DQ 1 ==
2393 22:49:57.190188 Final DQ duty delay cell = -4
2394 22:49:57.193729 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2395 22:49:57.197150 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2396 22:49:57.200395 [-4] AVG Duty = 4922%(X100)
2397 22:49:57.200476
2398 22:49:57.203691 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2399 22:49:57.203772
2400 22:49:57.207242 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2401 22:49:57.210488 [DutyScan_Calibration_Flow] ====Done====
2402 22:49:57.210569 ==
2403 22:49:57.213747 Dram Type= 6, Freq= 0, CH_1, rank 0
2404 22:49:57.217053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2405 22:49:57.217136 ==
2406 22:49:57.220264 [Duty_Offset_Calibration]
2407 22:49:57.220346 B0:1 B1:-2 CA:0
2408 22:49:57.220411
2409 22:49:57.223871 [DutyScan_Calibration_Flow] k_type=0
2410 22:49:57.234082
2411 22:49:57.234167 ==CLK 0==
2412 22:49:57.237428 Final CLK duty delay cell = 0
2413 22:49:57.240874 [0] MAX Duty = 5062%(X100), DQS PI = 30
2414 22:49:57.244332 [0] MIN Duty = 4875%(X100), DQS PI = 58
2415 22:49:57.244413 [0] AVG Duty = 4968%(X100)
2416 22:49:57.247926
2417 22:49:57.251062 CH1 CLK Duty spec in!! Max-Min= 187%
2418 22:49:57.253845 [DutyScan_Calibration_Flow] ====Done====
2419 22:49:57.253928
2420 22:49:57.257680 [DutyScan_Calibration_Flow] k_type=1
2421 22:49:57.272499
2422 22:49:57.272588 ==DQS 0 ==
2423 22:49:57.275914 Final DQS duty delay cell = -4
2424 22:49:57.279345 [-4] MAX Duty = 5000%(X100), DQS PI = 16
2425 22:49:57.282564 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2426 22:49:57.285766 [-4] AVG Duty = 4953%(X100)
2427 22:49:57.285848
2428 22:49:57.285912 ==DQS 1 ==
2429 22:49:57.289169 Final DQS duty delay cell = 0
2430 22:49:57.292528 [0] MAX Duty = 5093%(X100), DQS PI = 0
2431 22:49:57.296062 [0] MIN Duty = 4875%(X100), DQS PI = 26
2432 22:49:57.299275 [0] AVG Duty = 4984%(X100)
2433 22:49:57.299357
2434 22:49:57.303250 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2435 22:49:57.303333
2436 22:49:57.306176 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2437 22:49:57.309288 [DutyScan_Calibration_Flow] ====Done====
2438 22:49:57.309384
2439 22:49:57.312654 [DutyScan_Calibration_Flow] k_type=3
2440 22:49:57.329331
2441 22:49:57.329436 ==DQM 0 ==
2442 22:49:57.332526 Final DQM duty delay cell = 0
2443 22:49:57.336118 [0] MAX Duty = 5000%(X100), DQS PI = 22
2444 22:49:57.339703 [0] MIN Duty = 4876%(X100), DQS PI = 2
2445 22:49:57.339785 [0] AVG Duty = 4938%(X100)
2446 22:49:57.342369
2447 22:49:57.342449 ==DQM 1 ==
2448 22:49:57.345678 Final DQM duty delay cell = 0
2449 22:49:57.349435 [0] MAX Duty = 5031%(X100), DQS PI = 36
2450 22:49:57.352647 [0] MIN Duty = 4907%(X100), DQS PI = 0
2451 22:49:57.352728 [0] AVG Duty = 4969%(X100)
2452 22:49:57.356154
2453 22:49:57.359050 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2454 22:49:57.359130
2455 22:49:57.362382 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2456 22:49:57.366006 [DutyScan_Calibration_Flow] ====Done====
2457 22:49:57.366086
2458 22:49:57.369060 [DutyScan_Calibration_Flow] k_type=2
2459 22:49:57.385715
2460 22:49:57.385802 ==DQ 0 ==
2461 22:49:57.388940 Final DQ duty delay cell = 0
2462 22:49:57.392370 [0] MAX Duty = 5093%(X100), DQS PI = 20
2463 22:49:57.395582 [0] MIN Duty = 4938%(X100), DQS PI = 54
2464 22:49:57.395663 [0] AVG Duty = 5015%(X100)
2465 22:49:57.395727
2466 22:49:57.399076 ==DQ 1 ==
2467 22:49:57.402247 Final DQ duty delay cell = 0
2468 22:49:57.405501 [0] MAX Duty = 5093%(X100), DQS PI = 20
2469 22:49:57.409054 [0] MIN Duty = 4969%(X100), DQS PI = 26
2470 22:49:57.409134 [0] AVG Duty = 5031%(X100)
2471 22:49:57.409197
2472 22:49:57.412088 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2473 22:49:57.415572
2474 22:49:57.418906 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2475 22:49:57.422290 [DutyScan_Calibration_Flow] ====Done====
2476 22:49:57.425429 nWR fixed to 30
2477 22:49:57.425520 [ModeRegInit_LP4] CH0 RK0
2478 22:49:57.428577 [ModeRegInit_LP4] CH0 RK1
2479 22:49:57.431997 [ModeRegInit_LP4] CH1 RK0
2480 22:49:57.432080 [ModeRegInit_LP4] CH1 RK1
2481 22:49:57.435317 match AC timing 7
2482 22:49:57.438992 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2483 22:49:57.445634 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2484 22:49:57.448728 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2485 22:49:57.451874 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2486 22:49:57.458941 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2487 22:49:57.459025 ==
2488 22:49:57.462285 Dram Type= 6, Freq= 0, CH_0, rank 0
2489 22:49:57.465523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 22:49:57.465618 ==
2491 22:49:57.472315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 22:49:57.478485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 22:49:57.485553 [CA 0] Center 40 (10~71) winsize 62
2494 22:49:57.488943 [CA 1] Center 39 (9~70) winsize 62
2495 22:49:57.492260 [CA 2] Center 36 (6~66) winsize 61
2496 22:49:57.495687 [CA 3] Center 35 (5~66) winsize 62
2497 22:49:57.498718 [CA 4] Center 34 (4~65) winsize 62
2498 22:49:57.502083 [CA 5] Center 33 (3~64) winsize 62
2499 22:49:57.502163
2500 22:49:57.505418 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 22:49:57.505500
2502 22:49:57.509130 [CATrainingPosCal] consider 1 rank data
2503 22:49:57.512023 u2DelayCellTimex100 = 270/100 ps
2504 22:49:57.515453 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2505 22:49:57.522366 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2506 22:49:57.525722 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2507 22:49:57.528693 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2508 22:49:57.532174 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2509 22:49:57.535314 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2510 22:49:57.535397
2511 22:49:57.538977 CA PerBit enable=1, Macro0, CA PI delay=33
2512 22:49:57.539059
2513 22:49:57.542434 [CBTSetCACLKResult] CA Dly = 33
2514 22:49:57.542517 CS Dly: 7 (0~38)
2515 22:49:57.545560 ==
2516 22:49:57.549082 Dram Type= 6, Freq= 0, CH_0, rank 1
2517 22:49:57.552401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 22:49:57.552485 ==
2519 22:49:57.555816 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 22:49:57.562504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2521 22:49:57.571610 [CA 0] Center 40 (10~70) winsize 61
2522 22:49:57.575083 [CA 1] Center 40 (10~70) winsize 61
2523 22:49:57.578217 [CA 2] Center 35 (5~66) winsize 62
2524 22:49:57.581960 [CA 3] Center 35 (5~66) winsize 62
2525 22:49:57.584897 [CA 4] Center 34 (4~65) winsize 62
2526 22:49:57.588248 [CA 5] Center 33 (3~63) winsize 61
2527 22:49:57.588331
2528 22:49:57.591710 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2529 22:49:57.591793
2530 22:49:57.595050 [CATrainingPosCal] consider 2 rank data
2531 22:49:57.598689 u2DelayCellTimex100 = 270/100 ps
2532 22:49:57.601428 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2533 22:49:57.608244 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2534 22:49:57.611842 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2535 22:49:57.615213 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 22:49:57.618006 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2537 22:49:57.621467 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2538 22:49:57.621587
2539 22:49:57.624862 CA PerBit enable=1, Macro0, CA PI delay=33
2540 22:49:57.624947
2541 22:49:57.628269 [CBTSetCACLKResult] CA Dly = 33
2542 22:49:57.631504 CS Dly: 8 (0~40)
2543 22:49:57.631586
2544 22:49:57.634669 ----->DramcWriteLeveling(PI) begin...
2545 22:49:57.634752 ==
2546 22:49:57.637974 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 22:49:57.641677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 22:49:57.641759 ==
2549 22:49:57.645056 Write leveling (Byte 0): 33 => 33
2550 22:49:57.648326 Write leveling (Byte 1): 29 => 29
2551 22:49:57.651421 DramcWriteLeveling(PI) end<-----
2552 22:49:57.651502
2553 22:49:57.651566 ==
2554 22:49:57.654469 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 22:49:57.658103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 22:49:57.658184 ==
2557 22:49:57.661389 [Gating] SW mode calibration
2558 22:49:57.668302 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2559 22:49:57.674744 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2560 22:49:57.678242 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 22:49:57.681476 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2562 22:49:57.688223 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 22:49:57.691249 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 22:49:57.695727 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 22:49:57.701501 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 22:49:57.704828 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 22:49:57.708193 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2568 22:49:57.714883 1 0 0 | B1->B0 | 3232 2525 | 0 0 | (0 1) (0 1)
2569 22:49:57.718607 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2570 22:49:57.721684 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 22:49:57.724537 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 22:49:57.731353 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 22:49:57.734637 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 22:49:57.738308 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 22:49:57.745067 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2576 22:49:57.748427 1 1 0 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
2577 22:49:57.751625 1 1 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2578 22:49:57.758203 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 22:49:57.761251 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 22:49:57.764885 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 22:49:57.771682 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 22:49:57.775179 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 22:49:57.777931 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2584 22:49:57.785177 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2585 22:49:57.788282 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 22:49:57.791443 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 22:49:57.797920 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 22:49:57.801662 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 22:49:57.804769 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 22:49:57.811464 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 22:49:57.814540 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 22:49:57.818064 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 22:49:57.821330 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 22:49:57.827969 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 22:49:57.831285 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 22:49:57.834668 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 22:49:57.841216 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 22:49:57.844564 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 22:49:57.848275 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2600 22:49:57.855024 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2601 22:49:57.858548 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 22:49:57.861428 Total UI for P1: 0, mck2ui 16
2603 22:49:57.864665 best dqsien dly found for B0: ( 1, 3, 30)
2604 22:49:57.867973 Total UI for P1: 0, mck2ui 16
2605 22:49:57.871314 best dqsien dly found for B1: ( 1, 4, 0)
2606 22:49:57.874707 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2607 22:49:57.877843 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2608 22:49:57.877922
2609 22:49:57.881687 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2610 22:49:57.884511 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2611 22:49:57.887841 [Gating] SW calibration Done
2612 22:49:57.887921 ==
2613 22:49:57.891832 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 22:49:57.894875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 22:49:57.894956 ==
2616 22:49:57.898195 RX Vref Scan: 0
2617 22:49:57.898275
2618 22:49:57.901343 RX Vref 0 -> 0, step: 1
2619 22:49:57.901422
2620 22:49:57.901516 RX Delay -40 -> 252, step: 8
2621 22:49:57.907970 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2622 22:49:57.911654 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2623 22:49:57.915064 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2624 22:49:57.918008 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2625 22:49:57.921310 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2626 22:49:57.927986 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2627 22:49:57.931243 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2628 22:49:57.934627 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2629 22:49:57.938303 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2630 22:49:57.941359 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2631 22:49:57.948332 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2632 22:49:57.951499 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2633 22:49:57.954933 iDelay=200, Bit 12, Center 107 (40 ~ 175) 136
2634 22:49:57.958240 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2635 22:49:57.961423 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2636 22:49:57.968117 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2637 22:49:57.968197 ==
2638 22:49:57.971334 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 22:49:57.974506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 22:49:57.974587 ==
2641 22:49:57.974650 DQS Delay:
2642 22:49:57.977717 DQS0 = 0, DQS1 = 0
2643 22:49:57.977798 DQM Delay:
2644 22:49:57.981437 DQM0 = 113, DQM1 = 101
2645 22:49:57.981521 DQ Delay:
2646 22:49:57.984481 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2647 22:49:57.987875 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2648 22:49:57.991229 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2649 22:49:57.994503 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2650 22:49:57.994592
2651 22:49:57.994656
2652 22:49:57.994714 ==
2653 22:49:57.997793 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 22:49:58.004391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 22:49:58.004472 ==
2656 22:49:58.004535
2657 22:49:58.004593
2658 22:49:58.004650 TX Vref Scan disable
2659 22:49:58.008150 == TX Byte 0 ==
2660 22:49:58.011289 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2661 22:49:58.018182 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2662 22:49:58.018271 == TX Byte 1 ==
2663 22:49:58.021662 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2664 22:49:58.027805 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2665 22:49:58.027892 ==
2666 22:49:58.031473 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 22:49:58.034680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 22:49:58.034817 ==
2669 22:49:58.046167 TX Vref=22, minBit 0, minWin=25, winSum=420
2670 22:49:58.049998 TX Vref=24, minBit 7, minWin=25, winSum=428
2671 22:49:58.053155 TX Vref=26, minBit 2, minWin=26, winSum=433
2672 22:49:58.056275 TX Vref=28, minBit 1, minWin=27, winSum=437
2673 22:49:58.059694 TX Vref=30, minBit 1, minWin=27, winSum=437
2674 22:49:58.063098 TX Vref=32, minBit 1, minWin=26, winSum=433
2675 22:49:58.069849 [TxChooseVref] Worse bit 1, Min win 27, Win sum 437, Final Vref 28
2676 22:49:58.070015
2677 22:49:58.073103 Final TX Range 1 Vref 28
2678 22:49:58.073295
2679 22:49:58.073387 ==
2680 22:49:58.076397 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 22:49:58.079737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 22:49:58.079917 ==
2683 22:49:58.080010
2684 22:49:58.082991
2685 22:49:58.083180 TX Vref Scan disable
2686 22:49:58.086772 == TX Byte 0 ==
2687 22:49:58.089506 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2688 22:49:58.093281 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2689 22:49:58.096742 == TX Byte 1 ==
2690 22:49:58.100223 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2691 22:49:58.103410 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2692 22:49:58.103670
2693 22:49:58.106637 [DATLAT]
2694 22:49:58.106854 Freq=1200, CH0 RK0
2695 22:49:58.107015
2696 22:49:58.110014 DATLAT Default: 0xd
2697 22:49:58.110214 0, 0xFFFF, sum = 0
2698 22:49:58.113368 1, 0xFFFF, sum = 0
2699 22:49:58.113640 2, 0xFFFF, sum = 0
2700 22:49:58.116935 3, 0xFFFF, sum = 0
2701 22:49:58.117335 4, 0xFFFF, sum = 0
2702 22:49:58.120100 5, 0xFFFF, sum = 0
2703 22:49:58.120401 6, 0xFFFF, sum = 0
2704 22:49:58.123355 7, 0xFFFF, sum = 0
2705 22:49:58.126489 8, 0xFFFF, sum = 0
2706 22:49:58.126912 9, 0xFFFF, sum = 0
2707 22:49:58.129836 10, 0xFFFF, sum = 0
2708 22:49:58.130226 11, 0xFFFF, sum = 0
2709 22:49:58.133236 12, 0x0, sum = 1
2710 22:49:58.133499 13, 0x0, sum = 2
2711 22:49:58.136423 14, 0x0, sum = 3
2712 22:49:58.136609 15, 0x0, sum = 4
2713 22:49:58.136695 best_step = 13
2714 22:49:58.136761
2715 22:49:58.139732 ==
2716 22:49:58.142944 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 22:49:58.146350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 22:49:58.146474 ==
2719 22:49:58.146551 RX Vref Scan: 1
2720 22:49:58.146620
2721 22:49:58.149717 Set Vref Range= 32 -> 127
2722 22:49:58.149817
2723 22:49:58.152919 RX Vref 32 -> 127, step: 1
2724 22:49:58.153026
2725 22:49:58.156481 RX Delay -37 -> 252, step: 4
2726 22:49:58.156590
2727 22:49:58.159186 Set Vref, RX VrefLevel [Byte0]: 32
2728 22:49:58.163085 [Byte1]: 32
2729 22:49:58.163189
2730 22:49:58.165812 Set Vref, RX VrefLevel [Byte0]: 33
2731 22:49:58.169458 [Byte1]: 33
2732 22:49:58.172628
2733 22:49:58.172711 Set Vref, RX VrefLevel [Byte0]: 34
2734 22:49:58.175971 [Byte1]: 34
2735 22:49:58.180444
2736 22:49:58.180567 Set Vref, RX VrefLevel [Byte0]: 35
2737 22:49:58.183870 [Byte1]: 35
2738 22:49:58.188557
2739 22:49:58.188671 Set Vref, RX VrefLevel [Byte0]: 36
2740 22:49:58.191776 [Byte1]: 36
2741 22:49:58.196425
2742 22:49:58.196522 Set Vref, RX VrefLevel [Byte0]: 37
2743 22:49:58.199854 [Byte1]: 37
2744 22:49:58.204602
2745 22:49:58.204684 Set Vref, RX VrefLevel [Byte0]: 38
2746 22:49:58.208032 [Byte1]: 38
2747 22:49:58.212538
2748 22:49:58.212621 Set Vref, RX VrefLevel [Byte0]: 39
2749 22:49:58.216165 [Byte1]: 39
2750 22:49:58.220729
2751 22:49:58.220813 Set Vref, RX VrefLevel [Byte0]: 40
2752 22:49:58.224087 [Byte1]: 40
2753 22:49:58.228848
2754 22:49:58.228931 Set Vref, RX VrefLevel [Byte0]: 41
2755 22:49:58.231707 [Byte1]: 41
2756 22:49:58.236775
2757 22:49:58.236857 Set Vref, RX VrefLevel [Byte0]: 42
2758 22:49:58.239989 [Byte1]: 42
2759 22:49:58.244422
2760 22:49:58.244503 Set Vref, RX VrefLevel [Byte0]: 43
2761 22:49:58.247839 [Byte1]: 43
2762 22:49:58.252734
2763 22:49:58.252815 Set Vref, RX VrefLevel [Byte0]: 44
2764 22:49:58.256077 [Byte1]: 44
2765 22:49:58.260506
2766 22:49:58.260586 Set Vref, RX VrefLevel [Byte0]: 45
2767 22:49:58.263947 [Byte1]: 45
2768 22:49:58.268558
2769 22:49:58.268639 Set Vref, RX VrefLevel [Byte0]: 46
2770 22:49:58.271897 [Byte1]: 46
2771 22:49:58.276489
2772 22:49:58.276569 Set Vref, RX VrefLevel [Byte0]: 47
2773 22:49:58.279893 [Byte1]: 47
2774 22:49:58.284756
2775 22:49:58.284836 Set Vref, RX VrefLevel [Byte0]: 48
2776 22:49:58.290934 [Byte1]: 48
2777 22:49:58.291015
2778 22:49:58.294203 Set Vref, RX VrefLevel [Byte0]: 49
2779 22:49:58.297760 [Byte1]: 49
2780 22:49:58.297841
2781 22:49:58.300886 Set Vref, RX VrefLevel [Byte0]: 50
2782 22:49:58.304236 [Byte1]: 50
2783 22:49:58.308525
2784 22:49:58.308605 Set Vref, RX VrefLevel [Byte0]: 51
2785 22:49:58.311953 [Byte1]: 51
2786 22:49:58.316994
2787 22:49:58.317075 Set Vref, RX VrefLevel [Byte0]: 52
2788 22:49:58.320141 [Byte1]: 52
2789 22:49:58.324474
2790 22:49:58.324555 Set Vref, RX VrefLevel [Byte0]: 53
2791 22:49:58.327971 [Byte1]: 53
2792 22:49:58.333085
2793 22:49:58.333167 Set Vref, RX VrefLevel [Byte0]: 54
2794 22:49:58.335925 [Byte1]: 54
2795 22:49:58.340797
2796 22:49:58.340877 Set Vref, RX VrefLevel [Byte0]: 55
2797 22:49:58.344042 [Byte1]: 55
2798 22:49:58.348789
2799 22:49:58.348870 Set Vref, RX VrefLevel [Byte0]: 56
2800 22:49:58.352157 [Byte1]: 56
2801 22:49:58.356820
2802 22:49:58.356901 Set Vref, RX VrefLevel [Byte0]: 57
2803 22:49:58.360083 [Byte1]: 57
2804 22:49:58.364521
2805 22:49:58.364601 Set Vref, RX VrefLevel [Byte0]: 58
2806 22:49:58.367976 [Byte1]: 58
2807 22:49:58.372939
2808 22:49:58.373018 Set Vref, RX VrefLevel [Byte0]: 59
2809 22:49:58.376322 [Byte1]: 59
2810 22:49:58.380662
2811 22:49:58.380742 Set Vref, RX VrefLevel [Byte0]: 60
2812 22:49:58.384256 [Byte1]: 60
2813 22:49:58.388808
2814 22:49:58.388888 Set Vref, RX VrefLevel [Byte0]: 61
2815 22:49:58.391698 [Byte1]: 61
2816 22:49:58.396824
2817 22:49:58.396905 Set Vref, RX VrefLevel [Byte0]: 62
2818 22:49:58.400037 [Byte1]: 62
2819 22:49:58.404473
2820 22:49:58.404557 Set Vref, RX VrefLevel [Byte0]: 63
2821 22:49:58.408226 [Byte1]: 63
2822 22:49:58.412752
2823 22:49:58.412834 Set Vref, RX VrefLevel [Byte0]: 64
2824 22:49:58.416127 [Byte1]: 64
2825 22:49:58.420594
2826 22:49:58.420675 Set Vref, RX VrefLevel [Byte0]: 65
2827 22:49:58.423968 [Byte1]: 65
2828 22:49:58.428488
2829 22:49:58.428570 Set Vref, RX VrefLevel [Byte0]: 66
2830 22:49:58.431903 [Byte1]: 66
2831 22:49:58.436405
2832 22:49:58.436486 Set Vref, RX VrefLevel [Byte0]: 67
2833 22:49:58.440011 [Byte1]: 67
2834 22:49:58.444730
2835 22:49:58.444813 Set Vref, RX VrefLevel [Byte0]: 68
2836 22:49:58.448070 [Byte1]: 68
2837 22:49:58.452471
2838 22:49:58.452589 Set Vref, RX VrefLevel [Byte0]: 69
2839 22:49:58.455835 [Byte1]: 69
2840 22:49:58.460622
2841 22:49:58.460710 Set Vref, RX VrefLevel [Byte0]: 70
2842 22:49:58.464110 [Byte1]: 70
2843 22:49:58.468738
2844 22:49:58.468817 Set Vref, RX VrefLevel [Byte0]: 71
2845 22:49:58.472003 [Byte1]: 71
2846 22:49:58.476614
2847 22:49:58.476697 Set Vref, RX VrefLevel [Byte0]: 72
2848 22:49:58.479857 [Byte1]: 72
2849 22:49:58.484920
2850 22:49:58.485001 Set Vref, RX VrefLevel [Byte0]: 73
2851 22:49:58.487840 [Byte1]: 73
2852 22:49:58.492863
2853 22:49:58.492944 Final RX Vref Byte 0 = 60 to rank0
2854 22:49:58.495820 Final RX Vref Byte 1 = 46 to rank0
2855 22:49:58.499144 Final RX Vref Byte 0 = 60 to rank1
2856 22:49:58.503000 Final RX Vref Byte 1 = 46 to rank1==
2857 22:49:58.506177 Dram Type= 6, Freq= 0, CH_0, rank 0
2858 22:49:58.509490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 22:49:58.512638 ==
2860 22:49:58.512720 DQS Delay:
2861 22:49:58.512784 DQS0 = 0, DQS1 = 0
2862 22:49:58.516403 DQM Delay:
2863 22:49:58.516487 DQM0 = 112, DQM1 = 98
2864 22:49:58.519308 DQ Delay:
2865 22:49:58.522664 DQ0 =112, DQ1 =112, DQ2 =114, DQ3 =108
2866 22:49:58.525825 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2867 22:49:58.529274 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2868 22:49:58.532633 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2869 22:49:58.532719
2870 22:49:58.532784
2871 22:49:58.539501 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
2872 22:49:58.543214 CH0 RK0: MR19=303, MR18=FCFB
2873 22:49:58.549394 CH0_RK0: MR19=0x303, MR18=0xFCFB, DQSOSC=411, MR23=63, INC=38, DEC=25
2874 22:49:58.549575
2875 22:49:58.553194 ----->DramcWriteLeveling(PI) begin...
2876 22:49:58.553353 ==
2877 22:49:58.556612 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 22:49:58.560054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 22:49:58.560222 ==
2880 22:49:58.562879 Write leveling (Byte 0): 32 => 32
2881 22:49:58.566015 Write leveling (Byte 1): 30 => 30
2882 22:49:58.569443 DramcWriteLeveling(PI) end<-----
2883 22:49:58.569616
2884 22:49:58.569713 ==
2885 22:49:58.572827 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 22:49:58.576424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 22:49:58.579241 ==
2888 22:49:58.579421 [Gating] SW mode calibration
2889 22:49:58.589632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2890 22:49:58.592745 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2891 22:49:58.596050 0 15 0 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
2892 22:49:58.603314 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 22:49:58.605930 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 22:49:58.609617 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 22:49:58.616201 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 22:49:58.619993 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 22:49:58.623285 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2898 22:49:58.630034 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
2899 22:49:58.633343 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
2900 22:49:58.636501 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 22:49:58.643487 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 22:49:58.646671 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 22:49:58.650133 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 22:49:58.656377 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 22:49:58.660096 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2906 22:49:58.663613 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2907 22:49:58.667008 1 1 0 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
2908 22:49:58.673348 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 22:49:58.677184 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 22:49:58.680570 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 22:49:58.686977 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 22:49:58.689876 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 22:49:58.693188 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 22:49:58.700085 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2915 22:49:58.703238 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2916 22:49:58.706504 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 22:49:58.712788 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 22:49:58.716160 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 22:49:58.719822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 22:49:58.726684 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 22:49:58.729883 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 22:49:58.733098 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 22:49:58.739660 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 22:49:58.743513 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 22:49:58.746943 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 22:49:58.753582 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 22:49:58.756420 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 22:49:58.760261 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 22:49:58.763054 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2930 22:49:58.770462 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2931 22:49:58.773036 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2932 22:49:58.776554 Total UI for P1: 0, mck2ui 16
2933 22:49:58.780202 best dqsien dly found for B0: ( 1, 3, 26)
2934 22:49:58.783604 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 22:49:58.786691 Total UI for P1: 0, mck2ui 16
2936 22:49:58.789503 best dqsien dly found for B1: ( 1, 4, 0)
2937 22:49:58.793390 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2938 22:49:58.796074 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2939 22:49:58.796495
2940 22:49:58.803171 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2941 22:49:58.806144 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2942 22:49:58.809957 [Gating] SW calibration Done
2943 22:49:58.810550 ==
2944 22:49:58.812899 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 22:49:58.816579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 22:49:58.817114 ==
2947 22:49:58.817450 RX Vref Scan: 0
2948 22:49:58.817809
2949 22:49:58.819789 RX Vref 0 -> 0, step: 1
2950 22:49:58.820204
2951 22:49:58.822978 RX Delay -40 -> 252, step: 8
2952 22:49:58.826505 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2953 22:49:58.830299 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2954 22:49:58.836292 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2955 22:49:58.839475 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2956 22:49:58.842842 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2957 22:49:58.846699 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2958 22:49:58.849736 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2959 22:49:58.852984 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2960 22:49:58.859920 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2961 22:49:58.863188 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2962 22:49:58.866479 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2963 22:49:58.869409 iDelay=200, Bit 11, Center 87 (16 ~ 159) 144
2964 22:49:58.872907 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2965 22:49:58.879570 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2966 22:49:58.882915 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2967 22:49:58.886277 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2968 22:49:58.886790 ==
2969 22:49:58.889805 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 22:49:58.893286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 22:49:58.893831 ==
2972 22:49:58.896384 DQS Delay:
2973 22:49:58.896805 DQS0 = 0, DQS1 = 0
2974 22:49:58.899683 DQM Delay:
2975 22:49:58.900198 DQM0 = 112, DQM1 = 99
2976 22:49:58.900526 DQ Delay:
2977 22:49:58.906481 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2978 22:49:58.909674 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2979 22:49:58.912954 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =87
2980 22:49:58.916399 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2981 22:49:58.916910
2982 22:49:58.917313
2983 22:49:58.917687 ==
2984 22:49:58.919640 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 22:49:58.922696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 22:49:58.923110 ==
2987 22:49:58.923435
2988 22:49:58.923733
2989 22:49:58.926339 TX Vref Scan disable
2990 22:49:58.929695 == TX Byte 0 ==
2991 22:49:58.932466 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2992 22:49:58.935951 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2993 22:49:58.939256 == TX Byte 1 ==
2994 22:49:58.942758 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2995 22:49:58.946220 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2996 22:49:58.946635 ==
2997 22:49:58.950210 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 22:49:58.953092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 22:49:58.953649 ==
3000 22:49:58.965789 TX Vref=22, minBit 1, minWin=25, winSum=430
3001 22:49:58.969325 TX Vref=24, minBit 1, minWin=26, winSum=434
3002 22:49:58.972230 TX Vref=26, minBit 0, minWin=27, winSum=440
3003 22:49:58.976065 TX Vref=28, minBit 1, minWin=26, winSum=440
3004 22:49:58.979862 TX Vref=30, minBit 2, minWin=27, winSum=444
3005 22:49:58.983215 TX Vref=32, minBit 1, minWin=26, winSum=440
3006 22:49:58.989421 [TxChooseVref] Worse bit 2, Min win 27, Win sum 444, Final Vref 30
3007 22:49:58.989981
3008 22:49:58.993443 Final TX Range 1 Vref 30
3009 22:49:58.994015
3010 22:49:58.994342 ==
3011 22:49:58.996085 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 22:49:58.999684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 22:49:59.000198 ==
3014 22:49:59.000525
3015 22:49:59.000823
3016 22:49:59.002691 TX Vref Scan disable
3017 22:49:59.005885 == TX Byte 0 ==
3018 22:49:59.009490 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3019 22:49:59.012769 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3020 22:49:59.015648 == TX Byte 1 ==
3021 22:49:59.019554 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3022 22:49:59.022514 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3023 22:49:59.023015
3024 22:49:59.025970 [DATLAT]
3025 22:49:59.026434 Freq=1200, CH0 RK1
3026 22:49:59.026782
3027 22:49:59.029307 DATLAT Default: 0xd
3028 22:49:59.029908 0, 0xFFFF, sum = 0
3029 22:49:59.032273 1, 0xFFFF, sum = 0
3030 22:49:59.032698 2, 0xFFFF, sum = 0
3031 22:49:59.036230 3, 0xFFFF, sum = 0
3032 22:49:59.036655 4, 0xFFFF, sum = 0
3033 22:49:59.039076 5, 0xFFFF, sum = 0
3034 22:49:59.039501 6, 0xFFFF, sum = 0
3035 22:49:59.042553 7, 0xFFFF, sum = 0
3036 22:49:59.043010 8, 0xFFFF, sum = 0
3037 22:49:59.045986 9, 0xFFFF, sum = 0
3038 22:49:59.049284 10, 0xFFFF, sum = 0
3039 22:49:59.049815 11, 0xFFFF, sum = 0
3040 22:49:59.052671 12, 0x0, sum = 1
3041 22:49:59.053120 13, 0x0, sum = 2
3042 22:49:59.053465 14, 0x0, sum = 3
3043 22:49:59.056029 15, 0x0, sum = 4
3044 22:49:59.056451 best_step = 13
3045 22:49:59.056779
3046 22:49:59.058888 ==
3047 22:49:59.059321 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 22:49:59.065741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 22:49:59.066163 ==
3050 22:49:59.066495 RX Vref Scan: 0
3051 22:49:59.066803
3052 22:49:59.069714 RX Vref 0 -> 0, step: 1
3053 22:49:59.070133
3054 22:49:59.072445 RX Delay -37 -> 252, step: 4
3055 22:49:59.076127 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3056 22:49:59.082276 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3057 22:49:59.085956 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3058 22:49:59.089252 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3059 22:49:59.092468 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3060 22:49:59.095999 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3061 22:49:59.099267 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3062 22:49:59.105858 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3063 22:49:59.109849 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3064 22:49:59.112710 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3065 22:49:59.116044 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3066 22:49:59.119462 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3067 22:49:59.125777 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3068 22:49:59.129191 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3069 22:49:59.132616 iDelay=195, Bit 14, Center 110 (43 ~ 178) 136
3070 22:49:59.135548 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3071 22:49:59.136170 ==
3072 22:49:59.139068 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 22:49:59.142545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 22:49:59.145322 ==
3075 22:49:59.145633 DQS Delay:
3076 22:49:59.145883 DQS0 = 0, DQS1 = 0
3077 22:49:59.148592 DQM Delay:
3078 22:49:59.148857 DQM0 = 111, DQM1 = 98
3079 22:49:59.151921 DQ Delay:
3080 22:49:59.155207 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =110
3081 22:49:59.158977 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3082 22:49:59.161951 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3083 22:49:59.165369 DQ12 =108, DQ13 =106, DQ14 =110, DQ15 =108
3084 22:49:59.165485
3085 22:49:59.165617
3086 22:49:59.172277 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3087 22:49:59.175213 CH0 RK1: MR19=403, MR18=13FB
3088 22:49:59.182208 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3089 22:49:59.184932 [RxdqsGatingPostProcess] freq 1200
3090 22:49:59.192025 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 22:49:59.195441 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 22:49:59.195539 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 22:49:59.198811 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 22:49:59.202110 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 22:49:59.205646 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 22:49:59.208458 best DQS1 dly(2T, 0.5T) = (0, 12)
3097 22:49:59.211907 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 22:49:59.215190 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3099 22:49:59.218331 Pre-setting of DQS Precalculation
3100 22:49:59.225059 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 22:49:59.225226 ==
3102 22:49:59.228592 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 22:49:59.232035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 22:49:59.232160 ==
3105 22:49:59.238302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 22:49:59.242215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3107 22:49:59.251072 [CA 0] Center 37 (7~67) winsize 61
3108 22:49:59.254493 [CA 1] Center 37 (7~68) winsize 62
3109 22:49:59.258221 [CA 2] Center 34 (4~64) winsize 61
3110 22:49:59.261616 [CA 3] Center 34 (4~64) winsize 61
3111 22:49:59.264337 [CA 4] Center 34 (4~64) winsize 61
3112 22:49:59.268256 [CA 5] Center 33 (3~63) winsize 61
3113 22:49:59.268363
3114 22:49:59.271042 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3115 22:49:59.271171
3116 22:49:59.274556 [CATrainingPosCal] consider 1 rank data
3117 22:49:59.277955 u2DelayCellTimex100 = 270/100 ps
3118 22:49:59.280855 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3119 22:49:59.287925 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 22:49:59.291118 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 22:49:59.294165 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 22:49:59.298282 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 22:49:59.301018 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3124 22:49:59.301170
3125 22:49:59.304326 CA PerBit enable=1, Macro0, CA PI delay=33
3126 22:49:59.304467
3127 22:49:59.308160 [CBTSetCACLKResult] CA Dly = 33
3128 22:49:59.308300 CS Dly: 5 (0~36)
3129 22:49:59.311174 ==
3130 22:49:59.314176 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 22:49:59.317478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 22:49:59.317638 ==
3133 22:49:59.320789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 22:49:59.327551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3135 22:49:59.337032 [CA 0] Center 37 (7~67) winsize 61
3136 22:49:59.340501 [CA 1] Center 37 (7~68) winsize 62
3137 22:49:59.343302 [CA 2] Center 34 (4~65) winsize 62
3138 22:49:59.347196 [CA 3] Center 33 (3~64) winsize 62
3139 22:49:59.350065 [CA 4] Center 34 (4~65) winsize 62
3140 22:49:59.353464 [CA 5] Center 33 (3~64) winsize 62
3141 22:49:59.353592
3142 22:49:59.357213 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3143 22:49:59.357320
3144 22:49:59.360263 [CATrainingPosCal] consider 2 rank data
3145 22:49:59.363868 u2DelayCellTimex100 = 270/100 ps
3146 22:49:59.367186 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3147 22:49:59.370500 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 22:49:59.376800 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3149 22:49:59.380105 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 22:49:59.383614 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 22:49:59.386953 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3152 22:49:59.387379
3153 22:49:59.390186 CA PerBit enable=1, Macro0, CA PI delay=33
3154 22:49:59.390482
3155 22:49:59.393713 [CBTSetCACLKResult] CA Dly = 33
3156 22:49:59.393935 CS Dly: 6 (0~39)
3157 22:49:59.394111
3158 22:49:59.397072 ----->DramcWriteLeveling(PI) begin...
3159 22:49:59.400402 ==
3160 22:49:59.403646 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 22:49:59.406982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 22:49:59.407131 ==
3163 22:49:59.409982 Write leveling (Byte 0): 25 => 25
3164 22:49:59.413654 Write leveling (Byte 1): 27 => 27
3165 22:49:59.416891 DramcWriteLeveling(PI) end<-----
3166 22:49:59.417003
3167 22:49:59.417091 ==
3168 22:49:59.420134 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 22:49:59.423207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 22:49:59.423308 ==
3171 22:49:59.426591 [Gating] SW mode calibration
3172 22:49:59.433317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 22:49:59.439747 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 22:49:59.443197 0 15 0 | B1->B0 | 3131 2e2e | 1 0 | (1 1) (0 0)
3175 22:49:59.446646 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 22:49:59.450158 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 22:49:59.456892 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 22:49:59.460177 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 22:49:59.463609 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 22:49:59.470111 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 22:49:59.473771 0 15 28 | B1->B0 | 2727 2d2d | 0 0 | (0 0) (0 0)
3182 22:49:59.476819 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 22:49:59.483243 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 22:49:59.486508 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 22:49:59.490079 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 22:49:59.496514 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 22:49:59.499803 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 22:49:59.503029 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3189 22:49:59.509505 1 0 28 | B1->B0 | 4343 3d3c | 0 1 | (0 0) (0 0)
3190 22:49:59.512822 1 1 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3191 22:49:59.516065 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 22:49:59.522822 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 22:49:59.526048 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 22:49:59.529705 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 22:49:59.536307 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 22:49:59.539841 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 22:49:59.543173 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3198 22:49:59.549627 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 22:49:59.552971 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 22:49:59.556533 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 22:49:59.562827 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 22:49:59.566228 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 22:49:59.569598 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 22:49:59.572876 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 22:49:59.579556 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 22:49:59.583152 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 22:49:59.586194 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 22:49:59.592961 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 22:49:59.596494 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 22:49:59.599591 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 22:49:59.606674 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 22:49:59.609445 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 22:49:59.612909 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3214 22:49:59.619901 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 22:49:59.619985 Total UI for P1: 0, mck2ui 16
3216 22:49:59.626297 best dqsien dly found for B0: ( 1, 3, 28)
3217 22:49:59.626382 Total UI for P1: 0, mck2ui 16
3218 22:49:59.632999 best dqsien dly found for B1: ( 1, 3, 30)
3219 22:49:59.636692 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3220 22:49:59.639595 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3221 22:49:59.639715
3222 22:49:59.642991 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3223 22:49:59.646537 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3224 22:49:59.649930 [Gating] SW calibration Done
3225 22:49:59.650056 ==
3226 22:49:59.653435 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 22:49:59.656599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 22:49:59.656743 ==
3229 22:49:59.659846 RX Vref Scan: 0
3230 22:49:59.659978
3231 22:49:59.660084 RX Vref 0 -> 0, step: 1
3232 22:49:59.660192
3233 22:49:59.663082 RX Delay -40 -> 252, step: 8
3234 22:49:59.666703 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3235 22:49:59.673066 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3236 22:49:59.676558 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3237 22:49:59.679547 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3238 22:49:59.683278 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3239 22:49:59.686471 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3240 22:49:59.689576 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3241 22:49:59.696574 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3242 22:49:59.700005 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3243 22:49:59.703498 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3244 22:49:59.706881 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3245 22:49:59.710253 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3246 22:49:59.713578 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3247 22:49:59.719912 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3248 22:49:59.724073 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3249 22:49:59.726726 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3250 22:49:59.726831 ==
3251 22:49:59.730207 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 22:49:59.733432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 22:49:59.736921 ==
3254 22:49:59.737015 DQS Delay:
3255 22:49:59.737080 DQS0 = 0, DQS1 = 0
3256 22:49:59.740376 DQM Delay:
3257 22:49:59.740476 DQM0 = 113, DQM1 = 105
3258 22:49:59.743661 DQ Delay:
3259 22:49:59.746856 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =111
3260 22:49:59.750046 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3261 22:49:59.753441 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
3262 22:49:59.757046 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3263 22:49:59.757127
3264 22:49:59.757189
3265 22:49:59.757247 ==
3266 22:49:59.760358 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 22:49:59.763793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 22:49:59.763875 ==
3269 22:49:59.763938
3270 22:49:59.763997
3271 22:49:59.766823 TX Vref Scan disable
3272 22:49:59.770102 == TX Byte 0 ==
3273 22:49:59.773900 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3274 22:49:59.776751 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3275 22:49:59.780515 == TX Byte 1 ==
3276 22:49:59.783473 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3277 22:49:59.787152 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3278 22:49:59.787711 ==
3279 22:49:59.790625 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 22:49:59.794029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 22:49:59.797024 ==
3282 22:49:59.806742 TX Vref=22, minBit 10, minWin=24, winSum=409
3283 22:49:59.810230 TX Vref=24, minBit 10, minWin=24, winSum=413
3284 22:49:59.813746 TX Vref=26, minBit 9, minWin=25, winSum=418
3285 22:49:59.817387 TX Vref=28, minBit 9, minWin=25, winSum=421
3286 22:49:59.820176 TX Vref=30, minBit 9, minWin=25, winSum=421
3287 22:49:59.823893 TX Vref=32, minBit 9, minWin=25, winSum=421
3288 22:49:59.830226 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
3289 22:49:59.830657
3290 22:49:59.833741 Final TX Range 1 Vref 28
3291 22:49:59.834157
3292 22:49:59.834480 ==
3293 22:49:59.837264 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 22:49:59.840218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 22:49:59.840637 ==
3296 22:49:59.840957
3297 22:49:59.843713
3298 22:49:59.844280 TX Vref Scan disable
3299 22:49:59.847216 == TX Byte 0 ==
3300 22:49:59.850562 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3301 22:49:59.853807 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3302 22:49:59.856797 == TX Byte 1 ==
3303 22:49:59.860038 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3304 22:49:59.863587 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3305 22:49:59.864002
3306 22:49:59.867220 [DATLAT]
3307 22:49:59.867738 Freq=1200, CH1 RK0
3308 22:49:59.868067
3309 22:49:59.870690 DATLAT Default: 0xd
3310 22:49:59.871204 0, 0xFFFF, sum = 0
3311 22:49:59.873955 1, 0xFFFF, sum = 0
3312 22:49:59.874372 2, 0xFFFF, sum = 0
3313 22:49:59.877262 3, 0xFFFF, sum = 0
3314 22:49:59.877704 4, 0xFFFF, sum = 0
3315 22:49:59.880861 5, 0xFFFF, sum = 0
3316 22:49:59.881388 6, 0xFFFF, sum = 0
3317 22:49:59.884050 7, 0xFFFF, sum = 0
3318 22:49:59.886887 8, 0xFFFF, sum = 0
3319 22:49:59.887327 9, 0xFFFF, sum = 0
3320 22:49:59.890480 10, 0xFFFF, sum = 0
3321 22:49:59.890899 11, 0xFFFF, sum = 0
3322 22:49:59.893932 12, 0x0, sum = 1
3323 22:49:59.894351 13, 0x0, sum = 2
3324 22:49:59.897260 14, 0x0, sum = 3
3325 22:49:59.897904 15, 0x0, sum = 4
3326 22:49:59.898250 best_step = 13
3327 22:49:59.898616
3328 22:49:59.900647 ==
3329 22:49:59.901177 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 22:49:59.907194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 22:49:59.907609 ==
3332 22:49:59.907934 RX Vref Scan: 1
3333 22:49:59.908235
3334 22:49:59.910239 Set Vref Range= 32 -> 127
3335 22:49:59.910646
3336 22:49:59.913917 RX Vref 32 -> 127, step: 1
3337 22:49:59.914458
3338 22:49:59.916821 RX Delay -21 -> 252, step: 4
3339 22:49:59.917230
3340 22:49:59.920186 Set Vref, RX VrefLevel [Byte0]: 32
3341 22:49:59.923510 [Byte1]: 32
3342 22:49:59.923944
3343 22:49:59.926968 Set Vref, RX VrefLevel [Byte0]: 33
3344 22:49:59.930338 [Byte1]: 33
3345 22:49:59.930747
3346 22:49:59.933418 Set Vref, RX VrefLevel [Byte0]: 34
3347 22:49:59.937007 [Byte1]: 34
3348 22:49:59.941729
3349 22:49:59.942136 Set Vref, RX VrefLevel [Byte0]: 35
3350 22:49:59.944728 [Byte1]: 35
3351 22:49:59.949392
3352 22:49:59.949941 Set Vref, RX VrefLevel [Byte0]: 36
3353 22:49:59.952577 [Byte1]: 36
3354 22:49:59.957215
3355 22:49:59.957653 Set Vref, RX VrefLevel [Byte0]: 37
3356 22:49:59.960599 [Byte1]: 37
3357 22:49:59.965087
3358 22:49:59.965497 Set Vref, RX VrefLevel [Byte0]: 38
3359 22:49:59.968080 [Byte1]: 38
3360 22:49:59.972809
3361 22:49:59.973214 Set Vref, RX VrefLevel [Byte0]: 39
3362 22:49:59.976309 [Byte1]: 39
3363 22:49:59.980930
3364 22:49:59.981338 Set Vref, RX VrefLevel [Byte0]: 40
3365 22:49:59.983777 [Byte1]: 40
3366 22:49:59.988445
3367 22:49:59.988855 Set Vref, RX VrefLevel [Byte0]: 41
3368 22:49:59.991887 [Byte1]: 41
3369 22:49:59.996821
3370 22:49:59.997227 Set Vref, RX VrefLevel [Byte0]: 42
3371 22:50:00.000129 [Byte1]: 42
3372 22:50:00.004609
3373 22:50:00.005122 Set Vref, RX VrefLevel [Byte0]: 43
3374 22:50:00.007924 [Byte1]: 43
3375 22:50:00.012297
3376 22:50:00.012779 Set Vref, RX VrefLevel [Byte0]: 44
3377 22:50:00.015858 [Byte1]: 44
3378 22:50:00.020287
3379 22:50:00.020839 Set Vref, RX VrefLevel [Byte0]: 45
3380 22:50:00.023853 [Byte1]: 45
3381 22:50:00.028369
3382 22:50:00.028780 Set Vref, RX VrefLevel [Byte0]: 46
3383 22:50:00.031982 [Byte1]: 46
3384 22:50:00.036334
3385 22:50:00.036743 Set Vref, RX VrefLevel [Byte0]: 47
3386 22:50:00.039398 [Byte1]: 47
3387 22:50:00.044200
3388 22:50:00.044606 Set Vref, RX VrefLevel [Byte0]: 48
3389 22:50:00.047868 [Byte1]: 48
3390 22:50:00.052200
3391 22:50:00.052607 Set Vref, RX VrefLevel [Byte0]: 49
3392 22:50:00.055661 [Byte1]: 49
3393 22:50:00.060062
3394 22:50:00.060471 Set Vref, RX VrefLevel [Byte0]: 50
3395 22:50:00.063441 [Byte1]: 50
3396 22:50:00.068310
3397 22:50:00.068731 Set Vref, RX VrefLevel [Byte0]: 51
3398 22:50:00.071302 [Byte1]: 51
3399 22:50:00.075995
3400 22:50:00.076402 Set Vref, RX VrefLevel [Byte0]: 52
3401 22:50:00.078943 [Byte1]: 52
3402 22:50:00.083734
3403 22:50:00.084156 Set Vref, RX VrefLevel [Byte0]: 53
3404 22:50:00.087281 [Byte1]: 53
3405 22:50:00.091851
3406 22:50:00.092260 Set Vref, RX VrefLevel [Byte0]: 54
3407 22:50:00.094931 [Byte1]: 54
3408 22:50:00.099885
3409 22:50:00.100294 Set Vref, RX VrefLevel [Byte0]: 55
3410 22:50:00.102821 [Byte1]: 55
3411 22:50:00.107864
3412 22:50:00.108419 Set Vref, RX VrefLevel [Byte0]: 56
3413 22:50:00.111131 [Byte1]: 56
3414 22:50:00.115609
3415 22:50:00.116021 Set Vref, RX VrefLevel [Byte0]: 57
3416 22:50:00.118808 [Byte1]: 57
3417 22:50:00.123443
3418 22:50:00.123851 Set Vref, RX VrefLevel [Byte0]: 58
3419 22:50:00.126833 [Byte1]: 58
3420 22:50:00.131626
3421 22:50:00.132140 Set Vref, RX VrefLevel [Byte0]: 59
3422 22:50:00.134546 [Byte1]: 59
3423 22:50:00.139234
3424 22:50:00.139641 Set Vref, RX VrefLevel [Byte0]: 60
3425 22:50:00.142852 [Byte1]: 60
3426 22:50:00.146968
3427 22:50:00.147379 Set Vref, RX VrefLevel [Byte0]: 61
3428 22:50:00.150659 [Byte1]: 61
3429 22:50:00.154666
3430 22:50:00.155075 Set Vref, RX VrefLevel [Byte0]: 62
3431 22:50:00.158176 [Byte1]: 62
3432 22:50:00.163303
3433 22:50:00.163712 Set Vref, RX VrefLevel [Byte0]: 63
3434 22:50:00.166045 [Byte1]: 63
3435 22:50:00.170773
3436 22:50:00.171181 Set Vref, RX VrefLevel [Byte0]: 64
3437 22:50:00.174155 [Byte1]: 64
3438 22:50:00.178533
3439 22:50:00.178942 Set Vref, RX VrefLevel [Byte0]: 65
3440 22:50:00.182205 [Byte1]: 65
3441 22:50:00.186923
3442 22:50:00.187331 Set Vref, RX VrefLevel [Byte0]: 66
3443 22:50:00.189859 [Byte1]: 66
3444 22:50:00.194744
3445 22:50:00.195157 Final RX Vref Byte 0 = 57 to rank0
3446 22:50:00.198062 Final RX Vref Byte 1 = 46 to rank0
3447 22:50:00.201253 Final RX Vref Byte 0 = 57 to rank1
3448 22:50:00.204878 Final RX Vref Byte 1 = 46 to rank1==
3449 22:50:00.207840 Dram Type= 6, Freq= 0, CH_1, rank 0
3450 22:50:00.211627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 22:50:00.215062 ==
3452 22:50:00.215472 DQS Delay:
3453 22:50:00.215798 DQS0 = 0, DQS1 = 0
3454 22:50:00.217836 DQM Delay:
3455 22:50:00.218250 DQM0 = 114, DQM1 = 104
3456 22:50:00.221148 DQ Delay:
3457 22:50:00.224479 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3458 22:50:00.227911 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3459 22:50:00.231318 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =98
3460 22:50:00.234736 DQ12 =114, DQ13 =110, DQ14 =112, DQ15 =110
3461 22:50:00.235156
3462 22:50:00.235480
3463 22:50:00.241326 [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3464 22:50:00.244672 CH1 RK0: MR19=303, MR18=EEF5
3465 22:50:00.251511 CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25
3466 22:50:00.251933
3467 22:50:00.254571 ----->DramcWriteLeveling(PI) begin...
3468 22:50:00.254994 ==
3469 22:50:00.257949 Dram Type= 6, Freq= 0, CH_1, rank 1
3470 22:50:00.261361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 22:50:00.261823 ==
3472 22:50:00.264745 Write leveling (Byte 0): 25 => 25
3473 22:50:00.267640 Write leveling (Byte 1): 29 => 29
3474 22:50:00.271191 DramcWriteLeveling(PI) end<-----
3475 22:50:00.271618
3476 22:50:00.272038 ==
3477 22:50:00.274506 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 22:50:00.281223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 22:50:00.281666 ==
3480 22:50:00.281992 [Gating] SW mode calibration
3481 22:50:00.291012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3482 22:50:00.294455 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3483 22:50:00.297852 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 22:50:00.304324 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 22:50:00.307698 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 22:50:00.311236 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 22:50:00.317499 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 22:50:00.321143 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 22:50:00.324077 0 15 24 | B1->B0 | 3232 2727 | 0 0 | (0 1) (1 0)
3490 22:50:00.330962 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3491 22:50:00.333968 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 22:50:00.337463 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 22:50:00.344171 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 22:50:00.347795 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 22:50:00.350806 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 22:50:00.357318 1 0 20 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
3497 22:50:00.361097 1 0 24 | B1->B0 | 2d2d 4545 | 0 1 | (0 0) (0 0)
3498 22:50:00.364524 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3499 22:50:00.370633 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 22:50:00.374298 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 22:50:00.377233 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 22:50:00.384229 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 22:50:00.387540 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 22:50:00.390430 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3505 22:50:00.397451 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3506 22:50:00.400389 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3507 22:50:00.403990 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 22:50:00.410671 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 22:50:00.414074 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 22:50:00.417465 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 22:50:00.423591 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 22:50:00.426836 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 22:50:00.430154 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 22:50:00.437275 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 22:50:00.440303 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 22:50:00.444043 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 22:50:00.450273 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 22:50:00.453769 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 22:50:00.457086 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 22:50:00.460284 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3521 22:50:00.467030 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3522 22:50:00.470516 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3523 22:50:00.473322 Total UI for P1: 0, mck2ui 16
3524 22:50:00.476623 best dqsien dly found for B0: ( 1, 3, 24)
3525 22:50:00.479829 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 22:50:00.483468 Total UI for P1: 0, mck2ui 16
3527 22:50:00.486523 best dqsien dly found for B1: ( 1, 3, 28)
3528 22:50:00.489933 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3529 22:50:00.496986 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3530 22:50:00.497649
3531 22:50:00.499898 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3532 22:50:00.503058 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3533 22:50:00.506389 [Gating] SW calibration Done
3534 22:50:00.506774 ==
3535 22:50:00.509710 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 22:50:00.513302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 22:50:00.513711 ==
3538 22:50:00.513956 RX Vref Scan: 0
3539 22:50:00.516762
3540 22:50:00.517143 RX Vref 0 -> 0, step: 1
3541 22:50:00.517473
3542 22:50:00.519758 RX Delay -40 -> 252, step: 8
3543 22:50:00.523248 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3544 22:50:00.526633 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3545 22:50:00.532933 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3546 22:50:00.536271 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3547 22:50:00.539787 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3548 22:50:00.542985 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3549 22:50:00.546546 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3550 22:50:00.553406 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3551 22:50:00.556828 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3552 22:50:00.559767 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3553 22:50:00.562899 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3554 22:50:00.566750 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3555 22:50:00.573153 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3556 22:50:00.576430 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3557 22:50:00.579428 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3558 22:50:00.582955 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3559 22:50:00.583260 ==
3560 22:50:00.585881 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 22:50:00.593194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 22:50:00.593621 ==
3563 22:50:00.593933 DQS Delay:
3564 22:50:00.594225 DQS0 = 0, DQS1 = 0
3565 22:50:00.595935 DQM Delay:
3566 22:50:00.596240 DQM0 = 110, DQM1 = 106
3567 22:50:00.599313 DQ Delay:
3568 22:50:00.603139 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3569 22:50:00.605902 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3570 22:50:00.609147 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3571 22:50:00.612338 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =115
3572 22:50:00.612643
3573 22:50:00.612950
3574 22:50:00.613241 ==
3575 22:50:00.615692 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 22:50:00.619074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 22:50:00.622490 ==
3578 22:50:00.622857
3579 22:50:00.623208
3580 22:50:00.623567 TX Vref Scan disable
3581 22:50:00.625640 == TX Byte 0 ==
3582 22:50:00.628715 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3583 22:50:00.632147 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3584 22:50:00.635598 == TX Byte 1 ==
3585 22:50:00.639228 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3586 22:50:00.642686 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3587 22:50:00.643114 ==
3588 22:50:00.645427 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 22:50:00.652036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 22:50:00.652357 ==
3591 22:50:00.663340 TX Vref=22, minBit 9, minWin=25, winSum=425
3592 22:50:00.666356 TX Vref=24, minBit 1, minWin=26, winSum=428
3593 22:50:00.669742 TX Vref=26, minBit 8, minWin=26, winSum=434
3594 22:50:00.673124 TX Vref=28, minBit 8, minWin=26, winSum=436
3595 22:50:00.676627 TX Vref=30, minBit 1, minWin=27, winSum=439
3596 22:50:00.683019 TX Vref=32, minBit 3, minWin=26, winSum=434
3597 22:50:00.686670 [TxChooseVref] Worse bit 1, Min win 27, Win sum 439, Final Vref 30
3598 22:50:00.686963
3599 22:50:00.689585 Final TX Range 1 Vref 30
3600 22:50:00.689990
3601 22:50:00.690358 ==
3602 22:50:00.693296 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 22:50:00.696187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 22:50:00.699654 ==
3605 22:50:00.700061
3606 22:50:00.700328
3607 22:50:00.700549 TX Vref Scan disable
3608 22:50:00.703287 == TX Byte 0 ==
3609 22:50:00.706209 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3610 22:50:00.712856 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3611 22:50:00.713242 == TX Byte 1 ==
3612 22:50:00.716435 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3613 22:50:00.722986 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3614 22:50:00.723307
3615 22:50:00.723568 [DATLAT]
3616 22:50:00.723787 Freq=1200, CH1 RK1
3617 22:50:00.723994
3618 22:50:00.726043 DATLAT Default: 0xd
3619 22:50:00.726391 0, 0xFFFF, sum = 0
3620 22:50:00.729477 1, 0xFFFF, sum = 0
3621 22:50:00.729851 2, 0xFFFF, sum = 0
3622 22:50:00.732998 3, 0xFFFF, sum = 0
3623 22:50:00.736233 4, 0xFFFF, sum = 0
3624 22:50:00.736638 5, 0xFFFF, sum = 0
3625 22:50:00.739557 6, 0xFFFF, sum = 0
3626 22:50:00.739936 7, 0xFFFF, sum = 0
3627 22:50:00.742820 8, 0xFFFF, sum = 0
3628 22:50:00.743215 9, 0xFFFF, sum = 0
3629 22:50:00.746400 10, 0xFFFF, sum = 0
3630 22:50:00.746757 11, 0xFFFF, sum = 0
3631 22:50:00.749924 12, 0x0, sum = 1
3632 22:50:00.750261 13, 0x0, sum = 2
3633 22:50:00.752730 14, 0x0, sum = 3
3634 22:50:00.753059 15, 0x0, sum = 4
3635 22:50:00.753433 best_step = 13
3636 22:50:00.756139
3637 22:50:00.756441 ==
3638 22:50:00.759460 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 22:50:00.763000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 22:50:00.763306 ==
3641 22:50:00.763616 RX Vref Scan: 0
3642 22:50:00.763909
3643 22:50:00.766474 RX Vref 0 -> 0, step: 1
3644 22:50:00.766777
3645 22:50:00.769294 RX Delay -21 -> 252, step: 4
3646 22:50:00.772429 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3647 22:50:00.779541 iDelay=195, Bit 1, Center 106 (39 ~ 174) 136
3648 22:50:00.782769 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3649 22:50:00.785946 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3650 22:50:00.789236 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3651 22:50:00.792829 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3652 22:50:00.799177 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3653 22:50:00.802220 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3654 22:50:00.805797 iDelay=195, Bit 8, Center 92 (27 ~ 158) 132
3655 22:50:00.808969 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3656 22:50:00.812544 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3657 22:50:00.818885 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3658 22:50:00.822087 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3659 22:50:00.825643 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3660 22:50:00.828866 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3661 22:50:00.835271 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3662 22:50:00.835657 ==
3663 22:50:00.838583 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 22:50:00.841840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 22:50:00.842257 ==
3666 22:50:00.842527 DQS Delay:
3667 22:50:00.845103 DQS0 = 0, DQS1 = 0
3668 22:50:00.845503 DQM Delay:
3669 22:50:00.848537 DQM0 = 111, DQM1 = 109
3670 22:50:00.848887 DQ Delay:
3671 22:50:00.851871 DQ0 =114, DQ1 =106, DQ2 =100, DQ3 =108
3672 22:50:00.854816 DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =110
3673 22:50:00.858138 DQ8 =92, DQ9 =102, DQ10 =110, DQ11 =102
3674 22:50:00.861474 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =118
3675 22:50:00.861617
3676 22:50:00.865053
3677 22:50:00.871220 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3678 22:50:00.874643 CH1 RK1: MR19=304, MR18=FB0A
3679 22:50:00.881422 CH1_RK1: MR19=0x304, MR18=0xFB0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3680 22:50:00.884980 [RxdqsGatingPostProcess] freq 1200
3681 22:50:00.888290 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3682 22:50:00.891661 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 22:50:00.894926 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 22:50:00.898090 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 22:50:00.901631 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 22:50:00.904983 best DQS0 dly(2T, 0.5T) = (0, 11)
3687 22:50:00.908272 best DQS1 dly(2T, 0.5T) = (0, 11)
3688 22:50:00.911144 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3689 22:50:00.914621 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3690 22:50:00.917701 Pre-setting of DQS Precalculation
3691 22:50:00.921202 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3692 22:50:00.927954 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3693 22:50:00.937862 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3694 22:50:00.938247
3695 22:50:00.938545
3696 22:50:00.941295 [Calibration Summary] 2400 Mbps
3697 22:50:00.941862 CH 0, Rank 0
3698 22:50:00.944592 SW Impedance : PASS
3699 22:50:00.945082 DUTY Scan : NO K
3700 22:50:00.947649 ZQ Calibration : PASS
3701 22:50:00.951553 Jitter Meter : NO K
3702 22:50:00.951928 CBT Training : PASS
3703 22:50:00.954711 Write leveling : PASS
3704 22:50:00.958291 RX DQS gating : PASS
3705 22:50:00.958667 RX DQ/DQS(RDDQC) : PASS
3706 22:50:00.961279 TX DQ/DQS : PASS
3707 22:50:00.964227 RX DATLAT : PASS
3708 22:50:00.964608 RX DQ/DQS(Engine): PASS
3709 22:50:00.967899 TX OE : NO K
3710 22:50:00.968276 All Pass.
3711 22:50:00.968574
3712 22:50:00.971002 CH 0, Rank 1
3713 22:50:00.971400 SW Impedance : PASS
3714 22:50:00.974130 DUTY Scan : NO K
3715 22:50:00.974528 ZQ Calibration : PASS
3716 22:50:00.977363 Jitter Meter : NO K
3717 22:50:00.980584 CBT Training : PASS
3718 22:50:00.980968 Write leveling : PASS
3719 22:50:00.984649 RX DQS gating : PASS
3720 22:50:00.987440 RX DQ/DQS(RDDQC) : PASS
3721 22:50:00.987884 TX DQ/DQS : PASS
3722 22:50:00.990708 RX DATLAT : PASS
3723 22:50:00.994315 RX DQ/DQS(Engine): PASS
3724 22:50:00.994746 TX OE : NO K
3725 22:50:00.997844 All Pass.
3726 22:50:00.998218
3727 22:50:00.998558 CH 1, Rank 0
3728 22:50:01.000501 SW Impedance : PASS
3729 22:50:01.000910 DUTY Scan : NO K
3730 22:50:01.004315 ZQ Calibration : PASS
3731 22:50:01.007478 Jitter Meter : NO K
3732 22:50:01.007983 CBT Training : PASS
3733 22:50:01.010436 Write leveling : PASS
3734 22:50:01.013600 RX DQS gating : PASS
3735 22:50:01.013705 RX DQ/DQS(RDDQC) : PASS
3736 22:50:01.016879 TX DQ/DQS : PASS
3737 22:50:01.020459 RX DATLAT : PASS
3738 22:50:01.020538 RX DQ/DQS(Engine): PASS
3739 22:50:01.023409 TX OE : NO K
3740 22:50:01.023507 All Pass.
3741 22:50:01.023595
3742 22:50:01.026541 CH 1, Rank 1
3743 22:50:01.026610 SW Impedance : PASS
3744 22:50:01.029938 DUTY Scan : NO K
3745 22:50:01.033381 ZQ Calibration : PASS
3746 22:50:01.033486 Jitter Meter : NO K
3747 22:50:01.036566 CBT Training : PASS
3748 22:50:01.036663 Write leveling : PASS
3749 22:50:01.039996 RX DQS gating : PASS
3750 22:50:01.043126 RX DQ/DQS(RDDQC) : PASS
3751 22:50:01.043221 TX DQ/DQS : PASS
3752 22:50:01.046483 RX DATLAT : PASS
3753 22:50:01.049874 RX DQ/DQS(Engine): PASS
3754 22:50:01.049979 TX OE : NO K
3755 22:50:01.053316 All Pass.
3756 22:50:01.053429
3757 22:50:01.053570 DramC Write-DBI off
3758 22:50:01.056802 PER_BANK_REFRESH: Hybrid Mode
3759 22:50:01.059665 TX_TRACKING: ON
3760 22:50:01.066507 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3761 22:50:01.069743 [FAST_K] Save calibration result to emmc
3762 22:50:01.073471 dramc_set_vcore_voltage set vcore to 650000
3763 22:50:01.076192 Read voltage for 600, 5
3764 22:50:01.076368 Vio18 = 0
3765 22:50:01.080065 Vcore = 650000
3766 22:50:01.080268 Vdram = 0
3767 22:50:01.080481 Vddq = 0
3768 22:50:01.082888 Vmddr = 0
3769 22:50:01.086462 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3770 22:50:01.093047 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3771 22:50:01.096286 MEM_TYPE=3, freq_sel=19
3772 22:50:01.096661 sv_algorithm_assistance_LP4_1600
3773 22:50:01.102761 ============ PULL DRAM RESETB DOWN ============
3774 22:50:01.106639 ========== PULL DRAM RESETB DOWN end =========
3775 22:50:01.109869 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3776 22:50:01.113230 ===================================
3777 22:50:01.116698 LPDDR4 DRAM CONFIGURATION
3778 22:50:01.120090 ===================================
3779 22:50:01.122997 EX_ROW_EN[0] = 0x0
3780 22:50:01.123446 EX_ROW_EN[1] = 0x0
3781 22:50:01.126481 LP4Y_EN = 0x0
3782 22:50:01.126880 WORK_FSP = 0x0
3783 22:50:01.129469 WL = 0x2
3784 22:50:01.130034 RL = 0x2
3785 22:50:01.132985 BL = 0x2
3786 22:50:01.133481 RPST = 0x0
3787 22:50:01.136185 RD_PRE = 0x0
3788 22:50:01.136581 WR_PRE = 0x1
3789 22:50:01.139695 WR_PST = 0x0
3790 22:50:01.140143 DBI_WR = 0x0
3791 22:50:01.142547 DBI_RD = 0x0
3792 22:50:01.142975 OTF = 0x1
3793 22:50:01.146259 ===================================
3794 22:50:01.149434 ===================================
3795 22:50:01.152553 ANA top config
3796 22:50:01.156070 ===================================
3797 22:50:01.159616 DLL_ASYNC_EN = 0
3798 22:50:01.160048 ALL_SLAVE_EN = 1
3799 22:50:01.162384 NEW_RANK_MODE = 1
3800 22:50:01.165760 DLL_IDLE_MODE = 1
3801 22:50:01.169418 LP45_APHY_COMB_EN = 1
3802 22:50:01.172350 TX_ODT_DIS = 1
3803 22:50:01.172735 NEW_8X_MODE = 1
3804 22:50:01.175711 ===================================
3805 22:50:01.179352 ===================================
3806 22:50:01.182561 data_rate = 1200
3807 22:50:01.185493 CKR = 1
3808 22:50:01.188811 DQ_P2S_RATIO = 8
3809 22:50:01.192281 ===================================
3810 22:50:01.195251 CA_P2S_RATIO = 8
3811 22:50:01.198723 DQ_CA_OPEN = 0
3812 22:50:01.199108 DQ_SEMI_OPEN = 0
3813 22:50:01.202071 CA_SEMI_OPEN = 0
3814 22:50:01.205198 CA_FULL_RATE = 0
3815 22:50:01.208504 DQ_CKDIV4_EN = 1
3816 22:50:01.212294 CA_CKDIV4_EN = 1
3817 22:50:01.215399 CA_PREDIV_EN = 0
3818 22:50:01.215937 PH8_DLY = 0
3819 22:50:01.218375 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3820 22:50:01.221868 DQ_AAMCK_DIV = 4
3821 22:50:01.225393 CA_AAMCK_DIV = 4
3822 22:50:01.228648 CA_ADMCK_DIV = 4
3823 22:50:01.231853 DQ_TRACK_CA_EN = 0
3824 22:50:01.232239 CA_PICK = 600
3825 22:50:01.235761 CA_MCKIO = 600
3826 22:50:01.238955 MCKIO_SEMI = 0
3827 22:50:01.242337 PLL_FREQ = 2288
3828 22:50:01.245143 DQ_UI_PI_RATIO = 32
3829 22:50:01.248625 CA_UI_PI_RATIO = 0
3830 22:50:01.252126 ===================================
3831 22:50:01.254972 ===================================
3832 22:50:01.258270 memory_type:LPDDR4
3833 22:50:01.258689 GP_NUM : 10
3834 22:50:01.261917 SRAM_EN : 1
3835 22:50:01.262335 MD32_EN : 0
3836 22:50:01.265262 ===================================
3837 22:50:01.268294 [ANA_INIT] >>>>>>>>>>>>>>
3838 22:50:01.271623 <<<<<< [CONFIGURE PHASE]: ANA_TX
3839 22:50:01.275376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3840 22:50:01.278723 ===================================
3841 22:50:01.281336 data_rate = 1200,PCW = 0X5800
3842 22:50:01.285109 ===================================
3843 22:50:01.288876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3844 22:50:01.294832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3845 22:50:01.298359 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 22:50:01.305322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3847 22:50:01.308592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3848 22:50:01.311579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3849 22:50:01.312055 [ANA_INIT] flow start
3850 22:50:01.314539 [ANA_INIT] PLL >>>>>>>>
3851 22:50:01.318071 [ANA_INIT] PLL <<<<<<<<
3852 22:50:01.318532 [ANA_INIT] MIDPI >>>>>>>>
3853 22:50:01.321138 [ANA_INIT] MIDPI <<<<<<<<
3854 22:50:01.324564 [ANA_INIT] DLL >>>>>>>>
3855 22:50:01.325027 [ANA_INIT] flow end
3856 22:50:01.331739 ============ LP4 DIFF to SE enter ============
3857 22:50:01.334922 ============ LP4 DIFF to SE exit ============
3858 22:50:01.337472 [ANA_INIT] <<<<<<<<<<<<<
3859 22:50:01.340810 [Flow] Enable top DCM control >>>>>
3860 22:50:01.344586 [Flow] Enable top DCM control <<<<<
3861 22:50:01.345139 Enable DLL master slave shuffle
3862 22:50:01.351430 ==============================================================
3863 22:50:01.354105 Gating Mode config
3864 22:50:01.357909 ==============================================================
3865 22:50:01.361142 Config description:
3866 22:50:01.370889 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3867 22:50:01.377816 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3868 22:50:01.380536 SELPH_MODE 0: By rank 1: By Phase
3869 22:50:01.387641 ==============================================================
3870 22:50:01.390405 GAT_TRACK_EN = 1
3871 22:50:01.393680 RX_GATING_MODE = 2
3872 22:50:01.397884 RX_GATING_TRACK_MODE = 2
3873 22:50:01.400704 SELPH_MODE = 1
3874 22:50:01.401182 PICG_EARLY_EN = 1
3875 22:50:01.404084 VALID_LAT_VALUE = 1
3876 22:50:01.410773 ==============================================================
3877 22:50:01.414159 Enter into Gating configuration >>>>
3878 22:50:01.416812 Exit from Gating configuration <<<<
3879 22:50:01.420378 Enter into DVFS_PRE_config >>>>>
3880 22:50:01.430297 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3881 22:50:01.433603 Exit from DVFS_PRE_config <<<<<
3882 22:50:01.437100 Enter into PICG configuration >>>>
3883 22:50:01.440307 Exit from PICG configuration <<<<
3884 22:50:01.443630 [RX_INPUT] configuration >>>>>
3885 22:50:01.446716 [RX_INPUT] configuration <<<<<
3886 22:50:01.453647 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3887 22:50:01.456769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3888 22:50:01.462957 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 22:50:01.470205 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 22:50:01.476964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 22:50:01.483662 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 22:50:01.486538 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3893 22:50:01.489909 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3894 22:50:01.493065 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3895 22:50:01.500284 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3896 22:50:01.503124 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3897 22:50:01.506388 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 22:50:01.510118 ===================================
3899 22:50:01.512893 LPDDR4 DRAM CONFIGURATION
3900 22:50:01.516412 ===================================
3901 22:50:01.516919 EX_ROW_EN[0] = 0x0
3902 22:50:01.519851 EX_ROW_EN[1] = 0x0
3903 22:50:01.522706 LP4Y_EN = 0x0
3904 22:50:01.523159 WORK_FSP = 0x0
3905 22:50:01.526190 WL = 0x2
3906 22:50:01.526648 RL = 0x2
3907 22:50:01.529502 BL = 0x2
3908 22:50:01.529936 RPST = 0x0
3909 22:50:01.532983 RD_PRE = 0x0
3910 22:50:01.533396 WR_PRE = 0x1
3911 22:50:01.535890 WR_PST = 0x0
3912 22:50:01.536300 DBI_WR = 0x0
3913 22:50:01.539776 DBI_RD = 0x0
3914 22:50:01.540189 OTF = 0x1
3915 22:50:01.542735 ===================================
3916 22:50:01.545765 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3917 22:50:01.552592 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3918 22:50:01.555840 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3919 22:50:01.559195 ===================================
3920 22:50:01.562317 LPDDR4 DRAM CONFIGURATION
3921 22:50:01.566021 ===================================
3922 22:50:01.566435 EX_ROW_EN[0] = 0x10
3923 22:50:01.568813 EX_ROW_EN[1] = 0x0
3924 22:50:01.572269 LP4Y_EN = 0x0
3925 22:50:01.572682 WORK_FSP = 0x0
3926 22:50:01.575680 WL = 0x2
3927 22:50:01.576094 RL = 0x2
3928 22:50:01.578896 BL = 0x2
3929 22:50:01.579309 RPST = 0x0
3930 22:50:01.582336 RD_PRE = 0x0
3931 22:50:01.582751 WR_PRE = 0x1
3932 22:50:01.585330 WR_PST = 0x0
3933 22:50:01.585765 DBI_WR = 0x0
3934 22:50:01.588758 DBI_RD = 0x0
3935 22:50:01.589274 OTF = 0x1
3936 22:50:01.591741 ===================================
3937 22:50:01.598522 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3938 22:50:01.602990 nWR fixed to 30
3939 22:50:01.606213 [ModeRegInit_LP4] CH0 RK0
3940 22:50:01.606625 [ModeRegInit_LP4] CH0 RK1
3941 22:50:01.609317 [ModeRegInit_LP4] CH1 RK0
3942 22:50:01.613055 [ModeRegInit_LP4] CH1 RK1
3943 22:50:01.613468 match AC timing 17
3944 22:50:01.619494 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3945 22:50:01.622643 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3946 22:50:01.626136 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3947 22:50:01.633161 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3948 22:50:01.636645 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3949 22:50:01.637162 ==
3950 22:50:01.640093 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 22:50:01.642663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 22:50:01.643157 ==
3953 22:50:01.650034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 22:50:01.656224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3955 22:50:01.659245 [CA 0] Center 37 (7~67) winsize 61
3956 22:50:01.662750 [CA 1] Center 36 (6~67) winsize 62
3957 22:50:01.666218 [CA 2] Center 35 (5~65) winsize 61
3958 22:50:01.669664 [CA 3] Center 35 (5~65) winsize 61
3959 22:50:01.672825 [CA 4] Center 34 (4~64) winsize 61
3960 22:50:01.675999 [CA 5] Center 34 (4~64) winsize 61
3961 22:50:01.676560
3962 22:50:01.679190 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3963 22:50:01.679756
3964 22:50:01.682505 [CATrainingPosCal] consider 1 rank data
3965 22:50:01.685915 u2DelayCellTimex100 = 270/100 ps
3966 22:50:01.689311 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3967 22:50:01.692843 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3968 22:50:01.696050 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3969 22:50:01.699476 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3970 22:50:01.706065 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3971 22:50:01.709198 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3972 22:50:01.709699
3973 22:50:01.712385 CA PerBit enable=1, Macro0, CA PI delay=34
3974 22:50:01.712948
3975 22:50:01.715372 [CBTSetCACLKResult] CA Dly = 34
3976 22:50:01.715841 CS Dly: 6 (0~37)
3977 22:50:01.716203 ==
3978 22:50:01.718739 Dram Type= 6, Freq= 0, CH_0, rank 1
3979 22:50:01.725492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 22:50:01.726095 ==
3981 22:50:01.728906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 22:50:01.735545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3983 22:50:01.739000 [CA 0] Center 37 (7~67) winsize 61
3984 22:50:01.742504 [CA 1] Center 37 (7~67) winsize 61
3985 22:50:01.745360 [CA 2] Center 35 (5~65) winsize 61
3986 22:50:01.748971 [CA 3] Center 35 (5~65) winsize 61
3987 22:50:01.752309 [CA 4] Center 34 (3~65) winsize 63
3988 22:50:01.755723 [CA 5] Center 34 (3~65) winsize 63
3989 22:50:01.756240
3990 22:50:01.759228 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3991 22:50:01.759748
3992 22:50:01.761875 [CATrainingPosCal] consider 2 rank data
3993 22:50:01.765627 u2DelayCellTimex100 = 270/100 ps
3994 22:50:01.768848 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3995 22:50:01.772241 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3996 22:50:01.778855 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3997 22:50:01.781909 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3998 22:50:01.785742 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3999 22:50:01.788901 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4000 22:50:01.789415
4001 22:50:01.792571 CA PerBit enable=1, Macro0, CA PI delay=34
4002 22:50:01.793086
4003 22:50:01.795211 [CBTSetCACLKResult] CA Dly = 34
4004 22:50:01.795631 CS Dly: 6 (0~37)
4005 22:50:01.795956
4006 22:50:01.798303 ----->DramcWriteLeveling(PI) begin...
4007 22:50:01.802013 ==
4008 22:50:01.802531 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 22:50:01.808552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 22:50:01.809077 ==
4011 22:50:01.811905 Write leveling (Byte 0): 35 => 35
4012 22:50:01.814964 Write leveling (Byte 1): 31 => 31
4013 22:50:01.818479 DramcWriteLeveling(PI) end<-----
4014 22:50:01.818934
4015 22:50:01.819292 ==
4016 22:50:01.821937 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 22:50:01.825096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 22:50:01.825644 ==
4019 22:50:01.828500 [Gating] SW mode calibration
4020 22:50:01.835082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4021 22:50:01.838296 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4022 22:50:01.845239 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 22:50:01.848463 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 22:50:01.851878 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 22:50:01.858424 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4026 22:50:01.862023 0 9 16 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
4027 22:50:01.865061 0 9 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4028 22:50:01.871755 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 22:50:01.874946 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 22:50:01.878454 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 22:50:01.884939 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 22:50:01.888229 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 22:50:01.891376 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4034 22:50:01.898115 0 10 16 | B1->B0 | 3030 4242 | 0 0 | (1 1) (0 0)
4035 22:50:01.901393 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 22:50:01.904723 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 22:50:01.911878 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 22:50:01.914326 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 22:50:01.918212 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 22:50:01.924538 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 22:50:01.927916 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4042 22:50:01.931237 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 22:50:01.937928 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 22:50:01.940941 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 22:50:01.944393 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 22:50:01.951106 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 22:50:01.954683 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 22:50:01.957672 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 22:50:01.964403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 22:50:01.967534 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 22:50:01.971140 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 22:50:01.977489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 22:50:01.980719 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 22:50:01.984076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 22:50:01.991350 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 22:50:01.993922 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 22:50:01.997556 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4058 22:50:02.004423 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4059 22:50:02.007394 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 22:50:02.011005 Total UI for P1: 0, mck2ui 16
4061 22:50:02.014015 best dqsien dly found for B0: ( 0, 13, 14)
4062 22:50:02.017350 Total UI for P1: 0, mck2ui 16
4063 22:50:02.020432 best dqsien dly found for B1: ( 0, 13, 18)
4064 22:50:02.024104 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4065 22:50:02.027373 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4066 22:50:02.027839
4067 22:50:02.030710 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4068 22:50:02.033951 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4069 22:50:02.037295 [Gating] SW calibration Done
4070 22:50:02.037807 ==
4071 22:50:02.040449 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 22:50:02.044020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 22:50:02.047303 ==
4074 22:50:02.047810 RX Vref Scan: 0
4075 22:50:02.048183
4076 22:50:02.050241 RX Vref 0 -> 0, step: 1
4077 22:50:02.050687
4078 22:50:02.053416 RX Delay -230 -> 252, step: 16
4079 22:50:02.057179 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4080 22:50:02.060643 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4081 22:50:02.063741 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4082 22:50:02.067256 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4083 22:50:02.073641 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4084 22:50:02.076895 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4085 22:50:02.080533 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4086 22:50:02.083371 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4087 22:50:02.090408 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4088 22:50:02.093694 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4089 22:50:02.096955 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4090 22:50:02.100372 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4091 22:50:02.106863 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4092 22:50:02.110118 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4093 22:50:02.113409 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4094 22:50:02.116937 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4095 22:50:02.117360 ==
4096 22:50:02.120035 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 22:50:02.126595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 22:50:02.127123 ==
4099 22:50:02.127570 DQS Delay:
4100 22:50:02.129723 DQS0 = 0, DQS1 = 0
4101 22:50:02.130157 DQM Delay:
4102 22:50:02.130646 DQM0 = 40, DQM1 = 31
4103 22:50:02.133371 DQ Delay:
4104 22:50:02.136583 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =41
4105 22:50:02.139884 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4106 22:50:02.143244 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4107 22:50:02.146629 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4108 22:50:02.147139
4109 22:50:02.147471
4110 22:50:02.147777 ==
4111 22:50:02.149875 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 22:50:02.153154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 22:50:02.153716 ==
4114 22:50:02.154061
4115 22:50:02.154368
4116 22:50:02.156223 TX Vref Scan disable
4117 22:50:02.156643 == TX Byte 0 ==
4118 22:50:02.163383 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4119 22:50:02.166905 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4120 22:50:02.167415 == TX Byte 1 ==
4121 22:50:02.173655 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4122 22:50:02.176533 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4123 22:50:02.177044 ==
4124 22:50:02.179925 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 22:50:02.182989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 22:50:02.183414 ==
4127 22:50:02.186591
4128 22:50:02.187110
4129 22:50:02.187445 TX Vref Scan disable
4130 22:50:02.189822 == TX Byte 0 ==
4131 22:50:02.193496 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4132 22:50:02.200104 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4133 22:50:02.200620 == TX Byte 1 ==
4134 22:50:02.203576 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4135 22:50:02.210172 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4136 22:50:02.210878
4137 22:50:02.211231 [DATLAT]
4138 22:50:02.211541 Freq=600, CH0 RK0
4139 22:50:02.211843
4140 22:50:02.213022 DATLAT Default: 0x9
4141 22:50:02.213440 0, 0xFFFF, sum = 0
4142 22:50:02.216635 1, 0xFFFF, sum = 0
4143 22:50:02.217160 2, 0xFFFF, sum = 0
4144 22:50:02.220114 3, 0xFFFF, sum = 0
4145 22:50:02.223360 4, 0xFFFF, sum = 0
4146 22:50:02.223791 5, 0xFFFF, sum = 0
4147 22:50:02.226478 6, 0xFFFF, sum = 0
4148 22:50:02.226901 7, 0xFFFF, sum = 0
4149 22:50:02.229699 8, 0x0, sum = 1
4150 22:50:02.230125 9, 0x0, sum = 2
4151 22:50:02.230463 10, 0x0, sum = 3
4152 22:50:02.232998 11, 0x0, sum = 4
4153 22:50:02.233425 best_step = 9
4154 22:50:02.233812
4155 22:50:02.234128 ==
4156 22:50:02.236112 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 22:50:02.242946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 22:50:02.243451 ==
4159 22:50:02.243894 RX Vref Scan: 1
4160 22:50:02.244327
4161 22:50:02.246745 RX Vref 0 -> 0, step: 1
4162 22:50:02.247259
4163 22:50:02.249800 RX Delay -195 -> 252, step: 8
4164 22:50:02.250222
4165 22:50:02.253021 Set Vref, RX VrefLevel [Byte0]: 60
4166 22:50:02.256640 [Byte1]: 46
4167 22:50:02.257153
4168 22:50:02.260001 Final RX Vref Byte 0 = 60 to rank0
4169 22:50:02.263361 Final RX Vref Byte 1 = 46 to rank0
4170 22:50:02.266280 Final RX Vref Byte 0 = 60 to rank1
4171 22:50:02.269777 Final RX Vref Byte 1 = 46 to rank1==
4172 22:50:02.273179 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 22:50:02.276505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 22:50:02.277020 ==
4175 22:50:02.279724 DQS Delay:
4176 22:50:02.280234 DQS0 = 0, DQS1 = 0
4177 22:50:02.282893 DQM Delay:
4178 22:50:02.283314 DQM0 = 35, DQM1 = 29
4179 22:50:02.283645 DQ Delay:
4180 22:50:02.286084 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4181 22:50:02.289399 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4182 22:50:02.292991 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =24
4183 22:50:02.295710 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4184 22:50:02.296129
4185 22:50:02.296458
4186 22:50:02.305974 [DQSOSCAuto] RK0, (LSB)MR18= 0x4443, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4187 22:50:02.309229 CH0 RK0: MR19=808, MR18=4443
4188 22:50:02.315734 CH0_RK0: MR19=0x808, MR18=0x4443, DQSOSC=396, MR23=63, INC=167, DEC=111
4189 22:50:02.316285
4190 22:50:02.319118 ----->DramcWriteLeveling(PI) begin...
4191 22:50:02.319586 ==
4192 22:50:02.322743 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 22:50:02.326069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 22:50:02.326532 ==
4195 22:50:02.329394 Write leveling (Byte 0): 33 => 33
4196 22:50:02.332432 Write leveling (Byte 1): 30 => 30
4197 22:50:02.335881 DramcWriteLeveling(PI) end<-----
4198 22:50:02.336510
4199 22:50:02.336969 ==
4200 22:50:02.338900 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 22:50:02.342483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 22:50:02.342945 ==
4203 22:50:02.345775 [Gating] SW mode calibration
4204 22:50:02.352470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4205 22:50:02.358909 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4206 22:50:02.362414 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 22:50:02.365824 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 22:50:02.372613 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 22:50:02.376043 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (0 0) (1 0)
4210 22:50:02.378767 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4211 22:50:02.385725 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 22:50:02.388640 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 22:50:02.392043 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 22:50:02.398540 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 22:50:02.402334 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 22:50:02.405667 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 22:50:02.412252 0 10 12 | B1->B0 | 2929 3333 | 0 0 | (0 0) (0 0)
4218 22:50:02.415683 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4219 22:50:02.418523 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 22:50:02.425102 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 22:50:02.428674 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 22:50:02.432075 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 22:50:02.438771 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 22:50:02.442097 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 22:50:02.445137 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 22:50:02.452073 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 22:50:02.455280 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 22:50:02.458117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 22:50:02.465245 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 22:50:02.468133 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 22:50:02.471955 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 22:50:02.478326 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 22:50:02.481669 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 22:50:02.485083 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 22:50:02.487955 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 22:50:02.494623 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 22:50:02.498440 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 22:50:02.501643 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 22:50:02.508419 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 22:50:02.511751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4241 22:50:02.515107 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 22:50:02.521540 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 22:50:02.524717 Total UI for P1: 0, mck2ui 16
4244 22:50:02.528135 best dqsien dly found for B0: ( 0, 13, 14)
4245 22:50:02.531106 Total UI for P1: 0, mck2ui 16
4246 22:50:02.534591 best dqsien dly found for B1: ( 0, 13, 14)
4247 22:50:02.537829 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4248 22:50:02.541544 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4249 22:50:02.542108
4250 22:50:02.544584 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4251 22:50:02.548040 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4252 22:50:02.551083 [Gating] SW calibration Done
4253 22:50:02.551550 ==
4254 22:50:02.554358 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 22:50:02.557722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 22:50:02.558272 ==
4257 22:50:02.561224 RX Vref Scan: 0
4258 22:50:02.561817
4259 22:50:02.564567 RX Vref 0 -> 0, step: 1
4260 22:50:02.565119
4261 22:50:02.565486 RX Delay -230 -> 252, step: 16
4262 22:50:02.571427 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4263 22:50:02.574222 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4264 22:50:02.578036 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4265 22:50:02.580892 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4266 22:50:02.587972 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4267 22:50:02.591156 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4268 22:50:02.594334 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4269 22:50:02.598035 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4270 22:50:02.601125 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4271 22:50:02.607666 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4272 22:50:02.610590 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4273 22:50:02.614326 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4274 22:50:02.617395 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4275 22:50:02.624131 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4276 22:50:02.627216 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4277 22:50:02.630788 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4278 22:50:02.631375 ==
4279 22:50:02.634268 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 22:50:02.636969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 22:50:02.640545 ==
4282 22:50:02.641035 DQS Delay:
4283 22:50:02.641409 DQS0 = 0, DQS1 = 0
4284 22:50:02.643719 DQM Delay:
4285 22:50:02.644463 DQM0 = 36, DQM1 = 28
4286 22:50:02.647229 DQ Delay:
4287 22:50:02.650610 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4288 22:50:02.651029 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4289 22:50:02.653860 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4290 22:50:02.657160 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4291 22:50:02.660654
4292 22:50:02.661071
4293 22:50:02.661398 ==
4294 22:50:02.663887 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 22:50:02.666765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 22:50:02.667188 ==
4297 22:50:02.667520
4298 22:50:02.667843
4299 22:50:02.670097 TX Vref Scan disable
4300 22:50:02.670516 == TX Byte 0 ==
4301 22:50:02.676946 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4302 22:50:02.680382 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4303 22:50:02.680802 == TX Byte 1 ==
4304 22:50:02.687036 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4305 22:50:02.690057 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4306 22:50:02.690726 ==
4307 22:50:02.693581 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 22:50:02.696915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 22:50:02.697339 ==
4310 22:50:02.697734
4311 22:50:02.698051
4312 22:50:02.699787 TX Vref Scan disable
4313 22:50:02.703282 == TX Byte 0 ==
4314 22:50:02.706509 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4315 22:50:02.713060 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4316 22:50:02.713644 == TX Byte 1 ==
4317 22:50:02.716718 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4318 22:50:02.724475 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4319 22:50:02.724903
4320 22:50:02.725230 [DATLAT]
4321 22:50:02.725555 Freq=600, CH0 RK1
4322 22:50:02.725861
4323 22:50:02.726580 DATLAT Default: 0x9
4324 22:50:02.726985 0, 0xFFFF, sum = 0
4325 22:50:02.730461 1, 0xFFFF, sum = 0
4326 22:50:02.730884 2, 0xFFFF, sum = 0
4327 22:50:02.733033 3, 0xFFFF, sum = 0
4328 22:50:02.736483 4, 0xFFFF, sum = 0
4329 22:50:02.737048 5, 0xFFFF, sum = 0
4330 22:50:02.740360 6, 0xFFFF, sum = 0
4331 22:50:02.740949 7, 0xFFFF, sum = 0
4332 22:50:02.742697 8, 0x0, sum = 1
4333 22:50:02.743159 9, 0x0, sum = 2
4334 22:50:02.743541 10, 0x0, sum = 3
4335 22:50:02.746265 11, 0x0, sum = 4
4336 22:50:02.746677 best_step = 9
4337 22:50:02.746999
4338 22:50:02.747295 ==
4339 22:50:02.749833 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 22:50:02.755994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 22:50:02.756405 ==
4342 22:50:02.756724 RX Vref Scan: 0
4343 22:50:02.757024
4344 22:50:02.759417 RX Vref 0 -> 0, step: 1
4345 22:50:02.759708
4346 22:50:02.762840 RX Delay -195 -> 252, step: 8
4347 22:50:02.766156 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4348 22:50:02.772770 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4349 22:50:02.775867 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4350 22:50:02.779353 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4351 22:50:02.782635 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4352 22:50:02.788955 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4353 22:50:02.792294 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4354 22:50:02.795632 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4355 22:50:02.799052 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4356 22:50:02.805907 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4357 22:50:02.808961 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4358 22:50:02.812297 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4359 22:50:02.815962 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4360 22:50:02.819414 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4361 22:50:02.825551 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4362 22:50:02.829284 iDelay=205, Bit 15, Center 32 (-123 ~ 188) 312
4363 22:50:02.829885 ==
4364 22:50:02.832718 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 22:50:02.835635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 22:50:02.836160 ==
4367 22:50:02.838784 DQS Delay:
4368 22:50:02.839370 DQS0 = 0, DQS1 = 0
4369 22:50:02.842386 DQM Delay:
4370 22:50:02.842831 DQM0 = 33, DQM1 = 27
4371 22:50:02.843186 DQ Delay:
4372 22:50:02.845940 DQ0 =32, DQ1 =36, DQ2 =28, DQ3 =28
4373 22:50:02.849215 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4374 22:50:02.852213 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4375 22:50:02.855835 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =32
4376 22:50:02.856264
4377 22:50:02.856607
4378 22:50:02.865545 [DQSOSCAuto] RK1, (LSB)MR18= 0x703f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4379 22:50:02.868756 CH0 RK1: MR19=808, MR18=703F
4380 22:50:02.875898 CH0_RK1: MR19=0x808, MR18=0x703F, DQSOSC=388, MR23=63, INC=174, DEC=116
4381 22:50:02.876382 [RxdqsGatingPostProcess] freq 600
4382 22:50:02.882467 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4383 22:50:02.885551 Pre-setting of DQS Precalculation
4384 22:50:02.888950 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4385 22:50:02.889400 ==
4386 22:50:02.892372 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 22:50:02.898708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 22:50:02.899114 ==
4389 22:50:02.902058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 22:50:02.908760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4391 22:50:02.912083 [CA 0] Center 36 (6~66) winsize 61
4392 22:50:02.915948 [CA 1] Center 36 (6~66) winsize 61
4393 22:50:02.919153 [CA 2] Center 34 (4~65) winsize 62
4394 22:50:02.922392 [CA 3] Center 34 (3~65) winsize 63
4395 22:50:02.925704 [CA 4] Center 34 (4~65) winsize 62
4396 22:50:02.928748 [CA 5] Center 34 (4~64) winsize 61
4397 22:50:02.929145
4398 22:50:02.932262 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4399 22:50:02.932758
4400 22:50:02.935424 [CATrainingPosCal] consider 1 rank data
4401 22:50:02.939130 u2DelayCellTimex100 = 270/100 ps
4402 22:50:02.942431 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4403 22:50:02.945812 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4404 22:50:02.952389 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 22:50:02.955461 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4406 22:50:02.958948 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4407 22:50:02.961916 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4408 22:50:02.962306
4409 22:50:02.965433 CA PerBit enable=1, Macro0, CA PI delay=34
4410 22:50:02.965947
4411 22:50:02.968513 [CBTSetCACLKResult] CA Dly = 34
4412 22:50:02.969066 CS Dly: 4 (0~35)
4413 22:50:02.972267 ==
4414 22:50:02.975397 Dram Type= 6, Freq= 0, CH_1, rank 1
4415 22:50:02.978833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 22:50:02.979254 ==
4417 22:50:02.982292 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 22:50:02.988552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4419 22:50:02.992393 [CA 0] Center 36 (6~66) winsize 61
4420 22:50:02.995714 [CA 1] Center 36 (6~66) winsize 61
4421 22:50:02.999088 [CA 2] Center 34 (4~65) winsize 62
4422 22:50:03.002580 [CA 3] Center 34 (3~65) winsize 63
4423 22:50:03.005488 [CA 4] Center 34 (4~65) winsize 62
4424 22:50:03.008895 [CA 5] Center 33 (3~64) winsize 62
4425 22:50:03.009394
4426 22:50:03.011986 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4427 22:50:03.012482
4428 22:50:03.015690 [CATrainingPosCal] consider 2 rank data
4429 22:50:03.018864 u2DelayCellTimex100 = 270/100 ps
4430 22:50:03.021967 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4431 22:50:03.028787 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4432 22:50:03.031995 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4433 22:50:03.035707 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4434 22:50:03.039030 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4435 22:50:03.042409 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4436 22:50:03.042998
4437 22:50:03.045171 CA PerBit enable=1, Macro0, CA PI delay=34
4438 22:50:03.045762
4439 22:50:03.048851 [CBTSetCACLKResult] CA Dly = 34
4440 22:50:03.049398 CS Dly: 4 (0~36)
4441 22:50:03.051889
4442 22:50:03.055331 ----->DramcWriteLeveling(PI) begin...
4443 22:50:03.055932 ==
4444 22:50:03.058887 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 22:50:03.061732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 22:50:03.062269 ==
4447 22:50:03.065170 Write leveling (Byte 0): 31 => 31
4448 22:50:03.068530 Write leveling (Byte 1): 33 => 33
4449 22:50:03.071967 DramcWriteLeveling(PI) end<-----
4450 22:50:03.072581
4451 22:50:03.073104 ==
4452 22:50:03.075610 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 22:50:03.078886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 22:50:03.079513 ==
4455 22:50:03.081786 [Gating] SW mode calibration
4456 22:50:03.088823 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4457 22:50:03.095020 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4458 22:50:03.098240 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 22:50:03.101501 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 22:50:03.108305 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 22:50:03.111636 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
4462 22:50:03.114931 0 9 16 | B1->B0 | 2525 2424 | 0 0 | (1 1) (0 0)
4463 22:50:03.121619 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 22:50:03.124936 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 22:50:03.128066 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 22:50:03.134945 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 22:50:03.138579 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 22:50:03.141749 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 22:50:03.148016 0 10 12 | B1->B0 | 302f 2f2f | 1 0 | (0 0) (0 0)
4470 22:50:03.151139 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 22:50:03.154650 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 22:50:03.158241 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 22:50:03.164847 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 22:50:03.168118 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 22:50:03.171473 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 22:50:03.178270 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 22:50:03.181774 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4478 22:50:03.184818 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4479 22:50:03.191233 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 22:50:03.194663 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 22:50:03.198200 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 22:50:03.204900 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 22:50:03.208243 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 22:50:03.211162 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 22:50:03.217677 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 22:50:03.221716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 22:50:03.224385 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 22:50:03.231223 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 22:50:03.234413 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 22:50:03.237792 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 22:50:03.244485 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 22:50:03.247376 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 22:50:03.250815 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4494 22:50:03.257310 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4495 22:50:03.260296 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 22:50:03.263625 Total UI for P1: 0, mck2ui 16
4497 22:50:03.267259 best dqsien dly found for B0: ( 0, 13, 14)
4498 22:50:03.270340 Total UI for P1: 0, mck2ui 16
4499 22:50:03.273809 best dqsien dly found for B1: ( 0, 13, 14)
4500 22:50:03.276848 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4501 22:50:03.280534 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4502 22:50:03.280616
4503 22:50:03.283458 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4504 22:50:03.287004 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4505 22:50:03.290359 [Gating] SW calibration Done
4506 22:50:03.290441 ==
4507 22:50:03.293445 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 22:50:03.300194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 22:50:03.300277 ==
4510 22:50:03.300341 RX Vref Scan: 0
4511 22:50:03.300400
4512 22:50:03.303549 RX Vref 0 -> 0, step: 1
4513 22:50:03.303630
4514 22:50:03.307018 RX Delay -230 -> 252, step: 16
4515 22:50:03.310468 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4516 22:50:03.313750 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4517 22:50:03.316800 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4518 22:50:03.323405 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4519 22:50:03.326935 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4520 22:50:03.330310 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4521 22:50:03.333219 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4522 22:50:03.336622 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4523 22:50:03.343671 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4524 22:50:03.346731 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4525 22:50:03.350456 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4526 22:50:03.353170 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4527 22:50:03.360142 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4528 22:50:03.363005 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4529 22:50:03.366968 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4530 22:50:03.370255 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4531 22:50:03.370325 ==
4532 22:50:03.373504 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 22:50:03.380044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 22:50:03.380112 ==
4535 22:50:03.380172 DQS Delay:
4536 22:50:03.383373 DQS0 = 0, DQS1 = 0
4537 22:50:03.383438 DQM Delay:
4538 22:50:03.383499 DQM0 = 38, DQM1 = 28
4539 22:50:03.386809 DQ Delay:
4540 22:50:03.389928 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4541 22:50:03.393097 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4542 22:50:03.396842 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4543 22:50:03.399738 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4544 22:50:03.399810
4545 22:50:03.399869
4546 22:50:03.399925 ==
4547 22:50:03.403347 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 22:50:03.406841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 22:50:03.406938 ==
4550 22:50:03.407025
4551 22:50:03.407112
4552 22:50:03.410010 TX Vref Scan disable
4553 22:50:03.412896 == TX Byte 0 ==
4554 22:50:03.416398 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4555 22:50:03.419681 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4556 22:50:03.422938 == TX Byte 1 ==
4557 22:50:03.426450 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4558 22:50:03.429922 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4559 22:50:03.429988 ==
4560 22:50:03.433292 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 22:50:03.436044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 22:50:03.439659 ==
4563 22:50:03.439749
4564 22:50:03.439833
4565 22:50:03.439919 TX Vref Scan disable
4566 22:50:03.443721 == TX Byte 0 ==
4567 22:50:03.446657 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4568 22:50:03.453236 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4569 22:50:03.453330 == TX Byte 1 ==
4570 22:50:03.456753 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4571 22:50:03.463302 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4572 22:50:03.463394
4573 22:50:03.463482 [DATLAT]
4574 22:50:03.463569 Freq=600, CH1 RK0
4575 22:50:03.463653
4576 22:50:03.466546 DATLAT Default: 0x9
4577 22:50:03.466636 0, 0xFFFF, sum = 0
4578 22:50:03.469891 1, 0xFFFF, sum = 0
4579 22:50:03.469964 2, 0xFFFF, sum = 0
4580 22:50:03.473161 3, 0xFFFF, sum = 0
4581 22:50:03.476451 4, 0xFFFF, sum = 0
4582 22:50:03.476547 5, 0xFFFF, sum = 0
4583 22:50:03.479862 6, 0xFFFF, sum = 0
4584 22:50:03.479956 7, 0xFFFF, sum = 0
4585 22:50:03.483377 8, 0x0, sum = 1
4586 22:50:03.483468 9, 0x0, sum = 2
4587 22:50:03.483558 10, 0x0, sum = 3
4588 22:50:03.486789 11, 0x0, sum = 4
4589 22:50:03.486881 best_step = 9
4590 22:50:03.486966
4591 22:50:03.487023 ==
4592 22:50:03.489761 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 22:50:03.496210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 22:50:03.496277 ==
4595 22:50:03.496337 RX Vref Scan: 1
4596 22:50:03.496424
4597 22:50:03.499847 RX Vref 0 -> 0, step: 1
4598 22:50:03.499939
4599 22:50:03.503174 RX Delay -195 -> 252, step: 8
4600 22:50:03.503276
4601 22:50:03.506180 Set Vref, RX VrefLevel [Byte0]: 57
4602 22:50:03.509798 [Byte1]: 46
4603 22:50:03.509895
4604 22:50:03.512798 Final RX Vref Byte 0 = 57 to rank0
4605 22:50:03.516174 Final RX Vref Byte 1 = 46 to rank0
4606 22:50:03.519536 Final RX Vref Byte 0 = 57 to rank1
4607 22:50:03.523093 Final RX Vref Byte 1 = 46 to rank1==
4608 22:50:03.525904 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 22:50:03.529313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 22:50:03.529410 ==
4611 22:50:03.532634 DQS Delay:
4612 22:50:03.532703 DQS0 = 0, DQS1 = 0
4613 22:50:03.536219 DQM Delay:
4614 22:50:03.536312 DQM0 = 39, DQM1 = 29
4615 22:50:03.536401 DQ Delay:
4616 22:50:03.539342 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4617 22:50:03.542552 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4618 22:50:03.545975 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =24
4619 22:50:03.549455 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4620 22:50:03.549570
4621 22:50:03.549635
4622 22:50:03.559689 [DQSOSCAuto] RK0, (LSB)MR18= 0x2836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4623 22:50:03.562829 CH1 RK0: MR19=808, MR18=2836
4624 22:50:03.569419 CH1_RK0: MR19=0x808, MR18=0x2836, DQSOSC=399, MR23=63, INC=164, DEC=109
4625 22:50:03.569555
4626 22:50:03.573045 ----->DramcWriteLeveling(PI) begin...
4627 22:50:03.573151 ==
4628 22:50:03.576295 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 22:50:03.579191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 22:50:03.579289 ==
4631 22:50:03.582811 Write leveling (Byte 0): 28 => 28
4632 22:50:03.585769 Write leveling (Byte 1): 33 => 33
4633 22:50:03.589225 DramcWriteLeveling(PI) end<-----
4634 22:50:03.589306
4635 22:50:03.589370 ==
4636 22:50:03.592459 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 22:50:03.595913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 22:50:03.595996 ==
4639 22:50:03.599274 [Gating] SW mode calibration
4640 22:50:03.605774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4641 22:50:03.612562 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4642 22:50:03.615946 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 22:50:03.619324 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 22:50:03.625634 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4645 22:50:03.629283 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 0) (1 1)
4646 22:50:03.632365 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 22:50:03.639239 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 22:50:03.642391 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 22:50:03.645779 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 22:50:03.652304 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 22:50:03.655390 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 22:50:03.658931 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4653 22:50:03.665306 0 10 12 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
4654 22:50:03.669230 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4655 22:50:03.672259 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 22:50:03.678719 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 22:50:03.681984 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 22:50:03.685187 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 22:50:03.691822 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 22:50:03.695544 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4661 22:50:03.699033 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4662 22:50:03.701960 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 22:50:03.708647 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 22:50:03.711831 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 22:50:03.715317 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 22:50:03.722324 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 22:50:03.725287 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 22:50:03.728714 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 22:50:03.735554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 22:50:03.738863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 22:50:03.741752 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 22:50:03.748624 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 22:50:03.751822 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 22:50:03.755363 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 22:50:03.762043 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 22:50:03.765464 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 22:50:03.768465 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 22:50:03.772043 Total UI for P1: 0, mck2ui 16
4679 22:50:03.775376 best dqsien dly found for B0: ( 0, 13, 10)
4680 22:50:03.778490 Total UI for P1: 0, mck2ui 16
4681 22:50:03.781732 best dqsien dly found for B1: ( 0, 13, 10)
4682 22:50:03.785392 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4683 22:50:03.788633 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4684 22:50:03.788747
4685 22:50:03.795161 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4686 22:50:03.798574 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4687 22:50:03.801381 [Gating] SW calibration Done
4688 22:50:03.801483 ==
4689 22:50:03.804992 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 22:50:03.808599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 22:50:03.808700 ==
4692 22:50:03.808793 RX Vref Scan: 0
4693 22:50:03.808881
4694 22:50:03.811303 RX Vref 0 -> 0, step: 1
4695 22:50:03.811399
4696 22:50:03.815047 RX Delay -230 -> 252, step: 16
4697 22:50:03.818293 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4698 22:50:03.824385 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4699 22:50:03.828216 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4700 22:50:03.831250 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4701 22:50:03.834442 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4702 22:50:03.837890 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4703 22:50:03.844195 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4704 22:50:03.847764 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4705 22:50:03.851426 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4706 22:50:03.854325 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4707 22:50:03.861071 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4708 22:50:03.864279 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4709 22:50:03.867603 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4710 22:50:03.871010 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4711 22:50:03.877384 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4712 22:50:03.880727 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4713 22:50:03.880822 ==
4714 22:50:03.884650 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 22:50:03.887971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 22:50:03.888071 ==
4717 22:50:03.888159 DQS Delay:
4718 22:50:03.890923 DQS0 = 0, DQS1 = 0
4719 22:50:03.891008 DQM Delay:
4720 22:50:03.894186 DQM0 = 35, DQM1 = 27
4721 22:50:03.894272 DQ Delay:
4722 22:50:03.897941 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4723 22:50:03.901026 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4724 22:50:03.904479 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4725 22:50:03.908060 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4726 22:50:03.908164
4727 22:50:03.908227
4728 22:50:03.908285 ==
4729 22:50:03.910897 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 22:50:03.914500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 22:50:03.917651 ==
4732 22:50:03.917731
4733 22:50:03.917793
4734 22:50:03.917850 TX Vref Scan disable
4735 22:50:03.920811 == TX Byte 0 ==
4736 22:50:03.924221 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4737 22:50:03.927506 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4738 22:50:03.930856 == TX Byte 1 ==
4739 22:50:03.934384 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4740 22:50:03.937438 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4741 22:50:03.940943 ==
4742 22:50:03.944405 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 22:50:03.947919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 22:50:03.947999 ==
4745 22:50:03.948062
4746 22:50:03.948123
4747 22:50:03.950687 TX Vref Scan disable
4748 22:50:03.954158 == TX Byte 0 ==
4749 22:50:03.957465 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4750 22:50:03.961000 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4751 22:50:03.964184 == TX Byte 1 ==
4752 22:50:03.967665 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4753 22:50:03.970439 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4754 22:50:03.970519
4755 22:50:03.970583 [DATLAT]
4756 22:50:03.973940 Freq=600, CH1 RK1
4757 22:50:03.974020
4758 22:50:03.974082 DATLAT Default: 0x9
4759 22:50:03.977082 0, 0xFFFF, sum = 0
4760 22:50:03.980390 1, 0xFFFF, sum = 0
4761 22:50:03.980472 2, 0xFFFF, sum = 0
4762 22:50:03.983656 3, 0xFFFF, sum = 0
4763 22:50:03.983738 4, 0xFFFF, sum = 0
4764 22:50:03.987406 5, 0xFFFF, sum = 0
4765 22:50:03.987487 6, 0xFFFF, sum = 0
4766 22:50:03.990816 7, 0xFFFF, sum = 0
4767 22:50:03.990896 8, 0x0, sum = 1
4768 22:50:03.993664 9, 0x0, sum = 2
4769 22:50:03.993746 10, 0x0, sum = 3
4770 22:50:03.993810 11, 0x0, sum = 4
4771 22:50:03.997196 best_step = 9
4772 22:50:03.997275
4773 22:50:03.997337 ==
4774 22:50:04.000137 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 22:50:04.003482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 22:50:04.003561 ==
4777 22:50:04.007044 RX Vref Scan: 0
4778 22:50:04.007123
4779 22:50:04.007186 RX Vref 0 -> 0, step: 1
4780 22:50:04.010318
4781 22:50:04.010398 RX Delay -195 -> 252, step: 8
4782 22:50:04.018210 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4783 22:50:04.021140 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4784 22:50:04.024933 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4785 22:50:04.028043 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4786 22:50:04.034895 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4787 22:50:04.037985 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4788 22:50:04.041293 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4789 22:50:04.044683 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4790 22:50:04.051041 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4791 22:50:04.054274 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4792 22:50:04.057422 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4793 22:50:04.061083 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4794 22:50:04.064446 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4795 22:50:04.070710 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4796 22:50:04.074188 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4797 22:50:04.077675 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4798 22:50:04.077755 ==
4799 22:50:04.081014 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 22:50:04.087329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 22:50:04.087410 ==
4802 22:50:04.087473 DQS Delay:
4803 22:50:04.091009 DQS0 = 0, DQS1 = 0
4804 22:50:04.091088 DQM Delay:
4805 22:50:04.091150 DQM0 = 36, DQM1 = 30
4806 22:50:04.094031 DQ Delay:
4807 22:50:04.097446 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4808 22:50:04.100782 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4809 22:50:04.103940 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4810 22:50:04.107489 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4811 22:50:04.107591
4812 22:50:04.107682
4813 22:50:04.113988 [DQSOSCAuto] RK1, (LSB)MR18= 0x3757, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4814 22:50:04.117762 CH1 RK1: MR19=808, MR18=3757
4815 22:50:04.124025 CH1_RK1: MR19=0x808, MR18=0x3757, DQSOSC=393, MR23=63, INC=169, DEC=113
4816 22:50:04.127429 [RxdqsGatingPostProcess] freq 600
4817 22:50:04.130340 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4818 22:50:04.134005 Pre-setting of DQS Precalculation
4819 22:50:04.140903 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4820 22:50:04.147403 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4821 22:50:04.153782 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4822 22:50:04.153878
4823 22:50:04.153943
4824 22:50:04.156986 [Calibration Summary] 1200 Mbps
4825 22:50:04.157083 CH 0, Rank 0
4826 22:50:04.160535 SW Impedance : PASS
4827 22:50:04.163915 DUTY Scan : NO K
4828 22:50:04.164011 ZQ Calibration : PASS
4829 22:50:04.166816 Jitter Meter : NO K
4830 22:50:04.170148 CBT Training : PASS
4831 22:50:04.170238 Write leveling : PASS
4832 22:50:04.173642 RX DQS gating : PASS
4833 22:50:04.176955 RX DQ/DQS(RDDQC) : PASS
4834 22:50:04.177052 TX DQ/DQS : PASS
4835 22:50:04.180000 RX DATLAT : PASS
4836 22:50:04.183474 RX DQ/DQS(Engine): PASS
4837 22:50:04.183572 TX OE : NO K
4838 22:50:04.183665 All Pass.
4839 22:50:04.187097
4840 22:50:04.187195 CH 0, Rank 1
4841 22:50:04.190477 SW Impedance : PASS
4842 22:50:04.190548 DUTY Scan : NO K
4843 22:50:04.193208 ZQ Calibration : PASS
4844 22:50:04.193304 Jitter Meter : NO K
4845 22:50:04.197024 CBT Training : PASS
4846 22:50:04.200063 Write leveling : PASS
4847 22:50:04.200163 RX DQS gating : PASS
4848 22:50:04.203196 RX DQ/DQS(RDDQC) : PASS
4849 22:50:04.206960 TX DQ/DQS : PASS
4850 22:50:04.207058 RX DATLAT : PASS
4851 22:50:04.209838 RX DQ/DQS(Engine): PASS
4852 22:50:04.213222 TX OE : NO K
4853 22:50:04.213303 All Pass.
4854 22:50:04.213367
4855 22:50:04.213426 CH 1, Rank 0
4856 22:50:04.216646 SW Impedance : PASS
4857 22:50:04.219810 DUTY Scan : NO K
4858 22:50:04.219892 ZQ Calibration : PASS
4859 22:50:04.223357 Jitter Meter : NO K
4860 22:50:04.226653 CBT Training : PASS
4861 22:50:04.226734 Write leveling : PASS
4862 22:50:04.230172 RX DQS gating : PASS
4863 22:50:04.233390 RX DQ/DQS(RDDQC) : PASS
4864 22:50:04.233486 TX DQ/DQS : PASS
4865 22:50:04.236595 RX DATLAT : PASS
4866 22:50:04.239726 RX DQ/DQS(Engine): PASS
4867 22:50:04.239800 TX OE : NO K
4868 22:50:04.239860 All Pass.
4869 22:50:04.243284
4870 22:50:04.243362 CH 1, Rank 1
4871 22:50:04.246535 SW Impedance : PASS
4872 22:50:04.246614 DUTY Scan : NO K
4873 22:50:04.249737 ZQ Calibration : PASS
4874 22:50:04.253146 Jitter Meter : NO K
4875 22:50:04.253221 CBT Training : PASS
4876 22:50:04.256561 Write leveling : PASS
4877 22:50:04.256641 RX DQS gating : PASS
4878 22:50:04.259369 RX DQ/DQS(RDDQC) : PASS
4879 22:50:04.262788 TX DQ/DQS : PASS
4880 22:50:04.262867 RX DATLAT : PASS
4881 22:50:04.266265 RX DQ/DQS(Engine): PASS
4882 22:50:04.269644 TX OE : NO K
4883 22:50:04.269755 All Pass.
4884 22:50:04.269846
4885 22:50:04.272645 DramC Write-DBI off
4886 22:50:04.272719 PER_BANK_REFRESH: Hybrid Mode
4887 22:50:04.275953 TX_TRACKING: ON
4888 22:50:04.286124 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4889 22:50:04.289396 [FAST_K] Save calibration result to emmc
4890 22:50:04.292886 dramc_set_vcore_voltage set vcore to 662500
4891 22:50:04.292959 Read voltage for 933, 3
4892 22:50:04.296299 Vio18 = 0
4893 22:50:04.296409 Vcore = 662500
4894 22:50:04.296474 Vdram = 0
4895 22:50:04.299705 Vddq = 0
4896 22:50:04.299778 Vmddr = 0
4897 22:50:04.302926 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4898 22:50:04.309469 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4899 22:50:04.312627 MEM_TYPE=3, freq_sel=17
4900 22:50:04.315926 sv_algorithm_assistance_LP4_1600
4901 22:50:04.319337 ============ PULL DRAM RESETB DOWN ============
4902 22:50:04.322476 ========== PULL DRAM RESETB DOWN end =========
4903 22:50:04.329346 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4904 22:50:04.332536 ===================================
4905 22:50:04.332618 LPDDR4 DRAM CONFIGURATION
4906 22:50:04.335906 ===================================
4907 22:50:04.339272 EX_ROW_EN[0] = 0x0
4908 22:50:04.339344 EX_ROW_EN[1] = 0x0
4909 22:50:04.342226 LP4Y_EN = 0x0
4910 22:50:04.342300 WORK_FSP = 0x0
4911 22:50:04.345561 WL = 0x3
4912 22:50:04.349092 RL = 0x3
4913 22:50:04.349165 BL = 0x2
4914 22:50:04.352374 RPST = 0x0
4915 22:50:04.352446 RD_PRE = 0x0
4916 22:50:04.355852 WR_PRE = 0x1
4917 22:50:04.355948 WR_PST = 0x0
4918 22:50:04.359133 DBI_WR = 0x0
4919 22:50:04.359209 DBI_RD = 0x0
4920 22:50:04.362058 OTF = 0x1
4921 22:50:04.365529 ===================================
4922 22:50:04.368918 ===================================
4923 22:50:04.369012 ANA top config
4924 22:50:04.372088 ===================================
4925 22:50:04.375822 DLL_ASYNC_EN = 0
4926 22:50:04.379197 ALL_SLAVE_EN = 1
4927 22:50:04.379277 NEW_RANK_MODE = 1
4928 22:50:04.382024 DLL_IDLE_MODE = 1
4929 22:50:04.385458 LP45_APHY_COMB_EN = 1
4930 22:50:04.388919 TX_ODT_DIS = 1
4931 22:50:04.392009 NEW_8X_MODE = 1
4932 22:50:04.395529 ===================================
4933 22:50:04.398839 ===================================
4934 22:50:04.398914 data_rate = 1866
4935 22:50:04.401950 CKR = 1
4936 22:50:04.405297 DQ_P2S_RATIO = 8
4937 22:50:04.408322 ===================================
4938 22:50:04.412309 CA_P2S_RATIO = 8
4939 22:50:04.415057 DQ_CA_OPEN = 0
4940 22:50:04.418503 DQ_SEMI_OPEN = 0
4941 22:50:04.418579 CA_SEMI_OPEN = 0
4942 22:50:04.421984 CA_FULL_RATE = 0
4943 22:50:04.425234 DQ_CKDIV4_EN = 1
4944 22:50:04.428295 CA_CKDIV4_EN = 1
4945 22:50:04.431939 CA_PREDIV_EN = 0
4946 22:50:04.435302 PH8_DLY = 0
4947 22:50:04.435381 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4948 22:50:04.438273 DQ_AAMCK_DIV = 4
4949 22:50:04.441881 CA_AAMCK_DIV = 4
4950 22:50:04.444805 CA_ADMCK_DIV = 4
4951 22:50:04.448184 DQ_TRACK_CA_EN = 0
4952 22:50:04.451759 CA_PICK = 933
4953 22:50:04.455130 CA_MCKIO = 933
4954 22:50:04.455212 MCKIO_SEMI = 0
4955 22:50:04.458499 PLL_FREQ = 3732
4956 22:50:04.461739 DQ_UI_PI_RATIO = 32
4957 22:50:04.464897 CA_UI_PI_RATIO = 0
4958 22:50:04.468336 ===================================
4959 22:50:04.471716 ===================================
4960 22:50:04.474821 memory_type:LPDDR4
4961 22:50:04.474902 GP_NUM : 10
4962 22:50:04.478359 SRAM_EN : 1
4963 22:50:04.481485 MD32_EN : 0
4964 22:50:04.481605 ===================================
4965 22:50:04.484988 [ANA_INIT] >>>>>>>>>>>>>>
4966 22:50:04.488024 <<<<<< [CONFIGURE PHASE]: ANA_TX
4967 22:50:04.491439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4968 22:50:04.494856 ===================================
4969 22:50:04.498177 data_rate = 1866,PCW = 0X8f00
4970 22:50:04.501372 ===================================
4971 22:50:04.504896 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4972 22:50:04.511280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 22:50:04.514764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 22:50:04.521357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4975 22:50:04.524383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4976 22:50:04.527880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4977 22:50:04.527962 [ANA_INIT] flow start
4978 22:50:04.531164 [ANA_INIT] PLL >>>>>>>>
4979 22:50:04.534711 [ANA_INIT] PLL <<<<<<<<
4980 22:50:04.534818 [ANA_INIT] MIDPI >>>>>>>>
4981 22:50:04.537500 [ANA_INIT] MIDPI <<<<<<<<
4982 22:50:04.541081 [ANA_INIT] DLL >>>>>>>>
4983 22:50:04.541160 [ANA_INIT] flow end
4984 22:50:04.547541 ============ LP4 DIFF to SE enter ============
4985 22:50:04.551043 ============ LP4 DIFF to SE exit ============
4986 22:50:04.554483 [ANA_INIT] <<<<<<<<<<<<<
4987 22:50:04.557492 [Flow] Enable top DCM control >>>>>
4988 22:50:04.560961 [Flow] Enable top DCM control <<<<<
4989 22:50:04.561032 Enable DLL master slave shuffle
4990 22:50:04.567821 ==============================================================
4991 22:50:04.571011 Gating Mode config
4992 22:50:04.574350 ==============================================================
4993 22:50:04.577783 Config description:
4994 22:50:04.587800 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4995 22:50:04.594285 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4996 22:50:04.597824 SELPH_MODE 0: By rank 1: By Phase
4997 22:50:04.604564 ==============================================================
4998 22:50:04.607874 GAT_TRACK_EN = 1
4999 22:50:04.611096 RX_GATING_MODE = 2
5000 22:50:04.614566 RX_GATING_TRACK_MODE = 2
5001 22:50:04.617885 SELPH_MODE = 1
5002 22:50:04.617965 PICG_EARLY_EN = 1
5003 22:50:04.620972 VALID_LAT_VALUE = 1
5004 22:50:04.627396 ==============================================================
5005 22:50:04.630972 Enter into Gating configuration >>>>
5006 22:50:04.634384 Exit from Gating configuration <<<<
5007 22:50:04.637276 Enter into DVFS_PRE_config >>>>>
5008 22:50:04.647336 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5009 22:50:04.650539 Exit from DVFS_PRE_config <<<<<
5010 22:50:04.653859 Enter into PICG configuration >>>>
5011 22:50:04.657086 Exit from PICG configuration <<<<
5012 22:50:04.660130 [RX_INPUT] configuration >>>>>
5013 22:50:04.663632 [RX_INPUT] configuration <<<<<
5014 22:50:04.670377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5015 22:50:04.673785 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5016 22:50:04.680979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 22:50:04.687115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 22:50:04.693692 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5019 22:50:04.699969 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5020 22:50:04.703447 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5021 22:50:04.706582 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5022 22:50:04.710071 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5023 22:50:04.716380 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5024 22:50:04.719950 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5025 22:50:04.723105 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 22:50:04.726657 ===================================
5027 22:50:04.729970 LPDDR4 DRAM CONFIGURATION
5028 22:50:04.733148 ===================================
5029 22:50:04.733221 EX_ROW_EN[0] = 0x0
5030 22:50:04.736539 EX_ROW_EN[1] = 0x0
5031 22:50:04.739913 LP4Y_EN = 0x0
5032 22:50:04.739984 WORK_FSP = 0x0
5033 22:50:04.743378 WL = 0x3
5034 22:50:04.743477 RL = 0x3
5035 22:50:04.746141 BL = 0x2
5036 22:50:04.746219 RPST = 0x0
5037 22:50:04.750055 RD_PRE = 0x0
5038 22:50:04.750133 WR_PRE = 0x1
5039 22:50:04.752728 WR_PST = 0x0
5040 22:50:04.752799 DBI_WR = 0x0
5041 22:50:04.755934 DBI_RD = 0x0
5042 22:50:04.756008 OTF = 0x1
5043 22:50:04.759745 ===================================
5044 22:50:04.762600 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5045 22:50:04.769161 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5046 22:50:04.772695 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 22:50:04.776049 ===================================
5048 22:50:04.779424 LPDDR4 DRAM CONFIGURATION
5049 22:50:04.782775 ===================================
5050 22:50:04.782922 EX_ROW_EN[0] = 0x10
5051 22:50:04.785656 EX_ROW_EN[1] = 0x0
5052 22:50:04.789188 LP4Y_EN = 0x0
5053 22:50:04.789302 WORK_FSP = 0x0
5054 22:50:04.792667 WL = 0x3
5055 22:50:04.792768 RL = 0x3
5056 22:50:04.795534 BL = 0x2
5057 22:50:04.795606 RPST = 0x0
5058 22:50:04.799079 RD_PRE = 0x0
5059 22:50:04.799175 WR_PRE = 0x1
5060 22:50:04.802303 WR_PST = 0x0
5061 22:50:04.802412 DBI_WR = 0x0
5062 22:50:04.805583 DBI_RD = 0x0
5063 22:50:04.805657 OTF = 0x1
5064 22:50:04.808972 ===================================
5065 22:50:04.815399 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5066 22:50:04.820039 nWR fixed to 30
5067 22:50:04.823573 [ModeRegInit_LP4] CH0 RK0
5068 22:50:04.823655 [ModeRegInit_LP4] CH0 RK1
5069 22:50:04.826985 [ModeRegInit_LP4] CH1 RK0
5070 22:50:04.830477 [ModeRegInit_LP4] CH1 RK1
5071 22:50:04.830582 match AC timing 9
5072 22:50:04.837055 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5073 22:50:04.839996 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5074 22:50:04.843172 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5075 22:50:04.849845 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5076 22:50:04.853394 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5077 22:50:04.853468 ==
5078 22:50:04.856335 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 22:50:04.860103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 22:50:04.860178 ==
5081 22:50:04.866644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 22:50:04.873211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5083 22:50:04.876573 [CA 0] Center 38 (8~69) winsize 62
5084 22:50:04.879428 [CA 1] Center 38 (8~69) winsize 62
5085 22:50:04.882871 [CA 2] Center 35 (5~65) winsize 61
5086 22:50:04.886363 [CA 3] Center 35 (5~65) winsize 61
5087 22:50:04.889805 [CA 4] Center 34 (4~64) winsize 61
5088 22:50:04.892891 [CA 5] Center 33 (3~64) winsize 62
5089 22:50:04.892982
5090 22:50:04.896140 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5091 22:50:04.896240
5092 22:50:04.899660 [CATrainingPosCal] consider 1 rank data
5093 22:50:04.903213 u2DelayCellTimex100 = 270/100 ps
5094 22:50:04.906479 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5095 22:50:04.909359 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5096 22:50:04.912923 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5097 22:50:04.916236 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5098 22:50:04.922596 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5099 22:50:04.926115 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5100 22:50:04.926188
5101 22:50:04.928953 CA PerBit enable=1, Macro0, CA PI delay=33
5102 22:50:04.929050
5103 22:50:04.932748 [CBTSetCACLKResult] CA Dly = 33
5104 22:50:04.932849 CS Dly: 7 (0~38)
5105 22:50:04.932926 ==
5106 22:50:04.935925 Dram Type= 6, Freq= 0, CH_0, rank 1
5107 22:50:04.942818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 22:50:04.942905 ==
5109 22:50:04.945760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 22:50:04.952328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5111 22:50:04.955875 [CA 0] Center 38 (8~69) winsize 62
5112 22:50:04.958935 [CA 1] Center 38 (7~69) winsize 63
5113 22:50:04.962356 [CA 2] Center 35 (5~66) winsize 62
5114 22:50:04.965428 [CA 3] Center 35 (5~66) winsize 62
5115 22:50:04.968996 [CA 4] Center 34 (4~65) winsize 62
5116 22:50:04.972416 [CA 5] Center 33 (3~64) winsize 62
5117 22:50:04.972525
5118 22:50:04.975792 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5119 22:50:04.975872
5120 22:50:04.978860 [CATrainingPosCal] consider 2 rank data
5121 22:50:04.982354 u2DelayCellTimex100 = 270/100 ps
5122 22:50:04.985747 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5123 22:50:04.989138 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5124 22:50:04.992497 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5125 22:50:04.998635 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 22:50:05.002359 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5127 22:50:05.005270 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5128 22:50:05.005362
5129 22:50:05.008681 CA PerBit enable=1, Macro0, CA PI delay=33
5130 22:50:05.008767
5131 22:50:05.012040 [CBTSetCACLKResult] CA Dly = 33
5132 22:50:05.012125 CS Dly: 7 (0~38)
5133 22:50:05.012192
5134 22:50:05.015377 ----->DramcWriteLeveling(PI) begin...
5135 22:50:05.018851 ==
5136 22:50:05.022175 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 22:50:05.025278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 22:50:05.025415 ==
5139 22:50:05.028816 Write leveling (Byte 0): 32 => 32
5140 22:50:05.032163 Write leveling (Byte 1): 30 => 30
5141 22:50:05.035391 DramcWriteLeveling(PI) end<-----
5142 22:50:05.035505
5143 22:50:05.035654 ==
5144 22:50:05.038851 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 22:50:05.041993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 22:50:05.042101 ==
5147 22:50:05.045380 [Gating] SW mode calibration
5148 22:50:05.051611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5149 22:50:05.058529 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5150 22:50:05.061904 0 14 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
5151 22:50:05.065024 0 14 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5152 22:50:05.071660 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 22:50:05.075043 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 22:50:05.078503 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 22:50:05.081352 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 22:50:05.088331 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 22:50:05.091678 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5158 22:50:05.095113 0 15 0 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (1 1)
5159 22:50:05.101337 0 15 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
5160 22:50:05.104564 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5161 22:50:05.108108 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 22:50:05.114770 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 22:50:05.118200 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 22:50:05.121518 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 22:50:05.127912 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 22:50:05.131087 1 0 0 | B1->B0 | 2727 3a3a | 0 0 | (0 0) (0 0)
5167 22:50:05.134687 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5168 22:50:05.141429 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 22:50:05.144324 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 22:50:05.148028 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 22:50:05.154380 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 22:50:05.157930 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 22:50:05.161077 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5174 22:50:05.167961 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5175 22:50:05.170822 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 22:50:05.174177 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 22:50:05.180730 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 22:50:05.184328 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 22:50:05.187539 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 22:50:05.194200 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 22:50:05.197623 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 22:50:05.200710 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 22:50:05.207373 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 22:50:05.210916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 22:50:05.214211 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 22:50:05.220782 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 22:50:05.224274 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 22:50:05.227224 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 22:50:05.233760 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 22:50:05.237090 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5191 22:50:05.240533 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5192 22:50:05.244286 Total UI for P1: 0, mck2ui 16
5193 22:50:05.247463 best dqsien dly found for B0: ( 1, 3, 0)
5194 22:50:05.250497 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5195 22:50:05.257303 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 22:50:05.260878 Total UI for P1: 0, mck2ui 16
5197 22:50:05.264220 best dqsien dly found for B1: ( 1, 3, 6)
5198 22:50:05.267480 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5199 22:50:05.270329 best DQS1 dly(MCK, UI, PI) = (1, 3, 6)
5200 22:50:05.270410
5201 22:50:05.273744 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5202 22:50:05.277265 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 6)
5203 22:50:05.280392 [Gating] SW calibration Done
5204 22:50:05.280473 ==
5205 22:50:05.283795 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 22:50:05.287246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 22:50:05.287328 ==
5208 22:50:05.290381 RX Vref Scan: 0
5209 22:50:05.290461
5210 22:50:05.290525 RX Vref 0 -> 0, step: 1
5211 22:50:05.294146
5212 22:50:05.294226 RX Delay -80 -> 252, step: 8
5213 22:50:05.300342 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5214 22:50:05.303864 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5215 22:50:05.307259 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5216 22:50:05.310589 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5217 22:50:05.313851 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5218 22:50:05.317186 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5219 22:50:05.323872 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5220 22:50:05.326881 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5221 22:50:05.330119 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5222 22:50:05.333628 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5223 22:50:05.336958 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5224 22:50:05.343338 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5225 22:50:05.346847 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5226 22:50:05.350366 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5227 22:50:05.353631 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5228 22:50:05.356522 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5229 22:50:05.356615 ==
5230 22:50:05.359857 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 22:50:05.366937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 22:50:05.367019 ==
5233 22:50:05.367083 DQS Delay:
5234 22:50:05.370196 DQS0 = 0, DQS1 = 0
5235 22:50:05.370277 DQM Delay:
5236 22:50:05.373386 DQM0 = 94, DQM1 = 83
5237 22:50:05.373466 DQ Delay:
5238 22:50:05.376590 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5239 22:50:05.379767 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5240 22:50:05.383201 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5241 22:50:05.386282 DQ12 =83, DQ13 =91, DQ14 =91, DQ15 =91
5242 22:50:05.386362
5243 22:50:05.386425
5244 22:50:05.386483 ==
5245 22:50:05.389910 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 22:50:05.393216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 22:50:05.393297 ==
5248 22:50:05.393359
5249 22:50:05.393418
5250 22:50:05.396530 TX Vref Scan disable
5251 22:50:05.399645 == TX Byte 0 ==
5252 22:50:05.402950 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5253 22:50:05.406381 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5254 22:50:05.409771 == TX Byte 1 ==
5255 22:50:05.412999 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5256 22:50:05.416289 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5257 22:50:05.416370 ==
5258 22:50:05.419930 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 22:50:05.423092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 22:50:05.426085 ==
5261 22:50:05.426171
5262 22:50:05.426234
5263 22:50:05.426293 TX Vref Scan disable
5264 22:50:05.429845 == TX Byte 0 ==
5265 22:50:05.433167 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5266 22:50:05.440084 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5267 22:50:05.440209 == TX Byte 1 ==
5268 22:50:05.443465 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5269 22:50:05.449710 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5270 22:50:05.449829
5271 22:50:05.449910 [DATLAT]
5272 22:50:05.449982 Freq=933, CH0 RK0
5273 22:50:05.450042
5274 22:50:05.453130 DATLAT Default: 0xd
5275 22:50:05.453232 0, 0xFFFF, sum = 0
5276 22:50:05.456456 1, 0xFFFF, sum = 0
5277 22:50:05.459769 2, 0xFFFF, sum = 0
5278 22:50:05.459846 3, 0xFFFF, sum = 0
5279 22:50:05.463124 4, 0xFFFF, sum = 0
5280 22:50:05.463231 5, 0xFFFF, sum = 0
5281 22:50:05.466375 6, 0xFFFF, sum = 0
5282 22:50:05.466451 7, 0xFFFF, sum = 0
5283 22:50:05.469782 8, 0xFFFF, sum = 0
5284 22:50:05.469856 9, 0xFFFF, sum = 0
5285 22:50:05.473139 10, 0x0, sum = 1
5286 22:50:05.473220 11, 0x0, sum = 2
5287 22:50:05.476069 12, 0x0, sum = 3
5288 22:50:05.476165 13, 0x0, sum = 4
5289 22:50:05.476249 best_step = 11
5290 22:50:05.479691
5291 22:50:05.479777 ==
5292 22:50:05.483100 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 22:50:05.486161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 22:50:05.486246 ==
5295 22:50:05.486309 RX Vref Scan: 1
5296 22:50:05.486368
5297 22:50:05.489315 RX Vref 0 -> 0, step: 1
5298 22:50:05.489403
5299 22:50:05.492601 RX Delay -69 -> 252, step: 4
5300 22:50:05.492712
5301 22:50:05.496109 Set Vref, RX VrefLevel [Byte0]: 60
5302 22:50:05.499443 [Byte1]: 46
5303 22:50:05.499523
5304 22:50:05.502742 Final RX Vref Byte 0 = 60 to rank0
5305 22:50:05.505932 Final RX Vref Byte 1 = 46 to rank0
5306 22:50:05.509262 Final RX Vref Byte 0 = 60 to rank1
5307 22:50:05.512757 Final RX Vref Byte 1 = 46 to rank1==
5308 22:50:05.515898 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 22:50:05.519374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 22:50:05.522458 ==
5311 22:50:05.522549 DQS Delay:
5312 22:50:05.522614 DQS0 = 0, DQS1 = 0
5313 22:50:05.525913 DQM Delay:
5314 22:50:05.526027 DQM0 = 96, DQM1 = 82
5315 22:50:05.529082 DQ Delay:
5316 22:50:05.529196 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5317 22:50:05.532532 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5318 22:50:05.535920 DQ8 =74, DQ9 =70, DQ10 =84, DQ11 =76
5319 22:50:05.542342 DQ12 =86, DQ13 =86, DQ14 =94, DQ15 =88
5320 22:50:05.542447
5321 22:50:05.542546
5322 22:50:05.549220 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5323 22:50:05.552532 CH0 RK0: MR19=505, MR18=1414
5324 22:50:05.558903 CH0_RK0: MR19=0x505, MR18=0x1414, DQSOSC=415, MR23=63, INC=62, DEC=41
5325 22:50:05.559017
5326 22:50:05.562458 ----->DramcWriteLeveling(PI) begin...
5327 22:50:05.562540 ==
5328 22:50:05.565860 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 22:50:05.569400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 22:50:05.569502 ==
5331 22:50:05.572432 Write leveling (Byte 0): 34 => 34
5332 22:50:05.575611 Write leveling (Byte 1): 32 => 32
5333 22:50:05.578942 DramcWriteLeveling(PI) end<-----
5334 22:50:05.579020
5335 22:50:05.579083 ==
5336 22:50:05.582452 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 22:50:05.585907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 22:50:05.585991 ==
5339 22:50:05.588618 [Gating] SW mode calibration
5340 22:50:05.595314 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5341 22:50:05.602039 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5342 22:50:05.605579 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5343 22:50:05.611909 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 22:50:05.615370 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 22:50:05.618665 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 22:50:05.625408 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 22:50:05.628748 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 22:50:05.631746 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 22:50:05.638366 0 14 28 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
5350 22:50:05.641663 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5351 22:50:05.645202 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 22:50:05.648361 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 22:50:05.654862 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 22:50:05.658259 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 22:50:05.661602 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 22:50:05.668276 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 22:50:05.671690 0 15 28 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
5358 22:50:05.675158 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
5359 22:50:05.681378 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 22:50:05.684727 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 22:50:05.688290 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 22:50:05.694944 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 22:50:05.698282 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 22:50:05.701879 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 22:50:05.707949 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5366 22:50:05.711674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5367 22:50:05.714837 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 22:50:05.721380 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 22:50:05.725057 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 22:50:05.727783 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 22:50:05.734560 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 22:50:05.738068 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 22:50:05.741490 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 22:50:05.747865 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 22:50:05.750939 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 22:50:05.754314 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 22:50:05.761074 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 22:50:05.764115 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 22:50:05.768066 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 22:50:05.774569 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 22:50:05.777469 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5382 22:50:05.781015 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 22:50:05.784340 Total UI for P1: 0, mck2ui 16
5384 22:50:05.787278 best dqsien dly found for B0: ( 1, 2, 28)
5385 22:50:05.790765 Total UI for P1: 0, mck2ui 16
5386 22:50:05.794068 best dqsien dly found for B1: ( 1, 2, 30)
5387 22:50:05.797347 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5388 22:50:05.800849 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5389 22:50:05.800923
5390 22:50:05.807222 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5391 22:50:05.810638 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5392 22:50:05.810707 [Gating] SW calibration Done
5393 22:50:05.814001 ==
5394 22:50:05.817415 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 22:50:05.820832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 22:50:05.820911 ==
5397 22:50:05.820974 RX Vref Scan: 0
5398 22:50:05.821031
5399 22:50:05.824198 RX Vref 0 -> 0, step: 1
5400 22:50:05.824274
5401 22:50:05.827024 RX Delay -80 -> 252, step: 8
5402 22:50:05.830612 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5403 22:50:05.833879 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5404 22:50:05.837091 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5405 22:50:05.843779 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5406 22:50:05.847551 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5407 22:50:05.850320 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5408 22:50:05.854417 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5409 22:50:05.857163 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5410 22:50:05.860374 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5411 22:50:05.867093 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5412 22:50:05.870242 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5413 22:50:05.873796 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5414 22:50:05.877391 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5415 22:50:05.880547 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5416 22:50:05.886803 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5417 22:50:05.890037 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5418 22:50:05.890112 ==
5419 22:50:05.893502 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 22:50:05.897053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 22:50:05.897126 ==
5422 22:50:05.897191 DQS Delay:
5423 22:50:05.900164 DQS0 = 0, DQS1 = 0
5424 22:50:05.900251 DQM Delay:
5425 22:50:05.903846 DQM0 = 92, DQM1 = 82
5426 22:50:05.903917 DQ Delay:
5427 22:50:05.906932 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5428 22:50:05.909982 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =103
5429 22:50:05.913281 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5430 22:50:05.916731 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =91
5431 22:50:05.916803
5432 22:50:05.916862
5433 22:50:05.916918 ==
5434 22:50:05.920294 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 22:50:05.926599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 22:50:05.926677 ==
5437 22:50:05.926748
5438 22:50:05.926807
5439 22:50:05.926862 TX Vref Scan disable
5440 22:50:05.929805 == TX Byte 0 ==
5441 22:50:05.933211 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5442 22:50:05.939939 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5443 22:50:05.940013 == TX Byte 1 ==
5444 22:50:05.943440 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5445 22:50:05.949823 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5446 22:50:05.949901 ==
5447 22:50:05.953191 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 22:50:05.956582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 22:50:05.956682 ==
5450 22:50:05.956771
5451 22:50:05.956864
5452 22:50:05.959833 TX Vref Scan disable
5453 22:50:05.959943 == TX Byte 0 ==
5454 22:50:05.966469 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5455 22:50:05.969639 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5456 22:50:05.969713 == TX Byte 1 ==
5457 22:50:05.976533 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5458 22:50:05.980102 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5459 22:50:05.980192
5460 22:50:05.980256 [DATLAT]
5461 22:50:05.982842 Freq=933, CH0 RK1
5462 22:50:05.982948
5463 22:50:05.983014 DATLAT Default: 0xb
5464 22:50:05.986342 0, 0xFFFF, sum = 0
5465 22:50:05.986426 1, 0xFFFF, sum = 0
5466 22:50:05.989867 2, 0xFFFF, sum = 0
5467 22:50:05.989950 3, 0xFFFF, sum = 0
5468 22:50:05.993169 4, 0xFFFF, sum = 0
5469 22:50:05.996216 5, 0xFFFF, sum = 0
5470 22:50:05.996301 6, 0xFFFF, sum = 0
5471 22:50:05.999704 7, 0xFFFF, sum = 0
5472 22:50:05.999787 8, 0xFFFF, sum = 0
5473 22:50:06.002878 9, 0xFFFF, sum = 0
5474 22:50:06.002960 10, 0x0, sum = 1
5475 22:50:06.006371 11, 0x0, sum = 2
5476 22:50:06.006453 12, 0x0, sum = 3
5477 22:50:06.006519 13, 0x0, sum = 4
5478 22:50:06.009393 best_step = 11
5479 22:50:06.009476
5480 22:50:06.009579 ==
5481 22:50:06.012812 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 22:50:06.016198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 22:50:06.016281 ==
5484 22:50:06.019561 RX Vref Scan: 0
5485 22:50:06.019643
5486 22:50:06.019707 RX Vref 0 -> 0, step: 1
5487 22:50:06.023008
5488 22:50:06.023117 RX Delay -77 -> 252, step: 4
5489 22:50:06.030195 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5490 22:50:06.033865 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5491 22:50:06.037368 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5492 22:50:06.040789 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5493 22:50:06.044126 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5494 22:50:06.046913 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5495 22:50:06.053851 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5496 22:50:06.057236 iDelay=199, Bit 7, Center 102 (7 ~ 198) 192
5497 22:50:06.060442 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5498 22:50:06.063817 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5499 22:50:06.066740 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5500 22:50:06.073776 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5501 22:50:06.076900 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5502 22:50:06.080234 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5503 22:50:06.083680 iDelay=199, Bit 14, Center 92 (3 ~ 182) 180
5504 22:50:06.086556 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5505 22:50:06.090102 ==
5506 22:50:06.093672 Dram Type= 6, Freq= 0, CH_0, rank 1
5507 22:50:06.096613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 22:50:06.096689 ==
5509 22:50:06.096752 DQS Delay:
5510 22:50:06.099942 DQS0 = 0, DQS1 = 0
5511 22:50:06.100016 DQM Delay:
5512 22:50:06.103292 DQM0 = 92, DQM1 = 83
5513 22:50:06.103379 DQ Delay:
5514 22:50:06.106638 DQ0 =92, DQ1 =94, DQ2 =88, DQ3 =88
5515 22:50:06.109760 DQ4 =90, DQ5 =82, DQ6 =106, DQ7 =102
5516 22:50:06.113108 DQ8 =74, DQ9 =66, DQ10 =86, DQ11 =76
5517 22:50:06.116674 DQ12 =90, DQ13 =90, DQ14 =92, DQ15 =90
5518 22:50:06.116750
5519 22:50:06.116817
5520 22:50:06.122912 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f12, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5521 22:50:06.126251 CH0 RK1: MR19=505, MR18=2F12
5522 22:50:06.133160 CH0_RK1: MR19=0x505, MR18=0x2F12, DQSOSC=407, MR23=63, INC=65, DEC=43
5523 22:50:06.136169 [RxdqsGatingPostProcess] freq 933
5524 22:50:06.143032 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5525 22:50:06.146343 best DQS0 dly(2T, 0.5T) = (0, 11)
5526 22:50:06.146421 best DQS1 dly(2T, 0.5T) = (0, 11)
5527 22:50:06.149911 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5528 22:50:06.152734 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5529 22:50:06.156176 best DQS0 dly(2T, 0.5T) = (0, 10)
5530 22:50:06.159579 best DQS1 dly(2T, 0.5T) = (0, 10)
5531 22:50:06.162985 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5532 22:50:06.166067 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5533 22:50:06.169832 Pre-setting of DQS Precalculation
5534 22:50:06.176009 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5535 22:50:06.176091 ==
5536 22:50:06.179345 Dram Type= 6, Freq= 0, CH_1, rank 0
5537 22:50:06.183135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 22:50:06.183216 ==
5539 22:50:06.189531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5540 22:50:06.193005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5541 22:50:06.196993 [CA 0] Center 37 (7~67) winsize 61
5542 22:50:06.200342 [CA 1] Center 37 (7~68) winsize 62
5543 22:50:06.203637 [CA 2] Center 34 (5~64) winsize 60
5544 22:50:06.206883 [CA 3] Center 34 (4~64) winsize 61
5545 22:50:06.210355 [CA 4] Center 34 (5~64) winsize 60
5546 22:50:06.213696 [CA 5] Center 33 (4~63) winsize 60
5547 22:50:06.213769
5548 22:50:06.217058 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5549 22:50:06.217140
5550 22:50:06.219908 [CATrainingPosCal] consider 1 rank data
5551 22:50:06.223139 u2DelayCellTimex100 = 270/100 ps
5552 22:50:06.226655 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5553 22:50:06.233409 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5554 22:50:06.236665 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5555 22:50:06.240077 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5556 22:50:06.243259 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5557 22:50:06.246560 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5558 22:50:06.246640
5559 22:50:06.250272 CA PerBit enable=1, Macro0, CA PI delay=33
5560 22:50:06.250353
5561 22:50:06.253242 [CBTSetCACLKResult] CA Dly = 33
5562 22:50:06.253347 CS Dly: 6 (0~37)
5563 22:50:06.256621 ==
5564 22:50:06.260106 Dram Type= 6, Freq= 0, CH_1, rank 1
5565 22:50:06.263415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 22:50:06.263495 ==
5567 22:50:06.266354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5568 22:50:06.273007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5569 22:50:06.276910 [CA 0] Center 38 (8~68) winsize 61
5570 22:50:06.280268 [CA 1] Center 37 (7~68) winsize 62
5571 22:50:06.283636 [CA 2] Center 35 (5~65) winsize 61
5572 22:50:06.286638 [CA 3] Center 34 (4~64) winsize 61
5573 22:50:06.290396 [CA 4] Center 35 (5~65) winsize 61
5574 22:50:06.293392 [CA 5] Center 33 (3~64) winsize 62
5575 22:50:06.293472
5576 22:50:06.296755 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5577 22:50:06.296836
5578 22:50:06.300152 [CATrainingPosCal] consider 2 rank data
5579 22:50:06.303081 u2DelayCellTimex100 = 270/100 ps
5580 22:50:06.306583 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5581 22:50:06.313304 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5582 22:50:06.316709 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5583 22:50:06.320112 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5584 22:50:06.323368 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5585 22:50:06.326610 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5586 22:50:06.326690
5587 22:50:06.330011 CA PerBit enable=1, Macro0, CA PI delay=33
5588 22:50:06.330091
5589 22:50:06.333354 [CBTSetCACLKResult] CA Dly = 33
5590 22:50:06.333434 CS Dly: 7 (0~39)
5591 22:50:06.336344
5592 22:50:06.339833 ----->DramcWriteLeveling(PI) begin...
5593 22:50:06.339915 ==
5594 22:50:06.343182 Dram Type= 6, Freq= 0, CH_1, rank 0
5595 22:50:06.346674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 22:50:06.346756 ==
5597 22:50:06.349467 Write leveling (Byte 0): 26 => 26
5598 22:50:06.352813 Write leveling (Byte 1): 29 => 29
5599 22:50:06.356450 DramcWriteLeveling(PI) end<-----
5600 22:50:06.356530
5601 22:50:06.356593 ==
5602 22:50:06.359840 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 22:50:06.362719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 22:50:06.362799 ==
5605 22:50:06.366364 [Gating] SW mode calibration
5606 22:50:06.372842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5607 22:50:06.379685 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5608 22:50:06.382939 0 14 0 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
5609 22:50:06.385993 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 22:50:06.393029 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 22:50:06.395882 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 22:50:06.399592 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 22:50:06.406135 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 22:50:06.409442 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 22:50:06.412377 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5616 22:50:06.419277 0 15 0 | B1->B0 | 2d2d 2424 | 0 1 | (0 0) (1 0)
5617 22:50:06.422717 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 22:50:06.425439 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 22:50:06.432595 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 22:50:06.435570 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 22:50:06.439241 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 22:50:06.445740 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 22:50:06.448646 0 15 28 | B1->B0 | 3232 3333 | 0 0 | (0 0) (1 1)
5624 22:50:06.452079 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 22:50:06.458710 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 22:50:06.461933 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 22:50:06.465408 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 22:50:06.472228 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 22:50:06.475094 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 22:50:06.478666 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 22:50:06.485352 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5632 22:50:06.488562 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 22:50:06.491882 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 22:50:06.498269 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 22:50:06.501899 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 22:50:06.505459 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 22:50:06.511691 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 22:50:06.515280 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 22:50:06.518568 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 22:50:06.524782 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 22:50:06.528120 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 22:50:06.531605 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 22:50:06.534988 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 22:50:06.541800 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 22:50:06.544685 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 22:50:06.548117 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 22:50:06.554941 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 22:50:06.558180 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 22:50:06.561237 Total UI for P1: 0, mck2ui 16
5650 22:50:06.564531 best dqsien dly found for B0: ( 1, 2, 30)
5651 22:50:06.567893 Total UI for P1: 0, mck2ui 16
5652 22:50:06.571447 best dqsien dly found for B1: ( 1, 2, 30)
5653 22:50:06.574909 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5654 22:50:06.578211 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5655 22:50:06.578281
5656 22:50:06.581151 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5657 22:50:06.584980 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5658 22:50:06.588290 [Gating] SW calibration Done
5659 22:50:06.588360 ==
5660 22:50:06.591127 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 22:50:06.598033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 22:50:06.598107 ==
5663 22:50:06.598173 RX Vref Scan: 0
5664 22:50:06.598234
5665 22:50:06.601270 RX Vref 0 -> 0, step: 1
5666 22:50:06.601340
5667 22:50:06.604516 RX Delay -80 -> 252, step: 8
5668 22:50:06.608149 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5669 22:50:06.611059 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5670 22:50:06.614480 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5671 22:50:06.617716 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5672 22:50:06.624635 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5673 22:50:06.627550 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5674 22:50:06.631060 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5675 22:50:06.634092 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5676 22:50:06.637426 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5677 22:50:06.644297 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5678 22:50:06.647633 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5679 22:50:06.651208 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5680 22:50:06.654333 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5681 22:50:06.657321 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5682 22:50:06.664181 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5683 22:50:06.667316 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5684 22:50:06.667389 ==
5685 22:50:06.670319 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 22:50:06.673795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 22:50:06.673867 ==
5688 22:50:06.673933 DQS Delay:
5689 22:50:06.677123 DQS0 = 0, DQS1 = 0
5690 22:50:06.677192 DQM Delay:
5691 22:50:06.680646 DQM0 = 94, DQM1 = 85
5692 22:50:06.680716 DQ Delay:
5693 22:50:06.684062 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5694 22:50:06.687244 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5695 22:50:06.690601 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5696 22:50:06.693430 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5697 22:50:06.693498
5698 22:50:06.693572
5699 22:50:06.693631 ==
5700 22:50:06.696792 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 22:50:06.703459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 22:50:06.703532 ==
5703 22:50:06.703592
5704 22:50:06.703648
5705 22:50:06.703710 TX Vref Scan disable
5706 22:50:06.707366 == TX Byte 0 ==
5707 22:50:06.710601 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5708 22:50:06.716897 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5709 22:50:06.716969 == TX Byte 1 ==
5710 22:50:06.720516 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5711 22:50:06.726904 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5712 22:50:06.726982 ==
5713 22:50:06.730128 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 22:50:06.733356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 22:50:06.733429 ==
5716 22:50:06.733488
5717 22:50:06.733593
5718 22:50:06.736882 TX Vref Scan disable
5719 22:50:06.736949 == TX Byte 0 ==
5720 22:50:06.743497 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5721 22:50:06.746940 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5722 22:50:06.747020 == TX Byte 1 ==
5723 22:50:06.753271 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5724 22:50:06.756593 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5725 22:50:06.756671
5726 22:50:06.756732 [DATLAT]
5727 22:50:06.760086 Freq=933, CH1 RK0
5728 22:50:06.760159
5729 22:50:06.760219 DATLAT Default: 0xd
5730 22:50:06.763513 0, 0xFFFF, sum = 0
5731 22:50:06.763586 1, 0xFFFF, sum = 0
5732 22:50:06.766441 2, 0xFFFF, sum = 0
5733 22:50:06.766510 3, 0xFFFF, sum = 0
5734 22:50:06.769721 4, 0xFFFF, sum = 0
5735 22:50:06.773177 5, 0xFFFF, sum = 0
5736 22:50:06.773246 6, 0xFFFF, sum = 0
5737 22:50:06.776409 7, 0xFFFF, sum = 0
5738 22:50:06.776479 8, 0xFFFF, sum = 0
5739 22:50:06.779735 9, 0xFFFF, sum = 0
5740 22:50:06.779807 10, 0x0, sum = 1
5741 22:50:06.783320 11, 0x0, sum = 2
5742 22:50:06.783394 12, 0x0, sum = 3
5743 22:50:06.786800 13, 0x0, sum = 4
5744 22:50:06.786867 best_step = 11
5745 22:50:06.786925
5746 22:50:06.786980 ==
5747 22:50:06.789795 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 22:50:06.793173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 22:50:06.793241 ==
5750 22:50:06.796362 RX Vref Scan: 1
5751 22:50:06.796433
5752 22:50:06.799721 RX Vref 0 -> 0, step: 1
5753 22:50:06.799795
5754 22:50:06.799857 RX Delay -69 -> 252, step: 4
5755 22:50:06.799915
5756 22:50:06.802789 Set Vref, RX VrefLevel [Byte0]: 57
5757 22:50:06.806135 [Byte1]: 46
5758 22:50:06.811035
5759 22:50:06.811105 Final RX Vref Byte 0 = 57 to rank0
5760 22:50:06.814355 Final RX Vref Byte 1 = 46 to rank0
5761 22:50:06.817595 Final RX Vref Byte 0 = 57 to rank1
5762 22:50:06.820988 Final RX Vref Byte 1 = 46 to rank1==
5763 22:50:06.824131 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 22:50:06.830809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 22:50:06.830883 ==
5766 22:50:06.830945 DQS Delay:
5767 22:50:06.831002 DQS0 = 0, DQS1 = 0
5768 22:50:06.834574 DQM Delay:
5769 22:50:06.834647 DQM0 = 96, DQM1 = 88
5770 22:50:06.837453 DQ Delay:
5771 22:50:06.841012 DQ0 =102, DQ1 =90, DQ2 =86, DQ3 =92
5772 22:50:06.843918 DQ4 =94, DQ5 =106, DQ6 =110, DQ7 =94
5773 22:50:06.847727 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =82
5774 22:50:06.850847 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
5775 22:50:06.850924
5776 22:50:06.850985
5777 22:50:06.857130 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5778 22:50:06.861025 CH1 RK0: MR19=405, MR18=FE07
5779 22:50:06.867243 CH1_RK0: MR19=0x405, MR18=0xFE07, DQSOSC=419, MR23=63, INC=61, DEC=41
5780 22:50:06.867319
5781 22:50:06.870883 ----->DramcWriteLeveling(PI) begin...
5782 22:50:06.870956 ==
5783 22:50:06.874187 Dram Type= 6, Freq= 0, CH_1, rank 1
5784 22:50:06.877636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 22:50:06.877703 ==
5786 22:50:06.880461 Write leveling (Byte 0): 27 => 27
5787 22:50:06.883681 Write leveling (Byte 1): 28 => 28
5788 22:50:06.887381 DramcWriteLeveling(PI) end<-----
5789 22:50:06.887452
5790 22:50:06.887512 ==
5791 22:50:06.890194 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 22:50:06.893616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 22:50:06.897189 ==
5794 22:50:06.897257 [Gating] SW mode calibration
5795 22:50:06.903822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5796 22:50:06.910634 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5797 22:50:06.914030 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 22:50:06.920537 0 14 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
5799 22:50:06.923812 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 22:50:06.926997 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 22:50:06.933812 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 22:50:06.936997 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5803 22:50:06.940168 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5804 22:50:06.947012 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5805 22:50:06.950463 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5806 22:50:06.953355 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 22:50:06.960257 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 22:50:06.963389 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 22:50:06.966788 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 22:50:06.973657 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 22:50:06.977028 0 15 24 | B1->B0 | 2727 3737 | 0 0 | (0 0) (0 0)
5812 22:50:06.979773 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5813 22:50:06.986398 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 22:50:06.989807 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 22:50:06.993323 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 22:50:06.999989 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 22:50:07.003230 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 22:50:07.006609 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 22:50:07.012909 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5820 22:50:07.016216 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5821 22:50:07.019723 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 22:50:07.026029 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 22:50:07.029846 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 22:50:07.033024 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 22:50:07.039388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 22:50:07.042656 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 22:50:07.046109 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 22:50:07.049173 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 22:50:07.056221 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 22:50:07.059463 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 22:50:07.062710 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 22:50:07.069430 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 22:50:07.072325 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 22:50:07.075857 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 22:50:07.082371 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5836 22:50:07.085459 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 22:50:07.089262 Total UI for P1: 0, mck2ui 16
5838 22:50:07.092334 best dqsien dly found for B0: ( 1, 2, 24)
5839 22:50:07.095863 Total UI for P1: 0, mck2ui 16
5840 22:50:07.099119 best dqsien dly found for B1: ( 1, 2, 24)
5841 22:50:07.102144 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5842 22:50:07.105747 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5843 22:50:07.105821
5844 22:50:07.109010 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5845 22:50:07.112606 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5846 22:50:07.115914 [Gating] SW calibration Done
5847 22:50:07.115994 ==
5848 22:50:07.118850 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 22:50:07.125785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 22:50:07.125866 ==
5851 22:50:07.125929 RX Vref Scan: 0
5852 22:50:07.125988
5853 22:50:07.129256 RX Vref 0 -> 0, step: 1
5854 22:50:07.129335
5855 22:50:07.132087 RX Delay -80 -> 252, step: 8
5856 22:50:07.135451 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5857 22:50:07.139152 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5858 22:50:07.142594 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5859 22:50:07.145275 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5860 22:50:07.152230 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5861 22:50:07.155544 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5862 22:50:07.158687 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5863 22:50:07.162452 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5864 22:50:07.165287 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5865 22:50:07.168485 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5866 22:50:07.175208 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5867 22:50:07.178606 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5868 22:50:07.181927 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5869 22:50:07.185354 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5870 22:50:07.188844 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5871 22:50:07.195530 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5872 22:50:07.195610 ==
5873 22:50:07.198665 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 22:50:07.201859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 22:50:07.201940 ==
5876 22:50:07.202003 DQS Delay:
5877 22:50:07.205418 DQS0 = 0, DQS1 = 0
5878 22:50:07.205543 DQM Delay:
5879 22:50:07.208605 DQM0 = 93, DQM1 = 88
5880 22:50:07.208685 DQ Delay:
5881 22:50:07.211890 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5882 22:50:07.215545 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5883 22:50:07.218204 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5884 22:50:07.221410 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5885 22:50:07.221520
5886 22:50:07.221618
5887 22:50:07.221677 ==
5888 22:50:07.224843 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 22:50:07.228260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 22:50:07.228342 ==
5891 22:50:07.231819
5892 22:50:07.231898
5893 22:50:07.231961 TX Vref Scan disable
5894 22:50:07.235257 == TX Byte 0 ==
5895 22:50:07.238600 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5896 22:50:07.241355 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5897 22:50:07.244826 == TX Byte 1 ==
5898 22:50:07.248169 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5899 22:50:07.251405 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5900 22:50:07.251486 ==
5901 22:50:07.254781 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 22:50:07.261272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 22:50:07.261358 ==
5904 22:50:07.261459
5905 22:50:07.261566
5906 22:50:07.264386 TX Vref Scan disable
5907 22:50:07.264457 == TX Byte 0 ==
5908 22:50:07.270941 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5909 22:50:07.274368 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5910 22:50:07.274443 == TX Byte 1 ==
5911 22:50:07.280926 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5912 22:50:07.284510 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5913 22:50:07.284618
5914 22:50:07.284680 [DATLAT]
5915 22:50:07.287393 Freq=933, CH1 RK1
5916 22:50:07.287471
5917 22:50:07.287534 DATLAT Default: 0xb
5918 22:50:07.290817 0, 0xFFFF, sum = 0
5919 22:50:07.290888 1, 0xFFFF, sum = 0
5920 22:50:07.294336 2, 0xFFFF, sum = 0
5921 22:50:07.294410 3, 0xFFFF, sum = 0
5922 22:50:07.297746 4, 0xFFFF, sum = 0
5923 22:50:07.297815 5, 0xFFFF, sum = 0
5924 22:50:07.301084 6, 0xFFFF, sum = 0
5925 22:50:07.301153 7, 0xFFFF, sum = 0
5926 22:50:07.304428 8, 0xFFFF, sum = 0
5927 22:50:07.307733 9, 0xFFFF, sum = 0
5928 22:50:07.307804 10, 0x0, sum = 1
5929 22:50:07.307863 11, 0x0, sum = 2
5930 22:50:07.310788 12, 0x0, sum = 3
5931 22:50:07.310858 13, 0x0, sum = 4
5932 22:50:07.314219 best_step = 11
5933 22:50:07.314287
5934 22:50:07.314344 ==
5935 22:50:07.317576 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 22:50:07.320784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 22:50:07.320858 ==
5938 22:50:07.323858 RX Vref Scan: 0
5939 22:50:07.323926
5940 22:50:07.323986 RX Vref 0 -> 0, step: 1
5941 22:50:07.327613
5942 22:50:07.327681 RX Delay -69 -> 252, step: 4
5943 22:50:07.334988 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5944 22:50:07.337917 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5945 22:50:07.341418 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5946 22:50:07.344910 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5947 22:50:07.347817 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5948 22:50:07.354587 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5949 22:50:07.358040 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5950 22:50:07.361598 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5951 22:50:07.364956 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5952 22:50:07.367808 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5953 22:50:07.371455 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5954 22:50:07.378243 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5955 22:50:07.381479 iDelay=203, Bit 12, Center 96 (7 ~ 186) 180
5956 22:50:07.384962 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5957 22:50:07.387894 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5958 22:50:07.391439 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5959 22:50:07.391519 ==
5960 22:50:07.394652 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 22:50:07.401462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 22:50:07.401593 ==
5963 22:50:07.401657 DQS Delay:
5964 22:50:07.404318 DQS0 = 0, DQS1 = 0
5965 22:50:07.404398 DQM Delay:
5966 22:50:07.404461 DQM0 = 92, DQM1 = 90
5967 22:50:07.407840 DQ Delay:
5968 22:50:07.411301 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =90
5969 22:50:07.414645 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =90
5970 22:50:07.417937 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =82
5971 22:50:07.420968 DQ12 =96, DQ13 =98, DQ14 =100, DQ15 =96
5972 22:50:07.421048
5973 22:50:07.421112
5974 22:50:07.427586 [DQSOSCAuto] RK1, (LSB)MR18= 0x1024, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5975 22:50:07.431079 CH1 RK1: MR19=505, MR18=1024
5976 22:50:07.437823 CH1_RK1: MR19=0x505, MR18=0x1024, DQSOSC=410, MR23=63, INC=64, DEC=42
5977 22:50:07.440921 [RxdqsGatingPostProcess] freq 933
5978 22:50:07.447828 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5979 22:50:07.447908 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 22:50:07.450742 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 22:50:07.454236 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 22:50:07.457418 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 22:50:07.460950 best DQS0 dly(2T, 0.5T) = (0, 10)
5984 22:50:07.464200 best DQS1 dly(2T, 0.5T) = (0, 10)
5985 22:50:07.467256 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5986 22:50:07.470683 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5987 22:50:07.473878 Pre-setting of DQS Precalculation
5988 22:50:07.480547 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5989 22:50:07.487225 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5990 22:50:07.494112 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5991 22:50:07.494185
5992 22:50:07.494245
5993 22:50:07.497389 [Calibration Summary] 1866 Mbps
5994 22:50:07.497456 CH 0, Rank 0
5995 22:50:07.500427 SW Impedance : PASS
5996 22:50:07.503665 DUTY Scan : NO K
5997 22:50:07.503732 ZQ Calibration : PASS
5998 22:50:07.507065 Jitter Meter : NO K
5999 22:50:07.507134 CBT Training : PASS
6000 22:50:07.510481 Write leveling : PASS
6001 22:50:07.513878 RX DQS gating : PASS
6002 22:50:07.513947 RX DQ/DQS(RDDQC) : PASS
6003 22:50:07.516755 TX DQ/DQS : PASS
6004 22:50:07.520211 RX DATLAT : PASS
6005 22:50:07.520279 RX DQ/DQS(Engine): PASS
6006 22:50:07.523581 TX OE : NO K
6007 22:50:07.523652 All Pass.
6008 22:50:07.523710
6009 22:50:07.527153 CH 0, Rank 1
6010 22:50:07.527223 SW Impedance : PASS
6011 22:50:07.530340 DUTY Scan : NO K
6012 22:50:07.534020 ZQ Calibration : PASS
6013 22:50:07.534089 Jitter Meter : NO K
6014 22:50:07.536867 CBT Training : PASS
6015 22:50:07.540134 Write leveling : PASS
6016 22:50:07.540202 RX DQS gating : PASS
6017 22:50:07.543410 RX DQ/DQS(RDDQC) : PASS
6018 22:50:07.546933 TX DQ/DQS : PASS
6019 22:50:07.547003 RX DATLAT : PASS
6020 22:50:07.549823 RX DQ/DQS(Engine): PASS
6021 22:50:07.553199 TX OE : NO K
6022 22:50:07.553271 All Pass.
6023 22:50:07.553331
6024 22:50:07.553388 CH 1, Rank 0
6025 22:50:07.556742 SW Impedance : PASS
6026 22:50:07.560218 DUTY Scan : NO K
6027 22:50:07.560288 ZQ Calibration : PASS
6028 22:50:07.563573 Jitter Meter : NO K
6029 22:50:07.566496 CBT Training : PASS
6030 22:50:07.566570 Write leveling : PASS
6031 22:50:07.569995 RX DQS gating : PASS
6032 22:50:07.570064 RX DQ/DQS(RDDQC) : PASS
6033 22:50:07.573381 TX DQ/DQS : PASS
6034 22:50:07.576646 RX DATLAT : PASS
6035 22:50:07.576718 RX DQ/DQS(Engine): PASS
6036 22:50:07.580050 TX OE : NO K
6037 22:50:07.580117 All Pass.
6038 22:50:07.580185
6039 22:50:07.583411 CH 1, Rank 1
6040 22:50:07.583482 SW Impedance : PASS
6041 22:50:07.586452 DUTY Scan : NO K
6042 22:50:07.590001 ZQ Calibration : PASS
6043 22:50:07.590070 Jitter Meter : NO K
6044 22:50:07.592872 CBT Training : PASS
6045 22:50:07.596492 Write leveling : PASS
6046 22:50:07.596561 RX DQS gating : PASS
6047 22:50:07.599911 RX DQ/DQS(RDDQC) : PASS
6048 22:50:07.603120 TX DQ/DQS : PASS
6049 22:50:07.603189 RX DATLAT : PASS
6050 22:50:07.606437 RX DQ/DQS(Engine): PASS
6051 22:50:07.609731 TX OE : NO K
6052 22:50:07.609801 All Pass.
6053 22:50:07.609861
6054 22:50:07.609925 DramC Write-DBI off
6055 22:50:07.612984 PER_BANK_REFRESH: Hybrid Mode
6056 22:50:07.616393 TX_TRACKING: ON
6057 22:50:07.622721 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6058 22:50:07.629614 [FAST_K] Save calibration result to emmc
6059 22:50:07.632765 dramc_set_vcore_voltage set vcore to 650000
6060 22:50:07.632836 Read voltage for 400, 6
6061 22:50:07.635911 Vio18 = 0
6062 22:50:07.635982 Vcore = 650000
6063 22:50:07.636042 Vdram = 0
6064 22:50:07.639205 Vddq = 0
6065 22:50:07.639277 Vmddr = 0
6066 22:50:07.642689 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6067 22:50:07.649454 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6068 22:50:07.652710 MEM_TYPE=3, freq_sel=20
6069 22:50:07.655781 sv_algorithm_assistance_LP4_800
6070 22:50:07.659129 ============ PULL DRAM RESETB DOWN ============
6071 22:50:07.662549 ========== PULL DRAM RESETB DOWN end =========
6072 22:50:07.669201 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6073 22:50:07.669274 ===================================
6074 22:50:07.672568 LPDDR4 DRAM CONFIGURATION
6075 22:50:07.675937 ===================================
6076 22:50:07.679395 EX_ROW_EN[0] = 0x0
6077 22:50:07.679464 EX_ROW_EN[1] = 0x0
6078 22:50:07.682326 LP4Y_EN = 0x0
6079 22:50:07.682396 WORK_FSP = 0x0
6080 22:50:07.685637 WL = 0x2
6081 22:50:07.685704 RL = 0x2
6082 22:50:07.688867 BL = 0x2
6083 22:50:07.688935 RPST = 0x0
6084 22:50:07.692507 RD_PRE = 0x0
6085 22:50:07.695743 WR_PRE = 0x1
6086 22:50:07.695815 WR_PST = 0x0
6087 22:50:07.699168 DBI_WR = 0x0
6088 22:50:07.699242 DBI_RD = 0x0
6089 22:50:07.702217 OTF = 0x1
6090 22:50:07.705464 ===================================
6091 22:50:07.708918 ===================================
6092 22:50:07.708989 ANA top config
6093 22:50:07.712364 ===================================
6094 22:50:07.715398 DLL_ASYNC_EN = 0
6095 22:50:07.718692 ALL_SLAVE_EN = 1
6096 22:50:07.718761 NEW_RANK_MODE = 1
6097 22:50:07.722107 DLL_IDLE_MODE = 1
6098 22:50:07.725430 LP45_APHY_COMB_EN = 1
6099 22:50:07.728972 TX_ODT_DIS = 1
6100 22:50:07.729040 NEW_8X_MODE = 1
6101 22:50:07.732357 ===================================
6102 22:50:07.735738 ===================================
6103 22:50:07.738965 data_rate = 800
6104 22:50:07.742745 CKR = 1
6105 22:50:07.745476 DQ_P2S_RATIO = 4
6106 22:50:07.749056 ===================================
6107 22:50:07.752127 CA_P2S_RATIO = 4
6108 22:50:07.755797 DQ_CA_OPEN = 0
6109 22:50:07.755878 DQ_SEMI_OPEN = 1
6110 22:50:07.758965 CA_SEMI_OPEN = 1
6111 22:50:07.762051 CA_FULL_RATE = 0
6112 22:50:07.765364 DQ_CKDIV4_EN = 0
6113 22:50:07.768539 CA_CKDIV4_EN = 1
6114 22:50:07.772462 CA_PREDIV_EN = 0
6115 22:50:07.772542 PH8_DLY = 0
6116 22:50:07.775342 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6117 22:50:07.778787 DQ_AAMCK_DIV = 0
6118 22:50:07.782284 CA_AAMCK_DIV = 0
6119 22:50:07.785113 CA_ADMCK_DIV = 4
6120 22:50:07.788701 DQ_TRACK_CA_EN = 0
6121 22:50:07.788803 CA_PICK = 800
6122 22:50:07.792004 CA_MCKIO = 400
6123 22:50:07.795607 MCKIO_SEMI = 400
6124 22:50:07.798634 PLL_FREQ = 3016
6125 22:50:07.801905 DQ_UI_PI_RATIO = 32
6126 22:50:07.805104 CA_UI_PI_RATIO = 32
6127 22:50:07.808650 ===================================
6128 22:50:07.811743 ===================================
6129 22:50:07.815080 memory_type:LPDDR4
6130 22:50:07.815188 GP_NUM : 10
6131 22:50:07.818383 SRAM_EN : 1
6132 22:50:07.818488 MD32_EN : 0
6133 22:50:07.821661 ===================================
6134 22:50:07.825285 [ANA_INIT] >>>>>>>>>>>>>>
6135 22:50:07.828056 <<<<<< [CONFIGURE PHASE]: ANA_TX
6136 22:50:07.831571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6137 22:50:07.835191 ===================================
6138 22:50:07.838044 data_rate = 800,PCW = 0X7400
6139 22:50:07.841934 ===================================
6140 22:50:07.845025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6141 22:50:07.851260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 22:50:07.861411 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 22:50:07.864910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6144 22:50:07.867764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6145 22:50:07.874640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6146 22:50:07.874716 [ANA_INIT] flow start
6147 22:50:07.877708 [ANA_INIT] PLL >>>>>>>>
6148 22:50:07.877780 [ANA_INIT] PLL <<<<<<<<
6149 22:50:07.881166 [ANA_INIT] MIDPI >>>>>>>>
6150 22:50:07.884527 [ANA_INIT] MIDPI <<<<<<<<
6151 22:50:07.887927 [ANA_INIT] DLL >>>>>>>>
6152 22:50:07.887999 [ANA_INIT] flow end
6153 22:50:07.891413 ============ LP4 DIFF to SE enter ============
6154 22:50:07.897954 ============ LP4 DIFF to SE exit ============
6155 22:50:07.898030 [ANA_INIT] <<<<<<<<<<<<<
6156 22:50:07.901349 [Flow] Enable top DCM control >>>>>
6157 22:50:07.904535 [Flow] Enable top DCM control <<<<<
6158 22:50:07.907866 Enable DLL master slave shuffle
6159 22:50:07.914580 ==============================================================
6160 22:50:07.914656 Gating Mode config
6161 22:50:07.920925 ==============================================================
6162 22:50:07.924365 Config description:
6163 22:50:07.934034 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6164 22:50:07.940829 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6165 22:50:07.944193 SELPH_MODE 0: By rank 1: By Phase
6166 22:50:07.950625 ==============================================================
6167 22:50:07.954273 GAT_TRACK_EN = 0
6168 22:50:07.957161 RX_GATING_MODE = 2
6169 22:50:07.957241 RX_GATING_TRACK_MODE = 2
6170 22:50:07.960474 SELPH_MODE = 1
6171 22:50:07.964328 PICG_EARLY_EN = 1
6172 22:50:07.967143 VALID_LAT_VALUE = 1
6173 22:50:07.973656 ==============================================================
6174 22:50:07.977368 Enter into Gating configuration >>>>
6175 22:50:07.980778 Exit from Gating configuration <<<<
6176 22:50:07.984054 Enter into DVFS_PRE_config >>>>>
6177 22:50:07.993805 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6178 22:50:07.997482 Exit from DVFS_PRE_config <<<<<
6179 22:50:08.000462 Enter into PICG configuration >>>>
6180 22:50:08.003928 Exit from PICG configuration <<<<
6181 22:50:08.007235 [RX_INPUT] configuration >>>>>
6182 22:50:08.010713 [RX_INPUT] configuration <<<<<
6183 22:50:08.014019 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6184 22:50:08.020664 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6185 22:50:08.027044 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6186 22:50:08.034008 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6187 22:50:08.037242 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 22:50:08.043649 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 22:50:08.046995 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6190 22:50:08.053716 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6191 22:50:08.057085 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6192 22:50:08.060134 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6193 22:50:08.063578 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6194 22:50:08.070284 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6195 22:50:08.073542 ===================================
6196 22:50:08.073627 LPDDR4 DRAM CONFIGURATION
6197 22:50:08.077034 ===================================
6198 22:50:08.080037 EX_ROW_EN[0] = 0x0
6199 22:50:08.083239 EX_ROW_EN[1] = 0x0
6200 22:50:08.083318 LP4Y_EN = 0x0
6201 22:50:08.086737 WORK_FSP = 0x0
6202 22:50:08.086805 WL = 0x2
6203 22:50:08.089854 RL = 0x2
6204 22:50:08.089924 BL = 0x2
6205 22:50:08.093163 RPST = 0x0
6206 22:50:08.093230 RD_PRE = 0x0
6207 22:50:08.096877 WR_PRE = 0x1
6208 22:50:08.097018 WR_PST = 0x0
6209 22:50:08.100120 DBI_WR = 0x0
6210 22:50:08.100190 DBI_RD = 0x0
6211 22:50:08.103447 OTF = 0x1
6212 22:50:08.106343 ===================================
6213 22:50:08.110206 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6214 22:50:08.113505 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6215 22:50:08.120060 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6216 22:50:08.123107 ===================================
6217 22:50:08.123177 LPDDR4 DRAM CONFIGURATION
6218 22:50:08.126453 ===================================
6219 22:50:08.129694 EX_ROW_EN[0] = 0x10
6220 22:50:08.132714 EX_ROW_EN[1] = 0x0
6221 22:50:08.132793 LP4Y_EN = 0x0
6222 22:50:08.136090 WORK_FSP = 0x0
6223 22:50:08.136163 WL = 0x2
6224 22:50:08.139578 RL = 0x2
6225 22:50:08.139652 BL = 0x2
6226 22:50:08.143084 RPST = 0x0
6227 22:50:08.143151 RD_PRE = 0x0
6228 22:50:08.146278 WR_PRE = 0x1
6229 22:50:08.146348 WR_PST = 0x0
6230 22:50:08.149331 DBI_WR = 0x0
6231 22:50:08.149435 DBI_RD = 0x0
6232 22:50:08.152659 OTF = 0x1
6233 22:50:08.156101 ===================================
6234 22:50:08.162715 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6235 22:50:08.165953 nWR fixed to 30
6236 22:50:08.169142 [ModeRegInit_LP4] CH0 RK0
6237 22:50:08.169215 [ModeRegInit_LP4] CH0 RK1
6238 22:50:08.172780 [ModeRegInit_LP4] CH1 RK0
6239 22:50:08.176055 [ModeRegInit_LP4] CH1 RK1
6240 22:50:08.176130 match AC timing 19
6241 22:50:08.182839 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6242 22:50:08.185673 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6243 22:50:08.188960 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6244 22:50:08.195674 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6245 22:50:08.199008 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6246 22:50:08.199082 ==
6247 22:50:08.202464 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 22:50:08.205762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 22:50:08.205835 ==
6250 22:50:08.212183 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6251 22:50:08.218674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6252 22:50:08.222169 [CA 0] Center 36 (8~64) winsize 57
6253 22:50:08.225538 [CA 1] Center 36 (8~64) winsize 57
6254 22:50:08.228971 [CA 2] Center 36 (8~64) winsize 57
6255 22:50:08.232278 [CA 3] Center 36 (8~64) winsize 57
6256 22:50:08.232377 [CA 4] Center 36 (8~64) winsize 57
6257 22:50:08.235180 [CA 5] Center 36 (8~64) winsize 57
6258 22:50:08.235260
6259 22:50:08.242235 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6260 22:50:08.242316
6261 22:50:08.245708 [CATrainingPosCal] consider 1 rank data
6262 22:50:08.248464 u2DelayCellTimex100 = 270/100 ps
6263 22:50:08.252064 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 22:50:08.255180 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 22:50:08.258799 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 22:50:08.261773 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 22:50:08.265107 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 22:50:08.268521 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 22:50:08.268602
6270 22:50:08.271937 CA PerBit enable=1, Macro0, CA PI delay=36
6271 22:50:08.272017
6272 22:50:08.274797 [CBTSetCACLKResult] CA Dly = 36
6273 22:50:08.278469 CS Dly: 1 (0~32)
6274 22:50:08.278549 ==
6275 22:50:08.281539 Dram Type= 6, Freq= 0, CH_0, rank 1
6276 22:50:08.284915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 22:50:08.284999 ==
6278 22:50:08.291692 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 22:50:08.298193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6280 22:50:08.301434 [CA 0] Center 36 (8~64) winsize 57
6281 22:50:08.301525 [CA 1] Center 36 (8~64) winsize 57
6282 22:50:08.304790 [CA 2] Center 36 (8~64) winsize 57
6283 22:50:08.307988 [CA 3] Center 36 (8~64) winsize 57
6284 22:50:08.311819 [CA 4] Center 36 (8~64) winsize 57
6285 22:50:08.314677 [CA 5] Center 36 (8~64) winsize 57
6286 22:50:08.314757
6287 22:50:08.318042 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6288 22:50:08.318138
6289 22:50:08.324926 [CATrainingPosCal] consider 2 rank data
6290 22:50:08.325007 u2DelayCellTimex100 = 270/100 ps
6291 22:50:08.331620 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 22:50:08.334581 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 22:50:08.338110 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 22:50:08.341087 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 22:50:08.344344 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 22:50:08.347719 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 22:50:08.347800
6298 22:50:08.351226 CA PerBit enable=1, Macro0, CA PI delay=36
6299 22:50:08.351307
6300 22:50:08.354574 [CBTSetCACLKResult] CA Dly = 36
6301 22:50:08.357947 CS Dly: 1 (0~32)
6302 22:50:08.358029
6303 22:50:08.360683 ----->DramcWriteLeveling(PI) begin...
6304 22:50:08.360765 ==
6305 22:50:08.364427 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 22:50:08.367416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 22:50:08.367498 ==
6308 22:50:08.370974 Write leveling (Byte 0): 40 => 8
6309 22:50:08.374130 Write leveling (Byte 1): 32 => 0
6310 22:50:08.377486 DramcWriteLeveling(PI) end<-----
6311 22:50:08.377608
6312 22:50:08.377671 ==
6313 22:50:08.380757 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 22:50:08.384251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 22:50:08.384346 ==
6316 22:50:08.387373 [Gating] SW mode calibration
6317 22:50:08.393892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6318 22:50:08.400732 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6319 22:50:08.404289 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 22:50:08.407155 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 22:50:08.414035 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 22:50:08.417424 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 22:50:08.420555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 22:50:08.426831 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 22:50:08.430552 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 22:50:08.433293 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 22:50:08.440253 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 22:50:08.443493 Total UI for P1: 0, mck2ui 16
6329 22:50:08.446723 best dqsien dly found for B0: ( 0, 14, 24)
6330 22:50:08.446803 Total UI for P1: 0, mck2ui 16
6331 22:50:08.453099 best dqsien dly found for B1: ( 0, 14, 24)
6332 22:50:08.456558 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6333 22:50:08.460062 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6334 22:50:08.460142
6335 22:50:08.463490 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 22:50:08.466374 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 22:50:08.470236 [Gating] SW calibration Done
6338 22:50:08.470316 ==
6339 22:50:08.473290 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 22:50:08.476462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 22:50:08.476543 ==
6342 22:50:08.479875 RX Vref Scan: 0
6343 22:50:08.479954
6344 22:50:08.480016 RX Vref 0 -> 0, step: 1
6345 22:50:08.483242
6346 22:50:08.483320 RX Delay -410 -> 252, step: 16
6347 22:50:08.489543 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6348 22:50:08.492996 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6349 22:50:08.496286 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6350 22:50:08.502818 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6351 22:50:08.506222 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6352 22:50:08.509617 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6353 22:50:08.513044 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6354 22:50:08.516165 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6355 22:50:08.522953 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6356 22:50:08.526168 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6357 22:50:08.529077 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6358 22:50:08.535754 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6359 22:50:08.539085 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6360 22:50:08.542854 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6361 22:50:08.545920 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6362 22:50:08.552235 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6363 22:50:08.552317 ==
6364 22:50:08.556028 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 22:50:08.559217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 22:50:08.559297 ==
6367 22:50:08.559359 DQS Delay:
6368 22:50:08.562296 DQS0 = 59, DQS1 = 59
6369 22:50:08.562376 DQM Delay:
6370 22:50:08.565782 DQM0 = 18, DQM1 = 9
6371 22:50:08.565862 DQ Delay:
6372 22:50:08.569181 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6373 22:50:08.572737 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6374 22:50:08.575983 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6375 22:50:08.579251 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6376 22:50:08.579331
6377 22:50:08.579394
6378 22:50:08.579452 ==
6379 22:50:08.582373 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 22:50:08.586059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 22:50:08.586171 ==
6382 22:50:08.586234
6383 22:50:08.586292
6384 22:50:08.588811 TX Vref Scan disable
6385 22:50:08.592353 == TX Byte 0 ==
6386 22:50:08.595790 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 22:50:08.599173 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 22:50:08.601971 == TX Byte 1 ==
6389 22:50:08.605755 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6390 22:50:08.608844 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6391 22:50:08.608924 ==
6392 22:50:08.612308 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 22:50:08.615734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 22:50:08.618675 ==
6395 22:50:08.618756
6396 22:50:08.618819
6397 22:50:08.618878 TX Vref Scan disable
6398 22:50:08.622284 == TX Byte 0 ==
6399 22:50:08.625246 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 22:50:08.628434 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 22:50:08.632023 == TX Byte 1 ==
6402 22:50:08.635387 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6403 22:50:08.638737 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6404 22:50:08.638818
6405 22:50:08.642180 [DATLAT]
6406 22:50:08.642260 Freq=400, CH0 RK0
6407 22:50:08.642324
6408 22:50:08.645211 DATLAT Default: 0xf
6409 22:50:08.645308 0, 0xFFFF, sum = 0
6410 22:50:08.648580 1, 0xFFFF, sum = 0
6411 22:50:08.648662 2, 0xFFFF, sum = 0
6412 22:50:08.651939 3, 0xFFFF, sum = 0
6413 22:50:08.652021 4, 0xFFFF, sum = 0
6414 22:50:08.655108 5, 0xFFFF, sum = 0
6415 22:50:08.655190 6, 0xFFFF, sum = 0
6416 22:50:08.658214 7, 0xFFFF, sum = 0
6417 22:50:08.658296 8, 0xFFFF, sum = 0
6418 22:50:08.661853 9, 0xFFFF, sum = 0
6419 22:50:08.661935 10, 0xFFFF, sum = 0
6420 22:50:08.664996 11, 0xFFFF, sum = 0
6421 22:50:08.668279 12, 0xFFFF, sum = 0
6422 22:50:08.668375 13, 0x0, sum = 1
6423 22:50:08.668440 14, 0x0, sum = 2
6424 22:50:08.671658 15, 0x0, sum = 3
6425 22:50:08.671766 16, 0x0, sum = 4
6426 22:50:08.675175 best_step = 14
6427 22:50:08.675255
6428 22:50:08.675319 ==
6429 22:50:08.678699 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 22:50:08.681415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 22:50:08.681545 ==
6432 22:50:08.684954 RX Vref Scan: 1
6433 22:50:08.685050
6434 22:50:08.685114 RX Vref 0 -> 0, step: 1
6435 22:50:08.685174
6436 22:50:08.688657 RX Delay -359 -> 252, step: 8
6437 22:50:08.688772
6438 22:50:08.691676 Set Vref, RX VrefLevel [Byte0]: 60
6439 22:50:08.694778 [Byte1]: 46
6440 22:50:08.699962
6441 22:50:08.700042 Final RX Vref Byte 0 = 60 to rank0
6442 22:50:08.703432 Final RX Vref Byte 1 = 46 to rank0
6443 22:50:08.706683 Final RX Vref Byte 0 = 60 to rank1
6444 22:50:08.709721 Final RX Vref Byte 1 = 46 to rank1==
6445 22:50:08.713130 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 22:50:08.719801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 22:50:08.719882 ==
6448 22:50:08.719945 DQS Delay:
6449 22:50:08.723239 DQS0 = 60, DQS1 = 64
6450 22:50:08.723320 DQM Delay:
6451 22:50:08.723383 DQM0 = 14, DQM1 = 10
6452 22:50:08.726613 DQ Delay:
6453 22:50:08.729420 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6454 22:50:08.733182 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6455 22:50:08.733263 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6456 22:50:08.736242 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6457 22:50:08.739946
6458 22:50:08.740026
6459 22:50:08.746213 [DQSOSCAuto] RK0, (LSB)MR18= 0x8886, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6460 22:50:08.749978 CH0 RK0: MR19=C0C, MR18=8886
6461 22:50:08.756380 CH0_RK0: MR19=0xC0C, MR18=0x8886, DQSOSC=392, MR23=63, INC=384, DEC=256
6462 22:50:08.756462 ==
6463 22:50:08.759790 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 22:50:08.763043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 22:50:08.763124 ==
6466 22:50:08.766148 [Gating] SW mode calibration
6467 22:50:08.772939 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6468 22:50:08.779273 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6469 22:50:08.782914 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 22:50:08.786334 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 22:50:08.792377 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 22:50:08.795824 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 22:50:08.799432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 22:50:08.805881 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 22:50:08.809447 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 22:50:08.812328 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 22:50:08.819056 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 22:50:08.819135 Total UI for P1: 0, mck2ui 16
6479 22:50:08.825871 best dqsien dly found for B0: ( 0, 14, 24)
6480 22:50:08.825953 Total UI for P1: 0, mck2ui 16
6481 22:50:08.828949 best dqsien dly found for B1: ( 0, 14, 24)
6482 22:50:08.835965 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6483 22:50:08.839334 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6484 22:50:08.839415
6485 22:50:08.842310 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 22:50:08.845976 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 22:50:08.849294 [Gating] SW calibration Done
6488 22:50:08.849389 ==
6489 22:50:08.852566 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 22:50:08.855573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 22:50:08.855655 ==
6492 22:50:08.859335 RX Vref Scan: 0
6493 22:50:08.859416
6494 22:50:08.859479 RX Vref 0 -> 0, step: 1
6495 22:50:08.859538
6496 22:50:08.862616 RX Delay -410 -> 252, step: 16
6497 22:50:08.868900 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6498 22:50:08.872479 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6499 22:50:08.875398 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6500 22:50:08.878888 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6501 22:50:08.885921 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6502 22:50:08.888736 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6503 22:50:08.892453 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6504 22:50:08.895373 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6505 22:50:08.901888 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6506 22:50:08.905381 iDelay=230, Bit 9, Center -67 (-314 ~ 181) 496
6507 22:50:08.908632 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6508 22:50:08.911781 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6509 22:50:08.918741 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6510 22:50:08.921926 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6511 22:50:08.925228 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6512 22:50:08.928610 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6513 22:50:08.931553 ==
6514 22:50:08.934933 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 22:50:08.938145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 22:50:08.938286 ==
6517 22:50:08.938349 DQS Delay:
6518 22:50:08.941883 DQS0 = 59, DQS1 = 67
6519 22:50:08.941963 DQM Delay:
6520 22:50:08.944686 DQM0 = 15, DQM1 = 17
6521 22:50:08.944767 DQ Delay:
6522 22:50:08.948169 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6523 22:50:08.951463 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6524 22:50:08.954945 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6525 22:50:08.957827 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6526 22:50:08.957922
6527 22:50:08.957985
6528 22:50:08.958044 ==
6529 22:50:08.961160 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 22:50:08.964651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 22:50:08.964745 ==
6532 22:50:08.964808
6533 22:50:08.964867
6534 22:50:08.967803 TX Vref Scan disable
6535 22:50:08.967883 == TX Byte 0 ==
6536 22:50:08.974760 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6537 22:50:08.978195 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6538 22:50:08.978276 == TX Byte 1 ==
6539 22:50:08.984420 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6540 22:50:08.987803 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6541 22:50:08.987884 ==
6542 22:50:08.991550 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 22:50:08.995022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 22:50:08.995103 ==
6545 22:50:08.995166
6546 22:50:08.995241
6547 22:50:08.997786 TX Vref Scan disable
6548 22:50:08.997866 == TX Byte 0 ==
6549 22:50:09.004994 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6550 22:50:09.007809 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6551 22:50:09.007905 == TX Byte 1 ==
6552 22:50:09.014662 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6553 22:50:09.018070 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6554 22:50:09.018151
6555 22:50:09.018213 [DATLAT]
6556 22:50:09.020851 Freq=400, CH0 RK1
6557 22:50:09.020946
6558 22:50:09.021009 DATLAT Default: 0xe
6559 22:50:09.024393 0, 0xFFFF, sum = 0
6560 22:50:09.024475 1, 0xFFFF, sum = 0
6561 22:50:09.027738 2, 0xFFFF, sum = 0
6562 22:50:09.027819 3, 0xFFFF, sum = 0
6563 22:50:09.031045 4, 0xFFFF, sum = 0
6564 22:50:09.031126 5, 0xFFFF, sum = 0
6565 22:50:09.034353 6, 0xFFFF, sum = 0
6566 22:50:09.037837 7, 0xFFFF, sum = 0
6567 22:50:09.037920 8, 0xFFFF, sum = 0
6568 22:50:09.040825 9, 0xFFFF, sum = 0
6569 22:50:09.040923 10, 0xFFFF, sum = 0
6570 22:50:09.044284 11, 0xFFFF, sum = 0
6571 22:50:09.044366 12, 0xFFFF, sum = 0
6572 22:50:09.047660 13, 0x0, sum = 1
6573 22:50:09.047741 14, 0x0, sum = 2
6574 22:50:09.050941 15, 0x0, sum = 3
6575 22:50:09.051022 16, 0x0, sum = 4
6576 22:50:09.051086 best_step = 14
6577 22:50:09.053988
6578 22:50:09.054067 ==
6579 22:50:09.057385 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 22:50:09.060948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 22:50:09.061029 ==
6582 22:50:09.061092 RX Vref Scan: 0
6583 22:50:09.061151
6584 22:50:09.063825 RX Vref 0 -> 0, step: 1
6585 22:50:09.063906
6586 22:50:09.067265 RX Delay -359 -> 252, step: 8
6587 22:50:09.074745 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6588 22:50:09.077948 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6589 22:50:09.081053 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6590 22:50:09.088022 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6591 22:50:09.091274 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6592 22:50:09.094543 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6593 22:50:09.097683 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6594 22:50:09.104463 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6595 22:50:09.107462 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6596 22:50:09.110734 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6597 22:50:09.114789 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6598 22:50:09.120739 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6599 22:50:09.124213 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6600 22:50:09.127661 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6601 22:50:09.131076 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6602 22:50:09.137728 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6603 22:50:09.137809 ==
6604 22:50:09.141083 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 22:50:09.143960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 22:50:09.144042 ==
6607 22:50:09.144106 DQS Delay:
6608 22:50:09.147373 DQS0 = 60, DQS1 = 68
6609 22:50:09.147453 DQM Delay:
6610 22:50:09.150858 DQM0 = 11, DQM1 = 13
6611 22:50:09.151001 DQ Delay:
6612 22:50:09.153778 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6613 22:50:09.157190 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6614 22:50:09.160603 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6615 22:50:09.163891 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6616 22:50:09.163971
6617 22:50:09.164035
6618 22:50:09.170728 [DQSOSCAuto] RK1, (LSB)MR18= 0xce84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6619 22:50:09.174061 CH0 RK1: MR19=C0C, MR18=CE84
6620 22:50:09.180953 CH0_RK1: MR19=0xC0C, MR18=0xCE84, DQSOSC=384, MR23=63, INC=400, DEC=267
6621 22:50:09.183944 [RxdqsGatingPostProcess] freq 400
6622 22:50:09.190745 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6623 22:50:09.194105 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 22:50:09.194176 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 22:50:09.197038 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 22:50:09.200480 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 22:50:09.203854 best DQS0 dly(2T, 0.5T) = (0, 10)
6628 22:50:09.207451 best DQS1 dly(2T, 0.5T) = (0, 10)
6629 22:50:09.210755 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6630 22:50:09.213645 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6631 22:50:09.217147 Pre-setting of DQS Precalculation
6632 22:50:09.223789 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6633 22:50:09.223886 ==
6634 22:50:09.226816 Dram Type= 6, Freq= 0, CH_1, rank 0
6635 22:50:09.230274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 22:50:09.230347 ==
6637 22:50:09.236877 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6638 22:50:09.240304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6639 22:50:09.243645 [CA 0] Center 36 (8~64) winsize 57
6640 22:50:09.246931 [CA 1] Center 36 (8~64) winsize 57
6641 22:50:09.250236 [CA 2] Center 36 (8~64) winsize 57
6642 22:50:09.253234 [CA 3] Center 36 (8~64) winsize 57
6643 22:50:09.256754 [CA 4] Center 36 (8~64) winsize 57
6644 22:50:09.260144 [CA 5] Center 36 (8~64) winsize 57
6645 22:50:09.260225
6646 22:50:09.263147 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6647 22:50:09.263228
6648 22:50:09.266480 [CATrainingPosCal] consider 1 rank data
6649 22:50:09.270015 u2DelayCellTimex100 = 270/100 ps
6650 22:50:09.273364 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 22:50:09.276639 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 22:50:09.283332 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 22:50:09.286458 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 22:50:09.289721 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 22:50:09.293104 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 22:50:09.293181
6657 22:50:09.296586 CA PerBit enable=1, Macro0, CA PI delay=36
6658 22:50:09.296659
6659 22:50:09.299712 [CBTSetCACLKResult] CA Dly = 36
6660 22:50:09.299784 CS Dly: 1 (0~32)
6661 22:50:09.299847 ==
6662 22:50:09.303142 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 22:50:09.310151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 22:50:09.310223 ==
6665 22:50:09.312947 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 22:50:09.320088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6667 22:50:09.322992 [CA 0] Center 36 (8~64) winsize 57
6668 22:50:09.326692 [CA 1] Center 36 (8~64) winsize 57
6669 22:50:09.329825 [CA 2] Center 36 (8~64) winsize 57
6670 22:50:09.333205 [CA 3] Center 36 (8~64) winsize 57
6671 22:50:09.336644 [CA 4] Center 36 (8~64) winsize 57
6672 22:50:09.339746 [CA 5] Center 36 (8~64) winsize 57
6673 22:50:09.339814
6674 22:50:09.343040 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6675 22:50:09.343130
6676 22:50:09.346333 [CATrainingPosCal] consider 2 rank data
6677 22:50:09.349814 u2DelayCellTimex100 = 270/100 ps
6678 22:50:09.353242 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 22:50:09.356478 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 22:50:09.359592 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 22:50:09.362689 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 22:50:09.365979 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 22:50:09.372858 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 22:50:09.372934
6685 22:50:09.376320 CA PerBit enable=1, Macro0, CA PI delay=36
6686 22:50:09.376396
6687 22:50:09.379823 [CBTSetCACLKResult] CA Dly = 36
6688 22:50:09.379892 CS Dly: 1 (0~32)
6689 22:50:09.379951
6690 22:50:09.383123 ----->DramcWriteLeveling(PI) begin...
6691 22:50:09.383207 ==
6692 22:50:09.386506 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 22:50:09.389335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 22:50:09.393232 ==
6695 22:50:09.393313 Write leveling (Byte 0): 40 => 8
6696 22:50:09.396193 Write leveling (Byte 1): 40 => 8
6697 22:50:09.399667 DramcWriteLeveling(PI) end<-----
6698 22:50:09.399748
6699 22:50:09.399810 ==
6700 22:50:09.402947 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 22:50:09.409881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 22:50:09.409963 ==
6703 22:50:09.410027 [Gating] SW mode calibration
6704 22:50:09.419729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6705 22:50:09.422640 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6706 22:50:09.426023 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 22:50:09.432504 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 22:50:09.435974 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 22:50:09.439613 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 22:50:09.445866 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 22:50:09.449333 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 22:50:09.452593 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 22:50:09.459506 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 22:50:09.462444 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 22:50:09.465740 Total UI for P1: 0, mck2ui 16
6716 22:50:09.469087 best dqsien dly found for B0: ( 0, 14, 24)
6717 22:50:09.472688 Total UI for P1: 0, mck2ui 16
6718 22:50:09.475690 best dqsien dly found for B1: ( 0, 14, 24)
6719 22:50:09.479357 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6720 22:50:09.482736 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6721 22:50:09.482836
6722 22:50:09.485540 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 22:50:09.488884 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 22:50:09.492379 [Gating] SW calibration Done
6725 22:50:09.492478 ==
6726 22:50:09.495938 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 22:50:09.502130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 22:50:09.502227 ==
6729 22:50:09.502324 RX Vref Scan: 0
6730 22:50:09.502399
6731 22:50:09.505897 RX Vref 0 -> 0, step: 1
6732 22:50:09.505977
6733 22:50:09.509041 RX Delay -410 -> 252, step: 16
6734 22:50:09.512726 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6735 22:50:09.515737 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6736 22:50:09.522121 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6737 22:50:09.525713 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6738 22:50:09.529114 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6739 22:50:09.532496 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6740 22:50:09.535402 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6741 22:50:09.542312 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6742 22:50:09.545610 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6743 22:50:09.548912 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6744 22:50:09.552098 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6745 22:50:09.558832 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6746 22:50:09.562447 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6747 22:50:09.565652 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6748 22:50:09.572192 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6749 22:50:09.575264 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6750 22:50:09.575338 ==
6751 22:50:09.578653 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 22:50:09.581943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 22:50:09.582020 ==
6754 22:50:09.585445 DQS Delay:
6755 22:50:09.585525 DQS0 = 51, DQS1 = 67
6756 22:50:09.588775 DQM Delay:
6757 22:50:09.588848 DQM0 = 13, DQM1 = 17
6758 22:50:09.588908 DQ Delay:
6759 22:50:09.591937 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6760 22:50:09.595100 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6761 22:50:09.598552 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6762 22:50:09.601877 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6763 22:50:09.601953
6764 22:50:09.602014
6765 22:50:09.602071 ==
6766 22:50:09.605308 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 22:50:09.611457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 22:50:09.611530 ==
6769 22:50:09.611645
6770 22:50:09.611722
6771 22:50:09.611792 TX Vref Scan disable
6772 22:50:09.614899 == TX Byte 0 ==
6773 22:50:09.618162 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 22:50:09.621875 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 22:50:09.624737 == TX Byte 1 ==
6776 22:50:09.628332 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 22:50:09.631339 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 22:50:09.631484 ==
6779 22:50:09.634926 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 22:50:09.641139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 22:50:09.641212 ==
6782 22:50:09.641273
6783 22:50:09.641330
6784 22:50:09.641392 TX Vref Scan disable
6785 22:50:09.644683 == TX Byte 0 ==
6786 22:50:09.648120 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 22:50:09.651114 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 22:50:09.654712 == TX Byte 1 ==
6789 22:50:09.657822 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 22:50:09.661188 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 22:50:09.661285
6792 22:50:09.664475 [DATLAT]
6793 22:50:09.664574 Freq=400, CH1 RK0
6794 22:50:09.664696
6795 22:50:09.667995 DATLAT Default: 0xf
6796 22:50:09.668093 0, 0xFFFF, sum = 0
6797 22:50:09.671233 1, 0xFFFF, sum = 0
6798 22:50:09.671323 2, 0xFFFF, sum = 0
6799 22:50:09.674245 3, 0xFFFF, sum = 0
6800 22:50:09.674343 4, 0xFFFF, sum = 0
6801 22:50:09.677469 5, 0xFFFF, sum = 0
6802 22:50:09.680907 6, 0xFFFF, sum = 0
6803 22:50:09.680984 7, 0xFFFF, sum = 0
6804 22:50:09.684304 8, 0xFFFF, sum = 0
6805 22:50:09.684379 9, 0xFFFF, sum = 0
6806 22:50:09.687726 10, 0xFFFF, sum = 0
6807 22:50:09.687800 11, 0xFFFF, sum = 0
6808 22:50:09.691119 12, 0xFFFF, sum = 0
6809 22:50:09.691197 13, 0x0, sum = 1
6810 22:50:09.694314 14, 0x0, sum = 2
6811 22:50:09.694386 15, 0x0, sum = 3
6812 22:50:09.697895 16, 0x0, sum = 4
6813 22:50:09.697968 best_step = 14
6814 22:50:09.698027
6815 22:50:09.698084 ==
6816 22:50:09.700762 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 22:50:09.704095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 22:50:09.704191 ==
6819 22:50:09.707309 RX Vref Scan: 1
6820 22:50:09.707429
6821 22:50:09.710726 RX Vref 0 -> 0, step: 1
6822 22:50:09.710822
6823 22:50:09.710939 RX Delay -375 -> 252, step: 8
6824 22:50:09.713946
6825 22:50:09.714018 Set Vref, RX VrefLevel [Byte0]: 57
6826 22:50:09.717422 [Byte1]: 46
6827 22:50:09.723106
6828 22:50:09.723179 Final RX Vref Byte 0 = 57 to rank0
6829 22:50:09.726459 Final RX Vref Byte 1 = 46 to rank0
6830 22:50:09.729687 Final RX Vref Byte 0 = 57 to rank1
6831 22:50:09.733193 Final RX Vref Byte 1 = 46 to rank1==
6832 22:50:09.736296 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 22:50:09.743035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 22:50:09.743111 ==
6835 22:50:09.743219 DQS Delay:
6836 22:50:09.746427 DQS0 = 56, DQS1 = 68
6837 22:50:09.746495 DQM Delay:
6838 22:50:09.746552 DQM0 = 13, DQM1 = 14
6839 22:50:09.749224 DQ Delay:
6840 22:50:09.752759 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6841 22:50:09.756176 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6842 22:50:09.756248 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6843 22:50:09.759642 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6844 22:50:09.762575
6845 22:50:09.762668
6846 22:50:09.769369 [DQSOSCAuto] RK0, (LSB)MR18= 0x576b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6847 22:50:09.772911 CH1 RK0: MR19=C0C, MR18=576B
6848 22:50:09.779288 CH1_RK0: MR19=0xC0C, MR18=0x576B, DQSOSC=396, MR23=63, INC=376, DEC=251
6849 22:50:09.779389 ==
6850 22:50:09.782932 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 22:50:09.786047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 22:50:09.786120 ==
6853 22:50:09.789264 [Gating] SW mode calibration
6854 22:50:09.795976 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6855 22:50:09.802277 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6856 22:50:09.805977 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 22:50:09.809288 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 22:50:09.815779 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 22:50:09.819224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 22:50:09.822394 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 22:50:09.829199 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 22:50:09.832172 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 22:50:09.835687 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 22:50:09.841948 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 22:50:09.842024 Total UI for P1: 0, mck2ui 16
6866 22:50:09.849129 best dqsien dly found for B0: ( 0, 14, 24)
6867 22:50:09.849233 Total UI for P1: 0, mck2ui 16
6868 22:50:09.851995 best dqsien dly found for B1: ( 0, 14, 24)
6869 22:50:09.858946 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6870 22:50:09.861798 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6871 22:50:09.861872
6872 22:50:09.865253 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 22:50:09.868781 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 22:50:09.872161 [Gating] SW calibration Done
6875 22:50:09.872262 ==
6876 22:50:09.875462 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 22:50:09.878756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 22:50:09.878868 ==
6879 22:50:09.882202 RX Vref Scan: 0
6880 22:50:09.882274
6881 22:50:09.882337 RX Vref 0 -> 0, step: 1
6882 22:50:09.882395
6883 22:50:09.885217 RX Delay -410 -> 252, step: 16
6884 22:50:09.891904 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6885 22:50:09.895274 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6886 22:50:09.898555 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6887 22:50:09.901476 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6888 22:50:09.908487 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6889 22:50:09.911771 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6890 22:50:09.915073 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6891 22:50:09.918480 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6892 22:50:09.924816 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6893 22:50:09.928292 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6894 22:50:09.931351 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6895 22:50:09.934918 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6896 22:50:09.941273 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6897 22:50:09.944747 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6898 22:50:09.947955 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6899 22:50:09.951234 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6900 22:50:09.954759 ==
6901 22:50:09.958202 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 22:50:09.961297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 22:50:09.961409 ==
6904 22:50:09.961501 DQS Delay:
6905 22:50:09.964240 DQS0 = 59, DQS1 = 59
6906 22:50:09.964337 DQM Delay:
6907 22:50:09.967787 DQM0 = 19, DQM1 = 11
6908 22:50:09.967858 DQ Delay:
6909 22:50:09.971280 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6910 22:50:09.974163 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6911 22:50:09.977640 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =0
6912 22:50:09.981133 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6913 22:50:09.981205
6914 22:50:09.981265
6915 22:50:09.981322 ==
6916 22:50:09.984552 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 22:50:09.987439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 22:50:09.987508 ==
6919 22:50:09.987566
6920 22:50:09.987648
6921 22:50:09.991095 TX Vref Scan disable
6922 22:50:09.994139 == TX Byte 0 ==
6923 22:50:09.997625 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6924 22:50:10.000957 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6925 22:50:10.001024 == TX Byte 1 ==
6926 22:50:10.007748 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6927 22:50:10.010678 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6928 22:50:10.010748 ==
6929 22:50:10.014152 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 22:50:10.017482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 22:50:10.017576 ==
6932 22:50:10.017668
6933 22:50:10.020723
6934 22:50:10.020791 TX Vref Scan disable
6935 22:50:10.023728 == TX Byte 0 ==
6936 22:50:10.027178 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6937 22:50:10.030460 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6938 22:50:10.033819 == TX Byte 1 ==
6939 22:50:10.036984 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6940 22:50:10.040549 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6941 22:50:10.040649
6942 22:50:10.040740 [DATLAT]
6943 22:50:10.043633 Freq=400, CH1 RK1
6944 22:50:10.043739
6945 22:50:10.043799 DATLAT Default: 0xe
6946 22:50:10.046973 0, 0xFFFF, sum = 0
6947 22:50:10.050472 1, 0xFFFF, sum = 0
6948 22:50:10.050571 2, 0xFFFF, sum = 0
6949 22:50:10.053364 3, 0xFFFF, sum = 0
6950 22:50:10.053462 4, 0xFFFF, sum = 0
6951 22:50:10.056692 5, 0xFFFF, sum = 0
6952 22:50:10.056766 6, 0xFFFF, sum = 0
6953 22:50:10.060358 7, 0xFFFF, sum = 0
6954 22:50:10.060457 8, 0xFFFF, sum = 0
6955 22:50:10.063570 9, 0xFFFF, sum = 0
6956 22:50:10.063641 10, 0xFFFF, sum = 0
6957 22:50:10.067015 11, 0xFFFF, sum = 0
6958 22:50:10.067114 12, 0xFFFF, sum = 0
6959 22:50:10.070399 13, 0x0, sum = 1
6960 22:50:10.070473 14, 0x0, sum = 2
6961 22:50:10.073813 15, 0x0, sum = 3
6962 22:50:10.073918 16, 0x0, sum = 4
6963 22:50:10.076589 best_step = 14
6964 22:50:10.076663
6965 22:50:10.076755 ==
6966 22:50:10.080088 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 22:50:10.083514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 22:50:10.083589 ==
6969 22:50:10.086915 RX Vref Scan: 0
6970 22:50:10.087012
6971 22:50:10.087103 RX Vref 0 -> 0, step: 1
6972 22:50:10.087188
6973 22:50:10.089743 RX Delay -359 -> 252, step: 8
6974 22:50:10.097702 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6975 22:50:10.101040 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6976 22:50:10.104220 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6977 22:50:10.111242 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6978 22:50:10.114143 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6979 22:50:10.117819 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6980 22:50:10.121010 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6981 22:50:10.124050 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6982 22:50:10.130882 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6983 22:50:10.134080 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6984 22:50:10.137922 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6985 22:50:10.144106 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6986 22:50:10.147568 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6987 22:50:10.150807 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6988 22:50:10.153906 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6989 22:50:10.160731 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6990 22:50:10.160809 ==
6991 22:50:10.164352 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 22:50:10.167253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 22:50:10.167330 ==
6994 22:50:10.167391 DQS Delay:
6995 22:50:10.170374 DQS0 = 60, DQS1 = 64
6996 22:50:10.170476 DQM Delay:
6997 22:50:10.173952 DQM0 = 13, DQM1 = 10
6998 22:50:10.174056 DQ Delay:
6999 22:50:10.177343 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7000 22:50:10.180616 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7001 22:50:10.183832 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7002 22:50:10.187328 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =16
7003 22:50:10.187428
7004 22:50:10.187525
7005 22:50:10.193750 [DQSOSCAuto] RK1, (LSB)MR18= 0x76a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
7006 22:50:10.197262 CH1 RK1: MR19=C0C, MR18=76A6
7007 22:50:10.203753 CH1_RK1: MR19=0xC0C, MR18=0x76A6, DQSOSC=389, MR23=63, INC=390, DEC=260
7008 22:50:10.206960 [RxdqsGatingPostProcess] freq 400
7009 22:50:10.213732 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7010 22:50:10.217266 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 22:50:10.217368 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 22:50:10.220185 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 22:50:10.223744 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 22:50:10.227230 best DQS0 dly(2T, 0.5T) = (0, 10)
7015 22:50:10.230615 best DQS1 dly(2T, 0.5T) = (0, 10)
7016 22:50:10.233883 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7017 22:50:10.237084 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7018 22:50:10.240318 Pre-setting of DQS Precalculation
7019 22:50:10.246781 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7020 22:50:10.253213 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7021 22:50:10.259852 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7022 22:50:10.259957
7023 22:50:10.260048
7024 22:50:10.263539 [Calibration Summary] 800 Mbps
7025 22:50:10.263638 CH 0, Rank 0
7026 22:50:10.266546 SW Impedance : PASS
7027 22:50:10.269820 DUTY Scan : NO K
7028 22:50:10.269890 ZQ Calibration : PASS
7029 22:50:10.273340 Jitter Meter : NO K
7030 22:50:10.276806 CBT Training : PASS
7031 22:50:10.276880 Write leveling : PASS
7032 22:50:10.280098 RX DQS gating : PASS
7033 22:50:10.280196 RX DQ/DQS(RDDQC) : PASS
7034 22:50:10.283166 TX DQ/DQS : PASS
7035 22:50:10.286480 RX DATLAT : PASS
7036 22:50:10.286612 RX DQ/DQS(Engine): PASS
7037 22:50:10.290360 TX OE : NO K
7038 22:50:10.290448 All Pass.
7039 22:50:10.290580
7040 22:50:10.293447 CH 0, Rank 1
7041 22:50:10.293579 SW Impedance : PASS
7042 22:50:10.297019 DUTY Scan : NO K
7043 22:50:10.299849 ZQ Calibration : PASS
7044 22:50:10.299923 Jitter Meter : NO K
7045 22:50:10.303319 CBT Training : PASS
7046 22:50:10.306720 Write leveling : NO K
7047 22:50:10.306791 RX DQS gating : PASS
7048 22:50:10.309644 RX DQ/DQS(RDDQC) : PASS
7049 22:50:10.313006 TX DQ/DQS : PASS
7050 22:50:10.313104 RX DATLAT : PASS
7051 22:50:10.316495 RX DQ/DQS(Engine): PASS
7052 22:50:10.319903 TX OE : NO K
7053 22:50:10.319998 All Pass.
7054 22:50:10.320086
7055 22:50:10.320171 CH 1, Rank 0
7056 22:50:10.323449 SW Impedance : PASS
7057 22:50:10.326650 DUTY Scan : NO K
7058 22:50:10.326742 ZQ Calibration : PASS
7059 22:50:10.329673 Jitter Meter : NO K
7060 22:50:10.333139 CBT Training : PASS
7061 22:50:10.333231 Write leveling : PASS
7062 22:50:10.336308 RX DQS gating : PASS
7063 22:50:10.336419 RX DQ/DQS(RDDQC) : PASS
7064 22:50:10.339502 TX DQ/DQS : PASS
7065 22:50:10.342957 RX DATLAT : PASS
7066 22:50:10.343024 RX DQ/DQS(Engine): PASS
7067 22:50:10.346290 TX OE : NO K
7068 22:50:10.346356 All Pass.
7069 22:50:10.346414
7070 22:50:10.349745 CH 1, Rank 1
7071 22:50:10.349826 SW Impedance : PASS
7072 22:50:10.352884 DUTY Scan : NO K
7073 22:50:10.356569 ZQ Calibration : PASS
7074 22:50:10.356673 Jitter Meter : NO K
7075 22:50:10.360101 CBT Training : PASS
7076 22:50:10.363203 Write leveling : NO K
7077 22:50:10.363278 RX DQS gating : PASS
7078 22:50:10.366306 RX DQ/DQS(RDDQC) : PASS
7079 22:50:10.369531 TX DQ/DQS : PASS
7080 22:50:10.369618 RX DATLAT : PASS
7081 22:50:10.372837 RX DQ/DQS(Engine): PASS
7082 22:50:10.376177 TX OE : NO K
7083 22:50:10.376269 All Pass.
7084 22:50:10.376344
7085 22:50:10.376459 DramC Write-DBI off
7086 22:50:10.379524 PER_BANK_REFRESH: Hybrid Mode
7087 22:50:10.383063 TX_TRACKING: ON
7088 22:50:10.389461 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7089 22:50:10.392740 [FAST_K] Save calibration result to emmc
7090 22:50:10.399775 dramc_set_vcore_voltage set vcore to 725000
7091 22:50:10.399873 Read voltage for 1600, 0
7092 22:50:10.402688 Vio18 = 0
7093 22:50:10.402757 Vcore = 725000
7094 22:50:10.402816 Vdram = 0
7095 22:50:10.406389 Vddq = 0
7096 22:50:10.406477 Vmddr = 0
7097 22:50:10.409194 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7098 22:50:10.416198 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7099 22:50:10.419734 MEM_TYPE=3, freq_sel=13
7100 22:50:10.422528 sv_algorithm_assistance_LP4_3733
7101 22:50:10.426450 ============ PULL DRAM RESETB DOWN ============
7102 22:50:10.429386 ========== PULL DRAM RESETB DOWN end =========
7103 22:50:10.433033 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7104 22:50:10.436337 ===================================
7105 22:50:10.439526 LPDDR4 DRAM CONFIGURATION
7106 22:50:10.442584 ===================================
7107 22:50:10.445931 EX_ROW_EN[0] = 0x0
7108 22:50:10.446028 EX_ROW_EN[1] = 0x0
7109 22:50:10.449127 LP4Y_EN = 0x0
7110 22:50:10.449195 WORK_FSP = 0x1
7111 22:50:10.452463 WL = 0x5
7112 22:50:10.452549 RL = 0x5
7113 22:50:10.455832 BL = 0x2
7114 22:50:10.455903 RPST = 0x0
7115 22:50:10.459357 RD_PRE = 0x0
7116 22:50:10.459428 WR_PRE = 0x1
7117 22:50:10.462700 WR_PST = 0x1
7118 22:50:10.462782 DBI_WR = 0x0
7119 22:50:10.466149 DBI_RD = 0x0
7120 22:50:10.466218 OTF = 0x1
7121 22:50:10.469215 ===================================
7122 22:50:10.472464 ===================================
7123 22:50:10.476047 ANA top config
7124 22:50:10.479123 ===================================
7125 22:50:10.482618 DLL_ASYNC_EN = 0
7126 22:50:10.482692 ALL_SLAVE_EN = 0
7127 22:50:10.485483 NEW_RANK_MODE = 1
7128 22:50:10.489083 DLL_IDLE_MODE = 1
7129 22:50:10.492175 LP45_APHY_COMB_EN = 1
7130 22:50:10.495451 TX_ODT_DIS = 0
7131 22:50:10.495522 NEW_8X_MODE = 1
7132 22:50:10.499267 ===================================
7133 22:50:10.502374 ===================================
7134 22:50:10.506020 data_rate = 3200
7135 22:50:10.509154 CKR = 1
7136 22:50:10.512021 DQ_P2S_RATIO = 8
7137 22:50:10.515424 ===================================
7138 22:50:10.518863 CA_P2S_RATIO = 8
7139 22:50:10.522297 DQ_CA_OPEN = 0
7140 22:50:10.522373 DQ_SEMI_OPEN = 0
7141 22:50:10.525747 CA_SEMI_OPEN = 0
7142 22:50:10.528659 CA_FULL_RATE = 0
7143 22:50:10.532114 DQ_CKDIV4_EN = 0
7144 22:50:10.535429 CA_CKDIV4_EN = 0
7145 22:50:10.538845 CA_PREDIV_EN = 0
7146 22:50:10.538921 PH8_DLY = 12
7147 22:50:10.542310 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7148 22:50:10.545859 DQ_AAMCK_DIV = 4
7149 22:50:10.549129 CA_AAMCK_DIV = 4
7150 22:50:10.552272 CA_ADMCK_DIV = 4
7151 22:50:10.555258 DQ_TRACK_CA_EN = 0
7152 22:50:10.555333 CA_PICK = 1600
7153 22:50:10.558631 CA_MCKIO = 1600
7154 22:50:10.561997 MCKIO_SEMI = 0
7155 22:50:10.565189 PLL_FREQ = 3068
7156 22:50:10.568857 DQ_UI_PI_RATIO = 32
7157 22:50:10.571705 CA_UI_PI_RATIO = 0
7158 22:50:10.575033 ===================================
7159 22:50:10.578384 ===================================
7160 22:50:10.582309 memory_type:LPDDR4
7161 22:50:10.582399 GP_NUM : 10
7162 22:50:10.585494 SRAM_EN : 1
7163 22:50:10.585588 MD32_EN : 0
7164 22:50:10.588548 ===================================
7165 22:50:10.591823 [ANA_INIT] >>>>>>>>>>>>>>
7166 22:50:10.594989 <<<<<< [CONFIGURE PHASE]: ANA_TX
7167 22:50:10.598502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7168 22:50:10.601725 ===================================
7169 22:50:10.605027 data_rate = 3200,PCW = 0X7600
7170 22:50:10.608264 ===================================
7171 22:50:10.611731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7172 22:50:10.618185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 22:50:10.621230 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 22:50:10.628409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7175 22:50:10.631346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7176 22:50:10.634816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7177 22:50:10.634928 [ANA_INIT] flow start
7178 22:50:10.638277 [ANA_INIT] PLL >>>>>>>>
7179 22:50:10.641062 [ANA_INIT] PLL <<<<<<<<
7180 22:50:10.641150 [ANA_INIT] MIDPI >>>>>>>>
7181 22:50:10.644631 [ANA_INIT] MIDPI <<<<<<<<
7182 22:50:10.648012 [ANA_INIT] DLL >>>>>>>>
7183 22:50:10.648086 [ANA_INIT] DLL <<<<<<<<
7184 22:50:10.651071 [ANA_INIT] flow end
7185 22:50:10.654488 ============ LP4 DIFF to SE enter ============
7186 22:50:10.661266 ============ LP4 DIFF to SE exit ============
7187 22:50:10.661365 [ANA_INIT] <<<<<<<<<<<<<
7188 22:50:10.664743 [Flow] Enable top DCM control >>>>>
7189 22:50:10.667730 [Flow] Enable top DCM control <<<<<
7190 22:50:10.671162 Enable DLL master slave shuffle
7191 22:50:10.677879 ==============================================================
7192 22:50:10.677955 Gating Mode config
7193 22:50:10.684688 ==============================================================
7194 22:50:10.687520 Config description:
7195 22:50:10.694756 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7196 22:50:10.701192 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7197 22:50:10.707743 SELPH_MODE 0: By rank 1: By Phase
7198 22:50:10.714598 ==============================================================
7199 22:50:10.714677 GAT_TRACK_EN = 1
7200 22:50:10.717988 RX_GATING_MODE = 2
7201 22:50:10.721116 RX_GATING_TRACK_MODE = 2
7202 22:50:10.724453 SELPH_MODE = 1
7203 22:50:10.727731 PICG_EARLY_EN = 1
7204 22:50:10.731278 VALID_LAT_VALUE = 1
7205 22:50:10.737606 ==============================================================
7206 22:50:10.741107 Enter into Gating configuration >>>>
7207 22:50:10.744598 Exit from Gating configuration <<<<
7208 22:50:10.747419 Enter into DVFS_PRE_config >>>>>
7209 22:50:10.757773 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7210 22:50:10.760584 Exit from DVFS_PRE_config <<<<<
7211 22:50:10.764086 Enter into PICG configuration >>>>
7212 22:50:10.767554 Exit from PICG configuration <<<<
7213 22:50:10.771018 [RX_INPUT] configuration >>>>>
7214 22:50:10.771114 [RX_INPUT] configuration <<<<<
7215 22:50:10.777139 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7216 22:50:10.784011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7217 22:50:10.787287 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7218 22:50:10.794033 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7219 22:50:10.800451 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 22:50:10.807445 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 22:50:10.810823 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7222 22:50:10.813667 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7223 22:50:10.820383 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7224 22:50:10.823817 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7225 22:50:10.827047 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7226 22:50:10.833765 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7227 22:50:10.837248 ===================================
7228 22:50:10.837321 LPDDR4 DRAM CONFIGURATION
7229 22:50:10.840552 ===================================
7230 22:50:10.844048 EX_ROW_EN[0] = 0x0
7231 22:50:10.844123 EX_ROW_EN[1] = 0x0
7232 22:50:10.847139 LP4Y_EN = 0x0
7233 22:50:10.850265 WORK_FSP = 0x1
7234 22:50:10.850338 WL = 0x5
7235 22:50:10.853871 RL = 0x5
7236 22:50:10.853974 BL = 0x2
7237 22:50:10.857141 RPST = 0x0
7238 22:50:10.857226 RD_PRE = 0x0
7239 22:50:10.860512 WR_PRE = 0x1
7240 22:50:10.860609 WR_PST = 0x1
7241 22:50:10.863357 DBI_WR = 0x0
7242 22:50:10.863426 DBI_RD = 0x0
7243 22:50:10.866950 OTF = 0x1
7244 22:50:10.870343 ===================================
7245 22:50:10.873245 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7246 22:50:10.876749 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7247 22:50:10.883889 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7248 22:50:10.886699 ===================================
7249 22:50:10.886797 LPDDR4 DRAM CONFIGURATION
7250 22:50:10.890279 ===================================
7251 22:50:10.893602 EX_ROW_EN[0] = 0x10
7252 22:50:10.893677 EX_ROW_EN[1] = 0x0
7253 22:50:10.897013 LP4Y_EN = 0x0
7254 22:50:10.897089 WORK_FSP = 0x1
7255 22:50:10.899902 WL = 0x5
7256 22:50:10.903362 RL = 0x5
7257 22:50:10.903432 BL = 0x2
7258 22:50:10.906806 RPST = 0x0
7259 22:50:10.906877 RD_PRE = 0x0
7260 22:50:10.909839 WR_PRE = 0x1
7261 22:50:10.909909 WR_PST = 0x1
7262 22:50:10.913118 DBI_WR = 0x0
7263 22:50:10.913186 DBI_RD = 0x0
7264 22:50:10.916565 OTF = 0x1
7265 22:50:10.919857 ===================================
7266 22:50:10.926631 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7267 22:50:10.926733 ==
7268 22:50:10.929953 Dram Type= 6, Freq= 0, CH_0, rank 0
7269 22:50:10.933082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7270 22:50:10.933179 ==
7271 22:50:10.936718 [Duty_Offset_Calibration]
7272 22:50:10.936819 B0:2 B1:0 CA:3
7273 22:50:10.936962
7274 22:50:10.939716 [DutyScan_Calibration_Flow] k_type=0
7275 22:50:10.950151
7276 22:50:10.950226 ==CLK 0==
7277 22:50:10.953312 Final CLK duty delay cell = 0
7278 22:50:10.956608 [0] MAX Duty = 5062%(X100), DQS PI = 20
7279 22:50:10.959892 [0] MIN Duty = 4907%(X100), DQS PI = 6
7280 22:50:10.959990 [0] AVG Duty = 4984%(X100)
7281 22:50:10.963061
7282 22:50:10.966355 CH0 CLK Duty spec in!! Max-Min= 155%
7283 22:50:10.969762 [DutyScan_Calibration_Flow] ====Done====
7284 22:50:10.969832
7285 22:50:10.973027 [DutyScan_Calibration_Flow] k_type=1
7286 22:50:10.989067
7287 22:50:10.989169 ==DQS 0 ==
7288 22:50:10.992503 Final DQS duty delay cell = 0
7289 22:50:10.995907 [0] MAX Duty = 5062%(X100), DQS PI = 12
7290 22:50:10.998813 [0] MIN Duty = 4875%(X100), DQS PI = 48
7291 22:50:11.002284 [0] AVG Duty = 4968%(X100)
7292 22:50:11.002357
7293 22:50:11.002418 ==DQS 1 ==
7294 22:50:11.005659 Final DQS duty delay cell = -4
7295 22:50:11.008968 [-4] MAX Duty = 4969%(X100), DQS PI = 48
7296 22:50:11.012211 [-4] MIN Duty = 4844%(X100), DQS PI = 10
7297 22:50:11.015732 [-4] AVG Duty = 4906%(X100)
7298 22:50:11.015801
7299 22:50:11.018948 CH0 DQS 0 Duty spec in!! Max-Min= 187%
7300 22:50:11.019055
7301 22:50:11.021946 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7302 22:50:11.025467 [DutyScan_Calibration_Flow] ====Done====
7303 22:50:11.025606
7304 22:50:11.028417 [DutyScan_Calibration_Flow] k_type=3
7305 22:50:11.047446
7306 22:50:11.047524 ==DQM 0 ==
7307 22:50:11.050850 Final DQM duty delay cell = 0
7308 22:50:11.054357 [0] MAX Duty = 5187%(X100), DQS PI = 30
7309 22:50:11.057204 [0] MIN Duty = 4844%(X100), DQS PI = 52
7310 22:50:11.060445 [0] AVG Duty = 5015%(X100)
7311 22:50:11.060516
7312 22:50:11.060578 ==DQM 1 ==
7313 22:50:11.063800 Final DQM duty delay cell = 4
7314 22:50:11.067788 [4] MAX Duty = 5187%(X100), DQS PI = 62
7315 22:50:11.070905 [4] MIN Duty = 5000%(X100), DQS PI = 14
7316 22:50:11.073797 [4] AVG Duty = 5093%(X100)
7317 22:50:11.073871
7318 22:50:11.077145 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7319 22:50:11.077218
7320 22:50:11.080687 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7321 22:50:11.084050 [DutyScan_Calibration_Flow] ====Done====
7322 22:50:11.084121
7323 22:50:11.087026 [DutyScan_Calibration_Flow] k_type=2
7324 22:50:11.103837
7325 22:50:11.103938 ==DQ 0 ==
7326 22:50:11.107169 Final DQ duty delay cell = -4
7327 22:50:11.110475 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7328 22:50:11.113865 [-4] MIN Duty = 4876%(X100), DQS PI = 44
7329 22:50:11.117326 [-4] AVG Duty = 4938%(X100)
7330 22:50:11.117440
7331 22:50:11.117551 ==DQ 1 ==
7332 22:50:11.120586 Final DQ duty delay cell = 0
7333 22:50:11.123831 [0] MAX Duty = 5156%(X100), DQS PI = 60
7334 22:50:11.127027 [0] MIN Duty = 5000%(X100), DQS PI = 16
7335 22:50:11.130576 [0] AVG Duty = 5078%(X100)
7336 22:50:11.130657
7337 22:50:11.133681 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7338 22:50:11.133782
7339 22:50:11.136957 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7340 22:50:11.140268 [DutyScan_Calibration_Flow] ====Done====
7341 22:50:11.140365 ==
7342 22:50:11.143788 Dram Type= 6, Freq= 0, CH_1, rank 0
7343 22:50:11.146938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7344 22:50:11.147017 ==
7345 22:50:11.150807 [Duty_Offset_Calibration]
7346 22:50:11.150881 B0:1 B1:-2 CA:1
7347 22:50:11.150941
7348 22:50:11.153377 [DutyScan_Calibration_Flow] k_type=0
7349 22:50:11.164806
7350 22:50:11.164910 ==CLK 0==
7351 22:50:11.167639 Final CLK duty delay cell = 0
7352 22:50:11.171201 [0] MAX Duty = 5094%(X100), DQS PI = 22
7353 22:50:11.174615 [0] MIN Duty = 4844%(X100), DQS PI = 60
7354 22:50:11.177826 [0] AVG Duty = 4969%(X100)
7355 22:50:11.177897
7356 22:50:11.180875 CH1 CLK Duty spec in!! Max-Min= 250%
7357 22:50:11.184373 [DutyScan_Calibration_Flow] ====Done====
7358 22:50:11.184442
7359 22:50:11.187722 [DutyScan_Calibration_Flow] k_type=1
7360 22:50:11.204000
7361 22:50:11.204102 ==DQS 0 ==
7362 22:50:11.207305 Final DQS duty delay cell = 0
7363 22:50:11.210902 [0] MAX Duty = 5187%(X100), DQS PI = 22
7364 22:50:11.214277 [0] MIN Duty = 5062%(X100), DQS PI = 48
7365 22:50:11.217657 [0] AVG Duty = 5124%(X100)
7366 22:50:11.217753
7367 22:50:11.217842 ==DQS 1 ==
7368 22:50:11.220581 Final DQS duty delay cell = 0
7369 22:50:11.223881 [0] MAX Duty = 5093%(X100), DQS PI = 60
7370 22:50:11.227267 [0] MIN Duty = 4844%(X100), DQS PI = 24
7371 22:50:11.230541 [0] AVG Duty = 4968%(X100)
7372 22:50:11.230616
7373 22:50:11.233822 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7374 22:50:11.233918
7375 22:50:11.237723 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7376 22:50:11.240545 [DutyScan_Calibration_Flow] ====Done====
7377 22:50:11.240617
7378 22:50:11.243874 [DutyScan_Calibration_Flow] k_type=3
7379 22:50:11.261104
7380 22:50:11.261182 ==DQM 0 ==
7381 22:50:11.264918 Final DQM duty delay cell = 0
7382 22:50:11.267912 [0] MAX Duty = 5031%(X100), DQS PI = 24
7383 22:50:11.271343 [0] MIN Duty = 4782%(X100), DQS PI = 54
7384 22:50:11.274370 [0] AVG Duty = 4906%(X100)
7385 22:50:11.274449
7386 22:50:11.274548 ==DQM 1 ==
7387 22:50:11.277792 Final DQM duty delay cell = 0
7388 22:50:11.281186 [0] MAX Duty = 5062%(X100), DQS PI = 34
7389 22:50:11.284077 [0] MIN Duty = 4875%(X100), DQS PI = 24
7390 22:50:11.287507 [0] AVG Duty = 4968%(X100)
7391 22:50:11.287576
7392 22:50:11.291001 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7393 22:50:11.291072
7394 22:50:11.294081 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7395 22:50:11.297794 [DutyScan_Calibration_Flow] ====Done====
7396 22:50:11.297867
7397 22:50:11.300889 [DutyScan_Calibration_Flow] k_type=2
7398 22:50:11.318245
7399 22:50:11.318346 ==DQ 0 ==
7400 22:50:11.321690 Final DQ duty delay cell = 0
7401 22:50:11.324971 [0] MAX Duty = 5093%(X100), DQS PI = 20
7402 22:50:11.328224 [0] MIN Duty = 4938%(X100), DQS PI = 0
7403 22:50:11.328305 [0] AVG Duty = 5015%(X100)
7404 22:50:11.331657
7405 22:50:11.331729 ==DQ 1 ==
7406 22:50:11.334479 Final DQ duty delay cell = 0
7407 22:50:11.337856 [0] MAX Duty = 5125%(X100), DQS PI = 34
7408 22:50:11.341198 [0] MIN Duty = 4938%(X100), DQS PI = 24
7409 22:50:11.341274 [0] AVG Duty = 5031%(X100)
7410 22:50:11.341338
7411 22:50:11.344702 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7412 22:50:11.347948
7413 22:50:11.351189 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7414 22:50:11.354766 [DutyScan_Calibration_Flow] ====Done====
7415 22:50:11.357707 nWR fixed to 30
7416 22:50:11.357815 [ModeRegInit_LP4] CH0 RK0
7417 22:50:11.361122 [ModeRegInit_LP4] CH0 RK1
7418 22:50:11.364470 [ModeRegInit_LP4] CH1 RK0
7419 22:50:11.367758 [ModeRegInit_LP4] CH1 RK1
7420 22:50:11.367858 match AC timing 5
7421 22:50:11.371031 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7422 22:50:11.377575 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7423 22:50:11.380923 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7424 22:50:11.387667 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7425 22:50:11.391187 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7426 22:50:11.391286 [MiockJmeterHQA]
7427 22:50:11.391376
7428 22:50:11.394564 [DramcMiockJmeter] u1RxGatingPI = 0
7429 22:50:11.398042 0 : 4255, 4027
7430 22:50:11.398118 4 : 4252, 4027
7431 22:50:11.398215 8 : 4252, 4027
7432 22:50:11.401281 12 : 4254, 4029
7433 22:50:11.401385 16 : 4252, 4027
7434 22:50:11.404816 20 : 4363, 4137
7435 22:50:11.404913 24 : 4363, 4137
7436 22:50:11.407596 28 : 4253, 4026
7437 22:50:11.407698 32 : 4252, 4026
7438 22:50:11.410961 36 : 4252, 4027
7439 22:50:11.411048 40 : 4253, 4027
7440 22:50:11.411114 44 : 4255, 4029
7441 22:50:11.414317 48 : 4363, 4138
7442 22:50:11.414393 52 : 4252, 4027
7443 22:50:11.417503 56 : 4253, 4026
7444 22:50:11.417644 60 : 4250, 4027
7445 22:50:11.421098 64 : 4253, 4029
7446 22:50:11.421196 68 : 4250, 4027
7447 22:50:11.424236 72 : 4361, 4137
7448 22:50:11.424335 76 : 4361, 4137
7449 22:50:11.424425 80 : 4249, 4027
7450 22:50:11.427366 84 : 4250, 4026
7451 22:50:11.427461 88 : 4250, 4027
7452 22:50:11.430684 92 : 4253, 4027
7453 22:50:11.430753 96 : 4253, 4029
7454 22:50:11.433993 100 : 4360, 4138
7455 22:50:11.434089 104 : 4250, 3993
7456 22:50:11.437809 108 : 4250, 32
7457 22:50:11.437894 112 : 4360, 0
7458 22:50:11.437955 116 : 4361, 0
7459 22:50:11.440751 120 : 4250, 0
7460 22:50:11.440860 124 : 4250, 0
7461 22:50:11.444125 128 : 4250, 0
7462 22:50:11.444235 132 : 4250, 0
7463 22:50:11.444323 136 : 4250, 0
7464 22:50:11.447488 140 : 4250, 0
7465 22:50:11.447588 144 : 4363, 0
7466 22:50:11.447678 148 : 4250, 0
7467 22:50:11.450905 152 : 4250, 0
7468 22:50:11.451004 156 : 4253, 0
7469 22:50:11.454389 160 : 4361, 0
7470 22:50:11.454495 164 : 4250, 0
7471 22:50:11.454588 168 : 4361, 0
7472 22:50:11.457680 172 : 4250, 0
7473 22:50:11.457756 176 : 4360, 0
7474 22:50:11.460817 180 : 4250, 0
7475 22:50:11.460914 184 : 4250, 0
7476 22:50:11.461004 188 : 4250, 0
7477 22:50:11.463991 192 : 4361, 0
7478 22:50:11.464090 196 : 4250, 0
7479 22:50:11.467376 200 : 4250, 0
7480 22:50:11.467447 204 : 4250, 0
7481 22:50:11.467508 208 : 4253, 0
7482 22:50:11.470851 212 : 4250, 0
7483 22:50:11.470922 216 : 4360, 0
7484 22:50:11.470983 220 : 4250, 0
7485 22:50:11.474176 224 : 4250, 0
7486 22:50:11.474275 228 : 4360, 0
7487 22:50:11.477810 232 : 4250, 0
7488 22:50:11.477884 236 : 4250, 488
7489 22:50:11.480850 240 : 4252, 4024
7490 22:50:11.480921 244 : 4250, 4027
7491 22:50:11.480981 248 : 4361, 4137
7492 22:50:11.484180 252 : 4250, 4026
7493 22:50:11.484252 256 : 4250, 4027
7494 22:50:11.487041 260 : 4361, 4137
7495 22:50:11.487108 264 : 4250, 4027
7496 22:50:11.490743 268 : 4250, 4026
7497 22:50:11.490814 272 : 4363, 4139
7498 22:50:11.493984 276 : 4250, 4027
7499 22:50:11.494081 280 : 4250, 4027
7500 22:50:11.497367 284 : 4250, 4026
7501 22:50:11.497463 288 : 4253, 4029
7502 22:50:11.500857 292 : 4250, 4027
7503 22:50:11.500950 296 : 4249, 4027
7504 22:50:11.503799 300 : 4361, 4137
7505 22:50:11.503892 304 : 4250, 4026
7506 22:50:11.503982 308 : 4250, 4027
7507 22:50:11.507238 312 : 4360, 4138
7508 22:50:11.507306 316 : 4249, 4027
7509 22:50:11.510678 320 : 4250, 4027
7510 22:50:11.510760 324 : 4363, 4139
7511 22:50:11.513720 328 : 4250, 4027
7512 22:50:11.513820 332 : 4250, 4027
7513 22:50:11.517147 336 : 4250, 4027
7514 22:50:11.517245 340 : 4253, 4029
7515 22:50:11.520805 344 : 4250, 4027
7516 22:50:11.520910 348 : 4250, 4027
7517 22:50:11.523830 352 : 4361, 4135
7518 22:50:11.523907 356 : 4250, 2874
7519 22:50:11.523971 360 : 4250, 0
7520 22:50:11.527260
7521 22:50:11.527353 MIOCK jitter meter ch=0
7522 22:50:11.527440
7523 22:50:11.530744 1T = (360-108) = 252 dly cells
7524 22:50:11.536919 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7525 22:50:11.536996 ==
7526 22:50:11.540290 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 22:50:11.543637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 22:50:11.543734 ==
7529 22:50:11.550327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7530 22:50:11.553752 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7531 22:50:11.556703 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7532 22:50:11.563319 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7533 22:50:11.573086 [CA 0] Center 44 (14~75) winsize 62
7534 22:50:11.576473 [CA 1] Center 43 (13~74) winsize 62
7535 22:50:11.579467 [CA 2] Center 40 (11~69) winsize 59
7536 22:50:11.582919 [CA 3] Center 39 (10~68) winsize 59
7537 22:50:11.586305 [CA 4] Center 37 (8~67) winsize 60
7538 22:50:11.589950 [CA 5] Center 36 (7~66) winsize 60
7539 22:50:11.590048
7540 22:50:11.593009 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7541 22:50:11.593113
7542 22:50:11.599261 [CATrainingPosCal] consider 1 rank data
7543 22:50:11.599369 u2DelayCellTimex100 = 258/100 ps
7544 22:50:11.605856 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7545 22:50:11.609339 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7546 22:50:11.612889 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7547 22:50:11.615877 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7548 22:50:11.619264 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7549 22:50:11.622619 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7550 22:50:11.622716
7551 22:50:11.626322 CA PerBit enable=1, Macro0, CA PI delay=36
7552 22:50:11.626419
7553 22:50:11.629267 [CBTSetCACLKResult] CA Dly = 36
7554 22:50:11.632227 CS Dly: 11 (0~42)
7555 22:50:11.635555 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7556 22:50:11.639229 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7557 22:50:11.639339 ==
7558 22:50:11.642200 Dram Type= 6, Freq= 0, CH_0, rank 1
7559 22:50:11.648728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 22:50:11.648830 ==
7561 22:50:11.651998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7562 22:50:11.658516 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7563 22:50:11.661952 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7564 22:50:11.668748 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7565 22:50:11.676911 [CA 0] Center 44 (14~75) winsize 62
7566 22:50:11.680325 [CA 1] Center 43 (13~74) winsize 62
7567 22:50:11.683768 [CA 2] Center 39 (10~69) winsize 60
7568 22:50:11.686879 [CA 3] Center 39 (10~68) winsize 59
7569 22:50:11.690093 [CA 4] Center 37 (8~67) winsize 60
7570 22:50:11.693781 [CA 5] Center 36 (7~66) winsize 60
7571 22:50:11.693856
7572 22:50:11.696935 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7573 22:50:11.697032
7574 22:50:11.703405 [CATrainingPosCal] consider 2 rank data
7575 22:50:11.703507 u2DelayCellTimex100 = 258/100 ps
7576 22:50:11.710208 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7577 22:50:11.713199 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7578 22:50:11.716474 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7579 22:50:11.719898 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7580 22:50:11.723355 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7581 22:50:11.726929 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7582 22:50:11.727030
7583 22:50:11.730282 CA PerBit enable=1, Macro0, CA PI delay=36
7584 22:50:11.730383
7585 22:50:11.733590 [CBTSetCACLKResult] CA Dly = 36
7586 22:50:11.736897 CS Dly: 11 (0~43)
7587 22:50:11.740104 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7588 22:50:11.743297 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7589 22:50:11.743424
7590 22:50:11.746499 ----->DramcWriteLeveling(PI) begin...
7591 22:50:11.746575 ==
7592 22:50:11.750049 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 22:50:11.756075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 22:50:11.756183 ==
7595 22:50:11.759786 Write leveling (Byte 0): 37 => 37
7596 22:50:11.763318 Write leveling (Byte 1): 29 => 29
7597 22:50:11.766296 DramcWriteLeveling(PI) end<-----
7598 22:50:11.766378
7599 22:50:11.766440 ==
7600 22:50:11.769594 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 22:50:11.773017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 22:50:11.773088 ==
7603 22:50:11.776173 [Gating] SW mode calibration
7604 22:50:11.783022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7605 22:50:11.789379 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7606 22:50:11.792873 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 22:50:11.796229 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 22:50:11.799458 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 22:50:11.806005 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 22:50:11.809392 1 4 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7611 22:50:11.812746 1 4 20 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
7612 22:50:11.819605 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7613 22:50:11.822884 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 22:50:11.826228 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 22:50:11.832589 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 22:50:11.835815 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 22:50:11.839332 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7618 22:50:11.845725 1 5 16 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7619 22:50:11.849449 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (0 1) (0 0)
7620 22:50:11.852187 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
7621 22:50:11.858812 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 22:50:11.862435 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 22:50:11.865561 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 22:50:11.872132 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 22:50:11.875734 1 6 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7626 22:50:11.878712 1 6 16 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
7627 22:50:11.885368 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7628 22:50:11.888460 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 22:50:11.891848 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 22:50:11.898566 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 22:50:11.902052 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 22:50:11.905061 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 22:50:11.911881 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7634 22:50:11.914907 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7635 22:50:11.918316 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7636 22:50:11.925230 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7637 22:50:11.928721 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7638 22:50:11.931572 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 22:50:11.938594 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 22:50:11.941405 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 22:50:11.945073 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 22:50:11.951945 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 22:50:11.954957 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 22:50:11.958303 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 22:50:11.965288 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 22:50:11.968557 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 22:50:11.971802 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 22:50:11.978389 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 22:50:11.981497 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 22:50:11.984595 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7651 22:50:11.991392 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7652 22:50:11.991493 Total UI for P1: 0, mck2ui 16
7653 22:50:11.997760 best dqsien dly found for B0: ( 1, 9, 16)
7654 22:50:12.001227 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7655 22:50:12.004304 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 22:50:12.007739 Total UI for P1: 0, mck2ui 16
7657 22:50:12.011232 best dqsien dly found for B1: ( 1, 9, 24)
7658 22:50:12.014745 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7659 22:50:12.018236 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7660 22:50:12.018332
7661 22:50:12.021007 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7662 22:50:12.027838 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7663 22:50:12.027937 [Gating] SW calibration Done
7664 22:50:12.031257 ==
7665 22:50:12.031329 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 22:50:12.037722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 22:50:12.037798 ==
7668 22:50:12.037859 RX Vref Scan: 0
7669 22:50:12.037919
7670 22:50:12.041164 RX Vref 0 -> 0, step: 1
7671 22:50:12.041261
7672 22:50:12.044188 RX Delay 0 -> 252, step: 8
7673 22:50:12.047392 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7674 22:50:12.050729 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7675 22:50:12.054229 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7676 22:50:12.060669 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7677 22:50:12.064092 iDelay=192, Bit 4, Center 131 (80 ~ 183) 104
7678 22:50:12.067432 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7679 22:50:12.070739 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7680 22:50:12.074009 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7681 22:50:12.080953 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7682 22:50:12.084433 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7683 22:50:12.087519 iDelay=192, Bit 10, Center 119 (64 ~ 175) 112
7684 22:50:12.090845 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7685 22:50:12.093875 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7686 22:50:12.100357 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7687 22:50:12.103952 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7688 22:50:12.107059 iDelay=192, Bit 15, Center 127 (72 ~ 183) 112
7689 22:50:12.107159 ==
7690 22:50:12.110295 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 22:50:12.113846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 22:50:12.117143 ==
7693 22:50:12.117251 DQS Delay:
7694 22:50:12.117347 DQS0 = 0, DQS1 = 0
7695 22:50:12.120126 DQM Delay:
7696 22:50:12.120224 DQM0 = 128, DQM1 = 122
7697 22:50:12.123580 DQ Delay:
7698 22:50:12.126967 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7699 22:50:12.130367 DQ4 =131, DQ5 =115, DQ6 =135, DQ7 =139
7700 22:50:12.134046 DQ8 =115, DQ9 =111, DQ10 =119, DQ11 =115
7701 22:50:12.136841 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7702 22:50:12.136913
7703 22:50:12.136973
7704 22:50:12.137039 ==
7705 22:50:12.140229 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 22:50:12.143600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 22:50:12.143694 ==
7708 22:50:12.147043
7709 22:50:12.147136
7710 22:50:12.147232 TX Vref Scan disable
7711 22:50:12.150421 == TX Byte 0 ==
7712 22:50:12.153881 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7713 22:50:12.157251 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7714 22:50:12.160135 == TX Byte 1 ==
7715 22:50:12.163397 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7716 22:50:12.167178 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7717 22:50:12.167272 ==
7718 22:50:12.169940 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 22:50:12.176590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 22:50:12.176688 ==
7721 22:50:12.190633
7722 22:50:12.194054 TX Vref early break, caculate TX vref
7723 22:50:12.197447 TX Vref=16, minBit 9, minWin=20, winSum=360
7724 22:50:12.200785 TX Vref=18, minBit 8, minWin=21, winSum=374
7725 22:50:12.204128 TX Vref=20, minBit 8, minWin=22, winSum=385
7726 22:50:12.207058 TX Vref=22, minBit 8, minWin=23, winSum=389
7727 22:50:12.210420 TX Vref=24, minBit 8, minWin=23, winSum=394
7728 22:50:12.216980 TX Vref=26, minBit 8, minWin=23, winSum=403
7729 22:50:12.220324 TX Vref=28, minBit 8, minWin=24, winSum=404
7730 22:50:12.223793 TX Vref=30, minBit 12, minWin=23, winSum=398
7731 22:50:12.227265 TX Vref=32, minBit 8, minWin=23, winSum=390
7732 22:50:12.230040 TX Vref=34, minBit 9, minWin=22, winSum=386
7733 22:50:12.233460 TX Vref=36, minBit 8, minWin=21, winSum=373
7734 22:50:12.240271 [TxChooseVref] Worse bit 8, Min win 24, Win sum 404, Final Vref 28
7735 22:50:12.240379
7736 22:50:12.243768 Final TX Range 0 Vref 28
7737 22:50:12.243863
7738 22:50:12.243950 ==
7739 22:50:12.247172 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 22:50:12.250066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 22:50:12.250150 ==
7742 22:50:12.253703
7743 22:50:12.253799
7744 22:50:12.253885 TX Vref Scan disable
7745 22:50:12.260295 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7746 22:50:12.260397 == TX Byte 0 ==
7747 22:50:12.263279 u2DelayCellOfst[0]=15 cells (4 PI)
7748 22:50:12.266758 u2DelayCellOfst[1]=18 cells (5 PI)
7749 22:50:12.269751 u2DelayCellOfst[2]=15 cells (4 PI)
7750 22:50:12.273137 u2DelayCellOfst[3]=15 cells (4 PI)
7751 22:50:12.276465 u2DelayCellOfst[4]=7 cells (2 PI)
7752 22:50:12.280082 u2DelayCellOfst[5]=0 cells (0 PI)
7753 22:50:12.283278 u2DelayCellOfst[6]=18 cells (5 PI)
7754 22:50:12.286431 u2DelayCellOfst[7]=18 cells (5 PI)
7755 22:50:12.289852 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7756 22:50:12.293366 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7757 22:50:12.296305 == TX Byte 1 ==
7758 22:50:12.299677 u2DelayCellOfst[8]=0 cells (0 PI)
7759 22:50:12.303057 u2DelayCellOfst[9]=3 cells (1 PI)
7760 22:50:12.306602 u2DelayCellOfst[10]=7 cells (2 PI)
7761 22:50:12.309974 u2DelayCellOfst[11]=7 cells (2 PI)
7762 22:50:12.312821 u2DelayCellOfst[12]=15 cells (4 PI)
7763 22:50:12.312918 u2DelayCellOfst[13]=11 cells (3 PI)
7764 22:50:12.316156 u2DelayCellOfst[14]=18 cells (5 PI)
7765 22:50:12.319818 u2DelayCellOfst[15]=11 cells (3 PI)
7766 22:50:12.326326 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7767 22:50:12.329806 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7768 22:50:12.329900 DramC Write-DBI on
7769 22:50:12.333007 ==
7770 22:50:12.336592 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 22:50:12.339598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 22:50:12.339700 ==
7773 22:50:12.339799
7774 22:50:12.339915
7775 22:50:12.342582 TX Vref Scan disable
7776 22:50:12.342665 == TX Byte 0 ==
7777 22:50:12.349445 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7778 22:50:12.349569 == TX Byte 1 ==
7779 22:50:12.352588 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7780 22:50:12.356170 DramC Write-DBI off
7781 22:50:12.356281
7782 22:50:12.356371 [DATLAT]
7783 22:50:12.359469 Freq=1600, CH0 RK0
7784 22:50:12.359554
7785 22:50:12.359617 DATLAT Default: 0xf
7786 22:50:12.362629 0, 0xFFFF, sum = 0
7787 22:50:12.362738 1, 0xFFFF, sum = 0
7788 22:50:12.366205 2, 0xFFFF, sum = 0
7789 22:50:12.366279 3, 0xFFFF, sum = 0
7790 22:50:12.369440 4, 0xFFFF, sum = 0
7791 22:50:12.372931 5, 0xFFFF, sum = 0
7792 22:50:12.373029 6, 0xFFFF, sum = 0
7793 22:50:12.375739 7, 0xFFFF, sum = 0
7794 22:50:12.375846 8, 0xFFFF, sum = 0
7795 22:50:12.379227 9, 0xFFFF, sum = 0
7796 22:50:12.379326 10, 0xFFFF, sum = 0
7797 22:50:12.382685 11, 0xFFFF, sum = 0
7798 22:50:12.382759 12, 0xFFFF, sum = 0
7799 22:50:12.386252 13, 0xCFFF, sum = 0
7800 22:50:12.386324 14, 0x0, sum = 1
7801 22:50:12.389546 15, 0x0, sum = 2
7802 22:50:12.389653 16, 0x0, sum = 3
7803 22:50:12.392699 17, 0x0, sum = 4
7804 22:50:12.392804 best_step = 15
7805 22:50:12.392893
7806 22:50:12.392978 ==
7807 22:50:12.395681 Dram Type= 6, Freq= 0, CH_0, rank 0
7808 22:50:12.399360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7809 22:50:12.399433 ==
7810 22:50:12.402711 RX Vref Scan: 1
7811 22:50:12.402785
7812 22:50:12.406074 Set Vref Range= 24 -> 127
7813 22:50:12.406172
7814 22:50:12.406263 RX Vref 24 -> 127, step: 1
7815 22:50:12.408911
7816 22:50:12.408982 RX Delay 11 -> 252, step: 4
7817 22:50:12.409041
7818 22:50:12.412353 Set Vref, RX VrefLevel [Byte0]: 24
7819 22:50:12.415685 [Byte1]: 24
7820 22:50:12.419254
7821 22:50:12.419351 Set Vref, RX VrefLevel [Byte0]: 25
7822 22:50:12.422568 [Byte1]: 25
7823 22:50:12.426758
7824 22:50:12.426845 Set Vref, RX VrefLevel [Byte0]: 26
7825 22:50:12.430228 [Byte1]: 26
7826 22:50:12.434566
7827 22:50:12.434665 Set Vref, RX VrefLevel [Byte0]: 27
7828 22:50:12.438023 [Byte1]: 27
7829 22:50:12.442462
7830 22:50:12.442563 Set Vref, RX VrefLevel [Byte0]: 28
7831 22:50:12.445159 [Byte1]: 28
7832 22:50:12.449540
7833 22:50:12.449652 Set Vref, RX VrefLevel [Byte0]: 29
7834 22:50:12.452941 [Byte1]: 29
7835 22:50:12.457206
7836 22:50:12.457306 Set Vref, RX VrefLevel [Byte0]: 30
7837 22:50:12.461082 [Byte1]: 30
7838 22:50:12.464697
7839 22:50:12.464782 Set Vref, RX VrefLevel [Byte0]: 31
7840 22:50:12.468137 [Byte1]: 31
7841 22:50:12.472437
7842 22:50:12.472514 Set Vref, RX VrefLevel [Byte0]: 32
7843 22:50:12.475665 [Byte1]: 32
7844 22:50:12.480397
7845 22:50:12.480493 Set Vref, RX VrefLevel [Byte0]: 33
7846 22:50:12.483238 [Byte1]: 33
7847 22:50:12.487790
7848 22:50:12.487891 Set Vref, RX VrefLevel [Byte0]: 34
7849 22:50:12.491193 [Byte1]: 34
7850 22:50:12.495181
7851 22:50:12.495279 Set Vref, RX VrefLevel [Byte0]: 35
7852 22:50:12.498556 [Byte1]: 35
7853 22:50:12.502870
7854 22:50:12.502973 Set Vref, RX VrefLevel [Byte0]: 36
7855 22:50:12.506145 [Byte1]: 36
7856 22:50:12.510497
7857 22:50:12.510594 Set Vref, RX VrefLevel [Byte0]: 37
7858 22:50:12.513719 [Byte1]: 37
7859 22:50:12.518076
7860 22:50:12.518217 Set Vref, RX VrefLevel [Byte0]: 38
7861 22:50:12.521321 [Byte1]: 38
7862 22:50:12.526032
7863 22:50:12.526102 Set Vref, RX VrefLevel [Byte0]: 39
7864 22:50:12.529406 [Byte1]: 39
7865 22:50:12.533338
7866 22:50:12.533432 Set Vref, RX VrefLevel [Byte0]: 40
7867 22:50:12.536566 [Byte1]: 40
7868 22:50:12.541037
7869 22:50:12.541131 Set Vref, RX VrefLevel [Byte0]: 41
7870 22:50:12.544194 [Byte1]: 41
7871 22:50:12.548577
7872 22:50:12.548676 Set Vref, RX VrefLevel [Byte0]: 42
7873 22:50:12.551804 [Byte1]: 42
7874 22:50:12.556371
7875 22:50:12.556479 Set Vref, RX VrefLevel [Byte0]: 43
7876 22:50:12.559357 [Byte1]: 43
7877 22:50:12.563897
7878 22:50:12.563992 Set Vref, RX VrefLevel [Byte0]: 44
7879 22:50:12.567453 [Byte1]: 44
7880 22:50:12.571478
7881 22:50:12.571565 Set Vref, RX VrefLevel [Byte0]: 45
7882 22:50:12.574967 [Byte1]: 45
7883 22:50:12.579314
7884 22:50:12.579383 Set Vref, RX VrefLevel [Byte0]: 46
7885 22:50:12.582455 [Byte1]: 46
7886 22:50:12.586997
7887 22:50:12.587074 Set Vref, RX VrefLevel [Byte0]: 47
7888 22:50:12.590113 [Byte1]: 47
7889 22:50:12.594326
7890 22:50:12.594435 Set Vref, RX VrefLevel [Byte0]: 48
7891 22:50:12.597430 [Byte1]: 48
7892 22:50:12.602087
7893 22:50:12.602194 Set Vref, RX VrefLevel [Byte0]: 49
7894 22:50:12.605288 [Byte1]: 49
7895 22:50:12.609620
7896 22:50:12.609690 Set Vref, RX VrefLevel [Byte0]: 50
7897 22:50:12.613023 [Byte1]: 50
7898 22:50:12.617079
7899 22:50:12.617183 Set Vref, RX VrefLevel [Byte0]: 51
7900 22:50:12.620507 [Byte1]: 51
7901 22:50:12.624747
7902 22:50:12.624844 Set Vref, RX VrefLevel [Byte0]: 52
7903 22:50:12.628296 [Byte1]: 52
7904 22:50:12.632287
7905 22:50:12.632386 Set Vref, RX VrefLevel [Byte0]: 53
7906 22:50:12.635694 [Byte1]: 53
7907 22:50:12.640217
7908 22:50:12.640325 Set Vref, RX VrefLevel [Byte0]: 54
7909 22:50:12.643425 [Byte1]: 54
7910 22:50:12.647566
7911 22:50:12.647661 Set Vref, RX VrefLevel [Byte0]: 55
7912 22:50:12.650759 [Byte1]: 55
7913 22:50:12.655158
7914 22:50:12.655271 Set Vref, RX VrefLevel [Byte0]: 56
7915 22:50:12.658479 [Byte1]: 56
7916 22:50:12.662917
7917 22:50:12.663020 Set Vref, RX VrefLevel [Byte0]: 57
7918 22:50:12.666318 [Byte1]: 57
7919 22:50:12.670397
7920 22:50:12.670500 Set Vref, RX VrefLevel [Byte0]: 58
7921 22:50:12.673878 [Byte1]: 58
7922 22:50:12.678415
7923 22:50:12.678518 Set Vref, RX VrefLevel [Byte0]: 59
7924 22:50:12.681900 [Byte1]: 59
7925 22:50:12.685747
7926 22:50:12.685863 Set Vref, RX VrefLevel [Byte0]: 60
7927 22:50:12.689154 [Byte1]: 60
7928 22:50:12.693377
7929 22:50:12.693478 Set Vref, RX VrefLevel [Byte0]: 61
7930 22:50:12.696576 [Byte1]: 61
7931 22:50:12.700993
7932 22:50:12.701179 Set Vref, RX VrefLevel [Byte0]: 62
7933 22:50:12.704349 [Byte1]: 62
7934 22:50:12.708310
7935 22:50:12.708412 Set Vref, RX VrefLevel [Byte0]: 63
7936 22:50:12.711710 [Byte1]: 63
7937 22:50:12.715938
7938 22:50:12.716038 Set Vref, RX VrefLevel [Byte0]: 64
7939 22:50:12.719222 [Byte1]: 64
7940 22:50:12.723799
7941 22:50:12.723873 Set Vref, RX VrefLevel [Byte0]: 65
7942 22:50:12.727314 [Byte1]: 65
7943 22:50:12.731364
7944 22:50:12.731459 Set Vref, RX VrefLevel [Byte0]: 66
7945 22:50:12.734612 [Byte1]: 66
7946 22:50:12.739139
7947 22:50:12.739240 Set Vref, RX VrefLevel [Byte0]: 67
7948 22:50:12.742537 [Byte1]: 67
7949 22:50:12.746415
7950 22:50:12.746514 Set Vref, RX VrefLevel [Byte0]: 68
7951 22:50:12.749935 [Byte1]: 68
7952 22:50:12.754296
7953 22:50:12.754370 Set Vref, RX VrefLevel [Byte0]: 69
7954 22:50:12.757761 [Byte1]: 69
7955 22:50:12.761669
7956 22:50:12.761777 Set Vref, RX VrefLevel [Byte0]: 70
7957 22:50:12.765223 [Byte1]: 70
7958 22:50:12.769601
7959 22:50:12.769706 Set Vref, RX VrefLevel [Byte0]: 71
7960 22:50:12.772966 [Byte1]: 71
7961 22:50:12.776959
7962 22:50:12.777058 Set Vref, RX VrefLevel [Byte0]: 72
7963 22:50:12.780437 [Byte1]: 72
7964 22:50:12.785004
7965 22:50:12.785103 Set Vref, RX VrefLevel [Byte0]: 73
7966 22:50:12.787887 [Byte1]: 73
7967 22:50:12.792275
7968 22:50:12.792371 Set Vref, RX VrefLevel [Byte0]: 74
7969 22:50:12.795798 [Byte1]: 74
7970 22:50:12.800238
7971 22:50:12.800340 Set Vref, RX VrefLevel [Byte0]: 75
7972 22:50:12.804501 [Byte1]: 75
7973 22:50:12.807411
7974 22:50:12.807480 Set Vref, RX VrefLevel [Byte0]: 76
7975 22:50:12.810613 [Byte1]: 76
7976 22:50:12.815399
7977 22:50:12.815477 Set Vref, RX VrefLevel [Byte0]: 77
7978 22:50:12.818534 [Byte1]: 77
7979 22:50:12.822841
7980 22:50:12.822910 Set Vref, RX VrefLevel [Byte0]: 78
7981 22:50:12.826249 [Byte1]: 78
7982 22:50:12.830157
7983 22:50:12.830258 Final RX Vref Byte 0 = 62 to rank0
7984 22:50:12.833538 Final RX Vref Byte 1 = 61 to rank0
7985 22:50:12.837029 Final RX Vref Byte 0 = 62 to rank1
7986 22:50:12.840578 Final RX Vref Byte 1 = 61 to rank1==
7987 22:50:12.843390 Dram Type= 6, Freq= 0, CH_0, rank 0
7988 22:50:12.850357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7989 22:50:12.850435 ==
7990 22:50:12.850520 DQS Delay:
7991 22:50:12.850609 DQS0 = 0, DQS1 = 0
7992 22:50:12.853358 DQM Delay:
7993 22:50:12.853452 DQM0 = 125, DQM1 = 119
7994 22:50:12.856707 DQ Delay:
7995 22:50:12.859981 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7996 22:50:12.863445 DQ4 =124, DQ5 =114, DQ6 =132, DQ7 =138
7997 22:50:12.866897 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7998 22:50:12.870345 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7999 22:50:12.870447
8000 22:50:12.870537
8001 22:50:12.870623
8002 22:50:12.873877 [DramC_TX_OE_Calibration] TA2
8003 22:50:12.876488 Original DQ_B0 (3 6) =30, OEN = 27
8004 22:50:12.879743 Original DQ_B1 (3 6) =30, OEN = 27
8005 22:50:12.883313 24, 0x0, End_B0=24 End_B1=24
8006 22:50:12.883419 25, 0x0, End_B0=25 End_B1=25
8007 22:50:12.886840 26, 0x0, End_B0=26 End_B1=26
8008 22:50:12.890237 27, 0x0, End_B0=27 End_B1=27
8009 22:50:12.893128 28, 0x0, End_B0=28 End_B1=28
8010 22:50:12.897010 29, 0x0, End_B0=29 End_B1=29
8011 22:50:12.897104 30, 0x0, End_B0=30 End_B1=30
8012 22:50:12.899759 31, 0x4141, End_B0=30 End_B1=30
8013 22:50:12.903038 Byte0 end_step=30 best_step=27
8014 22:50:12.906519 Byte1 end_step=30 best_step=27
8015 22:50:12.909930 Byte0 TX OE(2T, 0.5T) = (3, 3)
8016 22:50:12.913222 Byte1 TX OE(2T, 0.5T) = (3, 3)
8017 22:50:12.913326
8018 22:50:12.913418
8019 22:50:12.919951 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8020 22:50:12.922988 CH0 RK0: MR19=303, MR18=1211
8021 22:50:12.930010 CH0_RK0: MR19=0x303, MR18=0x1211, DQSOSC=400, MR23=63, INC=23, DEC=15
8022 22:50:12.930111
8023 22:50:12.932915 ----->DramcWriteLeveling(PI) begin...
8024 22:50:12.933017 ==
8025 22:50:12.936289 Dram Type= 6, Freq= 0, CH_0, rank 1
8026 22:50:12.939694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8027 22:50:12.939824 ==
8028 22:50:12.942978 Write leveling (Byte 0): 33 => 33
8029 22:50:12.946413 Write leveling (Byte 1): 28 => 28
8030 22:50:12.949845 DramcWriteLeveling(PI) end<-----
8031 22:50:12.949916
8032 22:50:12.949999 ==
8033 22:50:12.953212 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 22:50:12.956226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 22:50:12.956348 ==
8036 22:50:12.959858 [Gating] SW mode calibration
8037 22:50:12.966097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8038 22:50:12.973007 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8039 22:50:12.976796 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 22:50:12.982986 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 22:50:12.986352 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 22:50:12.989578 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8043 22:50:12.996051 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (1 1) (1 1)
8044 22:50:12.999300 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 22:50:13.002581 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 22:50:13.006277 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 22:50:13.012732 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 22:50:13.016164 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 22:50:13.019598 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8050 22:50:13.026001 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
8051 22:50:13.029066 1 5 16 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8052 22:50:13.032730 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8053 22:50:13.039256 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8054 22:50:13.042512 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 22:50:13.045880 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 22:50:13.052313 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 22:50:13.055756 1 6 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8058 22:50:13.059256 1 6 12 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
8059 22:50:13.066088 1 6 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8060 22:50:13.068969 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8061 22:50:13.072302 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 22:50:13.078949 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 22:50:13.082347 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 22:50:13.085811 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 22:50:13.092192 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 22:50:13.095701 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8067 22:50:13.099098 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8068 22:50:13.105313 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8069 22:50:13.108528 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 22:50:13.111964 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 22:50:13.118387 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 22:50:13.122292 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 22:50:13.125161 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 22:50:13.131660 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 22:50:13.135131 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 22:50:13.138063 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 22:50:13.144958 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 22:50:13.148549 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 22:50:13.151419 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 22:50:13.158255 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 22:50:13.161676 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8082 22:50:13.164802 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8083 22:50:13.171459 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8084 22:50:13.171562 Total UI for P1: 0, mck2ui 16
8085 22:50:13.177801 best dqsien dly found for B0: ( 1, 9, 10)
8086 22:50:13.181331 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 22:50:13.184679 Total UI for P1: 0, mck2ui 16
8088 22:50:13.187972 best dqsien dly found for B1: ( 1, 9, 16)
8089 22:50:13.191101 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8090 22:50:13.194681 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8091 22:50:13.194794
8092 22:50:13.197796 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8093 22:50:13.201132 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8094 22:50:13.204535 [Gating] SW calibration Done
8095 22:50:13.204631 ==
8096 22:50:13.207606 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 22:50:13.214153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 22:50:13.214226 ==
8099 22:50:13.214291 RX Vref Scan: 0
8100 22:50:13.214350
8101 22:50:13.217239 RX Vref 0 -> 0, step: 1
8102 22:50:13.217346
8103 22:50:13.220591 RX Delay 0 -> 252, step: 8
8104 22:50:13.224522 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8105 22:50:13.227803 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8106 22:50:13.230705 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8107 22:50:13.233961 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8108 22:50:13.240756 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8109 22:50:13.243806 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8110 22:50:13.247132 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8111 22:50:13.250569 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8112 22:50:13.254034 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8113 22:50:13.260371 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8114 22:50:13.263816 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8115 22:50:13.267057 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8116 22:50:13.270244 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8117 22:50:13.276804 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8118 22:50:13.280203 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8119 22:50:13.283470 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8120 22:50:13.283566 ==
8121 22:50:13.286746 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 22:50:13.290655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 22:50:13.290759 ==
8124 22:50:13.293431 DQS Delay:
8125 22:50:13.293567 DQS0 = 0, DQS1 = 0
8126 22:50:13.296871 DQM Delay:
8127 22:50:13.296972 DQM0 = 128, DQM1 = 122
8128 22:50:13.297061 DQ Delay:
8129 22:50:13.300386 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8130 22:50:13.307098 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8131 22:50:13.310462 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8132 22:50:13.313728 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8133 22:50:13.313798
8134 22:50:13.313859
8135 22:50:13.313938 ==
8136 22:50:13.316636 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 22:50:13.320077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 22:50:13.320187 ==
8139 22:50:13.320275
8140 22:50:13.320360
8141 22:50:13.323407 TX Vref Scan disable
8142 22:50:13.326605 == TX Byte 0 ==
8143 22:50:13.330122 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8144 22:50:13.333672 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8145 22:50:13.336634 == TX Byte 1 ==
8146 22:50:13.339711 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8147 22:50:13.342947 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8148 22:50:13.343035 ==
8149 22:50:13.346370 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 22:50:13.352751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 22:50:13.352869 ==
8152 22:50:13.365947
8153 22:50:13.369410 TX Vref early break, caculate TX vref
8154 22:50:13.372308 TX Vref=16, minBit 9, minWin=21, winSum=360
8155 22:50:13.376192 TX Vref=18, minBit 9, minWin=21, winSum=367
8156 22:50:13.379108 TX Vref=20, minBit 8, minWin=22, winSum=374
8157 22:50:13.382301 TX Vref=22, minBit 0, minWin=23, winSum=384
8158 22:50:13.385878 TX Vref=24, minBit 8, minWin=23, winSum=393
8159 22:50:13.392415 TX Vref=26, minBit 0, minWin=24, winSum=402
8160 22:50:13.395569 TX Vref=28, minBit 8, minWin=24, winSum=401
8161 22:50:13.398865 TX Vref=30, minBit 8, minWin=22, winSum=397
8162 22:50:13.402133 TX Vref=32, minBit 8, minWin=22, winSum=393
8163 22:50:13.406081 TX Vref=34, minBit 8, minWin=22, winSum=382
8164 22:50:13.409021 TX Vref=36, minBit 8, minWin=22, winSum=375
8165 22:50:13.415937 [TxChooseVref] Worse bit 0, Min win 24, Win sum 402, Final Vref 26
8166 22:50:13.416073
8167 22:50:13.419139 Final TX Range 0 Vref 26
8168 22:50:13.419210
8169 22:50:13.419269 ==
8170 22:50:13.422671 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 22:50:13.425667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 22:50:13.425744 ==
8173 22:50:13.425809
8174 22:50:13.425866
8175 22:50:13.429090 TX Vref Scan disable
8176 22:50:13.435157 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8177 22:50:13.435258 == TX Byte 0 ==
8178 22:50:13.438875 u2DelayCellOfst[0]=15 cells (4 PI)
8179 22:50:13.441988 u2DelayCellOfst[1]=22 cells (6 PI)
8180 22:50:13.445405 u2DelayCellOfst[2]=15 cells (4 PI)
8181 22:50:13.448611 u2DelayCellOfst[3]=15 cells (4 PI)
8182 22:50:13.451855 u2DelayCellOfst[4]=11 cells (3 PI)
8183 22:50:13.455624 u2DelayCellOfst[5]=0 cells (0 PI)
8184 22:50:13.458483 u2DelayCellOfst[6]=22 cells (6 PI)
8185 22:50:13.462008 u2DelayCellOfst[7]=22 cells (6 PI)
8186 22:50:13.464956 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8187 22:50:13.468198 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8188 22:50:13.471736 == TX Byte 1 ==
8189 22:50:13.475425 u2DelayCellOfst[8]=0 cells (0 PI)
8190 22:50:13.478120 u2DelayCellOfst[9]=3 cells (1 PI)
8191 22:50:13.481748 u2DelayCellOfst[10]=7 cells (2 PI)
8192 22:50:13.485014 u2DelayCellOfst[11]=7 cells (2 PI)
8193 22:50:13.487961 u2DelayCellOfst[12]=15 cells (4 PI)
8194 22:50:13.491600 u2DelayCellOfst[13]=15 cells (4 PI)
8195 22:50:13.491711 u2DelayCellOfst[14]=18 cells (5 PI)
8196 22:50:13.494837 u2DelayCellOfst[15]=15 cells (4 PI)
8197 22:50:13.501167 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8198 22:50:13.504426 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8199 22:50:13.508105 DramC Write-DBI on
8200 22:50:13.508204 ==
8201 22:50:13.511081 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 22:50:13.514784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 22:50:13.514861 ==
8204 22:50:13.514924
8205 22:50:13.514981
8206 22:50:13.517840 TX Vref Scan disable
8207 22:50:13.517984 == TX Byte 0 ==
8208 22:50:13.524341 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8209 22:50:13.524466 == TX Byte 1 ==
8210 22:50:13.528104 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8211 22:50:13.531320 DramC Write-DBI off
8212 22:50:13.531391
8213 22:50:13.531451 [DATLAT]
8214 22:50:13.534588 Freq=1600, CH0 RK1
8215 22:50:13.534684
8216 22:50:13.534773 DATLAT Default: 0xf
8217 22:50:13.537751 0, 0xFFFF, sum = 0
8218 22:50:13.537847 1, 0xFFFF, sum = 0
8219 22:50:13.541039 2, 0xFFFF, sum = 0
8220 22:50:13.541143 3, 0xFFFF, sum = 0
8221 22:50:13.544288 4, 0xFFFF, sum = 0
8222 22:50:13.547591 5, 0xFFFF, sum = 0
8223 22:50:13.547740 6, 0xFFFF, sum = 0
8224 22:50:13.550766 7, 0xFFFF, sum = 0
8225 22:50:13.550869 8, 0xFFFF, sum = 0
8226 22:50:13.554100 9, 0xFFFF, sum = 0
8227 22:50:13.554203 10, 0xFFFF, sum = 0
8228 22:50:13.557703 11, 0xFFFF, sum = 0
8229 22:50:13.557820 12, 0xFFFF, sum = 0
8230 22:50:13.560919 13, 0xCFFF, sum = 0
8231 22:50:13.561028 14, 0x0, sum = 1
8232 22:50:13.564402 15, 0x0, sum = 2
8233 22:50:13.564500 16, 0x0, sum = 3
8234 22:50:13.567962 17, 0x0, sum = 4
8235 22:50:13.568065 best_step = 15
8236 22:50:13.568154
8237 22:50:13.568249 ==
8238 22:50:13.570790 Dram Type= 6, Freq= 0, CH_0, rank 1
8239 22:50:13.574148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8240 22:50:13.577621 ==
8241 22:50:13.577725 RX Vref Scan: 0
8242 22:50:13.577815
8243 22:50:13.581088 RX Vref 0 -> 0, step: 1
8244 22:50:13.581186
8245 22:50:13.581274 RX Delay 3 -> 252, step: 4
8246 22:50:13.588031 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8247 22:50:13.591391 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8248 22:50:13.594782 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8249 22:50:13.598036 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8250 22:50:13.604720 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8251 22:50:13.608282 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8252 22:50:13.611769 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8253 22:50:13.614429 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8254 22:50:13.617743 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8255 22:50:13.621033 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8256 22:50:13.627836 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8257 22:50:13.631363 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8258 22:50:13.634287 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8259 22:50:13.637883 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8260 22:50:13.645053 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8261 22:50:13.647835 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8262 22:50:13.647939 ==
8263 22:50:13.651293 Dram Type= 6, Freq= 0, CH_0, rank 1
8264 22:50:13.654075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 22:50:13.654179 ==
8266 22:50:13.657965 DQS Delay:
8267 22:50:13.658075 DQS0 = 0, DQS1 = 0
8268 22:50:13.658171 DQM Delay:
8269 22:50:13.661163 DQM0 = 124, DQM1 = 118
8270 22:50:13.661303 DQ Delay:
8271 22:50:13.664379 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8272 22:50:13.667609 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8273 22:50:13.671053 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8274 22:50:13.677744 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8275 22:50:13.677841
8276 22:50:13.677908
8277 22:50:13.677969
8278 22:50:13.680562 [DramC_TX_OE_Calibration] TA2
8279 22:50:13.684046 Original DQ_B0 (3 6) =30, OEN = 27
8280 22:50:13.684240 Original DQ_B1 (3 6) =30, OEN = 27
8281 22:50:13.687599 24, 0x0, End_B0=24 End_B1=24
8282 22:50:13.691016 25, 0x0, End_B0=25 End_B1=25
8283 22:50:13.693946 26, 0x0, End_B0=26 End_B1=26
8284 22:50:13.697314 27, 0x0, End_B0=27 End_B1=27
8285 22:50:13.697411 28, 0x0, End_B0=28 End_B1=28
8286 22:50:13.700816 29, 0x0, End_B0=29 End_B1=29
8287 22:50:13.703847 30, 0x0, End_B0=30 End_B1=30
8288 22:50:13.707153 31, 0x4545, End_B0=30 End_B1=30
8289 22:50:13.710521 Byte0 end_step=30 best_step=27
8290 22:50:13.710625 Byte1 end_step=30 best_step=27
8291 22:50:13.714036 Byte0 TX OE(2T, 0.5T) = (3, 3)
8292 22:50:13.717010 Byte1 TX OE(2T, 0.5T) = (3, 3)
8293 22:50:13.717115
8294 22:50:13.717203
8295 22:50:13.727005 [DQSOSCAuto] RK1, (LSB)MR18= 0x2512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8296 22:50:13.727104 CH0 RK1: MR19=303, MR18=2512
8297 22:50:13.733864 CH0_RK1: MR19=0x303, MR18=0x2512, DQSOSC=391, MR23=63, INC=24, DEC=16
8298 22:50:13.737204 [RxdqsGatingPostProcess] freq 1600
8299 22:50:13.743464 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8300 22:50:13.747237 best DQS0 dly(2T, 0.5T) = (1, 1)
8301 22:50:13.750169 best DQS1 dly(2T, 0.5T) = (1, 1)
8302 22:50:13.753670 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8303 22:50:13.757178 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8304 22:50:13.760426 best DQS0 dly(2T, 0.5T) = (1, 1)
8305 22:50:13.760501 best DQS1 dly(2T, 0.5T) = (1, 1)
8306 22:50:13.763550 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8307 22:50:13.767024 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8308 22:50:13.770175 Pre-setting of DQS Precalculation
8309 22:50:13.777027 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8310 22:50:13.777137 ==
8311 22:50:13.780102 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 22:50:13.783189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 22:50:13.783261 ==
8314 22:50:13.789982 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8315 22:50:13.793529 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8316 22:50:13.796922 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8317 22:50:13.803260 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8318 22:50:13.812612 [CA 0] Center 41 (12~71) winsize 60
8319 22:50:13.815994 [CA 1] Center 42 (12~72) winsize 61
8320 22:50:13.819252 [CA 2] Center 37 (9~66) winsize 58
8321 22:50:13.822247 [CA 3] Center 36 (7~66) winsize 60
8322 22:50:13.825463 [CA 4] Center 37 (8~66) winsize 59
8323 22:50:13.828820 [CA 5] Center 36 (7~66) winsize 60
8324 22:50:13.828915
8325 22:50:13.832267 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8326 22:50:13.832358
8327 22:50:13.835594 [CATrainingPosCal] consider 1 rank data
8328 22:50:13.839119 u2DelayCellTimex100 = 258/100 ps
8329 22:50:13.842555 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8330 22:50:13.848714 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8331 22:50:13.852419 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8332 22:50:13.855423 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8333 22:50:13.858818 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8334 22:50:13.862028 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8335 22:50:13.862119
8336 22:50:13.865343 CA PerBit enable=1, Macro0, CA PI delay=36
8337 22:50:13.865440
8338 22:50:13.868749 [CBTSetCACLKResult] CA Dly = 36
8339 22:50:13.872173 CS Dly: 9 (0~40)
8340 22:50:13.875619 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8341 22:50:13.878841 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8342 22:50:13.878943 ==
8343 22:50:13.881891 Dram Type= 6, Freq= 0, CH_1, rank 1
8344 22:50:13.885276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 22:50:13.888403 ==
8346 22:50:13.892035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8347 22:50:13.895246 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8348 22:50:13.901892 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8349 22:50:13.905261 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8350 22:50:13.915536 [CA 0] Center 41 (12~71) winsize 60
8351 22:50:13.918644 [CA 1] Center 42 (12~72) winsize 61
8352 22:50:13.922144 [CA 2] Center 37 (8~67) winsize 60
8353 22:50:13.925906 [CA 3] Center 36 (7~66) winsize 60
8354 22:50:13.928932 [CA 4] Center 37 (8~67) winsize 60
8355 22:50:13.932236 [CA 5] Center 36 (6~66) winsize 61
8356 22:50:13.932330
8357 22:50:13.935249 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8358 22:50:13.935324
8359 22:50:13.938697 [CATrainingPosCal] consider 2 rank data
8360 22:50:13.942047 u2DelayCellTimex100 = 258/100 ps
8361 22:50:13.945416 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8362 22:50:13.952385 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8363 22:50:13.955146 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8364 22:50:13.958571 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8365 22:50:13.961879 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8366 22:50:13.965298 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8367 22:50:13.965395
8368 22:50:13.968382 CA PerBit enable=1, Macro0, CA PI delay=36
8369 22:50:13.968454
8370 22:50:13.971531 [CBTSetCACLKResult] CA Dly = 36
8371 22:50:13.974923 CS Dly: 10 (0~43)
8372 22:50:13.978372 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8373 22:50:13.981779 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8374 22:50:13.981848
8375 22:50:13.984826 ----->DramcWriteLeveling(PI) begin...
8376 22:50:13.984920 ==
8377 22:50:13.988117 Dram Type= 6, Freq= 0, CH_1, rank 0
8378 22:50:13.994860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 22:50:13.994972 ==
8380 22:50:13.998175 Write leveling (Byte 0): 25 => 25
8381 22:50:13.998270 Write leveling (Byte 1): 28 => 28
8382 22:50:14.001878 DramcWriteLeveling(PI) end<-----
8383 22:50:14.001948
8384 22:50:14.004880 ==
8385 22:50:14.004972 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 22:50:14.011811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 22:50:14.011913 ==
8388 22:50:14.015156 [Gating] SW mode calibration
8389 22:50:14.021307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8390 22:50:14.024627 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8391 22:50:14.031180 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 22:50:14.035054 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 22:50:14.038333 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 22:50:14.044544 1 4 12 | B1->B0 | 2727 2322 | 0 1 | (0 0) (0 0)
8395 22:50:14.048014 1 4 16 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
8396 22:50:14.051413 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 22:50:14.058106 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 22:50:14.060881 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 22:50:14.064535 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 22:50:14.070842 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 22:50:14.074329 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 22:50:14.077534 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8403 22:50:14.084649 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8404 22:50:14.088088 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 22:50:14.090854 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 22:50:14.097467 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 22:50:14.100929 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 22:50:14.104326 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 22:50:14.111222 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 22:50:14.114360 1 6 12 | B1->B0 | 2929 2525 | 0 0 | (1 1) (0 0)
8411 22:50:14.117464 1 6 16 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
8412 22:50:14.120836 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 22:50:14.127442 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 22:50:14.130837 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 22:50:14.134205 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 22:50:14.140806 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 22:50:14.143945 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 22:50:14.147347 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 22:50:14.153696 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8420 22:50:14.157142 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 22:50:14.160403 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 22:50:14.167326 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 22:50:14.170264 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 22:50:14.173705 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 22:50:14.180517 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 22:50:14.184034 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 22:50:14.186782 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 22:50:14.193758 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 22:50:14.197168 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 22:50:14.200419 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 22:50:14.206570 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 22:50:14.210188 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 22:50:14.213732 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 22:50:14.219833 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 22:50:14.223558 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8436 22:50:14.226686 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 22:50:14.229824 Total UI for P1: 0, mck2ui 16
8438 22:50:14.233203 best dqsien dly found for B0: ( 1, 9, 16)
8439 22:50:14.236633 Total UI for P1: 0, mck2ui 16
8440 22:50:14.240029 best dqsien dly found for B1: ( 1, 9, 16)
8441 22:50:14.243577 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8442 22:50:14.246358 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8443 22:50:14.246466
8444 22:50:14.253365 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8445 22:50:14.256521 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8446 22:50:14.259667 [Gating] SW calibration Done
8447 22:50:14.259772 ==
8448 22:50:14.263524 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 22:50:14.266364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 22:50:14.266463 ==
8451 22:50:14.266560 RX Vref Scan: 0
8452 22:50:14.266654
8453 22:50:14.269468 RX Vref 0 -> 0, step: 1
8454 22:50:14.269572
8455 22:50:14.273462 RX Delay 0 -> 252, step: 8
8456 22:50:14.276262 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8457 22:50:14.279785 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8458 22:50:14.286112 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8459 22:50:14.289402 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8460 22:50:14.293127 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8461 22:50:14.296507 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8462 22:50:14.299866 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8463 22:50:14.303172 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8464 22:50:14.309694 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8465 22:50:14.313076 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8466 22:50:14.316280 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8467 22:50:14.319754 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8468 22:50:14.326560 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8469 22:50:14.329842 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8470 22:50:14.332979 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8471 22:50:14.336237 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8472 22:50:14.336330 ==
8473 22:50:14.339707 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 22:50:14.346526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 22:50:14.346598 ==
8476 22:50:14.346666 DQS Delay:
8477 22:50:14.346735 DQS0 = 0, DQS1 = 0
8478 22:50:14.349875 DQM Delay:
8479 22:50:14.349959 DQM0 = 131, DQM1 = 125
8480 22:50:14.352935 DQ Delay:
8481 22:50:14.356345 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8482 22:50:14.359313 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8483 22:50:14.362720 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8484 22:50:14.366142 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8485 22:50:14.366246
8486 22:50:14.366334
8487 22:50:14.366428 ==
8488 22:50:14.369625 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 22:50:14.372966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 22:50:14.375950 ==
8491 22:50:14.376020
8492 22:50:14.376079
8493 22:50:14.376136 TX Vref Scan disable
8494 22:50:14.379635 == TX Byte 0 ==
8495 22:50:14.382655 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8496 22:50:14.385930 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8497 22:50:14.389082 == TX Byte 1 ==
8498 22:50:14.392603 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8499 22:50:14.396101 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8500 22:50:14.399449 ==
8501 22:50:14.399545 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 22:50:14.405741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 22:50:14.405839 ==
8504 22:50:14.418707
8505 22:50:14.421841 TX Vref early break, caculate TX vref
8506 22:50:14.425418 TX Vref=16, minBit 8, minWin=22, winSum=367
8507 22:50:14.428856 TX Vref=18, minBit 9, minWin=22, winSum=375
8508 22:50:14.432272 TX Vref=20, minBit 8, minWin=23, winSum=387
8509 22:50:14.435393 TX Vref=22, minBit 12, minWin=23, winSum=396
8510 22:50:14.438963 TX Vref=24, minBit 13, minWin=24, winSum=409
8511 22:50:14.445124 TX Vref=26, minBit 1, minWin=25, winSum=415
8512 22:50:14.448533 TX Vref=28, minBit 1, minWin=25, winSum=418
8513 22:50:14.452133 TX Vref=30, minBit 0, minWin=25, winSum=410
8514 22:50:14.455020 TX Vref=32, minBit 0, minWin=24, winSum=409
8515 22:50:14.458735 TX Vref=34, minBit 0, minWin=24, winSum=400
8516 22:50:14.461827 TX Vref=36, minBit 0, minWin=23, winSum=388
8517 22:50:14.468763 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
8518 22:50:14.468843
8519 22:50:14.471720 Final TX Range 0 Vref 28
8520 22:50:14.471819
8521 22:50:14.471916 ==
8522 22:50:14.475263 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 22:50:14.478646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 22:50:14.478742 ==
8525 22:50:14.478841
8526 22:50:14.481964
8527 22:50:14.482038 TX Vref Scan disable
8528 22:50:14.488141 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8529 22:50:14.488238 == TX Byte 0 ==
8530 22:50:14.491899 u2DelayCellOfst[0]=18 cells (5 PI)
8531 22:50:14.494888 u2DelayCellOfst[1]=11 cells (3 PI)
8532 22:50:14.498528 u2DelayCellOfst[2]=0 cells (0 PI)
8533 22:50:14.501985 u2DelayCellOfst[3]=3 cells (1 PI)
8534 22:50:14.504855 u2DelayCellOfst[4]=7 cells (2 PI)
8535 22:50:14.508227 u2DelayCellOfst[5]=18 cells (5 PI)
8536 22:50:14.511634 u2DelayCellOfst[6]=22 cells (6 PI)
8537 22:50:14.515093 u2DelayCellOfst[7]=7 cells (2 PI)
8538 22:50:14.518060 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8539 22:50:14.521436 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8540 22:50:14.524860 == TX Byte 1 ==
8541 22:50:14.528174 u2DelayCellOfst[8]=0 cells (0 PI)
8542 22:50:14.531549 u2DelayCellOfst[9]=7 cells (2 PI)
8543 22:50:14.534818 u2DelayCellOfst[10]=15 cells (4 PI)
8544 22:50:14.534913 u2DelayCellOfst[11]=7 cells (2 PI)
8545 22:50:14.538120 u2DelayCellOfst[12]=18 cells (5 PI)
8546 22:50:14.541297 u2DelayCellOfst[13]=22 cells (6 PI)
8547 22:50:14.544792 u2DelayCellOfst[14]=22 cells (6 PI)
8548 22:50:14.548300 u2DelayCellOfst[15]=22 cells (6 PI)
8549 22:50:14.554410 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8550 22:50:14.557881 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8551 22:50:14.557977 DramC Write-DBI on
8552 22:50:14.560987 ==
8553 22:50:14.561073 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 22:50:14.567500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 22:50:14.567606 ==
8556 22:50:14.567701
8557 22:50:14.567787
8558 22:50:14.571100 TX Vref Scan disable
8559 22:50:14.571200 == TX Byte 0 ==
8560 22:50:14.577465 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8561 22:50:14.577605 == TX Byte 1 ==
8562 22:50:14.580778 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8563 22:50:14.584177 DramC Write-DBI off
8564 22:50:14.584284
8565 22:50:14.584382 [DATLAT]
8566 22:50:14.587741 Freq=1600, CH1 RK0
8567 22:50:14.587835
8568 22:50:14.587927 DATLAT Default: 0xf
8569 22:50:14.591000 0, 0xFFFF, sum = 0
8570 22:50:14.591087 1, 0xFFFF, sum = 0
8571 22:50:14.594230 2, 0xFFFF, sum = 0
8572 22:50:14.594303 3, 0xFFFF, sum = 0
8573 22:50:14.597140 4, 0xFFFF, sum = 0
8574 22:50:14.597213 5, 0xFFFF, sum = 0
8575 22:50:14.600679 6, 0xFFFF, sum = 0
8576 22:50:14.600768 7, 0xFFFF, sum = 0
8577 22:50:14.603888 8, 0xFFFF, sum = 0
8578 22:50:14.607556 9, 0xFFFF, sum = 0
8579 22:50:14.607634 10, 0xFFFF, sum = 0
8580 22:50:14.610838 11, 0xFFFF, sum = 0
8581 22:50:14.610914 12, 0xFFFF, sum = 0
8582 22:50:14.613714 13, 0x8FFF, sum = 0
8583 22:50:14.613789 14, 0x0, sum = 1
8584 22:50:14.617173 15, 0x0, sum = 2
8585 22:50:14.617272 16, 0x0, sum = 3
8586 22:50:14.620671 17, 0x0, sum = 4
8587 22:50:14.620745 best_step = 15
8588 22:50:14.620808
8589 22:50:14.620879 ==
8590 22:50:14.624073 Dram Type= 6, Freq= 0, CH_1, rank 0
8591 22:50:14.627385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8592 22:50:14.627466 ==
8593 22:50:14.630256 RX Vref Scan: 1
8594 22:50:14.630327
8595 22:50:14.634165 Set Vref Range= 24 -> 127
8596 22:50:14.634248
8597 22:50:14.634341 RX Vref 24 -> 127, step: 1
8598 22:50:14.636991
8599 22:50:14.637088 RX Delay 11 -> 252, step: 4
8600 22:50:14.637176
8601 22:50:14.640321 Set Vref, RX VrefLevel [Byte0]: 24
8602 22:50:14.643806 [Byte1]: 24
8603 22:50:14.647041
8604 22:50:14.647115 Set Vref, RX VrefLevel [Byte0]: 25
8605 22:50:14.650427 [Byte1]: 25
8606 22:50:14.654862
8607 22:50:14.654935 Set Vref, RX VrefLevel [Byte0]: 26
8608 22:50:14.658007 [Byte1]: 26
8609 22:50:14.662553
8610 22:50:14.662658 Set Vref, RX VrefLevel [Byte0]: 27
8611 22:50:14.666001 [Byte1]: 27
8612 22:50:14.670151
8613 22:50:14.670257 Set Vref, RX VrefLevel [Byte0]: 28
8614 22:50:14.673164 [Byte1]: 28
8615 22:50:14.677643
8616 22:50:14.677727 Set Vref, RX VrefLevel [Byte0]: 29
8617 22:50:14.680735 [Byte1]: 29
8618 22:50:14.685342
8619 22:50:14.685450 Set Vref, RX VrefLevel [Byte0]: 30
8620 22:50:14.688555 [Byte1]: 30
8621 22:50:14.692627
8622 22:50:14.692724 Set Vref, RX VrefLevel [Byte0]: 31
8623 22:50:14.696071 [Byte1]: 31
8624 22:50:14.700589
8625 22:50:14.700686 Set Vref, RX VrefLevel [Byte0]: 32
8626 22:50:14.703931 [Byte1]: 32
8627 22:50:14.707962
8628 22:50:14.708060 Set Vref, RX VrefLevel [Byte0]: 33
8629 22:50:14.711339 [Byte1]: 33
8630 22:50:14.715596
8631 22:50:14.715693 Set Vref, RX VrefLevel [Byte0]: 34
8632 22:50:14.719176 [Byte1]: 34
8633 22:50:14.723707
8634 22:50:14.723805 Set Vref, RX VrefLevel [Byte0]: 35
8635 22:50:14.727003 [Byte1]: 35
8636 22:50:14.731005
8637 22:50:14.731104 Set Vref, RX VrefLevel [Byte0]: 36
8638 22:50:14.734396 [Byte1]: 36
8639 22:50:14.738735
8640 22:50:14.738827 Set Vref, RX VrefLevel [Byte0]: 37
8641 22:50:14.741773 [Byte1]: 37
8642 22:50:14.746376
8643 22:50:14.746451 Set Vref, RX VrefLevel [Byte0]: 38
8644 22:50:14.749690 [Byte1]: 38
8645 22:50:14.753814
8646 22:50:14.753887 Set Vref, RX VrefLevel [Byte0]: 39
8647 22:50:14.757308 [Byte1]: 39
8648 22:50:14.761205
8649 22:50:14.761307 Set Vref, RX VrefLevel [Byte0]: 40
8650 22:50:14.764927 [Byte1]: 40
8651 22:50:14.769095
8652 22:50:14.769194 Set Vref, RX VrefLevel [Byte0]: 41
8653 22:50:14.772433 [Byte1]: 41
8654 22:50:14.776874
8655 22:50:14.776949 Set Vref, RX VrefLevel [Byte0]: 42
8656 22:50:14.780028 [Byte1]: 42
8657 22:50:14.784499
8658 22:50:14.784574 Set Vref, RX VrefLevel [Byte0]: 43
8659 22:50:14.787326 [Byte1]: 43
8660 22:50:14.791887
8661 22:50:14.791987 Set Vref, RX VrefLevel [Byte0]: 44
8662 22:50:14.795114 [Byte1]: 44
8663 22:50:14.799238
8664 22:50:14.799330 Set Vref, RX VrefLevel [Byte0]: 45
8665 22:50:14.802942 [Byte1]: 45
8666 22:50:14.806972
8667 22:50:14.807047 Set Vref, RX VrefLevel [Byte0]: 46
8668 22:50:14.810481 [Byte1]: 46
8669 22:50:14.815064
8670 22:50:14.815139 Set Vref, RX VrefLevel [Byte0]: 47
8671 22:50:14.818035 [Byte1]: 47
8672 22:50:14.822328
8673 22:50:14.822401 Set Vref, RX VrefLevel [Byte0]: 48
8674 22:50:14.825471 [Byte1]: 48
8675 22:50:14.829979
8676 22:50:14.830082 Set Vref, RX VrefLevel [Byte0]: 49
8677 22:50:14.833370 [Byte1]: 49
8678 22:50:14.837404
8679 22:50:14.837504 Set Vref, RX VrefLevel [Byte0]: 50
8680 22:50:14.840695 [Byte1]: 50
8681 22:50:14.845245
8682 22:50:14.845346 Set Vref, RX VrefLevel [Byte0]: 51
8683 22:50:14.848733 [Byte1]: 51
8684 22:50:14.852637
8685 22:50:14.852735 Set Vref, RX VrefLevel [Byte0]: 52
8686 22:50:14.856139 [Byte1]: 52
8687 22:50:14.860539
8688 22:50:14.860643 Set Vref, RX VrefLevel [Byte0]: 53
8689 22:50:14.863449 [Byte1]: 53
8690 22:50:14.867805
8691 22:50:14.867904 Set Vref, RX VrefLevel [Byte0]: 54
8692 22:50:14.871204 [Byte1]: 54
8693 22:50:14.875716
8694 22:50:14.875816 Set Vref, RX VrefLevel [Byte0]: 55
8695 22:50:14.878912 [Byte1]: 55
8696 22:50:14.883152
8697 22:50:14.883224 Set Vref, RX VrefLevel [Byte0]: 56
8698 22:50:14.886353 [Byte1]: 56
8699 22:50:14.890617
8700 22:50:14.890692 Set Vref, RX VrefLevel [Byte0]: 57
8701 22:50:14.894094 [Byte1]: 57
8702 22:50:14.898425
8703 22:50:14.898555 Set Vref, RX VrefLevel [Byte0]: 58
8704 22:50:14.901769 [Byte1]: 58
8705 22:50:14.905860
8706 22:50:14.905934 Set Vref, RX VrefLevel [Byte0]: 59
8707 22:50:14.909478 [Byte1]: 59
8708 22:50:14.913411
8709 22:50:14.913533 Set Vref, RX VrefLevel [Byte0]: 60
8710 22:50:14.916791 [Byte1]: 60
8711 22:50:14.921307
8712 22:50:14.921382 Set Vref, RX VrefLevel [Byte0]: 61
8713 22:50:14.924234 [Byte1]: 61
8714 22:50:14.928749
8715 22:50:14.928825 Set Vref, RX VrefLevel [Byte0]: 62
8716 22:50:14.931996 [Byte1]: 62
8717 22:50:14.936847
8718 22:50:14.936948 Set Vref, RX VrefLevel [Byte0]: 63
8719 22:50:14.939529 [Byte1]: 63
8720 22:50:14.943973
8721 22:50:14.944054 Set Vref, RX VrefLevel [Byte0]: 64
8722 22:50:14.947257 [Byte1]: 64
8723 22:50:14.951894
8724 22:50:14.951967 Set Vref, RX VrefLevel [Byte0]: 65
8725 22:50:14.955153 [Byte1]: 65
8726 22:50:14.959136
8727 22:50:14.959222 Set Vref, RX VrefLevel [Byte0]: 66
8728 22:50:14.962536 [Byte1]: 66
8729 22:50:14.967176
8730 22:50:14.967277 Set Vref, RX VrefLevel [Byte0]: 67
8731 22:50:14.970079 [Byte1]: 67
8732 22:50:14.974478
8733 22:50:14.974551 Set Vref, RX VrefLevel [Byte0]: 68
8734 22:50:14.977941 [Byte1]: 68
8735 22:50:14.981999
8736 22:50:14.982075 Set Vref, RX VrefLevel [Byte0]: 69
8737 22:50:14.985313 [Byte1]: 69
8738 22:50:14.989883
8739 22:50:14.989980 Set Vref, RX VrefLevel [Byte0]: 70
8740 22:50:14.993218 [Byte1]: 70
8741 22:50:14.997155
8742 22:50:14.997255 Final RX Vref Byte 0 = 57 to rank0
8743 22:50:15.000418 Final RX Vref Byte 1 = 55 to rank0
8744 22:50:15.003660 Final RX Vref Byte 0 = 57 to rank1
8745 22:50:15.007277 Final RX Vref Byte 1 = 55 to rank1==
8746 22:50:15.010337 Dram Type= 6, Freq= 0, CH_1, rank 0
8747 22:50:15.017081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 22:50:15.017171 ==
8749 22:50:15.017237 DQS Delay:
8750 22:50:15.020338 DQS0 = 0, DQS1 = 0
8751 22:50:15.020433 DQM Delay:
8752 22:50:15.020552 DQM0 = 131, DQM1 = 123
8753 22:50:15.023668 DQ Delay:
8754 22:50:15.026945 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8755 22:50:15.030606 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8756 22:50:15.033857 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8757 22:50:15.037152 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8758 22:50:15.037250
8759 22:50:15.037339
8760 22:50:15.037429
8761 22:50:15.040366 [DramC_TX_OE_Calibration] TA2
8762 22:50:15.043640 Original DQ_B0 (3 6) =30, OEN = 27
8763 22:50:15.046787 Original DQ_B1 (3 6) =30, OEN = 27
8764 22:50:15.050276 24, 0x0, End_B0=24 End_B1=24
8765 22:50:15.050365 25, 0x0, End_B0=25 End_B1=25
8766 22:50:15.053614 26, 0x0, End_B0=26 End_B1=26
8767 22:50:15.057217 27, 0x0, End_B0=27 End_B1=27
8768 22:50:15.060018 28, 0x0, End_B0=28 End_B1=28
8769 22:50:15.063466 29, 0x0, End_B0=29 End_B1=29
8770 22:50:15.063570 30, 0x0, End_B0=30 End_B1=30
8771 22:50:15.066843 31, 0x4141, End_B0=30 End_B1=30
8772 22:50:15.070333 Byte0 end_step=30 best_step=27
8773 22:50:15.073811 Byte1 end_step=30 best_step=27
8774 22:50:15.076572 Byte0 TX OE(2T, 0.5T) = (3, 3)
8775 22:50:15.079955 Byte1 TX OE(2T, 0.5T) = (3, 3)
8776 22:50:15.080057
8777 22:50:15.080150
8778 22:50:15.086943 [DQSOSCAuto] RK0, (LSB)MR18= 0x80c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8779 22:50:15.090348 CH1 RK0: MR19=303, MR18=80C
8780 22:50:15.096719 CH1_RK0: MR19=0x303, MR18=0x80C, DQSOSC=403, MR23=63, INC=22, DEC=15
8781 22:50:15.096793
8782 22:50:15.100183 ----->DramcWriteLeveling(PI) begin...
8783 22:50:15.100258 ==
8784 22:50:15.103132 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 22:50:15.106503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 22:50:15.106574 ==
8787 22:50:15.110004 Write leveling (Byte 0): 23 => 23
8788 22:50:15.113007 Write leveling (Byte 1): 29 => 29
8789 22:50:15.116296 DramcWriteLeveling(PI) end<-----
8790 22:50:15.116368
8791 22:50:15.116429 ==
8792 22:50:15.119639 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 22:50:15.122867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 22:50:15.122967 ==
8795 22:50:15.126249 [Gating] SW mode calibration
8796 22:50:15.132839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8797 22:50:15.139638 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8798 22:50:15.143080 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 22:50:15.149138 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 22:50:15.152635 1 4 8 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
8801 22:50:15.156218 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8802 22:50:15.162694 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 22:50:15.165883 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 22:50:15.169342 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 22:50:15.175680 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 22:50:15.179045 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 22:50:15.182458 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 22:50:15.189274 1 5 8 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8809 22:50:15.192222 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
8810 22:50:15.195748 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 22:50:15.202060 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 22:50:15.205411 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 22:50:15.208983 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 22:50:15.215898 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 22:50:15.218747 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 22:50:15.222203 1 6 8 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
8817 22:50:15.228771 1 6 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8818 22:50:15.232174 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 22:50:15.235504 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 22:50:15.241932 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 22:50:15.245214 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 22:50:15.248732 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 22:50:15.251622 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 22:50:15.258315 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8825 22:50:15.261884 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8826 22:50:15.264885 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 22:50:15.271731 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 22:50:15.275102 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 22:50:15.278501 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 22:50:15.284743 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 22:50:15.288123 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 22:50:15.291718 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 22:50:15.297839 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 22:50:15.301159 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 22:50:15.304560 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 22:50:15.311402 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 22:50:15.314866 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 22:50:15.317832 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 22:50:15.324886 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 22:50:15.327730 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8841 22:50:15.331225 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 22:50:15.334442 Total UI for P1: 0, mck2ui 16
8843 22:50:15.337667 best dqsien dly found for B0: ( 1, 9, 8)
8844 22:50:15.341168 Total UI for P1: 0, mck2ui 16
8845 22:50:15.344772 best dqsien dly found for B1: ( 1, 9, 10)
8846 22:50:15.347969 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8847 22:50:15.351199 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8848 22:50:15.351274
8849 22:50:15.357796 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8850 22:50:15.361285 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8851 22:50:15.361388 [Gating] SW calibration Done
8852 22:50:15.364790 ==
8853 22:50:15.367606 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 22:50:15.371031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 22:50:15.371125 ==
8856 22:50:15.371215 RX Vref Scan: 0
8857 22:50:15.371302
8858 22:50:15.374225 RX Vref 0 -> 0, step: 1
8859 22:50:15.374294
8860 22:50:15.377912 RX Delay 0 -> 252, step: 8
8861 22:50:15.381040 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8862 22:50:15.384169 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8863 22:50:15.387489 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8864 22:50:15.394167 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8865 22:50:15.397780 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8866 22:50:15.401065 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8867 22:50:15.403892 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8868 22:50:15.407239 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8869 22:50:15.414217 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8870 22:50:15.417660 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8871 22:50:15.421049 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8872 22:50:15.423897 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8873 22:50:15.430636 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8874 22:50:15.434051 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8875 22:50:15.437431 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8876 22:50:15.440746 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8877 22:50:15.440849 ==
8878 22:50:15.443954 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 22:50:15.450700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 22:50:15.450779 ==
8881 22:50:15.450842 DQS Delay:
8882 22:50:15.450912 DQS0 = 0, DQS1 = 0
8883 22:50:15.453824 DQM Delay:
8884 22:50:15.453925 DQM0 = 133, DQM1 = 127
8885 22:50:15.457025 DQ Delay:
8886 22:50:15.460576 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8887 22:50:15.463969 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8888 22:50:15.467105 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8889 22:50:15.470505 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8890 22:50:15.470611
8891 22:50:15.470700
8892 22:50:15.470795 ==
8893 22:50:15.473951 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 22:50:15.477378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 22:50:15.480508 ==
8896 22:50:15.480580
8897 22:50:15.480641
8898 22:50:15.480701 TX Vref Scan disable
8899 22:50:15.483694 == TX Byte 0 ==
8900 22:50:15.487226 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8901 22:50:15.490659 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8902 22:50:15.493940 == TX Byte 1 ==
8903 22:50:15.497262 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8904 22:50:15.500265 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8905 22:50:15.500344 ==
8906 22:50:15.503670 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 22:50:15.510168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 22:50:15.510241 ==
8909 22:50:15.523797
8910 22:50:15.527145 TX Vref early break, caculate TX vref
8911 22:50:15.530510 TX Vref=16, minBit 0, minWin=22, winSum=373
8912 22:50:15.533737 TX Vref=18, minBit 0, minWin=23, winSum=385
8913 22:50:15.536919 TX Vref=20, minBit 5, minWin=23, winSum=388
8914 22:50:15.540320 TX Vref=22, minBit 0, minWin=23, winSum=397
8915 22:50:15.543453 TX Vref=24, minBit 0, minWin=25, winSum=408
8916 22:50:15.550207 TX Vref=26, minBit 0, minWin=24, winSum=413
8917 22:50:15.553715 TX Vref=28, minBit 5, minWin=24, winSum=415
8918 22:50:15.557026 TX Vref=30, minBit 0, minWin=24, winSum=414
8919 22:50:15.560524 TX Vref=32, minBit 5, minWin=23, winSum=399
8920 22:50:15.563736 TX Vref=34, minBit 5, minWin=23, winSum=396
8921 22:50:15.566875 TX Vref=36, minBit 1, minWin=22, winSum=384
8922 22:50:15.573156 [TxChooseVref] Worse bit 0, Min win 25, Win sum 408, Final Vref 24
8923 22:50:15.573261
8924 22:50:15.576800 Final TX Range 0 Vref 24
8925 22:50:15.576904
8926 22:50:15.576992 ==
8927 22:50:15.579992 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 22:50:15.583405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 22:50:15.583476 ==
8930 22:50:15.583537
8931 22:50:15.586478
8932 22:50:15.586559 TX Vref Scan disable
8933 22:50:15.593157 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8934 22:50:15.593257 == TX Byte 0 ==
8935 22:50:15.596589 u2DelayCellOfst[0]=18 cells (5 PI)
8936 22:50:15.600119 u2DelayCellOfst[1]=15 cells (4 PI)
8937 22:50:15.603379 u2DelayCellOfst[2]=0 cells (0 PI)
8938 22:50:15.606316 u2DelayCellOfst[3]=11 cells (3 PI)
8939 22:50:15.609755 u2DelayCellOfst[4]=11 cells (3 PI)
8940 22:50:15.613316 u2DelayCellOfst[5]=22 cells (6 PI)
8941 22:50:15.616229 u2DelayCellOfst[6]=22 cells (6 PI)
8942 22:50:15.619848 u2DelayCellOfst[7]=7 cells (2 PI)
8943 22:50:15.623440 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8944 22:50:15.626201 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8945 22:50:15.629668 == TX Byte 1 ==
8946 22:50:15.633029 u2DelayCellOfst[8]=0 cells (0 PI)
8947 22:50:15.636408 u2DelayCellOfst[9]=3 cells (1 PI)
8948 22:50:15.639751 u2DelayCellOfst[10]=11 cells (3 PI)
8949 22:50:15.642764 u2DelayCellOfst[11]=3 cells (1 PI)
8950 22:50:15.642878 u2DelayCellOfst[12]=15 cells (4 PI)
8951 22:50:15.646271 u2DelayCellOfst[13]=15 cells (4 PI)
8952 22:50:15.649513 u2DelayCellOfst[14]=15 cells (4 PI)
8953 22:50:15.652760 u2DelayCellOfst[15]=18 cells (5 PI)
8954 22:50:15.659130 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8955 22:50:15.662490 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8956 22:50:15.662589 DramC Write-DBI on
8957 22:50:15.666266 ==
8958 22:50:15.669129 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 22:50:15.672634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 22:50:15.672729 ==
8961 22:50:15.672817
8962 22:50:15.672913
8963 22:50:15.675604 TX Vref Scan disable
8964 22:50:15.675698 == TX Byte 0 ==
8965 22:50:15.682187 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8966 22:50:15.682263 == TX Byte 1 ==
8967 22:50:15.685530 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8968 22:50:15.689146 DramC Write-DBI off
8969 22:50:15.689215
8970 22:50:15.689285 [DATLAT]
8971 22:50:15.692027 Freq=1600, CH1 RK1
8972 22:50:15.692156
8973 22:50:15.692255 DATLAT Default: 0xf
8974 22:50:15.695768 0, 0xFFFF, sum = 0
8975 22:50:15.695848 1, 0xFFFF, sum = 0
8976 22:50:15.698787 2, 0xFFFF, sum = 0
8977 22:50:15.698862 3, 0xFFFF, sum = 0
8978 22:50:15.702561 4, 0xFFFF, sum = 0
8979 22:50:15.702634 5, 0xFFFF, sum = 0
8980 22:50:15.705728 6, 0xFFFF, sum = 0
8981 22:50:15.709184 7, 0xFFFF, sum = 0
8982 22:50:15.709280 8, 0xFFFF, sum = 0
8983 22:50:15.712077 9, 0xFFFF, sum = 0
8984 22:50:15.712160 10, 0xFFFF, sum = 0
8985 22:50:15.715547 11, 0xFFFF, sum = 0
8986 22:50:15.715646 12, 0xFFFF, sum = 0
8987 22:50:15.718808 13, 0x8FFF, sum = 0
8988 22:50:15.718915 14, 0x0, sum = 1
8989 22:50:15.722138 15, 0x0, sum = 2
8990 22:50:15.722210 16, 0x0, sum = 3
8991 22:50:15.725309 17, 0x0, sum = 4
8992 22:50:15.725413 best_step = 15
8993 22:50:15.725503
8994 22:50:15.725661 ==
8995 22:50:15.728922 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 22:50:15.732207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 22:50:15.735556 ==
8998 22:50:15.735657 RX Vref Scan: 0
8999 22:50:15.735774
9000 22:50:15.738564 RX Vref 0 -> 0, step: 1
9001 22:50:15.738656
9002 22:50:15.738752 RX Delay 11 -> 252, step: 4
9003 22:50:15.745912 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9004 22:50:15.749321 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9005 22:50:15.752520 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9006 22:50:15.755979 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9007 22:50:15.762050 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9008 22:50:15.765409 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9009 22:50:15.768847 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9010 22:50:15.772164 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9011 22:50:15.775526 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9012 22:50:15.782252 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9013 22:50:15.785700 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9014 22:50:15.788912 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9015 22:50:15.791815 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9016 22:50:15.795649 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9017 22:50:15.801888 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9018 22:50:15.805271 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9019 22:50:15.805370 ==
9020 22:50:15.808725 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 22:50:15.811837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 22:50:15.811940 ==
9023 22:50:15.815165 DQS Delay:
9024 22:50:15.815270 DQS0 = 0, DQS1 = 0
9025 22:50:15.815363 DQM Delay:
9026 22:50:15.818524 DQM0 = 130, DQM1 = 125
9027 22:50:15.818623 DQ Delay:
9028 22:50:15.822034 DQ0 =134, DQ1 =126, DQ2 =116, DQ3 =128
9029 22:50:15.825175 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
9030 22:50:15.828724 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9031 22:50:15.835233 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =136
9032 22:50:15.835335
9033 22:50:15.835424
9034 22:50:15.835486
9035 22:50:15.838318 [DramC_TX_OE_Calibration] TA2
9036 22:50:15.842184 Original DQ_B0 (3 6) =30, OEN = 27
9037 22:50:15.842268 Original DQ_B1 (3 6) =30, OEN = 27
9038 22:50:15.845167 24, 0x0, End_B0=24 End_B1=24
9039 22:50:15.848976 25, 0x0, End_B0=25 End_B1=25
9040 22:50:15.851579 26, 0x0, End_B0=26 End_B1=26
9041 22:50:15.855294 27, 0x0, End_B0=27 End_B1=27
9042 22:50:15.855401 28, 0x0, End_B0=28 End_B1=28
9043 22:50:15.858540 29, 0x0, End_B0=29 End_B1=29
9044 22:50:15.861720 30, 0x0, End_B0=30 End_B1=30
9045 22:50:15.865151 31, 0x4545, End_B0=30 End_B1=30
9046 22:50:15.868501 Byte0 end_step=30 best_step=27
9047 22:50:15.868609 Byte1 end_step=30 best_step=27
9048 22:50:15.871923 Byte0 TX OE(2T, 0.5T) = (3, 3)
9049 22:50:15.875342 Byte1 TX OE(2T, 0.5T) = (3, 3)
9050 22:50:15.875446
9051 22:50:15.875542
9052 22:50:15.885144 [DQSOSCAuto] RK1, (LSB)MR18= 0x101b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
9053 22:50:15.885259 CH1 RK1: MR19=303, MR18=101B
9054 22:50:15.891886 CH1_RK1: MR19=0x303, MR18=0x101B, DQSOSC=396, MR23=63, INC=23, DEC=15
9055 22:50:15.894733 [RxdqsGatingPostProcess] freq 1600
9056 22:50:15.901309 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9057 22:50:15.904678 best DQS0 dly(2T, 0.5T) = (1, 1)
9058 22:50:15.908012 best DQS1 dly(2T, 0.5T) = (1, 1)
9059 22:50:15.911473 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9060 22:50:15.914665 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9061 22:50:15.918312 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 22:50:15.918416 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 22:50:15.921436 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 22:50:15.924798 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 22:50:15.928120 Pre-setting of DQS Precalculation
9066 22:50:15.934769 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9067 22:50:15.941369 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9068 22:50:15.947959 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9069 22:50:15.948060
9070 22:50:15.948150
9071 22:50:15.951096 [Calibration Summary] 3200 Mbps
9072 22:50:15.951192 CH 0, Rank 0
9073 22:50:15.954553 SW Impedance : PASS
9074 22:50:15.958145 DUTY Scan : NO K
9075 22:50:15.958244 ZQ Calibration : PASS
9076 22:50:15.960903 Jitter Meter : NO K
9077 22:50:15.964654 CBT Training : PASS
9078 22:50:15.964731 Write leveling : PASS
9079 22:50:15.968022 RX DQS gating : PASS
9080 22:50:15.971347 RX DQ/DQS(RDDQC) : PASS
9081 22:50:15.971423 TX DQ/DQS : PASS
9082 22:50:15.974320 RX DATLAT : PASS
9083 22:50:15.978026 RX DQ/DQS(Engine): PASS
9084 22:50:15.978097 TX OE : PASS
9085 22:50:15.981390 All Pass.
9086 22:50:15.981459
9087 22:50:15.981538 CH 0, Rank 1
9088 22:50:15.984154 SW Impedance : PASS
9089 22:50:15.984223 DUTY Scan : NO K
9090 22:50:15.987633 ZQ Calibration : PASS
9091 22:50:15.991173 Jitter Meter : NO K
9092 22:50:15.991242 CBT Training : PASS
9093 22:50:15.994614 Write leveling : PASS
9094 22:50:15.997694 RX DQS gating : PASS
9095 22:50:15.997789 RX DQ/DQS(RDDQC) : PASS
9096 22:50:16.001232 TX DQ/DQS : PASS
9097 22:50:16.001305 RX DATLAT : PASS
9098 22:50:16.004020 RX DQ/DQS(Engine): PASS
9099 22:50:16.007310 TX OE : PASS
9100 22:50:16.007406 All Pass.
9101 22:50:16.007492
9102 22:50:16.007580 CH 1, Rank 0
9103 22:50:16.010896 SW Impedance : PASS
9104 22:50:16.014269 DUTY Scan : NO K
9105 22:50:16.014338 ZQ Calibration : PASS
9106 22:50:16.017135 Jitter Meter : NO K
9107 22:50:16.020866 CBT Training : PASS
9108 22:50:16.020939 Write leveling : PASS
9109 22:50:16.024351 RX DQS gating : PASS
9110 22:50:16.027205 RX DQ/DQS(RDDQC) : PASS
9111 22:50:16.027279 TX DQ/DQS : PASS
9112 22:50:16.030639 RX DATLAT : PASS
9113 22:50:16.033849 RX DQ/DQS(Engine): PASS
9114 22:50:16.033952 TX OE : PASS
9115 22:50:16.037343 All Pass.
9116 22:50:16.037440
9117 22:50:16.037546 CH 1, Rank 1
9118 22:50:16.040571 SW Impedance : PASS
9119 22:50:16.040674 DUTY Scan : NO K
9120 22:50:16.043992 ZQ Calibration : PASS
9121 22:50:16.047591 Jitter Meter : NO K
9122 22:50:16.047667 CBT Training : PASS
9123 22:50:16.050364 Write leveling : PASS
9124 22:50:16.053753 RX DQS gating : PASS
9125 22:50:16.053820 RX DQ/DQS(RDDQC) : PASS
9126 22:50:16.057312 TX DQ/DQS : PASS
9127 22:50:16.057406 RX DATLAT : PASS
9128 22:50:16.060257 RX DQ/DQS(Engine): PASS
9129 22:50:16.063447 TX OE : PASS
9130 22:50:16.063547 All Pass.
9131 22:50:16.063636
9132 22:50:16.066919 DramC Write-DBI on
9133 22:50:16.067018 PER_BANK_REFRESH: Hybrid Mode
9134 22:50:16.070344 TX_TRACKING: ON
9135 22:50:16.080170 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9136 22:50:16.086949 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9137 22:50:16.093493 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9138 22:50:16.097135 [FAST_K] Save calibration result to emmc
9139 22:50:16.100430 sync common calibartion params.
9140 22:50:16.103371 sync cbt_mode0:1, 1:1
9141 22:50:16.103446 dram_init: ddr_geometry: 2
9142 22:50:16.106799 dram_init: ddr_geometry: 2
9143 22:50:16.110081 dram_init: ddr_geometry: 2
9144 22:50:16.113658 0:dram_rank_size:100000000
9145 22:50:16.113732 1:dram_rank_size:100000000
9146 22:50:16.120416 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9147 22:50:16.123276 DFS_SHUFFLE_HW_MODE: ON
9148 22:50:16.126548 dramc_set_vcore_voltage set vcore to 725000
9149 22:50:16.129957 Read voltage for 1600, 0
9150 22:50:16.130059 Vio18 = 0
9151 22:50:16.130155 Vcore = 725000
9152 22:50:16.133437 Vdram = 0
9153 22:50:16.133554 Vddq = 0
9154 22:50:16.133646 Vmddr = 0
9155 22:50:16.136958 switch to 3200 Mbps bootup
9156 22:50:16.137051 [DramcRunTimeConfig]
9157 22:50:16.140372 PHYPLL
9158 22:50:16.140474 DPM_CONTROL_AFTERK: ON
9159 22:50:16.143575 PER_BANK_REFRESH: ON
9160 22:50:16.146795 REFRESH_OVERHEAD_REDUCTION: ON
9161 22:50:16.146867 CMD_PICG_NEW_MODE: OFF
9162 22:50:16.149765 XRTWTW_NEW_MODE: ON
9163 22:50:16.149858 XRTRTR_NEW_MODE: ON
9164 22:50:16.153184 TX_TRACKING: ON
9165 22:50:16.153285 RDSEL_TRACKING: OFF
9166 22:50:16.156690 DQS Precalculation for DVFS: ON
9167 22:50:16.159758 RX_TRACKING: OFF
9168 22:50:16.159874 HW_GATING DBG: ON
9169 22:50:16.163243 ZQCS_ENABLE_LP4: ON
9170 22:50:16.163344 RX_PICG_NEW_MODE: ON
9171 22:50:16.166394 TX_PICG_NEW_MODE: ON
9172 22:50:16.166497 ENABLE_RX_DCM_DPHY: ON
9173 22:50:16.169769 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9174 22:50:16.173116 DUMMY_READ_FOR_TRACKING: OFF
9175 22:50:16.176472 !!! SPM_CONTROL_AFTERK: OFF
9176 22:50:16.179729 !!! SPM could not control APHY
9177 22:50:16.179824 IMPEDANCE_TRACKING: ON
9178 22:50:16.183194 TEMP_SENSOR: ON
9179 22:50:16.183288 HW_SAVE_FOR_SR: OFF
9180 22:50:16.186485 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9181 22:50:16.189763 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9182 22:50:16.192987 Read ODT Tracking: ON
9183 22:50:16.197086 Refresh Rate DeBounce: ON
9184 22:50:16.197189 DFS_NO_QUEUE_FLUSH: ON
9185 22:50:16.200000 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9186 22:50:16.203544 ENABLE_DFS_RUNTIME_MRW: OFF
9187 22:50:16.206198 DDR_RESERVE_NEW_MODE: ON
9188 22:50:16.206268 MR_CBT_SWITCH_FREQ: ON
9189 22:50:16.209527 =========================
9190 22:50:16.228534 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9191 22:50:16.231927 dram_init: ddr_geometry: 2
9192 22:50:16.250217 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9193 22:50:16.253655 dram_init: dram init end (result: 0)
9194 22:50:16.260126 DRAM-K: Full calibration passed in 24554 msecs
9195 22:50:16.263250 MRC: failed to locate region type 0.
9196 22:50:16.263364 DRAM rank0 size:0x100000000,
9197 22:50:16.266715 DRAM rank1 size=0x100000000
9198 22:50:16.276826 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9199 22:50:16.283491 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9200 22:50:16.290231 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9201 22:50:16.297010 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9202 22:50:16.299999 DRAM rank0 size:0x100000000,
9203 22:50:16.303247 DRAM rank1 size=0x100000000
9204 22:50:16.303318 CBMEM:
9205 22:50:16.306890 IMD: root @ 0xfffff000 254 entries.
9206 22:50:16.309765 IMD: root @ 0xffffec00 62 entries.
9207 22:50:16.313186 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9208 22:50:16.316445 WARNING: RO_VPD is uninitialized or empty.
9209 22:50:16.323197 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9210 22:50:16.330165 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9211 22:50:16.342687 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9212 22:50:16.354217 BS: romstage times (exec / console): total (unknown) / 24018 ms
9213 22:50:16.354321
9214 22:50:16.354410
9215 22:50:16.364317 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9216 22:50:16.367577 ARM64: Exception handlers installed.
9217 22:50:16.370653 ARM64: Testing exception
9218 22:50:16.374302 ARM64: Done test exception
9219 22:50:16.374388 Enumerating buses...
9220 22:50:16.377718 Show all devs... Before device enumeration.
9221 22:50:16.380816 Root Device: enabled 1
9222 22:50:16.384128 CPU_CLUSTER: 0: enabled 1
9223 22:50:16.384220 CPU: 00: enabled 1
9224 22:50:16.387219 Compare with tree...
9225 22:50:16.387336 Root Device: enabled 1
9226 22:50:16.390741 CPU_CLUSTER: 0: enabled 1
9227 22:50:16.394291 CPU: 00: enabled 1
9228 22:50:16.394369 Root Device scanning...
9229 22:50:16.397382 scan_static_bus for Root Device
9230 22:50:16.400616 CPU_CLUSTER: 0 enabled
9231 22:50:16.403800 scan_static_bus for Root Device done
9232 22:50:16.407078 scan_bus: bus Root Device finished in 8 msecs
9233 22:50:16.407232 done
9234 22:50:16.413903 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9235 22:50:16.417149 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9236 22:50:16.423678 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9237 22:50:16.427191 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9238 22:50:16.430120 Allocating resources...
9239 22:50:16.433505 Reading resources...
9240 22:50:16.436854 Root Device read_resources bus 0 link: 0
9241 22:50:16.440236 DRAM rank0 size:0x100000000,
9242 22:50:16.440316 DRAM rank1 size=0x100000000
9243 22:50:16.443651 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9244 22:50:16.447243 CPU: 00 missing read_resources
9245 22:50:16.453490 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9246 22:50:16.456876 Root Device read_resources bus 0 link: 0 done
9247 22:50:16.456957 Done reading resources.
9248 22:50:16.463360 Show resources in subtree (Root Device)...After reading.
9249 22:50:16.466824 Root Device child on link 0 CPU_CLUSTER: 0
9250 22:50:16.470350 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 22:50:16.480079 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 22:50:16.480161 CPU: 00
9253 22:50:16.483129 Root Device assign_resources, bus 0 link: 0
9254 22:50:16.486668 CPU_CLUSTER: 0 missing set_resources
9255 22:50:16.493173 Root Device assign_resources, bus 0 link: 0 done
9256 22:50:16.493350 Done setting resources.
9257 22:50:16.499730 Show resources in subtree (Root Device)...After assigning values.
9258 22:50:16.503427 Root Device child on link 0 CPU_CLUSTER: 0
9259 22:50:16.506342 CPU_CLUSTER: 0 child on link 0 CPU: 00
9260 22:50:16.516449 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9261 22:50:16.516535 CPU: 00
9262 22:50:16.519983 Done allocating resources.
9263 22:50:16.526554 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9264 22:50:16.526634 Enabling resources...
9265 22:50:16.526715 done.
9266 22:50:16.532671 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9267 22:50:16.536118 Initializing devices...
9268 22:50:16.536223 Root Device init
9269 22:50:16.539463 init hardware done!
9270 22:50:16.539544 0x00000018: ctrlr->caps
9271 22:50:16.542786 52.000 MHz: ctrlr->f_max
9272 22:50:16.546296 0.400 MHz: ctrlr->f_min
9273 22:50:16.546379 0x40ff8080: ctrlr->voltages
9274 22:50:16.549163 sclk: 390625
9275 22:50:16.549244 Bus Width = 1
9276 22:50:16.549306 sclk: 390625
9277 22:50:16.552617 Bus Width = 1
9278 22:50:16.552697 Early init status = 3
9279 22:50:16.559496 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9280 22:50:16.562837 in-header: 03 fc 00 00 01 00 00 00
9281 22:50:16.565772 in-data: 00
9282 22:50:16.569398 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9283 22:50:16.573940 in-header: 03 fd 00 00 00 00 00 00
9284 22:50:16.576772 in-data:
9285 22:50:16.580137 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9286 22:50:16.584713 in-header: 03 fc 00 00 01 00 00 00
9287 22:50:16.587876 in-data: 00
9288 22:50:16.591376 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9289 22:50:16.596728 in-header: 03 fd 00 00 00 00 00 00
9290 22:50:16.600173 in-data:
9291 22:50:16.603105 [SSUSB] Setting up USB HOST controller...
9292 22:50:16.606739 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9293 22:50:16.609991 [SSUSB] phy power-on done.
9294 22:50:16.612956 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9295 22:50:16.619787 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9296 22:50:16.623654 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9297 22:50:16.630014 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9298 22:50:16.636088 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9299 22:50:16.642952 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9300 22:50:16.649407 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9301 22:50:16.656330 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9302 22:50:16.659830 SPM: binary array size = 0x9dc
9303 22:50:16.662635 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9304 22:50:16.669787 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9305 22:50:16.676102 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9306 22:50:16.683003 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9307 22:50:16.686267 configure_display: Starting display init
9308 22:50:16.719833 anx7625_power_on_init: Init interface.
9309 22:50:16.723398 anx7625_disable_pd_protocol: Disabled PD feature.
9310 22:50:16.726851 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9311 22:50:16.754395 anx7625_start_dp_work: Secure OCM version=00
9312 22:50:16.757797 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9313 22:50:16.772637 sp_tx_get_edid_block: EDID Block = 1
9314 22:50:16.875137 Extracted contents:
9315 22:50:16.878069 header: 00 ff ff ff ff ff ff 00
9316 22:50:16.881383 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9317 22:50:16.884847 version: 01 04
9318 22:50:16.888363 basic params: 95 1f 11 78 0a
9319 22:50:16.891824 chroma info: 76 90 94 55 54 90 27 21 50 54
9320 22:50:16.895170 established: 00 00 00
9321 22:50:16.901433 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9322 22:50:16.904899 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9323 22:50:16.911355 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9324 22:50:16.918171 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9325 22:50:16.925133 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9326 22:50:16.927915 extensions: 00
9327 22:50:16.927996 checksum: fb
9328 22:50:16.928079
9329 22:50:16.931263 Manufacturer: IVO Model 57d Serial Number 0
9330 22:50:16.934417 Made week 0 of 2020
9331 22:50:16.934515 EDID version: 1.4
9332 22:50:16.938140 Digital display
9333 22:50:16.940954 6 bits per primary color channel
9334 22:50:16.941034 DisplayPort interface
9335 22:50:16.944448 Maximum image size: 31 cm x 17 cm
9336 22:50:16.947863 Gamma: 220%
9337 22:50:16.947937 Check DPMS levels
9338 22:50:16.951038 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9339 22:50:16.954561 First detailed timing is preferred timing
9340 22:50:16.957694 Established timings supported:
9341 22:50:16.961041 Standard timings supported:
9342 22:50:16.964551 Detailed timings
9343 22:50:16.967776 Hex of detail: 383680a07038204018303c0035ae10000019
9344 22:50:16.971309 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9345 22:50:16.977764 0780 0798 07c8 0820 hborder 0
9346 22:50:16.981211 0438 043b 0447 0458 vborder 0
9347 22:50:16.984771 -hsync -vsync
9348 22:50:16.984843 Did detailed timing
9349 22:50:16.991168 Hex of detail: 000000000000000000000000000000000000
9350 22:50:16.991246 Manufacturer-specified data, tag 0
9351 22:50:16.997841 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9352 22:50:17.000721 ASCII string: InfoVision
9353 22:50:17.004147 Hex of detail: 000000fe00523134304e574635205248200a
9354 22:50:17.007499 ASCII string: R140NWF5 RH
9355 22:50:17.007569 Checksum
9356 22:50:17.010934 Checksum: 0xfb (valid)
9357 22:50:17.014246 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9358 22:50:17.017389 DSI data_rate: 832800000 bps
9359 22:50:17.024315 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9360 22:50:17.027730 anx7625_parse_edid: pixelclock(138800).
9361 22:50:17.030566 hactive(1920), hsync(48), hfp(24), hbp(88)
9362 22:50:17.034033 vactive(1080), vsync(12), vfp(3), vbp(17)
9363 22:50:17.037440 anx7625_dsi_config: config dsi.
9364 22:50:17.043764 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9365 22:50:17.056883 anx7625_dsi_config: success to config DSI
9366 22:50:17.060462 anx7625_dp_start: MIPI phy setup OK.
9367 22:50:17.063745 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9368 22:50:17.067232 mtk_ddp_mode_set invalid vrefresh 60
9369 22:50:17.070397 main_disp_path_setup
9370 22:50:17.070475 ovl_layer_smi_id_en
9371 22:50:17.073417 ovl_layer_smi_id_en
9372 22:50:17.073568 ccorr_config
9373 22:50:17.073667 aal_config
9374 22:50:17.077182 gamma_config
9375 22:50:17.077260 postmask_config
9376 22:50:17.080132 dither_config
9377 22:50:17.083507 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9378 22:50:17.090177 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9379 22:50:17.093429 Root Device init finished in 553 msecs
9380 22:50:17.096686 CPU_CLUSTER: 0 init
9381 22:50:17.103534 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9382 22:50:17.106788 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9383 22:50:17.110378 APU_MBOX 0x190000b0 = 0x10001
9384 22:50:17.113298 APU_MBOX 0x190001b0 = 0x10001
9385 22:50:17.116723 APU_MBOX 0x190005b0 = 0x10001
9386 22:50:17.120022 APU_MBOX 0x190006b0 = 0x10001
9387 22:50:17.123756 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9388 22:50:17.136168 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9389 22:50:17.148361 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9390 22:50:17.155012 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9391 22:50:17.166964 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9392 22:50:17.175703 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9393 22:50:17.179403 CPU_CLUSTER: 0 init finished in 81 msecs
9394 22:50:17.182904 Devices initialized
9395 22:50:17.186132 Show all devs... After init.
9396 22:50:17.186212 Root Device: enabled 1
9397 22:50:17.189226 CPU_CLUSTER: 0: enabled 1
9398 22:50:17.192651 CPU: 00: enabled 1
9399 22:50:17.195903 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9400 22:50:17.199410 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9401 22:50:17.202364 ELOG: NV offset 0x57f000 size 0x1000
9402 22:50:17.208836 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9403 22:50:17.215251 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9404 22:50:17.218763 ELOG: Event(17) added with size 13 at 2024-05-07 22:50:18 UTC
9405 22:50:17.225432 out: cmd=0x121: 03 db 21 01 00 00 00 00
9406 22:50:17.228726 in-header: 03 72 00 00 2c 00 00 00
9407 22:50:17.238421 in-data: ed 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9408 22:50:17.245293 ELOG: Event(A1) added with size 10 at 2024-05-07 22:50:18 UTC
9409 22:50:17.252213 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9410 22:50:17.258410 ELOG: Event(A0) added with size 9 at 2024-05-07 22:50:18 UTC
9411 22:50:17.262236 elog_add_boot_reason: Logged dev mode boot
9412 22:50:17.268545 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9413 22:50:17.268626 Finalize devices...
9414 22:50:17.272002 Devices finalized
9415 22:50:17.275295 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9416 22:50:17.278684 Writing coreboot table at 0xffe64000
9417 22:50:17.281507 0. 000000000010a000-0000000000113fff: RAMSTAGE
9418 22:50:17.284985 1. 0000000040000000-00000000400fffff: RAM
9419 22:50:17.291664 2. 0000000040100000-000000004032afff: RAMSTAGE
9420 22:50:17.295330 3. 000000004032b000-00000000545fffff: RAM
9421 22:50:17.298298 4. 0000000054600000-000000005465ffff: BL31
9422 22:50:17.301416 5. 0000000054660000-00000000ffe63fff: RAM
9423 22:50:17.308523 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9424 22:50:17.311724 7. 0000000100000000-000000023fffffff: RAM
9425 22:50:17.314972 Passing 5 GPIOs to payload:
9426 22:50:17.318199 NAME | PORT | POLARITY | VALUE
9427 22:50:17.321702 EC in RW | 0x000000aa | low | undefined
9428 22:50:17.328102 EC interrupt | 0x00000005 | low | undefined
9429 22:50:17.331366 TPM interrupt | 0x000000ab | high | undefined
9430 22:50:17.338323 SD card detect | 0x00000011 | high | undefined
9431 22:50:17.341794 speaker enable | 0x00000093 | high | undefined
9432 22:50:17.344635 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9433 22:50:17.348213 in-header: 03 f9 00 00 02 00 00 00
9434 22:50:17.351177 in-data: 02 00
9435 22:50:17.351257 ADC[4]: Raw value=894081 ID=7
9436 22:50:17.354642 ADC[3]: Raw value=212700 ID=1
9437 22:50:17.358123 RAM Code: 0x71
9438 22:50:17.361393 ADC[6]: Raw value=74722 ID=0
9439 22:50:17.361473 ADC[5]: Raw value=211590 ID=1
9440 22:50:17.364797 SKU Code: 0x1
9441 22:50:17.367979 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d956
9442 22:50:17.370962 coreboot table: 964 bytes.
9443 22:50:17.374288 IMD ROOT 0. 0xfffff000 0x00001000
9444 22:50:17.377718 IMD SMALL 1. 0xffffe000 0x00001000
9445 22:50:17.380962 RO MCACHE 2. 0xffffc000 0x00001104
9446 22:50:17.384474 CONSOLE 3. 0xfff7c000 0x00080000
9447 22:50:17.387397 FMAP 4. 0xfff7b000 0x00000452
9448 22:50:17.390915 TIME STAMP 5. 0xfff7a000 0x00000910
9449 22:50:17.394340 VBOOT WORK 6. 0xfff66000 0x00014000
9450 22:50:17.397712 RAMOOPS 7. 0xffe66000 0x00100000
9451 22:50:17.400966 COREBOOT 8. 0xffe64000 0x00002000
9452 22:50:17.404230 IMD small region:
9453 22:50:17.407527 IMD ROOT 0. 0xffffec00 0x00000400
9454 22:50:17.410993 VPD 1. 0xffffeb80 0x0000006c
9455 22:50:17.414222 MMC STATUS 2. 0xffffeb60 0x00000004
9456 22:50:17.417223 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9457 22:50:17.420997 Probing TPM: done!
9458 22:50:17.424219 Connected to device vid:did:rid of 1ae0:0028:00
9459 22:50:17.435009 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9460 22:50:17.438222 Initialized TPM device CR50 revision 0
9461 22:50:17.442283 Checking cr50 for pending updates
9462 22:50:17.445420 Reading cr50 TPM mode
9463 22:50:17.454218 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9464 22:50:17.460546 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9465 22:50:17.501026 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9466 22:50:17.504480 Checking segment from ROM address 0x40100000
9467 22:50:17.507322 Checking segment from ROM address 0x4010001c
9468 22:50:17.514132 Loading segment from ROM address 0x40100000
9469 22:50:17.514213 code (compression=0)
9470 22:50:17.520772 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9471 22:50:17.531002 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9472 22:50:17.531089 it's not compressed!
9473 22:50:17.537482 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9474 22:50:17.540952 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9475 22:50:17.561622 Loading segment from ROM address 0x4010001c
9476 22:50:17.561704 Entry Point 0x80000000
9477 22:50:17.564895 Loaded segments
9478 22:50:17.567724 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9479 22:50:17.574356 Jumping to boot code at 0x80000000(0xffe64000)
9480 22:50:17.581196 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9481 22:50:17.587874 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9482 22:50:17.595762 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9483 22:50:17.599133 Checking segment from ROM address 0x40100000
9484 22:50:17.602602 Checking segment from ROM address 0x4010001c
9485 22:50:17.609089 Loading segment from ROM address 0x40100000
9486 22:50:17.609170 code (compression=1)
9487 22:50:17.615855 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9488 22:50:17.625377 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9489 22:50:17.625458 using LZMA
9490 22:50:17.634065 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9491 22:50:17.640735 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9492 22:50:17.643977 Loading segment from ROM address 0x4010001c
9493 22:50:17.644058 Entry Point 0x54601000
9494 22:50:17.647183 Loaded segments
9495 22:50:17.650461 NOTICE: MT8192 bl31_setup
9496 22:50:17.657654 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9497 22:50:17.661161 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9498 22:50:17.664027 WARNING: region 0:
9499 22:50:17.667772 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 22:50:17.667854 WARNING: region 1:
9501 22:50:17.674381 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9502 22:50:17.677444 WARNING: region 2:
9503 22:50:17.680844 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9504 22:50:17.683986 WARNING: region 3:
9505 22:50:17.687457 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 22:50:17.691163 WARNING: region 4:
9507 22:50:17.697686 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 22:50:17.697826 WARNING: region 5:
9509 22:50:17.701197 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 22:50:17.704100 WARNING: region 6:
9511 22:50:17.707498 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 22:50:17.711094 WARNING: region 7:
9513 22:50:17.714501 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 22:50:17.721177 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9515 22:50:17.724478 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9516 22:50:17.727687 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9517 22:50:17.734223 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9518 22:50:17.737485 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9519 22:50:17.741014 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9520 22:50:17.747954 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9521 22:50:17.750832 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9522 22:50:17.757456 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9523 22:50:17.760712 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9524 22:50:17.764224 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9525 22:50:17.771093 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9526 22:50:17.774527 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9527 22:50:17.777464 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9528 22:50:17.784133 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9529 22:50:17.787450 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9530 22:50:17.794332 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9531 22:50:17.797258 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9532 22:50:17.800856 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9533 22:50:17.807717 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9534 22:50:17.810868 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9535 22:50:17.813893 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9536 22:50:17.820689 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9537 22:50:17.823907 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9538 22:50:17.830674 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9539 22:50:17.834034 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9540 22:50:17.837400 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9541 22:50:17.843751 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9542 22:50:17.847176 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9543 22:50:17.853962 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9544 22:50:17.857389 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9545 22:50:17.860278 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9546 22:50:17.867054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9547 22:50:17.870362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9548 22:50:17.873792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9549 22:50:17.877271 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9550 22:50:17.883734 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9551 22:50:17.887221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9552 22:50:17.890644 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9553 22:50:17.894190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9554 22:50:17.900400 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9555 22:50:17.903784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9556 22:50:17.907035 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9557 22:50:17.910697 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9558 22:50:17.917179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9559 22:50:17.920845 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9560 22:50:17.924071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9561 22:50:17.927495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9562 22:50:17.934495 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9563 22:50:17.937417 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9564 22:50:17.944293 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9565 22:50:17.947100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9566 22:50:17.953770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9567 22:50:17.957363 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9568 22:50:17.960401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9569 22:50:17.967321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9570 22:50:17.970721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9571 22:50:17.976977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9572 22:50:17.980463 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9573 22:50:17.987142 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9574 22:50:17.990644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9575 22:50:17.993525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9576 22:50:18.000361 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9577 22:50:18.003777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9578 22:50:18.010421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9579 22:50:18.013826 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9580 22:50:18.020479 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9581 22:50:18.023937 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9582 22:50:18.027424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9583 22:50:18.033702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9584 22:50:18.037231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9585 22:50:18.044039 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9586 22:50:18.047228 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9587 22:50:18.053894 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9588 22:50:18.057101 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9589 22:50:18.060208 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9590 22:50:18.067437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9591 22:50:18.070349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9592 22:50:18.076976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9593 22:50:18.080360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9594 22:50:18.087250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9595 22:50:18.090670 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9596 22:50:18.097007 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9597 22:50:18.100743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9598 22:50:18.103788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9599 22:50:18.110414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9600 22:50:18.113924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9601 22:50:18.120290 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9602 22:50:18.123983 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9603 22:50:18.127104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9604 22:50:18.134043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9605 22:50:18.136842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9606 22:50:18.143693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9607 22:50:18.146926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9608 22:50:18.153997 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9609 22:50:18.157373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9610 22:50:18.160619 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9611 22:50:18.167308 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9612 22:50:18.170904 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9613 22:50:18.173658 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9614 22:50:18.176951 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9615 22:50:18.183756 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9616 22:50:18.187122 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9617 22:50:18.194186 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9618 22:50:18.196918 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9619 22:50:18.200352 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9620 22:50:18.207159 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9621 22:50:18.210444 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9622 22:50:18.216970 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9623 22:50:18.220612 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9624 22:50:18.223488 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9625 22:50:18.230268 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9626 22:50:18.233917 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9627 22:50:18.240513 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9628 22:50:18.243623 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9629 22:50:18.247111 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9630 22:50:18.250605 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9631 22:50:18.257485 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9632 22:50:18.260894 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9633 22:50:18.264386 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9634 22:50:18.270755 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9635 22:50:18.274239 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9636 22:50:18.277119 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9637 22:50:18.280814 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9638 22:50:18.287176 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9639 22:50:18.290671 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9640 22:50:18.297126 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9641 22:50:18.300961 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9642 22:50:18.303770 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9643 22:50:18.310624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9644 22:50:18.314077 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9645 22:50:18.317485 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9646 22:50:18.323681 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9647 22:50:18.327369 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9648 22:50:18.333978 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9649 22:50:18.337251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9650 22:50:18.340779 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9651 22:50:18.346993 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9652 22:50:18.350953 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9653 22:50:18.357369 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9654 22:50:18.360620 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9655 22:50:18.363715 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9656 22:50:18.370398 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9657 22:50:18.373888 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9658 22:50:18.377220 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9659 22:50:18.384057 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9660 22:50:18.387511 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9661 22:50:18.393734 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9662 22:50:18.397376 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9663 22:50:18.400800 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9664 22:50:18.407267 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9665 22:50:18.410843 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9666 22:50:18.417145 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9667 22:50:18.420482 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9668 22:50:18.424129 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9669 22:50:18.430807 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9670 22:50:18.433825 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9671 22:50:18.440860 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9672 22:50:18.443981 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9673 22:50:18.447090 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9674 22:50:18.454039 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9675 22:50:18.457011 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9676 22:50:18.460507 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9677 22:50:18.467430 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9678 22:50:18.470631 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9679 22:50:18.477204 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9680 22:50:18.480651 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9681 22:50:18.483753 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9682 22:50:18.490350 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9683 22:50:18.493781 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9684 22:50:18.500143 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9685 22:50:18.503625 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9686 22:50:18.507100 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9687 22:50:18.513223 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9688 22:50:18.517213 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9689 22:50:18.523254 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9690 22:50:18.527016 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9691 22:50:18.530395 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9692 22:50:18.536587 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9693 22:50:18.540097 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9694 22:50:18.546848 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9695 22:50:18.549638 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9696 22:50:18.553150 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9697 22:50:18.559592 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9698 22:50:18.563110 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9699 22:50:18.569652 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9700 22:50:18.573063 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9701 22:50:18.576240 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9702 22:50:18.583023 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9703 22:50:18.586198 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9704 22:50:18.592894 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9705 22:50:18.596235 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9706 22:50:18.599734 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9707 22:50:18.606375 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9708 22:50:18.609569 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9709 22:50:18.616511 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9710 22:50:18.619805 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9711 22:50:18.623378 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9712 22:50:18.629708 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9713 22:50:18.633093 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9714 22:50:18.639759 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9715 22:50:18.643086 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9716 22:50:18.649345 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9717 22:50:18.652737 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9718 22:50:18.656236 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9719 22:50:18.662540 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9720 22:50:18.665825 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9721 22:50:18.672536 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9722 22:50:18.675867 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9723 22:50:18.679105 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9724 22:50:18.685916 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9725 22:50:18.689122 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9726 22:50:18.695770 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9727 22:50:18.698981 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9728 22:50:18.705932 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9729 22:50:18.708837 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9730 22:50:18.712525 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9731 22:50:18.719245 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9732 22:50:18.722575 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9733 22:50:18.729385 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9734 22:50:18.732347 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9735 22:50:18.735846 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9736 22:50:18.742143 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9737 22:50:18.745709 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9738 22:50:18.752145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9739 22:50:18.755462 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9740 22:50:18.762414 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9741 22:50:18.765164 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9742 22:50:18.768631 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9743 22:50:18.775220 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9744 22:50:18.778638 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9745 22:50:18.782137 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9746 22:50:18.785710 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9747 22:50:18.789109 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9748 22:50:18.795265 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9749 22:50:18.799076 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9750 22:50:18.804994 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9751 22:50:18.808640 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9752 22:50:18.812056 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9753 22:50:18.818130 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9754 22:50:18.821756 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9755 22:50:18.828310 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9756 22:50:18.831741 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9757 22:50:18.834728 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9758 22:50:18.841496 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9759 22:50:18.844537 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9760 22:50:18.848473 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9761 22:50:18.854665 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9762 22:50:18.857870 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9763 22:50:18.864723 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9764 22:50:18.867917 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9765 22:50:18.871428 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9766 22:50:18.877486 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9767 22:50:18.881418 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9768 22:50:18.884259 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9769 22:50:18.891199 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9770 22:50:18.894519 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9771 22:50:18.901102 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9772 22:50:18.904635 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9773 22:50:18.907567 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9774 22:50:18.914560 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9775 22:50:18.917763 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9776 22:50:18.921000 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9777 22:50:18.927613 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9778 22:50:18.930742 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9779 22:50:18.933904 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9780 22:50:18.940505 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9781 22:50:18.943992 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9782 22:50:18.947309 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9783 22:50:18.954346 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9784 22:50:18.957232 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9785 22:50:18.960640 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9786 22:50:18.964181 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9787 22:50:18.967616 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9788 22:50:18.974106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9789 22:50:18.977653 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9790 22:50:18.980598 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9791 22:50:18.987351 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9792 22:50:18.990538 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9793 22:50:18.993877 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9794 22:50:18.997335 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9795 22:50:19.003764 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9796 22:50:19.007239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9797 22:50:19.013556 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9798 22:50:19.016865 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9799 22:50:19.020636 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9800 22:50:19.027140 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9801 22:50:19.030335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9802 22:50:19.036911 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9803 22:50:19.040358 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9804 22:50:19.043419 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9805 22:50:19.050135 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9806 22:50:19.053292 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9807 22:50:19.060017 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9808 22:50:19.063501 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9809 22:50:19.070308 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9810 22:50:19.073200 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9811 22:50:19.076677 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9812 22:50:19.083253 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9813 22:50:19.086603 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9814 22:50:19.092914 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9815 22:50:19.096522 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9816 22:50:19.099866 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9817 22:50:19.106311 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9818 22:50:19.110216 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9819 22:50:19.116324 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9820 22:50:19.119592 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9821 22:50:19.122869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9822 22:50:19.129887 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9823 22:50:19.133383 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9824 22:50:19.139533 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9825 22:50:19.142888 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9826 22:50:19.149628 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9827 22:50:19.152737 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9828 22:50:19.156307 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9829 22:50:19.162550 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9830 22:50:19.165874 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9831 22:50:19.172334 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9832 22:50:19.176310 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9833 22:50:19.179112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9834 22:50:19.186072 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9835 22:50:19.189344 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9836 22:50:19.195624 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9837 22:50:19.199126 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9838 22:50:19.202526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9839 22:50:19.209172 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9840 22:50:19.212907 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9841 22:50:19.219359 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9842 22:50:19.222537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9843 22:50:19.225937 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9844 22:50:19.232163 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9845 22:50:19.235904 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9846 22:50:19.242161 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9847 22:50:19.245652 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9848 22:50:19.252057 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9849 22:50:19.255376 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9850 22:50:19.258846 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9851 22:50:19.265745 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9852 22:50:19.268525 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9853 22:50:19.275185 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9854 22:50:19.278747 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9855 22:50:19.281644 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9856 22:50:19.288394 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9857 22:50:19.291791 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9858 22:50:19.298654 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9859 22:50:19.302129 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9860 22:50:19.305412 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9861 22:50:19.311762 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9862 22:50:19.315045 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9863 22:50:19.321988 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9864 22:50:19.325275 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9865 22:50:19.331728 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9866 22:50:19.334930 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9867 22:50:19.338443 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9868 22:50:19.344864 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9869 22:50:19.348135 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9870 22:50:19.355123 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9871 22:50:19.358385 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9872 22:50:19.364728 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9873 22:50:19.368176 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9874 22:50:19.375062 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9875 22:50:19.378233 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9876 22:50:19.381256 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9877 22:50:19.387988 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9878 22:50:19.391473 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9879 22:50:19.398119 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9880 22:50:19.401029 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9881 22:50:19.407702 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9882 22:50:19.411088 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9883 22:50:19.414469 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9884 22:50:19.421317 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9885 22:50:19.424084 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9886 22:50:19.430789 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9887 22:50:19.434276 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9888 22:50:19.440909 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9889 22:50:19.443964 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9890 22:50:19.450978 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9891 22:50:19.453850 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9892 22:50:19.457267 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9893 22:50:19.463868 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9894 22:50:19.467040 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9895 22:50:19.473670 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9896 22:50:19.477037 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9897 22:50:19.483622 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9898 22:50:19.487125 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9899 22:50:19.490390 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9900 22:50:19.497144 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9901 22:50:19.500171 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9902 22:50:19.506992 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9903 22:50:19.510412 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9904 22:50:19.516709 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9905 22:50:19.520156 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9906 22:50:19.526829 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9907 22:50:19.530421 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9908 22:50:19.533189 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9909 22:50:19.540032 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9910 22:50:19.543515 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9911 22:50:19.549899 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9912 22:50:19.553425 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9913 22:50:19.560066 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9914 22:50:19.563524 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9915 22:50:19.566951 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9916 22:50:19.573416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9917 22:50:19.576928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9918 22:50:19.583249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9919 22:50:19.586661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9920 22:50:19.593277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9921 22:50:19.596726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9922 22:50:19.600261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9923 22:50:19.606670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9924 22:50:19.610507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9925 22:50:19.617121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9926 22:50:19.620177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9927 22:50:19.626887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9928 22:50:19.630359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9929 22:50:19.636766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9930 22:50:19.639973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9931 22:50:19.646750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9932 22:50:19.650123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9933 22:50:19.656501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9934 22:50:19.659921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9935 22:50:19.666689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9936 22:50:19.669851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9937 22:50:19.676663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9938 22:50:19.680083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9939 22:50:19.686567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9940 22:50:19.689914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9941 22:50:19.696579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9942 22:50:19.699842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9943 22:50:19.706897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9944 22:50:19.709752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9945 22:50:19.716808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9946 22:50:19.720106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9947 22:50:19.726435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9948 22:50:19.729653 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9949 22:50:19.732638 INFO: [APUAPC] vio 0
9950 22:50:19.736242 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9951 22:50:19.739896 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9952 22:50:19.743192 INFO: [APUAPC] D0_APC_0: 0x400510
9953 22:50:19.746403 INFO: [APUAPC] D0_APC_1: 0x0
9954 22:50:19.749400 INFO: [APUAPC] D0_APC_2: 0x1540
9955 22:50:19.752824 INFO: [APUAPC] D0_APC_3: 0x0
9956 22:50:19.756212 INFO: [APUAPC] D1_APC_0: 0xffffffff
9957 22:50:19.759606 INFO: [APUAPC] D1_APC_1: 0xffffffff
9958 22:50:19.762908 INFO: [APUAPC] D1_APC_2: 0x3fffff
9959 22:50:19.766315 INFO: [APUAPC] D1_APC_3: 0x0
9960 22:50:19.769758 INFO: [APUAPC] D2_APC_0: 0xffffffff
9961 22:50:19.773132 INFO: [APUAPC] D2_APC_1: 0xffffffff
9962 22:50:19.776400 INFO: [APUAPC] D2_APC_2: 0x3fffff
9963 22:50:19.779632 INFO: [APUAPC] D2_APC_3: 0x0
9964 22:50:19.782847 INFO: [APUAPC] D3_APC_0: 0xffffffff
9965 22:50:19.786377 INFO: [APUAPC] D3_APC_1: 0xffffffff
9966 22:50:19.789245 INFO: [APUAPC] D3_APC_2: 0x3fffff
9967 22:50:19.792394 INFO: [APUAPC] D3_APC_3: 0x0
9968 22:50:19.795675 INFO: [APUAPC] D4_APC_0: 0xffffffff
9969 22:50:19.798971 INFO: [APUAPC] D4_APC_1: 0xffffffff
9970 22:50:19.802452 INFO: [APUAPC] D4_APC_2: 0x3fffff
9971 22:50:19.805900 INFO: [APUAPC] D4_APC_3: 0x0
9972 22:50:19.809235 INFO: [APUAPC] D5_APC_0: 0xffffffff
9973 22:50:19.812308 INFO: [APUAPC] D5_APC_1: 0xffffffff
9974 22:50:19.815670 INFO: [APUAPC] D5_APC_2: 0x3fffff
9975 22:50:19.819011 INFO: [APUAPC] D5_APC_3: 0x0
9976 22:50:19.822467 INFO: [APUAPC] D6_APC_0: 0xffffffff
9977 22:50:19.825447 INFO: [APUAPC] D6_APC_1: 0xffffffff
9978 22:50:19.829038 INFO: [APUAPC] D6_APC_2: 0x3fffff
9979 22:50:19.832278 INFO: [APUAPC] D6_APC_3: 0x0
9980 22:50:19.835642 INFO: [APUAPC] D7_APC_0: 0xffffffff
9981 22:50:19.839225 INFO: [APUAPC] D7_APC_1: 0xffffffff
9982 22:50:19.842297 INFO: [APUAPC] D7_APC_2: 0x3fffff
9983 22:50:19.845706 INFO: [APUAPC] D7_APC_3: 0x0
9984 22:50:19.849067 INFO: [APUAPC] D8_APC_0: 0xffffffff
9985 22:50:19.852364 INFO: [APUAPC] D8_APC_1: 0xffffffff
9986 22:50:19.855505 INFO: [APUAPC] D8_APC_2: 0x3fffff
9987 22:50:19.858958 INFO: [APUAPC] D8_APC_3: 0x0
9988 22:50:19.862351 INFO: [APUAPC] D9_APC_0: 0xffffffff
9989 22:50:19.865649 INFO: [APUAPC] D9_APC_1: 0xffffffff
9990 22:50:19.868549 INFO: [APUAPC] D9_APC_2: 0x3fffff
9991 22:50:19.868631 INFO: [APUAPC] D9_APC_3: 0x0
9992 22:50:19.875573 INFO: [APUAPC] D10_APC_0: 0xffffffff
9993 22:50:19.878930 INFO: [APUAPC] D10_APC_1: 0xffffffff
9994 22:50:19.882546 INFO: [APUAPC] D10_APC_2: 0x3fffff
9995 22:50:19.885294 INFO: [APUAPC] D10_APC_3: 0x0
9996 22:50:19.888589 INFO: [APUAPC] D11_APC_0: 0xffffffff
9997 22:50:19.891883 INFO: [APUAPC] D11_APC_1: 0xffffffff
9998 22:50:19.895534 INFO: [APUAPC] D11_APC_2: 0x3fffff
9999 22:50:19.898757 INFO: [APUAPC] D11_APC_3: 0x0
10000 22:50:19.902005 INFO: [APUAPC] D12_APC_0: 0xffffffff
10001 22:50:19.905484 INFO: [APUAPC] D12_APC_1: 0xffffffff
10002 22:50:19.908818 INFO: [APUAPC] D12_APC_2: 0x3fffff
10003 22:50:19.912333 INFO: [APUAPC] D12_APC_3: 0x0
10004 22:50:19.915535 INFO: [APUAPC] D13_APC_0: 0xffffffff
10005 22:50:19.918968 INFO: [APUAPC] D13_APC_1: 0xffffffff
10006 22:50:19.921765 INFO: [APUAPC] D13_APC_2: 0x3fffff
10007 22:50:19.925065 INFO: [APUAPC] D13_APC_3: 0x0
10008 22:50:19.928471 INFO: [APUAPC] D14_APC_0: 0xffffffff
10009 22:50:19.932077 INFO: [APUAPC] D14_APC_1: 0xffffffff
10010 22:50:19.935395 INFO: [APUAPC] D14_APC_2: 0x3fffff
10011 22:50:19.938719 INFO: [APUAPC] D14_APC_3: 0x0
10012 22:50:19.942117 INFO: [APUAPC] D15_APC_0: 0xffffffff
10013 22:50:19.945316 INFO: [APUAPC] D15_APC_1: 0xffffffff
10014 22:50:19.948750 INFO: [APUAPC] D15_APC_2: 0x3fffff
10015 22:50:19.951689 INFO: [APUAPC] D15_APC_3: 0x0
10016 22:50:19.951770 INFO: [APUAPC] APC_CON: 0x4
10017 22:50:19.954917 INFO: [NOCDAPC] D0_APC_0: 0x0
10018 22:50:19.958290 INFO: [NOCDAPC] D0_APC_1: 0x0
10019 22:50:19.961881 INFO: [NOCDAPC] D1_APC_0: 0x0
10020 22:50:19.965333 INFO: [NOCDAPC] D1_APC_1: 0xfff
10021 22:50:19.968685 INFO: [NOCDAPC] D2_APC_0: 0x0
10022 22:50:19.971869 INFO: [NOCDAPC] D2_APC_1: 0xfff
10023 22:50:19.974805 INFO: [NOCDAPC] D3_APC_0: 0x0
10024 22:50:19.978244 INFO: [NOCDAPC] D3_APC_1: 0xfff
10025 22:50:19.981716 INFO: [NOCDAPC] D4_APC_0: 0x0
10026 22:50:19.985099 INFO: [NOCDAPC] D4_APC_1: 0xfff
10027 22:50:19.985180 INFO: [NOCDAPC] D5_APC_0: 0x0
10028 22:50:19.988626 INFO: [NOCDAPC] D5_APC_1: 0xfff
10029 22:50:19.991565 INFO: [NOCDAPC] D6_APC_0: 0x0
10030 22:50:19.994963 INFO: [NOCDAPC] D6_APC_1: 0xfff
10031 22:50:19.998159 INFO: [NOCDAPC] D7_APC_0: 0x0
10032 22:50:20.001584 INFO: [NOCDAPC] D7_APC_1: 0xfff
10033 22:50:20.005064 INFO: [NOCDAPC] D8_APC_0: 0x0
10034 22:50:20.008285 INFO: [NOCDAPC] D8_APC_1: 0xfff
10035 22:50:20.011412 INFO: [NOCDAPC] D9_APC_0: 0x0
10036 22:50:20.014760 INFO: [NOCDAPC] D9_APC_1: 0xfff
10037 22:50:20.017776 INFO: [NOCDAPC] D10_APC_0: 0x0
10038 22:50:20.021483 INFO: [NOCDAPC] D10_APC_1: 0xfff
10039 22:50:20.021604 INFO: [NOCDAPC] D11_APC_0: 0x0
10040 22:50:20.024516 INFO: [NOCDAPC] D11_APC_1: 0xfff
10041 22:50:20.028090 INFO: [NOCDAPC] D12_APC_0: 0x0
10042 22:50:20.031089 INFO: [NOCDAPC] D12_APC_1: 0xfff
10043 22:50:20.034773 INFO: [NOCDAPC] D13_APC_0: 0x0
10044 22:50:20.037876 INFO: [NOCDAPC] D13_APC_1: 0xfff
10045 22:50:20.041263 INFO: [NOCDAPC] D14_APC_0: 0x0
10046 22:50:20.044535 INFO: [NOCDAPC] D14_APC_1: 0xfff
10047 22:50:20.047975 INFO: [NOCDAPC] D15_APC_0: 0x0
10048 22:50:20.051174 INFO: [NOCDAPC] D15_APC_1: 0xfff
10049 22:50:20.054657 INFO: [NOCDAPC] APC_CON: 0x4
10050 22:50:20.057907 INFO: [APUAPC] set_apusys_apc done
10051 22:50:20.061099 INFO: [DEVAPC] devapc_init done
10052 22:50:20.064698 INFO: GICv3 without legacy support detected.
10053 22:50:20.067470 INFO: ARM GICv3 driver initialized in EL3
10054 22:50:20.070822 INFO: Maximum SPI INTID supported: 639
10055 22:50:20.074413 INFO: BL31: Initializing runtime services
10056 22:50:20.081152 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10057 22:50:20.084026 INFO: SPM: enable CPC mode
10058 22:50:20.090891 INFO: mcdi ready for mcusys-off-idle and system suspend
10059 22:50:20.094328 INFO: BL31: Preparing for EL3 exit to normal world
10060 22:50:20.097737 INFO: Entry point address = 0x80000000
10061 22:50:20.101027 INFO: SPSR = 0x8
10062 22:50:20.105503
10063 22:50:20.105624
10064 22:50:20.105704
10065 22:50:20.109129 Starting depthcharge on Spherion...
10066 22:50:20.109236
10067 22:50:20.109316 Wipe memory regions:
10068 22:50:20.109375
10069 22:50:20.110018 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10070 22:50:20.110115 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10071 22:50:20.110197 Setting prompt string to ['asurada:']
10072 22:50:20.110277 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10073 22:50:20.112485 [0x00000040000000, 0x00000054600000)
10074 22:50:20.234473
10075 22:50:20.234585 [0x00000054660000, 0x00000080000000)
10076 22:50:20.494980
10077 22:50:20.495114 [0x000000821a7280, 0x000000ffe64000)
10078 22:50:21.239840
10079 22:50:21.239974 [0x00000100000000, 0x00000240000000)
10080 22:50:23.128949
10081 22:50:23.131906 Initializing XHCI USB controller at 0x11200000.
10082 22:50:24.169928
10083 22:50:24.173132 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10084 22:50:24.173220
10085 22:50:24.173283
10086 22:50:24.173342
10087 22:50:24.173626 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 22:50:24.273970 asurada: tftpboot 192.168.201.1 13683708/tftp-deploy-okay74ba/kernel/image.itb 13683708/tftp-deploy-okay74ba/kernel/cmdline
10090 22:50:24.274093 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 22:50:24.274176 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10092 22:50:24.278615 tftpboot 192.168.201.1 13683708/tftp-deploy-okay74ba/kernel/image.itp-deploy-okay74ba/kernel/cmdline
10093 22:50:24.278697
10094 22:50:24.278761 Waiting for link
10095 22:50:24.439132
10096 22:50:24.439240 R8152: Initializing
10097 22:50:24.439303
10098 22:50:24.442175 Version 6 (ocp_data = 5c30)
10099 22:50:24.442255
10100 22:50:24.445485 R8152: Done initializing
10101 22:50:24.445598
10102 22:50:24.445694 Adding net device
10103 22:50:26.348973
10104 22:50:26.349121 done.
10105 22:50:26.349189
10106 22:50:26.349277 MAC: 00:24:32:30:78:ff
10107 22:50:26.349336
10108 22:50:26.352468 Sending DHCP discover... done.
10109 22:50:26.352570
10110 22:50:34.890765 Waiting for reply... done.
10111 22:50:34.890913
10112 22:50:34.890981 Sending DHCP request... done.
10113 22:50:34.894138
10114 22:50:34.898178 Waiting for reply... done.
10115 22:50:34.898262
10116 22:50:34.898346 My ip is 192.168.201.21
10117 22:50:34.898426
10118 22:50:34.901472 The DHCP server ip is 192.168.201.1
10119 22:50:34.901576
10120 22:50:34.908197 TFTP server IP predefined by user: 192.168.201.1
10121 22:50:34.908283
10122 22:50:34.914517 Bootfile predefined by user: 13683708/tftp-deploy-okay74ba/kernel/image.itb
10123 22:50:34.914602
10124 22:50:34.917682 Sending tftp read request... done.
10125 22:50:34.917805
10126 22:50:34.921465 Waiting for the transfer...
10127 22:50:34.921614
10128 22:50:35.482828 00000000 ################################################################
10129 22:50:35.482963
10130 22:50:36.032495 00080000 ################################################################
10131 22:50:36.032639
10132 22:50:36.606526 00100000 ################################################################
10133 22:50:36.606675
10134 22:50:37.172622 00180000 ################################################################
10135 22:50:37.172768
10136 22:50:37.732317 00200000 ################################################################
10137 22:50:37.732466
10138 22:50:38.295682 00280000 ################################################################
10139 22:50:38.295824
10140 22:50:38.857149 00300000 ################################################################
10141 22:50:38.857323
10142 22:50:39.419367 00380000 ################################################################
10143 22:50:39.419508
10144 22:50:39.995599 00400000 ################################################################
10145 22:50:39.995743
10146 22:50:40.562533 00480000 ################################################################
10147 22:50:40.562671
10148 22:50:41.109930 00500000 ################################################################
10149 22:50:41.110067
10150 22:50:41.652099 00580000 ################################################################
10151 22:50:41.652232
10152 22:50:42.214812 00600000 ################################################################
10153 22:50:42.214946
10154 22:50:42.759569 00680000 ################################################################
10155 22:50:42.759700
10156 22:50:43.353646 00700000 ################################################################
10157 22:50:43.353791
10158 22:50:44.042776 00780000 ################################################################
10159 22:50:44.042924
10160 22:50:44.679740 00800000 ################################################################
10161 22:50:44.679897
10162 22:50:45.242293 00880000 ################################################################
10163 22:50:45.242423
10164 22:50:45.811291 00900000 ################################################################
10165 22:50:45.811465
10166 22:50:46.392629 00980000 ################################################################
10167 22:50:46.392764
10168 22:50:46.963479 00a00000 ################################################################
10169 22:50:46.963613
10170 22:50:47.513674 00a80000 ################################################################
10171 22:50:47.513826
10172 22:50:48.071514 00b00000 ################################################################
10173 22:50:48.071665
10174 22:50:48.630285 00b80000 ################################################################
10175 22:50:48.630420
10176 22:50:49.191489 00c00000 ################################################################
10177 22:50:49.191627
10178 22:50:49.732988 00c80000 ################################################################
10179 22:50:49.733124
10180 22:50:50.298182 00d00000 ################################################################
10181 22:50:50.298727
10182 22:50:50.885458 00d80000 ################################################################
10183 22:50:50.885644
10184 22:50:51.477130 00e00000 ################################################################
10185 22:50:51.477280
10186 22:50:52.080445 00e80000 ################################################################
10187 22:50:52.080583
10188 22:50:52.668873 00f00000 ################################################################
10189 22:50:52.669012
10190 22:50:53.241596 00f80000 ################################################################
10191 22:50:53.241742
10192 22:50:53.793733 01000000 ################################################################
10193 22:50:53.793906
10194 22:50:54.370591 01080000 ################################################################
10195 22:50:54.370736
10196 22:50:55.010686 01100000 ################################################################
10197 22:50:55.010833
10198 22:50:55.592536 01180000 ################################################################
10199 22:50:55.592672
10200 22:50:56.148413 01200000 ################################################################
10201 22:50:56.148645
10202 22:50:56.717754 01280000 ################################################################
10203 22:50:56.717923
10204 22:50:57.297731 01300000 ################################################################
10205 22:50:57.297862
10206 22:50:57.894735 01380000 ################################################################
10207 22:50:57.895247
10208 22:50:58.623630 01400000 ################################################################
10209 22:50:58.624132
10210 22:50:59.308523 01480000 ################################################################
10211 22:50:59.308752
10212 22:51:00.008354 01500000 ################################################################
10213 22:51:00.008932
10214 22:51:00.642244 01580000 ################################################################
10215 22:51:00.642398
10216 22:51:01.201945 01600000 ################################################################
10217 22:51:01.202089
10218 22:51:01.789448 01680000 ################################################################
10219 22:51:01.789634
10220 22:51:02.384709 01700000 ################################################################
10221 22:51:02.385228
10222 22:51:03.116922 01780000 ################################################################
10223 22:51:03.117455
10224 22:51:03.773200 01800000 ################################################################
10225 22:51:03.773376
10226 22:51:04.351852 01880000 ################################################################
10227 22:51:04.352003
10228 22:51:05.045585 01900000 ################################################################
10229 22:51:05.046153
10230 22:51:05.747817 01980000 ################################################################
10231 22:51:05.748350
10232 22:51:06.457308 01a00000 ################################################################
10233 22:51:06.457857
10234 22:51:07.168435 01a80000 ################################################################
10235 22:51:07.168988
10236 22:51:07.895396 01b00000 ################################################################
10237 22:51:07.896035
10238 22:51:08.592445 01b80000 ################################################################
10239 22:51:08.593003
10240 22:51:09.315925 01c00000 ################################################################
10241 22:51:09.316443
10242 22:51:10.048397 01c80000 ################################################################
10243 22:51:10.048987
10244 22:51:10.748771 01d00000 ################################################################
10245 22:51:10.749326
10246 22:51:11.483218 01d80000 ################################################################
10247 22:51:11.483764
10248 22:51:11.999831 01e00000 ############################################### done.
10249 22:51:12.000409
10250 22:51:12.003200 The bootfile was 31839506 bytes long.
10251 22:51:12.003657
10252 22:51:12.006636 Sending tftp read request... done.
10253 22:51:12.007109
10254 22:51:12.010561 Waiting for the transfer...
10255 22:51:12.011039
10256 22:51:12.011461 00000000 # done.
10257 22:51:12.011820
10258 22:51:12.017206 Command line loaded dynamically from TFTP file: 13683708/tftp-deploy-okay74ba/kernel/cmdline
10259 22:51:12.020580
10260 22:51:12.040428 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683708/extract-nfsrootfs-3ye22qzo,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10261 22:51:12.040957
10262 22:51:12.041282 Loading FIT.
10263 22:51:12.041639
10264 22:51:12.043486 Image ramdisk-1 has 18730658 bytes.
10265 22:51:12.043898
10266 22:51:12.047236 Image fdt-1 has 47258 bytes.
10267 22:51:12.047746
10268 22:51:12.050439 Image kernel-1 has 13059555 bytes.
10269 22:51:12.050864
10270 22:51:12.060007 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10271 22:51:12.060509
10272 22:51:12.076703 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10273 22:51:12.077224
10274 22:51:12.083630 Choosing best match conf-1 for compat google,spherion-rev2.
10275 22:51:12.084127
10276 22:51:12.091287 Connected to device vid:did:rid of 1ae0:0028:00
10277 22:51:12.098160
10278 22:51:12.101466 tpm_get_response: command 0x17b, return code 0x0
10279 22:51:12.101917
10280 22:51:12.104949 ec_init: CrosEC protocol v3 supported (256, 248)
10281 22:51:12.108749
10282 22:51:12.111829 tpm_cleanup: add release locality here.
10283 22:51:12.112281
10284 22:51:12.112632 Shutting down all USB controllers.
10285 22:51:12.115674
10286 22:51:12.116192 Removing current net device
10287 22:51:12.116559
10288 22:51:12.122390 Exiting depthcharge with code 4 at timestamp: 81306850
10289 22:51:12.122988
10290 22:51:12.125705 LZMA decompressing kernel-1 to 0x821a6718
10291 22:51:12.126266
10292 22:51:12.128917 LZMA decompressing kernel-1 to 0x40000000
10293 22:51:13.739924
10294 22:51:13.740471 jumping to kernel
10295 22:51:13.742317 end: 2.2.4 bootloader-commands (duration 00:00:54) [common]
10296 22:51:13.742950 start: 2.2.5 auto-login-action (timeout 00:03:32) [common]
10297 22:51:13.743529 Setting prompt string to ['Linux version [0-9]']
10298 22:51:13.744083 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10299 22:51:13.744635 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10300 22:51:13.822631
10301 22:51:13.825955 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10302 22:51:13.829608 start: 2.2.5.1 login-action (timeout 00:03:32) [common]
10303 22:51:13.829716 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10304 22:51:13.829819 Setting prompt string to []
10305 22:51:13.829920 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10306 22:51:13.830016 Using line separator: #'\n'#
10307 22:51:13.830101 No login prompt set.
10308 22:51:13.830189 Parsing kernel messages
10309 22:51:13.830271 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10310 22:51:13.830450 [login-action] Waiting for messages, (timeout 00:03:32)
10311 22:51:13.830534 Waiting using forced prompt support (timeout 00:01:46)
10312 22:51:13.849667 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10313 22:51:13.852643 [ 0.000000] random: crng init done
10314 22:51:13.859436 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10315 22:51:13.862490 [ 0.000000] efi: UEFI not found.
10316 22:51:13.869339 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10317 22:51:13.876342 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10318 22:51:13.885650 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10319 22:51:13.895874 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10320 22:51:13.902320 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10321 22:51:13.909017 [ 0.000000] printk: bootconsole [mtk8250] enabled
10322 22:51:13.915918 [ 0.000000] NUMA: No NUMA configuration found
10323 22:51:13.922313 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10324 22:51:13.925704 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10325 22:51:13.928909 [ 0.000000] Zone ranges:
10326 22:51:13.935108 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10327 22:51:13.938746 [ 0.000000] DMA32 empty
10328 22:51:13.945309 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10329 22:51:13.948883 [ 0.000000] Movable zone start for each node
10330 22:51:13.951815 [ 0.000000] Early memory node ranges
10331 22:51:13.958602 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10332 22:51:13.965048 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10333 22:51:13.971899 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10334 22:51:13.978647 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10335 22:51:13.981573 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10336 22:51:13.991500 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10337 22:51:14.046549 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10338 22:51:14.053517 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10339 22:51:14.059991 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10340 22:51:14.063157 [ 0.000000] psci: probing for conduit method from DT.
10341 22:51:14.069772 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10342 22:51:14.073132 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10343 22:51:14.080100 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10344 22:51:14.083130 [ 0.000000] psci: SMC Calling Convention v1.2
10345 22:51:14.089925 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10346 22:51:14.092959 [ 0.000000] Detected VIPT I-cache on CPU0
10347 22:51:14.099577 [ 0.000000] CPU features: detected: GIC system register CPU interface
10348 22:51:14.106270 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10349 22:51:14.113347 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10350 22:51:14.119578 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10351 22:51:14.126583 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10352 22:51:14.136160 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10353 22:51:14.139780 [ 0.000000] alternatives: applying boot alternatives
10354 22:51:14.143052 [ 0.000000] Fallback order for Node 0: 0
10355 22:51:14.153149 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10356 22:51:14.153297 [ 0.000000] Policy zone: Normal
10357 22:51:14.179790 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683708/extract-nfsrootfs-3ye22qzo,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10358 22:51:14.189195 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10359 22:51:14.199817 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10360 22:51:14.209523 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10361 22:51:14.216049 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10362 22:51:14.219434 <6>[ 0.000000] software IO TLB: area num 8.
10363 22:51:14.276091 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10364 22:51:14.426008 <6>[ 0.000000] Memory: 7945896K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406872K reserved, 32768K cma-reserved)
10365 22:51:14.432604 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10366 22:51:14.439290 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10367 22:51:14.442452 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10368 22:51:14.449264 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10369 22:51:14.455784 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10370 22:51:14.459130 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10371 22:51:14.469285 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10372 22:51:14.475930 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10373 22:51:14.482238 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10374 22:51:14.488637 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10375 22:51:14.491793 <6>[ 0.000000] GICv3: 608 SPIs implemented
10376 22:51:14.495492 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10377 22:51:14.502086 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10378 22:51:14.505331 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10379 22:51:14.512129 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10380 22:51:14.525223 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10381 22:51:14.534776 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10382 22:51:14.545074 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10383 22:51:14.552314 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10384 22:51:14.565739 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10385 22:51:14.572363 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10386 22:51:14.579025 <6>[ 0.009180] Console: colour dummy device 80x25
10387 22:51:14.589038 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10388 22:51:14.595435 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10389 22:51:14.598419 <6>[ 0.029225] LSM: Security Framework initializing
10390 22:51:14.605325 <6>[ 0.034161] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10391 22:51:14.615204 <6>[ 0.041975] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 22:51:14.622078 <6>[ 0.051449] cblist_init_generic: Setting adjustable number of callback queues.
10393 22:51:14.628429 <6>[ 0.058893] cblist_init_generic: Setting shift to 3 and lim to 1.
10394 22:51:14.638801 <6>[ 0.065232] cblist_init_generic: Setting adjustable number of callback queues.
10395 22:51:14.645213 <6>[ 0.072704] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 22:51:14.648362 <6>[ 0.079105] rcu: Hierarchical SRCU implementation.
10397 22:51:14.654979 <6>[ 0.084151] rcu: Max phase no-delay instances is 1000.
10398 22:51:14.661482 <6>[ 0.091171] EFI services will not be available.
10399 22:51:14.664854 <6>[ 0.096157] smp: Bringing up secondary CPUs ...
10400 22:51:14.673635 <6>[ 0.101206] Detected VIPT I-cache on CPU1
10401 22:51:14.680083 <6>[ 0.101280] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10402 22:51:14.686372 <6>[ 0.101313] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10403 22:51:14.689975 <6>[ 0.101647] Detected VIPT I-cache on CPU2
10404 22:51:14.696492 <6>[ 0.101695] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10405 22:51:14.703312 <6>[ 0.101711] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10406 22:51:14.709657 <6>[ 0.101971] Detected VIPT I-cache on CPU3
10407 22:51:14.716587 <6>[ 0.102017] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10408 22:51:14.723161 <6>[ 0.102031] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10409 22:51:14.726149 <6>[ 0.102336] CPU features: detected: Spectre-v4
10410 22:51:14.732824 <6>[ 0.102343] CPU features: detected: Spectre-BHB
10411 22:51:14.736124 <6>[ 0.102348] Detected PIPT I-cache on CPU4
10412 22:51:14.742652 <6>[ 0.102407] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10413 22:51:14.749887 <6>[ 0.102424] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10414 22:51:14.755964 <6>[ 0.102723] Detected PIPT I-cache on CPU5
10415 22:51:14.762613 <6>[ 0.102786] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10416 22:51:14.769476 <6>[ 0.102802] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10417 22:51:14.772936 <6>[ 0.103086] Detected PIPT I-cache on CPU6
10418 22:51:14.779086 <6>[ 0.103153] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10419 22:51:14.786395 <6>[ 0.103169] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10420 22:51:14.792527 <6>[ 0.103466] Detected PIPT I-cache on CPU7
10421 22:51:14.799215 <6>[ 0.103532] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10422 22:51:14.806142 <6>[ 0.103548] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10423 22:51:14.809216 <6>[ 0.103595] smp: Brought up 1 node, 8 CPUs
10424 22:51:14.815652 <6>[ 0.244833] SMP: Total of 8 processors activated.
10425 22:51:14.819130 <6>[ 0.249784] CPU features: detected: 32-bit EL0 Support
10426 22:51:14.829547 <6>[ 0.255180] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10427 22:51:14.835214 <6>[ 0.263982] CPU features: detected: Common not Private translations
10428 22:51:14.838808 <6>[ 0.270457] CPU features: detected: CRC32 instructions
10429 22:51:14.845402 <6>[ 0.275809] CPU features: detected: RCpc load-acquire (LDAPR)
10430 22:51:14.852101 <6>[ 0.281805] CPU features: detected: LSE atomic instructions
10431 22:51:14.858683 <6>[ 0.287587] CPU features: detected: Privileged Access Never
10432 22:51:14.861998 <6>[ 0.293367] CPU features: detected: RAS Extension Support
10433 22:51:14.872164 <6>[ 0.298975] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10434 22:51:14.875548 <6>[ 0.306194] CPU: All CPU(s) started at EL2
10435 22:51:14.881808 <6>[ 0.310510] alternatives: applying system-wide alternatives
10436 22:51:14.891002 <6>[ 0.321352] devtmpfs: initialized
10437 22:51:14.906197 <6>[ 0.330288] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10438 22:51:14.912907 <6>[ 0.340251] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10439 22:51:14.919156 <6>[ 0.348402] pinctrl core: initialized pinctrl subsystem
10440 22:51:14.922922 <6>[ 0.355054] DMI not present or invalid.
10441 22:51:14.929862 <6>[ 0.359465] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10442 22:51:14.939405 <6>[ 0.366334] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10443 22:51:14.945905 <6>[ 0.373923] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10444 22:51:14.955735 <6>[ 0.382135] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10445 22:51:14.959276 <6>[ 0.390377] audit: initializing netlink subsys (disabled)
10446 22:51:14.969477 <5>[ 0.396070] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10447 22:51:14.976062 <6>[ 0.396775] thermal_sys: Registered thermal governor 'step_wise'
10448 22:51:14.982857 <6>[ 0.404038] thermal_sys: Registered thermal governor 'power_allocator'
10449 22:51:14.986095 <6>[ 0.410294] cpuidle: using governor menu
10450 22:51:14.992705 <6>[ 0.421254] NET: Registered PF_QIPCRTR protocol family
10451 22:51:14.998755 <6>[ 0.426739] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10452 22:51:15.005430 <6>[ 0.433839] ASID allocator initialised with 32768 entries
10453 22:51:15.008470 <6>[ 0.440409] Serial: AMBA PL011 UART driver
10454 22:51:15.018608 <4>[ 0.449137] Trying to register duplicate clock ID: 134
10455 22:51:15.077328 <6>[ 0.510733] KASLR enabled
10456 22:51:15.091730 <6>[ 0.518504] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10457 22:51:15.097805 <6>[ 0.525516] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10458 22:51:15.104678 <6>[ 0.532006] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10459 22:51:15.111293 <6>[ 0.539010] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10460 22:51:15.117587 <6>[ 0.545494] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10461 22:51:15.124587 <6>[ 0.552496] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10462 22:51:15.131070 <6>[ 0.558980] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10463 22:51:15.137659 <6>[ 0.565987] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10464 22:51:15.141104 <6>[ 0.573503] ACPI: Interpreter disabled.
10465 22:51:15.149426 <6>[ 0.579923] iommu: Default domain type: Translated
10466 22:51:15.156003 <6>[ 0.585035] iommu: DMA domain TLB invalidation policy: strict mode
10467 22:51:15.159192 <5>[ 0.591692] SCSI subsystem initialized
10468 22:51:15.166029 <6>[ 0.595855] usbcore: registered new interface driver usbfs
10469 22:51:15.172631 <6>[ 0.601588] usbcore: registered new interface driver hub
10470 22:51:15.175875 <6>[ 0.607139] usbcore: registered new device driver usb
10471 22:51:15.182618 <6>[ 0.613234] pps_core: LinuxPPS API ver. 1 registered
10472 22:51:15.192357 <6>[ 0.618429] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10473 22:51:15.195848 <6>[ 0.627777] PTP clock support registered
10474 22:51:15.199150 <6>[ 0.632018] EDAC MC: Ver: 3.0.0
10475 22:51:15.206846 <6>[ 0.637176] FPGA manager framework
10476 22:51:15.213271 <6>[ 0.640863] Advanced Linux Sound Architecture Driver Initialized.
10477 22:51:15.216087 <6>[ 0.647637] vgaarb: loaded
10478 22:51:15.223073 <6>[ 0.650795] clocksource: Switched to clocksource arch_sys_counter
10479 22:51:15.226303 <5>[ 0.657238] VFS: Disk quotas dquot_6.6.0
10480 22:51:15.232750 <6>[ 0.661424] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10481 22:51:15.236323 <6>[ 0.668614] pnp: PnP ACPI: disabled
10482 22:51:15.244509 <6>[ 0.675333] NET: Registered PF_INET protocol family
10483 22:51:15.254568 <6>[ 0.680935] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10484 22:51:15.266112 <6>[ 0.693247] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10485 22:51:15.275997 <6>[ 0.702060] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10486 22:51:15.282490 <6>[ 0.710032] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10487 22:51:15.292512 <6>[ 0.718729] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10488 22:51:15.299190 <6>[ 0.728475] TCP: Hash tables configured (established 65536 bind 65536)
10489 22:51:15.305323 <6>[ 0.735334] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 22:51:15.315539 <6>[ 0.742532] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10491 22:51:15.322287 <6>[ 0.750226] NET: Registered PF_UNIX/PF_LOCAL protocol family
10492 22:51:15.325147 <6>[ 0.756386] RPC: Registered named UNIX socket transport module.
10493 22:51:15.332244 <6>[ 0.762542] RPC: Registered udp transport module.
10494 22:51:15.335155 <6>[ 0.767473] RPC: Registered tcp transport module.
10495 22:51:15.345154 <6>[ 0.772405] RPC: Registered tcp NFSv4.1 backchannel transport module.
10496 22:51:15.348880 <6>[ 0.779072] PCI: CLS 0 bytes, default 64
10497 22:51:15.351715 <6>[ 0.783433] Unpacking initramfs...
10498 22:51:15.375766 <6>[ 0.802901] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10499 22:51:15.385654 <6>[ 0.811567] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10500 22:51:15.388984 <6>[ 0.820412] kvm [1]: IPA Size Limit: 40 bits
10501 22:51:15.395430 <6>[ 0.824939] kvm [1]: GICv3: no GICV resource entry
10502 22:51:15.398666 <6>[ 0.829960] kvm [1]: disabling GICv2 emulation
10503 22:51:15.405636 <6>[ 0.834643] kvm [1]: GIC system register CPU interface enabled
10504 22:51:15.409071 <6>[ 0.840801] kvm [1]: vgic interrupt IRQ18
10505 22:51:15.415630 <6>[ 0.845172] kvm [1]: VHE mode initialized successfully
10506 22:51:15.421954 <5>[ 0.851499] Initialise system trusted keyrings
10507 22:51:15.428231 <6>[ 0.856306] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10508 22:51:15.435895 <6>[ 0.866289] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10509 22:51:15.442458 <5>[ 0.872675] NFS: Registering the id_resolver key type
10510 22:51:15.445834 <5>[ 0.877975] Key type id_resolver registered
10511 22:51:15.452676 <5>[ 0.882387] Key type id_legacy registered
10512 22:51:15.459232 <6>[ 0.886682] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10513 22:51:15.465612 <6>[ 0.893600] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10514 22:51:15.472340 <6>[ 0.901325] 9p: Installing v9fs 9p2000 file system support
10515 22:51:15.509806 <5>[ 0.940205] Key type asymmetric registered
10516 22:51:15.513020 <5>[ 0.944533] Asymmetric key parser 'x509' registered
10517 22:51:15.522961 <6>[ 0.949672] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10518 22:51:15.526439 <6>[ 0.957289] io scheduler mq-deadline registered
10519 22:51:15.529217 <6>[ 0.962064] io scheduler kyber registered
10520 22:51:15.547960 <6>[ 0.978795] EINJ: ACPI disabled.
10521 22:51:15.580820 <4>[ 1.004884] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 22:51:15.590622 <4>[ 1.015526] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 22:51:15.605903 <6>[ 1.036346] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10524 22:51:15.613369 <6>[ 1.044248] printk: console [ttyS0] disabled
10525 22:51:15.641582 <6>[ 1.068893] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10526 22:51:15.648272 <6>[ 1.078381] printk: console [ttyS0] enabled
10527 22:51:15.651295 <6>[ 1.078381] printk: console [ttyS0] enabled
10528 22:51:15.658392 <6>[ 1.087277] printk: bootconsole [mtk8250] disabled
10529 22:51:15.661676 <6>[ 1.087277] printk: bootconsole [mtk8250] disabled
10530 22:51:15.668217 <6>[ 1.098261] SuperH (H)SCI(F) driver initialized
10531 22:51:15.671772 <6>[ 1.103522] msm_serial: driver initialized
10532 22:51:15.684989 <6>[ 1.112387] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10533 22:51:15.695360 <6>[ 1.120930] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10534 22:51:15.701569 <6>[ 1.129473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10535 22:51:15.711595 <6>[ 1.138100] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10536 22:51:15.718620 <6>[ 1.146807] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10537 22:51:15.728255 <6>[ 1.155521] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10538 22:51:15.738124 <6>[ 1.164069] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10539 22:51:15.744938 <6>[ 1.172878] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10540 22:51:15.754812 <6>[ 1.181419] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10541 22:51:15.766254 <6>[ 1.196893] loop: module loaded
10542 22:51:15.773004 <6>[ 1.202864] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10543 22:51:15.795729 <4>[ 1.226210] mtk-pmic-keys: Failed to locate of_node [id: -1]
10544 22:51:15.802602 <6>[ 1.233058] megasas: 07.719.03.00-rc1
10545 22:51:15.811558 <6>[ 1.242535] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10546 22:51:15.819662 <6>[ 1.250178] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10547 22:51:15.836835 <6>[ 1.266792] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10548 22:51:15.892814 <6>[ 1.316735] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10549 22:51:16.142194 <6>[ 1.572682] Freeing initrd memory: 18284K
10550 22:51:16.153385 <6>[ 1.584166] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10551 22:51:16.164580 <6>[ 1.595044] tun: Universal TUN/TAP device driver, 1.6
10552 22:51:16.167758 <6>[ 1.601097] thunder_xcv, ver 1.0
10553 22:51:16.171278 <6>[ 1.604603] thunder_bgx, ver 1.0
10554 22:51:16.174779 <6>[ 1.608098] nicpf, ver 1.0
10555 22:51:16.184722 <6>[ 1.612119] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10556 22:51:16.188267 <6>[ 1.619594] hns3: Copyright (c) 2017 Huawei Corporation.
10557 22:51:16.191532 <6>[ 1.625181] hclge is initializing
10558 22:51:16.198186 <6>[ 1.628761] e1000: Intel(R) PRO/1000 Network Driver
10559 22:51:16.204671 <6>[ 1.633890] e1000: Copyright (c) 1999-2006 Intel Corporation.
10560 22:51:16.208273 <6>[ 1.639901] e1000e: Intel(R) PRO/1000 Network Driver
10561 22:51:16.215136 <6>[ 1.645117] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10562 22:51:16.221312 <6>[ 1.651305] igb: Intel(R) Gigabit Ethernet Network Driver
10563 22:51:16.228597 <6>[ 1.656956] igb: Copyright (c) 2007-2014 Intel Corporation.
10564 22:51:16.235273 <6>[ 1.662794] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10565 22:51:16.241293 <6>[ 1.669312] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10566 22:51:16.244750 <6>[ 1.675769] sky2: driver version 1.30
10567 22:51:16.251254 <6>[ 1.680692] usbcore: registered new device driver r8152-cfgselector
10568 22:51:16.258323 <6>[ 1.687226] usbcore: registered new interface driver r8152
10569 22:51:16.261854 <6>[ 1.693042] VFIO - User Level meta-driver version: 0.3
10570 22:51:16.270686 <6>[ 1.701299] usbcore: registered new interface driver usb-storage
10571 22:51:16.276924 <6>[ 1.707735] usbcore: registered new device driver onboard-usb-hub
10572 22:51:16.286245 <6>[ 1.716854] mt6397-rtc mt6359-rtc: registered as rtc0
10573 22:51:16.296060 <6>[ 1.722312] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:51:17 UTC (1715122277)
10574 22:51:16.299494 <6>[ 1.731873] i2c_dev: i2c /dev entries driver
10575 22:51:16.316125 <6>[ 1.743616] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10576 22:51:16.322790 <4>[ 1.752346] cpu cpu0: supply cpu not found, using dummy regulator
10577 22:51:16.329854 <4>[ 1.758770] cpu cpu1: supply cpu not found, using dummy regulator
10578 22:51:16.336237 <4>[ 1.765180] cpu cpu2: supply cpu not found, using dummy regulator
10579 22:51:16.343198 <4>[ 1.771596] cpu cpu3: supply cpu not found, using dummy regulator
10580 22:51:16.349460 <4>[ 1.777992] cpu cpu4: supply cpu not found, using dummy regulator
10581 22:51:16.356223 <4>[ 1.784389] cpu cpu5: supply cpu not found, using dummy regulator
10582 22:51:16.362782 <4>[ 1.790795] cpu cpu6: supply cpu not found, using dummy regulator
10583 22:51:16.369303 <4>[ 1.797191] cpu cpu7: supply cpu not found, using dummy regulator
10584 22:51:16.388218 <6>[ 1.818844] cpu cpu0: EM: created perf domain
10585 22:51:16.391174 <6>[ 1.823712] cpu cpu4: EM: created perf domain
10586 22:51:16.398480 <6>[ 1.829328] sdhci: Secure Digital Host Controller Interface driver
10587 22:51:16.405442 <6>[ 1.835760] sdhci: Copyright(c) Pierre Ossman
10588 22:51:16.412107 <6>[ 1.840716] Synopsys Designware Multimedia Card Interface Driver
10589 22:51:16.418729 <6>[ 1.847345] sdhci-pltfm: SDHCI platform and OF driver helper
10590 22:51:16.422122 <6>[ 1.847417] mmc0: CQHCI version 5.10
10591 22:51:16.429237 <6>[ 1.857689] ledtrig-cpu: registered to indicate activity on CPUs
10592 22:51:16.435982 <6>[ 1.864724] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10593 22:51:16.442121 <6>[ 1.871776] usbcore: registered new interface driver usbhid
10594 22:51:16.445124 <6>[ 1.877598] usbhid: USB HID core driver
10595 22:51:16.451798 <6>[ 1.881798] spi_master spi0: will run message pump with realtime priority
10596 22:51:16.495790 <6>[ 1.919534] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10597 22:51:16.511699 <6>[ 1.935046] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10598 22:51:16.519767 <6>[ 1.950506] mmc0: Command Queue Engine enabled
10599 22:51:16.526117 <6>[ 1.955289] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10600 22:51:16.532977 <6>[ 1.962010] cros-ec-spi spi0.0: Chrome EC device registered
10601 22:51:16.536607 <6>[ 1.962546] mmcblk0: mmc0:0001 DA4128 116 GiB
10602 22:51:16.548963 <6>[ 1.979491] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10603 22:51:16.556246 <6>[ 1.986716] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10604 22:51:16.566161 <6>[ 1.992596] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10605 22:51:16.572991 <6>[ 1.992741] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10606 22:51:16.576453 <6>[ 2.003328] NET: Registered PF_PACKET protocol family
10607 22:51:16.582807 <6>[ 2.007765] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10608 22:51:16.589287 <6>[ 2.012529] 9pnet: Installing 9P2000 support
10609 22:51:16.592618 <5>[ 2.023516] Key type dns_resolver registered
10610 22:51:16.596351 <6>[ 2.028493] registered taskstats version 1
10611 22:51:16.602480 <5>[ 2.032873] Loading compiled-in X.509 certificates
10612 22:51:16.632547 <4>[ 2.056537] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10613 22:51:16.642986 <4>[ 2.067278] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10614 22:51:16.649391 <3>[ 2.077828] debugfs: File 'uA_load' in directory '/' already present!
10615 22:51:16.656139 <3>[ 2.084600] debugfs: File 'min_uV' in directory '/' already present!
10616 22:51:16.662550 <3>[ 2.091227] debugfs: File 'max_uV' in directory '/' already present!
10617 22:51:16.669265 <3>[ 2.097856] debugfs: File 'constraint_flags' in directory '/' already present!
10618 22:51:16.680874 <6>[ 2.111492] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10619 22:51:16.688002 <6>[ 2.118467] xhci-mtk 11200000.usb: xHCI Host Controller
10620 22:51:16.694274 <6>[ 2.123963] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10621 22:51:16.704422 <6>[ 2.131807] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10622 22:51:16.711190 <6>[ 2.141231] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10623 22:51:16.717891 <6>[ 2.147308] xhci-mtk 11200000.usb: xHCI Host Controller
10624 22:51:16.724872 <6>[ 2.152783] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10625 22:51:16.731535 <6>[ 2.160427] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10626 22:51:16.738572 <6>[ 2.168028] hub 1-0:1.0: USB hub found
10627 22:51:16.741088 <6>[ 2.172040] hub 1-0:1.0: 1 port detected
10628 22:51:16.747998 <6>[ 2.176305] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10629 22:51:16.754201 <6>[ 2.184849] hub 2-0:1.0: USB hub found
10630 22:51:16.757888 <6>[ 2.188852] hub 2-0:1.0: 1 port detected
10631 22:51:16.766394 <6>[ 2.196947] mtk-msdc 11f70000.mmc: Got CD GPIO
10632 22:51:16.778749 <6>[ 2.205847] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10633 22:51:16.785768 <6>[ 2.213874] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10634 22:51:16.795391 <4>[ 2.221766] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10635 22:51:16.805305 <6>[ 2.231298] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10636 22:51:16.812150 <6>[ 2.239374] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10637 22:51:16.818121 <6>[ 2.247391] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10638 22:51:16.828253 <6>[ 2.255303] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10639 22:51:16.835003 <6>[ 2.263125] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10640 22:51:16.845556 <6>[ 2.270942] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10641 22:51:16.854632 <6>[ 2.281343] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10642 22:51:16.861589 <6>[ 2.289699] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10643 22:51:16.871628 <6>[ 2.298042] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10644 22:51:16.878165 <6>[ 2.306380] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10645 22:51:16.888243 <6>[ 2.314717] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10646 22:51:16.894332 <6>[ 2.323058] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10647 22:51:16.904406 <6>[ 2.331396] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10648 22:51:16.910750 <6>[ 2.339734] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10649 22:51:16.920980 <6>[ 2.348071] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10650 22:51:16.930447 <6>[ 2.356409] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10651 22:51:16.937199 <6>[ 2.364761] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10652 22:51:16.947187 <6>[ 2.373099] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10653 22:51:16.954138 <6>[ 2.381441] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10654 22:51:16.963664 <6>[ 2.389779] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10655 22:51:16.970454 <6>[ 2.398116] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10656 22:51:16.977079 <6>[ 2.406903] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10657 22:51:16.983686 <6>[ 2.414077] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10658 22:51:16.990428 <6>[ 2.420852] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10659 22:51:17.000128 <6>[ 2.427609] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10660 22:51:17.006476 <6>[ 2.434561] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10661 22:51:17.013445 <6>[ 2.441408] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10662 22:51:17.023468 <6>[ 2.450538] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10663 22:51:17.033229 <6>[ 2.459659] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10664 22:51:17.042953 <6>[ 2.468954] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10665 22:51:17.053184 <6>[ 2.478422] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10666 22:51:17.063346 <6>[ 2.487889] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10667 22:51:17.069465 <6>[ 2.497009] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10668 22:51:17.079479 <6>[ 2.506503] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10669 22:51:17.089679 <6>[ 2.515623] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10670 22:51:17.099237 <6>[ 2.524917] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10671 22:51:17.108959 <6>[ 2.535076] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10672 22:51:17.119321 <6>[ 2.546595] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10673 22:51:17.125699 <6>[ 2.556271] Trying to probe devices needed for running init ...
10674 22:51:17.148251 <6>[ 2.575368] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10675 22:51:17.176150 <6>[ 2.606472] hub 2-1:1.0: USB hub found
10676 22:51:17.178999 <6>[ 2.610929] hub 2-1:1.0: 3 ports detected
10677 22:51:17.187098 <6>[ 2.617831] hub 2-1:1.0: USB hub found
10678 22:51:17.190486 <6>[ 2.622201] hub 2-1:1.0: 3 ports detected
10679 22:51:17.299798 <6>[ 2.727067] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10680 22:51:17.454549 <6>[ 2.885023] hub 1-1:1.0: USB hub found
10681 22:51:17.457825 <6>[ 2.889482] hub 1-1:1.0: 4 ports detected
10682 22:51:17.467586 <6>[ 2.898337] hub 1-1:1.0: USB hub found
10683 22:51:17.470918 <6>[ 2.902922] hub 1-1:1.0: 4 ports detected
10684 22:51:17.539539 <6>[ 2.967324] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10685 22:51:17.647902 <6>[ 3.075753] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10686 22:51:17.684199 <4>[ 3.111822] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10687 22:51:17.694200 <4>[ 3.120914] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10688 22:51:17.729307 <6>[ 3.160165] r8152 2-1.3:1.0 eth0: v1.12.13
10689 22:51:17.791481 <6>[ 3.219102] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10690 22:51:17.924039 <6>[ 3.354920] hub 1-1.4:1.0: USB hub found
10691 22:51:17.927317 <6>[ 3.359585] hub 1-1.4:1.0: 2 ports detected
10692 22:51:17.937722 <6>[ 3.368180] hub 1-1.4:1.0: USB hub found
10693 22:51:17.940458 <6>[ 3.372776] hub 1-1.4:1.0: 2 ports detected
10694 22:51:18.239966 <6>[ 3.667080] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10695 22:51:18.431566 <6>[ 3.859110] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10696 22:51:19.315474 <6>[ 4.746400] r8152 2-1.3:1.0 eth0: carrier on
10697 22:51:21.995726 <5>[ 4.770875] Sending DHCP requests .., OK
10698 22:51:22.002386 <6>[ 7.431185] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10699 22:51:22.005472 <6>[ 7.439473] IP-Config: Complete:
10700 22:51:22.018594 <6>[ 7.442972] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10701 22:51:22.025289 <6>[ 7.453683] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10702 22:51:22.031886 <6>[ 7.462300] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10703 22:51:22.038170 <6>[ 7.462310] nameserver0=192.168.201.1
10704 22:51:22.041716 <6>[ 7.474457] clk: Disabling unused clocks
10705 22:51:22.045319 <6>[ 7.479946] ALSA device list:
10706 22:51:22.051590 <6>[ 7.483226] No soundcards found.
10707 22:51:22.060118 <6>[ 7.490964] Freeing unused kernel memory: 8512K
10708 22:51:22.063275 <6>[ 7.495876] Run /init as init process
10709 22:51:22.072343 Loading, please wait...
10710 22:51:22.101306 Starting systemd-udevd version 252.22-1~deb12u1
10711 22:51:22.101946
10712 22:51:22.383041 <6>[ 7.810924] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10713 22:51:22.408852 <6>[ 7.840271] remoteproc remoteproc0: scp is available
10714 22:51:22.418995 <3>[ 7.843996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 22:51:22.422191 <6>[ 7.845629] remoteproc remoteproc0: powering up scp
10716 22:51:22.429087 <6>[ 7.852768] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10717 22:51:22.438852 <6>[ 7.852799] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10718 22:51:22.448846 <6>[ 7.852806] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10719 22:51:22.455321 <3>[ 7.853898] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 22:51:22.464946 <6>[ 7.858980] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10721 22:51:22.472145 <3>[ 7.866536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 22:51:22.478825 <4>[ 7.874266] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10723 22:51:22.485250 <6>[ 7.875261] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10724 22:51:22.492087 <4>[ 7.922026] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10725 22:51:22.502034 <3>[ 7.929641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 22:51:22.508184 <3>[ 7.938071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 22:51:22.514661 <6>[ 7.938079] mc: Linux media interface: v0.10
10728 22:51:22.521625 <3>[ 7.951029] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 22:51:22.531581 <6>[ 7.951484] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10730 22:51:22.538254 <3>[ 7.959131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 22:51:22.548614 <3>[ 7.959137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 22:51:22.554743 <3>[ 7.984271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 22:51:22.566495 <3>[ 7.994278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 22:51:22.573179 <3>[ 8.002402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 22:51:22.583119 <4>[ 8.005123] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10736 22:51:22.589759 <4>[ 8.005123] Fallback method does not support PEC.
10737 22:51:22.596047 <3>[ 8.010489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 22:51:22.606020 <6>[ 8.011104] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10739 22:51:22.616288 <6>[ 8.011703] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10740 22:51:22.623112 <6>[ 8.036212] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10741 22:51:22.629936 <3>[ 8.042330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 22:51:22.639912 <3>[ 8.042335] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 22:51:22.646093 <3>[ 8.042337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 22:51:22.652982 <3>[ 8.042341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 22:51:22.663017 <6>[ 8.051454] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10746 22:51:22.669587 <6>[ 8.051496] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10747 22:51:22.676583 <6>[ 8.051507] remoteproc remoteproc0: remote processor scp is now up
10748 22:51:22.682514 <6>[ 8.057289] pci_bus 0000:00: root bus resource [bus 00-ff]
10749 22:51:22.689681 <6>[ 8.057311] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10750 22:51:22.699390 <6>[ 8.057319] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10751 22:51:22.706170 <6>[ 8.057502] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10752 22:51:22.712615 <6>[ 8.057532] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10753 22:51:22.716337 <6>[ 8.057720] pci 0000:00:00.0: supports D1 D2
10754 22:51:22.723308 <6>[ 8.057726] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10755 22:51:22.733332 <3>[ 8.058238] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 22:51:22.739488 <3>[ 8.118550] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10757 22:51:22.749687 <3>[ 8.126372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 22:51:22.759558 <6>[ 8.127848] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10759 22:51:22.763265 <6>[ 8.142173] videodev: Linux video capture interface: v2.00
10760 22:51:22.772711 <3>[ 8.156235] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10761 22:51:22.782770 <6>[ 8.188183] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10762 22:51:22.789570 <6>[ 8.221023] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10763 22:51:22.799566 <6>[ 8.227580] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10764 22:51:22.806609 <6>[ 8.235181] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10765 22:51:22.812643 <6>[ 8.243209] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10766 22:51:22.819790 <6>[ 8.251097] pci 0000:01:00.0: supports D1 D2
10767 22:51:22.826245 <6>[ 8.255720] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10768 22:51:22.829620 <6>[ 8.258137] Bluetooth: Core ver 2.22
10769 22:51:22.842633 <6>[ 8.274230] NET: Registered PF_BLUETOOTH protocol family
10770 22:51:22.849821 <6>[ 8.279971] Bluetooth: HCI device and connection manager initialized
10771 22:51:22.856412 <6>[ 8.286888] Bluetooth: HCI socket layer initialized
10772 22:51:22.862940 <6>[ 8.292223] Bluetooth: L2CAP socket layer initialized
10773 22:51:22.865991 <6>[ 8.297763] Bluetooth: SCO socket layer initialized
10774 22:51:22.876678 <6>[ 8.304531] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10775 22:51:22.883131 <6>[ 8.313003] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10776 22:51:22.893304 <6>[ 8.319921] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10777 22:51:22.899520 <6>[ 8.320190] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10778 22:51:22.906457 <6>[ 8.328003] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10779 22:51:22.916296 <6>[ 8.328014] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10780 22:51:22.922953 <6>[ 8.351046] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10781 22:51:22.929457 <6>[ 8.359054] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10782 22:51:22.942429 <6>[ 8.363182] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10783 22:51:22.948945 <6>[ 8.367058] pci 0000:00:00.0: PCI bridge to [bus 01]
10784 22:51:22.956097 <6>[ 8.367065] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10785 22:51:22.964277 <6>[ 8.395467] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10786 22:51:22.974278 <6>[ 8.401159] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10787 22:51:22.988654 <6>[ 8.419936] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10788 22:51:22.995800 <6>[ 8.426876] usbcore: registered new interface driver uvcvideo
10789 22:51:23.079905 <4>[ 8.504866] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10790 22:51:23.083612 <6>[ 8.505958] usbcore: registered new interface driver btusb
10791 22:51:23.090490 <3>[ 8.515430] Bluetooth: hci0: Failed to load firmware file (-2)
10792 22:51:23.097235 <3>[ 8.515435] Bluetooth: hci0: Failed to set up firmware (-2)
10793 22:51:23.106916 <4>[ 8.515439] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10794 22:51:23.113268 <6>[ 8.517718] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10795 22:51:23.119509 <6>[ 8.550266] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10796 22:51:23.145122 <5>[ 8.573052] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10797 22:51:23.166389 <5>[ 8.594605] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10798 22:51:23.173322 <5>[ 8.602577] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10799 22:51:23.183026 <4>[ 8.611124] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10800 22:51:23.189738 <6>[ 8.620041] cfg80211: failed to load regulatory.db
10801 22:51:23.248235 <6>[ 8.675985] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10802 22:51:23.254379 <6>[ 8.683624] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10803 22:51:23.275559 <6>[ 8.707004] mt7921e 0000:01:00.0: ASIC revision: 79610010
10804 22:51:23.379639 <6>[ 8.807316] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10805 22:51:23.382667 <6>[ 8.807316]
10806 22:51:23.390583 Begin: Loading essential drivers ... done.
10807 22:51:23.393727 Begin: Running /scripts/init-premount ... done.
10808 22:51:23.400157 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10809 22:51:23.409982 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10810 22:51:23.413390 Device /sys/class/net/eth0 found
10811 22:51:23.413893 done.
10812 22:51:23.420129 Begin: Waiting up to 180 secs for any network device to become available ... done.
10813 22:51:23.463623 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10814 22:51:23.471412 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10815 22:51:23.478378 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10816 22:51:23.484756 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10817 22:51:23.491356 host : mt8192-asurada-spherion-r0-cbg-8
10818 22:51:23.498252 domain : lava-rack
10819 22:51:23.501375 rootserver: 192.168.201.1 rootpath:
10820 22:51:23.504292 filename :
10821 22:51:23.647273 <6>[ 9.075927] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10822 22:51:23.679079 done.
10823 22:51:23.687716 Begin: Running /scripts/nfs-bottom ... done.
10824 22:51:23.703129 Begin: Running /scripts/init-bottom ... done.
10825 22:51:25.090224 <6>[ 10.521619] NET: Registered PF_INET6 protocol family
10826 22:51:25.096924 <6>[ 10.528580] Segment Routing with IPv6
10827 22:51:25.099901 <6>[ 10.532562] In-situ OAM (IOAM) with IPv6
10828 22:51:25.282450 <30>[ 10.687511] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10829 22:51:25.288781 <30>[ 10.720615] systemd[1]: Detected architecture arm64.
10830 22:51:25.299793
10831 22:51:25.303014 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10832 22:51:25.303468
10833 22:51:25.303826
10834 22:51:25.329602 <30>[ 10.761175] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10835 22:51:26.547637 <30>[ 11.976321] systemd[1]: Queued start job for default target graphical.target.
10836 22:51:26.579952 <30>[ 12.008275] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10837 22:51:26.586120 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10838 22:51:26.586674
10839 22:51:26.608642 <30>[ 12.036842] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10840 22:51:26.618317 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10841 22:51:26.618904
10842 22:51:26.636903 <30>[ 12.064881] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10843 22:51:26.646346 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10844 22:51:26.646927
10845 22:51:26.665012 <30>[ 12.093300] systemd[1]: Created slice user.slice - User and Session Slice.
10846 22:51:26.671500 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10847 22:51:26.672052
10848 22:51:26.694232 <30>[ 12.119219] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10849 22:51:26.700415 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10850 22:51:26.700963
10851 22:51:26.722764 <30>[ 12.147901] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10852 22:51:26.729663 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10853 22:51:26.730310
10854 22:51:26.756899 <30>[ 12.175275] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10855 22:51:26.766334 <30>[ 12.195093] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10856 22:51:26.773401 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10857 22:51:26.773901
10858 22:51:26.791053 <30>[ 12.219495] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10859 22:51:26.801402 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10860 22:51:26.802021
10861 22:51:26.818713 <30>[ 12.247171] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10862 22:51:26.828706 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10863 22:51:26.829337
10864 22:51:26.843939 <30>[ 12.275635] systemd[1]: Reached target paths.target - Path Units.
10865 22:51:26.850975 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10866 22:51:26.854043
10867 22:51:26.871440 <30>[ 12.299449] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10868 22:51:26.877369 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10869 22:51:26.877860
10870 22:51:26.891136 <30>[ 12.323066] systemd[1]: Reached target slices.target - Slice Units.
10871 22:51:26.901829 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10872 22:51:26.902383
10873 22:51:26.915973 <30>[ 12.347573] systemd[1]: Reached target swap.target - Swaps.
10874 22:51:26.922518 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10875 22:51:26.923074
10876 22:51:26.943158 <30>[ 12.371590] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10877 22:51:26.952964 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10878 22:51:26.953549
10879 22:51:26.971049 <30>[ 12.399574] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10880 22:51:26.980583 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10881 22:51:26.981049
10882 22:51:27.002698 <30>[ 12.430885] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10883 22:51:27.012268 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10884 22:51:27.012736
10885 22:51:27.028547 <30>[ 12.456807] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10886 22:51:27.038164 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10887 22:51:27.038866
10888 22:51:27.055079 <30>[ 12.483728] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10889 22:51:27.061942 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10890 22:51:27.062401
10891 22:51:27.080696 <30>[ 12.508986] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10892 22:51:27.090627 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10893 22:51:27.091187
10894 22:51:27.111226 <30>[ 12.539654] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10895 22:51:27.121408 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10896 22:51:27.122021
10897 22:51:27.139051 <30>[ 12.567577] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10898 22:51:27.149182 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10899 22:51:27.149667
10900 22:51:27.206933 <30>[ 12.635336] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10901 22:51:27.213399 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10902 22:51:27.213896
10903 22:51:27.234978 <30>[ 12.663744] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10904 22:51:27.242065 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10905 22:51:27.242488
10906 22:51:27.267094 <30>[ 12.695921] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10907 22:51:27.273865 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10908 22:51:27.274290
10909 22:51:27.301554 <30>[ 12.723576] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10910 22:51:27.351366 <30>[ 12.779721] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10911 22:51:27.360962 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10912 22:51:27.361554
10913 22:51:27.384367 <30>[ 12.812744] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10914 22:51:27.390748 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10915 22:51:27.391313
10916 22:51:27.414494 <30>[ 12.843058] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10917 22:51:27.420929 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10918 22:51:27.421395
10919 22:51:27.443965 <30>[ 12.872734] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10920 22:51:27.450788 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10921 22:51:27.451206
10922 22:51:27.460765 <6>[ 12.888362] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10923 22:51:27.475089 <30>[ 12.903562] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10924 22:51:27.484671 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10925 22:51:27.485111
10926 22:51:27.508424 <30>[ 12.936971] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10927 22:51:27.515123 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10928 22:51:27.515612
10929 22:51:27.540089 <30>[ 12.968732] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10930 22:51:27.550210 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 12.981533] fuse: init (API version 7.37)
10931 22:51:27.550629 el Module loop...
10932 22:51:27.550953
10933 22:51:27.578655 <30>[ 13.007336] systemd[1]: Starting systemd-journald.service - Journal Service...
10934 22:51:27.585664 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10935 22:51:27.586215
10936 22:51:27.647157 <30>[ 13.075850] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10937 22:51:27.653652 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10938 22:51:27.654067
10939 22:51:27.683475 <30>[ 13.108761] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10940 22:51:27.690055 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10941 22:51:27.690605
10942 22:51:27.716333 <30>[ 13.145021] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10943 22:51:27.727072 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10944 22:51:27.727627
10945 22:51:27.733587 <3>[ 13.162774] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 22:51:27.748106 <30>[ 13.176453] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10947 22:51:27.755330 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10948 22:51:27.755780
10949 22:51:27.765596 <3>[ 13.192394] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 22:51:27.779681 <30>[ 13.208488] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10951 22:51:27.786337 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10952 22:51:27.786754
10953 22:51:27.807053 <30>[ 13.235361] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10954 22:51:27.813457 <3>[ 13.240112] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 22:51:27.823656 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10956 22:51:27.824079
10957 22:51:27.843035 <30>[ 13.271371] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10958 22:51:27.853431 [[0;32m OK [<3>[ 13.280224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 22:51:27.859644 0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10960 22:51:27.860077
10961 22:51:27.879348 <30>[ 13.307576] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10962 22:51:27.889281 <3>[ 13.309818] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 22:51:27.895987 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10964 22:51:27.896410
10965 22:51:27.916324 <30>[ 13.344451] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10966 22:51:27.922565 <3>[ 13.345696] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 22:51:27.932739 <30>[ 13.352625] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10968 22:51:27.938905 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10969 22:51:27.939453
10970 22:51:27.952470 <3>[ 13.380630] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 22:51:27.961961 <30>[ 13.390507] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10972 22:51:27.968800 <30>[ 13.398607] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10973 22:51:27.982490 [[0;32m OK [0m] Finished [0<3>[ 13.409398] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 22:51:27.985933 ;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10975 22:51:27.986402
10976 22:51:28.001015 <30>[ 13.432260] systemd[1]: modprobe@drm.service: Deactivated successfully.
10977 22:51:28.011249 <3>[ 13.439492] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 22:51:28.017437 <30>[ 13.440152] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10979 22:51:28.027813 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10980 22:51:28.028414
10981 22:51:28.041390 <3>[ 13.469355] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 22:51:28.051722 <30>[ 13.480317] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10983 22:51:28.062311 <30>[ 13.488554] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10984 22:51:28.068815 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10985 22:51:28.069286
10986 22:51:28.084199 <30>[ 13.515899] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10987 22:51:28.095029 <30>[ 13.523462] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10988 22:51:28.101369 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10989 22:51:28.101954
10990 22:51:28.119184 <30>[ 13.547507] systemd[1]: Started systemd-journald.service - Journal Service.
10991 22:51:28.125300 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10992 22:51:28.125952
10993 22:51:28.144174 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10994 22:51:28.144735
10995 22:51:28.163938 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10996 22:51:28.164704
10997 22:51:28.183438 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10998 22:51:28.183993
10999 22:51:28.200432 <4>[ 13.618978] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11000 22:51:28.206670 <3>[ 13.635688] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11001 22:51:28.213737 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11002 22:51:28.214321
11003 22:51:28.237272 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11004 22:51:28.237920
11005 22:51:28.257742 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11006 22:51:28.258331
11007 22:51:28.299700 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11008 22:51:28.300271
11009 22:51:28.327213 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11010 22:51:28.327790
11011 22:51:28.352735 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11012 22:51:28.353287
11013 22:51:28.380590 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11014 22:51:28.381027
11015 22:51:28.428053 <46>[ 13.856546] systemd-journald[310]: Received client request to flush runtime journal.
11016 22:51:28.440246 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11017 22:51:28.440683
11018 22:51:28.466210 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11019 22:51:28.466835
11020 22:51:28.495256 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11021 22:51:28.495754
11022 22:51:28.519317 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11023 22:51:28.519749
11024 22:51:28.539614 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11025 22:51:28.540045
11026 22:51:29.539841 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11027 22:51:29.540001
11028 22:51:29.840114 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11029 22:51:29.840261
11030 22:51:29.860605 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11031 22:51:29.860702
11032 22:51:29.911658 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11033 22:51:29.912136
11034 22:51:30.032276 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11035 22:51:30.032849
11036 22:51:30.054872 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11037 22:51:30.055443
11038 22:51:30.074800 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11039 22:51:30.075364
11040 22:51:30.126998 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11041 22:51:30.127555
11042 22:51:30.151117 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11043 22:51:30.151585
11044 22:51:30.403930 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11045 22:51:30.404446
11046 22:51:30.443085 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11047 22:51:30.443641
11048 22:51:30.535859 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11049 22:51:30.536301
11050 22:51:30.826975 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11051 22:51:30.827572
11052 22:51:30.859469 <6>[ 16.291685] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11053 22:51:30.888143 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11054 22:51:30.888580
11055 22:51:30.930886 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11056 22:51:30.931315
11057 22:51:30.961004 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11058 22:51:30.961434
11059 22:51:31.042784 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11060 22:51:31.043395
11061 22:51:31.098908 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11062 22:51:31.099004
11063 22:51:31.123622 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11064 22:51:31.123727
11065 22:51:31.145645 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11066 22:51:31.145734
11067 22:51:31.173124 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11068 22:51:31.173772
11069 22:51:31.203715 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11070 22:51:31.204281
11071 22:51:31.271267 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11072 22:51:31.271815
11073 22:51:31.292773 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11074 22:51:31.293286
11075 22:51:31.334686 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11076 22:51:31.335232
11077 22:51:31.358747 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11078 22:51:31.359310
11079 22:51:31.374251 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11080 22:51:31.374925
11081 22:51:31.393959 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11082 22:51:31.394430
11083 22:51:31.414099 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11084 22:51:31.414647
11085 22:51:31.445251 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11086 22:51:31.445813
11087 22:51:31.470046 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11088 22:51:31.470591
11089 22:51:31.486147 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11090 22:51:31.486690
11091 22:51:31.506938 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11092 22:51:31.507512
11093 22:51:31.526606 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11094 22:51:31.527147
11095 22:51:31.542000 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11096 22:51:31.542541
11097 22:51:31.560620 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11098 22:51:31.561209
11099 22:51:31.578253 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11100 22:51:31.578796
11101 22:51:31.584876 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11102 22:51:31.585440
11103 22:51:31.652000 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11104 22:51:31.652549
11105 22:51:31.686932 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11106 22:51:31.687398
11107 22:51:31.807509 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11108 22:51:31.808016
11109 22:51:31.834215 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11110 22:51:31.834679
11111 22:51:31.879507 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11112 22:51:31.879609
11113 22:51:31.935076 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11114 22:51:31.935178
11115 22:51:31.978747 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11116 22:51:31.979015
11117 22:51:32.002475 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11118 22:51:32.002923
11119 22:51:32.018638 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11120 22:51:32.019098
11121 22:51:32.057908 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11122 22:51:32.058046
11123 22:51:32.174401 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11124 22:51:32.174960
11125 22:51:32.193316 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11126 22:51:32.193905
11127 22:51:32.211046 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11128 22:51:32.211624
11129 22:51:32.252030 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11130 22:51:32.252579
11131 22:51:32.311653 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11132 22:51:32.312200
11133 22:51:32.418307
11134 22:51:32.418855
11135 22:51:32.421650 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11136 22:51:32.422106
11137 22:51:32.424700 debian-bookworm-arm64 login: root (automatic login)
11138 22:51:32.425150
11139 22:51:32.425497
11140 22:51:32.722921 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
11141 22:51:32.723458
11142 22:51:32.729175 The programs included with the Debian GNU/Linux system are free software;
11143 22:51:32.735638 the exact distribution terms for each program are described in the
11144 22:51:32.738896 individual files in /usr/share/doc/*/copyright.
11145 22:51:32.738976
11146 22:51:32.745321 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11147 22:51:32.748488 permitted by applicable law.
11148 22:51:32.874604 Matched prompt #10: / #
11150 22:51:32.875818 Setting prompt string to ['/ #']
11151 22:51:32.876279 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11153 22:51:32.877323 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11154 22:51:32.877923 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
11155 22:51:32.878318 Setting prompt string to ['/ #']
11156 22:51:32.878654 Forcing a shell prompt, looking for ['/ #']
11158 22:51:32.929491 / #
11159 22:51:32.930167 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11160 22:51:32.930601 Waiting using forced prompt support (timeout 00:02:30)
11161 22:51:32.936355
11162 22:51:32.937281 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11163 22:51:32.937918 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
11165 22:51:33.039235 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683708/extract-nfsrootfs-3ye22qzo'
11166 22:51:33.046092 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683708/extract-nfsrootfs-3ye22qzo'
11168 22:51:33.147862 / # export NFS_SERVER_IP='192.168.201.1'
11169 22:51:33.154413 export NFS_SERVER_IP='192.168.201.1'
11170 22:51:33.155336 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11171 22:51:33.155836 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
11172 22:51:33.156304 end: 2 depthcharge-action (duration 00:01:48) [common]
11173 22:51:33.156783 start: 3 lava-test-retry (timeout 00:01:00) [common]
11174 22:51:33.157240 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11175 22:51:33.157671 Using namespace: common
11177 22:51:33.258808 / # #
11178 22:51:33.258984 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11179 22:51:33.264312 #
11180 22:51:33.264674 Using /lava-13683708
11182 22:51:33.365288 / # export SHELL=/bin/sh
11183 22:51:33.372163 export SHELL=/bin/sh
11185 22:51:33.473835 / # . /lava-13683708/environment
11186 22:51:33.480197 . /lava-13683708/environment
11188 22:51:33.588942 / # /lava-13683708/bin/lava-test-runner /lava-13683708/0
11189 22:51:33.589129 Test shell timeout: 10s (minimum of the action and connection timeout)
11190 22:51:33.594294 /lava-13683708/bin/lava-test-runner /lava-13683708/0
11191 22:51:33.889576 + export TESTRUN_ID=0_dmesg
11192 22:51:33.892751 + cd /lava-13683708/0/tests/0_dmesg
11193 22:51:33.895743 + cat uuid
11194 22:51:33.917501 + UUID=13683708_<8>[ 19.346420] <LAVA_SIGNAL_STARTRUN 0_dmesg 13683708_1.6.2.3.1>
11195 22:51:33.918154 1.6.2.3.1
11196 22:51:33.918539 + set +x
11197 22:51:33.919256 Received signal: <STARTRUN> 0_dmesg 13683708_1.6.2.3.1
11198 22:51:33.919690 Starting test lava.0_dmesg (13683708_1.6.2.3.1)
11199 22:51:33.920156 Skipping test definition patterns.
11200 22:51:33.923628 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11201 22:51:34.068725 <8>[ 19.497793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11202 22:51:34.069596 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11204 22:51:34.176039 <8>[ 19.605178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11205 22:51:34.177064 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11207 22:51:34.288734 <8>[ 19.718010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11208 22:51:34.289615 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11210 22:51:34.292478 + set +x
11211 22:51:34.295226 <8>[ 19.727718] <LAVA_SIGNAL_ENDRUN 0_dmesg 13683708_1.6.2.3.1>
11212 22:51:34.296017 Received signal: <ENDRUN> 0_dmesg 13683708_1.6.2.3.1
11213 22:51:34.296454 Ending use of test pattern.
11214 22:51:34.296811 Ending test lava.0_dmesg (13683708_1.6.2.3.1), duration 0.38
11216 22:51:34.302394 <LAVA_TEST_RUNNER EXIT>
11217 22:51:34.303216 ok: lava_test_shell seems to have completed
11218 22:51:34.303852 alert: pass
crit: pass
emerg: pass
11219 22:51:34.304304 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11220 22:51:34.304742 end: 3 lava-test-retry (duration 00:00:01) [common]
11221 22:51:34.305198 start: 4 finalize (timeout 00:07:45) [common]
11222 22:51:34.305714 start: 4.1 power-off (timeout 00:00:30) [common]
11223 22:51:34.306529 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11224 22:51:34.434498 >> Command sent successfully.
11225 22:51:34.446489 Returned 0 in 0 seconds
11226 22:51:34.547863 end: 4.1 power-off (duration 00:00:00) [common]
11228 22:51:34.549381 start: 4.2 read-feedback (timeout 00:07:45) [common]
11229 22:51:34.550859 Listened to connection for namespace 'common' for up to 1s
11230 22:51:35.551258 Finalising connection for namespace 'common'
11231 22:51:35.551458 Disconnecting from shell: Finalise
11232 22:51:35.551559 / #
11233 22:51:35.652132 end: 4.2 read-feedback (duration 00:00:01) [common]
11234 22:51:35.652868 end: 4 finalize (duration 00:00:01) [common]
11235 22:51:35.653487 Cleaning after the job
11236 22:51:35.654064 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/ramdisk
11237 22:51:35.664203 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/kernel
11238 22:51:35.689989 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/dtb
11239 22:51:35.690358 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/nfsrootfs
11240 22:51:35.755373 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683708/tftp-deploy-okay74ba/modules
11241 22:51:35.760871 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683708
11242 22:51:36.073932 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683708
11243 22:51:36.074109 Job finished correctly