Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 22
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
1 22:52:58.714901 lava-dispatcher, installed at version: 2024.01
2 22:52:58.715123 start: 0 validate
3 22:52:58.715258 Start time: 2024-05-07 22:52:58.715250+00:00 (UTC)
4 22:52:58.715393 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:52:58.715523 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 22:52:58.974366 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:52:58.974544 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:53:31.981942 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:53:31.982652 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:53:32.236856 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:53:32.237470 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:53:35.990575 validate duration: 37.28
14 22:53:35.991890 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:53:35.992476 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:53:35.993041 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:53:35.993692 Not decompressing ramdisk as can be used compressed.
18 22:53:35.994162 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 22:53:35.994531 saving as /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/ramdisk/rootfs.cpio.gz
20 22:53:35.994887 total size: 39026414 (37 MB)
21 22:53:36.255274 progress 0 % (0 MB)
22 22:53:36.265234 progress 5 % (1 MB)
23 22:53:36.275101 progress 10 % (3 MB)
24 22:53:36.284914 progress 15 % (5 MB)
25 22:53:36.294971 progress 20 % (7 MB)
26 22:53:36.304781 progress 25 % (9 MB)
27 22:53:36.314893 progress 30 % (11 MB)
28 22:53:36.324766 progress 35 % (13 MB)
29 22:53:36.334891 progress 40 % (14 MB)
30 22:53:36.344948 progress 45 % (16 MB)
31 22:53:36.355031 progress 50 % (18 MB)
32 22:53:36.365079 progress 55 % (20 MB)
33 22:53:36.375258 progress 60 % (22 MB)
34 22:53:36.385278 progress 65 % (24 MB)
35 22:53:36.395432 progress 70 % (26 MB)
36 22:53:36.405439 progress 75 % (27 MB)
37 22:53:36.415252 progress 80 % (29 MB)
38 22:53:36.425352 progress 85 % (31 MB)
39 22:53:36.435398 progress 90 % (33 MB)
40 22:53:36.445315 progress 95 % (35 MB)
41 22:53:36.455407 progress 100 % (37 MB)
42 22:53:36.455709 37 MB downloaded in 0.46 s (80.76 MB/s)
43 22:53:36.455874 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:53:36.456215 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:53:36.456302 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:53:36.456385 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:53:36.456527 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:53:36.456595 saving as /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/kernel/Image
50 22:53:36.456656 total size: 54682112 (52 MB)
51 22:53:36.456731 No compression specified
52 22:53:36.457867 progress 0 % (0 MB)
53 22:53:36.471809 progress 5 % (2 MB)
54 22:53:36.485789 progress 10 % (5 MB)
55 22:53:36.500557 progress 15 % (7 MB)
56 22:53:36.514487 progress 20 % (10 MB)
57 22:53:36.528454 progress 25 % (13 MB)
58 22:53:36.544220 progress 30 % (15 MB)
59 22:53:36.560098 progress 35 % (18 MB)
60 22:53:36.574228 progress 40 % (20 MB)
61 22:53:36.588011 progress 45 % (23 MB)
62 22:53:36.602098 progress 50 % (26 MB)
63 22:53:36.616085 progress 55 % (28 MB)
64 22:53:36.630529 progress 60 % (31 MB)
65 22:53:36.644247 progress 65 % (33 MB)
66 22:53:36.658552 progress 70 % (36 MB)
67 22:53:36.672471 progress 75 % (39 MB)
68 22:53:36.686565 progress 80 % (41 MB)
69 22:53:36.700392 progress 85 % (44 MB)
70 22:53:36.714235 progress 90 % (46 MB)
71 22:53:36.728118 progress 95 % (49 MB)
72 22:53:36.741874 progress 100 % (52 MB)
73 22:53:36.742153 52 MB downloaded in 0.29 s (182.66 MB/s)
74 22:53:36.742312 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:53:36.742546 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:53:36.742634 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:53:36.742726 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:53:36.742874 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:53:36.742943 saving as /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/dtb/mt8192-asurada-spherion-r0.dtb
81 22:53:36.743004 total size: 47258 (0 MB)
82 22:53:36.743065 No compression specified
83 22:53:36.744173 progress 69 % (0 MB)
84 22:53:36.744440 progress 100 % (0 MB)
85 22:53:36.744688 0 MB downloaded in 0.00 s (26.84 MB/s)
86 22:53:36.744905 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:53:36.745132 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:53:36.745216 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:53:36.745298 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:53:36.745414 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:53:36.745479 saving as /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/modules/modules.tar
93 22:53:36.745538 total size: 8594396 (8 MB)
94 22:53:36.745599 Using unxz to decompress xz
95 22:53:36.750298 progress 0 % (0 MB)
96 22:53:36.770177 progress 5 % (0 MB)
97 22:53:36.796448 progress 10 % (0 MB)
98 22:53:36.821748 progress 15 % (1 MB)
99 22:53:36.846775 progress 20 % (1 MB)
100 22:53:36.873116 progress 25 % (2 MB)
101 22:53:36.899019 progress 30 % (2 MB)
102 22:53:36.923968 progress 35 % (2 MB)
103 22:53:36.949461 progress 40 % (3 MB)
104 22:53:36.975235 progress 45 % (3 MB)
105 22:53:37.001099 progress 50 % (4 MB)
106 22:53:37.027700 progress 55 % (4 MB)
107 22:53:37.054724 progress 60 % (4 MB)
108 22:53:37.080099 progress 65 % (5 MB)
109 22:53:37.106169 progress 70 % (5 MB)
110 22:53:37.132056 progress 75 % (6 MB)
111 22:53:37.159245 progress 80 % (6 MB)
112 22:53:37.185513 progress 85 % (6 MB)
113 22:53:37.216009 progress 90 % (7 MB)
114 22:53:37.246799 progress 95 % (7 MB)
115 22:53:37.274135 progress 100 % (8 MB)
116 22:53:37.279412 8 MB downloaded in 0.53 s (15.35 MB/s)
117 22:53:37.279677 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:53:37.279943 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:53:37.280081 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:53:37.280197 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:53:37.280282 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:53:37.280373 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:53:37.280634 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o
125 22:53:37.280801 makedir: /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin
126 22:53:37.280936 makedir: /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/tests
127 22:53:37.281069 makedir: /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/results
128 22:53:37.281219 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-add-keys
129 22:53:37.281414 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-add-sources
130 22:53:37.281577 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-background-process-start
131 22:53:37.281725 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-background-process-stop
132 22:53:37.281853 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-common-functions
133 22:53:37.281980 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-echo-ipv4
134 22:53:37.282125 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-install-packages
135 22:53:37.282248 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-installed-packages
136 22:53:37.282371 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-os-build
137 22:53:37.282526 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-probe-channel
138 22:53:37.282647 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-probe-ip
139 22:53:37.282770 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-target-ip
140 22:53:37.282925 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-target-mac
141 22:53:37.283076 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-target-storage
142 22:53:37.283234 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-test-case
143 22:53:37.283436 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-test-event
144 22:53:37.283628 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-test-feedback
145 22:53:37.283774 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-test-raise
146 22:53:37.283909 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-test-reference
147 22:53:37.284063 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-test-runner
148 22:53:37.284189 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-test-set
149 22:53:37.284349 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-test-shell
150 22:53:37.284507 Updating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-install-packages (oe)
151 22:53:37.284652 Updating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/bin/lava-installed-packages (oe)
152 22:53:37.284819 Creating /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/environment
153 22:53:37.284932 LAVA metadata
154 22:53:37.285025 - LAVA_JOB_ID=13683680
155 22:53:37.285101 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:53:37.285225 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:53:37.285308 skipped lava-vland-overlay
158 22:53:37.285382 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:53:37.285462 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:53:37.285523 skipped lava-multinode-overlay
161 22:53:37.285596 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:53:37.285721 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:53:37.285828 Loading test definitions
164 22:53:37.285919 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:53:37.285993 Using /lava-13683680 at stage 0
166 22:53:37.286317 uuid=13683680_1.5.2.3.1 testdef=None
167 22:53:37.286406 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:53:37.286491 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:53:37.287048 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:53:37.287299 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:53:37.288051 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:53:37.288280 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:53:37.288946 runner path: /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/0/tests/0_cros-ec test_uuid 13683680_1.5.2.3.1
176 22:53:37.289104 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:53:37.289338 Creating lava-test-runner.conf files
179 22:53:37.289401 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683680/lava-overlay-yciu3k2o/lava-13683680/0 for stage 0
180 22:53:37.289490 - 0_cros-ec
181 22:53:37.289585 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:53:37.289693 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:53:37.297206 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:53:37.297400 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:53:37.297508 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:53:37.297597 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:53:37.297683 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:53:38.535021 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:53:38.535533 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 22:53:38.535704 extracting modules file /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683680/extract-overlay-ramdisk-_a45q6p0/ramdisk
191 22:53:38.771266 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:53:38.771442 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 22:53:38.771543 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683680/compress-overlay-59beg6r2/overlay-1.5.2.4.tar.gz to ramdisk
194 22:53:38.771614 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683680/compress-overlay-59beg6r2/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683680/extract-overlay-ramdisk-_a45q6p0/ramdisk
195 22:53:38.778383 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:53:38.778510 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 22:53:38.778655 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:53:38.778778 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 22:53:38.778872 Building ramdisk /var/lib/lava/dispatcher/tmp/13683680/extract-overlay-ramdisk-_a45q6p0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683680/extract-overlay-ramdisk-_a45q6p0/ramdisk
200 22:53:43.069553 >> 335863 blocks
201 22:53:48.198045 rename /var/lib/lava/dispatcher/tmp/13683680/extract-overlay-ramdisk-_a45q6p0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/ramdisk/ramdisk.cpio.gz
202 22:53:48.198515 end: 1.5.7 compress-ramdisk (duration 00:00:09) [common]
203 22:53:48.198698 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
204 22:53:48.198849 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
205 22:53:48.199032 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/kernel/Image'
206 22:54:03.118572 Returned 0 in 14 seconds
207 22:54:03.219233 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/kernel/image.itb
208 22:54:03.975984 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:54:03.976411 output: Created: Tue May 7 23:54:03 2024
210 22:54:03.976522 output: Image 0 (kernel-1)
211 22:54:03.976609 output: Description:
212 22:54:03.976693 output: Created: Tue May 7 23:54:03 2024
213 22:54:03.976774 output: Type: Kernel Image
214 22:54:03.976855 output: Compression: lzma compressed
215 22:54:03.976935 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
216 22:54:03.977035 output: Architecture: AArch64
217 22:54:03.977132 output: OS: Linux
218 22:54:03.977227 output: Load Address: 0x00000000
219 22:54:03.977323 output: Entry Point: 0x00000000
220 22:54:03.977425 output: Hash algo: crc32
221 22:54:03.977523 output: Hash value: 727ee7c6
222 22:54:03.977622 output: Image 1 (fdt-1)
223 22:54:03.977721 output: Description: mt8192-asurada-spherion-r0
224 22:54:03.977814 output: Created: Tue May 7 23:54:03 2024
225 22:54:03.977908 output: Type: Flat Device Tree
226 22:54:03.978003 output: Compression: uncompressed
227 22:54:03.978097 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 22:54:03.978192 output: Architecture: AArch64
229 22:54:03.978291 output: Hash algo: crc32
230 22:54:03.978409 output: Hash value: 0f8e4d2e
231 22:54:03.978494 output: Image 2 (ramdisk-1)
232 22:54:03.978578 output: Description: unavailable
233 22:54:03.978661 output: Created: Tue May 7 23:54:03 2024
234 22:54:03.978745 output: Type: RAMDisk Image
235 22:54:03.978828 output: Compression: Unknown Compression
236 22:54:03.978911 output: Data Size: 52129598 Bytes = 50907.81 KiB = 49.71 MiB
237 22:54:03.978994 output: Architecture: AArch64
238 22:54:03.979076 output: OS: Linux
239 22:54:03.979159 output: Load Address: unavailable
240 22:54:03.979241 output: Entry Point: unavailable
241 22:54:03.979326 output: Hash algo: crc32
242 22:54:03.979409 output: Hash value: 04e1935f
243 22:54:03.979491 output: Default Configuration: 'conf-1'
244 22:54:03.979573 output: Configuration 0 (conf-1)
245 22:54:03.979655 output: Description: mt8192-asurada-spherion-r0
246 22:54:03.979738 output: Kernel: kernel-1
247 22:54:03.979820 output: Init Ramdisk: ramdisk-1
248 22:54:03.979902 output: FDT: fdt-1
249 22:54:03.980025 output: Loadables: kernel-1
250 22:54:03.980108 output:
251 22:54:03.980349 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 22:54:03.980478 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 22:54:03.980616 end: 1.5 prepare-tftp-overlay (duration 00:00:27) [common]
254 22:54:03.980743 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:32) [common]
255 22:54:03.980849 No LXC device requested
256 22:54:03.980961 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:54:03.981080 start: 1.7 deploy-device-env (timeout 00:09:32) [common]
258 22:54:03.981192 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:54:03.981294 Checking files for TFTP limit of 4294967296 bytes.
260 22:54:03.981944 end: 1 tftp-deploy (duration 00:00:28) [common]
261 22:54:03.982082 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:54:03.982223 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:54:03.982399 substitutions:
264 22:54:03.982497 - {DTB}: 13683680/tftp-deploy-ae11a8wq/dtb/mt8192-asurada-spherion-r0.dtb
265 22:54:03.982590 - {INITRD}: 13683680/tftp-deploy-ae11a8wq/ramdisk/ramdisk.cpio.gz
266 22:54:03.982714 - {KERNEL}: 13683680/tftp-deploy-ae11a8wq/kernel/Image
267 22:54:03.982802 - {LAVA_MAC}: None
268 22:54:03.982890 - {PRESEED_CONFIG}: None
269 22:54:03.982976 - {PRESEED_LOCAL}: None
270 22:54:03.983061 - {RAMDISK}: 13683680/tftp-deploy-ae11a8wq/ramdisk/ramdisk.cpio.gz
271 22:54:03.983146 - {ROOT_PART}: None
272 22:54:03.983230 - {ROOT}: None
273 22:54:03.983315 - {SERVER_IP}: 192.168.201.1
274 22:54:03.983399 - {TEE}: None
275 22:54:03.983482 Parsed boot commands:
276 22:54:03.983565 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:54:03.983796 Parsed boot commands: tftpboot 192.168.201.1 13683680/tftp-deploy-ae11a8wq/kernel/image.itb 13683680/tftp-deploy-ae11a8wq/kernel/cmdline
278 22:54:03.983914 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:54:03.984057 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:54:03.984149 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:54:03.984235 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:54:03.984308 Not connected, no need to disconnect.
283 22:54:03.984382 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:54:03.984463 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:54:03.984532 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 22:54:03.988537 Setting prompt string to ['lava-test: # ']
287 22:54:03.988944 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:54:03.989071 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:54:03.989204 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:54:03.989323 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:54:03.989552 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 22:54:09.123332 >> Command sent successfully.
293 22:54:09.125719 Returned 0 in 5 seconds
294 22:54:09.226179 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:54:09.226653 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:54:09.226794 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:54:09.226912 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:54:09.227012 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:54:09.227114 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:54:09.227486 [Enter `^Ec?' for help]
302 22:54:09.399436
303 22:54:09.399646
304 22:54:09.399762 F0: 102B 0000
305 22:54:09.399867
306 22:54:09.399999 F3: 1001 0000 [0200]
307 22:54:09.402974
308 22:54:09.403143 F3: 1001 0000
309 22:54:09.403249
310 22:54:09.403342 F7: 102D 0000
311 22:54:09.403433
312 22:54:09.403523 F1: 0000 0000
313 22:54:09.407312
314 22:54:09.407500 V0: 0000 0000 [0001]
315 22:54:09.407610
316 22:54:09.407703 00: 0007 8000
317 22:54:09.407799
318 22:54:09.410596 01: 0000 0000
319 22:54:09.410763
320 22:54:09.410866 BP: 0C00 0209 [0000]
321 22:54:09.410959
322 22:54:09.414115 G0: 1182 0000
323 22:54:09.414287
324 22:54:09.414387 EC: 0000 0021 [4000]
325 22:54:09.414479
326 22:54:09.417428 S7: 0000 0000 [0000]
327 22:54:09.417599
328 22:54:09.417700 CC: 0000 0000 [0001]
329 22:54:09.417793
330 22:54:09.421325 T0: 0000 0040 [010F]
331 22:54:09.421504
332 22:54:09.421606 Jump to BL
333 22:54:09.421697
334 22:54:09.446223
335 22:54:09.446435
336 22:54:09.446546
337 22:54:09.453965 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:54:09.457904 ARM64: Exception handlers installed.
339 22:54:09.461417 ARM64: Testing exception
340 22:54:09.465345 ARM64: Done test exception
341 22:54:09.469133 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:54:09.480896 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:54:09.486988 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:54:09.496874 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:54:09.504014 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:54:09.513804 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:54:09.524579 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:54:09.530803 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:54:09.548987 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:54:09.552929 WDT: Last reset was cold boot
351 22:54:09.555700 SPI1(PAD0) initialized at 2873684 Hz
352 22:54:09.559226 SPI5(PAD0) initialized at 992727 Hz
353 22:54:09.562970 VBOOT: Loading verstage.
354 22:54:09.569060 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:54:09.572529 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:54:09.575475 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:54:09.579132 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:54:09.586374 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:54:09.593161 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:54:09.604581 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 22:54:09.604789
362 22:54:09.604897
363 22:54:09.615245 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:54:09.618163 ARM64: Exception handlers installed.
365 22:54:09.618301 ARM64: Testing exception
366 22:54:09.621554 ARM64: Done test exception
367 22:54:09.625610 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:54:09.631466 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:54:09.644833 Probing TPM: . done!
370 22:54:09.645001 TPM ready after 0 ms
371 22:54:09.651838 Connected to device vid:did:rid of 1ae0:0028:00
372 22:54:09.659036 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 22:54:09.718680 Initialized TPM device CR50 revision 0
374 22:54:09.730408 tlcl_send_startup: Startup return code is 0
375 22:54:09.730574 TPM: setup succeeded
376 22:54:09.741544 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:54:09.750503 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:54:09.762645 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:54:09.772617 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:54:09.776387 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:54:09.780126 in-header: 03 07 00 00 08 00 00 00
382 22:54:09.783382 in-data: aa e4 47 04 13 02 00 00
383 22:54:09.787692 Chrome EC: UHEPI supported
384 22:54:09.790721 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:54:09.796344 in-header: 03 95 00 00 08 00 00 00
386 22:54:09.799771 in-data: 18 20 20 08 00 00 00 00
387 22:54:09.799909 Phase 1
388 22:54:09.803624 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:54:09.811076 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:54:09.817960 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:54:09.818160 Recovery requested (1009000e)
392 22:54:09.830805 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:54:09.834416 tlcl_extend: response is 0
394 22:54:09.844709 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:54:09.848937 tlcl_extend: response is 0
396 22:54:09.856617 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:54:09.875798 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 22:54:09.882544 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:54:09.882704
400 22:54:09.882781
401 22:54:09.892653 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:54:09.896389 ARM64: Exception handlers installed.
403 22:54:09.899339 ARM64: Testing exception
404 22:54:09.899460 ARM64: Done test exception
405 22:54:09.921324 pmic_efuse_setting: Set efuses in 11 msecs
406 22:54:09.925039 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:54:09.931261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:54:09.934998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:54:09.942307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:54:09.946282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:54:09.949816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:54:09.956762 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:54:09.960514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:54:09.964574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:54:09.968787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:54:09.975773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:54:09.979831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:54:09.983409 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:54:09.986751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:54:09.994284 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:54:09.998110 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:54:10.004984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:54:10.012548 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:54:10.016997 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:54:10.024384 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:54:10.028025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:54:10.034912 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:54:10.038593 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:54:10.046557 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:54:10.050209 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:54:10.054037 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:54:10.061717 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:54:10.065141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:54:10.072345 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:54:10.075951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:54:10.079817 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:54:10.087219 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:54:10.090715 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:54:10.094488 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:54:10.101465 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:54:10.105158 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:54:10.108942 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:54:10.116419 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:54:10.119936 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:54:10.123756 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:54:10.130909 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:54:10.134887 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:54:10.139151 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:54:10.142984 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:54:10.145903 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:54:10.149619 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:54:10.157469 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:54:10.161240 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:54:10.164799 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:54:10.168351 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:54:10.171582 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:54:10.175318 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:54:10.183238 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:54:10.194429 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:54:10.197547 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:54:10.205262 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:54:10.216133 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:54:10.220080 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:54:10.223830 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:54:10.227066 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:54:10.235429 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 22:54:10.238447 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:54:10.243281 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 22:54:10.250223 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:54:10.259683 [RTC]rtc_get_frequency_meter,154: input=15, output=760
471 22:54:10.268751 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 22:54:10.278426 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 22:54:10.288018 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 22:54:10.297158 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 22:54:10.306574 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 22:54:10.316678 [RTC]rtc_get_frequency_meter,154: input=17, output=806
477 22:54:10.320006 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 22:54:10.326998 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 22:54:10.331321 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:54:10.334688 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:54:10.338417 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:54:10.342318 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:54:10.345670 ADC[4]: Raw value=905465 ID=7
484 22:54:10.349728 ADC[3]: Raw value=213441 ID=1
485 22:54:10.349899 RAM Code: 0x71
486 22:54:10.353281 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:54:10.361003 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:54:10.368438 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:54:10.375539 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:54:10.375745 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:54:10.379624 in-header: 03 07 00 00 08 00 00 00
492 22:54:10.383742 in-data: aa e4 47 04 13 02 00 00
493 22:54:10.387479 Chrome EC: UHEPI supported
494 22:54:10.391781 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:54:10.396776 in-header: 03 95 00 00 08 00 00 00
496 22:54:10.400552 in-data: 18 20 20 08 00 00 00 00
497 22:54:10.404209 MRC: failed to locate region type 0.
498 22:54:10.411840 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:54:10.415583 DRAM-K: Running full calibration
500 22:54:10.419308 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:54:10.422942 header.status = 0x0
502 22:54:10.426698 header.version = 0x6 (expected: 0x6)
503 22:54:10.426963 header.size = 0xd00 (expected: 0xd00)
504 22:54:10.431033 header.flags = 0x0
505 22:54:10.437793 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:54:10.454371 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 22:54:10.462219 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:54:10.462389 dram_init: ddr_geometry: 2
509 22:54:10.465262 [EMI] MDL number = 2
510 22:54:10.469169 [EMI] Get MDL freq = 0
511 22:54:10.469376 dram_init: ddr_type: 0
512 22:54:10.473379 is_discrete_lpddr4: 1
513 22:54:10.476859 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:54:10.477005
515 22:54:10.477078
516 22:54:10.477141 [Bian_co] ETT version 0.0.0.1
517 22:54:10.484543 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:54:10.484717
519 22:54:10.488279 dramc_set_vcore_voltage set vcore to 650000
520 22:54:10.488421 Read voltage for 800, 4
521 22:54:10.488497 Vio18 = 0
522 22:54:10.491739 Vcore = 650000
523 22:54:10.491886 Vdram = 0
524 22:54:10.491999 Vddq = 0
525 22:54:10.495568 Vmddr = 0
526 22:54:10.495737 dram_init: config_dvfs: 1
527 22:54:10.503093 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:54:10.506763 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:54:10.510769 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 22:54:10.514303 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 22:54:10.517413 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 22:54:10.520990 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 22:54:10.524280 MEM_TYPE=3, freq_sel=18
534 22:54:10.527892 sv_algorithm_assistance_LP4_1600
535 22:54:10.531167 ============ PULL DRAM RESETB DOWN ============
536 22:54:10.534943 ========== PULL DRAM RESETB DOWN end =========
537 22:54:10.541694 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:54:10.545549 ===================================
539 22:54:10.545697 LPDDR4 DRAM CONFIGURATION
540 22:54:10.549303 ===================================
541 22:54:10.553046 EX_ROW_EN[0] = 0x0
542 22:54:10.553184 EX_ROW_EN[1] = 0x0
543 22:54:10.556481 LP4Y_EN = 0x0
544 22:54:10.556600 WORK_FSP = 0x0
545 22:54:10.556672 WL = 0x2
546 22:54:10.560300 RL = 0x2
547 22:54:10.560421 BL = 0x2
548 22:54:10.563585 RPST = 0x0
549 22:54:10.566597 RD_PRE = 0x0
550 22:54:10.566715 WR_PRE = 0x1
551 22:54:10.569735 WR_PST = 0x0
552 22:54:10.569839 DBI_WR = 0x0
553 22:54:10.573144 DBI_RD = 0x0
554 22:54:10.573255 OTF = 0x1
555 22:54:10.576543 ===================================
556 22:54:10.581156 ===================================
557 22:54:10.581301 ANA top config
558 22:54:10.583894 ===================================
559 22:54:10.587886 DLL_ASYNC_EN = 0
560 22:54:10.590982 ALL_SLAVE_EN = 1
561 22:54:10.591111 NEW_RANK_MODE = 1
562 22:54:10.594576 DLL_IDLE_MODE = 1
563 22:54:10.598344 LP45_APHY_COMB_EN = 1
564 22:54:10.601932 TX_ODT_DIS = 1
565 22:54:10.602070 NEW_8X_MODE = 1
566 22:54:10.605828 ===================================
567 22:54:10.608579 ===================================
568 22:54:10.612082 data_rate = 1600
569 22:54:10.615308 CKR = 1
570 22:54:10.618844 DQ_P2S_RATIO = 8
571 22:54:10.622044 ===================================
572 22:54:10.625201 CA_P2S_RATIO = 8
573 22:54:10.625358 DQ_CA_OPEN = 0
574 22:54:10.629201 DQ_SEMI_OPEN = 0
575 22:54:10.631946 CA_SEMI_OPEN = 0
576 22:54:10.635056 CA_FULL_RATE = 0
577 22:54:10.638599 DQ_CKDIV4_EN = 1
578 22:54:10.641951 CA_CKDIV4_EN = 1
579 22:54:10.642107 CA_PREDIV_EN = 0
580 22:54:10.645378 PH8_DLY = 0
581 22:54:10.648379 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:54:10.651718 DQ_AAMCK_DIV = 4
583 22:54:10.654942 CA_AAMCK_DIV = 4
584 22:54:10.658799 CA_ADMCK_DIV = 4
585 22:54:10.658946 DQ_TRACK_CA_EN = 0
586 22:54:10.662316 CA_PICK = 800
587 22:54:10.665979 CA_MCKIO = 800
588 22:54:10.669631 MCKIO_SEMI = 0
589 22:54:10.673119 PLL_FREQ = 3068
590 22:54:10.673271 DQ_UI_PI_RATIO = 32
591 22:54:10.677011 CA_UI_PI_RATIO = 0
592 22:54:10.680567 ===================================
593 22:54:10.684230 ===================================
594 22:54:10.687948 memory_type:LPDDR4
595 22:54:10.688159 GP_NUM : 10
596 22:54:10.692465 SRAM_EN : 1
597 22:54:10.692623 MD32_EN : 0
598 22:54:10.695485 ===================================
599 22:54:10.699068 [ANA_INIT] >>>>>>>>>>>>>>
600 22:54:10.702633 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:54:10.705624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:54:10.709239 ===================================
603 22:54:10.709400 data_rate = 1600,PCW = 0X7600
604 22:54:10.712803 ===================================
605 22:54:10.716031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:54:10.722708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:54:10.729003 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:54:10.732219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:54:10.735540 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:54:10.739435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:54:10.742325 [ANA_INIT] flow start
612 22:54:10.742476 [ANA_INIT] PLL >>>>>>>>
613 22:54:10.745912 [ANA_INIT] PLL <<<<<<<<
614 22:54:10.749567 [ANA_INIT] MIDPI >>>>>>>>
615 22:54:10.749732 [ANA_INIT] MIDPI <<<<<<<<
616 22:54:10.752818 [ANA_INIT] DLL >>>>>>>>
617 22:54:10.755893 [ANA_INIT] flow end
618 22:54:10.759179 ============ LP4 DIFF to SE enter ============
619 22:54:10.762739 ============ LP4 DIFF to SE exit ============
620 22:54:10.766062 [ANA_INIT] <<<<<<<<<<<<<
621 22:54:10.769804 [Flow] Enable top DCM control >>>>>
622 22:54:10.772757 [Flow] Enable top DCM control <<<<<
623 22:54:10.775933 Enable DLL master slave shuffle
624 22:54:10.779322 ==============================================================
625 22:54:10.782753 Gating Mode config
626 22:54:10.789742 ==============================================================
627 22:54:10.789934 Config description:
628 22:54:10.799712 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:54:10.806369 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:54:10.809274 SELPH_MODE 0: By rank 1: By Phase
631 22:54:10.816607 ==============================================================
632 22:54:10.819622 GAT_TRACK_EN = 1
633 22:54:10.822592 RX_GATING_MODE = 2
634 22:54:10.826490 RX_GATING_TRACK_MODE = 2
635 22:54:10.829535 SELPH_MODE = 1
636 22:54:10.832712 PICG_EARLY_EN = 1
637 22:54:10.832867 VALID_LAT_VALUE = 1
638 22:54:10.839419 ==============================================================
639 22:54:10.842994 Enter into Gating configuration >>>>
640 22:54:10.846032 Exit from Gating configuration <<<<
641 22:54:10.849484 Enter into DVFS_PRE_config >>>>>
642 22:54:10.860054 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:54:10.863073 Exit from DVFS_PRE_config <<<<<
644 22:54:10.866870 Enter into PICG configuration >>>>
645 22:54:10.870015 Exit from PICG configuration <<<<
646 22:54:10.873189 [RX_INPUT] configuration >>>>>
647 22:54:10.876636 [RX_INPUT] configuration <<<<<
648 22:54:10.879572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:54:10.886508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:54:10.893200 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:54:10.899530 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:54:10.906578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:54:10.910217 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:54:10.913236 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:54:10.920163 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:54:10.923253 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:54:10.927166 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:54:10.930213 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:54:10.936485 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:54:10.940303 ===================================
661 22:54:10.940478 LPDDR4 DRAM CONFIGURATION
662 22:54:10.943570 ===================================
663 22:54:10.946950 EX_ROW_EN[0] = 0x0
664 22:54:10.950038 EX_ROW_EN[1] = 0x0
665 22:54:10.950193 LP4Y_EN = 0x0
666 22:54:10.953741 WORK_FSP = 0x0
667 22:54:10.953893 WL = 0x2
668 22:54:10.956540 RL = 0x2
669 22:54:10.956667 BL = 0x2
670 22:54:10.960224 RPST = 0x0
671 22:54:10.960362 RD_PRE = 0x0
672 22:54:10.963915 WR_PRE = 0x1
673 22:54:10.964144 WR_PST = 0x0
674 22:54:10.967198 DBI_WR = 0x0
675 22:54:10.967331 DBI_RD = 0x0
676 22:54:10.970077 OTF = 0x1
677 22:54:10.973845 ===================================
678 22:54:10.976948 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:54:10.979855 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:54:10.986810 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:54:10.990532 ===================================
682 22:54:10.990714 LPDDR4 DRAM CONFIGURATION
683 22:54:10.993579 ===================================
684 22:54:10.996942 EX_ROW_EN[0] = 0x10
685 22:54:10.997095 EX_ROW_EN[1] = 0x0
686 22:54:11.000154 LP4Y_EN = 0x0
687 22:54:11.000300 WORK_FSP = 0x0
688 22:54:11.003758 WL = 0x2
689 22:54:11.003906 RL = 0x2
690 22:54:11.006687 BL = 0x2
691 22:54:11.010706 RPST = 0x0
692 22:54:11.010875 RD_PRE = 0x0
693 22:54:11.013742 WR_PRE = 0x1
694 22:54:11.013877 WR_PST = 0x0
695 22:54:11.017007 DBI_WR = 0x0
696 22:54:11.017143 DBI_RD = 0x0
697 22:54:11.020059 OTF = 0x1
698 22:54:11.023989 ===================================
699 22:54:11.026925 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:54:11.032200 nWR fixed to 40
701 22:54:11.035765 [ModeRegInit_LP4] CH0 RK0
702 22:54:11.035929 [ModeRegInit_LP4] CH0 RK1
703 22:54:11.039047 [ModeRegInit_LP4] CH1 RK0
704 22:54:11.042738 [ModeRegInit_LP4] CH1 RK1
705 22:54:11.042903 match AC timing 13
706 22:54:11.049626 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:54:11.052337 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:54:11.056077 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:54:11.062256 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:54:11.065532 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:54:11.065701 [EMI DOE] emi_dcm 0
712 22:54:11.072645 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:54:11.072844 ==
714 22:54:11.075847 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:54:11.079502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:54:11.079643 ==
717 22:54:11.086465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:54:11.089490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:54:11.100281 [CA 0] Center 36 (6~67) winsize 62
720 22:54:11.103382 [CA 1] Center 36 (6~67) winsize 62
721 22:54:11.106287 [CA 2] Center 34 (4~65) winsize 62
722 22:54:11.109942 [CA 3] Center 33 (3~64) winsize 62
723 22:54:11.113005 [CA 4] Center 33 (3~64) winsize 62
724 22:54:11.116766 [CA 5] Center 32 (2~62) winsize 61
725 22:54:11.116901
726 22:54:11.120126 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 22:54:11.120238
728 22:54:11.123204 [CATrainingPosCal] consider 1 rank data
729 22:54:11.126146 u2DelayCellTimex100 = 270/100 ps
730 22:54:11.129596 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 22:54:11.132859 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 22:54:11.139697 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 22:54:11.142973 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 22:54:11.146608 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 22:54:11.150200 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 22:54:11.150346
737 22:54:11.153234 CA PerBit enable=1, Macro0, CA PI delay=32
738 22:54:11.153338
739 22:54:11.156390 [CBTSetCACLKResult] CA Dly = 32
740 22:54:11.156499 CS Dly: 5 (0~36)
741 22:54:11.156568 ==
742 22:54:11.159868 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:54:11.166864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:54:11.167021 ==
745 22:54:11.170093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:54:11.176250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:54:11.185795 [CA 0] Center 36 (6~67) winsize 62
748 22:54:11.189632 [CA 1] Center 36 (6~67) winsize 62
749 22:54:11.192679 [CA 2] Center 34 (3~65) winsize 63
750 22:54:11.195711 [CA 3] Center 33 (3~64) winsize 62
751 22:54:11.199557 [CA 4] Center 32 (2~63) winsize 62
752 22:54:11.202473 [CA 5] Center 32 (2~63) winsize 62
753 22:54:11.202602
754 22:54:11.205796 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 22:54:11.205916
756 22:54:11.209676 [CATrainingPosCal] consider 2 rank data
757 22:54:11.212737 u2DelayCellTimex100 = 270/100 ps
758 22:54:11.216181 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 22:54:11.219284 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 22:54:11.226032 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 22:54:11.229242 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 22:54:11.232674 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 22:54:11.236487 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 22:54:11.236626
765 22:54:11.239280 CA PerBit enable=1, Macro0, CA PI delay=32
766 22:54:11.239424
767 22:54:11.242515 [CBTSetCACLKResult] CA Dly = 32
768 22:54:11.242627 CS Dly: 5 (0~37)
769 22:54:11.242701
770 22:54:11.246497 ----->DramcWriteLeveling(PI) begin...
771 22:54:11.246619 ==
772 22:54:11.250306 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:54:11.253606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:54:11.253739 ==
775 22:54:11.257434 Write leveling (Byte 0): 34 => 34
776 22:54:11.262048 Write leveling (Byte 1): 31 => 31
777 22:54:11.265230 DramcWriteLeveling(PI) end<-----
778 22:54:11.265373
779 22:54:11.265446 ==
780 22:54:11.268793 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:54:11.271855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:54:11.271999 ==
783 22:54:11.275582 [Gating] SW mode calibration
784 22:54:11.282634 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:54:11.285812 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:54:11.292673 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:54:11.295739 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 22:54:11.299629 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 22:54:11.305851 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 22:54:11.309063 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:54:11.312623 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:54:11.319345 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:54:11.322956 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:54:11.325776 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:54:11.332476 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:54:11.336096 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:54:11.339308 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:54:11.346103 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:54:11.349352 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:54:11.352830 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:54:11.356059 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:54:11.362803 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:54:11.366292 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 22:54:11.369528 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 22:54:11.376050 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:54:11.379652 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:54:11.382748 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:54:11.389279 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:54:11.392743 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:54:11.396112 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:54:11.402703 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:54:11.405946 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
813 22:54:11.409559 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
814 22:54:11.416105 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:54:11.419537 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:54:11.422688 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:54:11.429421 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:54:11.432915 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:54:11.436396 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
820 22:54:11.439831 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
821 22:54:11.446060 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 22:54:11.449988 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:54:11.452865 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:54:11.459340 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:54:11.463391 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:54:11.466477 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:54:11.472559 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
828 22:54:11.476142 0 11 8 | B1->B0 | 2b2b 4040 | 0 0 | (0 0) (0 0)
829 22:54:11.479916 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
830 22:54:11.486514 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:54:11.489562 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:54:11.492832 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:54:11.499286 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:54:11.502897 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:54:11.506416 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 22:54:11.512748 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 22:54:11.516267 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:54:11.519513 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:54:11.526448 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:54:11.529781 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:54:11.533259 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:54:11.536350 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:54:11.542799 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:54:11.546484 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:54:11.549997 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:54:11.556676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:54:11.559699 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:54:11.563072 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:54:11.569905 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:54:11.573170 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:54:11.576326 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 22:54:11.583041 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 22:54:11.583188 Total UI for P1: 0, mck2ui 16
854 22:54:11.590124 best dqsien dly found for B0: ( 0, 14, 4)
855 22:54:11.593018 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 22:54:11.596972 Total UI for P1: 0, mck2ui 16
857 22:54:11.600655 best dqsien dly found for B1: ( 0, 14, 10)
858 22:54:11.604355 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 22:54:11.607444 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 22:54:11.607609
861 22:54:11.611004 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 22:54:11.614113 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 22:54:11.617407 [Gating] SW calibration Done
864 22:54:11.617525 ==
865 22:54:11.620947 Dram Type= 6, Freq= 0, CH_0, rank 0
866 22:54:11.624494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 22:54:11.624617 ==
868 22:54:11.627453 RX Vref Scan: 0
869 22:54:11.627555
870 22:54:11.627624 RX Vref 0 -> 0, step: 1
871 22:54:11.627687
872 22:54:11.630684 RX Delay -130 -> 252, step: 16
873 22:54:11.634263 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 22:54:11.641107 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 22:54:11.644272 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 22:54:11.647444 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 22:54:11.651067 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 22:54:11.654319 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 22:54:11.657458 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
880 22:54:11.664156 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
881 22:54:11.667282 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 22:54:11.671289 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
883 22:54:11.674382 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 22:54:11.677668 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 22:54:11.684269 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
886 22:54:11.687579 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
887 22:54:11.690715 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 22:54:11.694419 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
889 22:54:11.694539 ==
890 22:54:11.697409 Dram Type= 6, Freq= 0, CH_0, rank 0
891 22:54:11.704666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 22:54:11.704818 ==
893 22:54:11.704892 DQS Delay:
894 22:54:11.704955 DQS0 = 0, DQS1 = 0
895 22:54:11.707674 DQM Delay:
896 22:54:11.707765 DQM0 = 90, DQM1 = 82
897 22:54:11.711321 DQ Delay:
898 22:54:11.714202 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 22:54:11.717580 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
900 22:54:11.721015 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
901 22:54:11.724492 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
902 22:54:11.724617
903 22:54:11.724688
904 22:54:11.724749 ==
905 22:54:11.727843 Dram Type= 6, Freq= 0, CH_0, rank 0
906 22:54:11.731145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 22:54:11.731299 ==
908 22:54:11.731421
909 22:54:11.731517
910 22:54:11.734555 TX Vref Scan disable
911 22:54:11.734674 == TX Byte 0 ==
912 22:54:11.740920 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
913 22:54:11.744479 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
914 22:54:11.744603 == TX Byte 1 ==
915 22:54:11.751002 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 22:54:11.754656 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 22:54:11.754796 ==
918 22:54:11.758127 Dram Type= 6, Freq= 0, CH_0, rank 0
919 22:54:11.761628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 22:54:11.761724 ==
921 22:54:11.775047 TX Vref=22, minBit 7, minWin=27, winSum=449
922 22:54:11.778810 TX Vref=24, minBit 13, minWin=27, winSum=452
923 22:54:11.782012 TX Vref=26, minBit 0, minWin=28, winSum=455
924 22:54:11.785328 TX Vref=28, minBit 5, minWin=28, winSum=459
925 22:54:11.788350 TX Vref=30, minBit 5, minWin=28, winSum=457
926 22:54:11.791631 TX Vref=32, minBit 2, minWin=28, winSum=454
927 22:54:11.798629 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 28
928 22:54:11.798765
929 22:54:11.802292 Final TX Range 1 Vref 28
930 22:54:11.802390
931 22:54:11.802458 ==
932 22:54:11.805387 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:54:11.808983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:54:11.809078 ==
935 22:54:11.809146
936 22:54:11.812210
937 22:54:11.812298 TX Vref Scan disable
938 22:54:11.815130 == TX Byte 0 ==
939 22:54:11.819031 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 22:54:11.822068 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 22:54:11.825719 == TX Byte 1 ==
942 22:54:11.828606 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 22:54:11.831905 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 22:54:11.832044
945 22:54:11.835536 [DATLAT]
946 22:54:11.835627 Freq=800, CH0 RK0
947 22:54:11.835696
948 22:54:11.838625 DATLAT Default: 0xa
949 22:54:11.838711 0, 0xFFFF, sum = 0
950 22:54:11.842175 1, 0xFFFF, sum = 0
951 22:54:11.842272 2, 0xFFFF, sum = 0
952 22:54:11.845561 3, 0xFFFF, sum = 0
953 22:54:11.845650 4, 0xFFFF, sum = 0
954 22:54:11.848898 5, 0xFFFF, sum = 0
955 22:54:11.849011 6, 0xFFFF, sum = 0
956 22:54:11.852425 7, 0xFFFF, sum = 0
957 22:54:11.852522 8, 0xFFFF, sum = 0
958 22:54:11.855816 9, 0x0, sum = 1
959 22:54:11.855936 10, 0x0, sum = 2
960 22:54:11.858827 11, 0x0, sum = 3
961 22:54:11.858918 12, 0x0, sum = 4
962 22:54:11.861996 best_step = 10
963 22:54:11.862089
964 22:54:11.862192 ==
965 22:54:11.866112 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:54:11.869112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:54:11.869213 ==
968 22:54:11.871910 RX Vref Scan: 1
969 22:54:11.872030
970 22:54:11.872132 Set Vref Range= 32 -> 127
971 22:54:11.872229
972 22:54:11.875630 RX Vref 32 -> 127, step: 1
973 22:54:11.875783
974 22:54:11.878910 RX Delay -79 -> 252, step: 8
975 22:54:11.879030
976 22:54:11.881946 Set Vref, RX VrefLevel [Byte0]: 32
977 22:54:11.885787 [Byte1]: 32
978 22:54:11.885892
979 22:54:11.888523 Set Vref, RX VrefLevel [Byte0]: 33
980 22:54:11.892549 [Byte1]: 33
981 22:54:11.895299
982 22:54:11.895402 Set Vref, RX VrefLevel [Byte0]: 34
983 22:54:11.902418 [Byte1]: 34
984 22:54:11.902556
985 22:54:11.905480 Set Vref, RX VrefLevel [Byte0]: 35
986 22:54:11.908455 [Byte1]: 35
987 22:54:11.908552
988 22:54:11.912307 Set Vref, RX VrefLevel [Byte0]: 36
989 22:54:11.916126 [Byte1]: 36
990 22:54:11.916299
991 22:54:11.920509 Set Vref, RX VrefLevel [Byte0]: 37
992 22:54:11.923441 [Byte1]: 37
993 22:54:11.923586
994 22:54:11.927075 Set Vref, RX VrefLevel [Byte0]: 38
995 22:54:11.930845 [Byte1]: 38
996 22:54:11.930947
997 22:54:11.934791 Set Vref, RX VrefLevel [Byte0]: 39
998 22:54:11.938410 [Byte1]: 39
999 22:54:11.938512
1000 22:54:11.942135 Set Vref, RX VrefLevel [Byte0]: 40
1001 22:54:11.945969 [Byte1]: 40
1002 22:54:11.946076
1003 22:54:11.949736 Set Vref, RX VrefLevel [Byte0]: 41
1004 22:54:11.952685 [Byte1]: 41
1005 22:54:11.952788
1006 22:54:11.956172 Set Vref, RX VrefLevel [Byte0]: 42
1007 22:54:11.959461 [Byte1]: 42
1008 22:54:11.963485
1009 22:54:11.963614 Set Vref, RX VrefLevel [Byte0]: 43
1010 22:54:11.966509 [Byte1]: 43
1011 22:54:11.970805
1012 22:54:11.970920 Set Vref, RX VrefLevel [Byte0]: 44
1013 22:54:11.974199 [Byte1]: 44
1014 22:54:11.978200
1015 22:54:11.978313 Set Vref, RX VrefLevel [Byte0]: 45
1016 22:54:11.981494 [Byte1]: 45
1017 22:54:11.985860
1018 22:54:11.985990 Set Vref, RX VrefLevel [Byte0]: 46
1019 22:54:11.989425 [Byte1]: 46
1020 22:54:11.993650
1021 22:54:11.993764 Set Vref, RX VrefLevel [Byte0]: 47
1022 22:54:11.996788 [Byte1]: 47
1023 22:54:12.001222
1024 22:54:12.001341 Set Vref, RX VrefLevel [Byte0]: 48
1025 22:54:12.004274 [Byte1]: 48
1026 22:54:12.008830
1027 22:54:12.008956 Set Vref, RX VrefLevel [Byte0]: 49
1028 22:54:12.011696 [Byte1]: 49
1029 22:54:12.016203
1030 22:54:12.016328 Set Vref, RX VrefLevel [Byte0]: 50
1031 22:54:12.019880 [Byte1]: 50
1032 22:54:12.023675
1033 22:54:12.023781 Set Vref, RX VrefLevel [Byte0]: 51
1034 22:54:12.027464 [Byte1]: 51
1035 22:54:12.031462
1036 22:54:12.031567 Set Vref, RX VrefLevel [Byte0]: 52
1037 22:54:12.034699 [Byte1]: 52
1038 22:54:12.038764
1039 22:54:12.038872 Set Vref, RX VrefLevel [Byte0]: 53
1040 22:54:12.042363 [Byte1]: 53
1041 22:54:12.046403
1042 22:54:12.046507 Set Vref, RX VrefLevel [Byte0]: 54
1043 22:54:12.049938 [Byte1]: 54
1044 22:54:12.054297
1045 22:54:12.054400 Set Vref, RX VrefLevel [Byte0]: 55
1046 22:54:12.057363 [Byte1]: 55
1047 22:54:12.061355
1048 22:54:12.061455 Set Vref, RX VrefLevel [Byte0]: 56
1049 22:54:12.064652 [Byte1]: 56
1050 22:54:12.069137
1051 22:54:12.069254 Set Vref, RX VrefLevel [Byte0]: 57
1052 22:54:12.072586 [Byte1]: 57
1053 22:54:12.076480
1054 22:54:12.076599 Set Vref, RX VrefLevel [Byte0]: 58
1055 22:54:12.079639 [Byte1]: 58
1056 22:54:12.084186
1057 22:54:12.084305 Set Vref, RX VrefLevel [Byte0]: 59
1058 22:54:12.087449 [Byte1]: 59
1059 22:54:12.091740
1060 22:54:12.091857 Set Vref, RX VrefLevel [Byte0]: 60
1061 22:54:12.095337 [Byte1]: 60
1062 22:54:12.099598
1063 22:54:12.099727 Set Vref, RX VrefLevel [Byte0]: 61
1064 22:54:12.102729 [Byte1]: 61
1065 22:54:12.106651
1066 22:54:12.106757 Set Vref, RX VrefLevel [Byte0]: 62
1067 22:54:12.110351 [Byte1]: 62
1068 22:54:12.114774
1069 22:54:12.114882 Set Vref, RX VrefLevel [Byte0]: 63
1070 22:54:12.117642 [Byte1]: 63
1071 22:54:12.121963
1072 22:54:12.122072 Set Vref, RX VrefLevel [Byte0]: 64
1073 22:54:12.125114 [Byte1]: 64
1074 22:54:12.129538
1075 22:54:12.129642 Set Vref, RX VrefLevel [Byte0]: 65
1076 22:54:12.133071 [Byte1]: 65
1077 22:54:12.137444
1078 22:54:12.137547 Set Vref, RX VrefLevel [Byte0]: 66
1079 22:54:12.140092 [Byte1]: 66
1080 22:54:12.144295
1081 22:54:12.144394 Set Vref, RX VrefLevel [Byte0]: 67
1082 22:54:12.148149 [Byte1]: 67
1083 22:54:12.152329
1084 22:54:12.152437 Set Vref, RX VrefLevel [Byte0]: 68
1085 22:54:12.155418 [Byte1]: 68
1086 22:54:12.159483
1087 22:54:12.159580 Set Vref, RX VrefLevel [Byte0]: 69
1088 22:54:12.163208 [Byte1]: 69
1089 22:54:12.167081
1090 22:54:12.167189 Set Vref, RX VrefLevel [Byte0]: 70
1091 22:54:12.170550 [Byte1]: 70
1092 22:54:12.174839
1093 22:54:12.174973 Set Vref, RX VrefLevel [Byte0]: 71
1094 22:54:12.177967 [Byte1]: 71
1095 22:54:12.182149
1096 22:54:12.182287 Set Vref, RX VrefLevel [Byte0]: 72
1097 22:54:12.185888 [Byte1]: 72
1098 22:54:12.189860
1099 22:54:12.189993 Set Vref, RX VrefLevel [Byte0]: 73
1100 22:54:12.192868 [Byte1]: 73
1101 22:54:12.197266
1102 22:54:12.197389 Set Vref, RX VrefLevel [Byte0]: 74
1103 22:54:12.200469 [Byte1]: 74
1104 22:54:12.205055
1105 22:54:12.205183 Set Vref, RX VrefLevel [Byte0]: 75
1106 22:54:12.208272 [Byte1]: 75
1107 22:54:12.212539
1108 22:54:12.212693 Final RX Vref Byte 0 = 54 to rank0
1109 22:54:12.215849 Final RX Vref Byte 1 = 56 to rank0
1110 22:54:12.219210 Final RX Vref Byte 0 = 54 to rank1
1111 22:54:12.222211 Final RX Vref Byte 1 = 56 to rank1==
1112 22:54:12.226260 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 22:54:12.232577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 22:54:12.232755 ==
1115 22:54:12.232859 DQS Delay:
1116 22:54:12.232948 DQS0 = 0, DQS1 = 0
1117 22:54:12.236382 DQM Delay:
1118 22:54:12.236508 DQM0 = 91, DQM1 = 85
1119 22:54:12.239352 DQ Delay:
1120 22:54:12.243049 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1121 22:54:12.243199 DQ4 =92, DQ5 =80, DQ6 =96, DQ7 =100
1122 22:54:12.245962 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1123 22:54:12.249267 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1124 22:54:12.252801
1125 22:54:12.252957
1126 22:54:12.259519 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1127 22:54:12.262544 CH0 RK0: MR19=606, MR18=4B42
1128 22:54:12.269698 CH0_RK0: MR19=0x606, MR18=0x4B42, DQSOSC=391, MR23=63, INC=96, DEC=64
1129 22:54:12.269886
1130 22:54:12.272476 ----->DramcWriteLeveling(PI) begin...
1131 22:54:12.272632 ==
1132 22:54:12.276274 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 22:54:12.279517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 22:54:12.279655 ==
1135 22:54:12.282804 Write leveling (Byte 0): 32 => 32
1136 22:54:12.285983 Write leveling (Byte 1): 32 => 32
1137 22:54:12.289580 DramcWriteLeveling(PI) end<-----
1138 22:54:12.289734
1139 22:54:12.289828 ==
1140 22:54:12.293176 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 22:54:12.297715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 22:54:12.297864 ==
1143 22:54:12.299573 [Gating] SW mode calibration
1144 22:54:12.306641 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 22:54:12.312938 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 22:54:12.316074 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 22:54:12.319475 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1148 22:54:12.363463 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1149 22:54:12.363898 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 22:54:12.364076 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 22:54:12.364196 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 22:54:12.364292 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 22:54:12.364401 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 22:54:12.364749 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 22:54:12.364863 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:54:12.365116 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:54:12.365183 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:54:12.377827 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:54:12.378607 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:54:12.381147 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:54:12.381241 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:54:12.384893 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:54:12.391258 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:54:12.394872 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1165 22:54:12.398094 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1166 22:54:12.405030 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:54:12.407779 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:54:12.411794 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:54:12.418049 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:54:12.421528 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:54:12.424770 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:54:12.431139 0 9 8 | B1->B0 | 2d2d 2b2b | 1 0 | (1 1) (1 1)
1173 22:54:12.434975 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 22:54:12.438336 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 22:54:12.444803 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 22:54:12.448307 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 22:54:12.451551 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 22:54:12.458579 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 22:54:12.461562 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (0 0)
1180 22:54:12.464652 0 10 8 | B1->B0 | 2828 2727 | 0 0 | (1 0) (0 0)
1181 22:54:12.468348 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:54:12.474884 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 22:54:12.478061 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 22:54:12.481651 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:54:12.488121 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:54:12.492173 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:54:12.495892 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1188 22:54:12.499478 0 11 8 | B1->B0 | 3c3c 3939 | 0 0 | (0 0) (1 1)
1189 22:54:12.503701 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 22:54:12.510324 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 22:54:12.513483 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 22:54:12.517283 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 22:54:12.524427 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 22:54:12.527424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 22:54:12.530999 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:54:12.534311 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1197 22:54:12.540588 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1198 22:54:12.544447 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 22:54:12.547863 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 22:54:12.554099 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 22:54:12.557319 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 22:54:12.561091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 22:54:12.567336 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:54:12.571244 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:54:12.574273 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:54:12.580646 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:54:12.584270 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:54:12.587815 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:54:12.594039 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:54:12.597734 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:54:12.600897 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:54:12.604131 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1213 22:54:12.610892 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 22:54:12.614035 Total UI for P1: 0, mck2ui 16
1215 22:54:12.617379 best dqsien dly found for B0: ( 0, 14, 10)
1216 22:54:12.621006 Total UI for P1: 0, mck2ui 16
1217 22:54:12.624637 best dqsien dly found for B1: ( 0, 14, 8)
1218 22:54:12.627837 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1219 22:54:12.630747 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1220 22:54:12.630911
1221 22:54:12.634213 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1222 22:54:12.637324 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1223 22:54:12.640803 [Gating] SW calibration Done
1224 22:54:12.640948 ==
1225 22:54:12.644246 Dram Type= 6, Freq= 0, CH_0, rank 1
1226 22:54:12.647540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1227 22:54:12.647678 ==
1228 22:54:12.650908 RX Vref Scan: 0
1229 22:54:12.651061
1230 22:54:12.651161 RX Vref 0 -> 0, step: 1
1231 22:54:12.654031
1232 22:54:12.654144 RX Delay -130 -> 252, step: 16
1233 22:54:12.660963 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1234 22:54:12.663782 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1235 22:54:12.667072 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1236 22:54:12.670996 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1237 22:54:12.674115 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1238 22:54:12.680687 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1239 22:54:12.684051 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1240 22:54:12.687727 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1241 22:54:12.690753 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1242 22:54:12.694405 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1243 22:54:12.700803 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1244 22:54:12.704402 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1245 22:54:12.707512 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1246 22:54:12.710732 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1247 22:54:12.714502 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1248 22:54:12.720674 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1249 22:54:12.720852 ==
1250 22:54:12.724258 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 22:54:12.727802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 22:54:12.727995 ==
1253 22:54:12.728115 DQS Delay:
1254 22:54:12.731049 DQS0 = 0, DQS1 = 0
1255 22:54:12.731171 DQM Delay:
1256 22:54:12.734168 DQM0 = 93, DQM1 = 83
1257 22:54:12.734300 DQ Delay:
1258 22:54:12.737369 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1259 22:54:12.740875 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1260 22:54:12.744072 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1261 22:54:12.747484 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1262 22:54:12.747641
1263 22:54:12.747738
1264 22:54:12.747827 ==
1265 22:54:12.751142 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 22:54:12.754336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 22:54:12.754491 ==
1268 22:54:12.754590
1269 22:54:12.757739
1270 22:54:12.757877 TX Vref Scan disable
1271 22:54:12.760825 == TX Byte 0 ==
1272 22:54:12.764247 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1273 22:54:12.767279 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1274 22:54:12.770965 == TX Byte 1 ==
1275 22:54:12.774039 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1276 22:54:12.777521 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1277 22:54:12.777652 ==
1278 22:54:12.780817 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 22:54:12.787211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 22:54:12.787356 ==
1281 22:54:12.799367 TX Vref=22, minBit 8, minWin=27, winSum=447
1282 22:54:12.802257 TX Vref=24, minBit 15, minWin=27, winSum=454
1283 22:54:12.805809 TX Vref=26, minBit 5, minWin=28, winSum=457
1284 22:54:12.809228 TX Vref=28, minBit 5, minWin=28, winSum=460
1285 22:54:12.812438 TX Vref=30, minBit 4, minWin=28, winSum=458
1286 22:54:12.815737 TX Vref=32, minBit 2, minWin=28, winSum=453
1287 22:54:12.822486 [TxChooseVref] Worse bit 5, Min win 28, Win sum 460, Final Vref 28
1288 22:54:12.822633
1289 22:54:12.826044 Final TX Range 1 Vref 28
1290 22:54:12.826158
1291 22:54:12.826250 ==
1292 22:54:12.829006 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 22:54:12.832329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 22:54:12.832480 ==
1295 22:54:12.832579
1296 22:54:12.835588
1297 22:54:12.835697 TX Vref Scan disable
1298 22:54:12.838951 == TX Byte 0 ==
1299 22:54:12.842510 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1300 22:54:12.846137 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1301 22:54:12.849277 == TX Byte 1 ==
1302 22:54:12.852450 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1303 22:54:12.856046 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1304 22:54:12.856169
1305 22:54:12.859345 [DATLAT]
1306 22:54:12.859452 Freq=800, CH0 RK1
1307 22:54:12.859545
1308 22:54:12.862567 DATLAT Default: 0xa
1309 22:54:12.862678 0, 0xFFFF, sum = 0
1310 22:54:12.866032 1, 0xFFFF, sum = 0
1311 22:54:12.866165 2, 0xFFFF, sum = 0
1312 22:54:12.869002 3, 0xFFFF, sum = 0
1313 22:54:12.869137 4, 0xFFFF, sum = 0
1314 22:54:12.872575 5, 0xFFFF, sum = 0
1315 22:54:12.872688 6, 0xFFFF, sum = 0
1316 22:54:12.876324 7, 0xFFFF, sum = 0
1317 22:54:12.876432 8, 0xFFFF, sum = 0
1318 22:54:12.879436 9, 0x0, sum = 1
1319 22:54:12.879542 10, 0x0, sum = 2
1320 22:54:12.882679 11, 0x0, sum = 3
1321 22:54:12.882789 12, 0x0, sum = 4
1322 22:54:12.886431 best_step = 10
1323 22:54:12.886541
1324 22:54:12.886634 ==
1325 22:54:12.889436 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 22:54:12.892822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 22:54:12.892936 ==
1328 22:54:12.896256 RX Vref Scan: 0
1329 22:54:12.896364
1330 22:54:12.896454 RX Vref 0 -> 0, step: 1
1331 22:54:12.896543
1332 22:54:12.899450 RX Delay -95 -> 252, step: 8
1333 22:54:12.906204 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1334 22:54:12.909170 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1335 22:54:12.912901 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1336 22:54:12.916166 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1337 22:54:12.919218 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1338 22:54:12.922739 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1339 22:54:12.929928 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1340 22:54:12.932745 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1341 22:54:12.936251 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1342 22:54:12.939715 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1343 22:54:12.943229 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1344 22:54:12.949574 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1345 22:54:12.952785 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1346 22:54:12.956476 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1347 22:54:12.959664 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1348 22:54:12.962786 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1349 22:54:12.966790 ==
1350 22:54:12.969721 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 22:54:12.973059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 22:54:12.973156 ==
1353 22:54:12.973221 DQS Delay:
1354 22:54:12.976298 DQS0 = 0, DQS1 = 0
1355 22:54:12.976384 DQM Delay:
1356 22:54:12.979616 DQM0 = 92, DQM1 = 84
1357 22:54:12.979706 DQ Delay:
1358 22:54:12.982980 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1359 22:54:12.986375 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1360 22:54:12.989477 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1361 22:54:12.993113 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1362 22:54:12.993213
1363 22:54:12.993280
1364 22:54:12.999920 [DQSOSCAuto] RK1, (LSB)MR18= 0x4010, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1365 22:54:13.003094 CH0 RK1: MR19=606, MR18=4010
1366 22:54:13.009613 CH0_RK1: MR19=0x606, MR18=0x4010, DQSOSC=393, MR23=63, INC=95, DEC=63
1367 22:54:13.013141 [RxdqsGatingPostProcess] freq 800
1368 22:54:13.016391 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1369 22:54:13.019550 Pre-setting of DQS Precalculation
1370 22:54:13.026785 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1371 22:54:13.026952 ==
1372 22:54:13.029864 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 22:54:13.033093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 22:54:13.033246 ==
1375 22:54:13.040304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1376 22:54:13.046854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1377 22:54:13.054852 [CA 0] Center 36 (6~67) winsize 62
1378 22:54:13.058461 [CA 1] Center 36 (6~67) winsize 62
1379 22:54:13.061084 [CA 2] Center 35 (5~66) winsize 62
1380 22:54:13.064687 [CA 3] Center 34 (4~65) winsize 62
1381 22:54:13.067523 [CA 4] Center 34 (4~65) winsize 62
1382 22:54:13.070729 [CA 5] Center 34 (4~64) winsize 61
1383 22:54:13.070859
1384 22:54:13.074347 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1385 22:54:13.074465
1386 22:54:13.077450 [CATrainingPosCal] consider 1 rank data
1387 22:54:13.081280 u2DelayCellTimex100 = 270/100 ps
1388 22:54:13.084372 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1389 22:54:13.087315 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1390 22:54:13.094401 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1391 22:54:13.097530 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1392 22:54:13.101035 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1393 22:54:13.104227 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1394 22:54:13.104355
1395 22:54:13.107949 CA PerBit enable=1, Macro0, CA PI delay=34
1396 22:54:13.108090
1397 22:54:13.111070 [CBTSetCACLKResult] CA Dly = 34
1398 22:54:13.111179 CS Dly: 6 (0~37)
1399 22:54:13.111271 ==
1400 22:54:13.114189 Dram Type= 6, Freq= 0, CH_1, rank 1
1401 22:54:13.120774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 22:54:13.120923 ==
1403 22:54:13.124341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1404 22:54:13.130510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1405 22:54:13.140360 [CA 0] Center 36 (6~67) winsize 62
1406 22:54:13.144130 [CA 1] Center 37 (6~68) winsize 63
1407 22:54:13.147194 [CA 2] Center 35 (5~66) winsize 62
1408 22:54:13.150423 [CA 3] Center 34 (4~65) winsize 62
1409 22:54:13.154176 [CA 4] Center 35 (5~65) winsize 61
1410 22:54:13.158042 [CA 5] Center 34 (4~65) winsize 62
1411 22:54:13.158170
1412 22:54:13.161624 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1413 22:54:13.161746
1414 22:54:13.165173 [CATrainingPosCal] consider 2 rank data
1415 22:54:13.168460 u2DelayCellTimex100 = 270/100 ps
1416 22:54:13.172307 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1417 22:54:13.175940 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1418 22:54:13.179885 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1419 22:54:13.183767 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 22:54:13.186927 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1421 22:54:13.190893 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1422 22:54:13.191033
1423 22:54:13.194083 CA PerBit enable=1, Macro0, CA PI delay=34
1424 22:54:13.194221
1425 22:54:13.197430 [CBTSetCACLKResult] CA Dly = 34
1426 22:54:13.197546 CS Dly: 7 (0~39)
1427 22:54:13.197640
1428 22:54:13.200851 ----->DramcWriteLeveling(PI) begin...
1429 22:54:13.200963 ==
1430 22:54:13.204351 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 22:54:13.210772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 22:54:13.210929 ==
1433 22:54:13.214262 Write leveling (Byte 0): 26 => 26
1434 22:54:13.214383 Write leveling (Byte 1): 29 => 29
1435 22:54:13.217856 DramcWriteLeveling(PI) end<-----
1436 22:54:13.217970
1437 22:54:13.218061 ==
1438 22:54:13.220938 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 22:54:13.227518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 22:54:13.227651 ==
1441 22:54:13.231220 [Gating] SW mode calibration
1442 22:54:13.237836 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1443 22:54:13.241399 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1444 22:54:13.247737 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1445 22:54:13.251024 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1446 22:54:13.254231 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 22:54:13.257928 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 22:54:13.264277 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 22:54:13.267402 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 22:54:13.271331 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 22:54:13.278186 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 22:54:13.281254 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:54:13.284374 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:54:13.291383 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:54:13.294165 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:54:13.297520 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:54:13.304580 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:54:13.307968 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:54:13.311112 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:54:13.317634 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1461 22:54:13.320761 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1462 22:54:13.324364 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:54:13.330769 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:54:13.334108 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:54:13.337640 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:54:13.344204 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:54:13.347650 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:54:13.351100 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:54:13.354423 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1470 22:54:13.361676 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1471 22:54:13.364364 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 22:54:13.367493 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 22:54:13.374381 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 22:54:13.377849 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 22:54:13.380842 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 22:54:13.387918 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1477 22:54:13.391034 0 10 4 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (1 1)
1478 22:54:13.394219 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:54:13.401003 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 22:54:13.404664 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 22:54:13.407708 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:54:13.414560 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:54:13.417659 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:54:13.421467 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:54:13.428091 0 11 4 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
1486 22:54:13.431137 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1487 22:54:13.434936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 22:54:13.438389 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 22:54:13.444945 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 22:54:13.448452 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 22:54:13.451797 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 22:54:13.458199 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 22:54:13.461335 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1494 22:54:13.464728 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 22:54:13.471313 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 22:54:13.474833 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 22:54:13.478025 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 22:54:13.484527 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 22:54:13.487906 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 22:54:13.491620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:54:13.498114 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:54:13.501778 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:54:13.504967 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:54:13.508049 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:54:13.514578 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:54:13.518444 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:54:13.521693 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:54:13.528109 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1509 22:54:13.531510 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1510 22:54:13.535182 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 22:54:13.538058 Total UI for P1: 0, mck2ui 16
1512 22:54:13.542068 best dqsien dly found for B0: ( 0, 14, 2)
1513 22:54:13.545318 Total UI for P1: 0, mck2ui 16
1514 22:54:13.548222 best dqsien dly found for B1: ( 0, 14, 4)
1515 22:54:13.551780 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1516 22:54:13.555025 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1517 22:54:13.555132
1518 22:54:13.558505 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1519 22:54:13.565179 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1520 22:54:13.565302 [Gating] SW calibration Done
1521 22:54:13.565368 ==
1522 22:54:13.568275 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 22:54:13.575094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 22:54:13.575235 ==
1525 22:54:13.575304 RX Vref Scan: 0
1526 22:54:13.575365
1527 22:54:13.578471 RX Vref 0 -> 0, step: 1
1528 22:54:13.578560
1529 22:54:13.581885 RX Delay -130 -> 252, step: 16
1530 22:54:13.585386 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1531 22:54:13.588137 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1532 22:54:13.591828 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1533 22:54:13.598280 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1534 22:54:13.601883 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1535 22:54:13.604880 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1536 22:54:13.608271 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1537 22:54:13.611379 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1538 22:54:13.618198 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1539 22:54:13.621587 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1540 22:54:13.625283 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1541 22:54:13.628307 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1542 22:54:13.631591 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1543 22:54:13.638400 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1544 22:54:13.642030 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1545 22:54:13.644586 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1546 22:54:13.644684 ==
1547 22:54:13.648461 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 22:54:13.651330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1549 22:54:13.651429 ==
1550 22:54:13.655113 DQS Delay:
1551 22:54:13.655211 DQS0 = 0, DQS1 = 0
1552 22:54:13.658122 DQM Delay:
1553 22:54:13.658209 DQM0 = 95, DQM1 = 93
1554 22:54:13.658275 DQ Delay:
1555 22:54:13.661407 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1556 22:54:13.664532 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1557 22:54:13.667947 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1558 22:54:13.674675 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1559 22:54:13.674792
1560 22:54:13.674860
1561 22:54:13.674920 ==
1562 22:54:13.678175 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 22:54:13.681453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 22:54:13.681546 ==
1565 22:54:13.681612
1566 22:54:13.681673
1567 22:54:13.685100 TX Vref Scan disable
1568 22:54:13.685187 == TX Byte 0 ==
1569 22:54:13.691307 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1570 22:54:13.694974 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1571 22:54:13.695076 == TX Byte 1 ==
1572 22:54:13.701894 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1573 22:54:13.704997 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1574 22:54:13.705094 ==
1575 22:54:13.708601 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 22:54:13.711873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 22:54:13.711990 ==
1578 22:54:13.725017 TX Vref=22, minBit 0, minWin=26, winSum=429
1579 22:54:13.728530 TX Vref=24, minBit 3, minWin=26, winSum=435
1580 22:54:13.731840 TX Vref=26, minBit 3, minWin=26, winSum=439
1581 22:54:13.735593 TX Vref=28, minBit 7, minWin=26, winSum=443
1582 22:54:13.739281 TX Vref=30, minBit 3, minWin=26, winSum=442
1583 22:54:13.742807 TX Vref=32, minBit 3, minWin=26, winSum=445
1584 22:54:13.749676 [TxChooseVref] Worse bit 3, Min win 26, Win sum 445, Final Vref 32
1585 22:54:13.749799
1586 22:54:13.752861 Final TX Range 1 Vref 32
1587 22:54:13.752972
1588 22:54:13.753038 ==
1589 22:54:13.756089 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 22:54:13.759624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 22:54:13.759712 ==
1592 22:54:13.759804
1593 22:54:13.759866
1594 22:54:13.762726 TX Vref Scan disable
1595 22:54:13.766221 == TX Byte 0 ==
1596 22:54:13.769424 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1597 22:54:13.772683 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1598 22:54:13.776187 == TX Byte 1 ==
1599 22:54:13.779365 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1600 22:54:13.783075 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1601 22:54:13.783179
1602 22:54:13.783246 [DATLAT]
1603 22:54:13.786289 Freq=800, CH1 RK0
1604 22:54:13.786376
1605 22:54:13.789533 DATLAT Default: 0xa
1606 22:54:13.789618 0, 0xFFFF, sum = 0
1607 22:54:13.793584 1, 0xFFFF, sum = 0
1608 22:54:13.793673 2, 0xFFFF, sum = 0
1609 22:54:13.796062 3, 0xFFFF, sum = 0
1610 22:54:13.796147 4, 0xFFFF, sum = 0
1611 22:54:13.799389 5, 0xFFFF, sum = 0
1612 22:54:13.799473 6, 0xFFFF, sum = 0
1613 22:54:13.803065 7, 0xFFFF, sum = 0
1614 22:54:13.803169 8, 0xFFFF, sum = 0
1615 22:54:13.806224 9, 0x0, sum = 1
1616 22:54:13.806327 10, 0x0, sum = 2
1617 22:54:13.809728 11, 0x0, sum = 3
1618 22:54:13.809817 12, 0x0, sum = 4
1619 22:54:13.809884 best_step = 10
1620 22:54:13.812703
1621 22:54:13.812789 ==
1622 22:54:13.816398 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 22:54:13.819627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 22:54:13.819719 ==
1625 22:54:13.819785 RX Vref Scan: 1
1626 22:54:13.819845
1627 22:54:13.822689 Set Vref Range= 32 -> 127
1628 22:54:13.822773
1629 22:54:13.825954 RX Vref 32 -> 127, step: 1
1630 22:54:13.826040
1631 22:54:13.829543 RX Delay -63 -> 252, step: 8
1632 22:54:13.829630
1633 22:54:13.832804 Set Vref, RX VrefLevel [Byte0]: 32
1634 22:54:13.836422 [Byte1]: 32
1635 22:54:13.836510
1636 22:54:13.839849 Set Vref, RX VrefLevel [Byte0]: 33
1637 22:54:13.842929 [Byte1]: 33
1638 22:54:13.843020
1639 22:54:13.846408 Set Vref, RX VrefLevel [Byte0]: 34
1640 22:54:13.849804 [Byte1]: 34
1641 22:54:13.852945
1642 22:54:13.853048 Set Vref, RX VrefLevel [Byte0]: 35
1643 22:54:13.856393 [Byte1]: 35
1644 22:54:13.860761
1645 22:54:13.860859 Set Vref, RX VrefLevel [Byte0]: 36
1646 22:54:13.863771 [Byte1]: 36
1647 22:54:13.867723
1648 22:54:13.867820 Set Vref, RX VrefLevel [Byte0]: 37
1649 22:54:13.871300 [Byte1]: 37
1650 22:54:13.875716
1651 22:54:13.875814 Set Vref, RX VrefLevel [Byte0]: 38
1652 22:54:13.878855 [Byte1]: 38
1653 22:54:13.882795
1654 22:54:13.882897 Set Vref, RX VrefLevel [Byte0]: 39
1655 22:54:13.885955 [Byte1]: 39
1656 22:54:13.890258
1657 22:54:13.890354 Set Vref, RX VrefLevel [Byte0]: 40
1658 22:54:13.893489 [Byte1]: 40
1659 22:54:13.897820
1660 22:54:13.897919 Set Vref, RX VrefLevel [Byte0]: 41
1661 22:54:13.901115 [Byte1]: 41
1662 22:54:13.905492
1663 22:54:13.905591 Set Vref, RX VrefLevel [Byte0]: 42
1664 22:54:13.908512 [Byte1]: 42
1665 22:54:13.912680
1666 22:54:13.912776 Set Vref, RX VrefLevel [Byte0]: 43
1667 22:54:13.916156 [Byte1]: 43
1668 22:54:13.920296
1669 22:54:13.920387 Set Vref, RX VrefLevel [Byte0]: 44
1670 22:54:13.923599 [Byte1]: 44
1671 22:54:13.927907
1672 22:54:13.928044 Set Vref, RX VrefLevel [Byte0]: 45
1673 22:54:13.930971 [Byte1]: 45
1674 22:54:13.935634
1675 22:54:13.935727 Set Vref, RX VrefLevel [Byte0]: 46
1676 22:54:13.938683 [Byte1]: 46
1677 22:54:13.942703
1678 22:54:13.942819 Set Vref, RX VrefLevel [Byte0]: 47
1679 22:54:13.946335 [Byte1]: 47
1680 22:54:13.950635
1681 22:54:13.950728 Set Vref, RX VrefLevel [Byte0]: 48
1682 22:54:13.953679 [Byte1]: 48
1683 22:54:13.957933
1684 22:54:13.958029 Set Vref, RX VrefLevel [Byte0]: 49
1685 22:54:13.960975 [Byte1]: 49
1686 22:54:13.965298
1687 22:54:13.965410 Set Vref, RX VrefLevel [Byte0]: 50
1688 22:54:13.968434 [Byte1]: 50
1689 22:54:13.972905
1690 22:54:13.972995 Set Vref, RX VrefLevel [Byte0]: 51
1691 22:54:13.975887 [Byte1]: 51
1692 22:54:13.980148
1693 22:54:13.980246 Set Vref, RX VrefLevel [Byte0]: 52
1694 22:54:13.983394 [Byte1]: 52
1695 22:54:13.987869
1696 22:54:13.988019 Set Vref, RX VrefLevel [Byte0]: 53
1697 22:54:13.990920 [Byte1]: 53
1698 22:54:13.995412
1699 22:54:13.995522 Set Vref, RX VrefLevel [Byte0]: 54
1700 22:54:13.998598 [Byte1]: 54
1701 22:54:14.002451
1702 22:54:14.002557 Set Vref, RX VrefLevel [Byte0]: 55
1703 22:54:14.006026 [Byte1]: 55
1704 22:54:14.010100
1705 22:54:14.010212 Set Vref, RX VrefLevel [Byte0]: 56
1706 22:54:14.013683 [Byte1]: 56
1707 22:54:14.017587
1708 22:54:14.017701 Set Vref, RX VrefLevel [Byte0]: 57
1709 22:54:14.021058 [Byte1]: 57
1710 22:54:14.025020
1711 22:54:14.025126 Set Vref, RX VrefLevel [Byte0]: 58
1712 22:54:14.028330 [Byte1]: 58
1713 22:54:14.032613
1714 22:54:14.032726 Set Vref, RX VrefLevel [Byte0]: 59
1715 22:54:14.035898 [Byte1]: 59
1716 22:54:14.040365
1717 22:54:14.040478 Set Vref, RX VrefLevel [Byte0]: 60
1718 22:54:14.043430 [Byte1]: 60
1719 22:54:14.047871
1720 22:54:14.048033 Set Vref, RX VrefLevel [Byte0]: 61
1721 22:54:14.050921 [Byte1]: 61
1722 22:54:14.055394
1723 22:54:14.055502 Set Vref, RX VrefLevel [Byte0]: 62
1724 22:54:14.058258 [Byte1]: 62
1725 22:54:14.063136
1726 22:54:14.063240 Set Vref, RX VrefLevel [Byte0]: 63
1727 22:54:14.066322 [Byte1]: 63
1728 22:54:14.070466
1729 22:54:14.070579 Set Vref, RX VrefLevel [Byte0]: 64
1730 22:54:14.073813 [Byte1]: 64
1731 22:54:14.077765
1732 22:54:14.077868 Set Vref, RX VrefLevel [Byte0]: 65
1733 22:54:14.081045 [Byte1]: 65
1734 22:54:14.085419
1735 22:54:14.085527 Set Vref, RX VrefLevel [Byte0]: 66
1736 22:54:14.088536 [Byte1]: 66
1737 22:54:14.093023
1738 22:54:14.093123 Set Vref, RX VrefLevel [Byte0]: 67
1739 22:54:14.096162 [Byte1]: 67
1740 22:54:14.100180
1741 22:54:14.100281 Set Vref, RX VrefLevel [Byte0]: 68
1742 22:54:14.103530 [Byte1]: 68
1743 22:54:14.107901
1744 22:54:14.108048 Set Vref, RX VrefLevel [Byte0]: 69
1745 22:54:14.110711 [Byte1]: 69
1746 22:54:14.115258
1747 22:54:14.115366 Set Vref, RX VrefLevel [Byte0]: 70
1748 22:54:14.118263 [Byte1]: 70
1749 22:54:14.122507
1750 22:54:14.122695 Set Vref, RX VrefLevel [Byte0]: 71
1751 22:54:14.125694 [Byte1]: 71
1752 22:54:14.130222
1753 22:54:14.130334 Set Vref, RX VrefLevel [Byte0]: 72
1754 22:54:14.133291 [Byte1]: 72
1755 22:54:14.137644
1756 22:54:14.137756 Set Vref, RX VrefLevel [Byte0]: 73
1757 22:54:14.141281 [Byte1]: 73
1758 22:54:14.144836
1759 22:54:14.144936 Final RX Vref Byte 0 = 57 to rank0
1760 22:54:14.148710 Final RX Vref Byte 1 = 58 to rank0
1761 22:54:14.151754 Final RX Vref Byte 0 = 57 to rank1
1762 22:54:14.154885 Final RX Vref Byte 1 = 58 to rank1==
1763 22:54:14.158660 Dram Type= 6, Freq= 0, CH_1, rank 0
1764 22:54:14.161544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1765 22:54:14.165215 ==
1766 22:54:14.165345 DQS Delay:
1767 22:54:14.165439 DQS0 = 0, DQS1 = 0
1768 22:54:14.168486 DQM Delay:
1769 22:54:14.168597 DQM0 = 96, DQM1 = 89
1770 22:54:14.171763 DQ Delay:
1771 22:54:14.175214 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =92
1772 22:54:14.179237 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1773 22:54:14.181873 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1774 22:54:14.185045 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1775 22:54:14.185146
1776 22:54:14.185211
1777 22:54:14.192037 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
1778 22:54:14.195229 CH1 RK0: MR19=606, MR18=2F4B
1779 22:54:14.201660 CH1_RK0: MR19=0x606, MR18=0x2F4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1780 22:54:14.201787
1781 22:54:14.205367 ----->DramcWriteLeveling(PI) begin...
1782 22:54:14.205461 ==
1783 22:54:14.208989 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 22:54:14.212323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 22:54:14.212424 ==
1786 22:54:14.215377 Write leveling (Byte 0): 25 => 25
1787 22:54:14.218680 Write leveling (Byte 1): 30 => 30
1788 22:54:14.222058 DramcWriteLeveling(PI) end<-----
1789 22:54:14.222157
1790 22:54:14.222222 ==
1791 22:54:14.225120 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 22:54:14.228611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 22:54:14.228712 ==
1794 22:54:14.231898 [Gating] SW mode calibration
1795 22:54:14.239298 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1796 22:54:14.245575 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1797 22:54:14.249221 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1798 22:54:14.252301 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1799 22:54:14.258499 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 22:54:14.262550 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 22:54:14.266079 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 22:54:14.272241 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 22:54:14.275581 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 22:54:14.278904 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 22:54:14.282160 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 22:54:14.288866 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 22:54:14.291808 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 22:54:14.295817 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 22:54:14.301870 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 22:54:14.305390 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:54:14.308664 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:54:14.315347 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:54:14.318390 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1814 22:54:14.321832 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1815 22:54:14.328572 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:54:14.332263 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 22:54:14.335018 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:54:14.342216 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:54:14.345244 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:54:14.348981 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:54:14.355275 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:54:14.359002 0 9 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1823 22:54:14.362143 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1824 22:54:14.368929 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 22:54:14.372543 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 22:54:14.375796 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 22:54:14.379477 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 22:54:14.385632 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 22:54:14.388952 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 22:54:14.392156 0 10 4 | B1->B0 | 2c2c 3131 | 0 0 | (1 1) (0 1)
1831 22:54:14.398905 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:54:14.402598 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:54:14.405685 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:54:14.412800 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:54:14.415651 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:54:14.419003 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:54:14.425448 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:54:14.428886 0 11 4 | B1->B0 | 3a3a 2e2e | 0 0 | (0 0) (1 1)
1839 22:54:14.432198 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1840 22:54:14.438998 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 22:54:14.442619 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 22:54:14.445539 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 22:54:14.452546 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 22:54:14.455833 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 22:54:14.458948 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 22:54:14.462632 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1847 22:54:14.468959 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 22:54:14.472192 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 22:54:14.475502 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 22:54:14.482340 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 22:54:14.486085 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 22:54:14.489013 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 22:54:14.496125 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 22:54:14.499387 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 22:54:14.502935 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 22:54:14.509231 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 22:54:14.512665 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 22:54:14.516508 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 22:54:14.519924 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:54:14.526185 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:54:14.529582 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1862 22:54:14.532656 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1863 22:54:14.539550 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 22:54:14.543205 Total UI for P1: 0, mck2ui 16
1865 22:54:14.546406 best dqsien dly found for B0: ( 0, 14, 2)
1866 22:54:14.546505 Total UI for P1: 0, mck2ui 16
1867 22:54:14.552668 best dqsien dly found for B1: ( 0, 14, 4)
1868 22:54:14.556100 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1869 22:54:14.559575 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1870 22:54:14.559688
1871 22:54:14.563196 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1872 22:54:14.566359 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1873 22:54:14.569648 [Gating] SW calibration Done
1874 22:54:14.569769 ==
1875 22:54:14.572678 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 22:54:14.576609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 22:54:14.576721 ==
1878 22:54:14.579430 RX Vref Scan: 0
1879 22:54:14.579528
1880 22:54:14.579596 RX Vref 0 -> 0, step: 1
1881 22:54:14.579657
1882 22:54:14.582763 RX Delay -130 -> 252, step: 16
1883 22:54:14.586036 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1884 22:54:14.592765 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1885 22:54:14.596209 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1886 22:54:14.599524 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1887 22:54:14.602761 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1888 22:54:14.606293 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1889 22:54:14.613219 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1890 22:54:14.616191 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1891 22:54:14.619794 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1892 22:54:14.622943 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1893 22:54:14.626576 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1894 22:54:14.633136 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1895 22:54:14.636079 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1896 22:54:14.639898 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1897 22:54:14.643063 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1898 22:54:14.646651 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1899 22:54:14.646846 ==
1900 22:54:14.649460 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 22:54:14.656277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 22:54:14.656461 ==
1903 22:54:14.656570 DQS Delay:
1904 22:54:14.659772 DQS0 = 0, DQS1 = 0
1905 22:54:14.659884 DQM Delay:
1906 22:54:14.662673 DQM0 = 93, DQM1 = 91
1907 22:54:14.662765 DQ Delay:
1908 22:54:14.666048 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1909 22:54:14.669320 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1910 22:54:14.673219 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1911 22:54:14.676398 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1912 22:54:14.676507
1913 22:54:14.676574
1914 22:54:14.676634 ==
1915 22:54:14.679418 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 22:54:14.682622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 22:54:14.682745 ==
1918 22:54:14.682861
1919 22:54:14.682968
1920 22:54:14.686363 TX Vref Scan disable
1921 22:54:14.689441 == TX Byte 0 ==
1922 22:54:14.692593 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1923 22:54:14.696260 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1924 22:54:14.699535 == TX Byte 1 ==
1925 22:54:14.702735 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1926 22:54:14.706233 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1927 22:54:14.706349 ==
1928 22:54:14.709330 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 22:54:14.713328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 22:54:14.716067 ==
1931 22:54:14.728059 TX Vref=22, minBit 3, minWin=25, winSum=432
1932 22:54:14.731301 TX Vref=24, minBit 1, minWin=26, winSum=438
1933 22:54:14.734637 TX Vref=26, minBit 3, minWin=26, winSum=441
1934 22:54:14.737919 TX Vref=28, minBit 1, minWin=26, winSum=441
1935 22:54:14.741030 TX Vref=30, minBit 3, minWin=26, winSum=443
1936 22:54:14.744820 TX Vref=32, minBit 0, minWin=26, winSum=441
1937 22:54:14.750857 [TxChooseVref] Worse bit 3, Min win 26, Win sum 443, Final Vref 30
1938 22:54:14.750994
1939 22:54:14.754600 Final TX Range 1 Vref 30
1940 22:54:14.754724
1941 22:54:14.754791 ==
1942 22:54:14.757695 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 22:54:14.760946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 22:54:14.761048 ==
1945 22:54:14.761116
1946 22:54:14.761175
1947 22:54:14.764540 TX Vref Scan disable
1948 22:54:14.767673 == TX Byte 0 ==
1949 22:54:14.771412 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1950 22:54:14.774398 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1951 22:54:14.778123 == TX Byte 1 ==
1952 22:54:14.781658 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1953 22:54:14.784766 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1954 22:54:14.784868
1955 22:54:14.787850 [DATLAT]
1956 22:54:14.787940 Freq=800, CH1 RK1
1957 22:54:14.788051
1958 22:54:14.791463 DATLAT Default: 0xa
1959 22:54:14.791547 0, 0xFFFF, sum = 0
1960 22:54:14.794624 1, 0xFFFF, sum = 0
1961 22:54:14.794720 2, 0xFFFF, sum = 0
1962 22:54:14.797915 3, 0xFFFF, sum = 0
1963 22:54:14.798021 4, 0xFFFF, sum = 0
1964 22:54:14.801112 5, 0xFFFF, sum = 0
1965 22:54:14.801231 6, 0xFFFF, sum = 0
1966 22:54:14.804756 7, 0xFFFF, sum = 0
1967 22:54:14.804849 8, 0xFFFF, sum = 0
1968 22:54:14.808211 9, 0x0, sum = 1
1969 22:54:14.808315 10, 0x0, sum = 2
1970 22:54:14.811086 11, 0x0, sum = 3
1971 22:54:14.811191 12, 0x0, sum = 4
1972 22:54:14.814546 best_step = 10
1973 22:54:14.814642
1974 22:54:14.814730 ==
1975 22:54:14.818070 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 22:54:14.820945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 22:54:14.821037 ==
1978 22:54:14.824557 RX Vref Scan: 0
1979 22:54:14.824646
1980 22:54:14.824733 RX Vref 0 -> 0, step: 1
1981 22:54:14.824815
1982 22:54:14.828080 RX Delay -63 -> 252, step: 8
1983 22:54:14.834829 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1984 22:54:14.837880 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1985 22:54:14.841425 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1986 22:54:14.844759 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1987 22:54:14.847845 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1988 22:54:14.851553 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1989 22:54:14.858075 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1990 22:54:14.861194 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1991 22:54:14.865105 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1992 22:54:14.868479 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1993 22:54:14.871162 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
1994 22:54:14.875022 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1995 22:54:14.881778 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1996 22:54:14.884659 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1997 22:54:14.888307 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1998 22:54:14.891659 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1999 22:54:14.891774 ==
2000 22:54:14.894851 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 22:54:14.901354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 22:54:14.901482 ==
2003 22:54:14.901578 DQS Delay:
2004 22:54:14.901661 DQS0 = 0, DQS1 = 0
2005 22:54:14.904648 DQM Delay:
2006 22:54:14.904737 DQM0 = 97, DQM1 = 91
2007 22:54:14.908370 DQ Delay:
2008 22:54:14.911357 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2009 22:54:14.914800 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2010 22:54:14.918601 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2011 22:54:14.921629 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2012 22:54:14.921728
2013 22:54:14.921817
2014 22:54:14.928332 [DQSOSCAuto] RK1, (LSB)MR18= 0x450d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2015 22:54:14.931453 CH1 RK1: MR19=606, MR18=450D
2016 22:54:14.937942 CH1_RK1: MR19=0x606, MR18=0x450D, DQSOSC=392, MR23=63, INC=96, DEC=64
2017 22:54:14.941758 [RxdqsGatingPostProcess] freq 800
2018 22:54:14.944863 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2019 22:54:14.948174 Pre-setting of DQS Precalculation
2020 22:54:14.955129 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2021 22:54:14.961599 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2022 22:54:14.968017 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2023 22:54:14.968148
2024 22:54:14.968245
2025 22:54:14.971497 [Calibration Summary] 1600 Mbps
2026 22:54:14.971590 CH 0, Rank 0
2027 22:54:14.975179 SW Impedance : PASS
2028 22:54:14.977974 DUTY Scan : NO K
2029 22:54:14.978078 ZQ Calibration : PASS
2030 22:54:14.981314 Jitter Meter : NO K
2031 22:54:14.984627 CBT Training : PASS
2032 22:54:14.984734 Write leveling : PASS
2033 22:54:14.987881 RX DQS gating : PASS
2034 22:54:14.991883 RX DQ/DQS(RDDQC) : PASS
2035 22:54:14.992031 TX DQ/DQS : PASS
2036 22:54:14.995014 RX DATLAT : PASS
2037 22:54:14.995109 RX DQ/DQS(Engine): PASS
2038 22:54:14.998554 TX OE : NO K
2039 22:54:14.998652 All Pass.
2040 22:54:14.998741
2041 22:54:15.002142 CH 0, Rank 1
2042 22:54:15.002233 SW Impedance : PASS
2043 22:54:15.005120 DUTY Scan : NO K
2044 22:54:15.008411 ZQ Calibration : PASS
2045 22:54:15.008508 Jitter Meter : NO K
2046 22:54:15.011554 CBT Training : PASS
2047 22:54:15.014887 Write leveling : PASS
2048 22:54:15.014990 RX DQS gating : PASS
2049 22:54:15.018137 RX DQ/DQS(RDDQC) : PASS
2050 22:54:15.021589 TX DQ/DQS : PASS
2051 22:54:15.021691 RX DATLAT : PASS
2052 22:54:15.024641 RX DQ/DQS(Engine): PASS
2053 22:54:15.028117 TX OE : NO K
2054 22:54:15.028222 All Pass.
2055 22:54:15.028310
2056 22:54:15.028391 CH 1, Rank 0
2057 22:54:15.031454 SW Impedance : PASS
2058 22:54:15.035045 DUTY Scan : NO K
2059 22:54:15.035144 ZQ Calibration : PASS
2060 22:54:15.038063 Jitter Meter : NO K
2061 22:54:15.041550 CBT Training : PASS
2062 22:54:15.041655 Write leveling : PASS
2063 22:54:15.044699 RX DQS gating : PASS
2064 22:54:15.044793 RX DQ/DQS(RDDQC) : PASS
2065 22:54:15.048487 TX DQ/DQS : PASS
2066 22:54:15.051576 RX DATLAT : PASS
2067 22:54:15.051672 RX DQ/DQS(Engine): PASS
2068 22:54:15.054539 TX OE : NO K
2069 22:54:15.054631 All Pass.
2070 22:54:15.054733
2071 22:54:15.058282 CH 1, Rank 1
2072 22:54:15.058383 SW Impedance : PASS
2073 22:54:15.061478 DUTY Scan : NO K
2074 22:54:15.065070 ZQ Calibration : PASS
2075 22:54:15.065181 Jitter Meter : NO K
2076 22:54:15.068163 CBT Training : PASS
2077 22:54:15.071420 Write leveling : PASS
2078 22:54:15.071522 RX DQS gating : PASS
2079 22:54:15.074477 RX DQ/DQS(RDDQC) : PASS
2080 22:54:15.078128 TX DQ/DQS : PASS
2081 22:54:15.078228 RX DATLAT : PASS
2082 22:54:15.081630 RX DQ/DQS(Engine): PASS
2083 22:54:15.081719 TX OE : NO K
2084 22:54:15.084774 All Pass.
2085 22:54:15.084886
2086 22:54:15.084979 DramC Write-DBI off
2087 22:54:15.087912 PER_BANK_REFRESH: Hybrid Mode
2088 22:54:15.091281 TX_TRACKING: ON
2089 22:54:15.095013 [GetDramInforAfterCalByMRR] Vendor 6.
2090 22:54:15.098066 [GetDramInforAfterCalByMRR] Revision 606.
2091 22:54:15.101253 [GetDramInforAfterCalByMRR] Revision 2 0.
2092 22:54:15.101353 MR0 0x3b3b
2093 22:54:15.101418 MR8 0x5151
2094 22:54:15.108276 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 22:54:15.108396
2096 22:54:15.108463 MR0 0x3b3b
2097 22:54:15.108523 MR8 0x5151
2098 22:54:15.111417 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 22:54:15.111506
2100 22:54:15.121879 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2101 22:54:15.124702 [FAST_K] Save calibration result to emmc
2102 22:54:15.128304 [FAST_K] Save calibration result to emmc
2103 22:54:15.131747 dram_init: config_dvfs: 1
2104 22:54:15.134651 dramc_set_vcore_voltage set vcore to 662500
2105 22:54:15.138380 Read voltage for 1200, 2
2106 22:54:15.138497 Vio18 = 0
2107 22:54:15.138589 Vcore = 662500
2108 22:54:15.141451 Vdram = 0
2109 22:54:15.141556 Vddq = 0
2110 22:54:15.141622 Vmddr = 0
2111 22:54:15.148310 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2112 22:54:15.151655 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2113 22:54:15.154763 MEM_TYPE=3, freq_sel=15
2114 22:54:15.158024 sv_algorithm_assistance_LP4_1600
2115 22:54:15.161458 ============ PULL DRAM RESETB DOWN ============
2116 22:54:15.164624 ========== PULL DRAM RESETB DOWN end =========
2117 22:54:15.171484 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2118 22:54:15.174651 ===================================
2119 22:54:15.178660 LPDDR4 DRAM CONFIGURATION
2120 22:54:15.178759 ===================================
2121 22:54:15.181689 EX_ROW_EN[0] = 0x0
2122 22:54:15.184799 EX_ROW_EN[1] = 0x0
2123 22:54:15.184895 LP4Y_EN = 0x0
2124 22:54:15.188635 WORK_FSP = 0x0
2125 22:54:15.188736 WL = 0x4
2126 22:54:15.191662 RL = 0x4
2127 22:54:15.191752 BL = 0x2
2128 22:54:15.195139 RPST = 0x0
2129 22:54:15.195233 RD_PRE = 0x0
2130 22:54:15.198393 WR_PRE = 0x1
2131 22:54:15.198491 WR_PST = 0x0
2132 22:54:15.201619 DBI_WR = 0x0
2133 22:54:15.201716 DBI_RD = 0x0
2134 22:54:15.204717 OTF = 0x1
2135 22:54:15.208348 ===================================
2136 22:54:15.211364 ===================================
2137 22:54:15.211465 ANA top config
2138 22:54:15.214683 ===================================
2139 22:54:15.218700 DLL_ASYNC_EN = 0
2140 22:54:15.221348 ALL_SLAVE_EN = 0
2141 22:54:15.224669 NEW_RANK_MODE = 1
2142 22:54:15.224765 DLL_IDLE_MODE = 1
2143 22:54:15.228155 LP45_APHY_COMB_EN = 1
2144 22:54:15.231474 TX_ODT_DIS = 1
2145 22:54:15.234619 NEW_8X_MODE = 1
2146 22:54:15.237977 ===================================
2147 22:54:15.241296 ===================================
2148 22:54:15.244534 data_rate = 2400
2149 22:54:15.244631 CKR = 1
2150 22:54:15.248326 DQ_P2S_RATIO = 8
2151 22:54:15.251425 ===================================
2152 22:54:15.254919 CA_P2S_RATIO = 8
2153 22:54:15.258141 DQ_CA_OPEN = 0
2154 22:54:15.261372 DQ_SEMI_OPEN = 0
2155 22:54:15.261458 CA_SEMI_OPEN = 0
2156 22:54:15.264757 CA_FULL_RATE = 0
2157 22:54:15.267890 DQ_CKDIV4_EN = 0
2158 22:54:15.271474 CA_CKDIV4_EN = 0
2159 22:54:15.275033 CA_PREDIV_EN = 0
2160 22:54:15.278120 PH8_DLY = 17
2161 22:54:15.281991 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2162 22:54:15.282100 DQ_AAMCK_DIV = 4
2163 22:54:15.284894 CA_AAMCK_DIV = 4
2164 22:54:15.288031 CA_ADMCK_DIV = 4
2165 22:54:15.291748 DQ_TRACK_CA_EN = 0
2166 22:54:15.295496 CA_PICK = 1200
2167 22:54:15.298652 CA_MCKIO = 1200
2168 22:54:15.298760 MCKIO_SEMI = 0
2169 22:54:15.301889 PLL_FREQ = 2366
2170 22:54:15.304838 DQ_UI_PI_RATIO = 32
2171 22:54:15.308221 CA_UI_PI_RATIO = 0
2172 22:54:15.311360 ===================================
2173 22:54:15.314563 ===================================
2174 22:54:15.318539 memory_type:LPDDR4
2175 22:54:15.318638 GP_NUM : 10
2176 22:54:15.322013 SRAM_EN : 1
2177 22:54:15.325017 MD32_EN : 0
2178 22:54:15.328253 ===================================
2179 22:54:15.328442 [ANA_INIT] >>>>>>>>>>>>>>
2180 22:54:15.331885 <<<<<< [CONFIGURE PHASE]: ANA_TX
2181 22:54:15.335099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2182 22:54:15.338212 ===================================
2183 22:54:15.342021 data_rate = 2400,PCW = 0X5b00
2184 22:54:15.345012 ===================================
2185 22:54:15.348607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2186 22:54:15.354789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 22:54:15.358105 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 22:54:15.364731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2189 22:54:15.368143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2190 22:54:15.371486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2191 22:54:15.371651 [ANA_INIT] flow start
2192 22:54:15.374763 [ANA_INIT] PLL >>>>>>>>
2193 22:54:15.378239 [ANA_INIT] PLL <<<<<<<<
2194 22:54:15.378382 [ANA_INIT] MIDPI >>>>>>>>
2195 22:54:15.381545 [ANA_INIT] MIDPI <<<<<<<<
2196 22:54:15.384709 [ANA_INIT] DLL >>>>>>>>
2197 22:54:15.384841 [ANA_INIT] DLL <<<<<<<<
2198 22:54:15.388433 [ANA_INIT] flow end
2199 22:54:15.391864 ============ LP4 DIFF to SE enter ============
2200 22:54:15.394931 ============ LP4 DIFF to SE exit ============
2201 22:54:15.398443 [ANA_INIT] <<<<<<<<<<<<<
2202 22:54:15.401472 [Flow] Enable top DCM control >>>>>
2203 22:54:15.404920 [Flow] Enable top DCM control <<<<<
2204 22:54:15.408145 Enable DLL master slave shuffle
2205 22:54:15.415218 ==============================================================
2206 22:54:15.415370 Gating Mode config
2207 22:54:15.421525 ==============================================================
2208 22:54:15.421662 Config description:
2209 22:54:15.431345 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2210 22:54:15.438227 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2211 22:54:15.445224 SELPH_MODE 0: By rank 1: By Phase
2212 22:54:15.448323 ==============================================================
2213 22:54:15.451837 GAT_TRACK_EN = 1
2214 22:54:15.455231 RX_GATING_MODE = 2
2215 22:54:15.458539 RX_GATING_TRACK_MODE = 2
2216 22:54:15.461503 SELPH_MODE = 1
2217 22:54:15.464732 PICG_EARLY_EN = 1
2218 22:54:15.468516 VALID_LAT_VALUE = 1
2219 22:54:15.474943 ==============================================================
2220 22:54:15.477984 Enter into Gating configuration >>>>
2221 22:54:15.481590 Exit from Gating configuration <<<<
2222 22:54:15.481728 Enter into DVFS_PRE_config >>>>>
2223 22:54:15.494850 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2224 22:54:15.497977 Exit from DVFS_PRE_config <<<<<
2225 22:54:15.501722 Enter into PICG configuration >>>>
2226 22:54:15.504839 Exit from PICG configuration <<<<
2227 22:54:15.504977 [RX_INPUT] configuration >>>>>
2228 22:54:15.508169 [RX_INPUT] configuration <<<<<
2229 22:54:15.514942 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2230 22:54:15.518390 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2231 22:54:15.524738 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 22:54:15.531481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 22:54:15.538745 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 22:54:15.545038 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 22:54:15.548507 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2236 22:54:15.551796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2237 22:54:15.555376 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2238 22:54:15.562013 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2239 22:54:15.565385 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2240 22:54:15.568468 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2241 22:54:15.572261 ===================================
2242 22:54:15.575330 LPDDR4 DRAM CONFIGURATION
2243 22:54:15.578516 ===================================
2244 22:54:15.578609 EX_ROW_EN[0] = 0x0
2245 22:54:15.582066 EX_ROW_EN[1] = 0x0
2246 22:54:15.585100 LP4Y_EN = 0x0
2247 22:54:15.585192 WORK_FSP = 0x0
2248 22:54:15.588395 WL = 0x4
2249 22:54:15.588483 RL = 0x4
2250 22:54:15.591572 BL = 0x2
2251 22:54:15.591656 RPST = 0x0
2252 22:54:15.595369 RD_PRE = 0x0
2253 22:54:15.595455 WR_PRE = 0x1
2254 22:54:15.598485 WR_PST = 0x0
2255 22:54:15.598571 DBI_WR = 0x0
2256 22:54:15.601544 DBI_RD = 0x0
2257 22:54:15.601644 OTF = 0x1
2258 22:54:15.604789 ===================================
2259 22:54:15.608415 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2260 22:54:15.615124 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2261 22:54:15.618386 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 22:54:15.622371 ===================================
2263 22:54:15.625247 LPDDR4 DRAM CONFIGURATION
2264 22:54:15.628451 ===================================
2265 22:54:15.628538 EX_ROW_EN[0] = 0x10
2266 22:54:15.631473 EX_ROW_EN[1] = 0x0
2267 22:54:15.635190 LP4Y_EN = 0x0
2268 22:54:15.635274 WORK_FSP = 0x0
2269 22:54:15.638415 WL = 0x4
2270 22:54:15.638538 RL = 0x4
2271 22:54:15.641618 BL = 0x2
2272 22:54:15.641701 RPST = 0x0
2273 22:54:15.644860 RD_PRE = 0x0
2274 22:54:15.644944 WR_PRE = 0x1
2275 22:54:15.648507 WR_PST = 0x0
2276 22:54:15.648608 DBI_WR = 0x0
2277 22:54:15.651902 DBI_RD = 0x0
2278 22:54:15.652022 OTF = 0x1
2279 22:54:15.655248 ===================================
2280 22:54:15.661821 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2281 22:54:15.661917 ==
2282 22:54:15.664939 Dram Type= 6, Freq= 0, CH_0, rank 0
2283 22:54:15.668177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2284 22:54:15.668266 ==
2285 22:54:15.671504 [Duty_Offset_Calibration]
2286 22:54:15.675094 B0:2 B1:1 CA:1
2287 22:54:15.675204
2288 22:54:15.677934 [DutyScan_Calibration_Flow] k_type=0
2289 22:54:15.686434
2290 22:54:15.686627 ==CLK 0==
2291 22:54:15.689850 Final CLK duty delay cell = 0
2292 22:54:15.692979 [0] MAX Duty = 5218%(X100), DQS PI = 24
2293 22:54:15.696467 [0] MIN Duty = 4844%(X100), DQS PI = 48
2294 22:54:15.696604 [0] AVG Duty = 5031%(X100)
2295 22:54:15.699802
2296 22:54:15.702890 CH0 CLK Duty spec in!! Max-Min= 374%
2297 22:54:15.706495 [DutyScan_Calibration_Flow] ====Done====
2298 22:54:15.706613
2299 22:54:15.709543 [DutyScan_Calibration_Flow] k_type=1
2300 22:54:15.725356
2301 22:54:15.725492 ==DQS 0 ==
2302 22:54:15.728446 Final DQS duty delay cell = -4
2303 22:54:15.732156 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2304 22:54:15.735198 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2305 22:54:15.738369 [-4] AVG Duty = 4937%(X100)
2306 22:54:15.738454
2307 22:54:15.738518 ==DQS 1 ==
2308 22:54:15.742074 Final DQS duty delay cell = 0
2309 22:54:15.745314 [0] MAX Duty = 5156%(X100), DQS PI = 0
2310 22:54:15.748610 [0] MIN Duty = 5000%(X100), DQS PI = 32
2311 22:54:15.752050 [0] AVG Duty = 5078%(X100)
2312 22:54:15.752133
2313 22:54:15.755021 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2314 22:54:15.755104
2315 22:54:15.758667 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2316 22:54:15.762094 [DutyScan_Calibration_Flow] ====Done====
2317 22:54:15.762191
2318 22:54:15.765431 [DutyScan_Calibration_Flow] k_type=3
2319 22:54:15.781955
2320 22:54:15.782168 ==DQM 0 ==
2321 22:54:15.785211 Final DQM duty delay cell = 0
2322 22:54:15.788317 [0] MAX Duty = 5156%(X100), DQS PI = 30
2323 22:54:15.791792 [0] MIN Duty = 4906%(X100), DQS PI = 50
2324 22:54:15.791896 [0] AVG Duty = 5031%(X100)
2325 22:54:15.795059
2326 22:54:15.795142 ==DQM 1 ==
2327 22:54:15.798562 Final DQM duty delay cell = 0
2328 22:54:15.801634 [0] MAX Duty = 5093%(X100), DQS PI = 0
2329 22:54:15.804998 [0] MIN Duty = 5031%(X100), DQS PI = 16
2330 22:54:15.805088 [0] AVG Duty = 5062%(X100)
2331 22:54:15.808535
2332 22:54:15.812106 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2333 22:54:15.812196
2334 22:54:15.815167 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2335 22:54:15.818724 [DutyScan_Calibration_Flow] ====Done====
2336 22:54:15.818816
2337 22:54:15.821757 [DutyScan_Calibration_Flow] k_type=2
2338 22:54:15.838193
2339 22:54:15.838362 ==DQ 0 ==
2340 22:54:15.841681 Final DQ duty delay cell = 0
2341 22:54:15.845234 [0] MAX Duty = 5062%(X100), DQS PI = 32
2342 22:54:15.848461 [0] MIN Duty = 4875%(X100), DQS PI = 0
2343 22:54:15.848582 [0] AVG Duty = 4968%(X100)
2344 22:54:15.848678
2345 22:54:15.852083 ==DQ 1 ==
2346 22:54:15.855009 Final DQ duty delay cell = 0
2347 22:54:15.858255 [0] MAX Duty = 5093%(X100), DQS PI = 24
2348 22:54:15.861635 [0] MIN Duty = 4907%(X100), DQS PI = 36
2349 22:54:15.861736 [0] AVG Duty = 5000%(X100)
2350 22:54:15.861804
2351 22:54:15.864825 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2352 22:54:15.864956
2353 22:54:15.868046 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2354 22:54:15.875050 [DutyScan_Calibration_Flow] ====Done====
2355 22:54:15.875200 ==
2356 22:54:15.878631 Dram Type= 6, Freq= 0, CH_1, rank 0
2357 22:54:15.881804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 22:54:15.881887 ==
2359 22:54:15.885584 [Duty_Offset_Calibration]
2360 22:54:15.885672 B0:1 B1:0 CA:0
2361 22:54:15.885738
2362 22:54:15.888627 [DutyScan_Calibration_Flow] k_type=0
2363 22:54:15.897293
2364 22:54:15.897420 ==CLK 0==
2365 22:54:15.900769 Final CLK duty delay cell = -4
2366 22:54:15.903843 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2367 22:54:15.907344 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2368 22:54:15.911266 [-4] AVG Duty = 4953%(X100)
2369 22:54:15.911379
2370 22:54:15.914298 CH1 CLK Duty spec in!! Max-Min= 156%
2371 22:54:15.917462 [DutyScan_Calibration_Flow] ====Done====
2372 22:54:15.917550
2373 22:54:15.920789 [DutyScan_Calibration_Flow] k_type=1
2374 22:54:15.937263
2375 22:54:15.937405 ==DQS 0 ==
2376 22:54:15.940453 Final DQS duty delay cell = 0
2377 22:54:15.943885 [0] MAX Duty = 5094%(X100), DQS PI = 26
2378 22:54:15.947146 [0] MIN Duty = 4875%(X100), DQS PI = 0
2379 22:54:15.947250 [0] AVG Duty = 4984%(X100)
2380 22:54:15.950447
2381 22:54:15.950536 ==DQS 1 ==
2382 22:54:15.953726 Final DQS duty delay cell = 0
2383 22:54:15.957281 [0] MAX Duty = 5218%(X100), DQS PI = 18
2384 22:54:15.960198 [0] MIN Duty = 4938%(X100), DQS PI = 12
2385 22:54:15.963499 [0] AVG Duty = 5078%(X100)
2386 22:54:15.963591
2387 22:54:15.967080 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2388 22:54:15.967187
2389 22:54:15.970174 CH1 DQS 1 Duty spec in!! Max-Min= 280%
2390 22:54:15.973611 [DutyScan_Calibration_Flow] ====Done====
2391 22:54:15.973709
2392 22:54:15.976929 [DutyScan_Calibration_Flow] k_type=3
2393 22:54:15.993675
2394 22:54:15.993837 ==DQM 0 ==
2395 22:54:15.997610 Final DQM duty delay cell = 0
2396 22:54:16.000253 [0] MAX Duty = 5156%(X100), DQS PI = 6
2397 22:54:16.003973 [0] MIN Duty = 5031%(X100), DQS PI = 0
2398 22:54:16.004066 [0] AVG Duty = 5093%(X100)
2399 22:54:16.004154
2400 22:54:16.007038 ==DQM 1 ==
2401 22:54:16.010148 Final DQM duty delay cell = 0
2402 22:54:16.014008 [0] MAX Duty = 5031%(X100), DQS PI = 26
2403 22:54:16.017288 [0] MIN Duty = 4907%(X100), DQS PI = 36
2404 22:54:16.017389 [0] AVG Duty = 4969%(X100)
2405 22:54:16.017479
2406 22:54:16.020729 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2407 22:54:16.024117
2408 22:54:16.027571 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2409 22:54:16.030312 [DutyScan_Calibration_Flow] ====Done====
2410 22:54:16.030410
2411 22:54:16.033753 [DutyScan_Calibration_Flow] k_type=2
2412 22:54:16.049416
2413 22:54:16.049578 ==DQ 0 ==
2414 22:54:16.052550 Final DQ duty delay cell = -4
2415 22:54:16.056023 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2416 22:54:16.059567 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2417 22:54:16.062532 [-4] AVG Duty = 4984%(X100)
2418 22:54:16.062631
2419 22:54:16.062719 ==DQ 1 ==
2420 22:54:16.066004 Final DQ duty delay cell = 0
2421 22:54:16.069382 [0] MAX Duty = 5125%(X100), DQS PI = 20
2422 22:54:16.072820 [0] MIN Duty = 4969%(X100), DQS PI = 12
2423 22:54:16.072926 [0] AVG Duty = 5047%(X100)
2424 22:54:16.076048
2425 22:54:16.079566 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2426 22:54:16.079696
2427 22:54:16.083065 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2428 22:54:16.086126 [DutyScan_Calibration_Flow] ====Done====
2429 22:54:16.089381 nWR fixed to 30
2430 22:54:16.089505 [ModeRegInit_LP4] CH0 RK0
2431 22:54:16.092522 [ModeRegInit_LP4] CH0 RK1
2432 22:54:16.095982 [ModeRegInit_LP4] CH1 RK0
2433 22:54:16.099294 [ModeRegInit_LP4] CH1 RK1
2434 22:54:16.099392 match AC timing 7
2435 22:54:16.102603 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2436 22:54:16.109503 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2437 22:54:16.112842 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2438 22:54:16.116651 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2439 22:54:16.122690 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2440 22:54:16.122820 ==
2441 22:54:16.126659 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 22:54:16.129611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 22:54:16.129721 ==
2444 22:54:16.136573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2445 22:54:16.139487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2446 22:54:16.149615 [CA 0] Center 39 (8~70) winsize 63
2447 22:54:16.153258 [CA 1] Center 39 (8~70) winsize 63
2448 22:54:16.156294 [CA 2] Center 35 (5~66) winsize 62
2449 22:54:16.159608 [CA 3] Center 34 (4~65) winsize 62
2450 22:54:16.163194 [CA 4] Center 33 (3~64) winsize 62
2451 22:54:16.166491 [CA 5] Center 32 (3~62) winsize 60
2452 22:54:16.166621
2453 22:54:16.169636 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2454 22:54:16.169735
2455 22:54:16.173462 [CATrainingPosCal] consider 1 rank data
2456 22:54:16.176368 u2DelayCellTimex100 = 270/100 ps
2457 22:54:16.180149 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 22:54:16.183078 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2459 22:54:16.189716 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2460 22:54:16.192878 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2461 22:54:16.196090 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2462 22:54:16.199645 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2463 22:54:16.199768
2464 22:54:16.203476 CA PerBit enable=1, Macro0, CA PI delay=32
2465 22:54:16.203570
2466 22:54:16.206329 [CBTSetCACLKResult] CA Dly = 32
2467 22:54:16.206417 CS Dly: 6 (0~37)
2468 22:54:16.206505 ==
2469 22:54:16.209617 Dram Type= 6, Freq= 0, CH_0, rank 1
2470 22:54:16.216325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 22:54:16.216434 ==
2472 22:54:16.219538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 22:54:16.226576 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2474 22:54:16.235279 [CA 0] Center 38 (8~69) winsize 62
2475 22:54:16.239160 [CA 1] Center 38 (8~69) winsize 62
2476 22:54:16.242088 [CA 2] Center 35 (4~66) winsize 63
2477 22:54:16.245389 [CA 3] Center 34 (4~65) winsize 62
2478 22:54:16.248881 [CA 4] Center 33 (3~64) winsize 62
2479 22:54:16.252043 [CA 5] Center 32 (3~62) winsize 60
2480 22:54:16.252149
2481 22:54:16.255889 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2482 22:54:16.255994
2483 22:54:16.258960 [CATrainingPosCal] consider 2 rank data
2484 22:54:16.262113 u2DelayCellTimex100 = 270/100 ps
2485 22:54:16.265315 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 22:54:16.269194 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2487 22:54:16.275584 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2488 22:54:16.278696 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2489 22:54:16.282223 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2490 22:54:16.285777 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2491 22:54:16.285876
2492 22:54:16.289113 CA PerBit enable=1, Macro0, CA PI delay=32
2493 22:54:16.289205
2494 22:54:16.292124 [CBTSetCACLKResult] CA Dly = 32
2495 22:54:16.292210 CS Dly: 6 (0~38)
2496 22:54:16.292276
2497 22:54:16.295187 ----->DramcWriteLeveling(PI) begin...
2498 22:54:16.298651 ==
2499 22:54:16.302508 Dram Type= 6, Freq= 0, CH_0, rank 0
2500 22:54:16.305389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 22:54:16.305477 ==
2502 22:54:16.308940 Write leveling (Byte 0): 32 => 32
2503 22:54:16.312680 Write leveling (Byte 1): 29 => 29
2504 22:54:16.315285 DramcWriteLeveling(PI) end<-----
2505 22:54:16.315372
2506 22:54:16.315438 ==
2507 22:54:16.318803 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 22:54:16.322015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 22:54:16.322108 ==
2510 22:54:16.325637 [Gating] SW mode calibration
2511 22:54:16.331962 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2512 22:54:16.335561 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2513 22:54:16.342321 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 0)
2514 22:54:16.345460 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2515 22:54:16.349144 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 22:54:16.355687 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 22:54:16.359054 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 22:54:16.362166 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 22:54:16.368730 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2520 22:54:16.372174 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2521 22:54:16.375584 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (1 0)
2522 22:54:16.382483 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 22:54:16.385497 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 22:54:16.389247 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 22:54:16.395811 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 22:54:16.398874 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 22:54:16.402251 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2528 22:54:16.408992 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2529 22:54:16.412365 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2530 22:54:16.415541 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 22:54:16.418758 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 22:54:16.425869 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 22:54:16.429118 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 22:54:16.432436 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 22:54:16.438972 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2536 22:54:16.441977 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2537 22:54:16.445415 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2538 22:54:16.452760 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 22:54:16.455471 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 22:54:16.459362 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 22:54:16.465891 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 22:54:16.469317 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 22:54:16.472158 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 22:54:16.479084 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 22:54:16.482118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 22:54:16.485623 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 22:54:16.492556 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 22:54:16.495620 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 22:54:16.499066 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 22:54:16.502460 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:54:16.509347 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2552 22:54:16.512449 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2553 22:54:16.516164 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2554 22:54:16.519134 Total UI for P1: 0, mck2ui 16
2555 22:54:16.522273 best dqsien dly found for B0: ( 1, 3, 26)
2556 22:54:16.529250 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 22:54:16.529360 Total UI for P1: 0, mck2ui 16
2558 22:54:16.535863 best dqsien dly found for B1: ( 1, 4, 0)
2559 22:54:16.539323 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2560 22:54:16.542738 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2561 22:54:16.542871
2562 22:54:16.545625 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2563 22:54:16.549651 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2564 22:54:16.552337 [Gating] SW calibration Done
2565 22:54:16.552458 ==
2566 22:54:16.555935 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 22:54:16.559223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 22:54:16.559358 ==
2569 22:54:16.562536 RX Vref Scan: 0
2570 22:54:16.562670
2571 22:54:16.562777 RX Vref 0 -> 0, step: 1
2572 22:54:16.562882
2573 22:54:16.565734 RX Delay -40 -> 252, step: 8
2574 22:54:16.569555 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2575 22:54:16.575731 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2576 22:54:16.579271 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2577 22:54:16.582908 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2578 22:54:16.585801 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2579 22:54:16.589257 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2580 22:54:16.592541 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2581 22:54:16.599049 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2582 22:54:16.602667 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2583 22:54:16.606015 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2584 22:54:16.609070 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2585 22:54:16.612584 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2586 22:54:16.619237 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2587 22:54:16.623102 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2588 22:54:16.626080 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2589 22:54:16.629341 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2590 22:54:16.629455 ==
2591 22:54:16.632409 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 22:54:16.639143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 22:54:16.639275 ==
2594 22:54:16.639374 DQS Delay:
2595 22:54:16.643034 DQS0 = 0, DQS1 = 0
2596 22:54:16.643119 DQM Delay:
2597 22:54:16.643184 DQM0 = 121, DQM1 = 113
2598 22:54:16.645923 DQ Delay:
2599 22:54:16.649091 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2600 22:54:16.652484 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2601 22:54:16.655700 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
2602 22:54:16.659233 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2603 22:54:16.659390
2604 22:54:16.659505
2605 22:54:16.659597 ==
2606 22:54:16.662724 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 22:54:16.666536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 22:54:16.666670 ==
2609 22:54:16.669084
2610 22:54:16.669199
2611 22:54:16.669293 TX Vref Scan disable
2612 22:54:16.672621 == TX Byte 0 ==
2613 22:54:16.676167 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2614 22:54:16.679325 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2615 22:54:16.682502 == TX Byte 1 ==
2616 22:54:16.686033 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2617 22:54:16.689672 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2618 22:54:16.689814 ==
2619 22:54:16.692766 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 22:54:16.699027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 22:54:16.699160 ==
2622 22:54:16.709759 TX Vref=22, minBit 0, minWin=25, winSum=408
2623 22:54:16.713614 TX Vref=24, minBit 0, minWin=25, winSum=411
2624 22:54:16.716756 TX Vref=26, minBit 7, minWin=25, winSum=419
2625 22:54:16.720295 TX Vref=28, minBit 1, minWin=26, winSum=423
2626 22:54:16.723874 TX Vref=30, minBit 5, minWin=26, winSum=425
2627 22:54:16.726853 TX Vref=32, minBit 12, minWin=25, winSum=419
2628 22:54:16.733475 [TxChooseVref] Worse bit 5, Min win 26, Win sum 425, Final Vref 30
2629 22:54:16.733627
2630 22:54:16.737017 Final TX Range 1 Vref 30
2631 22:54:16.737147
2632 22:54:16.737221 ==
2633 22:54:16.740210 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 22:54:16.743742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 22:54:16.743876 ==
2636 22:54:16.744013
2637 22:54:16.746789
2638 22:54:16.746886 TX Vref Scan disable
2639 22:54:16.749957 == TX Byte 0 ==
2640 22:54:16.753867 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2641 22:54:16.756954 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2642 22:54:16.760360 == TX Byte 1 ==
2643 22:54:16.763488 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2644 22:54:16.766836 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2645 22:54:16.767033
2646 22:54:16.770528 [DATLAT]
2647 22:54:16.770721 Freq=1200, CH0 RK0
2648 22:54:16.770814
2649 22:54:16.773676 DATLAT Default: 0xd
2650 22:54:16.773769 0, 0xFFFF, sum = 0
2651 22:54:16.777014 1, 0xFFFF, sum = 0
2652 22:54:16.777104 2, 0xFFFF, sum = 0
2653 22:54:16.780562 3, 0xFFFF, sum = 0
2654 22:54:16.780660 4, 0xFFFF, sum = 0
2655 22:54:16.783571 5, 0xFFFF, sum = 0
2656 22:54:16.783666 6, 0xFFFF, sum = 0
2657 22:54:16.787477 7, 0xFFFF, sum = 0
2658 22:54:16.787625 8, 0xFFFF, sum = 0
2659 22:54:16.790405 9, 0xFFFF, sum = 0
2660 22:54:16.794045 10, 0xFFFF, sum = 0
2661 22:54:16.794181 11, 0xFFFF, sum = 0
2662 22:54:16.794253 12, 0x0, sum = 1
2663 22:54:16.796762 13, 0x0, sum = 2
2664 22:54:16.796866 14, 0x0, sum = 3
2665 22:54:16.800318 15, 0x0, sum = 4
2666 22:54:16.800462 best_step = 13
2667 22:54:16.800532
2668 22:54:16.800595 ==
2669 22:54:16.803615 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 22:54:16.810597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 22:54:16.810750 ==
2672 22:54:16.810821 RX Vref Scan: 1
2673 22:54:16.810885
2674 22:54:16.813688 Set Vref Range= 32 -> 127
2675 22:54:16.813855
2676 22:54:16.816918 RX Vref 32 -> 127, step: 1
2677 22:54:16.817027
2678 22:54:16.820294 RX Delay -13 -> 252, step: 4
2679 22:54:16.820409
2680 22:54:16.823457 Set Vref, RX VrefLevel [Byte0]: 32
2681 22:54:16.827192 [Byte1]: 32
2682 22:54:16.827290
2683 22:54:16.830153 Set Vref, RX VrefLevel [Byte0]: 33
2684 22:54:16.833622 [Byte1]: 33
2685 22:54:16.833713
2686 22:54:16.837398 Set Vref, RX VrefLevel [Byte0]: 34
2687 22:54:16.840714 [Byte1]: 34
2688 22:54:16.844303
2689 22:54:16.844391 Set Vref, RX VrefLevel [Byte0]: 35
2690 22:54:16.847743 [Byte1]: 35
2691 22:54:16.852072
2692 22:54:16.852157 Set Vref, RX VrefLevel [Byte0]: 36
2693 22:54:16.855372 [Byte1]: 36
2694 22:54:16.859979
2695 22:54:16.860070 Set Vref, RX VrefLevel [Byte0]: 37
2696 22:54:16.863515 [Byte1]: 37
2697 22:54:16.867671
2698 22:54:16.867797 Set Vref, RX VrefLevel [Byte0]: 38
2699 22:54:16.871333 [Byte1]: 38
2700 22:54:16.875868
2701 22:54:16.876002 Set Vref, RX VrefLevel [Byte0]: 39
2702 22:54:16.879017 [Byte1]: 39
2703 22:54:16.883540
2704 22:54:16.883629 Set Vref, RX VrefLevel [Byte0]: 40
2705 22:54:16.887043 [Byte1]: 40
2706 22:54:16.892077
2707 22:54:16.892176 Set Vref, RX VrefLevel [Byte0]: 41
2708 22:54:16.895329 [Byte1]: 41
2709 22:54:16.899978
2710 22:54:16.900068 Set Vref, RX VrefLevel [Byte0]: 42
2711 22:54:16.903011 [Byte1]: 42
2712 22:54:16.907610
2713 22:54:16.907697 Set Vref, RX VrefLevel [Byte0]: 43
2714 22:54:16.910836 [Byte1]: 43
2715 22:54:16.915658
2716 22:54:16.915745 Set Vref, RX VrefLevel [Byte0]: 44
2717 22:54:16.918994 [Byte1]: 44
2718 22:54:16.923419
2719 22:54:16.923508 Set Vref, RX VrefLevel [Byte0]: 45
2720 22:54:16.926589 [Byte1]: 45
2721 22:54:16.931141
2722 22:54:16.931229 Set Vref, RX VrefLevel [Byte0]: 46
2723 22:54:16.934049 [Byte1]: 46
2724 22:54:16.939275
2725 22:54:16.939394 Set Vref, RX VrefLevel [Byte0]: 47
2726 22:54:16.942340 [Byte1]: 47
2727 22:54:16.946913
2728 22:54:16.946997 Set Vref, RX VrefLevel [Byte0]: 48
2729 22:54:16.950153 [Byte1]: 48
2730 22:54:16.954669
2731 22:54:16.954752 Set Vref, RX VrefLevel [Byte0]: 49
2732 22:54:16.961032 [Byte1]: 49
2733 22:54:16.961121
2734 22:54:16.964585 Set Vref, RX VrefLevel [Byte0]: 50
2735 22:54:16.968160 [Byte1]: 50
2736 22:54:16.968246
2737 22:54:16.970901 Set Vref, RX VrefLevel [Byte0]: 51
2738 22:54:16.974294 [Byte1]: 51
2739 22:54:16.978196
2740 22:54:16.978294 Set Vref, RX VrefLevel [Byte0]: 52
2741 22:54:16.981748 [Byte1]: 52
2742 22:54:16.986154
2743 22:54:16.986283 Set Vref, RX VrefLevel [Byte0]: 53
2744 22:54:16.989412 [Byte1]: 53
2745 22:54:16.994125
2746 22:54:16.994213 Set Vref, RX VrefLevel [Byte0]: 54
2747 22:54:16.997385 [Byte1]: 54
2748 22:54:17.001980
2749 22:54:17.002115 Set Vref, RX VrefLevel [Byte0]: 55
2750 22:54:17.005269 [Byte1]: 55
2751 22:54:17.009656
2752 22:54:17.009746 Set Vref, RX VrefLevel [Byte0]: 56
2753 22:54:17.012844 [Byte1]: 56
2754 22:54:17.018086
2755 22:54:17.018179 Set Vref, RX VrefLevel [Byte0]: 57
2756 22:54:17.020958 [Byte1]: 57
2757 22:54:17.025794
2758 22:54:17.025881 Set Vref, RX VrefLevel [Byte0]: 58
2759 22:54:17.029034 [Byte1]: 58
2760 22:54:17.033509
2761 22:54:17.033594 Set Vref, RX VrefLevel [Byte0]: 59
2762 22:54:17.036665 [Byte1]: 59
2763 22:54:17.041334
2764 22:54:17.041420 Set Vref, RX VrefLevel [Byte0]: 60
2765 22:54:17.044912 [Byte1]: 60
2766 22:54:17.049723
2767 22:54:17.049812 Set Vref, RX VrefLevel [Byte0]: 61
2768 22:54:17.052893 [Byte1]: 61
2769 22:54:17.057333
2770 22:54:17.057416 Set Vref, RX VrefLevel [Byte0]: 62
2771 22:54:17.060574 [Byte1]: 62
2772 22:54:17.065085
2773 22:54:17.065170 Set Vref, RX VrefLevel [Byte0]: 63
2774 22:54:17.068150 [Byte1]: 63
2775 22:54:17.072945
2776 22:54:17.073031 Set Vref, RX VrefLevel [Byte0]: 64
2777 22:54:17.076233 [Byte1]: 64
2778 22:54:17.081064
2779 22:54:17.081154 Set Vref, RX VrefLevel [Byte0]: 65
2780 22:54:17.084234 [Byte1]: 65
2781 22:54:17.088971
2782 22:54:17.089056 Set Vref, RX VrefLevel [Byte0]: 66
2783 22:54:17.092518 [Byte1]: 66
2784 22:54:17.096425
2785 22:54:17.096510 Set Vref, RX VrefLevel [Byte0]: 67
2786 22:54:17.100295 [Byte1]: 67
2787 22:54:17.104595
2788 22:54:17.104678 Set Vref, RX VrefLevel [Byte0]: 68
2789 22:54:17.107765 [Byte1]: 68
2790 22:54:17.112280
2791 22:54:17.112361 Final RX Vref Byte 0 = 56 to rank0
2792 22:54:17.115839 Final RX Vref Byte 1 = 48 to rank0
2793 22:54:17.119457 Final RX Vref Byte 0 = 56 to rank1
2794 22:54:17.122242 Final RX Vref Byte 1 = 48 to rank1==
2795 22:54:17.125529 Dram Type= 6, Freq= 0, CH_0, rank 0
2796 22:54:17.132449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2797 22:54:17.132541 ==
2798 22:54:17.132607 DQS Delay:
2799 22:54:17.132668 DQS0 = 0, DQS1 = 0
2800 22:54:17.135453 DQM Delay:
2801 22:54:17.135535 DQM0 = 120, DQM1 = 111
2802 22:54:17.138835 DQ Delay:
2803 22:54:17.142089 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =120
2804 22:54:17.146251 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2805 22:54:17.149079 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2806 22:54:17.152686 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2807 22:54:17.152769
2808 22:54:17.152835
2809 22:54:17.159181 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2810 22:54:17.162463 CH0 RK0: MR19=404, MR18=140D
2811 22:54:17.169038 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2812 22:54:17.169125
2813 22:54:17.172777 ----->DramcWriteLeveling(PI) begin...
2814 22:54:17.172861 ==
2815 22:54:17.175736 Dram Type= 6, Freq= 0, CH_0, rank 1
2816 22:54:17.178932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 22:54:17.182676 ==
2818 22:54:17.182760 Write leveling (Byte 0): 35 => 35
2819 22:54:17.186255 Write leveling (Byte 1): 30 => 30
2820 22:54:17.189437 DramcWriteLeveling(PI) end<-----
2821 22:54:17.189521
2822 22:54:17.189585 ==
2823 22:54:17.192670 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 22:54:17.199357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 22:54:17.199448 ==
2826 22:54:17.199515 [Gating] SW mode calibration
2827 22:54:17.209217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2828 22:54:17.212399 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2829 22:54:17.216325 0 15 0 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 0)
2830 22:54:17.222656 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 22:54:17.225765 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 22:54:17.229408 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 22:54:17.236174 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 22:54:17.239070 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 22:54:17.242500 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 22:54:17.249483 0 15 28 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 0)
2837 22:54:17.252959 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 22:54:17.256212 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 22:54:17.262705 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 22:54:17.266034 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 22:54:17.269700 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 22:54:17.273128 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 22:54:17.279554 1 0 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2844 22:54:17.283049 1 0 28 | B1->B0 | 3a3a 3c3c | 1 0 | (0 0) (0 0)
2845 22:54:17.286420 1 1 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
2846 22:54:17.293096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 22:54:17.296248 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 22:54:17.300263 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 22:54:17.306519 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 22:54:17.310261 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 22:54:17.313477 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 22:54:17.319932 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2853 22:54:17.323080 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2854 22:54:17.326249 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 22:54:17.332881 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 22:54:17.336858 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 22:54:17.339904 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 22:54:17.346391 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 22:54:17.349614 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 22:54:17.353171 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 22:54:17.356581 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 22:54:17.363185 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 22:54:17.366986 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 22:54:17.370114 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 22:54:17.376464 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 22:54:17.379761 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 22:54:17.382954 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2868 22:54:17.390401 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2869 22:54:17.394005 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2870 22:54:17.396786 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 22:54:17.399659 Total UI for P1: 0, mck2ui 16
2872 22:54:17.403152 best dqsien dly found for B0: ( 1, 3, 28)
2873 22:54:17.406297 Total UI for P1: 0, mck2ui 16
2874 22:54:17.409875 best dqsien dly found for B1: ( 1, 3, 28)
2875 22:54:17.413253 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2876 22:54:17.417096 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2877 22:54:17.417184
2878 22:54:17.420257 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2879 22:54:17.426727 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2880 22:54:17.426822 [Gating] SW calibration Done
2881 22:54:17.426887 ==
2882 22:54:17.429880 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 22:54:17.436329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 22:54:17.436421 ==
2885 22:54:17.436486 RX Vref Scan: 0
2886 22:54:17.436546
2887 22:54:17.439813 RX Vref 0 -> 0, step: 1
2888 22:54:17.439907
2889 22:54:17.443550 RX Delay -40 -> 252, step: 8
2890 22:54:17.446518 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2891 22:54:17.450492 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2892 22:54:17.453506 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2893 22:54:17.459768 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2894 22:54:17.463854 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2895 22:54:17.466926 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2896 22:54:17.469937 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2897 22:54:17.473288 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2898 22:54:17.476517 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2899 22:54:17.483091 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2900 22:54:17.486827 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2901 22:54:17.489836 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2902 22:54:17.493046 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2903 22:54:17.499808 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2904 22:54:17.503528 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2905 22:54:17.506704 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2906 22:54:17.506788 ==
2907 22:54:17.510139 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 22:54:17.513319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 22:54:17.513402 ==
2910 22:54:17.516477 DQS Delay:
2911 22:54:17.516559 DQS0 = 0, DQS1 = 0
2912 22:54:17.516624 DQM Delay:
2913 22:54:17.519819 DQM0 = 121, DQM1 = 112
2914 22:54:17.519901 DQ Delay:
2915 22:54:17.523521 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2916 22:54:17.526452 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2917 22:54:17.533359 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2918 22:54:17.536705 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2919 22:54:17.536794
2920 22:54:17.536859
2921 22:54:17.536925 ==
2922 22:54:17.539784 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 22:54:17.542998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 22:54:17.543083 ==
2925 22:54:17.543148
2926 22:54:17.543207
2927 22:54:17.547217 TX Vref Scan disable
2928 22:54:17.547301 == TX Byte 0 ==
2929 22:54:17.553431 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2930 22:54:17.556541 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2931 22:54:17.556626 == TX Byte 1 ==
2932 22:54:17.563508 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2933 22:54:17.566789 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2934 22:54:17.566878 ==
2935 22:54:17.569830 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 22:54:17.573575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 22:54:17.573661 ==
2938 22:54:17.586483 TX Vref=22, minBit 1, minWin=25, winSum=414
2939 22:54:17.590349 TX Vref=24, minBit 3, minWin=25, winSum=416
2940 22:54:17.593444 TX Vref=26, minBit 3, minWin=25, winSum=415
2941 22:54:17.597211 TX Vref=28, minBit 5, minWin=25, winSum=420
2942 22:54:17.600318 TX Vref=30, minBit 15, minWin=25, winSum=424
2943 22:54:17.603333 TX Vref=32, minBit 5, minWin=25, winSum=421
2944 22:54:17.610446 [TxChooseVref] Worse bit 15, Min win 25, Win sum 424, Final Vref 30
2945 22:54:17.610533
2946 22:54:17.613729 Final TX Range 1 Vref 30
2947 22:54:17.613811
2948 22:54:17.613874 ==
2949 22:54:17.616891 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 22:54:17.620240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 22:54:17.620321 ==
2952 22:54:17.620387
2953 22:54:17.623144
2954 22:54:17.623253 TX Vref Scan disable
2955 22:54:17.626993 == TX Byte 0 ==
2956 22:54:17.630014 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2957 22:54:17.633317 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2958 22:54:17.636596 == TX Byte 1 ==
2959 22:54:17.640389 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2960 22:54:17.643613 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2961 22:54:17.643694
2962 22:54:17.646611 [DATLAT]
2963 22:54:17.646691 Freq=1200, CH0 RK1
2964 22:54:17.646756
2965 22:54:17.649988 DATLAT Default: 0xd
2966 22:54:17.650068 0, 0xFFFF, sum = 0
2967 22:54:17.653406 1, 0xFFFF, sum = 0
2968 22:54:17.653514 2, 0xFFFF, sum = 0
2969 22:54:17.656726 3, 0xFFFF, sum = 0
2970 22:54:17.656807 4, 0xFFFF, sum = 0
2971 22:54:17.660364 5, 0xFFFF, sum = 0
2972 22:54:17.660447 6, 0xFFFF, sum = 0
2973 22:54:17.663670 7, 0xFFFF, sum = 0
2974 22:54:17.666713 8, 0xFFFF, sum = 0
2975 22:54:17.666795 9, 0xFFFF, sum = 0
2976 22:54:17.670100 10, 0xFFFF, sum = 0
2977 22:54:17.670183 11, 0xFFFF, sum = 0
2978 22:54:17.674047 12, 0x0, sum = 1
2979 22:54:17.674155 13, 0x0, sum = 2
2980 22:54:17.676691 14, 0x0, sum = 3
2981 22:54:17.676773 15, 0x0, sum = 4
2982 22:54:17.676838 best_step = 13
2983 22:54:17.676897
2984 22:54:17.680249 ==
2985 22:54:17.680331 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 22:54:17.687060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 22:54:17.687144 ==
2988 22:54:17.687209 RX Vref Scan: 0
2989 22:54:17.687269
2990 22:54:17.690257 RX Vref 0 -> 0, step: 1
2991 22:54:17.690338
2992 22:54:17.693630 RX Delay -13 -> 252, step: 4
2993 22:54:17.696682 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2994 22:54:17.700449 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2995 22:54:17.707514 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2996 22:54:17.710286 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2997 22:54:17.713652 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
2998 22:54:17.716900 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
2999 22:54:17.720143 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3000 22:54:17.726688 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3001 22:54:17.730614 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3002 22:54:17.733785 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3003 22:54:17.736848 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3004 22:54:17.740043 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3005 22:54:17.747456 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3006 22:54:17.750637 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3007 22:54:17.753488 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3008 22:54:17.757120 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3009 22:54:17.757271 ==
3010 22:54:17.760114 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 22:54:17.767030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 22:54:17.767122 ==
3013 22:54:17.767187 DQS Delay:
3014 22:54:17.767246 DQS0 = 0, DQS1 = 0
3015 22:54:17.770565 DQM Delay:
3016 22:54:17.770644 DQM0 = 120, DQM1 = 110
3017 22:54:17.773552 DQ Delay:
3018 22:54:17.777043 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3019 22:54:17.780088 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3020 22:54:17.783629 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3021 22:54:17.786818 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3022 22:54:17.786901
3023 22:54:17.786965
3024 22:54:17.793876 [DQSOSCAuto] RK1, (LSB)MR18= 0xced, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3025 22:54:17.797135 CH0 RK1: MR19=403, MR18=CED
3026 22:54:17.803613 CH0_RK1: MR19=0x403, MR18=0xCED, DQSOSC=405, MR23=63, INC=39, DEC=26
3027 22:54:17.807460 [RxdqsGatingPostProcess] freq 1200
3028 22:54:17.813881 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3029 22:54:17.813971 best DQS0 dly(2T, 0.5T) = (0, 11)
3030 22:54:17.817025 best DQS1 dly(2T, 0.5T) = (0, 12)
3031 22:54:17.820792 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3032 22:54:17.824074 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3033 22:54:17.827078 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 22:54:17.830361 best DQS1 dly(2T, 0.5T) = (0, 11)
3035 22:54:17.833603 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 22:54:17.836960 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3037 22:54:17.840517 Pre-setting of DQS Precalculation
3038 22:54:17.843857 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3039 22:54:17.847796 ==
3040 22:54:17.847880 Dram Type= 6, Freq= 0, CH_1, rank 0
3041 22:54:17.854255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 22:54:17.854344 ==
3043 22:54:17.857555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3044 22:54:17.863784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3045 22:54:17.873142 [CA 0] Center 37 (7~68) winsize 62
3046 22:54:17.876219 [CA 1] Center 37 (7~68) winsize 62
3047 22:54:17.879547 [CA 2] Center 35 (5~65) winsize 61
3048 22:54:17.882756 [CA 3] Center 35 (5~65) winsize 61
3049 22:54:17.886577 [CA 4] Center 34 (4~64) winsize 61
3050 22:54:17.889831 [CA 5] Center 33 (3~63) winsize 61
3051 22:54:17.889915
3052 22:54:17.893299 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3053 22:54:17.893382
3054 22:54:17.896407 [CATrainingPosCal] consider 1 rank data
3055 22:54:17.899506 u2DelayCellTimex100 = 270/100 ps
3056 22:54:17.902693 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3057 22:54:17.906097 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3058 22:54:17.913184 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3059 22:54:17.916092 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3060 22:54:17.919538 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3061 22:54:17.922968 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3062 22:54:17.923051
3063 22:54:17.926445 CA PerBit enable=1, Macro0, CA PI delay=33
3064 22:54:17.926528
3065 22:54:17.929900 [CBTSetCACLKResult] CA Dly = 33
3066 22:54:17.929982 CS Dly: 7 (0~38)
3067 22:54:17.930047 ==
3068 22:54:17.932774 Dram Type= 6, Freq= 0, CH_1, rank 1
3069 22:54:17.940005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 22:54:17.940102 ==
3071 22:54:17.943459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 22:54:17.950243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3073 22:54:17.958338 [CA 0] Center 37 (7~68) winsize 62
3074 22:54:17.962033 [CA 1] Center 37 (7~68) winsize 62
3075 22:54:17.965122 [CA 2] Center 35 (5~65) winsize 61
3076 22:54:17.968469 [CA 3] Center 35 (5~65) winsize 61
3077 22:54:17.971830 [CA 4] Center 34 (4~65) winsize 62
3078 22:54:17.975623 [CA 5] Center 34 (4~64) winsize 61
3079 22:54:17.975732
3080 22:54:17.978557 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3081 22:54:17.978639
3082 22:54:17.982322 [CATrainingPosCal] consider 2 rank data
3083 22:54:17.985647 u2DelayCellTimex100 = 270/100 ps
3084 22:54:17.988735 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 22:54:17.992790 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 22:54:17.995839 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 22:54:18.002237 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3088 22:54:18.005760 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 22:54:18.008875 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3090 22:54:18.008963
3091 22:54:18.012243 CA PerBit enable=1, Macro0, CA PI delay=33
3092 22:54:18.012326
3093 22:54:18.015365 [CBTSetCACLKResult] CA Dly = 33
3094 22:54:18.015448 CS Dly: 8 (0~40)
3095 22:54:18.015513
3096 22:54:18.019342 ----->DramcWriteLeveling(PI) begin...
3097 22:54:18.019427 ==
3098 22:54:18.021991 Dram Type= 6, Freq= 0, CH_1, rank 0
3099 22:54:18.028595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 22:54:18.028683 ==
3101 22:54:18.032370 Write leveling (Byte 0): 28 => 28
3102 22:54:18.035397 Write leveling (Byte 1): 27 => 27
3103 22:54:18.035477 DramcWriteLeveling(PI) end<-----
3104 22:54:18.035541
3105 22:54:18.039114 ==
3106 22:54:18.042355 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 22:54:18.045647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 22:54:18.045728 ==
3109 22:54:18.048866 [Gating] SW mode calibration
3110 22:54:18.055478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3111 22:54:18.058835 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3112 22:54:18.065465 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 22:54:18.068972 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 22:54:18.072061 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 22:54:18.078932 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 22:54:18.082033 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 22:54:18.085649 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 22:54:18.092067 0 15 24 | B1->B0 | 3333 2e2e | 0 1 | (0 1) (1 0)
3119 22:54:18.095800 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3120 22:54:18.099088 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 22:54:18.105633 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 22:54:18.108726 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 22:54:18.112731 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 22:54:18.116018 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 22:54:18.122444 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 22:54:18.125798 1 0 24 | B1->B0 | 2e2e 3838 | 0 1 | (0 0) (0 0)
3127 22:54:18.128750 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 22:54:18.136065 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 22:54:18.139076 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 22:54:18.142343 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 22:54:18.148874 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 22:54:18.152496 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 22:54:18.155547 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 22:54:18.162546 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3135 22:54:18.166009 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3136 22:54:18.169037 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 22:54:18.175736 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 22:54:18.178789 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 22:54:18.182186 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 22:54:18.188919 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 22:54:18.192313 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 22:54:18.196016 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 22:54:18.199001 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 22:54:18.206024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 22:54:18.209179 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 22:54:18.213137 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 22:54:18.219273 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 22:54:18.222442 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 22:54:18.225754 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 22:54:18.232760 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3151 22:54:18.235644 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 22:54:18.239359 Total UI for P1: 0, mck2ui 16
3153 22:54:18.242933 best dqsien dly found for B0: ( 1, 3, 24)
3154 22:54:18.245811 Total UI for P1: 0, mck2ui 16
3155 22:54:18.249373 best dqsien dly found for B1: ( 1, 3, 24)
3156 22:54:18.252809 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3157 22:54:18.255903 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3158 22:54:18.256035
3159 22:54:18.259340 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3160 22:54:18.263048 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3161 22:54:18.265856 [Gating] SW calibration Done
3162 22:54:18.265937 ==
3163 22:54:18.269686 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 22:54:18.272682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 22:54:18.272764 ==
3166 22:54:18.275823 RX Vref Scan: 0
3167 22:54:18.275929
3168 22:54:18.279836 RX Vref 0 -> 0, step: 1
3169 22:54:18.280000
3170 22:54:18.280086 RX Delay -40 -> 252, step: 8
3171 22:54:18.286301 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3172 22:54:18.289320 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3173 22:54:18.292746 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3174 22:54:18.296196 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3175 22:54:18.299141 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3176 22:54:18.306270 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3177 22:54:18.309350 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3178 22:54:18.312866 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3179 22:54:18.315778 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3180 22:54:18.319410 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3181 22:54:18.325823 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3182 22:54:18.329636 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3183 22:54:18.333091 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3184 22:54:18.336285 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3185 22:54:18.339607 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3186 22:54:18.346572 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3187 22:54:18.346659 ==
3188 22:54:18.349576 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 22:54:18.352605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 22:54:18.352690 ==
3191 22:54:18.352791 DQS Delay:
3192 22:54:18.356273 DQS0 = 0, DQS1 = 0
3193 22:54:18.356358 DQM Delay:
3194 22:54:18.359536 DQM0 = 120, DQM1 = 116
3195 22:54:18.359631 DQ Delay:
3196 22:54:18.362795 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3197 22:54:18.366489 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3198 22:54:18.369448 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3199 22:54:18.372834 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3200 22:54:18.372920
3201 22:54:18.373005
3202 22:54:18.376245 ==
3203 22:54:18.376330 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 22:54:18.383159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 22:54:18.383247 ==
3206 22:54:18.383333
3207 22:54:18.383414
3208 22:54:18.386299 TX Vref Scan disable
3209 22:54:18.386383 == TX Byte 0 ==
3210 22:54:18.389454 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3211 22:54:18.396388 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3212 22:54:18.396475 == TX Byte 1 ==
3213 22:54:18.399650 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3214 22:54:18.406067 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3215 22:54:18.406159 ==
3216 22:54:18.409234 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 22:54:18.412639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 22:54:18.412724 ==
3219 22:54:18.424507 TX Vref=22, minBit 11, minWin=24, winSum=413
3220 22:54:18.427580 TX Vref=24, minBit 11, minWin=24, winSum=412
3221 22:54:18.431195 TX Vref=26, minBit 1, minWin=25, winSum=422
3222 22:54:18.434552 TX Vref=28, minBit 9, minWin=25, winSum=427
3223 22:54:18.437931 TX Vref=30, minBit 1, minWin=26, winSum=427
3224 22:54:18.444620 TX Vref=32, minBit 11, minWin=25, winSum=425
3225 22:54:18.447707 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
3226 22:54:18.447792
3227 22:54:18.451250 Final TX Range 1 Vref 30
3228 22:54:18.451335
3229 22:54:18.451421 ==
3230 22:54:18.454245 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 22:54:18.458079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 22:54:18.458167 ==
3233 22:54:18.461121
3234 22:54:18.461198
3235 22:54:18.461296 TX Vref Scan disable
3236 22:54:18.464258 == TX Byte 0 ==
3237 22:54:18.467720 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3238 22:54:18.471127 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3239 22:54:18.474485 == TX Byte 1 ==
3240 22:54:18.477851 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3241 22:54:18.480953 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3242 22:54:18.481082
3243 22:54:18.484556 [DATLAT]
3244 22:54:18.484701 Freq=1200, CH1 RK0
3245 22:54:18.484817
3246 22:54:18.487829 DATLAT Default: 0xd
3247 22:54:18.487927 0, 0xFFFF, sum = 0
3248 22:54:18.491046 1, 0xFFFF, sum = 0
3249 22:54:18.491147 2, 0xFFFF, sum = 0
3250 22:54:18.494444 3, 0xFFFF, sum = 0
3251 22:54:18.494532 4, 0xFFFF, sum = 0
3252 22:54:18.498240 5, 0xFFFF, sum = 0
3253 22:54:18.498326 6, 0xFFFF, sum = 0
3254 22:54:18.501441 7, 0xFFFF, sum = 0
3255 22:54:18.501525 8, 0xFFFF, sum = 0
3256 22:54:18.504567 9, 0xFFFF, sum = 0
3257 22:54:18.508223 10, 0xFFFF, sum = 0
3258 22:54:18.508322 11, 0xFFFF, sum = 0
3259 22:54:18.511562 12, 0x0, sum = 1
3260 22:54:18.511888 13, 0x0, sum = 2
3261 22:54:18.512185 14, 0x0, sum = 3
3262 22:54:18.514738 15, 0x0, sum = 4
3263 22:54:18.515230 best_step = 13
3264 22:54:18.515623
3265 22:54:18.518385 ==
3266 22:54:18.518750 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 22:54:18.525296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 22:54:18.525776 ==
3269 22:54:18.526168 RX Vref Scan: 1
3270 22:54:18.526524
3271 22:54:18.528121 Set Vref Range= 32 -> 127
3272 22:54:18.528485
3273 22:54:18.531214 RX Vref 32 -> 127, step: 1
3274 22:54:18.531580
3275 22:54:18.535579 RX Delay -5 -> 252, step: 4
3276 22:54:18.536133
3277 22:54:18.538756 Set Vref, RX VrefLevel [Byte0]: 32
3278 22:54:18.541962 [Byte1]: 32
3279 22:54:18.542331
3280 22:54:18.545049 Set Vref, RX VrefLevel [Byte0]: 33
3281 22:54:18.548182 [Byte1]: 33
3282 22:54:18.548661
3283 22:54:18.551587 Set Vref, RX VrefLevel [Byte0]: 34
3284 22:54:18.554528 [Byte1]: 34
3285 22:54:18.558803
3286 22:54:18.559279 Set Vref, RX VrefLevel [Byte0]: 35
3287 22:54:18.562114 [Byte1]: 35
3288 22:54:18.567146
3289 22:54:18.567674 Set Vref, RX VrefLevel [Byte0]: 36
3290 22:54:18.570200 [Byte1]: 36
3291 22:54:18.574156
3292 22:54:18.574521 Set Vref, RX VrefLevel [Byte0]: 37
3293 22:54:18.577263 [Byte1]: 37
3294 22:54:18.581967
3295 22:54:18.582135 Set Vref, RX VrefLevel [Byte0]: 38
3296 22:54:18.585257 [Byte1]: 38
3297 22:54:18.589737
3298 22:54:18.589870 Set Vref, RX VrefLevel [Byte0]: 39
3299 22:54:18.593209 [Byte1]: 39
3300 22:54:18.597681
3301 22:54:18.597807 Set Vref, RX VrefLevel [Byte0]: 40
3302 22:54:18.600859 [Byte1]: 40
3303 22:54:18.605230
3304 22:54:18.605331 Set Vref, RX VrefLevel [Byte0]: 41
3305 22:54:18.608646 [Byte1]: 41
3306 22:54:18.613287
3307 22:54:18.613373 Set Vref, RX VrefLevel [Byte0]: 42
3308 22:54:18.616951 [Byte1]: 42
3309 22:54:18.621622
3310 22:54:18.621747 Set Vref, RX VrefLevel [Byte0]: 43
3311 22:54:18.624869 [Byte1]: 43
3312 22:54:18.629288
3313 22:54:18.629379 Set Vref, RX VrefLevel [Byte0]: 44
3314 22:54:18.632571 [Byte1]: 44
3315 22:54:18.637106
3316 22:54:18.637187 Set Vref, RX VrefLevel [Byte0]: 45
3317 22:54:18.640250 [Byte1]: 45
3318 22:54:18.644904
3319 22:54:18.644985 Set Vref, RX VrefLevel [Byte0]: 46
3320 22:54:18.648263 [Byte1]: 46
3321 22:54:18.652648
3322 22:54:18.652728 Set Vref, RX VrefLevel [Byte0]: 47
3323 22:54:18.655978 [Byte1]: 47
3324 22:54:18.660653
3325 22:54:18.660732 Set Vref, RX VrefLevel [Byte0]: 48
3326 22:54:18.663993 [Byte1]: 48
3327 22:54:18.668528
3328 22:54:18.668608 Set Vref, RX VrefLevel [Byte0]: 49
3329 22:54:18.671887 [Byte1]: 49
3330 22:54:18.676617
3331 22:54:18.676696 Set Vref, RX VrefLevel [Byte0]: 50
3332 22:54:18.679689 [Byte1]: 50
3333 22:54:18.684226
3334 22:54:18.684306 Set Vref, RX VrefLevel [Byte0]: 51
3335 22:54:18.687165 [Byte1]: 51
3336 22:54:18.692361
3337 22:54:18.692441 Set Vref, RX VrefLevel [Byte0]: 52
3338 22:54:18.695620 [Byte1]: 52
3339 22:54:18.699586
3340 22:54:18.699666 Set Vref, RX VrefLevel [Byte0]: 53
3341 22:54:18.702755 [Byte1]: 53
3342 22:54:18.707500
3343 22:54:18.707579 Set Vref, RX VrefLevel [Byte0]: 54
3344 22:54:18.710593 [Byte1]: 54
3345 22:54:18.715543
3346 22:54:18.715622 Set Vref, RX VrefLevel [Byte0]: 55
3347 22:54:18.718994 [Byte1]: 55
3348 22:54:18.723328
3349 22:54:18.723408 Set Vref, RX VrefLevel [Byte0]: 56
3350 22:54:18.726327 [Byte1]: 56
3351 22:54:18.730946
3352 22:54:18.731026 Set Vref, RX VrefLevel [Byte0]: 57
3353 22:54:18.734313 [Byte1]: 57
3354 22:54:18.739084
3355 22:54:18.739165 Set Vref, RX VrefLevel [Byte0]: 58
3356 22:54:18.742280 [Byte1]: 58
3357 22:54:18.746705
3358 22:54:18.746785 Set Vref, RX VrefLevel [Byte0]: 59
3359 22:54:18.749981 [Byte1]: 59
3360 22:54:18.754554
3361 22:54:18.754634 Set Vref, RX VrefLevel [Byte0]: 60
3362 22:54:18.757699 [Byte1]: 60
3363 22:54:18.762511
3364 22:54:18.762592 Set Vref, RX VrefLevel [Byte0]: 61
3365 22:54:18.765662 [Byte1]: 61
3366 22:54:18.770214
3367 22:54:18.773527 Set Vref, RX VrefLevel [Byte0]: 62
3368 22:54:18.773609 [Byte1]: 62
3369 22:54:18.778101
3370 22:54:18.778191 Set Vref, RX VrefLevel [Byte0]: 63
3371 22:54:18.781415 [Byte1]: 63
3372 22:54:18.785908
3373 22:54:18.785996 Set Vref, RX VrefLevel [Byte0]: 64
3374 22:54:18.799555 [Byte1]: 64
3375 22:54:18.799682
3376 22:54:18.799749 Set Vref, RX VrefLevel [Byte0]: 65
3377 22:54:18.799811 [Byte1]: 65
3378 22:54:18.801788
3379 22:54:18.801868 Set Vref, RX VrefLevel [Byte0]: 66
3380 22:54:18.805047 [Byte1]: 66
3381 22:54:18.809629
3382 22:54:18.809709 Set Vref, RX VrefLevel [Byte0]: 67
3383 22:54:18.813232 [Byte1]: 67
3384 22:54:18.817548
3385 22:54:18.817628 Set Vref, RX VrefLevel [Byte0]: 68
3386 22:54:18.821179 [Byte1]: 68
3387 22:54:18.825189
3388 22:54:18.825270 Final RX Vref Byte 0 = 53 to rank0
3389 22:54:18.828762 Final RX Vref Byte 1 = 53 to rank0
3390 22:54:18.831899 Final RX Vref Byte 0 = 53 to rank1
3391 22:54:18.835633 Final RX Vref Byte 1 = 53 to rank1==
3392 22:54:18.838346 Dram Type= 6, Freq= 0, CH_1, rank 0
3393 22:54:18.845142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3394 22:54:18.845228 ==
3395 22:54:18.845314 DQS Delay:
3396 22:54:18.845395 DQS0 = 0, DQS1 = 0
3397 22:54:18.848542 DQM Delay:
3398 22:54:18.848625 DQM0 = 120, DQM1 = 117
3399 22:54:18.851975 DQ Delay:
3400 22:54:18.855218 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3401 22:54:18.858543 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3402 22:54:18.862024 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3403 22:54:18.865418 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3404 22:54:18.865539
3405 22:54:18.865625
3406 22:54:18.872136 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3407 22:54:18.875619 CH1 RK0: MR19=404, MR18=316
3408 22:54:18.882389 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3409 22:54:18.882474
3410 22:54:18.885636 ----->DramcWriteLeveling(PI) begin...
3411 22:54:18.885721 ==
3412 22:54:18.888835 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 22:54:18.892125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 22:54:18.892214 ==
3415 22:54:18.895614 Write leveling (Byte 0): 27 => 27
3416 22:54:18.898769 Write leveling (Byte 1): 29 => 29
3417 22:54:18.902609 DramcWriteLeveling(PI) end<-----
3418 22:54:18.902692
3419 22:54:18.902777 ==
3420 22:54:18.905520 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 22:54:18.908666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 22:54:18.912436 ==
3423 22:54:18.912520 [Gating] SW mode calibration
3424 22:54:18.919059 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3425 22:54:18.925594 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3426 22:54:18.928995 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 22:54:18.935570 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 22:54:18.938813 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 22:54:18.942751 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 22:54:18.949311 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 22:54:18.952481 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3432 22:54:18.955653 0 15 24 | B1->B0 | 2b2b 3333 | 0 1 | (1 0) (1 1)
3433 22:54:18.962381 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 1)
3434 22:54:18.965609 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 22:54:18.969274 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 22:54:18.972872 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 22:54:18.979272 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 22:54:18.983193 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 22:54:18.985977 1 0 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
3440 22:54:18.992600 1 0 24 | B1->B0 | 4040 2929 | 0 0 | (0 0) (0 0)
3441 22:54:18.996146 1 0 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
3442 22:54:18.999527 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 22:54:19.006479 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 22:54:19.009747 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 22:54:19.013015 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 22:54:19.019840 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 22:54:19.023198 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3448 22:54:19.026636 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3449 22:54:19.033150 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3450 22:54:19.036432 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 22:54:19.040020 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 22:54:19.046361 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 22:54:19.049973 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 22:54:19.053377 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 22:54:19.056276 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 22:54:19.062914 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 22:54:19.066761 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 22:54:19.069483 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 22:54:19.076471 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 22:54:19.079992 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 22:54:19.083360 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 22:54:19.089560 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 22:54:19.092690 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3464 22:54:19.096342 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3465 22:54:19.099776 Total UI for P1: 0, mck2ui 16
3466 22:54:19.102728 best dqsien dly found for B1: ( 1, 3, 20)
3467 22:54:19.109582 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3468 22:54:19.112390 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 22:54:19.115816 Total UI for P1: 0, mck2ui 16
3470 22:54:19.119101 best dqsien dly found for B0: ( 1, 3, 26)
3471 22:54:19.122689 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3472 22:54:19.126243 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3473 22:54:19.126735
3474 22:54:19.129382 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3475 22:54:19.132581 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3476 22:54:19.136034 [Gating] SW calibration Done
3477 22:54:19.136421 ==
3478 22:54:19.139304 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 22:54:19.142603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 22:54:19.145902 ==
3481 22:54:19.146282 RX Vref Scan: 0
3482 22:54:19.146585
3483 22:54:19.149264 RX Vref 0 -> 0, step: 1
3484 22:54:19.149644
3485 22:54:19.152845 RX Delay -40 -> 252, step: 8
3486 22:54:19.156307 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3487 22:54:19.159330 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3488 22:54:19.162341 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3489 22:54:19.165656 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3490 22:54:19.172296 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3491 22:54:19.175879 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3492 22:54:19.178968 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3493 22:54:19.182432 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3494 22:54:19.185851 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3495 22:54:19.192497 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3496 22:54:19.195766 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3497 22:54:19.199230 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3498 22:54:19.202399 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3499 22:54:19.205577 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3500 22:54:19.212347 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3501 22:54:19.215722 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3502 22:54:19.216188 ==
3503 22:54:19.218963 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 22:54:19.222661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 22:54:19.223186 ==
3506 22:54:19.225295 DQS Delay:
3507 22:54:19.225714 DQS0 = 0, DQS1 = 0
3508 22:54:19.226048 DQM Delay:
3509 22:54:19.228446 DQM0 = 121, DQM1 = 117
3510 22:54:19.228889 DQ Delay:
3511 22:54:19.231736 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3512 22:54:19.235287 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3513 22:54:19.241884 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3514 22:54:19.245241 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3515 22:54:19.245618
3516 22:54:19.245916
3517 22:54:19.246193 ==
3518 22:54:19.248462 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 22:54:19.251673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 22:54:19.252095 ==
3521 22:54:19.252401
3522 22:54:19.252701
3523 22:54:19.255150 TX Vref Scan disable
3524 22:54:19.258931 == TX Byte 0 ==
3525 22:54:19.261983 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3526 22:54:19.265478 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3527 22:54:19.268584 == TX Byte 1 ==
3528 22:54:19.271890 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3529 22:54:19.274774 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3530 22:54:19.275152 ==
3531 22:54:19.278778 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 22:54:19.281928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 22:54:19.284515 ==
3534 22:54:19.295492 TX Vref=22, minBit 1, minWin=25, winSum=418
3535 22:54:19.298296 TX Vref=24, minBit 1, minWin=26, winSum=425
3536 22:54:19.301305 TX Vref=26, minBit 8, minWin=26, winSum=432
3537 22:54:19.305105 TX Vref=28, minBit 10, minWin=25, winSum=431
3538 22:54:19.307870 TX Vref=30, minBit 10, minWin=26, winSum=434
3539 22:54:19.314837 TX Vref=32, minBit 0, minWin=27, winSum=436
3540 22:54:19.317995 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 32
3541 22:54:19.318415
3542 22:54:19.321594 Final TX Range 1 Vref 32
3543 22:54:19.322121
3544 22:54:19.322460 ==
3545 22:54:19.324731 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 22:54:19.328202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 22:54:19.331404 ==
3548 22:54:19.332030
3549 22:54:19.332528
3550 22:54:19.332888 TX Vref Scan disable
3551 22:54:19.334677 == TX Byte 0 ==
3552 22:54:19.338209 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3553 22:54:19.344837 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3554 22:54:19.345253 == TX Byte 1 ==
3555 22:54:19.347874 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3556 22:54:19.354916 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3557 22:54:19.355451
3558 22:54:19.355795 [DATLAT]
3559 22:54:19.356147 Freq=1200, CH1 RK1
3560 22:54:19.356452
3561 22:54:19.357720 DATLAT Default: 0xd
3562 22:54:19.358131 0, 0xFFFF, sum = 0
3563 22:54:19.361266 1, 0xFFFF, sum = 0
3564 22:54:19.364755 2, 0xFFFF, sum = 0
3565 22:54:19.365150 3, 0xFFFF, sum = 0
3566 22:54:19.367907 4, 0xFFFF, sum = 0
3567 22:54:19.368431 5, 0xFFFF, sum = 0
3568 22:54:19.371530 6, 0xFFFF, sum = 0
3569 22:54:19.371912 7, 0xFFFF, sum = 0
3570 22:54:19.374375 8, 0xFFFF, sum = 0
3571 22:54:19.374856 9, 0xFFFF, sum = 0
3572 22:54:19.377420 10, 0xFFFF, sum = 0
3573 22:54:19.377882 11, 0xFFFF, sum = 0
3574 22:54:19.380749 12, 0x0, sum = 1
3575 22:54:19.381137 13, 0x0, sum = 2
3576 22:54:19.384027 14, 0x0, sum = 3
3577 22:54:19.384442 15, 0x0, sum = 4
3578 22:54:19.387533 best_step = 13
3579 22:54:19.388058
3580 22:54:19.388369 ==
3581 22:54:19.391226 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 22:54:19.394717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 22:54:19.395211 ==
3584 22:54:19.395523 RX Vref Scan: 0
3585 22:54:19.397997
3586 22:54:19.398414 RX Vref 0 -> 0, step: 1
3587 22:54:19.398763
3588 22:54:19.401341 RX Delay -5 -> 252, step: 4
3589 22:54:19.404160 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3590 22:54:19.411391 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3591 22:54:19.414292 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3592 22:54:19.417626 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3593 22:54:19.420555 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3594 22:54:19.424021 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3595 22:54:19.431155 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3596 22:54:19.434425 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3597 22:54:19.437846 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3598 22:54:19.440888 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3599 22:54:19.444395 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3600 22:54:19.450890 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3601 22:54:19.454078 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3602 22:54:19.457833 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3603 22:54:19.460823 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3604 22:54:19.467625 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3605 22:54:19.468178 ==
3606 22:54:19.470738 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 22:54:19.474252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 22:54:19.474774 ==
3609 22:54:19.475113 DQS Delay:
3610 22:54:19.477314 DQS0 = 0, DQS1 = 0
3611 22:54:19.477731 DQM Delay:
3612 22:54:19.480628 DQM0 = 120, DQM1 = 118
3613 22:54:19.481048 DQ Delay:
3614 22:54:19.484264 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3615 22:54:19.487144 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3616 22:54:19.490538 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3617 22:54:19.493765 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3618 22:54:19.494189
3619 22:54:19.494520
3620 22:54:19.504323 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3621 22:54:19.506934 CH1 RK1: MR19=403, MR18=13F0
3622 22:54:19.510936 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3623 22:54:19.514128 [RxdqsGatingPostProcess] freq 1200
3624 22:54:19.520547 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3625 22:54:19.523723 best DQS0 dly(2T, 0.5T) = (0, 11)
3626 22:54:19.527248 best DQS1 dly(2T, 0.5T) = (0, 11)
3627 22:54:19.530380 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3628 22:54:19.533336 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3629 22:54:19.536476 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 22:54:19.539743 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 22:54:19.543109 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 22:54:19.546658 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 22:54:19.550264 Pre-setting of DQS Precalculation
3634 22:54:19.553329 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3635 22:54:19.560145 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3636 22:54:19.569731 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3637 22:54:19.570259
3638 22:54:19.570594
3639 22:54:19.573053 [Calibration Summary] 2400 Mbps
3640 22:54:19.573468 CH 0, Rank 0
3641 22:54:19.576620 SW Impedance : PASS
3642 22:54:19.577139 DUTY Scan : NO K
3643 22:54:19.580027 ZQ Calibration : PASS
3644 22:54:19.580553 Jitter Meter : NO K
3645 22:54:19.583237 CBT Training : PASS
3646 22:54:19.586678 Write leveling : PASS
3647 22:54:19.587214 RX DQS gating : PASS
3648 22:54:19.589725 RX DQ/DQS(RDDQC) : PASS
3649 22:54:19.593210 TX DQ/DQS : PASS
3650 22:54:19.593738 RX DATLAT : PASS
3651 22:54:19.596634 RX DQ/DQS(Engine): PASS
3652 22:54:19.599562 TX OE : NO K
3653 22:54:19.600153 All Pass.
3654 22:54:19.600508
3655 22:54:19.600821 CH 0, Rank 1
3656 22:54:19.603267 SW Impedance : PASS
3657 22:54:19.606533 DUTY Scan : NO K
3658 22:54:19.606949 ZQ Calibration : PASS
3659 22:54:19.609810 Jitter Meter : NO K
3660 22:54:19.613087 CBT Training : PASS
3661 22:54:19.613502 Write leveling : PASS
3662 22:54:19.617177 RX DQS gating : PASS
3663 22:54:19.619440 RX DQ/DQS(RDDQC) : PASS
3664 22:54:19.619857 TX DQ/DQS : PASS
3665 22:54:19.622830 RX DATLAT : PASS
3666 22:54:19.626144 RX DQ/DQS(Engine): PASS
3667 22:54:19.626565 TX OE : NO K
3668 22:54:19.626904 All Pass.
3669 22:54:19.627223
3670 22:54:19.629779 CH 1, Rank 0
3671 22:54:19.632876 SW Impedance : PASS
3672 22:54:19.633300 DUTY Scan : NO K
3673 22:54:19.636029 ZQ Calibration : PASS
3674 22:54:19.636566 Jitter Meter : NO K
3675 22:54:19.639758 CBT Training : PASS
3676 22:54:19.642935 Write leveling : PASS
3677 22:54:19.643504 RX DQS gating : PASS
3678 22:54:19.646408 RX DQ/DQS(RDDQC) : PASS
3679 22:54:19.649245 TX DQ/DQS : PASS
3680 22:54:19.649680 RX DATLAT : PASS
3681 22:54:19.652975 RX DQ/DQS(Engine): PASS
3682 22:54:19.656642 TX OE : NO K
3683 22:54:19.657159 All Pass.
3684 22:54:19.657495
3685 22:54:19.657805 CH 1, Rank 1
3686 22:54:19.659996 SW Impedance : PASS
3687 22:54:19.663130 DUTY Scan : NO K
3688 22:54:19.663545 ZQ Calibration : PASS
3689 22:54:19.665990 Jitter Meter : NO K
3690 22:54:19.669468 CBT Training : PASS
3691 22:54:19.669898 Write leveling : PASS
3692 22:54:19.672633 RX DQS gating : PASS
3693 22:54:19.675746 RX DQ/DQS(RDDQC) : PASS
3694 22:54:19.676263 TX DQ/DQS : PASS
3695 22:54:19.679397 RX DATLAT : PASS
3696 22:54:19.680006 RX DQ/DQS(Engine): PASS
3697 22:54:19.682429 TX OE : NO K
3698 22:54:19.682849 All Pass.
3699 22:54:19.683186
3700 22:54:19.686119 DramC Write-DBI off
3701 22:54:19.689219 PER_BANK_REFRESH: Hybrid Mode
3702 22:54:19.689655 TX_TRACKING: ON
3703 22:54:19.699412 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3704 22:54:19.702911 [FAST_K] Save calibration result to emmc
3705 22:54:19.706184 dramc_set_vcore_voltage set vcore to 650000
3706 22:54:19.708899 Read voltage for 600, 5
3707 22:54:19.709323 Vio18 = 0
3708 22:54:19.712551 Vcore = 650000
3709 22:54:19.713064 Vdram = 0
3710 22:54:19.713402 Vddq = 0
3711 22:54:19.713716 Vmddr = 0
3712 22:54:19.719747 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3713 22:54:19.726237 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3714 22:54:19.726741 MEM_TYPE=3, freq_sel=19
3715 22:54:19.729500 sv_algorithm_assistance_LP4_1600
3716 22:54:19.733205 ============ PULL DRAM RESETB DOWN ============
3717 22:54:19.739382 ========== PULL DRAM RESETB DOWN end =========
3718 22:54:19.742370 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3719 22:54:19.746057 ===================================
3720 22:54:19.749479 LPDDR4 DRAM CONFIGURATION
3721 22:54:19.752789 ===================================
3722 22:54:19.753388 EX_ROW_EN[0] = 0x0
3723 22:54:19.755897 EX_ROW_EN[1] = 0x0
3724 22:54:19.756354 LP4Y_EN = 0x0
3725 22:54:19.759281 WORK_FSP = 0x0
3726 22:54:19.759795 WL = 0x2
3727 22:54:19.762024 RL = 0x2
3728 22:54:19.762465 BL = 0x2
3729 22:54:19.765530 RPST = 0x0
3730 22:54:19.768699 RD_PRE = 0x0
3731 22:54:19.769121 WR_PRE = 0x1
3732 22:54:19.772269 WR_PST = 0x0
3733 22:54:19.772786 DBI_WR = 0x0
3734 22:54:19.775557 DBI_RD = 0x0
3735 22:54:19.776108 OTF = 0x1
3736 22:54:19.779082 ===================================
3737 22:54:19.782270 ===================================
3738 22:54:19.785620 ANA top config
3739 22:54:19.786133 ===================================
3740 22:54:19.788553 DLL_ASYNC_EN = 0
3741 22:54:19.792441 ALL_SLAVE_EN = 1
3742 22:54:19.795055 NEW_RANK_MODE = 1
3743 22:54:19.798972 DLL_IDLE_MODE = 1
3744 22:54:19.799439 LP45_APHY_COMB_EN = 1
3745 22:54:19.802081 TX_ODT_DIS = 1
3746 22:54:19.805495 NEW_8X_MODE = 1
3747 22:54:19.808659 ===================================
3748 22:54:19.811768 ===================================
3749 22:54:19.815528 data_rate = 1200
3750 22:54:19.818982 CKR = 1
3751 22:54:19.819565 DQ_P2S_RATIO = 8
3752 22:54:19.821704 ===================================
3753 22:54:19.825914 CA_P2S_RATIO = 8
3754 22:54:19.828610 DQ_CA_OPEN = 0
3755 22:54:19.832023 DQ_SEMI_OPEN = 0
3756 22:54:19.835589 CA_SEMI_OPEN = 0
3757 22:54:19.838997 CA_FULL_RATE = 0
3758 22:54:19.839509 DQ_CKDIV4_EN = 1
3759 22:54:19.842040 CA_CKDIV4_EN = 1
3760 22:54:19.845297 CA_PREDIV_EN = 0
3761 22:54:19.848575 PH8_DLY = 0
3762 22:54:19.851892 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3763 22:54:19.855743 DQ_AAMCK_DIV = 4
3764 22:54:19.856311 CA_AAMCK_DIV = 4
3765 22:54:19.858564 CA_ADMCK_DIV = 4
3766 22:54:19.861785 DQ_TRACK_CA_EN = 0
3767 22:54:19.865281 CA_PICK = 600
3768 22:54:19.868211 CA_MCKIO = 600
3769 22:54:19.871722 MCKIO_SEMI = 0
3770 22:54:19.875258 PLL_FREQ = 2288
3771 22:54:19.875775 DQ_UI_PI_RATIO = 32
3772 22:54:19.878286 CA_UI_PI_RATIO = 0
3773 22:54:19.882089 ===================================
3774 22:54:19.884961 ===================================
3775 22:54:19.888372 memory_type:LPDDR4
3776 22:54:19.891595 GP_NUM : 10
3777 22:54:19.892074 SRAM_EN : 1
3778 22:54:19.895248 MD32_EN : 0
3779 22:54:19.898525 ===================================
3780 22:54:19.901283 [ANA_INIT] >>>>>>>>>>>>>>
3781 22:54:19.901708 <<<<<< [CONFIGURE PHASE]: ANA_TX
3782 22:54:19.905092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3783 22:54:19.908333 ===================================
3784 22:54:19.911748 data_rate = 1200,PCW = 0X5800
3785 22:54:19.915399 ===================================
3786 22:54:19.918607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3787 22:54:19.925268 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3788 22:54:19.931511 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3789 22:54:19.934931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3790 22:54:19.938263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3791 22:54:19.941682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3792 22:54:19.944814 [ANA_INIT] flow start
3793 22:54:19.945230 [ANA_INIT] PLL >>>>>>>>
3794 22:54:19.948382 [ANA_INIT] PLL <<<<<<<<
3795 22:54:19.951678 [ANA_INIT] MIDPI >>>>>>>>
3796 22:54:19.955163 [ANA_INIT] MIDPI <<<<<<<<
3797 22:54:19.955683 [ANA_INIT] DLL >>>>>>>>
3798 22:54:19.958507 [ANA_INIT] flow end
3799 22:54:19.961399 ============ LP4 DIFF to SE enter ============
3800 22:54:19.964659 ============ LP4 DIFF to SE exit ============
3801 22:54:19.968413 [ANA_INIT] <<<<<<<<<<<<<
3802 22:54:19.971252 [Flow] Enable top DCM control >>>>>
3803 22:54:19.974615 [Flow] Enable top DCM control <<<<<
3804 22:54:19.978280 Enable DLL master slave shuffle
3805 22:54:19.984238 ==============================================================
3806 22:54:19.984686 Gating Mode config
3807 22:54:19.991208 ==============================================================
3808 22:54:19.991621 Config description:
3809 22:54:20.000835 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3810 22:54:20.007744 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3811 22:54:20.013993 SELPH_MODE 0: By rank 1: By Phase
3812 22:54:20.017266 ==============================================================
3813 22:54:20.020867 GAT_TRACK_EN = 1
3814 22:54:20.024085 RX_GATING_MODE = 2
3815 22:54:20.027638 RX_GATING_TRACK_MODE = 2
3816 22:54:20.031269 SELPH_MODE = 1
3817 22:54:20.034487 PICG_EARLY_EN = 1
3818 22:54:20.037658 VALID_LAT_VALUE = 1
3819 22:54:20.041275 ==============================================================
3820 22:54:20.043793 Enter into Gating configuration >>>>
3821 22:54:20.047302 Exit from Gating configuration <<<<
3822 22:54:20.050827 Enter into DVFS_PRE_config >>>>>
3823 22:54:20.064573 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3824 22:54:20.068122 Exit from DVFS_PRE_config <<<<<
3825 22:54:20.071114 Enter into PICG configuration >>>>
3826 22:54:20.073904 Exit from PICG configuration <<<<
3827 22:54:20.074326 [RX_INPUT] configuration >>>>>
3828 22:54:20.077097 [RX_INPUT] configuration <<<<<
3829 22:54:20.084016 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3830 22:54:20.087059 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3831 22:54:20.094479 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3832 22:54:20.100514 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3833 22:54:20.107292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3834 22:54:20.114042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3835 22:54:20.117321 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3836 22:54:20.120292 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3837 22:54:20.124032 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3838 22:54:20.131024 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3839 22:54:20.133897 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3840 22:54:20.137043 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3841 22:54:20.140392 ===================================
3842 22:54:20.143828 LPDDR4 DRAM CONFIGURATION
3843 22:54:20.146651 ===================================
3844 22:54:20.150415 EX_ROW_EN[0] = 0x0
3845 22:54:20.150842 EX_ROW_EN[1] = 0x0
3846 22:54:20.153642 LP4Y_EN = 0x0
3847 22:54:20.154307 WORK_FSP = 0x0
3848 22:54:20.156778 WL = 0x2
3849 22:54:20.157290 RL = 0x2
3850 22:54:20.160469 BL = 0x2
3851 22:54:20.160882 RPST = 0x0
3852 22:54:20.163208 RD_PRE = 0x0
3853 22:54:20.164131 WR_PRE = 0x1
3854 22:54:20.166898 WR_PST = 0x0
3855 22:54:20.167460 DBI_WR = 0x0
3856 22:54:20.170381 DBI_RD = 0x0
3857 22:54:20.170816 OTF = 0x1
3858 22:54:20.173739 ===================================
3859 22:54:20.179841 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3860 22:54:20.183142 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3861 22:54:20.187078 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 22:54:20.190304 ===================================
3863 22:54:20.193649 LPDDR4 DRAM CONFIGURATION
3864 22:54:20.196754 ===================================
3865 22:54:20.199560 EX_ROW_EN[0] = 0x10
3866 22:54:20.199949 EX_ROW_EN[1] = 0x0
3867 22:54:20.202873 LP4Y_EN = 0x0
3868 22:54:20.203252 WORK_FSP = 0x0
3869 22:54:20.206126 WL = 0x2
3870 22:54:20.206433 RL = 0x2
3871 22:54:20.210214 BL = 0x2
3872 22:54:20.210515 RPST = 0x0
3873 22:54:20.213256 RD_PRE = 0x0
3874 22:54:20.213498 WR_PRE = 0x1
3875 22:54:20.216297 WR_PST = 0x0
3876 22:54:20.216539 DBI_WR = 0x0
3877 22:54:20.219886 DBI_RD = 0x0
3878 22:54:20.220181 OTF = 0x1
3879 22:54:20.223274 ===================================
3880 22:54:20.229295 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3881 22:54:20.234804 nWR fixed to 30
3882 22:54:20.238014 [ModeRegInit_LP4] CH0 RK0
3883 22:54:20.238289 [ModeRegInit_LP4] CH0 RK1
3884 22:54:20.240715 [ModeRegInit_LP4] CH1 RK0
3885 22:54:20.244562 [ModeRegInit_LP4] CH1 RK1
3886 22:54:20.244753 match AC timing 17
3887 22:54:20.250657 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3888 22:54:20.254051 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3889 22:54:20.257531 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3890 22:54:20.264574 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3891 22:54:20.267281 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3892 22:54:20.267391 ==
3893 22:54:20.270804 Dram Type= 6, Freq= 0, CH_0, rank 0
3894 22:54:20.274025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3895 22:54:20.274110 ==
3896 22:54:20.280645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3897 22:54:20.287421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3898 22:54:20.290589 [CA 0] Center 35 (5~66) winsize 62
3899 22:54:20.293811 [CA 1] Center 35 (5~66) winsize 62
3900 22:54:20.297304 [CA 2] Center 33 (3~64) winsize 62
3901 22:54:20.300888 [CA 3] Center 33 (2~64) winsize 63
3902 22:54:20.303590 [CA 4] Center 33 (2~64) winsize 63
3903 22:54:20.307117 [CA 5] Center 32 (2~63) winsize 62
3904 22:54:20.307294
3905 22:54:20.310588 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3906 22:54:20.310767
3907 22:54:20.313929 [CATrainingPosCal] consider 1 rank data
3908 22:54:20.317242 u2DelayCellTimex100 = 270/100 ps
3909 22:54:20.320620 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3910 22:54:20.323579 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3911 22:54:20.327277 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3912 22:54:20.330623 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3913 22:54:20.336851 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3914 22:54:20.340395 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3915 22:54:20.340617
3916 22:54:20.343849 CA PerBit enable=1, Macro0, CA PI delay=32
3917 22:54:20.344072
3918 22:54:20.347468 [CBTSetCACLKResult] CA Dly = 32
3919 22:54:20.347810 CS Dly: 4 (0~35)
3920 22:54:20.348064 ==
3921 22:54:20.349894 Dram Type= 6, Freq= 0, CH_0, rank 1
3922 22:54:20.357500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 22:54:20.358018 ==
3924 22:54:20.360400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 22:54:20.367502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3926 22:54:20.370531 [CA 0] Center 35 (5~66) winsize 62
3927 22:54:20.373406 [CA 1] Center 35 (5~66) winsize 62
3928 22:54:20.377012 [CA 2] Center 34 (3~65) winsize 63
3929 22:54:20.380013 [CA 3] Center 34 (3~65) winsize 63
3930 22:54:20.383678 [CA 4] Center 32 (2~63) winsize 62
3931 22:54:20.386961 [CA 5] Center 32 (2~63) winsize 62
3932 22:54:20.387379
3933 22:54:20.390230 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3934 22:54:20.390681
3935 22:54:20.393605 [CATrainingPosCal] consider 2 rank data
3936 22:54:20.396649 u2DelayCellTimex100 = 270/100 ps
3937 22:54:20.400397 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3938 22:54:20.403217 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3939 22:54:20.407082 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3940 22:54:20.413358 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3941 22:54:20.416743 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3942 22:54:20.419951 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3943 22:54:20.420407
3944 22:54:20.423507 CA PerBit enable=1, Macro0, CA PI delay=32
3945 22:54:20.423922
3946 22:54:20.426823 [CBTSetCACLKResult] CA Dly = 32
3947 22:54:20.427234 CS Dly: 5 (0~37)
3948 22:54:20.427557
3949 22:54:20.429932 ----->DramcWriteLeveling(PI) begin...
3950 22:54:20.430352 ==
3951 22:54:20.433687 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 22:54:20.440073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 22:54:20.440544 ==
3954 22:54:20.443382 Write leveling (Byte 0): 35 => 35
3955 22:54:20.446641 Write leveling (Byte 1): 33 => 33
3956 22:54:20.447100 DramcWriteLeveling(PI) end<-----
3957 22:54:20.449879
3958 22:54:20.450289 ==
3959 22:54:20.453524 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 22:54:20.456782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 22:54:20.457216 ==
3962 22:54:20.460214 [Gating] SW mode calibration
3963 22:54:20.466607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3964 22:54:20.469899 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3965 22:54:20.476591 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 22:54:20.479676 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 22:54:20.482999 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 22:54:20.492819 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
3969 22:54:20.493245 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3970 22:54:20.496733 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 22:54:20.502776 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 22:54:20.506401 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 22:54:20.509416 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 22:54:20.515947 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 22:54:20.519531 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 22:54:20.522690 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
3977 22:54:20.529446 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3978 22:54:20.532782 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 22:54:20.536257 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 22:54:20.539615 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 22:54:20.546381 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 22:54:20.549529 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 22:54:20.553665 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 22:54:20.560002 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3985 22:54:20.563170 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 22:54:20.566229 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 22:54:20.573078 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 22:54:20.576429 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 22:54:20.579834 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 22:54:20.586332 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 22:54:20.589511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 22:54:20.592826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 22:54:20.599486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 22:54:20.602899 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 22:54:20.606435 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 22:54:20.612724 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 22:54:20.616602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 22:54:20.619541 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 22:54:20.625931 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 22:54:20.629847 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 22:54:20.632573 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 22:54:20.636505 Total UI for P1: 0, mck2ui 16
4003 22:54:20.639831 best dqsien dly found for B0: ( 0, 13, 14)
4004 22:54:20.643116 Total UI for P1: 0, mck2ui 16
4005 22:54:20.645943 best dqsien dly found for B1: ( 0, 13, 14)
4006 22:54:20.649835 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4007 22:54:20.653199 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4008 22:54:20.653578
4009 22:54:20.656361 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4010 22:54:20.662911 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4011 22:54:20.663511 [Gating] SW calibration Done
4012 22:54:20.663848 ==
4013 22:54:20.666866 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 22:54:20.673048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 22:54:20.673595 ==
4016 22:54:20.674073 RX Vref Scan: 0
4017 22:54:20.674509
4018 22:54:20.676379 RX Vref 0 -> 0, step: 1
4019 22:54:20.676788
4020 22:54:20.679599 RX Delay -230 -> 252, step: 16
4021 22:54:20.682975 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4022 22:54:20.686806 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4023 22:54:20.692979 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4024 22:54:20.696260 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4025 22:54:20.699711 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4026 22:54:20.702854 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4027 22:54:20.706412 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4028 22:54:20.713141 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4029 22:54:20.716412 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4030 22:54:20.719897 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4031 22:54:20.722990 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4032 22:54:20.726512 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4033 22:54:20.732973 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4034 22:54:20.736147 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4035 22:54:20.739587 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4036 22:54:20.743189 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4037 22:54:20.746417 ==
4038 22:54:20.749616 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 22:54:20.752884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 22:54:20.753298 ==
4041 22:54:20.753629 DQS Delay:
4042 22:54:20.756350 DQS0 = 0, DQS1 = 0
4043 22:54:20.756763 DQM Delay:
4044 22:54:20.759845 DQM0 = 48, DQM1 = 45
4045 22:54:20.760403 DQ Delay:
4046 22:54:20.762829 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4047 22:54:20.766758 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4048 22:54:20.770106 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4049 22:54:20.772572 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4050 22:54:20.772988
4051 22:54:20.773315
4052 22:54:20.773620 ==
4053 22:54:20.776111 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 22:54:20.779645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 22:54:20.780210 ==
4056 22:54:20.780558
4057 22:54:20.780865
4058 22:54:20.782986 TX Vref Scan disable
4059 22:54:20.786326 == TX Byte 0 ==
4060 22:54:20.789207 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4061 22:54:20.792361 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4062 22:54:20.795789 == TX Byte 1 ==
4063 22:54:20.799456 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4064 22:54:20.802507 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4065 22:54:20.802974 ==
4066 22:54:20.806000 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 22:54:20.812510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 22:54:20.812938 ==
4069 22:54:20.813269
4070 22:54:20.813575
4071 22:54:20.813865 TX Vref Scan disable
4072 22:54:20.817071 == TX Byte 0 ==
4073 22:54:20.820179 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4074 22:54:20.826701 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4075 22:54:20.826936 == TX Byte 1 ==
4076 22:54:20.829637 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4077 22:54:20.836377 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4078 22:54:20.836565
4079 22:54:20.836741 [DATLAT]
4080 22:54:20.836907 Freq=600, CH0 RK0
4081 22:54:20.837064
4082 22:54:20.839744 DATLAT Default: 0x9
4083 22:54:20.839839 0, 0xFFFF, sum = 0
4084 22:54:20.842898 1, 0xFFFF, sum = 0
4085 22:54:20.843011 2, 0xFFFF, sum = 0
4086 22:54:20.846124 3, 0xFFFF, sum = 0
4087 22:54:20.849661 4, 0xFFFF, sum = 0
4088 22:54:20.849776 5, 0xFFFF, sum = 0
4089 22:54:20.852639 6, 0xFFFF, sum = 0
4090 22:54:20.852723 7, 0xFFFF, sum = 0
4091 22:54:20.856268 8, 0x0, sum = 1
4092 22:54:20.856353 9, 0x0, sum = 2
4093 22:54:20.856418 10, 0x0, sum = 3
4094 22:54:20.859322 11, 0x0, sum = 4
4095 22:54:20.859405 best_step = 9
4096 22:54:20.859469
4097 22:54:20.859528 ==
4098 22:54:20.862906 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 22:54:20.869440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 22:54:20.869522 ==
4101 22:54:20.869586 RX Vref Scan: 1
4102 22:54:20.869645
4103 22:54:20.872774 RX Vref 0 -> 0, step: 1
4104 22:54:20.872854
4105 22:54:20.875887 RX Delay -163 -> 252, step: 8
4106 22:54:20.876025
4107 22:54:20.879502 Set Vref, RX VrefLevel [Byte0]: 56
4108 22:54:20.882869 [Byte1]: 48
4109 22:54:20.882953
4110 22:54:20.886023 Final RX Vref Byte 0 = 56 to rank0
4111 22:54:20.889423 Final RX Vref Byte 1 = 48 to rank0
4112 22:54:20.892744 Final RX Vref Byte 0 = 56 to rank1
4113 22:54:20.896082 Final RX Vref Byte 1 = 48 to rank1==
4114 22:54:20.899374 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 22:54:20.902844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 22:54:20.902929 ==
4117 22:54:20.906218 DQS Delay:
4118 22:54:20.906323 DQS0 = 0, DQS1 = 0
4119 22:54:20.909880 DQM Delay:
4120 22:54:20.910050 DQM0 = 53, DQM1 = 46
4121 22:54:20.910134 DQ Delay:
4122 22:54:20.913051 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4123 22:54:20.915878 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =64
4124 22:54:20.919251 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4125 22:54:20.922462 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4126 22:54:20.922582
4127 22:54:20.922677
4128 22:54:20.932724 [DQSOSCAuto] RK0, (LSB)MR18= 0x7568, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 387 ps
4129 22:54:20.936469 CH0 RK0: MR19=808, MR18=7568
4130 22:54:20.939767 CH0_RK0: MR19=0x808, MR18=0x7568, DQSOSC=387, MR23=63, INC=175, DEC=116
4131 22:54:20.942894
4132 22:54:20.946088 ----->DramcWriteLeveling(PI) begin...
4133 22:54:20.946508 ==
4134 22:54:20.949510 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 22:54:20.952667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 22:54:20.953254 ==
4137 22:54:20.955852 Write leveling (Byte 0): 32 => 32
4138 22:54:20.959301 Write leveling (Byte 1): 31 => 31
4139 22:54:20.962577 DramcWriteLeveling(PI) end<-----
4140 22:54:20.963141
4141 22:54:20.963571 ==
4142 22:54:20.966097 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 22:54:20.969172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 22:54:20.969587 ==
4145 22:54:20.972541 [Gating] SW mode calibration
4146 22:54:20.979329 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4147 22:54:20.985851 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4148 22:54:20.988936 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 22:54:20.992858 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 22:54:20.999231 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4151 22:54:21.002444 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4152 22:54:21.005992 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4153 22:54:21.012612 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 22:54:21.015858 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 22:54:21.019117 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 22:54:21.025274 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 22:54:21.028592 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 22:54:21.032554 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 22:54:21.035774 0 10 12 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
4160 22:54:21.042403 0 10 16 | B1->B0 | 3c3c 3e3e | 1 0 | (0 0) (0 0)
4161 22:54:21.045734 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 22:54:21.048428 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 22:54:21.055226 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 22:54:21.059056 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 22:54:21.062515 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 22:54:21.068538 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 22:54:21.072367 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4168 22:54:21.075551 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4169 22:54:21.082105 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 22:54:21.085580 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 22:54:21.088870 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 22:54:21.095768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 22:54:21.099223 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 22:54:21.102172 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 22:54:21.108791 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 22:54:21.111891 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 22:54:21.115500 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 22:54:21.121889 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 22:54:21.125355 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 22:54:21.128563 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 22:54:21.135209 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 22:54:21.139052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 22:54:21.142088 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4184 22:54:21.149014 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4185 22:54:21.152267 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 22:54:21.155750 Total UI for P1: 0, mck2ui 16
4187 22:54:21.158979 best dqsien dly found for B0: ( 0, 13, 14)
4188 22:54:21.162393 Total UI for P1: 0, mck2ui 16
4189 22:54:21.165219 best dqsien dly found for B1: ( 0, 13, 14)
4190 22:54:21.168779 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4191 22:54:21.172180 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4192 22:54:21.172856
4193 22:54:21.175138 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4194 22:54:21.178618 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4195 22:54:21.182176 [Gating] SW calibration Done
4196 22:54:21.182817 ==
4197 22:54:21.185288 Dram Type= 6, Freq= 0, CH_0, rank 1
4198 22:54:21.188236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 22:54:21.188700 ==
4200 22:54:21.191505 RX Vref Scan: 0
4201 22:54:21.191727
4202 22:54:21.194961 RX Vref 0 -> 0, step: 1
4203 22:54:21.195181
4204 22:54:21.195437 RX Delay -230 -> 252, step: 16
4205 22:54:21.201877 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4206 22:54:21.205012 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4207 22:54:21.207986 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4208 22:54:21.211762 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4209 22:54:21.218434 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4210 22:54:21.221385 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4211 22:54:21.224951 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4212 22:54:21.228411 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4213 22:54:21.235080 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4214 22:54:21.238333 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4215 22:54:21.240959 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4216 22:54:21.244273 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4217 22:54:21.251122 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4218 22:54:21.254789 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4219 22:54:21.258082 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4220 22:54:21.261507 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4221 22:54:21.261694 ==
4222 22:54:21.264889 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 22:54:21.271033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 22:54:21.271449 ==
4225 22:54:21.271781 DQS Delay:
4226 22:54:21.274184 DQS0 = 0, DQS1 = 0
4227 22:54:21.274594 DQM Delay:
4228 22:54:21.274922 DQM0 = 51, DQM1 = 43
4229 22:54:21.277829 DQ Delay:
4230 22:54:21.281004 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4231 22:54:21.284424 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4232 22:54:21.287641 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4233 22:54:21.291095 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4234 22:54:21.291515
4235 22:54:21.291842
4236 22:54:21.292201 ==
4237 22:54:21.294156 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 22:54:21.297527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 22:54:21.297940 ==
4240 22:54:21.298272
4241 22:54:21.298576
4242 22:54:21.300865 TX Vref Scan disable
4243 22:54:21.304435 == TX Byte 0 ==
4244 22:54:21.307205 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4245 22:54:21.310868 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4246 22:54:21.314241 == TX Byte 1 ==
4247 22:54:21.317125 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4248 22:54:21.320460 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4249 22:54:21.320640 ==
4250 22:54:21.324014 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 22:54:21.327495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 22:54:21.330909 ==
4253 22:54:21.331039
4254 22:54:21.331141
4255 22:54:21.331249 TX Vref Scan disable
4256 22:54:21.333960 == TX Byte 0 ==
4257 22:54:21.337434 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4258 22:54:21.344300 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4259 22:54:21.344411 == TX Byte 1 ==
4260 22:54:21.347200 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4261 22:54:21.354379 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4262 22:54:21.354471
4263 22:54:21.354537 [DATLAT]
4264 22:54:21.354597 Freq=600, CH0 RK1
4265 22:54:21.354655
4266 22:54:21.357529 DATLAT Default: 0x9
4267 22:54:21.360588 0, 0xFFFF, sum = 0
4268 22:54:21.360669 1, 0xFFFF, sum = 0
4269 22:54:21.364214 2, 0xFFFF, sum = 0
4270 22:54:21.364295 3, 0xFFFF, sum = 0
4271 22:54:21.366999 4, 0xFFFF, sum = 0
4272 22:54:21.367080 5, 0xFFFF, sum = 0
4273 22:54:21.370135 6, 0xFFFF, sum = 0
4274 22:54:21.370217 7, 0xFFFF, sum = 0
4275 22:54:21.373548 8, 0x0, sum = 1
4276 22:54:21.373629 9, 0x0, sum = 2
4277 22:54:21.373694 10, 0x0, sum = 3
4278 22:54:21.376818 11, 0x0, sum = 4
4279 22:54:21.376899 best_step = 9
4280 22:54:21.376963
4281 22:54:21.380250 ==
4282 22:54:21.380329 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 22:54:21.387416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 22:54:21.387497 ==
4285 22:54:21.387561 RX Vref Scan: 0
4286 22:54:21.387621
4287 22:54:21.390127 RX Vref 0 -> 0, step: 1
4288 22:54:21.390207
4289 22:54:21.393828 RX Delay -163 -> 252, step: 8
4290 22:54:21.396946 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4291 22:54:21.403471 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4292 22:54:21.406891 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4293 22:54:21.409998 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4294 22:54:21.413628 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4295 22:54:21.417142 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4296 22:54:21.424194 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4297 22:54:21.427041 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4298 22:54:21.430707 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4299 22:54:21.433659 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4300 22:54:21.436851 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4301 22:54:21.443824 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4302 22:54:21.446849 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4303 22:54:21.450281 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4304 22:54:21.453225 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4305 22:54:21.459886 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4306 22:54:21.460049 ==
4307 22:54:21.463635 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 22:54:21.466831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 22:54:21.466946 ==
4310 22:54:21.467036 DQS Delay:
4311 22:54:21.470274 DQS0 = 0, DQS1 = 0
4312 22:54:21.470386 DQM Delay:
4313 22:54:21.473527 DQM0 = 54, DQM1 = 46
4314 22:54:21.473649 DQ Delay:
4315 22:54:21.476920 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4316 22:54:21.480073 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4317 22:54:21.556583 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4318 22:54:21.557090 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4319 22:54:21.557425
4320 22:54:21.557734
4321 22:54:21.558025 [DQSOSCAuto] RK1, (LSB)MR18= 0x6928, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4322 22:54:21.558322 CH0 RK1: MR19=808, MR18=6928
4323 22:54:21.558605 CH0_RK1: MR19=0x808, MR18=0x6928, DQSOSC=390, MR23=63, INC=172, DEC=114
4324 22:54:21.558888 [RxdqsGatingPostProcess] freq 600
4325 22:54:21.559165 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4326 22:54:21.559445 Pre-setting of DQS Precalculation
4327 22:54:21.559720 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4328 22:54:21.560025 ==
4329 22:54:21.560304 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 22:54:21.560721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 22:54:21.561129 ==
4332 22:54:21.561422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4333 22:54:21.561701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4334 22:54:21.561978 [CA 0] Center 36 (5~67) winsize 63
4335 22:54:21.562252 [CA 1] Center 36 (5~67) winsize 63
4336 22:54:21.562521 [CA 2] Center 34 (4~65) winsize 62
4337 22:54:21.562791 [CA 3] Center 34 (3~65) winsize 63
4338 22:54:21.563060 [CA 4] Center 34 (4~65) winsize 62
4339 22:54:21.563666 [CA 5] Center 33 (3~64) winsize 62
4340 22:54:21.564000
4341 22:54:21.564362 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4342 22:54:21.564767
4343 22:54:21.566662 [CATrainingPosCal] consider 1 rank data
4344 22:54:21.569745 u2DelayCellTimex100 = 270/100 ps
4345 22:54:21.573028 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4346 22:54:21.576566 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4347 22:54:21.579811 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4348 22:54:21.582984 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4349 22:54:21.586459 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4350 22:54:21.589766 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4351 22:54:21.593073
4352 22:54:21.596032 CA PerBit enable=1, Macro0, CA PI delay=33
4353 22:54:21.596212
4354 22:54:21.599897 [CBTSetCACLKResult] CA Dly = 33
4355 22:54:21.600087 CS Dly: 5 (0~36)
4356 22:54:21.600214 ==
4357 22:54:21.603208 Dram Type= 6, Freq= 0, CH_1, rank 1
4358 22:54:21.606158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 22:54:21.606287 ==
4360 22:54:21.612872 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4361 22:54:21.619769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4362 22:54:21.622833 [CA 0] Center 36 (5~67) winsize 63
4363 22:54:21.626722 [CA 1] Center 36 (5~67) winsize 63
4364 22:54:21.629791 [CA 2] Center 35 (4~66) winsize 63
4365 22:54:21.633217 [CA 3] Center 34 (4~65) winsize 62
4366 22:54:21.635966 [CA 4] Center 35 (4~66) winsize 63
4367 22:54:21.639143 [CA 5] Center 34 (4~65) winsize 62
4368 22:54:21.639241
4369 22:54:21.642551 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4370 22:54:21.642624
4371 22:54:21.645717 [CATrainingPosCal] consider 2 rank data
4372 22:54:21.649112 u2DelayCellTimex100 = 270/100 ps
4373 22:54:21.652350 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4374 22:54:21.655895 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4375 22:54:21.659122 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4376 22:54:21.662591 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4377 22:54:21.669401 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4378 22:54:21.672465 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4379 22:54:21.672575
4380 22:54:21.675623 CA PerBit enable=1, Macro0, CA PI delay=34
4381 22:54:21.675732
4382 22:54:21.678884 [CBTSetCACLKResult] CA Dly = 34
4383 22:54:21.678992 CS Dly: 5 (0~37)
4384 22:54:21.679083
4385 22:54:21.682769 ----->DramcWriteLeveling(PI) begin...
4386 22:54:21.683146 ==
4387 22:54:21.686078 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 22:54:21.692284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 22:54:21.692826 ==
4390 22:54:21.695921 Write leveling (Byte 0): 29 => 29
4391 22:54:21.699071 Write leveling (Byte 1): 29 => 29
4392 22:54:21.699486 DramcWriteLeveling(PI) end<-----
4393 22:54:21.699813
4394 22:54:21.703187 ==
4395 22:54:21.705722 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 22:54:21.709188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 22:54:21.709641 ==
4398 22:54:21.712929 [Gating] SW mode calibration
4399 22:54:21.719392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4400 22:54:21.722667 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4401 22:54:21.729232 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 22:54:21.732894 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 22:54:21.735803 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4404 22:54:21.742528 0 9 12 | B1->B0 | 2e2e 2828 | 0 0 | (0 1) (1 0)
4405 22:54:21.749730 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 22:54:21.750145 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 22:54:21.755781 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 22:54:21.759053 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 22:54:21.762319 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 22:54:21.769270 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 22:54:21.772426 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 22:54:21.775861 0 10 12 | B1->B0 | 3737 3b3b | 0 0 | (0 0) (0 0)
4413 22:54:21.779081 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 22:54:21.785578 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 22:54:21.788921 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 22:54:21.792624 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 22:54:21.799221 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 22:54:21.801969 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 22:54:21.805467 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 22:54:21.811857 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4421 22:54:21.815317 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 22:54:21.818820 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 22:54:21.825348 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 22:54:21.828620 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 22:54:21.831937 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 22:54:21.838383 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 22:54:21.841631 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 22:54:21.844992 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 22:54:21.851867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 22:54:21.855446 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 22:54:21.858441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 22:54:21.865724 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 22:54:21.868417 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 22:54:21.871759 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 22:54:21.878692 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 22:54:21.881970 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4437 22:54:21.885208 Total UI for P1: 0, mck2ui 16
4438 22:54:21.888435 best dqsien dly found for B0: ( 0, 13, 10)
4439 22:54:21.891875 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 22:54:21.895303 Total UI for P1: 0, mck2ui 16
4441 22:54:21.898704 best dqsien dly found for B1: ( 0, 13, 12)
4442 22:54:21.902113 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4443 22:54:21.905371 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4444 22:54:21.905489
4445 22:54:21.908122 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4446 22:54:21.914973 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4447 22:54:21.915130 [Gating] SW calibration Done
4448 22:54:21.915235 ==
4449 22:54:21.918176 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 22:54:21.925138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 22:54:21.925225 ==
4452 22:54:21.925291 RX Vref Scan: 0
4453 22:54:21.925366
4454 22:54:21.928683 RX Vref 0 -> 0, step: 1
4455 22:54:21.928766
4456 22:54:21.931554 RX Delay -230 -> 252, step: 16
4457 22:54:21.934714 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4458 22:54:21.938301 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4459 22:54:21.944641 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4460 22:54:21.948091 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4461 22:54:21.951469 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4462 22:54:21.954934 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4463 22:54:21.958140 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4464 22:54:21.964959 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4465 22:54:21.968543 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4466 22:54:21.971828 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4467 22:54:21.974947 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4468 22:54:21.981649 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4469 22:54:21.984616 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4470 22:54:21.988735 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4471 22:54:21.991803 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4472 22:54:21.998716 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4473 22:54:21.998842 ==
4474 22:54:22.002243 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 22:54:22.005422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 22:54:22.005526 ==
4477 22:54:22.005609 DQS Delay:
4478 22:54:22.008646 DQS0 = 0, DQS1 = 0
4479 22:54:22.008795 DQM Delay:
4480 22:54:22.012225 DQM0 = 52, DQM1 = 49
4481 22:54:22.012642 DQ Delay:
4482 22:54:22.015571 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4483 22:54:22.018976 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4484 22:54:22.022147 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4485 22:54:22.025223 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4486 22:54:22.025638
4487 22:54:22.025968
4488 22:54:22.026275 ==
4489 22:54:22.028433 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 22:54:22.031845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 22:54:22.032285 ==
4492 22:54:22.032619
4493 22:54:22.032926
4494 22:54:22.035392 TX Vref Scan disable
4495 22:54:22.038582 == TX Byte 0 ==
4496 22:54:22.042064 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4497 22:54:22.045175 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4498 22:54:22.048534 == TX Byte 1 ==
4499 22:54:22.052128 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4500 22:54:22.055601 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4501 22:54:22.056060 ==
4502 22:54:22.058686 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 22:54:22.065323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 22:54:22.065944 ==
4505 22:54:22.066418
4506 22:54:22.066914
4507 22:54:22.067341 TX Vref Scan disable
4508 22:54:22.068851 == TX Byte 0 ==
4509 22:54:22.072471 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4510 22:54:22.075766 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4511 22:54:22.079163 == TX Byte 1 ==
4512 22:54:22.082701 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4513 22:54:22.086104 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4514 22:54:22.089630
4515 22:54:22.090066 [DATLAT]
4516 22:54:22.090395 Freq=600, CH1 RK0
4517 22:54:22.090705
4518 22:54:22.092377 DATLAT Default: 0x9
4519 22:54:22.092794 0, 0xFFFF, sum = 0
4520 22:54:22.096087 1, 0xFFFF, sum = 0
4521 22:54:22.096507 2, 0xFFFF, sum = 0
4522 22:54:22.099336 3, 0xFFFF, sum = 0
4523 22:54:22.099854 4, 0xFFFF, sum = 0
4524 22:54:22.102736 5, 0xFFFF, sum = 0
4525 22:54:22.103343 6, 0xFFFF, sum = 0
4526 22:54:22.105975 7, 0xFFFF, sum = 0
4527 22:54:22.106429 8, 0x0, sum = 1
4528 22:54:22.109425 9, 0x0, sum = 2
4529 22:54:22.109893 10, 0x0, sum = 3
4530 22:54:22.112661 11, 0x0, sum = 4
4531 22:54:22.113080 best_step = 9
4532 22:54:22.113410
4533 22:54:22.113712 ==
4534 22:54:22.116295 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 22:54:22.122747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 22:54:22.123161 ==
4537 22:54:22.123492 RX Vref Scan: 1
4538 22:54:22.123798
4539 22:54:22.126097 RX Vref 0 -> 0, step: 1
4540 22:54:22.126550
4541 22:54:22.129436 RX Delay -147 -> 252, step: 8
4542 22:54:22.129848
4543 22:54:22.132888 Set Vref, RX VrefLevel [Byte0]: 53
4544 22:54:22.135790 [Byte1]: 53
4545 22:54:22.136241
4546 22:54:22.139253 Final RX Vref Byte 0 = 53 to rank0
4547 22:54:22.142247 Final RX Vref Byte 1 = 53 to rank0
4548 22:54:22.145817 Final RX Vref Byte 0 = 53 to rank1
4549 22:54:22.149463 Final RX Vref Byte 1 = 53 to rank1==
4550 22:54:22.152036 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 22:54:22.155487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 22:54:22.155951 ==
4553 22:54:22.158684 DQS Delay:
4554 22:54:22.159099 DQS0 = 0, DQS1 = 0
4555 22:54:22.159423 DQM Delay:
4556 22:54:22.162080 DQM0 = 48, DQM1 = 45
4557 22:54:22.162492 DQ Delay:
4558 22:54:22.165588 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4559 22:54:22.168801 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4560 22:54:22.172119 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4561 22:54:22.176071 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4562 22:54:22.176539
4563 22:54:22.176881
4564 22:54:22.185797 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4565 22:54:22.186361 CH1 RK0: MR19=808, MR18=4B71
4566 22:54:22.192388 CH1_RK0: MR19=0x808, MR18=0x4B71, DQSOSC=388, MR23=63, INC=174, DEC=116
4567 22:54:22.192805
4568 22:54:22.195489 ----->DramcWriteLeveling(PI) begin...
4569 22:54:22.198900 ==
4570 22:54:22.199314 Dram Type= 6, Freq= 0, CH_1, rank 1
4571 22:54:22.206009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 22:54:22.206551 ==
4573 22:54:22.208644 Write leveling (Byte 0): 30 => 30
4574 22:54:22.212453 Write leveling (Byte 1): 30 => 30
4575 22:54:22.215386 DramcWriteLeveling(PI) end<-----
4576 22:54:22.215903
4577 22:54:22.216277 ==
4578 22:54:22.218624 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 22:54:22.222249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 22:54:22.222696 ==
4581 22:54:22.225193 [Gating] SW mode calibration
4582 22:54:22.232247 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4583 22:54:22.235306 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4584 22:54:22.241741 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 22:54:22.245288 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4586 22:54:22.248293 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4587 22:54:22.255596 0 9 12 | B1->B0 | 2e2e 3030 | 1 0 | (1 0) (0 0)
4588 22:54:22.258663 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 22:54:22.262233 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 22:54:22.268679 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 22:54:22.272328 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 22:54:22.275230 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 22:54:22.281969 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 22:54:22.285349 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 22:54:22.288860 0 10 12 | B1->B0 | 3939 3535 | 1 1 | (0 0) (0 0)
4596 22:54:22.295114 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4597 22:54:22.298733 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 22:54:22.301806 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 22:54:22.308533 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 22:54:22.311921 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 22:54:22.315049 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 22:54:22.322108 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 22:54:22.324800 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4604 22:54:22.327841 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 22:54:22.334921 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 22:54:22.338329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 22:54:22.341606 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 22:54:22.348250 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 22:54:22.351832 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 22:54:22.354776 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 22:54:22.361360 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 22:54:22.364772 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 22:54:22.368149 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 22:54:22.374507 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 22:54:22.378190 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 22:54:22.381454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 22:54:22.387950 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 22:54:22.390836 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4619 22:54:22.393903 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 22:54:22.397930 Total UI for P1: 0, mck2ui 16
4621 22:54:22.401101 best dqsien dly found for B0: ( 0, 13, 10)
4622 22:54:22.404306 Total UI for P1: 0, mck2ui 16
4623 22:54:22.407489 best dqsien dly found for B1: ( 0, 13, 8)
4624 22:54:22.410858 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4625 22:54:22.414230 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4626 22:54:22.414830
4627 22:54:22.417653 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4628 22:54:22.424458 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4629 22:54:22.424870 [Gating] SW calibration Done
4630 22:54:22.425199 ==
4631 22:54:22.427927 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 22:54:22.434521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 22:54:22.435067 ==
4634 22:54:22.435605 RX Vref Scan: 0
4635 22:54:22.436139
4636 22:54:22.437889 RX Vref 0 -> 0, step: 1
4637 22:54:22.438501
4638 22:54:22.440329 RX Delay -230 -> 252, step: 16
4639 22:54:22.444253 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4640 22:54:22.447207 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4641 22:54:22.453729 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4642 22:54:22.457353 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4643 22:54:22.460157 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4644 22:54:22.463353 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4645 22:54:22.467395 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4646 22:54:22.473387 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4647 22:54:22.476959 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4648 22:54:22.480242 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4649 22:54:22.483810 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4650 22:54:22.490382 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4651 22:54:22.493772 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4652 22:54:22.497087 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4653 22:54:22.500237 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4654 22:54:22.506835 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4655 22:54:22.507269 ==
4656 22:54:22.510202 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 22:54:22.513397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 22:54:22.513965 ==
4659 22:54:22.514550 DQS Delay:
4660 22:54:22.516763 DQS0 = 0, DQS1 = 0
4661 22:54:22.517441 DQM Delay:
4662 22:54:22.520367 DQM0 = 52, DQM1 = 48
4663 22:54:22.520785 DQ Delay:
4664 22:54:22.523793 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4665 22:54:22.526639 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4666 22:54:22.530055 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4667 22:54:22.533702 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4668 22:54:22.534220
4669 22:54:22.534550
4670 22:54:22.534855 ==
4671 22:54:22.536549 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 22:54:22.539999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 22:54:22.540424 ==
4674 22:54:22.540781
4675 22:54:22.541089
4676 22:54:22.543423 TX Vref Scan disable
4677 22:54:22.546920 == TX Byte 0 ==
4678 22:54:22.550200 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4679 22:54:22.553550 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4680 22:54:22.556781 == TX Byte 1 ==
4681 22:54:22.559793 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4682 22:54:22.563548 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4683 22:54:22.564110 ==
4684 22:54:22.566920 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 22:54:22.573447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 22:54:22.573898 ==
4687 22:54:22.574234
4688 22:54:22.574539
4689 22:54:22.574833 TX Vref Scan disable
4690 22:54:22.577360 == TX Byte 0 ==
4691 22:54:22.581275 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4692 22:54:22.584251 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4693 22:54:22.587703 == TX Byte 1 ==
4694 22:54:22.590735 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4695 22:54:22.597540 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4696 22:54:22.598058
4697 22:54:22.598411 [DATLAT]
4698 22:54:22.598756 Freq=600, CH1 RK1
4699 22:54:22.599057
4700 22:54:22.600869 DATLAT Default: 0x9
4701 22:54:22.601281 0, 0xFFFF, sum = 0
4702 22:54:22.604412 1, 0xFFFF, sum = 0
4703 22:54:22.604836 2, 0xFFFF, sum = 0
4704 22:54:22.607886 3, 0xFFFF, sum = 0
4705 22:54:22.608499 4, 0xFFFF, sum = 0
4706 22:54:22.611106 5, 0xFFFF, sum = 0
4707 22:54:22.614011 6, 0xFFFF, sum = 0
4708 22:54:22.614440 7, 0xFFFF, sum = 0
4709 22:54:22.614781 8, 0x0, sum = 1
4710 22:54:22.617137 9, 0x0, sum = 2
4711 22:54:22.617561 10, 0x0, sum = 3
4712 22:54:22.620804 11, 0x0, sum = 4
4713 22:54:22.621324 best_step = 9
4714 22:54:22.621663
4715 22:54:22.621974 ==
4716 22:54:22.624045 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 22:54:22.630649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 22:54:22.631094 ==
4719 22:54:22.631438 RX Vref Scan: 0
4720 22:54:22.631811
4721 22:54:22.634017 RX Vref 0 -> 0, step: 1
4722 22:54:22.634437
4723 22:54:22.637128 RX Delay -163 -> 252, step: 8
4724 22:54:22.640486 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4725 22:54:22.647545 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4726 22:54:22.651012 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4727 22:54:22.654235 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4728 22:54:22.657663 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4729 22:54:22.660660 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4730 22:54:22.667430 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4731 22:54:22.670756 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4732 22:54:22.674710 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4733 22:54:22.677091 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4734 22:54:22.680843 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4735 22:54:22.687200 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4736 22:54:22.691371 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4737 22:54:22.694492 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4738 22:54:22.697746 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4739 22:54:22.700883 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4740 22:54:22.704430 ==
4741 22:54:22.704991 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 22:54:22.710844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 22:54:22.711407 ==
4744 22:54:22.711778 DQS Delay:
4745 22:54:22.713972 DQS0 = 0, DQS1 = 0
4746 22:54:22.714423 DQM Delay:
4747 22:54:22.717533 DQM0 = 48, DQM1 = 45
4748 22:54:22.718090 DQ Delay:
4749 22:54:22.720613 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4750 22:54:22.723851 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4751 22:54:22.726910 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4752 22:54:22.730162 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4753 22:54:22.730580
4754 22:54:22.730916
4755 22:54:22.737549 [DQSOSCAuto] RK1, (LSB)MR18= 0x671c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4756 22:54:22.740232 CH1 RK1: MR19=808, MR18=671C
4757 22:54:22.746759 CH1_RK1: MR19=0x808, MR18=0x671C, DQSOSC=390, MR23=63, INC=172, DEC=114
4758 22:54:22.750104 [RxdqsGatingPostProcess] freq 600
4759 22:54:22.756780 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4760 22:54:22.760304 Pre-setting of DQS Precalculation
4761 22:54:22.763688 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4762 22:54:22.769947 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4763 22:54:22.776239 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4764 22:54:22.776688
4765 22:54:22.777022
4766 22:54:22.779808 [Calibration Summary] 1200 Mbps
4767 22:54:22.782896 CH 0, Rank 0
4768 22:54:22.783309 SW Impedance : PASS
4769 22:54:22.786207 DUTY Scan : NO K
4770 22:54:22.790206 ZQ Calibration : PASS
4771 22:54:22.790674 Jitter Meter : NO K
4772 22:54:22.792684 CBT Training : PASS
4773 22:54:22.796185 Write leveling : PASS
4774 22:54:22.796603 RX DQS gating : PASS
4775 22:54:22.800174 RX DQ/DQS(RDDQC) : PASS
4776 22:54:22.803007 TX DQ/DQS : PASS
4777 22:54:22.803426 RX DATLAT : PASS
4778 22:54:22.806613 RX DQ/DQS(Engine): PASS
4779 22:54:22.807033 TX OE : NO K
4780 22:54:22.809965 All Pass.
4781 22:54:22.810377
4782 22:54:22.810706 CH 0, Rank 1
4783 22:54:22.813333 SW Impedance : PASS
4784 22:54:22.813750 DUTY Scan : NO K
4785 22:54:22.816766 ZQ Calibration : PASS
4786 22:54:22.819450 Jitter Meter : NO K
4787 22:54:22.819869 CBT Training : PASS
4788 22:54:22.822967 Write leveling : PASS
4789 22:54:22.826360 RX DQS gating : PASS
4790 22:54:22.826775 RX DQ/DQS(RDDQC) : PASS
4791 22:54:22.829977 TX DQ/DQS : PASS
4792 22:54:22.833081 RX DATLAT : PASS
4793 22:54:22.833593 RX DQ/DQS(Engine): PASS
4794 22:54:22.836576 TX OE : NO K
4795 22:54:22.837096 All Pass.
4796 22:54:22.837431
4797 22:54:22.839610 CH 1, Rank 0
4798 22:54:22.840056 SW Impedance : PASS
4799 22:54:22.843649 DUTY Scan : NO K
4800 22:54:22.846400 ZQ Calibration : PASS
4801 22:54:22.846909 Jitter Meter : NO K
4802 22:54:22.849516 CBT Training : PASS
4803 22:54:22.852971 Write leveling : PASS
4804 22:54:22.853447 RX DQS gating : PASS
4805 22:54:22.856638 RX DQ/DQS(RDDQC) : PASS
4806 22:54:22.857150 TX DQ/DQS : PASS
4807 22:54:22.859567 RX DATLAT : PASS
4808 22:54:22.863033 RX DQ/DQS(Engine): PASS
4809 22:54:22.863552 TX OE : NO K
4810 22:54:22.866337 All Pass.
4811 22:54:22.866848
4812 22:54:22.867184 CH 1, Rank 1
4813 22:54:22.869514 SW Impedance : PASS
4814 22:54:22.869935 DUTY Scan : NO K
4815 22:54:22.873266 ZQ Calibration : PASS
4816 22:54:22.876329 Jitter Meter : NO K
4817 22:54:22.876795 CBT Training : PASS
4818 22:54:22.879868 Write leveling : PASS
4819 22:54:22.882933 RX DQS gating : PASS
4820 22:54:22.883344 RX DQ/DQS(RDDQC) : PASS
4821 22:54:22.886167 TX DQ/DQS : PASS
4822 22:54:22.889732 RX DATLAT : PASS
4823 22:54:22.890262 RX DQ/DQS(Engine): PASS
4824 22:54:22.893114 TX OE : NO K
4825 22:54:22.893532 All Pass.
4826 22:54:22.893860
4827 22:54:22.895815 DramC Write-DBI off
4828 22:54:22.899320 PER_BANK_REFRESH: Hybrid Mode
4829 22:54:22.899935 TX_TRACKING: ON
4830 22:54:22.910110 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4831 22:54:22.912857 [FAST_K] Save calibration result to emmc
4832 22:54:22.916082 dramc_set_vcore_voltage set vcore to 662500
4833 22:54:22.919310 Read voltage for 933, 3
4834 22:54:22.919744 Vio18 = 0
4835 22:54:22.920142 Vcore = 662500
4836 22:54:22.922940 Vdram = 0
4837 22:54:22.923372 Vddq = 0
4838 22:54:22.923812 Vmddr = 0
4839 22:54:22.929842 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4840 22:54:22.932497 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4841 22:54:22.936326 MEM_TYPE=3, freq_sel=17
4842 22:54:22.939546 sv_algorithm_assistance_LP4_1600
4843 22:54:22.942615 ============ PULL DRAM RESETB DOWN ============
4844 22:54:22.946441 ========== PULL DRAM RESETB DOWN end =========
4845 22:54:22.952394 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4846 22:54:22.956164 ===================================
4847 22:54:22.956686 LPDDR4 DRAM CONFIGURATION
4848 22:54:22.959255 ===================================
4849 22:54:22.962622 EX_ROW_EN[0] = 0x0
4850 22:54:22.965554 EX_ROW_EN[1] = 0x0
4851 22:54:22.966138 LP4Y_EN = 0x0
4852 22:54:22.969052 WORK_FSP = 0x0
4853 22:54:22.969655 WL = 0x3
4854 22:54:22.972618 RL = 0x3
4855 22:54:22.973029 BL = 0x2
4856 22:54:22.976108 RPST = 0x0
4857 22:54:22.976561 RD_PRE = 0x0
4858 22:54:22.979359 WR_PRE = 0x1
4859 22:54:22.980008 WR_PST = 0x0
4860 22:54:22.982591 DBI_WR = 0x0
4861 22:54:22.983014 DBI_RD = 0x0
4862 22:54:22.985671 OTF = 0x1
4863 22:54:22.988883 ===================================
4864 22:54:22.992464 ===================================
4865 22:54:22.992896 ANA top config
4866 22:54:22.995536 ===================================
4867 22:54:22.999083 DLL_ASYNC_EN = 0
4868 22:54:23.002546 ALL_SLAVE_EN = 1
4869 22:54:23.006468 NEW_RANK_MODE = 1
4870 22:54:23.006988 DLL_IDLE_MODE = 1
4871 22:54:23.008886 LP45_APHY_COMB_EN = 1
4872 22:54:23.012214 TX_ODT_DIS = 1
4873 22:54:23.016079 NEW_8X_MODE = 1
4874 22:54:23.019037 ===================================
4875 22:54:23.022383 ===================================
4876 22:54:23.025731 data_rate = 1866
4877 22:54:23.026169 CKR = 1
4878 22:54:23.028888 DQ_P2S_RATIO = 8
4879 22:54:23.032076 ===================================
4880 22:54:23.035441 CA_P2S_RATIO = 8
4881 22:54:23.038557 DQ_CA_OPEN = 0
4882 22:54:23.041951 DQ_SEMI_OPEN = 0
4883 22:54:23.042374 CA_SEMI_OPEN = 0
4884 22:54:23.045427 CA_FULL_RATE = 0
4885 22:54:23.048896 DQ_CKDIV4_EN = 1
4886 22:54:23.052467 CA_CKDIV4_EN = 1
4887 22:54:23.055597 CA_PREDIV_EN = 0
4888 22:54:23.058918 PH8_DLY = 0
4889 22:54:23.059340 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4890 22:54:23.062440 DQ_AAMCK_DIV = 4
4891 22:54:23.065333 CA_AAMCK_DIV = 4
4892 22:54:23.068573 CA_ADMCK_DIV = 4
4893 22:54:23.072056 DQ_TRACK_CA_EN = 0
4894 22:54:23.075348 CA_PICK = 933
4895 22:54:23.078561 CA_MCKIO = 933
4896 22:54:23.078943 MCKIO_SEMI = 0
4897 22:54:23.081964 PLL_FREQ = 3732
4898 22:54:23.085462 DQ_UI_PI_RATIO = 32
4899 22:54:23.088355 CA_UI_PI_RATIO = 0
4900 22:54:23.092293 ===================================
4901 22:54:23.095615 ===================================
4902 22:54:23.098827 memory_type:LPDDR4
4903 22:54:23.099345 GP_NUM : 10
4904 22:54:23.102170 SRAM_EN : 1
4905 22:54:23.105073 MD32_EN : 0
4906 22:54:23.108398 ===================================
4907 22:54:23.108807 [ANA_INIT] >>>>>>>>>>>>>>
4908 22:54:23.112279 <<<<<< [CONFIGURE PHASE]: ANA_TX
4909 22:54:23.115046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4910 22:54:23.118300 ===================================
4911 22:54:23.121759 data_rate = 1866,PCW = 0X8f00
4912 22:54:23.125203 ===================================
4913 22:54:23.128607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4914 22:54:23.135093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 22:54:23.138492 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4916 22:54:23.145088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4917 22:54:23.149025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4918 22:54:23.151933 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4919 22:54:23.152351 [ANA_INIT] flow start
4920 22:54:23.155127 [ANA_INIT] PLL >>>>>>>>
4921 22:54:23.158927 [ANA_INIT] PLL <<<<<<<<
4922 22:54:23.159586 [ANA_INIT] MIDPI >>>>>>>>
4923 22:54:23.161784 [ANA_INIT] MIDPI <<<<<<<<
4924 22:54:23.165367 [ANA_INIT] DLL >>>>>>>>
4925 22:54:23.165881 [ANA_INIT] flow end
4926 22:54:23.172380 ============ LP4 DIFF to SE enter ============
4927 22:54:23.175297 ============ LP4 DIFF to SE exit ============
4928 22:54:23.178462 [ANA_INIT] <<<<<<<<<<<<<
4929 22:54:23.181679 [Flow] Enable top DCM control >>>>>
4930 22:54:23.184827 [Flow] Enable top DCM control <<<<<
4931 22:54:23.185278 Enable DLL master slave shuffle
4932 22:54:23.192004 ==============================================================
4933 22:54:23.195050 Gating Mode config
4934 22:54:23.198260 ==============================================================
4935 22:54:23.201991 Config description:
4936 22:54:23.211460 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4937 22:54:23.218475 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4938 22:54:23.221674 SELPH_MODE 0: By rank 1: By Phase
4939 22:54:23.228627 ==============================================================
4940 22:54:23.231164 GAT_TRACK_EN = 1
4941 22:54:23.234612 RX_GATING_MODE = 2
4942 22:54:23.237982 RX_GATING_TRACK_MODE = 2
4943 22:54:23.241245 SELPH_MODE = 1
4944 22:54:23.241665 PICG_EARLY_EN = 1
4945 22:54:23.244470 VALID_LAT_VALUE = 1
4946 22:54:23.251398 ==============================================================
4947 22:54:23.254925 Enter into Gating configuration >>>>
4948 22:54:23.258369 Exit from Gating configuration <<<<
4949 22:54:23.261191 Enter into DVFS_PRE_config >>>>>
4950 22:54:23.271584 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4951 22:54:23.274706 Exit from DVFS_PRE_config <<<<<
4952 22:54:23.278026 Enter into PICG configuration >>>>
4953 22:54:23.281307 Exit from PICG configuration <<<<
4954 22:54:23.284905 [RX_INPUT] configuration >>>>>
4955 22:54:23.288221 [RX_INPUT] configuration <<<<<
4956 22:54:23.291375 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4957 22:54:23.297926 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4958 22:54:23.304551 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4959 22:54:23.311069 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4960 22:54:23.317601 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4961 22:54:23.320821 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4962 22:54:23.327771 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4963 22:54:23.330833 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4964 22:54:23.333953 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4965 22:54:23.337114 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4966 22:54:23.344165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4967 22:54:23.347510 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4968 22:54:23.351090 ===================================
4969 22:54:23.353908 LPDDR4 DRAM CONFIGURATION
4970 22:54:23.357365 ===================================
4971 22:54:23.357916 EX_ROW_EN[0] = 0x0
4972 22:54:23.360802 EX_ROW_EN[1] = 0x0
4973 22:54:23.361233 LP4Y_EN = 0x0
4974 22:54:23.364198 WORK_FSP = 0x0
4975 22:54:23.364614 WL = 0x3
4976 22:54:23.367549 RL = 0x3
4977 22:54:23.368145 BL = 0x2
4978 22:54:23.371058 RPST = 0x0
4979 22:54:23.371467 RD_PRE = 0x0
4980 22:54:23.374148 WR_PRE = 0x1
4981 22:54:23.377309 WR_PST = 0x0
4982 22:54:23.377858 DBI_WR = 0x0
4983 22:54:23.381026 DBI_RD = 0x0
4984 22:54:23.381443 OTF = 0x1
4985 22:54:23.384209 ===================================
4986 22:54:23.387884 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4987 22:54:23.391092 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4988 22:54:23.397384 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 22:54:23.400890 ===================================
4990 22:54:23.404186 LPDDR4 DRAM CONFIGURATION
4991 22:54:23.407812 ===================================
4992 22:54:23.408362 EX_ROW_EN[0] = 0x10
4993 22:54:23.410668 EX_ROW_EN[1] = 0x0
4994 22:54:23.411078 LP4Y_EN = 0x0
4995 22:54:23.414767 WORK_FSP = 0x0
4996 22:54:23.415285 WL = 0x3
4997 22:54:23.417683 RL = 0x3
4998 22:54:23.418143 BL = 0x2
4999 22:54:23.420940 RPST = 0x0
5000 22:54:23.421444 RD_PRE = 0x0
5001 22:54:23.424375 WR_PRE = 0x1
5002 22:54:23.424786 WR_PST = 0x0
5003 22:54:23.427743 DBI_WR = 0x0
5004 22:54:23.428197 DBI_RD = 0x0
5005 22:54:23.431506 OTF = 0x1
5006 22:54:23.433892 ===================================
5007 22:54:23.440513 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5008 22:54:23.443851 nWR fixed to 30
5009 22:54:23.447576 [ModeRegInit_LP4] CH0 RK0
5010 22:54:23.448049 [ModeRegInit_LP4] CH0 RK1
5011 22:54:23.450672 [ModeRegInit_LP4] CH1 RK0
5012 22:54:23.454206 [ModeRegInit_LP4] CH1 RK1
5013 22:54:23.454612 match AC timing 9
5014 22:54:23.460612 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5015 22:54:23.464225 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5016 22:54:23.467663 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5017 22:54:23.474220 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5018 22:54:23.477267 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5019 22:54:23.477695 ==
5020 22:54:23.480810 Dram Type= 6, Freq= 0, CH_0, rank 0
5021 22:54:23.483720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5022 22:54:23.484181 ==
5023 22:54:23.490973 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5024 22:54:23.497019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5025 22:54:23.500952 [CA 0] Center 37 (6~68) winsize 63
5026 22:54:23.504122 [CA 1] Center 37 (7~68) winsize 62
5027 22:54:23.507613 [CA 2] Center 34 (4~65) winsize 62
5028 22:54:23.510527 [CA 3] Center 34 (3~65) winsize 63
5029 22:54:23.514428 [CA 4] Center 33 (3~64) winsize 62
5030 22:54:23.516975 [CA 5] Center 32 (2~62) winsize 61
5031 22:54:23.517432
5032 22:54:23.520202 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5033 22:54:23.520691
5034 22:54:23.523799 [CATrainingPosCal] consider 1 rank data
5035 22:54:23.526778 u2DelayCellTimex100 = 270/100 ps
5036 22:54:23.529980 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5037 22:54:23.533266 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5038 22:54:23.536814 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5039 22:54:23.540070 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5040 22:54:23.543714 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5041 22:54:23.547419 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5042 22:54:23.550544
5043 22:54:23.554072 CA PerBit enable=1, Macro0, CA PI delay=32
5044 22:54:23.554705
5045 22:54:23.557167 [CBTSetCACLKResult] CA Dly = 32
5046 22:54:23.557682 CS Dly: 5 (0~36)
5047 22:54:23.558054 ==
5048 22:54:23.560250 Dram Type= 6, Freq= 0, CH_0, rank 1
5049 22:54:23.563945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5050 22:54:23.564538 ==
5051 22:54:23.570361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5052 22:54:23.577216 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5053 22:54:23.580209 [CA 0] Center 37 (7~68) winsize 62
5054 22:54:23.583917 [CA 1] Center 36 (6~67) winsize 62
5055 22:54:23.586996 [CA 2] Center 34 (4~65) winsize 62
5056 22:54:23.590064 [CA 3] Center 34 (3~65) winsize 63
5057 22:54:23.593505 [CA 4] Center 32 (2~63) winsize 62
5058 22:54:23.596937 [CA 5] Center 32 (2~62) winsize 61
5059 22:54:23.597464
5060 22:54:23.600077 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5061 22:54:23.600676
5062 22:54:23.603154 [CATrainingPosCal] consider 2 rank data
5063 22:54:23.606375 u2DelayCellTimex100 = 270/100 ps
5064 22:54:23.609604 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5065 22:54:23.613277 CA1 delay=37 (7~67),Diff = 5 PI (31 cell)
5066 22:54:23.616552 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5067 22:54:23.619794 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5068 22:54:23.626509 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5069 22:54:23.629845 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5070 22:54:23.630306
5071 22:54:23.632969 CA PerBit enable=1, Macro0, CA PI delay=32
5072 22:54:23.633476
5073 22:54:23.636766 [CBTSetCACLKResult] CA Dly = 32
5074 22:54:23.637183 CS Dly: 5 (0~37)
5075 22:54:23.637544
5076 22:54:23.639771 ----->DramcWriteLeveling(PI) begin...
5077 22:54:23.640383 ==
5078 22:54:23.643240 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 22:54:23.649714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 22:54:23.650273 ==
5081 22:54:23.652588 Write leveling (Byte 0): 31 => 31
5082 22:54:23.656209 Write leveling (Byte 1): 30 => 30
5083 22:54:23.656771 DramcWriteLeveling(PI) end<-----
5084 22:54:23.657171
5085 22:54:23.659763 ==
5086 22:54:23.662749 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 22:54:23.666483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 22:54:23.666899 ==
5089 22:54:23.669767 [Gating] SW mode calibration
5090 22:54:23.676640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5091 22:54:23.680097 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5092 22:54:23.686431 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
5093 22:54:23.689416 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 22:54:23.692611 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 22:54:23.699756 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 22:54:23.702986 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 22:54:23.706395 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 22:54:23.712534 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5099 22:54:23.716087 0 14 28 | B1->B0 | 3333 2424 | 0 0 | (0 0) (1 0)
5100 22:54:23.719196 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5101 22:54:23.726538 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 22:54:23.729061 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 22:54:23.732754 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 22:54:23.739664 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 22:54:23.742535 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 22:54:23.745731 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5107 22:54:23.749159 0 15 28 | B1->B0 | 2626 3939 | 0 0 | (0 0) (0 0)
5108 22:54:23.755731 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5109 22:54:23.759369 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 22:54:23.762584 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 22:54:23.769334 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 22:54:23.772753 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 22:54:23.776019 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 22:54:23.782823 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5115 22:54:23.786160 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5116 22:54:23.789077 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5117 22:54:23.796095 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 22:54:23.799273 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 22:54:23.802497 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 22:54:23.809316 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 22:54:23.812050 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 22:54:23.815665 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 22:54:23.822755 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 22:54:23.825456 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 22:54:23.828889 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 22:54:23.835786 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 22:54:23.839107 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 22:54:23.841964 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 22:54:23.848630 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 22:54:23.852084 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5131 22:54:23.855492 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5132 22:54:23.862005 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5133 22:54:23.862479 Total UI for P1: 0, mck2ui 16
5134 22:54:23.868635 best dqsien dly found for B0: ( 1, 2, 26)
5135 22:54:23.872089 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 22:54:23.875294 Total UI for P1: 0, mck2ui 16
5137 22:54:23.878596 best dqsien dly found for B1: ( 1, 3, 0)
5138 22:54:23.881669 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5139 22:54:23.885129 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5140 22:54:23.885546
5141 22:54:23.888423 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5142 22:54:23.891847 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5143 22:54:23.895346 [Gating] SW calibration Done
5144 22:54:23.895761 ==
5145 22:54:23.898976 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 22:54:23.902203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 22:54:23.902621 ==
5148 22:54:23.905524 RX Vref Scan: 0
5149 22:54:23.905940
5150 22:54:23.908679 RX Vref 0 -> 0, step: 1
5151 22:54:23.909095
5152 22:54:23.909426 RX Delay -80 -> 252, step: 8
5153 22:54:23.915056 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5154 22:54:23.918232 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5155 22:54:23.921732 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5156 22:54:23.925082 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5157 22:54:23.928574 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5158 22:54:23.932026 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5159 22:54:23.938230 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5160 22:54:23.942218 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5161 22:54:23.945324 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5162 22:54:23.948588 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5163 22:54:23.951403 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5164 22:54:23.958056 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5165 22:54:23.961460 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5166 22:54:23.964599 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5167 22:54:23.968036 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5168 22:54:23.971731 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5169 22:54:23.971813 ==
5170 22:54:23.974945 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 22:54:23.981358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 22:54:23.981442 ==
5173 22:54:23.981508 DQS Delay:
5174 22:54:23.981570 DQS0 = 0, DQS1 = 0
5175 22:54:23.984543 DQM Delay:
5176 22:54:23.984626 DQM0 = 105, DQM1 = 94
5177 22:54:23.987773 DQ Delay:
5178 22:54:23.991293 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5179 22:54:23.994862 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5180 22:54:23.998023 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5181 22:54:24.001086 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5182 22:54:24.001191
5183 22:54:24.001284
5184 22:54:24.001373 ==
5185 22:54:24.004453 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 22:54:24.007915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 22:54:24.008008 ==
5188 22:54:24.008075
5189 22:54:24.008136
5190 22:54:24.011239 TX Vref Scan disable
5191 22:54:24.014922 == TX Byte 0 ==
5192 22:54:24.018070 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5193 22:54:24.021641 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5194 22:54:24.024699 == TX Byte 1 ==
5195 22:54:24.027773 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5196 22:54:24.031236 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5197 22:54:24.031363 ==
5198 22:54:24.034736 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 22:54:24.041020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 22:54:24.041183 ==
5201 22:54:24.041335
5202 22:54:24.041490
5203 22:54:24.041638 TX Vref Scan disable
5204 22:54:24.044814 == TX Byte 0 ==
5205 22:54:24.048152 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5206 22:54:24.051874 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5207 22:54:24.055197 == TX Byte 1 ==
5208 22:54:24.057979 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5209 22:54:24.065006 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5210 22:54:24.065338
5211 22:54:24.065551 [DATLAT]
5212 22:54:24.065746 Freq=933, CH0 RK0
5213 22:54:24.065992
5214 22:54:24.068469 DATLAT Default: 0xd
5215 22:54:24.068727 0, 0xFFFF, sum = 0
5216 22:54:24.071208 1, 0xFFFF, sum = 0
5217 22:54:24.071474 2, 0xFFFF, sum = 0
5218 22:54:24.074653 3, 0xFFFF, sum = 0
5219 22:54:24.078079 4, 0xFFFF, sum = 0
5220 22:54:24.078441 5, 0xFFFF, sum = 0
5221 22:54:24.081431 6, 0xFFFF, sum = 0
5222 22:54:24.081743 7, 0xFFFF, sum = 0
5223 22:54:24.084867 8, 0xFFFF, sum = 0
5224 22:54:24.085203 9, 0xFFFF, sum = 0
5225 22:54:24.088025 10, 0x0, sum = 1
5226 22:54:24.088395 11, 0x0, sum = 2
5227 22:54:24.088679 12, 0x0, sum = 3
5228 22:54:24.091627 13, 0x0, sum = 4
5229 22:54:24.091896 best_step = 11
5230 22:54:24.092194
5231 22:54:24.095213 ==
5232 22:54:24.095514 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 22:54:24.101365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 22:54:24.101720 ==
5235 22:54:24.102044 RX Vref Scan: 1
5236 22:54:24.102315
5237 22:54:24.104720 RX Vref 0 -> 0, step: 1
5238 22:54:24.104991
5239 22:54:24.107880 RX Delay -53 -> 252, step: 4
5240 22:54:24.108249
5241 22:54:24.111391 Set Vref, RX VrefLevel [Byte0]: 56
5242 22:54:24.114765 [Byte1]: 48
5243 22:54:24.115021
5244 22:54:24.118171 Final RX Vref Byte 0 = 56 to rank0
5245 22:54:24.121110 Final RX Vref Byte 1 = 48 to rank0
5246 22:54:24.124395 Final RX Vref Byte 0 = 56 to rank1
5247 22:54:24.127615 Final RX Vref Byte 1 = 48 to rank1==
5248 22:54:24.131356 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 22:54:24.134861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 22:54:24.135209 ==
5251 22:54:24.137620 DQS Delay:
5252 22:54:24.137979 DQS0 = 0, DQS1 = 0
5253 22:54:24.141674 DQM Delay:
5254 22:54:24.141930 DQM0 = 104, DQM1 = 95
5255 22:54:24.142135 DQ Delay:
5256 22:54:24.144713 DQ0 =104, DQ1 =104, DQ2 =104, DQ3 =102
5257 22:54:24.151622 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5258 22:54:24.151887 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =88
5259 22:54:24.158001 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =104
5260 22:54:24.158304
5261 22:54:24.158596
5262 22:54:24.164650 [DQSOSCAuto] RK0, (LSB)MR18= 0x342b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5263 22:54:24.168112 CH0 RK0: MR19=505, MR18=342B
5264 22:54:24.174535 CH0_RK0: MR19=0x505, MR18=0x342B, DQSOSC=405, MR23=63, INC=66, DEC=44
5265 22:54:24.174883
5266 22:54:24.177912 ----->DramcWriteLeveling(PI) begin...
5267 22:54:24.178165 ==
5268 22:54:24.181400 Dram Type= 6, Freq= 0, CH_0, rank 1
5269 22:54:24.184331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 22:54:24.184585 ==
5271 22:54:24.187674 Write leveling (Byte 0): 32 => 32
5272 22:54:24.191205 Write leveling (Byte 1): 30 => 30
5273 22:54:24.194515 DramcWriteLeveling(PI) end<-----
5274 22:54:24.194895
5275 22:54:24.195187 ==
5276 22:54:24.198095 Dram Type= 6, Freq= 0, CH_0, rank 1
5277 22:54:24.201655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 22:54:24.201940 ==
5279 22:54:24.204605 [Gating] SW mode calibration
5280 22:54:24.211267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5281 22:54:24.217522 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5282 22:54:24.221038 0 14 0 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
5283 22:54:24.227838 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 22:54:24.231235 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 22:54:24.234546 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 22:54:24.240707 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 22:54:24.244051 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 22:54:24.247166 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 22:54:24.253893 0 14 28 | B1->B0 | 2c2c 2e2e | 0 1 | (0 0) (1 1)
5290 22:54:24.257502 0 15 0 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5291 22:54:24.260676 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 22:54:24.267272 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 22:54:24.270284 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 22:54:24.273891 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 22:54:24.280728 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 22:54:24.284040 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 22:54:24.287147 0 15 28 | B1->B0 | 3b3b 3c3c | 0 0 | (0 0) (0 0)
5298 22:54:24.290589 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 22:54:24.297420 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 22:54:24.300442 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 22:54:24.303538 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 22:54:24.310329 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 22:54:24.313699 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 22:54:24.317260 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 22:54:24.324024 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5306 22:54:24.326695 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 22:54:24.331009 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 22:54:24.336989 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 22:54:24.340527 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 22:54:24.344157 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 22:54:24.349934 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 22:54:24.353337 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 22:54:24.356741 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 22:54:24.363162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 22:54:24.367005 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 22:54:24.370201 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 22:54:24.376367 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 22:54:24.380571 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 22:54:24.383614 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 22:54:24.390216 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 22:54:24.393209 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5322 22:54:24.396745 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 22:54:24.399784 Total UI for P1: 0, mck2ui 16
5324 22:54:24.403588 best dqsien dly found for B0: ( 1, 2, 28)
5325 22:54:24.406990 Total UI for P1: 0, mck2ui 16
5326 22:54:24.409798 best dqsien dly found for B1: ( 1, 2, 28)
5327 22:54:24.413347 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5328 22:54:24.416973 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5329 22:54:24.417416
5330 22:54:24.422906 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5331 22:54:24.426359 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5332 22:54:24.426793 [Gating] SW calibration Done
5333 22:54:24.429542 ==
5334 22:54:24.432866 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 22:54:24.436336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 22:54:24.436756 ==
5337 22:54:24.437086 RX Vref Scan: 0
5338 22:54:24.437397
5339 22:54:24.439639 RX Vref 0 -> 0, step: 1
5340 22:54:24.440095
5341 22:54:24.443318 RX Delay -80 -> 252, step: 8
5342 22:54:24.446567 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5343 22:54:24.449953 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5344 22:54:24.453261 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5345 22:54:24.459938 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5346 22:54:24.463179 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5347 22:54:24.466458 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5348 22:54:24.469875 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5349 22:54:24.473130 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5350 22:54:24.476291 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5351 22:54:24.482897 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5352 22:54:24.486182 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5353 22:54:24.489525 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5354 22:54:24.493952 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5355 22:54:24.496891 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5356 22:54:24.500073 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5357 22:54:24.506577 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5358 22:54:24.507101 ==
5359 22:54:24.509993 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 22:54:24.513286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 22:54:24.513708 ==
5362 22:54:24.514042 DQS Delay:
5363 22:54:24.516373 DQS0 = 0, DQS1 = 0
5364 22:54:24.516791 DQM Delay:
5365 22:54:24.519873 DQM0 = 104, DQM1 = 94
5366 22:54:24.520424 DQ Delay:
5367 22:54:24.523127 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5368 22:54:24.526178 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5369 22:54:24.529808 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5370 22:54:24.532972 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5371 22:54:24.533402
5372 22:54:24.533741
5373 22:54:24.534076 ==
5374 22:54:24.535907 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 22:54:24.542659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 22:54:24.543085 ==
5377 22:54:24.543439
5378 22:54:24.543951
5379 22:54:24.544526 TX Vref Scan disable
5380 22:54:24.546387 == TX Byte 0 ==
5381 22:54:24.549823 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5382 22:54:24.556278 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5383 22:54:24.556971 == TX Byte 1 ==
5384 22:54:24.559373 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5385 22:54:24.566367 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5386 22:54:24.566858 ==
5387 22:54:24.569919 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 22:54:24.572931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 22:54:24.573494 ==
5390 22:54:24.573843
5391 22:54:24.574157
5392 22:54:24.575879 TX Vref Scan disable
5393 22:54:24.576343 == TX Byte 0 ==
5394 22:54:24.582800 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5395 22:54:24.586308 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5396 22:54:24.586857 == TX Byte 1 ==
5397 22:54:24.592769 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5398 22:54:24.596103 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5399 22:54:24.596526
5400 22:54:24.596856 [DATLAT]
5401 22:54:24.599225 Freq=933, CH0 RK1
5402 22:54:24.599644
5403 22:54:24.600026 DATLAT Default: 0xb
5404 22:54:24.602595 0, 0xFFFF, sum = 0
5405 22:54:24.603016 1, 0xFFFF, sum = 0
5406 22:54:24.606118 2, 0xFFFF, sum = 0
5407 22:54:24.606569 3, 0xFFFF, sum = 0
5408 22:54:24.609675 4, 0xFFFF, sum = 0
5409 22:54:24.612552 5, 0xFFFF, sum = 0
5410 22:54:24.613130 6, 0xFFFF, sum = 0
5411 22:54:24.615494 7, 0xFFFF, sum = 0
5412 22:54:24.616104 8, 0xFFFF, sum = 0
5413 22:54:24.619031 9, 0xFFFF, sum = 0
5414 22:54:24.619457 10, 0x0, sum = 1
5415 22:54:24.622610 11, 0x0, sum = 2
5416 22:54:24.623106 12, 0x0, sum = 3
5417 22:54:24.623458 13, 0x0, sum = 4
5418 22:54:24.625751 best_step = 11
5419 22:54:24.626244
5420 22:54:24.626627 ==
5421 22:54:24.629210 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 22:54:24.632321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 22:54:24.632787 ==
5424 22:54:24.636036 RX Vref Scan: 0
5425 22:54:24.636465
5426 22:54:24.636959 RX Vref 0 -> 0, step: 1
5427 22:54:24.639183
5428 22:54:24.639675 RX Delay -45 -> 252, step: 4
5429 22:54:24.646354 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5430 22:54:24.649932 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5431 22:54:24.653459 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5432 22:54:24.656726 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5433 22:54:24.659887 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5434 22:54:24.666623 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5435 22:54:24.669922 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5436 22:54:24.673549 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5437 22:54:24.676808 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5438 22:54:24.679423 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5439 22:54:24.686128 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5440 22:54:24.689520 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5441 22:54:24.693163 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5442 22:54:24.696471 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5443 22:54:24.700215 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5444 22:54:24.706392 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5445 22:54:24.706918 ==
5446 22:54:24.710180 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 22:54:24.713061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 22:54:24.713536 ==
5449 22:54:24.714003 DQS Delay:
5450 22:54:24.716531 DQS0 = 0, DQS1 = 0
5451 22:54:24.716953 DQM Delay:
5452 22:54:24.720066 DQM0 = 104, DQM1 = 93
5453 22:54:24.720489 DQ Delay:
5454 22:54:24.723346 DQ0 =100, DQ1 =108, DQ2 =100, DQ3 =102
5455 22:54:24.725883 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5456 22:54:24.729915 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5457 22:54:24.732873 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5458 22:54:24.733465
5459 22:54:24.733958
5460 22:54:24.743387 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5461 22:54:24.744012 CH0 RK1: MR19=505, MR18=2C05
5462 22:54:24.749507 CH0_RK1: MR19=0x505, MR18=0x2C05, DQSOSC=408, MR23=63, INC=65, DEC=43
5463 22:54:24.752993 [RxdqsGatingPostProcess] freq 933
5464 22:54:24.760007 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5465 22:54:24.763322 best DQS0 dly(2T, 0.5T) = (0, 10)
5466 22:54:24.766009 best DQS1 dly(2T, 0.5T) = (0, 11)
5467 22:54:24.769897 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5468 22:54:24.772649 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5469 22:54:24.776028 best DQS0 dly(2T, 0.5T) = (0, 10)
5470 22:54:24.776595 best DQS1 dly(2T, 0.5T) = (0, 10)
5471 22:54:24.779480 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5472 22:54:24.782563 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5473 22:54:24.785997 Pre-setting of DQS Precalculation
5474 22:54:24.792471 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5475 22:54:24.792932 ==
5476 22:54:24.796377 Dram Type= 6, Freq= 0, CH_1, rank 0
5477 22:54:24.799003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 22:54:24.799427 ==
5479 22:54:24.805767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5480 22:54:24.812229 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5481 22:54:24.815745 [CA 0] Center 36 (6~67) winsize 62
5482 22:54:24.818802 [CA 1] Center 37 (6~68) winsize 63
5483 22:54:24.822260 [CA 2] Center 34 (4~65) winsize 62
5484 22:54:24.825954 [CA 3] Center 34 (4~65) winsize 62
5485 22:54:24.829217 [CA 4] Center 34 (4~65) winsize 62
5486 22:54:24.832053 [CA 5] Center 33 (3~64) winsize 62
5487 22:54:24.832475
5488 22:54:24.835393 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5489 22:54:24.835832
5490 22:54:24.838663 [CATrainingPosCal] consider 1 rank data
5491 22:54:24.842333 u2DelayCellTimex100 = 270/100 ps
5492 22:54:24.845209 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5493 22:54:24.848861 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5494 22:54:24.852340 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5495 22:54:24.855526 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5496 22:54:24.859036 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5497 22:54:24.862480 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5498 22:54:24.863052
5499 22:54:24.868648 CA PerBit enable=1, Macro0, CA PI delay=33
5500 22:54:24.869251
5501 22:54:24.869790 [CBTSetCACLKResult] CA Dly = 33
5502 22:54:24.872098 CS Dly: 6 (0~37)
5503 22:54:24.872562 ==
5504 22:54:24.875254 Dram Type= 6, Freq= 0, CH_1, rank 1
5505 22:54:24.878308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 22:54:24.878954 ==
5507 22:54:24.885281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5508 22:54:24.892018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5509 22:54:24.895450 [CA 0] Center 36 (6~67) winsize 62
5510 22:54:24.898755 [CA 1] Center 37 (6~68) winsize 63
5511 22:54:24.901948 [CA 2] Center 35 (4~66) winsize 63
5512 22:54:24.905491 [CA 3] Center 34 (4~65) winsize 62
5513 22:54:24.908896 [CA 4] Center 34 (4~65) winsize 62
5514 22:54:24.912105 [CA 5] Center 34 (4~64) winsize 61
5515 22:54:24.912527
5516 22:54:24.915377 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5517 22:54:24.915797
5518 22:54:24.918603 [CATrainingPosCal] consider 2 rank data
5519 22:54:24.922333 u2DelayCellTimex100 = 270/100 ps
5520 22:54:24.925416 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5521 22:54:24.928299 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5522 22:54:24.932006 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5523 22:54:24.935704 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5524 22:54:24.938141 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5525 22:54:24.941701 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5526 22:54:24.942242
5527 22:54:24.948356 CA PerBit enable=1, Macro0, CA PI delay=34
5528 22:54:24.948800
5529 22:54:24.951801 [CBTSetCACLKResult] CA Dly = 34
5530 22:54:24.952323 CS Dly: 7 (0~39)
5531 22:54:24.952848
5532 22:54:24.955093 ----->DramcWriteLeveling(PI) begin...
5533 22:54:24.955639 ==
5534 22:54:24.958769 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 22:54:24.961749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 22:54:24.962493 ==
5537 22:54:24.965169 Write leveling (Byte 0): 25 => 25
5538 22:54:24.968276 Write leveling (Byte 1): 26 => 26
5539 22:54:24.971940 DramcWriteLeveling(PI) end<-----
5540 22:54:24.972650
5541 22:54:24.973334 ==
5542 22:54:24.975288 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 22:54:24.981450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 22:54:24.981849 ==
5545 22:54:24.982176 [Gating] SW mode calibration
5546 22:54:24.991770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5547 22:54:24.995152 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5548 22:54:24.997977 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 22:54:25.004814 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 22:54:25.008100 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 22:54:25.011743 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 22:54:25.018278 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 22:54:25.021322 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 22:54:25.025387 0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
5555 22:54:25.031277 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
5556 22:54:25.034978 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 22:54:25.038503 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 22:54:25.045036 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 22:54:25.048170 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 22:54:25.051776 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 22:54:25.058285 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 22:54:25.061648 0 15 24 | B1->B0 | 2727 3535 | 1 0 | (0 0) (0 0)
5563 22:54:25.064625 0 15 28 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
5564 22:54:25.071070 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 22:54:25.075024 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 22:54:25.078051 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 22:54:25.084665 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 22:54:25.088073 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 22:54:25.091479 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 22:54:25.097797 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5571 22:54:25.101148 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5572 22:54:25.104611 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 22:54:25.111263 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 22:54:25.114695 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 22:54:25.117972 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 22:54:25.121116 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 22:54:25.128043 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 22:54:25.130891 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 22:54:25.134333 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 22:54:25.141339 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 22:54:25.144716 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 22:54:25.148047 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 22:54:25.154888 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 22:54:25.157918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 22:54:25.161335 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 22:54:25.167776 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5587 22:54:25.171875 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 22:54:25.174498 Total UI for P1: 0, mck2ui 16
5589 22:54:25.178057 best dqsien dly found for B0: ( 1, 2, 24)
5590 22:54:25.181283 Total UI for P1: 0, mck2ui 16
5591 22:54:25.184666 best dqsien dly found for B1: ( 1, 2, 26)
5592 22:54:25.187781 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5593 22:54:25.191412 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5594 22:54:25.191927
5595 22:54:25.194320 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5596 22:54:25.197858 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5597 22:54:25.201146 [Gating] SW calibration Done
5598 22:54:25.201695 ==
5599 22:54:25.204744 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 22:54:25.207554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 22:54:25.211079 ==
5602 22:54:25.211516 RX Vref Scan: 0
5603 22:54:25.211995
5604 22:54:25.214677 RX Vref 0 -> 0, step: 1
5605 22:54:25.215113
5606 22:54:25.218004 RX Delay -80 -> 252, step: 8
5607 22:54:25.221498 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5608 22:54:25.224062 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5609 22:54:25.228239 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5610 22:54:25.230909 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5611 22:54:25.234645 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5612 22:54:25.240728 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5613 22:54:25.244082 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5614 22:54:25.247529 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5615 22:54:25.250725 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5616 22:54:25.254263 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5617 22:54:25.257130 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5618 22:54:25.264190 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5619 22:54:25.267414 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5620 22:54:25.270581 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5621 22:54:25.274341 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5622 22:54:25.277681 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5623 22:54:25.280905 ==
5624 22:54:25.281374 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 22:54:25.287610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 22:54:25.288089 ==
5627 22:54:25.288428 DQS Delay:
5628 22:54:25.290658 DQS0 = 0, DQS1 = 0
5629 22:54:25.291127 DQM Delay:
5630 22:54:25.293773 DQM0 = 102, DQM1 = 98
5631 22:54:25.294192 DQ Delay:
5632 22:54:25.297864 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5633 22:54:25.300694 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5634 22:54:25.304293 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5635 22:54:25.307695 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5636 22:54:25.308222
5637 22:54:25.308589
5638 22:54:25.308898 ==
5639 22:54:25.311127 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 22:54:25.313835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 22:54:25.314243 ==
5642 22:54:25.314575
5643 22:54:25.317334
5644 22:54:25.317823 TX Vref Scan disable
5645 22:54:25.321143 == TX Byte 0 ==
5646 22:54:25.324219 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5647 22:54:25.327673 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5648 22:54:25.330696 == TX Byte 1 ==
5649 22:54:25.334193 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5650 22:54:25.337190 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5651 22:54:25.337756 ==
5652 22:54:25.340832 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 22:54:25.346944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 22:54:25.347420 ==
5655 22:54:25.347944
5656 22:54:25.348454
5657 22:54:25.348969 TX Vref Scan disable
5658 22:54:25.351035 == TX Byte 0 ==
5659 22:54:25.354659 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5660 22:54:25.361076 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5661 22:54:25.361577 == TX Byte 1 ==
5662 22:54:25.364918 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5663 22:54:25.368007 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5664 22:54:25.371453
5665 22:54:25.371863 [DATLAT]
5666 22:54:25.372245 Freq=933, CH1 RK0
5667 22:54:25.372563
5668 22:54:25.374793 DATLAT Default: 0xd
5669 22:54:25.375204 0, 0xFFFF, sum = 0
5670 22:54:25.378035 1, 0xFFFF, sum = 0
5671 22:54:25.378456 2, 0xFFFF, sum = 0
5672 22:54:25.381456 3, 0xFFFF, sum = 0
5673 22:54:25.384967 4, 0xFFFF, sum = 0
5674 22:54:25.385389 5, 0xFFFF, sum = 0
5675 22:54:25.388230 6, 0xFFFF, sum = 0
5676 22:54:25.388651 7, 0xFFFF, sum = 0
5677 22:54:25.391199 8, 0xFFFF, sum = 0
5678 22:54:25.391618 9, 0xFFFF, sum = 0
5679 22:54:25.394663 10, 0x0, sum = 1
5680 22:54:25.395082 11, 0x0, sum = 2
5681 22:54:25.397880 12, 0x0, sum = 3
5682 22:54:25.398302 13, 0x0, sum = 4
5683 22:54:25.398634 best_step = 11
5684 22:54:25.398942
5685 22:54:25.400773 ==
5686 22:54:25.404363 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 22:54:25.407700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 22:54:25.408317 ==
5689 22:54:25.408682 RX Vref Scan: 1
5690 22:54:25.409058
5691 22:54:25.411083 RX Vref 0 -> 0, step: 1
5692 22:54:25.411457
5693 22:54:25.414365 RX Delay -45 -> 252, step: 4
5694 22:54:25.414967
5695 22:54:25.417680 Set Vref, RX VrefLevel [Byte0]: 53
5696 22:54:25.421071 [Byte1]: 53
5697 22:54:25.421484
5698 22:54:25.424785 Final RX Vref Byte 0 = 53 to rank0
5699 22:54:25.427452 Final RX Vref Byte 1 = 53 to rank0
5700 22:54:25.430650 Final RX Vref Byte 0 = 53 to rank1
5701 22:54:25.434236 Final RX Vref Byte 1 = 53 to rank1==
5702 22:54:25.437661 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 22:54:25.440927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 22:54:25.441486 ==
5705 22:54:25.444730 DQS Delay:
5706 22:54:25.445183 DQS0 = 0, DQS1 = 0
5707 22:54:25.447312 DQM Delay:
5708 22:54:25.447725 DQM0 = 104, DQM1 = 100
5709 22:54:25.450835 DQ Delay:
5710 22:54:25.454085 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5711 22:54:25.457433 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =104
5712 22:54:25.461248 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5713 22:54:25.464635 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =108
5714 22:54:25.465049
5715 22:54:25.465379
5716 22:54:25.470986 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5717 22:54:25.474407 CH1 RK0: MR19=505, MR18=1931
5718 22:54:25.480860 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5719 22:54:25.481441
5720 22:54:25.484550 ----->DramcWriteLeveling(PI) begin...
5721 22:54:25.485060 ==
5722 22:54:25.487634 Dram Type= 6, Freq= 0, CH_1, rank 1
5723 22:54:25.490774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 22:54:25.491213 ==
5725 22:54:25.494511 Write leveling (Byte 0): 28 => 28
5726 22:54:25.497271 Write leveling (Byte 1): 28 => 28
5727 22:54:25.501194 DramcWriteLeveling(PI) end<-----
5728 22:54:25.501749
5729 22:54:25.502161 ==
5730 22:54:25.503884 Dram Type= 6, Freq= 0, CH_1, rank 1
5731 22:54:25.507531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 22:54:25.508142 ==
5733 22:54:25.510944 [Gating] SW mode calibration
5734 22:54:25.517574 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5735 22:54:25.524214 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5736 22:54:25.527138 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 22:54:25.534171 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 22:54:25.537228 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 22:54:25.540614 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 22:54:25.547580 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 22:54:25.550893 0 14 20 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
5742 22:54:25.554075 0 14 24 | B1->B0 | 2d2d 3030 | 0 0 | (0 0) (0 1)
5743 22:54:25.560294 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5744 22:54:25.563656 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 22:54:25.567060 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 22:54:25.573927 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 22:54:25.576801 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 22:54:25.580213 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 22:54:25.587176 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 22:54:25.590006 0 15 24 | B1->B0 | 3a3a 2828 | 0 0 | (1 1) (0 0)
5751 22:54:25.593689 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5752 22:54:25.600372 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 22:54:25.603726 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 22:54:25.607274 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 22:54:25.610229 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 22:54:25.617047 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 22:54:25.620314 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5758 22:54:25.623643 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5759 22:54:25.630265 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5760 22:54:25.633754 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5761 22:54:25.636876 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 22:54:25.643736 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 22:54:25.646847 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 22:54:25.649746 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 22:54:25.656455 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 22:54:25.660007 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 22:54:25.663466 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 22:54:25.670382 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 22:54:25.673120 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 22:54:25.676439 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 22:54:25.683374 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 22:54:25.686970 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 22:54:25.690203 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 22:54:25.696771 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5775 22:54:25.699902 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 22:54:25.702935 Total UI for P1: 0, mck2ui 16
5777 22:54:25.706467 best dqsien dly found for B0: ( 1, 2, 24)
5778 22:54:25.709677 Total UI for P1: 0, mck2ui 16
5779 22:54:25.712895 best dqsien dly found for B1: ( 1, 2, 24)
5780 22:54:25.716937 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5781 22:54:25.719781 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5782 22:54:25.720316
5783 22:54:25.722888 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5784 22:54:25.726661 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5785 22:54:25.729716 [Gating] SW calibration Done
5786 22:54:25.730138 ==
5787 22:54:25.733131 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 22:54:25.736319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 22:54:25.739758 ==
5790 22:54:25.740230 RX Vref Scan: 0
5791 22:54:25.740568
5792 22:54:25.743296 RX Vref 0 -> 0, step: 1
5793 22:54:25.743715
5794 22:54:25.744103 RX Delay -80 -> 252, step: 8
5795 22:54:25.749746 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5796 22:54:25.753045 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5797 22:54:25.756290 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5798 22:54:25.759768 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5799 22:54:25.763025 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5800 22:54:25.766218 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5801 22:54:25.773018 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5802 22:54:25.776530 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5803 22:54:25.779532 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5804 22:54:25.782973 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5805 22:54:25.786389 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5806 22:54:25.789892 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5807 22:54:25.796185 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5808 22:54:25.799374 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5809 22:54:25.802734 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5810 22:54:25.806432 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5811 22:54:25.807075 ==
5812 22:54:25.809495 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 22:54:25.816045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 22:54:25.816508 ==
5815 22:54:25.816996 DQS Delay:
5816 22:54:25.819937 DQS0 = 0, DQS1 = 0
5817 22:54:25.820399 DQM Delay:
5818 22:54:25.820836 DQM0 = 103, DQM1 = 99
5819 22:54:25.823331 DQ Delay:
5820 22:54:25.826203 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5821 22:54:25.829549 DQ4 =95, DQ5 =119, DQ6 =115, DQ7 =99
5822 22:54:25.832788 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5823 22:54:25.836217 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5824 22:54:25.836661
5825 22:54:25.837002
5826 22:54:25.837358 ==
5827 22:54:25.839515 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 22:54:25.842657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 22:54:25.843082 ==
5830 22:54:25.843416
5831 22:54:25.843725
5832 22:54:25.845985 TX Vref Scan disable
5833 22:54:25.849764 == TX Byte 0 ==
5834 22:54:25.853121 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5835 22:54:25.856597 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5836 22:54:25.859827 == TX Byte 1 ==
5837 22:54:25.863195 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5838 22:54:25.865933 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5839 22:54:25.866354 ==
5840 22:54:25.869873 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 22:54:25.873081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 22:54:25.876025 ==
5843 22:54:25.876447
5844 22:54:25.876784
5845 22:54:25.877098 TX Vref Scan disable
5846 22:54:25.879946 == TX Byte 0 ==
5847 22:54:25.883169 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5848 22:54:25.886532 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5849 22:54:25.889908 == TX Byte 1 ==
5850 22:54:25.893041 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5851 22:54:25.896787 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5852 22:54:25.899935
5853 22:54:25.900412 [DATLAT]
5854 22:54:25.900857 Freq=933, CH1 RK1
5855 22:54:25.901277
5856 22:54:25.902969 DATLAT Default: 0xb
5857 22:54:25.903396 0, 0xFFFF, sum = 0
5858 22:54:25.906177 1, 0xFFFF, sum = 0
5859 22:54:25.906761 2, 0xFFFF, sum = 0
5860 22:54:25.909545 3, 0xFFFF, sum = 0
5861 22:54:25.912728 4, 0xFFFF, sum = 0
5862 22:54:25.913166 5, 0xFFFF, sum = 0
5863 22:54:25.916675 6, 0xFFFF, sum = 0
5864 22:54:25.917126 7, 0xFFFF, sum = 0
5865 22:54:25.920015 8, 0xFFFF, sum = 0
5866 22:54:25.920453 9, 0xFFFF, sum = 0
5867 22:54:25.923028 10, 0x0, sum = 1
5868 22:54:25.923556 11, 0x0, sum = 2
5869 22:54:25.925908 12, 0x0, sum = 3
5870 22:54:25.926370 13, 0x0, sum = 4
5871 22:54:25.926715 best_step = 11
5872 22:54:25.929106
5873 22:54:25.929457 ==
5874 22:54:25.932456 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 22:54:25.935772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 22:54:25.936242 ==
5877 22:54:25.936582 RX Vref Scan: 0
5878 22:54:25.936903
5879 22:54:25.939096 RX Vref 0 -> 0, step: 1
5880 22:54:25.939518
5881 22:54:25.942827 RX Delay -45 -> 252, step: 4
5882 22:54:25.949663 iDelay=199, Bit 0, Center 110 (31 ~ 190) 160
5883 22:54:25.952618 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5884 22:54:25.956232 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5885 22:54:25.959233 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5886 22:54:25.962651 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5887 22:54:25.965953 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5888 22:54:25.972419 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5889 22:54:25.976037 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5890 22:54:25.979413 iDelay=199, Bit 8, Center 92 (11 ~ 174) 164
5891 22:54:25.982542 iDelay=199, Bit 9, Center 94 (11 ~ 178) 168
5892 22:54:25.985879 iDelay=199, Bit 10, Center 102 (19 ~ 186) 168
5893 22:54:25.992216 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5894 22:54:25.995761 iDelay=199, Bit 12, Center 108 (19 ~ 198) 180
5895 22:54:25.999274 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5896 22:54:26.002504 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5897 22:54:26.005845 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5898 22:54:26.008811 ==
5899 22:54:26.011946 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 22:54:26.015263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 22:54:26.015676 ==
5902 22:54:26.016045 DQS Delay:
5903 22:54:26.019032 DQS0 = 0, DQS1 = 0
5904 22:54:26.019444 DQM Delay:
5905 22:54:26.022339 DQM0 = 104, DQM1 = 101
5906 22:54:26.022750 DQ Delay:
5907 22:54:26.025484 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5908 22:54:26.028663 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =102
5909 22:54:26.032104 DQ8 =92, DQ9 =94, DQ10 =102, DQ11 =94
5910 22:54:26.035350 DQ12 =108, DQ13 =106, DQ14 =104, DQ15 =108
5911 22:54:26.035773
5912 22:54:26.036148
5913 22:54:26.045113 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5914 22:54:26.048994 CH1 RK1: MR19=505, MR18=2C00
5915 22:54:26.051989 CH1_RK1: MR19=0x505, MR18=0x2C00, DQSOSC=408, MR23=63, INC=65, DEC=43
5916 22:54:26.055062 [RxdqsGatingPostProcess] freq 933
5917 22:54:26.062048 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5918 22:54:26.065173 best DQS0 dly(2T, 0.5T) = (0, 10)
5919 22:54:26.068551 best DQS1 dly(2T, 0.5T) = (0, 10)
5920 22:54:26.071499 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5921 22:54:26.074851 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5922 22:54:26.078168 best DQS0 dly(2T, 0.5T) = (0, 10)
5923 22:54:26.081636 best DQS1 dly(2T, 0.5T) = (0, 10)
5924 22:54:26.084983 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5925 22:54:26.088588 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5926 22:54:26.089117 Pre-setting of DQS Precalculation
5927 22:54:26.095092 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5928 22:54:26.102097 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5929 22:54:26.108211 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5930 22:54:26.108800
5931 22:54:26.109316
5932 22:54:26.112033 [Calibration Summary] 1866 Mbps
5933 22:54:26.115013 CH 0, Rank 0
5934 22:54:26.115442 SW Impedance : PASS
5935 22:54:26.118286 DUTY Scan : NO K
5936 22:54:26.121592 ZQ Calibration : PASS
5937 22:54:26.122066 Jitter Meter : NO K
5938 22:54:26.124737 CBT Training : PASS
5939 22:54:26.128396 Write leveling : PASS
5940 22:54:26.128807 RX DQS gating : PASS
5941 22:54:26.131617 RX DQ/DQS(RDDQC) : PASS
5942 22:54:26.132087 TX DQ/DQS : PASS
5943 22:54:26.134747 RX DATLAT : PASS
5944 22:54:26.137983 RX DQ/DQS(Engine): PASS
5945 22:54:26.138395 TX OE : NO K
5946 22:54:26.141749 All Pass.
5947 22:54:26.142258
5948 22:54:26.142589 CH 0, Rank 1
5949 22:54:26.145075 SW Impedance : PASS
5950 22:54:26.145508 DUTY Scan : NO K
5951 22:54:26.148260 ZQ Calibration : PASS
5952 22:54:26.151679 Jitter Meter : NO K
5953 22:54:26.152132 CBT Training : PASS
5954 22:54:26.154468 Write leveling : PASS
5955 22:54:26.158200 RX DQS gating : PASS
5956 22:54:26.158637 RX DQ/DQS(RDDQC) : PASS
5957 22:54:26.161170 TX DQ/DQS : PASS
5958 22:54:26.164516 RX DATLAT : PASS
5959 22:54:26.164943 RX DQ/DQS(Engine): PASS
5960 22:54:26.168015 TX OE : NO K
5961 22:54:26.168444 All Pass.
5962 22:54:26.168876
5963 22:54:26.171382 CH 1, Rank 0
5964 22:54:26.171878 SW Impedance : PASS
5965 22:54:26.174992 DUTY Scan : NO K
5966 22:54:26.178163 ZQ Calibration : PASS
5967 22:54:26.178664 Jitter Meter : NO K
5968 22:54:26.181578 CBT Training : PASS
5969 22:54:26.182035 Write leveling : PASS
5970 22:54:26.184608 RX DQS gating : PASS
5971 22:54:26.188597 RX DQ/DQS(RDDQC) : PASS
5972 22:54:26.189127 TX DQ/DQS : PASS
5973 22:54:26.191829 RX DATLAT : PASS
5974 22:54:26.194940 RX DQ/DQS(Engine): PASS
5975 22:54:26.195396 TX OE : NO K
5976 22:54:26.198164 All Pass.
5977 22:54:26.198573
5978 22:54:26.198905 CH 1, Rank 1
5979 22:54:26.201665 SW Impedance : PASS
5980 22:54:26.202168 DUTY Scan : NO K
5981 22:54:26.204834 ZQ Calibration : PASS
5982 22:54:26.208082 Jitter Meter : NO K
5983 22:54:26.208625 CBT Training : PASS
5984 22:54:26.211471 Write leveling : PASS
5985 22:54:26.214892 RX DQS gating : PASS
5986 22:54:26.215309 RX DQ/DQS(RDDQC) : PASS
5987 22:54:26.218324 TX DQ/DQS : PASS
5988 22:54:26.221207 RX DATLAT : PASS
5989 22:54:26.221627 RX DQ/DQS(Engine): PASS
5990 22:54:26.224394 TX OE : NO K
5991 22:54:26.224822 All Pass.
5992 22:54:26.225260
5993 22:54:26.227586 DramC Write-DBI off
5994 22:54:26.230880 PER_BANK_REFRESH: Hybrid Mode
5995 22:54:26.231320 TX_TRACKING: ON
5996 22:54:26.241574 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5997 22:54:26.244416 [FAST_K] Save calibration result to emmc
5998 22:54:26.247826 dramc_set_vcore_voltage set vcore to 650000
5999 22:54:26.251140 Read voltage for 400, 6
6000 22:54:26.251639 Vio18 = 0
6001 22:54:26.252170 Vcore = 650000
6002 22:54:26.254194 Vdram = 0
6003 22:54:26.254631 Vddq = 0
6004 22:54:26.255066 Vmddr = 0
6005 22:54:26.260951 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6006 22:54:26.264941 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6007 22:54:26.267654 MEM_TYPE=3, freq_sel=20
6008 22:54:26.270923 sv_algorithm_assistance_LP4_800
6009 22:54:26.274160 ============ PULL DRAM RESETB DOWN ============
6010 22:54:26.277601 ========== PULL DRAM RESETB DOWN end =========
6011 22:54:26.284095 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6012 22:54:26.287471 ===================================
6013 22:54:26.288010 LPDDR4 DRAM CONFIGURATION
6014 22:54:26.290837 ===================================
6015 22:54:26.294071 EX_ROW_EN[0] = 0x0
6016 22:54:26.297942 EX_ROW_EN[1] = 0x0
6017 22:54:26.298367 LP4Y_EN = 0x0
6018 22:54:26.300935 WORK_FSP = 0x0
6019 22:54:26.301361 WL = 0x2
6020 22:54:26.304453 RL = 0x2
6021 22:54:26.304878 BL = 0x2
6022 22:54:26.308024 RPST = 0x0
6023 22:54:26.308455 RD_PRE = 0x0
6024 22:54:26.310947 WR_PRE = 0x1
6025 22:54:26.311373 WR_PST = 0x0
6026 22:54:26.314101 DBI_WR = 0x0
6027 22:54:26.314614 DBI_RD = 0x0
6028 22:54:26.317841 OTF = 0x1
6029 22:54:26.321268 ===================================
6030 22:54:26.324129 ===================================
6031 22:54:26.324557 ANA top config
6032 22:54:26.327322 ===================================
6033 22:54:26.331390 DLL_ASYNC_EN = 0
6034 22:54:26.334469 ALL_SLAVE_EN = 1
6035 22:54:26.334896 NEW_RANK_MODE = 1
6036 22:54:26.337289 DLL_IDLE_MODE = 1
6037 22:54:26.341044 LP45_APHY_COMB_EN = 1
6038 22:54:26.344180 TX_ODT_DIS = 1
6039 22:54:26.347662 NEW_8X_MODE = 1
6040 22:54:26.351278 ===================================
6041 22:54:26.354134 ===================================
6042 22:54:26.354571 data_rate = 800
6043 22:54:26.357567 CKR = 1
6044 22:54:26.360707 DQ_P2S_RATIO = 4
6045 22:54:26.364224 ===================================
6046 22:54:26.367673 CA_P2S_RATIO = 4
6047 22:54:26.371364 DQ_CA_OPEN = 0
6048 22:54:26.374263 DQ_SEMI_OPEN = 1
6049 22:54:26.374695 CA_SEMI_OPEN = 1
6050 22:54:26.377695 CA_FULL_RATE = 0
6051 22:54:26.381200 DQ_CKDIV4_EN = 0
6052 22:54:26.383859 CA_CKDIV4_EN = 1
6053 22:54:26.388001 CA_PREDIV_EN = 0
6054 22:54:26.390700 PH8_DLY = 0
6055 22:54:26.391157 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6056 22:54:26.394039 DQ_AAMCK_DIV = 0
6057 22:54:26.397462 CA_AAMCK_DIV = 0
6058 22:54:26.401055 CA_ADMCK_DIV = 4
6059 22:54:26.404066 DQ_TRACK_CA_EN = 0
6060 22:54:26.407459 CA_PICK = 800
6061 22:54:26.407884 CA_MCKIO = 400
6062 22:54:26.410866 MCKIO_SEMI = 400
6063 22:54:26.414268 PLL_FREQ = 3016
6064 22:54:26.417824 DQ_UI_PI_RATIO = 32
6065 22:54:26.420708 CA_UI_PI_RATIO = 32
6066 22:54:26.423793 ===================================
6067 22:54:26.427238 ===================================
6068 22:54:26.430532 memory_type:LPDDR4
6069 22:54:26.430962 GP_NUM : 10
6070 22:54:26.433729 SRAM_EN : 1
6071 22:54:26.437484 MD32_EN : 0
6072 22:54:26.440416 ===================================
6073 22:54:26.440845 [ANA_INIT] >>>>>>>>>>>>>>
6074 22:54:26.443752 <<<<<< [CONFIGURE PHASE]: ANA_TX
6075 22:54:26.447398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6076 22:54:26.450532 ===================================
6077 22:54:26.453627 data_rate = 800,PCW = 0X7400
6078 22:54:26.457082 ===================================
6079 22:54:26.460338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6080 22:54:26.466974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6081 22:54:26.477000 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6082 22:54:26.480729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6083 22:54:26.483705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6084 22:54:26.490760 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6085 22:54:26.491344 [ANA_INIT] flow start
6086 22:54:26.493879 [ANA_INIT] PLL >>>>>>>>
6087 22:54:26.494344 [ANA_INIT] PLL <<<<<<<<
6088 22:54:26.497400 [ANA_INIT] MIDPI >>>>>>>>
6089 22:54:26.500429 [ANA_INIT] MIDPI <<<<<<<<
6090 22:54:26.503626 [ANA_INIT] DLL >>>>>>>>
6091 22:54:26.504227 [ANA_INIT] flow end
6092 22:54:26.507211 ============ LP4 DIFF to SE enter ============
6093 22:54:26.513844 ============ LP4 DIFF to SE exit ============
6094 22:54:26.514443 [ANA_INIT] <<<<<<<<<<<<<
6095 22:54:26.517030 [Flow] Enable top DCM control >>>>>
6096 22:54:26.520294 [Flow] Enable top DCM control <<<<<
6097 22:54:26.524083 Enable DLL master slave shuffle
6098 22:54:26.530293 ==============================================================
6099 22:54:26.530869 Gating Mode config
6100 22:54:26.536544 ==============================================================
6101 22:54:26.539983 Config description:
6102 22:54:26.550054 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6103 22:54:26.556569 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6104 22:54:26.559857 SELPH_MODE 0: By rank 1: By Phase
6105 22:54:26.566651 ==============================================================
6106 22:54:26.570197 GAT_TRACK_EN = 0
6107 22:54:26.573350 RX_GATING_MODE = 2
6108 22:54:26.573949 RX_GATING_TRACK_MODE = 2
6109 22:54:26.576180 SELPH_MODE = 1
6110 22:54:26.579526 PICG_EARLY_EN = 1
6111 22:54:26.582867 VALID_LAT_VALUE = 1
6112 22:54:26.589725 ==============================================================
6113 22:54:26.593235 Enter into Gating configuration >>>>
6114 22:54:26.596227 Exit from Gating configuration <<<<
6115 22:54:26.599598 Enter into DVFS_PRE_config >>>>>
6116 22:54:26.610042 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6117 22:54:26.613308 Exit from DVFS_PRE_config <<<<<
6118 22:54:26.616511 Enter into PICG configuration >>>>
6119 22:54:26.620082 Exit from PICG configuration <<<<
6120 22:54:26.622860 [RX_INPUT] configuration >>>>>
6121 22:54:26.626098 [RX_INPUT] configuration <<<<<
6122 22:54:26.629579 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6123 22:54:26.636287 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6124 22:54:26.643136 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6125 22:54:26.649606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6126 22:54:26.653012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 22:54:26.659501 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 22:54:26.662785 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6129 22:54:26.669222 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6130 22:54:26.672389 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6131 22:54:26.676703 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6132 22:54:26.679037 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6133 22:54:26.685583 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6134 22:54:26.689109 ===================================
6135 22:54:26.692607 LPDDR4 DRAM CONFIGURATION
6136 22:54:26.695838 ===================================
6137 22:54:26.696293 EX_ROW_EN[0] = 0x0
6138 22:54:26.699240 EX_ROW_EN[1] = 0x0
6139 22:54:26.699667 LP4Y_EN = 0x0
6140 22:54:26.702254 WORK_FSP = 0x0
6141 22:54:26.702676 WL = 0x2
6142 22:54:26.705648 RL = 0x2
6143 22:54:26.706072 BL = 0x2
6144 22:54:26.708867 RPST = 0x0
6145 22:54:26.709294 RD_PRE = 0x0
6146 22:54:26.712284 WR_PRE = 0x1
6147 22:54:26.712745 WR_PST = 0x0
6148 22:54:26.715559 DBI_WR = 0x0
6149 22:54:26.716003 DBI_RD = 0x0
6150 22:54:26.719220 OTF = 0x1
6151 22:54:26.722268 ===================================
6152 22:54:26.725321 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6153 22:54:26.729095 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6154 22:54:26.735648 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 22:54:26.739084 ===================================
6156 22:54:26.739740 LPDDR4 DRAM CONFIGURATION
6157 22:54:26.742169 ===================================
6158 22:54:26.745408 EX_ROW_EN[0] = 0x10
6159 22:54:26.749185 EX_ROW_EN[1] = 0x0
6160 22:54:26.749799 LP4Y_EN = 0x0
6161 22:54:26.752294 WORK_FSP = 0x0
6162 22:54:26.752707 WL = 0x2
6163 22:54:26.755448 RL = 0x2
6164 22:54:26.755865 BL = 0x2
6165 22:54:26.758826 RPST = 0x0
6166 22:54:26.759242 RD_PRE = 0x0
6167 22:54:26.762824 WR_PRE = 0x1
6168 22:54:26.763393 WR_PST = 0x0
6169 22:54:26.765694 DBI_WR = 0x0
6170 22:54:26.766204 DBI_RD = 0x0
6171 22:54:26.768959 OTF = 0x1
6172 22:54:26.772460 ===================================
6173 22:54:26.778351 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6174 22:54:26.781782 nWR fixed to 30
6175 22:54:26.785096 [ModeRegInit_LP4] CH0 RK0
6176 22:54:26.785511 [ModeRegInit_LP4] CH0 RK1
6177 22:54:26.788415 [ModeRegInit_LP4] CH1 RK0
6178 22:54:26.792496 [ModeRegInit_LP4] CH1 RK1
6179 22:54:26.793019 match AC timing 19
6180 22:54:26.798436 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6181 22:54:26.802148 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6182 22:54:26.805374 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6183 22:54:26.811487 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6184 22:54:26.815462 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6185 22:54:26.816033 ==
6186 22:54:26.819072 Dram Type= 6, Freq= 0, CH_0, rank 0
6187 22:54:26.821617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6188 22:54:26.822054 ==
6189 22:54:26.828422 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6190 22:54:26.834884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6191 22:54:26.838655 [CA 0] Center 36 (8~64) winsize 57
6192 22:54:26.841953 [CA 1] Center 36 (8~64) winsize 57
6193 22:54:26.842546 [CA 2] Center 36 (8~64) winsize 57
6194 22:54:26.844990 [CA 3] Center 36 (8~64) winsize 57
6195 22:54:26.848616 [CA 4] Center 36 (8~64) winsize 57
6196 22:54:26.851766 [CA 5] Center 36 (8~64) winsize 57
6197 22:54:26.852242
6198 22:54:26.855255 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6199 22:54:26.855682
6200 22:54:26.861938 [CATrainingPosCal] consider 1 rank data
6201 22:54:26.862471 u2DelayCellTimex100 = 270/100 ps
6202 22:54:26.868493 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 22:54:26.872347 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 22:54:26.875015 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 22:54:26.878820 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 22:54:26.882087 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 22:54:26.885183 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 22:54:26.885615
6209 22:54:26.888919 CA PerBit enable=1, Macro0, CA PI delay=36
6210 22:54:26.889434
6211 22:54:26.892034 [CBTSetCACLKResult] CA Dly = 36
6212 22:54:26.894731 CS Dly: 1 (0~32)
6213 22:54:26.895157 ==
6214 22:54:26.897959 Dram Type= 6, Freq= 0, CH_0, rank 1
6215 22:54:26.901700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 22:54:26.902226 ==
6217 22:54:26.908119 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 22:54:26.911193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6219 22:54:26.915060 [CA 0] Center 36 (8~64) winsize 57
6220 22:54:26.917642 [CA 1] Center 36 (8~64) winsize 57
6221 22:54:26.921404 [CA 2] Center 36 (8~64) winsize 57
6222 22:54:26.924818 [CA 3] Center 36 (8~64) winsize 57
6223 22:54:26.927740 [CA 4] Center 36 (8~64) winsize 57
6224 22:54:26.931295 [CA 5] Center 36 (8~64) winsize 57
6225 22:54:26.931708
6226 22:54:26.934686 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6227 22:54:26.935230
6228 22:54:26.937867 [CATrainingPosCal] consider 2 rank data
6229 22:54:26.940999 u2DelayCellTimex100 = 270/100 ps
6230 22:54:26.944199 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 22:54:26.947828 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 22:54:26.951606 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 22:54:26.957902 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 22:54:26.961293 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 22:54:26.964062 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 22:54:26.964642
6237 22:54:26.968016 CA PerBit enable=1, Macro0, CA PI delay=36
6238 22:54:26.968563
6239 22:54:26.971023 [CBTSetCACLKResult] CA Dly = 36
6240 22:54:26.971452 CS Dly: 1 (0~32)
6241 22:54:26.971885
6242 22:54:26.974175 ----->DramcWriteLeveling(PI) begin...
6243 22:54:26.974606 ==
6244 22:54:26.978012 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 22:54:26.984109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 22:54:26.984540 ==
6247 22:54:26.987655 Write leveling (Byte 0): 40 => 8
6248 22:54:26.990715 Write leveling (Byte 1): 40 => 8
6249 22:54:26.991169 DramcWriteLeveling(PI) end<-----
6250 22:54:26.994121
6251 22:54:26.994538 ==
6252 22:54:26.997331 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 22:54:27.001223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 22:54:27.001735 ==
6255 22:54:27.004431 [Gating] SW mode calibration
6256 22:54:27.011074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6257 22:54:27.014751 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6258 22:54:27.021422 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 22:54:27.024524 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6260 22:54:27.027632 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 22:54:27.034069 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 22:54:27.037536 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 22:54:27.040676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 22:54:27.046991 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 22:54:27.050328 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 22:54:27.054044 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 22:54:27.057402 Total UI for P1: 0, mck2ui 16
6268 22:54:27.060806 best dqsien dly found for B0: ( 0, 14, 24)
6269 22:54:27.064157 Total UI for P1: 0, mck2ui 16
6270 22:54:27.067607 best dqsien dly found for B1: ( 0, 14, 24)
6271 22:54:27.070663 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6272 22:54:27.073693 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6273 22:54:27.074107
6274 22:54:27.080329 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6275 22:54:27.083734 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6276 22:54:27.087006 [Gating] SW calibration Done
6277 22:54:27.087568 ==
6278 22:54:27.090171 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 22:54:27.094069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 22:54:27.094499 ==
6281 22:54:27.094832 RX Vref Scan: 0
6282 22:54:27.095235
6283 22:54:27.096988 RX Vref 0 -> 0, step: 1
6284 22:54:27.097405
6285 22:54:27.100672 RX Delay -410 -> 252, step: 16
6286 22:54:27.104010 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6287 22:54:27.111063 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6288 22:54:27.113695 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6289 22:54:27.117083 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6290 22:54:27.120366 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6291 22:54:27.127270 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6292 22:54:27.130101 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6293 22:54:27.133407 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6294 22:54:27.136884 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6295 22:54:27.140011 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6296 22:54:27.146815 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6297 22:54:27.149986 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6298 22:54:27.153365 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6299 22:54:27.160011 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6300 22:54:27.163203 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6301 22:54:27.166863 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6302 22:54:27.167273 ==
6303 22:54:27.169788 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 22:54:27.173448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 22:54:27.176424 ==
6306 22:54:27.176832 DQS Delay:
6307 22:54:27.177155 DQS0 = 27, DQS1 = 35
6308 22:54:27.179540 DQM Delay:
6309 22:54:27.180124 DQM0 = 11, DQM1 = 11
6310 22:54:27.183211 DQ Delay:
6311 22:54:27.186824 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6312 22:54:27.187290 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6313 22:54:27.190024 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6314 22:54:27.193298 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6315 22:54:27.193705
6316 22:54:27.194025
6317 22:54:27.196417 ==
6318 22:54:27.196826 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 22:54:27.203366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 22:54:27.203886 ==
6321 22:54:27.204259
6322 22:54:27.204561
6323 22:54:27.206401 TX Vref Scan disable
6324 22:54:27.206910 == TX Byte 0 ==
6325 22:54:27.210137 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6326 22:54:27.216478 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6327 22:54:27.216993 == TX Byte 1 ==
6328 22:54:27.219780 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6329 22:54:27.226653 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6330 22:54:27.227179 ==
6331 22:54:27.229583 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 22:54:27.233053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 22:54:27.233576 ==
6334 22:54:27.233910
6335 22:54:27.234212
6336 22:54:27.236315 TX Vref Scan disable
6337 22:54:27.236722 == TX Byte 0 ==
6338 22:54:27.239788 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 22:54:27.246247 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 22:54:27.246777 == TX Byte 1 ==
6341 22:54:27.249750 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 22:54:27.256297 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 22:54:27.256796
6344 22:54:27.257124 [DATLAT]
6345 22:54:27.257427 Freq=400, CH0 RK0
6346 22:54:27.257720
6347 22:54:27.260003 DATLAT Default: 0xf
6348 22:54:27.263158 0, 0xFFFF, sum = 0
6349 22:54:27.263691 1, 0xFFFF, sum = 0
6350 22:54:27.266548 2, 0xFFFF, sum = 0
6351 22:54:27.267060 3, 0xFFFF, sum = 0
6352 22:54:27.269619 4, 0xFFFF, sum = 0
6353 22:54:27.270033 5, 0xFFFF, sum = 0
6354 22:54:27.272814 6, 0xFFFF, sum = 0
6355 22:54:27.273231 7, 0xFFFF, sum = 0
6356 22:54:27.276268 8, 0xFFFF, sum = 0
6357 22:54:27.276789 9, 0xFFFF, sum = 0
6358 22:54:27.279873 10, 0xFFFF, sum = 0
6359 22:54:27.280437 11, 0xFFFF, sum = 0
6360 22:54:27.282907 12, 0xFFFF, sum = 0
6361 22:54:27.283416 13, 0x0, sum = 1
6362 22:54:27.285931 14, 0x0, sum = 2
6363 22:54:27.286345 15, 0x0, sum = 3
6364 22:54:27.289636 16, 0x0, sum = 4
6365 22:54:27.290156 best_step = 14
6366 22:54:27.290486
6367 22:54:27.290785 ==
6368 22:54:27.292772 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 22:54:27.295804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 22:54:27.299509 ==
6371 22:54:27.300107 RX Vref Scan: 1
6372 22:54:27.300475
6373 22:54:27.302963 RX Vref 0 -> 0, step: 1
6374 22:54:27.303595
6375 22:54:27.306264 RX Delay -311 -> 252, step: 8
6376 22:54:27.306819
6377 22:54:27.309534 Set Vref, RX VrefLevel [Byte0]: 56
6378 22:54:27.312417 [Byte1]: 48
6379 22:54:27.312992
6380 22:54:27.316017 Final RX Vref Byte 0 = 56 to rank0
6381 22:54:27.319260 Final RX Vref Byte 1 = 48 to rank0
6382 22:54:27.322363 Final RX Vref Byte 0 = 56 to rank1
6383 22:54:27.326010 Final RX Vref Byte 1 = 48 to rank1==
6384 22:54:27.329277 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 22:54:27.332024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 22:54:27.332486 ==
6387 22:54:27.336214 DQS Delay:
6388 22:54:27.336769 DQS0 = 28, DQS1 = 32
6389 22:54:27.338841 DQM Delay:
6390 22:54:27.339393 DQM0 = 10, DQM1 = 10
6391 22:54:27.339754 DQ Delay:
6392 22:54:27.342691 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6393 22:54:27.345477 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6394 22:54:27.349353 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6395 22:54:27.352956 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6396 22:54:27.353509
6397 22:54:27.353869
6398 22:54:27.362585 [DQSOSCAuto] RK0, (LSB)MR18= 0xccb9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6399 22:54:27.363144 CH0 RK0: MR19=C0C, MR18=CCB9
6400 22:54:27.368968 CH0_RK0: MR19=0xC0C, MR18=0xCCB9, DQSOSC=384, MR23=63, INC=400, DEC=267
6401 22:54:27.369520 ==
6402 22:54:27.372440 Dram Type= 6, Freq= 0, CH_0, rank 1
6403 22:54:27.379058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 22:54:27.379617 ==
6405 22:54:27.382151 [Gating] SW mode calibration
6406 22:54:27.389128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6407 22:54:27.392614 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6408 22:54:27.398946 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 22:54:27.402399 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6410 22:54:27.405474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 22:54:27.412793 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6412 22:54:27.415457 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 22:54:27.419089 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 22:54:27.422742 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 22:54:27.428621 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 22:54:27.432499 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 22:54:27.435450 Total UI for P1: 0, mck2ui 16
6418 22:54:27.438830 best dqsien dly found for B0: ( 0, 14, 24)
6419 22:54:27.442130 Total UI for P1: 0, mck2ui 16
6420 22:54:27.445152 best dqsien dly found for B1: ( 0, 14, 24)
6421 22:54:27.448386 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6422 22:54:27.451479 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6423 22:54:27.451891
6424 22:54:27.455254 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6425 22:54:27.461584 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6426 22:54:27.462037 [Gating] SW calibration Done
6427 22:54:27.465060 ==
6428 22:54:27.465477 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 22:54:27.471477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 22:54:27.472054 ==
6431 22:54:27.472402 RX Vref Scan: 0
6432 22:54:27.472758
6433 22:54:27.474929 RX Vref 0 -> 0, step: 1
6434 22:54:27.475446
6435 22:54:27.478165 RX Delay -410 -> 252, step: 16
6436 22:54:27.481358 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6437 22:54:27.484881 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6438 22:54:27.492165 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6439 22:54:27.495307 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6440 22:54:27.498326 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6441 22:54:27.501254 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6442 22:54:27.507883 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6443 22:54:27.511446 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6444 22:54:27.514526 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6445 22:54:27.518244 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6446 22:54:27.524793 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6447 22:54:27.528130 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6448 22:54:27.531609 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6449 22:54:27.537971 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6450 22:54:27.541030 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6451 22:54:27.544322 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6452 22:54:27.544780 ==
6453 22:54:27.547935 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 22:54:27.551569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 22:54:27.552218 ==
6456 22:54:27.554445 DQS Delay:
6457 22:54:27.555012 DQS0 = 19, DQS1 = 35
6458 22:54:27.557912 DQM Delay:
6459 22:54:27.558368 DQM0 = 5, DQM1 = 12
6460 22:54:27.561002 DQ Delay:
6461 22:54:27.561455 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6462 22:54:27.564265 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6463 22:54:27.567517 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6464 22:54:27.570899 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6465 22:54:27.571439
6466 22:54:27.571793
6467 22:54:27.572156 ==
6468 22:54:27.574298 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 22:54:27.580737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 22:54:27.581216 ==
6471 22:54:27.581653
6472 22:54:27.582063
6473 22:54:27.582460 TX Vref Scan disable
6474 22:54:27.583831 == TX Byte 0 ==
6475 22:54:27.587637 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6476 22:54:27.590861 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6477 22:54:27.594251 == TX Byte 1 ==
6478 22:54:27.597262 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6479 22:54:27.600496 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6480 22:54:27.600930 ==
6481 22:54:27.603732 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 22:54:27.611316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 22:54:27.611904 ==
6484 22:54:27.612383
6485 22:54:27.612804
6486 22:54:27.613207 TX Vref Scan disable
6487 22:54:27.613969 == TX Byte 0 ==
6488 22:54:27.617287 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6489 22:54:27.620553 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6490 22:54:27.624366 == TX Byte 1 ==
6491 22:54:27.627462 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6492 22:54:27.630895 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6493 22:54:27.631323
6494 22:54:27.634538 [DATLAT]
6495 22:54:27.635076 Freq=400, CH0 RK1
6496 22:54:27.635539
6497 22:54:27.637144 DATLAT Default: 0xe
6498 22:54:27.637570 0, 0xFFFF, sum = 0
6499 22:54:27.640854 1, 0xFFFF, sum = 0
6500 22:54:27.641287 2, 0xFFFF, sum = 0
6501 22:54:27.644549 3, 0xFFFF, sum = 0
6502 22:54:27.644980 4, 0xFFFF, sum = 0
6503 22:54:27.647481 5, 0xFFFF, sum = 0
6504 22:54:27.647914 6, 0xFFFF, sum = 0
6505 22:54:27.650965 7, 0xFFFF, sum = 0
6506 22:54:27.651394 8, 0xFFFF, sum = 0
6507 22:54:27.654232 9, 0xFFFF, sum = 0
6508 22:54:27.654666 10, 0xFFFF, sum = 0
6509 22:54:27.657502 11, 0xFFFF, sum = 0
6510 22:54:27.660694 12, 0xFFFF, sum = 0
6511 22:54:27.661110 13, 0x0, sum = 1
6512 22:54:27.661446 14, 0x0, sum = 2
6513 22:54:27.663708 15, 0x0, sum = 3
6514 22:54:27.664158 16, 0x0, sum = 4
6515 22:54:27.667315 best_step = 14
6516 22:54:27.667827
6517 22:54:27.668205 ==
6518 22:54:27.670472 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 22:54:27.673540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 22:54:27.673959 ==
6521 22:54:27.677521 RX Vref Scan: 0
6522 22:54:27.678092
6523 22:54:27.678603 RX Vref 0 -> 0, step: 1
6524 22:54:27.680744
6525 22:54:27.681157 RX Delay -311 -> 252, step: 8
6526 22:54:27.689125 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6527 22:54:27.692280 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6528 22:54:27.695428 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6529 22:54:27.699197 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6530 22:54:27.705711 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6531 22:54:27.709001 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6532 22:54:27.712400 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6533 22:54:27.715559 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6534 22:54:27.722401 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6535 22:54:27.725014 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6536 22:54:27.728876 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6537 22:54:27.732113 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6538 22:54:27.739022 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6539 22:54:27.742621 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6540 22:54:27.745034 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6541 22:54:27.752115 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6542 22:54:27.752649 ==
6543 22:54:27.755404 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 22:54:27.758772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 22:54:27.759306 ==
6546 22:54:27.759751 DQS Delay:
6547 22:54:27.762144 DQS0 = 24, DQS1 = 32
6548 22:54:27.762867 DQM Delay:
6549 22:54:27.765138 DQM0 = 9, DQM1 = 10
6550 22:54:27.765550 DQ Delay:
6551 22:54:27.768622 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6552 22:54:27.772069 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6553 22:54:27.775531 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6554 22:54:27.778814 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6555 22:54:27.779334
6556 22:54:27.779685
6557 22:54:27.784940 [DQSOSCAuto] RK1, (LSB)MR18= 0xc161, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 385 ps
6558 22:54:27.788259 CH0 RK1: MR19=C0C, MR18=C161
6559 22:54:27.795478 CH0_RK1: MR19=0xC0C, MR18=0xC161, DQSOSC=385, MR23=63, INC=398, DEC=265
6560 22:54:27.798044 [RxdqsGatingPostProcess] freq 400
6561 22:54:27.801894 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6562 22:54:27.805462 best DQS0 dly(2T, 0.5T) = (0, 10)
6563 22:54:27.808156 best DQS1 dly(2T, 0.5T) = (0, 10)
6564 22:54:27.812500 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6565 22:54:27.814724 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6566 22:54:27.818348 best DQS0 dly(2T, 0.5T) = (0, 10)
6567 22:54:27.822024 best DQS1 dly(2T, 0.5T) = (0, 10)
6568 22:54:27.825476 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6569 22:54:27.828419 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6570 22:54:27.831539 Pre-setting of DQS Precalculation
6571 22:54:27.835057 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6572 22:54:27.838162 ==
6573 22:54:27.841763 Dram Type= 6, Freq= 0, CH_1, rank 0
6574 22:54:27.844706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 22:54:27.845171 ==
6576 22:54:27.847880 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6577 22:54:27.855164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6578 22:54:27.858666 [CA 0] Center 36 (8~64) winsize 57
6579 22:54:27.862145 [CA 1] Center 36 (8~64) winsize 57
6580 22:54:27.864708 [CA 2] Center 36 (8~64) winsize 57
6581 22:54:27.868281 [CA 3] Center 36 (8~64) winsize 57
6582 22:54:27.871420 [CA 4] Center 36 (8~64) winsize 57
6583 22:54:27.874758 [CA 5] Center 36 (8~64) winsize 57
6584 22:54:27.875319
6585 22:54:27.878367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6586 22:54:27.878926
6587 22:54:27.881558 [CATrainingPosCal] consider 1 rank data
6588 22:54:27.884866 u2DelayCellTimex100 = 270/100 ps
6589 22:54:27.888115 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 22:54:27.891716 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 22:54:27.894699 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 22:54:27.897716 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 22:54:27.901444 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 22:54:27.908219 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 22:54:27.908767
6596 22:54:27.911641 CA PerBit enable=1, Macro0, CA PI delay=36
6597 22:54:27.912260
6598 22:54:27.914972 [CBTSetCACLKResult] CA Dly = 36
6599 22:54:27.915531 CS Dly: 1 (0~32)
6600 22:54:27.915901 ==
6601 22:54:27.918313 Dram Type= 6, Freq= 0, CH_1, rank 1
6602 22:54:27.921318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 22:54:27.924646 ==
6604 22:54:27.928074 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 22:54:27.934954 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6606 22:54:27.938175 [CA 0] Center 36 (8~64) winsize 57
6607 22:54:27.941281 [CA 1] Center 36 (8~64) winsize 57
6608 22:54:27.944590 [CA 2] Center 36 (8~64) winsize 57
6609 22:54:27.947759 [CA 3] Center 36 (8~64) winsize 57
6610 22:54:27.951218 [CA 4] Center 36 (8~64) winsize 57
6611 22:54:27.954523 [CA 5] Center 36 (8~64) winsize 57
6612 22:54:27.955091
6613 22:54:27.957856 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6614 22:54:27.958324
6615 22:54:27.961371 [CATrainingPosCal] consider 2 rank data
6616 22:54:27.965020 u2DelayCellTimex100 = 270/100 ps
6617 22:54:27.968583 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 22:54:27.971574 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 22:54:27.974430 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 22:54:27.978199 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 22:54:27.981799 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 22:54:27.984606 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 22:54:27.985193
6624 22:54:27.988137 CA PerBit enable=1, Macro0, CA PI delay=36
6625 22:54:27.988709
6626 22:54:27.991315 [CBTSetCACLKResult] CA Dly = 36
6627 22:54:27.994369 CS Dly: 1 (0~32)
6628 22:54:27.994829
6629 22:54:27.997735 ----->DramcWriteLeveling(PI) begin...
6630 22:54:27.998202 ==
6631 22:54:28.000899 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 22:54:28.004639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 22:54:28.005100 ==
6634 22:54:28.007918 Write leveling (Byte 0): 40 => 8
6635 22:54:28.011676 Write leveling (Byte 1): 40 => 8
6636 22:54:28.014908 DramcWriteLeveling(PI) end<-----
6637 22:54:28.015464
6638 22:54:28.015831 ==
6639 22:54:28.017896 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 22:54:28.021585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 22:54:28.022143 ==
6642 22:54:28.024546 [Gating] SW mode calibration
6643 22:54:28.031300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6644 22:54:28.037830 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6645 22:54:28.040648 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6646 22:54:28.047511 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6647 22:54:28.051268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 22:54:28.054126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 22:54:28.060595 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 22:54:28.063830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 22:54:28.067200 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 22:54:28.070521 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 22:54:28.077453 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 22:54:28.080575 Total UI for P1: 0, mck2ui 16
6655 22:54:28.084152 best dqsien dly found for B0: ( 0, 14, 24)
6656 22:54:28.087808 Total UI for P1: 0, mck2ui 16
6657 22:54:28.091331 best dqsien dly found for B1: ( 0, 14, 24)
6658 22:54:28.094160 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6659 22:54:28.098008 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6660 22:54:28.098434
6661 22:54:28.100515 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6662 22:54:28.104041 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6663 22:54:28.107405 [Gating] SW calibration Done
6664 22:54:28.107824 ==
6665 22:54:28.111065 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 22:54:28.114009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 22:54:28.114535 ==
6668 22:54:28.117925 RX Vref Scan: 0
6669 22:54:28.118349
6670 22:54:28.118687 RX Vref 0 -> 0, step: 1
6671 22:54:28.121373
6672 22:54:28.121899 RX Delay -410 -> 252, step: 16
6673 22:54:28.127679 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6674 22:54:28.130803 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6675 22:54:28.134218 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6676 22:54:28.137104 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6677 22:54:28.143874 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6678 22:54:28.147395 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6679 22:54:28.150481 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6680 22:54:28.154148 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6681 22:54:28.160725 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6682 22:54:28.164006 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6683 22:54:28.167827 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6684 22:54:28.170899 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6685 22:54:28.177809 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6686 22:54:28.180848 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6687 22:54:28.183912 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6688 22:54:28.190418 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6689 22:54:28.190989 ==
6690 22:54:28.193690 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 22:54:28.197335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 22:54:28.197821 ==
6693 22:54:28.198231 DQS Delay:
6694 22:54:28.200192 DQS0 = 35, DQS1 = 35
6695 22:54:28.200655 DQM Delay:
6696 22:54:28.203204 DQM0 = 17, DQM1 = 13
6697 22:54:28.203671 DQ Delay:
6698 22:54:28.206779 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6699 22:54:28.209812 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6700 22:54:28.213022 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6701 22:54:28.216875 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6702 22:54:28.217299
6703 22:54:28.217633
6704 22:54:28.217945 ==
6705 22:54:28.220198 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 22:54:28.223736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 22:54:28.224211 ==
6708 22:54:28.224550
6709 22:54:28.224863
6710 22:54:28.226294 TX Vref Scan disable
6711 22:54:28.229630 == TX Byte 0 ==
6712 22:54:28.233219 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6713 22:54:28.236633 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6714 22:54:28.240059 == TX Byte 1 ==
6715 22:54:28.243095 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6716 22:54:28.246407 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6717 22:54:28.246823 ==
6718 22:54:28.249472 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 22:54:28.252861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 22:54:28.253274 ==
6721 22:54:28.253602
6722 22:54:28.256178
6723 22:54:28.256587 TX Vref Scan disable
6724 22:54:28.259863 == TX Byte 0 ==
6725 22:54:28.262843 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 22:54:28.266216 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 22:54:28.270043 == TX Byte 1 ==
6728 22:54:28.273114 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 22:54:28.276628 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 22:54:28.277044
6731 22:54:28.277373 [DATLAT]
6732 22:54:28.279480 Freq=400, CH1 RK0
6733 22:54:28.280140
6734 22:54:28.280703 DATLAT Default: 0xf
6735 22:54:28.283248 0, 0xFFFF, sum = 0
6736 22:54:28.283674 1, 0xFFFF, sum = 0
6737 22:54:28.286559 2, 0xFFFF, sum = 0
6738 22:54:28.289868 3, 0xFFFF, sum = 0
6739 22:54:28.290294 4, 0xFFFF, sum = 0
6740 22:54:28.293340 5, 0xFFFF, sum = 0
6741 22:54:28.293766 6, 0xFFFF, sum = 0
6742 22:54:28.296655 7, 0xFFFF, sum = 0
6743 22:54:28.297144 8, 0xFFFF, sum = 0
6744 22:54:28.300011 9, 0xFFFF, sum = 0
6745 22:54:28.300454 10, 0xFFFF, sum = 0
6746 22:54:28.302951 11, 0xFFFF, sum = 0
6747 22:54:28.303376 12, 0xFFFF, sum = 0
6748 22:54:28.306660 13, 0x0, sum = 1
6749 22:54:28.307090 14, 0x0, sum = 2
6750 22:54:28.309934 15, 0x0, sum = 3
6751 22:54:28.310303 16, 0x0, sum = 4
6752 22:54:28.313121 best_step = 14
6753 22:54:28.313539
6754 22:54:28.313872 ==
6755 22:54:28.316391 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 22:54:28.319395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 22:54:28.319817 ==
6758 22:54:28.320194 RX Vref Scan: 1
6759 22:54:28.323022
6760 22:54:28.323438 RX Vref 0 -> 0, step: 1
6761 22:54:28.323772
6762 22:54:28.326353 RX Delay -311 -> 252, step: 8
6763 22:54:28.326787
6764 22:54:28.329590 Set Vref, RX VrefLevel [Byte0]: 53
6765 22:54:28.332780 [Byte1]: 53
6766 22:54:28.336547
6767 22:54:28.336956 Final RX Vref Byte 0 = 53 to rank0
6768 22:54:28.340422 Final RX Vref Byte 1 = 53 to rank0
6769 22:54:28.343294 Final RX Vref Byte 0 = 53 to rank1
6770 22:54:28.347228 Final RX Vref Byte 1 = 53 to rank1==
6771 22:54:28.350362 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 22:54:28.356526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 22:54:28.356952 ==
6774 22:54:28.357290 DQS Delay:
6775 22:54:28.359805 DQS0 = 32, DQS1 = 32
6776 22:54:28.360255 DQM Delay:
6777 22:54:28.360591 DQM0 = 13, DQM1 = 11
6778 22:54:28.363662 DQ Delay:
6779 22:54:28.366955 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6780 22:54:28.370227 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6781 22:54:28.370650 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6782 22:54:28.373093 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6783 22:54:28.373511
6784 22:54:28.376453
6785 22:54:28.383634 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6786 22:54:28.386706 CH1 RK0: MR19=C0C, MR18=8FC9
6787 22:54:28.393284 CH1_RK0: MR19=0xC0C, MR18=0x8FC9, DQSOSC=384, MR23=63, INC=400, DEC=267
6788 22:54:28.393714 ==
6789 22:54:28.396700 Dram Type= 6, Freq= 0, CH_1, rank 1
6790 22:54:28.400069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 22:54:28.400527 ==
6792 22:54:28.403311 [Gating] SW mode calibration
6793 22:54:28.409943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6794 22:54:28.416730 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6795 22:54:28.419823 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6796 22:54:28.423174 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6797 22:54:28.429928 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 22:54:28.433278 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6799 22:54:28.436660 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 22:54:28.439503 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 22:54:28.446502 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 22:54:28.450169 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 22:54:28.453364 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 22:54:28.456524 Total UI for P1: 0, mck2ui 16
6805 22:54:28.459825 best dqsien dly found for B0: ( 0, 14, 24)
6806 22:54:28.463575 Total UI for P1: 0, mck2ui 16
6807 22:54:28.466433 best dqsien dly found for B1: ( 0, 14, 24)
6808 22:54:28.469964 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6809 22:54:28.476133 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6810 22:54:28.476571
6811 22:54:28.479286 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6812 22:54:28.482432 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6813 22:54:28.486561 [Gating] SW calibration Done
6814 22:54:28.487061 ==
6815 22:54:28.489352 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 22:54:28.492598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 22:54:28.493021 ==
6818 22:54:28.496447 RX Vref Scan: 0
6819 22:54:28.496870
6820 22:54:28.497209 RX Vref 0 -> 0, step: 1
6821 22:54:28.497728
6822 22:54:28.499615 RX Delay -410 -> 252, step: 16
6823 22:54:28.502961 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6824 22:54:28.509229 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6825 22:54:28.512585 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6826 22:54:28.515807 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6827 22:54:28.519191 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6828 22:54:28.525851 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6829 22:54:28.529177 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6830 22:54:28.532511 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6831 22:54:28.535658 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6832 22:54:28.542242 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6833 22:54:28.545588 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6834 22:54:28.549030 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6835 22:54:28.552254 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6836 22:54:28.559214 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6837 22:54:28.562482 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6838 22:54:28.565701 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6839 22:54:28.566139 ==
6840 22:54:28.568627 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 22:54:28.575300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 22:54:28.575929 ==
6843 22:54:28.576431 DQS Delay:
6844 22:54:28.578713 DQS0 = 35, DQS1 = 35
6845 22:54:28.579272 DQM Delay:
6846 22:54:28.582218 DQM0 = 18, DQM1 = 15
6847 22:54:28.582818 DQ Delay:
6848 22:54:28.585383 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6849 22:54:28.588137 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6850 22:54:28.591854 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6851 22:54:28.594610 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6852 22:54:28.594696
6853 22:54:28.594797
6854 22:54:28.594897 ==
6855 22:54:28.598563 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 22:54:28.601763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 22:54:28.601848 ==
6858 22:54:28.601934
6859 22:54:28.602015
6860 22:54:28.605024 TX Vref Scan disable
6861 22:54:28.605109 == TX Byte 0 ==
6862 22:54:28.611220 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6863 22:54:28.614698 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6864 22:54:28.614783 == TX Byte 1 ==
6865 22:54:28.621519 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6866 22:54:28.624334 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6867 22:54:28.624419 ==
6868 22:54:28.628121 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 22:54:28.631429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 22:54:28.631530 ==
6871 22:54:28.631621
6872 22:54:28.631718
6873 22:54:28.634363 TX Vref Scan disable
6874 22:54:28.634461 == TX Byte 0 ==
6875 22:54:28.641453 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6876 22:54:28.644611 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6877 22:54:28.644693 == TX Byte 1 ==
6878 22:54:28.650929 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6879 22:54:28.654610 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6880 22:54:28.654714
6881 22:54:28.654806 [DATLAT]
6882 22:54:28.657971 Freq=400, CH1 RK1
6883 22:54:28.658064
6884 22:54:28.658151 DATLAT Default: 0xe
6885 22:54:28.661111 0, 0xFFFF, sum = 0
6886 22:54:28.661206 1, 0xFFFF, sum = 0
6887 22:54:28.664146 2, 0xFFFF, sum = 0
6888 22:54:28.664227 3, 0xFFFF, sum = 0
6889 22:54:28.667496 4, 0xFFFF, sum = 0
6890 22:54:28.667588 5, 0xFFFF, sum = 0
6891 22:54:28.670860 6, 0xFFFF, sum = 0
6892 22:54:28.670955 7, 0xFFFF, sum = 0
6893 22:54:28.674102 8, 0xFFFF, sum = 0
6894 22:54:28.674196 9, 0xFFFF, sum = 0
6895 22:54:28.677395 10, 0xFFFF, sum = 0
6896 22:54:28.681278 11, 0xFFFF, sum = 0
6897 22:54:28.681385 12, 0xFFFF, sum = 0
6898 22:54:28.683916 13, 0x0, sum = 1
6899 22:54:28.684016 14, 0x0, sum = 2
6900 22:54:28.687331 15, 0x0, sum = 3
6901 22:54:28.687427 16, 0x0, sum = 4
6902 22:54:28.687515 best_step = 14
6903 22:54:28.690669
6904 22:54:28.690760 ==
6905 22:54:28.693777 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 22:54:28.697372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 22:54:28.697484 ==
6908 22:54:28.697584 RX Vref Scan: 0
6909 22:54:28.697695
6910 22:54:28.700948 RX Vref 0 -> 0, step: 1
6911 22:54:28.701033
6912 22:54:28.704156 RX Delay -311 -> 252, step: 8
6913 22:54:28.710697 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6914 22:54:28.714542 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6915 22:54:28.717662 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6916 22:54:28.720943 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6917 22:54:28.727602 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6918 22:54:28.730810 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6919 22:54:28.734264 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6920 22:54:28.737614 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6921 22:54:28.743863 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6922 22:54:28.747202 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6923 22:54:28.750978 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6924 22:54:28.754340 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6925 22:54:28.760390 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6926 22:54:28.763709 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6927 22:54:28.767353 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6928 22:54:28.773641 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6929 22:54:28.773749 ==
6930 22:54:28.776858 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 22:54:28.780836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 22:54:28.780925 ==
6933 22:54:28.780989 DQS Delay:
6934 22:54:28.783561 DQS0 = 28, DQS1 = 36
6935 22:54:28.783654 DQM Delay:
6936 22:54:28.787353 DQM0 = 11, DQM1 = 14
6937 22:54:28.787452 DQ Delay:
6938 22:54:28.790797 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6939 22:54:28.794126 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6940 22:54:28.796914 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6941 22:54:28.800182 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6942 22:54:28.800289
6943 22:54:28.800381
6944 22:54:28.806965 [DQSOSCAuto] RK1, (LSB)MR18= 0xc858, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6945 22:54:28.810408 CH1 RK1: MR19=C0C, MR18=C858
6946 22:54:28.817060 CH1_RK1: MR19=0xC0C, MR18=0xC858, DQSOSC=385, MR23=63, INC=398, DEC=265
6947 22:54:28.820548 [RxdqsGatingPostProcess] freq 400
6948 22:54:28.823866 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6949 22:54:28.827131 best DQS0 dly(2T, 0.5T) = (0, 10)
6950 22:54:28.830338 best DQS1 dly(2T, 0.5T) = (0, 10)
6951 22:54:28.833471 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6952 22:54:28.836896 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6953 22:54:28.840326 best DQS0 dly(2T, 0.5T) = (0, 10)
6954 22:54:28.843673 best DQS1 dly(2T, 0.5T) = (0, 10)
6955 22:54:28.847510 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6956 22:54:28.850511 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6957 22:54:28.854020 Pre-setting of DQS Precalculation
6958 22:54:28.857025 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6959 22:54:28.867300 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6960 22:54:28.873590 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6961 22:54:28.873696
6962 22:54:28.873789
6963 22:54:28.876613 [Calibration Summary] 800 Mbps
6964 22:54:28.876696 CH 0, Rank 0
6965 22:54:28.880374 SW Impedance : PASS
6966 22:54:28.880460 DUTY Scan : NO K
6967 22:54:28.883372 ZQ Calibration : PASS
6968 22:54:28.887346 Jitter Meter : NO K
6969 22:54:28.887452 CBT Training : PASS
6970 22:54:28.890618 Write leveling : PASS
6971 22:54:28.893283 RX DQS gating : PASS
6972 22:54:28.893378 RX DQ/DQS(RDDQC) : PASS
6973 22:54:28.897333 TX DQ/DQS : PASS
6974 22:54:28.900621 RX DATLAT : PASS
6975 22:54:28.900718 RX DQ/DQS(Engine): PASS
6976 22:54:28.903898 TX OE : NO K
6977 22:54:28.904007 All Pass.
6978 22:54:28.904076
6979 22:54:28.906769 CH 0, Rank 1
6980 22:54:28.906862 SW Impedance : PASS
6981 22:54:28.910018 DUTY Scan : NO K
6982 22:54:28.910112 ZQ Calibration : PASS
6983 22:54:28.913415 Jitter Meter : NO K
6984 22:54:28.916834 CBT Training : PASS
6985 22:54:28.916905 Write leveling : NO K
6986 22:54:28.920101 RX DQS gating : PASS
6987 22:54:28.923538 RX DQ/DQS(RDDQC) : PASS
6988 22:54:28.923634 TX DQ/DQS : PASS
6989 22:54:28.926909 RX DATLAT : PASS
6990 22:54:28.930166 RX DQ/DQS(Engine): PASS
6991 22:54:28.930261 TX OE : NO K
6992 22:54:28.933721 All Pass.
6993 22:54:28.933794
6994 22:54:28.933864 CH 1, Rank 0
6995 22:54:28.936677 SW Impedance : PASS
6996 22:54:28.936744 DUTY Scan : NO K
6997 22:54:28.940459 ZQ Calibration : PASS
6998 22:54:28.943203 Jitter Meter : NO K
6999 22:54:28.943297 CBT Training : PASS
7000 22:54:28.946754 Write leveling : PASS
7001 22:54:28.950172 RX DQS gating : PASS
7002 22:54:28.950268 RX DQ/DQS(RDDQC) : PASS
7003 22:54:28.953635 TX DQ/DQS : PASS
7004 22:54:28.953709 RX DATLAT : PASS
7005 22:54:28.957156 RX DQ/DQS(Engine): PASS
7006 22:54:28.960343 TX OE : NO K
7007 22:54:28.960447 All Pass.
7008 22:54:28.960511
7009 22:54:28.960568 CH 1, Rank 1
7010 22:54:28.963447 SW Impedance : PASS
7011 22:54:28.966821 DUTY Scan : NO K
7012 22:54:28.966922 ZQ Calibration : PASS
7013 22:54:28.970185 Jitter Meter : NO K
7014 22:54:28.973674 CBT Training : PASS
7015 22:54:28.973772 Write leveling : NO K
7016 22:54:28.977023 RX DQS gating : PASS
7017 22:54:28.980345 RX DQ/DQS(RDDQC) : PASS
7018 22:54:28.980441 TX DQ/DQS : PASS
7019 22:54:28.983798 RX DATLAT : PASS
7020 22:54:28.986644 RX DQ/DQS(Engine): PASS
7021 22:54:28.986742 TX OE : NO K
7022 22:54:28.990127 All Pass.
7023 22:54:28.990197
7024 22:54:28.990261 DramC Write-DBI off
7025 22:54:28.993379 PER_BANK_REFRESH: Hybrid Mode
7026 22:54:28.993453 TX_TRACKING: ON
7027 22:54:29.003439 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7028 22:54:29.006751 [FAST_K] Save calibration result to emmc
7029 22:54:29.010045 dramc_set_vcore_voltage set vcore to 725000
7030 22:54:29.013404 Read voltage for 1600, 0
7031 22:54:29.013488 Vio18 = 0
7032 22:54:29.016794 Vcore = 725000
7033 22:54:29.016879 Vdram = 0
7034 22:54:29.016966 Vddq = 0
7035 22:54:29.020106 Vmddr = 0
7036 22:54:29.023551 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7037 22:54:29.030145 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7038 22:54:29.030230 MEM_TYPE=3, freq_sel=13
7039 22:54:29.033098 sv_algorithm_assistance_LP4_3733
7040 22:54:29.039601 ============ PULL DRAM RESETB DOWN ============
7041 22:54:29.043456 ========== PULL DRAM RESETB DOWN end =========
7042 22:54:29.046750 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7043 22:54:29.049416 ===================================
7044 22:54:29.052866 LPDDR4 DRAM CONFIGURATION
7045 22:54:29.056618 ===================================
7046 22:54:29.056717 EX_ROW_EN[0] = 0x0
7047 22:54:29.059382 EX_ROW_EN[1] = 0x0
7048 22:54:29.063390 LP4Y_EN = 0x0
7049 22:54:29.063465 WORK_FSP = 0x1
7050 22:54:29.066187 WL = 0x5
7051 22:54:29.066281 RL = 0x5
7052 22:54:29.069941 BL = 0x2
7053 22:54:29.070047 RPST = 0x0
7054 22:54:29.073084 RD_PRE = 0x0
7055 22:54:29.073159 WR_PRE = 0x1
7056 22:54:29.076216 WR_PST = 0x1
7057 22:54:29.076318 DBI_WR = 0x0
7058 22:54:29.079527 DBI_RD = 0x0
7059 22:54:29.079631 OTF = 0x1
7060 22:54:29.082550 ===================================
7061 22:54:29.086018 ===================================
7062 22:54:29.089236 ANA top config
7063 22:54:29.093055 ===================================
7064 22:54:29.093172 DLL_ASYNC_EN = 0
7065 22:54:29.096134 ALL_SLAVE_EN = 0
7066 22:54:29.099451 NEW_RANK_MODE = 1
7067 22:54:29.102543 DLL_IDLE_MODE = 1
7068 22:54:29.105870 LP45_APHY_COMB_EN = 1
7069 22:54:29.105956 TX_ODT_DIS = 0
7070 22:54:29.109293 NEW_8X_MODE = 1
7071 22:54:29.112810 ===================================
7072 22:54:29.116105 ===================================
7073 22:54:29.119530 data_rate = 3200
7074 22:54:29.122726 CKR = 1
7075 22:54:29.126069 DQ_P2S_RATIO = 8
7076 22:54:29.129219 ===================================
7077 22:54:29.132587 CA_P2S_RATIO = 8
7078 22:54:29.132660 DQ_CA_OPEN = 0
7079 22:54:29.136067 DQ_SEMI_OPEN = 0
7080 22:54:29.139217 CA_SEMI_OPEN = 0
7081 22:54:29.142670 CA_FULL_RATE = 0
7082 22:54:29.145801 DQ_CKDIV4_EN = 0
7083 22:54:29.145887 CA_CKDIV4_EN = 0
7084 22:54:29.149151 CA_PREDIV_EN = 0
7085 22:54:29.152582 PH8_DLY = 12
7086 22:54:29.155883 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7087 22:54:29.159246 DQ_AAMCK_DIV = 4
7088 22:54:29.162479 CA_AAMCK_DIV = 4
7089 22:54:29.162550 CA_ADMCK_DIV = 4
7090 22:54:29.165672 DQ_TRACK_CA_EN = 0
7091 22:54:29.168945 CA_PICK = 1600
7092 22:54:29.172254 CA_MCKIO = 1600
7093 22:54:29.176034 MCKIO_SEMI = 0
7094 22:54:29.178889 PLL_FREQ = 3068
7095 22:54:29.182082 DQ_UI_PI_RATIO = 32
7096 22:54:29.185982 CA_UI_PI_RATIO = 0
7097 22:54:29.189490 ===================================
7098 22:54:29.192837 ===================================
7099 22:54:29.192907 memory_type:LPDDR4
7100 22:54:29.195451 GP_NUM : 10
7101 22:54:29.195550 SRAM_EN : 1
7102 22:54:29.199091 MD32_EN : 0
7103 22:54:29.202570 ===================================
7104 22:54:29.205824 [ANA_INIT] >>>>>>>>>>>>>>
7105 22:54:29.208853 <<<<<< [CONFIGURE PHASE]: ANA_TX
7106 22:54:29.212529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7107 22:54:29.215352 ===================================
7108 22:54:29.218807 data_rate = 3200,PCW = 0X7600
7109 22:54:29.218879 ===================================
7110 22:54:29.225240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7111 22:54:29.229046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7112 22:54:29.235786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7113 22:54:29.239143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7114 22:54:29.242539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7115 22:54:29.245058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7116 22:54:29.248583 [ANA_INIT] flow start
7117 22:54:29.252065 [ANA_INIT] PLL >>>>>>>>
7118 22:54:29.252137 [ANA_INIT] PLL <<<<<<<<
7119 22:54:29.255241 [ANA_INIT] MIDPI >>>>>>>>
7120 22:54:29.258631 [ANA_INIT] MIDPI <<<<<<<<
7121 22:54:29.258727 [ANA_INIT] DLL >>>>>>>>
7122 22:54:29.261846 [ANA_INIT] DLL <<<<<<<<
7123 22:54:29.265388 [ANA_INIT] flow end
7124 22:54:29.268579 ============ LP4 DIFF to SE enter ============
7125 22:54:29.271778 ============ LP4 DIFF to SE exit ============
7126 22:54:29.275560 [ANA_INIT] <<<<<<<<<<<<<
7127 22:54:29.278707 [Flow] Enable top DCM control >>>>>
7128 22:54:29.282059 [Flow] Enable top DCM control <<<<<
7129 22:54:29.285775 Enable DLL master slave shuffle
7130 22:54:29.288858 ==============================================================
7131 22:54:29.291726 Gating Mode config
7132 22:54:29.298313 ==============================================================
7133 22:54:29.298428 Config description:
7134 22:54:29.308532 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7135 22:54:29.315418 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7136 22:54:29.318669 SELPH_MODE 0: By rank 1: By Phase
7137 22:54:29.325329 ==============================================================
7138 22:54:29.328748 GAT_TRACK_EN = 1
7139 22:54:29.331628 RX_GATING_MODE = 2
7140 22:54:29.335166 RX_GATING_TRACK_MODE = 2
7141 22:54:29.338038 SELPH_MODE = 1
7142 22:54:29.341487 PICG_EARLY_EN = 1
7143 22:54:29.344975 VALID_LAT_VALUE = 1
7144 22:54:29.348580 ==============================================================
7145 22:54:29.351597 Enter into Gating configuration >>>>
7146 22:54:29.355451 Exit from Gating configuration <<<<
7147 22:54:29.358311 Enter into DVFS_PRE_config >>>>>
7148 22:54:29.368693 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7149 22:54:29.371872 Exit from DVFS_PRE_config <<<<<
7150 22:54:29.374917 Enter into PICG configuration >>>>
7151 22:54:29.378572 Exit from PICG configuration <<<<
7152 22:54:29.381830 [RX_INPUT] configuration >>>>>
7153 22:54:29.385241 [RX_INPUT] configuration <<<<<
7154 22:54:29.391789 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7155 22:54:29.394952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7156 22:54:29.401898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7157 22:54:29.408646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7158 22:54:29.414944 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 22:54:29.421595 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 22:54:29.424778 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7161 22:54:29.428412 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7162 22:54:29.431414 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7163 22:54:29.438177 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7164 22:54:29.441429 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7165 22:54:29.444735 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7166 22:54:29.448026 ===================================
7167 22:54:29.451544 LPDDR4 DRAM CONFIGURATION
7168 22:54:29.454542 ===================================
7169 22:54:29.454633 EX_ROW_EN[0] = 0x0
7170 22:54:29.458386 EX_ROW_EN[1] = 0x0
7171 22:54:29.461703 LP4Y_EN = 0x0
7172 22:54:29.461817 WORK_FSP = 0x1
7173 22:54:29.464752 WL = 0x5
7174 22:54:29.464856 RL = 0x5
7175 22:54:29.468471 BL = 0x2
7176 22:54:29.468572 RPST = 0x0
7177 22:54:29.471436 RD_PRE = 0x0
7178 22:54:29.471535 WR_PRE = 0x1
7179 22:54:29.474785 WR_PST = 0x1
7180 22:54:29.474882 DBI_WR = 0x0
7181 22:54:29.477693 DBI_RD = 0x0
7182 22:54:29.477798 OTF = 0x1
7183 22:54:29.481517 ===================================
7184 22:54:29.484774 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7185 22:54:29.491015 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7186 22:54:29.494791 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 22:54:29.498088 ===================================
7188 22:54:29.501530 LPDDR4 DRAM CONFIGURATION
7189 22:54:29.504460 ===================================
7190 22:54:29.504563 EX_ROW_EN[0] = 0x10
7191 22:54:29.507659 EX_ROW_EN[1] = 0x0
7192 22:54:29.507762 LP4Y_EN = 0x0
7193 22:54:29.510832 WORK_FSP = 0x1
7194 22:54:29.514041 WL = 0x5
7195 22:54:29.514143 RL = 0x5
7196 22:54:29.517304 BL = 0x2
7197 22:54:29.517407 RPST = 0x0
7198 22:54:29.520666 RD_PRE = 0x0
7199 22:54:29.520738 WR_PRE = 0x1
7200 22:54:29.524089 WR_PST = 0x1
7201 22:54:29.524165 DBI_WR = 0x0
7202 22:54:29.527568 DBI_RD = 0x0
7203 22:54:29.527667 OTF = 0x1
7204 22:54:29.530742 ===================================
7205 22:54:29.537793 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7206 22:54:29.537892 ==
7207 22:54:29.540613 Dram Type= 6, Freq= 0, CH_0, rank 0
7208 22:54:29.543797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7209 22:54:29.547205 ==
7210 22:54:29.547305 [Duty_Offset_Calibration]
7211 22:54:29.550546 B0:2 B1:1 CA:1
7212 22:54:29.550643
7213 22:54:29.553949 [DutyScan_Calibration_Flow] k_type=0
7214 22:54:29.562906
7215 22:54:29.563020 ==CLK 0==
7216 22:54:29.566232 Final CLK duty delay cell = 0
7217 22:54:29.569633 [0] MAX Duty = 5156%(X100), DQS PI = 22
7218 22:54:29.572765 [0] MIN Duty = 4876%(X100), DQS PI = 48
7219 22:54:29.572838 [0] AVG Duty = 5016%(X100)
7220 22:54:29.575790
7221 22:54:29.579418 CH0 CLK Duty spec in!! Max-Min= 280%
7222 22:54:29.582794 [DutyScan_Calibration_Flow] ====Done====
7223 22:54:29.582895
7224 22:54:29.586318 [DutyScan_Calibration_Flow] k_type=1
7225 22:54:29.601991
7226 22:54:29.602085 ==DQS 0 ==
7227 22:54:29.605933 Final DQS duty delay cell = -4
7228 22:54:29.608639 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7229 22:54:29.612215 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7230 22:54:29.615196 [-4] AVG Duty = 4891%(X100)
7231 22:54:29.615297
7232 22:54:29.615387 ==DQS 1 ==
7233 22:54:29.618315 Final DQS duty delay cell = 0
7234 22:54:29.621757 [0] MAX Duty = 5187%(X100), DQS PI = 6
7235 22:54:29.624980 [0] MIN Duty = 5031%(X100), DQS PI = 52
7236 22:54:29.628929 [0] AVG Duty = 5109%(X100)
7237 22:54:29.629003
7238 22:54:29.631608 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7239 22:54:29.631677
7240 22:54:29.635323 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7241 22:54:29.638307 [DutyScan_Calibration_Flow] ====Done====
7242 22:54:29.638382
7243 22:54:29.641717 [DutyScan_Calibration_Flow] k_type=3
7244 22:54:29.659443
7245 22:54:29.659555 ==DQM 0 ==
7246 22:54:29.662881 Final DQM duty delay cell = 0
7247 22:54:29.666235 [0] MAX Duty = 5218%(X100), DQS PI = 32
7248 22:54:29.669153 [0] MIN Duty = 4875%(X100), DQS PI = 60
7249 22:54:29.669256 [0] AVG Duty = 5046%(X100)
7250 22:54:29.672555
7251 22:54:29.672623 ==DQM 1 ==
7252 22:54:29.675755 Final DQM duty delay cell = 0
7253 22:54:29.679209 [0] MAX Duty = 5187%(X100), DQS PI = 2
7254 22:54:29.682766 [0] MIN Duty = 5031%(X100), DQS PI = 50
7255 22:54:29.682865 [0] AVG Duty = 5109%(X100)
7256 22:54:29.685970
7257 22:54:29.689470 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7258 22:54:29.689570
7259 22:54:29.692526 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7260 22:54:29.696112 [DutyScan_Calibration_Flow] ====Done====
7261 22:54:29.696195
7262 22:54:29.699349 [DutyScan_Calibration_Flow] k_type=2
7263 22:54:29.716378
7264 22:54:29.716461 ==DQ 0 ==
7265 22:54:29.719887 Final DQ duty delay cell = 0
7266 22:54:29.723014 [0] MAX Duty = 5062%(X100), DQS PI = 26
7267 22:54:29.726192 [0] MIN Duty = 4907%(X100), DQS PI = 0
7268 22:54:29.726265 [0] AVG Duty = 4984%(X100)
7269 22:54:29.726327
7270 22:54:29.729996 ==DQ 1 ==
7271 22:54:29.733104 Final DQ duty delay cell = 0
7272 22:54:29.736056 [0] MAX Duty = 5094%(X100), DQS PI = 4
7273 22:54:29.739221 [0] MIN Duty = 4907%(X100), DQS PI = 34
7274 22:54:29.739302 [0] AVG Duty = 5000%(X100)
7275 22:54:29.739386
7276 22:54:29.743246 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7277 22:54:29.746187
7278 22:54:29.749644 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7279 22:54:29.752815 [DutyScan_Calibration_Flow] ====Done====
7280 22:54:29.752899 ==
7281 22:54:29.756185 Dram Type= 6, Freq= 0, CH_1, rank 0
7282 22:54:29.759567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 22:54:29.759652 ==
7284 22:54:29.762919 [Duty_Offset_Calibration]
7285 22:54:29.763003 B0:1 B1:0 CA:0
7286 22:54:29.763090
7287 22:54:29.766151 [DutyScan_Calibration_Flow] k_type=0
7288 22:54:29.775455
7289 22:54:29.775538 ==CLK 0==
7290 22:54:29.779296 Final CLK duty delay cell = -4
7291 22:54:29.782686 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7292 22:54:29.785724 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7293 22:54:29.788903 [-4] AVG Duty = 4906%(X100)
7294 22:54:29.788985
7295 22:54:29.792118 CH1 CLK Duty spec in!! Max-Min= 125%
7296 22:54:29.795471 [DutyScan_Calibration_Flow] ====Done====
7297 22:54:29.795551
7298 22:54:29.798594 [DutyScan_Calibration_Flow] k_type=1
7299 22:54:29.815865
7300 22:54:29.816078 ==DQS 0 ==
7301 22:54:29.819355 Final DQS duty delay cell = 0
7302 22:54:29.822740 [0] MAX Duty = 5094%(X100), DQS PI = 16
7303 22:54:29.825753 [0] MIN Duty = 4844%(X100), DQS PI = 48
7304 22:54:29.828809 [0] AVG Duty = 4969%(X100)
7305 22:54:29.828931
7306 22:54:29.828999 ==DQS 1 ==
7307 22:54:29.832587 Final DQS duty delay cell = 0
7308 22:54:29.835736 [0] MAX Duty = 5249%(X100), DQS PI = 16
7309 22:54:29.839416 [0] MIN Duty = 4969%(X100), DQS PI = 8
7310 22:54:29.842400 [0] AVG Duty = 5109%(X100)
7311 22:54:29.842482
7312 22:54:29.845544 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7313 22:54:29.845629
7314 22:54:29.848760 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7315 22:54:29.852208 [DutyScan_Calibration_Flow] ====Done====
7316 22:54:29.852289
7317 22:54:29.855072 [DutyScan_Calibration_Flow] k_type=3
7318 22:54:29.872583
7319 22:54:29.872667 ==DQM 0 ==
7320 22:54:29.875793 Final DQM duty delay cell = 0
7321 22:54:29.879804 [0] MAX Duty = 5218%(X100), DQS PI = 18
7322 22:54:29.883003 [0] MIN Duty = 4969%(X100), DQS PI = 48
7323 22:54:29.886353 [0] AVG Duty = 5093%(X100)
7324 22:54:29.886434
7325 22:54:29.886498 ==DQM 1 ==
7326 22:54:29.889717 Final DQM duty delay cell = 0
7327 22:54:29.892779 [0] MAX Duty = 5093%(X100), DQS PI = 16
7328 22:54:29.895927 [0] MIN Duty = 4907%(X100), DQS PI = 34
7329 22:54:29.896073 [0] AVG Duty = 5000%(X100)
7330 22:54:29.899529
7331 22:54:29.902959 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7332 22:54:29.903040
7333 22:54:29.906227 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7334 22:54:29.909375 [DutyScan_Calibration_Flow] ====Done====
7335 22:54:29.909458
7336 22:54:29.912868 [DutyScan_Calibration_Flow] k_type=2
7337 22:54:29.928695
7338 22:54:29.928776 ==DQ 0 ==
7339 22:54:29.931709 Final DQ duty delay cell = -4
7340 22:54:29.935630 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7341 22:54:29.938919 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7342 22:54:29.942016 [-4] AVG Duty = 4968%(X100)
7343 22:54:29.942098
7344 22:54:29.942164 ==DQ 1 ==
7345 22:54:29.945338 Final DQ duty delay cell = 0
7346 22:54:29.948664 [0] MAX Duty = 5124%(X100), DQS PI = 16
7347 22:54:29.952635 [0] MIN Duty = 4938%(X100), DQS PI = 8
7348 22:54:29.952716 [0] AVG Duty = 5031%(X100)
7349 22:54:29.952781
7350 22:54:29.959145 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7351 22:54:29.959227
7352 22:54:29.962492 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7353 22:54:29.965660 [DutyScan_Calibration_Flow] ====Done====
7354 22:54:29.968656 nWR fixed to 30
7355 22:54:29.968741 [ModeRegInit_LP4] CH0 RK0
7356 22:54:29.972236 [ModeRegInit_LP4] CH0 RK1
7357 22:54:29.975251 [ModeRegInit_LP4] CH1 RK0
7358 22:54:29.978849 [ModeRegInit_LP4] CH1 RK1
7359 22:54:29.978933 match AC timing 5
7360 22:54:29.982108 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7361 22:54:29.988784 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7362 22:54:29.992161 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7363 22:54:29.998781 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7364 22:54:30.002007 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7365 22:54:30.002092 [MiockJmeterHQA]
7366 22:54:30.002179
7367 22:54:30.005071 [DramcMiockJmeter] u1RxGatingPI = 0
7368 22:54:30.008377 0 : 4252, 4027
7369 22:54:30.008463 4 : 4257, 4027
7370 22:54:30.011799 8 : 4253, 4027
7371 22:54:30.011884 12 : 4252, 4026
7372 22:54:30.012013 16 : 4253, 4026
7373 22:54:30.014923 20 : 4368, 4140
7374 22:54:30.015008 24 : 4252, 4027
7375 22:54:30.018160 28 : 4363, 4138
7376 22:54:30.018246 32 : 4255, 4030
7377 22:54:30.021436 36 : 4253, 4026
7378 22:54:30.021522 40 : 4250, 4026
7379 22:54:30.024736 44 : 4361, 4137
7380 22:54:30.024821 48 : 4250, 4026
7381 22:54:30.024908 52 : 4252, 4027
7382 22:54:30.028077 56 : 4250, 4027
7383 22:54:30.028162 60 : 4250, 4026
7384 22:54:30.031838 64 : 4250, 4027
7385 22:54:30.031949 68 : 4249, 4027
7386 22:54:30.034991 72 : 4252, 4027
7387 22:54:30.035101 76 : 4250, 4027
7388 22:54:30.038343 80 : 4250, 4026
7389 22:54:30.038428 84 : 4250, 4027
7390 22:54:30.038515 88 : 4249, 124
7391 22:54:30.041362 92 : 4360, 0
7392 22:54:30.041448 96 : 4250, 0
7393 22:54:30.041533 100 : 4253, 0
7394 22:54:30.045303 104 : 4250, 0
7395 22:54:30.045389 108 : 4250, 0
7396 22:54:30.048478 112 : 4250, 0
7397 22:54:30.048589 116 : 4252, 0
7398 22:54:30.048693 120 : 4250, 0
7399 22:54:30.051570 124 : 4250, 0
7400 22:54:30.051682 128 : 4252, 0
7401 22:54:30.054753 132 : 4361, 0
7402 22:54:30.054839 136 : 4250, 0
7403 22:54:30.054943 140 : 4360, 0
7404 22:54:30.058117 144 : 4252, 0
7405 22:54:30.058203 148 : 4360, 0
7406 22:54:30.061757 152 : 4363, 0
7407 22:54:30.061842 156 : 4250, 0
7408 22:54:30.061929 160 : 4250, 0
7409 22:54:30.064745 164 : 4250, 0
7410 22:54:30.064830 168 : 4253, 0
7411 22:54:30.064916 172 : 4249, 0
7412 22:54:30.068114 176 : 4250, 0
7413 22:54:30.068200 180 : 4252, 0
7414 22:54:30.071423 184 : 4362, 0
7415 22:54:30.071508 188 : 4250, 0
7416 22:54:30.071594 192 : 4250, 0
7417 22:54:30.074681 196 : 4255, 0
7418 22:54:30.074766 200 : 4250, 0
7419 22:54:30.078457 204 : 4363, 1401
7420 22:54:30.078539 208 : 4361, 4115
7421 22:54:30.081757 212 : 4250, 4027
7422 22:54:30.081840 216 : 4250, 4027
7423 22:54:30.084531 220 : 4363, 4140
7424 22:54:30.084614 224 : 4250, 4027
7425 22:54:30.084680 228 : 4252, 4027
7426 22:54:30.088420 232 : 4250, 4027
7427 22:54:30.088502 236 : 4255, 4032
7428 22:54:30.091513 240 : 4250, 4027
7429 22:54:30.091596 244 : 4250, 4027
7430 22:54:30.095103 248 : 4361, 4137
7431 22:54:30.095185 252 : 4250, 4026
7432 22:54:30.098127 256 : 4361, 4137
7433 22:54:30.098209 260 : 4361, 4137
7434 22:54:30.101738 264 : 4252, 4027
7435 22:54:30.101821 268 : 4252, 4026
7436 22:54:30.105191 272 : 4363, 4140
7437 22:54:30.105273 276 : 4250, 4027
7438 22:54:30.108298 280 : 4250, 4027
7439 22:54:30.108381 284 : 4250, 4027
7440 22:54:30.108448 288 : 4253, 4029
7441 22:54:30.111636 292 : 4250, 4026
7442 22:54:30.111746 296 : 4360, 4138
7443 22:54:30.114630 300 : 4360, 4138
7444 22:54:30.114741 304 : 4250, 4026
7445 22:54:30.118117 308 : 4250, 3952
7446 22:54:30.118228 312 : 4250, 1900
7447 22:54:30.118370
7448 22:54:30.121258 MIOCK jitter meter ch=0
7449 22:54:30.121353
7450 22:54:30.124519 1T = (312-88) = 224 dly cells
7451 22:54:30.131131 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7452 22:54:30.131218 ==
7453 22:54:30.134961 Dram Type= 6, Freq= 0, CH_0, rank 0
7454 22:54:30.138014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7455 22:54:30.138100 ==
7456 22:54:30.144965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7457 22:54:30.148239 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7458 22:54:30.151666 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7459 22:54:30.157756 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7460 22:54:30.166149 [CA 0] Center 42 (12~73) winsize 62
7461 22:54:30.169353 [CA 1] Center 42 (12~73) winsize 62
7462 22:54:30.172890 [CA 2] Center 37 (7~67) winsize 61
7463 22:54:30.176097 [CA 3] Center 37 (7~67) winsize 61
7464 22:54:30.179494 [CA 4] Center 36 (6~66) winsize 61
7465 22:54:30.182857 [CA 5] Center 35 (6~64) winsize 59
7466 22:54:30.182941
7467 22:54:30.186344 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7468 22:54:30.186428
7469 22:54:30.189481 [CATrainingPosCal] consider 1 rank data
7470 22:54:30.192700 u2DelayCellTimex100 = 290/100 ps
7471 22:54:30.199748 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7472 22:54:30.202829 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7473 22:54:30.206245 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7474 22:54:30.209480 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7475 22:54:30.212719 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7476 22:54:30.215980 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7477 22:54:30.216076
7478 22:54:30.219530 CA PerBit enable=1, Macro0, CA PI delay=35
7479 22:54:30.219611
7480 22:54:30.223118 [CBTSetCACLKResult] CA Dly = 35
7481 22:54:30.226133 CS Dly: 9 (0~40)
7482 22:54:30.229402 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7483 22:54:30.232861 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7484 22:54:30.232943 ==
7485 22:54:30.236015 Dram Type= 6, Freq= 0, CH_0, rank 1
7486 22:54:30.239369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 22:54:30.239456 ==
7488 22:54:30.245837 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 22:54:30.249520 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 22:54:30.255851 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 22:54:30.259597 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 22:54:30.269848 [CA 0] Center 42 (12~73) winsize 62
7493 22:54:30.273050 [CA 1] Center 42 (12~73) winsize 62
7494 22:54:30.276454 [CA 2] Center 38 (8~68) winsize 61
7495 22:54:30.279845 [CA 3] Center 37 (7~67) winsize 61
7496 22:54:30.282808 [CA 4] Center 36 (6~66) winsize 61
7497 22:54:30.286219 [CA 5] Center 35 (5~65) winsize 61
7498 22:54:30.286330
7499 22:54:30.289421 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7500 22:54:30.289499
7501 22:54:30.293148 [CATrainingPosCal] consider 2 rank data
7502 22:54:30.295871 u2DelayCellTimex100 = 290/100 ps
7503 22:54:30.299241 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7504 22:54:30.306286 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7505 22:54:30.309625 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7506 22:54:30.313211 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7507 22:54:30.316418 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7508 22:54:30.319090 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7509 22:54:30.319175
7510 22:54:30.323078 CA PerBit enable=1, Macro0, CA PI delay=35
7511 22:54:30.323163
7512 22:54:30.326409 [CBTSetCACLKResult] CA Dly = 35
7513 22:54:30.329730 CS Dly: 10 (0~42)
7514 22:54:30.333091 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 22:54:30.336518 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 22:54:30.336602
7517 22:54:30.339715 ----->DramcWriteLeveling(PI) begin...
7518 22:54:30.339801 ==
7519 22:54:30.342873 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 22:54:30.345897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 22:54:30.349355 ==
7522 22:54:30.349458 Write leveling (Byte 0): 35 => 35
7523 22:54:30.352808 Write leveling (Byte 1): 29 => 29
7524 22:54:30.355832 DramcWriteLeveling(PI) end<-----
7525 22:54:30.355941
7526 22:54:30.356068 ==
7527 22:54:30.359583 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 22:54:30.366223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 22:54:30.366308 ==
7530 22:54:30.366395 [Gating] SW mode calibration
7531 22:54:30.375926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7532 22:54:30.379647 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7533 22:54:30.382369 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7534 22:54:30.389069 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7535 22:54:30.392780 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7536 22:54:30.395836 1 4 12 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
7537 22:54:30.402505 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7538 22:54:30.405834 1 4 20 | B1->B0 | 3333 3535 | 1 0 | (0 0) (0 0)
7539 22:54:30.409079 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7540 22:54:30.416295 1 4 28 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7541 22:54:30.419287 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7542 22:54:30.422276 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7543 22:54:30.428950 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7544 22:54:30.432489 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7545 22:54:30.436349 1 5 16 | B1->B0 | 3434 2423 | 0 1 | (0 0) (1 0)
7546 22:54:30.442303 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7547 22:54:30.445874 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7548 22:54:30.449736 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 22:54:30.455828 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7550 22:54:30.458957 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7551 22:54:30.462640 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7552 22:54:30.469320 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7553 22:54:30.472644 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7554 22:54:30.475339 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7555 22:54:30.482463 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 22:54:30.485349 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 22:54:30.488947 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 22:54:30.495370 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 22:54:30.499136 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 22:54:30.502044 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7561 22:54:30.508493 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7562 22:54:30.512135 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7563 22:54:30.515245 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7564 22:54:30.522409 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 22:54:30.525245 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 22:54:30.528751 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 22:54:30.534958 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 22:54:30.538488 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 22:54:30.541739 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 22:54:30.548402 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 22:54:30.551923 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 22:54:30.554947 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 22:54:30.561406 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 22:54:30.565265 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 22:54:30.568154 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7576 22:54:30.574641 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7577 22:54:30.577956 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7578 22:54:30.581863 Total UI for P1: 0, mck2ui 16
7579 22:54:30.584789 best dqsien dly found for B0: ( 1, 9, 10)
7580 22:54:30.588017 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7581 22:54:30.591125 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 22:54:30.594542 Total UI for P1: 0, mck2ui 16
7583 22:54:30.598217 best dqsien dly found for B1: ( 1, 9, 20)
7584 22:54:30.601672 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7585 22:54:30.604857 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7586 22:54:30.608102
7587 22:54:30.611603 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7588 22:54:30.614808 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7589 22:54:30.618117 [Gating] SW calibration Done
7590 22:54:30.618198 ==
7591 22:54:30.621316 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 22:54:30.624740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 22:54:30.624823 ==
7594 22:54:30.628439 RX Vref Scan: 0
7595 22:54:30.628521
7596 22:54:30.628585 RX Vref 0 -> 0, step: 1
7597 22:54:30.628646
7598 22:54:30.631900 RX Delay 0 -> 252, step: 8
7599 22:54:30.634462 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7600 22:54:30.637923 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7601 22:54:30.644474 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7602 22:54:30.648165 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7603 22:54:30.651560 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7604 22:54:30.654383 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7605 22:54:30.657577 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7606 22:54:30.664789 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7607 22:54:30.668097 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7608 22:54:30.671166 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7609 22:54:30.674337 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7610 22:54:30.677959 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7611 22:54:30.684712 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7612 22:54:30.688085 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7613 22:54:30.691266 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7614 22:54:30.694634 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7615 22:54:30.694731 ==
7616 22:54:30.697740 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 22:54:30.704441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 22:54:30.704525 ==
7619 22:54:30.704606 DQS Delay:
7620 22:54:30.704729 DQS0 = 0, DQS1 = 0
7621 22:54:30.707703 DQM Delay:
7622 22:54:30.707772 DQM0 = 136, DQM1 = 129
7623 22:54:30.711468 DQ Delay:
7624 22:54:30.714877 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7625 22:54:30.717550 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7626 22:54:30.720845 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7627 22:54:30.724102 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
7628 22:54:30.724174
7629 22:54:30.724235
7630 22:54:30.724293 ==
7631 22:54:30.727532 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 22:54:30.730887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 22:54:30.734048 ==
7634 22:54:30.734144
7635 22:54:30.734231
7636 22:54:30.734317 TX Vref Scan disable
7637 22:54:30.737337 == TX Byte 0 ==
7638 22:54:30.740776 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7639 22:54:30.744769 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7640 22:54:30.747574 == TX Byte 1 ==
7641 22:54:30.751313 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7642 22:54:30.754233 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7643 22:54:30.754333 ==
7644 22:54:30.757360 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 22:54:30.764131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 22:54:30.764208 ==
7647 22:54:30.776455
7648 22:54:30.779780 TX Vref early break, caculate TX vref
7649 22:54:30.783276 TX Vref=16, minBit 0, minWin=23, winSum=381
7650 22:54:30.786606 TX Vref=18, minBit 9, minWin=23, winSum=394
7651 22:54:30.789803 TX Vref=20, minBit 0, minWin=24, winSum=400
7652 22:54:30.793191 TX Vref=22, minBit 0, minWin=25, winSum=412
7653 22:54:30.796487 TX Vref=24, minBit 7, minWin=25, winSum=421
7654 22:54:30.803072 TX Vref=26, minBit 1, minWin=25, winSum=421
7655 22:54:30.806594 TX Vref=28, minBit 0, minWin=25, winSum=423
7656 22:54:30.810168 TX Vref=30, minBit 1, minWin=24, winSum=411
7657 22:54:30.813137 TX Vref=32, minBit 1, minWin=23, winSum=402
7658 22:54:30.816393 TX Vref=34, minBit 6, minWin=23, winSum=392
7659 22:54:30.822888 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
7660 22:54:30.822972
7661 22:54:30.826257 Final TX Range 0 Vref 28
7662 22:54:30.826339
7663 22:54:30.826404 ==
7664 22:54:30.829577 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 22:54:30.832865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 22:54:30.832947 ==
7667 22:54:30.833011
7668 22:54:30.833071
7669 22:54:30.836216 TX Vref Scan disable
7670 22:54:30.842708 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7671 22:54:30.842790 == TX Byte 0 ==
7672 22:54:30.846413 u2DelayCellOfst[0]=10 cells (3 PI)
7673 22:54:30.849369 u2DelayCellOfst[1]=16 cells (5 PI)
7674 22:54:30.852851 u2DelayCellOfst[2]=10 cells (3 PI)
7675 22:54:30.856179 u2DelayCellOfst[3]=10 cells (3 PI)
7676 22:54:30.859540 u2DelayCellOfst[4]=6 cells (2 PI)
7677 22:54:30.862775 u2DelayCellOfst[5]=0 cells (0 PI)
7678 22:54:30.866243 u2DelayCellOfst[6]=16 cells (5 PI)
7679 22:54:30.869367 u2DelayCellOfst[7]=16 cells (5 PI)
7680 22:54:30.872680 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7681 22:54:30.876364 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7682 22:54:30.879743 == TX Byte 1 ==
7683 22:54:30.879840 u2DelayCellOfst[8]=3 cells (1 PI)
7684 22:54:30.882862 u2DelayCellOfst[9]=0 cells (0 PI)
7685 22:54:30.886110 u2DelayCellOfst[10]=6 cells (2 PI)
7686 22:54:30.889727 u2DelayCellOfst[11]=3 cells (1 PI)
7687 22:54:30.892895 u2DelayCellOfst[12]=10 cells (3 PI)
7688 22:54:30.896448 u2DelayCellOfst[13]=10 cells (3 PI)
7689 22:54:30.899513 u2DelayCellOfst[14]=13 cells (4 PI)
7690 22:54:30.902654 u2DelayCellOfst[15]=10 cells (3 PI)
7691 22:54:30.905679 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7692 22:54:30.912798 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7693 22:54:30.912896 DramC Write-DBI on
7694 22:54:30.912991 ==
7695 22:54:30.915828 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 22:54:30.919140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 22:54:30.922490 ==
7698 22:54:30.922587
7699 22:54:30.922668
7700 22:54:30.922728 TX Vref Scan disable
7701 22:54:30.926316 == TX Byte 0 ==
7702 22:54:30.929312 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7703 22:54:30.932653 == TX Byte 1 ==
7704 22:54:30.935927 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7705 22:54:30.936100 DramC Write-DBI off
7706 22:54:30.939136
7707 22:54:30.939217 [DATLAT]
7708 22:54:30.939281 Freq=1600, CH0 RK0
7709 22:54:30.939342
7710 22:54:30.942591 DATLAT Default: 0xf
7711 22:54:30.942672 0, 0xFFFF, sum = 0
7712 22:54:30.945669 1, 0xFFFF, sum = 0
7713 22:54:30.945768 2, 0xFFFF, sum = 0
7714 22:54:30.949081 3, 0xFFFF, sum = 0
7715 22:54:30.952422 4, 0xFFFF, sum = 0
7716 22:54:30.952505 5, 0xFFFF, sum = 0
7717 22:54:30.955676 6, 0xFFFF, sum = 0
7718 22:54:30.955758 7, 0xFFFF, sum = 0
7719 22:54:30.959045 8, 0xFFFF, sum = 0
7720 22:54:30.959127 9, 0xFFFF, sum = 0
7721 22:54:30.962316 10, 0xFFFF, sum = 0
7722 22:54:30.962398 11, 0xFFFF, sum = 0
7723 22:54:30.966115 12, 0xFFFF, sum = 0
7724 22:54:30.966198 13, 0xFFFF, sum = 0
7725 22:54:30.969359 14, 0x0, sum = 1
7726 22:54:30.969442 15, 0x0, sum = 2
7727 22:54:30.972667 16, 0x0, sum = 3
7728 22:54:30.972749 17, 0x0, sum = 4
7729 22:54:30.976017 best_step = 15
7730 22:54:30.976112
7731 22:54:30.976177 ==
7732 22:54:30.979254 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 22:54:30.982550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 22:54:30.982659 ==
7735 22:54:30.982753 RX Vref Scan: 1
7736 22:54:30.985636
7737 22:54:30.985734 Set Vref Range= 24 -> 127
7738 22:54:30.985824
7739 22:54:30.989190 RX Vref 24 -> 127, step: 1
7740 22:54:30.989266
7741 22:54:30.992540 RX Delay 19 -> 252, step: 4
7742 22:54:30.992640
7743 22:54:30.995947 Set Vref, RX VrefLevel [Byte0]: 24
7744 22:54:30.999172 [Byte1]: 24
7745 22:54:30.999245
7746 22:54:31.002538 Set Vref, RX VrefLevel [Byte0]: 25
7747 22:54:31.005975 [Byte1]: 25
7748 22:54:31.006072
7749 22:54:31.009348 Set Vref, RX VrefLevel [Byte0]: 26
7750 22:54:31.012788 [Byte1]: 26
7751 22:54:31.016262
7752 22:54:31.016362 Set Vref, RX VrefLevel [Byte0]: 27
7753 22:54:31.019376 [Byte1]: 27
7754 22:54:31.024007
7755 22:54:31.024102 Set Vref, RX VrefLevel [Byte0]: 28
7756 22:54:31.027366 [Byte1]: 28
7757 22:54:31.031329
7758 22:54:31.031410 Set Vref, RX VrefLevel [Byte0]: 29
7759 22:54:31.034535 [Byte1]: 29
7760 22:54:31.039009
7761 22:54:31.039089 Set Vref, RX VrefLevel [Byte0]: 30
7762 22:54:31.042197 [Byte1]: 30
7763 22:54:31.046873
7764 22:54:31.046954 Set Vref, RX VrefLevel [Byte0]: 31
7765 22:54:31.050235 [Byte1]: 31
7766 22:54:31.053882
7767 22:54:31.053962 Set Vref, RX VrefLevel [Byte0]: 32
7768 22:54:31.057385 [Byte1]: 32
7769 22:54:31.061835
7770 22:54:31.061916 Set Vref, RX VrefLevel [Byte0]: 33
7771 22:54:31.064874 [Byte1]: 33
7772 22:54:31.069314
7773 22:54:31.069394 Set Vref, RX VrefLevel [Byte0]: 34
7774 22:54:31.072691 [Byte1]: 34
7775 22:54:31.077252
7776 22:54:31.077334 Set Vref, RX VrefLevel [Byte0]: 35
7777 22:54:31.080384 [Byte1]: 35
7778 22:54:31.084488
7779 22:54:31.084569 Set Vref, RX VrefLevel [Byte0]: 36
7780 22:54:31.087720 [Byte1]: 36
7781 22:54:31.092219
7782 22:54:31.094926 Set Vref, RX VrefLevel [Byte0]: 37
7783 22:54:31.098731 [Byte1]: 37
7784 22:54:31.098815
7785 22:54:31.101885 Set Vref, RX VrefLevel [Byte0]: 38
7786 22:54:31.105225 [Byte1]: 38
7787 22:54:31.105307
7788 22:54:31.108444 Set Vref, RX VrefLevel [Byte0]: 39
7789 22:54:31.111751 [Byte1]: 39
7790 22:54:31.111832
7791 22:54:31.115121 Set Vref, RX VrefLevel [Byte0]: 40
7792 22:54:31.118388 [Byte1]: 40
7793 22:54:31.122294
7794 22:54:31.122375 Set Vref, RX VrefLevel [Byte0]: 41
7795 22:54:31.125613 [Byte1]: 41
7796 22:54:31.129570
7797 22:54:31.129651 Set Vref, RX VrefLevel [Byte0]: 42
7798 22:54:31.133071 [Byte1]: 42
7799 22:54:31.137724
7800 22:54:31.137805 Set Vref, RX VrefLevel [Byte0]: 43
7801 22:54:31.140817 [Byte1]: 43
7802 22:54:31.144807
7803 22:54:31.144910 Set Vref, RX VrefLevel [Byte0]: 44
7804 22:54:31.148167 [Byte1]: 44
7805 22:54:31.152492
7806 22:54:31.152598 Set Vref, RX VrefLevel [Byte0]: 45
7807 22:54:31.155519 [Byte1]: 45
7808 22:54:31.160096
7809 22:54:31.160204 Set Vref, RX VrefLevel [Byte0]: 46
7810 22:54:31.163465 [Byte1]: 46
7811 22:54:31.167941
7812 22:54:31.168085 Set Vref, RX VrefLevel [Byte0]: 47
7813 22:54:31.171077 [Byte1]: 47
7814 22:54:31.175243
7815 22:54:31.175346 Set Vref, RX VrefLevel [Byte0]: 48
7816 22:54:31.178674 [Byte1]: 48
7817 22:54:31.182876
7818 22:54:31.182976 Set Vref, RX VrefLevel [Byte0]: 49
7819 22:54:31.185947 [Byte1]: 49
7820 22:54:31.190417
7821 22:54:31.190520 Set Vref, RX VrefLevel [Byte0]: 50
7822 22:54:31.193642 [Byte1]: 50
7823 22:54:31.198337
7824 22:54:31.198439 Set Vref, RX VrefLevel [Byte0]: 51
7825 22:54:31.201803 [Byte1]: 51
7826 22:54:31.205312
7827 22:54:31.205412 Set Vref, RX VrefLevel [Byte0]: 52
7828 22:54:31.209045 [Byte1]: 52
7829 22:54:31.212809
7830 22:54:31.212883 Set Vref, RX VrefLevel [Byte0]: 53
7831 22:54:31.216242 [Byte1]: 53
7832 22:54:31.220676
7833 22:54:31.220761 Set Vref, RX VrefLevel [Byte0]: 54
7834 22:54:31.227277 [Byte1]: 54
7835 22:54:31.227356
7836 22:54:31.230452 Set Vref, RX VrefLevel [Byte0]: 55
7837 22:54:31.233861 [Byte1]: 55
7838 22:54:31.233963
7839 22:54:31.237161 Set Vref, RX VrefLevel [Byte0]: 56
7840 22:54:31.240507 [Byte1]: 56
7841 22:54:31.240608
7842 22:54:31.244039 Set Vref, RX VrefLevel [Byte0]: 57
7843 22:54:31.247258 [Byte1]: 57
7844 22:54:31.251261
7845 22:54:31.251361 Set Vref, RX VrefLevel [Byte0]: 58
7846 22:54:31.254463 [Byte1]: 58
7847 22:54:31.258330
7848 22:54:31.258430 Set Vref, RX VrefLevel [Byte0]: 59
7849 22:54:31.262087 [Byte1]: 59
7850 22:54:31.266014
7851 22:54:31.266090 Set Vref, RX VrefLevel [Byte0]: 60
7852 22:54:31.269164 [Byte1]: 60
7853 22:54:31.273715
7854 22:54:31.273804 Set Vref, RX VrefLevel [Byte0]: 61
7855 22:54:31.277160 [Byte1]: 61
7856 22:54:31.281215
7857 22:54:31.281321 Set Vref, RX VrefLevel [Byte0]: 62
7858 22:54:31.284395 [Byte1]: 62
7859 22:54:31.288796
7860 22:54:31.288870 Set Vref, RX VrefLevel [Byte0]: 63
7861 22:54:31.291869 [Byte1]: 63
7862 22:54:31.296368
7863 22:54:31.296470 Set Vref, RX VrefLevel [Byte0]: 64
7864 22:54:31.299568 [Byte1]: 64
7865 22:54:31.304258
7866 22:54:31.304333 Set Vref, RX VrefLevel [Byte0]: 65
7867 22:54:31.307117 [Byte1]: 65
7868 22:54:31.311527
7869 22:54:31.311634 Set Vref, RX VrefLevel [Byte0]: 66
7870 22:54:31.314691 [Byte1]: 66
7871 22:54:31.319001
7872 22:54:31.319110 Set Vref, RX VrefLevel [Byte0]: 67
7873 22:54:31.325990 [Byte1]: 67
7874 22:54:31.326081
7875 22:54:31.328793 Set Vref, RX VrefLevel [Byte0]: 68
7876 22:54:31.332089 [Byte1]: 68
7877 22:54:31.332163
7878 22:54:31.335361 Set Vref, RX VrefLevel [Byte0]: 69
7879 22:54:31.338587 [Byte1]: 69
7880 22:54:31.338687
7881 22:54:31.342143 Set Vref, RX VrefLevel [Byte0]: 70
7882 22:54:31.345588 [Byte1]: 70
7883 22:54:31.349425
7884 22:54:31.349523 Set Vref, RX VrefLevel [Byte0]: 71
7885 22:54:31.352415 [Byte1]: 71
7886 22:54:31.356777
7887 22:54:31.356859 Set Vref, RX VrefLevel [Byte0]: 72
7888 22:54:31.360719 [Byte1]: 72
7889 22:54:31.364542
7890 22:54:31.364624 Set Vref, RX VrefLevel [Byte0]: 73
7891 22:54:31.367654 [Byte1]: 73
7892 22:54:31.371915
7893 22:54:31.372045 Set Vref, RX VrefLevel [Byte0]: 74
7894 22:54:31.375501 [Byte1]: 74
7895 22:54:31.379535
7896 22:54:31.379616 Set Vref, RX VrefLevel [Byte0]: 75
7897 22:54:31.382880 [Byte1]: 75
7898 22:54:31.387493
7899 22:54:31.387574 Set Vref, RX VrefLevel [Byte0]: 76
7900 22:54:31.390864 [Byte1]: 76
7901 22:54:31.394857
7902 22:54:31.394938 Set Vref, RX VrefLevel [Byte0]: 77
7903 22:54:31.398499 [Byte1]: 77
7904 22:54:31.402393
7905 22:54:31.402489 Final RX Vref Byte 0 = 56 to rank0
7906 22:54:31.406428 Final RX Vref Byte 1 = 62 to rank0
7907 22:54:31.408898 Final RX Vref Byte 0 = 56 to rank1
7908 22:54:31.412178 Final RX Vref Byte 1 = 62 to rank1==
7909 22:54:31.415518 Dram Type= 6, Freq= 0, CH_0, rank 0
7910 22:54:31.422511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7911 22:54:31.422594 ==
7912 22:54:31.422667 DQS Delay:
7913 22:54:31.425692 DQS0 = 0, DQS1 = 0
7914 22:54:31.425774 DQM Delay:
7915 22:54:31.425838 DQM0 = 133, DQM1 = 127
7916 22:54:31.428962 DQ Delay:
7917 22:54:31.432280 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7918 22:54:31.435619 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7919 22:54:31.438959 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7920 22:54:31.442229 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =134
7921 22:54:31.442311
7922 22:54:31.442376
7923 22:54:31.442435
7924 22:54:31.445530 [DramC_TX_OE_Calibration] TA2
7925 22:54:31.448746 Original DQ_B0 (3 6) =30, OEN = 27
7926 22:54:31.452424 Original DQ_B1 (3 6) =30, OEN = 27
7927 22:54:31.455196 24, 0x0, End_B0=24 End_B1=24
7928 22:54:31.455294 25, 0x0, End_B0=25 End_B1=25
7929 22:54:31.458832 26, 0x0, End_B0=26 End_B1=26
7930 22:54:31.462060 27, 0x0, End_B0=27 End_B1=27
7931 22:54:31.465579 28, 0x0, End_B0=28 End_B1=28
7932 22:54:31.468483 29, 0x0, End_B0=29 End_B1=29
7933 22:54:31.468606 30, 0x0, End_B0=30 End_B1=30
7934 22:54:31.471786 31, 0x4141, End_B0=30 End_B1=30
7935 22:54:31.475514 Byte0 end_step=30 best_step=27
7936 22:54:31.479126 Byte1 end_step=30 best_step=27
7937 22:54:31.481901 Byte0 TX OE(2T, 0.5T) = (3, 3)
7938 22:54:31.485211 Byte1 TX OE(2T, 0.5T) = (3, 3)
7939 22:54:31.485297
7940 22:54:31.485362
7941 22:54:31.492539 [DQSOSCAuto] RK0, (LSB)MR18= 0x2823, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
7942 22:54:31.495292 CH0 RK0: MR19=303, MR18=2823
7943 22:54:31.501981 CH0_RK0: MR19=0x303, MR18=0x2823, DQSOSC=389, MR23=63, INC=24, DEC=16
7944 22:54:31.502079
7945 22:54:31.505679 ----->DramcWriteLeveling(PI) begin...
7946 22:54:31.505762 ==
7947 22:54:31.508533 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 22:54:31.511884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 22:54:31.512024 ==
7950 22:54:31.515239 Write leveling (Byte 0): 34 => 34
7951 22:54:31.519066 Write leveling (Byte 1): 27 => 27
7952 22:54:31.521687 DramcWriteLeveling(PI) end<-----
7953 22:54:31.521768
7954 22:54:31.521871 ==
7955 22:54:31.525728 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 22:54:31.528756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 22:54:31.528855 ==
7958 22:54:31.532089 [Gating] SW mode calibration
7959 22:54:31.538718 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7960 22:54:31.545305 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7961 22:54:31.548174 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7962 22:54:31.551905 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7963 22:54:31.558345 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7964 22:54:31.561837 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7965 22:54:31.565230 1 4 16 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7966 22:54:31.571784 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7967 22:54:31.574955 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7968 22:54:31.578244 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7969 22:54:31.584925 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7970 22:54:31.588300 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7971 22:54:31.591568 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7972 22:54:31.598393 1 5 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
7973 22:54:31.601725 1 5 16 | B1->B0 | 3030 2626 | 0 0 | (0 1) (1 0)
7974 22:54:31.604870 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7975 22:54:31.611617 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7976 22:54:31.614679 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7977 22:54:31.618232 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7978 22:54:31.624772 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7979 22:54:31.628231 1 6 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7980 22:54:31.631792 1 6 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7981 22:54:31.638566 1 6 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7982 22:54:31.641759 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7983 22:54:31.644760 1 6 24 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
7984 22:54:31.651969 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 22:54:31.655171 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 22:54:31.658504 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 22:54:31.661825 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 22:54:31.667965 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 22:54:31.671740 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7990 22:54:31.675206 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 22:54:31.681639 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 22:54:31.684489 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 22:54:31.687889 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 22:54:31.694599 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 22:54:31.697826 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 22:54:31.701399 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 22:54:31.708425 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 22:54:31.711325 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 22:54:31.715288 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 22:54:31.721767 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 22:54:31.724771 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 22:54:31.727998 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 22:54:31.734678 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8004 22:54:31.737920 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8005 22:54:31.741162 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8006 22:54:31.747856 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 22:54:31.747987 Total UI for P1: 0, mck2ui 16
8008 22:54:31.754581 best dqsien dly found for B0: ( 1, 9, 12)
8009 22:54:31.754685 Total UI for P1: 0, mck2ui 16
8010 22:54:31.761166 best dqsien dly found for B1: ( 1, 9, 12)
8011 22:54:31.764745 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8012 22:54:31.768145 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8013 22:54:31.768218
8014 22:54:31.771032 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8015 22:54:31.774545 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8016 22:54:31.777808 [Gating] SW calibration Done
8017 22:54:31.777907 ==
8018 22:54:31.781130 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 22:54:31.784498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 22:54:31.784597 ==
8021 22:54:31.788037 RX Vref Scan: 0
8022 22:54:31.788136
8023 22:54:31.788200 RX Vref 0 -> 0, step: 1
8024 22:54:31.788286
8025 22:54:31.791084 RX Delay 0 -> 252, step: 8
8026 22:54:31.794474 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8027 22:54:31.801476 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8028 22:54:31.804710 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8029 22:54:31.807368 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8030 22:54:31.810644 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8031 22:54:31.814108 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8032 22:54:31.820713 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8033 22:54:31.824508 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8034 22:54:31.827208 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8035 22:54:31.831164 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8036 22:54:31.834343 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8037 22:54:31.840986 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8038 22:54:31.844508 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8039 22:54:31.847636 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8040 22:54:31.851050 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8041 22:54:31.854323 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8042 22:54:31.857500 ==
8043 22:54:31.857599 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 22:54:31.863805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 22:54:31.863934 ==
8046 22:54:31.864057 DQS Delay:
8047 22:54:31.867045 DQS0 = 0, DQS1 = 0
8048 22:54:31.867121 DQM Delay:
8049 22:54:31.870986 DQM0 = 137, DQM1 = 128
8050 22:54:31.871085 DQ Delay:
8051 22:54:31.873765 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
8052 22:54:31.877200 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8053 22:54:31.880442 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8054 22:54:31.884237 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8055 22:54:31.884338
8056 22:54:31.884426
8057 22:54:31.884512 ==
8058 22:54:31.887063 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 22:54:31.893893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 22:54:31.894002 ==
8061 22:54:31.894096
8062 22:54:31.894184
8063 22:54:31.894279 TX Vref Scan disable
8064 22:54:31.897846 == TX Byte 0 ==
8065 22:54:31.900696 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8066 22:54:31.907857 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8067 22:54:31.907966 == TX Byte 1 ==
8068 22:54:31.910847 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8069 22:54:31.917290 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8070 22:54:31.917405 ==
8071 22:54:31.920667 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 22:54:31.923748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 22:54:31.923844 ==
8074 22:54:31.937408
8075 22:54:31.940655 TX Vref early break, caculate TX vref
8076 22:54:31.944108 TX Vref=16, minBit 1, minWin=22, winSum=386
8077 22:54:31.947377 TX Vref=18, minBit 1, minWin=23, winSum=396
8078 22:54:31.950868 TX Vref=20, minBit 1, minWin=24, winSum=409
8079 22:54:31.954108 TX Vref=22, minBit 1, minWin=23, winSum=412
8080 22:54:31.957340 TX Vref=24, minBit 1, minWin=25, winSum=427
8081 22:54:31.964104 TX Vref=26, minBit 1, minWin=25, winSum=429
8082 22:54:31.967222 TX Vref=28, minBit 4, minWin=25, winSum=430
8083 22:54:31.970552 TX Vref=30, minBit 7, minWin=24, winSum=416
8084 22:54:31.973890 TX Vref=32, minBit 0, minWin=25, winSum=411
8085 22:54:31.977160 TX Vref=34, minBit 1, minWin=24, winSum=404
8086 22:54:31.983627 [TxChooseVref] Worse bit 4, Min win 25, Win sum 430, Final Vref 28
8087 22:54:31.983729
8088 22:54:31.987101 Final TX Range 0 Vref 28
8089 22:54:31.987198
8090 22:54:31.987286 ==
8091 22:54:31.990384 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 22:54:31.993520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 22:54:31.993589 ==
8094 22:54:31.993649
8095 22:54:31.993709
8096 22:54:31.996910 TX Vref Scan disable
8097 22:54:32.003791 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8098 22:54:32.003863 == TX Byte 0 ==
8099 22:54:32.007128 u2DelayCellOfst[0]=13 cells (4 PI)
8100 22:54:32.010131 u2DelayCellOfst[1]=16 cells (5 PI)
8101 22:54:32.013677 u2DelayCellOfst[2]=10 cells (3 PI)
8102 22:54:32.017436 u2DelayCellOfst[3]=10 cells (3 PI)
8103 22:54:32.020440 u2DelayCellOfst[4]=6 cells (2 PI)
8104 22:54:32.023562 u2DelayCellOfst[5]=0 cells (0 PI)
8105 22:54:32.027022 u2DelayCellOfst[6]=16 cells (5 PI)
8106 22:54:32.030328 u2DelayCellOfst[7]=16 cells (5 PI)
8107 22:54:32.033736 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8108 22:54:32.037024 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8109 22:54:32.040201 == TX Byte 1 ==
8110 22:54:32.040283 u2DelayCellOfst[8]=0 cells (0 PI)
8111 22:54:32.043411 u2DelayCellOfst[9]=0 cells (0 PI)
8112 22:54:32.046821 u2DelayCellOfst[10]=3 cells (1 PI)
8113 22:54:32.050051 u2DelayCellOfst[11]=0 cells (0 PI)
8114 22:54:32.053192 u2DelayCellOfst[12]=10 cells (3 PI)
8115 22:54:32.057276 u2DelayCellOfst[13]=6 cells (2 PI)
8116 22:54:32.059829 u2DelayCellOfst[14]=10 cells (3 PI)
8117 22:54:32.063412 u2DelayCellOfst[15]=10 cells (3 PI)
8118 22:54:32.066664 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8119 22:54:32.073445 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8120 22:54:32.073527 DramC Write-DBI on
8121 22:54:32.073592 ==
8122 22:54:32.076460 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 22:54:32.080289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 22:54:32.083843 ==
8125 22:54:32.083950
8126 22:54:32.084150
8127 22:54:32.084229 TX Vref Scan disable
8128 22:54:32.086910 == TX Byte 0 ==
8129 22:54:32.090340 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8130 22:54:32.093562 == TX Byte 1 ==
8131 22:54:32.096851 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8132 22:54:32.100120 DramC Write-DBI off
8133 22:54:32.100201
8134 22:54:32.100265 [DATLAT]
8135 22:54:32.100326 Freq=1600, CH0 RK1
8136 22:54:32.100402
8137 22:54:32.103197 DATLAT Default: 0xf
8138 22:54:32.103307 0, 0xFFFF, sum = 0
8139 22:54:32.107005 1, 0xFFFF, sum = 0
8140 22:54:32.107103 2, 0xFFFF, sum = 0
8141 22:54:32.110057 3, 0xFFFF, sum = 0
8142 22:54:32.113171 4, 0xFFFF, sum = 0
8143 22:54:32.113269 5, 0xFFFF, sum = 0
8144 22:54:32.116738 6, 0xFFFF, sum = 0
8145 22:54:32.116837 7, 0xFFFF, sum = 0
8146 22:54:32.119661 8, 0xFFFF, sum = 0
8147 22:54:32.119759 9, 0xFFFF, sum = 0
8148 22:54:32.122940 10, 0xFFFF, sum = 0
8149 22:54:32.123038 11, 0xFFFF, sum = 0
8150 22:54:32.126530 12, 0xFFFF, sum = 0
8151 22:54:32.126628 13, 0xFFFF, sum = 0
8152 22:54:32.129691 14, 0x0, sum = 1
8153 22:54:32.129789 15, 0x0, sum = 2
8154 22:54:32.133120 16, 0x0, sum = 3
8155 22:54:32.133219 17, 0x0, sum = 4
8156 22:54:32.136611 best_step = 15
8157 22:54:32.136708
8158 22:54:32.136802 ==
8159 22:54:32.139821 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 22:54:32.143188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 22:54:32.143280 ==
8162 22:54:32.146571 RX Vref Scan: 0
8163 22:54:32.146652
8164 22:54:32.146716 RX Vref 0 -> 0, step: 1
8165 22:54:32.146776
8166 22:54:32.150221 RX Delay 19 -> 252, step: 4
8167 22:54:32.153185 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8168 22:54:32.159786 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8169 22:54:32.163142 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8170 22:54:32.166492 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8171 22:54:32.169859 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8172 22:54:32.173217 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8173 22:54:32.179204 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8174 22:54:32.183330 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8175 22:54:32.186421 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8176 22:54:32.189525 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8177 22:54:32.193073 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8178 22:54:32.199355 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8179 22:54:32.202814 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8180 22:54:32.206426 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8181 22:54:32.209155 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8182 22:54:32.212491 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8183 22:54:32.216213 ==
8184 22:54:32.219259 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 22:54:32.222552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 22:54:32.222634 ==
8187 22:54:32.222699 DQS Delay:
8188 22:54:32.225968 DQS0 = 0, DQS1 = 0
8189 22:54:32.226075 DQM Delay:
8190 22:54:32.229212 DQM0 = 134, DQM1 = 126
8191 22:54:32.229293 DQ Delay:
8192 22:54:32.232382 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8193 22:54:32.235939 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =142
8194 22:54:32.239425 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8195 22:54:32.242609 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8196 22:54:32.242691
8197 22:54:32.242755
8198 22:54:32.242814
8199 22:54:32.245974 [DramC_TX_OE_Calibration] TA2
8200 22:54:32.249148 Original DQ_B0 (3 6) =30, OEN = 27
8201 22:54:32.252350 Original DQ_B1 (3 6) =30, OEN = 27
8202 22:54:32.255881 24, 0x0, End_B0=24 End_B1=24
8203 22:54:32.259180 25, 0x0, End_B0=25 End_B1=25
8204 22:54:32.259260 26, 0x0, End_B0=26 End_B1=26
8205 22:54:32.262541 27, 0x0, End_B0=27 End_B1=27
8206 22:54:32.265894 28, 0x0, End_B0=28 End_B1=28
8207 22:54:32.268927 29, 0x0, End_B0=29 End_B1=29
8208 22:54:32.272406 30, 0x0, End_B0=30 End_B1=30
8209 22:54:32.272496 31, 0x4141, End_B0=30 End_B1=30
8210 22:54:32.275703 Byte0 end_step=30 best_step=27
8211 22:54:32.279176 Byte1 end_step=30 best_step=27
8212 22:54:32.282423 Byte0 TX OE(2T, 0.5T) = (3, 3)
8213 22:54:32.285841 Byte1 TX OE(2T, 0.5T) = (3, 3)
8214 22:54:32.285937
8215 22:54:32.286027
8216 22:54:32.292548 [DQSOSCAuto] RK1, (LSB)MR18= 0x220b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8217 22:54:32.295788 CH0 RK1: MR19=303, MR18=220B
8218 22:54:32.302493 CH0_RK1: MR19=0x303, MR18=0x220B, DQSOSC=392, MR23=63, INC=24, DEC=16
8219 22:54:32.305639 [RxdqsGatingPostProcess] freq 1600
8220 22:54:32.312675 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8221 22:54:32.312777 best DQS0 dly(2T, 0.5T) = (1, 1)
8222 22:54:32.315435 best DQS1 dly(2T, 0.5T) = (1, 1)
8223 22:54:32.318684 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8224 22:54:32.322499 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8225 22:54:32.325841 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 22:54:32.328819 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 22:54:32.332122 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 22:54:32.335393 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 22:54:32.338805 Pre-setting of DQS Precalculation
8230 22:54:32.342055 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8231 22:54:32.342151 ==
8232 22:54:32.345243 Dram Type= 6, Freq= 0, CH_1, rank 0
8233 22:54:32.352136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 22:54:32.352236 ==
8235 22:54:32.355977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8236 22:54:32.362370 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8237 22:54:32.365718 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8238 22:54:32.372068 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8239 22:54:32.379594 [CA 0] Center 42 (13~72) winsize 60
8240 22:54:32.383168 [CA 1] Center 42 (13~72) winsize 60
8241 22:54:32.386633 [CA 2] Center 39 (10~68) winsize 59
8242 22:54:32.389775 [CA 3] Center 38 (9~68) winsize 60
8243 22:54:32.393245 [CA 4] Center 39 (10~68) winsize 59
8244 22:54:32.396581 [CA 5] Center 37 (8~67) winsize 60
8245 22:54:32.396678
8246 22:54:32.399719 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8247 22:54:32.399818
8248 22:54:32.402901 [CATrainingPosCal] consider 1 rank data
8249 22:54:32.406073 u2DelayCellTimex100 = 290/100 ps
8250 22:54:32.413212 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8251 22:54:32.416229 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8252 22:54:32.419634 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8253 22:54:32.422996 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8254 22:54:32.426252 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8255 22:54:32.429691 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8256 22:54:32.429789
8257 22:54:32.432683 CA PerBit enable=1, Macro0, CA PI delay=37
8258 22:54:32.432764
8259 22:54:32.436450 [CBTSetCACLKResult] CA Dly = 37
8260 22:54:32.440004 CS Dly: 11 (0~42)
8261 22:54:32.442514 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8262 22:54:32.446509 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8263 22:54:32.446600 ==
8264 22:54:32.449142 Dram Type= 6, Freq= 0, CH_1, rank 1
8265 22:54:32.456496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 22:54:32.456596 ==
8267 22:54:32.459676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 22:54:32.462875 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 22:54:32.469404 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 22:54:32.475846 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 22:54:32.483621 [CA 0] Center 42 (13~72) winsize 60
8272 22:54:32.486655 [CA 1] Center 42 (12~72) winsize 61
8273 22:54:32.489707 [CA 2] Center 38 (9~68) winsize 60
8274 22:54:32.493364 [CA 3] Center 38 (9~68) winsize 60
8275 22:54:32.496784 [CA 4] Center 39 (9~69) winsize 61
8276 22:54:32.499932 [CA 5] Center 38 (9~67) winsize 59
8277 22:54:32.500060
8278 22:54:32.503438 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8279 22:54:32.503513
8280 22:54:32.506219 [CATrainingPosCal] consider 2 rank data
8281 22:54:32.509982 u2DelayCellTimex100 = 290/100 ps
8282 22:54:32.512959 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8283 22:54:32.520013 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8284 22:54:32.523175 CA2 delay=39 (10~68),Diff = 1 PI (3 cell)
8285 22:54:32.526570 CA3 delay=38 (9~68),Diff = 0 PI (0 cell)
8286 22:54:32.529679 CA4 delay=39 (10~68),Diff = 1 PI (3 cell)
8287 22:54:32.532893 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8288 22:54:32.532960
8289 22:54:32.536367 CA PerBit enable=1, Macro0, CA PI delay=38
8290 22:54:32.536440
8291 22:54:32.539372 [CBTSetCACLKResult] CA Dly = 38
8292 22:54:32.542965 CS Dly: 12 (0~45)
8293 22:54:32.546417 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 22:54:32.549987 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 22:54:32.550084
8296 22:54:32.552883 ----->DramcWriteLeveling(PI) begin...
8297 22:54:32.552958 ==
8298 22:54:32.556208 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 22:54:32.562789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 22:54:32.562874 ==
8301 22:54:32.566551 Write leveling (Byte 0): 26 => 26
8302 22:54:32.566629 Write leveling (Byte 1): 28 => 28
8303 22:54:32.569428 DramcWriteLeveling(PI) end<-----
8304 22:54:32.569505
8305 22:54:32.572726 ==
8306 22:54:32.572811 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 22:54:32.579313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 22:54:32.579401 ==
8309 22:54:32.582504 [Gating] SW mode calibration
8310 22:54:32.589129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8311 22:54:32.592703 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8312 22:54:32.599066 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 22:54:32.602682 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 22:54:32.606209 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8315 22:54:32.612980 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8316 22:54:32.616173 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 22:54:32.619547 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 22:54:32.625912 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 22:54:32.629330 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 22:54:32.632439 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 22:54:32.638988 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 22:54:32.642376 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
8323 22:54:32.645812 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8324 22:54:32.649487 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8325 22:54:32.656438 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 22:54:32.659093 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 22:54:32.662356 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 22:54:32.669292 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 22:54:32.672813 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 22:54:32.675932 1 6 8 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
8331 22:54:32.682528 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8332 22:54:32.685965 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 22:54:32.689182 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 22:54:32.695749 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 22:54:32.699115 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 22:54:32.702550 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 22:54:32.709241 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 22:54:32.712813 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8339 22:54:32.716031 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8340 22:54:32.722831 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 22:54:32.726146 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 22:54:32.729094 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 22:54:32.735880 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 22:54:32.738823 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 22:54:32.742188 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 22:54:32.749129 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 22:54:32.752053 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 22:54:32.755538 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 22:54:32.762531 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 22:54:32.765859 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 22:54:32.769316 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 22:54:32.772535 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 22:54:32.779163 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 22:54:32.782417 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8355 22:54:32.785666 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8356 22:54:32.788644 Total UI for P1: 0, mck2ui 16
8357 22:54:32.792236 best dqsien dly found for B0: ( 1, 9, 8)
8358 22:54:32.798668 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 22:54:32.801926 Total UI for P1: 0, mck2ui 16
8360 22:54:32.805826 best dqsien dly found for B1: ( 1, 9, 10)
8361 22:54:32.809097 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8362 22:54:32.812355 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8363 22:54:32.812429
8364 22:54:32.815295 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8365 22:54:32.818563 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8366 22:54:32.821866 [Gating] SW calibration Done
8367 22:54:32.821939 ==
8368 22:54:32.825054 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 22:54:32.828631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 22:54:32.828707 ==
8371 22:54:32.831787 RX Vref Scan: 0
8372 22:54:32.831883
8373 22:54:32.831981 RX Vref 0 -> 0, step: 1
8374 22:54:32.835772
8375 22:54:32.835869 RX Delay 0 -> 252, step: 8
8376 22:54:32.838493 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8377 22:54:32.845092 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8378 22:54:32.848870 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8379 22:54:32.852086 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8380 22:54:32.855113 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8381 22:54:32.858581 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8382 22:54:32.865124 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8383 22:54:32.868549 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8384 22:54:32.871832 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8385 22:54:32.875057 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8386 22:54:32.878299 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8387 22:54:32.885427 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8388 22:54:32.888702 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8389 22:54:32.891986 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8390 22:54:32.895184 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8391 22:54:32.898393 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8392 22:54:32.902003 ==
8393 22:54:32.905248 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 22:54:32.908227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 22:54:32.908314 ==
8396 22:54:32.908377 DQS Delay:
8397 22:54:32.911692 DQS0 = 0, DQS1 = 0
8398 22:54:32.911775 DQM Delay:
8399 22:54:32.915537 DQM0 = 137, DQM1 = 133
8400 22:54:32.915626 DQ Delay:
8401 22:54:32.918820 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8402 22:54:32.921878 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8403 22:54:32.924820 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8404 22:54:32.928356 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8405 22:54:32.928449
8406 22:54:32.928513
8407 22:54:32.928575 ==
8408 22:54:32.931714 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 22:54:32.938682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 22:54:32.938777 ==
8411 22:54:32.938843
8412 22:54:32.938902
8413 22:54:32.938958 TX Vref Scan disable
8414 22:54:32.942117 == TX Byte 0 ==
8415 22:54:32.945481 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8416 22:54:32.952145 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8417 22:54:32.952222 == TX Byte 1 ==
8418 22:54:32.955558 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8419 22:54:32.961887 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8420 22:54:32.961967 ==
8421 22:54:32.965162 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 22:54:32.968209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 22:54:32.968292 ==
8424 22:54:32.980805
8425 22:54:32.983827 TX Vref early break, caculate TX vref
8426 22:54:32.986894 TX Vref=16, minBit 1, minWin=22, winSum=374
8427 22:54:32.990538 TX Vref=18, minBit 1, minWin=23, winSum=385
8428 22:54:32.993604 TX Vref=20, minBit 0, minWin=24, winSum=394
8429 22:54:32.997294 TX Vref=22, minBit 0, minWin=24, winSum=406
8430 22:54:33.000437 TX Vref=24, minBit 6, minWin=24, winSum=411
8431 22:54:33.007165 TX Vref=26, minBit 6, minWin=25, winSum=425
8432 22:54:33.010423 TX Vref=28, minBit 0, minWin=25, winSum=422
8433 22:54:33.013398 TX Vref=30, minBit 6, minWin=24, winSum=417
8434 22:54:33.017463 TX Vref=32, minBit 0, minWin=25, winSum=410
8435 22:54:33.020023 TX Vref=34, minBit 0, minWin=24, winSum=402
8436 22:54:33.026690 [TxChooseVref] Worse bit 6, Min win 25, Win sum 425, Final Vref 26
8437 22:54:33.026774
8438 22:54:33.029997 Final TX Range 0 Vref 26
8439 22:54:33.030070
8440 22:54:33.030131 ==
8441 22:54:33.033405 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 22:54:33.037275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 22:54:33.037346 ==
8444 22:54:33.037408
8445 22:54:33.037466
8446 22:54:33.040249 TX Vref Scan disable
8447 22:54:33.046537 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8448 22:54:33.046647 == TX Byte 0 ==
8449 22:54:33.050193 u2DelayCellOfst[0]=16 cells (5 PI)
8450 22:54:33.053688 u2DelayCellOfst[1]=10 cells (3 PI)
8451 22:54:33.056851 u2DelayCellOfst[2]=0 cells (0 PI)
8452 22:54:33.060342 u2DelayCellOfst[3]=3 cells (1 PI)
8453 22:54:33.063586 u2DelayCellOfst[4]=6 cells (2 PI)
8454 22:54:33.066750 u2DelayCellOfst[5]=16 cells (5 PI)
8455 22:54:33.070391 u2DelayCellOfst[6]=16 cells (5 PI)
8456 22:54:33.070465 u2DelayCellOfst[7]=3 cells (1 PI)
8457 22:54:33.077001 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8458 22:54:33.080175 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8459 22:54:33.080249 == TX Byte 1 ==
8460 22:54:33.083323 u2DelayCellOfst[8]=0 cells (0 PI)
8461 22:54:33.086720 u2DelayCellOfst[9]=3 cells (1 PI)
8462 22:54:33.090013 u2DelayCellOfst[10]=13 cells (4 PI)
8463 22:54:33.093397 u2DelayCellOfst[11]=6 cells (2 PI)
8464 22:54:33.096632 u2DelayCellOfst[12]=16 cells (5 PI)
8465 22:54:33.099814 u2DelayCellOfst[13]=16 cells (5 PI)
8466 22:54:33.103699 u2DelayCellOfst[14]=16 cells (5 PI)
8467 22:54:33.106887 u2DelayCellOfst[15]=16 cells (5 PI)
8468 22:54:33.109850 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8469 22:54:33.116378 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8470 22:54:33.116462 DramC Write-DBI on
8471 22:54:33.116539 ==
8472 22:54:33.120300 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 22:54:33.123246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 22:54:33.123320 ==
8475 22:54:33.126635
8476 22:54:33.126713
8477 22:54:33.126785 TX Vref Scan disable
8478 22:54:33.130332 == TX Byte 0 ==
8479 22:54:33.133276 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8480 22:54:33.136957 == TX Byte 1 ==
8481 22:54:33.140180 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8482 22:54:33.140257 DramC Write-DBI off
8483 22:54:33.143377
8484 22:54:33.143451 [DATLAT]
8485 22:54:33.143521 Freq=1600, CH1 RK0
8486 22:54:33.143581
8487 22:54:33.146772 DATLAT Default: 0xf
8488 22:54:33.146873 0, 0xFFFF, sum = 0
8489 22:54:33.149909 1, 0xFFFF, sum = 0
8490 22:54:33.149984 2, 0xFFFF, sum = 0
8491 22:54:33.153068 3, 0xFFFF, sum = 0
8492 22:54:33.156567 4, 0xFFFF, sum = 0
8493 22:54:33.156658 5, 0xFFFF, sum = 0
8494 22:54:33.159540 6, 0xFFFF, sum = 0
8495 22:54:33.159643 7, 0xFFFF, sum = 0
8496 22:54:33.162809 8, 0xFFFF, sum = 0
8497 22:54:33.162906 9, 0xFFFF, sum = 0
8498 22:54:33.166015 10, 0xFFFF, sum = 0
8499 22:54:33.166087 11, 0xFFFF, sum = 0
8500 22:54:33.169498 12, 0xFFFF, sum = 0
8501 22:54:33.169569 13, 0xFFFF, sum = 0
8502 22:54:33.173051 14, 0x0, sum = 1
8503 22:54:33.173120 15, 0x0, sum = 2
8504 22:54:33.176390 16, 0x0, sum = 3
8505 22:54:33.176459 17, 0x0, sum = 4
8506 22:54:33.179353 best_step = 15
8507 22:54:33.179430
8508 22:54:33.179491 ==
8509 22:54:33.182602 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 22:54:33.186322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 22:54:33.186393 ==
8512 22:54:33.186456 RX Vref Scan: 1
8513 22:54:33.189648
8514 22:54:33.189723 Set Vref Range= 24 -> 127
8515 22:54:33.189784
8516 22:54:33.193033 RX Vref 24 -> 127, step: 1
8517 22:54:33.193103
8518 22:54:33.196263 RX Delay 27 -> 252, step: 4
8519 22:54:33.196332
8520 22:54:33.199430 Set Vref, RX VrefLevel [Byte0]: 24
8521 22:54:33.202898 [Byte1]: 24
8522 22:54:33.203013
8523 22:54:33.205929 Set Vref, RX VrefLevel [Byte0]: 25
8524 22:54:33.209618 [Byte1]: 25
8525 22:54:33.209698
8526 22:54:33.213088 Set Vref, RX VrefLevel [Byte0]: 26
8527 22:54:33.215830 [Byte1]: 26
8528 22:54:33.220449
8529 22:54:33.220547 Set Vref, RX VrefLevel [Byte0]: 27
8530 22:54:33.223034 [Byte1]: 27
8531 22:54:33.227862
8532 22:54:33.227985 Set Vref, RX VrefLevel [Byte0]: 28
8533 22:54:33.230772 [Byte1]: 28
8534 22:54:33.235155
8535 22:54:33.235237 Set Vref, RX VrefLevel [Byte0]: 29
8536 22:54:33.238400 [Byte1]: 29
8537 22:54:33.242479
8538 22:54:33.242590 Set Vref, RX VrefLevel [Byte0]: 30
8539 22:54:33.245924 [Byte1]: 30
8540 22:54:33.250186
8541 22:54:33.250295 Set Vref, RX VrefLevel [Byte0]: 31
8542 22:54:33.253395 [Byte1]: 31
8543 22:54:33.257322
8544 22:54:33.257405 Set Vref, RX VrefLevel [Byte0]: 32
8545 22:54:33.261139 [Byte1]: 32
8546 22:54:33.265002
8547 22:54:33.265085 Set Vref, RX VrefLevel [Byte0]: 33
8548 22:54:33.268584 [Byte1]: 33
8549 22:54:33.272843
8550 22:54:33.272950 Set Vref, RX VrefLevel [Byte0]: 34
8551 22:54:33.276150 [Byte1]: 34
8552 22:54:33.280148
8553 22:54:33.280219 Set Vref, RX VrefLevel [Byte0]: 35
8554 22:54:33.283416 [Byte1]: 35
8555 22:54:33.287684
8556 22:54:33.287799 Set Vref, RX VrefLevel [Byte0]: 36
8557 22:54:33.290932 [Byte1]: 36
8558 22:54:33.295243
8559 22:54:33.295354 Set Vref, RX VrefLevel [Byte0]: 37
8560 22:54:33.298511 [Byte1]: 37
8561 22:54:33.302507
8562 22:54:33.302611 Set Vref, RX VrefLevel [Byte0]: 38
8563 22:54:33.306420 [Byte1]: 38
8564 22:54:33.310249
8565 22:54:33.310335 Set Vref, RX VrefLevel [Byte0]: 39
8566 22:54:33.313396 [Byte1]: 39
8567 22:54:33.317985
8568 22:54:33.318058 Set Vref, RX VrefLevel [Byte0]: 40
8569 22:54:33.321414 [Byte1]: 40
8570 22:54:33.325152
8571 22:54:33.325228 Set Vref, RX VrefLevel [Byte0]: 41
8572 22:54:33.328392 [Byte1]: 41
8573 22:54:33.332887
8574 22:54:33.332993 Set Vref, RX VrefLevel [Byte0]: 42
8575 22:54:33.336245 [Byte1]: 42
8576 22:54:33.340241
8577 22:54:33.340352 Set Vref, RX VrefLevel [Byte0]: 43
8578 22:54:33.343778 [Byte1]: 43
8579 22:54:33.347560
8580 22:54:33.347665 Set Vref, RX VrefLevel [Byte0]: 44
8581 22:54:33.351360 [Byte1]: 44
8582 22:54:33.355235
8583 22:54:33.355330 Set Vref, RX VrefLevel [Byte0]: 45
8584 22:54:33.358461 [Byte1]: 45
8585 22:54:33.362704
8586 22:54:33.362807 Set Vref, RX VrefLevel [Byte0]: 46
8587 22:54:33.366066 [Byte1]: 46
8588 22:54:33.370361
8589 22:54:33.370436 Set Vref, RX VrefLevel [Byte0]: 47
8590 22:54:33.373856 [Byte1]: 47
8591 22:54:33.377836
8592 22:54:33.377922 Set Vref, RX VrefLevel [Byte0]: 48
8593 22:54:33.381315 [Byte1]: 48
8594 22:54:33.385291
8595 22:54:33.385386 Set Vref, RX VrefLevel [Byte0]: 49
8596 22:54:33.388878 [Byte1]: 49
8597 22:54:33.393079
8598 22:54:33.393188 Set Vref, RX VrefLevel [Byte0]: 50
8599 22:54:33.396536 [Byte1]: 50
8600 22:54:33.400857
8601 22:54:33.400939 Set Vref, RX VrefLevel [Byte0]: 51
8602 22:54:33.404023 [Byte1]: 51
8603 22:54:33.407954
8604 22:54:33.408044 Set Vref, RX VrefLevel [Byte0]: 52
8605 22:54:33.411497 [Byte1]: 52
8606 22:54:33.416191
8607 22:54:33.416273 Set Vref, RX VrefLevel [Byte0]: 53
8608 22:54:33.419250 [Byte1]: 53
8609 22:54:33.423058
8610 22:54:33.423140 Set Vref, RX VrefLevel [Byte0]: 54
8611 22:54:33.426538 [Byte1]: 54
8612 22:54:33.430439
8613 22:54:33.433661 Set Vref, RX VrefLevel [Byte0]: 55
8614 22:54:33.437087 [Byte1]: 55
8615 22:54:33.437170
8616 22:54:33.440421 Set Vref, RX VrefLevel [Byte0]: 56
8617 22:54:33.443721 [Byte1]: 56
8618 22:54:33.443803
8619 22:54:33.447173 Set Vref, RX VrefLevel [Byte0]: 57
8620 22:54:33.450467 [Byte1]: 57
8621 22:54:33.450550
8622 22:54:33.453970 Set Vref, RX VrefLevel [Byte0]: 58
8623 22:54:33.457215 [Byte1]: 58
8624 22:54:33.460973
8625 22:54:33.461102 Set Vref, RX VrefLevel [Byte0]: 59
8626 22:54:33.464314 [Byte1]: 59
8627 22:54:33.468309
8628 22:54:33.468416 Set Vref, RX VrefLevel [Byte0]: 60
8629 22:54:33.471603 [Byte1]: 60
8630 22:54:33.475721
8631 22:54:33.475822 Set Vref, RX VrefLevel [Byte0]: 61
8632 22:54:33.479690 [Byte1]: 61
8633 22:54:33.483650
8634 22:54:33.483763 Set Vref, RX VrefLevel [Byte0]: 62
8635 22:54:33.487236 [Byte1]: 62
8636 22:54:33.491111
8637 22:54:33.491209 Set Vref, RX VrefLevel [Byte0]: 63
8638 22:54:33.494401 [Byte1]: 63
8639 22:54:33.498748
8640 22:54:33.498850 Set Vref, RX VrefLevel [Byte0]: 64
8641 22:54:33.502113 [Byte1]: 64
8642 22:54:33.506246
8643 22:54:33.506361 Set Vref, RX VrefLevel [Byte0]: 65
8644 22:54:33.509233 [Byte1]: 65
8645 22:54:33.513596
8646 22:54:33.513672 Set Vref, RX VrefLevel [Byte0]: 66
8647 22:54:33.516728 [Byte1]: 66
8648 22:54:33.521362
8649 22:54:33.521479 Set Vref, RX VrefLevel [Byte0]: 67
8650 22:54:33.524593 [Byte1]: 67
8651 22:54:33.528870
8652 22:54:33.528995 Set Vref, RX VrefLevel [Byte0]: 68
8653 22:54:33.531654 [Byte1]: 68
8654 22:54:33.536432
8655 22:54:33.536507 Set Vref, RX VrefLevel [Byte0]: 69
8656 22:54:33.539224 [Byte1]: 69
8657 22:54:33.543661
8658 22:54:33.543764 Set Vref, RX VrefLevel [Byte0]: 70
8659 22:54:33.547071 [Byte1]: 70
8660 22:54:33.551127
8661 22:54:33.551199 Set Vref, RX VrefLevel [Byte0]: 71
8662 22:54:33.554971 [Byte1]: 71
8663 22:54:33.559084
8664 22:54:33.559185 Set Vref, RX VrefLevel [Byte0]: 72
8665 22:54:33.562371 [Byte1]: 72
8666 22:54:33.566765
8667 22:54:33.566875 Set Vref, RX VrefLevel [Byte0]: 73
8668 22:54:33.569371 [Byte1]: 73
8669 22:54:33.573998
8670 22:54:33.574112 Set Vref, RX VrefLevel [Byte0]: 74
8671 22:54:33.577491 [Byte1]: 74
8672 22:54:33.581351
8673 22:54:33.581427 Set Vref, RX VrefLevel [Byte0]: 75
8674 22:54:33.584641 [Byte1]: 75
8675 22:54:33.588635
8676 22:54:33.588736 Final RX Vref Byte 0 = 58 to rank0
8677 22:54:33.592554 Final RX Vref Byte 1 = 58 to rank0
8678 22:54:33.595318 Final RX Vref Byte 0 = 58 to rank1
8679 22:54:33.599055 Final RX Vref Byte 1 = 58 to rank1==
8680 22:54:33.602150 Dram Type= 6, Freq= 0, CH_1, rank 0
8681 22:54:33.609063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8682 22:54:33.609144 ==
8683 22:54:33.609209 DQS Delay:
8684 22:54:33.609271 DQS0 = 0, DQS1 = 0
8685 22:54:33.612390 DQM Delay:
8686 22:54:33.612457 DQM0 = 134, DQM1 = 131
8687 22:54:33.615930 DQ Delay:
8688 22:54:33.619028 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8689 22:54:33.622033 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8690 22:54:33.625684 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8691 22:54:33.628653 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8692 22:54:33.628763
8693 22:54:33.628864
8694 22:54:33.628959
8695 22:54:33.632385 [DramC_TX_OE_Calibration] TA2
8696 22:54:33.636123 Original DQ_B0 (3 6) =30, OEN = 27
8697 22:54:33.639125 Original DQ_B1 (3 6) =30, OEN = 27
8698 22:54:33.642542 24, 0x0, End_B0=24 End_B1=24
8699 22:54:33.642661 25, 0x0, End_B0=25 End_B1=25
8700 22:54:33.645327 26, 0x0, End_B0=26 End_B1=26
8701 22:54:33.648746 27, 0x0, End_B0=27 End_B1=27
8702 22:54:33.652212 28, 0x0, End_B0=28 End_B1=28
8703 22:54:33.652302 29, 0x0, End_B0=29 End_B1=29
8704 22:54:33.655327 30, 0x0, End_B0=30 End_B1=30
8705 22:54:33.659212 31, 0x4141, End_B0=30 End_B1=30
8706 22:54:33.662661 Byte0 end_step=30 best_step=27
8707 22:54:33.665205 Byte1 end_step=30 best_step=27
8708 22:54:33.669304 Byte0 TX OE(2T, 0.5T) = (3, 3)
8709 22:54:33.669416 Byte1 TX OE(2T, 0.5T) = (3, 3)
8710 22:54:33.671824
8711 22:54:33.671927
8712 22:54:33.678332 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8713 22:54:33.682362 CH1 RK0: MR19=303, MR18=1623
8714 22:54:33.689196 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8715 22:54:33.689298
8716 22:54:33.692326 ----->DramcWriteLeveling(PI) begin...
8717 22:54:33.692401 ==
8718 22:54:33.695013 Dram Type= 6, Freq= 0, CH_1, rank 1
8719 22:54:33.698406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 22:54:33.698480 ==
8721 22:54:33.701583 Write leveling (Byte 0): 26 => 26
8722 22:54:33.705008 Write leveling (Byte 1): 27 => 27
8723 22:54:33.708492 DramcWriteLeveling(PI) end<-----
8724 22:54:33.708579
8725 22:54:33.708640 ==
8726 22:54:33.712179 Dram Type= 6, Freq= 0, CH_1, rank 1
8727 22:54:33.715112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 22:54:33.715225 ==
8729 22:54:33.718521 [Gating] SW mode calibration
8730 22:54:33.725171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8731 22:54:33.731453 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8732 22:54:33.735412 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 22:54:33.738838 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 22:54:33.744876 1 4 8 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
8735 22:54:33.748839 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8736 22:54:33.751365 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 22:54:33.758575 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 22:54:33.761654 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 22:54:33.765285 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 22:54:33.771337 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 22:54:33.774917 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8742 22:54:33.778564 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8743 22:54:33.784595 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 0)
8744 22:54:33.788118 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 22:54:33.791337 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 22:54:33.797875 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 22:54:33.801244 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 22:54:33.804631 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 22:54:33.811359 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 22:54:33.814789 1 6 8 | B1->B0 | 3c3c 2626 | 1 0 | (0 0) (0 0)
8751 22:54:33.817696 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8752 22:54:33.824782 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 22:54:33.827615 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 22:54:33.830804 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 22:54:33.837999 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 22:54:33.840783 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 22:54:33.844300 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 22:54:33.850948 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8759 22:54:33.854354 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8760 22:54:33.857533 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8761 22:54:33.864227 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 22:54:33.867332 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 22:54:33.871225 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 22:54:33.877196 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 22:54:33.881093 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 22:54:33.883767 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 22:54:33.890792 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 22:54:33.893759 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 22:54:33.897492 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 22:54:33.903851 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 22:54:33.907449 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 22:54:33.910524 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 22:54:33.913869 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8774 22:54:33.920685 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8775 22:54:33.924332 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8776 22:54:33.927382 Total UI for P1: 0, mck2ui 16
8777 22:54:33.930693 best dqsien dly found for B1: ( 1, 9, 6)
8778 22:54:33.934036 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 22:54:33.937253 Total UI for P1: 0, mck2ui 16
8780 22:54:33.940706 best dqsien dly found for B0: ( 1, 9, 12)
8781 22:54:33.943971 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8782 22:54:33.947338 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8783 22:54:33.950598
8784 22:54:33.953647 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8785 22:54:33.957520 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8786 22:54:33.960601 [Gating] SW calibration Done
8787 22:54:33.960684 ==
8788 22:54:33.963456 Dram Type= 6, Freq= 0, CH_1, rank 1
8789 22:54:33.966689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 22:54:33.966777 ==
8791 22:54:33.966864 RX Vref Scan: 0
8792 22:54:33.969936
8793 22:54:33.970021 RX Vref 0 -> 0, step: 1
8794 22:54:33.970109
8795 22:54:33.973690 RX Delay 0 -> 252, step: 8
8796 22:54:33.977123 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8797 22:54:33.980334 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8798 22:54:33.986953 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8799 22:54:33.990211 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8800 22:54:33.993626 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8801 22:54:33.996800 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8802 22:54:34.000086 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8803 22:54:34.006800 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8804 22:54:34.009943 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8805 22:54:34.013348 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8806 22:54:34.017154 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8807 22:54:34.020247 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8808 22:54:34.026468 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8809 22:54:34.030234 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8810 22:54:34.033106 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8811 22:54:34.036787 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8812 22:54:34.036875 ==
8813 22:54:34.040106 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 22:54:34.046744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 22:54:34.046830 ==
8816 22:54:34.046916 DQS Delay:
8817 22:54:34.050187 DQS0 = 0, DQS1 = 0
8818 22:54:34.050271 DQM Delay:
8819 22:54:34.050357 DQM0 = 135, DQM1 = 133
8820 22:54:34.053309 DQ Delay:
8821 22:54:34.056350 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8822 22:54:34.059847 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8823 22:54:34.063159 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8824 22:54:34.066830 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8825 22:54:34.066941
8826 22:54:34.067048
8827 22:54:34.067136 ==
8828 22:54:34.069672 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 22:54:34.072852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 22:54:34.076343 ==
8831 22:54:34.076419
8832 22:54:34.076497
8833 22:54:34.076576 TX Vref Scan disable
8834 22:54:34.079562 == TX Byte 0 ==
8835 22:54:34.083055 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8836 22:54:34.086169 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8837 22:54:34.089611 == TX Byte 1 ==
8838 22:54:34.093119 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8839 22:54:34.096381 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8840 22:54:34.099601 ==
8841 22:54:34.102892 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 22:54:34.106144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 22:54:34.106220 ==
8844 22:54:34.119598
8845 22:54:34.122851 TX Vref early break, caculate TX vref
8846 22:54:34.126179 TX Vref=16, minBit 0, minWin=22, winSum=381
8847 22:54:34.129442 TX Vref=18, minBit 0, minWin=23, winSum=397
8848 22:54:34.132777 TX Vref=20, minBit 0, minWin=24, winSum=405
8849 22:54:34.135497 TX Vref=22, minBit 1, minWin=24, winSum=409
8850 22:54:34.139315 TX Vref=24, minBit 0, minWin=25, winSum=417
8851 22:54:34.145912 TX Vref=26, minBit 0, minWin=25, winSum=424
8852 22:54:34.149193 TX Vref=28, minBit 0, minWin=26, winSum=428
8853 22:54:34.152422 TX Vref=30, minBit 1, minWin=25, winSum=424
8854 22:54:34.156072 TX Vref=32, minBit 0, minWin=25, winSum=415
8855 22:54:34.158957 TX Vref=34, minBit 0, minWin=24, winSum=408
8856 22:54:34.162477 TX Vref=36, minBit 1, minWin=23, winSum=397
8857 22:54:34.168798 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8858 22:54:34.168899
8859 22:54:34.172700 Final TX Range 0 Vref 28
8860 22:54:34.172777
8861 22:54:34.172841 ==
8862 22:54:34.176102 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 22:54:34.178986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 22:54:34.179096 ==
8865 22:54:34.179199
8866 22:54:34.179290
8867 22:54:34.182174 TX Vref Scan disable
8868 22:54:34.189064 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8869 22:54:34.189144 == TX Byte 0 ==
8870 22:54:34.192296 u2DelayCellOfst[0]=16 cells (5 PI)
8871 22:54:34.195723 u2DelayCellOfst[1]=10 cells (3 PI)
8872 22:54:34.198741 u2DelayCellOfst[2]=0 cells (0 PI)
8873 22:54:34.202459 u2DelayCellOfst[3]=6 cells (2 PI)
8874 22:54:34.205525 u2DelayCellOfst[4]=6 cells (2 PI)
8875 22:54:34.208790 u2DelayCellOfst[5]=20 cells (6 PI)
8876 22:54:34.212191 u2DelayCellOfst[6]=16 cells (5 PI)
8877 22:54:34.215534 u2DelayCellOfst[7]=3 cells (1 PI)
8878 22:54:34.218872 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8879 22:54:34.221979 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8880 22:54:34.225231 == TX Byte 1 ==
8881 22:54:34.228516 u2DelayCellOfst[8]=0 cells (0 PI)
8882 22:54:34.228592 u2DelayCellOfst[9]=3 cells (1 PI)
8883 22:54:34.232403 u2DelayCellOfst[10]=10 cells (3 PI)
8884 22:54:34.235137 u2DelayCellOfst[11]=3 cells (1 PI)
8885 22:54:34.238469 u2DelayCellOfst[12]=13 cells (4 PI)
8886 22:54:34.241802 u2DelayCellOfst[13]=13 cells (4 PI)
8887 22:54:34.245348 u2DelayCellOfst[14]=16 cells (5 PI)
8888 22:54:34.248720 u2DelayCellOfst[15]=16 cells (5 PI)
8889 22:54:34.251953 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8890 22:54:34.258381 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8891 22:54:34.258495 DramC Write-DBI on
8892 22:54:34.258588 ==
8893 22:54:34.261879 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 22:54:34.268493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 22:54:34.268575 ==
8896 22:54:34.268654
8897 22:54:34.268763
8898 22:54:34.268838 TX Vref Scan disable
8899 22:54:34.272501 == TX Byte 0 ==
8900 22:54:34.276034 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8901 22:54:34.279226 == TX Byte 1 ==
8902 22:54:34.282493 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8903 22:54:34.285544 DramC Write-DBI off
8904 22:54:34.285644
8905 22:54:34.285793 [DATLAT]
8906 22:54:34.285898 Freq=1600, CH1 RK1
8907 22:54:34.285984
8908 22:54:34.288980 DATLAT Default: 0xf
8909 22:54:34.289067 0, 0xFFFF, sum = 0
8910 22:54:34.292149 1, 0xFFFF, sum = 0
8911 22:54:34.292235 2, 0xFFFF, sum = 0
8912 22:54:34.295376 3, 0xFFFF, sum = 0
8913 22:54:34.298896 4, 0xFFFF, sum = 0
8914 22:54:34.299011 5, 0xFFFF, sum = 0
8915 22:54:34.302414 6, 0xFFFF, sum = 0
8916 22:54:34.302513 7, 0xFFFF, sum = 0
8917 22:54:34.305562 8, 0xFFFF, sum = 0
8918 22:54:34.305707 9, 0xFFFF, sum = 0
8919 22:54:34.308771 10, 0xFFFF, sum = 0
8920 22:54:34.308858 11, 0xFFFF, sum = 0
8921 22:54:34.311981 12, 0xFFFF, sum = 0
8922 22:54:34.312087 13, 0xFFFF, sum = 0
8923 22:54:34.315529 14, 0x0, sum = 1
8924 22:54:34.315631 15, 0x0, sum = 2
8925 22:54:34.319006 16, 0x0, sum = 3
8926 22:54:34.319114 17, 0x0, sum = 4
8927 22:54:34.321997 best_step = 15
8928 22:54:34.322115
8929 22:54:34.322238 ==
8930 22:54:34.325367 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 22:54:34.328790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 22:54:34.328902 ==
8933 22:54:34.331976 RX Vref Scan: 0
8934 22:54:34.332090
8935 22:54:34.332179 RX Vref 0 -> 0, step: 1
8936 22:54:34.332269
8937 22:54:34.335374 RX Delay 19 -> 252, step: 4
8938 22:54:34.338483 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8939 22:54:34.345669 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8940 22:54:34.348979 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8941 22:54:34.352040 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8942 22:54:34.355374 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8943 22:54:34.358780 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8944 22:54:34.365322 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8945 22:54:34.368652 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8946 22:54:34.371877 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8947 22:54:34.375527 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8948 22:54:34.378861 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8949 22:54:34.385187 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8950 22:54:34.388571 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8951 22:54:34.391906 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8952 22:54:34.395195 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8953 22:54:34.398589 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8954 22:54:34.402006 ==
8955 22:54:34.402109 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 22:54:34.407950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 22:54:34.408043 ==
8958 22:54:34.408109 DQS Delay:
8959 22:54:34.411898 DQS0 = 0, DQS1 = 0
8960 22:54:34.412008 DQM Delay:
8961 22:54:34.415143 DQM0 = 133, DQM1 = 130
8962 22:54:34.415246 DQ Delay:
8963 22:54:34.418469 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8964 22:54:34.421810 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =132
8965 22:54:34.424952 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8966 22:54:34.428172 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8967 22:54:34.428247
8968 22:54:34.428309
8969 22:54:34.428372
8970 22:54:34.431519 [DramC_TX_OE_Calibration] TA2
8971 22:54:34.434464 Original DQ_B0 (3 6) =30, OEN = 27
8972 22:54:34.437789 Original DQ_B1 (3 6) =30, OEN = 27
8973 22:54:34.441613 24, 0x0, End_B0=24 End_B1=24
8974 22:54:34.444754 25, 0x0, End_B0=25 End_B1=25
8975 22:54:34.444856 26, 0x0, End_B0=26 End_B1=26
8976 22:54:34.448482 27, 0x0, End_B0=27 End_B1=27
8977 22:54:34.451113 28, 0x0, End_B0=28 End_B1=28
8978 22:54:34.454576 29, 0x0, End_B0=29 End_B1=29
8979 22:54:34.458018 30, 0x0, End_B0=30 End_B1=30
8980 22:54:34.458126 31, 0x5151, End_B0=30 End_B1=30
8981 22:54:34.461298 Byte0 end_step=30 best_step=27
8982 22:54:34.464391 Byte1 end_step=30 best_step=27
8983 22:54:34.467707 Byte0 TX OE(2T, 0.5T) = (3, 3)
8984 22:54:34.471375 Byte1 TX OE(2T, 0.5T) = (3, 3)
8985 22:54:34.471479
8986 22:54:34.471571
8987 22:54:34.477923 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8988 22:54:34.481370 CH1 RK1: MR19=303, MR18=2106
8989 22:54:34.487931 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
8990 22:54:34.491149 [RxdqsGatingPostProcess] freq 1600
8991 22:54:34.497777 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8992 22:54:34.497856 best DQS0 dly(2T, 0.5T) = (1, 1)
8993 22:54:34.501165 best DQS1 dly(2T, 0.5T) = (1, 1)
8994 22:54:34.504497 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8995 22:54:34.507630 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8996 22:54:34.510987 best DQS0 dly(2T, 0.5T) = (1, 1)
8997 22:54:34.514372 best DQS1 dly(2T, 0.5T) = (1, 1)
8998 22:54:34.517703 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8999 22:54:34.521058 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9000 22:54:34.524740 Pre-setting of DQS Precalculation
9001 22:54:34.527770 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9002 22:54:34.537690 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9003 22:54:34.544102 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9004 22:54:34.544212
9005 22:54:34.544305
9006 22:54:34.548088 [Calibration Summary] 3200 Mbps
9007 22:54:34.548175 CH 0, Rank 0
9008 22:54:34.550600 SW Impedance : PASS
9009 22:54:34.550699 DUTY Scan : NO K
9010 22:54:34.553992 ZQ Calibration : PASS
9011 22:54:34.557413 Jitter Meter : NO K
9012 22:54:34.557522 CBT Training : PASS
9013 22:54:34.560751 Write leveling : PASS
9014 22:54:34.564515 RX DQS gating : PASS
9015 22:54:34.564619 RX DQ/DQS(RDDQC) : PASS
9016 22:54:34.567685 TX DQ/DQS : PASS
9017 22:54:34.570988 RX DATLAT : PASS
9018 22:54:34.571085 RX DQ/DQS(Engine): PASS
9019 22:54:34.574209 TX OE : PASS
9020 22:54:34.574308 All Pass.
9021 22:54:34.574397
9022 22:54:34.577303 CH 0, Rank 1
9023 22:54:34.577409 SW Impedance : PASS
9024 22:54:34.580997 DUTY Scan : NO K
9025 22:54:34.581097 ZQ Calibration : PASS
9026 22:54:34.583791 Jitter Meter : NO K
9027 22:54:34.587273 CBT Training : PASS
9028 22:54:34.587371 Write leveling : PASS
9029 22:54:34.590401 RX DQS gating : PASS
9030 22:54:34.593732 RX DQ/DQS(RDDQC) : PASS
9031 22:54:34.593816 TX DQ/DQS : PASS
9032 22:54:34.597954 RX DATLAT : PASS
9033 22:54:34.600741 RX DQ/DQS(Engine): PASS
9034 22:54:34.600840 TX OE : PASS
9035 22:54:34.604038 All Pass.
9036 22:54:34.604148
9037 22:54:34.604241 CH 1, Rank 0
9038 22:54:34.607669 SW Impedance : PASS
9039 22:54:34.607783 DUTY Scan : NO K
9040 22:54:34.610925 ZQ Calibration : PASS
9041 22:54:34.613880 Jitter Meter : NO K
9042 22:54:34.613986 CBT Training : PASS
9043 22:54:34.617274 Write leveling : PASS
9044 22:54:34.620703 RX DQS gating : PASS
9045 22:54:34.620806 RX DQ/DQS(RDDQC) : PASS
9046 22:54:34.623848 TX DQ/DQS : PASS
9047 22:54:34.623947 RX DATLAT : PASS
9048 22:54:34.627324 RX DQ/DQS(Engine): PASS
9049 22:54:34.630788 TX OE : PASS
9050 22:54:34.630888 All Pass.
9051 22:54:34.630981
9052 22:54:34.631069 CH 1, Rank 1
9053 22:54:34.634067 SW Impedance : PASS
9054 22:54:34.637211 DUTY Scan : NO K
9055 22:54:34.637296 ZQ Calibration : PASS
9056 22:54:34.640690 Jitter Meter : NO K
9057 22:54:34.644062 CBT Training : PASS
9058 22:54:34.644174 Write leveling : PASS
9059 22:54:34.647173 RX DQS gating : PASS
9060 22:54:34.650242 RX DQ/DQS(RDDQC) : PASS
9061 22:54:34.650348 TX DQ/DQS : PASS
9062 22:54:34.653860 RX DATLAT : PASS
9063 22:54:34.657175 RX DQ/DQS(Engine): PASS
9064 22:54:34.657260 TX OE : PASS
9065 22:54:34.660593 All Pass.
9066 22:54:34.660687
9067 22:54:34.660776 DramC Write-DBI on
9068 22:54:34.663624 PER_BANK_REFRESH: Hybrid Mode
9069 22:54:34.663733 TX_TRACKING: ON
9070 22:54:34.673571 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9071 22:54:34.680373 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9072 22:54:34.690323 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9073 22:54:34.694148 [FAST_K] Save calibration result to emmc
9074 22:54:34.697327 sync common calibartion params.
9075 22:54:34.697401 sync cbt_mode0:1, 1:1
9076 22:54:34.700590 dram_init: ddr_geometry: 2
9077 22:54:34.703755 dram_init: ddr_geometry: 2
9078 22:54:34.703872 dram_init: ddr_geometry: 2
9079 22:54:34.707341 0:dram_rank_size:100000000
9080 22:54:34.710398 1:dram_rank_size:100000000
9081 22:54:34.713713 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9082 22:54:34.717513 DFS_SHUFFLE_HW_MODE: ON
9083 22:54:34.720701 dramc_set_vcore_voltage set vcore to 725000
9084 22:54:34.723683 Read voltage for 1600, 0
9085 22:54:34.723803 Vio18 = 0
9086 22:54:34.727276 Vcore = 725000
9087 22:54:34.727391 Vdram = 0
9088 22:54:34.727519 Vddq = 0
9089 22:54:34.727624 Vmddr = 0
9090 22:54:34.730331 switch to 3200 Mbps bootup
9091 22:54:34.733527 [DramcRunTimeConfig]
9092 22:54:34.733617 PHYPLL
9093 22:54:34.737392 DPM_CONTROL_AFTERK: ON
9094 22:54:34.737466 PER_BANK_REFRESH: ON
9095 22:54:34.740279 REFRESH_OVERHEAD_REDUCTION: ON
9096 22:54:34.743620 CMD_PICG_NEW_MODE: OFF
9097 22:54:34.743731 XRTWTW_NEW_MODE: ON
9098 22:54:34.747326 XRTRTR_NEW_MODE: ON
9099 22:54:34.747425 TX_TRACKING: ON
9100 22:54:34.750281 RDSEL_TRACKING: OFF
9101 22:54:34.753769 DQS Precalculation for DVFS: ON
9102 22:54:34.753877 RX_TRACKING: OFF
9103 22:54:34.757027 HW_GATING DBG: ON
9104 22:54:34.757126 ZQCS_ENABLE_LP4: ON
9105 22:54:34.760078 RX_PICG_NEW_MODE: ON
9106 22:54:34.760151 TX_PICG_NEW_MODE: ON
9107 22:54:34.763880 ENABLE_RX_DCM_DPHY: ON
9108 22:54:34.767094 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9109 22:54:34.770380 DUMMY_READ_FOR_TRACKING: OFF
9110 22:54:34.770481 !!! SPM_CONTROL_AFTERK: OFF
9111 22:54:34.773793 !!! SPM could not control APHY
9112 22:54:34.777140 IMPEDANCE_TRACKING: ON
9113 22:54:34.777235 TEMP_SENSOR: ON
9114 22:54:34.780751 HW_SAVE_FOR_SR: OFF
9115 22:54:34.784040 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9116 22:54:34.786612 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9117 22:54:34.786686 Read ODT Tracking: ON
9118 22:54:34.790574 Refresh Rate DeBounce: ON
9119 22:54:34.793947 DFS_NO_QUEUE_FLUSH: ON
9120 22:54:34.797386 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9121 22:54:34.797458 ENABLE_DFS_RUNTIME_MRW: OFF
9122 22:54:34.800477 DDR_RESERVE_NEW_MODE: ON
9123 22:54:34.803477 MR_CBT_SWITCH_FREQ: ON
9124 22:54:34.803579 =========================
9125 22:54:34.823323 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9126 22:54:34.826806 dram_init: ddr_geometry: 2
9127 22:54:34.845165 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9128 22:54:34.848629 dram_init: dram init end (result: 0)
9129 22:54:34.854904 DRAM-K: Full calibration passed in 24429 msecs
9130 22:54:34.858129 MRC: failed to locate region type 0.
9131 22:54:34.858239 DRAM rank0 size:0x100000000,
9132 22:54:34.861750 DRAM rank1 size=0x100000000
9133 22:54:34.871611 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9134 22:54:34.878135 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9135 22:54:34.884700 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9136 22:54:34.891070 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9137 22:54:34.894561 DRAM rank0 size:0x100000000,
9138 22:54:34.897811 DRAM rank1 size=0x100000000
9139 22:54:34.897913 CBMEM:
9140 22:54:34.901225 IMD: root @ 0xfffff000 254 entries.
9141 22:54:34.904582 IMD: root @ 0xffffec00 62 entries.
9142 22:54:34.907859 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9143 22:54:34.914605 WARNING: RO_VPD is uninitialized or empty.
9144 22:54:34.917784 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9145 22:54:34.925087 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9146 22:54:34.937854 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9147 22:54:34.949422 BS: romstage times (exec / console): total (unknown) / 23966 ms
9148 22:54:34.949506
9149 22:54:34.949572
9150 22:54:34.959030 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9151 22:54:34.962875 ARM64: Exception handlers installed.
9152 22:54:34.965923 ARM64: Testing exception
9153 22:54:34.969376 ARM64: Done test exception
9154 22:54:34.969453 Enumerating buses...
9155 22:54:34.972753 Show all devs... Before device enumeration.
9156 22:54:34.975778 Root Device: enabled 1
9157 22:54:34.979178 CPU_CLUSTER: 0: enabled 1
9158 22:54:34.979290 CPU: 00: enabled 1
9159 22:54:34.982582 Compare with tree...
9160 22:54:34.982684 Root Device: enabled 1
9161 22:54:34.985719 CPU_CLUSTER: 0: enabled 1
9162 22:54:34.989011 CPU: 00: enabled 1
9163 22:54:34.989086 Root Device scanning...
9164 22:54:34.992524 scan_static_bus for Root Device
9165 22:54:34.995866 CPU_CLUSTER: 0 enabled
9166 22:54:34.999169 scan_static_bus for Root Device done
9167 22:54:35.002556 scan_bus: bus Root Device finished in 8 msecs
9168 22:54:35.002655 done
9169 22:54:35.008973 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9170 22:54:35.012693 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9171 22:54:35.019059 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9172 22:54:35.022527 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9173 22:54:35.025685 Allocating resources...
9174 22:54:35.028902 Reading resources...
9175 22:54:35.032320 Root Device read_resources bus 0 link: 0
9176 22:54:35.032396 DRAM rank0 size:0x100000000,
9177 22:54:35.035480 DRAM rank1 size=0x100000000
9178 22:54:35.038598 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9179 22:54:35.042060 CPU: 00 missing read_resources
9180 22:54:35.045367 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9181 22:54:35.052534 Root Device read_resources bus 0 link: 0 done
9182 22:54:35.052613 Done reading resources.
9183 22:54:35.058827 Show resources in subtree (Root Device)...After reading.
9184 22:54:35.062784 Root Device child on link 0 CPU_CLUSTER: 0
9185 22:54:35.065605 CPU_CLUSTER: 0 child on link 0 CPU: 00
9186 22:54:35.075369 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9187 22:54:35.075486 CPU: 00
9188 22:54:35.078658 Root Device assign_resources, bus 0 link: 0
9189 22:54:35.081863 CPU_CLUSTER: 0 missing set_resources
9190 22:54:35.085752 Root Device assign_resources, bus 0 link: 0 done
9191 22:54:35.089193 Done setting resources.
9192 22:54:35.095479 Show resources in subtree (Root Device)...After assigning values.
9193 22:54:35.098749 Root Device child on link 0 CPU_CLUSTER: 0
9194 22:54:35.102190 CPU_CLUSTER: 0 child on link 0 CPU: 00
9195 22:54:35.111798 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9196 22:54:35.111901 CPU: 00
9197 22:54:35.115097 Done allocating resources.
9198 22:54:35.118630 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9199 22:54:35.122120 Enabling resources...
9200 22:54:35.122218 done.
9201 22:54:35.128828 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9202 22:54:35.128902 Initializing devices...
9203 22:54:35.131976 Root Device init
9204 22:54:35.132046 init hardware done!
9205 22:54:35.135638 0x00000018: ctrlr->caps
9206 22:54:35.138422 52.000 MHz: ctrlr->f_max
9207 22:54:35.138521 0.400 MHz: ctrlr->f_min
9208 22:54:35.141877 0x40ff8080: ctrlr->voltages
9209 22:54:35.141950 sclk: 390625
9210 22:54:35.145633 Bus Width = 1
9211 22:54:35.145734 sclk: 390625
9212 22:54:35.145828 Bus Width = 1
9213 22:54:35.148765 Early init status = 3
9214 22:54:35.155859 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9215 22:54:35.159221 in-header: 03 fc 00 00 01 00 00 00
9216 22:54:35.159322 in-data: 00
9217 22:54:35.165082 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9218 22:54:35.169232 in-header: 03 fd 00 00 00 00 00 00
9219 22:54:35.171782 in-data:
9220 22:54:35.175445 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9221 22:54:35.179670 in-header: 03 fc 00 00 01 00 00 00
9222 22:54:35.182917 in-data: 00
9223 22:54:35.185781 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9224 22:54:35.191771 in-header: 03 fd 00 00 00 00 00 00
9225 22:54:35.194976 in-data:
9226 22:54:35.198283 [SSUSB] Setting up USB HOST controller...
9227 22:54:35.201659 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9228 22:54:35.204924 [SSUSB] phy power-on done.
9229 22:54:35.208351 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9230 22:54:35.214957 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9231 22:54:35.218235 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9232 22:54:35.225030 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9233 22:54:35.231027 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9234 22:54:35.237807 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9235 22:54:35.244660 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9236 22:54:35.251143 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9237 22:54:35.254566 SPM: binary array size = 0x9dc
9238 22:54:35.257877 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9239 22:54:35.264131 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9240 22:54:35.270659 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9241 22:54:35.277531 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9242 22:54:35.280527 configure_display: Starting display init
9243 22:54:35.315297 anx7625_power_on_init: Init interface.
9244 22:54:35.318590 anx7625_disable_pd_protocol: Disabled PD feature.
9245 22:54:35.321793 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9246 22:54:35.349684 anx7625_start_dp_work: Secure OCM version=00
9247 22:54:35.352434 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9248 22:54:35.367318 sp_tx_get_edid_block: EDID Block = 1
9249 22:54:35.470074 Extracted contents:
9250 22:54:35.473572 header: 00 ff ff ff ff ff ff 00
9251 22:54:35.477110 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9252 22:54:35.479975 version: 01 04
9253 22:54:35.483185 basic params: 95 1f 11 78 0a
9254 22:54:35.486430 chroma info: 76 90 94 55 54 90 27 21 50 54
9255 22:54:35.489746 established: 00 00 00
9256 22:54:35.496149 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9257 22:54:35.499423 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9258 22:54:35.505886 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9259 22:54:35.512879 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9260 22:54:35.519168 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9261 22:54:35.522753 extensions: 00
9262 22:54:35.522862 checksum: fb
9263 22:54:35.522962
9264 22:54:35.525993 Manufacturer: IVO Model 57d Serial Number 0
9265 22:54:35.529387 Made week 0 of 2020
9266 22:54:35.532458 EDID version: 1.4
9267 22:54:35.532556 Digital display
9268 22:54:35.536095 6 bits per primary color channel
9269 22:54:35.536194 DisplayPort interface
9270 22:54:35.539182 Maximum image size: 31 cm x 17 cm
9271 22:54:35.542648 Gamma: 220%
9272 22:54:35.542747 Check DPMS levels
9273 22:54:35.546115 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9274 22:54:35.552378 First detailed timing is preferred timing
9275 22:54:35.552455 Established timings supported:
9276 22:54:35.555746 Standard timings supported:
9277 22:54:35.559201 Detailed timings
9278 22:54:35.562496 Hex of detail: 383680a07038204018303c0035ae10000019
9279 22:54:35.565877 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9280 22:54:35.572430 0780 0798 07c8 0820 hborder 0
9281 22:54:35.575822 0438 043b 0447 0458 vborder 0
9282 22:54:35.579171 -hsync -vsync
9283 22:54:35.579270 Did detailed timing
9284 22:54:35.585675 Hex of detail: 000000000000000000000000000000000000
9285 22:54:35.588834 Manufacturer-specified data, tag 0
9286 22:54:35.592200 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9287 22:54:35.595587 ASCII string: InfoVision
9288 22:54:35.599289 Hex of detail: 000000fe00523134304e574635205248200a
9289 22:54:35.602482 ASCII string: R140NWF5 RH
9290 22:54:35.602587 Checksum
9291 22:54:35.606044 Checksum: 0xfb (valid)
9292 22:54:35.609079 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9293 22:54:35.612198 DSI data_rate: 832800000 bps
9294 22:54:35.618627 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9295 22:54:35.622408 anx7625_parse_edid: pixelclock(138800).
9296 22:54:35.625762 hactive(1920), hsync(48), hfp(24), hbp(88)
9297 22:54:35.628975 vactive(1080), vsync(12), vfp(3), vbp(17)
9298 22:54:35.632129 anx7625_dsi_config: config dsi.
9299 22:54:35.639175 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9300 22:54:35.651761 anx7625_dsi_config: success to config DSI
9301 22:54:35.655553 anx7625_dp_start: MIPI phy setup OK.
9302 22:54:35.658576 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9303 22:54:35.662038 mtk_ddp_mode_set invalid vrefresh 60
9304 22:54:35.665546 main_disp_path_setup
9305 22:54:35.665650 ovl_layer_smi_id_en
9306 22:54:35.668509 ovl_layer_smi_id_en
9307 22:54:35.668580 ccorr_config
9308 22:54:35.668656 aal_config
9309 22:54:35.672022 gamma_config
9310 22:54:35.672109 postmask_config
9311 22:54:35.675085 dither_config
9312 22:54:35.678690 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9313 22:54:35.685128 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9314 22:54:35.688583 Root Device init finished in 553 msecs
9315 22:54:35.692072 CPU_CLUSTER: 0 init
9316 22:54:35.698791 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9317 22:54:35.701963 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9318 22:54:35.705176 APU_MBOX 0x190000b0 = 0x10001
9319 22:54:35.708220 APU_MBOX 0x190001b0 = 0x10001
9320 22:54:35.711782 APU_MBOX 0x190005b0 = 0x10001
9321 22:54:35.715534 APU_MBOX 0x190006b0 = 0x10001
9322 22:54:35.718518 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9323 22:54:35.731398 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9324 22:54:35.743381 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9325 22:54:35.750007 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9326 22:54:35.762010 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9327 22:54:35.770530 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9328 22:54:35.773861 CPU_CLUSTER: 0 init finished in 81 msecs
9329 22:54:35.777007 Devices initialized
9330 22:54:35.780616 Show all devs... After init.
9331 22:54:35.780720 Root Device: enabled 1
9332 22:54:35.784026 CPU_CLUSTER: 0: enabled 1
9333 22:54:35.787059 CPU: 00: enabled 1
9334 22:54:35.790362 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9335 22:54:35.794145 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9336 22:54:35.797115 ELOG: NV offset 0x57f000 size 0x1000
9337 22:54:35.803812 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9338 22:54:35.810206 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9339 22:54:35.814089 ELOG: Event(17) added with size 13 at 2024-05-07 22:50:13 UTC
9340 22:54:35.817118 out: cmd=0x121: 03 db 21 01 00 00 00 00
9341 22:54:35.820876 in-header: 03 fa 00 00 2c 00 00 00
9342 22:54:35.834396 in-data: 65 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9343 22:54:35.840766 ELOG: Event(A1) added with size 10 at 2024-05-07 22:50:13 UTC
9344 22:54:35.847692 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9345 22:54:35.854450 ELOG: Event(A0) added with size 9 at 2024-05-07 22:50:13 UTC
9346 22:54:35.857595 elog_add_boot_reason: Logged dev mode boot
9347 22:54:35.860964 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9348 22:54:35.864433 Finalize devices...
9349 22:54:35.864533 Devices finalized
9350 22:54:35.870992 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9351 22:54:35.874389 Writing coreboot table at 0xffe64000
9352 22:54:35.877794 0. 000000000010a000-0000000000113fff: RAMSTAGE
9353 22:54:35.881027 1. 0000000040000000-00000000400fffff: RAM
9354 22:54:35.884240 2. 0000000040100000-000000004032afff: RAMSTAGE
9355 22:54:35.890712 3. 000000004032b000-00000000545fffff: RAM
9356 22:54:35.894137 4. 0000000054600000-000000005465ffff: BL31
9357 22:54:35.897516 5. 0000000054660000-00000000ffe63fff: RAM
9358 22:54:35.901263 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9359 22:54:35.907651 7. 0000000100000000-000000023fffffff: RAM
9360 22:54:35.907759 Passing 5 GPIOs to payload:
9361 22:54:35.914072 NAME | PORT | POLARITY | VALUE
9362 22:54:35.917279 EC in RW | 0x000000aa | low | undefined
9363 22:54:35.923818 EC interrupt | 0x00000005 | low | undefined
9364 22:54:35.927175 TPM interrupt | 0x000000ab | high | undefined
9365 22:54:35.930823 SD card detect | 0x00000011 | high | undefined
9366 22:54:35.937293 speaker enable | 0x00000093 | high | undefined
9367 22:54:35.940704 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9368 22:54:35.943604 in-header: 03 f9 00 00 02 00 00 00
9369 22:54:35.943689 in-data: 02 00
9370 22:54:35.947699 ADC[4]: Raw value=904726 ID=7
9371 22:54:35.950590 ADC[3]: Raw value=213441 ID=1
9372 22:54:35.953948 RAM Code: 0x71
9373 22:54:35.954024 ADC[6]: Raw value=75332 ID=0
9374 22:54:35.956748 ADC[5]: Raw value=212703 ID=1
9375 22:54:35.960243 SKU Code: 0x1
9376 22:54:35.963767 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 27a6
9377 22:54:35.966908 coreboot table: 964 bytes.
9378 22:54:35.970462 IMD ROOT 0. 0xfffff000 0x00001000
9379 22:54:35.973712 IMD SMALL 1. 0xffffe000 0x00001000
9380 22:54:35.976929 RO MCACHE 2. 0xffffc000 0x00001104
9381 22:54:35.980292 CONSOLE 3. 0xfff7c000 0x00080000
9382 22:54:35.983716 FMAP 4. 0xfff7b000 0x00000452
9383 22:54:35.986941 TIME STAMP 5. 0xfff7a000 0x00000910
9384 22:54:35.990268 VBOOT WORK 6. 0xfff66000 0x00014000
9385 22:54:35.993614 RAMOOPS 7. 0xffe66000 0x00100000
9386 22:54:35.997162 COREBOOT 8. 0xffe64000 0x00002000
9387 22:54:35.997234 IMD small region:
9388 22:54:36.000136 IMD ROOT 0. 0xffffec00 0x00000400
9389 22:54:36.003363 VPD 1. 0xffffeb80 0x0000006c
9390 22:54:36.006865 MMC STATUS 2. 0xffffeb60 0x00000004
9391 22:54:36.013286 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9392 22:54:36.016745 Probing TPM: done!
9393 22:54:36.020401 Connected to device vid:did:rid of 1ae0:0028:00
9394 22:54:36.029852 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9395 22:54:36.033731 Initialized TPM device CR50 revision 0
9396 22:54:36.037558 Checking cr50 for pending updates
9397 22:54:36.040892 Reading cr50 TPM mode
9398 22:54:36.049243 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9399 22:54:36.056174 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9400 22:54:36.096148 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9401 22:54:36.099289 Checking segment from ROM address 0x40100000
9402 22:54:36.102674 Checking segment from ROM address 0x4010001c
9403 22:54:36.109322 Loading segment from ROM address 0x40100000
9404 22:54:36.109402 code (compression=0)
9405 22:54:36.116411 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9406 22:54:36.125962 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9407 22:54:36.126068 it's not compressed!
9408 22:54:36.133293 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9409 22:54:36.136204 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9410 22:54:36.156409 Loading segment from ROM address 0x4010001c
9411 22:54:36.156522 Entry Point 0x80000000
9412 22:54:36.159708 Loaded segments
9413 22:54:36.162778 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9414 22:54:36.169441 Jumping to boot code at 0x80000000(0xffe64000)
9415 22:54:36.176764 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9416 22:54:36.183385 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9417 22:54:36.190687 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9418 22:54:36.194045 Checking segment from ROM address 0x40100000
9419 22:54:36.197586 Checking segment from ROM address 0x4010001c
9420 22:54:36.203776 Loading segment from ROM address 0x40100000
9421 22:54:36.203853 code (compression=1)
9422 22:54:36.211393 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9423 22:54:36.220653 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9424 22:54:36.220734 using LZMA
9425 22:54:36.229564 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9426 22:54:36.235929 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9427 22:54:36.239203 Loading segment from ROM address 0x4010001c
9428 22:54:36.239278 Entry Point 0x54601000
9429 22:54:36.242719 Loaded segments
9430 22:54:36.245731 NOTICE: MT8192 bl31_setup
9431 22:54:36.252503 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9432 22:54:36.256433 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9433 22:54:36.259581 WARNING: region 0:
9434 22:54:36.263126 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9435 22:54:36.263206 WARNING: region 1:
9436 22:54:36.269782 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9437 22:54:36.269864 WARNING: region 2:
9438 22:54:36.276408 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9439 22:54:36.279665 WARNING: region 3:
9440 22:54:36.283105 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9441 22:54:36.286284 WARNING: region 4:
9442 22:54:36.289860 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9443 22:54:36.293290 WARNING: region 5:
9444 22:54:36.296580 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 22:54:36.299859 WARNING: region 6:
9446 22:54:36.303476 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 22:54:36.303581 WARNING: region 7:
9448 22:54:36.309846 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 22:54:36.316340 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9450 22:54:36.320306 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9451 22:54:36.323725 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9452 22:54:36.326299 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9453 22:54:36.333165 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9454 22:54:36.336398 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9455 22:54:36.343612 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9456 22:54:36.346638 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9457 22:54:36.349885 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9458 22:54:36.356654 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9459 22:54:36.359674 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9460 22:54:36.362932 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9461 22:54:36.370040 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9462 22:54:36.372972 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9463 22:54:36.379752 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9464 22:54:36.383241 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9465 22:54:36.386738 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9466 22:54:36.393292 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9467 22:54:36.396317 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9468 22:54:36.400308 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9469 22:54:36.406891 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9470 22:54:36.409626 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9471 22:54:36.416480 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9472 22:54:36.420312 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9473 22:54:36.422966 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9474 22:54:36.430364 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9475 22:54:36.433022 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9476 22:54:36.440055 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9477 22:54:36.443196 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9478 22:54:36.446690 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9479 22:54:36.453400 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9480 22:54:36.456597 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9481 22:54:36.459890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9482 22:54:36.466399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9483 22:54:36.469615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9484 22:54:36.473513 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9485 22:54:36.476640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9486 22:54:36.483772 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9487 22:54:36.486848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9488 22:54:36.489848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9489 22:54:36.493424 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9490 22:54:36.499777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9491 22:54:36.503315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9492 22:54:36.507168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9493 22:54:36.509720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9494 22:54:36.516386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9495 22:54:36.519744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9496 22:54:36.523152 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9497 22:54:36.529991 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9498 22:54:36.533686 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9499 22:54:36.537350 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9500 22:54:36.543244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9501 22:54:36.546867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9502 22:54:36.553427 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9503 22:54:36.557004 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9504 22:54:36.560441 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9505 22:54:36.566624 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9506 22:54:36.570404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9507 22:54:36.577073 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9508 22:54:36.580454 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9509 22:54:36.586699 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9510 22:54:36.590004 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9511 22:54:36.596913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9512 22:54:36.600122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9513 22:54:36.603792 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9514 22:54:36.610185 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9515 22:54:36.613808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9516 22:54:36.621062 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9517 22:54:36.623766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9518 22:54:36.627071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9519 22:54:36.633725 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9520 22:54:36.637076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9521 22:54:36.643728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9522 22:54:36.647732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9523 22:54:36.654116 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9524 22:54:36.657486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9525 22:54:36.660828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9526 22:54:36.667406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9527 22:54:36.670887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9528 22:54:36.677133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9529 22:54:36.680729 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9530 22:54:36.687541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9531 22:54:36.690673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9532 22:54:36.693735 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9533 22:54:36.700303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9534 22:54:36.704129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9535 22:54:36.710709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9536 22:54:36.713815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9537 22:54:36.721071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9538 22:54:36.724043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9539 22:54:36.727733 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9540 22:54:36.734311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9541 22:54:36.737196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9542 22:54:36.744429 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9543 22:54:36.747940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9544 22:54:36.754346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9545 22:54:36.757653 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9546 22:54:36.761113 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9547 22:54:36.764019 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9548 22:54:36.770630 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9549 22:54:36.773816 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9550 22:54:36.777763 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9551 22:54:36.784306 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9552 22:54:36.787199 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9553 22:54:36.793557 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9554 22:54:36.796940 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9555 22:54:36.800240 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9556 22:54:36.806948 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9557 22:54:36.810689 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9558 22:54:36.817048 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9559 22:54:36.820655 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9560 22:54:36.824124 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9561 22:54:36.830877 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9562 22:54:36.834014 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9563 22:54:36.840558 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9564 22:54:36.843980 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9565 22:54:36.847138 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9566 22:54:36.850453 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9567 22:54:36.857235 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9568 22:54:36.860337 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9569 22:54:36.863646 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9570 22:54:36.867625 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9571 22:54:36.874559 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9572 22:54:36.877506 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9573 22:54:36.880881 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9574 22:54:36.887689 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9575 22:54:36.890650 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9576 22:54:36.894191 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9577 22:54:36.901046 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9578 22:54:36.904349 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9579 22:54:36.910977 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9580 22:54:36.914086 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9581 22:54:36.917462 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9582 22:54:36.923896 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9583 22:54:36.927197 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9584 22:54:36.934108 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9585 22:54:36.936938 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9586 22:54:36.940738 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9587 22:54:36.947139 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9588 22:54:36.950416 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9589 22:54:36.956968 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9590 22:54:36.960350 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9591 22:54:36.963746 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9592 22:54:36.970962 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9593 22:54:36.974211 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9594 22:54:36.977622 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9595 22:54:36.983755 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9596 22:54:36.987640 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9597 22:54:36.993669 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9598 22:54:36.997724 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9599 22:54:37.000971 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9600 22:54:37.007827 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9601 22:54:37.011005 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9602 22:54:37.014359 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9603 22:54:37.021224 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9604 22:54:37.024663 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9605 22:54:37.031137 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9606 22:54:37.034457 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9607 22:54:37.037642 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9608 22:54:37.044621 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9609 22:54:37.048005 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9610 22:54:37.051049 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9611 22:54:37.057643 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9612 22:54:37.061287 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9613 22:54:37.067794 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9614 22:54:37.070931 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9615 22:54:37.074394 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9616 22:54:37.081539 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9617 22:54:37.084285 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9618 22:54:37.087792 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9619 22:54:37.094576 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9620 22:54:37.097885 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9621 22:54:37.104537 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9622 22:54:37.108112 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9623 22:54:37.111081 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9624 22:54:37.117749 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9625 22:54:37.121065 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9626 22:54:37.127724 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9627 22:54:37.131134 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9628 22:54:37.134418 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9629 22:54:37.140859 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9630 22:54:37.144739 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9631 22:54:37.148301 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9632 22:54:37.154052 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9633 22:54:37.157901 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9634 22:54:37.164612 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9635 22:54:37.167672 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9636 22:54:37.170907 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9637 22:54:37.177554 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9638 22:54:37.181331 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9639 22:54:37.187343 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9640 22:54:37.190732 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9641 22:54:37.197465 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9642 22:54:37.200984 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9643 22:54:37.204272 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9644 22:54:37.210896 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9645 22:54:37.214405 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9646 22:54:37.220678 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9647 22:54:37.223979 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9648 22:54:37.227559 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9649 22:54:37.233964 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9650 22:54:37.237228 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9651 22:54:37.244040 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9652 22:54:37.247774 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9653 22:54:37.251326 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9654 22:54:37.257839 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9655 22:54:37.260685 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9656 22:54:37.267598 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9657 22:54:37.270626 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9658 22:54:37.277547 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9659 22:54:37.280913 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9660 22:54:37.284143 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9661 22:54:37.291056 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9662 22:54:37.294142 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9663 22:54:37.300380 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9664 22:54:37.304176 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9665 22:54:37.307391 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9666 22:54:37.314076 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9667 22:54:37.317424 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9668 22:54:37.324125 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9669 22:54:37.327406 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9670 22:54:37.331175 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9671 22:54:37.337930 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9672 22:54:37.340917 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9673 22:54:37.347326 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9674 22:54:37.350548 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9675 22:54:37.357262 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9676 22:54:37.360694 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9677 22:54:37.364583 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9678 22:54:37.371077 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9679 22:54:37.374037 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9680 22:54:37.377233 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9681 22:54:37.381150 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9682 22:54:37.383651 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9683 22:54:37.390428 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9684 22:54:37.393778 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9685 22:54:37.400335 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9686 22:54:37.403558 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9687 22:54:37.407235 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9688 22:54:37.413398 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9689 22:54:37.417313 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9690 22:54:37.423880 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9691 22:54:37.426754 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9692 22:54:37.430025 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9693 22:54:37.437225 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9694 22:54:37.440387 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9695 22:54:37.443691 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9696 22:54:37.450382 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9697 22:54:37.453826 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9698 22:54:37.457013 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9699 22:54:37.463678 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9700 22:54:37.467133 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9701 22:54:37.473546 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9702 22:54:37.476814 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9703 22:54:37.480490 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9704 22:54:37.486780 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9705 22:54:37.489926 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9706 22:54:37.493261 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9707 22:54:37.500082 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9708 22:54:37.503407 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9709 22:54:37.506588 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9710 22:54:37.513457 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9711 22:54:37.516724 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9712 22:54:37.520308 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9713 22:54:37.526730 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9714 22:54:37.530159 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9715 22:54:37.536677 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9716 22:54:37.540363 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9717 22:54:37.543264 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9718 22:54:37.547147 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9719 22:54:37.553392 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9720 22:54:37.557072 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9721 22:54:37.559985 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9722 22:54:37.563226 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9723 22:54:37.569954 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9724 22:54:37.573397 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9725 22:54:37.576611 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9726 22:54:37.580139 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9727 22:54:37.586838 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9728 22:54:37.589764 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9729 22:54:37.593225 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9730 22:54:37.597145 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9731 22:54:37.603580 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9732 22:54:37.606868 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9733 22:54:37.613352 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9734 22:54:37.616215 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9735 22:54:37.623239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9736 22:54:37.626509 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9737 22:54:37.629791 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9738 22:54:37.636484 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9739 22:54:37.639755 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9740 22:54:37.646361 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9741 22:54:37.649550 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9742 22:54:37.653067 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9743 22:54:37.659497 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9744 22:54:37.663239 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9745 22:54:37.669489 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9746 22:54:37.672728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9747 22:54:37.675987 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9748 22:54:37.682468 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9749 22:54:37.686390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9750 22:54:37.692822 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9751 22:54:37.695648 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9752 22:54:37.702911 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9753 22:54:37.705955 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9754 22:54:37.708931 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9755 22:54:37.715672 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9756 22:54:37.718882 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9757 22:54:37.725981 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9758 22:54:37.728882 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9759 22:54:37.732709 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9760 22:54:37.739435 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9761 22:54:37.742164 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9762 22:54:37.748964 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9763 22:54:37.752717 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9764 22:54:37.755628 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9765 22:54:37.762174 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9766 22:54:37.765513 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9767 22:54:37.772632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9768 22:54:37.775986 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9769 22:54:37.782708 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9770 22:54:37.785429 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9771 22:54:37.789028 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9772 22:54:37.795166 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9773 22:54:37.798904 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9774 22:54:37.805356 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9775 22:54:37.808650 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9776 22:54:37.811636 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9777 22:54:37.818454 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9778 22:54:37.821926 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9779 22:54:37.828578 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9780 22:54:37.832287 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9781 22:54:37.835492 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9782 22:54:37.841683 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9783 22:54:37.844960 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9784 22:54:37.851716 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9785 22:54:37.855072 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9786 22:54:37.858309 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9787 22:54:37.865499 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9788 22:54:37.868324 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9789 22:54:37.875198 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9790 22:54:37.878870 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9791 22:54:37.882009 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9792 22:54:37.888740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9793 22:54:37.892002 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9794 22:54:37.898520 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9795 22:54:37.901914 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9796 22:54:37.905296 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9797 22:54:37.912026 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9798 22:54:37.914998 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9799 22:54:37.922020 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9800 22:54:37.925155 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9801 22:54:37.931564 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9802 22:54:37.934926 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9803 22:54:37.938319 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9804 22:54:37.944786 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9805 22:54:37.948289 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9806 22:54:37.955389 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9807 22:54:37.958699 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9808 22:54:37.965304 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9809 22:54:37.968633 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9810 22:54:37.972012 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9811 22:54:37.978362 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9812 22:54:37.981424 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9813 22:54:37.988402 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9814 22:54:37.991406 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9815 22:54:37.998535 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9816 22:54:38.001669 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9817 22:54:38.005094 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9818 22:54:38.011734 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9819 22:54:38.014988 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9820 22:54:38.021667 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9821 22:54:38.025404 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9822 22:54:38.031599 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9823 22:54:38.034887 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9824 22:54:38.038089 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9825 22:54:38.044841 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9826 22:54:38.048435 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9827 22:54:38.055199 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9828 22:54:38.058189 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9829 22:54:38.064501 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9830 22:54:38.068116 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9831 22:54:38.071417 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9832 22:54:38.078212 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9833 22:54:38.081473 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9834 22:54:38.087838 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9835 22:54:38.091906 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9836 22:54:38.098151 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9837 22:54:38.101148 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9838 22:54:38.104503 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9839 22:54:38.111322 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9840 22:54:38.114521 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9841 22:54:38.121611 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9842 22:54:38.124834 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9843 22:54:38.131417 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9844 22:54:38.134724 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9845 22:54:38.138109 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9846 22:54:38.144425 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9847 22:54:38.147968 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9848 22:54:38.154798 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9849 22:54:38.157639 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9850 22:54:38.164696 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9851 22:54:38.167749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9852 22:54:38.170897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9853 22:54:38.177613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9854 22:54:38.181208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9855 22:54:38.187769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9856 22:54:38.191127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9857 22:54:38.197898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9858 22:54:38.201071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9859 22:54:38.208111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9860 22:54:38.211102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9861 22:54:38.217889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9862 22:54:38.220888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9863 22:54:38.227465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9864 22:54:38.230695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9865 22:54:38.237933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9866 22:54:38.240636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9867 22:54:38.247377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9868 22:54:38.250740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9869 22:54:38.257381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9870 22:54:38.260620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9871 22:54:38.263820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9872 22:54:38.270853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9873 22:54:38.277245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9874 22:54:38.280654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9875 22:54:38.287416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9876 22:54:38.290850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9877 22:54:38.297561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9878 22:54:38.300866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9879 22:54:38.307521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9880 22:54:38.310596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9881 22:54:38.317073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9882 22:54:38.320358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9883 22:54:38.323608 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9884 22:54:38.327442 INFO: [APUAPC] vio 0
9885 22:54:38.330470 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9886 22:54:38.337470 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9887 22:54:38.340398 INFO: [APUAPC] D0_APC_0: 0x400510
9888 22:54:38.344279 INFO: [APUAPC] D0_APC_1: 0x0
9889 22:54:38.347204 INFO: [APUAPC] D0_APC_2: 0x1540
9890 22:54:38.347288 INFO: [APUAPC] D0_APC_3: 0x0
9891 22:54:38.350170 INFO: [APUAPC] D1_APC_0: 0xffffffff
9892 22:54:38.357217 INFO: [APUAPC] D1_APC_1: 0xffffffff
9893 22:54:38.357304 INFO: [APUAPC] D1_APC_2: 0x3fffff
9894 22:54:38.360599 INFO: [APUAPC] D1_APC_3: 0x0
9895 22:54:38.364058 INFO: [APUAPC] D2_APC_0: 0xffffffff
9896 22:54:38.367221 INFO: [APUAPC] D2_APC_1: 0xffffffff
9897 22:54:38.370524 INFO: [APUAPC] D2_APC_2: 0x3fffff
9898 22:54:38.373580 INFO: [APUAPC] D2_APC_3: 0x0
9899 22:54:38.376740 INFO: [APUAPC] D3_APC_0: 0xffffffff
9900 22:54:38.380698 INFO: [APUAPC] D3_APC_1: 0xffffffff
9901 22:54:38.383417 INFO: [APUAPC] D3_APC_2: 0x3fffff
9902 22:54:38.386789 INFO: [APUAPC] D3_APC_3: 0x0
9903 22:54:38.390126 INFO: [APUAPC] D4_APC_0: 0xffffffff
9904 22:54:38.393308 INFO: [APUAPC] D4_APC_1: 0xffffffff
9905 22:54:38.397006 INFO: [APUAPC] D4_APC_2: 0x3fffff
9906 22:54:38.400491 INFO: [APUAPC] D4_APC_3: 0x0
9907 22:54:38.403598 INFO: [APUAPC] D5_APC_0: 0xffffffff
9908 22:54:38.407145 INFO: [APUAPC] D5_APC_1: 0xffffffff
9909 22:54:38.410505 INFO: [APUAPC] D5_APC_2: 0x3fffff
9910 22:54:38.413906 INFO: [APUAPC] D5_APC_3: 0x0
9911 22:54:38.417227 INFO: [APUAPC] D6_APC_0: 0xffffffff
9912 22:54:38.420268 INFO: [APUAPC] D6_APC_1: 0xffffffff
9913 22:54:38.423411 INFO: [APUAPC] D6_APC_2: 0x3fffff
9914 22:54:38.426823 INFO: [APUAPC] D6_APC_3: 0x0
9915 22:54:38.430048 INFO: [APUAPC] D7_APC_0: 0xffffffff
9916 22:54:38.433475 INFO: [APUAPC] D7_APC_1: 0xffffffff
9917 22:54:38.436755 INFO: [APUAPC] D7_APC_2: 0x3fffff
9918 22:54:38.439883 INFO: [APUAPC] D7_APC_3: 0x0
9919 22:54:38.443318 INFO: [APUAPC] D8_APC_0: 0xffffffff
9920 22:54:38.446821 INFO: [APUAPC] D8_APC_1: 0xffffffff
9921 22:54:38.450589 INFO: [APUAPC] D8_APC_2: 0x3fffff
9922 22:54:38.453650 INFO: [APUAPC] D8_APC_3: 0x0
9923 22:54:38.456756 INFO: [APUAPC] D9_APC_0: 0xffffffff
9924 22:54:38.460328 INFO: [APUAPC] D9_APC_1: 0xffffffff
9925 22:54:38.463162 INFO: [APUAPC] D9_APC_2: 0x3fffff
9926 22:54:38.466792 INFO: [APUAPC] D9_APC_3: 0x0
9927 22:54:38.470179 INFO: [APUAPC] D10_APC_0: 0xffffffff
9928 22:54:38.473391 INFO: [APUAPC] D10_APC_1: 0xffffffff
9929 22:54:38.476336 INFO: [APUAPC] D10_APC_2: 0x3fffff
9930 22:54:38.479867 INFO: [APUAPC] D10_APC_3: 0x0
9931 22:54:38.483604 INFO: [APUAPC] D11_APC_0: 0xffffffff
9932 22:54:38.486685 INFO: [APUAPC] D11_APC_1: 0xffffffff
9933 22:54:38.489822 INFO: [APUAPC] D11_APC_2: 0x3fffff
9934 22:54:38.492849 INFO: [APUAPC] D11_APC_3: 0x0
9935 22:54:38.496196 INFO: [APUAPC] D12_APC_0: 0xffffffff
9936 22:54:38.499735 INFO: [APUAPC] D12_APC_1: 0xffffffff
9937 22:54:38.502969 INFO: [APUAPC] D12_APC_2: 0x3fffff
9938 22:54:38.506837 INFO: [APUAPC] D12_APC_3: 0x0
9939 22:54:38.510179 INFO: [APUAPC] D13_APC_0: 0xffffffff
9940 22:54:38.513257 INFO: [APUAPC] D13_APC_1: 0xffffffff
9941 22:54:38.516459 INFO: [APUAPC] D13_APC_2: 0x3fffff
9942 22:54:38.519831 INFO: [APUAPC] D13_APC_3: 0x0
9943 22:54:38.523036 INFO: [APUAPC] D14_APC_0: 0xffffffff
9944 22:54:38.526527 INFO: [APUAPC] D14_APC_1: 0xffffffff
9945 22:54:38.529985 INFO: [APUAPC] D14_APC_2: 0x3fffff
9946 22:54:38.532822 INFO: [APUAPC] D14_APC_3: 0x0
9947 22:54:38.536465 INFO: [APUAPC] D15_APC_0: 0xffffffff
9948 22:54:38.539599 INFO: [APUAPC] D15_APC_1: 0xffffffff
9949 22:54:38.542796 INFO: [APUAPC] D15_APC_2: 0x3fffff
9950 22:54:38.546182 INFO: [APUAPC] D15_APC_3: 0x0
9951 22:54:38.549481 INFO: [APUAPC] APC_CON: 0x4
9952 22:54:38.552668 INFO: [NOCDAPC] D0_APC_0: 0x0
9953 22:54:38.552746 INFO: [NOCDAPC] D0_APC_1: 0x0
9954 22:54:38.556092 INFO: [NOCDAPC] D1_APC_0: 0x0
9955 22:54:38.560028 INFO: [NOCDAPC] D1_APC_1: 0xfff
9956 22:54:38.563038 INFO: [NOCDAPC] D2_APC_0: 0x0
9957 22:54:38.566075 INFO: [NOCDAPC] D2_APC_1: 0xfff
9958 22:54:38.569578 INFO: [NOCDAPC] D3_APC_0: 0x0
9959 22:54:38.573154 INFO: [NOCDAPC] D3_APC_1: 0xfff
9960 22:54:38.576038 INFO: [NOCDAPC] D4_APC_0: 0x0
9961 22:54:38.579404 INFO: [NOCDAPC] D4_APC_1: 0xfff
9962 22:54:38.582833 INFO: [NOCDAPC] D5_APC_0: 0x0
9963 22:54:38.582913 INFO: [NOCDAPC] D5_APC_1: 0xfff
9964 22:54:38.585965 INFO: [NOCDAPC] D6_APC_0: 0x0
9965 22:54:38.589847 INFO: [NOCDAPC] D6_APC_1: 0xfff
9966 22:54:38.593056 INFO: [NOCDAPC] D7_APC_0: 0x0
9967 22:54:38.596157 INFO: [NOCDAPC] D7_APC_1: 0xfff
9968 22:54:38.599833 INFO: [NOCDAPC] D8_APC_0: 0x0
9969 22:54:38.602892 INFO: [NOCDAPC] D8_APC_1: 0xfff
9970 22:54:38.605800 INFO: [NOCDAPC] D9_APC_0: 0x0
9971 22:54:38.609034 INFO: [NOCDAPC] D9_APC_1: 0xfff
9972 22:54:38.612474 INFO: [NOCDAPC] D10_APC_0: 0x0
9973 22:54:38.615706 INFO: [NOCDAPC] D10_APC_1: 0xfff
9974 22:54:38.618978 INFO: [NOCDAPC] D11_APC_0: 0x0
9975 22:54:38.622628 INFO: [NOCDAPC] D11_APC_1: 0xfff
9976 22:54:38.622709 INFO: [NOCDAPC] D12_APC_0: 0x0
9977 22:54:38.626037 INFO: [NOCDAPC] D12_APC_1: 0xfff
9978 22:54:38.629313 INFO: [NOCDAPC] D13_APC_0: 0x0
9979 22:54:38.632619 INFO: [NOCDAPC] D13_APC_1: 0xfff
9980 22:54:38.636006 INFO: [NOCDAPC] D14_APC_0: 0x0
9981 22:54:38.639312 INFO: [NOCDAPC] D14_APC_1: 0xfff
9982 22:54:38.642422 INFO: [NOCDAPC] D15_APC_0: 0x0
9983 22:54:38.646032 INFO: [NOCDAPC] D15_APC_1: 0xfff
9984 22:54:38.649069 INFO: [NOCDAPC] APC_CON: 0x4
9985 22:54:38.652380 INFO: [APUAPC] set_apusys_apc done
9986 22:54:38.655802 INFO: [DEVAPC] devapc_init done
9987 22:54:38.659498 INFO: GICv3 without legacy support detected.
9988 22:54:38.662564 INFO: ARM GICv3 driver initialized in EL3
9989 22:54:38.665858 INFO: Maximum SPI INTID supported: 639
9990 22:54:38.672542 INFO: BL31: Initializing runtime services
9991 22:54:38.675771 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9992 22:54:38.679667 INFO: SPM: enable CPC mode
9993 22:54:38.685700 INFO: mcdi ready for mcusys-off-idle and system suspend
9994 22:54:38.689507 INFO: BL31: Preparing for EL3 exit to normal world
9995 22:54:38.692397 INFO: Entry point address = 0x80000000
9996 22:54:38.695510 INFO: SPSR = 0x8
9997 22:54:38.700986
9998 22:54:38.701066
9999 22:54:38.701134
10000 22:54:38.704193 Starting depthcharge on Spherion...
10001 22:54:38.704269
10002 22:54:38.704331 Wipe memory regions:
10003 22:54:38.704400
10004 22:54:38.705071 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10005 22:54:38.705178 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10006 22:54:38.705259 Setting prompt string to ['asurada:']
10007 22:54:38.705335 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10008 22:54:38.707833 [0x00000040000000, 0x00000054600000)
10009 22:54:38.830093
10010 22:54:38.830224 [0x00000054660000, 0x00000080000000)
10011 22:54:39.090356
10012 22:54:39.090495 [0x000000821a7280, 0x000000ffe64000)
10013 22:54:39.835686
10014 22:54:39.835837 [0x00000100000000, 0x00000240000000)
10015 22:54:41.726218
10016 22:54:41.728955 Initializing XHCI USB controller at 0x11200000.
10017 22:54:42.767766
10018 22:54:42.771235 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10019 22:54:42.771346
10020 22:54:42.771416
10021 22:54:42.771482
10022 22:54:42.771802 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10024 22:54:42.872192 asurada: tftpboot 192.168.201.1 13683680/tftp-deploy-ae11a8wq/kernel/image.itb 13683680/tftp-deploy-ae11a8wq/kernel/cmdline
10025 22:54:42.872343 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10026 22:54:42.872437 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10027 22:54:42.876598 tftpboot 192.168.201.1 13683680/tftp-deploy-ae11a8wq/kernel/image.itp-deploy-ae11a8wq/kernel/cmdline
10028 22:54:42.876686
10029 22:54:42.876760 Waiting for link
10030 22:54:43.037016
10031 22:54:43.037163 R8152: Initializing
10032 22:54:43.037253
10033 22:54:43.040206 Version 9 (ocp_data = 6010)
10034 22:54:43.040285
10035 22:54:43.043607 R8152: Done initializing
10036 22:54:43.043699
10037 22:54:43.043766 Adding net device
10038 22:54:44.916610
10039 22:54:44.916760 done.
10040 22:54:44.916827
10041 22:54:44.916935 MAC: 00:e0:4c:78:7a:aa
10042 22:54:44.917033
10043 22:54:44.919745 Sending DHCP discover... done.
10044 22:54:44.919826
10045 22:54:50.680265 Waiting for reply... done.
10046 22:54:50.680436
10047 22:54:50.680533 Sending DHCP request... done.
10048 22:54:50.684225
10049 22:54:50.684302 Waiting for reply... done.
10050 22:54:50.684365
10051 22:54:50.686824 My ip is 192.168.201.12
10052 22:54:50.686890
10053 22:54:50.690235 The DHCP server ip is 192.168.201.1
10054 22:54:50.690304
10055 22:54:50.693598 TFTP server IP predefined by user: 192.168.201.1
10056 22:54:50.693666
10057 22:54:50.700240 Bootfile predefined by user: 13683680/tftp-deploy-ae11a8wq/kernel/image.itb
10058 22:54:50.700313
10059 22:54:50.703782 Sending tftp read request... done.
10060 22:54:50.703855
10061 22:54:50.706859 Waiting for the transfer...
10062 22:54:50.706937
10063 22:54:50.957834 00000000 ################################################################
10064 22:54:50.957967
10065 22:54:51.208365 00080000 ################################################################
10066 22:54:51.208516
10067 22:54:51.460567 00100000 ################################################################
10068 22:54:51.460707
10069 22:54:51.715908 00180000 ################################################################
10070 22:54:51.716115
10071 22:54:51.967940 00200000 ################################################################
10072 22:54:51.968101
10073 22:54:52.216198 00280000 ################################################################
10074 22:54:52.216339
10075 22:54:52.463651 00300000 ################################################################
10076 22:54:52.463812
10077 22:54:52.711853 00380000 ################################################################
10078 22:54:52.712053
10079 22:54:52.957598 00400000 ################################################################
10080 22:54:52.957744
10081 22:54:53.206226 00480000 ################################################################
10082 22:54:53.206365
10083 22:54:53.456398 00500000 ################################################################
10084 22:54:53.456527
10085 22:54:53.703695 00580000 ################################################################
10086 22:54:53.703830
10087 22:54:53.957527 00600000 ################################################################
10088 22:54:53.957658
10089 22:54:54.208089 00680000 ################################################################
10090 22:54:54.208221
10091 22:54:54.459961 00700000 ################################################################
10092 22:54:54.460123
10093 22:54:54.724522 00780000 ################################################################
10094 22:54:54.724652
10095 22:54:54.975323 00800000 ################################################################
10096 22:54:54.975485
10097 22:54:55.227314 00880000 ################################################################
10098 22:54:55.227477
10099 22:54:55.481077 00900000 ################################################################
10100 22:54:55.481243
10101 22:54:55.731611 00980000 ################################################################
10102 22:54:55.731768
10103 22:54:55.979871 00a00000 ################################################################
10104 22:54:55.980070
10105 22:54:56.236708 00a80000 ################################################################
10106 22:54:56.236845
10107 22:54:56.488007 00b00000 ################################################################
10108 22:54:56.488138
10109 22:54:56.752355 00b80000 ################################################################
10110 22:54:56.752494
10111 22:54:57.001386 00c00000 ################################################################
10112 22:54:57.001518
10113 22:54:57.250193 00c80000 ################################################################
10114 22:54:57.250330
10115 22:54:57.498184 00d00000 ################################################################
10116 22:54:57.498375
10117 22:54:57.744791 00d80000 ################################################################
10118 22:54:57.744924
10119 22:54:57.993120 00e00000 ################################################################
10120 22:54:57.993290
10121 22:54:58.243828 00e80000 ################################################################
10122 22:54:58.243969
10123 22:54:58.491428 00f00000 ################################################################
10124 22:54:58.491565
10125 22:54:58.749971 00f80000 ################################################################
10126 22:54:58.750131
10127 22:54:59.008342 01000000 ################################################################
10128 22:54:59.008476
10129 22:54:59.268017 01080000 ################################################################
10130 22:54:59.268150
10131 22:54:59.515405 01100000 ################################################################
10132 22:54:59.515607
10133 22:54:59.778724 01180000 ################################################################
10134 22:54:59.778853
10135 22:55:00.037803 01200000 ################################################################
10136 22:55:00.037937
10137 22:55:00.290456 01280000 ################################################################
10138 22:55:00.290595
10139 22:55:00.549404 01300000 ################################################################
10140 22:55:00.549537
10141 22:55:00.794991 01380000 ################################################################
10142 22:55:00.795142
10143 22:55:01.041681 01400000 ################################################################
10144 22:55:01.041870
10145 22:55:01.293977 01480000 ################################################################
10146 22:55:01.294145
10147 22:55:01.540000 01500000 ################################################################
10148 22:55:01.540163
10149 22:55:01.788797 01580000 ################################################################
10150 22:55:01.788958
10151 22:55:02.040846 01600000 ################################################################
10152 22:55:02.040999
10153 22:55:02.305590 01680000 ################################################################
10154 22:55:02.305728
10155 22:55:02.563417 01700000 ################################################################
10156 22:55:02.563565
10157 22:55:02.809676 01780000 ################################################################
10158 22:55:02.809850
10159 22:55:03.059917 01800000 ################################################################
10160 22:55:03.060107
10161 22:55:03.316477 01880000 ################################################################
10162 22:55:03.316647
10163 22:55:03.575351 01900000 ################################################################
10164 22:55:03.575488
10165 22:55:03.830374 01980000 ################################################################
10166 22:55:03.830517
10167 22:55:04.082244 01a00000 ################################################################
10168 22:55:04.082377
10169 22:55:04.345063 01a80000 ################################################################
10170 22:55:04.345211
10171 22:55:04.598681 01b00000 ################################################################
10172 22:55:04.598833
10173 22:55:04.853521 01b80000 ################################################################
10174 22:55:04.853710
10175 22:55:05.099966 01c00000 ################################################################
10176 22:55:05.100141
10177 22:55:05.354983 01c80000 ################################################################
10178 22:55:05.355169
10179 22:55:05.606598 01d00000 ################################################################
10180 22:55:05.606783
10181 22:55:05.861028 01d80000 ################################################################
10182 22:55:05.861173
10183 22:55:06.110639 01e00000 ################################################################
10184 22:55:06.110803
10185 22:55:06.367782 01e80000 ################################################################
10186 22:55:06.367920
10187 22:55:06.620839 01f00000 ################################################################
10188 22:55:06.620990
10189 22:55:06.876424 01f80000 ################################################################
10190 22:55:06.876616
10191 22:55:07.132907 02000000 ################################################################
10192 22:55:07.133083
10193 22:55:07.386245 02080000 ################################################################
10194 22:55:07.386421
10195 22:55:07.637230 02100000 ################################################################
10196 22:55:07.637403
10197 22:55:07.893866 02180000 ################################################################
10198 22:55:07.894044
10199 22:55:08.150942 02200000 ################################################################
10200 22:55:08.151107
10201 22:55:08.412473 02280000 ################################################################
10202 22:55:08.412643
10203 22:55:08.676740 02300000 ################################################################
10204 22:55:08.676906
10205 22:55:08.931626 02380000 ################################################################
10206 22:55:08.931801
10207 22:55:09.181794 02400000 ################################################################
10208 22:55:09.181963
10209 22:55:09.431685 02480000 ################################################################
10210 22:55:09.431821
10211 22:55:09.676873 02500000 ################################################################
10212 22:55:09.677024
10213 22:55:09.924322 02580000 ################################################################
10214 22:55:09.924478
10215 22:55:10.173514 02600000 ################################################################
10216 22:55:10.173658
10217 22:55:10.421805 02680000 ################################################################
10218 22:55:10.421970
10219 22:55:10.670482 02700000 ################################################################
10220 22:55:10.670620
10221 22:55:10.916697 02780000 ################################################################
10222 22:55:10.916834
10223 22:55:11.169417 02800000 ################################################################
10224 22:55:11.169571
10225 22:55:11.416183 02880000 ################################################################
10226 22:55:11.416345
10227 22:55:11.663239 02900000 ################################################################
10228 22:55:11.663419
10229 22:55:11.910204 02980000 ################################################################
10230 22:55:11.910385
10231 22:55:12.156599 02a00000 ################################################################
10232 22:55:12.156798
10233 22:55:12.402410 02a80000 ################################################################
10234 22:55:12.402551
10235 22:55:12.652718 02b00000 ################################################################
10236 22:55:12.652891
10237 22:55:12.894449 02b80000 ################################################################
10238 22:55:12.894612
10239 22:55:13.142663 02c00000 ################################################################
10240 22:55:13.142795
10241 22:55:13.392809 02c80000 ################################################################
10242 22:55:13.392956
10243 22:55:13.640300 02d00000 ################################################################
10244 22:55:13.640468
10245 22:55:13.896199 02d80000 ################################################################
10246 22:55:13.896351
10247 22:55:14.146447 02e00000 ################################################################
10248 22:55:14.146616
10249 22:55:14.398828 02e80000 ################################################################
10250 22:55:14.399004
10251 22:55:14.659422 02f00000 ################################################################
10252 22:55:14.659585
10253 22:55:14.906424 02f80000 ################################################################
10254 22:55:14.906584
10255 22:55:15.155005 03000000 ################################################################
10256 22:55:15.155170
10257 22:55:15.404677 03080000 ################################################################
10258 22:55:15.404838
10259 22:55:15.658942 03100000 ################################################################
10260 22:55:15.659084
10261 22:55:15.926826 03180000 ################################################################
10262 22:55:15.926984
10263 22:55:16.184046 03200000 ################################################################
10264 22:55:16.184188
10265 22:55:16.446766 03280000 ################################################################
10266 22:55:16.446939
10267 22:55:16.703633 03300000 ################################################################
10268 22:55:16.703801
10269 22:55:16.956052 03380000 ################################################################
10270 22:55:16.956210
10271 22:55:17.205729 03400000 ################################################################
10272 22:55:17.205934
10273 22:55:17.466113 03480000 ################################################################
10274 22:55:17.466250
10275 22:55:17.718710 03500000 ################################################################
10276 22:55:17.718872
10277 22:55:17.966446 03580000 ################################################################
10278 22:55:17.966606
10279 22:55:18.221221 03600000 ################################################################
10280 22:55:18.221384
10281 22:55:18.469736 03680000 ################################################################
10282 22:55:18.469905
10283 22:55:18.713803 03700000 ################################################################
10284 22:55:18.713964
10285 22:55:18.959256 03780000 ################################################################
10286 22:55:18.959425
10287 22:55:19.211025 03800000 ################################################################
10288 22:55:19.211206
10289 22:55:19.456217 03880000 ################################################################
10290 22:55:19.456392
10291 22:55:19.705827 03900000 ################################################################
10292 22:55:19.705990
10293 22:55:19.950591 03980000 ################################################################
10294 22:55:19.950771
10295 22:55:20.196653 03a00000 ################################################################
10296 22:55:20.196826
10297 22:55:20.442015 03a80000 ################################################################
10298 22:55:20.442178
10299 22:55:20.689226 03b00000 ################################################################
10300 22:55:20.689394
10301 22:55:20.947048 03b80000 ################################################################
10302 22:55:20.947214
10303 22:55:21.196464 03c00000 ################################################################
10304 22:55:21.196630
10305 22:55:21.447808 03c80000 ################################################################
10306 22:55:21.448001
10307 22:55:21.696163 03d00000 ################################################################
10308 22:55:21.696305
10309 22:55:21.952778 03d80000 ################################################################
10310 22:55:21.952925
10311 22:55:22.066174 03e00000 ############################ done.
10312 22:55:22.066322
10313 22:55:22.069315 The bootfile was 65238446 bytes long.
10314 22:55:22.069392
10315 22:55:22.069456 Sending tftp read request... done.
10316 22:55:22.073073
10317 22:55:22.073171 Waiting for the transfer...
10318 22:55:22.073270
10319 22:55:22.075944 00000000 # done.
10320 22:55:22.076039
10321 22:55:22.082758 Command line loaded dynamically from TFTP file: 13683680/tftp-deploy-ae11a8wq/kernel/cmdline
10322 22:55:22.082860
10323 22:55:22.096499 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10324 22:55:22.096587
10325 22:55:22.099082 Loading FIT.
10326 22:55:22.099162
10327 22:55:22.102698 Image ramdisk-1 has 52129598 bytes.
10328 22:55:22.102780
10329 22:55:22.102844 Image fdt-1 has 47258 bytes.
10330 22:55:22.102939
10331 22:55:22.105976 Image kernel-1 has 13059555 bytes.
10332 22:55:22.106083
10333 22:55:22.116163 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10334 22:55:22.116277
10335 22:55:22.132523 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10336 22:55:22.132633
10337 22:55:22.139230 Choosing best match conf-1 for compat google,spherion-rev2.
10338 22:55:22.143039
10339 22:55:22.147734 Connected to device vid:did:rid of 1ae0:0028:00
10340 22:55:22.155802
10341 22:55:22.159014 tpm_get_response: command 0x17b, return code 0x0
10342 22:55:22.159111
10343 22:55:22.165762 ec_init: CrosEC protocol v3 supported (256, 248)
10344 22:55:22.165862
10345 22:55:22.169020 tpm_cleanup: add release locality here.
10346 22:55:22.169095
10347 22:55:22.172266 Shutting down all USB controllers.
10348 22:55:22.172335
10349 22:55:22.175607 Removing current net device
10350 22:55:22.175700
10351 22:55:22.178943 Exiting depthcharge with code 4 at timestamp: 72731519
10352 22:55:22.179024
10353 22:55:22.185675 LZMA decompressing kernel-1 to 0x821a6718
10354 22:55:22.185773
10355 22:55:22.189260 LZMA decompressing kernel-1 to 0x40000000
10356 22:55:23.799328
10357 22:55:23.799474 jumping to kernel
10358 22:55:23.800539 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10359 22:55:23.800669 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10360 22:55:23.800777 Setting prompt string to ['Linux version [0-9]']
10361 22:55:23.800876 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10362 22:55:23.800975 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10363 22:55:23.882156
10364 22:55:23.885120 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10365 22:55:23.888586 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10366 22:55:23.888690 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10367 22:55:23.888763 Setting prompt string to []
10368 22:55:23.888841 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10369 22:55:23.888933 Using line separator: #'\n'#
10370 22:55:23.888995 No login prompt set.
10371 22:55:23.889056 Parsing kernel messages
10372 22:55:23.889112 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10373 22:55:23.889231 [login-action] Waiting for messages, (timeout 00:03:40)
10374 22:55:23.889324 Waiting using forced prompt support (timeout 00:01:50)
10375 22:55:23.908491 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10376 22:55:23.911585 [ 0.000000] random: crng init done
10377 22:55:23.918443 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10378 22:55:23.921645 [ 0.000000] efi: UEFI not found.
10379 22:55:23.928471 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10380 22:55:23.934530 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10381 22:55:23.944924 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10382 22:55:23.954493 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10383 22:55:23.961062 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10384 22:55:23.967651 [ 0.000000] printk: bootconsole [mtk8250] enabled
10385 22:55:23.974447 [ 0.000000] NUMA: No NUMA configuration found
10386 22:55:23.981134 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10387 22:55:23.984574 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10388 22:55:23.987786 [ 0.000000] Zone ranges:
10389 22:55:23.994254 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10390 22:55:23.997426 [ 0.000000] DMA32 empty
10391 22:55:24.004432 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10392 22:55:24.007114 [ 0.000000] Movable zone start for each node
10393 22:55:24.011187 [ 0.000000] Early memory node ranges
10394 22:55:24.017400 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10395 22:55:24.024413 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10396 22:55:24.031073 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10397 22:55:24.037518 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10398 22:55:24.040886 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10399 22:55:24.050509 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10400 22:55:24.106797 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10401 22:55:24.112984 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10402 22:55:24.119932 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10403 22:55:24.123224 [ 0.000000] psci: probing for conduit method from DT.
10404 22:55:24.129638 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10405 22:55:24.133034 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10406 22:55:24.139596 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10407 22:55:24.142944 [ 0.000000] psci: SMC Calling Convention v1.2
10408 22:55:24.149763 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10409 22:55:24.153082 [ 0.000000] Detected VIPT I-cache on CPU0
10410 22:55:24.159549 [ 0.000000] CPU features: detected: GIC system register CPU interface
10411 22:55:24.165953 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10412 22:55:24.172445 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10413 22:55:24.179567 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10414 22:55:24.189340 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10415 22:55:24.195611 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10416 22:55:24.199180 [ 0.000000] alternatives: applying boot alternatives
10417 22:55:24.206053 [ 0.000000] Fallback order for Node 0: 0
10418 22:55:24.212333 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10419 22:55:24.216018 [ 0.000000] Policy zone: Normal
10420 22:55:24.228816 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10421 22:55:24.238770 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10422 22:55:24.250297 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10423 22:55:24.260145 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10424 22:55:24.266688 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10425 22:55:24.269971 <6>[ 0.000000] software IO TLB: area num 8.
10426 22:55:24.326048 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10427 22:55:24.475597 <6>[ 0.000000] Memory: 7913280K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 439488K reserved, 32768K cma-reserved)
10428 22:55:24.482171 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10429 22:55:24.488995 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10430 22:55:24.492130 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10431 22:55:24.498991 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10432 22:55:24.505371 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10433 22:55:24.509131 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10434 22:55:24.519168 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10435 22:55:24.525638 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10436 22:55:24.529083 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10437 22:55:24.536464 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10438 22:55:24.539977 <6>[ 0.000000] GICv3: 608 SPIs implemented
10439 22:55:24.546319 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10440 22:55:24.549955 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10441 22:55:24.553418 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10442 22:55:24.563289 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10443 22:55:24.572757 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10444 22:55:24.586403 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10445 22:55:24.592923 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10446 22:55:24.601929 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10447 22:55:24.615598 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10448 22:55:24.621921 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10449 22:55:24.628639 <6>[ 0.009183] Console: colour dummy device 80x25
10450 22:55:24.638751 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10451 22:55:24.642093 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10452 22:55:24.648865 <6>[ 0.029222] LSM: Security Framework initializing
10453 22:55:24.655417 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 22:55:24.664992 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10455 22:55:24.671688 <6>[ 0.051410] cblist_init_generic: Setting adjustable number of callback queues.
10456 22:55:24.678862 <6>[ 0.058900] cblist_init_generic: Setting shift to 3 and lim to 1.
10457 22:55:24.688412 <6>[ 0.065277] cblist_init_generic: Setting adjustable number of callback queues.
10458 22:55:24.694954 <6>[ 0.072704] cblist_init_generic: Setting shift to 3 and lim to 1.
10459 22:55:24.698186 <6>[ 0.079119] rcu: Hierarchical SRCU implementation.
10460 22:55:24.705165 <6>[ 0.084165] rcu: Max phase no-delay instances is 1000.
10461 22:55:24.711828 <6>[ 0.091186] EFI services will not be available.
10462 22:55:24.715206 <6>[ 0.096155] smp: Bringing up secondary CPUs ...
10463 22:55:24.723261 <6>[ 0.101234] Detected VIPT I-cache on CPU1
10464 22:55:24.730007 <6>[ 0.101306] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10465 22:55:24.736461 <6>[ 0.101337] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10466 22:55:24.739835 <6>[ 0.101670] Detected VIPT I-cache on CPU2
10467 22:55:24.746575 <6>[ 0.101717] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10468 22:55:24.756196 <6>[ 0.101733] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10469 22:55:24.759310 <6>[ 0.101991] Detected VIPT I-cache on CPU3
10470 22:55:24.766578 <6>[ 0.102039] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10471 22:55:24.772602 <6>[ 0.102053] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10472 22:55:24.775896 <6>[ 0.102358] CPU features: detected: Spectre-v4
10473 22:55:24.782768 <6>[ 0.102364] CPU features: detected: Spectre-BHB
10474 22:55:24.786048 <6>[ 0.102369] Detected PIPT I-cache on CPU4
10475 22:55:24.792806 <6>[ 0.102428] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10476 22:55:24.799083 <6>[ 0.102446] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10477 22:55:24.805989 <6>[ 0.102741] Detected PIPT I-cache on CPU5
10478 22:55:24.813058 <6>[ 0.102803] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10479 22:55:24.819523 <6>[ 0.102819] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10480 22:55:24.822777 <6>[ 0.103101] Detected PIPT I-cache on CPU6
10481 22:55:24.829506 <6>[ 0.103167] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10482 22:55:24.836042 <6>[ 0.103183] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10483 22:55:24.842552 <6>[ 0.103482] Detected PIPT I-cache on CPU7
10484 22:55:24.849022 <6>[ 0.103545] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10485 22:55:24.856123 <6>[ 0.103561] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10486 22:55:24.858823 <6>[ 0.103609] smp: Brought up 1 node, 8 CPUs
10487 22:55:24.865623 <6>[ 0.244867] SMP: Total of 8 processors activated.
10488 22:55:24.869623 <6>[ 0.249818] CPU features: detected: 32-bit EL0 Support
10489 22:55:24.878955 <6>[ 0.255214] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10490 22:55:24.885683 <6>[ 0.264015] CPU features: detected: Common not Private translations
10491 22:55:24.888883 <6>[ 0.270491] CPU features: detected: CRC32 instructions
10492 22:55:24.895673 <6>[ 0.275875] CPU features: detected: RCpc load-acquire (LDAPR)
10493 22:55:24.902314 <6>[ 0.281836] CPU features: detected: LSE atomic instructions
10494 22:55:24.909103 <6>[ 0.287617] CPU features: detected: Privileged Access Never
10495 22:55:24.912209 <6>[ 0.293397] CPU features: detected: RAS Extension Support
10496 22:55:24.922219 <6>[ 0.299005] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10497 22:55:24.925859 <6>[ 0.306270] CPU: All CPU(s) started at EL2
10498 22:55:24.931834 <6>[ 0.310613] alternatives: applying system-wide alternatives
10499 22:55:24.940837 <6>[ 0.321455] devtmpfs: initialized
10500 22:55:24.953154 <6>[ 0.330423] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10501 22:55:24.962864 <6>[ 0.340384] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10502 22:55:24.969808 <6>[ 0.348424] pinctrl core: initialized pinctrl subsystem
10503 22:55:24.972888 <6>[ 0.355077] DMI not present or invalid.
10504 22:55:24.979587 <6>[ 0.359494] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10505 22:55:24.989331 <6>[ 0.366356] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10506 22:55:24.996725 <6>[ 0.373946] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10507 22:55:25.006583 <6>[ 0.382167] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10508 22:55:25.009350 <6>[ 0.390411] audit: initializing netlink subsys (disabled)
10509 22:55:25.019232 <5>[ 0.396103] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10510 22:55:25.026312 <6>[ 0.396811] thermal_sys: Registered thermal governor 'step_wise'
10511 22:55:25.032824 <6>[ 0.404069] thermal_sys: Registered thermal governor 'power_allocator'
10512 22:55:25.035933 <6>[ 0.410323] cpuidle: using governor menu
10513 22:55:25.039252 <6>[ 0.421280] NET: Registered PF_QIPCRTR protocol family
10514 22:55:25.049346 <6>[ 0.426761] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10515 22:55:25.052599 <6>[ 0.433863] ASID allocator initialised with 32768 entries
10516 22:55:25.059820 <6>[ 0.440441] Serial: AMBA PL011 UART driver
10517 22:55:25.068711 <4>[ 0.449170] Trying to register duplicate clock ID: 134
10518 22:55:25.126651 <6>[ 0.510782] KASLR enabled
10519 22:55:25.141252 <6>[ 0.518589] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10520 22:55:25.147835 <6>[ 0.525603] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10521 22:55:25.154276 <6>[ 0.532096] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10522 22:55:25.161143 <6>[ 0.539100] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10523 22:55:25.167854 <6>[ 0.545588] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10524 22:55:25.174431 <6>[ 0.552593] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10525 22:55:25.181455 <6>[ 0.559077] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10526 22:55:25.187653 <6>[ 0.566083] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10527 22:55:25.190894 <6>[ 0.573618] ACPI: Interpreter disabled.
10528 22:55:25.199722 <6>[ 0.580053] iommu: Default domain type: Translated
10529 22:55:25.205935 <6>[ 0.585168] iommu: DMA domain TLB invalidation policy: strict mode
10530 22:55:25.209620 <5>[ 0.591831] SCSI subsystem initialized
10531 22:55:25.216319 <6>[ 0.595999] usbcore: registered new interface driver usbfs
10532 22:55:25.222877 <6>[ 0.601730] usbcore: registered new interface driver hub
10533 22:55:25.225775 <6>[ 0.607283] usbcore: registered new device driver usb
10534 22:55:25.233010 <6>[ 0.613380] pps_core: LinuxPPS API ver. 1 registered
10535 22:55:25.242883 <6>[ 0.618573] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10536 22:55:25.245954 <6>[ 0.627919] PTP clock support registered
10537 22:55:25.249042 <6>[ 0.632155] EDAC MC: Ver: 3.0.0
10538 22:55:25.256594 <6>[ 0.637309] FPGA manager framework
10539 22:55:25.263265 <6>[ 0.640995] Advanced Linux Sound Architecture Driver Initialized.
10540 22:55:25.266235 <6>[ 0.647777] vgaarb: loaded
10541 22:55:25.273600 <6>[ 0.650937] clocksource: Switched to clocksource arch_sys_counter
10542 22:55:25.276333 <5>[ 0.657382] VFS: Disk quotas dquot_6.6.0
10543 22:55:25.283002 <6>[ 0.661569] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10544 22:55:25.286474 <6>[ 0.668760] pnp: PnP ACPI: disabled
10545 22:55:25.294762 <6>[ 0.675500] NET: Registered PF_INET protocol family
10546 22:55:25.305063 <6>[ 0.681109] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10547 22:55:25.316458 <6>[ 0.693455] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10548 22:55:25.326276 <6>[ 0.702273] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10549 22:55:25.332800 <6>[ 0.710247] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10550 22:55:25.339586 <6>[ 0.718948] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10551 22:55:25.351439 <6>[ 0.728705] TCP: Hash tables configured (established 65536 bind 65536)
10552 22:55:25.358032 <6>[ 0.735576] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10553 22:55:25.364909 <6>[ 0.742775] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10554 22:55:25.371002 <6>[ 0.750480] NET: Registered PF_UNIX/PF_LOCAL protocol family
10555 22:55:25.378286 <6>[ 0.756629] RPC: Registered named UNIX socket transport module.
10556 22:55:25.381884 <6>[ 0.762782] RPC: Registered udp transport module.
10557 22:55:25.387649 <6>[ 0.767717] RPC: Registered tcp transport module.
10558 22:55:25.394570 <6>[ 0.772651] RPC: Registered tcp NFSv4.1 backchannel transport module.
10559 22:55:25.397732 <6>[ 0.779319] PCI: CLS 0 bytes, default 64
10560 22:55:25.400957 <6>[ 0.783664] Unpacking initramfs...
10561 22:55:25.425914 <6>[ 0.803044] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10562 22:55:25.435523 <6>[ 0.811711] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10563 22:55:25.438822 <6>[ 0.820559] kvm [1]: IPA Size Limit: 40 bits
10564 22:55:25.445448 <6>[ 0.825088] kvm [1]: GICv3: no GICV resource entry
10565 22:55:25.448718 <6>[ 0.830108] kvm [1]: disabling GICv2 emulation
10566 22:55:25.455399 <6>[ 0.834799] kvm [1]: GIC system register CPU interface enabled
10567 22:55:25.459169 <6>[ 0.840962] kvm [1]: vgic interrupt IRQ18
10568 22:55:25.465154 <6>[ 0.845315] kvm [1]: VHE mode initialized successfully
10569 22:55:25.472704 <5>[ 0.851746] Initialise system trusted keyrings
10570 22:55:25.478472 <6>[ 0.856576] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10571 22:55:25.486040 <6>[ 0.866709] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10572 22:55:25.492875 <5>[ 0.873126] NFS: Registering the id_resolver key type
10573 22:55:25.495763 <5>[ 0.878432] Key type id_resolver registered
10574 22:55:25.503192 <5>[ 0.882850] Key type id_legacy registered
10575 22:55:25.509095 <6>[ 0.887132] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10576 22:55:25.515878 <6>[ 0.894054] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10577 22:55:25.522355 <6>[ 0.901770] 9p: Installing v9fs 9p2000 file system support
10578 22:55:25.559068 <5>[ 0.939573] Key type asymmetric registered
10579 22:55:25.562626 <5>[ 0.943902] Asymmetric key parser 'x509' registered
10580 22:55:25.572245 <6>[ 0.949045] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10581 22:55:25.575747 <6>[ 0.956658] io scheduler mq-deadline registered
10582 22:55:25.579279 <6>[ 0.961441] io scheduler kyber registered
10583 22:55:25.597694 <6>[ 0.978431] EINJ: ACPI disabled.
10584 22:55:25.630843 <4>[ 1.004982] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 22:55:25.640676 <4>[ 1.015616] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 22:55:25.655982 <6>[ 1.036790] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10587 22:55:25.663960 <6>[ 1.044829] printk: console [ttyS0] disabled
10588 22:55:25.692171 <6>[ 1.069466] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10589 22:55:25.698799 <6>[ 1.078964] printk: console [ttyS0] enabled
10590 22:55:25.701785 <6>[ 1.078964] printk: console [ttyS0] enabled
10591 22:55:25.708784 <6>[ 1.087862] printk: bootconsole [mtk8250] disabled
10592 22:55:25.711943 <6>[ 1.087862] printk: bootconsole [mtk8250] disabled
10593 22:55:25.718553 <6>[ 1.099192] SuperH (H)SCI(F) driver initialized
10594 22:55:25.721935 <6>[ 1.104475] msm_serial: driver initialized
10595 22:55:25.735891 <6>[ 1.113541] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10596 22:55:25.746283 <6>[ 1.122090] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10597 22:55:25.752923 <6>[ 1.130633] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10598 22:55:25.762628 <6>[ 1.139260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10599 22:55:25.772783 <6>[ 1.147972] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10600 22:55:25.779206 <6>[ 1.156687] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10601 22:55:25.788701 <6>[ 1.165227] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10602 22:55:25.795786 <6>[ 1.174038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10603 22:55:25.805537 <6>[ 1.182581] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10604 22:55:25.817726 <6>[ 1.198378] loop: module loaded
10605 22:55:25.824317 <6>[ 1.204338] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10606 22:55:25.846780 <4>[ 1.227718] mtk-pmic-keys: Failed to locate of_node [id: -1]
10607 22:55:25.854005 <6>[ 1.234662] megasas: 07.719.03.00-rc1
10608 22:55:25.863595 <6>[ 1.244349] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10609 22:55:25.870348 <6>[ 1.250321] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10610 22:55:25.886590 <6>[ 1.267109] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10611 22:55:25.943052 <6>[ 1.317271] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10612 22:55:27.618857 <6>[ 2.999926] Freeing initrd memory: 50904K
10613 22:55:27.630570 <6>[ 3.011578] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10614 22:55:27.641620 <6>[ 3.022546] tun: Universal TUN/TAP device driver, 1.6
10615 22:55:27.644954 <6>[ 3.028610] thunder_xcv, ver 1.0
10616 22:55:27.648160 <6>[ 3.032115] thunder_bgx, ver 1.0
10617 22:55:27.651526 <6>[ 3.035609] nicpf, ver 1.0
10618 22:55:27.661701 <6>[ 3.039629] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10619 22:55:27.665107 <6>[ 3.047106] hns3: Copyright (c) 2017 Huawei Corporation.
10620 22:55:27.671806 <6>[ 3.052695] hclge is initializing
10621 22:55:27.675325 <6>[ 3.056269] e1000: Intel(R) PRO/1000 Network Driver
10622 22:55:27.681717 <6>[ 3.061398] e1000: Copyright (c) 1999-2006 Intel Corporation.
10623 22:55:27.684918 <6>[ 3.067414] e1000e: Intel(R) PRO/1000 Network Driver
10624 22:55:27.691563 <6>[ 3.072629] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10625 22:55:27.698269 <6>[ 3.078814] igb: Intel(R) Gigabit Ethernet Network Driver
10626 22:55:27.705170 <6>[ 3.084464] igb: Copyright (c) 2007-2014 Intel Corporation.
10627 22:55:27.711582 <6>[ 3.090300] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10628 22:55:27.718584 <6>[ 3.096817] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10629 22:55:27.721557 <6>[ 3.103278] sky2: driver version 1.30
10630 22:55:27.728355 <6>[ 3.108201] usbcore: registered new device driver r8152-cfgselector
10631 22:55:27.734689 <6>[ 3.114739] usbcore: registered new interface driver r8152
10632 22:55:27.741782 <6>[ 3.120556] VFIO - User Level meta-driver version: 0.3
10633 22:55:27.747853 <6>[ 3.128798] usbcore: registered new interface driver usb-storage
10634 22:55:27.754839 <6>[ 3.135245] usbcore: registered new device driver onboard-usb-hub
10635 22:55:27.763377 <6>[ 3.144402] mt6397-rtc mt6359-rtc: registered as rtc0
10636 22:55:27.773803 <6>[ 3.149862] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:51:05 UTC (1715122265)
10637 22:55:27.776609 <6>[ 3.159437] i2c_dev: i2c /dev entries driver
10638 22:55:27.793517 <6>[ 3.171310] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10639 22:55:27.800383 <4>[ 3.180038] cpu cpu0: supply cpu not found, using dummy regulator
10640 22:55:27.806845 <4>[ 3.186480] cpu cpu1: supply cpu not found, using dummy regulator
10641 22:55:27.813506 <4>[ 3.192885] cpu cpu2: supply cpu not found, using dummy regulator
10642 22:55:27.820201 <4>[ 3.199293] cpu cpu3: supply cpu not found, using dummy regulator
10643 22:55:27.826787 <4>[ 3.205691] cpu cpu4: supply cpu not found, using dummy regulator
10644 22:55:27.833696 <4>[ 3.212086] cpu cpu5: supply cpu not found, using dummy regulator
10645 22:55:27.839852 <4>[ 3.218506] cpu cpu6: supply cpu not found, using dummy regulator
10646 22:55:27.846505 <4>[ 3.224906] cpu cpu7: supply cpu not found, using dummy regulator
10647 22:55:27.865807 <6>[ 3.246497] cpu cpu0: EM: created perf domain
10648 22:55:27.868660 <6>[ 3.251432] cpu cpu4: EM: created perf domain
10649 22:55:27.876117 <6>[ 3.257067] sdhci: Secure Digital Host Controller Interface driver
10650 22:55:27.882485 <6>[ 3.263499] sdhci: Copyright(c) Pierre Ossman
10651 22:55:27.889724 <6>[ 3.268459] Synopsys Designware Multimedia Card Interface Driver
10652 22:55:27.896422 <6>[ 3.275108] sdhci-pltfm: SDHCI platform and OF driver helper
10653 22:55:27.899653 <6>[ 3.275176] mmc0: CQHCI version 5.10
10654 22:55:27.905780 <6>[ 3.285170] ledtrig-cpu: registered to indicate activity on CPUs
10655 22:55:27.912907 <6>[ 3.292229] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10656 22:55:27.919040 <6>[ 3.299283] usbcore: registered new interface driver usbhid
10657 22:55:27.922479 <6>[ 3.305105] usbhid: USB HID core driver
10658 22:55:27.929303 <6>[ 3.309302] spi_master spi0: will run message pump with realtime priority
10659 22:55:27.972057 <6>[ 3.346657] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10660 22:55:27.991423 <6>[ 3.362183] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10661 22:55:27.998642 <6>[ 3.378636] cros-ec-spi spi0.0: Chrome EC device registered
10662 22:55:28.005403 <6>[ 3.384647] mmc0: Command Queue Engine enabled
10663 22:55:28.011440 <6>[ 3.389379] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10664 22:55:28.018231 <6>[ 3.396472] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10665 22:55:28.024548 <6>[ 3.396724] mmcblk0: mmc0:0001 DA4128 116 GiB
10666 22:55:28.031789 <6>[ 3.406871] NET: Registered PF_PACKET protocol family
10667 22:55:28.034484 <6>[ 3.415141] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10668 22:55:28.041412 <6>[ 3.415879] 9pnet: Installing 9P2000 support
10669 22:55:28.044697 <6>[ 3.423099] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10670 22:55:28.051373 <5>[ 3.426256] Key type dns_resolver registered
10671 22:55:28.055049 <6>[ 3.432019] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10672 22:55:28.058101 <6>[ 3.436491] registered taskstats version 1
10673 22:55:28.064996 <6>[ 3.441819] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10674 22:55:28.071372 <5>[ 3.445558] Loading compiled-in X.509 certificates
10675 22:55:28.100660 <4>[ 3.475114] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10676 22:55:28.111023 <4>[ 3.485832] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10677 22:55:28.117419 <3>[ 3.496361] debugfs: File 'uA_load' in directory '/' already present!
10678 22:55:28.124262 <3>[ 3.503077] debugfs: File 'min_uV' in directory '/' already present!
10679 22:55:28.130841 <3>[ 3.509686] debugfs: File 'max_uV' in directory '/' already present!
10680 22:55:28.137479 <3>[ 3.516360] debugfs: File 'constraint_flags' in directory '/' already present!
10681 22:55:28.150053 <6>[ 3.531206] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10682 22:55:28.157489 <6>[ 3.538120] xhci-mtk 11200000.usb: xHCI Host Controller
10683 22:55:28.163663 <6>[ 3.543625] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10684 22:55:28.173741 <6>[ 3.551460] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10685 22:55:28.180295 <6>[ 3.560876] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10686 22:55:28.186880 <6>[ 3.566952] xhci-mtk 11200000.usb: xHCI Host Controller
10687 22:55:28.194213 <6>[ 3.572428] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10688 22:55:28.200615 <6>[ 3.580074] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10689 22:55:28.207361 <6>[ 3.587708] hub 1-0:1.0: USB hub found
10690 22:55:28.210764 <6>[ 3.591721] hub 1-0:1.0: 1 port detected
10691 22:55:28.217203 <6>[ 3.595987] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10692 22:55:28.223988 <6>[ 3.604530] hub 2-0:1.0: USB hub found
10693 22:55:28.227046 <6>[ 3.608537] hub 2-0:1.0: 1 port detected
10694 22:55:28.235612 <6>[ 3.616516] mtk-msdc 11f70000.mmc: Got CD GPIO
10695 22:55:28.247474 <6>[ 3.624790] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10696 22:55:28.253671 <6>[ 3.632815] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10697 22:55:28.263933 <4>[ 3.640874] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10698 22:55:28.273660 <6>[ 3.650552] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10699 22:55:28.280274 <6>[ 3.658654] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10700 22:55:28.286626 <6>[ 3.666674] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10701 22:55:28.297229 <6>[ 3.674606] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10702 22:55:28.303457 <6>[ 3.682424] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10703 22:55:28.313760 <6>[ 3.690254] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10704 22:55:28.323279 <6>[ 3.700721] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10705 22:55:28.330315 <6>[ 3.709094] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10706 22:55:28.340014 <6>[ 3.717436] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10707 22:55:28.346434 <6>[ 3.725786] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10708 22:55:28.356605 <6>[ 3.734124] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10709 22:55:28.366575 <6>[ 3.742474] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10710 22:55:28.373154 <6>[ 3.750812] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10711 22:55:28.383131 <6>[ 3.759160] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10712 22:55:28.389821 <6>[ 3.767500] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10713 22:55:28.399570 <6>[ 3.775849] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10714 22:55:28.406393 <6>[ 3.784187] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10715 22:55:28.416428 <6>[ 3.792525] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10716 22:55:28.422999 <6>[ 3.800864] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10717 22:55:28.432842 <6>[ 3.809203] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10718 22:55:28.439358 <6>[ 3.817540] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10719 22:55:28.446153 <6>[ 3.826313] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10720 22:55:28.452479 <6>[ 3.833196] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10721 22:55:28.459174 <6>[ 3.839955] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10722 22:55:28.465821 <6>[ 3.846719] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10723 22:55:28.476108 <6>[ 3.853651] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10724 22:55:28.482635 <6>[ 3.860510] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10725 22:55:28.492542 <6>[ 3.869639] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10726 22:55:28.502876 <6>[ 3.878758] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10727 22:55:28.512309 <6>[ 3.888085] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10728 22:55:28.522166 <6>[ 3.897557] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10729 22:55:28.529426 <6>[ 3.907028] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10730 22:55:28.538773 <6>[ 3.916147] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10731 22:55:28.548825 <6>[ 3.925613] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10732 22:55:28.558926 <6>[ 3.934732] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10733 22:55:28.569362 <6>[ 3.944027] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10734 22:55:28.579284 <6>[ 3.954187] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10735 22:55:28.588852 <6>[ 3.966131] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10736 22:55:28.617276 <6>[ 3.995350] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10737 22:55:28.645929 <6>[ 4.026686] hub 2-1:1.0: USB hub found
10738 22:55:28.649202 <6>[ 4.031163] hub 2-1:1.0: 3 ports detected
10739 22:55:28.657725 <6>[ 4.038573] hub 2-1:1.0: USB hub found
10740 22:55:28.660905 <6>[ 4.043014] hub 2-1:1.0: 3 ports detected
10741 22:55:28.769073 <6>[ 4.147209] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10742 22:55:28.924160 <6>[ 4.305306] hub 1-1:1.0: USB hub found
10743 22:55:28.927619 <6>[ 4.309805] hub 1-1:1.0: 4 ports detected
10744 22:55:28.936872 <6>[ 4.318037] hub 1-1:1.0: USB hub found
10745 22:55:28.940120 <6>[ 4.322498] hub 1-1:1.0: 4 ports detected
10746 22:55:29.009469 <6>[ 4.387468] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10747 22:55:29.118283 <6>[ 4.495898] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10748 22:55:29.174729 <6>[ 4.552321] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10749 22:55:29.214926 <6>[ 4.596208] r8152 2-1.3:1.0 eth0: v1.12.13
10750 22:55:29.261053 <6>[ 4.639245] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10751 22:55:29.394214 <6>[ 4.775071] hub 1-1.4:1.0: USB hub found
10752 22:55:29.397479 <6>[ 4.779739] hub 1-1.4:1.0: 2 ports detected
10753 22:55:29.407433 <6>[ 4.788331] hub 1-1.4:1.0: USB hub found
10754 22:55:29.410534 <6>[ 4.792932] hub 1-1.4:1.0: 2 ports detected
10755 22:55:29.709441 <6>[ 5.087296] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10756 22:55:29.901660 <6>[ 5.279267] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10757 22:55:30.850834 <6>[ 6.231747] r8152 2-1.3:1.0 eth0: carrier on
10758 22:55:33.470309 <5>[ 6.258986] Sending DHCP requests .., OK
10759 22:55:33.476442 <6>[ 8.855369] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10760 22:55:33.479382 <6>[ 8.863667] IP-Config: Complete:
10761 22:55:33.492684 <6>[ 8.867166] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10762 22:55:33.499468 <6>[ 8.877885] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10763 22:55:33.505984 <6>[ 8.886503] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10764 22:55:33.512368 <6>[ 8.886512] nameserver0=192.168.201.1
10765 22:55:33.515606 <6>[ 8.898660] clk: Disabling unused clocks
10766 22:55:33.519392 <6>[ 8.904079] ALSA device list:
10767 22:55:33.525917 <6>[ 8.907370] No soundcards found.
10768 22:55:33.533114 <6>[ 8.914636] Freeing unused kernel memory: 8512K
10769 22:55:33.536479 <6>[ 8.919599] Run /init as init process
10770 22:55:33.565412 <6>[ 8.947096] NET: Registered PF_INET6 protocol family
10771 22:55:33.572125 <6>[ 8.953610] Segment Routing with IPv6
10772 22:55:33.575715 <6>[ 8.957555] In-situ OAM (IOAM) with IPv6
10773 22:55:33.615433 <30>[ 8.970301] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10774 22:55:33.621947 <30>[ 9.003356] systemd[1]: Detected architecture arm64.
10775 22:55:33.622153
10776 22:55:33.628602 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10777 22:55:33.628748
10778 22:55:33.628826
10779 22:55:33.641606 <30>[ 9.023228] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10780 22:55:33.748421 <30>[ 9.126226] systemd[1]: Queued start job for default target graphical.target.
10781 22:55:33.778787 <30>[ 9.156683] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10782 22:55:33.785552 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10783 22:55:33.786114
10784 22:55:33.806022 <30>[ 9.183684] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10785 22:55:33.815834 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10786 22:55:33.816592
10787 22:55:33.833831 <30>[ 9.211824] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10788 22:55:33.843809 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10789 22:55:33.844324
10790 22:55:33.863263 <30>[ 9.240583] systemd[1]: Created slice user.slice - User and Session Slice.
10791 22:55:33.869611 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10792 22:55:33.870174
10793 22:55:33.894005 <30>[ 9.267862] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10794 22:55:33.900058 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10795 22:55:33.900631
10796 22:55:33.921423 <30>[ 9.295237] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10797 22:55:33.928151 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10798 22:55:33.928711
10799 22:55:33.956078 <30>[ 9.323672] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10800 22:55:33.966436 <30>[ 9.343543] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10801 22:55:33.972164 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10802 22:55:33.972707
10803 22:55:33.990030 <30>[ 9.367541] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10804 22:55:33.996675 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10805 22:55:34.000040
10806 22:55:34.013558 <30>[ 9.391339] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10807 22:55:34.023495 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10808 22:55:34.024116
10809 22:55:34.038489 <30>[ 9.419759] systemd[1]: Reached target paths.target - Path Units.
10810 22:55:34.045783 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10811 22:55:34.048768
10812 22:55:34.066185 <30>[ 9.443683] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10813 22:55:34.072686 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10814 22:55:34.073152
10815 22:55:34.085733 <30>[ 9.467229] systemd[1]: Reached target slices.target - Slice Units.
10816 22:55:34.096531 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10817 22:55:34.096980
10818 22:55:34.110601 <30>[ 9.491737] systemd[1]: Reached target swap.target - Swaps.
10819 22:55:34.117132 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10820 22:55:34.117556
10821 22:55:34.137993 <30>[ 9.515753] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10822 22:55:34.148378 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10823 22:55:34.148946
10824 22:55:34.166569 <30>[ 9.544220] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10825 22:55:34.176420 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10826 22:55:34.176971
10827 22:55:34.195631 <30>[ 9.573294] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10828 22:55:34.205856 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10829 22:55:34.206410
10830 22:55:34.221972 <30>[ 9.599882] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10831 22:55:34.231898 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10832 22:55:34.232506
10833 22:55:34.250523 <30>[ 9.627817] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10834 22:55:34.256967 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10835 22:55:34.257527
10836 22:55:34.274233 <30>[ 9.651911] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10837 22:55:34.284198 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10838 22:55:34.284751
10839 22:55:34.303265 <30>[ 9.680704] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10840 22:55:34.312617 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10841 22:55:34.313166
10842 22:55:34.329961 <30>[ 9.707687] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10843 22:55:34.339519 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10844 22:55:34.340024
10845 22:55:34.393457 <30>[ 9.771484] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10846 22:55:34.400185 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10847 22:55:34.400746
10848 22:55:34.413570 <30>[ 9.791074] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10849 22:55:34.420394 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10850 22:55:34.420945
10851 22:55:34.442005 <30>[ 9.819717] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10852 22:55:34.448494 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10853 22:55:34.448960
10854 22:55:34.476420 <30>[ 9.847720] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10855 22:55:34.529861 <30>[ 9.907632] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10856 22:55:34.540060 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10857 22:55:34.540679
10858 22:55:34.562550 <30>[ 9.940568] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10859 22:55:34.568874 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10860 22:55:34.569295
10861 22:55:34.594339 <30>[ 9.972394] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10862 22:55:34.607031 Starting [0;1;39mmodpr<6>[ 9.983516] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10863 22:55:34.610582 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10864 22:55:34.610671
10865 22:55:34.665879 <30>[ 10.043729] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10866 22:55:34.672267 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10867 22:55:34.672519
10868 22:55:34.693905 <30>[ 10.071922] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10869 22:55:34.700750 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10870 22:55:34.701302
10871 22:55:34.758031 <30>[ 10.135790] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10872 22:55:34.764646 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10873 22:55:34.765163
10874 22:55:34.794486 <30>[ 10.172182] systemd[1]: Starting systemd-journald.service - Journal Service...
10875 22:55:34.800961 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10876 22:55:34.801426
10877 22:55:34.820105 <30>[ 10.197771] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10878 22:55:34.826431 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10879 22:55:34.826952
10880 22:55:34.852075 <30>[ 10.226351] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10881 22:55:34.858526 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10882 22:55:34.859051
10883 22:55:34.901940 <30>[ 10.279804] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10884 22:55:34.912005 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10885 22:55:34.912568
10886 22:55:34.934089 <30>[ 10.312202] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10887 22:55:34.940902 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10888 22:55:34.941352
10889 22:55:34.968996 <30>[ 10.347419] systemd[1]: Started systemd-journald.service - Journal Service.
10890 22:55:34.975934 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10891 22:55:34.976266
10892 22:55:34.997228 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10893 22:55:34.997724
10894 22:55:35.014736 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10895 22:55:35.015308
10896 22:55:35.034498 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10897 22:55:35.035000
10898 22:55:35.055046 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10899 22:55:35.055679
10900 22:55:35.076120 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10901 22:55:35.076537
10902 22:55:35.096429 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10903 22:55:35.096658
10904 22:55:35.120341 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10905 22:55:35.120615
10906 22:55:35.144455 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10907 22:55:35.144722
10908 22:55:35.164811 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10909 22:55:35.165050
10910 22:55:35.182478 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10911 22:55:35.182789
10912 22:55:35.206174 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10913 22:55:35.206436
10914 22:55:35.227768 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10915 22:55:35.228067
10916 22:55:35.241493 See 'systemctl status systemd-remount-fs.service' for details.
10917 22:55:35.241735
10918 22:55:35.262637 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10919 22:55:35.262877
10920 22:55:35.287795 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10921 22:55:35.288059
10922 22:55:35.341388 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10923 22:55:35.341715
10924 22:55:35.362026 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10925 22:55:35.362260
10926 22:55:35.383665 <46>[ 10.761880] systemd-journald[190]: Received client request to flush runtime journal.
10927 22:55:35.390514 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10928 22:55:35.390600
10929 22:55:35.457700 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10930 22:55:35.458203
10931 22:55:35.484803 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10932 22:55:35.485380
10933 22:55:35.510592 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10934 22:55:35.511068
10935 22:55:35.530572 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10936 22:55:35.530801
10937 22:55:35.550286 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10938 22:55:35.550378
10939 22:55:35.570142 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10940 22:55:35.570230
10941 22:55:35.589900 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10942 22:55:35.589995
10943 22:55:35.633168 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10944 22:55:35.633264
10945 22:55:35.657911 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10946 22:55:35.658002
10947 22:55:35.677296 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10948 22:55:35.677395
10949 22:55:35.696924 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10950 22:55:35.697007
10951 22:55:35.733961 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10952 22:55:35.734092
10953 22:55:35.749047 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10954 22:55:35.749131
10955 22:55:35.775642 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10956 22:55:35.775729
10957 22:55:35.808528 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10958 22:55:35.808617
10959 22:55:35.833169 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10960 22:55:35.833655
10961 22:55:35.853545 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10962 22:55:35.853729
10963 22:55:35.888040 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10964 22:55:35.888245
10965 22:55:35.922958 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10966 22:55:35.923123
10967 22:55:35.933035 <46>[ 11.314784] systemd-journald[190]: Time jumped backwards, rotating.
10968 22:55:35.953256 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10969 22:55:35.953410
10970 22:55:36.060709 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10971 22:55:36.060962
10972 22:55:36.077513 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10973 22:55:36.077721
10974 22:55:36.097574 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10975 22:55:36.097850
10976 22:55:36.119380 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10977 22:55:36.119693
10978 22:55:36.137622 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10979 22:55:36.137918
10980 22:55:36.155248 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10981 22:55:36.155804
10982 22:55:36.167104 <6>[ 11.545235] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10983 22:55:36.174011 <3>[ 11.550250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10984 22:55:36.183928 <6>[ 11.552986] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10985 22:55:36.190457 <3>[ 11.561278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10986 22:55:36.200048 <6>[ 11.569662] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10987 22:55:36.206598 <3>[ 11.577866] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10988 22:55:36.216834 [[0;32m OK [0m] Reached targ<6>[ 11.597429] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10989 22:55:36.223266 et [0;1;39msockets.target[0m - Socket Units.
10990 22:55:36.223789
10991 22:55:36.233840 <3>[ 11.612400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10992 22:55:36.244588 <3>[ 11.621408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10993 22:55:36.250641 <3>[ 11.629568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10994 22:55:36.257266 <6>[ 11.632043] remoteproc remoteproc0: scp is available
10995 22:55:36.263753 <3>[ 11.637964] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10996 22:55:36.270585 <6>[ 11.643232] remoteproc remoteproc0: powering up scp
10997 22:55:36.277495 <3>[ 11.651178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10998 22:55:36.287224 <3>[ 11.653449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10999 22:55:36.293634 <6>[ 11.656512] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11000 22:55:36.300356 <6>[ 11.658366] mc: Linux media interface: v0.10
11001 22:55:36.306921 <4>[ 11.666251] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11002 22:55:36.313988 <3>[ 11.671480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11003 22:55:36.324227 <3>[ 11.671494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11004 22:55:36.330343 <3>[ 11.671500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11005 22:55:36.340242 <3>[ 11.671635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11006 22:55:36.346760 <3>[ 11.671639] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11007 22:55:36.354064 <3>[ 11.671641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11008 22:55:36.363664 <3>[ 11.671655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11009 22:55:36.370877 <3>[ 11.671659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11010 22:55:36.380229 <3>[ 11.671687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11011 22:55:36.384113 <6>[ 11.672691] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11012 22:55:36.391320 <4>[ 11.683595] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11013 22:55:36.401411 <6>[ 11.697936] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11014 22:55:36.407942 <6>[ 11.717245] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11015 22:55:36.411206 <6>[ 11.725965] videodev: Linux video capture interface: v2.00
11016 22:55:36.418107 <6>[ 11.733763] pci_bus 0000:00: root bus resource [bus 00-ff]
11017 22:55:36.425957 <4>[ 11.745553] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11018 22:55:36.432748 <4>[ 11.745553] Fallback method does not support PEC.
11019 22:55:36.439187 <6>[ 11.749739] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11020 22:55:36.449109 <6>[ 11.771814] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11021 22:55:36.458890 <3>[ 11.774871] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 22:55:36.469154 <6>[ 11.778845] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11023 22:55:36.475655 <6>[ 11.787386] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11024 22:55:36.482406 <6>[ 11.793381] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11025 22:55:36.488926 <6>[ 11.811203] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11026 22:55:36.498725 <3>[ 11.811204] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11027 22:55:36.509318 <6>[ 11.811236] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11028 22:55:36.515736 <6>[ 11.811244] remoteproc remoteproc0: remote processor scp is now up
11029 22:55:36.522521 <6>[ 11.818469] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11030 22:55:36.528618 <3>[ 11.825968] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11031 22:55:36.538435 <6>[ 11.830287] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11032 22:55:36.541896 <6>[ 11.835754] pci 0000:00:00.0: supports D1 D2
11033 22:55:36.551782 <6>[ 11.856624] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11034 22:55:36.558633 <6>[ 11.863420] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11035 22:55:36.565401 <6>[ 11.864650] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11036 22:55:36.571933 <6>[ 11.864685] Bluetooth: Core ver 2.22
11037 22:55:36.575815 <6>[ 11.864761] NET: Registered PF_BLUETOOTH protocol family
11038 22:55:36.582947 <6>[ 11.864763] Bluetooth: HCI device and connection manager initialized
11039 22:55:36.586887 <6>[ 11.864780] Bluetooth: HCI socket layer initialized
11040 22:55:36.593268 <6>[ 11.864784] Bluetooth: L2CAP socket layer initialized
11041 22:55:36.596276 <6>[ 11.864803] Bluetooth: SCO socket layer initialized
11042 22:55:36.606818 <6>[ 11.894168] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11043 22:55:36.613507 <6>[ 11.900663] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11044 22:55:36.619889 <6>[ 11.902259] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11045 22:55:36.630118 <6>[ 11.903388] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11046 22:55:36.637052 <6>[ 11.903484] usbcore: registered new interface driver uvcvideo
11047 22:55:36.644639 <6>[ 11.930163] usbcore: registered new interface driver btusb
11048 22:55:36.653974 <4>[ 11.930579] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11049 22:55:36.660816 <3>[ 11.930590] Bluetooth: hci0: Failed to load firmware file (-2)
11050 22:55:36.667213 <3>[ 11.930594] Bluetooth: hci0: Failed to set up firmware (-2)
11051 22:55:36.677421 <4>[ 11.930597] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11052 22:55:36.684044 <6>[ 11.937704] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11053 22:55:36.690751 <6>[ 11.938233] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11054 22:55:36.700668 <3>[ 11.971400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11055 22:55:36.707112 <3>[ 11.972190] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11056 22:55:36.716940 <3>[ 11.972908] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11057 22:55:36.723290 <6>[ 11.973925] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11058 22:55:36.734076 <3>[ 11.995743] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11059 22:55:36.740668 <6>[ 11.998861] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11060 22:55:36.747397 <5>[ 12.021661] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11061 22:55:36.754546 <6>[ 12.024405] pci 0000:01:00.0: supports D1 D2
11062 22:55:36.760482 <3>[ 12.030112] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11063 22:55:36.768223 <6>[ 12.040543] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11064 22:55:36.774921 <5>[ 12.043048] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11065 22:55:36.781154 <6>[ 12.051161] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11066 22:55:36.792259 <5>[ 12.052818] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11067 22:55:36.799110 <6>[ 12.062938] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11068 22:55:36.809276 <4>[ 12.070440] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11069 22:55:36.816089 <6>[ 12.076888] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11070 22:55:36.822848 <6>[ 12.076902] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11071 22:55:36.829303 <6>[ 12.085694] cfg80211: failed to load regulatory.db
11072 22:55:36.836907 <6>[ 12.094448] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11073 22:55:36.847202 <3>[ 12.122696] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11074 22:55:36.854275 <6>[ 12.126930] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11075 22:55:36.860869 <3>[ 12.154587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11076 22:55:36.867619 <6>[ 12.155073] pci 0000:00:00.0: PCI bridge to [bus 01]
11077 22:55:36.874725 <6>[ 12.253713] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11078 22:55:36.881052 <6>[ 12.253880] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11079 22:55:36.890558 Startin<6>[ 12.268700] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11080 22:55:36.897202 g [0;1;39msyste<6>[ 12.276520] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11081 22:55:36.900657 md-networkd.…ice[0m - Network Configuration...
11082 22:55:36.901076
11083 22:55:36.922167 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11084 22:55:36.922721
11085 22:55:36.947515 <6>[ 12.325296] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11086 22:55:36.953818 <6>[ 12.332815] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11087 22:55:36.978044 Starting [0;1;39mdbus.service[0m - D-<6>[ 12.359523] mt7921e 0000:01:00.0: ASIC revision: 79610010
11088 22:55:36.981193 Bus System Message Bus...
11089 22:55:36.981662
11090 22:55:37.012754 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11091 22:55:37.013318
11092 22:55:37.030262 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11093 22:55:37.030821
11094 22:55:37.050197 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11095 22:55:37.050747
11096 22:55:37.083905 <6>[ 12.462127] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11097 22:55:37.086987 <6>[ 12.462127]
11098 22:55:37.103591 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11099 22:55:37.104176
11100 22:55:37.121561 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11101 22:55:37.122109
11102 22:55:37.133865 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11103 22:55:37.134328
11104 22:55:37.153114 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11105 22:55:37.153539
11106 22:55:37.206438 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11107 22:55:37.206901
11108 22:55:37.230917 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11109 22:55:37.231399
11110 22:55:37.252121 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11111 22:55:37.252568
11112 22:55:37.271021 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11113 22:55:37.271651
11114 22:55:37.292205 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11115 22:55:37.292631
11116 22:55:37.353423 <6>[ 12.731946] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11117 22:55:37.360038 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11118 22:55:37.360459
11119 22:55:37.383695 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11120 22:55:37.384163
11121 22:55:37.402641 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11122 22:55:37.403135
11123 22:55:37.418123 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11124 22:55:37.418432
11125 22:55:37.437406 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11126 22:55:37.437718
11127 22:55:37.490556 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11128 22:55:37.490998
11129 22:55:37.515884 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11130 22:55:37.516369
11131 22:55:37.536969 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11132 22:55:37.537409
11133 22:55:37.575028 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11134 22:55:37.575480
11135 22:55:37.642033
11136 22:55:37.642556
11137 22:55:37.645315 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11138 22:55:37.645791
11139 22:55:37.648224 debian-bookworm-arm64 login: root (automatic login)
11140 22:55:37.648657
11141 22:55:37.649095
11142 22:55:37.661251 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
11143 22:55:37.661700
11144 22:55:37.668199 The programs included with the Debian GNU/Linux system are free software;
11145 22:55:37.674550 the exact distribution terms for each program are described in the
11146 22:55:37.677833 individual files in /usr/share/doc/*/copyright.
11147 22:55:37.678299
11148 22:55:37.684651 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11149 22:55:37.687747 permitted by applicable law.
11150 22:55:37.689127 Matched prompt #10: / #
11152 22:55:37.690400 Setting prompt string to ['/ #']
11153 22:55:37.690943 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11155 22:55:37.692121 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11156 22:55:37.692664 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
11157 22:55:37.693076 Setting prompt string to ['/ #']
11158 22:55:37.693466 Forcing a shell prompt, looking for ['/ #']
11160 22:55:37.744451 / #
11161 22:55:37.745079 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11162 22:55:37.745532 Waiting using forced prompt support (timeout 00:02:30)
11163 22:55:37.750348
11164 22:55:37.751119 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11165 22:55:37.751663 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
11166 22:55:37.752241 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11167 22:55:37.752757 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
11168 22:55:37.753247 end: 2 depthcharge-action (duration 00:01:34) [common]
11169 22:55:37.753790 start: 3 lava-test-retry (timeout 00:05:00) [common]
11170 22:55:37.754319 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11171 22:55:37.754747 Using namespace: common
11173 22:55:37.855827 / # #
11174 22:55:37.856270 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11175 22:55:37.861822 #
11176 22:55:37.862378 Using /lava-13683680
11178 22:55:37.963232 / # export SHELL=/bin/sh
11179 22:55:37.969088 export SHELL=/bin/sh
11181 22:55:38.070178 / # . /lava-13683680/environment
11182 22:55:38.076105 . /lava-13683680/environment
11184 22:55:38.177197 / # /lava-13683680/bin/lava-test-runner /lava-13683680/0
11185 22:55:38.177752 Test shell timeout: 10s (minimum of the action and connection timeout)
11186 22:55:38.182751 /lava-13683680/bin/lava-test-runner /lava-13683680/0
11187 22:55:38.206681 + export TESTRUN_ID=0_cros-ec
11188 22:55:38.212877 +<8>[ 13.593425] <LAVA_SIGNAL_STARTRUN 0_cros-ec 13683680_1.5.2.3.1>
11189 22:55:38.213886 Received signal: <STARTRUN> 0_cros-ec 13683680_1.5.2.3.1
11190 22:55:38.214380 Starting test lava.0_cros-ec (13683680_1.5.2.3.1)
11191 22:55:38.214810 Skipping test definition patterns.
11192 22:55:38.216233 cd /lava-13683680/0/tests/0_cros-ec
11193 22:55:38.219460 + cat uuid
11194 22:55:38.219912 + UUID=13683680_1.5.2.3.1
11195 22:55:38.220392 + set +x
11196 22:55:38.226603 + python3<6>[ 13.607591] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11197 22:55:38.229395 -m cros.runners.lava_runner -v
11198 22:55:38.690562 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11199 22:55:38.696863 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11200 22:55:38.697217
11201 22:55:38.703549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11202 22:55:38.704173 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11204 22:55:38.713585 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11205 22:55:38.724026 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11206 22:55:38.724384
11207 22:55:38.730455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11208 22:55:38.731053 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11210 22:55:38.740351 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11211 22:55:38.746844 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11212 22:55:38.747197
11213 22:55:38.753227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11214 22:55:38.753818 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11216 22:55:38.759820 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11217 22:55:38.763103 Checks the standard ABI for the main Embedded Controller. ... ok
11218 22:55:38.766606
11219 22:55:38.769856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11220 22:55:38.770558 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11222 22:55:38.776532 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11223 22:55:38.783259 Checks the main Embedded controller character device. ... ok
11224 22:55:38.783610
11225 22:55:38.789686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11226 22:55:38.790278 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11228 22:55:38.796652 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11229 22:55:38.803337 Checks basic comunication with the main Embedded controller. ... ok
11230 22:55:38.803720
11231 22:55:38.809853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11232 22:55:38.810601 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11234 22:55:38.816689 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11235 22:55:38.822880 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11236 22:55:38.823233
11237 22:55:38.829799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11238 22:55:38.830393 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11240 22:55:38.836537 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11241 22:55:38.842874 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11242 22:55:38.843287
11243 22:55:38.849614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11244 22:55:38.850202 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11246 22:55:38.856527 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11247 22:55:38.862884 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11248 22:55:38.863242
11249 22:55:38.869481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11250 22:55:38.870079 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11252 22:55:38.876165 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11253 22:55:38.882930 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11254 22:55:38.883285
11255 22:55:38.889586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11256 22:55:38.890169 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11258 22:55:38.895808 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11259 22:55:38.906080 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11260 22:55:38.906527
11261 22:55:38.912726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11262 22:55:38.913330 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11264 22:55:38.918869 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11265 22:55:38.925958 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11266 22:55:38.926332
11267 22:55:38.932046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11268 22:55:38.932659 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11270 22:55:38.938754 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11271 22:55:38.946053 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11272 22:55:38.946434
11273 22:55:38.952026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11274 22:55:38.952620 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11276 22:55:38.959232 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11277 22:55:38.968578 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11278 22:55:38.968940
11279 22:55:38.975505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11280 22:55:38.976102 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11282 22:55:38.985654 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11283 22:55:38.988943 Check the cros battery ABI. ... skipped 'No BAT found'
11284 22:55:38.989427
11285 22:55:38.995162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11286 22:55:38.995926 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11288 22:55:39.005503 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11289 22:55:39.012080 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11290 22:55:39.012440
11291 22:55:39.018404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11292 22:55:39.018997 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11294 22:55:39.025315 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11295 22:55:39.031935 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11296 22:55:39.032325
11297 22:55:39.038223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11298 22:55:39.038831 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11300 22:55:39.048513 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11301 22:55:39.055246 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11302 22:55:39.055645
11303 22:55:39.062032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11304 22:55:39.062421
11305 22:55:39.062943 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11307 22:55:39.068272 --------------------------<8>[ 14.449162] <LAVA_SIGNAL_ENDRUN 0_cros-ec 13683680_1.5.2.3.1>
11308 22:55:39.068852 Received signal: <ENDRUN> 0_cros-ec 13683680_1.5.2.3.1
11309 22:55:39.069182 Ending use of test pattern.
11310 22:55:39.069476 Ending test lava.0_cros-ec (13683680_1.5.2.3.1), duration 0.86
11312 22:55:39.071875 --------------------------------------------
11313 22:55:39.075184 Ran 18 tests in 0.338s
11314 22:55:39.075650
11315 22:55:39.078585 OK (skipped=15)
11316 22:55:39.079074 + set +x
11317 22:55:39.079555 <LAVA_TEST_RUNNER EXIT>
11318 22:55:39.080249 ok: lava_test_shell seems to have completed
11319 22:55:39.081377 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11320 22:55:39.081860 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11321 22:55:39.082398 end: 3 lava-test-retry (duration 00:00:01) [common]
11322 22:55:39.083024 start: 4 finalize (timeout 00:07:57) [common]
11323 22:55:39.083618 start: 4.1 power-off (timeout 00:00:30) [common]
11324 22:55:39.084672 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11325 22:55:39.200312 >> Command sent successfully.
11326 22:55:39.203114 Returned 0 in 0 seconds
11327 22:55:39.303549 end: 4.1 power-off (duration 00:00:00) [common]
11329 22:55:39.303936 start: 4.2 read-feedback (timeout 00:07:57) [common]
11330 22:55:39.304221 Listened to connection for namespace 'common' for up to 1s
11331 22:55:39.304502 Listened to connection for namespace 'common' for up to 1s
11332 22:55:40.305125 Finalising connection for namespace 'common'
11333 22:55:40.305287 Disconnecting from shell: Finalise
11334 22:55:40.305370 / #
11335 22:55:40.405739 end: 4.2 read-feedback (duration 00:00:01) [common]
11336 22:55:40.405907 end: 4 finalize (duration 00:00:01) [common]
11337 22:55:40.406026 Cleaning after the job
11338 22:55:40.406124 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/ramdisk
11339 22:55:40.411805 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/kernel
11340 22:55:40.419310 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/dtb
11341 22:55:40.419481 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683680/tftp-deploy-ae11a8wq/modules
11342 22:55:40.425059 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683680
11343 22:55:40.515500 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683680
11344 22:55:40.515688 Job finished correctly