Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
1 22:48:28.001918 lava-dispatcher, installed at version: 2024.01
2 22:48:28.002137 start: 0 validate
3 22:48:28.002265 Start time: 2024-05-07 22:48:28.002258+00:00 (UTC)
4 22:48:28.002396 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:48:28.002525 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 22:48:28.262799 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:48:28.262972 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:48:28.521457 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:48:28.521880 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:49:19.983866 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:49:19.984689 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:49:20.495950 validate duration: 52.49
14 22:49:20.497434 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:49:20.497943 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:49:20.498396 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:49:20.499111 Not decompressing ramdisk as can be used compressed.
18 22:49:20.499602 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 22:49:20.499939 saving as /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/ramdisk/rootfs.cpio.gz
20 22:49:20.500267 total size: 47897469 (45 MB)
21 22:49:29.160891 progress 0 % (0 MB)
22 22:49:29.176712 progress 5 % (2 MB)
23 22:49:29.188565 progress 10 % (4 MB)
24 22:49:29.200399 progress 15 % (6 MB)
25 22:49:29.212195 progress 20 % (9 MB)
26 22:49:29.224217 progress 25 % (11 MB)
27 22:49:29.236446 progress 30 % (13 MB)
28 22:49:29.248495 progress 35 % (16 MB)
29 22:49:29.260581 progress 40 % (18 MB)
30 22:49:29.272756 progress 45 % (20 MB)
31 22:49:29.284775 progress 50 % (22 MB)
32 22:49:29.296833 progress 55 % (25 MB)
33 22:49:29.308923 progress 60 % (27 MB)
34 22:49:29.320941 progress 65 % (29 MB)
35 22:49:29.333052 progress 70 % (32 MB)
36 22:49:29.345076 progress 75 % (34 MB)
37 22:49:29.357275 progress 80 % (36 MB)
38 22:49:29.369478 progress 85 % (38 MB)
39 22:49:29.381508 progress 90 % (41 MB)
40 22:49:29.393378 progress 95 % (43 MB)
41 22:49:29.405057 progress 100 % (45 MB)
42 22:49:29.405267 45 MB downloaded in 8.91 s (5.13 MB/s)
43 22:49:29.405441 end: 1.1.1 http-download (duration 00:00:09) [common]
45 22:49:29.405679 end: 1.1 download-retry (duration 00:00:09) [common]
46 22:49:29.405771 start: 1.2 download-retry (timeout 00:09:51) [common]
47 22:49:29.405855 start: 1.2.1 http-download (timeout 00:09:51) [common]
48 22:49:29.405986 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:49:29.406055 saving as /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/kernel/Image
50 22:49:29.406115 total size: 54682112 (52 MB)
51 22:49:29.406175 No compression specified
52 22:49:29.407276 progress 0 % (0 MB)
53 22:49:29.420793 progress 5 % (2 MB)
54 22:49:29.434416 progress 10 % (5 MB)
55 22:49:29.448184 progress 15 % (7 MB)
56 22:49:29.461880 progress 20 % (10 MB)
57 22:49:29.475816 progress 25 % (13 MB)
58 22:49:29.489791 progress 30 % (15 MB)
59 22:49:29.503475 progress 35 % (18 MB)
60 22:49:29.517136 progress 40 % (20 MB)
61 22:49:29.530674 progress 45 % (23 MB)
62 22:49:29.544558 progress 50 % (26 MB)
63 22:49:29.558420 progress 55 % (28 MB)
64 22:49:29.572165 progress 60 % (31 MB)
65 22:49:29.586118 progress 65 % (33 MB)
66 22:49:29.600212 progress 70 % (36 MB)
67 22:49:29.614100 progress 75 % (39 MB)
68 22:49:29.628427 progress 80 % (41 MB)
69 22:49:29.642845 progress 85 % (44 MB)
70 22:49:29.657571 progress 90 % (46 MB)
71 22:49:29.671674 progress 95 % (49 MB)
72 22:49:29.685289 progress 100 % (52 MB)
73 22:49:29.685587 52 MB downloaded in 0.28 s (186.60 MB/s)
74 22:49:29.685750 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:49:29.685978 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:49:29.686069 start: 1.3 download-retry (timeout 00:09:51) [common]
78 22:49:29.686157 start: 1.3.1 http-download (timeout 00:09:51) [common]
79 22:49:29.686296 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:49:29.686366 saving as /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/dtb/mt8192-asurada-spherion-r0.dtb
81 22:49:29.686427 total size: 47258 (0 MB)
82 22:49:29.686488 No compression specified
83 22:49:29.687603 progress 69 % (0 MB)
84 22:49:29.687875 progress 100 % (0 MB)
85 22:49:29.688029 0 MB downloaded in 0.00 s (28.17 MB/s)
86 22:49:29.688151 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:49:29.688371 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:49:29.688455 start: 1.4 download-retry (timeout 00:09:51) [common]
90 22:49:29.688537 start: 1.4.1 http-download (timeout 00:09:51) [common]
91 22:49:29.688648 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:49:29.688715 saving as /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/modules/modules.tar
93 22:49:29.688774 total size: 8594396 (8 MB)
94 22:49:29.688834 Using unxz to decompress xz
95 22:49:29.692897 progress 0 % (0 MB)
96 22:49:29.712172 progress 5 % (0 MB)
97 22:49:29.737669 progress 10 % (0 MB)
98 22:49:29.762301 progress 15 % (1 MB)
99 22:49:29.785931 progress 20 % (1 MB)
100 22:49:29.811398 progress 25 % (2 MB)
101 22:49:29.836053 progress 30 % (2 MB)
102 22:49:29.861212 progress 35 % (2 MB)
103 22:49:29.887341 progress 40 % (3 MB)
104 22:49:29.913376 progress 45 % (3 MB)
105 22:49:29.939551 progress 50 % (4 MB)
106 22:49:29.966243 progress 55 % (4 MB)
107 22:49:29.992446 progress 60 % (4 MB)
108 22:49:30.018718 progress 65 % (5 MB)
109 22:49:30.044682 progress 70 % (5 MB)
110 22:49:30.069570 progress 75 % (6 MB)
111 22:49:30.095505 progress 80 % (6 MB)
112 22:49:30.121779 progress 85 % (6 MB)
113 22:49:30.150961 progress 90 % (7 MB)
114 22:49:30.180755 progress 95 % (7 MB)
115 22:49:30.207252 progress 100 % (8 MB)
116 22:49:30.212478 8 MB downloaded in 0.52 s (15.65 MB/s)
117 22:49:30.212757 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:49:30.213030 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:49:30.213128 start: 1.5 prepare-tftp-overlay (timeout 00:09:50) [common]
121 22:49:30.213225 start: 1.5.1 extract-nfsrootfs (timeout 00:09:50) [common]
122 22:49:30.213307 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:49:30.213414 start: 1.5.2 lava-overlay (timeout 00:09:50) [common]
124 22:49:30.213640 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat
125 22:49:30.213779 makedir: /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin
126 22:49:30.213885 makedir: /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/tests
127 22:49:30.213985 makedir: /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/results
128 22:49:30.214102 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-add-keys
129 22:49:30.214252 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-add-sources
130 22:49:30.214386 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-background-process-start
131 22:49:30.214518 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-background-process-stop
132 22:49:30.214646 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-common-functions
133 22:49:30.214773 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-echo-ipv4
134 22:49:30.214902 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-install-packages
135 22:49:30.215029 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-installed-packages
136 22:49:30.215154 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-os-build
137 22:49:30.215282 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-probe-channel
138 22:49:30.215409 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-probe-ip
139 22:49:30.215537 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-target-ip
140 22:49:30.215663 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-target-mac
141 22:49:30.215788 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-target-storage
142 22:49:30.215919 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-test-case
143 22:49:30.216057 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-test-event
144 22:49:30.216232 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-test-feedback
145 22:49:30.216365 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-test-raise
146 22:49:30.216497 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-test-reference
147 22:49:30.216625 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-test-runner
148 22:49:30.216753 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-test-set
149 22:49:30.216882 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-test-shell
150 22:49:30.217014 Updating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-install-packages (oe)
151 22:49:30.217167 Updating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/bin/lava-installed-packages (oe)
152 22:49:30.217293 Creating /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/environment
153 22:49:30.217413 LAVA metadata
154 22:49:30.217491 - LAVA_JOB_ID=13683676
155 22:49:30.217557 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:49:30.217665 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:50) [common]
157 22:49:30.217735 skipped lava-vland-overlay
158 22:49:30.217812 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:49:30.217899 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
160 22:49:30.217962 skipped lava-multinode-overlay
161 22:49:30.218039 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:49:30.218123 start: 1.5.2.3 test-definition (timeout 00:09:50) [common]
163 22:49:30.218200 Loading test definitions
164 22:49:30.218295 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:50) [common]
165 22:49:30.218382 Using /lava-13683676 at stage 0
166 22:49:30.218717 uuid=13683676_1.5.2.3.1 testdef=None
167 22:49:30.218809 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:49:30.218899 start: 1.5.2.3.2 test-overlay (timeout 00:09:50) [common]
169 22:49:30.219465 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:49:30.219694 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:50) [common]
172 22:49:30.220344 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:49:30.220580 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
175 22:49:30.221190 runner path: /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/0/tests/0_igt-gpu-panfrost test_uuid 13683676_1.5.2.3.1
176 22:49:30.221365 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:49:30.221575 Creating lava-test-runner.conf files
179 22:49:30.221642 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683676/lava-overlay-hz2xjlat/lava-13683676/0 for stage 0
180 22:49:30.221733 - 0_igt-gpu-panfrost
181 22:49:30.221831 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:49:30.221921 start: 1.5.2.4 compress-overlay (timeout 00:09:50) [common]
183 22:49:30.229467 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:49:30.229615 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
185 22:49:30.229707 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:49:30.229802 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:49:30.229891 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
188 22:49:32.016403 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 22:49:32.016804 start: 1.5.4 extract-modules (timeout 00:09:48) [common]
190 22:49:32.016923 extracting modules file /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683676/extract-overlay-ramdisk-4vcaqwu1/ramdisk
191 22:49:32.237643 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:49:32.237821 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
193 22:49:32.237917 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683676/compress-overlay-k1s2a_5v/overlay-1.5.2.4.tar.gz to ramdisk
194 22:49:32.237986 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683676/compress-overlay-k1s2a_5v/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683676/extract-overlay-ramdisk-4vcaqwu1/ramdisk
195 22:49:32.244501 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:49:32.244627 start: 1.5.6 configure-preseed-file (timeout 00:09:48) [common]
197 22:49:32.244720 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:49:32.244807 start: 1.5.7 compress-ramdisk (timeout 00:09:48) [common]
199 22:49:32.244883 Building ramdisk /var/lib/lava/dispatcher/tmp/13683676/extract-overlay-ramdisk-4vcaqwu1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683676/extract-overlay-ramdisk-4vcaqwu1/ramdisk
200 22:49:33.456614 >> 465910 blocks
201 22:49:39.756334 rename /var/lib/lava/dispatcher/tmp/13683676/extract-overlay-ramdisk-4vcaqwu1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/ramdisk/ramdisk.cpio.gz
202 22:49:39.756899 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 22:49:39.757075 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
204 22:49:39.757240 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
205 22:49:39.757476 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/kernel/Image'
206 22:49:53.687597 Returned 0 in 13 seconds
207 22:49:53.788242 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/kernel/image.itb
208 22:49:54.618808 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:49:54.619187 output: Created: Tue May 7 23:49:54 2024
210 22:49:54.619260 output: Image 0 (kernel-1)
211 22:49:54.619326 output: Description:
212 22:49:54.619389 output: Created: Tue May 7 23:49:54 2024
213 22:49:54.619448 output: Type: Kernel Image
214 22:49:54.619506 output: Compression: lzma compressed
215 22:49:54.619563 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
216 22:49:54.619621 output: Architecture: AArch64
217 22:49:54.619677 output: OS: Linux
218 22:49:54.619734 output: Load Address: 0x00000000
219 22:49:54.619791 output: Entry Point: 0x00000000
220 22:49:54.619846 output: Hash algo: crc32
221 22:49:54.619906 output: Hash value: 727ee7c6
222 22:49:54.619963 output: Image 1 (fdt-1)
223 22:49:54.620021 output: Description: mt8192-asurada-spherion-r0
224 22:49:54.620074 output: Created: Tue May 7 23:49:54 2024
225 22:49:54.620127 output: Type: Flat Device Tree
226 22:49:54.620179 output: Compression: uncompressed
227 22:49:54.620230 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 22:49:54.620282 output: Architecture: AArch64
229 22:49:54.620334 output: Hash algo: crc32
230 22:49:54.620386 output: Hash value: 0f8e4d2e
231 22:49:54.620437 output: Image 2 (ramdisk-1)
232 22:49:54.620489 output: Description: unavailable
233 22:49:54.620551 output: Created: Tue May 7 23:49:54 2024
234 22:49:54.620622 output: Type: RAMDisk Image
235 22:49:54.620677 output: Compression: Unknown Compression
236 22:49:54.620729 output: Data Size: 60992931 Bytes = 59563.41 KiB = 58.17 MiB
237 22:49:54.620782 output: Architecture: AArch64
238 22:49:54.620835 output: OS: Linux
239 22:49:54.620887 output: Load Address: unavailable
240 22:49:54.620938 output: Entry Point: unavailable
241 22:49:54.620990 output: Hash algo: crc32
242 22:49:54.621042 output: Hash value: 63295a9e
243 22:49:54.621093 output: Default Configuration: 'conf-1'
244 22:49:54.621145 output: Configuration 0 (conf-1)
245 22:49:54.621196 output: Description: mt8192-asurada-spherion-r0
246 22:49:54.621248 output: Kernel: kernel-1
247 22:49:54.621299 output: Init Ramdisk: ramdisk-1
248 22:49:54.621405 output: FDT: fdt-1
249 22:49:54.621461 output: Loadables: kernel-1
250 22:49:54.621514 output:
251 22:49:54.621720 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 22:49:54.621820 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 22:49:54.621931 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 22:49:54.622049 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:26) [common]
255 22:49:54.622144 No LXC device requested
256 22:49:54.622222 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:49:54.622305 start: 1.7 deploy-device-env (timeout 00:09:26) [common]
258 22:49:54.622382 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:49:54.622457 Checking files for TFTP limit of 4294967296 bytes.
260 22:49:54.622970 end: 1 tftp-deploy (duration 00:00:34) [common]
261 22:49:54.623071 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:49:54.623164 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:49:54.623287 substitutions:
264 22:49:54.623352 - {DTB}: 13683676/tftp-deploy-mn31krvj/dtb/mt8192-asurada-spherion-r0.dtb
265 22:49:54.623415 - {INITRD}: 13683676/tftp-deploy-mn31krvj/ramdisk/ramdisk.cpio.gz
266 22:49:54.623474 - {KERNEL}: 13683676/tftp-deploy-mn31krvj/kernel/Image
267 22:49:54.623530 - {LAVA_MAC}: None
268 22:49:54.623586 - {PRESEED_CONFIG}: None
269 22:49:54.623640 - {PRESEED_LOCAL}: None
270 22:49:54.623694 - {RAMDISK}: 13683676/tftp-deploy-mn31krvj/ramdisk/ramdisk.cpio.gz
271 22:49:54.623748 - {ROOT_PART}: None
272 22:49:54.623801 - {ROOT}: None
273 22:49:54.623857 - {SERVER_IP}: 192.168.201.1
274 22:49:54.623910 - {TEE}: None
275 22:49:54.623962 Parsed boot commands:
276 22:49:54.624014 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:49:54.624193 Parsed boot commands: tftpboot 192.168.201.1 13683676/tftp-deploy-mn31krvj/kernel/image.itb 13683676/tftp-deploy-mn31krvj/kernel/cmdline
278 22:49:54.624284 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:49:54.624387 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:49:54.624477 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:49:54.624559 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:49:54.624631 Not connected, no need to disconnect.
283 22:49:54.624706 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:49:54.624788 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:49:54.624854 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 22:49:54.629116 Setting prompt string to ['lava-test: # ']
287 22:49:54.629577 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:49:54.629694 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:49:54.629845 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:49:54.630000 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:49:54.630226 Calling: '/usr/local/bin/chromebook-reboot.sh' 'mt8192-asurada-spherion-r0-cbg-9'
292 22:50:08.499847 Returned 0 in 13 seconds
293 22:50:08.600581 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 22:50:08.601234 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 22:50:08.601357 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 22:50:08.601474 Setting prompt string to 'Starting depthcharge on Spherion...'
298 22:50:08.601543 Changing prompt to 'Starting depthcharge on Spherion...'
299 22:50:08.601621 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 22:50:08.601970 [Enter `^Ec?' for help]
301 22:50:08.602123
302 22:50:08.602192 F0: 102B 0000
303 22:50:08.602258
304 22:50:08.602320 F3: 1001 0000 [0200]
305 22:50:08.602399
306 22:50:08.602463 F3: 1001 0000
307 22:50:08.602533
308 22:50:08.602587 F7: 102D 0000
309 22:50:08.602660
310 22:50:08.602715 F1: 0000 0000
311 22:50:08.602769
312 22:50:08.602823 V0: 0000 0000 [0001]
313 22:50:08.602896
314 22:50:08.602952 00: 0007 8000
315 22:50:08.603009
316 22:50:08.603063 01: 0000 0000
317 22:50:08.603130
318 22:50:08.603186 BP: 0C00 0209 [0000]
319 22:50:08.603240
320 22:50:08.603293 G0: 1182 0000
321 22:50:08.603351
322 22:50:08.603439 EC: 0000 0021 [4000]
323 22:50:08.603522
324 22:50:08.603609 S7: 0000 0000 [0000]
325 22:50:08.603697
326 22:50:08.603780 CC: 0000 0000 [0001]
327 22:50:08.603901
328 22:50:08.603985 T0: 0000 0040 [010F]
329 22:50:08.604068
330 22:50:08.604159 Jump to BL
331 22:50:08.604242
332 22:50:08.604324
333 22:50:08.604414
334 22:50:08.604496
335 22:50:08.604580 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 22:50:08.604675 ARM64: Exception handlers installed.
337 22:50:08.604798 ARM64: Testing exception
338 22:50:08.604926 ARM64: Done test exception
339 22:50:08.605015 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 22:50:08.605105 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 22:50:08.605195 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 22:50:08.605283 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 22:50:08.605397 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 22:50:08.605455 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 22:50:08.605510 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 22:50:08.605565 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 22:50:08.605619 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 22:50:08.605673 WDT: Last reset was cold boot
349 22:50:08.605727 SPI1(PAD0) initialized at 2873684 Hz
350 22:50:08.605780 SPI5(PAD0) initialized at 992727 Hz
351 22:50:08.605834 VBOOT: Loading verstage.
352 22:50:08.605888 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 22:50:08.605982 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 22:50:08.606036 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 22:50:08.606090 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 22:50:08.606144 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 22:50:08.606198 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 22:50:08.606251 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 22:50:08.606307
360 22:50:08.606360
361 22:50:08.606413 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 22:50:08.606467 ARM64: Exception handlers installed.
363 22:50:08.606520 ARM64: Testing exception
364 22:50:08.606573 ARM64: Done test exception
365 22:50:08.606625 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 22:50:08.606678 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 22:50:08.606732 Probing TPM: . done!
368 22:50:08.606785 TPM ready after 0 ms
369 22:50:08.606838 Connected to device vid:did:rid of 1ae0:0028:00
370 22:50:08.606891 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
371 22:50:08.606946 Initialized TPM device CR50 revision 0
372 22:50:08.607000 tlcl_send_startup: Startup return code is 0
373 22:50:08.607053 TPM: setup succeeded
374 22:50:08.607106 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 22:50:08.607160 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 22:50:08.607224 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 22:50:08.607299 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:50:08.607355 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 22:50:08.607410 in-header: 03 07 00 00 08 00 00 00
380 22:50:08.607463 in-data: aa e4 47 04 13 02 00 00
381 22:50:08.607516 Chrome EC: UHEPI supported
382 22:50:08.607569 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 22:50:08.607623 in-header: 03 a9 00 00 08 00 00 00
384 22:50:08.607675 in-data: 84 60 60 08 00 00 00 00
385 22:50:08.607728 Phase 1
386 22:50:08.607781 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 22:50:08.607835 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 22:50:08.607888 VB2:vb2_check_recovery() Recovery was requested manually
389 22:50:08.607942 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 22:50:08.607995 Recovery requested (1009000e)
391 22:50:08.608048 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 22:50:08.608102 tlcl_extend: response is 0
393 22:50:08.608155 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 22:50:08.608237 tlcl_extend: response is 0
395 22:50:08.608311 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 22:50:08.608418 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 22:50:08.608523 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 22:50:08.608610
399 22:50:08.608696
400 22:50:08.608757 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 22:50:08.608814 ARM64: Exception handlers installed.
402 22:50:08.608869 ARM64: Testing exception
403 22:50:08.608923 ARM64: Done test exception
404 22:50:08.608977 pmic_efuse_setting: Set efuses in 11 msecs
405 22:50:08.609030 pmwrap_interface_init: Select PMIF_VLD_RDY
406 22:50:08.609084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 22:50:08.609335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 22:50:08.609510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 22:50:08.609570 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 22:50:08.609626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 22:50:08.609680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 22:50:08.609735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 22:50:08.609789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 22:50:08.609844 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 22:50:08.609913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 22:50:08.609966 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 22:50:08.610020 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 22:50:08.610072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 22:50:08.610126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 22:50:08.610195 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 22:50:08.610264 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 22:50:08.610318 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 22:50:08.610371 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 22:50:08.610425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 22:50:08.610478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 22:50:08.610531 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 22:50:08.610585 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 22:50:08.610638 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 22:50:08.610692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 22:50:08.610777 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 22:50:08.610830 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 22:50:08.610883 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 22:50:08.610937 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 22:50:08.610990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 22:50:08.611073 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 22:50:08.611126 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 22:50:08.611179 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 22:50:08.611249 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 22:50:08.611304 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 22:50:08.611358 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 22:50:08.611413 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 22:50:08.611481 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 22:50:08.611535 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 22:50:08.611587 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 22:50:08.611640 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 22:50:08.611693 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 22:50:08.611746 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 22:50:08.611799 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 22:50:08.611870 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 22:50:08.611937 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 22:50:08.611990 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 22:50:08.612043 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 22:50:08.612096 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 22:50:08.612148 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 22:50:08.612202 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 22:50:08.612254 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 22:50:08.612308 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 22:50:08.612362 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 22:50:08.612416 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 22:50:08.612469 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 22:50:08.612602 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 22:50:08.612707 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 22:50:08.612795 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 22:50:08.612879 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:50:08.612938 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1b
466 22:50:08.612993 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 22:50:08.613048 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
468 22:50:08.613102 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 22:50:08.613156 [RTC]rtc_get_frequency_meter,154: input=15, output=836
470 22:50:08.613209 [RTC]rtc_get_frequency_meter,154: input=7, output=708
471 22:50:08.613262 [RTC]rtc_get_frequency_meter,154: input=11, output=772
472 22:50:08.613316 [RTC]rtc_get_frequency_meter,154: input=13, output=804
473 22:50:08.613410 [RTC]rtc_get_frequency_meter,154: input=12, output=788
474 22:50:08.613464 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 22:50:08.613517 [RTC]rtc_get_frequency_meter,154: input=13, output=804
476 22:50:08.613570 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
477 22:50:08.613827 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
478 22:50:08.613890 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 22:50:08.613946 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 22:50:08.614001 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 22:50:08.614056 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 22:50:08.614110 ADC[4]: Raw value=904879 ID=7
483 22:50:08.614165 ADC[3]: Raw value=213282 ID=1
484 22:50:08.614219 RAM Code: 0x71
485 22:50:08.614287 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 22:50:08.614341 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 22:50:08.614411 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 22:50:08.614482 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 22:50:08.614536 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 22:50:08.614589 in-header: 03 07 00 00 08 00 00 00
491 22:50:08.614642 in-data: aa e4 47 04 13 02 00 00
492 22:50:08.614695 Chrome EC: UHEPI supported
493 22:50:08.614748 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 22:50:08.614802 in-header: 03 a9 00 00 08 00 00 00
495 22:50:08.614855 in-data: 84 60 60 08 00 00 00 00
496 22:50:08.614908 MRC: failed to locate region type 0.
497 22:50:08.614960 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 22:50:08.615014 DRAM-K: Running full calibration
499 22:50:08.615067 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 22:50:08.615121 header.status = 0x0
501 22:50:08.615174 header.version = 0x6 (expected: 0x6)
502 22:50:08.615227 header.size = 0xd00 (expected: 0xd00)
503 22:50:08.615280 header.flags = 0x0
504 22:50:08.615333 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 22:50:08.615386 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 22:50:08.615440 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 22:50:08.615494 dram_init: ddr_geometry: 2
508 22:50:08.615547 [EMI] MDL number = 2
509 22:50:08.615600 [EMI] Get MDL freq = 0
510 22:50:08.615653 dram_init: ddr_type: 0
511 22:50:08.615705 is_discrete_lpddr4: 1
512 22:50:08.615758 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 22:50:08.615811
514 22:50:08.615886
515 22:50:08.615991 [Bian_co] ETT version 0.0.0.1
516 22:50:08.616063 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 22:50:08.616134
518 22:50:08.616229 dramc_set_vcore_voltage set vcore to 650000
519 22:50:08.616317 Read voltage for 800, 4
520 22:50:08.616403 Vio18 = 0
521 22:50:08.616457 Vcore = 650000
522 22:50:08.616511 Vdram = 0
523 22:50:08.616603 Vddq = 0
524 22:50:08.616708 Vmddr = 0
525 22:50:08.616801 dram_init: config_dvfs: 1
526 22:50:08.616881 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 22:50:08.616979 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 22:50:08.617041 [SwImpedanceCal] DRVP=8, DRVN=15, ODTN=9
529 22:50:08.617127 freq_region=0, Reg: DRVP=8, DRVN=15, ODTN=9
530 22:50:08.617184 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
531 22:50:08.617239 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
532 22:50:08.617295 MEM_TYPE=3, freq_sel=18
533 22:50:08.617360 sv_algorithm_assistance_LP4_1600
534 22:50:08.617416 ============ PULL DRAM RESETB DOWN ============
535 22:50:08.617474 ========== PULL DRAM RESETB DOWN end =========
536 22:50:08.617529 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 22:50:08.617584 ===================================
538 22:50:08.617639 LPDDR4 DRAM CONFIGURATION
539 22:50:08.617693 ===================================
540 22:50:08.617748 EX_ROW_EN[0] = 0x0
541 22:50:08.617808 EX_ROW_EN[1] = 0x0
542 22:50:08.617865 LP4Y_EN = 0x0
543 22:50:08.617919 WORK_FSP = 0x0
544 22:50:08.617973 WL = 0x2
545 22:50:08.618027 RL = 0x2
546 22:50:08.618081 BL = 0x2
547 22:50:08.618135 RPST = 0x0
548 22:50:08.618189 RD_PRE = 0x0
549 22:50:08.618242 WR_PRE = 0x1
550 22:50:08.618296 WR_PST = 0x0
551 22:50:08.618350 DBI_WR = 0x0
552 22:50:08.618404 DBI_RD = 0x0
553 22:50:08.618458 OTF = 0x1
554 22:50:08.618525 ===================================
555 22:50:08.618577 ===================================
556 22:50:08.618693 ANA top config
557 22:50:08.618772 ===================================
558 22:50:08.618854 DLL_ASYNC_EN = 0
559 22:50:08.618924 ALL_SLAVE_EN = 1
560 22:50:08.619036 NEW_RANK_MODE = 1
561 22:50:08.619132 DLL_IDLE_MODE = 1
562 22:50:08.619187 LP45_APHY_COMB_EN = 1
563 22:50:08.619265 TX_ODT_DIS = 1
564 22:50:08.619363 NEW_8X_MODE = 1
565 22:50:08.619452 ===================================
566 22:50:08.619506 ===================================
567 22:50:08.619560 data_rate = 1600
568 22:50:08.619676 CKR = 1
569 22:50:08.619732 DQ_P2S_RATIO = 8
570 22:50:08.619811 ===================================
571 22:50:08.619906 CA_P2S_RATIO = 8
572 22:50:08.619994 DQ_CA_OPEN = 0
573 22:50:08.620047 DQ_SEMI_OPEN = 0
574 22:50:08.620100 CA_SEMI_OPEN = 0
575 22:50:08.620153 CA_FULL_RATE = 0
576 22:50:08.620206 DQ_CKDIV4_EN = 1
577 22:50:08.620258 CA_CKDIV4_EN = 1
578 22:50:08.620312 CA_PREDIV_EN = 0
579 22:50:08.620365 PH8_DLY = 0
580 22:50:08.620418 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 22:50:08.620471 DQ_AAMCK_DIV = 4
582 22:50:08.620524 CA_AAMCK_DIV = 4
583 22:50:08.620577 CA_ADMCK_DIV = 4
584 22:50:08.620629 DQ_TRACK_CA_EN = 0
585 22:50:08.620703 CA_PICK = 800
586 22:50:08.620796 CA_MCKIO = 800
587 22:50:08.620881 MCKIO_SEMI = 0
588 22:50:08.620967 PLL_FREQ = 3068
589 22:50:08.621029 DQ_UI_PI_RATIO = 32
590 22:50:08.621083 CA_UI_PI_RATIO = 0
591 22:50:08.621137 ===================================
592 22:50:08.621190 ===================================
593 22:50:08.621243 memory_type:LPDDR4
594 22:50:08.621296 GP_NUM : 10
595 22:50:08.621373 SRAM_EN : 1
596 22:50:08.621441 MD32_EN : 0
597 22:50:08.621711 ===================================
598 22:50:08.621785 [ANA_INIT] >>>>>>>>>>>>>>
599 22:50:08.621839 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 22:50:08.621928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 22:50:08.622004 ===================================
602 22:50:08.622102 data_rate = 1600,PCW = 0X7600
603 22:50:08.622158 ===================================
604 22:50:08.622212 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 22:50:08.622266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 22:50:08.622321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:50:08.622375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 22:50:08.622430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 22:50:08.622482 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:50:08.622536 [ANA_INIT] flow start
611 22:50:08.622589 [ANA_INIT] PLL >>>>>>>>
612 22:50:08.622642 [ANA_INIT] PLL <<<<<<<<
613 22:50:08.622695 [ANA_INIT] MIDPI >>>>>>>>
614 22:50:08.622748 [ANA_INIT] MIDPI <<<<<<<<
615 22:50:08.622800 [ANA_INIT] DLL >>>>>>>>
616 22:50:08.622853 [ANA_INIT] flow end
617 22:50:08.622906 ============ LP4 DIFF to SE enter ============
618 22:50:08.622960 ============ LP4 DIFF to SE exit ============
619 22:50:08.623013 [ANA_INIT] <<<<<<<<<<<<<
620 22:50:08.623066 [Flow] Enable top DCM control >>>>>
621 22:50:08.623119 [Flow] Enable top DCM control <<<<<
622 22:50:08.623172 Enable DLL master slave shuffle
623 22:50:08.623225 ==============================================================
624 22:50:08.623278 Gating Mode config
625 22:50:08.623331 ==============================================================
626 22:50:08.623383 Config description:
627 22:50:08.623436 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 22:50:08.623490 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 22:50:08.623544 SELPH_MODE 0: By rank 1: By Phase
630 22:50:08.623597 ==============================================================
631 22:50:08.623650 GAT_TRACK_EN = 1
632 22:50:08.623703 RX_GATING_MODE = 2
633 22:50:08.623755 RX_GATING_TRACK_MODE = 2
634 22:50:08.623808 SELPH_MODE = 1
635 22:50:08.623860 PICG_EARLY_EN = 1
636 22:50:08.623913 VALID_LAT_VALUE = 1
637 22:50:08.623966 ==============================================================
638 22:50:08.624019 Enter into Gating configuration >>>>
639 22:50:08.624071 Exit from Gating configuration <<<<
640 22:50:08.624124 Enter into DVFS_PRE_config >>>>>
641 22:50:08.624177 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 22:50:08.624247 Exit from DVFS_PRE_config <<<<<
643 22:50:08.624336 Enter into PICG configuration >>>>
644 22:50:08.624421 Exit from PICG configuration <<<<
645 22:50:08.624505 [RX_INPUT] configuration >>>>>
646 22:50:08.624579 [RX_INPUT] configuration <<<<<
647 22:50:08.624636 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 22:50:08.624691 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 22:50:08.624745 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 22:50:08.624798 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 22:50:08.624852 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 22:50:08.624906 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 22:50:08.624960 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 22:50:08.625013 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 22:50:08.625066 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 22:50:08.625118 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 22:50:08.625172 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 22:50:08.625225 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 22:50:08.625278 ===================================
660 22:50:08.625358 LPDDR4 DRAM CONFIGURATION
661 22:50:08.625427 ===================================
662 22:50:08.625480 EX_ROW_EN[0] = 0x0
663 22:50:08.625533 EX_ROW_EN[1] = 0x0
664 22:50:08.625585 LP4Y_EN = 0x0
665 22:50:08.625637 WORK_FSP = 0x0
666 22:50:08.625689 WL = 0x2
667 22:50:08.625742 RL = 0x2
668 22:50:08.625794 BL = 0x2
669 22:50:08.625846 RPST = 0x0
670 22:50:08.625899 RD_PRE = 0x0
671 22:50:08.625951 WR_PRE = 0x1
672 22:50:08.626003 WR_PST = 0x0
673 22:50:08.626055 DBI_WR = 0x0
674 22:50:08.626107 DBI_RD = 0x0
675 22:50:08.626159 OTF = 0x1
676 22:50:08.626212 ===================================
677 22:50:08.626265 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 22:50:08.626318 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 22:50:08.626371 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 22:50:08.626424 ===================================
681 22:50:08.626476 LPDDR4 DRAM CONFIGURATION
682 22:50:08.626529 ===================================
683 22:50:08.626582 EX_ROW_EN[0] = 0x10
684 22:50:08.626635 EX_ROW_EN[1] = 0x0
685 22:50:08.626687 LP4Y_EN = 0x0
686 22:50:08.626739 WORK_FSP = 0x0
687 22:50:08.626792 WL = 0x2
688 22:50:08.626844 RL = 0x2
689 22:50:08.626896 BL = 0x2
690 22:50:08.626948 RPST = 0x0
691 22:50:08.627000 RD_PRE = 0x0
692 22:50:08.627052 WR_PRE = 0x1
693 22:50:08.627104 WR_PST = 0x0
694 22:50:08.627156 DBI_WR = 0x0
695 22:50:08.627208 DBI_RD = 0x0
696 22:50:08.627261 OTF = 0x1
697 22:50:08.627313 ===================================
698 22:50:08.627367 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 22:50:08.627420 nWR fixed to 40
700 22:50:08.627473 [ModeRegInit_LP4] CH0 RK0
701 22:50:08.627525 [ModeRegInit_LP4] CH0 RK1
702 22:50:08.627578 [ModeRegInit_LP4] CH1 RK0
703 22:50:08.627630 [ModeRegInit_LP4] CH1 RK1
704 22:50:08.627683 match AC timing 13
705 22:50:08.627947 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 22:50:08.628025 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 22:50:08.628080 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 22:50:08.628133 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 22:50:08.628187 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 22:50:08.628240 [EMI DOE] emi_dcm 0
711 22:50:08.628293 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 22:50:08.628346 ==
713 22:50:08.628427 Dram Type= 6, Freq= 0, CH_0, rank 0
714 22:50:08.628517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 22:50:08.628605 ==
716 22:50:08.628709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 22:50:08.628771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 22:50:08.628828 [CA 0] Center 37 (7~68) winsize 62
719 22:50:08.628883 [CA 1] Center 37 (6~68) winsize 63
720 22:50:08.628938 [CA 2] Center 34 (4~65) winsize 62
721 22:50:08.628992 [CA 3] Center 34 (4~65) winsize 62
722 22:50:08.629046 [CA 4] Center 33 (3~64) winsize 62
723 22:50:08.629099 [CA 5] Center 33 (3~64) winsize 62
724 22:50:08.629154
725 22:50:08.629208 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 22:50:08.629263
727 22:50:08.629317 [CATrainingPosCal] consider 1 rank data
728 22:50:08.629424 u2DelayCellTimex100 = 270/100 ps
729 22:50:08.629508 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 22:50:08.629599 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 22:50:08.629695 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 22:50:08.629766 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 22:50:08.629837 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 22:50:08.629922 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 22:50:08.630006
736 22:50:08.630061 CA PerBit enable=1, Macro0, CA PI delay=33
737 22:50:08.630116
738 22:50:08.630171 [CBTSetCACLKResult] CA Dly = 33
739 22:50:08.630225 CS Dly: 7 (0~38)
740 22:50:08.630279 ==
741 22:50:08.630333 Dram Type= 6, Freq= 0, CH_0, rank 1
742 22:50:08.630388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 22:50:08.630442 ==
744 22:50:08.630497 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 22:50:08.630551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 22:50:08.630606 [CA 0] Center 37 (6~68) winsize 63
747 22:50:08.630660 [CA 1] Center 37 (7~68) winsize 62
748 22:50:08.630714 [CA 2] Center 34 (4~65) winsize 62
749 22:50:08.630767 [CA 3] Center 34 (4~65) winsize 62
750 22:50:08.630821 [CA 4] Center 33 (3~64) winsize 62
751 22:50:08.630874 [CA 5] Center 33 (2~64) winsize 63
752 22:50:08.630928
753 22:50:08.630982 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 22:50:08.631035
755 22:50:08.631089 [CATrainingPosCal] consider 2 rank data
756 22:50:08.631143 u2DelayCellTimex100 = 270/100 ps
757 22:50:08.631198 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 22:50:08.631252 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 22:50:08.631306 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 22:50:08.631361 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 22:50:08.631415 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 22:50:08.631469 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 22:50:08.631523
764 22:50:08.631577 CA PerBit enable=1, Macro0, CA PI delay=33
765 22:50:08.631631
766 22:50:08.631685 [CBTSetCACLKResult] CA Dly = 33
767 22:50:08.631749 CS Dly: 7 (0~38)
768 22:50:08.631804
769 22:50:08.631858 ----->DramcWriteLeveling(PI) begin...
770 22:50:08.631916 ==
771 22:50:08.631970 Dram Type= 6, Freq= 0, CH_0, rank 0
772 22:50:08.632024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 22:50:08.632080 ==
774 22:50:08.632148 Write leveling (Byte 0): 31 => 31
775 22:50:08.632222 Write leveling (Byte 1): 30 => 30
776 22:50:08.632279 DramcWriteLeveling(PI) end<-----
777 22:50:08.632334
778 22:50:08.632387 ==
779 22:50:08.632442 Dram Type= 6, Freq= 0, CH_0, rank 0
780 22:50:08.632500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 22:50:08.632593 ==
782 22:50:08.632681 [Gating] SW mode calibration
783 22:50:08.632769 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 22:50:08.632850 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 22:50:08.632910 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 22:50:08.632967 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:50:08.633023 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 22:50:08.633078 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:50:08.633132 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:50:08.633186 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:50:08.633240 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:50:08.633294 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:50:08.633373 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:50:08.633428 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:50:08.633481 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:50:08.633534 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:50:08.633587 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:50:08.633640 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:50:08.633693 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:50:08.633764 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:50:08.633832 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:50:08.633903 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
803 22:50:08.633992 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 22:50:08.634063 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:50:08.634118 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:50:08.634188 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:50:08.634255 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:50:08.634309 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:50:08.634363 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:50:08.634432 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:50:08.634499 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
812 22:50:08.634582 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
813 22:50:08.634877 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 22:50:08.634942 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:50:08.634997 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:50:08.635052 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:50:08.635107 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:50:08.635161 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:50:08.635215 0 10 8 | B1->B0 | 3232 2929 | 0 0 | (0 1) (1 1)
820 22:50:08.635270 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
821 22:50:08.635323 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 22:50:08.635378 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:50:08.635432 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:50:08.635486 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:50:08.635540 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:50:08.635594 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
827 22:50:08.635648 0 11 8 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
828 22:50:08.635702 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
829 22:50:08.635756 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 22:50:08.635810 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:50:08.635864 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:50:08.635918 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:50:08.635972 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:50:08.636026 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 22:50:08.636080 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 22:50:08.636134 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:50:08.636188 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:50:08.636242 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:50:08.636296 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:50:08.636350 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:50:08.636404 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:50:08.636458 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:50:08.636512 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:50:08.636566 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:50:08.636631 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:50:08.636708 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:50:08.636797 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:50:08.636887 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:50:08.636971 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:50:08.637030 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 22:50:08.637086 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 22:50:08.637141 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 22:50:08.637195 Total UI for P1: 0, mck2ui 16
854 22:50:08.637250 best dqsien dly found for B0: ( 0, 14, 6)
855 22:50:08.637305 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 22:50:08.637370 Total UI for P1: 0, mck2ui 16
857 22:50:08.637425 best dqsien dly found for B1: ( 0, 14, 10)
858 22:50:08.637480 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 22:50:08.637534 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 22:50:08.637589
861 22:50:08.637643 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 22:50:08.637697 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 22:50:08.637751 [Gating] SW calibration Done
864 22:50:08.637805 ==
865 22:50:08.637859 Dram Type= 6, Freq= 0, CH_0, rank 0
866 22:50:08.637913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 22:50:08.637967 ==
868 22:50:08.638021 RX Vref Scan: 0
869 22:50:08.638075
870 22:50:08.638129 RX Vref 0 -> 0, step: 1
871 22:50:08.638182
872 22:50:08.638236 RX Delay -130 -> 252, step: 16
873 22:50:08.638290 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 22:50:08.638343 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 22:50:08.638397 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 22:50:08.638451 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 22:50:08.638506 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 22:50:08.638559 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 22:50:08.638612 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 22:50:08.638666 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 22:50:08.638720 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 22:50:08.638773 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
883 22:50:08.638827 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 22:50:08.638881 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 22:50:08.638935 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
886 22:50:08.638988 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 22:50:08.639042 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 22:50:08.639096 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 22:50:08.639150 ==
890 22:50:08.639205 Dram Type= 6, Freq= 0, CH_0, rank 0
891 22:50:08.639259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 22:50:08.639313 ==
893 22:50:08.639367 DQS Delay:
894 22:50:08.639420 DQS0 = 0, DQS1 = 0
895 22:50:08.639474 DQM Delay:
896 22:50:08.639528 DQM0 = 86, DQM1 = 74
897 22:50:08.639582 DQ Delay:
898 22:50:08.639635 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 22:50:08.639689 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
900 22:50:08.639743 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
901 22:50:08.639797 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
902 22:50:08.639850
903 22:50:08.639904
904 22:50:08.639958 ==
905 22:50:08.640026 Dram Type= 6, Freq= 0, CH_0, rank 0
906 22:50:08.640116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 22:50:08.640202 ==
908 22:50:08.640261
909 22:50:08.640343
910 22:50:08.640436 TX Vref Scan disable
911 22:50:08.640524 == TX Byte 0 ==
912 22:50:08.640611 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 22:50:08.640677 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 22:50:08.640733 == TX Byte 1 ==
915 22:50:08.640788 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 22:50:08.640843 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 22:50:08.640898 ==
918 22:50:08.640952 Dram Type= 6, Freq= 0, CH_0, rank 0
919 22:50:08.641006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 22:50:08.641061 ==
921 22:50:08.641310 TX Vref=22, minBit 4, minWin=27, winSum=440
922 22:50:08.641383 TX Vref=24, minBit 5, minWin=27, winSum=444
923 22:50:08.641440 TX Vref=26, minBit 5, minWin=27, winSum=448
924 22:50:08.641495 TX Vref=28, minBit 10, minWin=27, winSum=450
925 22:50:08.641550 TX Vref=30, minBit 4, minWin=27, winSum=448
926 22:50:08.641604 TX Vref=32, minBit 4, minWin=27, winSum=444
927 22:50:08.641659 [TxChooseVref] Worse bit 10, Min win 27, Win sum 450, Final Vref 28
928 22:50:08.641714
929 22:50:08.641768 Final TX Range 1 Vref 28
930 22:50:08.641823
931 22:50:08.641876 ==
932 22:50:08.641930 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:50:08.641984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:50:08.642039 ==
935 22:50:08.642094
936 22:50:08.642147
937 22:50:08.642201 TX Vref Scan disable
938 22:50:08.642254 == TX Byte 0 ==
939 22:50:08.642308 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 22:50:08.642362 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 22:50:08.642416 == TX Byte 1 ==
942 22:50:08.642470 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 22:50:08.642528 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 22:50:08.642582
945 22:50:08.642636 [DATLAT]
946 22:50:08.642689 Freq=800, CH0 RK0
947 22:50:08.642743
948 22:50:08.642796 DATLAT Default: 0xa
949 22:50:08.642849 0, 0xFFFF, sum = 0
950 22:50:08.642904 1, 0xFFFF, sum = 0
951 22:50:08.642958 2, 0xFFFF, sum = 0
952 22:50:08.643012 3, 0xFFFF, sum = 0
953 22:50:08.643066 4, 0xFFFF, sum = 0
954 22:50:08.643120 5, 0xFFFF, sum = 0
955 22:50:08.643174 6, 0xFFFF, sum = 0
956 22:50:08.643229 7, 0xFFFF, sum = 0
957 22:50:08.643284 8, 0xFFFF, sum = 0
958 22:50:08.643338 9, 0x0, sum = 1
959 22:50:08.643392 10, 0x0, sum = 2
960 22:50:08.643447 11, 0x0, sum = 3
961 22:50:08.643501 12, 0x0, sum = 4
962 22:50:08.643555 best_step = 10
963 22:50:08.643609
964 22:50:08.643662 ==
965 22:50:08.643716 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:50:08.643769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:50:08.643824 ==
968 22:50:08.643876 RX Vref Scan: 1
969 22:50:08.643930
970 22:50:08.643982 Set Vref Range= 32 -> 127
971 22:50:08.644036
972 22:50:08.644089 RX Vref 32 -> 127, step: 1
973 22:50:08.644143
974 22:50:08.644196 RX Delay -111 -> 252, step: 8
975 22:50:08.644250
976 22:50:08.644303 Set Vref, RX VrefLevel [Byte0]: 32
977 22:50:08.644357 [Byte1]: 32
978 22:50:08.644410
979 22:50:08.644463 Set Vref, RX VrefLevel [Byte0]: 33
980 22:50:08.644517 [Byte1]: 33
981 22:50:08.644571
982 22:50:08.644624 Set Vref, RX VrefLevel [Byte0]: 34
983 22:50:08.644683 [Byte1]: 34
984 22:50:08.644763
985 22:50:08.644853 Set Vref, RX VrefLevel [Byte0]: 35
986 22:50:08.644941 [Byte1]: 35
987 22:50:08.645028
988 22:50:08.645088 Set Vref, RX VrefLevel [Byte0]: 36
989 22:50:08.645144 [Byte1]: 36
990 22:50:08.645199
991 22:50:08.645254 Set Vref, RX VrefLevel [Byte0]: 37
992 22:50:08.645308 [Byte1]: 37
993 22:50:08.645375
994 22:50:08.645430 Set Vref, RX VrefLevel [Byte0]: 38
995 22:50:08.645485 [Byte1]: 38
996 22:50:08.645539
997 22:50:08.645593 Set Vref, RX VrefLevel [Byte0]: 39
998 22:50:08.645647 [Byte1]: 39
999 22:50:08.645701
1000 22:50:08.645754 Set Vref, RX VrefLevel [Byte0]: 40
1001 22:50:08.645809 [Byte1]: 40
1002 22:50:08.645862
1003 22:50:08.645916 Set Vref, RX VrefLevel [Byte0]: 41
1004 22:50:08.645970 [Byte1]: 41
1005 22:50:08.646024
1006 22:50:08.646077 Set Vref, RX VrefLevel [Byte0]: 42
1007 22:50:08.646131 [Byte1]: 42
1008 22:50:08.646184
1009 22:50:08.646238 Set Vref, RX VrefLevel [Byte0]: 43
1010 22:50:08.646293 [Byte1]: 43
1011 22:50:08.646346
1012 22:50:08.646400 Set Vref, RX VrefLevel [Byte0]: 44
1013 22:50:08.646454 [Byte1]: 44
1014 22:50:08.646508
1015 22:50:08.646561 Set Vref, RX VrefLevel [Byte0]: 45
1016 22:50:08.646615 [Byte1]: 45
1017 22:50:08.646670
1018 22:50:08.646726 Set Vref, RX VrefLevel [Byte0]: 46
1019 22:50:08.646780 [Byte1]: 46
1020 22:50:08.646834
1021 22:50:08.646888 Set Vref, RX VrefLevel [Byte0]: 47
1022 22:50:08.646942 [Byte1]: 47
1023 22:50:08.646996
1024 22:50:08.647049 Set Vref, RX VrefLevel [Byte0]: 48
1025 22:50:08.647110 [Byte1]: 48
1026 22:50:08.647167
1027 22:50:08.647222 Set Vref, RX VrefLevel [Byte0]: 49
1028 22:50:08.647276 [Byte1]: 49
1029 22:50:08.647330
1030 22:50:08.647383 Set Vref, RX VrefLevel [Byte0]: 50
1031 22:50:08.647437 [Byte1]: 50
1032 22:50:08.647491
1033 22:50:08.647543 Set Vref, RX VrefLevel [Byte0]: 51
1034 22:50:08.647596 [Byte1]: 51
1035 22:50:08.647649
1036 22:50:08.647702 Set Vref, RX VrefLevel [Byte0]: 52
1037 22:50:08.647755 [Byte1]: 52
1038 22:50:08.647807
1039 22:50:08.647860 Set Vref, RX VrefLevel [Byte0]: 53
1040 22:50:08.647913 [Byte1]: 53
1041 22:50:08.647966
1042 22:50:08.648018 Set Vref, RX VrefLevel [Byte0]: 54
1043 22:50:08.648071 [Byte1]: 54
1044 22:50:08.648123
1045 22:50:08.648176 Set Vref, RX VrefLevel [Byte0]: 55
1046 22:50:08.648229 [Byte1]: 55
1047 22:50:08.648281
1048 22:50:08.648334 Set Vref, RX VrefLevel [Byte0]: 56
1049 22:50:08.648394 [Byte1]: 56
1050 22:50:08.648467
1051 22:50:08.648557 Set Vref, RX VrefLevel [Byte0]: 57
1052 22:50:08.648643 [Byte1]: 57
1053 22:50:08.648731
1054 22:50:08.648791 Set Vref, RX VrefLevel [Byte0]: 58
1055 22:50:08.648847 [Byte1]: 58
1056 22:50:08.648902
1057 22:50:08.648956 Set Vref, RX VrefLevel [Byte0]: 59
1058 22:50:08.649010 [Byte1]: 59
1059 22:50:08.649063
1060 22:50:08.649116 Set Vref, RX VrefLevel [Byte0]: 60
1061 22:50:08.649169 [Byte1]: 60
1062 22:50:08.649222
1063 22:50:08.649275 Set Vref, RX VrefLevel [Byte0]: 61
1064 22:50:08.649338 [Byte1]: 61
1065 22:50:08.649394
1066 22:50:08.649457 Set Vref, RX VrefLevel [Byte0]: 62
1067 22:50:08.649525 [Byte1]: 62
1068 22:50:08.649580
1069 22:50:08.649633 Set Vref, RX VrefLevel [Byte0]: 63
1070 22:50:08.649687 [Byte1]: 63
1071 22:50:08.649740
1072 22:50:08.649792 Set Vref, RX VrefLevel [Byte0]: 64
1073 22:50:08.649846 [Byte1]: 64
1074 22:50:08.649899
1075 22:50:08.649952 Set Vref, RX VrefLevel [Byte0]: 65
1076 22:50:08.650006 [Byte1]: 65
1077 22:50:08.650059
1078 22:50:08.650112 Set Vref, RX VrefLevel [Byte0]: 66
1079 22:50:08.650165 [Byte1]: 66
1080 22:50:08.650218
1081 22:50:08.650271 Set Vref, RX VrefLevel [Byte0]: 67
1082 22:50:08.650324 [Byte1]: 67
1083 22:50:08.650377
1084 22:50:08.650430 Set Vref, RX VrefLevel [Byte0]: 68
1085 22:50:08.650482 [Byte1]: 68
1086 22:50:08.650536
1087 22:50:08.650589 Set Vref, RX VrefLevel [Byte0]: 69
1088 22:50:08.650839 [Byte1]: 69
1089 22:50:08.650899
1090 22:50:08.650953 Set Vref, RX VrefLevel [Byte0]: 70
1091 22:50:08.651007 [Byte1]: 70
1092 22:50:08.651060
1093 22:50:08.651113 Set Vref, RX VrefLevel [Byte0]: 71
1094 22:50:08.651166 [Byte1]: 71
1095 22:50:08.651219
1096 22:50:08.651273 Set Vref, RX VrefLevel [Byte0]: 72
1097 22:50:08.651326 [Byte1]: 72
1098 22:50:08.651380
1099 22:50:08.651432 Set Vref, RX VrefLevel [Byte0]: 73
1100 22:50:08.651486 [Byte1]: 73
1101 22:50:08.651539
1102 22:50:08.651593 Set Vref, RX VrefLevel [Byte0]: 74
1103 22:50:08.651646 [Byte1]: 74
1104 22:50:08.651698
1105 22:50:08.651750 Set Vref, RX VrefLevel [Byte0]: 75
1106 22:50:08.651803 [Byte1]: 75
1107 22:50:08.651856
1108 22:50:08.651908 Set Vref, RX VrefLevel [Byte0]: 76
1109 22:50:08.651961 [Byte1]: 76
1110 22:50:08.652014
1111 22:50:08.652066 Set Vref, RX VrefLevel [Byte0]: 77
1112 22:50:08.652119 [Byte1]: 77
1113 22:50:08.652172
1114 22:50:08.652225 Set Vref, RX VrefLevel [Byte0]: 78
1115 22:50:08.652278 [Byte1]: 78
1116 22:50:08.652332
1117 22:50:08.652384 Set Vref, RX VrefLevel [Byte0]: 79
1118 22:50:08.652437 [Byte1]: 79
1119 22:50:08.652490
1120 22:50:08.652543 Set Vref, RX VrefLevel [Byte0]: 80
1121 22:50:08.652595 [Byte1]: 80
1122 22:50:08.652648
1123 22:50:08.652700 Set Vref, RX VrefLevel [Byte0]: 81
1124 22:50:08.652782 [Byte1]: 81
1125 22:50:08.652867
1126 22:50:08.652960 Final RX Vref Byte 0 = 63 to rank0
1127 22:50:08.653050 Final RX Vref Byte 1 = 54 to rank0
1128 22:50:08.653143 Final RX Vref Byte 0 = 63 to rank1
1129 22:50:08.653229 Final RX Vref Byte 1 = 54 to rank1==
1130 22:50:08.653313 Dram Type= 6, Freq= 0, CH_0, rank 0
1131 22:50:08.653383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1132 22:50:08.653439 ==
1133 22:50:08.653493 DQS Delay:
1134 22:50:08.653547 DQS0 = 0, DQS1 = 0
1135 22:50:08.653600 DQM Delay:
1136 22:50:08.653654 DQM0 = 87, DQM1 = 75
1137 22:50:08.653708 DQ Delay:
1138 22:50:08.653761 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1139 22:50:08.653814 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1140 22:50:08.653867 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1141 22:50:08.653920 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1142 22:50:08.653973
1143 22:50:08.654026
1144 22:50:08.654079 [DQSOSCAuto] RK0, (LSB)MR18= 0x4829, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1145 22:50:08.654134 CH0 RK0: MR19=606, MR18=4829
1146 22:50:08.654188 CH0_RK0: MR19=0x606, MR18=0x4829, DQSOSC=391, MR23=63, INC=96, DEC=64
1147 22:50:08.654242
1148 22:50:08.654294 ----->DramcWriteLeveling(PI) begin...
1149 22:50:08.654348 ==
1150 22:50:08.654402 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 22:50:08.654454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 22:50:08.654508 ==
1153 22:50:08.654560 Write leveling (Byte 0): 33 => 33
1154 22:50:08.654614 Write leveling (Byte 1): 33 => 33
1155 22:50:08.654667 DramcWriteLeveling(PI) end<-----
1156 22:50:08.654720
1157 22:50:08.654773 ==
1158 22:50:08.654826 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 22:50:08.654879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 22:50:08.654932 ==
1161 22:50:08.654985 [Gating] SW mode calibration
1162 22:50:08.655038 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1163 22:50:08.655092 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1164 22:50:08.655146 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1165 22:50:08.655199 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1166 22:50:08.655252 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:50:08.655306 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1168 22:50:08.655359 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:50:08.655412 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:50:08.655466 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:50:08.655519 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:50:08.655572 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:50:08.655625 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:50:08.655678 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:50:08.655730 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:50:08.655784 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:50:08.655837 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:50:08.655891 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:50:08.655943 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:50:08.655996 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:50:08.656049 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1182 22:50:08.656102 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1183 22:50:08.656155 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 22:50:08.656208 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:50:08.656261 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:50:08.656314 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:50:08.656368 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:50:08.656421 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:50:08.656502 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:50:08.656595 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1191 22:50:08.656681 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1192 22:50:08.656767 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 22:50:08.656831 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 22:50:08.656886 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 22:50:08.656940 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 22:50:08.656994 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 22:50:08.657048 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1198 22:50:08.657102 0 10 8 | B1->B0 | 3232 2727 | 1 0 | (1 0) (0 0)
1199 22:50:08.657155 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1200 22:50:08.657209 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:50:08.657263 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 22:50:08.657513 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 22:50:08.657575 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:50:08.657631 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:50:08.657687 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1206 22:50:08.657741 0 11 8 | B1->B0 | 2b2b 3636 | 0 0 | (0 0) (1 1)
1207 22:50:08.657796 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1208 22:50:08.657850 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 22:50:08.657905 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 22:50:08.657958 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 22:50:08.658013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 22:50:08.658067 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 22:50:08.658120 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 22:50:08.658173 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1215 22:50:08.658227 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:50:08.658280 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:50:08.658334 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:50:08.658387 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:50:08.658441 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:50:08.658494 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:50:08.658547 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 22:50:08.658601 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 22:50:08.658654 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 22:50:08.658708 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 22:50:08.658761 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 22:50:08.658814 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 22:50:08.658868 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 22:50:08.658921 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 22:50:08.658973 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 22:50:08.659027 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1231 22:50:08.659080 Total UI for P1: 0, mck2ui 16
1232 22:50:08.659134 best dqsien dly found for B0: ( 0, 14, 6)
1233 22:50:08.659187 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1234 22:50:08.659241 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 22:50:08.659293 Total UI for P1: 0, mck2ui 16
1236 22:50:08.659347 best dqsien dly found for B1: ( 0, 14, 10)
1237 22:50:08.659400 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1238 22:50:08.659453 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1239 22:50:08.659508
1240 22:50:08.659561 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1241 22:50:08.659615 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1242 22:50:08.659669 [Gating] SW calibration Done
1243 22:50:08.659722 ==
1244 22:50:08.659775 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 22:50:08.659829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 22:50:08.659883 ==
1247 22:50:08.659936 RX Vref Scan: 0
1248 22:50:08.659989
1249 22:50:08.660042 RX Vref 0 -> 0, step: 1
1250 22:50:08.660094
1251 22:50:08.660147 RX Delay -130 -> 252, step: 16
1252 22:50:08.660201 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1253 22:50:08.660280 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1254 22:50:08.660373 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1255 22:50:08.660458 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1256 22:50:08.660546 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1257 22:50:08.660610 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1258 22:50:08.660665 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1259 22:50:08.660720 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1260 22:50:08.660774 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1261 22:50:08.660828 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1262 22:50:08.660881 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1263 22:50:08.660935 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1264 22:50:08.660989 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1265 22:50:08.661042 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1266 22:50:08.661096 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1267 22:50:08.661149 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1268 22:50:08.661203 ==
1269 22:50:08.661256 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 22:50:08.661310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 22:50:08.661377 ==
1272 22:50:08.661432 DQS Delay:
1273 22:50:08.661485 DQS0 = 0, DQS1 = 0
1274 22:50:08.661538 DQM Delay:
1275 22:50:08.661591 DQM0 = 83, DQM1 = 76
1276 22:50:08.661645 DQ Delay:
1277 22:50:08.661698 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1278 22:50:08.661752 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1279 22:50:08.661805 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1280 22:50:08.661858 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1281 22:50:08.661911
1282 22:50:08.661965
1283 22:50:08.662018 ==
1284 22:50:08.662071 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 22:50:08.662125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 22:50:08.662179 ==
1287 22:50:08.662233
1288 22:50:08.662285
1289 22:50:08.662338 TX Vref Scan disable
1290 22:50:08.662391 == TX Byte 0 ==
1291 22:50:08.662444 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1292 22:50:08.662498 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1293 22:50:08.662552 == TX Byte 1 ==
1294 22:50:08.662605 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1295 22:50:08.662658 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1296 22:50:08.662711 ==
1297 22:50:08.662763 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 22:50:08.662817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 22:50:08.662870 ==
1300 22:50:08.662922 TX Vref=22, minBit 3, minWin=27, winSum=444
1301 22:50:08.662976 TX Vref=24, minBit 4, minWin=27, winSum=446
1302 22:50:08.663029 TX Vref=26, minBit 0, minWin=28, winSum=450
1303 22:50:08.663081 TX Vref=28, minBit 3, minWin=27, winSum=446
1304 22:50:08.663134 TX Vref=30, minBit 13, minWin=27, winSum=448
1305 22:50:08.663187 TX Vref=32, minBit 9, minWin=27, winSum=445
1306 22:50:08.663240 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 26
1307 22:50:08.663294
1308 22:50:08.663346 Final TX Range 1 Vref 26
1309 22:50:08.663399
1310 22:50:08.663450 ==
1311 22:50:08.663503 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 22:50:08.663556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 22:50:08.663609 ==
1314 22:50:08.663661
1315 22:50:08.663712
1316 22:50:08.663765 TX Vref Scan disable
1317 22:50:08.663818 == TX Byte 0 ==
1318 22:50:08.664065 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1319 22:50:08.664125 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1320 22:50:08.664180 == TX Byte 1 ==
1321 22:50:08.664233 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1322 22:50:08.664286 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1323 22:50:08.664340
1324 22:50:08.664420 [DATLAT]
1325 22:50:08.664485 Freq=800, CH0 RK1
1326 22:50:08.664573
1327 22:50:08.664660 DATLAT Default: 0xa
1328 22:50:08.664746 0, 0xFFFF, sum = 0
1329 22:50:08.664806 1, 0xFFFF, sum = 0
1330 22:50:08.664861 2, 0xFFFF, sum = 0
1331 22:50:08.664917 3, 0xFFFF, sum = 0
1332 22:50:08.664971 4, 0xFFFF, sum = 0
1333 22:50:08.665025 5, 0xFFFF, sum = 0
1334 22:50:08.665079 6, 0xFFFF, sum = 0
1335 22:50:08.665133 7, 0xFFFF, sum = 0
1336 22:50:08.665188 8, 0xFFFF, sum = 0
1337 22:50:08.665242 9, 0x0, sum = 1
1338 22:50:08.665296 10, 0x0, sum = 2
1339 22:50:08.665359 11, 0x0, sum = 3
1340 22:50:08.665414 12, 0x0, sum = 4
1341 22:50:08.665468 best_step = 10
1342 22:50:08.665521
1343 22:50:08.665573 ==
1344 22:50:08.665626 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 22:50:08.665679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 22:50:08.665733 ==
1347 22:50:08.665786 RX Vref Scan: 0
1348 22:50:08.665839
1349 22:50:08.665891 RX Vref 0 -> 0, step: 1
1350 22:50:08.665944
1351 22:50:08.665996 RX Delay -111 -> 252, step: 8
1352 22:50:08.666049 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1353 22:50:08.666102 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1354 22:50:08.666156 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1355 22:50:08.666209 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1356 22:50:08.666262 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1357 22:50:08.666314 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1358 22:50:08.666367 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1359 22:50:08.666420 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1360 22:50:08.666472 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1361 22:50:08.666525 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1362 22:50:08.666578 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1363 22:50:08.666631 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1364 22:50:08.666684 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1365 22:50:08.666736 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1366 22:50:08.666789 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1367 22:50:08.666843 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1368 22:50:08.666896 ==
1369 22:50:08.666949 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 22:50:08.667002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 22:50:08.667056 ==
1372 22:50:08.667109 DQS Delay:
1373 22:50:08.667161 DQS0 = 0, DQS1 = 0
1374 22:50:08.667213 DQM Delay:
1375 22:50:08.667266 DQM0 = 85, DQM1 = 76
1376 22:50:08.667318 DQ Delay:
1377 22:50:08.667372 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1378 22:50:08.667425 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =92
1379 22:50:08.667477 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1380 22:50:08.667530 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1381 22:50:08.667583
1382 22:50:08.667636
1383 22:50:08.667688 [DQSOSCAuto] RK1, (LSB)MR18= 0x4107, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1384 22:50:08.667742 CH0 RK1: MR19=606, MR18=4107
1385 22:50:08.667795 CH0_RK1: MR19=0x606, MR18=0x4107, DQSOSC=393, MR23=63, INC=95, DEC=63
1386 22:50:08.667850 [RxdqsGatingPostProcess] freq 800
1387 22:50:08.667903 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1388 22:50:08.667956 Pre-setting of DQS Precalculation
1389 22:50:08.668009 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1390 22:50:08.668063 ==
1391 22:50:08.668116 Dram Type= 6, Freq= 0, CH_1, rank 0
1392 22:50:08.668168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 22:50:08.668221 ==
1394 22:50:08.668273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 22:50:08.668327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 22:50:08.668380 [CA 0] Center 36 (6~67) winsize 62
1397 22:50:08.668433 [CA 1] Center 36 (6~67) winsize 62
1398 22:50:08.668486 [CA 2] Center 34 (4~65) winsize 62
1399 22:50:08.668539 [CA 3] Center 34 (3~65) winsize 63
1400 22:50:08.668591 [CA 4] Center 34 (4~65) winsize 62
1401 22:50:08.668671 [CA 5] Center 34 (3~65) winsize 63
1402 22:50:08.668741
1403 22:50:08.668826 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1404 22:50:08.668914
1405 22:50:08.668995 [CATrainingPosCal] consider 1 rank data
1406 22:50:08.669053 u2DelayCellTimex100 = 270/100 ps
1407 22:50:08.669108 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1408 22:50:08.669161 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1409 22:50:08.669215 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 22:50:08.669268 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1411 22:50:08.669321 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 22:50:08.669385 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1413 22:50:08.669438
1414 22:50:08.669491 CA PerBit enable=1, Macro0, CA PI delay=34
1415 22:50:08.669545
1416 22:50:08.669599 [CBTSetCACLKResult] CA Dly = 34
1417 22:50:08.669652 CS Dly: 4 (0~35)
1418 22:50:08.669705 ==
1419 22:50:08.669758 Dram Type= 6, Freq= 0, CH_1, rank 1
1420 22:50:08.669813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 22:50:08.669891 ==
1422 22:50:08.669947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 22:50:08.670001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 22:50:08.670055 [CA 0] Center 36 (6~67) winsize 62
1425 22:50:08.670108 [CA 1] Center 36 (6~67) winsize 62
1426 22:50:08.670160 [CA 2] Center 34 (4~65) winsize 62
1427 22:50:08.670213 [CA 3] Center 34 (3~65) winsize 63
1428 22:50:08.670266 [CA 4] Center 34 (4~65) winsize 62
1429 22:50:08.670318 [CA 5] Center 34 (3~65) winsize 63
1430 22:50:08.670371
1431 22:50:08.670423 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1432 22:50:08.670476
1433 22:50:08.670528 [CATrainingPosCal] consider 2 rank data
1434 22:50:08.670581 u2DelayCellTimex100 = 270/100 ps
1435 22:50:08.670633 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 22:50:08.670686 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1437 22:50:08.670738 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 22:50:08.670791 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1439 22:50:08.670844 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1440 22:50:08.670896 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1441 22:50:08.670949
1442 22:50:08.671001 CA PerBit enable=1, Macro0, CA PI delay=34
1443 22:50:08.671054
1444 22:50:08.671107 [CBTSetCACLKResult] CA Dly = 34
1445 22:50:08.671158 CS Dly: 5 (0~38)
1446 22:50:08.671211
1447 22:50:08.671263 ----->DramcWriteLeveling(PI) begin...
1448 22:50:08.671317 ==
1449 22:50:08.671369 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 22:50:08.671622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 22:50:08.671686 ==
1452 22:50:08.671741 Write leveling (Byte 0): 29 => 29
1453 22:50:08.671795 Write leveling (Byte 1): 29 => 29
1454 22:50:08.671848 DramcWriteLeveling(PI) end<-----
1455 22:50:08.671902
1456 22:50:08.671956 ==
1457 22:50:08.672008 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 22:50:08.672062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 22:50:08.672116 ==
1460 22:50:08.672168 [Gating] SW mode calibration
1461 22:50:08.672221 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1462 22:50:08.672275 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1463 22:50:08.672329 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1464 22:50:08.672382 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1465 22:50:08.672435 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:50:08.672508 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:50:08.672598 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:50:08.672683 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:50:08.672768 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:50:08.672836 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:50:08.672892 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:50:08.672945 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:50:08.672999 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:50:08.673052 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:50:08.673105 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:50:08.673158 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:50:08.673211 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:50:08.673264 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:50:08.673316 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1480 22:50:08.673380 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1481 22:50:08.673434 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:50:08.673487 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:50:08.673540 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:50:08.673593 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:50:08.673646 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:50:08.673699 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:50:08.673751 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:50:08.673804 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1489 22:50:08.673857 0 9 8 | B1->B0 | 2e2e 2f2f | 1 0 | (0 0) (0 0)
1490 22:50:08.673911 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 22:50:08.673964 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 22:50:08.674017 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 22:50:08.674070 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 22:50:08.674122 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 22:50:08.674175 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 22:50:08.674227 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 1)
1497 22:50:08.674280 0 10 8 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1498 22:50:08.674332 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:50:08.674385 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 22:50:08.674438 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 22:50:08.674491 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:50:08.674544 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 22:50:08.674596 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 22:50:08.674649 0 11 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1505 22:50:08.674701 0 11 8 | B1->B0 | 3b3b 3c3c | 0 0 | (0 0) (0 0)
1506 22:50:08.674753 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 22:50:08.674806 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 22:50:08.674858 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 22:50:08.674910 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 22:50:08.674963 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 22:50:08.675015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 22:50:08.675068 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1513 22:50:08.675119 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1514 22:50:08.675172 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:50:08.675225 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:50:08.675277 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:50:08.675330 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:50:08.675382 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:50:08.675434 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 22:50:08.675487 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 22:50:08.675540 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 22:50:08.675592 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 22:50:08.675645 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 22:50:08.675698 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 22:50:08.675750 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 22:50:08.675802 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 22:50:08.675854 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 22:50:08.675907 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1529 22:50:08.675959 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 22:50:08.676012 Total UI for P1: 0, mck2ui 16
1531 22:50:08.676065 best dqsien dly found for B0: ( 0, 14, 4)
1532 22:50:08.676118 Total UI for P1: 0, mck2ui 16
1533 22:50:08.676171 best dqsien dly found for B1: ( 0, 14, 4)
1534 22:50:08.676234 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1535 22:50:08.676311 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1536 22:50:08.676396
1537 22:50:08.676483 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1538 22:50:08.676761 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1539 22:50:08.676825 [Gating] SW calibration Done
1540 22:50:08.676882 ==
1541 22:50:08.676937 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 22:50:08.676992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 22:50:08.677046 ==
1544 22:50:08.677100 RX Vref Scan: 0
1545 22:50:08.677153
1546 22:50:08.677206 RX Vref 0 -> 0, step: 1
1547 22:50:08.677260
1548 22:50:08.677312 RX Delay -130 -> 252, step: 16
1549 22:50:08.677376 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1550 22:50:08.677430 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1551 22:50:08.677484 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1552 22:50:08.677537 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1553 22:50:08.677590 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1554 22:50:08.677643 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1555 22:50:08.677696 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1556 22:50:08.677749 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1557 22:50:08.677802 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1558 22:50:08.677855 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1559 22:50:08.677907 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1560 22:50:08.677962 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1561 22:50:08.678014 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1562 22:50:08.678067 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1563 22:50:08.678119 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1564 22:50:08.678172 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1565 22:50:08.678224 ==
1566 22:50:08.678277 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 22:50:08.678331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 22:50:08.678384 ==
1569 22:50:08.678436 DQS Delay:
1570 22:50:08.678489 DQS0 = 0, DQS1 = 0
1571 22:50:08.678542 DQM Delay:
1572 22:50:08.678594 DQM0 = 89, DQM1 = 78
1573 22:50:08.678647 DQ Delay:
1574 22:50:08.678699 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1575 22:50:08.678751 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1576 22:50:08.678803 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1577 22:50:08.678856 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1578 22:50:08.678909
1579 22:50:08.678961
1580 22:50:08.679012 ==
1581 22:50:08.679065 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 22:50:08.679118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 22:50:08.679171 ==
1584 22:50:08.679223
1585 22:50:08.679275
1586 22:50:08.679328 TX Vref Scan disable
1587 22:50:08.679380 == TX Byte 0 ==
1588 22:50:08.679433 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1589 22:50:08.679486 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1590 22:50:08.679539 == TX Byte 1 ==
1591 22:50:08.679592 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1592 22:50:08.679645 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1593 22:50:08.679698 ==
1594 22:50:08.679751 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 22:50:08.679804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 22:50:08.679857 ==
1597 22:50:08.679909 TX Vref=22, minBit 15, minWin=26, winSum=442
1598 22:50:08.679963 TX Vref=24, minBit 10, minWin=26, winSum=446
1599 22:50:08.680016 TX Vref=26, minBit 8, minWin=27, winSum=445
1600 22:50:08.680068 TX Vref=28, minBit 9, minWin=27, winSum=453
1601 22:50:08.680122 TX Vref=30, minBit 9, minWin=27, winSum=449
1602 22:50:08.680176 TX Vref=32, minBit 8, minWin=27, winSum=447
1603 22:50:08.680229 [TxChooseVref] Worse bit 9, Min win 27, Win sum 453, Final Vref 28
1604 22:50:08.680282
1605 22:50:08.680334 Final TX Range 1 Vref 28
1606 22:50:08.680387
1607 22:50:08.680448 ==
1608 22:50:08.680523 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 22:50:08.680611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 22:50:08.680699 ==
1611 22:50:08.680784
1612 22:50:08.680843
1613 22:50:08.680896 TX Vref Scan disable
1614 22:50:08.680950 == TX Byte 0 ==
1615 22:50:08.681003 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1616 22:50:08.681057 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1617 22:50:08.681110 == TX Byte 1 ==
1618 22:50:08.681163 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1619 22:50:08.681216 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1620 22:50:08.681269
1621 22:50:08.681321 [DATLAT]
1622 22:50:08.681379 Freq=800, CH1 RK0
1623 22:50:08.681432
1624 22:50:08.681484 DATLAT Default: 0xa
1625 22:50:08.681537 0, 0xFFFF, sum = 0
1626 22:50:08.681592 1, 0xFFFF, sum = 0
1627 22:50:08.681646 2, 0xFFFF, sum = 0
1628 22:50:08.681700 3, 0xFFFF, sum = 0
1629 22:50:08.681754 4, 0xFFFF, sum = 0
1630 22:50:08.681807 5, 0xFFFF, sum = 0
1631 22:50:08.681861 6, 0xFFFF, sum = 0
1632 22:50:08.681914 7, 0xFFFF, sum = 0
1633 22:50:08.681968 8, 0xFFFF, sum = 0
1634 22:50:08.682021 9, 0x0, sum = 1
1635 22:50:08.682075 10, 0x0, sum = 2
1636 22:50:08.682128 11, 0x0, sum = 3
1637 22:50:08.682183 12, 0x0, sum = 4
1638 22:50:08.682236 best_step = 10
1639 22:50:08.682288
1640 22:50:08.682340 ==
1641 22:50:08.682393 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 22:50:08.682446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 22:50:08.682499 ==
1644 22:50:08.682551 RX Vref Scan: 1
1645 22:50:08.682605
1646 22:50:08.682658 Set Vref Range= 32 -> 127
1647 22:50:08.682710
1648 22:50:08.682762 RX Vref 32 -> 127, step: 1
1649 22:50:08.682814
1650 22:50:08.682867 RX Delay -95 -> 252, step: 8
1651 22:50:08.682919
1652 22:50:08.682972 Set Vref, RX VrefLevel [Byte0]: 32
1653 22:50:08.683024 [Byte1]: 32
1654 22:50:08.683077
1655 22:50:08.683129 Set Vref, RX VrefLevel [Byte0]: 33
1656 22:50:08.683182 [Byte1]: 33
1657 22:50:08.683234
1658 22:50:08.683286 Set Vref, RX VrefLevel [Byte0]: 34
1659 22:50:08.683338 [Byte1]: 34
1660 22:50:08.683391
1661 22:50:08.683443 Set Vref, RX VrefLevel [Byte0]: 35
1662 22:50:08.683495 [Byte1]: 35
1663 22:50:08.683547
1664 22:50:08.683599 Set Vref, RX VrefLevel [Byte0]: 36
1665 22:50:08.683652 [Byte1]: 36
1666 22:50:08.683704
1667 22:50:08.683756 Set Vref, RX VrefLevel [Byte0]: 37
1668 22:50:08.683809 [Byte1]: 37
1669 22:50:08.683861
1670 22:50:08.683914 Set Vref, RX VrefLevel [Byte0]: 38
1671 22:50:08.683966 [Byte1]: 38
1672 22:50:08.684019
1673 22:50:08.684071 Set Vref, RX VrefLevel [Byte0]: 39
1674 22:50:08.684123 [Byte1]: 39
1675 22:50:08.684175
1676 22:50:08.684226 Set Vref, RX VrefLevel [Byte0]: 40
1677 22:50:08.684279 [Byte1]: 40
1678 22:50:08.684332
1679 22:50:08.684383 Set Vref, RX VrefLevel [Byte0]: 41
1680 22:50:08.684436 [Byte1]: 41
1681 22:50:08.684489
1682 22:50:08.684540 Set Vref, RX VrefLevel [Byte0]: 42
1683 22:50:08.684593 [Byte1]: 42
1684 22:50:08.684645
1685 22:50:08.684713 Set Vref, RX VrefLevel [Byte0]: 43
1686 22:50:08.684787 [Byte1]: 43
1687 22:50:08.684872
1688 22:50:08.684961 Set Vref, RX VrefLevel [Byte0]: 44
1689 22:50:08.685044 [Byte1]: 44
1690 22:50:08.685102
1691 22:50:08.685156 Set Vref, RX VrefLevel [Byte0]: 45
1692 22:50:08.685209 [Byte1]: 45
1693 22:50:08.685262
1694 22:50:08.685510 Set Vref, RX VrefLevel [Byte0]: 46
1695 22:50:08.685571 [Byte1]: 46
1696 22:50:08.685627
1697 22:50:08.685680 Set Vref, RX VrefLevel [Byte0]: 47
1698 22:50:08.685734 [Byte1]: 47
1699 22:50:08.685787
1700 22:50:08.685840 Set Vref, RX VrefLevel [Byte0]: 48
1701 22:50:08.685894 [Byte1]: 48
1702 22:50:08.685946
1703 22:50:08.685999 Set Vref, RX VrefLevel [Byte0]: 49
1704 22:50:08.686052 [Byte1]: 49
1705 22:50:08.686105
1706 22:50:08.686156 Set Vref, RX VrefLevel [Byte0]: 50
1707 22:50:08.686209 [Byte1]: 50
1708 22:50:08.686261
1709 22:50:08.686313 Set Vref, RX VrefLevel [Byte0]: 51
1710 22:50:08.686366 [Byte1]: 51
1711 22:50:08.686419
1712 22:50:08.686471 Set Vref, RX VrefLevel [Byte0]: 52
1713 22:50:08.686524 [Byte1]: 52
1714 22:50:08.686577
1715 22:50:08.686628 Set Vref, RX VrefLevel [Byte0]: 53
1716 22:50:08.686681 [Byte1]: 53
1717 22:50:08.686734
1718 22:50:08.686787 Set Vref, RX VrefLevel [Byte0]: 54
1719 22:50:08.686839 [Byte1]: 54
1720 22:50:08.686892
1721 22:50:08.686944 Set Vref, RX VrefLevel [Byte0]: 55
1722 22:50:08.686996 [Byte1]: 55
1723 22:50:08.687049
1724 22:50:08.687101 Set Vref, RX VrefLevel [Byte0]: 56
1725 22:50:08.687153 [Byte1]: 56
1726 22:50:08.687206
1727 22:50:08.687259 Set Vref, RX VrefLevel [Byte0]: 57
1728 22:50:08.687311 [Byte1]: 57
1729 22:50:08.687363
1730 22:50:08.687415 Set Vref, RX VrefLevel [Byte0]: 58
1731 22:50:08.687468 [Byte1]: 58
1732 22:50:08.687521
1733 22:50:08.687573 Set Vref, RX VrefLevel [Byte0]: 59
1734 22:50:08.687626 [Byte1]: 59
1735 22:50:08.687679
1736 22:50:08.687732 Set Vref, RX VrefLevel [Byte0]: 60
1737 22:50:08.687784 [Byte1]: 60
1738 22:50:08.687837
1739 22:50:08.687889 Set Vref, RX VrefLevel [Byte0]: 61
1740 22:50:08.687941 [Byte1]: 61
1741 22:50:08.687994
1742 22:50:08.688046 Set Vref, RX VrefLevel [Byte0]: 62
1743 22:50:08.688099 [Byte1]: 62
1744 22:50:08.688151
1745 22:50:08.688203 Set Vref, RX VrefLevel [Byte0]: 63
1746 22:50:08.688255 [Byte1]: 63
1747 22:50:08.688307
1748 22:50:08.688359 Set Vref, RX VrefLevel [Byte0]: 64
1749 22:50:08.688411 [Byte1]: 64
1750 22:50:08.688479
1751 22:50:08.688550 Set Vref, RX VrefLevel [Byte0]: 65
1752 22:50:08.688636 [Byte1]: 65
1753 22:50:08.688723
1754 22:50:08.688807 Set Vref, RX VrefLevel [Byte0]: 66
1755 22:50:08.688865 [Byte1]: 66
1756 22:50:08.688919
1757 22:50:08.688972 Set Vref, RX VrefLevel [Byte0]: 67
1758 22:50:08.689025 [Byte1]: 67
1759 22:50:08.689079
1760 22:50:08.689131 Set Vref, RX VrefLevel [Byte0]: 68
1761 22:50:08.689183 [Byte1]: 68
1762 22:50:08.689236
1763 22:50:08.689288 Set Vref, RX VrefLevel [Byte0]: 69
1764 22:50:08.689350 [Byte1]: 69
1765 22:50:08.689404
1766 22:50:08.689456 Set Vref, RX VrefLevel [Byte0]: 70
1767 22:50:08.689509 [Byte1]: 70
1768 22:50:08.689562
1769 22:50:08.689614 Set Vref, RX VrefLevel [Byte0]: 71
1770 22:50:08.689667 [Byte1]: 71
1771 22:50:08.689719
1772 22:50:08.689772 Set Vref, RX VrefLevel [Byte0]: 72
1773 22:50:08.689825 [Byte1]: 72
1774 22:50:08.689878
1775 22:50:08.689929 Set Vref, RX VrefLevel [Byte0]: 73
1776 22:50:08.689982 [Byte1]: 73
1777 22:50:08.690035
1778 22:50:08.690087 Set Vref, RX VrefLevel [Byte0]: 74
1779 22:50:08.690139 [Byte1]: 74
1780 22:50:08.690191
1781 22:50:08.690243 Set Vref, RX VrefLevel [Byte0]: 75
1782 22:50:08.690295 [Byte1]: 75
1783 22:50:08.690347
1784 22:50:08.690399 Set Vref, RX VrefLevel [Byte0]: 76
1785 22:50:08.690452 [Byte1]: 76
1786 22:50:08.690505
1787 22:50:08.690557 Final RX Vref Byte 0 = 52 to rank0
1788 22:50:08.690609 Final RX Vref Byte 1 = 66 to rank0
1789 22:50:08.690662 Final RX Vref Byte 0 = 52 to rank1
1790 22:50:08.690715 Final RX Vref Byte 1 = 66 to rank1==
1791 22:50:08.690767 Dram Type= 6, Freq= 0, CH_1, rank 0
1792 22:50:08.690820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 22:50:08.690873 ==
1794 22:50:08.690925 DQS Delay:
1795 22:50:08.690977 DQS0 = 0, DQS1 = 0
1796 22:50:08.691030 DQM Delay:
1797 22:50:08.691082 DQM0 = 86, DQM1 = 78
1798 22:50:08.691134 DQ Delay:
1799 22:50:08.691186 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1800 22:50:08.691239 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1801 22:50:08.691291 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1802 22:50:08.691343 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1803 22:50:08.691395
1804 22:50:08.691447
1805 22:50:08.691499 [DQSOSCAuto] RK0, (LSB)MR18= 0x3622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1806 22:50:08.691553 CH1 RK0: MR19=606, MR18=3622
1807 22:50:08.691605 CH1_RK0: MR19=0x606, MR18=0x3622, DQSOSC=396, MR23=63, INC=94, DEC=62
1808 22:50:08.691659
1809 22:50:08.691712 ----->DramcWriteLeveling(PI) begin...
1810 22:50:08.691765 ==
1811 22:50:08.691818 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 22:50:08.691871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 22:50:08.691925 ==
1814 22:50:08.691978 Write leveling (Byte 0): 28 => 28
1815 22:50:08.692031 Write leveling (Byte 1): 29 => 29
1816 22:50:08.692084 DramcWriteLeveling(PI) end<-----
1817 22:50:08.692136
1818 22:50:08.692188 ==
1819 22:50:08.692240 Dram Type= 6, Freq= 0, CH_1, rank 1
1820 22:50:08.692292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1821 22:50:08.692345 ==
1822 22:50:08.692398 [Gating] SW mode calibration
1823 22:50:08.692480 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1824 22:50:08.692571 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1825 22:50:08.692657 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1826 22:50:08.692743 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1827 22:50:08.692809 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1828 22:50:08.692865 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:50:08.692918 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:50:08.692972 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:50:08.693025 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:50:08.693078 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:50:08.693131 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:50:08.693183 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:50:08.693235 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:50:08.693482 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:50:08.693543 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:50:08.693598 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:50:08.693651 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:50:08.693704 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:50:08.693757 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1842 22:50:08.693810 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1843 22:50:08.693863 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1844 22:50:08.693917 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 22:50:08.693970 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 22:50:08.694023 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 22:50:08.694076 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 22:50:08.694129 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 22:50:08.694183 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:50:08.694236 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:50:08.694289 0 9 8 | B1->B0 | 3131 2626 | 1 0 | (1 1) (0 0)
1852 22:50:08.694355 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 22:50:08.694430 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 22:50:08.694485 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 22:50:08.694538 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 22:50:08.694591 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 22:50:08.694644 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 22:50:08.694697 0 10 4 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
1859 22:50:08.694750 0 10 8 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
1860 22:50:08.694802 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 22:50:08.694855 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 22:50:08.694908 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 22:50:08.694960 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 22:50:08.695012 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 22:50:08.695065 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 22:50:08.695118 0 11 4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1867 22:50:08.695171 0 11 8 | B1->B0 | 4141 3535 | 0 0 | (0 0) (0 0)
1868 22:50:08.695223 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 22:50:08.695275 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 22:50:08.695327 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 22:50:08.695380 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 22:50:08.695433 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 22:50:08.695485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 22:50:08.695538 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1875 22:50:08.695590 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:50:08.695643 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:50:08.695696 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:50:08.695749 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:50:08.695801 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:50:08.695853 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 22:50:08.695905 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 22:50:08.695959 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 22:50:08.696011 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 22:50:08.696063 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 22:50:08.696116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 22:50:08.696169 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 22:50:08.696222 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 22:50:08.696274 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 22:50:08.696327 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 22:50:08.696379 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1891 22:50:08.696432 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1892 22:50:08.696484 Total UI for P1: 0, mck2ui 16
1893 22:50:08.696538 best dqsien dly found for B1: ( 0, 14, 4)
1894 22:50:08.696591 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 22:50:08.696643 Total UI for P1: 0, mck2ui 16
1896 22:50:08.696697 best dqsien dly found for B0: ( 0, 14, 6)
1897 22:50:08.696750 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1898 22:50:08.696803 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1899 22:50:08.696855
1900 22:50:08.696912 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1901 22:50:08.696989 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1902 22:50:08.697079 [Gating] SW calibration Done
1903 22:50:08.697165 ==
1904 22:50:08.697251 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 22:50:08.697349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1906 22:50:08.697408 ==
1907 22:50:08.697463 RX Vref Scan: 0
1908 22:50:08.697516
1909 22:50:08.697570 RX Vref 0 -> 0, step: 1
1910 22:50:08.697623
1911 22:50:08.697676 RX Delay -130 -> 252, step: 16
1912 22:50:08.697729 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1913 22:50:08.697782 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1914 22:50:08.697835 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1915 22:50:08.697887 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1916 22:50:08.697940 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1917 22:50:08.697993 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1918 22:50:08.698047 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1919 22:50:08.849524 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1920 22:50:08.849657 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1921 22:50:08.849723 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1922 22:50:08.849783 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1923 22:50:08.849841 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1924 22:50:08.849897 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1925 22:50:08.849951 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1926 22:50:08.850006 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1927 22:50:08.850282 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1928 22:50:08.850362 ==
1929 22:50:08.850420 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 22:50:08.850477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 22:50:08.850551 ==
1932 22:50:08.850606 DQS Delay:
1933 22:50:08.850661 DQS0 = 0, DQS1 = 0
1934 22:50:08.850716 DQM Delay:
1935 22:50:08.850784 DQM0 = 86, DQM1 = 78
1936 22:50:08.850837 DQ Delay:
1937 22:50:08.850890 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =77
1938 22:50:08.850943 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1939 22:50:08.850996 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1940 22:50:08.851063 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1941 22:50:08.851116
1942 22:50:08.851168
1943 22:50:08.851251 ==
1944 22:50:08.851319 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 22:50:08.851388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 22:50:08.851456 ==
1947 22:50:08.851526
1948 22:50:08.851578
1949 22:50:08.851662 TX Vref Scan disable
1950 22:50:08.851715 == TX Byte 0 ==
1951 22:50:08.851768 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1952 22:50:08.851821 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1953 22:50:08.851874 == TX Byte 1 ==
1954 22:50:08.851927 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1955 22:50:08.851979 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1956 22:50:08.852047 ==
1957 22:50:08.852118 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 22:50:08.852174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 22:50:08.852240 ==
1960 22:50:08.852304 TX Vref=22, minBit 9, minWin=26, winSum=446
1961 22:50:08.852360 TX Vref=24, minBit 9, minWin=27, winSum=449
1962 22:50:08.852414 TX Vref=26, minBit 8, minWin=27, winSum=450
1963 22:50:08.852468 TX Vref=28, minBit 8, minWin=27, winSum=450
1964 22:50:08.852521 TX Vref=30, minBit 8, minWin=27, winSum=448
1965 22:50:08.852574 TX Vref=32, minBit 8, minWin=27, winSum=448
1966 22:50:08.852627 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 26
1967 22:50:08.852681
1968 22:50:08.852733 Final TX Range 1 Vref 26
1969 22:50:08.852787
1970 22:50:08.852838 ==
1971 22:50:08.852905 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 22:50:08.852957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 22:50:08.853010 ==
1974 22:50:08.853062
1975 22:50:08.853113
1976 22:50:08.853164 TX Vref Scan disable
1977 22:50:08.853216 == TX Byte 0 ==
1978 22:50:08.853268 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1979 22:50:08.853319 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1980 22:50:08.853418 == TX Byte 1 ==
1981 22:50:08.853471 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1982 22:50:08.853524 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1983 22:50:08.853575
1984 22:50:08.853626 [DATLAT]
1985 22:50:08.853688 Freq=800, CH1 RK1
1986 22:50:08.853760
1987 22:50:08.853843 DATLAT Default: 0xa
1988 22:50:08.853925 0, 0xFFFF, sum = 0
1989 22:50:08.854010 1, 0xFFFF, sum = 0
1990 22:50:08.854091 2, 0xFFFF, sum = 0
1991 22:50:08.854148 3, 0xFFFF, sum = 0
1992 22:50:08.854204 4, 0xFFFF, sum = 0
1993 22:50:08.854258 5, 0xFFFF, sum = 0
1994 22:50:08.854312 6, 0xFFFF, sum = 0
1995 22:50:08.854365 7, 0xFFFF, sum = 0
1996 22:50:08.854418 8, 0xFFFF, sum = 0
1997 22:50:08.854471 9, 0x0, sum = 1
1998 22:50:08.854525 10, 0x0, sum = 2
1999 22:50:08.854579 11, 0x0, sum = 3
2000 22:50:08.854632 12, 0x0, sum = 4
2001 22:50:08.854717 best_step = 10
2002 22:50:08.854769
2003 22:50:08.854821 ==
2004 22:50:08.854873 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 22:50:08.854925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 22:50:08.854978 ==
2007 22:50:08.855031 RX Vref Scan: 0
2008 22:50:08.855082
2009 22:50:08.855156 RX Vref 0 -> 0, step: 1
2010 22:50:08.855221
2011 22:50:08.855272 RX Delay -95 -> 252, step: 8
2012 22:50:08.855324 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2013 22:50:08.855376 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2014 22:50:08.855428 iDelay=217, Bit 2, Center 76 (-31 ~ 184) 216
2015 22:50:08.855480 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2016 22:50:08.855532 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2017 22:50:08.855584 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2018 22:50:08.855636 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2019 22:50:08.855690 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2020 22:50:08.855764 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2021 22:50:08.855818 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2022 22:50:08.855887 iDelay=217, Bit 10, Center 80 (-31 ~ 192) 224
2023 22:50:08.855953 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2024 22:50:08.856023 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2025 22:50:08.856076 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2026 22:50:08.856134 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2027 22:50:08.856189 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
2028 22:50:08.856241 ==
2029 22:50:08.856325 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 22:50:08.856393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 22:50:08.856446 ==
2032 22:50:08.856497 DQS Delay:
2033 22:50:08.856549 DQS0 = 0, DQS1 = 0
2034 22:50:08.856609 DQM Delay:
2035 22:50:08.856718 DQM0 = 86, DQM1 = 78
2036 22:50:08.856784 DQ Delay:
2037 22:50:08.856869 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
2038 22:50:08.856949 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2039 22:50:08.857026 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2040 22:50:08.857101 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =84
2041 22:50:08.857175
2042 22:50:08.857256
2043 22:50:08.857369 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
2044 22:50:08.857444 CH1 RK1: MR19=606, MR18=1B14
2045 22:50:08.857498 CH1_RK1: MR19=0x606, MR18=0x1B14, DQSOSC=403, MR23=63, INC=90, DEC=60
2046 22:50:08.857553 [RxdqsGatingPostProcess] freq 800
2047 22:50:08.857606 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2048 22:50:08.857659 Pre-setting of DQS Precalculation
2049 22:50:08.857712 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2050 22:50:08.857806 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2051 22:50:08.857921 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2052 22:50:08.858004
2053 22:50:08.858080
2054 22:50:08.858185 [Calibration Summary] 1600 Mbps
2055 22:50:08.858261 CH 0, Rank 0
2056 22:50:08.858337 SW Impedance : PASS
2057 22:50:08.858424 DUTY Scan : NO K
2058 22:50:08.858508 ZQ Calibration : PASS
2059 22:50:08.858567 Jitter Meter : NO K
2060 22:50:08.858622 CBT Training : PASS
2061 22:50:08.858699 Write leveling : PASS
2062 22:50:08.858788 RX DQS gating : PASS
2063 22:50:08.858902 RX DQ/DQS(RDDQC) : PASS
2064 22:50:08.859016 TX DQ/DQS : PASS
2065 22:50:08.859100 RX DATLAT : PASS
2066 22:50:08.859183 RX DQ/DQS(Engine): PASS
2067 22:50:08.859265 TX OE : NO K
2068 22:50:08.859347 All Pass.
2069 22:50:08.859428
2070 22:50:08.859509 CH 0, Rank 1
2071 22:50:08.859591 SW Impedance : PASS
2072 22:50:08.859672 DUTY Scan : NO K
2073 22:50:08.859963 ZQ Calibration : PASS
2074 22:50:08.860082 Jitter Meter : NO K
2075 22:50:08.860189 CBT Training : PASS
2076 22:50:08.860283 Write leveling : PASS
2077 22:50:08.860373 RX DQS gating : PASS
2078 22:50:08.860470 RX DQ/DQS(RDDQC) : PASS
2079 22:50:08.860552 TX DQ/DQS : PASS
2080 22:50:08.860634 RX DATLAT : PASS
2081 22:50:08.860715 RX DQ/DQS(Engine): PASS
2082 22:50:08.860796 TX OE : NO K
2083 22:50:08.860877 All Pass.
2084 22:50:08.860957
2085 22:50:08.861039 CH 1, Rank 0
2086 22:50:08.861120 SW Impedance : PASS
2087 22:50:08.861202 DUTY Scan : NO K
2088 22:50:08.861283 ZQ Calibration : PASS
2089 22:50:08.861397 Jitter Meter : NO K
2090 22:50:08.861452 CBT Training : PASS
2091 22:50:08.861505 Write leveling : PASS
2092 22:50:08.861561 RX DQS gating : PASS
2093 22:50:08.861619 RX DQ/DQS(RDDQC) : PASS
2094 22:50:08.861672 TX DQ/DQS : PASS
2095 22:50:08.861725 RX DATLAT : PASS
2096 22:50:08.861778 RX DQ/DQS(Engine): PASS
2097 22:50:08.861858 TX OE : NO K
2098 22:50:08.861933 All Pass.
2099 22:50:08.862001
2100 22:50:08.862053 CH 1, Rank 1
2101 22:50:08.862106 SW Impedance : PASS
2102 22:50:08.862232 DUTY Scan : NO K
2103 22:50:08.862293 ZQ Calibration : PASS
2104 22:50:08.862345 Jitter Meter : NO K
2105 22:50:08.862397 CBT Training : PASS
2106 22:50:08.862450 Write leveling : PASS
2107 22:50:08.862502 RX DQS gating : PASS
2108 22:50:08.862554 RX DQ/DQS(RDDQC) : PASS
2109 22:50:08.862606 TX DQ/DQS : PASS
2110 22:50:08.862659 RX DATLAT : PASS
2111 22:50:08.862710 RX DQ/DQS(Engine): PASS
2112 22:50:08.862762 TX OE : NO K
2113 22:50:08.862814 All Pass.
2114 22:50:08.862865
2115 22:50:08.862916 DramC Write-DBI off
2116 22:50:08.862969 PER_BANK_REFRESH: Hybrid Mode
2117 22:50:08.863021 TX_TRACKING: ON
2118 22:50:08.863074 [GetDramInforAfterCalByMRR] Vendor 6.
2119 22:50:08.863126 [GetDramInforAfterCalByMRR] Revision 606.
2120 22:50:08.863178 [GetDramInforAfterCalByMRR] Revision 2 0.
2121 22:50:08.863230 MR0 0x3b3b
2122 22:50:08.863282 MR8 0x5151
2123 22:50:08.863334 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 22:50:08.863386
2125 22:50:08.863438 MR0 0x3b3b
2126 22:50:08.863488 MR8 0x5151
2127 22:50:08.863540 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2128 22:50:08.863592
2129 22:50:08.863644 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2130 22:50:08.863698 [FAST_K] Save calibration result to emmc
2131 22:50:08.863750 [FAST_K] Save calibration result to emmc
2132 22:50:08.863803 dram_init: config_dvfs: 1
2133 22:50:08.863854 dramc_set_vcore_voltage set vcore to 662500
2134 22:50:08.863907 Read voltage for 1200, 2
2135 22:50:08.863959 Vio18 = 0
2136 22:50:08.864011 Vcore = 662500
2137 22:50:08.864063 Vdram = 0
2138 22:50:08.864139 Vddq = 0
2139 22:50:08.864204 Vmddr = 0
2140 22:50:08.864256 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2141 22:50:08.864310 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2142 22:50:08.864363 MEM_TYPE=3, freq_sel=15
2143 22:50:08.864414 sv_algorithm_assistance_LP4_1600
2144 22:50:08.864466 ============ PULL DRAM RESETB DOWN ============
2145 22:50:08.864519 ========== PULL DRAM RESETB DOWN end =========
2146 22:50:08.864572 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2147 22:50:08.864625 ===================================
2148 22:50:08.864677 LPDDR4 DRAM CONFIGURATION
2149 22:50:08.864729 ===================================
2150 22:50:08.864781 EX_ROW_EN[0] = 0x0
2151 22:50:08.864833 EX_ROW_EN[1] = 0x0
2152 22:50:08.864884 LP4Y_EN = 0x0
2153 22:50:08.864936 WORK_FSP = 0x0
2154 22:50:08.864987 WL = 0x4
2155 22:50:08.865039 RL = 0x4
2156 22:50:08.865090 BL = 0x2
2157 22:50:08.865142 RPST = 0x0
2158 22:50:08.865193 RD_PRE = 0x0
2159 22:50:08.865245 WR_PRE = 0x1
2160 22:50:08.865297 WR_PST = 0x0
2161 22:50:08.865400 DBI_WR = 0x0
2162 22:50:08.865454 DBI_RD = 0x0
2163 22:50:08.865506 OTF = 0x1
2164 22:50:08.865559 ===================================
2165 22:50:08.865612 ===================================
2166 22:50:08.865664 ANA top config
2167 22:50:08.865749 ===================================
2168 22:50:08.865811 DLL_ASYNC_EN = 0
2169 22:50:08.865883 ALL_SLAVE_EN = 0
2170 22:50:08.865936 NEW_RANK_MODE = 1
2171 22:50:08.865990 DLL_IDLE_MODE = 1
2172 22:50:08.866043 LP45_APHY_COMB_EN = 1
2173 22:50:08.866095 TX_ODT_DIS = 1
2174 22:50:08.866162 NEW_8X_MODE = 1
2175 22:50:08.866235 ===================================
2176 22:50:08.866327 ===================================
2177 22:50:08.866398 data_rate = 2400
2178 22:50:08.866456 CKR = 1
2179 22:50:08.866509 DQ_P2S_RATIO = 8
2180 22:50:08.866562 ===================================
2181 22:50:08.866627 CA_P2S_RATIO = 8
2182 22:50:08.866683 DQ_CA_OPEN = 0
2183 22:50:08.866735 DQ_SEMI_OPEN = 0
2184 22:50:08.866787 CA_SEMI_OPEN = 0
2185 22:50:08.866839 CA_FULL_RATE = 0
2186 22:50:08.866905 DQ_CKDIV4_EN = 0
2187 22:50:08.866961 CA_CKDIV4_EN = 0
2188 22:50:08.867013 CA_PREDIV_EN = 0
2189 22:50:08.867066 PH8_DLY = 17
2190 22:50:08.867122 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2191 22:50:08.867184 DQ_AAMCK_DIV = 4
2192 22:50:08.867237 CA_AAMCK_DIV = 4
2193 22:50:08.867290 CA_ADMCK_DIV = 4
2194 22:50:08.867342 DQ_TRACK_CA_EN = 0
2195 22:50:08.867414 CA_PICK = 1200
2196 22:50:08.867498 CA_MCKIO = 1200
2197 22:50:08.867579 MCKIO_SEMI = 0
2198 22:50:08.867669 PLL_FREQ = 2366
2199 22:50:08.867751 DQ_UI_PI_RATIO = 32
2200 22:50:08.867833 CA_UI_PI_RATIO = 0
2201 22:50:08.867923 ===================================
2202 22:50:08.868005 ===================================
2203 22:50:08.868087 memory_type:LPDDR4
2204 22:50:08.868202 GP_NUM : 10
2205 22:50:08.868287 SRAM_EN : 1
2206 22:50:08.868412 MD32_EN : 0
2207 22:50:08.868467 ===================================
2208 22:50:08.868521 [ANA_INIT] >>>>>>>>>>>>>>
2209 22:50:08.868573 <<<<<< [CONFIGURE PHASE]: ANA_TX
2210 22:50:08.868635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2211 22:50:08.868693 ===================================
2212 22:50:08.868745 data_rate = 2400,PCW = 0X5b00
2213 22:50:08.868797 ===================================
2214 22:50:08.868849 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2215 22:50:08.868918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 22:50:08.868974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2217 22:50:08.869245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2218 22:50:08.869357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2219 22:50:08.869424 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2220 22:50:08.869479 [ANA_INIT] flow start
2221 22:50:08.869566 [ANA_INIT] PLL >>>>>>>>
2222 22:50:08.869638 [ANA_INIT] PLL <<<<<<<<
2223 22:50:08.869696 [ANA_INIT] MIDPI >>>>>>>>
2224 22:50:08.869749 [ANA_INIT] MIDPI <<<<<<<<
2225 22:50:08.869803 [ANA_INIT] DLL >>>>>>>>
2226 22:50:08.869868 [ANA_INIT] DLL <<<<<<<<
2227 22:50:08.869926 [ANA_INIT] flow end
2228 22:50:08.869979 ============ LP4 DIFF to SE enter ============
2229 22:50:08.870034 ============ LP4 DIFF to SE exit ============
2230 22:50:08.870088 [ANA_INIT] <<<<<<<<<<<<<
2231 22:50:08.870175 [Flow] Enable top DCM control >>>>>
2232 22:50:08.870260 [Flow] Enable top DCM control <<<<<
2233 22:50:08.870343 Enable DLL master slave shuffle
2234 22:50:08.870437 ==============================================================
2235 22:50:08.870521 Gating Mode config
2236 22:50:08.870611 ==============================================================
2237 22:50:08.870698 Config description:
2238 22:50:08.870784 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2239 22:50:08.870878 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2240 22:50:08.870977 SELPH_MODE 0: By rank 1: By Phase
2241 22:50:08.871060 ==============================================================
2242 22:50:08.871151 GAT_TRACK_EN = 1
2243 22:50:08.871233 RX_GATING_MODE = 2
2244 22:50:08.871315 RX_GATING_TRACK_MODE = 2
2245 22:50:08.871404 SELPH_MODE = 1
2246 22:50:08.871487 PICG_EARLY_EN = 1
2247 22:50:08.871568 VALID_LAT_VALUE = 1
2248 22:50:08.871691 ==============================================================
2249 22:50:08.871774 Enter into Gating configuration >>>>
2250 22:50:08.871860 Exit from Gating configuration <<<<
2251 22:50:08.871946 Enter into DVFS_PRE_config >>>>>
2252 22:50:08.872061 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2253 22:50:08.872198 Exit from DVFS_PRE_config <<<<<
2254 22:50:08.872311 Enter into PICG configuration >>>>
2255 22:50:08.872412 Exit from PICG configuration <<<<
2256 22:50:08.872468 [RX_INPUT] configuration >>>>>
2257 22:50:08.872521 [RX_INPUT] configuration <<<<<
2258 22:50:08.872575 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2259 22:50:08.872628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2260 22:50:08.872681 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 22:50:08.872735 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 22:50:08.872788 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2263 22:50:08.872840 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2264 22:50:08.872893 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2265 22:50:08.872945 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2266 22:50:08.873033 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2267 22:50:08.873085 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2268 22:50:08.873138 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2269 22:50:08.873191 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2270 22:50:08.873243 ===================================
2271 22:50:08.873295 LPDDR4 DRAM CONFIGURATION
2272 22:50:08.873389 ===================================
2273 22:50:08.873444 EX_ROW_EN[0] = 0x0
2274 22:50:08.873496 EX_ROW_EN[1] = 0x0
2275 22:50:08.873549 LP4Y_EN = 0x0
2276 22:50:08.873600 WORK_FSP = 0x0
2277 22:50:08.873652 WL = 0x4
2278 22:50:08.873704 RL = 0x4
2279 22:50:08.873756 BL = 0x2
2280 22:50:08.873807 RPST = 0x0
2281 22:50:08.873859 RD_PRE = 0x0
2282 22:50:08.873911 WR_PRE = 0x1
2283 22:50:08.873963 WR_PST = 0x0
2284 22:50:08.874014 DBI_WR = 0x0
2285 22:50:08.874065 DBI_RD = 0x0
2286 22:50:08.874148 OTF = 0x1
2287 22:50:08.874235 ===================================
2288 22:50:08.874287 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2289 22:50:08.874339 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2290 22:50:08.874393 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2291 22:50:08.874445 ===================================
2292 22:50:08.874497 LPDDR4 DRAM CONFIGURATION
2293 22:50:08.874549 ===================================
2294 22:50:08.874601 EX_ROW_EN[0] = 0x10
2295 22:50:08.874652 EX_ROW_EN[1] = 0x0
2296 22:50:08.874703 LP4Y_EN = 0x0
2297 22:50:08.874754 WORK_FSP = 0x0
2298 22:50:08.874806 WL = 0x4
2299 22:50:08.874857 RL = 0x4
2300 22:50:08.874908 BL = 0x2
2301 22:50:08.874959 RPST = 0x0
2302 22:50:08.875010 RD_PRE = 0x0
2303 22:50:08.875060 WR_PRE = 0x1
2304 22:50:08.875111 WR_PST = 0x0
2305 22:50:08.875162 DBI_WR = 0x0
2306 22:50:08.875213 DBI_RD = 0x0
2307 22:50:08.875264 OTF = 0x1
2308 22:50:08.875316 ===================================
2309 22:50:08.875367 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2310 22:50:08.875420 ==
2311 22:50:08.875472 Dram Type= 6, Freq= 0, CH_0, rank 0
2312 22:50:08.875524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2313 22:50:08.875577 ==
2314 22:50:08.875667 [Duty_Offset_Calibration]
2315 22:50:08.875718 B0:1 B1:-1 CA:0
2316 22:50:08.875776
2317 22:50:08.875890 [DutyScan_Calibration_Flow] k_type=0
2318 22:50:08.875988
2319 22:50:08.876073 ==CLK 0==
2320 22:50:08.876179 Final CLK duty delay cell = 0
2321 22:50:08.876273 [0] MAX Duty = 5094%(X100), DQS PI = 16
2322 22:50:08.876374 [0] MIN Duty = 4875%(X100), DQS PI = 8
2323 22:50:08.876476 [0] AVG Duty = 4984%(X100)
2324 22:50:08.876537
2325 22:50:08.876634 CH0 CLK Duty spec in!! Max-Min= 219%
2326 22:50:08.876732 [DutyScan_Calibration_Flow] ====Done====
2327 22:50:08.876812
2328 22:50:08.876927 [DutyScan_Calibration_Flow] k_type=1
2329 22:50:08.877007
2330 22:50:08.877087 ==DQS 0 ==
2331 22:50:08.877200 Final DQS duty delay cell = -4
2332 22:50:08.877286 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2333 22:50:08.877405 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2334 22:50:08.877736 [-4] AVG Duty = 4953%(X100)
2335 22:50:08.877899
2336 22:50:08.878009 ==DQS 1 ==
2337 22:50:08.878113 Final DQS duty delay cell = -4
2338 22:50:08.878210 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2339 22:50:08.878311 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2340 22:50:08.878401 [-4] AVG Duty = 4938%(X100)
2341 22:50:08.878487
2342 22:50:08.878572 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2343 22:50:08.878655
2344 22:50:08.878748 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2345 22:50:08.878834 [DutyScan_Calibration_Flow] ====Done====
2346 22:50:08.878924
2347 22:50:08.879009 [DutyScan_Calibration_Flow] k_type=3
2348 22:50:08.879091
2349 22:50:08.879173 ==DQM 0 ==
2350 22:50:08.879256 Final DQM duty delay cell = 0
2351 22:50:08.879340 [0] MAX Duty = 5062%(X100), DQS PI = 20
2352 22:50:08.879435 [0] MIN Duty = 4844%(X100), DQS PI = 8
2353 22:50:08.879530 [0] AVG Duty = 4953%(X100)
2354 22:50:08.879621
2355 22:50:08.879710 ==DQM 1 ==
2356 22:50:08.879795 Final DQM duty delay cell = 4
2357 22:50:08.879880 [4] MAX Duty = 5187%(X100), DQS PI = 16
2358 22:50:08.879964 [4] MIN Duty = 5000%(X100), DQS PI = 22
2359 22:50:08.880064 [4] AVG Duty = 5093%(X100)
2360 22:50:08.880148
2361 22:50:08.880244 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2362 22:50:08.880348
2363 22:50:08.880442 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2364 22:50:08.880528 [DutyScan_Calibration_Flow] ====Done====
2365 22:50:08.880612
2366 22:50:08.880698 [DutyScan_Calibration_Flow] k_type=2
2367 22:50:08.880782
2368 22:50:08.880896 ==DQ 0 ==
2369 22:50:08.880992 Final DQ duty delay cell = -4
2370 22:50:08.881074 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2371 22:50:08.881171 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2372 22:50:08.881253 [-4] AVG Duty = 4953%(X100)
2373 22:50:08.881348
2374 22:50:08.881433 ==DQ 1 ==
2375 22:50:08.881516 Final DQ duty delay cell = 0
2376 22:50:08.881600 [0] MAX Duty = 5125%(X100), DQS PI = 52
2377 22:50:08.881683 [0] MIN Duty = 4969%(X100), DQS PI = 40
2378 22:50:08.881767 [0] AVG Duty = 5047%(X100)
2379 22:50:08.881851
2380 22:50:08.881949 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2381 22:50:08.882036
2382 22:50:08.882120 CH0 DQ 1 Duty spec in!! Max-Min= 156%
2383 22:50:08.882212 [DutyScan_Calibration_Flow] ====Done====
2384 22:50:08.882295 ==
2385 22:50:08.882379 Dram Type= 6, Freq= 0, CH_1, rank 0
2386 22:50:08.882462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2387 22:50:08.882544 ==
2388 22:50:08.882628 [Duty_Offset_Calibration]
2389 22:50:08.882710 B0:-1 B1:1 CA:2
2390 22:50:08.882791
2391 22:50:08.882874 [DutyScan_Calibration_Flow] k_type=0
2392 22:50:08.882956
2393 22:50:08.883038 ==CLK 0==
2394 22:50:08.883120 Final CLK duty delay cell = 0
2395 22:50:08.883204 [0] MAX Duty = 5156%(X100), DQS PI = 22
2396 22:50:08.883287 [0] MIN Duty = 4969%(X100), DQS PI = 62
2397 22:50:08.883369 [0] AVG Duty = 5062%(X100)
2398 22:50:08.883451
2399 22:50:08.883533 CH1 CLK Duty spec in!! Max-Min= 187%
2400 22:50:08.883616 [DutyScan_Calibration_Flow] ====Done====
2401 22:50:08.883711
2402 22:50:08.883806 [DutyScan_Calibration_Flow] k_type=1
2403 22:50:08.883917
2404 22:50:08.884025 ==DQS 0 ==
2405 22:50:08.884120 Final DQS duty delay cell = 0
2406 22:50:08.884201 [0] MAX Duty = 5125%(X100), DQS PI = 48
2407 22:50:08.884282 [0] MIN Duty = 4875%(X100), DQS PI = 8
2408 22:50:08.884377 [0] AVG Duty = 5000%(X100)
2409 22:50:08.884458
2410 22:50:08.884553 ==DQS 1 ==
2411 22:50:08.884664 Final DQS duty delay cell = 0
2412 22:50:08.884746 [0] MAX Duty = 5094%(X100), DQS PI = 12
2413 22:50:08.884826 [0] MIN Duty = 4969%(X100), DQS PI = 56
2414 22:50:08.884949 [0] AVG Duty = 5031%(X100)
2415 22:50:08.885030
2416 22:50:08.885126 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2417 22:50:08.885208
2418 22:50:08.885290 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2419 22:50:08.885385 [DutyScan_Calibration_Flow] ====Done====
2420 22:50:08.885439
2421 22:50:08.885491 [DutyScan_Calibration_Flow] k_type=3
2422 22:50:08.885545
2423 22:50:08.885606 ==DQM 0 ==
2424 22:50:08.885671 Final DQM duty delay cell = -4
2425 22:50:08.885724 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2426 22:50:08.885776 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2427 22:50:08.885828 [-4] AVG Duty = 4953%(X100)
2428 22:50:08.885922
2429 22:50:08.885990 ==DQM 1 ==
2430 22:50:08.886043 Final DQM duty delay cell = 0
2431 22:50:08.886096 [0] MAX Duty = 5156%(X100), DQS PI = 4
2432 22:50:08.886148 [0] MIN Duty = 4969%(X100), DQS PI = 28
2433 22:50:08.886200 [0] AVG Duty = 5062%(X100)
2434 22:50:08.886252
2435 22:50:08.886303 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2436 22:50:08.886355
2437 22:50:08.886406 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2438 22:50:08.886458 [DutyScan_Calibration_Flow] ====Done====
2439 22:50:08.886509
2440 22:50:08.886561 [DutyScan_Calibration_Flow] k_type=2
2441 22:50:08.886650
2442 22:50:08.886702 ==DQ 0 ==
2443 22:50:08.886784 Final DQ duty delay cell = 0
2444 22:50:08.886836 [0] MAX Duty = 5156%(X100), DQS PI = 28
2445 22:50:08.886887 [0] MIN Duty = 4876%(X100), DQS PI = 8
2446 22:50:08.886955 [0] AVG Duty = 5016%(X100)
2447 22:50:08.887022
2448 22:50:08.887073 ==DQ 1 ==
2449 22:50:08.887156 Final DQ duty delay cell = 0
2450 22:50:08.887207 [0] MAX Duty = 5156%(X100), DQS PI = 10
2451 22:50:08.887259 [0] MIN Duty = 4969%(X100), DQS PI = 0
2452 22:50:08.887311 [0] AVG Duty = 5062%(X100)
2453 22:50:08.887362
2454 22:50:08.887413 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2455 22:50:08.887464
2456 22:50:08.887515 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2457 22:50:08.887567 [DutyScan_Calibration_Flow] ====Done====
2458 22:50:08.887619 nWR fixed to 30
2459 22:50:08.887671 [ModeRegInit_LP4] CH0 RK0
2460 22:50:08.887722 [ModeRegInit_LP4] CH0 RK1
2461 22:50:08.887773 [ModeRegInit_LP4] CH1 RK0
2462 22:50:08.887825 [ModeRegInit_LP4] CH1 RK1
2463 22:50:08.887877 match AC timing 7
2464 22:50:08.887934 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2465 22:50:08.887987 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2466 22:50:08.888068 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2467 22:50:08.888121 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2468 22:50:08.888172 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2469 22:50:08.888240 ==
2470 22:50:08.888292 Dram Type= 6, Freq= 0, CH_0, rank 0
2471 22:50:08.888346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 22:50:08.888400 ==
2473 22:50:08.888457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2474 22:50:08.888523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2475 22:50:08.888576 [CA 0] Center 39 (9~70) winsize 62
2476 22:50:08.888632 [CA 1] Center 39 (9~69) winsize 61
2477 22:50:08.888684 [CA 2] Center 35 (5~66) winsize 62
2478 22:50:08.888765 [CA 3] Center 35 (4~66) winsize 63
2479 22:50:08.888848 [CA 4] Center 33 (4~63) winsize 60
2480 22:50:08.888900 [CA 5] Center 33 (3~63) winsize 61
2481 22:50:08.888951
2482 22:50:08.889026 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2483 22:50:08.889109
2484 22:50:08.889205 [CATrainingPosCal] consider 1 rank data
2485 22:50:08.889288 u2DelayCellTimex100 = 270/100 ps
2486 22:50:08.889614 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2487 22:50:08.889765 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2488 22:50:08.889881 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2489 22:50:08.889989 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2490 22:50:08.890078 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2491 22:50:08.890197 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2492 22:50:08.890333
2493 22:50:08.890512 CA PerBit enable=1, Macro0, CA PI delay=33
2494 22:50:08.890649
2495 22:50:08.890797 [CBTSetCACLKResult] CA Dly = 33
2496 22:50:08.890911 CS Dly: 8 (0~39)
2497 22:50:08.891047 ==
2498 22:50:08.891141 Dram Type= 6, Freq= 0, CH_0, rank 1
2499 22:50:08.891252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 22:50:08.891368 ==
2501 22:50:08.891510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2502 22:50:08.891664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2503 22:50:08.891775 [CA 0] Center 39 (8~70) winsize 63
2504 22:50:08.891873 [CA 1] Center 39 (9~70) winsize 62
2505 22:50:08.891997 [CA 2] Center 35 (5~66) winsize 62
2506 22:50:08.892075 [CA 3] Center 34 (4~65) winsize 62
2507 22:50:08.892133 [CA 4] Center 33 (3~63) winsize 61
2508 22:50:08.892188 [CA 5] Center 33 (3~63) winsize 61
2509 22:50:08.892243
2510 22:50:08.892327 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2511 22:50:08.892396
2512 22:50:08.892448 [CATrainingPosCal] consider 2 rank data
2513 22:50:08.892502 u2DelayCellTimex100 = 270/100 ps
2514 22:50:08.892555 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2515 22:50:08.892608 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2516 22:50:08.892661 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2517 22:50:08.892714 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2518 22:50:08.892810 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2519 22:50:08.892877 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2520 22:50:08.892929
2521 22:50:08.892997 CA PerBit enable=1, Macro0, CA PI delay=33
2522 22:50:08.893064
2523 22:50:08.893132 [CBTSetCACLKResult] CA Dly = 33
2524 22:50:08.893186 CS Dly: 8 (0~40)
2525 22:50:08.893239
2526 22:50:08.893292 ----->DramcWriteLeveling(PI) begin...
2527 22:50:08.893376 ==
2528 22:50:08.893431 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 22:50:08.893484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 22:50:08.893537 ==
2531 22:50:08.893589 Write leveling (Byte 0): 32 => 32
2532 22:50:08.893642 Write leveling (Byte 1): 29 => 29
2533 22:50:08.893694 DramcWriteLeveling(PI) end<-----
2534 22:50:08.893747
2535 22:50:08.893798 ==
2536 22:50:08.893851 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 22:50:08.893935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 22:50:08.894009 ==
2539 22:50:08.894099 [Gating] SW mode calibration
2540 22:50:08.894202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2541 22:50:08.894291 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2542 22:50:08.894351 0 15 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2543 22:50:08.894408 0 15 4 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
2544 22:50:08.894462 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 22:50:08.894515 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 22:50:08.894568 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 22:50:08.894622 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 22:50:08.894675 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2549 22:50:08.894727 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
2550 22:50:08.894780 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
2551 22:50:08.894833 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 22:50:08.894885 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 22:50:08.894938 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 22:50:08.894990 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 22:50:08.895042 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 22:50:08.895094 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 22:50:08.895147 1 0 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2558 22:50:08.895200 1 1 0 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)
2559 22:50:08.895252 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2560 22:50:08.895335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 22:50:08.895418 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 22:50:08.895470 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 22:50:08.895523 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 22:50:08.895575 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 22:50:08.895628 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2566 22:50:08.895680 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2567 22:50:08.895733 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:50:08.895835 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:50:08.895919 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:50:08.896016 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 22:50:08.896113 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 22:50:08.896199 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 22:50:08.896256 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 22:50:08.896326 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 22:50:08.896392 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 22:50:08.896446 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 22:50:08.896499 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 22:50:08.896551 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 22:50:08.896604 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 22:50:08.896656 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 22:50:08.896708 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2582 22:50:08.896760 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2583 22:50:08.896812 Total UI for P1: 0, mck2ui 16
2584 22:50:08.896866 best dqsien dly found for B0: ( 1, 3, 28)
2585 22:50:08.896918 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2586 22:50:08.896971 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 22:50:08.897060 Total UI for P1: 0, mck2ui 16
2588 22:50:08.897113 best dqsien dly found for B1: ( 1, 4, 2)
2589 22:50:08.897394 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2590 22:50:08.897455 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2591 22:50:08.897510
2592 22:50:08.897563 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2593 22:50:08.897616 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2594 22:50:08.897669 [Gating] SW calibration Done
2595 22:50:08.897721 ==
2596 22:50:08.897774 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 22:50:08.897828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 22:50:08.897881 ==
2599 22:50:08.897935 RX Vref Scan: 0
2600 22:50:08.898015
2601 22:50:08.898101 RX Vref 0 -> 0, step: 1
2602 22:50:08.898188
2603 22:50:08.898270 RX Delay -40 -> 252, step: 8
2604 22:50:08.898357 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2605 22:50:08.898441 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2606 22:50:08.898523 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2607 22:50:08.898605 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2608 22:50:08.898687 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2609 22:50:08.898774 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2610 22:50:08.898831 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2611 22:50:08.898884 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2612 22:50:08.898938 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2613 22:50:08.898992 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2614 22:50:08.899045 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2615 22:50:08.899098 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2616 22:50:08.899151 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2617 22:50:08.899204 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2618 22:50:08.899255 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2619 22:50:08.899307 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2620 22:50:08.899359 ==
2621 22:50:08.899412 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 22:50:08.899465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 22:50:08.899517 ==
2624 22:50:08.899570 DQS Delay:
2625 22:50:08.899622 DQS0 = 0, DQS1 = 0
2626 22:50:08.899704 DQM Delay:
2627 22:50:08.899756 DQM0 = 118, DQM1 = 106
2628 22:50:08.899808 DQ Delay:
2629 22:50:08.899859 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2630 22:50:08.899911 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2631 22:50:08.899964 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2632 22:50:08.900016 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2633 22:50:08.900068
2634 22:50:08.900120
2635 22:50:08.900171 ==
2636 22:50:08.900223 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 22:50:08.900275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 22:50:08.900328 ==
2639 22:50:08.900379
2640 22:50:08.900431
2641 22:50:08.900483 TX Vref Scan disable
2642 22:50:08.900534 == TX Byte 0 ==
2643 22:50:08.900586 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2644 22:50:08.900639 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2645 22:50:08.900691 == TX Byte 1 ==
2646 22:50:08.900743 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2647 22:50:08.900796 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2648 22:50:08.900848 ==
2649 22:50:08.900900 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 22:50:08.900952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 22:50:08.901004 ==
2652 22:50:08.901057 TX Vref=22, minBit 14, minWin=24, winSum=410
2653 22:50:08.901110 TX Vref=24, minBit 1, minWin=25, winSum=417
2654 22:50:08.901164 TX Vref=26, minBit 1, minWin=25, winSum=421
2655 22:50:08.901217 TX Vref=28, minBit 4, minWin=26, winSum=431
2656 22:50:08.901269 TX Vref=30, minBit 10, minWin=26, winSum=431
2657 22:50:08.901322 TX Vref=32, minBit 10, minWin=25, winSum=423
2658 22:50:08.901431 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 28
2659 22:50:08.901498
2660 22:50:08.901552 Final TX Range 1 Vref 28
2661 22:50:08.901605
2662 22:50:08.901658 ==
2663 22:50:08.901710 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 22:50:08.901763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 22:50:08.901834 ==
2666 22:50:08.901901
2667 22:50:08.901953
2668 22:50:08.902005 TX Vref Scan disable
2669 22:50:08.902057 == TX Byte 0 ==
2670 22:50:08.902109 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2671 22:50:08.902162 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2672 22:50:08.902215 == TX Byte 1 ==
2673 22:50:08.902267 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2674 22:50:08.902320 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2675 22:50:08.902372
2676 22:50:08.902458 [DATLAT]
2677 22:50:08.902541 Freq=1200, CH0 RK0
2678 22:50:08.902624
2679 22:50:08.902714 DATLAT Default: 0xd
2680 22:50:08.902797 0, 0xFFFF, sum = 0
2681 22:50:08.902856 1, 0xFFFF, sum = 0
2682 22:50:08.902911 2, 0xFFFF, sum = 0
2683 22:50:08.902965 3, 0xFFFF, sum = 0
2684 22:50:08.903019 4, 0xFFFF, sum = 0
2685 22:50:08.903072 5, 0xFFFF, sum = 0
2686 22:50:08.903126 6, 0xFFFF, sum = 0
2687 22:50:08.903180 7, 0xFFFF, sum = 0
2688 22:50:08.903233 8, 0xFFFF, sum = 0
2689 22:50:08.903286 9, 0xFFFF, sum = 0
2690 22:50:08.903338 10, 0xFFFF, sum = 0
2691 22:50:08.903391 11, 0xFFFF, sum = 0
2692 22:50:08.903445 12, 0x0, sum = 1
2693 22:50:08.903497 13, 0x0, sum = 2
2694 22:50:08.903571 14, 0x0, sum = 3
2695 22:50:08.903639 15, 0x0, sum = 4
2696 22:50:08.903692 best_step = 13
2697 22:50:08.903745
2698 22:50:08.903798 ==
2699 22:50:08.903850 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 22:50:08.903903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 22:50:08.903956 ==
2702 22:50:08.904009 RX Vref Scan: 1
2703 22:50:08.904061
2704 22:50:08.904113 Set Vref Range= 32 -> 127
2705 22:50:08.904165
2706 22:50:08.904216 RX Vref 32 -> 127, step: 1
2707 22:50:08.904269
2708 22:50:08.904320 RX Delay -21 -> 252, step: 4
2709 22:50:08.904373
2710 22:50:08.904424 Set Vref, RX VrefLevel [Byte0]: 32
2711 22:50:08.904477 [Byte1]: 32
2712 22:50:08.904530
2713 22:50:08.904581 Set Vref, RX VrefLevel [Byte0]: 33
2714 22:50:08.904633 [Byte1]: 33
2715 22:50:08.904685
2716 22:50:08.904738 Set Vref, RX VrefLevel [Byte0]: 34
2717 22:50:08.904790 [Byte1]: 34
2718 22:50:08.904879
2719 22:50:08.904930 Set Vref, RX VrefLevel [Byte0]: 35
2720 22:50:08.904982 [Byte1]: 35
2721 22:50:08.905034
2722 22:50:08.905086 Set Vref, RX VrefLevel [Byte0]: 36
2723 22:50:08.905139 [Byte1]: 36
2724 22:50:08.905190
2725 22:50:08.905242 Set Vref, RX VrefLevel [Byte0]: 37
2726 22:50:08.905314 [Byte1]: 37
2727 22:50:08.905391
2728 22:50:08.905443 Set Vref, RX VrefLevel [Byte0]: 38
2729 22:50:08.905496 [Byte1]: 38
2730 22:50:08.905548
2731 22:50:08.905600 Set Vref, RX VrefLevel [Byte0]: 39
2732 22:50:08.905652 [Byte1]: 39
2733 22:50:08.905704
2734 22:50:08.905756 Set Vref, RX VrefLevel [Byte0]: 40
2735 22:50:08.905808 [Byte1]: 40
2736 22:50:08.905861
2737 22:50:08.905912 Set Vref, RX VrefLevel [Byte0]: 41
2738 22:50:08.905965 [Byte1]: 41
2739 22:50:08.906017
2740 22:50:08.906068 Set Vref, RX VrefLevel [Byte0]: 42
2741 22:50:08.906122 [Byte1]: 42
2742 22:50:08.906174
2743 22:50:08.906226 Set Vref, RX VrefLevel [Byte0]: 43
2744 22:50:08.906480 [Byte1]: 43
2745 22:50:08.906568
2746 22:50:08.906656 Set Vref, RX VrefLevel [Byte0]: 44
2747 22:50:08.906740 [Byte1]: 44
2748 22:50:08.906829
2749 22:50:08.906884 Set Vref, RX VrefLevel [Byte0]: 45
2750 22:50:08.906936 [Byte1]: 45
2751 22:50:08.906989
2752 22:50:08.907071 Set Vref, RX VrefLevel [Byte0]: 46
2753 22:50:08.907123 [Byte1]: 46
2754 22:50:08.907176
2755 22:50:08.907242 Set Vref, RX VrefLevel [Byte0]: 47
2756 22:50:08.907309 [Byte1]: 47
2757 22:50:08.907362
2758 22:50:08.907413 Set Vref, RX VrefLevel [Byte0]: 48
2759 22:50:08.907465 [Byte1]: 48
2760 22:50:08.907516
2761 22:50:08.907568 Set Vref, RX VrefLevel [Byte0]: 49
2762 22:50:08.907620 [Byte1]: 49
2763 22:50:08.907677
2764 22:50:08.907733 Set Vref, RX VrefLevel [Byte0]: 50
2765 22:50:08.907786 [Byte1]: 50
2766 22:50:08.907838
2767 22:50:08.907891 Set Vref, RX VrefLevel [Byte0]: 51
2768 22:50:08.907942 [Byte1]: 51
2769 22:50:08.907994
2770 22:50:08.908046 Set Vref, RX VrefLevel [Byte0]: 52
2771 22:50:08.908098 [Byte1]: 52
2772 22:50:08.908150
2773 22:50:08.908202 Set Vref, RX VrefLevel [Byte0]: 53
2774 22:50:08.908254 [Byte1]: 53
2775 22:50:08.908306
2776 22:50:08.908358 Set Vref, RX VrefLevel [Byte0]: 54
2777 22:50:08.908409 [Byte1]: 54
2778 22:50:08.908461
2779 22:50:08.908513 Set Vref, RX VrefLevel [Byte0]: 55
2780 22:50:08.908565 [Byte1]: 55
2781 22:50:08.908618
2782 22:50:08.908670 Set Vref, RX VrefLevel [Byte0]: 56
2783 22:50:08.908723 [Byte1]: 56
2784 22:50:08.908775
2785 22:50:08.908827 Set Vref, RX VrefLevel [Byte0]: 57
2786 22:50:08.908878 [Byte1]: 57
2787 22:50:08.908930
2788 22:50:08.908981 Set Vref, RX VrefLevel [Byte0]: 58
2789 22:50:08.909033 [Byte1]: 58
2790 22:50:08.909085
2791 22:50:08.909137 Set Vref, RX VrefLevel [Byte0]: 59
2792 22:50:08.909189 [Byte1]: 59
2793 22:50:08.909257
2794 22:50:08.909310 Set Vref, RX VrefLevel [Byte0]: 60
2795 22:50:08.909386 [Byte1]: 60
2796 22:50:08.909439
2797 22:50:08.909491 Set Vref, RX VrefLevel [Byte0]: 61
2798 22:50:08.909543 [Byte1]: 61
2799 22:50:08.909595
2800 22:50:08.909647 Set Vref, RX VrefLevel [Byte0]: 62
2801 22:50:08.909700 [Byte1]: 62
2802 22:50:08.909752
2803 22:50:08.909804 Set Vref, RX VrefLevel [Byte0]: 63
2804 22:50:08.909855 [Byte1]: 63
2805 22:50:08.909907
2806 22:50:08.909958 Set Vref, RX VrefLevel [Byte0]: 64
2807 22:50:08.910011 [Byte1]: 64
2808 22:50:08.910063
2809 22:50:08.910114 Set Vref, RX VrefLevel [Byte0]: 65
2810 22:50:08.910166 [Byte1]: 65
2811 22:50:08.910218
2812 22:50:08.910269 Set Vref, RX VrefLevel [Byte0]: 66
2813 22:50:08.910321 [Byte1]: 66
2814 22:50:08.910373
2815 22:50:08.910424 Set Vref, RX VrefLevel [Byte0]: 67
2816 22:50:08.910477 [Byte1]: 67
2817 22:50:08.910584
2818 22:50:08.910666 Set Vref, RX VrefLevel [Byte0]: 68
2819 22:50:08.910752 [Byte1]: 68
2820 22:50:08.910831
2821 22:50:08.910887 Set Vref, RX VrefLevel [Byte0]: 69
2822 22:50:08.910941 [Byte1]: 69
2823 22:50:08.910993
2824 22:50:08.911045 Set Vref, RX VrefLevel [Byte0]: 70
2825 22:50:08.911099 [Byte1]: 70
2826 22:50:08.911152
2827 22:50:08.911204 Set Vref, RX VrefLevel [Byte0]: 71
2828 22:50:08.911256 [Byte1]: 71
2829 22:50:08.911308
2830 22:50:08.911360 Set Vref, RX VrefLevel [Byte0]: 72
2831 22:50:08.911413 [Byte1]: 72
2832 22:50:08.911464
2833 22:50:08.911516 Set Vref, RX VrefLevel [Byte0]: 73
2834 22:50:08.911569 [Byte1]: 73
2835 22:50:08.911621
2836 22:50:08.911673 Set Vref, RX VrefLevel [Byte0]: 74
2837 22:50:08.911725 [Byte1]: 74
2838 22:50:08.911789
2839 22:50:08.911842 Set Vref, RX VrefLevel [Byte0]: 75
2840 22:50:08.911895 [Byte1]: 75
2841 22:50:08.911947
2842 22:50:08.911998 Set Vref, RX VrefLevel [Byte0]: 76
2843 22:50:08.912051 [Byte1]: 76
2844 22:50:08.912103
2845 22:50:08.912154 Final RX Vref Byte 0 = 59 to rank0
2846 22:50:08.912207 Final RX Vref Byte 1 = 49 to rank0
2847 22:50:08.912259 Final RX Vref Byte 0 = 59 to rank1
2848 22:50:08.912312 Final RX Vref Byte 1 = 49 to rank1==
2849 22:50:08.912364 Dram Type= 6, Freq= 0, CH_0, rank 0
2850 22:50:08.912416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 22:50:08.912469 ==
2852 22:50:08.912521 DQS Delay:
2853 22:50:08.912573 DQS0 = 0, DQS1 = 0
2854 22:50:08.912625 DQM Delay:
2855 22:50:08.912678 DQM0 = 118, DQM1 = 105
2856 22:50:08.912730 DQ Delay:
2857 22:50:08.912783 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2858 22:50:08.912835 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =126
2859 22:50:08.912887 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =100
2860 22:50:08.912938 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =114
2861 22:50:08.912990
2862 22:50:08.913041
2863 22:50:08.913093 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
2864 22:50:08.913146 CH0 RK0: MR19=403, MR18=10FB
2865 22:50:08.913199 CH0_RK0: MR19=0x403, MR18=0x10FB, DQSOSC=403, MR23=63, INC=40, DEC=26
2866 22:50:08.913253
2867 22:50:08.913306 ----->DramcWriteLeveling(PI) begin...
2868 22:50:08.913400 ==
2869 22:50:08.913454 Dram Type= 6, Freq= 0, CH_0, rank 1
2870 22:50:08.913506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 22:50:08.913559 ==
2872 22:50:08.913612 Write leveling (Byte 0): 32 => 32
2873 22:50:08.913665 Write leveling (Byte 1): 29 => 29
2874 22:50:08.913717 DramcWriteLeveling(PI) end<-----
2875 22:50:08.913769
2876 22:50:08.913821 ==
2877 22:50:08.913873 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 22:50:08.913926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 22:50:08.913978 ==
2880 22:50:08.914031 [Gating] SW mode calibration
2881 22:50:08.914084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2882 22:50:08.914137 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2883 22:50:08.914190 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2884 22:50:08.914243 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2885 22:50:08.914300 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 22:50:08.914388 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 22:50:08.914473 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 22:50:08.914559 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 22:50:08.914619 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2890 22:50:08.914864 0 15 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
2891 22:50:08.914924 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2892 22:50:08.914978 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 22:50:08.915032 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 22:50:08.915085 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 22:50:08.915138 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 22:50:08.915190 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 22:50:08.915244 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 22:50:08.915297 1 0 28 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
2899 22:50:08.915349 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2900 22:50:08.915401 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 22:50:08.915454 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 22:50:08.915508 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 22:50:08.915561 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 22:50:08.915612 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 22:50:08.915664 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2906 22:50:08.915716 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2907 22:50:08.915769 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2908 22:50:08.915821 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 22:50:08.915873 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 22:50:08.915926 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 22:50:08.915978 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 22:50:08.916030 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 22:50:08.916082 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 22:50:08.916134 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 22:50:08.916186 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 22:50:08.916239 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 22:50:08.916291 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 22:50:08.916343 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 22:50:08.916394 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 22:50:08.916446 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 22:50:08.916498 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2922 22:50:08.916550 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2923 22:50:08.916602 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2924 22:50:08.916654 Total UI for P1: 0, mck2ui 16
2925 22:50:08.916706 best dqsien dly found for B0: ( 1, 3, 26)
2926 22:50:08.916758 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 22:50:08.916811 Total UI for P1: 0, mck2ui 16
2928 22:50:08.916864 best dqsien dly found for B1: ( 1, 4, 0)
2929 22:50:08.916916 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2930 22:50:08.916968 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2931 22:50:08.917020
2932 22:50:08.917072 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2933 22:50:08.917125 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2934 22:50:08.917177 [Gating] SW calibration Done
2935 22:50:08.917229 ==
2936 22:50:08.917281 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 22:50:09.140010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 22:50:09.140206 ==
2939 22:50:09.140309 RX Vref Scan: 0
2940 22:50:09.140399
2941 22:50:09.140493 RX Vref 0 -> 0, step: 1
2942 22:50:09.140582
2943 22:50:09.140666 RX Delay -40 -> 252, step: 8
2944 22:50:09.140759 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2945 22:50:09.140845 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2946 22:50:09.140928 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2947 22:50:09.141021 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2948 22:50:09.141105 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2949 22:50:09.141188 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2950 22:50:09.141280 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2951 22:50:09.141406 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2952 22:50:09.141496 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2953 22:50:09.141555 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2954 22:50:09.141609 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2955 22:50:09.141662 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2956 22:50:09.141715 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2957 22:50:09.141784 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2958 22:50:09.141838 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2959 22:50:09.141891 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2960 22:50:09.141944 ==
2961 22:50:09.142013 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 22:50:09.142069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 22:50:09.142123 ==
2964 22:50:09.142176 DQS Delay:
2965 22:50:09.142237 DQS0 = 0, DQS1 = 0
2966 22:50:09.142295 DQM Delay:
2967 22:50:09.142349 DQM0 = 117, DQM1 = 107
2968 22:50:09.142402 DQ Delay:
2969 22:50:09.142455 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2970 22:50:09.142525 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2971 22:50:09.142579 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2972 22:50:09.142665 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2973 22:50:09.142718
2974 22:50:09.142807
2975 22:50:09.142889 ==
2976 22:50:09.142973 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 22:50:09.143062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 22:50:09.143144 ==
2979 22:50:09.143230
2980 22:50:09.143315
2981 22:50:09.143396 TX Vref Scan disable
2982 22:50:09.143483 == TX Byte 0 ==
2983 22:50:09.143569 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2984 22:50:09.143652 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2985 22:50:09.143806 == TX Byte 1 ==
2986 22:50:09.143889 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2987 22:50:09.143974 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2988 22:50:09.144061 ==
2989 22:50:09.144143 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 22:50:09.144228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 22:50:09.144316 ==
2992 22:50:09.144398 TX Vref=22, minBit 10, minWin=25, winSum=411
2993 22:50:09.144487 TX Vref=24, minBit 10, minWin=25, winSum=418
2994 22:50:09.144573 TX Vref=26, minBit 13, minWin=25, winSum=421
2995 22:50:09.144655 TX Vref=28, minBit 13, minWin=25, winSum=421
2996 22:50:09.144746 TX Vref=30, minBit 12, minWin=25, winSum=423
2997 22:50:09.144830 TX Vref=32, minBit 13, minWin=25, winSum=426
2998 22:50:09.145122 [TxChooseVref] Worse bit 13, Min win 25, Win sum 426, Final Vref 32
2999 22:50:09.145210
3000 22:50:09.145302 Final TX Range 1 Vref 32
3001 22:50:09.145425
3002 22:50:09.145511 ==
3003 22:50:09.145568 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 22:50:09.145621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 22:50:09.145675 ==
3006 22:50:09.145737
3007 22:50:09.145795
3008 22:50:09.145847 TX Vref Scan disable
3009 22:50:09.145900 == TX Byte 0 ==
3010 22:50:09.145952 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3011 22:50:09.146023 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3012 22:50:09.146077 == TX Byte 1 ==
3013 22:50:09.146147 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3014 22:50:09.146214 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3015 22:50:09.146282
3016 22:50:09.146336 [DATLAT]
3017 22:50:09.146389 Freq=1200, CH0 RK1
3018 22:50:09.146442
3019 22:50:09.146512 DATLAT Default: 0xd
3020 22:50:09.146567 0, 0xFFFF, sum = 0
3021 22:50:09.146622 1, 0xFFFF, sum = 0
3022 22:50:09.146676 2, 0xFFFF, sum = 0
3023 22:50:09.146740 3, 0xFFFF, sum = 0
3024 22:50:09.146826 4, 0xFFFF, sum = 0
3025 22:50:09.146910 5, 0xFFFF, sum = 0
3026 22:50:09.147001 6, 0xFFFF, sum = 0
3027 22:50:09.147085 7, 0xFFFF, sum = 0
3028 22:50:09.147168 8, 0xFFFF, sum = 0
3029 22:50:09.147324 9, 0xFFFF, sum = 0
3030 22:50:09.147408 10, 0xFFFF, sum = 0
3031 22:50:09.147534 11, 0xFFFF, sum = 0
3032 22:50:09.147618 12, 0x0, sum = 1
3033 22:50:09.147702 13, 0x0, sum = 2
3034 22:50:09.147793 14, 0x0, sum = 3
3035 22:50:09.147877 15, 0x0, sum = 4
3036 22:50:09.147961 best_step = 13
3037 22:50:09.148051
3038 22:50:09.148132 ==
3039 22:50:09.148214 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 22:50:09.148305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 22:50:09.148388 ==
3042 22:50:09.148473 RX Vref Scan: 0
3043 22:50:09.148592
3044 22:50:09.148674 RX Vref 0 -> 0, step: 1
3045 22:50:09.148764
3046 22:50:09.148847 RX Delay -21 -> 252, step: 4
3047 22:50:09.148929 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3048 22:50:09.149020 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3049 22:50:09.149103 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3050 22:50:09.149186 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3051 22:50:09.149277 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3052 22:50:09.149398 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3053 22:50:09.149488 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3054 22:50:09.149547 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3055 22:50:09.149601 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3056 22:50:09.149654 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3057 22:50:09.149707 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3058 22:50:09.149807 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3059 22:50:09.149862 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3060 22:50:09.149915 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3061 22:50:09.149968 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3062 22:50:09.150035 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3063 22:50:09.150088 ==
3064 22:50:09.150142 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 22:50:09.150195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 22:50:09.150266 ==
3067 22:50:09.150321 DQS Delay:
3068 22:50:09.150374 DQS0 = 0, DQS1 = 0
3069 22:50:09.150427 DQM Delay:
3070 22:50:09.150490 DQM0 = 116, DQM1 = 107
3071 22:50:09.150547 DQ Delay:
3072 22:50:09.150601 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3073 22:50:09.150654 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3074 22:50:09.150707 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3075 22:50:09.150777 DQ12 =112, DQ13 =116, DQ14 =118, DQ15 =116
3076 22:50:09.150831
3077 22:50:09.150885
3078 22:50:09.150938 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 403 ps
3079 22:50:09.151005 CH0 RK1: MR19=403, MR18=10EA
3080 22:50:09.151064 CH0_RK1: MR19=0x403, MR18=0x10EA, DQSOSC=403, MR23=63, INC=40, DEC=26
3081 22:50:09.151119 [RxdqsGatingPostProcess] freq 1200
3082 22:50:09.151172 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3083 22:50:09.151234 best DQS0 dly(2T, 0.5T) = (0, 11)
3084 22:50:09.151293 best DQS1 dly(2T, 0.5T) = (0, 12)
3085 22:50:09.151347 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3086 22:50:09.151400 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3087 22:50:09.151474 best DQS0 dly(2T, 0.5T) = (0, 11)
3088 22:50:09.151609 best DQS1 dly(2T, 0.5T) = (0, 12)
3089 22:50:09.151692 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3090 22:50:09.151783 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3091 22:50:09.151865 Pre-setting of DQS Precalculation
3092 22:50:09.151948 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3093 22:50:09.152038 ==
3094 22:50:09.152122 Dram Type= 6, Freq= 0, CH_1, rank 0
3095 22:50:09.152204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 22:50:09.152294 ==
3097 22:50:09.152378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 22:50:09.152462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3099 22:50:09.152554 [CA 0] Center 37 (7~67) winsize 61
3100 22:50:09.152636 [CA 1] Center 37 (7~68) winsize 62
3101 22:50:09.152719 [CA 2] Center 34 (4~64) winsize 61
3102 22:50:09.152810 [CA 3] Center 33 (3~64) winsize 62
3103 22:50:09.152892 [CA 4] Center 34 (4~64) winsize 61
3104 22:50:09.152977 [CA 5] Center 33 (3~64) winsize 62
3105 22:50:09.153063
3106 22:50:09.153176 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 22:50:09.153266
3108 22:50:09.153370 [CATrainingPosCal] consider 1 rank data
3109 22:50:09.153468 u2DelayCellTimex100 = 270/100 ps
3110 22:50:09.153559 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3111 22:50:09.153643 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3112 22:50:09.153728 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 22:50:09.153816 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3114 22:50:09.153898 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 22:50:09.153986 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3116 22:50:09.154070
3117 22:50:09.154152 CA PerBit enable=1, Macro0, CA PI delay=33
3118 22:50:09.154242
3119 22:50:09.154325 [CBTSetCACLKResult] CA Dly = 33
3120 22:50:09.154406 CS Dly: 6 (0~37)
3121 22:50:09.154545 ==
3122 22:50:09.154675 Dram Type= 6, Freq= 0, CH_1, rank 1
3123 22:50:09.154766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 22:50:09.154849 ==
3125 22:50:09.154931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 22:50:09.155015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3127 22:50:09.155071 [CA 0] Center 37 (7~67) winsize 61
3128 22:50:09.155125 [CA 1] Center 38 (8~68) winsize 61
3129 22:50:09.155178 [CA 2] Center 34 (4~65) winsize 62
3130 22:50:09.155243 [CA 3] Center 33 (3~64) winsize 62
3131 22:50:09.155299 [CA 4] Center 33 (3~64) winsize 62
3132 22:50:09.155551 [CA 5] Center 33 (3~64) winsize 62
3133 22:50:09.155656
3134 22:50:09.155795 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3135 22:50:09.155894
3136 22:50:09.156034 [CATrainingPosCal] consider 2 rank data
3137 22:50:09.156118 u2DelayCellTimex100 = 270/100 ps
3138 22:50:09.156200 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3139 22:50:09.156292 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3140 22:50:09.156374 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 22:50:09.156457 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3142 22:50:09.156548 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 22:50:09.156631 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3144 22:50:09.156712
3145 22:50:09.156803 CA PerBit enable=1, Macro0, CA PI delay=33
3146 22:50:09.156886
3147 22:50:09.156968 [CBTSetCACLKResult] CA Dly = 33
3148 22:50:09.157058 CS Dly: 7 (0~40)
3149 22:50:09.157139
3150 22:50:09.157223 ----->DramcWriteLeveling(PI) begin...
3151 22:50:09.157338 ==
3152 22:50:09.157446 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 22:50:09.157563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 22:50:09.157623 ==
3155 22:50:09.157709 Write leveling (Byte 0): 24 => 24
3156 22:50:09.157795 Write leveling (Byte 1): 26 => 26
3157 22:50:09.157849 DramcWriteLeveling(PI) end<-----
3158 22:50:09.157902
3159 22:50:09.157953 ==
3160 22:50:09.158023 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 22:50:09.158091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 22:50:09.158144 ==
3163 22:50:09.158197 [Gating] SW mode calibration
3164 22:50:09.158267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3165 22:50:09.158337 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3166 22:50:09.158391 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3167 22:50:09.158444 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 22:50:09.158515 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 22:50:09.158582 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 22:50:09.158635 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 22:50:09.158687 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 22:50:09.158756 0 15 24 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
3173 22:50:09.158823 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
3174 22:50:09.158876 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 22:50:09.158929 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 22:50:09.158999 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 22:50:09.159067 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 22:50:09.159120 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 22:50:09.159173 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 22:50:09.159256 1 0 24 | B1->B0 | 2323 3837 | 0 1 | (0 0) (1 1)
3181 22:50:09.159339 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 22:50:09.159391 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 22:50:09.159444 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 22:50:09.159496 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 22:50:09.159549 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 22:50:09.159602 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 22:50:09.159655 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 22:50:09.159707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3189 22:50:09.159792 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3190 22:50:09.159845 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3191 22:50:09.159898 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 22:50:09.159951 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 22:50:09.160003 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 22:50:09.160057 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 22:50:09.160110 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 22:50:09.160163 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 22:50:09.160215 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 22:50:09.160268 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 22:50:09.160321 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 22:50:09.160374 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 22:50:09.160426 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 22:50:09.160478 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 22:50:09.160531 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 22:50:09.160584 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3205 22:50:09.160636 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3206 22:50:09.160688 Total UI for P1: 0, mck2ui 16
3207 22:50:09.160742 best dqsien dly found for B0: ( 1, 3, 24)
3208 22:50:09.160795 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 22:50:09.160848 Total UI for P1: 0, mck2ui 16
3210 22:50:09.160900 best dqsien dly found for B1: ( 1, 3, 26)
3211 22:50:09.160953 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3212 22:50:09.161005 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3213 22:50:09.161057
3214 22:50:09.161109 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3215 22:50:09.161162 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3216 22:50:09.161216 [Gating] SW calibration Done
3217 22:50:09.161268 ==
3218 22:50:09.161320 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 22:50:09.161412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 22:50:09.161465 ==
3221 22:50:09.161518 RX Vref Scan: 0
3222 22:50:09.161570
3223 22:50:09.161622 RX Vref 0 -> 0, step: 1
3224 22:50:09.161675
3225 22:50:09.161727 RX Delay -40 -> 252, step: 8
3226 22:50:09.161780 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3227 22:50:09.161832 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3228 22:50:09.161885 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3229 22:50:09.161937 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3230 22:50:09.161989 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3231 22:50:09.162042 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3232 22:50:09.162094 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3233 22:50:09.162146 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3234 22:50:09.162198 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3235 22:50:09.162250 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3236 22:50:09.162496 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3237 22:50:09.162556 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3238 22:50:09.162610 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3239 22:50:09.162663 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3240 22:50:09.162731 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3241 22:50:09.162816 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3242 22:50:09.162916 ==
3243 22:50:09.162969 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 22:50:09.163022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 22:50:09.163076 ==
3246 22:50:09.163129 DQS Delay:
3247 22:50:09.163182 DQS0 = 0, DQS1 = 0
3248 22:50:09.163266 DQM Delay:
3249 22:50:09.163318 DQM0 = 117, DQM1 = 108
3250 22:50:09.163370 DQ Delay:
3251 22:50:09.163423 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3252 22:50:09.163475 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3253 22:50:09.163528 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3254 22:50:09.163580 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3255 22:50:09.163633
3256 22:50:09.163684
3257 22:50:09.163736 ==
3258 22:50:09.163789 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 22:50:09.163841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 22:50:09.163894 ==
3261 22:50:09.163946
3262 22:50:09.163997
3263 22:50:09.164050 TX Vref Scan disable
3264 22:50:09.164102 == TX Byte 0 ==
3265 22:50:09.164155 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3266 22:50:09.164208 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3267 22:50:09.164261 == TX Byte 1 ==
3268 22:50:09.164313 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3269 22:50:09.164366 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3270 22:50:09.164419 ==
3271 22:50:09.164471 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 22:50:09.164525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 22:50:09.164577 ==
3274 22:50:09.164630 TX Vref=22, minBit 9, minWin=24, winSum=412
3275 22:50:09.164683 TX Vref=24, minBit 8, minWin=25, winSum=418
3276 22:50:09.164736 TX Vref=26, minBit 10, minWin=25, winSum=424
3277 22:50:09.164789 TX Vref=28, minBit 10, minWin=25, winSum=431
3278 22:50:09.164841 TX Vref=30, minBit 9, minWin=25, winSum=431
3279 22:50:09.164894 TX Vref=32, minBit 9, minWin=25, winSum=425
3280 22:50:09.164946 [TxChooseVref] Worse bit 10, Min win 25, Win sum 431, Final Vref 28
3281 22:50:09.164999
3282 22:50:09.165051 Final TX Range 1 Vref 28
3283 22:50:09.165104
3284 22:50:09.165155 ==
3285 22:50:09.165208 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 22:50:09.165259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 22:50:09.165312 ==
3288 22:50:09.165405
3289 22:50:09.165457
3290 22:50:09.165508 TX Vref Scan disable
3291 22:50:09.165561 == TX Byte 0 ==
3292 22:50:09.165614 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3293 22:50:09.165667 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3294 22:50:09.165719 == TX Byte 1 ==
3295 22:50:09.165771 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3296 22:50:09.165823 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3297 22:50:09.165876
3298 22:50:09.165928 [DATLAT]
3299 22:50:09.165979 Freq=1200, CH1 RK0
3300 22:50:09.166031
3301 22:50:09.166083 DATLAT Default: 0xd
3302 22:50:09.166135 0, 0xFFFF, sum = 0
3303 22:50:09.166188 1, 0xFFFF, sum = 0
3304 22:50:09.166240 2, 0xFFFF, sum = 0
3305 22:50:09.166310 3, 0xFFFF, sum = 0
3306 22:50:09.166411 4, 0xFFFF, sum = 0
3307 22:50:09.166464 5, 0xFFFF, sum = 0
3308 22:50:09.166516 6, 0xFFFF, sum = 0
3309 22:50:09.166569 7, 0xFFFF, sum = 0
3310 22:50:09.166621 8, 0xFFFF, sum = 0
3311 22:50:09.166674 9, 0xFFFF, sum = 0
3312 22:50:09.166727 10, 0xFFFF, sum = 0
3313 22:50:09.166780 11, 0xFFFF, sum = 0
3314 22:50:09.166832 12, 0x0, sum = 1
3315 22:50:09.166884 13, 0x0, sum = 2
3316 22:50:09.166938 14, 0x0, sum = 3
3317 22:50:09.166990 15, 0x0, sum = 4
3318 22:50:09.167043 best_step = 13
3319 22:50:09.167094
3320 22:50:09.167144 ==
3321 22:50:09.167196 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 22:50:09.167281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 22:50:09.167334 ==
3324 22:50:09.167385 RX Vref Scan: 1
3325 22:50:09.167437
3326 22:50:09.167488 Set Vref Range= 32 -> 127
3327 22:50:09.167540
3328 22:50:09.167591 RX Vref 32 -> 127, step: 1
3329 22:50:09.167642
3330 22:50:09.167693 RX Delay -21 -> 252, step: 4
3331 22:50:09.167745
3332 22:50:09.167796 Set Vref, RX VrefLevel [Byte0]: 32
3333 22:50:09.167848 [Byte1]: 32
3334 22:50:09.167900
3335 22:50:09.167952 Set Vref, RX VrefLevel [Byte0]: 33
3336 22:50:09.168004 [Byte1]: 33
3337 22:50:09.168055
3338 22:50:09.168107 Set Vref, RX VrefLevel [Byte0]: 34
3339 22:50:09.168161 [Byte1]: 34
3340 22:50:09.168213
3341 22:50:09.168286 Set Vref, RX VrefLevel [Byte0]: 35
3342 22:50:09.168340 [Byte1]: 35
3343 22:50:09.168392
3344 22:50:09.168444 Set Vref, RX VrefLevel [Byte0]: 36
3345 22:50:09.168582 [Byte1]: 36
3346 22:50:09.168651
3347 22:50:09.168704 Set Vref, RX VrefLevel [Byte0]: 37
3348 22:50:09.168774 [Byte1]: 37
3349 22:50:09.168828
3350 22:50:09.168880 Set Vref, RX VrefLevel [Byte0]: 38
3351 22:50:09.168965 [Byte1]: 38
3352 22:50:09.169066
3353 22:50:09.169119 Set Vref, RX VrefLevel [Byte0]: 39
3354 22:50:09.169172 [Byte1]: 39
3355 22:50:09.169230
3356 22:50:09.169317 Set Vref, RX VrefLevel [Byte0]: 40
3357 22:50:09.169424 [Byte1]: 40
3358 22:50:09.169487
3359 22:50:09.169545 Set Vref, RX VrefLevel [Byte0]: 41
3360 22:50:09.169597 [Byte1]: 41
3361 22:50:09.169650
3362 22:50:09.169702 Set Vref, RX VrefLevel [Byte0]: 42
3363 22:50:09.169771 [Byte1]: 42
3364 22:50:09.169825
3365 22:50:09.169877 Set Vref, RX VrefLevel [Byte0]: 43
3366 22:50:09.169929 [Byte1]: 43
3367 22:50:09.169994
3368 22:50:09.170049 Set Vref, RX VrefLevel [Byte0]: 44
3369 22:50:09.170101 [Byte1]: 44
3370 22:50:09.170154
3371 22:50:09.170206 Set Vref, RX VrefLevel [Byte0]: 45
3372 22:50:09.170275 [Byte1]: 45
3373 22:50:09.170329
3374 22:50:09.170381 Set Vref, RX VrefLevel [Byte0]: 46
3375 22:50:09.170433 [Byte1]: 46
3376 22:50:09.170499
3377 22:50:09.170554 Set Vref, RX VrefLevel [Byte0]: 47
3378 22:50:09.170607 [Byte1]: 47
3379 22:50:09.170659
3380 22:50:09.170711 Set Vref, RX VrefLevel [Byte0]: 48
3381 22:50:09.170781 [Byte1]: 48
3382 22:50:09.170835
3383 22:50:09.170886 Set Vref, RX VrefLevel [Byte0]: 49
3384 22:50:09.170938 [Byte1]: 49
3385 22:50:09.171003
3386 22:50:09.171058 Set Vref, RX VrefLevel [Byte0]: 50
3387 22:50:09.171111 [Byte1]: 50
3388 22:50:09.171162
3389 22:50:09.171215 Set Vref, RX VrefLevel [Byte0]: 51
3390 22:50:09.171280 [Byte1]: 51
3391 22:50:09.171333
3392 22:50:09.171385 Set Vref, RX VrefLevel [Byte0]: 52
3393 22:50:09.171437 [Byte1]: 52
3394 22:50:09.171503
3395 22:50:09.171601 Set Vref, RX VrefLevel [Byte0]: 53
3396 22:50:09.171702 [Byte1]: 53
3397 22:50:09.171779
3398 22:50:09.171833 Set Vref, RX VrefLevel [Byte0]: 54
3399 22:50:09.172099 [Byte1]: 54
3400 22:50:09.172175
3401 22:50:09.172240 Set Vref, RX VrefLevel [Byte0]: 55
3402 22:50:09.172315 [Byte1]: 55
3403 22:50:09.172402
3404 22:50:09.172529 Set Vref, RX VrefLevel [Byte0]: 56
3405 22:50:09.172585 [Byte1]: 56
3406 22:50:09.172638
3407 22:50:09.172691 Set Vref, RX VrefLevel [Byte0]: 57
3408 22:50:09.172759 [Byte1]: 57
3409 22:50:09.172814
3410 22:50:09.172866 Set Vref, RX VrefLevel [Byte0]: 58
3411 22:50:09.172918 [Byte1]: 58
3412 22:50:09.172973
3413 22:50:09.173036 Set Vref, RX VrefLevel [Byte0]: 59
3414 22:50:09.173090 [Byte1]: 59
3415 22:50:09.173142
3416 22:50:09.173194 Set Vref, RX VrefLevel [Byte0]: 60
3417 22:50:09.173271 [Byte1]: 60
3418 22:50:09.173394
3419 22:50:09.173523 Set Vref, RX VrefLevel [Byte0]: 61
3420 22:50:09.173611 [Byte1]: 61
3421 22:50:09.173679
3422 22:50:09.173748 Set Vref, RX VrefLevel [Byte0]: 62
3423 22:50:09.173818 [Byte1]: 62
3424 22:50:09.173871
3425 22:50:09.173923 Set Vref, RX VrefLevel [Byte0]: 63
3426 22:50:09.173993 [Byte1]: 63
3427 22:50:09.174060
3428 22:50:09.174112 Set Vref, RX VrefLevel [Byte0]: 64
3429 22:50:09.174164 [Byte1]: 64
3430 22:50:09.174230
3431 22:50:09.174296 Set Vref, RX VrefLevel [Byte0]: 65
3432 22:50:09.174349 [Byte1]: 65
3433 22:50:09.174400
3434 22:50:09.174452 Set Vref, RX VrefLevel [Byte0]: 66
3435 22:50:09.174534 [Byte1]: 66
3436 22:50:09.174586
3437 22:50:09.174638 Set Vref, RX VrefLevel [Byte0]: 67
3438 22:50:09.174690 [Byte1]: 67
3439 22:50:09.174758
3440 22:50:09.174825 Set Vref, RX VrefLevel [Byte0]: 68
3441 22:50:09.174877 [Byte1]: 68
3442 22:50:09.174929
3443 22:50:09.174997 Set Vref, RX VrefLevel [Byte0]: 69
3444 22:50:09.175063 [Byte1]: 69
3445 22:50:09.175147
3446 22:50:09.175199 Set Vref, RX VrefLevel [Byte0]: 70
3447 22:50:09.175251 [Byte1]: 70
3448 22:50:09.175304
3449 22:50:09.175356 Set Vref, RX VrefLevel [Byte0]: 71
3450 22:50:09.175408 [Byte1]: 71
3451 22:50:09.175508
3452 22:50:09.175606 Final RX Vref Byte 0 = 46 to rank0
3453 22:50:09.175659 Final RX Vref Byte 1 = 57 to rank0
3454 22:50:09.175722 Final RX Vref Byte 0 = 46 to rank1
3455 22:50:09.175811 Final RX Vref Byte 1 = 57 to rank1==
3456 22:50:09.175864 Dram Type= 6, Freq= 0, CH_1, rank 0
3457 22:50:09.175917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 22:50:09.175970 ==
3459 22:50:09.176060 DQS Delay:
3460 22:50:09.176112 DQS0 = 0, DQS1 = 0
3461 22:50:09.176165 DQM Delay:
3462 22:50:09.176216 DQM0 = 115, DQM1 = 110
3463 22:50:09.176269 DQ Delay:
3464 22:50:09.176321 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3465 22:50:09.176374 DQ4 =112, DQ5 =126, DQ6 =124, DQ7 =114
3466 22:50:09.176427 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =100
3467 22:50:09.176479 DQ12 =118, DQ13 =120, DQ14 =120, DQ15 =120
3468 22:50:09.176531
3469 22:50:09.176582
3470 22:50:09.176633 [DQSOSCAuto] RK0, (LSB)MR18= 0x6fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3471 22:50:09.176687 CH1 RK0: MR19=403, MR18=6FA
3472 22:50:09.176738 CH1_RK0: MR19=0x403, MR18=0x6FA, DQSOSC=407, MR23=63, INC=39, DEC=26
3473 22:50:09.176791
3474 22:50:09.176842 ----->DramcWriteLeveling(PI) begin...
3475 22:50:09.176902 ==
3476 22:50:09.176987 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 22:50:09.177043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 22:50:09.177097 ==
3479 22:50:09.177149 Write leveling (Byte 0): 24 => 24
3480 22:50:09.177202 Write leveling (Byte 1): 28 => 28
3481 22:50:09.177255 DramcWriteLeveling(PI) end<-----
3482 22:50:09.177307
3483 22:50:09.177402 ==
3484 22:50:09.177455 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 22:50:09.177507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 22:50:09.177560 ==
3487 22:50:09.177613 [Gating] SW mode calibration
3488 22:50:09.177665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3489 22:50:09.177717 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3490 22:50:09.177770 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 22:50:09.177823 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 22:50:09.177876 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 22:50:09.177928 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 22:50:09.177980 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 22:50:09.178032 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 22:50:09.178085 0 15 24 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
3497 22:50:09.178138 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
3498 22:50:09.178190 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 22:50:09.178265 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 22:50:09.178352 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 22:50:09.178445 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 22:50:09.178539 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 22:50:09.178633 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 22:50:09.178754 1 0 24 | B1->B0 | 3e3e 2d2c | 0 1 | (0 0) (1 1)
3505 22:50:09.178872 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 22:50:09.178961 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 22:50:09.179050 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 22:50:09.179138 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 22:50:09.179254 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 22:50:09.179341 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 22:50:09.179428 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 22:50:09.179514 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 22:50:09.179600 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3514 22:50:09.179681 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 22:50:09.179765 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 22:50:09.179849 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 22:50:09.179936 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 22:50:09.180021 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 22:50:09.180106 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 22:50:09.180192 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 22:50:09.180496 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 22:50:09.180599 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 22:50:09.180693 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 22:50:09.180779 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 22:50:09.180867 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 22:50:09.180957 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 22:50:09.181046 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 22:50:09.181137 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3529 22:50:09.181226 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3530 22:50:09.181312 Total UI for P1: 0, mck2ui 16
3531 22:50:09.181443 best dqsien dly found for B1: ( 1, 3, 24)
3532 22:50:09.181528 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 22:50:09.181614 Total UI for P1: 0, mck2ui 16
3534 22:50:09.181700 best dqsien dly found for B0: ( 1, 3, 28)
3535 22:50:09.181790 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3536 22:50:09.181878 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3537 22:50:09.181965
3538 22:50:09.182053 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3539 22:50:09.182141 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3540 22:50:09.182228 [Gating] SW calibration Done
3541 22:50:09.182366 ==
3542 22:50:09.182489 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 22:50:09.182624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 22:50:09.182713 ==
3545 22:50:09.182802 RX Vref Scan: 0
3546 22:50:09.182886
3547 22:50:09.182971 RX Vref 0 -> 0, step: 1
3548 22:50:09.183058
3549 22:50:09.183144 RX Delay -40 -> 252, step: 8
3550 22:50:09.183282 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3551 22:50:09.183433 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3552 22:50:09.183546 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3553 22:50:09.183728 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3554 22:50:09.183833 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3555 22:50:09.183982 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3556 22:50:09.184119 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3557 22:50:09.184209 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3558 22:50:09.184298 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3559 22:50:09.184387 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3560 22:50:09.184474 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3561 22:50:09.184563 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3562 22:50:09.184651 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3563 22:50:09.184742 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3564 22:50:09.184830 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3565 22:50:09.184920 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3566 22:50:09.185018 ==
3567 22:50:09.185111 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 22:50:09.185205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 22:50:09.185300 ==
3570 22:50:09.185416 DQS Delay:
3571 22:50:09.185508 DQS0 = 0, DQS1 = 0
3572 22:50:09.185599 DQM Delay:
3573 22:50:09.185691 DQM0 = 117, DQM1 = 110
3574 22:50:09.185784 DQ Delay:
3575 22:50:09.185877 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3576 22:50:09.185973 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3577 22:50:09.186068 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103
3578 22:50:09.186163 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3579 22:50:09.186255
3580 22:50:09.186341
3581 22:50:09.186433 ==
3582 22:50:09.186530 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 22:50:09.186623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 22:50:09.186717 ==
3585 22:50:09.186803
3586 22:50:09.186890
3587 22:50:09.186977 TX Vref Scan disable
3588 22:50:09.187065 == TX Byte 0 ==
3589 22:50:09.187153 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3590 22:50:09.187244 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3591 22:50:09.187332 == TX Byte 1 ==
3592 22:50:09.187420 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3593 22:50:09.187508 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3594 22:50:09.187600 ==
3595 22:50:09.187689 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 22:50:09.187781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 22:50:09.187874 ==
3598 22:50:09.187965 TX Vref=22, minBit 11, minWin=24, winSum=420
3599 22:50:09.188058 TX Vref=24, minBit 9, minWin=25, winSum=428
3600 22:50:09.188146 TX Vref=26, minBit 9, minWin=25, winSum=430
3601 22:50:09.188235 TX Vref=28, minBit 3, minWin=26, winSum=436
3602 22:50:09.188320 TX Vref=30, minBit 9, minWin=26, winSum=435
3603 22:50:09.188408 TX Vref=32, minBit 7, minWin=26, winSum=435
3604 22:50:09.188497 [TxChooseVref] Worse bit 3, Min win 26, Win sum 436, Final Vref 28
3605 22:50:09.188587
3606 22:50:09.188676 Final TX Range 1 Vref 28
3607 22:50:09.188766
3608 22:50:09.188853 ==
3609 22:50:09.188941 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 22:50:09.189026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 22:50:09.189112 ==
3612 22:50:09.189199
3613 22:50:09.189289
3614 22:50:09.189425 TX Vref Scan disable
3615 22:50:09.189520 == TX Byte 0 ==
3616 22:50:09.189610 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3617 22:50:09.189705 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3618 22:50:09.189796 == TX Byte 1 ==
3619 22:50:09.189884 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3620 22:50:09.189973 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3621 22:50:09.190067
3622 22:50:09.190156 [DATLAT]
3623 22:50:09.190239 Freq=1200, CH1 RK1
3624 22:50:09.190329
3625 22:50:09.190420 DATLAT Default: 0xd
3626 22:50:09.190510 0, 0xFFFF, sum = 0
3627 22:50:09.190602 1, 0xFFFF, sum = 0
3628 22:50:09.190694 2, 0xFFFF, sum = 0
3629 22:50:09.190786 3, 0xFFFF, sum = 0
3630 22:50:09.190879 4, 0xFFFF, sum = 0
3631 22:50:09.190973 5, 0xFFFF, sum = 0
3632 22:50:09.191065 6, 0xFFFF, sum = 0
3633 22:50:09.191157 7, 0xFFFF, sum = 0
3634 22:50:09.191248 8, 0xFFFF, sum = 0
3635 22:50:09.191339 9, 0xFFFF, sum = 0
3636 22:50:09.191438 10, 0xFFFF, sum = 0
3637 22:50:09.191535 11, 0xFFFF, sum = 0
3638 22:50:09.191632 12, 0x0, sum = 1
3639 22:50:09.191730 13, 0x0, sum = 2
3640 22:50:09.191824 14, 0x0, sum = 3
3641 22:50:09.191923 15, 0x0, sum = 4
3642 22:50:09.192021 best_step = 13
3643 22:50:09.192118
3644 22:50:09.192215 ==
3645 22:50:09.192311 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 22:50:09.192405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 22:50:09.192494 ==
3648 22:50:09.192582 RX Vref Scan: 0
3649 22:50:09.192669
3650 22:50:09.192759 RX Vref 0 -> 0, step: 1
3651 22:50:09.192846
3652 22:50:09.192936 RX Delay -21 -> 252, step: 4
3653 22:50:09.193028 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3654 22:50:09.193122 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3655 22:50:09.193216 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3656 22:50:09.193309 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3657 22:50:09.193445 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3658 22:50:09.193538 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3659 22:50:09.193858 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3660 22:50:09.193964 iDelay=199, Bit 7, Center 112 (47 ~ 178) 132
3661 22:50:09.194062 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3662 22:50:09.194156 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3663 22:50:09.194249 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3664 22:50:09.194341 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3665 22:50:09.194432 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3666 22:50:09.194523 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3667 22:50:09.194613 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3668 22:50:09.194703 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3669 22:50:09.194790 ==
3670 22:50:09.194881 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 22:50:09.194972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 22:50:09.195062 ==
3673 22:50:09.195152 DQS Delay:
3674 22:50:09.195242 DQS0 = 0, DQS1 = 0
3675 22:50:09.195330 DQM Delay:
3676 22:50:09.195420 DQM0 = 116, DQM1 = 110
3677 22:50:09.195510 DQ Delay:
3678 22:50:09.195606 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =112
3679 22:50:09.195698 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =112
3680 22:50:09.195789 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3681 22:50:09.195878 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3682 22:50:09.195965
3683 22:50:09.196051
3684 22:50:09.196136 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
3685 22:50:09.196226 CH1 RK1: MR19=303, MR18=F4F0
3686 22:50:09.196319 CH1_RK1: MR19=0x303, MR18=0xF4F0, DQSOSC=415, MR23=63, INC=38, DEC=25
3687 22:50:09.196407 [RxdqsGatingPostProcess] freq 1200
3688 22:50:09.196496 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3689 22:50:09.196582 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 22:50:09.196667 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 22:50:09.196757 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 22:50:09.196842 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 22:50:09.196926 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 22:50:09.197014 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 22:50:09.197102 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 22:50:09.197192 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 22:50:09.197280 Pre-setting of DQS Precalculation
3698 22:50:09.197417 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3699 22:50:09.197512 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3700 22:50:09.197604 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3701 22:50:09.197696
3702 22:50:09.197785
3703 22:50:09.197873 [Calibration Summary] 2400 Mbps
3704 22:50:09.197962 CH 0, Rank 0
3705 22:50:09.198054 SW Impedance : PASS
3706 22:50:09.198144 DUTY Scan : NO K
3707 22:50:09.198233 ZQ Calibration : PASS
3708 22:50:09.198317 Jitter Meter : NO K
3709 22:50:09.198402 CBT Training : PASS
3710 22:50:09.198498 Write leveling : PASS
3711 22:50:09.198597 RX DQS gating : PASS
3712 22:50:09.198688 RX DQ/DQS(RDDQC) : PASS
3713 22:50:09.198777 TX DQ/DQS : PASS
3714 22:50:09.198865 RX DATLAT : PASS
3715 22:50:09.198956 RX DQ/DQS(Engine): PASS
3716 22:50:09.199046 TX OE : NO K
3717 22:50:09.199137 All Pass.
3718 22:50:09.199228
3719 22:50:09.199316 CH 0, Rank 1
3720 22:50:09.199404 SW Impedance : PASS
3721 22:50:09.199490 DUTY Scan : NO K
3722 22:50:09.199582 ZQ Calibration : PASS
3723 22:50:09.199673 Jitter Meter : NO K
3724 22:50:09.199760 CBT Training : PASS
3725 22:50:09.199849 Write leveling : PASS
3726 22:50:09.199936 RX DQS gating : PASS
3727 22:50:09.200026 RX DQ/DQS(RDDQC) : PASS
3728 22:50:09.200113 TX DQ/DQS : PASS
3729 22:50:09.200199 RX DATLAT : PASS
3730 22:50:09.200290 RX DQ/DQS(Engine): PASS
3731 22:50:09.200381 TX OE : NO K
3732 22:50:09.200475 All Pass.
3733 22:50:09.200570
3734 22:50:09.200663 CH 1, Rank 0
3735 22:50:09.200756 SW Impedance : PASS
3736 22:50:09.200849 DUTY Scan : NO K
3737 22:50:09.200936 ZQ Calibration : PASS
3738 22:50:09.201020 Jitter Meter : NO K
3739 22:50:09.201111 CBT Training : PASS
3740 22:50:09.201203 Write leveling : PASS
3741 22:50:09.201297 RX DQS gating : PASS
3742 22:50:09.201445 RX DQ/DQS(RDDQC) : PASS
3743 22:50:09.201529 TX DQ/DQS : PASS
3744 22:50:09.201619 RX DATLAT : PASS
3745 22:50:09.201709 RX DQ/DQS(Engine): PASS
3746 22:50:09.201799 TX OE : NO K
3747 22:50:09.201887 All Pass.
3748 22:50:09.201979
3749 22:50:09.202071 CH 1, Rank 1
3750 22:50:09.202163 SW Impedance : PASS
3751 22:50:09.202253 DUTY Scan : NO K
3752 22:50:09.202345 ZQ Calibration : PASS
3753 22:50:09.202437 Jitter Meter : NO K
3754 22:50:09.202527 CBT Training : PASS
3755 22:50:09.202620 Write leveling : PASS
3756 22:50:09.202711 RX DQS gating : PASS
3757 22:50:09.202802 RX DQ/DQS(RDDQC) : PASS
3758 22:50:09.202886 TX DQ/DQS : PASS
3759 22:50:09.202975 RX DATLAT : PASS
3760 22:50:09.203068 RX DQ/DQS(Engine): PASS
3761 22:50:09.203160 TX OE : NO K
3762 22:50:09.203252 All Pass.
3763 22:50:09.203344
3764 22:50:09.203435 DramC Write-DBI off
3765 22:50:09.203532 PER_BANK_REFRESH: Hybrid Mode
3766 22:50:09.203627 TX_TRACKING: ON
3767 22:50:09.203721 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3768 22:50:09.203818 [FAST_K] Save calibration result to emmc
3769 22:50:09.203913 dramc_set_vcore_voltage set vcore to 650000
3770 22:50:09.204005 Read voltage for 600, 5
3771 22:50:09.204098 Vio18 = 0
3772 22:50:09.204191 Vcore = 650000
3773 22:50:09.204284 Vdram = 0
3774 22:50:09.204377 Vddq = 0
3775 22:50:09.204471 Vmddr = 0
3776 22:50:09.204566 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3777 22:50:09.204662 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3778 22:50:09.204759 MEM_TYPE=3, freq_sel=19
3779 22:50:09.204852 sv_algorithm_assistance_LP4_1600
3780 22:50:09.204947 ============ PULL DRAM RESETB DOWN ============
3781 22:50:09.205045 ========== PULL DRAM RESETB DOWN end =========
3782 22:50:09.205144 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3783 22:50:09.205242 ===================================
3784 22:50:09.205343 LPDDR4 DRAM CONFIGURATION
3785 22:50:09.205438 ===================================
3786 22:50:09.205533 EX_ROW_EN[0] = 0x0
3787 22:50:09.205626 EX_ROW_EN[1] = 0x0
3788 22:50:09.205720 LP4Y_EN = 0x0
3789 22:50:09.205813 WORK_FSP = 0x0
3790 22:50:09.205906 WL = 0x2
3791 22:50:09.206000 RL = 0x2
3792 22:50:09.206092 BL = 0x2
3793 22:50:09.206184 RPST = 0x0
3794 22:50:09.206275 RD_PRE = 0x0
3795 22:50:09.206362 WR_PRE = 0x1
3796 22:50:09.206448 WR_PST = 0x0
3797 22:50:09.206533 DBI_WR = 0x0
3798 22:50:09.206617 DBI_RD = 0x0
3799 22:50:09.206700 OTF = 0x1
3800 22:50:09.207018 ===================================
3801 22:50:09.207119 ===================================
3802 22:50:09.207251 ANA top config
3803 22:50:09.207350 ===================================
3804 22:50:09.207452 DLL_ASYNC_EN = 0
3805 22:50:09.207550 ALL_SLAVE_EN = 1
3806 22:50:09.207648 NEW_RANK_MODE = 1
3807 22:50:09.207744 DLL_IDLE_MODE = 1
3808 22:50:09.207837 LP45_APHY_COMB_EN = 1
3809 22:50:09.207932 TX_ODT_DIS = 1
3810 22:50:09.208030 NEW_8X_MODE = 1
3811 22:50:09.208120 ===================================
3812 22:50:09.208210 ===================================
3813 22:50:09.208304 data_rate = 1200
3814 22:50:09.208393 CKR = 1
3815 22:50:09.208486 DQ_P2S_RATIO = 8
3816 22:50:09.208588 ===================================
3817 22:50:09.208694 CA_P2S_RATIO = 8
3818 22:50:09.208780 DQ_CA_OPEN = 0
3819 22:50:09.208862 DQ_SEMI_OPEN = 0
3820 22:50:09.208960 CA_SEMI_OPEN = 0
3821 22:50:09.209067 CA_FULL_RATE = 0
3822 22:50:09.209172 DQ_CKDIV4_EN = 1
3823 22:50:09.209278 CA_CKDIV4_EN = 1
3824 22:50:09.209425 CA_PREDIV_EN = 0
3825 22:50:09.209529 PH8_DLY = 0
3826 22:50:09.209635 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3827 22:50:09.209739 DQ_AAMCK_DIV = 4
3828 22:50:09.209842 CA_AAMCK_DIV = 4
3829 22:50:09.209946 CA_ADMCK_DIV = 4
3830 22:50:09.210052 DQ_TRACK_CA_EN = 0
3831 22:50:09.210157 CA_PICK = 600
3832 22:50:09.210263 CA_MCKIO = 600
3833 22:50:09.210370 MCKIO_SEMI = 0
3834 22:50:09.210475 PLL_FREQ = 2288
3835 22:50:09.210584 DQ_UI_PI_RATIO = 32
3836 22:50:09.210692 CA_UI_PI_RATIO = 0
3837 22:50:09.210798 ===================================
3838 22:50:09.210903 ===================================
3839 22:50:09.211012 memory_type:LPDDR4
3840 22:50:09.211120 GP_NUM : 10
3841 22:50:09.211243 SRAM_EN : 1
3842 22:50:09.211354 MD32_EN : 0
3843 22:50:09.211493 ===================================
3844 22:50:09.211597 [ANA_INIT] >>>>>>>>>>>>>>
3845 22:50:09.211744 <<<<<< [CONFIGURE PHASE]: ANA_TX
3846 22:50:09.211857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3847 22:50:09.212257 ===================================
3848 22:50:09.215322 data_rate = 1200,PCW = 0X5800
3849 22:50:09.218852 ===================================
3850 22:50:09.222223 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3851 22:50:09.228637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3852 22:50:09.235165 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 22:50:09.238425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3854 22:50:09.242051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3855 22:50:09.245084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3856 22:50:09.248348 [ANA_INIT] flow start
3857 22:50:09.248450 [ANA_INIT] PLL >>>>>>>>
3858 22:50:09.251576 [ANA_INIT] PLL <<<<<<<<
3859 22:50:09.255036 [ANA_INIT] MIDPI >>>>>>>>
3860 22:50:09.258088 [ANA_INIT] MIDPI <<<<<<<<
3861 22:50:09.258190 [ANA_INIT] DLL >>>>>>>>
3862 22:50:09.261572 [ANA_INIT] flow end
3863 22:50:09.264496 ============ LP4 DIFF to SE enter ============
3864 22:50:09.268300 ============ LP4 DIFF to SE exit ============
3865 22:50:09.271341 [ANA_INIT] <<<<<<<<<<<<<
3866 22:50:09.274512 [Flow] Enable top DCM control >>>>>
3867 22:50:09.278313 [Flow] Enable top DCM control <<<<<
3868 22:50:09.281062 Enable DLL master slave shuffle
3869 22:50:09.287755 ==============================================================
3870 22:50:09.287873 Gating Mode config
3871 22:50:09.294313 ==============================================================
3872 22:50:09.294432 Config description:
3873 22:50:09.304395 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3874 22:50:09.310795 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3875 22:50:09.317632 SELPH_MODE 0: By rank 1: By Phase
3876 22:50:09.320847 ==============================================================
3877 22:50:09.323802 GAT_TRACK_EN = 1
3878 22:50:09.327530 RX_GATING_MODE = 2
3879 22:50:09.330775 RX_GATING_TRACK_MODE = 2
3880 22:50:09.334079 SELPH_MODE = 1
3881 22:50:09.337075 PICG_EARLY_EN = 1
3882 22:50:09.340505 VALID_LAT_VALUE = 1
3883 22:50:09.347142 ==============================================================
3884 22:50:09.350269 Enter into Gating configuration >>>>
3885 22:50:09.353669 Exit from Gating configuration <<<<
3886 22:50:09.357308 Enter into DVFS_PRE_config >>>>>
3887 22:50:09.366627 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3888 22:50:09.370014 Exit from DVFS_PRE_config <<<<<
3889 22:50:09.373628 Enter into PICG configuration >>>>
3890 22:50:09.376689 Exit from PICG configuration <<<<
3891 22:50:09.379970 [RX_INPUT] configuration >>>>>
3892 22:50:09.380062 [RX_INPUT] configuration <<<<<
3893 22:50:09.386658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3894 22:50:09.393494 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3895 22:50:09.396610 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3896 22:50:09.403470 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3897 22:50:09.409782 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 22:50:09.416805 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 22:50:09.419619 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3900 22:50:09.423015 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3901 22:50:09.429475 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3902 22:50:09.433285 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3903 22:50:09.436015 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3904 22:50:09.443223 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 22:50:09.446169 ===================================
3906 22:50:09.446274 LPDDR4 DRAM CONFIGURATION
3907 22:50:09.449684 ===================================
3908 22:50:09.453138 EX_ROW_EN[0] = 0x0
3909 22:50:09.456221 EX_ROW_EN[1] = 0x0
3910 22:50:09.456338 LP4Y_EN = 0x0
3911 22:50:09.459413 WORK_FSP = 0x0
3912 22:50:09.459490 WL = 0x2
3913 22:50:09.462764 RL = 0x2
3914 22:50:09.462836 BL = 0x2
3915 22:50:09.466070 RPST = 0x0
3916 22:50:09.466140 RD_PRE = 0x0
3917 22:50:09.469367 WR_PRE = 0x1
3918 22:50:09.469447 WR_PST = 0x0
3919 22:50:09.472824 DBI_WR = 0x0
3920 22:50:09.472918 DBI_RD = 0x0
3921 22:50:09.476448 OTF = 0x1
3922 22:50:09.479193 ===================================
3923 22:50:09.482659 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3924 22:50:09.485929 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3925 22:50:09.492387 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 22:50:09.495585 ===================================
3927 22:50:09.495663 LPDDR4 DRAM CONFIGURATION
3928 22:50:09.499095 ===================================
3929 22:50:09.502963 EX_ROW_EN[0] = 0x10
3930 22:50:09.505623 EX_ROW_EN[1] = 0x0
3931 22:50:09.505705 LP4Y_EN = 0x0
3932 22:50:09.508964 WORK_FSP = 0x0
3933 22:50:09.509076 WL = 0x2
3934 22:50:09.512144 RL = 0x2
3935 22:50:09.512251 BL = 0x2
3936 22:50:09.516145 RPST = 0x0
3937 22:50:09.516248 RD_PRE = 0x0
3938 22:50:09.518775 WR_PRE = 0x1
3939 22:50:09.518866 WR_PST = 0x0
3940 22:50:09.522238 DBI_WR = 0x0
3941 22:50:09.522309 DBI_RD = 0x0
3942 22:50:09.525530 OTF = 0x1
3943 22:50:09.529147 ===================================
3944 22:50:09.535379 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3945 22:50:09.538850 nWR fixed to 30
3946 22:50:09.538953 [ModeRegInit_LP4] CH0 RK0
3947 22:50:09.541970 [ModeRegInit_LP4] CH0 RK1
3948 22:50:09.545137 [ModeRegInit_LP4] CH1 RK0
3949 22:50:09.548674 [ModeRegInit_LP4] CH1 RK1
3950 22:50:09.548755 match AC timing 17
3951 22:50:09.555078 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3952 22:50:09.558371 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3953 22:50:09.561852 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3954 22:50:09.568568 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3955 22:50:09.571605 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3956 22:50:09.571707 ==
3957 22:50:09.574944 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 22:50:09.578131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 22:50:09.578230 ==
3960 22:50:09.584888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 22:50:09.591728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3962 22:50:09.594515 [CA 0] Center 36 (6~66) winsize 61
3963 22:50:09.597876 [CA 1] Center 36 (6~66) winsize 61
3964 22:50:09.601168 [CA 2] Center 34 (4~65) winsize 62
3965 22:50:09.604442 [CA 3] Center 34 (4~65) winsize 62
3966 22:50:09.608005 [CA 4] Center 33 (3~64) winsize 62
3967 22:50:09.611117 [CA 5] Center 33 (3~64) winsize 62
3968 22:50:09.611227
3969 22:50:09.614694 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3970 22:50:09.614797
3971 22:50:09.617853 [CATrainingPosCal] consider 1 rank data
3972 22:50:09.620726 u2DelayCellTimex100 = 270/100 ps
3973 22:50:09.624126 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 22:50:09.627896 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 22:50:09.631255 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 22:50:09.633822 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3977 22:50:09.640804 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 22:50:09.644232 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 22:50:09.644333
3980 22:50:09.647226 CA PerBit enable=1, Macro0, CA PI delay=33
3981 22:50:09.647323
3982 22:50:09.650627 [CBTSetCACLKResult] CA Dly = 33
3983 22:50:09.650726 CS Dly: 4 (0~35)
3984 22:50:09.650814 ==
3985 22:50:09.653771 Dram Type= 6, Freq= 0, CH_0, rank 1
3986 22:50:09.660624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 22:50:09.660723 ==
3988 22:50:09.663569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 22:50:09.670091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3990 22:50:09.673645 [CA 0] Center 35 (5~66) winsize 62
3991 22:50:09.676638 [CA 1] Center 36 (6~66) winsize 61
3992 22:50:09.680111 [CA 2] Center 34 (4~64) winsize 61
3993 22:50:09.683639 [CA 3] Center 34 (4~64) winsize 61
3994 22:50:09.686752 [CA 4] Center 33 (3~64) winsize 62
3995 22:50:09.689769 [CA 5] Center 33 (3~64) winsize 62
3996 22:50:09.689851
3997 22:50:09.693238 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3998 22:50:09.693341
3999 22:50:09.696638 [CATrainingPosCal] consider 2 rank data
4000 22:50:09.700200 u2DelayCellTimex100 = 270/100 ps
4001 22:50:09.703150 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4002 22:50:09.709733 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4003 22:50:09.713214 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4004 22:50:09.716675 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4005 22:50:09.719923 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 22:50:09.722654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 22:50:09.722735
4008 22:50:09.726369 CA PerBit enable=1, Macro0, CA PI delay=33
4009 22:50:09.726451
4010 22:50:09.729644 [CBTSetCACLKResult] CA Dly = 33
4011 22:50:09.732706 CS Dly: 4 (0~36)
4012 22:50:09.732788
4013 22:50:09.736109 ----->DramcWriteLeveling(PI) begin...
4014 22:50:09.736193 ==
4015 22:50:09.739520 Dram Type= 6, Freq= 0, CH_0, rank 0
4016 22:50:09.742385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 22:50:09.742467 ==
4018 22:50:09.746194 Write leveling (Byte 0): 34 => 34
4019 22:50:09.748931 Write leveling (Byte 1): 29 => 29
4020 22:50:09.752107 DramcWriteLeveling(PI) end<-----
4021 22:50:09.752203
4022 22:50:09.752284 ==
4023 22:50:09.755730 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 22:50:09.758966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 22:50:09.759063 ==
4026 22:50:09.761899 [Gating] SW mode calibration
4027 22:50:09.768814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4028 22:50:09.775122 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4029 22:50:09.778608 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 22:50:09.785105 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 22:50:09.788112 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 22:50:09.791624 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4033 22:50:09.798534 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4034 22:50:09.801718 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 22:50:09.804844 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 22:50:09.811201 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 22:50:09.814508 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 22:50:09.818202 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 22:50:09.824102 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 22:50:09.827546 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4041 22:50:09.830954 0 10 16 | B1->B0 | 3535 4141 | 1 0 | (0 0) (0 0)
4042 22:50:09.837363 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 22:50:09.841117 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 22:50:09.844318 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 22:50:09.850554 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 22:50:09.853923 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 22:50:09.857285 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 22:50:09.863620 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4049 22:50:09.867198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 22:50:09.870821 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 22:50:09.877212 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 22:50:09.880516 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 22:50:09.883338 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 22:50:09.890361 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 22:50:09.893837 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 22:50:09.896686 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 22:50:09.903609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 22:50:09.906778 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 22:50:09.909869 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 22:50:09.916838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 22:50:09.919820 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 22:50:09.923059 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 22:50:09.929992 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 22:50:09.933107 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 22:50:09.936202 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4066 22:50:09.939864 Total UI for P1: 0, mck2ui 16
4067 22:50:09.942994 best dqsien dly found for B0: ( 0, 13, 14)
4068 22:50:09.949715 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 22:50:09.949808 Total UI for P1: 0, mck2ui 16
4070 22:50:09.956241 best dqsien dly found for B1: ( 0, 13, 16)
4071 22:50:09.959354 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4072 22:50:09.962692 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4073 22:50:09.962774
4074 22:50:09.966246 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4075 22:50:09.969795 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4076 22:50:09.972690 [Gating] SW calibration Done
4077 22:50:09.972808 ==
4078 22:50:09.975894 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 22:50:09.979557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 22:50:09.979650 ==
4081 22:50:09.982823 RX Vref Scan: 0
4082 22:50:09.982907
4083 22:50:09.982972 RX Vref 0 -> 0, step: 1
4084 22:50:09.985825
4085 22:50:09.985907 RX Delay -230 -> 252, step: 16
4086 22:50:09.992801 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4087 22:50:09.995709 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4088 22:50:09.999507 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4089 22:50:10.002251 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4090 22:50:10.009175 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4091 22:50:10.012141 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4092 22:50:10.015609 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4093 22:50:10.018784 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4094 22:50:10.022123 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4095 22:50:10.028851 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4096 22:50:10.032218 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4097 22:50:10.035465 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4098 22:50:10.038849 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4099 22:50:10.045251 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4100 22:50:10.048647 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4101 22:50:10.052127 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4102 22:50:10.052209 ==
4103 22:50:10.055259 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 22:50:10.062005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 22:50:10.062117 ==
4106 22:50:10.062221 DQS Delay:
4107 22:50:10.062323 DQS0 = 0, DQS1 = 0
4108 22:50:10.065057 DQM Delay:
4109 22:50:10.065140 DQM0 = 40, DQM1 = 29
4110 22:50:10.068621 DQ Delay:
4111 22:50:10.072348 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4112 22:50:10.074929 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4113 22:50:10.078416 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4114 22:50:10.081371 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4115 22:50:10.081457
4116 22:50:10.081523
4117 22:50:10.081583 ==
4118 22:50:10.113859 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 22:50:10.114023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 22:50:10.114174 ==
4121 22:50:10.114253
4122 22:50:10.114368
4123 22:50:10.114459 TX Vref Scan disable
4124 22:50:10.114530 == TX Byte 0 ==
4125 22:50:10.114603 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4126 22:50:10.114660 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4127 22:50:10.114717 == TX Byte 1 ==
4128 22:50:10.114784 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4129 22:50:10.114839 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4130 22:50:10.114892 ==
4131 22:50:10.115133 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 22:50:10.117513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 22:50:10.120680 ==
4134 22:50:10.120779
4135 22:50:10.120843
4136 22:50:10.120920 TX Vref Scan disable
4137 22:50:10.124710 == TX Byte 0 ==
4138 22:50:10.127923 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4139 22:50:10.135050 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4140 22:50:10.135192 == TX Byte 1 ==
4141 22:50:10.138364 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4142 22:50:10.145017 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4143 22:50:10.145101
4144 22:50:10.145166 [DATLAT]
4145 22:50:10.145227 Freq=600, CH0 RK0
4146 22:50:10.145285
4147 22:50:10.147793 DATLAT Default: 0x9
4148 22:50:10.150898 0, 0xFFFF, sum = 0
4149 22:50:10.150984 1, 0xFFFF, sum = 0
4150 22:50:10.154327 2, 0xFFFF, sum = 0
4151 22:50:10.154424 3, 0xFFFF, sum = 0
4152 22:50:10.157621 4, 0xFFFF, sum = 0
4153 22:50:10.157705 5, 0xFFFF, sum = 0
4154 22:50:10.161051 6, 0xFFFF, sum = 0
4155 22:50:10.161136 7, 0xFFFF, sum = 0
4156 22:50:10.164180 8, 0x0, sum = 1
4157 22:50:10.164263 9, 0x0, sum = 2
4158 22:50:10.167802 10, 0x0, sum = 3
4159 22:50:10.167934 11, 0x0, sum = 4
4160 22:50:10.168015 best_step = 9
4161 22:50:10.168091
4162 22:50:10.171251 ==
4163 22:50:10.174368 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 22:50:10.177878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 22:50:10.177960 ==
4166 22:50:10.178055 RX Vref Scan: 1
4167 22:50:10.178115
4168 22:50:10.180770 RX Vref 0 -> 0, step: 1
4169 22:50:10.180852
4170 22:50:10.183860 RX Delay -195 -> 252, step: 8
4171 22:50:10.183943
4172 22:50:10.187529 Set Vref, RX VrefLevel [Byte0]: 59
4173 22:50:10.191045 [Byte1]: 49
4174 22:50:10.191127
4175 22:50:10.193717 Final RX Vref Byte 0 = 59 to rank0
4176 22:50:10.196982 Final RX Vref Byte 1 = 49 to rank0
4177 22:50:10.200546 Final RX Vref Byte 0 = 59 to rank1
4178 22:50:10.204072 Final RX Vref Byte 1 = 49 to rank1==
4179 22:50:10.206946 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 22:50:10.213930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 22:50:10.214058 ==
4182 22:50:10.214128 DQS Delay:
4183 22:50:10.214187 DQS0 = 0, DQS1 = 0
4184 22:50:10.216866 DQM Delay:
4185 22:50:10.216948 DQM0 = 43, DQM1 = 32
4186 22:50:10.220526 DQ Delay:
4187 22:50:10.223853 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4188 22:50:10.223951 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4189 22:50:10.227261 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4190 22:50:10.233508 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4191 22:50:10.233599
4192 22:50:10.233664
4193 22:50:10.240399 [DQSOSCAuto] RK0, (LSB)MR18= 0x663d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4194 22:50:10.243973 CH0 RK0: MR19=808, MR18=663D
4195 22:50:10.250430 CH0_RK0: MR19=0x808, MR18=0x663D, DQSOSC=390, MR23=63, INC=172, DEC=114
4196 22:50:10.250514
4197 22:50:10.253259 ----->DramcWriteLeveling(PI) begin...
4198 22:50:10.253379 ==
4199 22:50:10.257355 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 22:50:10.260258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 22:50:10.260341 ==
4202 22:50:10.263269 Write leveling (Byte 0): 33 => 33
4203 22:50:10.266724 Write leveling (Byte 1): 33 => 33
4204 22:50:10.269791 DramcWriteLeveling(PI) end<-----
4205 22:50:10.269873
4206 22:50:10.269937 ==
4207 22:50:10.273010 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 22:50:10.276556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 22:50:10.276641 ==
4210 22:50:10.279853 [Gating] SW mode calibration
4211 22:50:10.286178 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4212 22:50:10.292995 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4213 22:50:10.296579 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 22:50:10.302810 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 22:50:10.306334 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 22:50:10.309499 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 22:50:10.316075 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4218 22:50:10.319530 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 22:50:10.322482 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 22:50:10.328993 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 22:50:10.332462 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 22:50:10.336023 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 22:50:10.342343 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 22:50:10.345504 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4225 22:50:10.349296 0 10 16 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
4226 22:50:10.355269 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 22:50:10.358590 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 22:50:10.362264 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 22:50:10.368601 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 22:50:10.371809 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 22:50:10.374883 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 22:50:10.381809 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4233 22:50:10.385342 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4234 22:50:10.388735 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 22:50:10.395260 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 22:50:10.398031 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 22:50:10.401521 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 22:50:10.408188 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 22:50:10.411087 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 22:50:10.414717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 22:50:10.421475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 22:50:10.424660 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 22:50:10.427838 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 22:50:10.434240 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 22:50:10.437762 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 22:50:10.441101 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 22:50:10.447703 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 22:50:10.451056 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4249 22:50:10.454633 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4250 22:50:10.457771 Total UI for P1: 0, mck2ui 16
4251 22:50:10.461197 best dqsien dly found for B0: ( 0, 13, 12)
4252 22:50:10.467649 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 22:50:10.467821 Total UI for P1: 0, mck2ui 16
4254 22:50:10.473993 best dqsien dly found for B1: ( 0, 13, 14)
4255 22:50:10.477114 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4256 22:50:10.480583 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4257 22:50:10.480777
4258 22:50:10.483620 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4259 22:50:10.487316 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4260 22:50:10.490495 [Gating] SW calibration Done
4261 22:50:10.490667 ==
4262 22:50:10.493459 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 22:50:10.496944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 22:50:10.497086 ==
4265 22:50:10.500103 RX Vref Scan: 0
4266 22:50:10.500254
4267 22:50:10.504056 RX Vref 0 -> 0, step: 1
4268 22:50:10.504223
4269 22:50:10.504360 RX Delay -230 -> 252, step: 16
4270 22:50:10.510406 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4271 22:50:10.513150 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4272 22:50:10.516547 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4273 22:50:10.520203 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4274 22:50:10.526339 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4275 22:50:10.529813 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4276 22:50:10.533158 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4277 22:50:10.536657 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4278 22:50:10.543008 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4279 22:50:10.546242 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4280 22:50:10.550013 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4281 22:50:10.553006 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4282 22:50:10.559582 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4283 22:50:10.563009 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4284 22:50:10.566091 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4285 22:50:10.569630 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4286 22:50:10.569712 ==
4287 22:50:10.573104 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 22:50:10.579131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 22:50:10.579231 ==
4290 22:50:10.579300 DQS Delay:
4291 22:50:10.582546 DQS0 = 0, DQS1 = 0
4292 22:50:10.582638 DQM Delay:
4293 22:50:10.582704 DQM0 = 40, DQM1 = 31
4294 22:50:10.585852 DQ Delay:
4295 22:50:10.589338 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4296 22:50:10.592784 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4297 22:50:10.595740 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4298 22:50:10.599105 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =33
4299 22:50:10.599201
4300 22:50:10.599264
4301 22:50:10.599323 ==
4302 22:50:10.602670 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 22:50:10.605619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 22:50:10.605745 ==
4305 22:50:10.605837
4306 22:50:10.605923
4307 22:50:10.609461 TX Vref Scan disable
4308 22:50:10.612630 == TX Byte 0 ==
4309 22:50:10.615454 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4310 22:50:10.618996 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4311 22:50:10.622188 == TX Byte 1 ==
4312 22:50:10.625899 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4313 22:50:10.629008 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4314 22:50:10.629091 ==
4315 22:50:10.632451 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 22:50:10.635651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 22:50:10.638613 ==
4318 22:50:10.638701
4319 22:50:10.638765
4320 22:50:10.638823 TX Vref Scan disable
4321 22:50:10.642614 == TX Byte 0 ==
4322 22:50:10.646082 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4323 22:50:10.652393 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4324 22:50:10.652498 == TX Byte 1 ==
4325 22:50:10.655776 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4326 22:50:10.662551 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4327 22:50:10.662657
4328 22:50:10.662722 [DATLAT]
4329 22:50:10.662781 Freq=600, CH0 RK1
4330 22:50:10.662838
4331 22:50:10.665816 DATLAT Default: 0x9
4332 22:50:10.669050 0, 0xFFFF, sum = 0
4333 22:50:10.669138 1, 0xFFFF, sum = 0
4334 22:50:10.672570 2, 0xFFFF, sum = 0
4335 22:50:10.672688 3, 0xFFFF, sum = 0
4336 22:50:10.675485 4, 0xFFFF, sum = 0
4337 22:50:10.675589 5, 0xFFFF, sum = 0
4338 22:50:10.678868 6, 0xFFFF, sum = 0
4339 22:50:10.678951 7, 0xFFFF, sum = 0
4340 22:50:10.682139 8, 0x0, sum = 1
4341 22:50:10.682251 9, 0x0, sum = 2
4342 22:50:10.685935 10, 0x0, sum = 3
4343 22:50:10.686018 11, 0x0, sum = 4
4344 22:50:10.686083 best_step = 9
4345 22:50:10.686142
4346 22:50:10.688731 ==
4347 22:50:10.692323 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 22:50:10.695412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 22:50:10.695494 ==
4350 22:50:10.695558 RX Vref Scan: 0
4351 22:50:10.695618
4352 22:50:10.698629 RX Vref 0 -> 0, step: 1
4353 22:50:10.698711
4354 22:50:10.702157 RX Delay -195 -> 252, step: 8
4355 22:50:10.708681 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4356 22:50:10.711754 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4357 22:50:10.715471 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4358 22:50:10.718727 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4359 22:50:10.721993 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4360 22:50:10.728377 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4361 22:50:10.731627 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4362 22:50:10.734888 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4363 22:50:10.738095 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4364 22:50:10.744923 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4365 22:50:10.748330 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4366 22:50:10.751130 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4367 22:50:10.754946 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4368 22:50:10.761266 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4369 22:50:10.764423 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4370 22:50:10.767866 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4371 22:50:10.767948 ==
4372 22:50:10.771256 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 22:50:10.774830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 22:50:10.778150 ==
4375 22:50:10.778290 DQS Delay:
4376 22:50:10.778372 DQS0 = 0, DQS1 = 0
4377 22:50:10.781305 DQM Delay:
4378 22:50:10.781410 DQM0 = 41, DQM1 = 37
4379 22:50:10.784649 DQ Delay:
4380 22:50:10.787809 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4381 22:50:10.787891 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4382 22:50:10.791198 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4383 22:50:10.794117 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4384 22:50:10.797796
4385 22:50:10.797878
4386 22:50:10.804519 [DQSOSCAuto] RK1, (LSB)MR18= 0x6013, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4387 22:50:10.807581 CH0 RK1: MR19=808, MR18=6013
4388 22:50:10.814343 CH0_RK1: MR19=0x808, MR18=0x6013, DQSOSC=391, MR23=63, INC=171, DEC=114
4389 22:50:10.817583 [RxdqsGatingPostProcess] freq 600
4390 22:50:10.821162 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4391 22:50:10.823860 Pre-setting of DQS Precalculation
4392 22:50:10.830649 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4393 22:50:10.830731 ==
4394 22:50:10.833588 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 22:50:10.837177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 22:50:10.837286 ==
4397 22:50:10.843938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 22:50:10.847343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4399 22:50:10.851794 [CA 0] Center 35 (5~66) winsize 62
4400 22:50:10.866732 [CA 1] Center 35 (5~66) winsize 62
4401 22:50:10.866908 [CA 2] Center 33 (3~64) winsize 62
4402 22:50:10.866993 [CA 3] Center 33 (3~64) winsize 62
4403 22:50:10.867053 [CA 4] Center 34 (4~64) winsize 61
4404 22:50:10.868236 [CA 5] Center 33 (3~64) winsize 62
4405 22:50:10.868318
4406 22:50:10.871701 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4407 22:50:10.871783
4408 22:50:10.874888 [CATrainingPosCal] consider 1 rank data
4409 22:50:10.877745 u2DelayCellTimex100 = 270/100 ps
4410 22:50:10.881541 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4411 22:50:10.887809 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4412 22:50:10.891037 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4413 22:50:10.894838 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 22:50:10.897672 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4415 22:50:10.901140 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 22:50:10.901223
4417 22:50:10.904602 CA PerBit enable=1, Macro0, CA PI delay=33
4418 22:50:10.904684
4419 22:50:10.907953 [CBTSetCACLKResult] CA Dly = 33
4420 22:50:10.911043 CS Dly: 5 (0~36)
4421 22:50:10.911124 ==
4422 22:50:10.914295 Dram Type= 6, Freq= 0, CH_1, rank 1
4423 22:50:10.917809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 22:50:10.917908 ==
4425 22:50:10.924234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 22:50:10.927501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4427 22:50:10.931723 [CA 0] Center 35 (5~66) winsize 62
4428 22:50:10.935236 [CA 1] Center 36 (6~66) winsize 61
4429 22:50:10.938295 [CA 2] Center 34 (4~65) winsize 62
4430 22:50:10.941948 [CA 3] Center 33 (3~64) winsize 62
4431 22:50:10.944679 [CA 4] Center 34 (3~65) winsize 63
4432 22:50:10.948203 [CA 5] Center 34 (3~65) winsize 63
4433 22:50:10.948286
4434 22:50:10.951550 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4435 22:50:10.951632
4436 22:50:10.954765 [CATrainingPosCal] consider 2 rank data
4437 22:50:10.957965 u2DelayCellTimex100 = 270/100 ps
4438 22:50:10.961233 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 22:50:10.967921 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4440 22:50:10.971556 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4441 22:50:10.974521 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 22:50:10.977989 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4443 22:50:10.981029 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 22:50:10.981109
4445 22:50:10.984498 CA PerBit enable=1, Macro0, CA PI delay=33
4446 22:50:10.984571
4447 22:50:10.988128 [CBTSetCACLKResult] CA Dly = 33
4448 22:50:10.991163 CS Dly: 5 (0~37)
4449 22:50:10.991244
4450 22:50:10.994723 ----->DramcWriteLeveling(PI) begin...
4451 22:50:10.994806 ==
4452 22:50:10.998073 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 22:50:11.001537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 22:50:11.001694 ==
4455 22:50:11.004227 Write leveling (Byte 0): 31 => 31
4456 22:50:11.007657 Write leveling (Byte 1): 31 => 31
4457 22:50:11.010774 DramcWriteLeveling(PI) end<-----
4458 22:50:11.010855
4459 22:50:11.010919 ==
4460 22:50:11.014329 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 22:50:11.017464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 22:50:11.017546 ==
4463 22:50:11.020766 [Gating] SW mode calibration
4464 22:50:11.027761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 22:50:11.033961 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4466 22:50:11.037022 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 22:50:11.040298 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 22:50:11.046827 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4469 22:50:11.050386 0 9 12 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 0)
4470 22:50:11.053343 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 22:50:11.060171 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 22:50:11.063393 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 22:50:11.066838 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 22:50:11.073507 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 22:50:11.077017 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 22:50:11.079880 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4477 22:50:11.086844 0 10 12 | B1->B0 | 2e2e 3737 | 0 1 | (1 1) (0 0)
4478 22:50:11.090103 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 22:50:11.093645 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 22:50:11.100054 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 22:50:11.103203 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 22:50:11.106443 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 22:50:11.112845 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 22:50:11.116303 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 22:50:11.119758 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4486 22:50:11.125838 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 22:50:11.129090 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 22:50:11.132613 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 22:50:11.139186 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 22:50:11.142980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 22:50:11.145657 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 22:50:11.152301 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 22:50:11.155670 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 22:50:11.159166 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 22:50:11.165700 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 22:50:11.169076 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 22:50:11.172394 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 22:50:11.178830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 22:50:11.182591 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 22:50:11.185501 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4501 22:50:11.192168 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4502 22:50:11.195381 Total UI for P1: 0, mck2ui 16
4503 22:50:11.198713 best dqsien dly found for B0: ( 0, 13, 8)
4504 22:50:11.202036 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 22:50:11.205010 Total UI for P1: 0, mck2ui 16
4506 22:50:11.208359 best dqsien dly found for B1: ( 0, 13, 14)
4507 22:50:11.211594 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4508 22:50:11.214972 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4509 22:50:11.215053
4510 22:50:11.218434 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4511 22:50:11.224632 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4512 22:50:11.224714 [Gating] SW calibration Done
4513 22:50:11.224778 ==
4514 22:50:11.228078 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 22:50:11.234978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 22:50:11.235061 ==
4517 22:50:11.235126 RX Vref Scan: 0
4518 22:50:11.235186
4519 22:50:11.237996 RX Vref 0 -> 0, step: 1
4520 22:50:11.238077
4521 22:50:11.241001 RX Delay -230 -> 252, step: 16
4522 22:50:11.244535 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4523 22:50:11.248032 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4524 22:50:11.254238 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4525 22:50:11.257482 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4526 22:50:11.261084 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4527 22:50:11.264350 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4528 22:50:11.270778 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4529 22:50:11.274413 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4530 22:50:11.277272 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4531 22:50:11.280308 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4532 22:50:11.286917 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4533 22:50:11.290439 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4534 22:50:11.294012 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4535 22:50:11.297026 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4536 22:50:11.303912 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4537 22:50:11.306850 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4538 22:50:11.306931 ==
4539 22:50:11.309929 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 22:50:11.313437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 22:50:11.313520 ==
4542 22:50:11.316406 DQS Delay:
4543 22:50:11.316487 DQS0 = 0, DQS1 = 0
4544 22:50:11.316551 DQM Delay:
4545 22:50:11.319823 DQM0 = 45, DQM1 = 36
4546 22:50:11.319947 DQ Delay:
4547 22:50:11.323070 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4548 22:50:11.326605 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4549 22:50:11.329619 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4550 22:50:11.332909 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4551 22:50:11.332990
4552 22:50:11.333053
4553 22:50:11.333112 ==
4554 22:50:11.336480 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 22:50:11.343110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 22:50:11.343193 ==
4557 22:50:11.343258
4558 22:50:11.343317
4559 22:50:11.345989 TX Vref Scan disable
4560 22:50:11.346070 == TX Byte 0 ==
4561 22:50:11.349534 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4562 22:50:11.356165 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4563 22:50:11.356263 == TX Byte 1 ==
4564 22:50:11.362790 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4565 22:50:11.366158 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4566 22:50:11.366240 ==
4567 22:50:11.369084 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 22:50:11.372666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 22:50:11.372748 ==
4570 22:50:11.372812
4571 22:50:11.372871
4572 22:50:11.375478 TX Vref Scan disable
4573 22:50:11.379334 == TX Byte 0 ==
4574 22:50:11.382649 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4575 22:50:11.385631 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4576 22:50:11.388903 == TX Byte 1 ==
4577 22:50:11.392651 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4578 22:50:11.395367 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4579 22:50:11.395449
4580 22:50:11.398774 [DATLAT]
4581 22:50:11.398858 Freq=600, CH1 RK0
4582 22:50:11.398922
4583 22:50:11.402088 DATLAT Default: 0x9
4584 22:50:11.402169 0, 0xFFFF, sum = 0
4585 22:50:11.405843 1, 0xFFFF, sum = 0
4586 22:50:11.405925 2, 0xFFFF, sum = 0
4587 22:50:11.409254 3, 0xFFFF, sum = 0
4588 22:50:11.409346 4, 0xFFFF, sum = 0
4589 22:50:11.412046 5, 0xFFFF, sum = 0
4590 22:50:11.415196 6, 0xFFFF, sum = 0
4591 22:50:11.415278 7, 0xFFFF, sum = 0
4592 22:50:11.415343 8, 0x0, sum = 1
4593 22:50:11.418872 9, 0x0, sum = 2
4594 22:50:11.418954 10, 0x0, sum = 3
4595 22:50:11.421583 11, 0x0, sum = 4
4596 22:50:11.421666 best_step = 9
4597 22:50:11.421730
4598 22:50:11.421789 ==
4599 22:50:11.425017 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 22:50:11.431561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 22:50:11.431645 ==
4602 22:50:11.431710 RX Vref Scan: 1
4603 22:50:11.431769
4604 22:50:11.435103 RX Vref 0 -> 0, step: 1
4605 22:50:11.435184
4606 22:50:11.438105 RX Delay -195 -> 252, step: 8
4607 22:50:11.438187
4608 22:50:11.441777 Set Vref, RX VrefLevel [Byte0]: 46
4609 22:50:11.444859 [Byte1]: 57
4610 22:50:11.444940
4611 22:50:11.448388 Final RX Vref Byte 0 = 46 to rank0
4612 22:50:11.451170 Final RX Vref Byte 1 = 57 to rank0
4613 22:50:11.454728 Final RX Vref Byte 0 = 46 to rank1
4614 22:50:11.458217 Final RX Vref Byte 1 = 57 to rank1==
4615 22:50:11.461299 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 22:50:11.465111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 22:50:11.465193 ==
4618 22:50:11.467782 DQS Delay:
4619 22:50:11.467863 DQS0 = 0, DQS1 = 0
4620 22:50:11.471281 DQM Delay:
4621 22:50:11.471362 DQM0 = 44, DQM1 = 34
4622 22:50:11.471425 DQ Delay:
4623 22:50:11.474441 DQ0 =48, DQ1 =40, DQ2 =36, DQ3 =40
4624 22:50:11.477787 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =36
4625 22:50:11.481543 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4626 22:50:11.484232 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4627 22:50:11.484313
4628 22:50:11.487707
4629 22:50:11.494367 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4630 22:50:11.497444 CH1 RK0: MR19=808, MR18=4B30
4631 22:50:11.503985 CH1_RK0: MR19=0x808, MR18=0x4B30, DQSOSC=395, MR23=63, INC=168, DEC=112
4632 22:50:11.504067
4633 22:50:11.507208 ----->DramcWriteLeveling(PI) begin...
4634 22:50:11.507290 ==
4635 22:50:11.510480 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 22:50:11.514027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 22:50:11.514109 ==
4638 22:50:11.517394 Write leveling (Byte 0): 29 => 29
4639 22:50:11.520467 Write leveling (Byte 1): 31 => 31
4640 22:50:11.523963 DramcWriteLeveling(PI) end<-----
4641 22:50:11.524063
4642 22:50:11.524132 ==
4643 22:50:11.527122 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 22:50:11.530531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 22:50:11.530613 ==
4646 22:50:11.533638 [Gating] SW mode calibration
4647 22:50:11.540375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4648 22:50:11.547313 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4649 22:50:11.550363 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4650 22:50:11.556710 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 22:50:11.560099 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 22:50:11.563864 0 9 12 | B1->B0 | 3030 3232 | 0 0 | (0 1) (0 1)
4653 22:50:11.569633 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4654 22:50:11.573084 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 22:50:11.576651 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 22:50:11.583070 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 22:50:11.586665 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 22:50:11.589451 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 22:50:11.596383 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 22:50:11.599931 0 10 12 | B1->B0 | 3231 2c2c | 1 0 | (0 0) (0 0)
4661 22:50:11.603009 0 10 16 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
4662 22:50:11.609108 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 22:50:11.612874 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 22:50:11.616104 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 22:50:11.622669 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 22:50:11.625809 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 22:50:11.629387 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 22:50:11.636279 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4669 22:50:11.639096 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 22:50:11.642522 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 22:50:11.649096 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 22:50:11.652189 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 22:50:11.655725 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 22:50:11.661995 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 22:50:11.665290 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 22:50:11.668579 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 22:50:11.675680 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 22:50:11.678598 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 22:50:11.682243 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 22:50:11.688651 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 22:50:11.691679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 22:50:11.695255 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 22:50:11.701706 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 22:50:11.704834 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4685 22:50:11.708512 Total UI for P1: 0, mck2ui 16
4686 22:50:11.711442 best dqsien dly found for B1: ( 0, 13, 10)
4687 22:50:11.714565 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 22:50:11.718393 Total UI for P1: 0, mck2ui 16
4689 22:50:11.721481 best dqsien dly found for B0: ( 0, 13, 12)
4690 22:50:11.724946 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4691 22:50:11.727958 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4692 22:50:11.728061
4693 22:50:11.734691 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4694 22:50:11.737845 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4695 22:50:11.737950 [Gating] SW calibration Done
4696 22:50:11.741226 ==
4697 22:50:11.744392 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 22:50:11.747637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 22:50:11.747744 ==
4700 22:50:11.747845 RX Vref Scan: 0
4701 22:50:11.747945
4702 22:50:11.751038 RX Vref 0 -> 0, step: 1
4703 22:50:11.751136
4704 22:50:11.754682 RX Delay -230 -> 252, step: 16
4705 22:50:11.757452 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4706 22:50:11.764284 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4707 22:50:11.767775 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4708 22:50:11.770665 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4709 22:50:11.773981 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4710 22:50:11.777502 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4711 22:50:11.783889 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4712 22:50:11.787472 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4713 22:50:11.790321 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4714 22:50:11.793629 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4715 22:50:11.800845 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4716 22:50:11.803601 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4717 22:50:11.807212 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4718 22:50:11.810255 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4719 22:50:11.816992 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4720 22:50:11.819998 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4721 22:50:11.820108 ==
4722 22:50:11.823313 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 22:50:11.826825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 22:50:11.826930 ==
4725 22:50:11.830229 DQS Delay:
4726 22:50:11.830309 DQS0 = 0, DQS1 = 0
4727 22:50:11.830402 DQM Delay:
4728 22:50:11.833561 DQM0 = 42, DQM1 = 35
4729 22:50:11.833657 DQ Delay:
4730 22:50:11.837047 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4731 22:50:11.840115 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =33
4732 22:50:11.843354 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4733 22:50:11.846902 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4734 22:50:11.846983
4735 22:50:11.847045
4736 22:50:11.847104 ==
4737 22:50:11.849668 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 22:50:11.856714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 22:50:11.856795 ==
4740 22:50:11.856858
4741 22:50:11.856917
4742 22:50:11.856974 TX Vref Scan disable
4743 22:50:11.860457 == TX Byte 0 ==
4744 22:50:11.863739 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4745 22:50:11.870050 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4746 22:50:11.870130 == TX Byte 1 ==
4747 22:50:11.873950 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4748 22:50:11.880080 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4749 22:50:11.880162 ==
4750 22:50:11.883671 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 22:50:11.886820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 22:50:11.886901 ==
4753 22:50:11.886964
4754 22:50:11.887022
4755 22:50:11.889749 TX Vref Scan disable
4756 22:50:11.893170 == TX Byte 0 ==
4757 22:50:11.896504 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4758 22:50:11.900118 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4759 22:50:11.903617 == TX Byte 1 ==
4760 22:50:11.906788 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4761 22:50:11.909667 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4762 22:50:11.909749
4763 22:50:11.909834 [DATLAT]
4764 22:50:11.913141 Freq=600, CH1 RK1
4765 22:50:11.913223
4766 22:50:11.916933 DATLAT Default: 0x9
4767 22:50:11.917013 0, 0xFFFF, sum = 0
4768 22:50:11.919948 1, 0xFFFF, sum = 0
4769 22:50:11.920029 2, 0xFFFF, sum = 0
4770 22:50:11.923234 3, 0xFFFF, sum = 0
4771 22:50:11.923316 4, 0xFFFF, sum = 0
4772 22:50:11.926476 5, 0xFFFF, sum = 0
4773 22:50:11.926558 6, 0xFFFF, sum = 0
4774 22:50:11.929950 7, 0xFFFF, sum = 0
4775 22:50:11.930031 8, 0x0, sum = 1
4776 22:50:11.933168 9, 0x0, sum = 2
4777 22:50:11.933250 10, 0x0, sum = 3
4778 22:50:11.936727 11, 0x0, sum = 4
4779 22:50:11.936809 best_step = 9
4780 22:50:11.936871
4781 22:50:11.936930 ==
4782 22:50:11.939803 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 22:50:11.942731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 22:50:11.942812 ==
4785 22:50:11.946376 RX Vref Scan: 0
4786 22:50:11.946457
4787 22:50:11.949680 RX Vref 0 -> 0, step: 1
4788 22:50:11.949761
4789 22:50:11.949834 RX Delay -195 -> 252, step: 8
4790 22:50:11.957561 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4791 22:50:11.960609 iDelay=205, Bit 1, Center 36 (-115 ~ 188) 304
4792 22:50:11.964184 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4793 22:50:11.967320 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4794 22:50:11.973900 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4795 22:50:11.977530 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4796 22:50:11.980633 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4797 22:50:11.983870 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4798 22:50:11.986996 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4799 22:50:11.993747 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4800 22:50:11.997251 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4801 22:50:12.000621 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4802 22:50:12.003673 iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312
4803 22:50:12.010193 iDelay=205, Bit 13, Center 44 (-115 ~ 204) 320
4804 22:50:12.013442 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4805 22:50:12.016795 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4806 22:50:12.016875 ==
4807 22:50:12.020328 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 22:50:12.026558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 22:50:12.026642 ==
4810 22:50:12.026705 DQS Delay:
4811 22:50:12.026765 DQS0 = 0, DQS1 = 0
4812 22:50:12.030206 DQM Delay:
4813 22:50:12.030286 DQM0 = 42, DQM1 = 34
4814 22:50:12.033306 DQ Delay:
4815 22:50:12.036539 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =40
4816 22:50:12.039705 DQ4 =40, DQ5 =56, DQ6 =52, DQ7 =36
4817 22:50:12.043580 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4818 22:50:12.046578 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =44
4819 22:50:12.046658
4820 22:50:12.046721
4821 22:50:12.053132 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4822 22:50:12.056397 CH1 RK1: MR19=808, MR18=2B20
4823 22:50:12.063230 CH1_RK1: MR19=0x808, MR18=0x2B20, DQSOSC=401, MR23=63, INC=163, DEC=108
4824 22:50:12.066113 [RxdqsGatingPostProcess] freq 600
4825 22:50:12.069355 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4826 22:50:12.072892 Pre-setting of DQS Precalculation
4827 22:50:12.079961 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4828 22:50:12.086122 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4829 22:50:12.092714 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4830 22:50:12.092816
4831 22:50:12.092915
4832 22:50:12.095691 [Calibration Summary] 1200 Mbps
4833 22:50:12.095793 CH 0, Rank 0
4834 22:50:12.099227 SW Impedance : PASS
4835 22:50:12.102680 DUTY Scan : NO K
4836 22:50:12.102764 ZQ Calibration : PASS
4837 22:50:12.105662 Jitter Meter : NO K
4838 22:50:12.109149 CBT Training : PASS
4839 22:50:12.109250 Write leveling : PASS
4840 22:50:12.112816 RX DQS gating : PASS
4841 22:50:12.115753 RX DQ/DQS(RDDQC) : PASS
4842 22:50:12.115827 TX DQ/DQS : PASS
4843 22:50:12.118869 RX DATLAT : PASS
4844 22:50:12.122108 RX DQ/DQS(Engine): PASS
4845 22:50:12.122179 TX OE : NO K
4846 22:50:12.125668 All Pass.
4847 22:50:12.125747
4848 22:50:12.125808 CH 0, Rank 1
4849 22:50:12.129007 SW Impedance : PASS
4850 22:50:12.129102 DUTY Scan : NO K
4851 22:50:12.132009 ZQ Calibration : PASS
4852 22:50:12.135556 Jitter Meter : NO K
4853 22:50:12.135655 CBT Training : PASS
4854 22:50:12.138684 Write leveling : PASS
4855 22:50:12.141955 RX DQS gating : PASS
4856 22:50:12.142030 RX DQ/DQS(RDDQC) : PASS
4857 22:50:12.145440 TX DQ/DQS : PASS
4858 22:50:12.148451 RX DATLAT : PASS
4859 22:50:12.148532 RX DQ/DQS(Engine): PASS
4860 22:50:12.151774 TX OE : NO K
4861 22:50:12.151859 All Pass.
4862 22:50:12.151922
4863 22:50:12.155307 CH 1, Rank 0
4864 22:50:12.155416 SW Impedance : PASS
4865 22:50:12.158163 DUTY Scan : NO K
4866 22:50:12.161480 ZQ Calibration : PASS
4867 22:50:12.161557 Jitter Meter : NO K
4868 22:50:12.164802 CBT Training : PASS
4869 22:50:12.168173 Write leveling : PASS
4870 22:50:12.168303 RX DQS gating : PASS
4871 22:50:12.171801 RX DQ/DQS(RDDQC) : PASS
4872 22:50:12.171904 TX DQ/DQS : PASS
4873 22:50:12.174943 RX DATLAT : PASS
4874 22:50:12.178038 RX DQ/DQS(Engine): PASS
4875 22:50:12.178117 TX OE : NO K
4876 22:50:12.181747 All Pass.
4877 22:50:12.181853
4878 22:50:12.181953 CH 1, Rank 1
4879 22:50:12.185029 SW Impedance : PASS
4880 22:50:12.185129 DUTY Scan : NO K
4881 22:50:12.187953 ZQ Calibration : PASS
4882 22:50:12.191411 Jitter Meter : NO K
4883 22:50:12.191509 CBT Training : PASS
4884 22:50:12.194982 Write leveling : PASS
4885 22:50:12.198291 RX DQS gating : PASS
4886 22:50:12.198366 RX DQ/DQS(RDDQC) : PASS
4887 22:50:12.201140 TX DQ/DQS : PASS
4888 22:50:12.204705 RX DATLAT : PASS
4889 22:50:12.204805 RX DQ/DQS(Engine): PASS
4890 22:50:12.208360 TX OE : NO K
4891 22:50:12.208436 All Pass.
4892 22:50:12.208515
4893 22:50:12.211055 DramC Write-DBI off
4894 22:50:12.214479 PER_BANK_REFRESH: Hybrid Mode
4895 22:50:12.214554 TX_TRACKING: ON
4896 22:50:12.224519 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4897 22:50:12.227807 [FAST_K] Save calibration result to emmc
4898 22:50:12.231643 dramc_set_vcore_voltage set vcore to 662500
4899 22:50:12.234408 Read voltage for 933, 3
4900 22:50:12.234510 Vio18 = 0
4901 22:50:12.234610 Vcore = 662500
4902 22:50:12.237731 Vdram = 0
4903 22:50:12.237833 Vddq = 0
4904 22:50:12.237932 Vmddr = 0
4905 22:50:12.244275 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4906 22:50:12.248078 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4907 22:50:12.250708 MEM_TYPE=3, freq_sel=17
4908 22:50:12.254140 sv_algorithm_assistance_LP4_1600
4909 22:50:12.257607 ============ PULL DRAM RESETB DOWN ============
4910 22:50:12.260846 ========== PULL DRAM RESETB DOWN end =========
4911 22:50:12.267550 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4912 22:50:12.270530 ===================================
4913 22:50:12.274440 LPDDR4 DRAM CONFIGURATION
4914 22:50:12.277158 ===================================
4915 22:50:12.277257 EX_ROW_EN[0] = 0x0
4916 22:50:12.280733 EX_ROW_EN[1] = 0x0
4917 22:50:12.280831 LP4Y_EN = 0x0
4918 22:50:12.284028 WORK_FSP = 0x0
4919 22:50:12.284132 WL = 0x3
4920 22:50:12.287150 RL = 0x3
4921 22:50:12.287224 BL = 0x2
4922 22:50:12.290307 RPST = 0x0
4923 22:50:12.290391 RD_PRE = 0x0
4924 22:50:12.294017 WR_PRE = 0x1
4925 22:50:12.294099 WR_PST = 0x0
4926 22:50:12.297049 DBI_WR = 0x0
4927 22:50:12.297153 DBI_RD = 0x0
4928 22:50:12.300577 OTF = 0x1
4929 22:50:12.303541 ===================================
4930 22:50:12.307391 ===================================
4931 22:50:12.307490 ANA top config
4932 22:50:12.310814 ===================================
4933 22:50:12.313876 DLL_ASYNC_EN = 0
4934 22:50:12.317037 ALL_SLAVE_EN = 1
4935 22:50:12.319912 NEW_RANK_MODE = 1
4936 22:50:12.323190 DLL_IDLE_MODE = 1
4937 22:50:12.323264 LP45_APHY_COMB_EN = 1
4938 22:50:12.326975 TX_ODT_DIS = 1
4939 22:50:12.329946 NEW_8X_MODE = 1
4940 22:50:12.333325 ===================================
4941 22:50:12.336775 ===================================
4942 22:50:12.340147 data_rate = 1866
4943 22:50:12.343648 CKR = 1
4944 22:50:12.343729 DQ_P2S_RATIO = 8
4945 22:50:12.346563 ===================================
4946 22:50:12.350078 CA_P2S_RATIO = 8
4947 22:50:12.353031 DQ_CA_OPEN = 0
4948 22:50:12.356456 DQ_SEMI_OPEN = 0
4949 22:50:12.359742 CA_SEMI_OPEN = 0
4950 22:50:12.363301 CA_FULL_RATE = 0
4951 22:50:12.363382 DQ_CKDIV4_EN = 1
4952 22:50:12.366287 CA_CKDIV4_EN = 1
4953 22:50:12.369689 CA_PREDIV_EN = 0
4954 22:50:12.372741 PH8_DLY = 0
4955 22:50:12.376369 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4956 22:50:12.379426 DQ_AAMCK_DIV = 4
4957 22:50:12.382945 CA_AAMCK_DIV = 4
4958 22:50:12.383026 CA_ADMCK_DIV = 4
4959 22:50:12.386218 DQ_TRACK_CA_EN = 0
4960 22:50:12.389294 CA_PICK = 933
4961 22:50:12.392769 CA_MCKIO = 933
4962 22:50:12.396161 MCKIO_SEMI = 0
4963 22:50:12.399270 PLL_FREQ = 3732
4964 22:50:12.402350 DQ_UI_PI_RATIO = 32
4965 22:50:12.402431 CA_UI_PI_RATIO = 0
4966 22:50:12.406226 ===================================
4967 22:50:12.409096 ===================================
4968 22:50:12.412627 memory_type:LPDDR4
4969 22:50:12.416092 GP_NUM : 10
4970 22:50:12.416173 SRAM_EN : 1
4971 22:50:12.419013 MD32_EN : 0
4972 22:50:12.422435 ===================================
4973 22:50:12.425795 [ANA_INIT] >>>>>>>>>>>>>>
4974 22:50:12.429141 <<<<<< [CONFIGURE PHASE]: ANA_TX
4975 22:50:12.432171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4976 22:50:12.435360 ===================================
4977 22:50:12.435444 data_rate = 1866,PCW = 0X8f00
4978 22:50:12.438689 ===================================
4979 22:50:12.445426 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4980 22:50:12.448898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4981 22:50:12.455123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 22:50:12.458794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4983 22:50:12.462063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4984 22:50:12.464981 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4985 22:50:12.468391 [ANA_INIT] flow start
4986 22:50:12.472039 [ANA_INIT] PLL >>>>>>>>
4987 22:50:12.472146 [ANA_INIT] PLL <<<<<<<<
4988 22:50:12.475195 [ANA_INIT] MIDPI >>>>>>>>
4989 22:50:12.478229 [ANA_INIT] MIDPI <<<<<<<<
4990 22:50:12.481640 [ANA_INIT] DLL >>>>>>>>
4991 22:50:12.481721 [ANA_INIT] flow end
4992 22:50:12.485126 ============ LP4 DIFF to SE enter ============
4993 22:50:12.491196 ============ LP4 DIFF to SE exit ============
4994 22:50:12.491301 [ANA_INIT] <<<<<<<<<<<<<
4995 22:50:12.494590 [Flow] Enable top DCM control >>>>>
4996 22:50:12.497726 [Flow] Enable top DCM control <<<<<
4997 22:50:12.501339 Enable DLL master slave shuffle
4998 22:50:12.507630 ==============================================================
4999 22:50:12.507713 Gating Mode config
5000 22:50:12.514432 ==============================================================
5001 22:50:12.517343 Config description:
5002 22:50:12.527292 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5003 22:50:12.533965 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5004 22:50:12.537498 SELPH_MODE 0: By rank 1: By Phase
5005 22:50:12.544239 ==============================================================
5006 22:50:12.547303 GAT_TRACK_EN = 1
5007 22:50:12.550192 RX_GATING_MODE = 2
5008 22:50:12.553805 RX_GATING_TRACK_MODE = 2
5009 22:50:12.553886 SELPH_MODE = 1
5010 22:50:12.557257 PICG_EARLY_EN = 1
5011 22:50:12.560603 VALID_LAT_VALUE = 1
5012 22:50:12.566917 ==============================================================
5013 22:50:12.570508 Enter into Gating configuration >>>>
5014 22:50:12.573227 Exit from Gating configuration <<<<
5015 22:50:12.576783 Enter into DVFS_PRE_config >>>>>
5016 22:50:12.586794 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5017 22:50:12.589857 Exit from DVFS_PRE_config <<<<<
5018 22:50:12.593263 Enter into PICG configuration >>>>
5019 22:50:12.596654 Exit from PICG configuration <<<<
5020 22:50:12.599918 [RX_INPUT] configuration >>>>>
5021 22:50:12.602962 [RX_INPUT] configuration <<<<<
5022 22:50:12.606291 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5023 22:50:12.613037 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5024 22:50:12.619421 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 22:50:12.626202 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 22:50:12.632530 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 22:50:12.639388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 22:50:12.642705 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5029 22:50:12.645915 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5030 22:50:12.649005 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5031 22:50:12.655490 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5032 22:50:12.659366 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5033 22:50:12.662057 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5034 22:50:12.665547 ===================================
5035 22:50:12.669069 LPDDR4 DRAM CONFIGURATION
5036 22:50:12.671993 ===================================
5037 22:50:12.672090 EX_ROW_EN[0] = 0x0
5038 22:50:12.675703 EX_ROW_EN[1] = 0x0
5039 22:50:12.678514 LP4Y_EN = 0x0
5040 22:50:12.678586 WORK_FSP = 0x0
5041 22:50:12.682135 WL = 0x3
5042 22:50:12.682209 RL = 0x3
5043 22:50:12.685503 BL = 0x2
5044 22:50:12.685573 RPST = 0x0
5045 22:50:12.688495 RD_PRE = 0x0
5046 22:50:12.688589 WR_PRE = 0x1
5047 22:50:12.691927 WR_PST = 0x0
5048 22:50:12.692031 DBI_WR = 0x0
5049 22:50:12.695126 DBI_RD = 0x0
5050 22:50:12.695230 OTF = 0x1
5051 22:50:12.698716 ===================================
5052 22:50:12.704934 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5053 22:50:12.708192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5054 22:50:12.711370 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 22:50:12.714772 ===================================
5056 22:50:12.718385 LPDDR4 DRAM CONFIGURATION
5057 22:50:12.721202 ===================================
5058 22:50:12.724931 EX_ROW_EN[0] = 0x10
5059 22:50:12.725028 EX_ROW_EN[1] = 0x0
5060 22:50:12.728079 LP4Y_EN = 0x0
5061 22:50:12.728185 WORK_FSP = 0x0
5062 22:50:12.731426 WL = 0x3
5063 22:50:12.731523 RL = 0x3
5064 22:50:12.734383 BL = 0x2
5065 22:50:12.734459 RPST = 0x0
5066 22:50:12.737637 RD_PRE = 0x0
5067 22:50:12.737710 WR_PRE = 0x1
5068 22:50:12.741247 WR_PST = 0x0
5069 22:50:12.741371 DBI_WR = 0x0
5070 22:50:12.744469 DBI_RD = 0x0
5071 22:50:12.744563 OTF = 0x1
5072 22:50:12.748200 ===================================
5073 22:50:12.754497 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5074 22:50:12.759240 nWR fixed to 30
5075 22:50:12.762831 [ModeRegInit_LP4] CH0 RK0
5076 22:50:12.762911 [ModeRegInit_LP4] CH0 RK1
5077 22:50:12.765816 [ModeRegInit_LP4] CH1 RK0
5078 22:50:12.769234 [ModeRegInit_LP4] CH1 RK1
5079 22:50:12.769335 match AC timing 9
5080 22:50:12.775756 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5081 22:50:12.779372 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5082 22:50:12.782555 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5083 22:50:12.789056 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5084 22:50:12.792222 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5085 22:50:12.792301 ==
5086 22:50:12.795593 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 22:50:12.798557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 22:50:12.798647 ==
5089 22:50:12.805430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 22:50:12.812041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5091 22:50:12.815292 [CA 0] Center 37 (7~68) winsize 62
5092 22:50:12.818590 [CA 1] Center 37 (7~68) winsize 62
5093 22:50:12.821889 [CA 2] Center 34 (4~65) winsize 62
5094 22:50:12.825221 [CA 3] Center 34 (4~65) winsize 62
5095 22:50:12.828130 [CA 4] Center 33 (3~64) winsize 62
5096 22:50:12.831378 [CA 5] Center 33 (3~64) winsize 62
5097 22:50:12.831481
5098 22:50:12.835090 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5099 22:50:12.835174
5100 22:50:12.838047 [CATrainingPosCal] consider 1 rank data
5101 22:50:12.841210 u2DelayCellTimex100 = 270/100 ps
5102 22:50:12.844773 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5103 22:50:12.847903 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5104 22:50:12.851033 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5105 22:50:12.857925 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5106 22:50:12.861351 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5107 22:50:12.864408 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5108 22:50:12.864506
5109 22:50:12.867556 CA PerBit enable=1, Macro0, CA PI delay=33
5110 22:50:12.867631
5111 22:50:12.871080 [CBTSetCACLKResult] CA Dly = 33
5112 22:50:12.871156 CS Dly: 7 (0~38)
5113 22:50:12.871253 ==
5114 22:50:12.874209 Dram Type= 6, Freq= 0, CH_0, rank 1
5115 22:50:12.880744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 22:50:12.880850 ==
5117 22:50:12.884252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 22:50:12.890626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5119 22:50:12.894467 [CA 0] Center 37 (7~68) winsize 62
5120 22:50:12.897452 [CA 1] Center 37 (7~68) winsize 62
5121 22:50:12.900832 [CA 2] Center 34 (4~65) winsize 62
5122 22:50:12.904103 [CA 3] Center 34 (4~65) winsize 62
5123 22:50:12.907448 [CA 4] Center 33 (3~64) winsize 62
5124 22:50:12.910766 [CA 5] Center 33 (3~63) winsize 61
5125 22:50:12.910864
5126 22:50:12.913732 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5127 22:50:12.913830
5128 22:50:12.917426 [CATrainingPosCal] consider 2 rank data
5129 22:50:12.920150 u2DelayCellTimex100 = 270/100 ps
5130 22:50:12.926664 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5131 22:50:12.929986 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5132 22:50:12.933141 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5133 22:50:12.936780 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5134 22:50:12.940250 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5135 22:50:12.943624 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5136 22:50:12.943732
5137 22:50:12.946950 CA PerBit enable=1, Macro0, CA PI delay=33
5138 22:50:12.947055
5139 22:50:12.950176 [CBTSetCACLKResult] CA Dly = 33
5140 22:50:12.953460 CS Dly: 7 (0~39)
5141 22:50:12.953544
5142 22:50:12.956342 ----->DramcWriteLeveling(PI) begin...
5143 22:50:12.956444 ==
5144 22:50:12.959527 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 22:50:12.962781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 22:50:12.962884 ==
5147 22:50:12.966121 Write leveling (Byte 0): 35 => 35
5148 22:50:12.969539 Write leveling (Byte 1): 28 => 28
5149 22:50:12.973033 DramcWriteLeveling(PI) end<-----
5150 22:50:12.973133
5151 22:50:12.973232 ==
5152 22:50:12.976456 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 22:50:12.979825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 22:50:12.979927 ==
5155 22:50:12.982912 [Gating] SW mode calibration
5156 22:50:12.989474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5157 22:50:12.996076 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5158 22:50:12.999043 0 14 0 | B1->B0 | 2322 3232 | 1 0 | (0 0) (0 0)
5159 22:50:13.005673 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5160 22:50:13.009236 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 22:50:13.012156 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 22:50:13.018889 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 22:50:13.022456 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 22:50:13.026176 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5165 22:50:13.032217 0 14 28 | B1->B0 | 3434 2c2c | 0 1 | (0 1) (1 0)
5166 22:50:13.035599 0 15 0 | B1->B0 | 3232 2424 | 0 0 | (0 1) (0 0)
5167 22:50:13.038606 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5168 22:50:13.045371 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 22:50:13.048850 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 22:50:13.052224 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 22:50:13.058653 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 22:50:13.061877 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 22:50:13.065528 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5174 22:50:13.071864 1 0 0 | B1->B0 | 3030 4141 | 1 0 | (0 0) (1 1)
5175 22:50:13.074961 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 22:50:13.078652 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 22:50:13.085029 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 22:50:13.088480 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 22:50:13.091403 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 22:50:13.098544 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 22:50:13.101647 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 22:50:13.104615 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5183 22:50:13.111525 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 22:50:13.114846 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 22:50:13.117630 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 22:50:13.124779 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 22:50:13.127544 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 22:50:13.131060 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 22:50:13.137541 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 22:50:13.140789 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 22:50:13.144025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 22:50:13.150673 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 22:50:13.154115 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 22:50:13.157486 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 22:50:13.163806 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 22:50:13.167559 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 22:50:13.170933 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5198 22:50:13.177397 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5199 22:50:13.177479 Total UI for P1: 0, mck2ui 16
5200 22:50:13.183768 best dqsien dly found for B0: ( 1, 2, 28)
5201 22:50:13.186939 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5202 22:50:13.190184 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 22:50:13.193273 Total UI for P1: 0, mck2ui 16
5204 22:50:13.197397 best dqsien dly found for B1: ( 1, 3, 2)
5205 22:50:13.200519 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5206 22:50:13.203301 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5207 22:50:13.203382
5208 22:50:13.209901 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5209 22:50:13.213394 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5210 22:50:13.213475 [Gating] SW calibration Done
5211 22:50:13.216793 ==
5212 22:50:13.219734 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 22:50:13.223037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 22:50:13.223119 ==
5215 22:50:13.223183 RX Vref Scan: 0
5216 22:50:13.223242
5217 22:50:13.226616 RX Vref 0 -> 0, step: 1
5218 22:50:13.226697
5219 22:50:13.229927 RX Delay -80 -> 252, step: 8
5220 22:50:13.233239 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5221 22:50:13.236167 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5222 22:50:13.239469 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5223 22:50:13.246379 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5224 22:50:13.249914 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5225 22:50:13.252710 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5226 22:50:13.256331 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5227 22:50:13.260041 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5228 22:50:13.263146 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5229 22:50:13.269598 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5230 22:50:13.272494 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5231 22:50:13.276238 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5232 22:50:13.279212 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5233 22:50:13.282407 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5234 22:50:13.289380 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5235 22:50:13.292285 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5236 22:50:13.292366 ==
5237 22:50:13.295907 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 22:50:13.298861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 22:50:13.298942 ==
5240 22:50:13.302471 DQS Delay:
5241 22:50:13.302551 DQS0 = 0, DQS1 = 0
5242 22:50:13.302615 DQM Delay:
5243 22:50:13.305566 DQM0 = 96, DQM1 = 86
5244 22:50:13.305647 DQ Delay:
5245 22:50:13.308959 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5246 22:50:13.312050 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5247 22:50:13.315456 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5248 22:50:13.319129 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5249 22:50:13.319208
5250 22:50:13.319292
5251 22:50:13.321934 ==
5252 22:50:13.322015 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 22:50:13.328783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 22:50:13.328866 ==
5255 22:50:13.328929
5256 22:50:13.328987
5257 22:50:13.331861 TX Vref Scan disable
5258 22:50:13.331942 == TX Byte 0 ==
5259 22:50:13.335111 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5260 22:50:13.342017 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5261 22:50:13.342114 == TX Byte 1 ==
5262 22:50:13.344961 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5263 22:50:13.351956 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5264 22:50:13.352062 ==
5265 22:50:13.354964 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 22:50:13.358152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 22:50:13.358231 ==
5268 22:50:13.358314
5269 22:50:13.358411
5270 22:50:13.361293 TX Vref Scan disable
5271 22:50:13.365157 == TX Byte 0 ==
5272 22:50:13.368537 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5273 22:50:13.372023 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5274 22:50:13.375245 == TX Byte 1 ==
5275 22:50:13.378114 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5276 22:50:13.381544 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5277 22:50:13.381622
5278 22:50:13.384947 [DATLAT]
5279 22:50:13.385045 Freq=933, CH0 RK0
5280 22:50:13.385142
5281 22:50:13.388308 DATLAT Default: 0xd
5282 22:50:13.388405 0, 0xFFFF, sum = 0
5283 22:50:13.391563 1, 0xFFFF, sum = 0
5284 22:50:13.391664 2, 0xFFFF, sum = 0
5285 22:50:13.394936 3, 0xFFFF, sum = 0
5286 22:50:13.395012 4, 0xFFFF, sum = 0
5287 22:50:13.398081 5, 0xFFFF, sum = 0
5288 22:50:13.398154 6, 0xFFFF, sum = 0
5289 22:50:13.401237 7, 0xFFFF, sum = 0
5290 22:50:13.401349 8, 0xFFFF, sum = 0
5291 22:50:13.404780 9, 0xFFFF, sum = 0
5292 22:50:13.404882 10, 0x0, sum = 1
5293 22:50:13.408042 11, 0x0, sum = 2
5294 22:50:13.408153 12, 0x0, sum = 3
5295 22:50:13.411171 13, 0x0, sum = 4
5296 22:50:13.411282 best_step = 11
5297 22:50:13.411372
5298 22:50:13.411459 ==
5299 22:50:13.414361 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 22:50:13.421087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 22:50:13.421197 ==
5302 22:50:13.421291 RX Vref Scan: 1
5303 22:50:13.421409
5304 22:50:13.424248 RX Vref 0 -> 0, step: 1
5305 22:50:13.424354
5306 22:50:13.427776 RX Delay -61 -> 252, step: 4
5307 22:50:13.427848
5308 22:50:13.430745 Set Vref, RX VrefLevel [Byte0]: 59
5309 22:50:13.434175 [Byte1]: 49
5310 22:50:13.434269
5311 22:50:13.437968 Final RX Vref Byte 0 = 59 to rank0
5312 22:50:13.440629 Final RX Vref Byte 1 = 49 to rank0
5313 22:50:13.443955 Final RX Vref Byte 0 = 59 to rank1
5314 22:50:13.447366 Final RX Vref Byte 1 = 49 to rank1==
5315 22:50:13.450998 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 22:50:13.454167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 22:50:13.454236 ==
5318 22:50:13.457224 DQS Delay:
5319 22:50:13.457316 DQS0 = 0, DQS1 = 0
5320 22:50:13.460433 DQM Delay:
5321 22:50:13.460524 DQM0 = 97, DQM1 = 85
5322 22:50:13.460609 DQ Delay:
5323 22:50:13.463843 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5324 22:50:13.467137 DQ4 =98, DQ5 =88, DQ6 =108, DQ7 =106
5325 22:50:13.470682 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5326 22:50:13.474259 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =92
5327 22:50:13.474335
5328 22:50:13.477614
5329 22:50:13.484062 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5330 22:50:13.486947 CH0 RK0: MR19=505, MR18=2D13
5331 22:50:13.493226 CH0_RK0: MR19=0x505, MR18=0x2D13, DQSOSC=407, MR23=63, INC=65, DEC=43
5332 22:50:13.493325
5333 22:50:13.496836 ----->DramcWriteLeveling(PI) begin...
5334 22:50:13.496932 ==
5335 22:50:13.500397 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 22:50:13.503455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 22:50:13.503527 ==
5338 22:50:13.507025 Write leveling (Byte 0): 33 => 33
5339 22:50:13.509767 Write leveling (Byte 1): 32 => 32
5340 22:50:13.513321 DramcWriteLeveling(PI) end<-----
5341 22:50:13.513456
5342 22:50:13.513543 ==
5343 22:50:13.516724 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 22:50:13.520014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 22:50:13.520108 ==
5346 22:50:13.523392 [Gating] SW mode calibration
5347 22:50:13.529942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5348 22:50:13.536367 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5349 22:50:13.539556 0 14 0 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 0)
5350 22:50:13.546003 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 22:50:13.549482 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 22:50:13.553114 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 22:50:13.559440 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 22:50:13.562575 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 22:50:13.565907 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 22:50:13.572909 0 14 28 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
5357 22:50:13.575735 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
5358 22:50:13.579144 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 22:50:13.586092 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 22:50:13.589251 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 22:50:13.592404 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 22:50:13.598887 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 22:50:13.602447 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 22:50:13.605747 0 15 28 | B1->B0 | 2727 3232 | 0 1 | (0 0) (0 0)
5365 22:50:13.612283 1 0 0 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
5366 22:50:13.615377 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 22:50:13.618495 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 22:50:13.625096 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 22:50:13.628483 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 22:50:13.631621 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 22:50:13.638317 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 22:50:13.641611 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 22:50:13.644586 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 22:50:13.651660 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 22:50:13.654668 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 22:50:13.658394 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 22:50:13.664513 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 22:50:13.668040 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 22:50:13.670835 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 22:50:13.677925 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 22:50:13.681294 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 22:50:13.684629 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 22:50:13.691332 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 22:50:13.693974 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 22:50:13.697393 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 22:50:13.704363 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 22:50:13.707399 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 22:50:13.710653 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5389 22:50:13.717605 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5390 22:50:13.717687 Total UI for P1: 0, mck2ui 16
5391 22:50:13.723781 best dqsien dly found for B0: ( 1, 2, 28)
5392 22:50:13.727274 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 22:50:13.730669 Total UI for P1: 0, mck2ui 16
5394 22:50:13.734080 best dqsien dly found for B1: ( 1, 2, 30)
5395 22:50:13.736884 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5396 22:50:13.740315 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5397 22:50:13.740409
5398 22:50:13.743782 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5399 22:50:13.747229 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5400 22:50:13.750645 [Gating] SW calibration Done
5401 22:50:13.750719 ==
5402 22:50:13.753457 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 22:50:13.760174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 22:50:13.760275 ==
5405 22:50:13.760365 RX Vref Scan: 0
5406 22:50:13.760455
5407 22:50:13.763257 RX Vref 0 -> 0, step: 1
5408 22:50:13.763354
5409 22:50:13.766777 RX Delay -80 -> 252, step: 8
5410 22:50:13.769699 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5411 22:50:13.773748 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5412 22:50:13.776444 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5413 22:50:13.779967 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5414 22:50:13.783189 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5415 22:50:13.790016 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5416 22:50:13.793121 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5417 22:50:13.796637 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5418 22:50:13.799385 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5419 22:50:13.802979 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5420 22:50:13.809122 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5421 22:50:13.812547 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5422 22:50:13.816318 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5423 22:50:13.819100 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5424 22:50:13.822735 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5425 22:50:13.829107 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5426 22:50:13.829189 ==
5427 22:50:13.832847 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 22:50:13.835628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 22:50:13.835740 ==
5430 22:50:13.835831 DQS Delay:
5431 22:50:13.838980 DQS0 = 0, DQS1 = 0
5432 22:50:13.839060 DQM Delay:
5433 22:50:13.842488 DQM0 = 96, DQM1 = 88
5434 22:50:13.842569 DQ Delay:
5435 22:50:13.845464 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5436 22:50:13.849079 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5437 22:50:13.852353 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5438 22:50:13.856024 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5439 22:50:13.856106
5440 22:50:13.856169
5441 22:50:13.856228 ==
5442 22:50:13.858778 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 22:50:13.862267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 22:50:13.865531 ==
5445 22:50:13.865612
5446 22:50:13.865674
5447 22:50:13.865732 TX Vref Scan disable
5448 22:50:13.868626 == TX Byte 0 ==
5449 22:50:13.872244 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5450 22:50:13.875348 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5451 22:50:13.878474 == TX Byte 1 ==
5452 22:50:13.882188 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5453 22:50:13.885532 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5454 22:50:13.888598 ==
5455 22:50:13.892019 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 22:50:13.895344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 22:50:13.895435 ==
5458 22:50:13.895524
5459 22:50:13.895595
5460 22:50:13.898872 TX Vref Scan disable
5461 22:50:13.898954 == TX Byte 0 ==
5462 22:50:13.905345 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5463 22:50:13.908555 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5464 22:50:13.908634 == TX Byte 1 ==
5465 22:50:13.915097 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5466 22:50:13.918430 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5467 22:50:13.918512
5468 22:50:13.918575 [DATLAT]
5469 22:50:13.921499 Freq=933, CH0 RK1
5470 22:50:13.921580
5471 22:50:13.921643 DATLAT Default: 0xb
5472 22:50:13.924869 0, 0xFFFF, sum = 0
5473 22:50:13.928227 1, 0xFFFF, sum = 0
5474 22:50:13.928310 2, 0xFFFF, sum = 0
5475 22:50:13.931575 3, 0xFFFF, sum = 0
5476 22:50:13.931656 4, 0xFFFF, sum = 0
5477 22:50:13.934685 5, 0xFFFF, sum = 0
5478 22:50:13.934768 6, 0xFFFF, sum = 0
5479 22:50:13.937801 7, 0xFFFF, sum = 0
5480 22:50:13.937916 8, 0xFFFF, sum = 0
5481 22:50:13.941423 9, 0xFFFF, sum = 0
5482 22:50:13.941505 10, 0x0, sum = 1
5483 22:50:13.944779 11, 0x0, sum = 2
5484 22:50:13.944860 12, 0x0, sum = 3
5485 22:50:13.947614 13, 0x0, sum = 4
5486 22:50:13.947696 best_step = 11
5487 22:50:13.947759
5488 22:50:13.947817 ==
5489 22:50:13.951060 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 22:50:13.954563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 22:50:13.954645 ==
5492 22:50:13.957583 RX Vref Scan: 0
5493 22:50:13.957664
5494 22:50:13.960644 RX Vref 0 -> 0, step: 1
5495 22:50:13.960726
5496 22:50:13.960790 RX Delay -61 -> 252, step: 4
5497 22:50:13.969112 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5498 22:50:13.972587 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5499 22:50:13.975770 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5500 22:50:13.978885 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5501 22:50:13.982259 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5502 22:50:13.988864 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5503 22:50:13.991913 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5504 22:50:13.995347 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5505 22:50:13.998922 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5506 22:50:14.002168 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5507 22:50:14.008994 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5508 22:50:14.011835 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5509 22:50:14.015125 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5510 22:50:14.018482 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5511 22:50:14.021444 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5512 22:50:14.028408 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5513 22:50:14.028516 ==
5514 22:50:14.031720 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 22:50:14.035056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 22:50:14.035138 ==
5517 22:50:14.035202 DQS Delay:
5518 22:50:14.037940 DQS0 = 0, DQS1 = 0
5519 22:50:14.038084 DQM Delay:
5520 22:50:14.041176 DQM0 = 94, DQM1 = 85
5521 22:50:14.041274 DQ Delay:
5522 22:50:14.044911 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5523 22:50:14.048259 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =104
5524 22:50:14.051193 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5525 22:50:14.054617 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5526 22:50:14.054698
5527 22:50:14.054760
5528 22:50:14.064661 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5529 22:50:14.064800 CH0 RK1: MR19=504, MR18=2BFB
5530 22:50:14.071214 CH0_RK1: MR19=0x504, MR18=0x2BFB, DQSOSC=408, MR23=63, INC=65, DEC=43
5531 22:50:14.074442 [RxdqsGatingPostProcess] freq 933
5532 22:50:14.080754 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5533 22:50:14.084532 best DQS0 dly(2T, 0.5T) = (0, 10)
5534 22:50:14.087518 best DQS1 dly(2T, 0.5T) = (0, 11)
5535 22:50:14.090931 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5536 22:50:14.093793 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5537 22:50:14.097368 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 22:50:14.097489 best DQS1 dly(2T, 0.5T) = (0, 10)
5539 22:50:14.100808 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 22:50:14.103860 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5541 22:50:14.107307 Pre-setting of DQS Precalculation
5542 22:50:14.113427 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5543 22:50:14.113509 ==
5544 22:50:14.116632 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 22:50:14.119828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 22:50:14.119910 ==
5547 22:50:14.126581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 22:50:14.133050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5549 22:50:14.136412 [CA 0] Center 36 (6~67) winsize 62
5550 22:50:14.140136 [CA 1] Center 36 (6~67) winsize 62
5551 22:50:14.142954 [CA 2] Center 34 (4~65) winsize 62
5552 22:50:14.146488 [CA 3] Center 33 (3~64) winsize 62
5553 22:50:14.150038 [CA 4] Center 34 (4~64) winsize 61
5554 22:50:14.152975 [CA 5] Center 33 (3~64) winsize 62
5555 22:50:14.153082
5556 22:50:14.156347 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5557 22:50:14.156429
5558 22:50:14.159378 [CATrainingPosCal] consider 1 rank data
5559 22:50:14.163307 u2DelayCellTimex100 = 270/100 ps
5560 22:50:14.166044 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 22:50:14.169462 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5562 22:50:14.173084 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 22:50:14.175801 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 22:50:14.182379 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5565 22:50:14.186188 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5566 22:50:14.186269
5567 22:50:14.189017 CA PerBit enable=1, Macro0, CA PI delay=33
5568 22:50:14.189098
5569 22:50:14.192424 [CBTSetCACLKResult] CA Dly = 33
5570 22:50:14.192506 CS Dly: 5 (0~36)
5571 22:50:14.192583 ==
5572 22:50:14.195826 Dram Type= 6, Freq= 0, CH_1, rank 1
5573 22:50:14.202346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 22:50:14.202429 ==
5575 22:50:14.205559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 22:50:14.212217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5577 22:50:14.215340 [CA 0] Center 36 (6~67) winsize 62
5578 22:50:14.219013 [CA 1] Center 37 (7~67) winsize 61
5579 22:50:14.222303 [CA 2] Center 34 (4~65) winsize 62
5580 22:50:14.225764 [CA 3] Center 33 (3~64) winsize 62
5581 22:50:14.228635 [CA 4] Center 34 (3~65) winsize 63
5582 22:50:14.231720 [CA 5] Center 33 (3~64) winsize 62
5583 22:50:14.231802
5584 22:50:14.235137 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5585 22:50:14.235218
5586 22:50:14.238497 [CATrainingPosCal] consider 2 rank data
5587 22:50:14.242386 u2DelayCellTimex100 = 270/100 ps
5588 22:50:14.245216 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5589 22:50:14.248576 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5590 22:50:14.255182 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5591 22:50:14.258094 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 22:50:14.261556 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5593 22:50:14.265070 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5594 22:50:14.265152
5595 22:50:14.268208 CA PerBit enable=1, Macro0, CA PI delay=33
5596 22:50:14.268320
5597 22:50:14.271380 [CBTSetCACLKResult] CA Dly = 33
5598 22:50:14.274609 CS Dly: 6 (0~39)
5599 22:50:14.274690
5600 22:50:14.277802 ----->DramcWriteLeveling(PI) begin...
5601 22:50:14.277884 ==
5602 22:50:14.281019 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 22:50:14.284617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 22:50:14.284699 ==
5605 22:50:14.287741 Write leveling (Byte 0): 28 => 28
5606 22:50:14.291484 Write leveling (Byte 1): 30 => 30
5607 22:50:14.294671 DramcWriteLeveling(PI) end<-----
5608 22:50:14.294752
5609 22:50:14.294815 ==
5610 22:50:14.297557 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 22:50:14.301507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 22:50:14.301589 ==
5613 22:50:14.304304 [Gating] SW mode calibration
5614 22:50:14.310773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5615 22:50:14.317652 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5616 22:50:14.320646 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5617 22:50:14.324176 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 22:50:14.330788 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 22:50:14.334042 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 22:50:14.337107 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 22:50:14.343893 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5622 22:50:14.347312 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5623 22:50:14.350362 0 14 28 | B1->B0 | 2f2f 2b2b | 0 0 | (1 1) (0 0)
5624 22:50:14.356807 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5625 22:50:14.360278 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 22:50:14.363759 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 22:50:14.370353 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 22:50:14.373451 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 22:50:14.376430 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 22:50:14.383058 0 15 24 | B1->B0 | 2424 2828 | 1 0 | (0 0) (0 0)
5631 22:50:14.386333 0 15 28 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (1 1)
5632 22:50:14.389761 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 22:50:14.396609 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 22:50:14.399697 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 22:50:14.406480 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 22:50:14.409326 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 22:50:14.412844 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 22:50:14.416296 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5639 22:50:14.422801 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5640 22:50:14.426352 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 22:50:14.429474 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 22:50:14.436240 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 22:50:14.439334 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 22:50:14.442842 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 22:50:14.449587 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 22:50:14.452655 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 22:50:14.456065 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 22:50:14.462649 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 22:50:14.465713 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 22:50:14.469220 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 22:50:14.475469 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 22:50:14.479001 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 22:50:14.482357 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 22:50:14.488873 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5655 22:50:14.492631 Total UI for P1: 0, mck2ui 16
5656 22:50:14.495412 best dqsien dly found for B0: ( 1, 2, 22)
5657 22:50:14.498955 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 22:50:14.502457 Total UI for P1: 0, mck2ui 16
5659 22:50:14.505458 best dqsien dly found for B1: ( 1, 2, 24)
5660 22:50:14.508826 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5661 22:50:14.512482 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5662 22:50:14.512563
5663 22:50:14.515348 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5664 22:50:14.518522 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5665 22:50:14.521990 [Gating] SW calibration Done
5666 22:50:14.522070 ==
5667 22:50:14.524959 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 22:50:14.532071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 22:50:14.532151 ==
5670 22:50:14.532214 RX Vref Scan: 0
5671 22:50:14.532273
5672 22:50:14.535032 RX Vref 0 -> 0, step: 1
5673 22:50:14.535112
5674 22:50:14.538809 RX Delay -80 -> 252, step: 8
5675 22:50:14.541972 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5676 22:50:14.545042 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5677 22:50:14.548559 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5678 22:50:14.551693 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5679 22:50:14.558340 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5680 22:50:14.562188 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5681 22:50:14.564749 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5682 22:50:14.568537 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5683 22:50:14.571403 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5684 22:50:14.578272 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5685 22:50:14.581114 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5686 22:50:14.584605 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5687 22:50:14.588138 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5688 22:50:14.591052 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5689 22:50:14.594444 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5690 22:50:14.600784 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5691 22:50:14.600865 ==
5692 22:50:14.604043 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 22:50:14.607597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 22:50:14.607679 ==
5695 22:50:14.607743 DQS Delay:
5696 22:50:14.610656 DQS0 = 0, DQS1 = 0
5697 22:50:14.610737 DQM Delay:
5698 22:50:14.614193 DQM0 = 102, DQM1 = 90
5699 22:50:14.614274 DQ Delay:
5700 22:50:14.617584 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5701 22:50:14.620914 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5702 22:50:14.624072 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5703 22:50:14.627468 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5704 22:50:14.627549
5705 22:50:14.627612
5706 22:50:14.627670 ==
5707 22:50:14.630961 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 22:50:14.637544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 22:50:14.637627 ==
5710 22:50:14.637722
5711 22:50:14.637828
5712 22:50:14.637889 TX Vref Scan disable
5713 22:50:14.641025 == TX Byte 0 ==
5714 22:50:14.643775 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5715 22:50:14.650495 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5716 22:50:14.650576 == TX Byte 1 ==
5717 22:50:14.654061 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5718 22:50:14.660428 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5719 22:50:14.660509 ==
5720 22:50:14.663818 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 22:50:14.666687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 22:50:14.666769 ==
5723 22:50:14.666833
5724 22:50:14.666891
5725 22:50:14.670066 TX Vref Scan disable
5726 22:50:14.673777 == TX Byte 0 ==
5727 22:50:14.676814 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5728 22:50:14.680106 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5729 22:50:14.683068 == TX Byte 1 ==
5730 22:50:14.686743 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5731 22:50:14.690334 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5732 22:50:14.690415
5733 22:50:14.690478 [DATLAT]
5734 22:50:14.692950 Freq=933, CH1 RK0
5735 22:50:14.693031
5736 22:50:14.696502 DATLAT Default: 0xd
5737 22:50:14.696583 0, 0xFFFF, sum = 0
5738 22:50:14.700254 1, 0xFFFF, sum = 0
5739 22:50:14.700335 2, 0xFFFF, sum = 0
5740 22:50:14.702952 3, 0xFFFF, sum = 0
5741 22:50:14.703034 4, 0xFFFF, sum = 0
5742 22:50:14.706555 5, 0xFFFF, sum = 0
5743 22:50:14.706637 6, 0xFFFF, sum = 0
5744 22:50:14.710219 7, 0xFFFF, sum = 0
5745 22:50:14.710301 8, 0xFFFF, sum = 0
5746 22:50:14.712743 9, 0xFFFF, sum = 0
5747 22:50:14.712825 10, 0x0, sum = 1
5748 22:50:14.716007 11, 0x0, sum = 2
5749 22:50:14.716137 12, 0x0, sum = 3
5750 22:50:14.719843 13, 0x0, sum = 4
5751 22:50:14.719925 best_step = 11
5752 22:50:14.719989
5753 22:50:14.720047 ==
5754 22:50:14.723029 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 22:50:14.725927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 22:50:14.729234 ==
5757 22:50:14.729315 RX Vref Scan: 1
5758 22:50:14.729417
5759 22:50:14.732662 RX Vref 0 -> 0, step: 1
5760 22:50:14.732742
5761 22:50:14.735982 RX Delay -69 -> 252, step: 4
5762 22:50:14.736063
5763 22:50:14.739425 Set Vref, RX VrefLevel [Byte0]: 46
5764 22:50:14.742418 [Byte1]: 57
5765 22:50:14.742510
5766 22:50:14.746056 Final RX Vref Byte 0 = 46 to rank0
5767 22:50:14.749515 Final RX Vref Byte 1 = 57 to rank0
5768 22:50:14.752808 Final RX Vref Byte 0 = 46 to rank1
5769 22:50:14.756021 Final RX Vref Byte 1 = 57 to rank1==
5770 22:50:14.759301 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 22:50:14.762535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 22:50:14.762616 ==
5773 22:50:14.765908 DQS Delay:
5774 22:50:14.765988 DQS0 = 0, DQS1 = 0
5775 22:50:14.766050 DQM Delay:
5776 22:50:14.769272 DQM0 = 100, DQM1 = 94
5777 22:50:14.769376 DQ Delay:
5778 22:50:14.771989 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =96
5779 22:50:14.775481 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =94
5780 22:50:14.778672 DQ8 =84, DQ9 =86, DQ10 =92, DQ11 =84
5781 22:50:14.782566 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102
5782 22:50:14.782662
5783 22:50:14.785163
5784 22:50:14.792573 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5785 22:50:14.795378 CH1 RK0: MR19=505, MR18=1909
5786 22:50:14.801831 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5787 22:50:14.801912
5788 22:50:14.805763 ----->DramcWriteLeveling(PI) begin...
5789 22:50:14.805855 ==
5790 22:50:14.808389 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 22:50:14.812079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 22:50:14.812170 ==
5793 22:50:14.815545 Write leveling (Byte 0): 24 => 24
5794 22:50:14.818649 Write leveling (Byte 1): 25 => 25
5795 22:50:14.821698 DramcWriteLeveling(PI) end<-----
5796 22:50:14.821778
5797 22:50:14.821839 ==
5798 22:50:14.825268 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 22:50:14.828015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 22:50:14.828096 ==
5801 22:50:14.831933 [Gating] SW mode calibration
5802 22:50:14.838215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5803 22:50:14.844898 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5804 22:50:14.847726 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5805 22:50:14.854782 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 22:50:14.857940 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 22:50:14.860852 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 22:50:14.867433 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 22:50:14.870561 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 22:50:14.873972 0 14 24 | B1->B0 | 3030 3333 | 1 1 | (1 0) (1 1)
5811 22:50:14.880548 0 14 28 | B1->B0 | 2d2d 3030 | 0 1 | (1 0) (1 0)
5812 22:50:14.884128 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 22:50:14.887604 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 22:50:14.894058 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 22:50:14.897477 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 22:50:14.900719 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 22:50:14.907373 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 22:50:14.910734 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5819 22:50:14.913622 0 15 28 | B1->B0 | 3c3c 3434 | 0 0 | (0 0) (0 0)
5820 22:50:14.920426 1 0 0 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
5821 22:50:14.923348 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 22:50:14.926758 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 22:50:14.933410 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 22:50:14.936843 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 22:50:14.940396 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 22:50:14.946455 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5827 22:50:14.950185 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5828 22:50:14.953173 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 22:50:14.959803 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 22:50:14.963018 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 22:50:14.966560 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 22:50:14.972794 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 22:50:14.976391 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 22:50:14.979499 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 22:50:14.986344 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 22:50:14.989602 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 22:50:14.993008 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 22:50:14.999240 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 22:50:15.002669 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 22:50:15.006317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 22:50:15.012735 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 22:50:15.016013 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5843 22:50:15.019318 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5844 22:50:15.022758 Total UI for P1: 0, mck2ui 16
5845 22:50:15.026065 best dqsien dly found for B1: ( 1, 2, 24)
5846 22:50:15.032892 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5847 22:50:15.035946 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 22:50:15.038779 Total UI for P1: 0, mck2ui 16
5849 22:50:15.042612 best dqsien dly found for B0: ( 1, 2, 28)
5850 22:50:15.045763 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5851 22:50:15.049515 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5852 22:50:15.049597
5853 22:50:15.052010 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5854 22:50:15.055523 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5855 22:50:15.059154 [Gating] SW calibration Done
5856 22:50:15.059236 ==
5857 22:50:15.062105 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 22:50:15.065885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 22:50:15.068694 ==
5860 22:50:15.068775 RX Vref Scan: 0
5861 22:50:15.068839
5862 22:50:15.072145 RX Vref 0 -> 0, step: 1
5863 22:50:15.072227
5864 22:50:15.075603 RX Delay -80 -> 252, step: 8
5865 22:50:15.078549 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5866 22:50:15.085662 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5867 22:50:15.085750 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5868 22:50:15.088666 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5869 22:50:15.091631 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5870 22:50:15.098992 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5871 22:50:15.101956 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5872 22:50:15.104990 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5873 22:50:15.108102 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5874 22:50:15.111768 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5875 22:50:15.118131 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5876 22:50:15.121888 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5877 22:50:15.124744 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5878 22:50:15.128367 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5879 22:50:15.131331 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5880 22:50:15.134579 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5881 22:50:15.138266 ==
5882 22:50:15.141436 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 22:50:15.144567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 22:50:15.144650 ==
5885 22:50:15.144713 DQS Delay:
5886 22:50:15.148108 DQS0 = 0, DQS1 = 0
5887 22:50:15.148192 DQM Delay:
5888 22:50:15.151290 DQM0 = 99, DQM1 = 90
5889 22:50:15.151371 DQ Delay:
5890 22:50:15.154968 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5891 22:50:15.158284 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5892 22:50:15.161035 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5893 22:50:15.164905 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5894 22:50:15.164987
5895 22:50:15.165051
5896 22:50:15.165110 ==
5897 22:50:15.168094 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 22:50:15.170873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 22:50:15.170958 ==
5900 22:50:15.174346
5901 22:50:15.174417
5902 22:50:15.174479 TX Vref Scan disable
5903 22:50:15.177765 == TX Byte 0 ==
5904 22:50:15.180758 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5905 22:50:15.184403 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5906 22:50:15.187723 == TX Byte 1 ==
5907 22:50:15.190608 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5908 22:50:15.194005 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5909 22:50:15.194075 ==
5910 22:50:15.197567 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 22:50:15.204050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 22:50:15.204129 ==
5913 22:50:15.204192
5914 22:50:15.204250
5915 22:50:15.207024 TX Vref Scan disable
5916 22:50:15.207095 == TX Byte 0 ==
5917 22:50:15.214164 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5918 22:50:15.217034 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5919 22:50:15.217102 == TX Byte 1 ==
5920 22:50:15.223670 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5921 22:50:15.226731 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5922 22:50:15.226810
5923 22:50:15.226876 [DATLAT]
5924 22:50:15.230005 Freq=933, CH1 RK1
5925 22:50:15.230080
5926 22:50:15.230141 DATLAT Default: 0xb
5927 22:50:15.233863 0, 0xFFFF, sum = 0
5928 22:50:15.233939 1, 0xFFFF, sum = 0
5929 22:50:15.236848 2, 0xFFFF, sum = 0
5930 22:50:15.236918 3, 0xFFFF, sum = 0
5931 22:50:15.240396 4, 0xFFFF, sum = 0
5932 22:50:15.240480 5, 0xFFFF, sum = 0
5933 22:50:15.243545 6, 0xFFFF, sum = 0
5934 22:50:15.246669 7, 0xFFFF, sum = 0
5935 22:50:15.246752 8, 0xFFFF, sum = 0
5936 22:50:15.250281 9, 0xFFFF, sum = 0
5937 22:50:15.250364 10, 0x0, sum = 1
5938 22:50:15.250429 11, 0x0, sum = 2
5939 22:50:15.253292 12, 0x0, sum = 3
5940 22:50:15.253414 13, 0x0, sum = 4
5941 22:50:15.256571 best_step = 11
5942 22:50:15.256653
5943 22:50:15.256716 ==
5944 22:50:15.260091 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 22:50:15.263236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 22:50:15.263317 ==
5947 22:50:15.266686 RX Vref Scan: 0
5948 22:50:15.266761
5949 22:50:15.266822 RX Vref 0 -> 0, step: 1
5950 22:50:15.269963
5951 22:50:15.270035 RX Delay -61 -> 252, step: 4
5952 22:50:15.277156 iDelay=203, Bit 0, Center 104 (15 ~ 194) 180
5953 22:50:15.280669 iDelay=203, Bit 1, Center 94 (7 ~ 182) 176
5954 22:50:15.284220 iDelay=203, Bit 2, Center 90 (3 ~ 178) 176
5955 22:50:15.287156 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5956 22:50:15.290585 iDelay=203, Bit 4, Center 100 (11 ~ 190) 180
5957 22:50:15.296945 iDelay=203, Bit 5, Center 112 (27 ~ 198) 172
5958 22:50:15.300763 iDelay=203, Bit 6, Center 112 (23 ~ 202) 180
5959 22:50:15.303597 iDelay=203, Bit 7, Center 98 (7 ~ 190) 184
5960 22:50:15.306668 iDelay=203, Bit 8, Center 84 (-5 ~ 174) 180
5961 22:50:15.310127 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5962 22:50:15.316510 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5963 22:50:15.319777 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5964 22:50:15.323295 iDelay=203, Bit 12, Center 102 (11 ~ 194) 184
5965 22:50:15.327050 iDelay=203, Bit 13, Center 102 (11 ~ 194) 184
5966 22:50:15.329785 iDelay=203, Bit 14, Center 102 (11 ~ 194) 184
5967 22:50:15.336569 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5968 22:50:15.336655 ==
5969 22:50:15.339907 Dram Type= 6, Freq= 0, CH_1, rank 1
5970 22:50:15.342838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5971 22:50:15.342914 ==
5972 22:50:15.342981 DQS Delay:
5973 22:50:15.346354 DQS0 = 0, DQS1 = 0
5974 22:50:15.346434 DQM Delay:
5975 22:50:15.349828 DQM0 = 101, DQM1 = 94
5976 22:50:15.349909 DQ Delay:
5977 22:50:15.352966 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
5978 22:50:15.356411 DQ4 =100, DQ5 =112, DQ6 =112, DQ7 =98
5979 22:50:15.359553 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5980 22:50:15.362947 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5981 22:50:15.363018
5982 22:50:15.363077
5983 22:50:15.372329 [DQSOSCAuto] RK1, (LSB)MR18= 0xb05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
5984 22:50:15.375651 CH1 RK1: MR19=505, MR18=B05
5985 22:50:15.378956 CH1_RK1: MR19=0x505, MR18=0xB05, DQSOSC=418, MR23=63, INC=62, DEC=41
5986 22:50:15.382289 [RxdqsGatingPostProcess] freq 933
5987 22:50:15.389072 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5988 22:50:15.392437 best DQS0 dly(2T, 0.5T) = (0, 10)
5989 22:50:15.396018 best DQS1 dly(2T, 0.5T) = (0, 10)
5990 22:50:15.398862 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5991 22:50:15.402748 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5992 22:50:15.405680 best DQS0 dly(2T, 0.5T) = (0, 10)
5993 22:50:15.409228 best DQS1 dly(2T, 0.5T) = (0, 10)
5994 22:50:15.412082 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5995 22:50:15.415555 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5996 22:50:15.418928 Pre-setting of DQS Precalculation
5997 22:50:15.422120 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5998 22:50:15.428359 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5999 22:50:15.435057 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6000 22:50:15.438370
6001 22:50:15.438437
6002 22:50:15.438496 [Calibration Summary] 1866 Mbps
6003 22:50:15.441761 CH 0, Rank 0
6004 22:50:15.441837 SW Impedance : PASS
6005 22:50:15.444918 DUTY Scan : NO K
6006 22:50:15.448634 ZQ Calibration : PASS
6007 22:50:15.448710 Jitter Meter : NO K
6008 22:50:15.451680 CBT Training : PASS
6009 22:50:15.454998 Write leveling : PASS
6010 22:50:15.455068 RX DQS gating : PASS
6011 22:50:15.458497 RX DQ/DQS(RDDQC) : PASS
6012 22:50:15.461762 TX DQ/DQS : PASS
6013 22:50:15.461839 RX DATLAT : PASS
6014 22:50:15.464639 RX DQ/DQS(Engine): PASS
6015 22:50:15.468300 TX OE : NO K
6016 22:50:15.468376 All Pass.
6017 22:50:15.468437
6018 22:50:15.468495 CH 0, Rank 1
6019 22:50:15.471303 SW Impedance : PASS
6020 22:50:15.475085 DUTY Scan : NO K
6021 22:50:15.475158 ZQ Calibration : PASS
6022 22:50:15.478140 Jitter Meter : NO K
6023 22:50:15.481249 CBT Training : PASS
6024 22:50:15.481351 Write leveling : PASS
6025 22:50:15.484670 RX DQS gating : PASS
6026 22:50:15.488184 RX DQ/DQS(RDDQC) : PASS
6027 22:50:15.488256 TX DQ/DQS : PASS
6028 22:50:15.491143 RX DATLAT : PASS
6029 22:50:15.494646 RX DQ/DQS(Engine): PASS
6030 22:50:15.494720 TX OE : NO K
6031 22:50:15.494784 All Pass.
6032 22:50:15.497869
6033 22:50:15.497937 CH 1, Rank 0
6034 22:50:15.501528 SW Impedance : PASS
6035 22:50:15.501600 DUTY Scan : NO K
6036 22:50:15.504811 ZQ Calibration : PASS
6037 22:50:15.507920 Jitter Meter : NO K
6038 22:50:15.507995 CBT Training : PASS
6039 22:50:15.510822 Write leveling : PASS
6040 22:50:15.510891 RX DQS gating : PASS
6041 22:50:15.514219 RX DQ/DQS(RDDQC) : PASS
6042 22:50:15.517819 TX DQ/DQS : PASS
6043 22:50:15.517902 RX DATLAT : PASS
6044 22:50:15.521149 RX DQ/DQS(Engine): PASS
6045 22:50:15.524090 TX OE : NO K
6046 22:50:15.524163 All Pass.
6047 22:50:15.524224
6048 22:50:15.524285 CH 1, Rank 1
6049 22:50:15.527795 SW Impedance : PASS
6050 22:50:15.530779 DUTY Scan : NO K
6051 22:50:15.530851 ZQ Calibration : PASS
6052 22:50:15.534466 Jitter Meter : NO K
6053 22:50:15.537219 CBT Training : PASS
6054 22:50:15.537317 Write leveling : PASS
6055 22:50:15.540433 RX DQS gating : PASS
6056 22:50:15.544115 RX DQ/DQS(RDDQC) : PASS
6057 22:50:15.544192 TX DQ/DQS : PASS
6058 22:50:15.547449 RX DATLAT : PASS
6059 22:50:15.550549 RX DQ/DQS(Engine): PASS
6060 22:50:15.550629 TX OE : NO K
6061 22:50:15.553676 All Pass.
6062 22:50:15.553746
6063 22:50:15.553806 DramC Write-DBI off
6064 22:50:15.557125 PER_BANK_REFRESH: Hybrid Mode
6065 22:50:15.557223 TX_TRACKING: ON
6066 22:50:15.566875 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6067 22:50:15.570297 [FAST_K] Save calibration result to emmc
6068 22:50:15.573207 dramc_set_vcore_voltage set vcore to 650000
6069 22:50:15.576595 Read voltage for 400, 6
6070 22:50:15.576676 Vio18 = 0
6071 22:50:15.579970 Vcore = 650000
6072 22:50:15.580041 Vdram = 0
6073 22:50:15.580101 Vddq = 0
6074 22:50:15.583408 Vmddr = 0
6075 22:50:15.586865 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6076 22:50:15.593546 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6077 22:50:15.593626 MEM_TYPE=3, freq_sel=20
6078 22:50:15.596758 sv_algorithm_assistance_LP4_800
6079 22:50:15.603246 ============ PULL DRAM RESETB DOWN ============
6080 22:50:15.606367 ========== PULL DRAM RESETB DOWN end =========
6081 22:50:15.609849 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6082 22:50:15.613325 ===================================
6083 22:50:15.616401 LPDDR4 DRAM CONFIGURATION
6084 22:50:15.619355 ===================================
6085 22:50:15.622758 EX_ROW_EN[0] = 0x0
6086 22:50:15.622833 EX_ROW_EN[1] = 0x0
6087 22:50:15.626227 LP4Y_EN = 0x0
6088 22:50:15.626297 WORK_FSP = 0x0
6089 22:50:15.629885 WL = 0x2
6090 22:50:15.629958 RL = 0x2
6091 22:50:15.632688 BL = 0x2
6092 22:50:15.632759 RPST = 0x0
6093 22:50:15.636463 RD_PRE = 0x0
6094 22:50:15.636532 WR_PRE = 0x1
6095 22:50:15.639453 WR_PST = 0x0
6096 22:50:15.639529 DBI_WR = 0x0
6097 22:50:15.642731 DBI_RD = 0x0
6098 22:50:15.642814 OTF = 0x1
6099 22:50:15.645839 ===================================
6100 22:50:15.649355 ===================================
6101 22:50:15.653156 ANA top config
6102 22:50:15.656142 ===================================
6103 22:50:15.659582 DLL_ASYNC_EN = 0
6104 22:50:15.659658 ALL_SLAVE_EN = 1
6105 22:50:15.662625 NEW_RANK_MODE = 1
6106 22:50:15.665958 DLL_IDLE_MODE = 1
6107 22:50:15.669549 LP45_APHY_COMB_EN = 1
6108 22:50:15.672358 TX_ODT_DIS = 1
6109 22:50:15.672433 NEW_8X_MODE = 1
6110 22:50:15.675910 ===================================
6111 22:50:15.679247 ===================================
6112 22:50:15.682572 data_rate = 800
6113 22:50:15.685859 CKR = 1
6114 22:50:15.689182 DQ_P2S_RATIO = 4
6115 22:50:15.692396 ===================================
6116 22:50:15.695781 CA_P2S_RATIO = 4
6117 22:50:15.699006 DQ_CA_OPEN = 0
6118 22:50:15.699082 DQ_SEMI_OPEN = 1
6119 22:50:15.702493 CA_SEMI_OPEN = 1
6120 22:50:15.705856 CA_FULL_RATE = 0
6121 22:50:15.708671 DQ_CKDIV4_EN = 0
6122 22:50:15.712119 CA_CKDIV4_EN = 1
6123 22:50:15.715659 CA_PREDIV_EN = 0
6124 22:50:15.715741 PH8_DLY = 0
6125 22:50:15.718721 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6126 22:50:15.722010 DQ_AAMCK_DIV = 0
6127 22:50:15.725117 CA_AAMCK_DIV = 0
6128 22:50:15.728836 CA_ADMCK_DIV = 4
6129 22:50:15.732081 DQ_TRACK_CA_EN = 0
6130 22:50:15.732162 CA_PICK = 800
6131 22:50:15.735312 CA_MCKIO = 400
6132 22:50:15.738627 MCKIO_SEMI = 400
6133 22:50:15.742099 PLL_FREQ = 3016
6134 22:50:15.745642 DQ_UI_PI_RATIO = 32
6135 22:50:15.748690 CA_UI_PI_RATIO = 32
6136 22:50:15.752172 ===================================
6137 22:50:15.755168 ===================================
6138 22:50:15.758289 memory_type:LPDDR4
6139 22:50:15.758366 GP_NUM : 10
6140 22:50:15.762071 SRAM_EN : 1
6141 22:50:15.762146 MD32_EN : 0
6142 22:50:15.764945 ===================================
6143 22:50:15.768307 [ANA_INIT] >>>>>>>>>>>>>>
6144 22:50:15.771751 <<<<<< [CONFIGURE PHASE]: ANA_TX
6145 22:50:15.775210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6146 22:50:15.778124 ===================================
6147 22:50:15.781683 data_rate = 800,PCW = 0X7400
6148 22:50:15.785007 ===================================
6149 22:50:15.787961 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6150 22:50:15.794716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6151 22:50:15.804574 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6152 22:50:15.807679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6153 22:50:15.811290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6154 22:50:15.814427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6155 22:50:15.817976 [ANA_INIT] flow start
6156 22:50:15.821057 [ANA_INIT] PLL >>>>>>>>
6157 22:50:15.821130 [ANA_INIT] PLL <<<<<<<<
6158 22:50:15.824542 [ANA_INIT] MIDPI >>>>>>>>
6159 22:50:15.827937 [ANA_INIT] MIDPI <<<<<<<<
6160 22:50:15.830917 [ANA_INIT] DLL >>>>>>>>
6161 22:50:15.830995 [ANA_INIT] flow end
6162 22:50:15.834183 ============ LP4 DIFF to SE enter ============
6163 22:50:15.840850 ============ LP4 DIFF to SE exit ============
6164 22:50:15.840930 [ANA_INIT] <<<<<<<<<<<<<
6165 22:50:15.844457 [Flow] Enable top DCM control >>>>>
6166 22:50:15.847394 [Flow] Enable top DCM control <<<<<
6167 22:50:15.851053 Enable DLL master slave shuffle
6168 22:50:15.857892 ==============================================================
6169 22:50:15.857970 Gating Mode config
6170 22:50:15.863880 ==============================================================
6171 22:50:15.867835 Config description:
6172 22:50:15.876967 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6173 22:50:15.884044 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6174 22:50:15.886847 SELPH_MODE 0: By rank 1: By Phase
6175 22:50:15.893776 ==============================================================
6176 22:50:15.897159 GAT_TRACK_EN = 0
6177 22:50:15.900213 RX_GATING_MODE = 2
6178 22:50:15.903510 RX_GATING_TRACK_MODE = 2
6179 22:50:15.903615 SELPH_MODE = 1
6180 22:50:15.907022 PICG_EARLY_EN = 1
6181 22:50:15.910167 VALID_LAT_VALUE = 1
6182 22:50:15.916597 ==============================================================
6183 22:50:15.919727 Enter into Gating configuration >>>>
6184 22:50:15.923005 Exit from Gating configuration <<<<
6185 22:50:15.926571 Enter into DVFS_PRE_config >>>>>
6186 22:50:15.936485 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6187 22:50:15.939715 Exit from DVFS_PRE_config <<<<<
6188 22:50:15.943214 Enter into PICG configuration >>>>
6189 22:50:15.946071 Exit from PICG configuration <<<<
6190 22:50:15.949538 [RX_INPUT] configuration >>>>>
6191 22:50:15.952793 [RX_INPUT] configuration <<<<<
6192 22:50:15.956296 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6193 22:50:15.962722 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6194 22:50:15.969548 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6195 22:50:15.975900 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6196 22:50:15.982477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6197 22:50:15.989225 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6198 22:50:15.992632 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6199 22:50:15.995733 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6200 22:50:15.998987 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6201 22:50:16.005748 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6202 22:50:16.008775 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6203 22:50:16.012303 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6204 22:50:16.015695 ===================================
6205 22:50:16.018990 LPDDR4 DRAM CONFIGURATION
6206 22:50:16.022434 ===================================
6207 22:50:16.022517 EX_ROW_EN[0] = 0x0
6208 22:50:16.025791 EX_ROW_EN[1] = 0x0
6209 22:50:16.029180 LP4Y_EN = 0x0
6210 22:50:16.029262 WORK_FSP = 0x0
6211 22:50:16.032407 WL = 0x2
6212 22:50:16.032485 RL = 0x2
6213 22:50:16.035199 BL = 0x2
6214 22:50:16.035274 RPST = 0x0
6215 22:50:16.038657 RD_PRE = 0x0
6216 22:50:16.038736 WR_PRE = 0x1
6217 22:50:16.041605 WR_PST = 0x0
6218 22:50:16.041687 DBI_WR = 0x0
6219 22:50:16.045181 DBI_RD = 0x0
6220 22:50:16.045261 OTF = 0x1
6221 22:50:16.048424 ===================================
6222 22:50:16.051911 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6223 22:50:16.058376 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6224 22:50:16.061908 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6225 22:50:16.065170 ===================================
6226 22:50:16.068780 LPDDR4 DRAM CONFIGURATION
6227 22:50:16.071510 ===================================
6228 22:50:16.071583 EX_ROW_EN[0] = 0x10
6229 22:50:16.074948 EX_ROW_EN[1] = 0x0
6230 22:50:16.078093 LP4Y_EN = 0x0
6231 22:50:16.078163 WORK_FSP = 0x0
6232 22:50:16.081286 WL = 0x2
6233 22:50:16.081366 RL = 0x2
6234 22:50:16.084606 BL = 0x2
6235 22:50:16.084688 RPST = 0x0
6236 22:50:16.088001 RD_PRE = 0x0
6237 22:50:16.088071 WR_PRE = 0x1
6238 22:50:16.091417 WR_PST = 0x0
6239 22:50:16.091486 DBI_WR = 0x0
6240 22:50:16.094603 DBI_RD = 0x0
6241 22:50:16.094712 OTF = 0x1
6242 22:50:16.098071 ===================================
6243 22:50:16.104413 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6244 22:50:16.108817 nWR fixed to 30
6245 22:50:16.112057 [ModeRegInit_LP4] CH0 RK0
6246 22:50:16.112138 [ModeRegInit_LP4] CH0 RK1
6247 22:50:16.115726 [ModeRegInit_LP4] CH1 RK0
6248 22:50:16.119003 [ModeRegInit_LP4] CH1 RK1
6249 22:50:16.119087 match AC timing 19
6250 22:50:16.125234 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6251 22:50:16.129052 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6252 22:50:16.132338 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6253 22:50:16.139409 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6254 22:50:16.142030 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6255 22:50:16.142115 ==
6256 22:50:16.145652 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 22:50:16.149026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 22:50:16.149105 ==
6259 22:50:16.155300 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6260 22:50:16.161833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6261 22:50:16.165166 [CA 0] Center 36 (8~64) winsize 57
6262 22:50:16.168630 [CA 1] Center 36 (8~64) winsize 57
6263 22:50:16.172116 [CA 2] Center 36 (8~64) winsize 57
6264 22:50:16.175086 [CA 3] Center 36 (8~64) winsize 57
6265 22:50:16.178555 [CA 4] Center 36 (8~64) winsize 57
6266 22:50:16.178631 [CA 5] Center 36 (8~64) winsize 57
6267 22:50:16.178692
6268 22:50:16.184877 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6269 22:50:16.184948
6270 22:50:16.188539 [CATrainingPosCal] consider 1 rank data
6271 22:50:16.192005 u2DelayCellTimex100 = 270/100 ps
6272 22:50:16.195286 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 22:50:16.198561 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 22:50:16.201468 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 22:50:16.205249 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 22:50:16.208200 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 22:50:16.211809 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 22:50:16.211882
6279 22:50:16.214771 CA PerBit enable=1, Macro0, CA PI delay=36
6280 22:50:16.214848
6281 22:50:16.218004 [CBTSetCACLKResult] CA Dly = 36
6282 22:50:16.221864 CS Dly: 1 (0~32)
6283 22:50:16.221937 ==
6284 22:50:16.224888 Dram Type= 6, Freq= 0, CH_0, rank 1
6285 22:50:16.228082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 22:50:16.228152 ==
6287 22:50:16.235333 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6288 22:50:16.241606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6289 22:50:16.244892 [CA 0] Center 36 (8~64) winsize 57
6290 22:50:16.244992 [CA 1] Center 36 (8~64) winsize 57
6291 22:50:16.248315 [CA 2] Center 36 (8~64) winsize 57
6292 22:50:16.251169 [CA 3] Center 36 (8~64) winsize 57
6293 22:50:16.254874 [CA 4] Center 36 (8~64) winsize 57
6294 22:50:16.258143 [CA 5] Center 36 (8~64) winsize 57
6295 22:50:16.258251
6296 22:50:16.260944 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6297 22:50:16.261040
6298 22:50:16.267909 [CATrainingPosCal] consider 2 rank data
6299 22:50:16.268001 u2DelayCellTimex100 = 270/100 ps
6300 22:50:16.274366 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 22:50:16.277922 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 22:50:16.280951 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 22:50:16.284443 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 22:50:16.287397 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 22:50:16.290863 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 22:50:16.290959
6307 22:50:16.294343 CA PerBit enable=1, Macro0, CA PI delay=36
6308 22:50:16.294442
6309 22:50:16.297507 [CBTSetCACLKResult] CA Dly = 36
6310 22:50:16.300851 CS Dly: 1 (0~32)
6311 22:50:16.300925
6312 22:50:16.304022 ----->DramcWriteLeveling(PI) begin...
6313 22:50:16.304134 ==
6314 22:50:16.307350 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 22:50:16.310536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 22:50:16.310626 ==
6317 22:50:16.313933 Write leveling (Byte 0): 40 => 8
6318 22:50:16.317732 Write leveling (Byte 1): 32 => 0
6319 22:50:16.320613 DramcWriteLeveling(PI) end<-----
6320 22:50:16.320686
6321 22:50:16.320747 ==
6322 22:50:16.323651 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 22:50:16.327130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 22:50:16.327229 ==
6325 22:50:16.330394 [Gating] SW mode calibration
6326 22:50:16.337640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6327 22:50:16.343833 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6328 22:50:16.347114 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6329 22:50:16.350086 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6330 22:50:16.356930 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 22:50:16.360099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6332 22:50:16.363816 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 22:50:16.370333 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 22:50:16.373809 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 22:50:16.376790 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 22:50:16.383225 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 22:50:16.386980 Total UI for P1: 0, mck2ui 16
6338 22:50:16.389811 best dqsien dly found for B0: ( 0, 14, 24)
6339 22:50:16.389885 Total UI for P1: 0, mck2ui 16
6340 22:50:16.396719 best dqsien dly found for B1: ( 0, 14, 24)
6341 22:50:16.399927 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6342 22:50:16.403511 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6343 22:50:16.403584
6344 22:50:16.406571 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6345 22:50:16.409579 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6346 22:50:16.413048 [Gating] SW calibration Done
6347 22:50:16.413127 ==
6348 22:50:16.416789 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 22:50:16.419770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 22:50:16.419841 ==
6351 22:50:16.423123 RX Vref Scan: 0
6352 22:50:16.423194
6353 22:50:16.426242 RX Vref 0 -> 0, step: 1
6354 22:50:16.426318
6355 22:50:16.426386 RX Delay -410 -> 252, step: 16
6356 22:50:16.432584 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6357 22:50:16.436142 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6358 22:50:16.439573 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6359 22:50:16.442668 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6360 22:50:16.449567 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6361 22:50:16.452755 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6362 22:50:16.455885 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6363 22:50:16.462667 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6364 22:50:16.466206 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6365 22:50:16.469077 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6366 22:50:16.472601 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6367 22:50:16.479211 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6368 22:50:16.482554 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6369 22:50:16.485428 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6370 22:50:16.488981 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6371 22:50:16.495413 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6372 22:50:16.495491 ==
6373 22:50:16.498802 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 22:50:16.502272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 22:50:16.502342 ==
6376 22:50:16.502406 DQS Delay:
6377 22:50:16.505192 DQS0 = 43, DQS1 = 59
6378 22:50:16.505262 DQM Delay:
6379 22:50:16.508748 DQM0 = 11, DQM1 = 11
6380 22:50:16.508822 DQ Delay:
6381 22:50:16.511678 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6382 22:50:16.515228 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6383 22:50:16.518785 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6384 22:50:16.521645 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6385 22:50:16.521718
6386 22:50:16.521779
6387 22:50:16.521837 ==
6388 22:50:16.525122 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 22:50:16.528426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 22:50:16.528503 ==
6391 22:50:16.531620
6392 22:50:16.531694
6393 22:50:16.531759 TX Vref Scan disable
6394 22:50:16.535025 == TX Byte 0 ==
6395 22:50:16.538406 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6396 22:50:16.541756 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6397 22:50:16.544719 == TX Byte 1 ==
6398 22:50:16.548264 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6399 22:50:16.551198 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6400 22:50:16.551270 ==
6401 22:50:16.554618 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 22:50:16.561244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 22:50:16.561317 ==
6404 22:50:16.561416
6405 22:50:16.561481
6406 22:50:16.561537 TX Vref Scan disable
6407 22:50:16.564570 == TX Byte 0 ==
6408 22:50:16.567753 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6409 22:50:16.571035 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6410 22:50:16.574634 == TX Byte 1 ==
6411 22:50:16.577617 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6412 22:50:16.581371 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6413 22:50:16.581446
6414 22:50:16.584388 [DATLAT]
6415 22:50:16.584461 Freq=400, CH0 RK0
6416 22:50:16.584521
6417 22:50:16.587935 DATLAT Default: 0xf
6418 22:50:16.588017 0, 0xFFFF, sum = 0
6419 22:50:16.591501 1, 0xFFFF, sum = 0
6420 22:50:16.591584 2, 0xFFFF, sum = 0
6421 22:50:16.594289 3, 0xFFFF, sum = 0
6422 22:50:16.594371 4, 0xFFFF, sum = 0
6423 22:50:16.597737 5, 0xFFFF, sum = 0
6424 22:50:16.600650 6, 0xFFFF, sum = 0
6425 22:50:16.600732 7, 0xFFFF, sum = 0
6426 22:50:16.604609 8, 0xFFFF, sum = 0
6427 22:50:16.604691 9, 0xFFFF, sum = 0
6428 22:50:16.607345 10, 0xFFFF, sum = 0
6429 22:50:16.607427 11, 0xFFFF, sum = 0
6430 22:50:16.610798 12, 0xFFFF, sum = 0
6431 22:50:16.610880 13, 0x0, sum = 1
6432 22:50:16.614135 14, 0x0, sum = 2
6433 22:50:16.614218 15, 0x0, sum = 3
6434 22:50:16.617626 16, 0x0, sum = 4
6435 22:50:16.617709 best_step = 14
6436 22:50:16.617774
6437 22:50:16.617835 ==
6438 22:50:16.620738 Dram Type= 6, Freq= 0, CH_0, rank 0
6439 22:50:16.624026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 22:50:16.624108 ==
6441 22:50:16.627526 RX Vref Scan: 1
6442 22:50:16.627607
6443 22:50:16.630362 RX Vref 0 -> 0, step: 1
6444 22:50:16.630444
6445 22:50:16.634207 RX Delay -359 -> 252, step: 8
6446 22:50:16.634289
6447 22:50:16.637472 Set Vref, RX VrefLevel [Byte0]: 59
6448 22:50:16.640220 [Byte1]: 49
6449 22:50:16.640301
6450 22:50:16.643762 Final RX Vref Byte 0 = 59 to rank0
6451 22:50:16.647076 Final RX Vref Byte 1 = 49 to rank0
6452 22:50:16.650388 Final RX Vref Byte 0 = 59 to rank1
6453 22:50:16.653620 Final RX Vref Byte 1 = 49 to rank1==
6454 22:50:16.657026 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 22:50:16.660334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 22:50:16.660416 ==
6457 22:50:16.663690 DQS Delay:
6458 22:50:16.663770 DQS0 = 48, DQS1 = 60
6459 22:50:16.667145 DQM Delay:
6460 22:50:16.667226 DQM0 = 12, DQM1 = 12
6461 22:50:16.667290 DQ Delay:
6462 22:50:16.670584 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6463 22:50:16.673555 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6464 22:50:16.676878 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6465 22:50:16.680182 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6466 22:50:16.680263
6467 22:50:16.680327
6468 22:50:16.690045 [DQSOSCAuto] RK0, (LSB)MR18= 0xbd7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6469 22:50:16.693264 CH0 RK0: MR19=C0C, MR18=BD7F
6470 22:50:16.696808 CH0_RK0: MR19=0xC0C, MR18=0xBD7F, DQSOSC=386, MR23=63, INC=396, DEC=264
6471 22:50:16.699788 ==
6472 22:50:16.703207 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 22:50:16.706544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 22:50:16.706613 ==
6475 22:50:16.709528 [Gating] SW mode calibration
6476 22:50:16.716677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6477 22:50:16.719710 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6478 22:50:16.726401 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6479 22:50:16.729947 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6480 22:50:16.733202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 22:50:16.739536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6482 22:50:16.742508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 22:50:16.745837 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 22:50:16.752697 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 22:50:16.756034 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 22:50:16.759798 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 22:50:16.762618 Total UI for P1: 0, mck2ui 16
6488 22:50:16.765942 best dqsien dly found for B0: ( 0, 14, 24)
6489 22:50:16.768892 Total UI for P1: 0, mck2ui 16
6490 22:50:16.772369 best dqsien dly found for B1: ( 0, 14, 24)
6491 22:50:16.775768 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6492 22:50:16.782129 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6493 22:50:16.782211
6494 22:50:16.785512 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6495 22:50:16.788989 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6496 22:50:16.792456 [Gating] SW calibration Done
6497 22:50:16.792538 ==
6498 22:50:16.795307 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 22:50:16.798431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 22:50:16.798513 ==
6501 22:50:16.802567 RX Vref Scan: 0
6502 22:50:16.802649
6503 22:50:16.802713 RX Vref 0 -> 0, step: 1
6504 22:50:16.802773
6505 22:50:16.805593 RX Delay -410 -> 252, step: 16
6506 22:50:16.812092 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6507 22:50:16.815502 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6508 22:50:16.819129 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6509 22:50:16.821676 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6510 22:50:16.828623 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6511 22:50:16.831541 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6512 22:50:16.835078 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6513 22:50:16.838653 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6514 22:50:16.845001 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6515 22:50:16.848441 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6516 22:50:16.851892 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6517 22:50:16.854822 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6518 22:50:16.861311 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6519 22:50:16.864873 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6520 22:50:16.868092 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6521 22:50:16.871841 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6522 22:50:16.874779 ==
6523 22:50:16.874853 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 22:50:16.881745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 22:50:16.881841 ==
6526 22:50:16.881906 DQS Delay:
6527 22:50:16.884547 DQS0 = 43, DQS1 = 59
6528 22:50:16.884618 DQM Delay:
6529 22:50:16.888013 DQM0 = 10, DQM1 = 16
6530 22:50:16.888093 DQ Delay:
6531 22:50:16.891314 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6532 22:50:16.894199 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6533 22:50:16.897682 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6534 22:50:16.901224 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6535 22:50:16.901312
6536 22:50:16.901391
6537 22:50:16.901450 ==
6538 22:50:16.904214 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 22:50:16.907732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 22:50:16.907806 ==
6541 22:50:16.907875
6542 22:50:16.907932
6543 22:50:16.911328 TX Vref Scan disable
6544 22:50:16.911393 == TX Byte 0 ==
6545 22:50:16.917553 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6546 22:50:16.920974 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6547 22:50:16.921125 == TX Byte 1 ==
6548 22:50:16.927852 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6549 22:50:16.931187 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6550 22:50:16.931265 ==
6551 22:50:16.934080 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 22:50:16.937860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 22:50:16.937968 ==
6554 22:50:16.938105
6555 22:50:16.938234
6556 22:50:16.940693 TX Vref Scan disable
6557 22:50:16.940772 == TX Byte 0 ==
6558 22:50:16.947555 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6559 22:50:16.950512 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6560 22:50:16.950628 == TX Byte 1 ==
6561 22:50:16.957527 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6562 22:50:16.960702 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6563 22:50:16.960778
6564 22:50:16.960876 [DATLAT]
6565 22:50:16.964178 Freq=400, CH0 RK1
6566 22:50:16.964256
6567 22:50:16.964343 DATLAT Default: 0xe
6568 22:50:16.967299 0, 0xFFFF, sum = 0
6569 22:50:16.967377 1, 0xFFFF, sum = 0
6570 22:50:16.970692 2, 0xFFFF, sum = 0
6571 22:50:16.970764 3, 0xFFFF, sum = 0
6572 22:50:16.973655 4, 0xFFFF, sum = 0
6573 22:50:16.973752 5, 0xFFFF, sum = 0
6574 22:50:16.977062 6, 0xFFFF, sum = 0
6575 22:50:16.977138 7, 0xFFFF, sum = 0
6576 22:50:16.980803 8, 0xFFFF, sum = 0
6577 22:50:16.983719 9, 0xFFFF, sum = 0
6578 22:50:16.983793 10, 0xFFFF, sum = 0
6579 22:50:16.986872 11, 0xFFFF, sum = 0
6580 22:50:16.986951 12, 0xFFFF, sum = 0
6581 22:50:16.990669 13, 0x0, sum = 1
6582 22:50:16.990749 14, 0x0, sum = 2
6583 22:50:16.993300 15, 0x0, sum = 3
6584 22:50:16.993417 16, 0x0, sum = 4
6585 22:50:16.993495 best_step = 14
6586 22:50:16.997138
6587 22:50:16.997207 ==
6588 22:50:17.000128 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 22:50:17.003595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 22:50:17.003678 ==
6591 22:50:17.003742 RX Vref Scan: 0
6592 22:50:17.003802
6593 22:50:17.006645 RX Vref 0 -> 0, step: 1
6594 22:50:17.006727
6595 22:50:17.010054 RX Delay -359 -> 252, step: 8
6596 22:50:17.017371 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6597 22:50:17.020882 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6598 22:50:17.023588 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6599 22:50:17.030737 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6600 22:50:17.033657 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6601 22:50:17.037150 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6602 22:50:17.040468 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6603 22:50:17.047102 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6604 22:50:17.050504 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6605 22:50:17.053222 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6606 22:50:17.056666 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6607 22:50:17.063696 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6608 22:50:17.066583 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6609 22:50:17.070054 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6610 22:50:17.073312 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6611 22:50:17.080087 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6612 22:50:17.080169 ==
6613 22:50:17.083036 Dram Type= 6, Freq= 0, CH_0, rank 1
6614 22:50:17.086510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 22:50:17.086591 ==
6616 22:50:17.086655 DQS Delay:
6617 22:50:17.089794 DQS0 = 44, DQS1 = 60
6618 22:50:17.089900 DQM Delay:
6619 22:50:17.093154 DQM0 = 9, DQM1 = 15
6620 22:50:17.093235 DQ Delay:
6621 22:50:17.096640 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6622 22:50:17.100010 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6623 22:50:17.103194 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6624 22:50:17.106071 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6625 22:50:17.106176
6626 22:50:17.106260
6627 22:50:17.116269 [DQSOSCAuto] RK1, (LSB)MR18= 0xb33f, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6628 22:50:17.116351 CH0 RK1: MR19=C0C, MR18=B33F
6629 22:50:17.123025 CH0_RK1: MR19=0xC0C, MR18=0xB33F, DQSOSC=387, MR23=63, INC=394, DEC=262
6630 22:50:17.125853 [RxdqsGatingPostProcess] freq 400
6631 22:50:17.132571 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6632 22:50:17.136076 best DQS0 dly(2T, 0.5T) = (0, 10)
6633 22:50:17.139231 best DQS1 dly(2T, 0.5T) = (0, 10)
6634 22:50:17.142831 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6635 22:50:17.145928 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6636 22:50:17.148809 best DQS0 dly(2T, 0.5T) = (0, 10)
6637 22:50:17.148890 best DQS1 dly(2T, 0.5T) = (0, 10)
6638 22:50:17.152178 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6639 22:50:17.155590 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6640 22:50:17.159251 Pre-setting of DQS Precalculation
6641 22:50:17.165371 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6642 22:50:17.165466 ==
6643 22:50:17.169028 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 22:50:17.172041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 22:50:17.172122 ==
6646 22:50:17.178867 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6647 22:50:17.185089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6648 22:50:17.188651 [CA 0] Center 36 (8~64) winsize 57
6649 22:50:17.191932 [CA 1] Center 36 (8~64) winsize 57
6650 22:50:17.195395 [CA 2] Center 36 (8~64) winsize 57
6651 22:50:17.198699 [CA 3] Center 36 (8~64) winsize 57
6652 22:50:17.198783 [CA 4] Center 36 (8~64) winsize 57
6653 22:50:17.201812 [CA 5] Center 36 (8~64) winsize 57
6654 22:50:17.201892
6655 22:50:17.208196 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6656 22:50:17.208278
6657 22:50:17.211654 [CATrainingPosCal] consider 1 rank data
6658 22:50:17.214711 u2DelayCellTimex100 = 270/100 ps
6659 22:50:17.218177 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 22:50:17.221730 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 22:50:17.225167 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 22:50:17.228126 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 22:50:17.231653 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 22:50:17.234785 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 22:50:17.234864
6666 22:50:17.238128 CA PerBit enable=1, Macro0, CA PI delay=36
6667 22:50:17.238214
6668 22:50:17.241109 [CBTSetCACLKResult] CA Dly = 36
6669 22:50:17.244536 CS Dly: 1 (0~32)
6670 22:50:17.244618 ==
6671 22:50:17.248131 Dram Type= 6, Freq= 0, CH_1, rank 1
6672 22:50:17.250987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 22:50:17.251068 ==
6674 22:50:17.257820 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6675 22:50:17.264770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6676 22:50:17.267858 [CA 0] Center 36 (8~64) winsize 57
6677 22:50:17.271204 [CA 1] Center 36 (8~64) winsize 57
6678 22:50:17.271285 [CA 2] Center 36 (8~64) winsize 57
6679 22:50:17.274100 [CA 3] Center 36 (8~64) winsize 57
6680 22:50:17.277686 [CA 4] Center 36 (8~64) winsize 57
6681 22:50:17.281104 [CA 5] Center 36 (8~64) winsize 57
6682 22:50:17.281184
6683 22:50:17.284810 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6684 22:50:17.287419
6685 22:50:17.290624 [CATrainingPosCal] consider 2 rank data
6686 22:50:17.290705 u2DelayCellTimex100 = 270/100 ps
6687 22:50:17.297011 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 22:50:17.300446 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 22:50:17.304118 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 22:50:17.307399 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 22:50:17.310244 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 22:50:17.313708 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 22:50:17.313790
6694 22:50:17.316965 CA PerBit enable=1, Macro0, CA PI delay=36
6695 22:50:17.317046
6696 22:50:17.320133 [CBTSetCACLKResult] CA Dly = 36
6697 22:50:17.323765 CS Dly: 1 (0~32)
6698 22:50:17.323864
6699 22:50:17.327399 ----->DramcWriteLeveling(PI) begin...
6700 22:50:17.327481 ==
6701 22:50:17.330361 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 22:50:17.333732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 22:50:17.333814 ==
6704 22:50:17.336773 Write leveling (Byte 0): 40 => 8
6705 22:50:17.340109 Write leveling (Byte 1): 40 => 8
6706 22:50:17.343318 DramcWriteLeveling(PI) end<-----
6707 22:50:17.343420
6708 22:50:17.343483 ==
6709 22:50:17.346547 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 22:50:17.350222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 22:50:17.350303 ==
6712 22:50:17.353368 [Gating] SW mode calibration
6713 22:50:17.359566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6714 22:50:17.366544 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6715 22:50:17.369909 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6716 22:50:17.376153 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6717 22:50:17.379710 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 22:50:17.382945 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6719 22:50:17.389481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 22:50:17.393025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 22:50:17.395896 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 22:50:17.402820 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 22:50:17.406100 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 22:50:17.409326 Total UI for P1: 0, mck2ui 16
6725 22:50:17.412503 best dqsien dly found for B0: ( 0, 14, 24)
6726 22:50:17.415975 Total UI for P1: 0, mck2ui 16
6727 22:50:17.419287 best dqsien dly found for B1: ( 0, 14, 24)
6728 22:50:17.422999 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6729 22:50:17.426026 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6730 22:50:17.426153
6731 22:50:17.429229 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6732 22:50:17.432465 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6733 22:50:17.435891 [Gating] SW calibration Done
6734 22:50:17.435992 ==
6735 22:50:17.439013 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 22:50:17.442497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 22:50:17.445832 ==
6738 22:50:17.445914 RX Vref Scan: 0
6739 22:50:17.445978
6740 22:50:17.449113 RX Vref 0 -> 0, step: 1
6741 22:50:17.449219
6742 22:50:17.451955 RX Delay -410 -> 252, step: 16
6743 22:50:17.455401 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6744 22:50:17.459346 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6745 22:50:17.462292 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6746 22:50:17.468821 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6747 22:50:17.472344 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6748 22:50:17.475128 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6749 22:50:17.478986 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6750 22:50:17.485301 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6751 22:50:17.488490 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6752 22:50:17.492191 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6753 22:50:17.494852 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6754 22:50:17.501439 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6755 22:50:17.504867 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6756 22:50:17.508020 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6757 22:50:17.514822 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6758 22:50:17.518266 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6759 22:50:17.518351 ==
6760 22:50:17.521317 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 22:50:17.524766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 22:50:17.524847 ==
6763 22:50:17.527956 DQS Delay:
6764 22:50:17.528037 DQS0 = 43, DQS1 = 51
6765 22:50:17.531134 DQM Delay:
6766 22:50:17.531222 DQM0 = 12, DQM1 = 14
6767 22:50:17.531290 DQ Delay:
6768 22:50:17.534891 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6769 22:50:17.537950 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6770 22:50:17.541232 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6771 22:50:17.544388 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6772 22:50:17.544499
6773 22:50:17.544595
6774 22:50:17.544687 ==
6775 22:50:17.547669 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 22:50:17.551108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 22:50:17.554692 ==
6778 22:50:17.554786
6779 22:50:17.554878
6780 22:50:17.554971 TX Vref Scan disable
6781 22:50:17.557486 == TX Byte 0 ==
6782 22:50:17.561010 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6783 22:50:17.564444 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6784 22:50:17.568117 == TX Byte 1 ==
6785 22:50:17.570704 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 22:50:17.573989 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 22:50:17.574071 ==
6788 22:50:17.577297 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 22:50:17.584321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 22:50:17.584402 ==
6791 22:50:17.584466
6792 22:50:17.584524
6793 22:50:17.584580 TX Vref Scan disable
6794 22:50:17.587701 == TX Byte 0 ==
6795 22:50:17.590827 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 22:50:17.594144 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 22:50:17.597702 == TX Byte 1 ==
6798 22:50:17.600805 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 22:50:17.603665 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 22:50:17.603749
6801 22:50:17.607202 [DATLAT]
6802 22:50:17.607283 Freq=400, CH1 RK0
6803 22:50:17.607346
6804 22:50:17.610383 DATLAT Default: 0xf
6805 22:50:17.610464 0, 0xFFFF, sum = 0
6806 22:50:17.613595 1, 0xFFFF, sum = 0
6807 22:50:17.613678 2, 0xFFFF, sum = 0
6808 22:50:17.616965 3, 0xFFFF, sum = 0
6809 22:50:17.617046 4, 0xFFFF, sum = 0
6810 22:50:17.620485 5, 0xFFFF, sum = 0
6811 22:50:17.620567 6, 0xFFFF, sum = 0
6812 22:50:17.623750 7, 0xFFFF, sum = 0
6813 22:50:17.627467 8, 0xFFFF, sum = 0
6814 22:50:17.627568 9, 0xFFFF, sum = 0
6815 22:50:17.630507 10, 0xFFFF, sum = 0
6816 22:50:17.630591 11, 0xFFFF, sum = 0
6817 22:50:17.633369 12, 0xFFFF, sum = 0
6818 22:50:17.633465 13, 0x0, sum = 1
6819 22:50:17.636789 14, 0x0, sum = 2
6820 22:50:17.636871 15, 0x0, sum = 3
6821 22:50:17.640094 16, 0x0, sum = 4
6822 22:50:17.640176 best_step = 14
6823 22:50:17.640239
6824 22:50:17.640322 ==
6825 22:50:17.643420 Dram Type= 6, Freq= 0, CH_1, rank 0
6826 22:50:17.646580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 22:50:17.646662 ==
6828 22:50:17.650257 RX Vref Scan: 1
6829 22:50:17.650338
6830 22:50:17.653123 RX Vref 0 -> 0, step: 1
6831 22:50:17.653204
6832 22:50:17.656420 RX Delay -343 -> 252, step: 8
6833 22:50:17.656501
6834 22:50:17.660141 Set Vref, RX VrefLevel [Byte0]: 46
6835 22:50:17.663178 [Byte1]: 57
6836 22:50:17.663259
6837 22:50:17.666560 Final RX Vref Byte 0 = 46 to rank0
6838 22:50:17.669617 Final RX Vref Byte 1 = 57 to rank0
6839 22:50:17.672907 Final RX Vref Byte 0 = 46 to rank1
6840 22:50:17.676287 Final RX Vref Byte 1 = 57 to rank1==
6841 22:50:17.679160 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 22:50:17.682644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 22:50:17.682725 ==
6844 22:50:17.686283 DQS Delay:
6845 22:50:17.686363 DQS0 = 44, DQS1 = 56
6846 22:50:17.689098 DQM Delay:
6847 22:50:17.689178 DQM0 = 9, DQM1 = 14
6848 22:50:17.692664 DQ Delay:
6849 22:50:17.692745 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6850 22:50:17.695911 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6851 22:50:17.699125 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4
6852 22:50:17.702602 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6853 22:50:17.702683
6854 22:50:17.702746
6855 22:50:17.712399 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6856 22:50:17.715637 CH1 RK0: MR19=C0C, MR18=9C72
6857 22:50:17.719100 CH1_RK0: MR19=0xC0C, MR18=0x9C72, DQSOSC=390, MR23=63, INC=388, DEC=258
6858 22:50:17.722005 ==
6859 22:50:17.725796 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 22:50:17.729047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 22:50:17.729129 ==
6862 22:50:17.731972 [Gating] SW mode calibration
6863 22:50:17.738703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6864 22:50:17.741883 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6865 22:50:17.748312 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6866 22:50:17.751798 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6867 22:50:17.755030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 22:50:17.762077 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6869 22:50:17.765005 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 22:50:17.768452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 22:50:17.775349 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 22:50:17.778199 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 22:50:17.781579 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 22:50:17.785049 Total UI for P1: 0, mck2ui 16
6875 22:50:17.788263 best dqsien dly found for B0: ( 0, 14, 24)
6876 22:50:17.791693 Total UI for P1: 0, mck2ui 16
6877 22:50:17.794529 best dqsien dly found for B1: ( 0, 14, 24)
6878 22:50:17.798007 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6879 22:50:17.804702 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6880 22:50:17.804783
6881 22:50:17.807974 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6882 22:50:17.811282 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6883 22:50:17.814367 [Gating] SW calibration Done
6884 22:50:17.814447 ==
6885 22:50:17.817798 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 22:50:17.821227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 22:50:17.821308 ==
6888 22:50:17.824466 RX Vref Scan: 0
6889 22:50:17.824546
6890 22:50:17.824609 RX Vref 0 -> 0, step: 1
6891 22:50:17.824667
6892 22:50:17.827782 RX Delay -410 -> 252, step: 16
6893 22:50:17.834252 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6894 22:50:17.837810 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6895 22:50:17.840852 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6896 22:50:17.844151 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6897 22:50:17.850481 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6898 22:50:17.854021 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6899 22:50:17.857070 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6900 22:50:17.860465 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6901 22:50:17.867089 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6902 22:50:17.870260 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6903 22:50:17.873792 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6904 22:50:17.876746 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6905 22:50:17.883399 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6906 22:50:17.886489 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6907 22:50:17.890072 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6908 22:50:17.896555 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6909 22:50:17.896654 ==
6910 22:50:17.900185 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 22:50:17.903076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 22:50:17.903158 ==
6913 22:50:17.903222 DQS Delay:
6914 22:50:17.906637 DQS0 = 51, DQS1 = 59
6915 22:50:17.906718 DQM Delay:
6916 22:50:17.909669 DQM0 = 19, DQM1 = 22
6917 22:50:17.909750 DQ Delay:
6918 22:50:17.913260 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6919 22:50:17.916384 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6920 22:50:17.919499 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6921 22:50:17.923033 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6922 22:50:17.923114
6923 22:50:17.923178
6924 22:50:17.923236 ==
6925 22:50:17.926428 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 22:50:17.929314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 22:50:17.932941 ==
6928 22:50:17.933047
6929 22:50:17.933141
6930 22:50:17.933230 TX Vref Scan disable
6931 22:50:17.936666 == TX Byte 0 ==
6932 22:50:17.939524 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6933 22:50:17.943097 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6934 22:50:17.945974 == TX Byte 1 ==
6935 22:50:17.949130 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6936 22:50:17.952660 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6937 22:50:17.952768 ==
6938 22:50:17.956291 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 22:50:17.962545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 22:50:17.962643 ==
6941 22:50:17.962723
6942 22:50:17.962845
6943 22:50:17.962964 TX Vref Scan disable
6944 22:50:17.965423 == TX Byte 0 ==
6945 22:50:17.968914 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6946 22:50:17.972249 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6947 22:50:17.975674 == TX Byte 1 ==
6948 22:50:17.978626 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6949 22:50:17.982326 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6950 22:50:17.982438
6951 22:50:17.984986 [DATLAT]
6952 22:50:17.985067 Freq=400, CH1 RK1
6953 22:50:17.985131
6954 22:50:17.988456 DATLAT Default: 0xe
6955 22:50:17.988536 0, 0xFFFF, sum = 0
6956 22:50:17.991700 1, 0xFFFF, sum = 0
6957 22:50:17.991799 2, 0xFFFF, sum = 0
6958 22:50:17.994932 3, 0xFFFF, sum = 0
6959 22:50:17.995014 4, 0xFFFF, sum = 0
6960 22:50:17.998583 5, 0xFFFF, sum = 0
6961 22:50:17.998665 6, 0xFFFF, sum = 0
6962 22:50:18.001843 7, 0xFFFF, sum = 0
6963 22:50:18.001937 8, 0xFFFF, sum = 0
6964 22:50:18.005443 9, 0xFFFF, sum = 0
6965 22:50:18.008075 10, 0xFFFF, sum = 0
6966 22:50:18.008176 11, 0xFFFF, sum = 0
6967 22:50:18.011617 12, 0xFFFF, sum = 0
6968 22:50:18.011698 13, 0x0, sum = 1
6969 22:50:18.014867 14, 0x0, sum = 2
6970 22:50:18.014975 15, 0x0, sum = 3
6971 22:50:18.018002 16, 0x0, sum = 4
6972 22:50:18.018113 best_step = 14
6973 22:50:18.018176
6974 22:50:18.018235 ==
6975 22:50:18.021486 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 22:50:18.024903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 22:50:18.024986 ==
6978 22:50:18.027929 RX Vref Scan: 0
6979 22:50:18.028009
6980 22:50:18.031596 RX Vref 0 -> 0, step: 1
6981 22:50:18.031682
6982 22:50:18.031787 RX Delay -359 -> 252, step: 8
6983 22:50:18.040158 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6984 22:50:18.043586 iDelay=217, Bit 1, Center -40 (-279 ~ 200) 480
6985 22:50:18.047071 iDelay=217, Bit 2, Center -48 (-287 ~ 192) 480
6986 22:50:18.053675 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6987 22:50:18.056553 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6988 22:50:18.060094 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
6989 22:50:18.063572 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6990 22:50:18.069995 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6991 22:50:18.073402 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6992 22:50:18.076267 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6993 22:50:18.079503 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6994 22:50:18.086589 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6995 22:50:18.089780 iDelay=217, Bit 12, Center -36 (-287 ~ 216) 504
6996 22:50:18.092869 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6997 22:50:18.096290 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6998 22:50:18.103047 iDelay=217, Bit 15, Center -36 (-287 ~ 216) 504
6999 22:50:18.103168 ==
7000 22:50:18.106325 Dram Type= 6, Freq= 0, CH_1, rank 1
7001 22:50:18.109365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7002 22:50:18.109447 ==
7003 22:50:18.109511 DQS Delay:
7004 22:50:18.112898 DQS0 = 48, DQS1 = 56
7005 22:50:18.112979 DQM Delay:
7006 22:50:18.115984 DQM0 = 13, DQM1 = 10
7007 22:50:18.116065 DQ Delay:
7008 22:50:18.119662 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7009 22:50:18.122735 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7010 22:50:18.126235 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7011 22:50:18.129111 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7012 22:50:18.129188
7013 22:50:18.129288
7014 22:50:18.138825 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7015 22:50:18.138905 CH1 RK1: MR19=C0C, MR18=6A5B
7016 22:50:18.145521 CH1_RK1: MR19=0xC0C, MR18=0x6A5B, DQSOSC=396, MR23=63, INC=376, DEC=251
7017 22:50:18.149078 [RxdqsGatingPostProcess] freq 400
7018 22:50:18.155833 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7019 22:50:18.158743 best DQS0 dly(2T, 0.5T) = (0, 10)
7020 22:50:18.162235 best DQS1 dly(2T, 0.5T) = (0, 10)
7021 22:50:18.165756 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7022 22:50:18.168877 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7023 22:50:18.172344 best DQS0 dly(2T, 0.5T) = (0, 10)
7024 22:50:18.172487 best DQS1 dly(2T, 0.5T) = (0, 10)
7025 22:50:18.175678 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7026 22:50:18.179163 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7027 22:50:18.182098 Pre-setting of DQS Precalculation
7028 22:50:18.189031 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7029 22:50:18.195130 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7030 22:50:18.202467 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7031 22:50:18.202542
7032 22:50:18.202642
7033 22:50:18.205312 [Calibration Summary] 800 Mbps
7034 22:50:18.205407 CH 0, Rank 0
7035 22:50:18.208721 SW Impedance : PASS
7036 22:50:18.211694 DUTY Scan : NO K
7037 22:50:18.211796 ZQ Calibration : PASS
7038 22:50:18.215261 Jitter Meter : NO K
7039 22:50:18.218796 CBT Training : PASS
7040 22:50:18.218911 Write leveling : PASS
7041 22:50:18.221892 RX DQS gating : PASS
7042 22:50:18.225349 RX DQ/DQS(RDDQC) : PASS
7043 22:50:18.225462 TX DQ/DQS : PASS
7044 22:50:18.228847 RX DATLAT : PASS
7045 22:50:18.231890 RX DQ/DQS(Engine): PASS
7046 22:50:18.232009 TX OE : NO K
7047 22:50:18.235223 All Pass.
7048 22:50:18.235304
7049 22:50:18.235366 CH 0, Rank 1
7050 22:50:18.238788 SW Impedance : PASS
7051 22:50:18.238860 DUTY Scan : NO K
7052 22:50:18.241766 ZQ Calibration : PASS
7053 22:50:18.244838 Jitter Meter : NO K
7054 22:50:18.244919 CBT Training : PASS
7055 22:50:18.248452 Write leveling : NO K
7056 22:50:18.252005 RX DQS gating : PASS
7057 22:50:18.252086 RX DQ/DQS(RDDQC) : PASS
7058 22:50:18.255031 TX DQ/DQS : PASS
7059 22:50:18.255142 RX DATLAT : PASS
7060 22:50:18.258290 RX DQ/DQS(Engine): PASS
7061 22:50:18.261748 TX OE : NO K
7062 22:50:18.261830 All Pass.
7063 22:50:18.261894
7064 22:50:18.261952 CH 1, Rank 0
7065 22:50:18.265011 SW Impedance : PASS
7066 22:50:18.268184 DUTY Scan : NO K
7067 22:50:18.268264 ZQ Calibration : PASS
7068 22:50:18.272114 Jitter Meter : NO K
7069 22:50:18.274596 CBT Training : PASS
7070 22:50:18.274690 Write leveling : PASS
7071 22:50:18.278080 RX DQS gating : PASS
7072 22:50:18.281288 RX DQ/DQS(RDDQC) : PASS
7073 22:50:18.281392 TX DQ/DQS : PASS
7074 22:50:18.284922 RX DATLAT : PASS
7075 22:50:18.288088 RX DQ/DQS(Engine): PASS
7076 22:50:18.288169 TX OE : NO K
7077 22:50:18.291556 All Pass.
7078 22:50:18.291637
7079 22:50:18.291701 CH 1, Rank 1
7080 22:50:18.295189 SW Impedance : PASS
7081 22:50:18.295285 DUTY Scan : NO K
7082 22:50:18.298003 ZQ Calibration : PASS
7083 22:50:18.301476 Jitter Meter : NO K
7084 22:50:18.301557 CBT Training : PASS
7085 22:50:18.304760 Write leveling : NO K
7086 22:50:18.307934 RX DQS gating : PASS
7087 22:50:18.308014 RX DQ/DQS(RDDQC) : PASS
7088 22:50:18.310929 TX DQ/DQS : PASS
7089 22:50:18.314433 RX DATLAT : PASS
7090 22:50:18.314513 RX DQ/DQS(Engine): PASS
7091 22:50:18.317618 TX OE : NO K
7092 22:50:18.317699 All Pass.
7093 22:50:18.317763
7094 22:50:18.321060 DramC Write-DBI off
7095 22:50:18.324258 PER_BANK_REFRESH: Hybrid Mode
7096 22:50:18.324340 TX_TRACKING: ON
7097 22:50:18.334065 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7098 22:50:18.337922 [FAST_K] Save calibration result to emmc
7099 22:50:18.340913 dramc_set_vcore_voltage set vcore to 725000
7100 22:50:18.344306 Read voltage for 1600, 0
7101 22:50:18.344389 Vio18 = 0
7102 22:50:18.344452 Vcore = 725000
7103 22:50:18.347838 Vdram = 0
7104 22:50:18.347908 Vddq = 0
7105 22:50:18.347968 Vmddr = 0
7106 22:50:18.354209 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7107 22:50:18.357452 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7108 22:50:18.360851 MEM_TYPE=3, freq_sel=13
7109 22:50:18.363790 sv_algorithm_assistance_LP4_3733
7110 22:50:18.367248 ============ PULL DRAM RESETB DOWN ============
7111 22:50:18.370933 ========== PULL DRAM RESETB DOWN end =========
7112 22:50:18.377319 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7113 22:50:18.380690 ===================================
7114 22:50:18.380761 LPDDR4 DRAM CONFIGURATION
7115 22:50:18.384135 ===================================
7116 22:50:18.387648 EX_ROW_EN[0] = 0x0
7117 22:50:18.390317 EX_ROW_EN[1] = 0x0
7118 22:50:18.390385 LP4Y_EN = 0x0
7119 22:50:18.393861 WORK_FSP = 0x1
7120 22:50:18.393926 WL = 0x5
7121 22:50:18.396831 RL = 0x5
7122 22:50:18.396905 BL = 0x2
7123 22:50:18.400131 RPST = 0x0
7124 22:50:18.400230 RD_PRE = 0x0
7125 22:50:18.403797 WR_PRE = 0x1
7126 22:50:18.403870 WR_PST = 0x1
7127 22:50:18.407156 DBI_WR = 0x0
7128 22:50:18.407226 DBI_RD = 0x0
7129 22:50:18.410374 OTF = 0x1
7130 22:50:18.413652 ===================================
7131 22:50:18.416744 ===================================
7132 22:50:18.416819 ANA top config
7133 22:50:18.420184 ===================================
7134 22:50:18.423654 DLL_ASYNC_EN = 0
7135 22:50:18.426528 ALL_SLAVE_EN = 0
7136 22:50:18.430164 NEW_RANK_MODE = 1
7137 22:50:18.433459 DLL_IDLE_MODE = 1
7138 22:50:18.433554 LP45_APHY_COMB_EN = 1
7139 22:50:18.436627 TX_ODT_DIS = 0
7140 22:50:18.440143 NEW_8X_MODE = 1
7141 22:50:18.443607 ===================================
7142 22:50:18.446641 ===================================
7143 22:50:18.449649 data_rate = 3200
7144 22:50:18.453000 CKR = 1
7145 22:50:18.453099 DQ_P2S_RATIO = 8
7146 22:50:18.456468 ===================================
7147 22:50:18.459527 CA_P2S_RATIO = 8
7148 22:50:18.463446 DQ_CA_OPEN = 0
7149 22:50:18.466612 DQ_SEMI_OPEN = 0
7150 22:50:18.469475 CA_SEMI_OPEN = 0
7151 22:50:18.473144 CA_FULL_RATE = 0
7152 22:50:18.473242 DQ_CKDIV4_EN = 0
7153 22:50:18.475836 CA_CKDIV4_EN = 0
7154 22:50:18.479542 CA_PREDIV_EN = 0
7155 22:50:18.482844 PH8_DLY = 12
7156 22:50:18.485798 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7157 22:50:18.489088 DQ_AAMCK_DIV = 4
7158 22:50:18.492469 CA_AAMCK_DIV = 4
7159 22:50:18.492567 CA_ADMCK_DIV = 4
7160 22:50:18.495895 DQ_TRACK_CA_EN = 0
7161 22:50:18.499049 CA_PICK = 1600
7162 22:50:18.502441 CA_MCKIO = 1600
7163 22:50:18.505545 MCKIO_SEMI = 0
7164 22:50:18.509219 PLL_FREQ = 3068
7165 22:50:18.512471 DQ_UI_PI_RATIO = 32
7166 22:50:18.512571 CA_UI_PI_RATIO = 0
7167 22:50:18.516108 ===================================
7168 22:50:18.518883 ===================================
7169 22:50:18.522458 memory_type:LPDDR4
7170 22:50:18.525515 GP_NUM : 10
7171 22:50:18.525588 SRAM_EN : 1
7172 22:50:18.528807 MD32_EN : 0
7173 22:50:18.532202 ===================================
7174 22:50:18.535276 [ANA_INIT] >>>>>>>>>>>>>>
7175 22:50:18.539097 <<<<<< [CONFIGURE PHASE]: ANA_TX
7176 22:50:18.541675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7177 22:50:18.545478 ===================================
7178 22:50:18.548766 data_rate = 3200,PCW = 0X7600
7179 22:50:18.548841 ===================================
7180 22:50:18.555196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7181 22:50:18.558493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7182 22:50:18.564909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7183 22:50:18.568659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7184 22:50:18.571465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7185 22:50:18.574999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7186 22:50:18.578067 [ANA_INIT] flow start
7187 22:50:18.581669 [ANA_INIT] PLL >>>>>>>>
7188 22:50:18.581739 [ANA_INIT] PLL <<<<<<<<
7189 22:50:18.584733 [ANA_INIT] MIDPI >>>>>>>>
7190 22:50:18.588596 [ANA_INIT] MIDPI <<<<<<<<
7191 22:50:18.591403 [ANA_INIT] DLL >>>>>>>>
7192 22:50:18.591500 [ANA_INIT] DLL <<<<<<<<
7193 22:50:18.594458 [ANA_INIT] flow end
7194 22:50:18.598194 ============ LP4 DIFF to SE enter ============
7195 22:50:18.601321 ============ LP4 DIFF to SE exit ============
7196 22:50:18.604487 [ANA_INIT] <<<<<<<<<<<<<
7197 22:50:18.607809 [Flow] Enable top DCM control >>>>>
7198 22:50:18.610775 [Flow] Enable top DCM control <<<<<
7199 22:50:18.614723 Enable DLL master slave shuffle
7200 22:50:18.621013 ==============================================================
7201 22:50:18.621113 Gating Mode config
7202 22:50:18.627446 ==============================================================
7203 22:50:18.627548 Config description:
7204 22:50:18.637307 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7205 22:50:18.643699 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7206 22:50:18.650813 SELPH_MODE 0: By rank 1: By Phase
7207 22:50:18.653623 ==============================================================
7208 22:50:18.657040 GAT_TRACK_EN = 1
7209 22:50:18.660249 RX_GATING_MODE = 2
7210 22:50:18.663760 RX_GATING_TRACK_MODE = 2
7211 22:50:18.666788 SELPH_MODE = 1
7212 22:50:18.670171 PICG_EARLY_EN = 1
7213 22:50:18.673318 VALID_LAT_VALUE = 1
7214 22:50:18.680372 ==============================================================
7215 22:50:18.683470 Enter into Gating configuration >>>>
7216 22:50:18.686723 Exit from Gating configuration <<<<
7217 22:50:18.690234 Enter into DVFS_PRE_config >>>>>
7218 22:50:18.700254 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7219 22:50:18.703193 Exit from DVFS_PRE_config <<<<<
7220 22:50:18.706850 Enter into PICG configuration >>>>
7221 22:50:18.710355 Exit from PICG configuration <<<<
7222 22:50:18.713046 [RX_INPUT] configuration >>>>>
7223 22:50:18.713162 [RX_INPUT] configuration <<<<<
7224 22:50:18.719795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7225 22:50:18.726355 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7226 22:50:18.733295 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7227 22:50:18.736032 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7228 22:50:18.742961 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7229 22:50:18.749423 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7230 22:50:18.752948 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7231 22:50:18.759103 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7232 22:50:18.762381 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7233 22:50:18.765997 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7234 22:50:18.769175 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7235 22:50:18.775775 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7236 22:50:18.779076 ===================================
7237 22:50:18.779149 LPDDR4 DRAM CONFIGURATION
7238 22:50:18.782174 ===================================
7239 22:50:18.785731 EX_ROW_EN[0] = 0x0
7240 22:50:18.788894 EX_ROW_EN[1] = 0x0
7241 22:50:18.788993 LP4Y_EN = 0x0
7242 22:50:18.792458 WORK_FSP = 0x1
7243 22:50:18.792531 WL = 0x5
7244 22:50:18.795815 RL = 0x5
7245 22:50:18.795885 BL = 0x2
7246 22:50:18.799239 RPST = 0x0
7247 22:50:18.799312 RD_PRE = 0x0
7248 22:50:18.802383 WR_PRE = 0x1
7249 22:50:18.802478 WR_PST = 0x1
7250 22:50:18.805438 DBI_WR = 0x0
7251 22:50:18.805531 DBI_RD = 0x0
7252 22:50:18.808893 OTF = 0x1
7253 22:50:18.812283 ===================================
7254 22:50:18.815566 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7255 22:50:18.818935 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7256 22:50:18.825218 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7257 22:50:18.828760 ===================================
7258 22:50:18.828862 LPDDR4 DRAM CONFIGURATION
7259 22:50:18.831969 ===================================
7260 22:50:18.835544 EX_ROW_EN[0] = 0x10
7261 22:50:18.838977 EX_ROW_EN[1] = 0x0
7262 22:50:18.839077 LP4Y_EN = 0x0
7263 22:50:18.842016 WORK_FSP = 0x1
7264 22:50:18.842106 WL = 0x5
7265 22:50:18.845191 RL = 0x5
7266 22:50:18.845294 BL = 0x2
7267 22:50:18.848744 RPST = 0x0
7268 22:50:18.848844 RD_PRE = 0x0
7269 22:50:18.851959 WR_PRE = 0x1
7270 22:50:18.852055 WR_PST = 0x1
7271 22:50:18.854980 DBI_WR = 0x0
7272 22:50:18.855050 DBI_RD = 0x0
7273 22:50:18.858492 OTF = 0x1
7274 22:50:18.861652 ===================================
7275 22:50:18.868159 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7276 22:50:18.868260 ==
7277 22:50:18.871843 Dram Type= 6, Freq= 0, CH_0, rank 0
7278 22:50:18.875012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7279 22:50:18.875092 ==
7280 22:50:18.878217 [Duty_Offset_Calibration]
7281 22:50:18.878314 B0:1 B1:-1 CA:0
7282 22:50:18.878412
7283 22:50:18.881193 [DutyScan_Calibration_Flow] k_type=0
7284 22:50:18.892617
7285 22:50:18.892712 ==CLK 0==
7286 22:50:18.896222 Final CLK duty delay cell = 0
7287 22:50:18.898934 [0] MAX Duty = 5124%(X100), DQS PI = 22
7288 22:50:18.902437 [0] MIN Duty = 4907%(X100), DQS PI = 4
7289 22:50:18.905267 [0] AVG Duty = 5015%(X100)
7290 22:50:18.905394
7291 22:50:18.908805 CH0 CLK Duty spec in!! Max-Min= 217%
7292 22:50:18.912322 [DutyScan_Calibration_Flow] ====Done====
7293 22:50:18.912424
7294 22:50:18.915387 [DutyScan_Calibration_Flow] k_type=1
7295 22:50:18.931398
7296 22:50:18.931489 ==DQS 0 ==
7297 22:50:18.934941 Final DQS duty delay cell = -4
7298 22:50:18.938036 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7299 22:50:18.941503 [-4] MIN Duty = 4844%(X100), DQS PI = 10
7300 22:50:18.944505 [-4] AVG Duty = 4906%(X100)
7301 22:50:18.944586
7302 22:50:18.944648 ==DQS 1 ==
7303 22:50:18.947983 Final DQS duty delay cell = 0
7304 22:50:18.951435 [0] MAX Duty = 5156%(X100), DQS PI = 2
7305 22:50:18.954460 [0] MIN Duty = 5000%(X100), DQS PI = 20
7306 22:50:18.958125 [0] AVG Duty = 5078%(X100)
7307 22:50:18.958205
7308 22:50:18.961106 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7309 22:50:18.961186
7310 22:50:18.964641 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7311 22:50:18.967826 [DutyScan_Calibration_Flow] ====Done====
7312 22:50:18.967906
7313 22:50:18.970808 [DutyScan_Calibration_Flow] k_type=3
7314 22:50:18.989041
7315 22:50:18.989122 ==DQM 0 ==
7316 22:50:18.992376 Final DQM duty delay cell = 0
7317 22:50:18.995546 [0] MAX Duty = 5093%(X100), DQS PI = 18
7318 22:50:18.998855 [0] MIN Duty = 4876%(X100), DQS PI = 10
7319 22:50:19.002395 [0] AVG Duty = 4984%(X100)
7320 22:50:19.002489
7321 22:50:19.002554 ==DQM 1 ==
7322 22:50:19.005653 Final DQM duty delay cell = 0
7323 22:50:19.009087 [0] MAX Duty = 5031%(X100), DQS PI = 52
7324 22:50:19.012042 [0] MIN Duty = 4782%(X100), DQS PI = 20
7325 22:50:19.015751 [0] AVG Duty = 4906%(X100)
7326 22:50:19.015831
7327 22:50:19.019271 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7328 22:50:19.019352
7329 22:50:19.022731 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7330 22:50:19.025410 [DutyScan_Calibration_Flow] ====Done====
7331 22:50:19.025490
7332 22:50:19.028879 [DutyScan_Calibration_Flow] k_type=2
7333 22:50:19.045488
7334 22:50:19.045682 ==DQ 0 ==
7335 22:50:19.048996 Final DQ duty delay cell = -4
7336 22:50:19.051948 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7337 22:50:19.055495 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7338 22:50:19.058766 [-4] AVG Duty = 4953%(X100)
7339 22:50:19.058847
7340 22:50:19.058911 ==DQ 1 ==
7341 22:50:19.061859 Final DQ duty delay cell = 0
7342 22:50:19.065393 [0] MAX Duty = 5125%(X100), DQS PI = 2
7343 22:50:19.068550 [0] MIN Duty = 5000%(X100), DQS PI = 34
7344 22:50:19.071594 [0] AVG Duty = 5062%(X100)
7345 22:50:19.071676
7346 22:50:19.074810 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7347 22:50:19.074892
7348 22:50:19.078707 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7349 22:50:19.081762 [DutyScan_Calibration_Flow] ====Done====
7350 22:50:19.081874 ==
7351 22:50:19.084835 Dram Type= 6, Freq= 0, CH_1, rank 0
7352 22:50:19.088204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7353 22:50:19.088286 ==
7354 22:50:19.091817 [Duty_Offset_Calibration]
7355 22:50:19.091898 B0:-1 B1:1 CA:2
7356 22:50:19.091962
7357 22:50:19.095322 [DutyScan_Calibration_Flow] k_type=0
7358 22:50:19.106020
7359 22:50:19.106116 ==CLK 0==
7360 22:50:19.109562 Final CLK duty delay cell = 0
7361 22:50:19.112448 [0] MAX Duty = 5187%(X100), DQS PI = 22
7362 22:50:19.115941 [0] MIN Duty = 4969%(X100), DQS PI = 0
7363 22:50:19.119605 [0] AVG Duty = 5078%(X100)
7364 22:50:19.119686
7365 22:50:19.122741 CH1 CLK Duty spec in!! Max-Min= 218%
7366 22:50:19.125892 [DutyScan_Calibration_Flow] ====Done====
7367 22:50:19.125973
7368 22:50:19.129286 [DutyScan_Calibration_Flow] k_type=1
7369 22:50:19.146095
7370 22:50:19.146251 ==DQS 0 ==
7371 22:50:19.149047 Final DQS duty delay cell = 0
7372 22:50:19.152564 [0] MAX Duty = 5124%(X100), DQS PI = 18
7373 22:50:19.155831 [0] MIN Duty = 4907%(X100), DQS PI = 8
7374 22:50:19.159147 [0] AVG Duty = 5015%(X100)
7375 22:50:19.159246
7376 22:50:19.159340 ==DQS 1 ==
7377 22:50:19.162634 Final DQS duty delay cell = 0
7378 22:50:19.165537 [0] MAX Duty = 5093%(X100), DQS PI = 26
7379 22:50:19.169079 [0] MIN Duty = 4969%(X100), DQS PI = 54
7380 22:50:19.172503 [0] AVG Duty = 5031%(X100)
7381 22:50:19.172599
7382 22:50:19.175602 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7383 22:50:19.175691
7384 22:50:19.179196 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7385 22:50:19.182184 [DutyScan_Calibration_Flow] ====Done====
7386 22:50:19.182266
7387 22:50:19.185538 [DutyScan_Calibration_Flow] k_type=3
7388 22:50:19.203053
7389 22:50:19.203134 ==DQM 0 ==
7390 22:50:19.205878 Final DQM duty delay cell = 0
7391 22:50:19.209255 [0] MAX Duty = 5218%(X100), DQS PI = 18
7392 22:50:19.212691 [0] MIN Duty = 5000%(X100), DQS PI = 10
7393 22:50:19.215840 [0] AVG Duty = 5109%(X100)
7394 22:50:19.215936
7395 22:50:19.216015 ==DQM 1 ==
7396 22:50:19.219272 Final DQM duty delay cell = 0
7397 22:50:19.222371 [0] MAX Duty = 5156%(X100), DQS PI = 2
7398 22:50:19.226011 [0] MIN Duty = 4938%(X100), DQS PI = 36
7399 22:50:19.228749 [0] AVG Duty = 5047%(X100)
7400 22:50:19.228831
7401 22:50:19.232193 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7402 22:50:19.232274
7403 22:50:19.235620 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7404 22:50:19.239029 [DutyScan_Calibration_Flow] ====Done====
7405 22:50:19.239111
7406 22:50:19.242115 [DutyScan_Calibration_Flow] k_type=2
7407 22:50:19.259728
7408 22:50:19.259815 ==DQ 0 ==
7409 22:50:19.262583 Final DQ duty delay cell = 0
7410 22:50:19.266064 [0] MAX Duty = 5156%(X100), DQS PI = 28
7411 22:50:19.269437 [0] MIN Duty = 4906%(X100), DQS PI = 8
7412 22:50:19.269520 [0] AVG Duty = 5031%(X100)
7413 22:50:19.272956
7414 22:50:19.273037 ==DQ 1 ==
7415 22:50:19.275751 Final DQ duty delay cell = 0
7416 22:50:19.279402 [0] MAX Duty = 5156%(X100), DQS PI = 8
7417 22:50:19.282780 [0] MIN Duty = 4938%(X100), DQS PI = 60
7418 22:50:19.282862 [0] AVG Duty = 5047%(X100)
7419 22:50:19.282926
7420 22:50:19.288989 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7421 22:50:19.289071
7422 22:50:19.292585 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7423 22:50:19.295457 [DutyScan_Calibration_Flow] ====Done====
7424 22:50:19.299339 nWR fixed to 30
7425 22:50:19.299421 [ModeRegInit_LP4] CH0 RK0
7426 22:50:19.302758 [ModeRegInit_LP4] CH0 RK1
7427 22:50:19.305809 [ModeRegInit_LP4] CH1 RK0
7428 22:50:19.308962 [ModeRegInit_LP4] CH1 RK1
7429 22:50:19.309043 match AC timing 5
7430 22:50:19.315911 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7431 22:50:19.319189 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7432 22:50:19.322039 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7433 22:50:19.329052 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7434 22:50:19.331920 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7435 22:50:19.332002 [MiockJmeterHQA]
7436 22:50:19.332065
7437 22:50:19.335534 [DramcMiockJmeter] u1RxGatingPI = 0
7438 22:50:19.338742 0 : 4366, 4137
7439 22:50:19.338825 4 : 4253, 4027
7440 22:50:19.341964 8 : 4253, 4027
7441 22:50:19.342054 12 : 4253, 4027
7442 22:50:19.342131 16 : 4253, 4026
7443 22:50:19.345395 20 : 4255, 4029
7444 22:50:19.345493 24 : 4252, 4027
7445 22:50:19.348945 28 : 4363, 4138
7446 22:50:19.349027 32 : 4253, 4027
7447 22:50:19.351898 36 : 4252, 4027
7448 22:50:19.351995 40 : 4250, 4027
7449 22:50:19.355259 44 : 4253, 4026
7450 22:50:19.355356 48 : 4250, 4027
7451 22:50:19.355421 52 : 4361, 4137
7452 22:50:19.358872 56 : 4363, 4140
7453 22:50:19.358971 60 : 4253, 4027
7454 22:50:19.362234 64 : 4250, 4027
7455 22:50:19.362362 68 : 4250, 4027
7456 22:50:19.365110 72 : 4250, 4027
7457 22:50:19.365192 76 : 4250, 4026
7458 22:50:19.368257 80 : 4360, 4138
7459 22:50:19.368340 84 : 4250, 4027
7460 22:50:19.368405 88 : 4250, 4026
7461 22:50:19.371603 92 : 4250, 344
7462 22:50:19.371686 96 : 4362, 0
7463 22:50:19.375086 100 : 4250, 0
7464 22:50:19.375169 104 : 4250, 0
7465 22:50:19.375235 108 : 4250, 0
7466 22:50:19.378620 112 : 4250, 0
7467 22:50:19.378703 116 : 4361, 0
7468 22:50:19.381566 120 : 4360, 0
7469 22:50:19.381648 124 : 4250, 0
7470 22:50:19.381713 128 : 4250, 0
7471 22:50:19.385111 132 : 4361, 0
7472 22:50:19.385193 136 : 4250, 0
7473 22:50:19.388451 140 : 4250, 0
7474 22:50:19.388533 144 : 4250, 0
7475 22:50:19.388598 148 : 4250, 0
7476 22:50:19.391346 152 : 4250, 0
7477 22:50:19.391429 156 : 4250, 0
7478 22:50:19.391494 160 : 4249, 0
7479 22:50:19.394811 164 : 4250, 0
7480 22:50:19.394893 168 : 4361, 0
7481 22:50:19.398302 172 : 4360, 0
7482 22:50:19.398384 176 : 4365, 0
7483 22:50:19.398449 180 : 4250, 0
7484 22:50:19.401668 184 : 4250, 0
7485 22:50:19.401765 188 : 4363, 0
7486 22:50:19.405162 192 : 4250, 0
7487 22:50:19.405244 196 : 4250, 0
7488 22:50:19.405309 200 : 4250, 0
7489 22:50:19.407830 204 : 4250, 0
7490 22:50:19.407925 208 : 4250, 0
7491 22:50:19.411878 212 : 4249, 0
7492 22:50:19.411956 216 : 4252, 0
7493 22:50:19.412023 220 : 4361, 0
7494 22:50:19.414525 224 : 4360, 252
7495 22:50:19.414609 228 : 4250, 3714
7496 22:50:19.418255 232 : 4249, 4027
7497 22:50:19.418337 236 : 4250, 4026
7498 22:50:19.421030 240 : 4250, 4027
7499 22:50:19.421113 244 : 4361, 4137
7500 22:50:19.424704 248 : 4249, 4027
7501 22:50:19.424798 252 : 4250, 4027
7502 22:50:19.427750 256 : 4360, 4138
7503 22:50:19.427832 260 : 4250, 4027
7504 22:50:19.431148 264 : 4250, 4027
7505 22:50:19.431231 268 : 4361, 4137
7506 22:50:19.431297 272 : 4250, 4027
7507 22:50:19.434299 276 : 4253, 4027
7508 22:50:19.434397 280 : 4250, 4027
7509 22:50:19.437661 284 : 4252, 4029
7510 22:50:19.437743 288 : 4250, 4027
7511 22:50:19.441132 292 : 4250, 4027
7512 22:50:19.441215 296 : 4361, 4137
7513 22:50:19.444031 300 : 4252, 4027
7514 22:50:19.444114 304 : 4250, 4027
7515 22:50:19.447721 308 : 4360, 4138
7516 22:50:19.447804 312 : 4250, 4027
7517 22:50:19.451100 316 : 4252, 4027
7518 22:50:19.451183 320 : 4361, 4137
7519 22:50:19.453988 324 : 4250, 4027
7520 22:50:19.454071 328 : 4250, 4027
7521 22:50:19.457735 332 : 4250, 4027
7522 22:50:19.457852 336 : 4250, 3774
7523 22:50:19.457948 340 : 4250, 1889
7524 22:50:19.460897
7525 22:50:19.460994 MIOCK jitter meter ch=0
7526 22:50:19.461088
7527 22:50:19.464334 1T = (340-92) = 248 dly cells
7528 22:50:19.470755 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7529 22:50:19.470852 ==
7530 22:50:19.474125 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 22:50:19.477368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 22:50:19.477510 ==
7533 22:50:19.483569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7534 22:50:19.487193 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7535 22:50:19.490844 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7536 22:50:19.497063 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7537 22:50:19.506353 [CA 0] Center 43 (13~74) winsize 62
7538 22:50:19.510007 [CA 1] Center 42 (12~73) winsize 62
7539 22:50:19.513361 [CA 2] Center 38 (9~68) winsize 60
7540 22:50:19.516540 [CA 3] Center 38 (8~68) winsize 61
7541 22:50:19.519949 [CA 4] Center 36 (7~66) winsize 60
7542 22:50:19.522842 [CA 5] Center 35 (6~65) winsize 60
7543 22:50:19.522965
7544 22:50:19.526376 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7545 22:50:19.526472
7546 22:50:19.529637 [CATrainingPosCal] consider 1 rank data
7547 22:50:19.532770 u2DelayCellTimex100 = 262/100 ps
7548 22:50:19.539581 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7549 22:50:19.543063 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7550 22:50:19.546278 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7551 22:50:19.549691 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7552 22:50:19.552805 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7553 22:50:19.556425 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7554 22:50:19.556509
7555 22:50:19.559738 CA PerBit enable=1, Macro0, CA PI delay=35
7556 22:50:19.559821
7557 22:50:19.563170 [CBTSetCACLKResult] CA Dly = 35
7558 22:50:19.565833 CS Dly: 12 (0~43)
7559 22:50:19.569231 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7560 22:50:19.572847 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7561 22:50:19.572931 ==
7562 22:50:19.575938 Dram Type= 6, Freq= 0, CH_0, rank 1
7563 22:50:19.582762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 22:50:19.582846 ==
7565 22:50:19.586178 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7566 22:50:19.592469 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7567 22:50:19.595775 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7568 22:50:19.601987 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7569 22:50:19.610093 [CA 0] Center 43 (13~74) winsize 62
7570 22:50:19.613567 [CA 1] Center 44 (14~74) winsize 61
7571 22:50:19.616395 [CA 2] Center 38 (9~68) winsize 60
7572 22:50:19.619729 [CA 3] Center 38 (9~68) winsize 60
7573 22:50:19.622981 [CA 4] Center 36 (7~66) winsize 60
7574 22:50:19.626534 [CA 5] Center 36 (6~66) winsize 61
7575 22:50:19.626618
7576 22:50:19.629929 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7577 22:50:19.630013
7578 22:50:19.633174 [CATrainingPosCal] consider 2 rank data
7579 22:50:19.636231 u2DelayCellTimex100 = 262/100 ps
7580 22:50:19.643008 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7581 22:50:19.646144 CA1 delay=43 (14~73),Diff = 8 PI (29 cell)
7582 22:50:19.649680 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7583 22:50:19.652839 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7584 22:50:19.656120 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7585 22:50:19.659613 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7586 22:50:19.659695
7587 22:50:19.662936 CA PerBit enable=1, Macro0, CA PI delay=35
7588 22:50:19.663018
7589 22:50:19.666244 [CBTSetCACLKResult] CA Dly = 35
7590 22:50:19.669630 CS Dly: 12 (0~44)
7591 22:50:19.672476 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7592 22:50:19.676071 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7593 22:50:19.676153
7594 22:50:19.679392 ----->DramcWriteLeveling(PI) begin...
7595 22:50:19.679475 ==
7596 22:50:19.682382 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 22:50:19.688962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 22:50:19.689044 ==
7599 22:50:19.692258 Write leveling (Byte 0): 37 => 37
7600 22:50:19.695593 Write leveling (Byte 1): 28 => 28
7601 22:50:19.698999 DramcWriteLeveling(PI) end<-----
7602 22:50:19.699095
7603 22:50:19.699190 ==
7604 22:50:19.702049 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 22:50:19.705818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 22:50:19.705900 ==
7607 22:50:19.708907 [Gating] SW mode calibration
7608 22:50:19.715457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7609 22:50:19.721874 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7610 22:50:19.725371 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 22:50:19.728804 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 22:50:19.735248 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 22:50:19.738321 1 4 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7614 22:50:19.741722 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7615 22:50:19.748436 1 4 20 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
7616 22:50:19.751459 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
7617 22:50:19.754703 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 22:50:19.761771 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 22:50:19.764769 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7620 22:50:19.768064 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 22:50:19.774984 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7622 22:50:19.778027 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7623 22:50:19.781205 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7624 22:50:19.787737 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
7625 22:50:19.791255 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 22:50:19.794906 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 22:50:19.800821 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 22:50:19.804466 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 22:50:19.808164 1 6 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
7630 22:50:19.814145 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7631 22:50:19.817424 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7632 22:50:19.820652 1 6 24 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
7633 22:50:19.827318 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 22:50:19.830711 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 22:50:19.834063 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 22:50:19.841165 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7637 22:50:19.843878 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7638 22:50:19.847381 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 22:50:19.853776 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7640 22:50:19.857338 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 22:50:19.860728 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 22:50:19.866902 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 22:50:19.870417 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 22:50:19.874013 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 22:50:19.880139 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 22:50:19.883818 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 22:50:19.886806 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 22:50:19.890395 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 22:50:19.896697 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 22:50:19.900163 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 22:50:19.903648 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 22:50:19.910165 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7653 22:50:19.913550 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7654 22:50:19.916999 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7655 22:50:19.923471 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7656 22:50:19.926824 Total UI for P1: 0, mck2ui 16
7657 22:50:19.929954 best dqsien dly found for B0: ( 1, 9, 12)
7658 22:50:19.933589 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 22:50:19.936529 Total UI for P1: 0, mck2ui 16
7660 22:50:19.940135 best dqsien dly found for B1: ( 1, 9, 20)
7661 22:50:19.943273 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7662 22:50:19.946703 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7663 22:50:19.946815
7664 22:50:19.950161 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7665 22:50:19.956294 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7666 22:50:19.956396 [Gating] SW calibration Done
7667 22:50:19.959924 ==
7668 22:50:19.960022 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 22:50:19.966163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 22:50:19.966272 ==
7671 22:50:19.966369 RX Vref Scan: 0
7672 22:50:19.966459
7673 22:50:19.969255 RX Vref 0 -> 0, step: 1
7674 22:50:19.969357
7675 22:50:19.972858 RX Delay 0 -> 252, step: 8
7676 22:50:19.975792 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7677 22:50:19.979560 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7678 22:50:19.982870 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7679 22:50:19.989283 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7680 22:50:19.992199 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7681 22:50:19.995507 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7682 22:50:19.998990 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7683 22:50:20.002327 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7684 22:50:20.008720 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7685 22:50:20.012125 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7686 22:50:20.015686 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7687 22:50:20.018620 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7688 22:50:20.025563 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7689 22:50:20.029283 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7690 22:50:20.032494 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7691 22:50:20.035638 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7692 22:50:20.035734 ==
7693 22:50:20.039036 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 22:50:20.041999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 22:50:20.045186 ==
7696 22:50:20.045296 DQS Delay:
7697 22:50:20.045433 DQS0 = 0, DQS1 = 0
7698 22:50:20.048608 DQM Delay:
7699 22:50:20.048681 DQM0 = 136, DQM1 = 126
7700 22:50:20.052316 DQ Delay:
7701 22:50:20.055300 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7702 22:50:20.058787 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7703 22:50:20.062156 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7704 22:50:20.065191 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7705 22:50:20.065324
7706 22:50:20.065421
7707 22:50:20.065502 ==
7708 22:50:20.068555 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 22:50:20.071532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 22:50:20.074869 ==
7711 22:50:20.074973
7712 22:50:20.075061
7713 22:50:20.075146 TX Vref Scan disable
7714 22:50:20.078656 == TX Byte 0 ==
7715 22:50:20.081557 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7716 22:50:20.084819 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7717 22:50:20.088385 == TX Byte 1 ==
7718 22:50:20.091377 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7719 22:50:20.094924 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7720 22:50:20.098077 ==
7721 22:50:20.101258 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 22:50:20.104958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 22:50:20.105043 ==
7724 22:50:20.117447
7725 22:50:20.120871 TX Vref early break, caculate TX vref
7726 22:50:20.124350 TX Vref=16, minBit 4, minWin=22, winSum=371
7727 22:50:20.127238 TX Vref=18, minBit 4, minWin=22, winSum=378
7728 22:50:20.131216 TX Vref=20, minBit 1, minWin=23, winSum=390
7729 22:50:20.134000 TX Vref=22, minBit 3, minWin=24, winSum=399
7730 22:50:20.137093 TX Vref=24, minBit 3, minWin=24, winSum=407
7731 22:50:20.144035 TX Vref=26, minBit 0, minWin=25, winSum=419
7732 22:50:20.147597 TX Vref=28, minBit 4, minWin=25, winSum=419
7733 22:50:20.150919 TX Vref=30, minBit 0, minWin=24, winSum=411
7734 22:50:20.154092 TX Vref=32, minBit 0, minWin=24, winSum=401
7735 22:50:20.157354 TX Vref=34, minBit 4, minWin=23, winSum=392
7736 22:50:20.163858 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
7737 22:50:20.163957
7738 22:50:20.166853 Final TX Range 0 Vref 26
7739 22:50:20.166926
7740 22:50:20.166987 ==
7741 22:50:20.170182 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 22:50:20.173749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 22:50:20.173819 ==
7744 22:50:20.173878
7745 22:50:20.173935
7746 22:50:20.176631 TX Vref Scan disable
7747 22:50:20.183535 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7748 22:50:20.183609 == TX Byte 0 ==
7749 22:50:20.187239 u2DelayCellOfst[0]=14 cells (4 PI)
7750 22:50:20.190198 u2DelayCellOfst[1]=18 cells (5 PI)
7751 22:50:20.193297 u2DelayCellOfst[2]=14 cells (4 PI)
7752 22:50:20.196813 u2DelayCellOfst[3]=14 cells (4 PI)
7753 22:50:20.199568 u2DelayCellOfst[4]=11 cells (3 PI)
7754 22:50:20.203237 u2DelayCellOfst[5]=0 cells (0 PI)
7755 22:50:20.206733 u2DelayCellOfst[6]=22 cells (6 PI)
7756 22:50:20.209752 u2DelayCellOfst[7]=22 cells (6 PI)
7757 22:50:20.213015 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7758 22:50:20.216790 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7759 22:50:20.219482 == TX Byte 1 ==
7760 22:50:20.222718 u2DelayCellOfst[8]=0 cells (0 PI)
7761 22:50:20.226439 u2DelayCellOfst[9]=0 cells (0 PI)
7762 22:50:20.229573 u2DelayCellOfst[10]=7 cells (2 PI)
7763 22:50:20.229670 u2DelayCellOfst[11]=0 cells (0 PI)
7764 22:50:20.232743 u2DelayCellOfst[12]=11 cells (3 PI)
7765 22:50:20.236572 u2DelayCellOfst[13]=11 cells (3 PI)
7766 22:50:20.239697 u2DelayCellOfst[14]=14 cells (4 PI)
7767 22:50:20.242984 u2DelayCellOfst[15]=11 cells (3 PI)
7768 22:50:20.249614 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7769 22:50:20.252719 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7770 22:50:20.252815 DramC Write-DBI on
7771 22:50:20.256260 ==
7772 22:50:20.259388 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 22:50:20.262608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 22:50:20.262676 ==
7775 22:50:20.262735
7776 22:50:20.262790
7777 22:50:20.266126 TX Vref Scan disable
7778 22:50:20.266195 == TX Byte 0 ==
7779 22:50:20.272842 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7780 22:50:20.272919 == TX Byte 1 ==
7781 22:50:20.275851 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7782 22:50:20.279435 DramC Write-DBI off
7783 22:50:20.279514
7784 22:50:20.279574 [DATLAT]
7785 22:50:20.282604 Freq=1600, CH0 RK0
7786 22:50:20.282675
7787 22:50:20.282741 DATLAT Default: 0xf
7788 22:50:20.286168 0, 0xFFFF, sum = 0
7789 22:50:20.286240 1, 0xFFFF, sum = 0
7790 22:50:20.289086 2, 0xFFFF, sum = 0
7791 22:50:20.289152 3, 0xFFFF, sum = 0
7792 22:50:20.292382 4, 0xFFFF, sum = 0
7793 22:50:20.292458 5, 0xFFFF, sum = 0
7794 22:50:20.295654 6, 0xFFFF, sum = 0
7795 22:50:20.299082 7, 0xFFFF, sum = 0
7796 22:50:20.299184 8, 0xFFFF, sum = 0
7797 22:50:20.302001 9, 0xFFFF, sum = 0
7798 22:50:20.302070 10, 0xFFFF, sum = 0
7799 22:50:20.305861 11, 0xFFFF, sum = 0
7800 22:50:20.305929 12, 0xFFFF, sum = 0
7801 22:50:20.308498 13, 0xFFFF, sum = 0
7802 22:50:20.308568 14, 0x0, sum = 1
7803 22:50:20.312281 15, 0x0, sum = 2
7804 22:50:20.312351 16, 0x0, sum = 3
7805 22:50:20.315678 17, 0x0, sum = 4
7806 22:50:20.315752 best_step = 15
7807 22:50:20.315810
7808 22:50:20.315867 ==
7809 22:50:20.319028 Dram Type= 6, Freq= 0, CH_0, rank 0
7810 22:50:20.321829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7811 22:50:20.325290 ==
7812 22:50:20.325389 RX Vref Scan: 1
7813 22:50:20.325449
7814 22:50:20.328756 Set Vref Range= 24 -> 127
7815 22:50:20.328852
7816 22:50:20.332106 RX Vref 24 -> 127, step: 1
7817 22:50:20.332203
7818 22:50:20.332291 RX Delay 19 -> 252, step: 4
7819 22:50:20.332374
7820 22:50:20.335317 Set Vref, RX VrefLevel [Byte0]: 24
7821 22:50:20.338404 [Byte1]: 24
7822 22:50:20.342294
7823 22:50:20.342399 Set Vref, RX VrefLevel [Byte0]: 25
7824 22:50:20.345546 [Byte1]: 25
7825 22:50:20.349901
7826 22:50:20.353293 Set Vref, RX VrefLevel [Byte0]: 26
7827 22:50:20.356248 [Byte1]: 26
7828 22:50:20.356342
7829 22:50:20.359698 Set Vref, RX VrefLevel [Byte0]: 27
7830 22:50:20.362884 [Byte1]: 27
7831 22:50:20.362976
7832 22:50:20.366445 Set Vref, RX VrefLevel [Byte0]: 28
7833 22:50:20.369314 [Byte1]: 28
7834 22:50:20.369409
7835 22:50:20.372966 Set Vref, RX VrefLevel [Byte0]: 29
7836 22:50:20.375797 [Byte1]: 29
7837 22:50:20.380198
7838 22:50:20.380270 Set Vref, RX VrefLevel [Byte0]: 30
7839 22:50:20.383253 [Byte1]: 30
7840 22:50:20.387497
7841 22:50:20.387595 Set Vref, RX VrefLevel [Byte0]: 31
7842 22:50:20.390945 [Byte1]: 31
7843 22:50:20.394953
7844 22:50:20.395052 Set Vref, RX VrefLevel [Byte0]: 32
7845 22:50:20.398685 [Byte1]: 32
7846 22:50:20.402553
7847 22:50:20.402648 Set Vref, RX VrefLevel [Byte0]: 33
7848 22:50:20.405803 [Byte1]: 33
7849 22:50:20.410627
7850 22:50:20.410696 Set Vref, RX VrefLevel [Byte0]: 34
7851 22:50:20.413372 [Byte1]: 34
7852 22:50:20.417806
7853 22:50:20.417880 Set Vref, RX VrefLevel [Byte0]: 35
7854 22:50:20.421184 [Byte1]: 35
7855 22:50:20.425833
7856 22:50:20.425907 Set Vref, RX VrefLevel [Byte0]: 36
7857 22:50:20.428683 [Byte1]: 36
7858 22:50:20.432801
7859 22:50:20.432903 Set Vref, RX VrefLevel [Byte0]: 37
7860 22:50:20.436254 [Byte1]: 37
7861 22:50:20.441033
7862 22:50:20.441128 Set Vref, RX VrefLevel [Byte0]: 38
7863 22:50:20.443694 [Byte1]: 38
7864 22:50:20.448021
7865 22:50:20.448138 Set Vref, RX VrefLevel [Byte0]: 39
7866 22:50:20.451404 [Byte1]: 39
7867 22:50:20.455949
7868 22:50:20.456048 Set Vref, RX VrefLevel [Byte0]: 40
7869 22:50:20.458822 [Byte1]: 40
7870 22:50:20.463389
7871 22:50:20.463493 Set Vref, RX VrefLevel [Byte0]: 41
7872 22:50:20.466796 [Byte1]: 41
7873 22:50:20.471183
7874 22:50:20.471283 Set Vref, RX VrefLevel [Byte0]: 42
7875 22:50:20.473983 [Byte1]: 42
7876 22:50:20.479039
7877 22:50:20.479144 Set Vref, RX VrefLevel [Byte0]: 43
7878 22:50:20.481909 [Byte1]: 43
7879 22:50:20.485959
7880 22:50:20.486056 Set Vref, RX VrefLevel [Byte0]: 44
7881 22:50:20.489207 [Byte1]: 44
7882 22:50:20.493909
7883 22:50:20.493996 Set Vref, RX VrefLevel [Byte0]: 45
7884 22:50:20.497140 [Byte1]: 45
7885 22:50:20.501465
7886 22:50:20.501539 Set Vref, RX VrefLevel [Byte0]: 46
7887 22:50:20.504802 [Byte1]: 46
7888 22:50:20.508902
7889 22:50:20.509017 Set Vref, RX VrefLevel [Byte0]: 47
7890 22:50:20.511999 [Byte1]: 47
7891 22:50:20.516532
7892 22:50:20.516634 Set Vref, RX VrefLevel [Byte0]: 48
7893 22:50:20.519495 [Byte1]: 48
7894 22:50:20.524086
7895 22:50:20.524184 Set Vref, RX VrefLevel [Byte0]: 49
7896 22:50:20.527093 [Byte1]: 49
7897 22:50:20.531591
7898 22:50:20.531691 Set Vref, RX VrefLevel [Byte0]: 50
7899 22:50:20.535344 [Byte1]: 50
7900 22:50:20.539165
7901 22:50:20.539239 Set Vref, RX VrefLevel [Byte0]: 51
7902 22:50:20.542811 [Byte1]: 51
7903 22:50:20.546933
7904 22:50:20.547035 Set Vref, RX VrefLevel [Byte0]: 52
7905 22:50:20.550140 [Byte1]: 52
7906 22:50:20.554372
7907 22:50:20.554469 Set Vref, RX VrefLevel [Byte0]: 53
7908 22:50:20.557546 [Byte1]: 53
7909 22:50:20.562046
7910 22:50:20.562122 Set Vref, RX VrefLevel [Byte0]: 54
7911 22:50:20.565441 [Byte1]: 54
7912 22:50:20.569518
7913 22:50:20.569618 Set Vref, RX VrefLevel [Byte0]: 55
7914 22:50:20.572583 [Byte1]: 55
7915 22:50:20.577218
7916 22:50:20.577336 Set Vref, RX VrefLevel [Byte0]: 56
7917 22:50:20.580164 [Byte1]: 56
7918 22:50:20.584241
7919 22:50:20.584337 Set Vref, RX VrefLevel [Byte0]: 57
7920 22:50:20.587664 [Byte1]: 57
7921 22:50:20.592083
7922 22:50:20.592177 Set Vref, RX VrefLevel [Byte0]: 58
7923 22:50:20.595607 [Byte1]: 58
7924 22:50:20.599698
7925 22:50:20.599793 Set Vref, RX VrefLevel [Byte0]: 59
7926 22:50:20.602777 [Byte1]: 59
7927 22:50:20.607065
7928 22:50:20.607134 Set Vref, RX VrefLevel [Byte0]: 60
7929 22:50:20.610751 [Byte1]: 60
7930 22:50:20.614903
7931 22:50:20.615000 Set Vref, RX VrefLevel [Byte0]: 61
7932 22:50:20.618448 [Byte1]: 61
7933 22:50:20.622288
7934 22:50:20.622383 Set Vref, RX VrefLevel [Byte0]: 62
7935 22:50:20.625373 [Byte1]: 62
7936 22:50:20.629998
7937 22:50:20.630073 Set Vref, RX VrefLevel [Byte0]: 63
7938 22:50:20.633210 [Byte1]: 63
7939 22:50:20.637315
7940 22:50:20.637425 Set Vref, RX VrefLevel [Byte0]: 64
7941 22:50:20.641436 [Byte1]: 64
7942 22:50:20.645313
7943 22:50:20.645434 Set Vref, RX VrefLevel [Byte0]: 65
7944 22:50:20.648550 [Byte1]: 65
7945 22:50:20.652559
7946 22:50:20.652635 Set Vref, RX VrefLevel [Byte0]: 66
7947 22:50:20.655916 [Byte1]: 66
7948 22:50:20.660605
7949 22:50:20.660679 Set Vref, RX VrefLevel [Byte0]: 67
7950 22:50:20.663329 [Byte1]: 67
7951 22:50:20.667827
7952 22:50:20.667943 Set Vref, RX VrefLevel [Byte0]: 68
7953 22:50:20.670923 [Byte1]: 68
7954 22:50:20.675670
7955 22:50:20.675744 Set Vref, RX VrefLevel [Byte0]: 69
7956 22:50:20.678555 [Byte1]: 69
7957 22:50:20.683485
7958 22:50:20.683581 Set Vref, RX VrefLevel [Byte0]: 70
7959 22:50:20.686246 [Byte1]: 70
7960 22:50:20.690396
7961 22:50:20.690492 Set Vref, RX VrefLevel [Byte0]: 71
7962 22:50:20.693896 [Byte1]: 71
7963 22:50:20.698278
7964 22:50:20.698354 Set Vref, RX VrefLevel [Byte0]: 72
7965 22:50:20.701179 [Byte1]: 72
7966 22:50:20.705885
7967 22:50:20.705983 Set Vref, RX VrefLevel [Byte0]: 73
7968 22:50:20.708738 [Byte1]: 73
7969 22:50:20.713346
7970 22:50:20.713461 Set Vref, RX VrefLevel [Byte0]: 74
7971 22:50:20.716580 [Byte1]: 74
7972 22:50:20.720863
7973 22:50:20.720963 Set Vref, RX VrefLevel [Byte0]: 75
7974 22:50:20.724058 [Byte1]: 75
7975 22:50:20.728696
7976 22:50:20.728794 Set Vref, RX VrefLevel [Byte0]: 76
7977 22:50:20.731723 [Byte1]: 76
7978 22:50:20.736336
7979 22:50:20.736435 Set Vref, RX VrefLevel [Byte0]: 77
7980 22:50:20.739449 [Byte1]: 77
7981 22:50:20.743336
7982 22:50:20.743432 Set Vref, RX VrefLevel [Byte0]: 78
7983 22:50:20.746901 [Byte1]: 78
7984 22:50:20.750955
7985 22:50:20.751055 Set Vref, RX VrefLevel [Byte0]: 79
7986 22:50:20.754185 [Byte1]: 79
7987 22:50:20.758487
7988 22:50:20.758569 Final RX Vref Byte 0 = 64 to rank0
7989 22:50:20.762190 Final RX Vref Byte 1 = 59 to rank0
7990 22:50:20.765425 Final RX Vref Byte 0 = 64 to rank1
7991 22:50:20.768744 Final RX Vref Byte 1 = 59 to rank1==
7992 22:50:20.771726 Dram Type= 6, Freq= 0, CH_0, rank 0
7993 22:50:20.778514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7994 22:50:20.778598 ==
7995 22:50:20.778662 DQS Delay:
7996 22:50:20.781805 DQS0 = 0, DQS1 = 0
7997 22:50:20.781886 DQM Delay:
7998 22:50:20.781950 DQM0 = 133, DQM1 = 122
7999 22:50:20.784935 DQ Delay:
8000 22:50:20.788582 DQ0 =130, DQ1 =134, DQ2 =132, DQ3 =132
8001 22:50:20.791506 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8002 22:50:20.795188 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
8003 22:50:20.798385 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8004 22:50:20.798466
8005 22:50:20.798530
8006 22:50:20.798588
8007 22:50:20.801518 [DramC_TX_OE_Calibration] TA2
8008 22:50:20.804588 Original DQ_B0 (3 6) =30, OEN = 27
8009 22:50:20.808056 Original DQ_B1 (3 6) =30, OEN = 27
8010 22:50:20.811032 24, 0x0, End_B0=24 End_B1=24
8011 22:50:20.814753 25, 0x0, End_B0=25 End_B1=25
8012 22:50:20.814833 26, 0x0, End_B0=26 End_B1=26
8013 22:50:20.818341 27, 0x0, End_B0=27 End_B1=27
8014 22:50:20.821534 28, 0x0, End_B0=28 End_B1=28
8015 22:50:20.824505 29, 0x0, End_B0=29 End_B1=29
8016 22:50:20.824588 30, 0x0, End_B0=30 End_B1=30
8017 22:50:20.827817 31, 0x4141, End_B0=30 End_B1=30
8018 22:50:20.831221 Byte0 end_step=30 best_step=27
8019 22:50:20.834735 Byte1 end_step=30 best_step=27
8020 22:50:20.837808 Byte0 TX OE(2T, 0.5T) = (3, 3)
8021 22:50:20.841311 Byte1 TX OE(2T, 0.5T) = (3, 3)
8022 22:50:20.841455
8023 22:50:20.841546
8024 22:50:20.847828 [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
8025 22:50:20.851373 CH0 RK0: MR19=303, MR18=2415
8026 22:50:20.857635 CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16
8027 22:50:20.857740
8028 22:50:20.861271 ----->DramcWriteLeveling(PI) begin...
8029 22:50:20.861390 ==
8030 22:50:20.864580 Dram Type= 6, Freq= 0, CH_0, rank 1
8031 22:50:20.867308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 22:50:20.867409 ==
8033 22:50:20.870477 Write leveling (Byte 0): 34 => 34
8034 22:50:20.874005 Write leveling (Byte 1): 29 => 29
8035 22:50:20.877239 DramcWriteLeveling(PI) end<-----
8036 22:50:20.877348
8037 22:50:20.877426 ==
8038 22:50:20.880617 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 22:50:20.887018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 22:50:20.887101 ==
8041 22:50:20.887165 [Gating] SW mode calibration
8042 22:50:20.897096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8043 22:50:20.900665 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8044 22:50:20.903773 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 22:50:20.910247 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 22:50:20.913637 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 22:50:20.917145 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8048 22:50:20.923677 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8049 22:50:20.926953 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8050 22:50:20.930558 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 22:50:20.937061 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 22:50:20.940088 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 22:50:20.943338 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 22:50:20.949913 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 22:50:20.953532 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8056 22:50:20.956772 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8057 22:50:20.963546 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
8058 22:50:20.966491 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8059 22:50:20.969533 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 22:50:20.976864 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 22:50:20.979603 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 22:50:20.982862 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 22:50:20.989406 1 6 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8064 22:50:20.992895 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8065 22:50:20.996268 1 6 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8066 22:50:21.002880 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 22:50:21.005898 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 22:50:21.009220 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 22:50:21.016024 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 22:50:21.019876 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 22:50:21.022831 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8072 22:50:21.029198 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8073 22:50:21.032609 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8074 22:50:21.036094 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 22:50:21.042447 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 22:50:21.046346 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 22:50:21.048890 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 22:50:21.055649 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 22:50:21.058665 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 22:50:21.062065 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 22:50:21.068868 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 22:50:21.072230 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 22:50:21.075567 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 22:50:21.082290 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 22:50:21.085668 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 22:50:21.088558 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 22:50:21.095235 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8088 22:50:21.098600 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8089 22:50:21.101958 Total UI for P1: 0, mck2ui 16
8090 22:50:21.104769 best dqsien dly found for B0: ( 1, 9, 12)
8091 22:50:21.108470 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 22:50:21.111347 Total UI for P1: 0, mck2ui 16
8093 22:50:21.114851 best dqsien dly found for B1: ( 1, 9, 16)
8094 22:50:21.118444 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8095 22:50:21.121724 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8096 22:50:21.121834
8097 22:50:21.128044 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8098 22:50:21.131617 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8099 22:50:21.134902 [Gating] SW calibration Done
8100 22:50:21.135001 ==
8101 22:50:21.137686 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 22:50:21.141210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 22:50:21.141308 ==
8104 22:50:21.144662 RX Vref Scan: 0
8105 22:50:21.144777
8106 22:50:21.144868 RX Vref 0 -> 0, step: 1
8107 22:50:21.144956
8108 22:50:21.147959 RX Delay 0 -> 252, step: 8
8109 22:50:21.150803 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8110 22:50:21.154460 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8111 22:50:21.160780 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8112 22:50:21.164280 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8113 22:50:21.167308 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8114 22:50:21.170759 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8115 22:50:21.174259 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8116 22:50:21.180950 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8117 22:50:21.184233 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8118 22:50:21.187648 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8119 22:50:21.191056 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8120 22:50:21.194549 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8121 22:50:21.200717 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8122 22:50:21.204232 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8123 22:50:21.207105 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8124 22:50:21.210815 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8125 22:50:21.213883 ==
8126 22:50:21.213983 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 22:50:21.220555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 22:50:21.220667 ==
8129 22:50:21.220761 DQS Delay:
8130 22:50:21.223710 DQS0 = 0, DQS1 = 0
8131 22:50:21.223809 DQM Delay:
8132 22:50:21.227133 DQM0 = 132, DQM1 = 128
8133 22:50:21.227231 DQ Delay:
8134 22:50:21.230623 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8135 22:50:21.233484 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8136 22:50:21.237308 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8137 22:50:21.240080 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8138 22:50:21.240153
8139 22:50:21.240214
8140 22:50:21.240273 ==
8141 22:50:21.243496 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 22:50:21.250265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 22:50:21.250346 ==
8144 22:50:21.250410
8145 22:50:21.250475
8146 22:50:21.250533 TX Vref Scan disable
8147 22:50:21.253662 == TX Byte 0 ==
8148 22:50:21.257251 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8149 22:50:21.263923 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8150 22:50:21.264025 == TX Byte 1 ==
8151 22:50:21.267145 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8152 22:50:21.273754 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8153 22:50:21.273831 ==
8154 22:50:21.276474 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 22:50:21.280063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 22:50:21.280139 ==
8157 22:50:21.293083
8158 22:50:21.296318 TX Vref early break, caculate TX vref
8159 22:50:21.299632 TX Vref=16, minBit 0, minWin=22, winSum=378
8160 22:50:21.303135 TX Vref=18, minBit 3, minWin=22, winSum=385
8161 22:50:21.306036 TX Vref=20, minBit 1, minWin=22, winSum=395
8162 22:50:21.309414 TX Vref=22, minBit 1, minWin=24, winSum=403
8163 22:50:21.313045 TX Vref=24, minBit 1, minWin=24, winSum=412
8164 22:50:21.319444 TX Vref=26, minBit 1, minWin=24, winSum=415
8165 22:50:21.322753 TX Vref=28, minBit 1, minWin=24, winSum=411
8166 22:50:21.325891 TX Vref=30, minBit 0, minWin=24, winSum=406
8167 22:50:21.329482 TX Vref=32, minBit 1, minWin=23, winSum=397
8168 22:50:21.332529 TX Vref=34, minBit 1, minWin=22, winSum=391
8169 22:50:21.339130 [TxChooseVref] Worse bit 1, Min win 24, Win sum 415, Final Vref 26
8170 22:50:21.339231
8171 22:50:21.342493 Final TX Range 0 Vref 26
8172 22:50:21.342565
8173 22:50:21.342625 ==
8174 22:50:21.345625 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 22:50:21.349180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 22:50:21.349284 ==
8177 22:50:21.349397
8178 22:50:21.349459
8179 22:50:21.352388 TX Vref Scan disable
8180 22:50:21.359028 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8181 22:50:21.359138 == TX Byte 0 ==
8182 22:50:21.362426 u2DelayCellOfst[0]=11 cells (3 PI)
8183 22:50:21.365545 u2DelayCellOfst[1]=14 cells (4 PI)
8184 22:50:21.368914 u2DelayCellOfst[2]=11 cells (3 PI)
8185 22:50:21.371930 u2DelayCellOfst[3]=14 cells (4 PI)
8186 22:50:21.375745 u2DelayCellOfst[4]=7 cells (2 PI)
8187 22:50:21.379021 u2DelayCellOfst[5]=0 cells (0 PI)
8188 22:50:21.381966 u2DelayCellOfst[6]=18 cells (5 PI)
8189 22:50:21.385334 u2DelayCellOfst[7]=14 cells (4 PI)
8190 22:50:21.388581 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8191 22:50:21.392188 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8192 22:50:21.395387 == TX Byte 1 ==
8193 22:50:21.398664 u2DelayCellOfst[8]=0 cells (0 PI)
8194 22:50:21.402034 u2DelayCellOfst[9]=3 cells (1 PI)
8195 22:50:21.402111 u2DelayCellOfst[10]=11 cells (3 PI)
8196 22:50:21.405498 u2DelayCellOfst[11]=3 cells (1 PI)
8197 22:50:21.408263 u2DelayCellOfst[12]=14 cells (4 PI)
8198 22:50:21.411772 u2DelayCellOfst[13]=14 cells (4 PI)
8199 22:50:21.415368 u2DelayCellOfst[14]=18 cells (5 PI)
8200 22:50:21.418262 u2DelayCellOfst[15]=14 cells (4 PI)
8201 22:50:21.425419 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8202 22:50:21.428093 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8203 22:50:21.428173 DramC Write-DBI on
8204 22:50:21.428233 ==
8205 22:50:21.431787 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 22:50:21.438236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 22:50:21.438340 ==
8208 22:50:21.438432
8209 22:50:21.438516
8210 22:50:21.441620 TX Vref Scan disable
8211 22:50:21.441689 == TX Byte 0 ==
8212 22:50:21.448506 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8213 22:50:21.448608 == TX Byte 1 ==
8214 22:50:21.451239 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8215 22:50:21.454400 DramC Write-DBI off
8216 22:50:21.454496
8217 22:50:21.454588 [DATLAT]
8218 22:50:21.458017 Freq=1600, CH0 RK1
8219 22:50:21.458115
8220 22:50:21.458202 DATLAT Default: 0xf
8221 22:50:21.461441 0, 0xFFFF, sum = 0
8222 22:50:21.461518 1, 0xFFFF, sum = 0
8223 22:50:21.464401 2, 0xFFFF, sum = 0
8224 22:50:21.464473 3, 0xFFFF, sum = 0
8225 22:50:21.467717 4, 0xFFFF, sum = 0
8226 22:50:21.467786 5, 0xFFFF, sum = 0
8227 22:50:21.470888 6, 0xFFFF, sum = 0
8228 22:50:21.474591 7, 0xFFFF, sum = 0
8229 22:50:21.474661 8, 0xFFFF, sum = 0
8230 22:50:21.478093 9, 0xFFFF, sum = 0
8231 22:50:21.478171 10, 0xFFFF, sum = 0
8232 22:50:21.480709 11, 0xFFFF, sum = 0
8233 22:50:21.480807 12, 0xFFFF, sum = 0
8234 22:50:21.484296 13, 0xFFFF, sum = 0
8235 22:50:21.484391 14, 0x0, sum = 1
8236 22:50:21.487644 15, 0x0, sum = 2
8237 22:50:21.487741 16, 0x0, sum = 3
8238 22:50:21.490839 17, 0x0, sum = 4
8239 22:50:21.490907 best_step = 15
8240 22:50:21.490969
8241 22:50:21.491037 ==
8242 22:50:21.494205 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 22:50:21.497487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 22:50:21.500533 ==
8245 22:50:21.500627 RX Vref Scan: 0
8246 22:50:21.500713
8247 22:50:21.504219 RX Vref 0 -> 0, step: 1
8248 22:50:21.504289
8249 22:50:21.504354 RX Delay 11 -> 252, step: 4
8250 22:50:21.511504 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8251 22:50:21.514808 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8252 22:50:21.518449 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8253 22:50:21.521122 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8254 22:50:21.524591 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8255 22:50:21.531228 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8256 22:50:21.534740 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8257 22:50:21.538235 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8258 22:50:21.540934 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8259 22:50:21.544365 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8260 22:50:21.550884 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8261 22:50:21.554448 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8262 22:50:21.557302 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8263 22:50:21.560755 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8264 22:50:21.567516 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8265 22:50:21.571338 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8266 22:50:21.571417 ==
8267 22:50:21.574587 Dram Type= 6, Freq= 0, CH_0, rank 1
8268 22:50:21.577365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 22:50:21.577448 ==
8270 22:50:21.581207 DQS Delay:
8271 22:50:21.581290 DQS0 = 0, DQS1 = 0
8272 22:50:21.581411 DQM Delay:
8273 22:50:21.583991 DQM0 = 130, DQM1 = 125
8274 22:50:21.584074 DQ Delay:
8275 22:50:21.587223 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8276 22:50:21.590542 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8277 22:50:21.597600 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8278 22:50:21.600557 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8279 22:50:21.600664
8280 22:50:21.600763
8281 22:50:21.600867
8282 22:50:21.603638 [DramC_TX_OE_Calibration] TA2
8283 22:50:21.606787 Original DQ_B0 (3 6) =30, OEN = 27
8284 22:50:21.610051 Original DQ_B1 (3 6) =30, OEN = 27
8285 22:50:21.610156 24, 0x0, End_B0=24 End_B1=24
8286 22:50:21.613573 25, 0x0, End_B0=25 End_B1=25
8287 22:50:21.616498 26, 0x0, End_B0=26 End_B1=26
8288 22:50:21.619892 27, 0x0, End_B0=27 End_B1=27
8289 22:50:21.623789 28, 0x0, End_B0=28 End_B1=28
8290 22:50:21.623891 29, 0x0, End_B0=29 End_B1=29
8291 22:50:21.626500 30, 0x0, End_B0=30 End_B1=30
8292 22:50:21.629765 31, 0x4141, End_B0=30 End_B1=30
8293 22:50:21.632861 Byte0 end_step=30 best_step=27
8294 22:50:21.636375 Byte1 end_step=30 best_step=27
8295 22:50:21.639750 Byte0 TX OE(2T, 0.5T) = (3, 3)
8296 22:50:21.639830 Byte1 TX OE(2T, 0.5T) = (3, 3)
8297 22:50:21.642598
8298 22:50:21.642677
8299 22:50:21.649906 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8300 22:50:21.652558 CH0 RK1: MR19=303, MR18=2104
8301 22:50:21.659346 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8302 22:50:21.662476 [RxdqsGatingPostProcess] freq 1600
8303 22:50:21.666076 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8304 22:50:21.668944 best DQS0 dly(2T, 0.5T) = (1, 1)
8305 22:50:21.672384 best DQS1 dly(2T, 0.5T) = (1, 1)
8306 22:50:21.676272 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8307 22:50:21.678963 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8308 22:50:21.682635 best DQS0 dly(2T, 0.5T) = (1, 1)
8309 22:50:21.685896 best DQS1 dly(2T, 0.5T) = (1, 1)
8310 22:50:21.688884 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8311 22:50:21.692709 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8312 22:50:21.695674 Pre-setting of DQS Precalculation
8313 22:50:21.698907 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8314 22:50:21.698988 ==
8315 22:50:21.702207 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 22:50:21.705550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 22:50:21.709097 ==
8318 22:50:21.712021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8319 22:50:21.715489 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8320 22:50:21.721713 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8321 22:50:21.728417 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8322 22:50:21.738820 [CA 0] Center 42 (13~72) winsize 60
8323 22:50:21.738939 [CA 1] Center 43 (14~72) winsize 59
8324 22:50:21.742018 [CA 2] Center 37 (9~66) winsize 58
8325 22:50:21.745601 [CA 3] Center 37 (8~66) winsize 59
8326 22:50:21.748553 [CA 4] Center 38 (8~68) winsize 61
8327 22:50:21.752040 [CA 5] Center 37 (8~67) winsize 60
8328 22:50:21.752140
8329 22:50:21.755613 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8330 22:50:21.755706
8331 22:50:21.762211 [CATrainingPosCal] consider 1 rank data
8332 22:50:21.762308 u2DelayCellTimex100 = 262/100 ps
8333 22:50:21.768235 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8334 22:50:21.771741 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8335 22:50:21.775269 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8336 22:50:21.778368 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8337 22:50:21.781375 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8338 22:50:21.785372 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8339 22:50:21.785470
8340 22:50:21.788069 CA PerBit enable=1, Macro0, CA PI delay=37
8341 22:50:21.788150
8342 22:50:21.791182 [CBTSetCACLKResult] CA Dly = 37
8343 22:50:21.794623 CS Dly: 8 (0~39)
8344 22:50:21.797772 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8345 22:50:21.801318 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8346 22:50:21.801423 ==
8347 22:50:21.804675 Dram Type= 6, Freq= 0, CH_1, rank 1
8348 22:50:21.811288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 22:50:21.811387 ==
8350 22:50:21.814518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8351 22:50:21.821214 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8352 22:50:21.824374 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8353 22:50:21.831095 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8354 22:50:21.838870 [CA 0] Center 41 (12~71) winsize 60
8355 22:50:21.842550 [CA 1] Center 42 (13~72) winsize 60
8356 22:50:21.845790 [CA 2] Center 37 (8~67) winsize 60
8357 22:50:21.848754 [CA 3] Center 36 (7~66) winsize 60
8358 22:50:21.852350 [CA 4] Center 37 (8~67) winsize 60
8359 22:50:21.855714 [CA 5] Center 37 (8~67) winsize 60
8360 22:50:21.856020
8361 22:50:21.859085 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8362 22:50:21.859483
8363 22:50:21.862330 [CATrainingPosCal] consider 2 rank data
8364 22:50:21.865918 u2DelayCellTimex100 = 262/100 ps
8365 22:50:21.871878 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8366 22:50:21.875477 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8367 22:50:21.879039 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8368 22:50:21.881950 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8369 22:50:21.885595 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8370 22:50:21.888507 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8371 22:50:21.888937
8372 22:50:21.891822 CA PerBit enable=1, Macro0, CA PI delay=37
8373 22:50:21.892409
8374 22:50:21.895317 [CBTSetCACLKResult] CA Dly = 37
8375 22:50:21.899325 CS Dly: 10 (0~43)
8376 22:50:21.902029 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8377 22:50:21.904914 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8378 22:50:21.905420
8379 22:50:21.908388 ----->DramcWriteLeveling(PI) begin...
8380 22:50:21.908876 ==
8381 22:50:21.911861 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 22:50:21.918559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 22:50:21.918993 ==
8384 22:50:21.921607 Write leveling (Byte 0): 24 => 24
8385 22:50:21.925269 Write leveling (Byte 1): 27 => 27
8386 22:50:21.925724 DramcWriteLeveling(PI) end<-----
8387 22:50:21.928361
8388 22:50:21.928790 ==
8389 22:50:21.931695 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 22:50:21.934882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 22:50:21.935317 ==
8392 22:50:21.938078 [Gating] SW mode calibration
8393 22:50:21.945051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8394 22:50:21.948155 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8395 22:50:21.954744 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 22:50:21.958052 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 22:50:21.961602 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 22:50:21.968436 1 4 12 | B1->B0 | 2929 2d2d | 1 0 | (1 1) (0 0)
8399 22:50:21.971380 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 22:50:21.975117 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 22:50:21.982009 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 22:50:21.984915 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 22:50:21.988486 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 22:50:21.994621 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 22:50:21.997982 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 22:50:22.001412 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8407 22:50:22.008031 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 22:50:22.011103 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 22:50:22.014478 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 22:50:22.021482 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 22:50:22.024056 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 22:50:22.027447 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 22:50:22.034323 1 6 8 | B1->B0 | 2525 302f | 0 1 | (0 0) (0 0)
8414 22:50:22.037523 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 22:50:22.040989 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 22:50:22.047234 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 22:50:22.050760 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 22:50:22.054254 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 22:50:22.060458 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 22:50:22.064036 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 22:50:22.067261 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8422 22:50:22.073785 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8423 22:50:22.076763 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 22:50:22.080174 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 22:50:22.087090 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 22:50:22.090416 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 22:50:22.093398 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 22:50:22.099818 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 22:50:22.103698 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 22:50:22.106872 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 22:50:22.112848 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 22:50:22.116437 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 22:50:22.119974 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 22:50:22.126264 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 22:50:22.130116 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 22:50:22.133499 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 22:50:22.139707 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8438 22:50:22.142823 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8439 22:50:22.145925 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 22:50:22.149446 Total UI for P1: 0, mck2ui 16
8441 22:50:22.152491 best dqsien dly found for B0: ( 1, 9, 10)
8442 22:50:22.156160 Total UI for P1: 0, mck2ui 16
8443 22:50:22.159418 best dqsien dly found for B1: ( 1, 9, 12)
8444 22:50:22.163035 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8445 22:50:22.165832 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8446 22:50:22.166258
8447 22:50:22.172794 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8448 22:50:22.175902 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8449 22:50:22.178886 [Gating] SW calibration Done
8450 22:50:22.179332 ==
8451 22:50:22.182489 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 22:50:22.185866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 22:50:22.186299 ==
8454 22:50:22.186635 RX Vref Scan: 0
8455 22:50:22.189170
8456 22:50:22.189765 RX Vref 0 -> 0, step: 1
8457 22:50:22.190341
8458 22:50:22.192026 RX Delay 0 -> 252, step: 8
8459 22:50:22.195306 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8460 22:50:22.198805 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8461 22:50:22.205787 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8462 22:50:22.208745 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8463 22:50:22.212181 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8464 22:50:22.215847 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8465 22:50:22.218681 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8466 22:50:22.225373 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8467 22:50:22.228300 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8468 22:50:22.231694 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8469 22:50:22.235514 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8470 22:50:22.241432 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8471 22:50:22.245011 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8472 22:50:22.248609 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8473 22:50:22.251496 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8474 22:50:22.255059 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8475 22:50:22.258026 ==
8476 22:50:22.258450 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 22:50:22.264864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 22:50:22.265291 ==
8479 22:50:22.265677 DQS Delay:
8480 22:50:22.268458 DQS0 = 0, DQS1 = 0
8481 22:50:22.268888 DQM Delay:
8482 22:50:22.271212 DQM0 = 138, DQM1 = 129
8483 22:50:22.271644 DQ Delay:
8484 22:50:22.274544 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8485 22:50:22.277970 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8486 22:50:22.281679 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8487 22:50:22.285005 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8488 22:50:22.285511
8489 22:50:22.285847
8490 22:50:22.286210 ==
8491 22:50:22.287989 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 22:50:22.294350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 22:50:22.294771 ==
8494 22:50:22.295269
8495 22:50:22.295677
8496 22:50:22.295983 TX Vref Scan disable
8497 22:50:22.298155 == TX Byte 0 ==
8498 22:50:22.301406 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8499 22:50:22.308159 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8500 22:50:22.308572 == TX Byte 1 ==
8501 22:50:22.311489 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8502 22:50:22.318217 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8503 22:50:22.318843 ==
8504 22:50:22.321130 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 22:50:22.324478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 22:50:22.324902 ==
8507 22:50:22.337175
8508 22:50:22.340620 TX Vref early break, caculate TX vref
8509 22:50:22.343450 TX Vref=16, minBit 5, minWin=21, winSum=374
8510 22:50:22.347574 TX Vref=18, minBit 0, minWin=22, winSum=381
8511 22:50:22.350503 TX Vref=20, minBit 5, minWin=23, winSum=393
8512 22:50:22.353493 TX Vref=22, minBit 0, minWin=24, winSum=405
8513 22:50:22.356954 TX Vref=24, minBit 5, minWin=24, winSum=411
8514 22:50:22.363716 TX Vref=26, minBit 0, minWin=25, winSum=420
8515 22:50:22.367003 TX Vref=28, minBit 5, minWin=25, winSum=421
8516 22:50:22.370462 TX Vref=30, minBit 0, minWin=25, winSum=418
8517 22:50:22.373311 TX Vref=32, minBit 0, minWin=24, winSum=403
8518 22:50:22.376562 TX Vref=34, minBit 6, minWin=23, winSum=395
8519 22:50:22.383449 [TxChooseVref] Worse bit 5, Min win 25, Win sum 421, Final Vref 28
8520 22:50:22.383895
8521 22:50:22.386752 Final TX Range 0 Vref 28
8522 22:50:22.387202
8523 22:50:22.387631 ==
8524 22:50:22.389723 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 22:50:22.393083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 22:50:22.393573 ==
8527 22:50:22.394007
8528 22:50:22.394424
8529 22:50:22.396325 TX Vref Scan disable
8530 22:50:22.402889 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8531 22:50:22.403334 == TX Byte 0 ==
8532 22:50:22.406442 u2DelayCellOfst[0]=22 cells (6 PI)
8533 22:50:22.409717 u2DelayCellOfst[1]=14 cells (4 PI)
8534 22:50:22.412815 u2DelayCellOfst[2]=0 cells (0 PI)
8535 22:50:22.416011 u2DelayCellOfst[3]=7 cells (2 PI)
8536 22:50:22.419457 u2DelayCellOfst[4]=11 cells (3 PI)
8537 22:50:22.423183 u2DelayCellOfst[5]=22 cells (6 PI)
8538 22:50:22.425985 u2DelayCellOfst[6]=22 cells (6 PI)
8539 22:50:22.429402 u2DelayCellOfst[7]=7 cells (2 PI)
8540 22:50:22.432908 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8541 22:50:22.436352 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8542 22:50:22.439573 == TX Byte 1 ==
8543 22:50:22.442904 u2DelayCellOfst[8]=0 cells (0 PI)
8544 22:50:22.443580 u2DelayCellOfst[9]=3 cells (1 PI)
8545 22:50:22.446204 u2DelayCellOfst[10]=11 cells (3 PI)
8546 22:50:22.449526 u2DelayCellOfst[11]=3 cells (1 PI)
8547 22:50:22.452300 u2DelayCellOfst[12]=14 cells (4 PI)
8548 22:50:22.455658 u2DelayCellOfst[13]=18 cells (5 PI)
8549 22:50:22.459626 u2DelayCellOfst[14]=18 cells (5 PI)
8550 22:50:22.462412 u2DelayCellOfst[15]=18 cells (5 PI)
8551 22:50:22.469174 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8552 22:50:22.472334 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8553 22:50:22.472760 DramC Write-DBI on
8554 22:50:22.473090 ==
8555 22:50:22.475434 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 22:50:22.482425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 22:50:22.482853 ==
8558 22:50:22.483188
8559 22:50:22.483497
8560 22:50:22.485493 TX Vref Scan disable
8561 22:50:22.485938 == TX Byte 0 ==
8562 22:50:22.491645 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8563 22:50:22.492071 == TX Byte 1 ==
8564 22:50:22.495092 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8565 22:50:22.498553 DramC Write-DBI off
8566 22:50:22.498971
8567 22:50:22.499298 [DATLAT]
8568 22:50:22.501530 Freq=1600, CH1 RK0
8569 22:50:22.501951
8570 22:50:22.502280 DATLAT Default: 0xf
8571 22:50:22.505151 0, 0xFFFF, sum = 0
8572 22:50:22.505625 1, 0xFFFF, sum = 0
8573 22:50:22.508768 2, 0xFFFF, sum = 0
8574 22:50:22.509195 3, 0xFFFF, sum = 0
8575 22:50:22.511587 4, 0xFFFF, sum = 0
8576 22:50:22.512014 5, 0xFFFF, sum = 0
8577 22:50:22.515146 6, 0xFFFF, sum = 0
8578 22:50:22.515572 7, 0xFFFF, sum = 0
8579 22:50:22.518557 8, 0xFFFF, sum = 0
8580 22:50:22.521502 9, 0xFFFF, sum = 0
8581 22:50:22.521944 10, 0xFFFF, sum = 0
8582 22:50:22.524782 11, 0xFFFF, sum = 0
8583 22:50:22.525286 12, 0xFFFF, sum = 0
8584 22:50:22.528309 13, 0xFFFF, sum = 0
8585 22:50:22.528761 14, 0x0, sum = 1
8586 22:50:22.531145 15, 0x0, sum = 2
8587 22:50:22.531570 16, 0x0, sum = 3
8588 22:50:22.534909 17, 0x0, sum = 4
8589 22:50:22.535416 best_step = 15
8590 22:50:22.535847
8591 22:50:22.536162 ==
8592 22:50:22.538177 Dram Type= 6, Freq= 0, CH_1, rank 0
8593 22:50:22.541226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8594 22:50:22.544535 ==
8595 22:50:22.544977 RX Vref Scan: 1
8596 22:50:22.545311
8597 22:50:22.548024 Set Vref Range= 24 -> 127
8598 22:50:22.548451
8599 22:50:22.548798 RX Vref 24 -> 127, step: 1
8600 22:50:22.551355
8601 22:50:22.551791 RX Delay 19 -> 252, step: 4
8602 22:50:22.552344
8603 22:50:22.554187 Set Vref, RX VrefLevel [Byte0]: 24
8604 22:50:22.557870 [Byte1]: 24
8605 22:50:22.561450
8606 22:50:22.561866 Set Vref, RX VrefLevel [Byte0]: 25
8607 22:50:22.565130 [Byte1]: 25
8608 22:50:22.568945
8609 22:50:22.569594 Set Vref, RX VrefLevel [Byte0]: 26
8610 22:50:22.572408 [Byte1]: 26
8611 22:50:22.576705
8612 22:50:22.577119 Set Vref, RX VrefLevel [Byte0]: 27
8613 22:50:22.579760 [Byte1]: 27
8614 22:50:22.584665
8615 22:50:22.585080 Set Vref, RX VrefLevel [Byte0]: 28
8616 22:50:22.587491 [Byte1]: 28
8617 22:50:22.592041
8618 22:50:22.592471 Set Vref, RX VrefLevel [Byte0]: 29
8619 22:50:22.594634 [Byte1]: 29
8620 22:50:22.598924
8621 22:50:22.599030 Set Vref, RX VrefLevel [Byte0]: 30
8622 22:50:22.602381 [Byte1]: 30
8623 22:50:22.606376
8624 22:50:22.606457 Set Vref, RX VrefLevel [Byte0]: 31
8625 22:50:22.609628 [Byte1]: 31
8626 22:50:22.614141
8627 22:50:22.614226 Set Vref, RX VrefLevel [Byte0]: 32
8628 22:50:22.617309 [Byte1]: 32
8629 22:50:22.621886
8630 22:50:22.621970 Set Vref, RX VrefLevel [Byte0]: 33
8631 22:50:22.624852 [Byte1]: 33
8632 22:50:22.629342
8633 22:50:22.629436 Set Vref, RX VrefLevel [Byte0]: 34
8634 22:50:22.632657 [Byte1]: 34
8635 22:50:22.636886
8636 22:50:22.636966 Set Vref, RX VrefLevel [Byte0]: 35
8637 22:50:22.640124 [Byte1]: 35
8638 22:50:22.644810
8639 22:50:22.644890 Set Vref, RX VrefLevel [Byte0]: 36
8640 22:50:22.647821 [Byte1]: 36
8641 22:50:22.652220
8642 22:50:22.652317 Set Vref, RX VrefLevel [Byte0]: 37
8643 22:50:22.655546 [Byte1]: 37
8644 22:50:22.659490
8645 22:50:22.662842 Set Vref, RX VrefLevel [Byte0]: 38
8646 22:50:22.665818 [Byte1]: 38
8647 22:50:22.665898
8648 22:50:22.669256 Set Vref, RX VrefLevel [Byte0]: 39
8649 22:50:22.672579 [Byte1]: 39
8650 22:50:22.672660
8651 22:50:22.675561 Set Vref, RX VrefLevel [Byte0]: 40
8652 22:50:22.679013 [Byte1]: 40
8653 22:50:22.679097
8654 22:50:22.682567 Set Vref, RX VrefLevel [Byte0]: 41
8655 22:50:22.685864 [Byte1]: 41
8656 22:50:22.690102
8657 22:50:22.690181 Set Vref, RX VrefLevel [Byte0]: 42
8658 22:50:22.693046 [Byte1]: 42
8659 22:50:22.697632
8660 22:50:22.697712 Set Vref, RX VrefLevel [Byte0]: 43
8661 22:50:22.700892 [Byte1]: 43
8662 22:50:22.705019
8663 22:50:22.705100 Set Vref, RX VrefLevel [Byte0]: 44
8664 22:50:22.708306 [Byte1]: 44
8665 22:50:22.712604
8666 22:50:22.712684 Set Vref, RX VrefLevel [Byte0]: 45
8667 22:50:22.715955 [Byte1]: 45
8668 22:50:22.720173
8669 22:50:22.720280 Set Vref, RX VrefLevel [Byte0]: 46
8670 22:50:22.723884 [Byte1]: 46
8671 22:50:22.727776
8672 22:50:22.727856 Set Vref, RX VrefLevel [Byte0]: 47
8673 22:50:22.731049 [Byte1]: 47
8674 22:50:22.735224
8675 22:50:22.735304 Set Vref, RX VrefLevel [Byte0]: 48
8676 22:50:22.738505 [Byte1]: 48
8677 22:50:22.742645
8678 22:50:22.742725 Set Vref, RX VrefLevel [Byte0]: 49
8679 22:50:22.745978 [Byte1]: 49
8680 22:50:22.750752
8681 22:50:22.750832 Set Vref, RX VrefLevel [Byte0]: 50
8682 22:50:22.753306 [Byte1]: 50
8683 22:50:22.757491
8684 22:50:22.760897 Set Vref, RX VrefLevel [Byte0]: 51
8685 22:50:22.764429 [Byte1]: 51
8686 22:50:22.764510
8687 22:50:22.767818 Set Vref, RX VrefLevel [Byte0]: 52
8688 22:50:22.771429 [Byte1]: 52
8689 22:50:22.771510
8690 22:50:22.774799 Set Vref, RX VrefLevel [Byte0]: 53
8691 22:50:22.777270 [Byte1]: 53
8692 22:50:22.777388
8693 22:50:22.780860 Set Vref, RX VrefLevel [Byte0]: 54
8694 22:50:22.784581 [Byte1]: 54
8695 22:50:22.788290
8696 22:50:22.788384 Set Vref, RX VrefLevel [Byte0]: 55
8697 22:50:22.794992 [Byte1]: 55
8698 22:50:22.795073
8699 22:50:22.797776 Set Vref, RX VrefLevel [Byte0]: 56
8700 22:50:22.801102 [Byte1]: 56
8701 22:50:22.801183
8702 22:50:22.804898 Set Vref, RX VrefLevel [Byte0]: 57
8703 22:50:22.808173 [Byte1]: 57
8704 22:50:22.808253
8705 22:50:22.811326 Set Vref, RX VrefLevel [Byte0]: 58
8706 22:50:22.814241 [Byte1]: 58
8707 22:50:22.818408
8708 22:50:22.818488 Set Vref, RX VrefLevel [Byte0]: 59
8709 22:50:22.821971 [Byte1]: 59
8710 22:50:22.825958
8711 22:50:22.826038 Set Vref, RX VrefLevel [Byte0]: 60
8712 22:50:22.829523 [Byte1]: 60
8713 22:50:22.833554
8714 22:50:22.833634 Set Vref, RX VrefLevel [Byte0]: 61
8715 22:50:22.836849 [Byte1]: 61
8716 22:50:22.841690
8717 22:50:22.841770 Set Vref, RX VrefLevel [Byte0]: 62
8718 22:50:22.844527 [Byte1]: 62
8719 22:50:22.849041
8720 22:50:22.849122 Set Vref, RX VrefLevel [Byte0]: 63
8721 22:50:22.852008 [Byte1]: 63
8722 22:50:22.856685
8723 22:50:22.856766 Set Vref, RX VrefLevel [Byte0]: 64
8724 22:50:22.859514 [Byte1]: 64
8725 22:50:22.863924
8726 22:50:22.864024 Set Vref, RX VrefLevel [Byte0]: 65
8727 22:50:22.867191 [Byte1]: 65
8728 22:50:22.871635
8729 22:50:22.871715 Set Vref, RX VrefLevel [Byte0]: 66
8730 22:50:22.875342 [Byte1]: 66
8731 22:50:22.879010
8732 22:50:22.879090 Set Vref, RX VrefLevel [Byte0]: 67
8733 22:50:22.885729 [Byte1]: 67
8734 22:50:22.886635
8735 22:50:22.886715 Set Vref, RX VrefLevel [Byte0]: 68
8736 22:50:22.889737 [Byte1]: 68
8737 22:50:22.894465
8738 22:50:22.894545 Set Vref, RX VrefLevel [Byte0]: 69
8739 22:50:22.897804 [Byte1]: 69
8740 22:50:22.902138
8741 22:50:22.902218 Set Vref, RX VrefLevel [Byte0]: 70
8742 22:50:22.905575 [Byte1]: 70
8743 22:50:22.909543
8744 22:50:22.909623 Set Vref, RX VrefLevel [Byte0]: 71
8745 22:50:22.912410 [Byte1]: 71
8746 22:50:22.916985
8747 22:50:22.917067 Set Vref, RX VrefLevel [Byte0]: 72
8748 22:50:22.920027 [Byte1]: 72
8749 22:50:22.924509
8750 22:50:22.924589 Set Vref, RX VrefLevel [Byte0]: 73
8751 22:50:22.927797 [Byte1]: 73
8752 22:50:22.931837
8753 22:50:22.931921 Set Vref, RX VrefLevel [Byte0]: 74
8754 22:50:22.935147 [Byte1]: 74
8755 22:50:22.939474
8756 22:50:22.939554 Set Vref, RX VrefLevel [Byte0]: 75
8757 22:50:22.942842 [Byte1]: 75
8758 22:50:22.947214
8759 22:50:22.947325 Final RX Vref Byte 0 = 54 to rank0
8760 22:50:22.950329 Final RX Vref Byte 1 = 58 to rank0
8761 22:50:22.953975 Final RX Vref Byte 0 = 54 to rank1
8762 22:50:22.956911 Final RX Vref Byte 1 = 58 to rank1==
8763 22:50:22.960377 Dram Type= 6, Freq= 0, CH_1, rank 0
8764 22:50:22.966879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 22:50:22.966961 ==
8766 22:50:22.967024 DQS Delay:
8767 22:50:22.970294 DQS0 = 0, DQS1 = 0
8768 22:50:22.970374 DQM Delay:
8769 22:50:22.970438 DQM0 = 135, DQM1 = 129
8770 22:50:22.973861 DQ Delay:
8771 22:50:22.976967 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8772 22:50:22.980135 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8773 22:50:22.983467 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =118
8774 22:50:22.986634 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8775 22:50:22.986715
8776 22:50:22.986778
8777 22:50:22.986837
8778 22:50:22.989768 [DramC_TX_OE_Calibration] TA2
8779 22:50:22.993493 Original DQ_B0 (3 6) =30, OEN = 27
8780 22:50:22.997086 Original DQ_B1 (3 6) =30, OEN = 27
8781 22:50:22.999809 24, 0x0, End_B0=24 End_B1=24
8782 22:50:23.003439 25, 0x0, End_B0=25 End_B1=25
8783 22:50:23.003521 26, 0x0, End_B0=26 End_B1=26
8784 22:50:23.006300 27, 0x0, End_B0=27 End_B1=27
8785 22:50:23.009624 28, 0x0, End_B0=28 End_B1=28
8786 22:50:23.013028 29, 0x0, End_B0=29 End_B1=29
8787 22:50:23.013109 30, 0x0, End_B0=30 End_B1=30
8788 22:50:23.016624 31, 0x5151, End_B0=30 End_B1=30
8789 22:50:23.020029 Byte0 end_step=30 best_step=27
8790 22:50:23.023081 Byte1 end_step=30 best_step=27
8791 22:50:23.026340 Byte0 TX OE(2T, 0.5T) = (3, 3)
8792 22:50:23.029775 Byte1 TX OE(2T, 0.5T) = (3, 3)
8793 22:50:23.029856
8794 22:50:23.029919
8795 22:50:23.036171 [DQSOSCAuto] RK0, (LSB)MR18= 0x170d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8796 22:50:23.039414 CH1 RK0: MR19=303, MR18=170D
8797 22:50:23.046334 CH1_RK0: MR19=0x303, MR18=0x170D, DQSOSC=398, MR23=63, INC=23, DEC=15
8798 22:50:23.046416
8799 22:50:23.049273 ----->DramcWriteLeveling(PI) begin...
8800 22:50:23.049376 ==
8801 22:50:23.052622 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 22:50:23.055821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 22:50:23.055903 ==
8804 22:50:23.059719 Write leveling (Byte 0): 24 => 24
8805 22:50:23.062511 Write leveling (Byte 1): 26 => 26
8806 22:50:23.065800 DramcWriteLeveling(PI) end<-----
8807 22:50:23.065882
8808 22:50:23.065945 ==
8809 22:50:23.069195 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 22:50:23.072700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 22:50:23.075862 ==
8812 22:50:23.075949 [Gating] SW mode calibration
8813 22:50:23.085936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8814 22:50:23.089196 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8815 22:50:23.092124 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 22:50:23.098998 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 22:50:23.101998 1 4 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8818 22:50:23.105589 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8819 22:50:23.111874 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 22:50:23.115290 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 22:50:23.119000 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 22:50:23.125177 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 22:50:23.128808 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 22:50:23.131701 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 22:50:23.138498 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8826 22:50:23.141872 1 5 12 | B1->B0 | 2c2c 3434 | 0 1 | (1 0) (1 0)
8827 22:50:23.145082 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8828 22:50:23.151587 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 22:50:23.154794 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 22:50:23.157945 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 22:50:23.164627 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 22:50:23.168067 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 22:50:23.171158 1 6 8 | B1->B0 | 3232 2323 | 0 0 | (1 1) (0 0)
8834 22:50:23.178095 1 6 12 | B1->B0 | 4646 2828 | 0 0 | (0 0) (0 0)
8835 22:50:23.180834 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 22:50:23.184352 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 22:50:23.191057 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 22:50:23.194537 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 22:50:23.197852 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 22:50:23.204588 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 22:50:23.207313 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8842 22:50:23.210977 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8843 22:50:23.217382 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8844 22:50:23.220896 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 22:50:23.224138 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 22:50:23.231043 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 22:50:23.234370 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 22:50:23.237699 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 22:50:23.244205 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 22:50:23.247555 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 22:50:23.250440 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 22:50:23.257113 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 22:50:23.260940 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 22:50:23.263544 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 22:50:23.270416 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 22:50:23.273770 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 22:50:23.276868 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8858 22:50:23.283039 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8859 22:50:23.286813 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 22:50:23.290034 Total UI for P1: 0, mck2ui 16
8861 22:50:23.293040 best dqsien dly found for B0: ( 1, 9, 12)
8862 22:50:23.296401 Total UI for P1: 0, mck2ui 16
8863 22:50:23.299963 best dqsien dly found for B1: ( 1, 9, 10)
8864 22:50:23.303017 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8865 22:50:23.306170 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8866 22:50:23.306251
8867 22:50:23.309531 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8868 22:50:23.316717 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8869 22:50:23.316826 [Gating] SW calibration Done
8870 22:50:23.319314 ==
8871 22:50:23.319421 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 22:50:23.326224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 22:50:23.326307 ==
8874 22:50:23.326440 RX Vref Scan: 0
8875 22:50:23.326654
8876 22:50:23.329481 RX Vref 0 -> 0, step: 1
8877 22:50:23.329561
8878 22:50:23.333077 RX Delay 0 -> 252, step: 8
8879 22:50:23.335915 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8880 22:50:23.339675 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8881 22:50:23.342627 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8882 22:50:23.349123 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8883 22:50:23.352631 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8884 22:50:23.356250 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8885 22:50:23.358872 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8886 22:50:23.362330 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8887 22:50:23.369125 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8888 22:50:23.372063 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8889 22:50:23.375411 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8890 22:50:23.378923 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8891 22:50:23.385309 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8892 22:50:23.388675 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8893 22:50:23.391931 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8894 22:50:23.395502 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8895 22:50:23.395583 ==
8896 22:50:23.398474 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 22:50:23.404753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 22:50:23.404835 ==
8899 22:50:23.404898 DQS Delay:
8900 22:50:23.408606 DQS0 = 0, DQS1 = 0
8901 22:50:23.408687 DQM Delay:
8902 22:50:23.408751 DQM0 = 136, DQM1 = 129
8903 22:50:23.411546 DQ Delay:
8904 22:50:23.414844 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8905 22:50:23.418249 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8906 22:50:23.421655 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8907 22:50:23.424933 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8908 22:50:23.425020
8909 22:50:23.425121
8910 22:50:23.425211 ==
8911 22:50:23.427927 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 22:50:23.434793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 22:50:23.434875 ==
8914 22:50:23.434939
8915 22:50:23.434996
8916 22:50:23.435052 TX Vref Scan disable
8917 22:50:23.438333 == TX Byte 0 ==
8918 22:50:23.441739 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8919 22:50:23.444791 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8920 22:50:23.448096 == TX Byte 1 ==
8921 22:50:23.451637 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8922 22:50:23.457741 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8923 22:50:23.457825 ==
8924 22:50:23.461213 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 22:50:23.464735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 22:50:23.464817 ==
8927 22:50:23.476985
8928 22:50:23.480042 TX Vref early break, caculate TX vref
8929 22:50:23.483397 TX Vref=16, minBit 5, minWin=22, winSum=383
8930 22:50:23.486437 TX Vref=18, minBit 0, minWin=23, winSum=396
8931 22:50:23.490033 TX Vref=20, minBit 0, minWin=24, winSum=402
8932 22:50:23.493226 TX Vref=22, minBit 0, minWin=24, winSum=410
8933 22:50:23.496788 TX Vref=24, minBit 5, minWin=24, winSum=416
8934 22:50:23.502840 TX Vref=26, minBit 0, minWin=24, winSum=421
8935 22:50:23.506424 TX Vref=28, minBit 0, minWin=25, winSum=423
8936 22:50:23.509795 TX Vref=30, minBit 0, minWin=24, winSum=415
8937 22:50:23.513208 TX Vref=32, minBit 0, minWin=24, winSum=410
8938 22:50:23.516520 TX Vref=34, minBit 5, minWin=23, winSum=397
8939 22:50:23.522843 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8940 22:50:23.522924
8941 22:50:23.526221 Final TX Range 0 Vref 28
8942 22:50:23.526310
8943 22:50:23.526373 ==
8944 22:50:23.529392 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 22:50:23.532591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 22:50:23.532673 ==
8947 22:50:23.532736
8948 22:50:23.532796
8949 22:50:23.536111 TX Vref Scan disable
8950 22:50:23.543041 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8951 22:50:23.543122 == TX Byte 0 ==
8952 22:50:23.545924 u2DelayCellOfst[0]=18 cells (5 PI)
8953 22:50:23.549066 u2DelayCellOfst[1]=14 cells (4 PI)
8954 22:50:23.552454 u2DelayCellOfst[2]=0 cells (0 PI)
8955 22:50:23.555570 u2DelayCellOfst[3]=7 cells (2 PI)
8956 22:50:23.559285 u2DelayCellOfst[4]=7 cells (2 PI)
8957 22:50:23.562068 u2DelayCellOfst[5]=22 cells (6 PI)
8958 22:50:23.565842 u2DelayCellOfst[6]=18 cells (5 PI)
8959 22:50:23.568733 u2DelayCellOfst[7]=7 cells (2 PI)
8960 22:50:23.572156 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8961 22:50:23.575347 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8962 22:50:23.578859 == TX Byte 1 ==
8963 22:50:23.582298 u2DelayCellOfst[8]=0 cells (0 PI)
8964 22:50:23.585835 u2DelayCellOfst[9]=7 cells (2 PI)
8965 22:50:23.585916 u2DelayCellOfst[10]=11 cells (3 PI)
8966 22:50:23.588807 u2DelayCellOfst[11]=7 cells (2 PI)
8967 22:50:23.592334 u2DelayCellOfst[12]=14 cells (4 PI)
8968 22:50:23.595220 u2DelayCellOfst[13]=18 cells (5 PI)
8969 22:50:23.598674 u2DelayCellOfst[14]=22 cells (6 PI)
8970 22:50:23.602027 u2DelayCellOfst[15]=18 cells (5 PI)
8971 22:50:23.608711 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8972 22:50:23.612041 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8973 22:50:23.612123 DramC Write-DBI on
8974 22:50:23.612186 ==
8975 22:50:23.615159 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 22:50:23.621674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 22:50:23.621756 ==
8978 22:50:23.621820
8979 22:50:23.621877
8980 22:50:23.621931 TX Vref Scan disable
8981 22:50:23.626223 == TX Byte 0 ==
8982 22:50:23.629198 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8983 22:50:23.632704 == TX Byte 1 ==
8984 22:50:23.636113 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8985 22:50:23.636194 DramC Write-DBI off
8986 22:50:23.639127
8987 22:50:23.639207 [DATLAT]
8988 22:50:23.639271 Freq=1600, CH1 RK1
8989 22:50:23.639330
8990 22:50:23.643186 DATLAT Default: 0xf
8991 22:50:23.643267 0, 0xFFFF, sum = 0
8992 22:50:23.646047 1, 0xFFFF, sum = 0
8993 22:50:23.649317 2, 0xFFFF, sum = 0
8994 22:50:23.649407 3, 0xFFFF, sum = 0
8995 22:50:23.652542 4, 0xFFFF, sum = 0
8996 22:50:23.652624 5, 0xFFFF, sum = 0
8997 22:50:23.655734 6, 0xFFFF, sum = 0
8998 22:50:23.655817 7, 0xFFFF, sum = 0
8999 22:50:23.658856 8, 0xFFFF, sum = 0
9000 22:50:23.658939 9, 0xFFFF, sum = 0
9001 22:50:23.662298 10, 0xFFFF, sum = 0
9002 22:50:23.662380 11, 0xFFFF, sum = 0
9003 22:50:23.665586 12, 0xFFFF, sum = 0
9004 22:50:23.665668 13, 0xFFFF, sum = 0
9005 22:50:23.668794 14, 0x0, sum = 1
9006 22:50:23.668875 15, 0x0, sum = 2
9007 22:50:23.672301 16, 0x0, sum = 3
9008 22:50:23.672383 17, 0x0, sum = 4
9009 22:50:23.675173 best_step = 15
9010 22:50:23.675254
9011 22:50:23.675316 ==
9012 22:50:23.678656 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 22:50:23.682161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 22:50:23.682242 ==
9015 22:50:23.685044 RX Vref Scan: 0
9016 22:50:23.685124
9017 22:50:23.685188 RX Vref 0 -> 0, step: 1
9018 22:50:23.685247
9019 22:50:23.688141 RX Delay 11 -> 252, step: 4
9020 22:50:23.694987 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9021 22:50:23.698023 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9022 22:50:23.701489 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9023 22:50:23.704911 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9024 22:50:23.708532 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9025 22:50:23.714986 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9026 22:50:23.717806 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9027 22:50:23.721490 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9028 22:50:23.724407 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9029 22:50:23.731349 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9030 22:50:23.734361 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9031 22:50:23.738017 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9032 22:50:23.741236 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9033 22:50:23.744186 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9034 22:50:23.751097 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9035 22:50:23.754031 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9036 22:50:23.754227 ==
9037 22:50:23.757827 Dram Type= 6, Freq= 0, CH_1, rank 1
9038 22:50:23.761196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9039 22:50:23.761421 ==
9040 22:50:23.764190 DQS Delay:
9041 22:50:23.764381 DQS0 = 0, DQS1 = 0
9042 22:50:23.767029 DQM Delay:
9043 22:50:23.767219 DQM0 = 134, DQM1 = 126
9044 22:50:23.767337 DQ Delay:
9045 22:50:23.773874 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9046 22:50:23.777441 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9047 22:50:23.780613 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9048 22:50:23.783595 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =138
9049 22:50:23.783675
9050 22:50:23.783738
9051 22:50:23.783798
9052 22:50:23.786950 [DramC_TX_OE_Calibration] TA2
9053 22:50:23.790652 Original DQ_B0 (3 6) =30, OEN = 27
9054 22:50:23.793843 Original DQ_B1 (3 6) =30, OEN = 27
9055 22:50:23.793924 24, 0x0, End_B0=24 End_B1=24
9056 22:50:23.796798 25, 0x0, End_B0=25 End_B1=25
9057 22:50:23.800684 26, 0x0, End_B0=26 End_B1=26
9058 22:50:23.803300 27, 0x0, End_B0=27 End_B1=27
9059 22:50:23.806751 28, 0x0, End_B0=28 End_B1=28
9060 22:50:23.806833 29, 0x0, End_B0=29 End_B1=29
9061 22:50:23.810307 30, 0x0, End_B0=30 End_B1=30
9062 22:50:23.813378 31, 0x4141, End_B0=30 End_B1=30
9063 22:50:23.816892 Byte0 end_step=30 best_step=27
9064 22:50:23.819932 Byte1 end_step=30 best_step=27
9065 22:50:23.823546 Byte0 TX OE(2T, 0.5T) = (3, 3)
9066 22:50:23.823627 Byte1 TX OE(2T, 0.5T) = (3, 3)
9067 22:50:23.823690
9068 22:50:23.823748
9069 22:50:23.833456 [DQSOSCAuto] RK1, (LSB)MR18= 0xc09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9070 22:50:23.836272 CH1 RK1: MR19=303, MR18=C09
9071 22:50:23.839705 CH1_RK1: MR19=0x303, MR18=0xC09, DQSOSC=403, MR23=63, INC=22, DEC=15
9072 22:50:23.843364 [RxdqsGatingPostProcess] freq 1600
9073 22:50:23.849520 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9074 22:50:23.852964 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 22:50:23.856166 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 22:50:23.859812 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 22:50:23.862743 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 22:50:23.866330 best DQS0 dly(2T, 0.5T) = (1, 1)
9079 22:50:23.869251 best DQS1 dly(2T, 0.5T) = (1, 1)
9080 22:50:23.872831 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9081 22:50:23.875973 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9082 22:50:23.876054 Pre-setting of DQS Precalculation
9083 22:50:23.882849 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9084 22:50:23.889228 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9085 22:50:23.896240 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 22:50:23.896321
9087 22:50:23.896384
9088 22:50:23.899302 [Calibration Summary] 3200 Mbps
9089 22:50:23.903473 CH 0, Rank 0
9090 22:50:23.903554 SW Impedance : PASS
9091 22:50:23.906199 DUTY Scan : NO K
9092 22:50:23.909272 ZQ Calibration : PASS
9093 22:50:23.909392 Jitter Meter : NO K
9094 22:50:23.912698 CBT Training : PASS
9095 22:50:23.915900 Write leveling : PASS
9096 22:50:23.915980 RX DQS gating : PASS
9097 22:50:23.919243 RX DQ/DQS(RDDQC) : PASS
9098 22:50:23.922194 TX DQ/DQS : PASS
9099 22:50:23.922276 RX DATLAT : PASS
9100 22:50:23.926061 RX DQ/DQS(Engine): PASS
9101 22:50:23.926143 TX OE : PASS
9102 22:50:23.929262 All Pass.
9103 22:50:23.929381
9104 22:50:23.929445 CH 0, Rank 1
9105 22:50:23.932348 SW Impedance : PASS
9106 22:50:23.932428 DUTY Scan : NO K
9107 22:50:23.935715 ZQ Calibration : PASS
9108 22:50:23.938997 Jitter Meter : NO K
9109 22:50:23.939079 CBT Training : PASS
9110 22:50:23.942321 Write leveling : PASS
9111 22:50:23.945663 RX DQS gating : PASS
9112 22:50:23.945744 RX DQ/DQS(RDDQC) : PASS
9113 22:50:23.948877 TX DQ/DQS : PASS
9114 22:50:23.952336 RX DATLAT : PASS
9115 22:50:23.952416 RX DQ/DQS(Engine): PASS
9116 22:50:23.955487 TX OE : PASS
9117 22:50:23.955582 All Pass.
9118 22:50:23.955646
9119 22:50:23.958671 CH 1, Rank 0
9120 22:50:23.958751 SW Impedance : PASS
9121 22:50:23.961950 DUTY Scan : NO K
9122 22:50:23.965593 ZQ Calibration : PASS
9123 22:50:23.965675 Jitter Meter : NO K
9124 22:50:23.968808 CBT Training : PASS
9125 22:50:23.972436 Write leveling : PASS
9126 22:50:23.972516 RX DQS gating : PASS
9127 22:50:23.975607 RX DQ/DQS(RDDQC) : PASS
9128 22:50:23.978772 TX DQ/DQS : PASS
9129 22:50:23.978853 RX DATLAT : PASS
9130 22:50:23.981802 RX DQ/DQS(Engine): PASS
9131 22:50:23.981884 TX OE : PASS
9132 22:50:23.985371 All Pass.
9133 22:50:23.985452
9134 22:50:23.985514 CH 1, Rank 1
9135 22:50:23.988658 SW Impedance : PASS
9136 22:50:23.988738 DUTY Scan : NO K
9137 22:50:23.991835 ZQ Calibration : PASS
9138 22:50:23.995523 Jitter Meter : NO K
9139 22:50:23.995604 CBT Training : PASS
9140 22:50:23.998372 Write leveling : PASS
9141 22:50:24.001954 RX DQS gating : PASS
9142 22:50:24.002035 RX DQ/DQS(RDDQC) : PASS
9143 22:50:24.004845 TX DQ/DQS : PASS
9144 22:50:24.008416 RX DATLAT : PASS
9145 22:50:24.008496 RX DQ/DQS(Engine): PASS
9146 22:50:24.011816 TX OE : PASS
9147 22:50:24.011897 All Pass.
9148 22:50:24.011960
9149 22:50:24.014985 DramC Write-DBI on
9150 22:50:24.018287 PER_BANK_REFRESH: Hybrid Mode
9151 22:50:24.018368 TX_TRACKING: ON
9152 22:50:24.028082 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9153 22:50:24.034529 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9154 22:50:24.044609 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9155 22:50:24.047649 [FAST_K] Save calibration result to emmc
9156 22:50:24.051040 sync common calibartion params.
9157 22:50:24.051120 sync cbt_mode0:1, 1:1
9158 22:50:24.054882 dram_init: ddr_geometry: 2
9159 22:50:24.057583 dram_init: ddr_geometry: 2
9160 22:50:24.057677 dram_init: ddr_geometry: 2
9161 22:50:24.061107 0:dram_rank_size:100000000
9162 22:50:24.064757 1:dram_rank_size:100000000
9163 22:50:24.067348 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9164 22:50:24.071194 DFS_SHUFFLE_HW_MODE: ON
9165 22:50:24.074242 dramc_set_vcore_voltage set vcore to 725000
9166 22:50:24.077155 Read voltage for 1600, 0
9167 22:50:24.077275 Vio18 = 0
9168 22:50:24.080660 Vcore = 725000
9169 22:50:24.080792 Vdram = 0
9170 22:50:24.080896 Vddq = 0
9171 22:50:24.084114 Vmddr = 0
9172 22:50:24.084263 switch to 3200 Mbps bootup
9173 22:50:24.087140 [DramcRunTimeConfig]
9174 22:50:24.087288 PHYPLL
9175 22:50:24.090624 DPM_CONTROL_AFTERK: ON
9176 22:50:24.090794 PER_BANK_REFRESH: ON
9177 22:50:24.093617 REFRESH_OVERHEAD_REDUCTION: ON
9178 22:50:24.097358 CMD_PICG_NEW_MODE: OFF
9179 22:50:24.097584 XRTWTW_NEW_MODE: ON
9180 22:50:24.100820 XRTRTR_NEW_MODE: ON
9181 22:50:24.101056 TX_TRACKING: ON
9182 22:50:24.104034 RDSEL_TRACKING: OFF
9183 22:50:24.107601 DQS Precalculation for DVFS: ON
9184 22:50:24.107990 RX_TRACKING: OFF
9185 22:50:24.110895 HW_GATING DBG: ON
9186 22:50:24.111281 ZQCS_ENABLE_LP4: ON
9187 22:50:24.114091 RX_PICG_NEW_MODE: ON
9188 22:50:24.114568 TX_PICG_NEW_MODE: ON
9189 22:50:24.117554 ENABLE_RX_DCM_DPHY: ON
9190 22:50:24.120476 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9191 22:50:24.123759 DUMMY_READ_FOR_TRACKING: OFF
9192 22:50:24.124181 !!! SPM_CONTROL_AFTERK: OFF
9193 22:50:24.127407 !!! SPM could not control APHY
9194 22:50:24.130208 IMPEDANCE_TRACKING: ON
9195 22:50:24.130626 TEMP_SENSOR: ON
9196 22:50:24.133503 HW_SAVE_FOR_SR: OFF
9197 22:50:24.137625 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9198 22:50:24.140528 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9199 22:50:24.143122 Read ODT Tracking: ON
9200 22:50:24.143203 Refresh Rate DeBounce: ON
9201 22:50:24.146512 DFS_NO_QUEUE_FLUSH: ON
9202 22:50:24.150131 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9203 22:50:24.153876 ENABLE_DFS_RUNTIME_MRW: OFF
9204 22:50:24.153961 DDR_RESERVE_NEW_MODE: ON
9205 22:50:24.156188 MR_CBT_SWITCH_FREQ: ON
9206 22:50:24.159299 =========================
9207 22:50:24.177391 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9208 22:50:24.180788 dram_init: ddr_geometry: 2
9209 22:50:24.199031 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9210 22:50:24.202576 dram_init: dram init end (result: 0)
9211 22:50:24.209084 DRAM-K: Full calibration passed in 24667 msecs
9212 22:50:24.212348 MRC: failed to locate region type 0.
9213 22:50:24.212557 DRAM rank0 size:0x100000000,
9214 22:50:24.215467 DRAM rank1 size=0x100000000
9215 22:50:24.225641 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9216 22:50:24.232052 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9217 22:50:24.239250 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9218 22:50:24.245497 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9219 22:50:24.248699 DRAM rank0 size:0x100000000,
9220 22:50:24.252338 DRAM rank1 size=0x100000000
9221 22:50:24.252758 CBMEM:
9222 22:50:24.255662 IMD: root @ 0xfffff000 254 entries.
9223 22:50:24.259147 IMD: root @ 0xffffec00 62 entries.
9224 22:50:24.262661 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9225 22:50:24.268791 WARNING: RO_VPD is uninitialized or empty.
9226 22:50:24.271662 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9227 22:50:24.279181 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9228 22:50:24.292182 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9229 22:50:24.303212 BS: romstage times (exec / console): total (unknown) / 24157 ms
9230 22:50:24.303629
9231 22:50:24.303955
9232 22:50:24.313108 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9233 22:50:24.316381 ARM64: Exception handlers installed.
9234 22:50:24.320059 ARM64: Testing exception
9235 22:50:24.323231 ARM64: Done test exception
9236 22:50:24.323668 Enumerating buses...
9237 22:50:24.326469 Show all devs... Before device enumeration.
9238 22:50:24.329598 Root Device: enabled 1
9239 22:50:24.333158 CPU_CLUSTER: 0: enabled 1
9240 22:50:24.333599 CPU: 00: enabled 1
9241 22:50:24.336273 Compare with tree...
9242 22:50:24.336694 Root Device: enabled 1
9243 22:50:24.339987 CPU_CLUSTER: 0: enabled 1
9244 22:50:24.343187 CPU: 00: enabled 1
9245 22:50:24.343605 Root Device scanning...
9246 22:50:24.346231 scan_static_bus for Root Device
9247 22:50:24.349521 CPU_CLUSTER: 0 enabled
9248 22:50:24.352700 scan_static_bus for Root Device done
9249 22:50:24.356152 scan_bus: bus Root Device finished in 8 msecs
9250 22:50:24.356579 done
9251 22:50:24.362668 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9252 22:50:24.366138 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9253 22:50:24.372614 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9254 22:50:24.376043 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9255 22:50:24.379455 Allocating resources...
9256 22:50:24.382680 Reading resources...
9257 22:50:24.385737 Root Device read_resources bus 0 link: 0
9258 22:50:24.389348 DRAM rank0 size:0x100000000,
9259 22:50:24.389769 DRAM rank1 size=0x100000000
9260 22:50:24.395399 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9261 22:50:24.395824 CPU: 00 missing read_resources
9262 22:50:24.402399 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9263 22:50:24.405654 Root Device read_resources bus 0 link: 0 done
9264 22:50:24.408602 Done reading resources.
9265 22:50:24.412157 Show resources in subtree (Root Device)...After reading.
9266 22:50:24.415494 Root Device child on link 0 CPU_CLUSTER: 0
9267 22:50:24.418485 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 22:50:24.428314 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 22:50:24.428792 CPU: 00
9270 22:50:24.434970 Root Device assign_resources, bus 0 link: 0
9271 22:50:24.438228 CPU_CLUSTER: 0 missing set_resources
9272 22:50:24.441939 Root Device assign_resources, bus 0 link: 0 done
9273 22:50:24.445163 Done setting resources.
9274 22:50:24.448379 Show resources in subtree (Root Device)...After assigning values.
9275 22:50:24.451496 Root Device child on link 0 CPU_CLUSTER: 0
9276 22:50:24.457889 CPU_CLUSTER: 0 child on link 0 CPU: 00
9277 22:50:24.464449 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9278 22:50:24.467741 CPU: 00
9279 22:50:24.468159 Done allocating resources.
9280 22:50:24.474682 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9281 22:50:24.475107 Enabling resources...
9282 22:50:24.477947 done.
9283 22:50:24.481383 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9284 22:50:24.484393 Initializing devices...
9285 22:50:24.484810 Root Device init
9286 22:50:24.488013 init hardware done!
9287 22:50:24.488431 0x00000018: ctrlr->caps
9288 22:50:24.491197 52.000 MHz: ctrlr->f_max
9289 22:50:24.494252 0.400 MHz: ctrlr->f_min
9290 22:50:24.498026 0x40ff8080: ctrlr->voltages
9291 22:50:24.498457 sclk: 390625
9292 22:50:24.498788 Bus Width = 1
9293 22:50:24.501078 sclk: 390625
9294 22:50:24.501604 Bus Width = 1
9295 22:50:24.504524 Early init status = 3
9296 22:50:24.507361 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9297 22:50:24.511018 in-header: 03 fc 00 00 01 00 00 00
9298 22:50:24.514420 in-data: 00
9299 22:50:24.517563 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9300 22:50:24.522513 in-header: 03 fd 00 00 00 00 00 00
9301 22:50:24.525198 in-data:
9302 22:50:24.528625 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9303 22:50:24.532544 in-header: 03 fc 00 00 01 00 00 00
9304 22:50:24.535939 in-data: 00
9305 22:50:24.538696 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9306 22:50:24.543158 in-header: 03 fd 00 00 00 00 00 00
9307 22:50:24.547060 in-data:
9308 22:50:24.549577 [SSUSB] Setting up USB HOST controller...
9309 22:50:24.553058 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9310 22:50:24.556500 [SSUSB] phy power-on done.
9311 22:50:24.559776 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9312 22:50:24.566294 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9313 22:50:24.569846 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9314 22:50:24.576195 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9315 22:50:24.583539 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9316 22:50:24.589683 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9317 22:50:24.596389 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9318 22:50:24.603089 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9319 22:50:24.605929 SPM: binary array size = 0x9dc
9320 22:50:24.609399 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9321 22:50:24.615914 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9322 22:50:24.622393 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9323 22:50:24.629103 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9324 22:50:24.632625 configure_display: Starting display init
9325 22:50:24.666880 anx7625_power_on_init: Init interface.
9326 22:50:24.669695 anx7625_disable_pd_protocol: Disabled PD feature.
9327 22:50:24.673375 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9328 22:50:24.701040 anx7625_start_dp_work: Secure OCM version=00
9329 22:50:24.704345 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9330 22:50:24.719400 sp_tx_get_edid_block: EDID Block = 1
9331 22:50:24.821886 Extracted contents:
9332 22:50:24.825389 header: 00 ff ff ff ff ff ff 00
9333 22:50:24.828165 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9334 22:50:24.831675 version: 01 04
9335 22:50:24.835106 basic params: 95 1f 11 78 0a
9336 22:50:24.838502 chroma info: 76 90 94 55 54 90 27 21 50 54
9337 22:50:24.841837 established: 00 00 00
9338 22:50:24.848028 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9339 22:50:24.851694 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9340 22:50:24.858159 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9341 22:50:24.864725 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9342 22:50:24.871250 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9343 22:50:24.874456 extensions: 00
9344 22:50:24.874874 checksum: fb
9345 22:50:24.875223
9346 22:50:24.877447 Manufacturer: IVO Model 57d Serial Number 0
9347 22:50:24.880779 Made week 0 of 2020
9348 22:50:24.884546 EDID version: 1.4
9349 22:50:24.884974 Digital display
9350 22:50:24.888049 6 bits per primary color channel
9351 22:50:24.888477 DisplayPort interface
9352 22:50:24.891113 Maximum image size: 31 cm x 17 cm
9353 22:50:24.894407 Gamma: 220%
9354 22:50:24.894825 Check DPMS levels
9355 22:50:24.897430 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9356 22:50:24.904314 First detailed timing is preferred timing
9357 22:50:24.904735 Established timings supported:
9358 22:50:24.907454 Standard timings supported:
9359 22:50:24.910619 Detailed timings
9360 22:50:24.913933 Hex of detail: 383680a07038204018303c0035ae10000019
9361 22:50:24.920974 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9362 22:50:24.924138 0780 0798 07c8 0820 hborder 0
9363 22:50:24.927225 0438 043b 0447 0458 vborder 0
9364 22:50:24.930697 -hsync -vsync
9365 22:50:24.931142 Did detailed timing
9366 22:50:24.936935 Hex of detail: 000000000000000000000000000000000000
9367 22:50:24.940830 Manufacturer-specified data, tag 0
9368 22:50:24.943925 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9369 22:50:24.946934 ASCII string: InfoVision
9370 22:50:24.950442 Hex of detail: 000000fe00523134304e574635205248200a
9371 22:50:24.953542 ASCII string: R140NWF5 RH
9372 22:50:24.954055 Checksum
9373 22:50:24.957025 Checksum: 0xfb (valid)
9374 22:50:24.960354 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9375 22:50:24.963401 DSI data_rate: 832800000 bps
9376 22:50:24.969867 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9377 22:50:24.973308 anx7625_parse_edid: pixelclock(138800).
9378 22:50:24.976804 hactive(1920), hsync(48), hfp(24), hbp(88)
9379 22:50:24.980215 vactive(1080), vsync(12), vfp(3), vbp(17)
9380 22:50:24.982925 anx7625_dsi_config: config dsi.
9381 22:50:24.989631 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9382 22:50:25.003606 anx7625_dsi_config: success to config DSI
9383 22:50:25.006737 anx7625_dp_start: MIPI phy setup OK.
9384 22:50:25.010233 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9385 22:50:25.013430 mtk_ddp_mode_set invalid vrefresh 60
9386 22:50:25.016764 main_disp_path_setup
9387 22:50:25.017195 ovl_layer_smi_id_en
9388 22:50:25.020643 ovl_layer_smi_id_en
9389 22:50:25.021059 ccorr_config
9390 22:50:25.021435 aal_config
9391 22:50:25.023458 gamma_config
9392 22:50:25.023944 postmask_config
9393 22:50:25.026599 dither_config
9394 22:50:25.029935 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9395 22:50:25.036446 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9396 22:50:25.040111 Root Device init finished in 551 msecs
9397 22:50:25.042832 CPU_CLUSTER: 0 init
9398 22:50:25.049884 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9399 22:50:25.056466 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9400 22:50:25.056915 APU_MBOX 0x190000b0 = 0x10001
9401 22:50:25.059333 APU_MBOX 0x190001b0 = 0x10001
9402 22:50:25.062553 APU_MBOX 0x190005b0 = 0x10001
9403 22:50:25.066027 APU_MBOX 0x190006b0 = 0x10001
9404 22:50:25.072675 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9405 22:50:25.082802 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9406 22:50:25.095169 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9407 22:50:25.101851 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9408 22:50:25.113582 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9409 22:50:25.122510 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9410 22:50:25.125736 CPU_CLUSTER: 0 init finished in 81 msecs
9411 22:50:25.129026 Devices initialized
9412 22:50:25.132083 Show all devs... After init.
9413 22:50:25.132559 Root Device: enabled 1
9414 22:50:25.135535 CPU_CLUSTER: 0: enabled 1
9415 22:50:25.138816 CPU: 00: enabled 1
9416 22:50:25.142385 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9417 22:50:25.145202 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9418 22:50:25.149214 ELOG: NV offset 0x57f000 size 0x1000
9419 22:50:25.155681 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9420 22:50:25.162164 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9421 22:50:25.165217 ELOG: Event(17) added with size 13 at 2024-05-07 22:50:25 UTC
9422 22:50:25.171958 out: cmd=0x121: 03 db 21 01 00 00 00 00
9423 22:50:25.175459 in-header: 03 90 00 00 2c 00 00 00
9424 22:50:25.188618 in-data: ad 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9425 22:50:25.191506 ELOG: Event(A1) added with size 10 at 2024-05-07 22:50:25 UTC
9426 22:50:25.198375 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9427 22:50:25.204915 ELOG: Event(A0) added with size 9 at 2024-05-07 22:50:25 UTC
9428 22:50:25.208241 elog_add_boot_reason: Logged dev mode boot
9429 22:50:25.214706 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9430 22:50:25.215219 Finalize devices...
9431 22:50:25.218376 Devices finalized
9432 22:50:25.221240 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9433 22:50:25.224592 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9434 22:50:25.228456 in-header: 03 07 00 00 08 00 00 00
9435 22:50:25.231588 in-data: aa e4 47 04 13 02 00 00
9436 22:50:25.234956 Chrome EC: UHEPI supported
9437 22:50:25.241312 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9438 22:50:25.244740 in-header: 03 a9 00 00 08 00 00 00
9439 22:50:25.248297 in-data: 84 60 60 08 00 00 00 00
9440 22:50:25.254907 ELOG: Event(91) added with size 10 at 2024-05-07 22:50:25 UTC
9441 22:50:25.258063 Chrome EC: clear events_b mask to 0x0000000020004000
9442 22:50:25.264523 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9443 22:50:25.269007 in-header: 03 fd 00 00 00 00 00 00
9444 22:50:25.271946 in-data:
9445 22:50:25.275281 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9446 22:50:25.278855 Writing coreboot table at 0xffe64000
9447 22:50:25.285268 0. 000000000010a000-0000000000113fff: RAMSTAGE
9448 22:50:25.288618 1. 0000000040000000-00000000400fffff: RAM
9449 22:50:25.292087 2. 0000000040100000-000000004032afff: RAMSTAGE
9450 22:50:25.295160 3. 000000004032b000-00000000545fffff: RAM
9451 22:50:25.298359 4. 0000000054600000-000000005465ffff: BL31
9452 22:50:25.301973 5. 0000000054660000-00000000ffe63fff: RAM
9453 22:50:25.308333 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9454 22:50:25.311794 7. 0000000100000000-000000023fffffff: RAM
9455 22:50:25.315010 Passing 5 GPIOs to payload:
9456 22:50:25.318547 NAME | PORT | POLARITY | VALUE
9457 22:50:25.324992 EC in RW | 0x000000aa | low | undefined
9458 22:50:25.328498 EC interrupt | 0x00000005 | low | undefined
9459 22:50:25.334998 TPM interrupt | 0x000000ab | high | undefined
9460 22:50:25.338416 SD card detect | 0x00000011 | high | undefined
9461 22:50:25.341221 speaker enable | 0x00000093 | high | undefined
9462 22:50:25.344992 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9463 22:50:25.348641 in-header: 03 f9 00 00 02 00 00 00
9464 22:50:25.352003 in-data: 02 00
9465 22:50:25.355173 ADC[4]: Raw value=903400 ID=7
9466 22:50:25.358240 ADC[3]: Raw value=213282 ID=1
9467 22:50:25.358655 RAM Code: 0x71
9468 22:50:25.361555 ADC[6]: Raw value=75036 ID=0
9469 22:50:25.364951 ADC[5]: Raw value=213652 ID=1
9470 22:50:25.365406 SKU Code: 0x1
9471 22:50:25.371599 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b14b
9472 22:50:25.372207 coreboot table: 964 bytes.
9473 22:50:25.374695 IMD ROOT 0. 0xfffff000 0x00001000
9474 22:50:25.378074 IMD SMALL 1. 0xffffe000 0x00001000
9475 22:50:25.381475 RO MCACHE 2. 0xffffc000 0x00001104
9476 22:50:25.384900 CONSOLE 3. 0xfff7c000 0x00080000
9477 22:50:25.388247 FMAP 4. 0xfff7b000 0x00000452
9478 22:50:25.391472 TIME STAMP 5. 0xfff7a000 0x00000910
9479 22:50:25.394458 VBOOT WORK 6. 0xfff66000 0x00014000
9480 22:50:25.398474 RAMOOPS 7. 0xffe66000 0x00100000
9481 22:50:25.401925 COREBOOT 8. 0xffe64000 0x00002000
9482 22:50:25.404540 IMD small region:
9483 22:50:25.407783 IMD ROOT 0. 0xffffec00 0x00000400
9484 22:50:25.410879 VPD 1. 0xffffeb80 0x0000006c
9485 22:50:25.414213 MMC STATUS 2. 0xffffeb60 0x00000004
9486 22:50:25.421200 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9487 22:50:25.427679 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9488 22:50:25.465966 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9489 22:50:25.469222 Checking segment from ROM address 0x40100000
9490 22:50:25.475695 Checking segment from ROM address 0x4010001c
9491 22:50:25.479158 Loading segment from ROM address 0x40100000
9492 22:50:25.479572 code (compression=0)
9493 22:50:25.488800 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9494 22:50:25.495657 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9495 22:50:25.496138 it's not compressed!
9496 22:50:25.502518 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9497 22:50:25.508914 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9498 22:50:25.526974 Loading segment from ROM address 0x4010001c
9499 22:50:25.527510 Entry Point 0x80000000
9500 22:50:25.530105 Loaded segments
9501 22:50:25.533411 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9502 22:50:25.539964 Jumping to boot code at 0x80000000(0xffe64000)
9503 22:50:25.546869 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9504 22:50:25.553199 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9505 22:50:25.560940 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9506 22:50:25.563873 Checking segment from ROM address 0x40100000
9507 22:50:25.567383 Checking segment from ROM address 0x4010001c
9508 22:50:25.574115 Loading segment from ROM address 0x40100000
9509 22:50:25.574561 code (compression=1)
9510 22:50:25.580506 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9511 22:50:25.590161 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9512 22:50:25.590666 using LZMA
9513 22:50:25.599320 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9514 22:50:25.605379 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9515 22:50:25.609054 Loading segment from ROM address 0x4010001c
9516 22:50:25.612352 Entry Point 0x54601000
9517 22:50:25.612767 Loaded segments
9518 22:50:25.615621 NOTICE: MT8192 bl31_setup
9519 22:50:25.622824 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9520 22:50:25.626271 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9521 22:50:25.629427 WARNING: region 0:
9522 22:50:25.632614 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 22:50:25.633051 WARNING: region 1:
9524 22:50:25.638976 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9525 22:50:25.642509 WARNING: region 2:
9526 22:50:25.646320 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9527 22:50:25.649426 WARNING: region 3:
9528 22:50:25.655594 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9529 22:50:25.656012 WARNING: region 4:
9530 22:50:25.662481 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9531 22:50:25.662909 WARNING: region 5:
9532 22:50:25.665501 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 22:50:25.668688 WARNING: region 6:
9534 22:50:25.671712 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 22:50:25.675113 WARNING: region 7:
9536 22:50:25.678682 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 22:50:25.685686 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9538 22:50:25.688594 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9539 22:50:25.695352 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9540 22:50:25.698480 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9541 22:50:25.701883 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9542 22:50:25.708479 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9543 22:50:25.711907 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9544 22:50:25.715588 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9545 22:50:25.721593 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9546 22:50:25.724898 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9547 22:50:25.731423 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9548 22:50:25.734990 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9549 22:50:25.737801 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9550 22:50:25.744718 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9551 22:50:25.748203 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9552 22:50:25.754599 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9553 22:50:25.757844 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9554 22:50:25.761136 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9555 22:50:25.767875 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9556 22:50:25.770873 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9557 22:50:25.777775 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9558 22:50:25.781244 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9559 22:50:25.784357 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9560 22:50:25.790974 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9561 22:50:25.794286 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9562 22:50:25.800778 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9563 22:50:25.803822 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9564 22:50:25.807171 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9565 22:50:25.814137 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9566 22:50:25.817081 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9567 22:50:25.823977 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9568 22:50:25.826915 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9569 22:50:25.830516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9570 22:50:25.837059 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9571 22:50:25.840399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9572 22:50:25.843890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9573 22:50:25.847185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9574 22:50:25.853562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9575 22:50:25.856881 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9576 22:50:25.860284 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9577 22:50:25.863347 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9578 22:50:25.870518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9579 22:50:25.873476 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9580 22:50:25.877285 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9581 22:50:25.880002 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9582 22:50:25.886656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9583 22:50:25.889752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9584 22:50:25.893173 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9585 22:50:25.899859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9586 22:50:25.903071 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9587 22:50:25.909605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9588 22:50:25.912854 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9589 22:50:25.915795 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9590 22:50:25.922468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9591 22:50:25.926139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9592 22:50:25.932362 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9593 22:50:25.935978 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9594 22:50:25.942357 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9595 22:50:25.945850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9596 22:50:25.952237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9597 22:50:25.955873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9598 22:50:25.959527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9599 22:50:25.965734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9600 22:50:25.968802 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9601 22:50:25.975656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9602 22:50:25.979288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9603 22:50:25.985627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9604 22:50:25.989240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9605 22:50:25.995631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9606 22:50:26.001317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9607 22:50:26.002352 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9608 22:50:26.008854 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9609 22:50:26.011813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9610 22:50:26.018901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9611 22:50:26.021769 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9612 22:50:26.029005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9613 22:50:26.031671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9614 22:50:26.038773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9615 22:50:26.041574 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9616 22:50:26.045073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9617 22:50:26.051400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9618 22:50:26.054836 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9619 22:50:26.061411 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9620 22:50:26.064956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9621 22:50:26.071730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9622 22:50:26.075114 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9623 22:50:26.078301 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9624 22:50:26.084890 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9625 22:50:26.087878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9626 22:50:26.094923 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9627 22:50:26.098059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9628 22:50:26.104223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9629 22:50:26.107595 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9630 22:50:26.114508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9631 22:50:26.117607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9632 22:50:26.124408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9633 22:50:26.127297 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9634 22:50:26.130727 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9635 22:50:26.134128 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9636 22:50:26.140952 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9637 22:50:26.144053 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9638 22:50:26.147267 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9639 22:50:26.153958 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9640 22:50:26.157102 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9641 22:50:26.163354 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9642 22:50:26.166736 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9643 22:50:26.170141 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9644 22:50:26.176979 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9645 22:50:26.180497 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9646 22:50:26.187074 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9647 22:50:26.189976 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9648 22:50:26.193261 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9649 22:50:26.199979 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9650 22:50:26.203020 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9651 22:50:26.209392 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9652 22:50:26.212838 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9653 22:50:26.216458 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9654 22:50:26.222820 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9655 22:50:26.226065 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9656 22:50:26.229237 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9657 22:50:26.235982 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9658 22:50:26.239339 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9659 22:50:26.242784 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9660 22:50:26.245635 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9661 22:50:26.252187 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9662 22:50:26.255433 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9663 22:50:26.262508 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9664 22:50:26.265815 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9665 22:50:26.268955 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9666 22:50:26.275175 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9667 22:50:26.278511 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9668 22:50:26.285272 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9669 22:50:26.288499 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9670 22:50:26.291963 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9671 22:50:26.298794 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9672 22:50:26.301690 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9673 22:50:26.308406 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9674 22:50:26.312171 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9675 22:50:26.315401 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9676 22:50:26.321844 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9677 22:50:26.324790 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9678 22:50:26.331884 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9679 22:50:26.334698 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9680 22:50:26.337985 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9681 22:50:26.344629 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9682 22:50:26.348344 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9683 22:50:26.354972 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9684 22:50:26.358069 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9685 22:50:26.361230 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9686 22:50:26.367826 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9687 22:50:26.371428 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9688 22:50:26.377381 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9689 22:50:26.380712 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9690 22:50:26.384200 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9691 22:50:26.390954 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9692 22:50:26.394238 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9693 22:50:26.400823 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9694 22:50:26.404038 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9695 22:50:26.407063 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9696 22:50:26.413883 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9697 22:50:26.417410 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9698 22:50:26.423579 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9699 22:50:26.427091 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9700 22:50:26.430218 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9701 22:50:26.436820 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9702 22:50:26.440241 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9703 22:50:26.446433 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9704 22:50:26.449729 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9705 22:50:26.453179 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9706 22:50:26.459946 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9707 22:50:26.463192 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9708 22:50:26.469841 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9709 22:50:26.472984 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9710 22:50:26.476834 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9711 22:50:26.483132 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9712 22:50:26.486627 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9713 22:50:26.492822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9714 22:50:26.496048 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9715 22:50:26.499540 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9716 22:50:26.505941 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9717 22:50:26.509191 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9718 22:50:26.516110 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9719 22:50:26.519484 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9720 22:50:26.522705 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9721 22:50:26.529235 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9722 22:50:26.532413 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9723 22:50:26.536019 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9724 22:50:26.542495 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9725 22:50:26.545793 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9726 22:50:26.551947 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9727 22:50:26.555734 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9728 22:50:26.562404 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9729 22:50:26.565248 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9730 22:50:26.572156 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9731 22:50:26.575269 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9732 22:50:26.578424 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9733 22:50:26.585225 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9734 22:50:26.588368 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9735 22:50:26.595202 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9736 22:50:26.598064 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9737 22:50:26.604822 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9738 22:50:26.608003 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9739 22:50:26.611375 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9740 22:50:26.618189 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9741 22:50:26.621277 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9742 22:50:26.627999 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9743 22:50:26.630899 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9744 22:50:26.638094 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9745 22:50:26.640872 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9746 22:50:26.644620 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9747 22:50:26.651227 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9748 22:50:26.654602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9749 22:50:26.661288 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9750 22:50:26.664701 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9751 22:50:26.667956 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9752 22:50:26.674275 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9753 22:50:26.677266 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9754 22:50:26.684163 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9755 22:50:26.687130 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9756 22:50:26.693849 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9757 22:50:26.697067 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9758 22:50:26.700735 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9759 22:50:26.707381 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9760 22:50:26.710298 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9761 22:50:26.717297 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9762 22:50:26.720113 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9763 22:50:26.726878 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9764 22:50:26.730249 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9765 22:50:26.733656 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9766 22:50:26.739903 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9767 22:50:26.743635 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9768 22:50:26.746679 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9769 22:50:26.749920 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9770 22:50:26.756499 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9771 22:50:26.759332 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9772 22:50:26.763091 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9773 22:50:26.769466 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9774 22:50:26.772616 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9775 22:50:26.776048 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9776 22:50:26.783039 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9777 22:50:26.786286 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9778 22:50:26.792831 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9779 22:50:26.796346 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9780 22:50:26.799778 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9781 22:50:26.806154 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9782 22:50:26.809539 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9783 22:50:26.816435 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9784 22:50:26.819222 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9785 22:50:26.822297 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9786 22:50:26.829174 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9787 22:50:26.832110 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9788 22:50:26.835681 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9789 22:50:26.842425 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9790 22:50:26.845487 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9791 22:50:26.848702 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9792 22:50:26.855330 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9793 22:50:26.858841 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9794 22:50:26.865828 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9795 22:50:26.868548 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9796 22:50:26.871992 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9797 22:50:26.878606 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9798 22:50:26.881991 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9799 22:50:26.888373 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9800 22:50:26.891926 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9801 22:50:26.895015 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9802 22:50:26.901735 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9803 22:50:26.905519 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9804 22:50:26.908200 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9805 22:50:26.915009 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9806 22:50:26.918443 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9807 22:50:26.921444 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9808 22:50:26.924976 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9809 22:50:26.931445 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9810 22:50:26.934678 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9811 22:50:26.938471 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9812 22:50:26.941347 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9813 22:50:26.948243 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9814 22:50:26.951437 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9815 22:50:26.954955 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9816 22:50:26.958035 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9817 22:50:26.964716 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9818 22:50:26.967929 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9819 22:50:26.971336 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9820 22:50:26.978157 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9821 22:50:26.981018 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9822 22:50:26.987614 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9823 22:50:26.991388 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9824 22:50:26.997301 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9825 22:50:27.000992 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9826 22:50:27.004557 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9827 22:50:27.010716 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9828 22:50:27.014260 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9829 22:50:27.020976 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9830 22:50:27.024181 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9831 22:50:27.027229 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9832 22:50:27.033920 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9833 22:50:27.036997 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9834 22:50:27.044254 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9835 22:50:27.046864 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9836 22:50:27.050854 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9837 22:50:27.056827 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9838 22:50:27.060157 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9839 22:50:27.066764 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9840 22:50:27.070357 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9841 22:50:27.076986 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9842 22:50:27.080178 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9843 22:50:27.083381 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9844 22:50:27.089879 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9845 22:50:27.093616 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9846 22:50:27.099754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9847 22:50:27.103212 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9848 22:50:27.109771 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9849 22:50:27.113255 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9850 22:50:27.116060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9851 22:50:27.122684 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9852 22:50:27.126272 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9853 22:50:27.132899 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9854 22:50:27.135774 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9855 22:50:27.139413 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9856 22:50:27.145962 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9857 22:50:27.149222 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9858 22:50:27.155793 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9859 22:50:27.159147 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9860 22:50:27.162370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9861 22:50:27.169368 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9862 22:50:27.172213 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9863 22:50:27.179054 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9864 22:50:27.182147 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9865 22:50:27.188819 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9866 22:50:27.192392 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9867 22:50:27.195389 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9868 22:50:27.201977 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9869 22:50:27.205503 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9870 22:50:27.211909 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9871 22:50:27.215211 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9872 22:50:27.222261 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9873 22:50:27.225257 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9874 22:50:27.228612 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9875 22:50:27.234985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9876 22:50:27.238178 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9877 22:50:27.245188 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9878 22:50:27.248235 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9879 22:50:27.251710 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9880 22:50:27.257929 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9881 22:50:27.261518 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9882 22:50:27.267998 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9883 22:50:27.271299 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9884 22:50:27.274817 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9885 22:50:27.281615 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9886 22:50:27.284625 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9887 22:50:27.290902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9888 22:50:27.294546 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9889 22:50:27.301414 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9890 22:50:27.304275 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9891 22:50:27.307576 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9892 22:50:27.314064 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9893 22:50:27.317501 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9894 22:50:27.324799 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9895 22:50:27.327923 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9896 22:50:27.334342 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9897 22:50:27.337450 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9898 22:50:27.340792 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9899 22:50:27.347679 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9900 22:50:27.350615 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9901 22:50:27.357398 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9902 22:50:27.360888 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9903 22:50:27.367583 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9904 22:50:27.370360 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9905 22:50:27.376911 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9906 22:50:27.380385 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9907 22:50:27.383558 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9908 22:50:27.390111 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9909 22:50:27.393575 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9910 22:50:27.400606 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9911 22:50:27.403813 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9912 22:50:27.410418 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9913 22:50:27.413388 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9914 22:50:27.416809 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9915 22:50:27.423262 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9916 22:50:27.427059 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9917 22:50:27.433142 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9918 22:50:27.436671 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9919 22:50:27.443613 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9920 22:50:27.446554 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9921 22:50:27.453461 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9922 22:50:27.456254 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9923 22:50:27.460015 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9924 22:50:27.465977 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9925 22:50:27.469805 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9926 22:50:27.476268 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9927 22:50:27.479345 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9928 22:50:27.486310 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9929 22:50:27.489400 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9930 22:50:27.495893 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9931 22:50:27.499512 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9932 22:50:27.502823 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9933 22:50:27.509184 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9934 22:50:27.512524 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9935 22:50:27.519325 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9936 22:50:27.522239 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9937 22:50:27.529079 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9938 22:50:27.532517 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9939 22:50:27.535572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9940 22:50:27.542233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9941 22:50:27.545709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9942 22:50:27.551912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9943 22:50:27.555736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9944 22:50:27.562420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9945 22:50:27.565463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9946 22:50:27.571752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9947 22:50:27.575402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9948 22:50:27.581983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9949 22:50:27.585171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9950 22:50:27.591432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9951 22:50:27.594908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9952 22:50:27.601829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9953 22:50:27.605249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9954 22:50:27.611226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9955 22:50:27.614870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9956 22:50:27.621828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9957 22:50:27.624734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9958 22:50:27.631373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9959 22:50:27.635014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9960 22:50:27.640942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9961 22:50:27.644317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9962 22:50:27.650911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9963 22:50:27.654156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9964 22:50:27.661149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9965 22:50:27.664465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9966 22:50:27.670815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9967 22:50:27.673944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9968 22:50:27.680515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9969 22:50:27.684138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9970 22:50:27.690866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9971 22:50:27.693741 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9972 22:50:27.697381 INFO: [APUAPC] vio 0
9973 22:50:27.700810 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9974 22:50:27.707015 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9975 22:50:27.710300 INFO: [APUAPC] D0_APC_0: 0x400510
9976 22:50:27.713555 INFO: [APUAPC] D0_APC_1: 0x0
9977 22:50:27.713629 INFO: [APUAPC] D0_APC_2: 0x1540
9978 22:50:27.716843 INFO: [APUAPC] D0_APC_3: 0x0
9979 22:50:27.720118 INFO: [APUAPC] D1_APC_0: 0xffffffff
9980 22:50:27.723664 INFO: [APUAPC] D1_APC_1: 0xffffffff
9981 22:50:27.727112 INFO: [APUAPC] D1_APC_2: 0x3fffff
9982 22:50:27.730321 INFO: [APUAPC] D1_APC_3: 0x0
9983 22:50:27.733789 INFO: [APUAPC] D2_APC_0: 0xffffffff
9984 22:50:27.736873 INFO: [APUAPC] D2_APC_1: 0xffffffff
9985 22:50:27.740065 INFO: [APUAPC] D2_APC_2: 0x3fffff
9986 22:50:27.743221 INFO: [APUAPC] D2_APC_3: 0x0
9987 22:50:27.746709 INFO: [APUAPC] D3_APC_0: 0xffffffff
9988 22:50:27.750390 INFO: [APUAPC] D3_APC_1: 0xffffffff
9989 22:50:27.753467 INFO: [APUAPC] D3_APC_2: 0x3fffff
9990 22:50:27.756645 INFO: [APUAPC] D3_APC_3: 0x0
9991 22:50:27.760079 INFO: [APUAPC] D4_APC_0: 0xffffffff
9992 22:50:27.763628 INFO: [APUAPC] D4_APC_1: 0xffffffff
9993 22:50:27.766761 INFO: [APUAPC] D4_APC_2: 0x3fffff
9994 22:50:27.769840 INFO: [APUAPC] D4_APC_3: 0x0
9995 22:50:27.773658 INFO: [APUAPC] D5_APC_0: 0xffffffff
9996 22:50:27.776639 INFO: [APUAPC] D5_APC_1: 0xffffffff
9997 22:50:27.780038 INFO: [APUAPC] D5_APC_2: 0x3fffff
9998 22:50:27.783512 INFO: [APUAPC] D5_APC_3: 0x0
9999 22:50:27.786462 INFO: [APUAPC] D6_APC_0: 0xffffffff
10000 22:50:27.790019 INFO: [APUAPC] D6_APC_1: 0xffffffff
10001 22:50:27.793629 INFO: [APUAPC] D6_APC_2: 0x3fffff
10002 22:50:27.796385 INFO: [APUAPC] D6_APC_3: 0x0
10003 22:50:27.799840 INFO: [APUAPC] D7_APC_0: 0xffffffff
10004 22:50:27.803420 INFO: [APUAPC] D7_APC_1: 0xffffffff
10005 22:50:27.806270 INFO: [APUAPC] D7_APC_2: 0x3fffff
10006 22:50:27.809742 INFO: [APUAPC] D7_APC_3: 0x0
10007 22:50:27.813002 INFO: [APUAPC] D8_APC_0: 0xffffffff
10008 22:50:27.816088 INFO: [APUAPC] D8_APC_1: 0xffffffff
10009 22:50:27.819833 INFO: [APUAPC] D8_APC_2: 0x3fffff
10010 22:50:27.823269 INFO: [APUAPC] D8_APC_3: 0x0
10011 22:50:27.826065 INFO: [APUAPC] D9_APC_0: 0xffffffff
10012 22:50:27.829630 INFO: [APUAPC] D9_APC_1: 0xffffffff
10013 22:50:27.832739 INFO: [APUAPC] D9_APC_2: 0x3fffff
10014 22:50:27.835970 INFO: [APUAPC] D9_APC_3: 0x0
10015 22:50:27.839196 INFO: [APUAPC] D10_APC_0: 0xffffffff
10016 22:50:27.842558 INFO: [APUAPC] D10_APC_1: 0xffffffff
10017 22:50:27.845999 INFO: [APUAPC] D10_APC_2: 0x3fffff
10018 22:50:27.849315 INFO: [APUAPC] D10_APC_3: 0x0
10019 22:50:27.852750 INFO: [APUAPC] D11_APC_0: 0xffffffff
10020 22:50:27.856001 INFO: [APUAPC] D11_APC_1: 0xffffffff
10021 22:50:27.859358 INFO: [APUAPC] D11_APC_2: 0x3fffff
10022 22:50:27.862561 INFO: [APUAPC] D11_APC_3: 0x0
10023 22:50:27.865976 INFO: [APUAPC] D12_APC_0: 0xffffffff
10024 22:50:27.869541 INFO: [APUAPC] D12_APC_1: 0xffffffff
10025 22:50:27.872590 INFO: [APUAPC] D12_APC_2: 0x3fffff
10026 22:50:27.876352 INFO: [APUAPC] D12_APC_3: 0x0
10027 22:50:27.879036 INFO: [APUAPC] D13_APC_0: 0xffffffff
10028 22:50:27.886290 INFO: [APUAPC] D13_APC_1: 0xffffffff
10029 22:50:27.886371 INFO: [APUAPC] D13_APC_2: 0x3fffff
10030 22:50:27.889449 INFO: [APUAPC] D13_APC_3: 0x0
10031 22:50:27.892499 INFO: [APUAPC] D14_APC_0: 0xffffffff
10032 22:50:27.895608 INFO: [APUAPC] D14_APC_1: 0xffffffff
10033 22:50:27.898850 INFO: [APUAPC] D14_APC_2: 0x3fffff
10034 22:50:27.902331 INFO: [APUAPC] D14_APC_3: 0x0
10035 22:50:27.905831 INFO: [APUAPC] D15_APC_0: 0xffffffff
10036 22:50:27.909264 INFO: [APUAPC] D15_APC_1: 0xffffffff
10037 22:50:27.912242 INFO: [APUAPC] D15_APC_2: 0x3fffff
10038 22:50:27.915732 INFO: [APUAPC] D15_APC_3: 0x0
10039 22:50:27.919138 INFO: [APUAPC] APC_CON: 0x4
10040 22:50:27.922382 INFO: [NOCDAPC] D0_APC_0: 0x0
10041 22:50:27.925622 INFO: [NOCDAPC] D0_APC_1: 0x0
10042 22:50:27.925703 INFO: [NOCDAPC] D1_APC_0: 0x0
10043 22:50:27.928534 INFO: [NOCDAPC] D1_APC_1: 0xfff
10044 22:50:27.931802 INFO: [NOCDAPC] D2_APC_0: 0x0
10045 22:50:27.935504 INFO: [NOCDAPC] D2_APC_1: 0xfff
10046 22:50:27.938741 INFO: [NOCDAPC] D3_APC_0: 0x0
10047 22:50:27.941920 INFO: [NOCDAPC] D3_APC_1: 0xfff
10048 22:50:27.945672 INFO: [NOCDAPC] D4_APC_0: 0x0
10049 22:50:27.948332 INFO: [NOCDAPC] D4_APC_1: 0xfff
10050 22:50:27.952024 INFO: [NOCDAPC] D5_APC_0: 0x0
10051 22:50:27.955229 INFO: [NOCDAPC] D5_APC_1: 0xfff
10052 22:50:27.958181 INFO: [NOCDAPC] D6_APC_0: 0x0
10053 22:50:27.958262 INFO: [NOCDAPC] D6_APC_1: 0xfff
10054 22:50:27.961567 INFO: [NOCDAPC] D7_APC_0: 0x0
10055 22:50:27.965423 INFO: [NOCDAPC] D7_APC_1: 0xfff
10056 22:50:27.968292 INFO: [NOCDAPC] D8_APC_0: 0x0
10057 22:50:27.971854 INFO: [NOCDAPC] D8_APC_1: 0xfff
10058 22:50:27.974787 INFO: [NOCDAPC] D9_APC_0: 0x0
10059 22:50:27.978439 INFO: [NOCDAPC] D9_APC_1: 0xfff
10060 22:50:27.981934 INFO: [NOCDAPC] D10_APC_0: 0x0
10061 22:50:27.985284 INFO: [NOCDAPC] D10_APC_1: 0xfff
10062 22:50:27.987987 INFO: [NOCDAPC] D11_APC_0: 0x0
10063 22:50:27.991572 INFO: [NOCDAPC] D11_APC_1: 0xfff
10064 22:50:27.994941 INFO: [NOCDAPC] D12_APC_0: 0x0
10065 22:50:27.998278 INFO: [NOCDAPC] D12_APC_1: 0xfff
10066 22:50:28.001611 INFO: [NOCDAPC] D13_APC_0: 0x0
10067 22:50:28.001693 INFO: [NOCDAPC] D13_APC_1: 0xfff
10068 22:50:28.004608 INFO: [NOCDAPC] D14_APC_0: 0x0
10069 22:50:28.008105 INFO: [NOCDAPC] D14_APC_1: 0xfff
10070 22:50:28.011376 INFO: [NOCDAPC] D15_APC_0: 0x0
10071 22:50:28.014929 INFO: [NOCDAPC] D15_APC_1: 0xfff
10072 22:50:28.018428 INFO: [NOCDAPC] APC_CON: 0x4
10073 22:50:28.021283 INFO: [APUAPC] set_apusys_apc done
10074 22:50:28.024148 INFO: [DEVAPC] devapc_init done
10075 22:50:28.027845 INFO: GICv3 without legacy support detected.
10076 22:50:28.034018 INFO: ARM GICv3 driver initialized in EL3
10077 22:50:28.037726 INFO: Maximum SPI INTID supported: 639
10078 22:50:28.040609 INFO: BL31: Initializing runtime services
10079 22:50:28.047283 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10080 22:50:28.047366 INFO: SPM: enable CPC mode
10081 22:50:28.054061 INFO: mcdi ready for mcusys-off-idle and system suspend
10082 22:50:28.057899 INFO: BL31: Preparing for EL3 exit to normal world
10083 22:50:28.064369 INFO: Entry point address = 0x80000000
10084 22:50:28.064451 INFO: SPSR = 0x8
10085 22:50:28.070413
10086 22:50:28.070496
10087 22:50:28.070560
10088 22:50:28.073631 Starting depthcharge on Spherion...
10089 22:50:28.073713
10090 22:50:28.073777 Wipe memory regions:
10091 22:50:28.073837
10092 22:50:28.074459 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10093 22:50:28.074558 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10094 22:50:28.074639 Setting prompt string to ['asurada:']
10095 22:50:28.074717 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10096 22:50:28.077193 [0x00000040000000, 0x00000054600000)
10097 22:50:28.199750
10098 22:50:28.200239 [0x00000054660000, 0x00000080000000)
10099 22:50:28.460270
10100 22:50:28.460751 [0x000000821a7280, 0x000000ffe64000)
10101 22:50:29.204373
10102 22:50:29.204872 [0x00000100000000, 0x00000240000000)
10103 22:50:31.093436
10104 22:50:31.096800 Initializing XHCI USB controller at 0x11200000.
10105 22:50:32.134568
10106 22:50:32.137788 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10107 22:50:32.138227
10108 22:50:32.138555
10109 22:50:32.138862
10110 22:50:32.139600 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10112 22:50:32.240814 asurada: tftpboot 192.168.201.1 13683676/tftp-deploy-mn31krvj/kernel/image.itb 13683676/tftp-deploy-mn31krvj/kernel/cmdline
10113 22:50:32.241442 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10114 22:50:32.241889 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10115 22:50:32.246571 tftpboot 192.168.201.1 13683676/tftp-deploy-mn31krvj/kernel/image.ittp-deploy-mn31krvj/kernel/cmdline
10116 22:50:32.246996
10117 22:50:32.247325 Waiting for link
10118 22:50:32.405066
10119 22:50:32.405627 R8152: Initializing
10120 22:50:32.405968
10121 22:50:32.408148 Version 6 (ocp_data = 5c30)
10122 22:50:32.408563
10123 22:50:32.411531 R8152: Done initializing
10124 22:50:32.411944
10125 22:50:32.412270 Adding net device
10126 22:50:34.265909
10127 22:50:34.266049 done.
10128 22:50:34.266117
10129 22:50:34.266177 MAC: 00:e0:4c:68:02:81
10130 22:50:34.266236
10131 22:50:34.269314 Sending DHCP discover... done.
10132 22:50:34.269435
10133 22:50:34.273052 Waiting for reply... done.
10134 22:50:34.273128
10135 22:50:34.275836 Sending DHCP request... done.
10136 22:50:34.275913
10137 22:50:34.280514 Waiting for reply... done.
10138 22:50:34.280602
10139 22:50:34.280705 My ip is 192.168.201.14
10140 22:50:34.280766
10141 22:50:34.283873 The DHCP server ip is 192.168.201.1
10142 22:50:34.283956
10143 22:50:34.290320 TFTP server IP predefined by user: 192.168.201.1
10144 22:50:34.290406
10145 22:50:34.296773 Bootfile predefined by user: 13683676/tftp-deploy-mn31krvj/kernel/image.itb
10146 22:50:34.296858
10147 22:50:34.300076 Sending tftp read request... done.
10148 22:50:34.300160
10149 22:50:34.304039 Waiting for the transfer...
10150 22:50:34.304122
10151 22:50:34.841206 00000000 ################################################################
10152 22:50:34.841370
10153 22:50:35.379400 00080000 ################################################################
10154 22:50:35.379534
10155 22:50:35.914761 00100000 ################################################################
10156 22:50:35.914902
10157 22:50:36.451313 00180000 ################################################################
10158 22:50:36.451451
10159 22:50:37.000937 00200000 ################################################################
10160 22:50:37.001108
10161 22:50:37.562351 00280000 ################################################################
10162 22:50:37.562500
10163 22:50:38.127710 00300000 ################################################################
10164 22:50:38.127862
10165 22:50:38.678710 00380000 ################################################################
10166 22:50:38.678884
10167 22:50:39.216462 00400000 ################################################################
10168 22:50:39.216604
10169 22:50:39.757191 00480000 ################################################################
10170 22:50:39.757347
10171 22:50:40.300902 00500000 ################################################################
10172 22:50:40.301038
10173 22:50:40.848228 00580000 ################################################################
10174 22:50:40.848465
10175 22:50:41.384352 00600000 ################################################################
10176 22:50:41.384486
10177 22:50:41.929271 00680000 ################################################################
10178 22:50:41.929426
10179 22:50:42.472355 00700000 ################################################################
10180 22:50:42.472490
10181 22:50:43.017095 00780000 ################################################################
10182 22:50:43.017242
10183 22:50:43.553854 00800000 ################################################################
10184 22:50:43.553996
10185 22:50:44.100989 00880000 ################################################################
10186 22:50:44.101138
10187 22:50:44.643119 00900000 ################################################################
10188 22:50:44.643268
10189 22:50:45.183982 00980000 ################################################################
10190 22:50:45.184128
10191 22:50:45.728832 00a00000 ################################################################
10192 22:50:45.729001
10193 22:50:46.263760 00a80000 ################################################################
10194 22:50:46.263902
10195 22:50:46.803490 00b00000 ################################################################
10196 22:50:46.803635
10197 22:50:47.350243 00b80000 ################################################################
10198 22:50:47.350382
10199 22:50:47.903009 00c00000 ################################################################
10200 22:50:47.903152
10201 22:50:48.453876 00c80000 ################################################################
10202 22:50:48.454022
10203 22:50:48.998100 00d00000 ################################################################
10204 22:50:48.998243
10205 22:50:49.621384 00d80000 ################################################################
10206 22:50:49.621912
10207 22:50:50.283319 00e00000 ################################################################
10208 22:50:50.283467
10209 22:50:50.954856 00e80000 ################################################################
10210 22:50:50.955390
10211 22:50:51.637454 00f00000 ################################################################
10212 22:50:51.637591
10213 22:50:52.209316 00f80000 ################################################################
10214 22:50:52.209470
10215 22:50:52.758152 01000000 ################################################################
10216 22:50:52.758294
10217 22:50:53.350529 01080000 ################################################################
10218 22:50:53.350711
10219 22:50:53.953861 01100000 ################################################################
10220 22:50:53.954029
10221 22:50:54.623023 01180000 ################################################################
10222 22:50:54.623188
10223 22:50:55.245600 01200000 ################################################################
10224 22:50:55.246130
10225 22:50:55.952660 01280000 ################################################################
10226 22:50:55.953201
10227 22:50:56.638484 01300000 ################################################################
10228 22:50:56.639133
10229 22:50:57.329428 01380000 ################################################################
10230 22:50:57.329918
10231 22:50:58.026979 01400000 ################################################################
10232 22:50:58.027577
10233 22:50:58.715221 01480000 ################################################################
10234 22:50:58.715804
10235 22:50:59.399109 01500000 ################################################################
10236 22:50:59.399646
10237 22:51:00.101466 01580000 ################################################################
10238 22:51:00.102025
10239 22:51:00.798874 01600000 ################################################################
10240 22:51:00.799386
10241 22:51:01.433288 01680000 ################################################################
10242 22:51:01.433477
10243 22:51:02.122993 01700000 ################################################################
10244 22:51:02.123542
10245 22:51:02.817710 01780000 ################################################################
10246 22:51:02.818246
10247 22:51:03.512339 01800000 ################################################################
10248 22:51:03.512940
10249 22:51:04.174236 01880000 ################################################################
10250 22:51:04.174386
10251 22:51:04.816506 01900000 ################################################################
10252 22:51:04.816651
10253 22:51:05.446705 01980000 ################################################################
10254 22:51:05.446839
10255 22:51:06.035816 01a00000 ################################################################
10256 22:51:06.035954
10257 22:51:06.665829 01a80000 ################################################################
10258 22:51:06.665978
10259 22:51:07.223820 01b00000 ################################################################
10260 22:51:07.223990
10261 22:51:07.820945 01b80000 ################################################################
10262 22:51:07.821096
10263 22:51:08.404768 01c00000 ################################################################
10264 22:51:08.404899
10265 22:51:08.972475 01c80000 ################################################################
10266 22:51:08.972634
10267 22:51:09.538355 01d00000 ################################################################
10268 22:51:09.538489
10269 22:51:10.119653 01d80000 ################################################################
10270 22:51:10.119913
10271 22:51:10.773396 01e00000 ################################################################
10272 22:51:10.773891
10273 22:51:11.393296 01e80000 ################################################################
10274 22:51:11.393452
10275 22:51:11.932713 01f00000 ################################################################
10276 22:51:11.932848
10277 22:51:12.485091 01f80000 ################################################################
10278 22:51:12.485260
10279 22:51:13.038949 02000000 ################################################################
10280 22:51:13.039119
10281 22:51:13.637560 02080000 ################################################################
10282 22:51:13.638057
10283 22:51:14.252447 02100000 ################################################################
10284 22:51:14.252602
10285 22:51:14.787962 02180000 ################################################################
10286 22:51:14.788102
10287 22:51:15.316342 02200000 ################################################################
10288 22:51:15.316503
10289 22:51:15.840241 02280000 ################################################################
10290 22:51:15.840400
10291 22:51:16.381354 02300000 ################################################################
10292 22:51:16.381501
10293 22:51:16.961585 02380000 ################################################################
10294 22:51:16.962123
10295 22:51:17.643632 02400000 ################################################################
10296 22:51:17.644150
10297 22:51:18.335185 02480000 ################################################################
10298 22:51:18.335720
10299 22:51:19.002472 02500000 ################################################################
10300 22:51:19.003037
10301 22:51:19.674923 02580000 ################################################################
10302 22:51:19.675465
10303 22:51:20.322482 02600000 ################################################################
10304 22:51:20.323003
10305 22:51:21.010780 02680000 ################################################################
10306 22:51:21.011475
10307 22:51:21.676711 02700000 ################################################################
10308 22:51:21.677358
10309 22:51:22.267159 02780000 ################################################################
10310 22:51:22.267318
10311 22:51:22.823216 02800000 ################################################################
10312 22:51:22.823361
10313 22:51:23.423535 02880000 ################################################################
10314 22:51:23.423682
10315 22:51:23.983062 02900000 ################################################################
10316 22:51:23.983203
10317 22:51:24.554760 02980000 ################################################################
10318 22:51:24.554906
10319 22:51:25.141142 02a00000 ################################################################
10320 22:51:25.141324
10321 22:51:25.706452 02a80000 ################################################################
10322 22:51:25.706666
10323 22:51:26.315982 02b00000 ################################################################
10324 22:51:26.316503
10325 22:51:26.948365 02b80000 ################################################################
10326 22:51:26.948509
10327 22:51:27.536928 02c00000 ################################################################
10328 22:51:27.537100
10329 22:51:28.095153 02c80000 ################################################################
10330 22:51:28.095301
10331 22:51:28.757540 02d00000 ################################################################
10332 22:51:28.758074
10333 22:51:29.430007 02d80000 ################################################################
10334 22:51:29.430176
10335 22:51:30.012511 02e00000 ################################################################
10336 22:51:30.012669
10337 22:51:30.584692 02e80000 ################################################################
10338 22:51:30.584854
10339 22:51:31.161669 02f00000 ################################################################
10340 22:51:31.161806
10341 22:51:31.736498 02f80000 ################################################################
10342 22:51:31.736636
10343 22:51:32.311162 03000000 ################################################################
10344 22:51:32.311307
10345 22:51:32.874630 03080000 ################################################################
10346 22:51:32.874861
10347 22:51:33.425158 03100000 ################################################################
10348 22:51:33.425295
10349 22:51:33.972028 03180000 ################################################################
10350 22:51:33.972167
10351 22:51:34.520244 03200000 ################################################################
10352 22:51:34.520390
10353 22:51:35.075164 03280000 ################################################################
10354 22:51:35.075318
10355 22:51:35.628037 03300000 ################################################################
10356 22:51:35.628181
10357 22:51:36.182182 03380000 ################################################################
10358 22:51:36.182320
10359 22:51:36.743422 03400000 ################################################################
10360 22:51:36.743560
10361 22:51:37.305445 03480000 ################################################################
10362 22:51:37.305581
10363 22:51:37.866174 03500000 ################################################################
10364 22:51:37.866310
10365 22:51:38.420774 03580000 ################################################################
10366 22:51:38.420923
10367 22:51:38.957718 03600000 ################################################################
10368 22:51:38.957863
10369 22:51:39.507010 03680000 ################################################################
10370 22:51:39.507210
10371 22:51:40.051211 03700000 ################################################################
10372 22:51:40.051357
10373 22:51:40.642431 03780000 ################################################################
10374 22:51:40.642879
10375 22:51:41.199827 03800000 ################################################################
10376 22:51:41.200002
10377 22:51:41.732067 03880000 ################################################################
10378 22:51:41.732250
10379 22:51:42.301647 03900000 ################################################################
10380 22:51:42.301789
10381 22:51:42.863502 03980000 ################################################################
10382 22:51:42.863645
10383 22:51:43.427458 03a00000 ################################################################
10384 22:51:43.427597
10385 22:51:43.959216 03a80000 ################################################################
10386 22:51:43.959363
10387 22:51:44.506544 03b00000 ################################################################
10388 22:51:44.506676
10389 22:51:45.072457 03b80000 ################################################################
10390 22:51:45.072618
10391 22:51:45.637081 03c00000 ################################################################
10392 22:51:45.637218
10393 22:51:46.199363 03c80000 ################################################################
10394 22:51:46.199523
10395 22:51:46.757418 03d00000 ################################################################
10396 22:51:46.757552
10397 22:51:47.297878 03d80000 ################################################################
10398 22:51:47.298024
10399 22:51:47.841939 03e00000 ################################################################
10400 22:51:47.842100
10401 22:51:48.396492 03e80000 ################################################################
10402 22:51:48.396650
10403 22:51:48.949751 03f00000 ################################################################
10404 22:51:48.949887
10405 22:51:49.510584 03f80000 ################################################################
10406 22:51:49.510723
10407 22:51:50.049016 04000000 ################################################################
10408 22:51:50.049159
10409 22:51:50.603140 04080000 ################################################################
10410 22:51:50.603314
10411 22:51:51.165681 04100000 ################################################################
10412 22:51:51.165881
10413 22:51:51.726189 04180000 ################################################################
10414 22:51:51.726328
10415 22:51:52.290620 04200000 ################################################################
10416 22:51:52.290770
10417 22:51:52.840336 04280000 ################################################################
10418 22:51:52.840483
10419 22:51:53.405626 04300000 ################################################################
10420 22:51:53.405823
10421 22:51:53.969380 04380000 ################################################################
10422 22:51:53.969556
10423 22:51:54.535955 04400000 ################################################################
10424 22:51:54.536108
10425 22:51:55.114557 04480000 ################################################################
10426 22:51:55.114712
10427 22:51:55.695002 04500000 ################################################################
10428 22:51:55.695158
10429 22:51:56.257964 04580000 ################################################################
10430 22:51:56.258126
10431 22:51:56.838489 04600000 ################################################################
10432 22:51:56.838643
10433 22:51:57.044273 04680000 ###################### done.
10434 22:51:57.044423
10435 22:51:57.047422 The bootfile was 74101778 bytes long.
10436 22:51:57.047513
10437 22:51:57.050815 Sending tftp read request... done.
10438 22:51:57.050904
10439 22:51:57.050968 Waiting for the transfer...
10440 22:51:57.054090
10441 22:51:57.054177 00000000 # done.
10442 22:51:57.054246
10443 22:51:57.060507 Command line loaded dynamically from TFTP file: 13683676/tftp-deploy-mn31krvj/kernel/cmdline
10444 22:51:57.060606
10445 22:51:57.074096 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10446 22:51:57.076796
10447 22:51:57.076894 Loading FIT.
10448 22:51:57.076959
10449 22:51:57.080047 Image ramdisk-1 has 60992931 bytes.
10450 22:51:57.080134
10451 22:51:57.083484 Image fdt-1 has 47258 bytes.
10452 22:51:57.083588
10453 22:51:57.087145 Image kernel-1 has 13059555 bytes.
10454 22:51:57.087239
10455 22:51:57.093577 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10456 22:51:57.093681
10457 22:51:57.112909 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10458 22:51:57.113063
10459 22:51:57.116026 Choosing best match conf-1 for compat google,spherion-rev2.
10460 22:51:57.121057
10461 22:51:57.146889 Connected to device vid:did:rid of 1ae0:0028:00
10462 22:51:57.167230
10463 22:51:57.170799 tpm_get_response: command 0x17b, return code 0x0
10464 22:51:57.170896
10465 22:51:57.174162 ec_init: CrosEC protocol v3 supported (256, 248)
10466 22:51:57.179125
10467 22:51:57.181916 tpm_cleanup: add release locality here.
10468 22:51:57.182009
10469 22:51:57.182073 Shutting down all USB controllers.
10470 22:51:57.185457
10471 22:51:57.185547 Removing current net device
10472 22:51:57.185613
10473 22:51:57.192089 Exiting depthcharge with code 4 at timestamp: 118604568
10474 22:51:57.192194
10475 22:51:57.195273 LZMA decompressing kernel-1 to 0x821a6718
10476 22:51:57.195360
10477 22:51:57.198249 LZMA decompressing kernel-1 to 0x40000000
10478 22:51:58.810266
10479 22:51:58.810415 jumping to kernel
10480 22:51:58.810946 end: 2.2.4 bootloader-commands (duration 00:01:31) [common]
10481 22:51:58.811047 start: 2.2.5 auto-login-action (timeout 00:02:56) [common]
10482 22:51:58.811123 Setting prompt string to ['Linux version [0-9]']
10483 22:51:58.811192 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10484 22:51:58.811258 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10485 22:51:58.892350
10486 22:51:58.895485 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10487 22:51:58.898844 start: 2.2.5.1 login-action (timeout 00:02:56) [common]
10488 22:51:58.898965 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10489 22:51:58.899038 Setting prompt string to []
10490 22:51:58.899118 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10491 22:51:58.899192 Using line separator: #'\n'#
10492 22:51:58.899250 No login prompt set.
10493 22:51:58.899310 Parsing kernel messages
10494 22:51:58.899364 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10495 22:51:58.899464 [login-action] Waiting for messages, (timeout 00:02:56)
10496 22:51:58.899528 Waiting using forced prompt support (timeout 00:01:28)
10497 22:51:58.918688 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10498 22:51:58.922278 [ 0.000000] random: crng init done
10499 22:51:58.928578 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10500 22:51:58.931518 [ 0.000000] efi: UEFI not found.
10501 22:51:58.938041 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10502 22:51:58.948208 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10503 22:51:58.958150 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10504 22:51:58.964596 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10505 22:51:58.971248 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10506 22:51:58.977442 [ 0.000000] printk: bootconsole [mtk8250] enabled
10507 22:51:58.983996 [ 0.000000] NUMA: No NUMA configuration found
10508 22:51:58.990799 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10509 22:51:58.997304 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10510 22:51:58.997491 [ 0.000000] Zone ranges:
10511 22:51:59.004073 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10512 22:51:59.007087 [ 0.000000] DMA32 empty
10513 22:51:59.013747 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10514 22:51:59.016990 [ 0.000000] Movable zone start for each node
10515 22:51:59.020625 [ 0.000000] Early memory node ranges
10516 22:51:59.027388 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10517 22:51:59.033275 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10518 22:51:59.040158 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10519 22:51:59.046749 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10520 22:51:59.053265 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10521 22:51:59.059756 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10522 22:51:59.117271 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10523 22:51:59.123489 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10524 22:51:59.130593 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10525 22:51:59.133016 [ 0.000000] psci: probing for conduit method from DT.
10526 22:51:59.140078 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10527 22:51:59.143219 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10528 22:51:59.150146 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10529 22:51:59.153501 [ 0.000000] psci: SMC Calling Convention v1.2
10530 22:51:59.160216 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10531 22:51:59.162731 [ 0.000000] Detected VIPT I-cache on CPU0
10532 22:51:59.170636 [ 0.000000] CPU features: detected: GIC system register CPU interface
10533 22:51:59.175929 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10534 22:51:59.182454 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10535 22:51:59.189172 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10536 22:51:59.199276 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10537 22:51:59.205646 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10538 22:51:59.208876 [ 0.000000] alternatives: applying boot alternatives
10539 22:51:59.215968 [ 0.000000] Fallback order for Node 0: 0
10540 22:51:59.223134 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10541 22:51:59.225672 [ 0.000000] Policy zone: Normal
10542 22:51:59.238846 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10543 22:51:59.248499 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10544 22:51:59.261056 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10545 22:51:59.271262 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10546 22:51:59.277505 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10547 22:51:59.281090 <6>[ 0.000000] software IO TLB: area num 8.
10548 22:51:59.338079 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10549 22:51:59.487375 <6>[ 0.000000] Memory: 7904628K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 448140K reserved, 32768K cma-reserved)
10550 22:51:59.493622 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10551 22:51:59.500292 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10552 22:51:59.503770 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10553 22:51:59.510548 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10554 22:51:59.516937 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10555 22:51:59.520457 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10556 22:51:59.530269 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10557 22:51:59.536833 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10558 22:51:59.543117 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10559 22:51:59.550009 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10560 22:51:59.553479 <6>[ 0.000000] GICv3: 608 SPIs implemented
10561 22:51:59.556325 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10562 22:51:59.563216 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10563 22:51:59.566209 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10564 22:51:59.572602 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10565 22:51:59.586369 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10566 22:51:59.598986 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10567 22:51:59.605741 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10568 22:51:59.614016 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10569 22:51:59.626838 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10570 22:51:59.633682 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10571 22:51:59.640537 <6>[ 0.009184] Console: colour dummy device 80x25
10572 22:51:59.650291 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10573 22:51:59.656579 <6>[ 0.024409] pid_max: default: 32768 minimum: 301
10574 22:51:59.660724 <6>[ 0.029281] LSM: Security Framework initializing
10575 22:51:59.666574 <6>[ 0.034249] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10576 22:51:59.676643 <6>[ 0.042062] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10577 22:51:59.686441 <6>[ 0.051493] cblist_init_generic: Setting adjustable number of callback queues.
10578 22:51:59.692772 <6>[ 0.058938] cblist_init_generic: Setting shift to 3 and lim to 1.
10579 22:51:59.699610 <6>[ 0.065277] cblist_init_generic: Setting adjustable number of callback queues.
10580 22:51:59.705951 <6>[ 0.072750] cblist_init_generic: Setting shift to 3 and lim to 1.
10581 22:51:59.709725 <6>[ 0.079154] rcu: Hierarchical SRCU implementation.
10582 22:51:59.715995 <6>[ 0.084170] rcu: Max phase no-delay instances is 1000.
10583 22:51:59.722285 <6>[ 0.091227] EFI services will not be available.
10584 22:51:59.725906 <6>[ 0.096215] smp: Bringing up secondary CPUs ...
10585 22:51:59.734599 <6>[ 0.101267] Detected VIPT I-cache on CPU1
10586 22:51:59.741215 <6>[ 0.101338] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10587 22:51:59.747896 <6>[ 0.101369] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10588 22:51:59.751026 <6>[ 0.101702] Detected VIPT I-cache on CPU2
10589 22:51:59.760760 <6>[ 0.101751] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10590 22:51:59.768235 <6>[ 0.101766] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10591 22:51:59.770941 <6>[ 0.102021] Detected VIPT I-cache on CPU3
10592 22:51:59.777727 <6>[ 0.102067] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10593 22:51:59.784726 <6>[ 0.102081] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10594 22:51:59.790564 <6>[ 0.102385] CPU features: detected: Spectre-v4
10595 22:51:59.793917 <6>[ 0.102391] CPU features: detected: Spectre-BHB
10596 22:51:59.797349 <6>[ 0.102396] Detected PIPT I-cache on CPU4
10597 22:51:59.804407 <6>[ 0.102454] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10598 22:51:59.811013 <6>[ 0.102471] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10599 22:51:59.817126 <6>[ 0.102765] Detected PIPT I-cache on CPU5
10600 22:51:59.823869 <6>[ 0.102828] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10601 22:51:59.829940 <6>[ 0.102844] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10602 22:51:59.833602 <6>[ 0.103126] Detected PIPT I-cache on CPU6
10603 22:51:59.843580 <6>[ 0.103192] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10604 22:51:59.850083 <6>[ 0.103208] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10605 22:51:59.852831 <6>[ 0.103505] Detected PIPT I-cache on CPU7
10606 22:51:59.859449 <6>[ 0.103571] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10607 22:51:59.866110 <6>[ 0.103587] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10608 22:51:59.869273 <6>[ 0.103634] smp: Brought up 1 node, 8 CPUs
10609 22:51:59.876120 <6>[ 0.244916] SMP: Total of 8 processors activated.
10610 22:51:59.882833 <6>[ 0.249837] CPU features: detected: 32-bit EL0 Support
10611 22:51:59.889247 <6>[ 0.255200] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10612 22:51:59.895639 <6>[ 0.264001] CPU features: detected: Common not Private translations
10613 22:51:59.902299 <6>[ 0.270477] CPU features: detected: CRC32 instructions
10614 22:51:59.908984 <6>[ 0.275828] CPU features: detected: RCpc load-acquire (LDAPR)
10615 22:51:59.912427 <6>[ 0.281788] CPU features: detected: LSE atomic instructions
10616 22:51:59.918579 <6>[ 0.287570] CPU features: detected: Privileged Access Never
10617 22:51:59.925795 <6>[ 0.293349] CPU features: detected: RAS Extension Support
10618 22:51:59.932335 <6>[ 0.298958] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10619 22:51:59.935117 <6>[ 0.306179] CPU: All CPU(s) started at EL2
10620 22:51:59.941777 <6>[ 0.310522] alternatives: applying system-wide alternatives
10621 22:51:59.952505 <6>[ 0.321357] devtmpfs: initialized
10622 22:51:59.967977 <6>[ 0.330356] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10623 22:51:59.974804 <6>[ 0.340318] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10624 22:51:59.980922 <6>[ 0.348523] pinctrl core: initialized pinctrl subsystem
10625 22:51:59.984464 <6>[ 0.355177] DMI not present or invalid.
10626 22:51:59.990896 <6>[ 0.359587] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10627 22:52:00.000853 <6>[ 0.366344] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10628 22:52:00.007557 <6>[ 0.373932] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10629 22:52:00.017321 <6>[ 0.382161] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10630 22:52:00.020402 <6>[ 0.390403] audit: initializing netlink subsys (disabled)
10631 22:52:00.030411 <5>[ 0.396093] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10632 22:52:00.037010 <6>[ 0.396797] thermal_sys: Registered thermal governor 'step_wise'
10633 22:52:00.043673 <6>[ 0.404060] thermal_sys: Registered thermal governor 'power_allocator'
10634 22:52:00.046961 <6>[ 0.410317] cpuidle: using governor menu
10635 22:52:00.053604 <6>[ 0.421278] NET: Registered PF_QIPCRTR protocol family
10636 22:52:00.059977 <6>[ 0.426754] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10637 22:52:00.066977 <6>[ 0.433857] ASID allocator initialised with 32768 entries
10638 22:52:00.070117 <6>[ 0.440431] Serial: AMBA PL011 UART driver
10639 22:52:00.079997 <4>[ 0.449147] Trying to register duplicate clock ID: 134
10640 22:52:00.140066 <6>[ 0.512271] KASLR enabled
10641 22:52:00.154303 <6>[ 0.520014] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10642 22:52:00.161321 <6>[ 0.527025] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10643 22:52:00.167544 <6>[ 0.533514] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10644 22:52:00.174460 <6>[ 0.540517] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10645 22:52:00.181072 <6>[ 0.547006] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10646 22:52:00.187161 <6>[ 0.554011] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10647 22:52:00.193692 <6>[ 0.560499] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10648 22:52:00.200672 <6>[ 0.567505] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10649 22:52:00.203679 <6>[ 0.574966] ACPI: Interpreter disabled.
10650 22:52:00.212486 <6>[ 0.581382] iommu: Default domain type: Translated
10651 22:52:00.219267 <6>[ 0.586532] iommu: DMA domain TLB invalidation policy: strict mode
10652 22:52:00.222334 <5>[ 0.593192] SCSI subsystem initialized
10653 22:52:00.228799 <6>[ 0.597442] usbcore: registered new interface driver usbfs
10654 22:52:00.235647 <6>[ 0.603173] usbcore: registered new interface driver hub
10655 22:52:00.238921 <6>[ 0.608725] usbcore: registered new device driver usb
10656 22:52:00.245716 <6>[ 0.614834] pps_core: LinuxPPS API ver. 1 registered
10657 22:52:00.255608 <6>[ 0.620028] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10658 22:52:00.259091 <6>[ 0.629371] PTP clock support registered
10659 22:52:00.262110 <6>[ 0.633614] EDAC MC: Ver: 3.0.0
10660 22:52:00.270073 <6>[ 0.638795] FPGA manager framework
10661 22:52:00.272981 <6>[ 0.642473] Advanced Linux Sound Architecture Driver Initialized.
10662 22:52:00.277078 <6>[ 0.649253] vgaarb: loaded
10663 22:52:00.283619 <6>[ 0.652409] clocksource: Switched to clocksource arch_sys_counter
10664 22:52:00.290420 <5>[ 0.658862] VFS: Disk quotas dquot_6.6.0
10665 22:52:00.296829 <6>[ 0.663047] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10666 22:52:00.300197 <6>[ 0.670239] pnp: PnP ACPI: disabled
10667 22:52:00.308007 <6>[ 0.676981] NET: Registered PF_INET protocol family
10668 22:52:00.318290 <6>[ 0.682583] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10669 22:52:00.329236 <6>[ 0.694920] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10670 22:52:00.339482 <6>[ 0.703736] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10671 22:52:00.345724 <6>[ 0.711708] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10672 22:52:00.355614 <6>[ 0.720413] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10673 22:52:00.362024 <6>[ 0.730157] TCP: Hash tables configured (established 65536 bind 65536)
10674 22:52:00.368423 <6>[ 0.737025] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10675 22:52:00.378631 <6>[ 0.744224] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10676 22:52:00.385195 <6>[ 0.751927] NET: Registered PF_UNIX/PF_LOCAL protocol family
10677 22:52:00.391643 <6>[ 0.758076] RPC: Registered named UNIX socket transport module.
10678 22:52:00.394855 <6>[ 0.764229] RPC: Registered udp transport module.
10679 22:52:00.401523 <6>[ 0.769163] RPC: Registered tcp transport module.
10680 22:52:00.408567 <6>[ 0.774097] RPC: Registered tcp NFSv4.1 backchannel transport module.
10681 22:52:00.412023 <6>[ 0.780762] PCI: CLS 0 bytes, default 64
10682 22:52:00.414751 <6>[ 0.785052] Unpacking initramfs...
10683 22:52:00.424687 <6>[ 0.788769] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10684 22:52:00.431477 <6>[ 0.797429] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10685 22:52:00.438127 <6>[ 0.806279] kvm [1]: IPA Size Limit: 40 bits
10686 22:52:00.441052 <6>[ 0.810818] kvm [1]: GICv3: no GICV resource entry
10687 22:52:00.448158 <6>[ 0.815839] kvm [1]: disabling GICv2 emulation
10688 22:52:00.451120 <6>[ 0.820529] kvm [1]: GIC system register CPU interface enabled
10689 22:52:00.457846 <6>[ 0.826705] kvm [1]: vgic interrupt IRQ18
10690 22:52:00.464635 <6>[ 0.832478] kvm [1]: VHE mode initialized successfully
10691 22:52:00.471271 <5>[ 0.838884] Initialise system trusted keyrings
10692 22:52:00.477638 <6>[ 0.843677] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10693 22:52:00.484981 <6>[ 0.853774] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10694 22:52:00.491313 <5>[ 0.860148] NFS: Registering the id_resolver key type
10695 22:52:00.495029 <5>[ 0.865458] Key type id_resolver registered
10696 22:52:00.501309 <5>[ 0.869876] Key type id_legacy registered
10697 22:52:00.508009 <6>[ 0.874156] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10698 22:52:00.514278 <6>[ 0.881080] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10699 22:52:00.521035 <6>[ 0.888779] 9p: Installing v9fs 9p2000 file system support
10700 22:52:00.558037 <5>[ 0.926730] Key type asymmetric registered
10701 22:52:00.561198 <5>[ 0.931061] Asymmetric key parser 'x509' registered
10702 22:52:00.570893 <6>[ 0.936199] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10703 22:52:00.574312 <6>[ 0.943822] io scheduler mq-deadline registered
10704 22:52:00.578100 <6>[ 0.948582] io scheduler kyber registered
10705 22:52:00.597259 <6>[ 0.965622] EINJ: ACPI disabled.
10706 22:52:00.629574 <4>[ 0.991783] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10707 22:52:00.638926 <4>[ 1.002406] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10708 22:52:00.654111 <6>[ 1.023244] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10709 22:52:00.661964 <6>[ 1.031196] printk: console [ttyS0] disabled
10710 22:52:00.690148 <6>[ 1.055828] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10711 22:52:00.696695 <6>[ 1.065301] printk: console [ttyS0] enabled
10712 22:52:00.700077 <6>[ 1.065301] printk: console [ttyS0] enabled
10713 22:52:00.706791 <6>[ 1.074194] printk: bootconsole [mtk8250] disabled
10714 22:52:00.709811 <6>[ 1.074194] printk: bootconsole [mtk8250] disabled
10715 22:52:00.716762 <6>[ 1.085257] SuperH (H)SCI(F) driver initialized
10716 22:52:00.719775 <6>[ 1.090525] msm_serial: driver initialized
10717 22:52:00.734260 <6>[ 1.099426] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10718 22:52:00.743814 <6>[ 1.107979] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10719 22:52:00.750176 <6>[ 1.116520] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10720 22:52:00.760537 <6>[ 1.125148] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10721 22:52:00.769845 <6>[ 1.133855] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10722 22:52:00.776886 <6>[ 1.142569] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10723 22:52:00.786993 <6>[ 1.151108] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10724 22:52:00.793308 <6>[ 1.159899] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10725 22:52:00.803405 <6>[ 1.168441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10726 22:52:00.814834 <6>[ 1.184060] loop: module loaded
10727 22:52:00.821357 <6>[ 1.189874] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10728 22:52:00.844583 <4>[ 1.213214] mtk-pmic-keys: Failed to locate of_node [id: -1]
10729 22:52:00.851068 <6>[ 1.219997] megasas: 07.719.03.00-rc1
10730 22:52:00.860730 <6>[ 1.229615] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10731 22:52:00.867459 <6>[ 1.235794] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10732 22:52:00.882600 <6>[ 1.251708] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10733 22:52:00.942091 <6>[ 1.304735] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10734 22:52:03.097646 <6>[ 3.466690] Freeing initrd memory: 59556K
10735 22:52:03.109053 <6>[ 3.478292] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10736 22:52:03.120133 <6>[ 3.489433] tun: Universal TUN/TAP device driver, 1.6
10737 22:52:03.123460 <6>[ 3.495507] thunder_xcv, ver 1.0
10738 22:52:03.126601 <6>[ 3.499011] thunder_bgx, ver 1.0
10739 22:52:03.130185 <6>[ 3.502509] nicpf, ver 1.0
10740 22:52:03.140565 <6>[ 3.506534] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10741 22:52:03.144033 <6>[ 3.514011] hns3: Copyright (c) 2017 Huawei Corporation.
10742 22:52:03.150410 <6>[ 3.519599] hclge is initializing
10743 22:52:03.154088 <6>[ 3.523180] e1000: Intel(R) PRO/1000 Network Driver
10744 22:52:03.160287 <6>[ 3.528310] e1000: Copyright (c) 1999-2006 Intel Corporation.
10745 22:52:03.163586 <6>[ 3.534325] e1000e: Intel(R) PRO/1000 Network Driver
10746 22:52:03.170240 <6>[ 3.539540] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10747 22:52:03.176862 <6>[ 3.545725] igb: Intel(R) Gigabit Ethernet Network Driver
10748 22:52:03.183239 <6>[ 3.551374] igb: Copyright (c) 2007-2014 Intel Corporation.
10749 22:52:03.190249 <6>[ 3.557210] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10750 22:52:03.196726 <6>[ 3.563727] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10751 22:52:03.199923 <6>[ 3.570192] sky2: driver version 1.30
10752 22:52:03.206912 <6>[ 3.575124] usbcore: registered new device driver r8152-cfgselector
10753 22:52:03.213292 <6>[ 3.581664] usbcore: registered new interface driver r8152
10754 22:52:03.219871 <6>[ 3.587480] VFIO - User Level meta-driver version: 0.3
10755 22:52:03.226533 <6>[ 3.595738] usbcore: registered new interface driver usb-storage
10756 22:52:03.233110 <6>[ 3.602189] usbcore: registered new device driver onboard-usb-hub
10757 22:52:03.241850 <6>[ 3.611348] mt6397-rtc mt6359-rtc: registered as rtc0
10758 22:52:03.252173 <6>[ 3.616811] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:52:03 UTC (1715122323)
10759 22:52:03.255157 <6>[ 3.626375] i2c_dev: i2c /dev entries driver
10760 22:52:03.272381 <6>[ 3.638244] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10761 22:52:03.279344 <4>[ 3.646970] cpu cpu0: supply cpu not found, using dummy regulator
10762 22:52:03.285553 <4>[ 3.653391] cpu cpu1: supply cpu not found, using dummy regulator
10763 22:52:03.291974 <4>[ 3.659811] cpu cpu2: supply cpu not found, using dummy regulator
10764 22:52:03.298483 <4>[ 3.666213] cpu cpu3: supply cpu not found, using dummy regulator
10765 22:52:03.305289 <4>[ 3.672614] cpu cpu4: supply cpu not found, using dummy regulator
10766 22:52:03.311600 <4>[ 3.679012] cpu cpu5: supply cpu not found, using dummy regulator
10767 22:52:03.318605 <4>[ 3.685409] cpu cpu6: supply cpu not found, using dummy regulator
10768 22:52:03.325030 <4>[ 3.691822] cpu cpu7: supply cpu not found, using dummy regulator
10769 22:52:03.344176 <6>[ 3.713474] cpu cpu0: EM: created perf domain
10770 22:52:03.347744 <6>[ 3.718396] cpu cpu4: EM: created perf domain
10771 22:52:03.354548 <6>[ 3.724052] sdhci: Secure Digital Host Controller Interface driver
10772 22:52:03.361611 <6>[ 3.730484] sdhci: Copyright(c) Pierre Ossman
10773 22:52:03.368129 <6>[ 3.735446] Synopsys Designware Multimedia Card Interface Driver
10774 22:52:03.375182 <6>[ 3.742083] sdhci-pltfm: SDHCI platform and OF driver helper
10775 22:52:03.377752 <6>[ 3.742128] mmc0: CQHCI version 5.10
10776 22:52:03.384530 <6>[ 3.751995] ledtrig-cpu: registered to indicate activity on CPUs
10777 22:52:03.390848 <6>[ 3.759064] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10778 22:52:03.397799 <6>[ 3.766131] usbcore: registered new interface driver usbhid
10779 22:52:03.401185 <6>[ 3.771953] usbhid: USB HID core driver
10780 22:52:03.407900 <6>[ 3.776150] spi_master spi0: will run message pump with realtime priority
10781 22:52:03.452410 <6>[ 3.815143] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10782 22:52:03.472434 <6>[ 3.830928] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10783 22:52:03.475220 <6>[ 3.845932] mmc0: Command Queue Engine enabled
10784 22:52:03.481800 <6>[ 3.847128] cros-ec-spi spi0.0: Chrome EC device registered
10785 22:52:03.488717 <6>[ 3.850667] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10786 22:52:03.495351 <6>[ 3.863723] mmcblk0: mmc0:0001 DA4128 116 GiB
10787 22:52:03.505186 <6>[ 3.870733] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10788 22:52:03.512010 <6>[ 3.879492] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10789 22:52:03.518435 <6>[ 3.881190] NET: Registered PF_PACKET protocol family
10790 22:52:03.521965 <6>[ 3.886806] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10791 22:52:03.528186 <6>[ 3.891341] 9pnet: Installing 9P2000 support
10792 22:52:03.532028 <6>[ 3.897086] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10793 22:52:03.535325 <5>[ 3.901028] Key type dns_resolver registered
10794 22:52:03.541231 <6>[ 3.906756] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10795 22:52:03.547850 <6>[ 3.911223] registered taskstats version 1
10796 22:52:03.551260 <5>[ 3.921646] Loading compiled-in X.509 certificates
10797 22:52:03.582864 <4>[ 3.945014] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10798 22:52:03.592506 <4>[ 3.955706] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10799 22:52:03.599196 <3>[ 3.966235] debugfs: File 'uA_load' in directory '/' already present!
10800 22:52:03.605553 <3>[ 3.972933] debugfs: File 'min_uV' in directory '/' already present!
10801 22:52:03.612066 <3>[ 3.979595] debugfs: File 'max_uV' in directory '/' already present!
10802 22:52:03.618621 <3>[ 3.986209] debugfs: File 'constraint_flags' in directory '/' already present!
10803 22:52:03.632469 <6>[ 4.001863] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10804 22:52:03.639826 <6>[ 4.009011] xhci-mtk 11200000.usb: xHCI Host Controller
10805 22:52:03.646200 <6>[ 4.014502] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10806 22:52:03.656203 <6>[ 4.022346] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10807 22:52:03.662919 <6>[ 4.031776] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10808 22:52:03.669508 <6>[ 4.037851] xhci-mtk 11200000.usb: xHCI Host Controller
10809 22:52:03.676231 <6>[ 4.043332] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10810 22:52:03.682751 <6>[ 4.050980] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10811 22:52:03.689113 <6>[ 4.058671] hub 1-0:1.0: USB hub found
10812 22:52:03.692931 <6>[ 4.062687] hub 1-0:1.0: 1 port detected
10813 22:52:03.702565 <6>[ 4.066967] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10814 22:52:03.705819 <6>[ 4.075533] hub 2-0:1.0: USB hub found
10815 22:52:03.709383 <6>[ 4.079553] hub 2-0:1.0: 1 port detected
10816 22:52:03.718656 <6>[ 4.088053] mtk-msdc 11f70000.mmc: Got CD GPIO
10817 22:52:03.729945 <6>[ 4.096062] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10818 22:52:03.736649 <6>[ 4.104111] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10819 22:52:03.746675 <4>[ 4.112035] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10820 22:52:03.756330 <6>[ 4.121563] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10821 22:52:03.762866 <6>[ 4.129640] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10822 22:52:03.770124 <6>[ 4.137661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10823 22:52:03.779527 <6>[ 4.145586] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10824 22:52:03.785991 <6>[ 4.153402] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10825 22:52:03.795764 <6>[ 4.161218] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10826 22:52:03.806021 <6>[ 4.171398] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10827 22:52:03.812712 <6>[ 4.179760] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10828 22:52:03.822701 <6>[ 4.188108] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10829 22:52:03.829215 <6>[ 4.196446] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10830 22:52:03.839072 <6>[ 4.204783] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10831 22:52:03.845670 <6>[ 4.213123] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10832 22:52:03.855510 <6>[ 4.221460] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10833 22:52:03.865524 <6>[ 4.229797] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10834 22:52:03.872025 <6>[ 4.238135] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10835 22:52:03.881916 <6>[ 4.246475] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10836 22:52:03.888671 <6>[ 4.254826] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10837 22:52:03.898665 <6>[ 4.263164] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10838 22:52:03.905188 <6>[ 4.271502] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10839 22:52:03.914732 <6>[ 4.279839] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10840 22:52:03.921321 <6>[ 4.288177] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10841 22:52:03.928229 <6>[ 4.296943] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10842 22:52:03.934736 <6>[ 4.304124] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10843 22:52:03.941617 <6>[ 4.311002] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10844 22:52:03.951999 <6>[ 4.317852] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10845 22:52:03.958257 <6>[ 4.324865] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10846 22:52:03.964944 <6>[ 4.331723] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10847 22:52:03.975211 <6>[ 4.340853] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10848 22:52:03.985007 <6>[ 4.349972] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10849 22:52:03.994779 <6>[ 4.359265] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10850 22:52:04.004864 <6>[ 4.368732] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10851 22:52:04.014759 <6>[ 4.378199] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10852 22:52:04.021077 <6>[ 4.387320] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10853 22:52:04.031580 <6>[ 4.396788] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10854 22:52:04.041156 <6>[ 4.405907] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10855 22:52:04.050839 <6>[ 4.415202] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10856 22:52:04.060630 <6>[ 4.425363] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10857 22:52:04.070754 <6>[ 4.436893] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10858 22:52:04.122449 <6>[ 4.488561] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10859 22:52:04.277887 <6>[ 4.646790] hub 1-1:1.0: USB hub found
10860 22:52:04.280752 <6>[ 4.651314] hub 1-1:1.0: 4 ports detected
10861 22:52:04.290884 <6>[ 4.659984] hub 1-1:1.0: USB hub found
10862 22:52:04.293761 <6>[ 4.664324] hub 1-1:1.0: 4 ports detected
10863 22:52:04.402803 <6>[ 4.769038] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10864 22:52:04.429046 <6>[ 4.798302] hub 2-1:1.0: USB hub found
10865 22:52:04.432407 <6>[ 4.802798] hub 2-1:1.0: 3 ports detected
10866 22:52:04.441723 <6>[ 4.810863] hub 2-1:1.0: USB hub found
10867 22:52:04.444979 <6>[ 4.815307] hub 2-1:1.0: 3 ports detected
10868 22:52:04.618821 <6>[ 4.984777] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10869 22:52:04.750874 <6>[ 5.120381] hub 1-1.4:1.0: USB hub found
10870 22:52:04.754327 <6>[ 5.125047] hub 1-1.4:1.0: 2 ports detected
10871 22:52:04.764362 <6>[ 5.133635] hub 1-1.4:1.0: USB hub found
10872 22:52:04.767433 <6>[ 5.138251] hub 1-1.4:1.0: 2 ports detected
10873 22:52:04.834787 <6>[ 5.200912] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10874 22:52:04.943137 <6>[ 5.309362] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10875 22:52:04.979330 <4>[ 5.345472] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10876 22:52:04.988963 <4>[ 5.354565] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10877 22:52:05.024983 <6>[ 5.394638] r8152 2-1.3:1.0 eth0: v1.12.13
10878 22:52:05.066479 <6>[ 5.432681] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10879 22:52:05.258870 <6>[ 5.624742] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10880 22:52:06.698906 <6>[ 7.068673] r8152 2-1.3:1.0 eth0: carrier on
10881 22:52:09.278470 <5>[ 7.096724] Sending DHCP requests .., OK
10882 22:52:09.285427 <6>[ 9.652801] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10883 22:52:09.288808 <6>[ 9.661132] IP-Config: Complete:
10884 22:52:09.301500 <6>[ 9.664633] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10885 22:52:09.308290 <6>[ 9.675355] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10886 22:52:09.314821 <6>[ 9.683974] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10887 22:52:09.321261 <6>[ 9.683983] nameserver0=192.168.201.1
10888 22:52:09.324965 <6>[ 9.696173] clk: Disabling unused clocks
10889 22:52:09.328647 <6>[ 9.701553] ALSA device list:
10890 22:52:09.334696 <6>[ 9.704875] No soundcards found.
10891 22:52:09.341725 <6>[ 9.711581] Freeing unused kernel memory: 8512K
10892 22:52:09.344784 <6>[ 9.716617] Run /init as init process
10893 22:52:09.373064 <6>[ 9.743034] NET: Registered PF_INET6 protocol family
10894 22:52:09.379643 <6>[ 9.749517] Segment Routing with IPv6
10895 22:52:09.382756 <6>[ 9.753475] In-situ OAM (IOAM) with IPv6
10896 22:52:09.425967 <30>[ 9.769405] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10897 22:52:09.432461 <30>[ 9.802442] systemd[1]: Detected architecture arm64.
10898 22:52:09.432566
10899 22:52:09.439154 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10900 22:52:09.439238
10901 22:52:09.439303
10902 22:52:09.450689 <30>[ 9.820650] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10903 22:52:09.579446 <30>[ 9.945669] systemd[1]: Queued start job for default target graphical.target.
10904 22:52:09.631055 <30>[ 9.997833] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10905 22:52:09.637947 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10906 22:52:09.638096
10907 22:52:09.658495 <30>[ 10.025260] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10908 22:52:09.665216 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10909 22:52:09.668327
10910 22:52:09.686957 <30>[ 10.053609] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10911 22:52:09.696967 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10912 22:52:09.697084
10913 22:52:09.715118 <30>[ 10.081725] systemd[1]: Created slice user.slice - User and Session Slice.
10914 22:52:09.721571 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10915 22:52:09.721768
10916 22:52:09.741495 <30>[ 10.104875] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10917 22:52:09.748115 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10918 22:52:09.751322
10919 22:52:09.770354 <30>[ 10.133394] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10920 22:52:09.776852 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10921 22:52:09.776970
10922 22:52:09.803742 <30>[ 10.160799] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10923 22:52:09.813963 <30>[ 10.180607] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10924 22:52:09.820836 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10925 22:52:09.820921
10926 22:52:09.838397 <30>[ 10.204990] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10927 22:52:09.844990 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10928 22:52:09.848017
10929 22:52:09.862224 <30>[ 10.228777] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10930 22:52:09.871640 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10931 22:52:09.871760
10932 22:52:09.887044 <30>[ 10.257128] systemd[1]: Reached target paths.target - Path Units.
10933 22:52:09.894175 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10934 22:52:09.896896
10935 22:52:09.914363 <30>[ 10.281086] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10936 22:52:09.920817 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10937 22:52:09.920932
10938 22:52:09.934533 <30>[ 10.304683] systemd[1]: Reached target slices.target - Slice Units.
10939 22:52:09.944606 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10940 22:52:09.944701
10941 22:52:09.959438 <30>[ 10.329141] systemd[1]: Reached target swap.target - Swaps.
10942 22:52:09.965681 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10943 22:52:09.965796
10944 22:52:09.986058 <30>[ 10.352787] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10945 22:52:09.996098 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10946 22:52:09.996196
10947 22:52:10.014827 <30>[ 10.381519] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10948 22:52:10.024461 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10949 22:52:10.024558
10950 22:52:10.043567 <30>[ 10.410441] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10951 22:52:10.053274 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10952 22:52:10.053411
10953 22:52:10.070768 <30>[ 10.437327] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10954 22:52:10.080325 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10955 22:52:10.080459
10956 22:52:10.098393 <30>[ 10.465311] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10957 22:52:10.105042 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10958 22:52:10.105130
10959 22:52:10.123032 <30>[ 10.489344] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10960 22:52:10.132372 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10961 22:52:10.132474
10962 22:52:10.150465 <30>[ 10.517295] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10963 22:52:10.160518 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10964 22:52:10.160613
10965 22:52:10.198474 <30>[ 10.564810] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10966 22:52:10.204480 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10967 22:52:10.204577
10968 22:52:10.230179 <30>[ 10.596850] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10969 22:52:10.236378 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10970 22:52:10.236485
10971 22:52:10.282082 <30>[ 10.648839] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10972 22:52:10.288747 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10973 22:52:10.288841
10974 22:52:10.316855 <30>[ 10.677266] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10975 22:52:10.331243 <30>[ 10.697761] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10976 22:52:10.340809 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10977 22:52:10.340923
10978 22:52:10.366878 <30>[ 10.733746] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10979 22:52:10.374241 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10980 22:52:10.374355
10981 22:52:10.399425 <30>[ 10.765837] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10982 22:52:10.412250 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 10.778791] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10983 22:52:10.415607 Module dm_mod...
10984 22:52:10.415699
10985 22:52:10.458597 <30>[ 10.824963] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10986 22:52:10.464833 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10987 22:52:10.464946
10988 22:52:10.486911 <30>[ 10.853744] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10989 22:52:10.493684 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10990 22:52:10.493795
10991 22:52:10.518621 <30>[ 10.885313] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10992 22:52:10.524880 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10993 22:52:10.524981
10994 22:52:10.590481 <30>[ 10.957285] systemd[1]: Starting systemd-journald.service - Journal Service...
10995 22:52:10.596924 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10996 22:52:10.597034
10997 22:52:10.617321 <30>[ 10.983799] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10998 22:52:10.623609 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10999 22:52:10.623704
11000 22:52:10.648001 <30>[ 11.010950] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
11001 22:52:10.654325 Starting [0;1;39msystemd-network-g… units from Kernel command line...
11002 22:52:10.654436
11003 22:52:10.702033 <30>[ 11.069072] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11004 22:52:10.711871 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
11005 22:52:10.712045
11006 22:52:10.732416 <30>[ 11.099153] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11007 22:52:10.738779 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
11008 22:52:10.738891
11009 22:52:10.763981 <30>[ 11.130670] systemd[1]: Started systemd-journald.service - Journal Service.
11010 22:52:10.770300 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11011 22:52:10.770401
11012 22:52:10.793167 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
11013 22:52:10.793338
11014 22:52:10.810421 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11015 22:52:10.810541
11016 22:52:10.826333 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11017 22:52:10.826438
11018 22:52:10.842480 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11019 22:52:10.842580
11020 22:52:10.858197 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11021 22:52:10.858299
11022 22:52:10.874192 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11023 22:52:10.874347
11024 22:52:10.890129 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11025 22:52:10.890243
11026 22:52:10.908447 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11027 22:52:10.908564
11028 22:52:10.929214 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11029 22:52:10.929370
11030 22:52:10.947815 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11031 22:52:10.947920
11032 22:52:10.967287 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11033 22:52:10.967393
11034 22:52:10.988633 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
11035 22:52:10.988747
11036 22:52:10.994855 See 'systemctl status systemd-remount-fs.service' for details.
11037 22:52:10.994939
11038 22:52:11.004528 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11039 22:52:11.004620
11040 22:52:11.024564 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11041 22:52:11.024679
11042 22:52:11.082497 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11043 22:52:11.082652
11044 22:52:11.106819 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11045 22:52:11.106954
11046 22:52:11.123334 <46>[ 11.490376] systemd-journald[185]: Received client request to flush runtime journal.
11047 22:52:11.137369 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11048 22:52:11.137512
11049 22:52:11.156469 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11050 22:52:11.156591
11051 22:52:11.178544 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11052 22:52:11.178669
11053 22:52:11.203142 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11054 22:52:11.203307
11055 22:52:11.223176 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11056 22:52:11.223296
11057 22:52:11.243185 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11058 22:52:11.243295
11059 22:52:11.266975 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11060 22:52:11.267102
11061 22:52:11.287132 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11062 22:52:11.287243
11063 22:52:11.342583 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11064 22:52:11.342732
11065 22:52:11.370640 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11066 22:52:11.370776
11067 22:52:11.390641 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11068 22:52:11.390768
11069 22:52:11.410186 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11070 22:52:11.410308
11071 22:52:11.457962 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11072 22:52:11.458115
11073 22:52:11.476449 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11074 22:52:11.476569
11075 22:52:11.498203 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11076 22:52:11.498334
11077 22:52:11.518541 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11078 22:52:11.518679
11079 22:52:11.538421 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11080 22:52:11.538554
11081 22:52:11.641787 <6>[ 12.008893] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11082 22:52:11.651828 [[0;32m OK [<6>[ 12.017887] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11083 22:52:11.662364 0m] Created slic<6>[ 12.027002] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11084 22:52:11.671618 e [0;1;39msystem-syste…- Slic<3>[ 12.038195] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11085 22:52:11.678320 <6>[ 12.047210] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11086 22:52:11.687929 e /system/system<3>[ 12.047723] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11087 22:52:11.691942 d-backlight.
11088 22:52:11.692033
11089 22:52:11.697833 <3>[ 12.064532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11090 22:52:11.704387 <6>[ 12.072702] remoteproc remoteproc0: scp is available
11091 22:52:11.711050 <4>[ 12.072779] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11092 22:52:11.717959 <3>[ 12.074703] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11093 22:52:11.727802 <4>[ 12.074722] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11094 22:52:11.730884 <6>[ 12.079069] remoteproc remoteproc0: powering up scp
11095 22:52:11.740688 <3>[ 12.086333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11096 22:52:11.747600 <3>[ 12.086337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11097 22:52:11.757754 <3>[ 12.086341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11098 22:52:11.763809 <3>[ 12.086345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11099 22:52:11.770802 <3>[ 12.092554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11100 22:52:11.780863 <6>[ 12.094481] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11101 22:52:11.786746 <3>[ 12.105539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11102 22:52:11.793915 <6>[ 12.106884] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11103 22:52:11.803843 <3>[ 12.114966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11104 22:52:11.807339 <6>[ 12.151699] mc: Linux media interface: v0.10
11105 22:52:11.813208 <6>[ 12.153577] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11106 22:52:11.823812 <3>[ 12.155707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11107 22:52:11.830006 <3>[ 12.155748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11108 22:52:11.837485 <6>[ 12.157780] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11109 22:52:11.843313 <6>[ 12.157784] pci_bus 0000:00: root bus resource [bus 00-ff]
11110 22:52:11.849989 <6>[ 12.157787] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11111 22:52:11.859825 <6>[ 12.157789] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11112 22:52:11.866927 <6>[ 12.157805] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11113 22:52:11.874176 <6>[ 12.157818] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11114 22:52:11.877277 <6>[ 12.157872] pci 0000:00:00.0: supports D1 D2
11115 22:52:11.886810 <6>[ 12.157874] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11116 22:52:11.893386 <6>[ 12.160602] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11117 22:52:11.899937 <6>[ 12.165115] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11118 22:52:11.907043 <3>[ 12.169451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11119 22:52:11.916656 <3>[ 12.169454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11120 22:52:11.923647 <6>[ 12.177556] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11121 22:52:11.933776 <4>[ 12.178809] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11122 22:52:11.937249 <4>[ 12.178809] Fallback method does not support PEC.
11123 22:52:11.944459 <3>[ 12.182051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11124 22:52:11.954522 <6>[ 12.184262] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11125 22:52:11.961261 <6>[ 12.189704] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11126 22:52:11.971217 <3>[ 12.194074] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11127 22:52:11.978208 <3>[ 12.197767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11128 22:52:11.987605 <6>[ 12.205855] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11129 22:52:11.994481 <3>[ 12.212719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11130 22:52:11.997747 <6>[ 12.218541] pci 0000:01:00.0: supports D1 D2
11131 22:52:12.008378 <3>[ 12.247026] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11132 22:52:12.015437 <3>[ 12.247974] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11133 22:52:12.022240 <6>[ 12.248618] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11134 22:52:12.031814 <6>[ 12.249188] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11135 22:52:12.038488 <6>[ 12.249192] remoteproc remoteproc0: remote processor scp is now up
11136 22:52:12.048210 <6>[ 12.249263] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11137 22:52:12.057971 <6>[ 12.249748] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11138 22:52:12.064809 <6>[ 12.249833] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11139 22:52:12.071718 <6>[ 12.261355] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11140 22:52:12.077995 <6>[ 12.261891] videodev: Linux video capture interface: v2.00
11141 22:52:12.084851 <6>[ 12.264455] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11142 22:52:12.095027 <6>[ 12.264470] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11143 22:52:12.101146 <6>[ 12.264473] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11144 22:52:12.108168 <6>[ 12.264480] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11145 22:52:12.117788 <6>[ 12.264493] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11146 22:52:12.124824 <6>[ 12.264506] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11147 22:52:12.131321 <6>[ 12.264518] pci 0000:00:00.0: PCI bridge to [bus 01]
11148 22:52:12.138381 <6>[ 12.264523] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11149 22:52:12.144635 <6>[ 12.264601] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11150 22:52:12.151150 <6>[ 12.264974] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11151 22:52:12.157962 <6>[ 12.265323] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11152 22:52:12.161340 <6>[ 12.269261] Bluetooth: Core ver 2.22
11153 22:52:12.167966 <6>[ 12.283530] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11154 22:52:12.178223 <5>[ 12.284574] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11155 22:52:12.181248 <6>[ 12.291784] NET: Registered PF_BLUETOOTH protocol family
11156 22:52:12.188151 <5>[ 12.297787] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11157 22:52:12.198347 <5>[ 12.298012] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11158 22:52:12.205751 <4>[ 12.298048] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11159 22:52:12.212130 <6>[ 12.298051] cfg80211: failed to load regulatory.db
11160 22:52:12.222064 <3>[ 12.316685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11161 22:52:12.228707 <6>[ 12.320500] Bluetooth: HCI device and connection manager initialized
11162 22:52:12.232322 <6>[ 12.320511] Bluetooth: HCI socket layer initialized
11163 22:52:12.238662 <6>[ 12.321944] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11164 22:52:12.252800 <6>[ 12.323444] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11165 22:52:12.259621 <6>[ 12.323587] usbcore: registered new interface driver uvcvideo
11166 22:52:12.265923 <3>[ 12.329516] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11167 22:52:12.272461 <6>[ 12.354726] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11168 22:52:12.278951 <6>[ 12.361594] Bluetooth: L2CAP socket layer initialized
11169 22:52:12.282025 <6>[ 12.361602] Bluetooth: SCO socket layer initialized
11170 22:52:12.291906 <6>[ 12.382232] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11171 22:52:12.298400 <3>[ 12.386767] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11172 22:52:12.304953 <6>[ 12.391803] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11173 22:52:12.314984 <3>[ 12.399808] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11174 22:52:12.321621 <6>[ 12.424168] usbcore: registered new interface driver btusb
11175 22:52:12.324948 <6>[ 12.424450] mt7921e 0000:01:00.0: ASIC revision: 79610010
11176 22:52:12.334886 <4>[ 12.424658] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11177 22:52:12.341433 <3>[ 12.424663] Bluetooth: hci0: Failed to load firmware file (-2)
11178 22:52:12.347954 <3>[ 12.424664] Bluetooth: hci0: Failed to set up firmware (-2)
11179 22:52:12.357812 <4>[ 12.424666] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11180 22:52:12.367883 <3>[ 12.458892] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11181 22:52:12.374502 <3>[ 12.476810] power_supply sbs-5-000b: driver failed to report `manufacturer' property: -6
11182 22:52:12.384174 <6>[ 12.511856] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11183 22:52:12.384268 <6>[ 12.511856]
11184 22:52:12.394116 <3>[ 12.513999] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11185 22:52:12.410782 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight..<6>[ 12.776564] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11186 22:52:12.410888 .
11187 22:52:12.410956
11188 22:52:12.474725 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11189 22:52:12.474859
11190 22:52:12.493547 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11191 22:52:12.493652
11192 22:52:12.511922 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11193 22:52:12.512023
11194 22:52:12.536204 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11195 22:52:12.536318
11196 22:52:12.583939 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11197 22:52:12.584059
11198 22:52:12.602896 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11199 22:52:12.603051
11200 22:52:12.622834 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11201 22:52:12.623072
11202 22:52:12.649563 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11203 22:52:12.649741
11204 22:52:12.666425 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11205 22:52:12.666723
11206 22:52:12.682999 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11207 22:52:12.683212
11208 22:52:12.702034 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11209 22:52:12.702227
11210 22:52:12.717554 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11211 22:52:12.717736
11212 22:52:12.747425 [[0;32m OK [<46>[ 13.101556] systemd-journald[185]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.0 (1536 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
11213 22:52:12.764059 0m] Listening on<46>[ 13.124030] systemd-journald[185]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11214 22:52:12.770590 [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11215 22:52:12.770751
11216 22:52:12.786590 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11217 22:52:12.786779
11218 22:52:12.803837 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11219 22:52:12.804225
11220 22:52:12.858854 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11221 22:52:12.859344
11222 22:52:12.885495 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11223 22:52:12.886118
11224 22:52:12.907379 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11225 22:52:12.907834
11226 22:52:12.929844 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11227 22:52:12.930323
11228 22:52:12.949747 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11229 22:52:12.950442
11230 22:52:12.981497 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11231 22:52:12.981769
11232 22:52:12.999340 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11233 22:52:12.999546
11234 22:52:13.048459 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11235 22:52:13.048923
11236 22:52:13.071296 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11237 22:52:13.071818
11238 22:52:13.093105 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11239 22:52:13.093533
11240 22:52:13.114872 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11241 22:52:13.115076
11242 22:52:13.135937 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11243 22:52:13.136082
11244 22:52:13.155511 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11245 22:52:13.155653
11246 22:52:13.198332 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11247 22:52:13.198476
11248 22:52:13.231302 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11249 22:52:13.231469
11250 22:52:13.267349 <6>[ 13.637712] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11251 22:52:13.277121
11252 22:52:13.277561
11253 22:52:13.280509 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11254 22:52:13.280890
11255 22:52:13.283678 debian-bookworm-arm64 login: root (automatic login)
11256 22:52:13.284093
11257 22:52:13.284395
11258 22:52:13.297527 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
11259 22:52:13.297915
11260 22:52:13.304227 The programs included with the Debian GNU/Linux system are free software;
11261 22:52:13.311271 the exact distribution terms for each program are described in the
11262 22:52:13.314577 individual files in /usr/share/doc/*/copyright.
11263 22:52:13.315048
11264 22:52:13.320619 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11265 22:52:13.324237 permitted by applicable law.
11266 22:52:13.325668 Matched prompt #10: / #
11268 22:52:13.326599 Setting prompt string to ['/ #']
11269 22:52:13.327001 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11271 22:52:13.327885 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11272 22:52:13.328271 start: 2.2.6 expect-shell-connection (timeout 00:02:41) [common]
11273 22:52:13.328615 Setting prompt string to ['/ #']
11274 22:52:13.328917 Forcing a shell prompt, looking for ['/ #']
11276 22:52:13.380012 / #
11277 22:52:13.380630 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11278 22:52:13.381071 Waiting using forced prompt support (timeout 00:02:30)
11279 22:52:13.386224
11280 22:52:13.386988 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11281 22:52:13.387449 start: 2.2.7 export-device-env (timeout 00:02:41) [common]
11282 22:52:13.388039 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11283 22:52:13.388772 end: 2.2 depthcharge-retry (duration 00:02:19) [common]
11284 22:52:13.389255 end: 2 depthcharge-action (duration 00:02:19) [common]
11285 22:52:13.389763 start: 3 lava-test-retry (timeout 00:07:07) [common]
11286 22:52:13.390197 start: 3.1 lava-test-shell (timeout 00:07:07) [common]
11287 22:52:13.390569 Using namespace: common
11289 22:52:13.491752 / # #
11290 22:52:13.492442 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11291 22:52:13.497955 #
11292 22:52:13.498781 Using /lava-13683676
11294 22:52:13.599907 / # export SHELL=/bin/sh
11295 22:52:13.606505 export SHELL=/bin/sh
11297 22:52:13.708147 / # . /lava-13683676/environment
11298 22:52:13.714994 . /lava-13683676/environment
11300 22:52:13.816940 / # /lava-13683676/bin/lava-test-runner /lava-13683676/0
11301 22:52:13.817566 Test shell timeout: 10s (minimum of the action and connection timeout)
11302 22:52:13.823259 /lava-13683676/bin/lava-test-runner /lava-13683676/0
11303 22:52:13.850403 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 14.218663] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 13683676_1.5.2.3.1>
11304 22:52:13.851180 Received signal: <STARTRUN> 0_igt-gpu-panfrost 13683676_1.5.2.3.1
11305 22:52:13.851553 Starting test lava.0_igt-gpu-panfrost (13683676_1.5.2.3.1)
11306 22:52:13.851957 Skipping test definition patterns.
11307 22:52:13.853731 nfrost
11308 22:52:13.857065 + cd /lava-13683676/0/tests/0_igt-gpu-panfrost
11309 22:52:13.857528 + cat uuid
11310 22:52:13.859836 + UUID=13683676_1.5.2.3.1
11311 22:52:13.860259 + set +x
11312 22:52:13.876582 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime p<8>[ 14.244100] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11313 22:52:13.877254 anfrost_submit
11314 22:52:13.877963 Received signal: <TESTSET> START panfrost_gem_new
11315 22:52:13.878342 Starting test_set panfrost_gem_new
11316 22:52:13.893075 <14>[ 14.263141] [IGT] panfrost_gem_new: executing
11317 22:52:13.899918 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.269880] [IGT] panfrost_gem_new: exiting, ret=77
11318 22:52:13.903174 h64) (Linux: 6.1.90-cip20 aarch64)
11319 22:52:13.912666 Using IGT_SRANDOM=1715122334<8>[ 14.280557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11320 22:52:13.913451 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11322 22:52:13.916353 for randomisation
11323 22:52:13.922867 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11324 22:52:13.926008 Test requirement: !(fd<0)
11325 22:52:13.932462 No known gpu found for chipset flags 0x32 (panf<14>[ 14.302681] [IGT] panfrost_gem_new: executing
11326 22:52:13.932951 rost)
11327 22:52:13.942296 Last errno: 2, No such fi<14>[ 14.310442] [IGT] panfrost_gem_new: exiting, ret=77
11328 22:52:13.942868 le or directory
11329 22:52:13.945634 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11330 22:52:13.952433 IG<8>[ 14.322016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11331 22:52:13.953109 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11333 22:52:13.958900 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11334 22:52:13.962230 Using IGT_SRANDOM=1715122334 for randomisation
11335 22:52:13.968895 Test requireme<14>[ 14.339070] [IGT] panfrost_gem_new: executing
11336 22:52:13.978731 nt not met in function drm_open_<14>[ 14.346530] [IGT] panfrost_gem_new: exiting, ret=77
11337 22:52:13.982088 driver, file ../lib/drmtest.c:694:
11338 22:52:13.982553 Test requirement: !(fd<0)
11339 22:52:13.989106 N<8>[ 14.357320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11340 22:52:13.989955 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11342 22:52:13.995555 o known gpu foun<8>[ 14.366664] <LAVA_SIGNAL_TESTSET STOP>
11343 22:52:13.996427 Received signal: <TESTSET> STOP
11344 22:52:13.996808 Closing test_set panfrost_gem_new
11345 22:52:13.998433 d for chipset flags 0x32 (panfrost)
11346 22:52:14.001970 Last errno: 2, No such file or directory
11347 22:52:14.005584 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11348 22:52:14.012053 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11349 22:52:14.015165 Using IGT_SRANDOM=1715122334 for randomisation
11350 22:52:14.028699 Test requirement not met in function drm_open_driver, file ../lib/d<8>[ 14.396018] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11351 22:52:14.029229 rmtest.c:694:
11352 22:52:14.029886 Received signal: <TESTSET> START panfrost_get_param
11353 22:52:14.030226 Starting test_set panfrost_get_param
11354 22:52:14.032079 Test requirement: !(fd<0)
11355 22:52:14.035117 No known gpu found for chipset flags 0x32 (panfrost)
11356 22:52:14.038389 Last errno: 2, No such file or directory
11357 22:52:14.045190 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11358 22:52:14.059545 <14>[ 14.429736] [IGT] panfrost_get_param: executing
11359 22:52:14.069289 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.438869] [IGT] panfrost_get_param: exiting, ret=77
11360 22:52:14.072987 .90-cip20 aarch64)
11361 22:52:14.082335 Using IGT_SRANDOM=1715122334 for randomisati<8>[ 14.449036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11362 22:52:14.082780 on
11363 22:52:14.083479 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11365 22:52:14.089274 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11366 22:52:14.092633 Test requirement: !(fd<0)
11367 22:52:14.099282 No known gpu fo<14>[ 14.468032] [IGT] panfrost_get_param: executing
11368 22:52:14.105924 und for chipset flags 0x32 (panf<14>[ 14.474792] [IGT] panfrost_get_param: exiting, ret=77
11369 22:52:14.106450 rost)
11370 22:52:14.109109 Last errno: 2, No such file or directory
11371 22:52:14.119075 [1mSubtest bas<8>[ 14.486395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11372 22:52:14.119985 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11374 22:52:14.121883 e-params: SKIP (0.000s)[0m
11375 22:52:14.128499 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11376 22:52:14.132115 Using IGT_SRANDOM=1715122334 for randomisation
11377 22:52:14.135625 <14>[ 14.505138] [IGT] panfrost_get_param: executing
11378 22:52:14.136208
11379 22:52:14.145238 Test requirement not met in fun<14>[ 14.513095] [IGT] panfrost_get_param: exiting, ret=77
11380 22:52:14.148867 ction drm_open_driver, file ../lib/drmtest.c:694:
11381 22:52:14.158646 Test requirem<8>[ 14.523968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11382 22:52:14.159080 ent: !(fd<0)
11383 22:52:14.159663 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11385 22:52:14.161375 No<8>[ 14.533497] <LAVA_SIGNAL_TESTSET STOP>
11386 22:52:14.162047 Received signal: <TESTSET> STOP
11387 22:52:14.162392 Closing test_set panfrost_get_param
11388 22:52:14.168376 known gpu found for chipset flags 0x32 (panfrost)
11389 22:52:14.171667 Last errno: 2, No such file or directory
11390 22:52:14.175008 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11391 22:52:14.184641 IGT-Version: 1.28-ga44ebfe (aarch64)<8>[ 14.552348] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11392 22:52:14.185145 (Linux: 6.1.90-cip20 aarch64)
11393 22:52:14.185779 Received signal: <TESTSET> START panfrost_prime
11394 22:52:14.186117 Starting test_set panfrost_prime
11395 22:52:14.191468 Using IGT_SRANDOM=1715122334 for randomisation
11396 22:52:14.197848 Test requirement not met in function drm_open_dr<14>[ 14.568540] [IGT] panfrost_prime: executing
11397 22:52:14.208133 iver, file ../lib/drmtest.c:694:<14>[ 14.575851] [IGT] panfrost_prime: exiting, ret=77
11398 22:52:14.208659
11399 22:52:14.208991 Test requirement: !(fd<0)
11400 22:52:14.220905 No known gpu found for chipset flag<8>[ 14.587206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11401 22:52:14.221709 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11403 22:52:14.224432 s 0x32 (panfrost<8>[ 14.596041] <LAVA_SIGNAL_TESTSET STOP>
11404 22:52:14.224848 )
11405 22:52:14.225439 Received signal: <TESTSET> STOP
11406 22:52:14.225772 Closing test_set panfrost_prime
11407 22:52:14.227742 Last errno: 2, No such file or directory
11408 22:52:14.233984 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11409 22:52:14.240723 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11410 22:52:14.244066 Using IGT_SRANDOM=1715122334 for randomisation
11411 22:52:14.253972 Received signal: <TESTSET> START panfrost_submit
11412 22:52:14.254393 Starting test_set panfrost_submit
11413 22:52:14.257535 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694<8>[ 14.625220] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11414 22:52:14.258064 :
11415 22:52:14.258399 Test requirement: !(fd<0)
11416 22:52:14.263839 No known gpu found for chipset flags 0x32 (panfrost)
11417 22:52:14.267304 Last errno: 2, No such file or directory
11418 22:52:14.270459 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11419 22:52:14.281424 <14>[ 14.651637] [IGT] panfrost_submit: executing
11420 22:52:14.288118 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.658981] [IGT] panfrost_submit: exiting, ret=77
11421 22:52:14.291266 h64) (Linux: 6.1.90-cip20 aarch64)
11422 22:52:14.297959 Using IGT_SRANDOM=1715122334 for randomisation
11423 22:52:14.304474 Test require<8>[ 14.671573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11424 22:52:14.305249 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11426 22:52:14.311000 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
11427 22:52:14.314297 Test requirement: !(fd<0)
11428 22:52:14.321190 No known gpu found for chipset <14>[ 14.690325] [IGT] panfrost_submit: executing
11429 22:52:14.321694 flags 0x32 (panfrost)
11430 22:52:14.327558 Last errn<14>[ 14.697368] [IGT] panfrost_submit: exiting, ret=77
11431 22:52:14.331009 o: 2, No such file or directory
11432 22:52:14.340833 [1mSubtest pan-submit: SKIP (0<8>[ 14.707859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11433 22:52:14.341526 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11435 22:52:14.343911 .000s)[0m
11436 22:52:14.347066 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11437 22:52:14.353621 Using IGT_SRANDOM=1715122334 for randomisation
11438 22:52:14.360427 Test requirement not met in func<14>[ 14.730148] [IGT] panfrost_submit: executing
11439 22:52:14.366964 tion drm_open_driver, file ../li<14>[ 14.737344] [IGT] panfrost_submit: exiting, ret=77
11440 22:52:14.370128 b/drmtest.c:694:
11441 22:52:14.373704 Test requirement: !(fd<0)
11442 22:52:14.383426 No known gpu found <8>[ 14.747913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11443 22:52:14.384149 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11445 22:52:14.386577 for chipset flags 0x32 (panfrost)
11446 22:52:14.390137 Last errno: 2, No such file or directory
11447 22:52:14.396745 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[<14>[ 14.767388] [IGT] panfrost_submit: executing
11448 22:52:14.397198 0m
11449 22:52:14.406794 IGT-Version: 1.28-ga44ebfe (<14>[ 14.774860] [IGT] panfrost_submit: exiting, ret=77
11450 22:52:14.409751 aarch64) (Linux: 6.1.90-cip20 aarch64)
11451 22:52:14.419756 Using IGT_SRANDOM=171512<8>[ 14.785415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11452 22:52:14.420434 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11454 22:52:14.423383 2334 for randomisation
11455 22:52:14.429764 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11456 22:52:14.432927 Test requirement: !(fd<0)
11457 22:52:14.439382 No known gpu found for chipset flags 0x32 (<14>[ 14.809592] [IGT] panfrost_submit: executing
11458 22:52:14.439821 panfrost)
11459 22:52:14.449479 Last errno: 2, No suc<14>[ 14.817014] [IGT] panfrost_submit: exiting, ret=77
11460 22:52:14.449898 h file or directory
11461 22:52:14.462442 [1mSubtest pan-submit-error-bad-in-syncs: <8>[ 14.827365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11462 22:52:14.462954 SKIP (0.000s)[0m
11463 22:52:14.463552 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11465 22:52:14.469464 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11466 22:52:14.475789 Using IGT_SRANDOM=1715122334 for randomisation
11467 22:52:14.481914 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11468 22:52:14.482434 Test requirement: !(fd<0)
11469 22:52:14.488598 No known gpu<14>[ 14.859118] [IGT] panfrost_submit: executing
11470 22:52:14.491771 found for chipset flags 0x32 (panfrost)
11471 22:52:14.498678 Last e<14>[ 14.867379] [IGT] panfrost_submit: exiting, ret=77
11472 22:52:14.502244 rrno: 2, No such file or directory
11473 22:52:14.514899 [1mSubtest pan-submit-error-bad-bo-handles:<8>[ 14.879945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11474 22:52:14.515410 SKIP (0.000s)[0m
11475 22:52:14.516021 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11477 22:52:14.521546 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11478 22:52:14.525094 Using IGT_SRANDOM=1715122334 for randomisation
11479 22:52:14.531736 Test requirement not met<14>[ 14.902842] [IGT] panfrost_submit: executing
11480 22:52:14.541550 in function drm_open_driver, fi<14>[ 14.909643] [IGT] panfrost_submit: exiting, ret=77
11481 22:52:14.542069 le ../lib/drmtest.c:694:
11482 22:52:14.544892 Test requirement: !(fd<0)
11483 22:52:14.551501 No known gp<8>[ 14.920029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11484 22:52:14.552318 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11486 22:52:14.557773 u found for chipset flags 0x32 (panfrost)
11487 22:52:14.561159 Last errno: 2, No such file or directory
11488 22:52:14.565774 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11489 22:52:14.573955 IGT-Version: 1.28-ga44ebf<14>[ 14.941878] [IGT] panfrost_submit: executing
11490 22:52:14.580552 e (aarch64) (Linux: 6.1.90-cip20<14>[ 14.949806] [IGT] panfrost_submit: exiting, ret=77
11491 22:52:14.580979 aarch64)
11492 22:52:14.587143 Using IGT_SRANDOM=1715122334 for randomisation
11493 22:52:14.593370 Test <8>[ 14.960171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11494 22:52:14.594070 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11496 22:52:14.600627 requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11497 22:52:14.603248 Test requirement: !(fd<0)
11498 22:52:14.610081 No known gpu found for c<14>[ 14.979766] [IGT] panfrost_submit: executing
11499 22:52:14.613112 hipset flags 0x32 (panfrost)
11500 22:52:14.616557 La<14>[ 14.986745] [IGT] panfrost_submit: exiting, ret=77
11501 22:52:14.620481 st errno: 2, No such file or directory
11502 22:52:14.629965 [1mSubtest pan-submit-e<8>[ 14.998002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11503 22:52:14.630650 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11505 22:52:14.636364 rror-bad-out-syn<8>[ 15.007370] <LAVA_SIGNAL_TESTSET STOP>
11506 22:52:14.637151 Received signal: <TESTSET> STOP
11507 22:52:14.637581 Closing test_set panfrost_submit
11508 22:52:14.643008 c: SKIP (0.000s)<8>[ 15.012725] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 13683676_1.5.2.3.1>
11509 22:52:14.643785 Received signal: <ENDRUN> 0_igt-gpu-panfrost 13683676_1.5.2.3.1
11510 22:52:14.644228 Ending use of test pattern.
11511 22:52:14.644580 Ending test lava.0_igt-gpu-panfrost (13683676_1.5.2.3.1), duration 0.79
11513 22:52:14.646574 [0m
11514 22:52:14.649611 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11515 22:52:14.656692 Using IGT_SRANDOM=1715122334 for randomisation
11516 22:52:14.663216 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11517 22:52:14.666107 Test requirement: !(fd<0)
11518 22:52:14.669609 No known gpu found for chipset flags 0x32 (panfrost)
11519 22:52:14.673080 Last errno: 2, No such file or directory
11520 22:52:14.676424 [1mSubtest pan-reset: SKIP (0.000s)[0m
11521 22:52:14.682780 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11522 22:52:14.685915 Using IGT_SRANDOM=1715122334 for randomisation
11523 22:52:14.692908 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11524 22:52:14.696188 Test requirement: !(fd<0)
11525 22:52:14.702424 No known gpu found for chipset flags 0x32 (panfrost)
11526 22:52:14.705757 Last errno: 2, No such file or directory
11527 22:52:14.709366 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11528 22:52:14.715974 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11529 22:52:14.719191 Using IGT_SRANDOM=1715122334 for randomisation
11530 22:52:14.725528 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11531 22:52:14.729634 Test requirement: !(fd<0)
11532 22:52:14.732200 No known gpu found for chipset flags 0x32 (panfrost)
11533 22:52:14.735719 Last errno: 2, No such file or directory
11534 22:52:14.741924 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11535 22:52:14.742468 + set +x
11536 22:52:14.745180 <LAVA_TEST_RUNNER EXIT>
11537 22:52:14.745893 ok: lava_test_shell seems to have completed
11538 22:52:14.747423 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11539 22:52:14.747896 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11540 22:52:14.748312 end: 3 lava-test-retry (duration 00:00:01) [common]
11541 22:52:14.748741 start: 4 finalize (timeout 00:07:06) [common]
11542 22:52:14.749168 start: 4.1 power-off (timeout 00:00:30) [common]
11543 22:52:14.749955 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11544 22:52:14.996833 >> Command sent successfully.
11545 22:52:14.999467 Returned 0 in 0 seconds
11546 22:52:15.099995 end: 4.1 power-off (duration 00:00:00) [common]
11548 22:52:15.100609 start: 4.2 read-feedback (timeout 00:07:05) [common]
11549 22:52:15.101100 Listened to connection for namespace 'common' for up to 1s
11550 22:52:16.101637 Finalising connection for namespace 'common'
11551 22:52:16.102318 Disconnecting from shell: Finalise
11552 22:52:16.102735 / #
11553 22:52:16.203763 end: 4.2 read-feedback (duration 00:00:01) [common]
11554 22:52:16.204705 end: 4 finalize (duration 00:00:01) [common]
11555 22:52:16.205549 Cleaning after the job
11556 22:52:16.206212 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/ramdisk
11557 22:52:16.233639 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/kernel
11558 22:52:16.259976 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/dtb
11559 22:52:16.260249 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683676/tftp-deploy-mn31krvj/modules
11560 22:52:16.266833 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683676
11561 22:52:16.384999 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683676
11562 22:52:16.385200 Job finished correctly