Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 23
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
1 22:52:15.565588 lava-dispatcher, installed at version: 2024.01
2 22:52:15.565840 start: 0 validate
3 22:52:15.565975 Start time: 2024-05-07 22:52:15.565968+00:00 (UTC)
4 22:52:15.566111 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:52:15.566243 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 22:52:15.825492 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:52:15.825710 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:52:16.083778 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:52:16.083957 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:52:16.333295 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:52:16.333474 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:52:16.592183 validate duration: 1.03
14 22:52:16.592469 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:52:16.592571 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:52:16.592658 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:52:16.592779 Not decompressing ramdisk as can be used compressed.
18 22:52:16.592901 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 22:52:16.592964 saving as /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/ramdisk/rootfs.cpio.gz
20 22:52:16.593026 total size: 47897469 (45 MB)
21 22:52:16.594133 progress 0 % (0 MB)
22 22:52:16.606834 progress 5 % (2 MB)
23 22:52:16.619234 progress 10 % (4 MB)
24 22:52:16.631600 progress 15 % (6 MB)
25 22:52:16.644322 progress 20 % (9 MB)
26 22:52:16.656779 progress 25 % (11 MB)
27 22:52:16.669054 progress 30 % (13 MB)
28 22:52:16.681694 progress 35 % (16 MB)
29 22:52:16.693879 progress 40 % (18 MB)
30 22:52:16.706280 progress 45 % (20 MB)
31 22:52:16.718636 progress 50 % (22 MB)
32 22:52:16.731010 progress 55 % (25 MB)
33 22:52:16.743560 progress 60 % (27 MB)
34 22:52:16.755955 progress 65 % (29 MB)
35 22:52:16.768146 progress 70 % (32 MB)
36 22:52:16.780435 progress 75 % (34 MB)
37 22:52:16.792669 progress 80 % (36 MB)
38 22:52:16.804831 progress 85 % (38 MB)
39 22:52:16.816977 progress 90 % (41 MB)
40 22:52:16.828939 progress 95 % (43 MB)
41 22:52:16.841095 progress 100 % (45 MB)
42 22:52:16.841344 45 MB downloaded in 0.25 s (183.95 MB/s)
43 22:52:16.841505 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:52:16.841780 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:52:16.841864 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:52:16.841947 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:52:16.842086 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:52:16.842153 saving as /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/kernel/Image
50 22:52:16.842213 total size: 54682112 (52 MB)
51 22:52:16.842274 No compression specified
52 22:52:16.843387 progress 0 % (0 MB)
53 22:52:16.857386 progress 5 % (2 MB)
54 22:52:16.871416 progress 10 % (5 MB)
55 22:52:16.885690 progress 15 % (7 MB)
56 22:52:16.899536 progress 20 % (10 MB)
57 22:52:16.913457 progress 25 % (13 MB)
58 22:52:16.927089 progress 30 % (15 MB)
59 22:52:16.941003 progress 35 % (18 MB)
60 22:52:16.955169 progress 40 % (20 MB)
61 22:52:16.969255 progress 45 % (23 MB)
62 22:52:16.983673 progress 50 % (26 MB)
63 22:52:16.997470 progress 55 % (28 MB)
64 22:52:17.011444 progress 60 % (31 MB)
65 22:52:17.025098 progress 65 % (33 MB)
66 22:52:17.038998 progress 70 % (36 MB)
67 22:52:17.052842 progress 75 % (39 MB)
68 22:52:17.067069 progress 80 % (41 MB)
69 22:52:17.081354 progress 85 % (44 MB)
70 22:52:17.095311 progress 90 % (46 MB)
71 22:52:17.109281 progress 95 % (49 MB)
72 22:52:17.123128 progress 100 % (52 MB)
73 22:52:17.123400 52 MB downloaded in 0.28 s (185.46 MB/s)
74 22:52:17.123551 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:52:17.123778 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:52:17.123864 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:52:17.123956 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:52:17.124095 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:52:17.124164 saving as /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/dtb/mt8192-asurada-spherion-r0.dtb
81 22:52:17.124224 total size: 47258 (0 MB)
82 22:52:17.124285 No compression specified
83 22:52:17.125415 progress 69 % (0 MB)
84 22:52:17.125736 progress 100 % (0 MB)
85 22:52:17.125891 0 MB downloaded in 0.00 s (27.07 MB/s)
86 22:52:17.126014 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:52:17.126232 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:52:17.126316 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:52:17.126397 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:52:17.126509 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:52:17.126575 saving as /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/modules/modules.tar
93 22:52:17.126635 total size: 8594396 (8 MB)
94 22:52:17.126695 Using unxz to decompress xz
95 22:52:17.130850 progress 0 % (0 MB)
96 22:52:17.150057 progress 5 % (0 MB)
97 22:52:17.174895 progress 10 % (0 MB)
98 22:52:17.199484 progress 15 % (1 MB)
99 22:52:17.223245 progress 20 % (1 MB)
100 22:52:17.248319 progress 25 % (2 MB)
101 22:52:17.272321 progress 30 % (2 MB)
102 22:52:17.296553 progress 35 % (2 MB)
103 22:52:17.322175 progress 40 % (3 MB)
104 22:52:17.348139 progress 45 % (3 MB)
105 22:52:17.373199 progress 50 % (4 MB)
106 22:52:17.398248 progress 55 % (4 MB)
107 22:52:17.424700 progress 60 % (4 MB)
108 22:52:17.449946 progress 65 % (5 MB)
109 22:52:17.475293 progress 70 % (5 MB)
110 22:52:17.499623 progress 75 % (6 MB)
111 22:52:17.525091 progress 80 % (6 MB)
112 22:52:17.550788 progress 85 % (6 MB)
113 22:52:17.579684 progress 90 % (7 MB)
114 22:52:17.608932 progress 95 % (7 MB)
115 22:52:17.635089 progress 100 % (8 MB)
116 22:52:17.640443 8 MB downloaded in 0.51 s (15.95 MB/s)
117 22:52:17.640701 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:52:17.640961 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:52:17.641052 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:52:17.641146 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:52:17.641226 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:52:17.641317 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:52:17.641574 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4
125 22:52:17.641708 makedir: /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin
126 22:52:17.641808 makedir: /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/tests
127 22:52:17.641904 makedir: /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/results
128 22:52:17.642020 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-add-keys
129 22:52:17.642166 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-add-sources
130 22:52:17.642294 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-background-process-start
131 22:52:17.642423 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-background-process-stop
132 22:52:17.642578 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-common-functions
133 22:52:17.642701 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-echo-ipv4
134 22:52:17.642855 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-install-packages
135 22:52:17.642977 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-installed-packages
136 22:52:17.643098 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-os-build
137 22:52:17.643222 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-probe-channel
138 22:52:17.643343 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-probe-ip
139 22:52:17.643466 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-target-ip
140 22:52:17.643588 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-target-mac
141 22:52:17.643708 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-target-storage
142 22:52:17.643835 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-test-case
143 22:52:17.643959 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-test-event
144 22:52:17.644080 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-test-feedback
145 22:52:17.644203 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-test-raise
146 22:52:17.644327 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-test-reference
147 22:52:17.644479 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-test-runner
148 22:52:17.644601 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-test-set
149 22:52:17.644724 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-test-shell
150 22:52:17.644849 Updating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-install-packages (oe)
151 22:52:17.644999 Updating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/bin/lava-installed-packages (oe)
152 22:52:17.645120 Creating /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/environment
153 22:52:17.645220 LAVA metadata
154 22:52:17.645294 - LAVA_JOB_ID=13683715
155 22:52:17.645357 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:52:17.645458 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:52:17.645547 skipped lava-vland-overlay
158 22:52:17.645636 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:52:17.645714 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:52:17.645773 skipped lava-multinode-overlay
161 22:52:17.645845 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:52:17.645925 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:52:17.645997 Loading test definitions
164 22:52:17.646087 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:52:17.646161 Using /lava-13683715 at stage 0
166 22:52:17.646509 uuid=13683715_1.5.2.3.1 testdef=None
167 22:52:17.646596 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:52:17.646682 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:52:17.647206 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:52:17.647425 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:52:17.648021 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:52:17.648246 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:52:17.648838 runner path: /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/0/tests/0_igt-kms-mediatek test_uuid 13683715_1.5.2.3.1
176 22:52:17.648998 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:52:17.649199 Creating lava-test-runner.conf files
179 22:52:17.649260 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683715/lava-overlay-_t8sn4i4/lava-13683715/0 for stage 0
180 22:52:17.649348 - 0_igt-kms-mediatek
181 22:52:17.649442 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:52:17.649547 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:52:17.656667 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:52:17.656780 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:52:17.656867 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:52:17.656952 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:52:17.657035 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:52:19.427679 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 22:52:19.428065 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 22:52:19.428173 extracting modules file /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683715/extract-overlay-ramdisk-yk8445i_/ramdisk
191 22:52:19.649446 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:52:19.649730 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 22:52:19.649827 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683715/compress-overlay-lqwu71bx/overlay-1.5.2.4.tar.gz to ramdisk
194 22:52:19.649904 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683715/compress-overlay-lqwu71bx/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683715/extract-overlay-ramdisk-yk8445i_/ramdisk
195 22:52:19.656667 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:52:19.656785 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 22:52:19.656877 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:52:19.656966 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 22:52:19.657042 Building ramdisk /var/lib/lava/dispatcher/tmp/13683715/extract-overlay-ramdisk-yk8445i_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683715/extract-overlay-ramdisk-yk8445i_/ramdisk
200 22:52:20.882686 >> 465910 blocks
201 22:52:27.144546 rename /var/lib/lava/dispatcher/tmp/13683715/extract-overlay-ramdisk-yk8445i_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/ramdisk/ramdisk.cpio.gz
202 22:52:27.145011 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 22:52:27.145135 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 22:52:27.145234 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 22:52:27.145361 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/kernel/Image'
206 22:52:40.451273 Returned 0 in 13 seconds
207 22:52:40.551894 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/kernel/image.itb
208 22:52:41.421146 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:52:41.421575 output: Created: Tue May 7 23:52:41 2024
210 22:52:41.421714 output: Image 0 (kernel-1)
211 22:52:41.421802 output: Description:
212 22:52:41.421868 output: Created: Tue May 7 23:52:41 2024
213 22:52:41.421932 output: Type: Kernel Image
214 22:52:41.421989 output: Compression: lzma compressed
215 22:52:41.422046 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
216 22:52:41.422105 output: Architecture: AArch64
217 22:52:41.422159 output: OS: Linux
218 22:52:41.422214 output: Load Address: 0x00000000
219 22:52:41.422271 output: Entry Point: 0x00000000
220 22:52:41.422327 output: Hash algo: crc32
221 22:52:41.422384 output: Hash value: 727ee7c6
222 22:52:41.422441 output: Image 1 (fdt-1)
223 22:52:41.422496 output: Description: mt8192-asurada-spherion-r0
224 22:52:41.422549 output: Created: Tue May 7 23:52:41 2024
225 22:52:41.422601 output: Type: Flat Device Tree
226 22:52:41.422654 output: Compression: uncompressed
227 22:52:41.422706 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 22:52:41.422759 output: Architecture: AArch64
229 22:52:41.422810 output: Hash algo: crc32
230 22:52:41.422863 output: Hash value: 0f8e4d2e
231 22:52:41.422933 output: Image 2 (ramdisk-1)
232 22:52:41.422988 output: Description: unavailable
233 22:52:41.423041 output: Created: Tue May 7 23:52:41 2024
234 22:52:41.423094 output: Type: RAMDisk Image
235 22:52:41.423146 output: Compression: Unknown Compression
236 22:52:41.423198 output: Data Size: 60987273 Bytes = 59557.88 KiB = 58.16 MiB
237 22:52:41.423271 output: Architecture: AArch64
238 22:52:41.423339 output: OS: Linux
239 22:52:41.423390 output: Load Address: unavailable
240 22:52:41.423442 output: Entry Point: unavailable
241 22:52:41.423494 output: Hash algo: crc32
242 22:52:41.423546 output: Hash value: ffa659bf
243 22:52:41.423598 output: Default Configuration: 'conf-1'
244 22:52:41.423649 output: Configuration 0 (conf-1)
245 22:52:41.423701 output: Description: mt8192-asurada-spherion-r0
246 22:52:41.423752 output: Kernel: kernel-1
247 22:52:41.423804 output: Init Ramdisk: ramdisk-1
248 22:52:41.423855 output: FDT: fdt-1
249 22:52:41.423907 output: Loadables: kernel-1
250 22:52:41.423959 output:
251 22:52:41.424149 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 22:52:41.424248 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 22:52:41.424349 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 22:52:41.424448 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 22:52:41.424581 No LXC device requested
256 22:52:41.424681 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:52:41.424770 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 22:52:41.424844 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:52:41.424911 Checking files for TFTP limit of 4294967296 bytes.
260 22:52:41.425407 end: 1 tftp-deploy (duration 00:00:25) [common]
261 22:52:41.425519 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:52:41.425646 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:52:41.425770 substitutions:
264 22:52:41.425836 - {DTB}: 13683715/tftp-deploy-x7een8un/dtb/mt8192-asurada-spherion-r0.dtb
265 22:52:41.425901 - {INITRD}: 13683715/tftp-deploy-x7een8un/ramdisk/ramdisk.cpio.gz
266 22:52:41.425959 - {KERNEL}: 13683715/tftp-deploy-x7een8un/kernel/Image
267 22:52:41.426016 - {LAVA_MAC}: None
268 22:52:41.426072 - {PRESEED_CONFIG}: None
269 22:52:41.426127 - {PRESEED_LOCAL}: None
270 22:52:41.426181 - {RAMDISK}: 13683715/tftp-deploy-x7een8un/ramdisk/ramdisk.cpio.gz
271 22:52:41.426236 - {ROOT_PART}: None
272 22:52:41.426291 - {ROOT}: None
273 22:52:41.426344 - {SERVER_IP}: 192.168.201.1
274 22:52:41.426397 - {TEE}: None
275 22:52:41.426451 Parsed boot commands:
276 22:52:41.426503 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:52:41.426681 Parsed boot commands: tftpboot 192.168.201.1 13683715/tftp-deploy-x7een8un/kernel/image.itb 13683715/tftp-deploy-x7een8un/kernel/cmdline
278 22:52:41.426769 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:52:41.426851 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:52:41.426940 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:52:41.427022 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:52:41.427093 Not connected, no need to disconnect.
283 22:52:41.427164 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:52:41.427242 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:52:41.427308 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 22:52:41.431157 Setting prompt string to ['lava-test: # ']
287 22:52:41.431551 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:52:41.431654 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:52:41.431779 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:52:41.431900 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:52:41.432113 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 22:52:46.564679 >> Command sent successfully.
293 22:52:46.566997 Returned 0 in 5 seconds
294 22:52:46.667351 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:52:46.667661 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:52:46.667761 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:52:46.667851 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:52:46.667918 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:52:46.667985 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:52:46.668255 [Enter `^Ec?' for help]
302 22:52:46.839588
303 22:52:46.839730
304 22:52:46.839802 F0: 102B 0000
305 22:52:46.839869
306 22:52:46.839932 F3: 1001 0000 [0200]
307 22:52:46.839991
308 22:52:46.843532 F3: 1001 0000
309 22:52:46.843616
310 22:52:46.843683 F7: 102D 0000
311 22:52:46.843745
312 22:52:46.843803 F1: 0000 0000
313 22:52:46.843861
314 22:52:46.846893 V0: 0000 0000 [0001]
315 22:52:46.847016
316 22:52:46.847084 00: 0007 8000
317 22:52:46.847151
318 22:52:46.851013 01: 0000 0000
319 22:52:46.851108
320 22:52:46.851204 BP: 0C00 0209 [0000]
321 22:52:46.851287
322 22:52:46.851381 G0: 1182 0000
323 22:52:46.854447
324 22:52:46.854555 EC: 0000 0021 [4000]
325 22:52:46.854648
326 22:52:46.858073 S7: 0000 0000 [0000]
327 22:52:46.858168
328 22:52:46.858263 CC: 0000 0000 [0001]
329 22:52:46.858343
330 22:52:46.861057 T0: 0000 0040 [010F]
331 22:52:46.861170
332 22:52:46.861269 Jump to BL
333 22:52:46.861360
334 22:52:46.886415
335 22:52:46.886528
336 22:52:46.886631
337 22:52:46.893527 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:52:46.897077 ARM64: Exception handlers installed.
339 22:52:46.900452 ARM64: Testing exception
340 22:52:46.904646 ARM64: Done test exception
341 22:52:46.911766 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:52:46.919464 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:52:46.926383 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:52:46.936871 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:52:46.943826 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:52:46.953631 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:52:46.963934 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:52:46.970713 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:52:46.989072 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:52:46.992167 WDT: Last reset was cold boot
351 22:52:46.995405 SPI1(PAD0) initialized at 2873684 Hz
352 22:52:46.998517 SPI5(PAD0) initialized at 992727 Hz
353 22:52:47.002075 VBOOT: Loading verstage.
354 22:52:47.008784 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:52:47.012437 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:52:47.015275 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:52:47.018778 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:52:47.026254 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:52:47.033039 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:52:47.043823 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 22:52:47.043907
362 22:52:47.043973
363 22:52:47.053771 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:52:47.057347 ARM64: Exception handlers installed.
365 22:52:47.060723 ARM64: Testing exception
366 22:52:47.060809 ARM64: Done test exception
367 22:52:47.067091 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:52:47.070605 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:52:47.084975 Probing TPM: . done!
370 22:52:47.085065 TPM ready after 0 ms
371 22:52:47.091711 Connected to device vid:did:rid of 1ae0:0028:00
372 22:52:47.098787 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 22:52:47.138708 Initialized TPM device CR50 revision 0
374 22:52:47.150495 tlcl_send_startup: Startup return code is 0
375 22:52:47.150591 TPM: setup succeeded
376 22:52:47.162167 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:52:47.170739 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:52:47.183455 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:52:47.191841 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:52:47.195010 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:52:47.199255 in-header: 03 07 00 00 08 00 00 00
382 22:52:47.202450 in-data: aa e4 47 04 13 02 00 00
383 22:52:47.205994 Chrome EC: UHEPI supported
384 22:52:47.212889 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:52:47.217101 in-header: 03 9d 00 00 08 00 00 00
386 22:52:47.220502 in-data: 10 20 20 08 00 00 00 00
387 22:52:47.220586 Phase 1
388 22:52:47.227738 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:52:47.231774 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:52:47.238697 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:52:47.242642 Recovery requested (1009000e)
392 22:52:47.248033 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:52:47.253269 tlcl_extend: response is 0
394 22:52:47.261517 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:52:47.267275 tlcl_extend: response is 0
396 22:52:47.273503 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:52:47.295006 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:52:47.301912 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:52:47.302001
400 22:52:47.302068
401 22:52:47.312803 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:52:47.312890 ARM64: Exception handlers installed.
403 22:52:47.316109 ARM64: Testing exception
404 22:52:47.319329 ARM64: Done test exception
405 22:52:47.339684 pmic_efuse_setting: Set efuses in 11 msecs
406 22:52:47.343618 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:52:47.347345 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:52:47.354485 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:52:47.357902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:52:47.361499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:52:47.369165 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:52:47.372781 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:52:47.376202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:52:47.383782 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:52:47.386733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:52:47.393377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:52:47.396911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:52:47.400174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:52:47.406429 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:52:47.413211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:52:47.416910 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:52:47.423343 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:52:47.430206 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:52:47.433308 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:52:47.440291 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:52:47.447472 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:52:47.450978 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:52:47.458907 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:52:47.461532 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:52:47.468586 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:52:47.472627 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:52:47.479087 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:52:47.485241 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:52:47.488769 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:52:47.492122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:52:47.499131 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:52:47.502749 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:52:47.510103 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:52:47.514104 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:52:47.517728 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:52:47.525305 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:52:47.529251 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:52:47.532628 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:52:47.539327 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:52:47.542425 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:52:47.545894 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:52:47.552664 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:52:47.556207 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:52:47.559619 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:52:47.565754 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:52:47.569202 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:52:47.572608 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:52:47.576129 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:52:47.582506 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:52:47.585682 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:52:47.589315 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:52:47.596368 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:52:47.602430 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:52:47.609279 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:52:47.616278 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:52:47.622981 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:52:47.632507 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:52:47.635944 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:52:47.642324 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:52:47.645888 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:52:47.652218 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x35
467 22:52:47.659145 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:52:47.662574 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 22:52:47.666028 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:52:47.676613 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 22:52:47.680005 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 22:52:47.686964 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 22:52:47.689897 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 22:52:47.693466 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 22:52:47.696901 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 22:52:47.700643 ADC[4]: Raw value=897780 ID=7
477 22:52:47.703306 ADC[3]: Raw value=213070 ID=1
478 22:52:47.703390 RAM Code: 0x71
479 22:52:47.710219 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 22:52:47.713499 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 22:52:47.723887 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 22:52:47.730810 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 22:52:47.734091 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 22:52:47.737692 in-header: 03 07 00 00 08 00 00 00
485 22:52:47.740822 in-data: aa e4 47 04 13 02 00 00
486 22:52:47.740928 Chrome EC: UHEPI supported
487 22:52:47.747734 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 22:52:47.752343 in-header: 03 d5 00 00 08 00 00 00
489 22:52:47.755586 in-data: 98 20 60 08 00 00 00 00
490 22:52:47.759466 MRC: failed to locate region type 0.
491 22:52:47.766767 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 22:52:47.770302 DRAM-K: Running full calibration
493 22:52:47.773748 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 22:52:47.776532 header.status = 0x0
495 22:52:47.780531 header.version = 0x6 (expected: 0x6)
496 22:52:47.784557 header.size = 0xd00 (expected: 0xd00)
497 22:52:47.784673 header.flags = 0x0
498 22:52:47.790854 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 22:52:47.809280 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 22:52:47.815884 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 22:52:47.818922 dram_init: ddr_geometry: 2
502 22:52:47.822977 [EMI] MDL number = 2
503 22:52:47.823080 [EMI] Get MDL freq = 0
504 22:52:47.826059 dram_init: ddr_type: 0
505 22:52:47.826137 is_discrete_lpddr4: 1
506 22:52:47.829286 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 22:52:47.829373
508 22:52:47.829475
509 22:52:47.832689 [Bian_co] ETT version 0.0.0.1
510 22:52:47.838962 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 22:52:47.839065
512 22:52:47.842434 dramc_set_vcore_voltage set vcore to 650000
513 22:52:47.845471 Read voltage for 800, 4
514 22:52:47.845603 Vio18 = 0
515 22:52:47.845696 Vcore = 650000
516 22:52:47.845785 Vdram = 0
517 22:52:47.849350 Vddq = 0
518 22:52:47.849526 Vmddr = 0
519 22:52:47.852193 dram_init: config_dvfs: 1
520 22:52:47.855777 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 22:52:47.862556 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 22:52:47.865340 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 22:52:47.869037 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 22:52:47.872581 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 22:52:47.875548 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 22:52:47.879176 MEM_TYPE=3, freq_sel=18
527 22:52:47.882213 sv_algorithm_assistance_LP4_1600
528 22:52:47.885422 ============ PULL DRAM RESETB DOWN ============
529 22:52:47.888850 ========== PULL DRAM RESETB DOWN end =========
530 22:52:47.896073 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 22:52:47.898846 ===================================
532 22:52:47.902473 LPDDR4 DRAM CONFIGURATION
533 22:52:47.902561 ===================================
534 22:52:47.905915 EX_ROW_EN[0] = 0x0
535 22:52:47.909059 EX_ROW_EN[1] = 0x0
536 22:52:47.909196 LP4Y_EN = 0x0
537 22:52:47.912397 WORK_FSP = 0x0
538 22:52:47.912496 WL = 0x2
539 22:52:47.915853 RL = 0x2
540 22:52:47.915964 BL = 0x2
541 22:52:47.918794 RPST = 0x0
542 22:52:47.918920 RD_PRE = 0x0
543 22:52:47.922402 WR_PRE = 0x1
544 22:52:47.922520 WR_PST = 0x0
545 22:52:47.925542 DBI_WR = 0x0
546 22:52:47.925673 DBI_RD = 0x0
547 22:52:47.929216 OTF = 0x1
548 22:52:47.932853 ===================================
549 22:52:47.936236 ===================================
550 22:52:47.936424 ANA top config
551 22:52:47.939302 ===================================
552 22:52:47.942758 DLL_ASYNC_EN = 0
553 22:52:47.946439 ALL_SLAVE_EN = 1
554 22:52:47.949648 NEW_RANK_MODE = 1
555 22:52:47.949881 DLL_IDLE_MODE = 1
556 22:52:47.952946 LP45_APHY_COMB_EN = 1
557 22:52:47.956343 TX_ODT_DIS = 1
558 22:52:47.956711 NEW_8X_MODE = 1
559 22:52:47.959911 ===================================
560 22:52:47.963944 ===================================
561 22:52:47.967424 data_rate = 1600
562 22:52:47.970698 CKR = 1
563 22:52:47.974743 DQ_P2S_RATIO = 8
564 22:52:47.978275 ===================================
565 22:52:47.978718 CA_P2S_RATIO = 8
566 22:52:47.982083 DQ_CA_OPEN = 0
567 22:52:47.985364 DQ_SEMI_OPEN = 0
568 22:52:47.989006 CA_SEMI_OPEN = 0
569 22:52:47.989535 CA_FULL_RATE = 0
570 22:52:47.992961 DQ_CKDIV4_EN = 1
571 22:52:47.996568 CA_CKDIV4_EN = 1
572 22:52:47.999760 CA_PREDIV_EN = 0
573 22:52:48.000323 PH8_DLY = 0
574 22:52:48.003682 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 22:52:48.007277 DQ_AAMCK_DIV = 4
576 22:52:48.011237 CA_AAMCK_DIV = 4
577 22:52:48.011647 CA_ADMCK_DIV = 4
578 22:52:48.014728 DQ_TRACK_CA_EN = 0
579 22:52:48.018587 CA_PICK = 800
580 22:52:48.022355 CA_MCKIO = 800
581 22:52:48.022859 MCKIO_SEMI = 0
582 22:52:48.025897 PLL_FREQ = 3068
583 22:52:48.029278 DQ_UI_PI_RATIO = 32
584 22:52:48.033457 CA_UI_PI_RATIO = 0
585 22:52:48.037478 ===================================
586 22:52:48.041296 ===================================
587 22:52:48.041604 memory_type:LPDDR4
588 22:52:48.044968 GP_NUM : 10
589 22:52:48.045195 SRAM_EN : 1
590 22:52:48.047816 MD32_EN : 0
591 22:52:48.051371 ===================================
592 22:52:48.054661 [ANA_INIT] >>>>>>>>>>>>>>
593 22:52:48.054898 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 22:52:48.058033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 22:52:48.061340 ===================================
596 22:52:48.064216 data_rate = 1600,PCW = 0X7600
597 22:52:48.067697 ===================================
598 22:52:48.071032 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 22:52:48.077731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 22:52:48.084442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 22:52:48.087952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 22:52:48.091823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 22:52:48.095136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 22:52:48.095208 [ANA_INIT] flow start
605 22:52:48.098468 [ANA_INIT] PLL >>>>>>>>
606 22:52:48.102272 [ANA_INIT] PLL <<<<<<<<
607 22:52:48.102365 [ANA_INIT] MIDPI >>>>>>>>
608 22:52:48.105824 [ANA_INIT] MIDPI <<<<<<<<
609 22:52:48.109459 [ANA_INIT] DLL >>>>>>>>
610 22:52:48.109563 [ANA_INIT] flow end
611 22:52:48.112971 ============ LP4 DIFF to SE enter ============
612 22:52:48.116781 ============ LP4 DIFF to SE exit ============
613 22:52:48.120447 [ANA_INIT] <<<<<<<<<<<<<
614 22:52:48.123819 [Flow] Enable top DCM control >>>>>
615 22:52:48.127624 [Flow] Enable top DCM control <<<<<
616 22:52:48.131810 Enable DLL master slave shuffle
617 22:52:48.135147 ==============================================================
618 22:52:48.138564 Gating Mode config
619 22:52:48.142129 ==============================================================
620 22:52:48.145484 Config description:
621 22:52:48.155451 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 22:52:48.161819 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 22:52:48.165258 SELPH_MODE 0: By rank 1: By Phase
624 22:52:48.172128 ==============================================================
625 22:52:48.175651 GAT_TRACK_EN = 1
626 22:52:48.178616 RX_GATING_MODE = 2
627 22:52:48.182204 RX_GATING_TRACK_MODE = 2
628 22:52:48.182298 SELPH_MODE = 1
629 22:52:48.185470 PICG_EARLY_EN = 1
630 22:52:48.188857 VALID_LAT_VALUE = 1
631 22:52:48.195254 ==============================================================
632 22:52:48.198659 Enter into Gating configuration >>>>
633 22:52:48.201930 Exit from Gating configuration <<<<
634 22:52:48.205543 Enter into DVFS_PRE_config >>>>>
635 22:52:48.215198 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 22:52:48.218642 Exit from DVFS_PRE_config <<<<<
637 22:52:48.221992 Enter into PICG configuration >>>>
638 22:52:48.225460 Exit from PICG configuration <<<<
639 22:52:48.229013 [RX_INPUT] configuration >>>>>
640 22:52:48.232123 [RX_INPUT] configuration <<<<<
641 22:52:48.235847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 22:52:48.242100 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 22:52:48.248526 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 22:52:48.255295 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 22:52:48.258722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 22:52:48.265853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 22:52:48.268715 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 22:52:48.275774 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 22:52:48.279035 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 22:52:48.281965 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 22:52:48.285591 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 22:52:48.292073 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 22:52:48.295564 ===================================
654 22:52:48.296004 LPDDR4 DRAM CONFIGURATION
655 22:52:48.298810 ===================================
656 22:52:48.301943 EX_ROW_EN[0] = 0x0
657 22:52:48.305811 EX_ROW_EN[1] = 0x0
658 22:52:48.306250 LP4Y_EN = 0x0
659 22:52:48.309178 WORK_FSP = 0x0
660 22:52:48.309643 WL = 0x2
661 22:52:48.312034 RL = 0x2
662 22:52:48.312475 BL = 0x2
663 22:52:48.315292 RPST = 0x0
664 22:52:48.315736 RD_PRE = 0x0
665 22:52:48.318832 WR_PRE = 0x1
666 22:52:48.319268 WR_PST = 0x0
667 22:52:48.322337 DBI_WR = 0x0
668 22:52:48.322771 DBI_RD = 0x0
669 22:52:48.325722 OTF = 0x1
670 22:52:48.328625 ===================================
671 22:52:48.332020 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 22:52:48.335262 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 22:52:48.342290 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 22:52:48.345400 ===================================
675 22:52:48.345873 LPDDR4 DRAM CONFIGURATION
676 22:52:48.349072 ===================================
677 22:52:48.352183 EX_ROW_EN[0] = 0x10
678 22:52:48.352722 EX_ROW_EN[1] = 0x0
679 22:52:48.355828 LP4Y_EN = 0x0
680 22:52:48.356388 WORK_FSP = 0x0
681 22:52:48.358714 WL = 0x2
682 22:52:48.362221 RL = 0x2
683 22:52:48.362793 BL = 0x2
684 22:52:48.365427 RPST = 0x0
685 22:52:48.365989 RD_PRE = 0x0
686 22:52:48.369180 WR_PRE = 0x1
687 22:52:48.369793 WR_PST = 0x0
688 22:52:48.372307 DBI_WR = 0x0
689 22:52:48.372895 DBI_RD = 0x0
690 22:52:48.375538 OTF = 0x1
691 22:52:48.378946 ===================================
692 22:52:48.382308 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 22:52:48.387585 nWR fixed to 40
694 22:52:48.391254 [ModeRegInit_LP4] CH0 RK0
695 22:52:48.391713 [ModeRegInit_LP4] CH0 RK1
696 22:52:48.393967 [ModeRegInit_LP4] CH1 RK0
697 22:52:48.397843 [ModeRegInit_LP4] CH1 RK1
698 22:52:48.398144 match AC timing 13
699 22:52:48.404172 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 22:52:48.407463 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 22:52:48.410657 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 22:52:48.417590 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 22:52:48.420750 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 22:52:48.420838 [EMI DOE] emi_dcm 0
705 22:52:48.427436 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 22:52:48.427518 ==
707 22:52:48.430902 Dram Type= 6, Freq= 0, CH_0, rank 0
708 22:52:48.433733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 22:52:48.433816 ==
710 22:52:48.440736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 22:52:48.446919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 22:52:48.454848 [CA 0] Center 38 (7~69) winsize 63
713 22:52:48.458160 [CA 1] Center 37 (7~68) winsize 62
714 22:52:48.461405 [CA 2] Center 35 (5~66) winsize 62
715 22:52:48.464912 [CA 3] Center 35 (5~66) winsize 62
716 22:52:48.468120 [CA 4] Center 34 (4~65) winsize 62
717 22:52:48.471838 [CA 5] Center 34 (3~65) winsize 63
718 22:52:48.471947
719 22:52:48.475074 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 22:52:48.475184
721 22:52:48.478531 [CATrainingPosCal] consider 1 rank data
722 22:52:48.481635 u2DelayCellTimex100 = 270/100 ps
723 22:52:48.485178 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 22:52:48.488421 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 22:52:48.491738 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 22:52:48.498582 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 22:52:48.501682 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 22:52:48.505101 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
729 22:52:48.505184
730 22:52:48.508398 CA PerBit enable=1, Macro0, CA PI delay=34
731 22:52:48.508483
732 22:52:48.511836 [CBTSetCACLKResult] CA Dly = 34
733 22:52:48.511921 CS Dly: 5 (0~36)
734 22:52:48.512016 ==
735 22:52:48.515675 Dram Type= 6, Freq= 0, CH_0, rank 1
736 22:52:48.519084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 22:52:48.519167 ==
738 22:52:48.526396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 22:52:48.533171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 22:52:48.541263 [CA 0] Center 38 (7~69) winsize 63
741 22:52:48.544992 [CA 1] Center 37 (7~68) winsize 62
742 22:52:48.548606 [CA 2] Center 35 (5~66) winsize 62
743 22:52:48.552646 [CA 3] Center 35 (5~66) winsize 62
744 22:52:48.556581 [CA 4] Center 34 (4~65) winsize 62
745 22:52:48.559810 [CA 5] Center 34 (3~65) winsize 63
746 22:52:48.559920
747 22:52:48.563531 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 22:52:48.563616
749 22:52:48.567302 [CATrainingPosCal] consider 2 rank data
750 22:52:48.567388 u2DelayCellTimex100 = 270/100 ps
751 22:52:48.570733 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 22:52:48.574166 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 22:52:48.577936 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 22:52:48.581483 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 22:52:48.585443 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 22:52:48.588886 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
757 22:52:48.589012
758 22:52:48.596446 CA PerBit enable=1, Macro0, CA PI delay=34
759 22:52:48.596553
760 22:52:48.596628 [CBTSetCACLKResult] CA Dly = 34
761 22:52:48.600175 CS Dly: 6 (0~38)
762 22:52:48.600275
763 22:52:48.603851 ----->DramcWriteLeveling(PI) begin...
764 22:52:48.603927 ==
765 22:52:48.607618 Dram Type= 6, Freq= 0, CH_0, rank 0
766 22:52:48.611112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 22:52:48.611190 ==
768 22:52:48.615230 Write leveling (Byte 0): 32 => 32
769 22:52:48.615337 Write leveling (Byte 1): 29 => 29
770 22:52:48.619213 DramcWriteLeveling(PI) end<-----
771 22:52:48.619328
772 22:52:48.619425 ==
773 22:52:48.623100 Dram Type= 6, Freq= 0, CH_0, rank 0
774 22:52:48.627117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 22:52:48.627193 ==
776 22:52:48.630393 [Gating] SW mode calibration
777 22:52:48.638395 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 22:52:48.641983 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 22:52:48.645365 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 22:52:48.652937 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 22:52:48.656976 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
782 22:52:48.660392 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 22:52:48.664095 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 22:52:48.667302 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 22:52:48.675166 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 22:52:48.678950 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 22:52:48.682438 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 22:52:48.685942 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:52:48.689769 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:52:48.697301 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:52:48.700703 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:52:48.704447 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:52:48.707735 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:52:48.711249 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:52:48.718678 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:52:48.722730 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:52:48.726624 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
798 22:52:48.730150 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 22:52:48.733999 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:52:48.740921 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:52:48.744979 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:52:48.748583 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:52:48.751874 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:52:48.755933 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:52:48.763425 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
806 22:52:48.766741 0 9 12 | B1->B0 | 2828 3131 | 1 1 | (1 1) (1 1)
807 22:52:48.770805 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
808 22:52:48.774058 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 22:52:48.777723 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 22:52:48.781704 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 22:52:48.788669 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 22:52:48.792090 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 22:52:48.796201 0 10 8 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 1)
814 22:52:48.800107 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
815 22:52:48.804007 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:52:48.810837 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:52:48.814743 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:52:48.818719 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:52:48.822180 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 22:52:48.825751 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:52:48.833133 0 11 8 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
822 22:52:48.837143 0 11 12 | B1->B0 | 3030 4141 | 0 1 | (0 0) (0 0)
823 22:52:48.840728 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
824 22:52:48.844064 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 22:52:48.850796 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 22:52:48.853961 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 22:52:48.857352 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 22:52:48.860957 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 22:52:48.867566 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
830 22:52:48.870837 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
831 22:52:48.874336 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 22:52:48.880800 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 22:52:48.884225 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 22:52:48.887488 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 22:52:48.894066 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 22:52:48.897442 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:52:48.900626 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:52:48.907398 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:52:48.910683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:52:48.914122 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:52:48.920585 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:52:48.924026 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:52:48.927365 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:52:48.934286 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:52:48.937159 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:52:48.940748 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 22:52:48.944260 Total UI for P1: 0, mck2ui 16
848 22:52:48.947414 best dqsien dly found for B0: ( 0, 14, 10)
849 22:52:48.950922 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 22:52:48.954197 Total UI for P1: 0, mck2ui 16
851 22:52:48.957312 best dqsien dly found for B1: ( 0, 14, 12)
852 22:52:48.960564 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
853 22:52:48.967396 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 22:52:48.967479
855 22:52:48.970589 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 22:52:48.973843 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 22:52:48.977423 [Gating] SW calibration Done
858 22:52:48.977557 ==
859 22:52:48.980719 Dram Type= 6, Freq= 0, CH_0, rank 0
860 22:52:48.983963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 22:52:48.984042 ==
862 22:52:48.987639 RX Vref Scan: 0
863 22:52:48.987711
864 22:52:48.987773 RX Vref 0 -> 0, step: 1
865 22:52:48.987833
866 22:52:48.990957 RX Delay -130 -> 252, step: 16
867 22:52:48.993922 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 22:52:49.000638 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
869 22:52:49.003867 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 22:52:49.007528 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 22:52:49.010606 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
872 22:52:49.013827 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 22:52:49.017283 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 22:52:49.023956 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 22:52:49.027470 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 22:52:49.030737 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 22:52:49.034213 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 22:52:49.037097 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 22:52:49.044141 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 22:52:49.047495 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 22:52:49.050581 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 22:52:49.054382 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 22:52:49.054465 ==
884 22:52:49.057219 Dram Type= 6, Freq= 0, CH_0, rank 0
885 22:52:49.063901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 22:52:49.063985 ==
887 22:52:49.064051 DQS Delay:
888 22:52:49.067194 DQS0 = 0, DQS1 = 0
889 22:52:49.067277 DQM Delay:
890 22:52:49.067343 DQM0 = 79, DQM1 = 69
891 22:52:49.070620 DQ Delay:
892 22:52:49.074053 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
893 22:52:49.077473 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
894 22:52:49.080794 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 22:52:49.084565 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 22:52:49.084648
897 22:52:49.084712
898 22:52:49.084773 ==
899 22:52:49.088379 Dram Type= 6, Freq= 0, CH_0, rank 0
900 22:52:49.091515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 22:52:49.091598 ==
902 22:52:49.091670
903 22:52:49.091741
904 22:52:49.094740 TX Vref Scan disable
905 22:52:49.094823 == TX Byte 0 ==
906 22:52:49.098111 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 22:52:49.104881 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 22:52:49.104994 == TX Byte 1 ==
909 22:52:49.108047 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
910 22:52:49.114917 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
911 22:52:49.115000 ==
912 22:52:49.117925 Dram Type= 6, Freq= 0, CH_0, rank 0
913 22:52:49.121194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 22:52:49.121306 ==
915 22:52:49.134563 TX Vref=22, minBit 5, minWin=26, winSum=432
916 22:52:49.138469 TX Vref=24, minBit 1, minWin=27, winSum=439
917 22:52:49.141813 TX Vref=26, minBit 5, minWin=27, winSum=440
918 22:52:49.144599 TX Vref=28, minBit 2, minWin=27, winSum=442
919 22:52:49.147954 TX Vref=30, minBit 10, minWin=27, winSum=444
920 22:52:49.154947 TX Vref=32, minBit 10, minWin=26, winSum=439
921 22:52:49.157903 [TxChooseVref] Worse bit 10, Min win 27, Win sum 444, Final Vref 30
922 22:52:49.157987
923 22:52:49.161165 Final TX Range 1 Vref 30
924 22:52:49.161275
925 22:52:49.161384 ==
926 22:52:49.164593 Dram Type= 6, Freq= 0, CH_0, rank 0
927 22:52:49.168138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 22:52:49.171423 ==
929 22:52:49.171505
930 22:52:49.171570
931 22:52:49.171630 TX Vref Scan disable
932 22:52:49.174942 == TX Byte 0 ==
933 22:52:49.178595 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
934 22:52:49.181920 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
935 22:52:49.185270 == TX Byte 1 ==
936 22:52:49.188181 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
937 22:52:49.192222 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
938 22:52:49.192305
939 22:52:49.194991 [DATLAT]
940 22:52:49.195074 Freq=800, CH0 RK0
941 22:52:49.195140
942 22:52:49.198410 DATLAT Default: 0xa
943 22:52:49.198507 0, 0xFFFF, sum = 0
944 22:52:49.201788 1, 0xFFFF, sum = 0
945 22:52:49.201875 2, 0xFFFF, sum = 0
946 22:52:49.204964 3, 0xFFFF, sum = 0
947 22:52:49.205049 4, 0xFFFF, sum = 0
948 22:52:49.208664 5, 0xFFFF, sum = 0
949 22:52:49.208749 6, 0xFFFF, sum = 0
950 22:52:49.211623 7, 0xFFFF, sum = 0
951 22:52:49.215018 8, 0xFFFF, sum = 0
952 22:52:49.215157 9, 0x0, sum = 1
953 22:52:49.215252 10, 0x0, sum = 2
954 22:52:49.218254 11, 0x0, sum = 3
955 22:52:49.218337 12, 0x0, sum = 4
956 22:52:49.221482 best_step = 10
957 22:52:49.221593
958 22:52:49.221660 ==
959 22:52:49.225145 Dram Type= 6, Freq= 0, CH_0, rank 0
960 22:52:49.228464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 22:52:49.228548 ==
962 22:52:49.231637 RX Vref Scan: 1
963 22:52:49.231720
964 22:52:49.231785 Set Vref Range= 32 -> 127
965 22:52:49.231845
966 22:52:49.234896 RX Vref 32 -> 127, step: 1
967 22:52:49.234978
968 22:52:49.238263 RX Delay -111 -> 252, step: 8
969 22:52:49.238345
970 22:52:49.241839 Set Vref, RX VrefLevel [Byte0]: 32
971 22:52:49.245387 [Byte1]: 32
972 22:52:49.245495
973 22:52:49.248310 Set Vref, RX VrefLevel [Byte0]: 33
974 22:52:49.251669 [Byte1]: 33
975 22:52:49.255652
976 22:52:49.255735 Set Vref, RX VrefLevel [Byte0]: 34
977 22:52:49.258669 [Byte1]: 34
978 22:52:49.263018
979 22:52:49.263100 Set Vref, RX VrefLevel [Byte0]: 35
980 22:52:49.266599 [Byte1]: 35
981 22:52:49.270923
982 22:52:49.271004 Set Vref, RX VrefLevel [Byte0]: 36
983 22:52:49.274171 [Byte1]: 36
984 22:52:49.278259
985 22:52:49.278367 Set Vref, RX VrefLevel [Byte0]: 37
986 22:52:49.281665 [Byte1]: 37
987 22:52:49.285771
988 22:52:49.285854 Set Vref, RX VrefLevel [Byte0]: 38
989 22:52:49.289202 [Byte1]: 38
990 22:52:49.293863
991 22:52:49.293944 Set Vref, RX VrefLevel [Byte0]: 39
992 22:52:49.296750 [Byte1]: 39
993 22:52:49.301394
994 22:52:49.301476 Set Vref, RX VrefLevel [Byte0]: 40
995 22:52:49.304788 [Byte1]: 40
996 22:52:49.308666
997 22:52:49.308753 Set Vref, RX VrefLevel [Byte0]: 41
998 22:52:49.312185 [Byte1]: 41
999 22:52:49.316418
1000 22:52:49.316500 Set Vref, RX VrefLevel [Byte0]: 42
1001 22:52:49.320237 [Byte1]: 42
1002 22:52:49.324306
1003 22:52:49.324388 Set Vref, RX VrefLevel [Byte0]: 43
1004 22:52:49.327510 [Byte1]: 43
1005 22:52:49.331881
1006 22:52:49.331965 Set Vref, RX VrefLevel [Byte0]: 44
1007 22:52:49.335109 [Byte1]: 44
1008 22:52:49.339666
1009 22:52:49.339747 Set Vref, RX VrefLevel [Byte0]: 45
1010 22:52:49.343256 [Byte1]: 45
1011 22:52:49.347323
1012 22:52:49.347406 Set Vref, RX VrefLevel [Byte0]: 46
1013 22:52:49.351163 [Byte1]: 46
1014 22:52:49.355450
1015 22:52:49.355534 Set Vref, RX VrefLevel [Byte0]: 47
1016 22:52:49.359094 [Byte1]: 47
1017 22:52:49.363170
1018 22:52:49.363260 Set Vref, RX VrefLevel [Byte0]: 48
1019 22:52:49.365960 [Byte1]: 48
1020 22:52:49.370111
1021 22:52:49.370193 Set Vref, RX VrefLevel [Byte0]: 49
1022 22:52:49.373552 [Byte1]: 49
1023 22:52:49.378096
1024 22:52:49.378179 Set Vref, RX VrefLevel [Byte0]: 50
1025 22:52:49.381344 [Byte1]: 50
1026 22:52:49.385188
1027 22:52:49.385270 Set Vref, RX VrefLevel [Byte0]: 51
1028 22:52:49.388670 [Byte1]: 51
1029 22:52:49.393445
1030 22:52:49.393592 Set Vref, RX VrefLevel [Byte0]: 52
1031 22:52:49.396484 [Byte1]: 52
1032 22:52:49.400538
1033 22:52:49.400620 Set Vref, RX VrefLevel [Byte0]: 53
1034 22:52:49.403967 [Byte1]: 53
1035 22:52:49.408505
1036 22:52:49.408586 Set Vref, RX VrefLevel [Byte0]: 54
1037 22:52:49.411946 [Byte1]: 54
1038 22:52:49.415934
1039 22:52:49.416015 Set Vref, RX VrefLevel [Byte0]: 55
1040 22:52:49.419362 [Byte1]: 55
1041 22:52:49.423850
1042 22:52:49.423957 Set Vref, RX VrefLevel [Byte0]: 56
1043 22:52:49.427065 [Byte1]: 56
1044 22:52:49.431122
1045 22:52:49.431205 Set Vref, RX VrefLevel [Byte0]: 57
1046 22:52:49.434236 [Byte1]: 57
1047 22:52:49.439030
1048 22:52:49.439124 Set Vref, RX VrefLevel [Byte0]: 58
1049 22:52:49.441900 [Byte1]: 58
1050 22:52:49.446683
1051 22:52:49.446767 Set Vref, RX VrefLevel [Byte0]: 59
1052 22:52:49.449779 [Byte1]: 59
1053 22:52:49.453992
1054 22:52:49.454076 Set Vref, RX VrefLevel [Byte0]: 60
1055 22:52:49.457386 [Byte1]: 60
1056 22:52:49.462107
1057 22:52:49.462209 Set Vref, RX VrefLevel [Byte0]: 61
1058 22:52:49.464842 [Byte1]: 61
1059 22:52:49.469489
1060 22:52:49.469619 Set Vref, RX VrefLevel [Byte0]: 62
1061 22:52:49.472562 [Byte1]: 62
1062 22:52:49.477226
1063 22:52:49.477311 Set Vref, RX VrefLevel [Byte0]: 63
1064 22:52:49.480098 [Byte1]: 63
1065 22:52:49.484598
1066 22:52:49.484691 Set Vref, RX VrefLevel [Byte0]: 64
1067 22:52:49.488419 [Byte1]: 64
1068 22:52:49.492337
1069 22:52:49.492468 Set Vref, RX VrefLevel [Byte0]: 65
1070 22:52:49.495564 [Byte1]: 65
1071 22:52:49.500244
1072 22:52:49.500351 Set Vref, RX VrefLevel [Byte0]: 66
1073 22:52:49.503676 [Byte1]: 66
1074 22:52:49.507656
1075 22:52:49.507738 Set Vref, RX VrefLevel [Byte0]: 67
1076 22:52:49.511088 [Byte1]: 67
1077 22:52:49.515552
1078 22:52:49.515659 Set Vref, RX VrefLevel [Byte0]: 68
1079 22:52:49.518810 [Byte1]: 68
1080 22:52:49.523028
1081 22:52:49.523132 Set Vref, RX VrefLevel [Byte0]: 69
1082 22:52:49.526194 [Byte1]: 69
1083 22:52:49.530672
1084 22:52:49.530784 Set Vref, RX VrefLevel [Byte0]: 70
1085 22:52:49.533748 [Byte1]: 70
1086 22:52:49.538100
1087 22:52:49.538213 Set Vref, RX VrefLevel [Byte0]: 71
1088 22:52:49.541795 [Byte1]: 71
1089 22:52:49.545811
1090 22:52:49.545912 Set Vref, RX VrefLevel [Byte0]: 72
1091 22:52:49.549377 [Byte1]: 72
1092 22:52:49.553404
1093 22:52:49.553537 Set Vref, RX VrefLevel [Byte0]: 73
1094 22:52:49.556683 [Byte1]: 73
1095 22:52:49.561378
1096 22:52:49.561493 Set Vref, RX VrefLevel [Byte0]: 74
1097 22:52:49.564358 [Byte1]: 74
1098 22:52:49.568720
1099 22:52:49.568804 Set Vref, RX VrefLevel [Byte0]: 75
1100 22:52:49.572133 [Byte1]: 75
1101 22:52:49.576630
1102 22:52:49.576712 Set Vref, RX VrefLevel [Byte0]: 76
1103 22:52:49.579770 [Byte1]: 76
1104 22:52:49.584319
1105 22:52:49.584400 Set Vref, RX VrefLevel [Byte0]: 77
1106 22:52:49.587526 [Byte1]: 77
1107 22:52:49.592161
1108 22:52:49.592269 Set Vref, RX VrefLevel [Byte0]: 78
1109 22:52:49.595044 [Byte1]: 78
1110 22:52:49.599283
1111 22:52:49.599364 Set Vref, RX VrefLevel [Byte0]: 79
1112 22:52:49.602834 [Byte1]: 79
1113 22:52:49.606904
1114 22:52:49.606986 Final RX Vref Byte 0 = 59 to rank0
1115 22:52:49.610429 Final RX Vref Byte 1 = 56 to rank0
1116 22:52:49.613847 Final RX Vref Byte 0 = 59 to rank1
1117 22:52:49.617104 Final RX Vref Byte 1 = 56 to rank1==
1118 22:52:49.620948 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 22:52:49.627229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 22:52:49.627695 ==
1121 22:52:49.628060 DQS Delay:
1122 22:52:49.628400 DQS0 = 0, DQS1 = 0
1123 22:52:49.630648 DQM Delay:
1124 22:52:49.631110 DQM0 = 81, DQM1 = 67
1125 22:52:49.634040 DQ Delay:
1126 22:52:49.637663 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 22:52:49.638130 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1128 22:52:49.640801 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 22:52:49.644149 DQ12 =72, DQ13 =68, DQ14 =76, DQ15 =76
1130 22:52:49.647363
1131 22:52:49.647890
1132 22:52:49.654244 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1133 22:52:49.657583 CH0 RK0: MR19=606, MR18=2C2B
1134 22:52:49.664428 CH0_RK0: MR19=0x606, MR18=0x2C2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1135 22:52:49.665124
1136 22:52:49.667871 ----->DramcWriteLeveling(PI) begin...
1137 22:52:49.668578 ==
1138 22:52:49.670999 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 22:52:49.674537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 22:52:49.675012 ==
1141 22:52:49.677865 Write leveling (Byte 0): 33 => 33
1142 22:52:49.681075 Write leveling (Byte 1): 32 => 32
1143 22:52:49.684546 DramcWriteLeveling(PI) end<-----
1144 22:52:49.684999
1145 22:52:49.685350 ==
1146 22:52:49.687901 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 22:52:49.691240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 22:52:49.691682 ==
1149 22:52:49.694108 [Gating] SW mode calibration
1150 22:52:49.701025 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 22:52:49.707809 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 22:52:49.710876 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 22:52:49.714153 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 22:52:49.721127 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1155 22:52:49.724009 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:52:49.727462 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:52:49.734246 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:52:49.737619 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:52:49.740904 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:52:49.747269 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:52:49.750851 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:52:49.754212 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:52:49.757766 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:52:49.764422 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:52:49.808779 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:52:49.809261 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:52:49.809708 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:52:49.810500 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:52:49.810901 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1170 22:52:49.811233 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 22:52:49.811619 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:52:49.811981 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:52:49.812324 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:52:49.812653 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:52:49.813382 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:52:49.816891 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:52:49.820137 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:52:49.823718 0 9 8 | B1->B0 | 2323 2c2c | 1 1 | (1 1) (1 1)
1179 22:52:49.830373 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1180 22:52:49.833747 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 22:52:49.837244 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 22:52:49.843553 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 22:52:49.846810 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 22:52:49.850147 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:52:49.856980 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1186 22:52:49.860306 0 10 8 | B1->B0 | 3232 2a2a | 0 1 | (0 0) (1 0)
1187 22:52:49.863326 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1188 22:52:49.870007 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:52:49.873156 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:52:49.876645 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 22:52:49.883433 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:52:49.886337 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:52:49.889836 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:52:49.893098 0 11 8 | B1->B0 | 2b2b 3838 | 0 0 | (0 0) (0 0)
1195 22:52:49.899710 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1196 22:52:49.903558 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 22:52:49.906417 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 22:52:49.913278 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 22:52:49.916576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 22:52:49.920504 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:52:49.927399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 22:52:49.930404 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 22:52:49.934713 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1204 22:52:49.937798 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:52:49.944420 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:52:49.947780 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:52:49.951646 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:52:49.955205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:52:49.961773 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:52:49.965000 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:52:49.968591 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:52:49.975206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:52:49.978527 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:52:49.982108 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:52:49.988446 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:52:49.991975 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:52:49.994819 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1218 22:52:50.001750 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 22:52:50.005288 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1220 22:52:50.008169 Total UI for P1: 0, mck2ui 16
1221 22:52:50.011649 best dqsien dly found for B0: ( 0, 14, 6)
1222 22:52:50.015443 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 22:52:50.018623 Total UI for P1: 0, mck2ui 16
1224 22:52:50.021963 best dqsien dly found for B1: ( 0, 14, 10)
1225 22:52:50.025429 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1226 22:52:50.028259 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1227 22:52:50.028337
1228 22:52:50.031857 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1229 22:52:50.038611 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1230 22:52:50.038694 [Gating] SW calibration Done
1231 22:52:50.038760 ==
1232 22:52:50.041896 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 22:52:50.048340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 22:52:50.048429 ==
1235 22:52:50.048496 RX Vref Scan: 0
1236 22:52:50.048560
1237 22:52:50.051488 RX Vref 0 -> 0, step: 1
1238 22:52:50.051567
1239 22:52:50.054961 RX Delay -130 -> 252, step: 16
1240 22:52:50.058166 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1241 22:52:50.061492 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1242 22:52:50.064939 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1243 22:52:50.071554 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1244 22:52:50.075220 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1245 22:52:50.078238 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1246 22:52:50.082013 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1247 22:52:50.084990 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1248 22:52:50.091476 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1249 22:52:50.094849 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1250 22:52:50.098242 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1251 22:52:50.101699 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1252 22:52:50.105265 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1253 22:52:50.111465 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1254 22:52:50.114833 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1255 22:52:50.118264 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1256 22:52:50.118347 ==
1257 22:52:50.121415 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 22:52:50.125023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 22:52:50.125098 ==
1260 22:52:50.128326 DQS Delay:
1261 22:52:50.128399 DQS0 = 0, DQS1 = 0
1262 22:52:50.131604 DQM Delay:
1263 22:52:50.131703 DQM0 = 77, DQM1 = 71
1264 22:52:50.131790 DQ Delay:
1265 22:52:50.135146 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1266 22:52:50.137983 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
1267 22:52:50.141343 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
1268 22:52:50.144881 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1269 22:52:50.144989
1270 22:52:50.145081
1271 22:52:50.147895 ==
1272 22:52:50.147978 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 22:52:50.154827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 22:52:50.154930 ==
1275 22:52:50.155026
1276 22:52:50.155119
1277 22:52:50.158351 TX Vref Scan disable
1278 22:52:50.158423 == TX Byte 0 ==
1279 22:52:50.160991 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1280 22:52:50.167904 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1281 22:52:50.167982 == TX Byte 1 ==
1282 22:52:50.171336 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1283 22:52:50.177987 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1284 22:52:50.178072 ==
1285 22:52:50.181127 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 22:52:50.184398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 22:52:50.184506 ==
1288 22:52:50.197894 TX Vref=22, minBit 1, minWin=27, winSum=437
1289 22:52:50.201259 TX Vref=24, minBit 1, minWin=27, winSum=441
1290 22:52:50.204156 TX Vref=26, minBit 1, minWin=27, winSum=439
1291 22:52:50.207757 TX Vref=28, minBit 1, minWin=27, winSum=443
1292 22:52:50.211229 TX Vref=30, minBit 1, minWin=27, winSum=441
1293 22:52:50.214735 TX Vref=32, minBit 10, minWin=27, winSum=444
1294 22:52:50.221061 [TxChooseVref] Worse bit 10, Min win 27, Win sum 444, Final Vref 32
1295 22:52:50.221144
1296 22:52:50.224571 Final TX Range 1 Vref 32
1297 22:52:50.224653
1298 22:52:50.224717 ==
1299 22:52:50.228085 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 22:52:50.231121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 22:52:50.231196 ==
1302 22:52:50.234511
1303 22:52:50.234623
1304 22:52:50.234715 TX Vref Scan disable
1305 22:52:50.237536 == TX Byte 0 ==
1306 22:52:50.240890 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1307 22:52:50.247753 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1308 22:52:50.247859 == TX Byte 1 ==
1309 22:52:50.251174 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1310 22:52:50.257433 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1311 22:52:50.257576
1312 22:52:50.257668 [DATLAT]
1313 22:52:50.257755 Freq=800, CH0 RK1
1314 22:52:50.257845
1315 22:52:50.261121 DATLAT Default: 0xa
1316 22:52:50.261216 0, 0xFFFF, sum = 0
1317 22:52:50.264440 1, 0xFFFF, sum = 0
1318 22:52:50.264520 2, 0xFFFF, sum = 0
1319 22:52:50.267915 3, 0xFFFF, sum = 0
1320 22:52:50.267996 4, 0xFFFF, sum = 0
1321 22:52:50.271185 5, 0xFFFF, sum = 0
1322 22:52:50.274737 6, 0xFFFF, sum = 0
1323 22:52:50.274818 7, 0xFFFF, sum = 0
1324 22:52:50.277886 8, 0xFFFF, sum = 0
1325 22:52:50.277966 9, 0x0, sum = 1
1326 22:52:50.278030 10, 0x0, sum = 2
1327 22:52:50.280948 11, 0x0, sum = 3
1328 22:52:50.281028 12, 0x0, sum = 4
1329 22:52:50.284290 best_step = 10
1330 22:52:50.284380
1331 22:52:50.284472 ==
1332 22:52:50.287542 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 22:52:50.290825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 22:52:50.290898 ==
1335 22:52:50.294216 RX Vref Scan: 0
1336 22:52:50.294318
1337 22:52:50.294412 RX Vref 0 -> 0, step: 1
1338 22:52:50.294488
1339 22:52:50.297681 RX Delay -111 -> 252, step: 8
1340 22:52:50.304447 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1341 22:52:50.308098 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1342 22:52:50.311362 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1343 22:52:50.314942 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1344 22:52:50.317819 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1345 22:52:50.324552 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1346 22:52:50.328204 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1347 22:52:50.331087 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1348 22:52:50.334422 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1349 22:52:50.337845 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1350 22:52:50.344725 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1351 22:52:50.347865 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1352 22:52:50.351543 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1353 22:52:50.354543 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1354 22:52:50.357864 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1355 22:52:50.364368 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1356 22:52:50.364471 ==
1357 22:52:50.367932 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 22:52:50.371338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 22:52:50.371419 ==
1360 22:52:50.371482 DQS Delay:
1361 22:52:50.374683 DQS0 = 0, DQS1 = 0
1362 22:52:50.374762 DQM Delay:
1363 22:52:50.377929 DQM0 = 79, DQM1 = 68
1364 22:52:50.378009 DQ Delay:
1365 22:52:50.381451 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1366 22:52:50.384814 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1367 22:52:50.387821 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1368 22:52:50.391583 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1369 22:52:50.391730
1370 22:52:50.391797
1371 22:52:50.398145 [DQSOSCAuto] RK1, (LSB)MR18= 0x4925, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1372 22:52:50.401179 CH0 RK1: MR19=606, MR18=4925
1373 22:52:50.408565 CH0_RK1: MR19=0x606, MR18=0x4925, DQSOSC=391, MR23=63, INC=96, DEC=64
1374 22:52:50.411079 [RxdqsGatingPostProcess] freq 800
1375 22:52:50.417868 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 22:52:50.421330 Pre-setting of DQS Precalculation
1377 22:52:50.424726 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 22:52:50.424805 ==
1379 22:52:50.428126 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 22:52:50.431082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 22:52:50.431162 ==
1382 22:52:50.437914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 22:52:50.444226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 22:52:50.452789 [CA 0] Center 36 (6~67) winsize 62
1385 22:52:50.456218 [CA 1] Center 37 (7~67) winsize 61
1386 22:52:50.459390 [CA 2] Center 34 (4~64) winsize 61
1387 22:52:50.462668 [CA 3] Center 34 (4~64) winsize 61
1388 22:52:50.466189 [CA 4] Center 34 (5~64) winsize 60
1389 22:52:50.469760 [CA 5] Center 34 (4~64) winsize 61
1390 22:52:50.469840
1391 22:52:50.472856 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1392 22:52:50.472935
1393 22:52:50.476114 [CATrainingPosCal] consider 1 rank data
1394 22:52:50.479614 u2DelayCellTimex100 = 270/100 ps
1395 22:52:50.482668 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 22:52:50.486111 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1397 22:52:50.493050 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 22:52:50.496204 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 22:52:50.499646 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1400 22:52:50.503130 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 22:52:50.503210
1402 22:52:50.506047 CA PerBit enable=1, Macro0, CA PI delay=34
1403 22:52:50.506128
1404 22:52:50.509301 [CBTSetCACLKResult] CA Dly = 34
1405 22:52:50.509381 CS Dly: 5 (0~36)
1406 22:52:50.509445 ==
1407 22:52:50.512618 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 22:52:50.519243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 22:52:50.519323 ==
1410 22:52:50.522919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 22:52:50.529913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 22:52:50.539110 [CA 0] Center 36 (6~67) winsize 62
1413 22:52:50.542027 [CA 1] Center 36 (6~67) winsize 62
1414 22:52:50.545643 [CA 2] Center 34 (4~65) winsize 62
1415 22:52:50.548650 [CA 3] Center 33 (3~64) winsize 62
1416 22:52:50.552504 [CA 4] Center 34 (4~65) winsize 62
1417 22:52:50.555355 [CA 5] Center 33 (3~64) winsize 62
1418 22:52:50.555443
1419 22:52:50.559217 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1420 22:52:50.559296
1421 22:52:50.562148 [CATrainingPosCal] consider 2 rank data
1422 22:52:50.565407 u2DelayCellTimex100 = 270/100 ps
1423 22:52:50.568763 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 22:52:50.572255 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1425 22:52:50.578953 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 22:52:50.582747 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 22:52:50.586528 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1428 22:52:50.589848 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 22:52:50.589927
1430 22:52:50.593673 CA PerBit enable=1, Macro0, CA PI delay=34
1431 22:52:50.593762
1432 22:52:50.593831 [CBTSetCACLKResult] CA Dly = 34
1433 22:52:50.597098 CS Dly: 6 (0~38)
1434 22:52:50.597177
1435 22:52:50.600866 ----->DramcWriteLeveling(PI) begin...
1436 22:52:50.600973 ==
1437 22:52:50.604808 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 22:52:50.608297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 22:52:50.608371 ==
1440 22:52:50.611847 Write leveling (Byte 0): 26 => 26
1441 22:52:50.615644 Write leveling (Byte 1): 31 => 31
1442 22:52:50.618999 DramcWriteLeveling(PI) end<-----
1443 22:52:50.619074
1444 22:52:50.619136 ==
1445 22:52:50.622311 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 22:52:50.625765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 22:52:50.625846 ==
1448 22:52:50.628948 [Gating] SW mode calibration
1449 22:52:50.636145 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 22:52:50.639089 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 22:52:50.646084 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 22:52:50.649402 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1453 22:52:50.652590 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 22:52:50.659274 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:52:50.662604 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:52:50.666125 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:52:50.672758 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:52:50.676064 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:52:50.679541 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:52:50.685795 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:52:50.689181 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:52:50.692832 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:52:50.699149 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:52:50.702505 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:52:50.705868 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:52:50.708948 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:52:50.716037 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:52:50.719626 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1469 22:52:50.722495 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1470 22:52:50.729081 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:52:50.732518 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:52:50.735940 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:52:50.742513 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:52:50.745799 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:52:50.749127 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:52:50.755792 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:52:50.758632 0 9 8 | B1->B0 | 2727 2727 | 1 0 | (0 0) (0 0)
1478 22:52:50.762086 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 22:52:50.768647 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 22:52:50.772010 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:52:50.775384 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:52:50.782237 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 22:52:50.785671 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 22:52:50.788658 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1485 22:52:50.795603 0 10 8 | B1->B0 | 2b2b 2828 | 0 0 | (1 0) (1 0)
1486 22:52:50.798986 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:52:50.802442 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:52:50.808922 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:52:50.812143 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:52:50.815717 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:52:50.822174 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:52:50.825429 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1493 22:52:50.828759 0 11 8 | B1->B0 | 3232 3939 | 0 1 | (1 1) (1 1)
1494 22:52:50.832169 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 22:52:50.838852 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:52:50.842317 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:52:50.845797 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:52:50.852180 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 22:52:50.855653 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 22:52:50.858564 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1501 22:52:50.865305 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 22:52:50.868717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:52:50.871850 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:52:50.879077 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:52:50.881780 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:52:50.885686 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:52:50.892519 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:52:50.895273 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:52:50.898687 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:52:50.905297 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:52:50.908646 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:52:50.912197 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:52:50.915509 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:52:50.922428 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:52:50.925748 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:52:50.928627 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 22:52:50.935504 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 22:52:50.939151 Total UI for P1: 0, mck2ui 16
1519 22:52:50.942333 best dqsien dly found for B0: ( 0, 14, 4)
1520 22:52:50.945790 Total UI for P1: 0, mck2ui 16
1521 22:52:50.949269 best dqsien dly found for B1: ( 0, 14, 4)
1522 22:52:50.952589 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1523 22:52:50.955847 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1524 22:52:50.955971
1525 22:52:50.959192 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 22:52:50.962647 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1527 22:52:50.965483 [Gating] SW calibration Done
1528 22:52:50.965599 ==
1529 22:52:50.968796 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 22:52:50.972348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 22:52:50.972459 ==
1532 22:52:50.975961 RX Vref Scan: 0
1533 22:52:50.976079
1534 22:52:50.976185 RX Vref 0 -> 0, step: 1
1535 22:52:50.976280
1536 22:52:50.979023 RX Delay -130 -> 252, step: 16
1537 22:52:50.982533 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1538 22:52:50.989265 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1539 22:52:50.992432 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1540 22:52:50.995931 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1541 22:52:50.999447 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1542 22:52:51.002730 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1543 22:52:51.009814 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1544 22:52:51.012746 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1545 22:52:51.016052 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1546 22:52:51.019534 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1547 22:52:51.022693 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1548 22:52:51.029769 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1549 22:52:51.032587 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1550 22:52:51.036168 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1551 22:52:51.039586 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1552 22:52:51.042711 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1553 22:52:51.043139 ==
1554 22:52:51.046274 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 22:52:51.052676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 22:52:51.053115 ==
1557 22:52:51.053656 DQS Delay:
1558 22:52:51.056275 DQS0 = 0, DQS1 = 0
1559 22:52:51.056826 DQM Delay:
1560 22:52:51.057185 DQM0 = 79, DQM1 = 70
1561 22:52:51.059745 DQ Delay:
1562 22:52:51.062760 DQ0 =77, DQ1 =77, DQ2 =61, DQ3 =77
1563 22:52:51.066153 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1564 22:52:51.069606 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1565 22:52:51.073181 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1566 22:52:51.073830
1567 22:52:51.074264
1568 22:52:51.074673 ==
1569 22:52:51.075991 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 22:52:51.079532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 22:52:51.080134 ==
1572 22:52:51.080679
1573 22:52:51.081194
1574 22:52:51.082907 TX Vref Scan disable
1575 22:52:51.083523 == TX Byte 0 ==
1576 22:52:51.089704 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1577 22:52:51.092989 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1578 22:52:51.093637 == TX Byte 1 ==
1579 22:52:51.099527 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1580 22:52:51.102880 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1581 22:52:51.103493 ==
1582 22:52:51.106413 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 22:52:51.109609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 22:52:51.110062 ==
1585 22:52:51.123805 TX Vref=22, minBit 1, minWin=27, winSum=445
1586 22:52:51.127110 TX Vref=24, minBit 1, minWin=27, winSum=448
1587 22:52:51.130547 TX Vref=26, minBit 0, minWin=28, winSum=451
1588 22:52:51.133967 TX Vref=28, minBit 1, minWin=27, winSum=451
1589 22:52:51.137287 TX Vref=30, minBit 4, minWin=28, winSum=456
1590 22:52:51.144207 TX Vref=32, minBit 6, minWin=27, winSum=451
1591 22:52:51.147071 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 30
1592 22:52:51.147532
1593 22:52:51.150456 Final TX Range 1 Vref 30
1594 22:52:51.150896
1595 22:52:51.151231 ==
1596 22:52:51.153892 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 22:52:51.157329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 22:52:51.157811 ==
1599 22:52:51.160479
1600 22:52:51.160906
1601 22:52:51.161389 TX Vref Scan disable
1602 22:52:51.163929 == TX Byte 0 ==
1603 22:52:51.167237 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 22:52:51.170554 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 22:52:51.173923 == TX Byte 1 ==
1606 22:52:51.177179 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1607 22:52:51.180648 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1608 22:52:51.184060
1609 22:52:51.184467 [DATLAT]
1610 22:52:51.184790 Freq=800, CH1 RK0
1611 22:52:51.185097
1612 22:52:51.187578 DATLAT Default: 0xa
1613 22:52:51.187987 0, 0xFFFF, sum = 0
1614 22:52:51.191033 1, 0xFFFF, sum = 0
1615 22:52:51.191448 2, 0xFFFF, sum = 0
1616 22:52:51.193937 3, 0xFFFF, sum = 0
1617 22:52:51.194352 4, 0xFFFF, sum = 0
1618 22:52:51.197295 5, 0xFFFF, sum = 0
1619 22:52:51.197741 6, 0xFFFF, sum = 0
1620 22:52:51.200829 7, 0xFFFF, sum = 0
1621 22:52:51.204033 8, 0xFFFF, sum = 0
1622 22:52:51.204449 9, 0x0, sum = 1
1623 22:52:51.204781 10, 0x0, sum = 2
1624 22:52:51.207479 11, 0x0, sum = 3
1625 22:52:51.207896 12, 0x0, sum = 4
1626 22:52:51.210490 best_step = 10
1627 22:52:51.210899
1628 22:52:51.211224 ==
1629 22:52:51.214309 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 22:52:51.217360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 22:52:51.217836 ==
1632 22:52:51.220786 RX Vref Scan: 1
1633 22:52:51.221195
1634 22:52:51.221552 Set Vref Range= 32 -> 127
1635 22:52:51.221968
1636 22:52:51.223778 RX Vref 32 -> 127, step: 1
1637 22:52:51.224189
1638 22:52:51.227325 RX Delay -111 -> 252, step: 8
1639 22:52:51.227809
1640 22:52:51.230673 Set Vref, RX VrefLevel [Byte0]: 32
1641 22:52:51.233877 [Byte1]: 32
1642 22:52:51.234390
1643 22:52:51.237691 Set Vref, RX VrefLevel [Byte0]: 33
1644 22:52:51.240959 [Byte1]: 33
1645 22:52:51.244584
1646 22:52:51.245006 Set Vref, RX VrefLevel [Byte0]: 34
1647 22:52:51.247864 [Byte1]: 34
1648 22:52:51.251928
1649 22:52:51.252375 Set Vref, RX VrefLevel [Byte0]: 35
1650 22:52:51.255711 [Byte1]: 35
1651 22:52:51.260004
1652 22:52:51.260440 Set Vref, RX VrefLevel [Byte0]: 36
1653 22:52:51.263012 [Byte1]: 36
1654 22:52:51.267467
1655 22:52:51.267890 Set Vref, RX VrefLevel [Byte0]: 37
1656 22:52:51.271150 [Byte1]: 37
1657 22:52:51.275053
1658 22:52:51.275477 Set Vref, RX VrefLevel [Byte0]: 38
1659 22:52:51.278174 [Byte1]: 38
1660 22:52:51.282586
1661 22:52:51.283142 Set Vref, RX VrefLevel [Byte0]: 39
1662 22:52:51.285892 [Byte1]: 39
1663 22:52:51.289932
1664 22:52:51.290012 Set Vref, RX VrefLevel [Byte0]: 40
1665 22:52:51.293676 [Byte1]: 40
1666 22:52:51.297547
1667 22:52:51.297640 Set Vref, RX VrefLevel [Byte0]: 41
1668 22:52:51.300992 [Byte1]: 41
1669 22:52:51.305129
1670 22:52:51.305227 Set Vref, RX VrefLevel [Byte0]: 42
1671 22:52:51.308279 [Byte1]: 42
1672 22:52:51.313034
1673 22:52:51.313106 Set Vref, RX VrefLevel [Byte0]: 43
1674 22:52:51.316572 [Byte1]: 43
1675 22:52:51.320594
1676 22:52:51.320690 Set Vref, RX VrefLevel [Byte0]: 44
1677 22:52:51.324215 [Byte1]: 44
1678 22:52:51.328403
1679 22:52:51.328503 Set Vref, RX VrefLevel [Byte0]: 45
1680 22:52:51.331252 [Byte1]: 45
1681 22:52:51.335797
1682 22:52:51.335898 Set Vref, RX VrefLevel [Byte0]: 46
1683 22:52:51.339208 [Byte1]: 46
1684 22:52:51.343765
1685 22:52:51.343868 Set Vref, RX VrefLevel [Byte0]: 47
1686 22:52:51.346841 [Byte1]: 47
1687 22:52:51.351111
1688 22:52:51.351209 Set Vref, RX VrefLevel [Byte0]: 48
1689 22:52:51.354477 [Byte1]: 48
1690 22:52:51.358786
1691 22:52:51.358887 Set Vref, RX VrefLevel [Byte0]: 49
1692 22:52:51.362027 [Byte1]: 49
1693 22:52:51.366568
1694 22:52:51.366642 Set Vref, RX VrefLevel [Byte0]: 50
1695 22:52:51.369908 [Byte1]: 50
1696 22:52:51.373966
1697 22:52:51.374048 Set Vref, RX VrefLevel [Byte0]: 51
1698 22:52:51.377598 [Byte1]: 51
1699 22:52:51.381849
1700 22:52:51.381922 Set Vref, RX VrefLevel [Byte0]: 52
1701 22:52:51.385180 [Byte1]: 52
1702 22:52:51.389698
1703 22:52:51.389783 Set Vref, RX VrefLevel [Byte0]: 53
1704 22:52:51.392943 [Byte1]: 53
1705 22:52:51.396939
1706 22:52:51.397027 Set Vref, RX VrefLevel [Byte0]: 54
1707 22:52:51.400140 [Byte1]: 54
1708 22:52:51.404770
1709 22:52:51.404849 Set Vref, RX VrefLevel [Byte0]: 55
1710 22:52:51.408258 [Byte1]: 55
1711 22:52:51.412662
1712 22:52:51.412742 Set Vref, RX VrefLevel [Byte0]: 56
1713 22:52:51.415509 [Byte1]: 56
1714 22:52:51.419906
1715 22:52:51.419985 Set Vref, RX VrefLevel [Byte0]: 57
1716 22:52:51.423361 [Byte1]: 57
1717 22:52:51.427944
1718 22:52:51.428023 Set Vref, RX VrefLevel [Byte0]: 58
1719 22:52:51.430842 [Byte1]: 58
1720 22:52:51.435137
1721 22:52:51.435220 Set Vref, RX VrefLevel [Byte0]: 59
1722 22:52:51.438504 [Byte1]: 59
1723 22:52:51.442874
1724 22:52:51.442953 Set Vref, RX VrefLevel [Byte0]: 60
1725 22:52:51.446428 [Byte1]: 60
1726 22:52:51.450493
1727 22:52:51.450573 Set Vref, RX VrefLevel [Byte0]: 61
1728 22:52:51.454035 [Byte1]: 61
1729 22:52:51.458311
1730 22:52:51.458391 Set Vref, RX VrefLevel [Byte0]: 62
1731 22:52:51.461333 [Byte1]: 62
1732 22:52:51.465762
1733 22:52:51.465841 Set Vref, RX VrefLevel [Byte0]: 63
1734 22:52:51.469082 [Byte1]: 63
1735 22:52:51.473687
1736 22:52:51.473766 Set Vref, RX VrefLevel [Byte0]: 64
1737 22:52:51.476657 [Byte1]: 64
1738 22:52:51.481103
1739 22:52:51.481182 Set Vref, RX VrefLevel [Byte0]: 65
1740 22:52:51.484816 [Byte1]: 65
1741 22:52:51.488814
1742 22:52:51.488893 Set Vref, RX VrefLevel [Byte0]: 66
1743 22:52:51.492254 [Byte1]: 66
1744 22:52:51.496225
1745 22:52:51.496304 Set Vref, RX VrefLevel [Byte0]: 67
1746 22:52:51.500096 [Byte1]: 67
1747 22:52:51.504248
1748 22:52:51.504328 Set Vref, RX VrefLevel [Byte0]: 68
1749 22:52:51.507634 [Byte1]: 68
1750 22:52:51.512228
1751 22:52:51.512307 Set Vref, RX VrefLevel [Byte0]: 69
1752 22:52:51.515192 [Byte1]: 69
1753 22:52:51.519520
1754 22:52:51.519599 Set Vref, RX VrefLevel [Byte0]: 70
1755 22:52:51.522727 [Byte1]: 70
1756 22:52:51.527202
1757 22:52:51.527281 Set Vref, RX VrefLevel [Byte0]: 71
1758 22:52:51.530742 [Byte1]: 71
1759 22:52:51.534752
1760 22:52:51.534831 Set Vref, RX VrefLevel [Byte0]: 72
1761 22:52:51.538152 [Byte1]: 72
1762 22:52:51.542385
1763 22:52:51.542497 Final RX Vref Byte 0 = 56 to rank0
1764 22:52:51.545803 Final RX Vref Byte 1 = 55 to rank0
1765 22:52:51.549349 Final RX Vref Byte 0 = 56 to rank1
1766 22:52:51.552344 Final RX Vref Byte 1 = 55 to rank1==
1767 22:52:51.555700 Dram Type= 6, Freq= 0, CH_1, rank 0
1768 22:52:51.562339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1769 22:52:51.562419 ==
1770 22:52:51.562483 DQS Delay:
1771 22:52:51.562542 DQS0 = 0, DQS1 = 0
1772 22:52:51.565625 DQM Delay:
1773 22:52:51.565706 DQM0 = 81, DQM1 = 72
1774 22:52:51.569003 DQ Delay:
1775 22:52:51.572410 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1776 22:52:51.575775 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1777 22:52:51.575855 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1778 22:52:51.582166 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1779 22:52:51.582250
1780 22:52:51.582340
1781 22:52:51.588530 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1782 22:52:51.592014 CH1 RK0: MR19=606, MR18=F1A
1783 22:52:51.598573 CH1_RK0: MR19=0x606, MR18=0xF1A, DQSOSC=403, MR23=63, INC=90, DEC=60
1784 22:52:51.598653
1785 22:52:51.601938 ----->DramcWriteLeveling(PI) begin...
1786 22:52:51.602012 ==
1787 22:52:51.605457 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 22:52:51.608724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 22:52:51.608798 ==
1790 22:52:51.612170 Write leveling (Byte 0): 25 => 25
1791 22:52:51.615424 Write leveling (Byte 1): 32 => 32
1792 22:52:51.619000 DramcWriteLeveling(PI) end<-----
1793 22:52:51.619100
1794 22:52:51.619190 ==
1795 22:52:51.622391 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 22:52:51.625688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 22:52:51.625787 ==
1798 22:52:51.628709 [Gating] SW mode calibration
1799 22:52:51.635487 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1800 22:52:51.641795 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1801 22:52:51.645130 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1802 22:52:51.648848 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1803 22:52:51.655100 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 22:52:51.658612 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 22:52:51.662378 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 22:52:51.668766 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 22:52:51.672311 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 22:52:51.675085 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 22:52:51.681986 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 22:52:51.685438 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:52:51.688449 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:52:51.695311 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:52:51.698636 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:52:51.701943 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 22:52:51.705437 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:52:51.712329 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 22:52:51.715650 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:52:51.718878 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1819 22:52:51.725308 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1820 22:52:51.728784 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:52:51.732106 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:52:51.738647 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:52:51.741793 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:52:51.745529 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:52:51.752110 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:52:51.755258 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1827 22:52:51.758329 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
1828 22:52:51.765373 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 22:52:51.768812 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 22:52:51.772043 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 22:52:51.778376 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 22:52:51.781756 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 22:52:51.785256 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 22:52:51.791739 0 10 4 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (0 1)
1835 22:52:51.795040 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1836 22:52:51.798611 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:52:51.804796 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:52:51.808273 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:52:51.811745 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:52:51.818643 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:52:51.821412 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 22:52:51.824736 0 11 4 | B1->B0 | 2828 3b3b | 0 0 | (0 0) (0 0)
1843 22:52:51.831805 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1844 22:52:51.834865 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 22:52:51.838108 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 22:52:51.845008 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 22:52:51.847983 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 22:52:51.851353 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 22:52:51.854773 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 22:52:51.861502 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1851 22:52:51.864948 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1852 22:52:51.868002 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 22:52:51.875015 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 22:52:51.878306 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 22:52:51.881646 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 22:52:51.888002 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 22:52:51.891446 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 22:52:51.894838 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 22:52:51.901225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:52:51.904736 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:52:51.908277 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:52:51.915150 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 22:52:51.917970 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:52:51.921357 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 22:52:51.928108 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1866 22:52:51.931572 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1867 22:52:51.935024 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1868 22:52:51.937862 Total UI for P1: 0, mck2ui 16
1869 22:52:51.941270 best dqsien dly found for B0: ( 0, 14, 2)
1870 22:52:51.944702 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 22:52:51.948035 Total UI for P1: 0, mck2ui 16
1872 22:52:51.951279 best dqsien dly found for B1: ( 0, 14, 8)
1873 22:52:51.955164 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1874 22:52:51.961591 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1875 22:52:51.961667
1876 22:52:51.964855 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1877 22:52:51.968313 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1878 22:52:51.971622 [Gating] SW calibration Done
1879 22:52:51.971709 ==
1880 22:52:51.975031 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 22:52:51.978236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 22:52:51.978317 ==
1883 22:52:51.978380 RX Vref Scan: 0
1884 22:52:51.978440
1885 22:52:51.981496 RX Vref 0 -> 0, step: 1
1886 22:52:51.981617
1887 22:52:51.985355 RX Delay -130 -> 252, step: 16
1888 22:52:51.988149 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1889 22:52:51.991488 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1890 22:52:51.997863 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1891 22:52:52.001367 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1892 22:52:52.004615 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1893 22:52:52.007864 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1894 22:52:52.011283 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1895 22:52:52.018181 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1896 22:52:52.021747 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1897 22:52:52.024546 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1898 22:52:52.027928 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1899 22:52:52.031241 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1900 22:52:52.038196 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1901 22:52:52.041499 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1902 22:52:52.044523 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1903 22:52:52.047885 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1904 22:52:52.047965 ==
1905 22:52:52.051405 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 22:52:52.054728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 22:52:52.058310 ==
1908 22:52:52.058389 DQS Delay:
1909 22:52:52.058452 DQS0 = 0, DQS1 = 0
1910 22:52:52.061686 DQM Delay:
1911 22:52:52.061765 DQM0 = 79, DQM1 = 71
1912 22:52:52.064558 DQ Delay:
1913 22:52:52.068014 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1914 22:52:52.068093 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1915 22:52:52.071186 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1916 22:52:52.074711 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1917 22:52:52.077887
1918 22:52:52.077966
1919 22:53:01.543028 ==
1920 22:53:01.543459 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 22:53:01.543627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 22:53:01.543718 ==
1923 22:53:01.543811
1924 22:53:01.543898
1925 22:53:01.543982 TX Vref Scan disable
1926 22:53:01.544074 == TX Byte 0 ==
1927 22:53:01.544160 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1928 22:53:01.544260 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1929 22:53:01.544351 == TX Byte 1 ==
1930 22:53:01.544435 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1931 22:53:01.544562 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1932 22:53:01.544692 ==
1933 22:53:01.544784 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 22:53:01.544867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 22:53:01.544957 ==
1936 22:53:01.545040 TX Vref=22, minBit 11, minWin=27, winSum=454
1937 22:53:01.545125 TX Vref=24, minBit 2, minWin=28, winSum=458
1938 22:53:01.545215 TX Vref=26, minBit 2, minWin=28, winSum=461
1939 22:53:01.545308 TX Vref=28, minBit 5, minWin=28, winSum=463
1940 22:53:01.545390 TX Vref=30, minBit 1, minWin=28, winSum=466
1941 22:53:01.545480 TX Vref=32, minBit 1, minWin=28, winSum=466
1942 22:53:01.545567 [TxChooseVref] Worse bit 1, Min win 28, Win sum 466, Final Vref 30
1943 22:53:01.545635
1944 22:53:01.545701 Final TX Range 1 Vref 30
1945 22:53:01.545758
1946 22:53:01.545810 ==
1947 22:53:01.545863 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 22:53:01.545915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 22:53:01.545985 ==
1950 22:53:01.546039
1951 22:53:01.546091
1952 22:53:01.546143 TX Vref Scan disable
1953 22:53:01.546195 == TX Byte 0 ==
1954 22:53:01.546247 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1955 22:53:01.546311 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1956 22:53:01.546367 == TX Byte 1 ==
1957 22:53:01.546419 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1958 22:53:01.546471 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1959 22:53:01.546522
1960 22:53:01.546590 [DATLAT]
1961 22:53:01.546644 Freq=800, CH1 RK1
1962 22:53:01.546696
1963 22:53:01.546748 DATLAT Default: 0xa
1964 22:53:01.546806 0, 0xFFFF, sum = 0
1965 22:53:01.546868 1, 0xFFFF, sum = 0
1966 22:53:01.546921 2, 0xFFFF, sum = 0
1967 22:53:01.546974 3, 0xFFFF, sum = 0
1968 22:53:01.547027 4, 0xFFFF, sum = 0
1969 22:53:01.547096 5, 0xFFFF, sum = 0
1970 22:53:01.547151 6, 0xFFFF, sum = 0
1971 22:53:01.547203 7, 0xFFFF, sum = 0
1972 22:53:01.547255 8, 0xFFFF, sum = 0
1973 22:53:01.547312 9, 0x0, sum = 1
1974 22:53:01.547374 10, 0x0, sum = 2
1975 22:53:01.547427 11, 0x0, sum = 3
1976 22:53:01.547479 12, 0x0, sum = 4
1977 22:53:01.547531 best_step = 10
1978 22:53:01.547582
1979 22:53:01.547634 ==
1980 22:53:01.547703 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 22:53:01.547757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 22:53:01.547810 ==
1983 22:53:01.547862 RX Vref Scan: 0
1984 22:53:01.547914
1985 22:53:01.548004 RX Vref 0 -> 0, step: 1
1986 22:53:01.548085
1987 22:53:01.548166 RX Delay -111 -> 252, step: 8
1988 22:53:01.548257 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1989 22:53:01.548339 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1990 22:53:01.548420 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1991 22:53:01.548510 iDelay=209, Bit 3, Center 68 (-55 ~ 192) 248
1992 22:53:01.548602 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1993 22:53:01.548688 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1994 22:53:01.548774 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1995 22:53:01.548855 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1996 22:53:01.548939 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1997 22:53:01.549025 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1998 22:53:01.549105 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1999 22:53:01.549203 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2000 22:53:01.549287 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2001 22:53:01.549368 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2002 22:53:01.549449 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2003 22:53:01.549562 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2004 22:53:01.549638 ==
2005 22:53:01.549692 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 22:53:01.549744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 22:53:01.549800 ==
2008 22:53:01.549853 DQS Delay:
2009 22:53:01.549916 DQS0 = 0, DQS1 = 0
2010 22:53:01.549971 DQM Delay:
2011 22:53:01.550023 DQM0 = 76, DQM1 = 74
2012 22:53:01.550080 DQ Delay:
2013 22:53:01.550135 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =68
2014 22:53:01.550222 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2015 22:53:01.550305 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =64
2016 22:53:01.550387 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2017 22:53:01.550467
2018 22:53:01.550554
2019 22:53:01.550638 [DQSOSCAuto] RK1, (LSB)MR18= 0x243d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2020 22:53:01.550720 CH1 RK1: MR19=606, MR18=243D
2021 22:53:01.550807 CH1_RK1: MR19=0x606, MR18=0x243D, DQSOSC=394, MR23=63, INC=95, DEC=63
2022 22:53:01.550867 [RxdqsGatingPostProcess] freq 800
2023 22:53:01.550919 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 22:53:01.550972 Pre-setting of DQS Precalculation
2025 22:53:01.551025 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 22:53:01.551094 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 22:53:01.551148 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 22:53:01.551201
2029 22:53:01.551252
2030 22:53:01.551310 [Calibration Summary] 1600 Mbps
2031 22:53:01.551370 CH 0, Rank 0
2032 22:53:01.551433 SW Impedance : PASS
2033 22:53:01.551487 DUTY Scan : NO K
2034 22:53:01.551539 ZQ Calibration : PASS
2035 22:53:01.551607 Jitter Meter : NO K
2036 22:53:01.551660 CBT Training : PASS
2037 22:53:01.551711 Write leveling : PASS
2038 22:53:01.551763 RX DQS gating : PASS
2039 22:53:01.551825 RX DQ/DQS(RDDQC) : PASS
2040 22:53:01.551880 TX DQ/DQS : PASS
2041 22:53:01.551932 RX DATLAT : PASS
2042 22:53:01.551983 RX DQ/DQS(Engine): PASS
2043 22:53:01.552035 TX OE : NO K
2044 22:53:01.552087 All Pass.
2045 22:53:01.552139
2046 22:53:01.552217 CH 0, Rank 1
2047 22:53:01.552298 SW Impedance : PASS
2048 22:53:01.552379 DUTY Scan : NO K
2049 22:53:01.552470 ZQ Calibration : PASS
2050 22:53:01.552552 Jitter Meter : NO K
2051 22:53:01.552633 CBT Training : PASS
2052 22:53:01.552723 Write leveling : PASS
2053 22:53:01.552805 RX DQS gating : PASS
2054 22:53:01.552886 RX DQ/DQS(RDDQC) : PASS
2055 22:53:01.552975 TX DQ/DQS : PASS
2056 22:53:01.553058 RX DATLAT : PASS
2057 22:53:01.553139 RX DQ/DQS(Engine): PASS
2058 22:53:01.553228 TX OE : NO K
2059 22:53:01.553310 All Pass.
2060 22:53:01.553391
2061 22:53:01.553487 CH 1, Rank 0
2062 22:53:01.553626 SW Impedance : PASS
2063 22:53:01.553709 DUTY Scan : NO K
2064 22:53:01.553793 ZQ Calibration : PASS
2065 22:53:01.553880 Jitter Meter : NO K
2066 22:53:01.553961 CBT Training : PASS
2067 22:53:01.554242 Write leveling : PASS
2068 22:53:01.554337 RX DQS gating : PASS
2069 22:53:01.554421 RX DQ/DQS(RDDQC) : PASS
2070 22:53:01.554504 TX DQ/DQS : PASS
2071 22:53:01.554595 RX DATLAT : PASS
2072 22:53:01.554677 RX DQ/DQS(Engine): PASS
2073 22:53:01.554757 TX OE : NO K
2074 22:53:01.554839 All Pass.
2075 22:53:01.554903
2076 22:53:01.554991 CH 1, Rank 1
2077 22:53:01.555044 SW Impedance : PASS
2078 22:53:01.555097 DUTY Scan : NO K
2079 22:53:01.555158 ZQ Calibration : PASS
2080 22:53:01.555216 Jitter Meter : NO K
2081 22:53:01.555268 CBT Training : PASS
2082 22:53:01.555326 Write leveling : PASS
2083 22:53:01.555387 RX DQS gating : PASS
2084 22:53:01.555463 RX DQ/DQS(RDDQC) : PASS
2085 22:53:01.555545 TX DQ/DQS : PASS
2086 22:53:01.555637 RX DATLAT : PASS
2087 22:53:01.555727 RX DQ/DQS(Engine): PASS
2088 22:53:01.555809 TX OE : NO K
2089 22:53:01.555890 All Pass.
2090 22:53:01.555979
2091 22:53:01.556061 DramC Write-DBI off
2092 22:53:01.556142 PER_BANK_REFRESH: Hybrid Mode
2093 22:53:01.556232 TX_TRACKING: ON
2094 22:53:01.556314 [GetDramInforAfterCalByMRR] Vendor 6.
2095 22:53:01.556396 [GetDramInforAfterCalByMRR] Revision 606.
2096 22:53:01.556486 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 22:53:01.556568 MR0 0x3b3b
2098 22:53:01.556649 MR8 0x5151
2099 22:53:01.556738 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 22:53:01.556820
2101 22:53:01.556901 MR0 0x3b3b
2102 22:53:01.556989 MR8 0x5151
2103 22:53:01.557071 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 22:53:01.557152
2105 22:53:01.557235 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 22:53:01.557326 [FAST_K] Save calibration result to emmc
2107 22:53:01.557409 [FAST_K] Save calibration result to emmc
2108 22:53:01.557490 dram_init: config_dvfs: 1
2109 22:53:01.557633 dramc_set_vcore_voltage set vcore to 662500
2110 22:53:01.557716 Read voltage for 1200, 2
2111 22:53:01.557798 Vio18 = 0
2112 22:53:01.557887 Vcore = 662500
2113 22:53:01.557977 Vdram = 0
2114 22:53:01.558105 Vddq = 0
2115 22:53:01.558208 Vmddr = 0
2116 22:53:01.558310 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 22:53:01.558369 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 22:53:01.558423 MEM_TYPE=3, freq_sel=15
2119 22:53:01.558475 sv_algorithm_assistance_LP4_1600
2120 22:53:01.558528 ============ PULL DRAM RESETB DOWN ============
2121 22:53:01.558601 ========== PULL DRAM RESETB DOWN end =========
2122 22:53:01.558661 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 22:53:01.558745 ===================================
2124 22:53:01.558835 LPDDR4 DRAM CONFIGURATION
2125 22:53:01.558918 ===================================
2126 22:53:01.558999 EX_ROW_EN[0] = 0x0
2127 22:53:01.559088 EX_ROW_EN[1] = 0x0
2128 22:53:01.559170 LP4Y_EN = 0x0
2129 22:53:01.559253 WORK_FSP = 0x0
2130 22:53:01.559350 WL = 0x4
2131 22:53:01.559432 RL = 0x4
2132 22:53:01.559508 BL = 0x2
2133 22:53:01.559572 RPST = 0x0
2134 22:53:01.559646 RD_PRE = 0x0
2135 22:53:01.559739 WR_PRE = 0x1
2136 22:53:01.559791 WR_PST = 0x0
2137 22:53:01.559858 DBI_WR = 0x0
2138 22:53:01.559911 DBI_RD = 0x0
2139 22:53:01.559977 OTF = 0x1
2140 22:53:01.560035 ===================================
2141 22:53:01.560170 ===================================
2142 22:53:01.560253 ANA top config
2143 22:53:01.560343 ===================================
2144 22:53:01.560425 DLL_ASYNC_EN = 0
2145 22:53:01.560512 ALL_SLAVE_EN = 0
2146 22:53:01.560589 NEW_RANK_MODE = 1
2147 22:53:01.560644 DLL_IDLE_MODE = 1
2148 22:53:01.560697 LP45_APHY_COMB_EN = 1
2149 22:53:01.560749 TX_ODT_DIS = 1
2150 22:53:01.560810 NEW_8X_MODE = 1
2151 22:53:01.560868 ===================================
2152 22:53:01.560921 ===================================
2153 22:53:01.560974 data_rate = 2400
2154 22:53:01.561026 CKR = 1
2155 22:53:01.561095 DQ_P2S_RATIO = 8
2156 22:53:01.561149 ===================================
2157 22:53:01.561201 CA_P2S_RATIO = 8
2158 22:53:01.561253 DQ_CA_OPEN = 0
2159 22:53:01.561309 DQ_SEMI_OPEN = 0
2160 22:53:01.561397 CA_SEMI_OPEN = 0
2161 22:53:01.561478 CA_FULL_RATE = 0
2162 22:53:01.561614 DQ_CKDIV4_EN = 0
2163 22:53:01.561679 CA_CKDIV4_EN = 0
2164 22:53:01.561732 CA_PREDIV_EN = 0
2165 22:53:01.561784 PH8_DLY = 17
2166 22:53:01.561836 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 22:53:01.561888 DQ_AAMCK_DIV = 4
2168 22:53:01.561956 CA_AAMCK_DIV = 4
2169 22:53:01.562009 CA_ADMCK_DIV = 4
2170 22:53:01.562061 DQ_TRACK_CA_EN = 0
2171 22:53:01.562116 CA_PICK = 1200
2172 22:53:01.562174 CA_MCKIO = 1200
2173 22:53:01.562235 MCKIO_SEMI = 0
2174 22:53:01.562321 PLL_FREQ = 2366
2175 22:53:01.562374 DQ_UI_PI_RATIO = 32
2176 22:53:01.562437 CA_UI_PI_RATIO = 0
2177 22:53:01.562492 ===================================
2178 22:53:01.562544 ===================================
2179 22:53:01.562601 memory_type:LPDDR4
2180 22:53:01.562668 GP_NUM : 10
2181 22:53:01.562758 SRAM_EN : 1
2182 22:53:01.562841 MD32_EN : 0
2183 22:53:01.562926 ===================================
2184 22:53:01.563013 [ANA_INIT] >>>>>>>>>>>>>>
2185 22:53:01.563094 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 22:53:01.563179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 22:53:01.563266 ===================================
2188 22:53:01.563347 data_rate = 2400,PCW = 0X5b00
2189 22:53:01.563432 ===================================
2190 22:53:01.563493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 22:53:01.563546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 22:53:01.563603 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 22:53:01.563691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 22:53:01.563778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 22:53:01.563859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 22:53:01.563945 [ANA_INIT] flow start
2197 22:53:01.564030 [ANA_INIT] PLL >>>>>>>>
2198 22:53:01.564111 [ANA_INIT] PLL <<<<<<<<
2199 22:53:01.564192 [ANA_INIT] MIDPI >>>>>>>>
2200 22:53:01.564274 [ANA_INIT] MIDPI <<<<<<<<
2201 22:53:01.564364 [ANA_INIT] DLL >>>>>>>>
2202 22:53:01.564445 [ANA_INIT] DLL <<<<<<<<
2203 22:53:01.564525 [ANA_INIT] flow end
2204 22:53:01.564614 ============ LP4 DIFF to SE enter ============
2205 22:53:01.564903 ============ LP4 DIFF to SE exit ============
2206 22:53:01.564992 [ANA_INIT] <<<<<<<<<<<<<
2207 22:53:01.565083 [Flow] Enable top DCM control >>>>>
2208 22:53:01.565167 [Flow] Enable top DCM control <<<<<
2209 22:53:01.565249 Enable DLL master slave shuffle
2210 22:53:01.565339 ==============================================================
2211 22:53:01.565423 Gating Mode config
2212 22:53:01.565505 ==============================================================
2213 22:53:01.565616 Config description:
2214 22:53:01.565737 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 22:53:01.565793 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 22:53:01.565847 SELPH_MODE 0: By rank 1: By Phase
2217 22:53:01.565900 ==============================================================
2218 22:53:01.565969 GAT_TRACK_EN = 1
2219 22:53:01.566023 RX_GATING_MODE = 2
2220 22:53:01.566084 RX_GATING_TRACK_MODE = 2
2221 22:53:01.566137 SELPH_MODE = 1
2222 22:53:01.566202 PICG_EARLY_EN = 1
2223 22:53:01.566256 VALID_LAT_VALUE = 1
2224 22:53:01.566308 ==============================================================
2225 22:53:01.566360 Enter into Gating configuration >>>>
2226 22:53:01.566413 Exit from Gating configuration <<<<
2227 22:53:01.566483 Enter into DVFS_PRE_config >>>>>
2228 22:53:01.566537 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 22:53:01.566591 Exit from DVFS_PRE_config <<<<<
2230 22:53:01.566647 Enter into PICG configuration >>>>
2231 22:53:01.566718 Exit from PICG configuration <<<<
2232 22:53:01.566772 [RX_INPUT] configuration >>>>>
2233 22:53:01.566824 [RX_INPUT] configuration <<<<<
2234 22:53:01.566876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 22:53:01.566949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 22:53:01.567036 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 22:53:01.567121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 22:53:01.567211 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 22:53:01.567296 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 22:53:01.567377 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 22:53:01.567468 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 22:53:01.567551 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 22:53:01.567648 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 22:53:01.567740 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 22:53:01.567823 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 22:53:01.567905 ===================================
2247 22:53:01.568000 LPDDR4 DRAM CONFIGURATION
2248 22:53:01.568085 ===================================
2249 22:53:01.568223 EX_ROW_EN[0] = 0x0
2250 22:53:01.568313 EX_ROW_EN[1] = 0x0
2251 22:53:01.568395 LP4Y_EN = 0x0
2252 22:53:01.568479 WORK_FSP = 0x0
2253 22:53:01.568570 WL = 0x4
2254 22:53:01.568663 RL = 0x4
2255 22:53:01.568745 BL = 0x2
2256 22:53:01.568833 RPST = 0x0
2257 22:53:01.568915 RD_PRE = 0x0
2258 22:53:01.568996 WR_PRE = 0x1
2259 22:53:01.569082 WR_PST = 0x0
2260 22:53:01.569156 DBI_WR = 0x0
2261 22:53:01.569227 DBI_RD = 0x0
2262 22:53:01.569280 OTF = 0x1
2263 22:53:01.569333 ===================================
2264 22:53:01.569385 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 22:53:01.569473 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 22:53:01.569599 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 22:53:01.569702 ===================================
2268 22:53:01.569801 LPDDR4 DRAM CONFIGURATION
2269 22:53:01.569885 ===================================
2270 22:53:01.569982 EX_ROW_EN[0] = 0x10
2271 22:53:01.570078 EX_ROW_EN[1] = 0x0
2272 22:53:01.570142 LP4Y_EN = 0x0
2273 22:53:01.570195 WORK_FSP = 0x0
2274 22:53:01.570247 WL = 0x4
2275 22:53:01.570299 RL = 0x4
2276 22:53:01.570352 BL = 0x2
2277 22:53:01.570413 RPST = 0x0
2278 22:53:01.570474 RD_PRE = 0x0
2279 22:53:01.570543 WR_PRE = 0x1
2280 22:53:01.570596 WR_PST = 0x0
2281 22:53:01.570647 DBI_WR = 0x0
2282 22:53:01.570699 DBI_RD = 0x0
2283 22:53:01.570751 OTF = 0x1
2284 22:53:01.570804 ===================================
2285 22:53:01.570856 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 22:53:01.570909 ==
2287 22:53:01.570962 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 22:53:01.571014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 22:53:01.571076 ==
2290 22:53:01.571147 [Duty_Offset_Calibration]
2291 22:53:01.571202 B0:2 B1:0 CA:3
2292 22:53:01.571255
2293 22:53:01.571316 [DutyScan_Calibration_Flow] k_type=0
2294 22:53:01.571434
2295 22:53:01.571508 ==CLK 0==
2296 22:53:01.571561 Final CLK duty delay cell = 0
2297 22:53:01.571618 [0] MAX Duty = 5031%(X100), DQS PI = 12
2298 22:53:01.571778 [0] MIN Duty = 4906%(X100), DQS PI = 54
2299 22:53:01.571885 [0] AVG Duty = 4968%(X100)
2300 22:53:01.571970
2301 22:53:01.572023 CH0 CLK Duty spec in!! Max-Min= 125%
2302 22:53:01.572076 [DutyScan_Calibration_Flow] ====Done====
2303 22:53:01.572128
2304 22:53:01.572179 [DutyScan_Calibration_Flow] k_type=1
2305 22:53:01.572231
2306 22:53:01.572282 ==DQS 0 ==
2307 22:53:01.572334 Final DQS duty delay cell = 0
2308 22:53:01.572386 [0] MAX Duty = 5062%(X100), DQS PI = 12
2309 22:53:01.572448 [0] MIN Duty = 4907%(X100), DQS PI = 2
2310 22:53:01.572527 [0] AVG Duty = 4984%(X100)
2311 22:53:01.572596
2312 22:53:01.572647 ==DQS 1 ==
2313 22:53:01.572699 Final DQS duty delay cell = 0
2314 22:53:01.572779 [0] MAX Duty = 5125%(X100), DQS PI = 34
2315 22:53:01.572832 [0] MIN Duty = 5000%(X100), DQS PI = 2
2316 22:53:01.572883 [0] AVG Duty = 5062%(X100)
2317 22:53:01.572934
2318 22:53:01.573017 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2319 22:53:01.573135
2320 22:53:01.573189 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2321 22:53:01.573241 [DutyScan_Calibration_Flow] ====Done====
2322 22:53:01.573293
2323 22:53:01.573344 [DutyScan_Calibration_Flow] k_type=3
2324 22:53:01.573395
2325 22:53:01.573447 ==DQM 0 ==
2326 22:53:01.573499 Final DQM duty delay cell = 0
2327 22:53:01.573819 [0] MAX Duty = 5124%(X100), DQS PI = 28
2328 22:53:01.573905 [0] MIN Duty = 4876%(X100), DQS PI = 0
2329 22:53:01.573976 [0] AVG Duty = 5000%(X100)
2330 22:53:01.574040
2331 22:53:01.574094 ==DQM 1 ==
2332 22:53:01.574147 Final DQM duty delay cell = 4
2333 22:53:01.574201 [4] MAX Duty = 5124%(X100), DQS PI = 50
2334 22:53:01.574254 [4] MIN Duty = 5000%(X100), DQS PI = 12
2335 22:53:01.574307 [4] AVG Duty = 5062%(X100)
2336 22:53:01.574361
2337 22:53:01.574414 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2338 22:53:01.574478
2339 22:53:01.574546 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2340 22:53:01.574623 [DutyScan_Calibration_Flow] ====Done====
2341 22:53:01.574700
2342 22:53:01.574753 [DutyScan_Calibration_Flow] k_type=2
2343 22:53:01.574848
2344 22:53:01.574926 ==DQ 0 ==
2345 22:53:01.574982 Final DQ duty delay cell = -4
2346 22:53:01.575204 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2347 22:53:01.575336 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2348 22:53:01.575440 [-4] AVG Duty = 4969%(X100)
2349 22:53:01.575524
2350 22:53:01.575605 ==DQ 1 ==
2351 22:53:01.575687 Final DQ duty delay cell = -4
2352 22:53:01.575778 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2353 22:53:01.575860 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2354 22:53:01.575958 [-4] AVG Duty = 4938%(X100)
2355 22:53:01.576041
2356 22:53:01.576139 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2357 22:53:01.576233
2358 22:53:01.576314 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2359 22:53:01.576395 [DutyScan_Calibration_Flow] ====Done====
2360 22:53:01.576475 ==
2361 22:53:01.576570 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 22:53:01.576626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 22:53:01.576679 ==
2364 22:53:01.576730 [Duty_Offset_Calibration]
2365 22:53:01.576782 B0:1 B1:-2 CA:0
2366 22:53:01.576833
2367 22:53:01.576884 [DutyScan_Calibration_Flow] k_type=0
2368 22:53:01.576936
2369 22:53:01.576986 ==CLK 0==
2370 22:53:01.577039 Final CLK duty delay cell = 0
2371 22:53:01.577100 [0] MAX Duty = 5062%(X100), DQS PI = 30
2372 22:53:01.577182 [0] MIN Duty = 4876%(X100), DQS PI = 2
2373 22:53:01.577263 [0] AVG Duty = 4969%(X100)
2374 22:53:01.577343
2375 22:53:01.577424 CH1 CLK Duty spec in!! Max-Min= 186%
2376 22:53:01.577505 [DutyScan_Calibration_Flow] ====Done====
2377 22:53:01.577598
2378 22:53:01.577660 [DutyScan_Calibration_Flow] k_type=1
2379 22:53:01.577715
2380 22:53:01.577780 ==DQS 0 ==
2381 22:53:01.577832 Final DQS duty delay cell = -4
2382 22:53:01.577885 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2383 22:53:01.577937 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2384 22:53:01.577988 [-4] AVG Duty = 4969%(X100)
2385 22:53:01.578040
2386 22:53:01.578092 ==DQS 1 ==
2387 22:53:01.578144 Final DQS duty delay cell = 0
2388 22:53:01.578196 [0] MAX Duty = 5093%(X100), DQS PI = 0
2389 22:53:01.578257 [0] MIN Duty = 4875%(X100), DQS PI = 26
2390 22:53:01.578309 [0] AVG Duty = 4984%(X100)
2391 22:53:01.578360
2392 22:53:01.578421 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2393 22:53:01.578495
2394 22:53:01.578550 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2395 22:53:01.578603 [DutyScan_Calibration_Flow] ====Done====
2396 22:53:01.578679
2397 22:53:01.578762 [DutyScan_Calibration_Flow] k_type=3
2398 22:53:01.578816
2399 22:53:01.578867 ==DQM 0 ==
2400 22:53:01.578919 Final DQM duty delay cell = 0
2401 22:53:01.578971 [0] MAX Duty = 5031%(X100), DQS PI = 24
2402 22:53:01.579023 [0] MIN Duty = 4876%(X100), DQS PI = 0
2403 22:53:01.579075 [0] AVG Duty = 4953%(X100)
2404 22:53:01.579126
2405 22:53:01.579177 ==DQM 1 ==
2406 22:53:01.579229 Final DQM duty delay cell = 0
2407 22:53:01.579281 [0] MAX Duty = 5031%(X100), DQS PI = 36
2408 22:53:01.579332 [0] MIN Duty = 4907%(X100), DQS PI = 0
2409 22:53:01.579431 [0] AVG Duty = 4969%(X100)
2410 22:53:01.579561
2411 22:53:01.579666 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2412 22:53:01.579763
2413 22:53:01.579852 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2414 22:53:01.579934 [DutyScan_Calibration_Flow] ====Done====
2415 22:53:01.580014
2416 22:53:01.580095 [DutyScan_Calibration_Flow] k_type=2
2417 22:53:01.580174
2418 22:53:01.580254 ==DQ 0 ==
2419 22:53:01.580335 Final DQ duty delay cell = 0
2420 22:53:01.580425 [0] MAX Duty = 5093%(X100), DQS PI = 26
2421 22:53:01.580514 [0] MIN Duty = 4907%(X100), DQS PI = 56
2422 22:53:01.580596 [0] AVG Duty = 5000%(X100)
2423 22:53:01.580676
2424 22:53:01.580756 ==DQ 1 ==
2425 22:53:01.580837 Final DQ duty delay cell = 0
2426 22:53:01.580918 [0] MAX Duty = 5093%(X100), DQS PI = 18
2427 22:53:01.581008 [0] MIN Duty = 4969%(X100), DQS PI = 26
2428 22:53:01.581108 [0] AVG Duty = 5031%(X100)
2429 22:53:01.581189
2430 22:53:01.581270 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2431 22:53:01.581367
2432 22:53:01.581459 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2433 22:53:01.581554 [DutyScan_Calibration_Flow] ====Done====
2434 22:53:01.581608 nWR fixed to 30
2435 22:53:01.581661 [ModeRegInit_LP4] CH0 RK0
2436 22:53:01.581713 [ModeRegInit_LP4] CH0 RK1
2437 22:53:01.581765 [ModeRegInit_LP4] CH1 RK0
2438 22:53:01.581816 [ModeRegInit_LP4] CH1 RK1
2439 22:53:01.581868 match AC timing 7
2440 22:53:01.581919 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 22:53:01.581971 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 22:53:01.582022 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 22:53:01.582074 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 22:53:01.582126 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 22:53:01.582178 ==
2446 22:53:01.582229 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 22:53:01.582296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 22:53:01.582456 ==
2449 22:53:01.582553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 22:53:01.582613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2451 22:53:01.582667 [CA 0] Center 40 (10~71) winsize 62
2452 22:53:01.582720 [CA 1] Center 40 (10~70) winsize 61
2453 22:53:01.582772 [CA 2] Center 36 (6~66) winsize 61
2454 22:53:01.582824 [CA 3] Center 35 (5~66) winsize 62
2455 22:53:01.582875 [CA 4] Center 34 (4~65) winsize 62
2456 22:53:01.582927 [CA 5] Center 33 (3~64) winsize 62
2457 22:53:01.582978
2458 22:53:01.583029 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2459 22:53:01.583081
2460 22:53:01.583146 [CATrainingPosCal] consider 1 rank data
2461 22:53:01.583215 u2DelayCellTimex100 = 270/100 ps
2462 22:53:01.583269 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2463 22:53:01.583321 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2464 22:53:01.583373 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2465 22:53:01.583434 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2466 22:53:01.583486 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2467 22:53:01.583537 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2468 22:53:01.583588
2469 22:53:01.583640 CA PerBit enable=1, Macro0, CA PI delay=33
2470 22:53:01.583691
2471 22:53:01.583743 [CBTSetCACLKResult] CA Dly = 33
2472 22:53:01.583794 CS Dly: 7 (0~38)
2473 22:53:01.583845 ==
2474 22:53:01.583897 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 22:53:01.584147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 22:53:01.584206 ==
2477 22:53:01.584258 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 22:53:01.584311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2479 22:53:01.584363 [CA 0] Center 40 (10~71) winsize 62
2480 22:53:01.584415 [CA 1] Center 40 (10~70) winsize 61
2481 22:53:01.584467 [CA 2] Center 35 (5~66) winsize 62
2482 22:53:01.584519 [CA 3] Center 35 (5~66) winsize 62
2483 22:53:01.584581 [CA 4] Center 34 (4~65) winsize 62
2484 22:53:01.584633 [CA 5] Center 33 (3~63) winsize 61
2485 22:53:01.584684
2486 22:53:01.584736 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2487 22:53:01.584788
2488 22:53:01.584839 [CATrainingPosCal] consider 2 rank data
2489 22:53:01.584891 u2DelayCellTimex100 = 270/100 ps
2490 22:53:01.584942 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2491 22:53:01.584995 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2492 22:53:01.585046 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2493 22:53:01.585102 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 22:53:01.585161 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2495 22:53:01.585213 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2496 22:53:01.585264
2497 22:53:01.585316 CA PerBit enable=1, Macro0, CA PI delay=33
2498 22:53:01.585368
2499 22:53:01.585419 [CBTSetCACLKResult] CA Dly = 33
2500 22:53:01.585471 CS Dly: 8 (0~40)
2501 22:53:01.585567
2502 22:53:01.585621 ----->DramcWriteLeveling(PI) begin...
2503 22:53:01.585674 ==
2504 22:53:01.585725 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 22:53:01.585778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 22:53:01.585830 ==
2507 22:53:01.585881 Write leveling (Byte 0): 32 => 32
2508 22:53:01.585933 Write leveling (Byte 1): 30 => 30
2509 22:53:01.585985 DramcWriteLeveling(PI) end<-----
2510 22:53:01.586036
2511 22:53:01.586087 ==
2512 22:53:01.586139 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 22:53:01.586191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 22:53:01.586242 ==
2515 22:53:01.586293 [Gating] SW mode calibration
2516 22:53:01.586345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 22:53:01.586397 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 22:53:01.586450 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2519 22:53:01.586502 0 15 4 | B1->B0 | 2727 3232 | 0 1 | (0 0) (1 1)
2520 22:53:01.586553 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 22:53:01.586605 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 22:53:01.586657 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 22:53:01.586708 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 22:53:01.586759 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2525 22:53:01.586811 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2526 22:53:01.586863 1 0 0 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (1 0)
2527 22:53:01.586914 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 22:53:01.586965 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 22:53:01.587017 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 22:53:01.587078 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 22:53:01.587139 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 22:53:01.587203 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 22:53:01.587309 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2534 22:53:01.587393 1 1 0 | B1->B0 | 2828 3131 | 0 1 | (0 0) (0 0)
2535 22:53:01.587451 1 1 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2536 22:53:01.587503 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 22:53:01.587555 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 22:53:01.587608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 22:53:01.587660 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 22:53:01.587723 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 22:53:01.587775 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 22:53:01.587826 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2543 22:53:01.587877 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 22:53:01.587929 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 22:53:01.587980 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 22:53:01.588032 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 22:53:01.588083 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 22:53:01.588134 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 22:53:01.588184 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 22:53:01.588235 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:53:01.588287 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 22:53:01.588350 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:53:01.588416 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 22:53:01.588469 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 22:53:01.588521 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 22:53:01.588572 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 22:53:01.588624 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 22:53:01.588675 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2559 22:53:01.588727 Total UI for P1: 0, mck2ui 16
2560 22:53:01.588780 best dqsien dly found for B0: ( 1, 3, 28)
2561 22:53:01.588832 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2562 22:53:01.588884 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 22:53:01.588935 Total UI for P1: 0, mck2ui 16
2564 22:53:01.588996 best dqsien dly found for B1: ( 1, 4, 4)
2565 22:53:01.589071 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2566 22:53:01.589179 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2567 22:53:01.589267
2568 22:53:01.589366 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2569 22:53:01.589450 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2570 22:53:01.589563 [Gating] SW calibration Done
2571 22:53:01.589618 ==
2572 22:53:01.589671 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 22:53:01.589724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 22:53:01.589776 ==
2575 22:53:01.589828 RX Vref Scan: 0
2576 22:53:01.589880
2577 22:53:01.589931 RX Vref 0 -> 0, step: 1
2578 22:53:01.589993
2579 22:53:01.590061 RX Delay -40 -> 252, step: 8
2580 22:53:01.590309 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2581 22:53:01.590368 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2582 22:53:01.590421 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
2583 22:53:01.590473 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2584 22:53:01.590525 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2585 22:53:01.590587 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2586 22:53:01.590673 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2587 22:53:01.590729 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2588 22:53:01.590781 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2589 22:53:01.590833 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2590 22:53:01.590885 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2591 22:53:01.590937 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2592 22:53:01.590999 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2593 22:53:01.591055 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2594 22:53:01.591114 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2595 22:53:01.591225 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2596 22:53:01.591278 ==
2597 22:53:01.591330 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 22:53:01.591382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 22:53:01.591434 ==
2600 22:53:01.591486 DQS Delay:
2601 22:53:01.591551 DQS0 = 0, DQS1 = 0
2602 22:53:01.591638 DQM Delay:
2603 22:53:01.591710 DQM0 = 111, DQM1 = 102
2604 22:53:01.591791 DQ Delay:
2605 22:53:01.591872 DQ0 =111, DQ1 =111, DQ2 =107, DQ3 =107
2606 22:53:01.591954 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2607 22:53:01.592034 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2608 22:53:01.592115 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2609 22:53:01.592195
2610 22:53:01.592275
2611 22:53:01.592355 ==
2612 22:53:01.592436 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 22:53:01.592518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 22:53:01.592598 ==
2615 22:53:01.592678
2616 22:53:01.592758
2617 22:53:01.592837 TX Vref Scan disable
2618 22:53:01.592917 == TX Byte 0 ==
2619 22:53:01.592998 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2620 22:53:01.593079 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2621 22:53:01.593170 == TX Byte 1 ==
2622 22:53:01.593252 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2623 22:53:01.593333 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2624 22:53:01.593413 ==
2625 22:53:01.593494 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 22:53:01.593601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 22:53:01.593682 ==
2628 22:53:01.593755 TX Vref=22, minBit 4, minWin=25, winSum=420
2629 22:53:01.593809 TX Vref=24, minBit 0, minWin=26, winSum=426
2630 22:53:01.593862 TX Vref=26, minBit 7, minWin=26, winSum=436
2631 22:53:01.593914 TX Vref=28, minBit 4, minWin=27, winSum=442
2632 22:53:01.593965 TX Vref=30, minBit 8, minWin=26, winSum=439
2633 22:53:01.594019 TX Vref=32, minBit 10, minWin=26, winSum=434
2634 22:53:01.594074 [TxChooseVref] Worse bit 4, Min win 27, Win sum 442, Final Vref 28
2635 22:53:01.594129
2636 22:53:01.594194 Final TX Range 1 Vref 28
2637 22:53:01.594249
2638 22:53:01.594301 ==
2639 22:53:01.594353 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 22:53:01.594405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 22:53:01.594457 ==
2642 22:53:01.594508
2643 22:53:01.594558
2644 22:53:01.594609 TX Vref Scan disable
2645 22:53:01.594661 == TX Byte 0 ==
2646 22:53:01.594712 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2647 22:53:01.594764 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2648 22:53:01.594816 == TX Byte 1 ==
2649 22:53:01.594867 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2650 22:53:01.594919 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2651 22:53:01.594970
2652 22:53:01.595021 [DATLAT]
2653 22:53:01.595072 Freq=1200, CH0 RK0
2654 22:53:01.595137
2655 22:53:01.595197 DATLAT Default: 0xd
2656 22:53:01.595248 0, 0xFFFF, sum = 0
2657 22:53:01.595301 1, 0xFFFF, sum = 0
2658 22:53:01.595354 2, 0xFFFF, sum = 0
2659 22:53:01.595408 3, 0xFFFF, sum = 0
2660 22:53:01.595461 4, 0xFFFF, sum = 0
2661 22:53:01.595521 5, 0xFFFF, sum = 0
2662 22:53:01.595574 6, 0xFFFF, sum = 0
2663 22:53:01.595625 7, 0xFFFF, sum = 0
2664 22:53:01.595677 8, 0xFFFF, sum = 0
2665 22:53:01.595729 9, 0xFFFF, sum = 0
2666 22:53:01.595782 10, 0xFFFF, sum = 0
2667 22:53:01.595843 11, 0xFFFF, sum = 0
2668 22:53:01.595899 12, 0x0, sum = 1
2669 22:53:01.595955 13, 0x0, sum = 2
2670 22:53:01.596051 14, 0x0, sum = 3
2671 22:53:01.596134 15, 0x0, sum = 4
2672 22:53:01.596217 best_step = 13
2673 22:53:01.596297
2674 22:53:01.596380 ==
2675 22:53:01.596467 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 22:53:01.596550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 22:53:01.596631 ==
2678 22:53:01.596712 RX Vref Scan: 1
2679 22:53:01.596792
2680 22:53:01.596872 Set Vref Range= 32 -> 127
2681 22:53:01.596953
2682 22:53:01.597033 RX Vref 32 -> 127, step: 1
2683 22:53:01.597117
2684 22:53:01.597211 RX Delay -37 -> 252, step: 4
2685 22:53:01.597292
2686 22:53:01.597372 Set Vref, RX VrefLevel [Byte0]: 32
2687 22:53:01.597463 [Byte1]: 32
2688 22:53:01.597572
2689 22:53:01.597626 Set Vref, RX VrefLevel [Byte0]: 33
2690 22:53:01.597678 [Byte1]: 33
2691 22:53:01.597729
2692 22:53:01.597781 Set Vref, RX VrefLevel [Byte0]: 34
2693 22:53:01.597832 [Byte1]: 34
2694 22:53:01.597883
2695 22:53:01.597935 Set Vref, RX VrefLevel [Byte0]: 35
2696 22:53:01.597986 [Byte1]: 35
2697 22:53:01.598037
2698 22:53:01.598088 Set Vref, RX VrefLevel [Byte0]: 36
2699 22:53:01.598141 [Byte1]: 36
2700 22:53:01.598192
2701 22:53:01.598244 Set Vref, RX VrefLevel [Byte0]: 37
2702 22:53:01.598295 [Byte1]: 37
2703 22:53:01.598345
2704 22:53:01.598397 Set Vref, RX VrefLevel [Byte0]: 38
2705 22:53:01.598449 [Byte1]: 38
2706 22:53:01.598500
2707 22:53:01.598551 Set Vref, RX VrefLevel [Byte0]: 39
2708 22:53:01.598602 [Byte1]: 39
2709 22:53:01.598653
2710 22:53:01.598704 Set Vref, RX VrefLevel [Byte0]: 40
2711 22:53:01.598755 [Byte1]: 40
2712 22:53:01.598807
2713 22:53:01.598858 Set Vref, RX VrefLevel [Byte0]: 41
2714 22:53:01.598909 [Byte1]: 41
2715 22:53:01.598959
2716 22:53:01.599010 Set Vref, RX VrefLevel [Byte0]: 42
2717 22:53:01.599060 [Byte1]: 42
2718 22:53:01.599111
2719 22:53:01.599162 Set Vref, RX VrefLevel [Byte0]: 43
2720 22:53:01.599213 [Byte1]: 43
2721 22:53:01.599264
2722 22:53:01.599316 Set Vref, RX VrefLevel [Byte0]: 44
2723 22:53:01.599376 [Byte1]: 44
2724 22:53:01.599427
2725 22:53:01.599479 Set Vref, RX VrefLevel [Byte0]: 45
2726 22:53:01.599530 [Byte1]: 45
2727 22:53:01.599581
2728 22:53:01.599632 Set Vref, RX VrefLevel [Byte0]: 46
2729 22:53:01.599683 [Byte1]: 46
2730 22:53:01.599734
2731 22:53:01.599785 Set Vref, RX VrefLevel [Byte0]: 47
2732 22:53:01.599836 [Byte1]: 47
2733 22:53:01.599888
2734 22:53:01.599939 Set Vref, RX VrefLevel [Byte0]: 48
2735 22:53:01.599990 [Byte1]: 48
2736 22:53:01.600041
2737 22:53:01.600286 Set Vref, RX VrefLevel [Byte0]: 49
2738 22:53:01.600348 [Byte1]: 49
2739 22:53:01.600401
2740 22:53:01.600453 Set Vref, RX VrefLevel [Byte0]: 50
2741 22:53:01.600505 [Byte1]: 50
2742 22:53:01.600557
2743 22:53:01.600608 Set Vref, RX VrefLevel [Byte0]: 51
2744 22:53:01.600660 [Byte1]: 51
2745 22:53:01.600711
2746 22:53:01.600763 Set Vref, RX VrefLevel [Byte0]: 52
2747 22:53:01.600814 [Byte1]: 52
2748 22:53:01.600865
2749 22:53:01.600916 Set Vref, RX VrefLevel [Byte0]: 53
2750 22:53:01.600968 [Byte1]: 53
2751 22:53:01.601030
2752 22:53:01.601081 Set Vref, RX VrefLevel [Byte0]: 54
2753 22:53:01.601133 [Byte1]: 54
2754 22:53:01.601185
2755 22:53:01.601235 Set Vref, RX VrefLevel [Byte0]: 55
2756 22:53:01.601287 [Byte1]: 55
2757 22:53:01.601337
2758 22:53:01.601389 Set Vref, RX VrefLevel [Byte0]: 56
2759 22:53:01.601440 [Byte1]: 56
2760 22:53:01.601491
2761 22:53:01.601590 Set Vref, RX VrefLevel [Byte0]: 57
2762 22:53:01.601642 [Byte1]: 57
2763 22:53:01.601693
2764 22:53:01.601744 Set Vref, RX VrefLevel [Byte0]: 58
2765 22:53:01.601796 [Byte1]: 58
2766 22:53:01.601847
2767 22:53:01.601898 Set Vref, RX VrefLevel [Byte0]: 59
2768 22:53:01.601949 [Byte1]: 59
2769 22:53:01.602000
2770 22:53:01.602051 Set Vref, RX VrefLevel [Byte0]: 60
2771 22:53:01.602102 [Byte1]: 60
2772 22:53:01.602153
2773 22:53:01.602203 Set Vref, RX VrefLevel [Byte0]: 61
2774 22:53:01.602255 [Byte1]: 61
2775 22:53:01.602306
2776 22:53:01.602358 Set Vref, RX VrefLevel [Byte0]: 62
2777 22:53:01.602410 [Byte1]: 62
2778 22:53:01.602461
2779 22:53:01.602512 Set Vref, RX VrefLevel [Byte0]: 63
2780 22:53:01.602563 [Byte1]: 63
2781 22:53:01.602614
2782 22:53:01.602665 Set Vref, RX VrefLevel [Byte0]: 64
2783 22:53:01.602718 [Byte1]: 64
2784 22:53:01.602770
2785 22:53:01.602821 Set Vref, RX VrefLevel [Byte0]: 65
2786 22:53:01.602872 [Byte1]: 65
2787 22:53:01.602923
2788 22:53:01.602974 Set Vref, RX VrefLevel [Byte0]: 66
2789 22:53:01.603025 [Byte1]: 66
2790 22:53:01.603076
2791 22:53:01.603127 Set Vref, RX VrefLevel [Byte0]: 67
2792 22:53:01.603188 [Byte1]: 67
2793 22:53:01.603240
2794 22:53:01.603290 Set Vref, RX VrefLevel [Byte0]: 68
2795 22:53:01.603342 [Byte1]: 68
2796 22:53:01.603393
2797 22:53:01.603444 Set Vref, RX VrefLevel [Byte0]: 69
2798 22:53:01.603496 [Byte1]: 69
2799 22:53:01.603547
2800 22:53:01.603598 Set Vref, RX VrefLevel [Byte0]: 70
2801 22:53:01.603649 [Byte1]: 70
2802 22:53:01.603700
2803 22:53:01.603751 Set Vref, RX VrefLevel [Byte0]: 71
2804 22:53:01.603802 [Byte1]: 71
2805 22:53:01.603853
2806 22:53:01.603904 Set Vref, RX VrefLevel [Byte0]: 72
2807 22:53:01.603955 [Byte1]: 72
2808 22:53:01.604006
2809 22:53:01.604058 Set Vref, RX VrefLevel [Byte0]: 73
2810 22:53:01.604110 [Byte1]: 73
2811 22:53:01.604161
2812 22:53:01.604212 Set Vref, RX VrefLevel [Byte0]: 74
2813 22:53:01.604263 [Byte1]: 74
2814 22:53:01.604314
2815 22:53:01.604365 Final RX Vref Byte 0 = 63 to rank0
2816 22:53:01.604417 Final RX Vref Byte 1 = 58 to rank0
2817 22:53:01.604478 Final RX Vref Byte 0 = 63 to rank1
2818 22:53:01.604530 Final RX Vref Byte 1 = 58 to rank1==
2819 22:53:01.604582 Dram Type= 6, Freq= 0, CH_0, rank 0
2820 22:53:01.604636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 22:53:01.604692 ==
2822 22:53:01.604757 DQS Delay:
2823 22:53:01.604916 DQS0 = 0, DQS1 = 0
2824 22:53:01.605014 DQM Delay:
2825 22:53:01.605099 DQM0 = 112, DQM1 = 102
2826 22:53:01.605181 DQ Delay:
2827 22:53:01.605262 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =106
2828 22:53:01.605343 DQ4 =114, DQ5 =104, DQ6 =118, DQ7 =120
2829 22:53:01.605424 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2830 22:53:01.605515 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2831 22:53:01.605615
2832 22:53:01.605775
2833 22:53:01.605880 [DQSOSCAuto] RK0, (LSB)MR18= 0x0, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2834 22:53:01.605948 CH0 RK0: MR19=404, MR18=0
2835 22:53:01.606019 CH0_RK0: MR19=0x404, MR18=0x0, DQSOSC=410, MR23=63, INC=39, DEC=26
2836 22:53:01.606110
2837 22:53:01.606192 ----->DramcWriteLeveling(PI) begin...
2838 22:53:01.606275 ==
2839 22:53:01.606357 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 22:53:01.606439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 22:53:01.606520 ==
2842 22:53:01.606604 Write leveling (Byte 0): 32 => 32
2843 22:53:01.606693 Write leveling (Byte 1): 30 => 30
2844 22:53:01.606773 DramcWriteLeveling(PI) end<-----
2845 22:53:01.606853
2846 22:53:01.606933 ==
2847 22:53:01.607014 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 22:53:01.607105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 22:53:01.607186 ==
2850 22:53:01.607267 [Gating] SW mode calibration
2851 22:53:01.607350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2852 22:53:01.607432 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2853 22:53:01.607513 0 15 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2854 22:53:01.607594 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 22:53:01.607676 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 22:53:01.607757 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 22:53:01.607848 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 22:53:01.607929 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 22:53:01.608010 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2860 22:53:01.608091 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2861 22:53:01.608172 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2862 22:53:01.608253 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 22:53:01.608335 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 22:53:01.608416 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 22:53:01.608497 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 22:53:01.608578 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 22:53:01.608681 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2868 22:53:01.608766 1 0 28 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
2869 22:53:01.608904 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2870 22:53:01.609022 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 22:53:01.609313 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 22:53:01.609429 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 22:53:01.609624 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 22:53:01.609729 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 22:53:01.609819 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2876 22:53:01.609935 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2877 22:53:01.610018 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2878 22:53:01.610106 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 22:53:01.610205 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 22:53:01.610301 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 22:53:01.610383 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 22:53:01.610464 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 22:53:01.610545 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 22:53:01.610637 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:53:01.610719 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:53:01.610800 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:53:01.610881 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:53:01.610972 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 22:53:01.611054 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 22:53:01.611135 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 22:53:01.611216 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 22:53:01.611297 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2893 22:53:01.611378 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2894 22:53:01.611459 Total UI for P1: 0, mck2ui 16
2895 22:53:01.611540 best dqsien dly found for B0: ( 1, 3, 28)
2896 22:53:01.611621 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 22:53:01.611703 Total UI for P1: 0, mck2ui 16
2898 22:53:01.611785 best dqsien dly found for B1: ( 1, 4, 0)
2899 22:53:01.611874 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2900 22:53:01.611956 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2901 22:53:01.612045
2902 22:53:01.612127 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2903 22:53:01.612208 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2904 22:53:01.612289 [Gating] SW calibration Done
2905 22:53:01.612369 ==
2906 22:53:01.612450 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 22:53:01.612532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 22:53:01.612616 ==
2909 22:53:01.612762 RX Vref Scan: 0
2910 22:53:01.612843
2911 22:53:01.612924 RX Vref 0 -> 0, step: 1
2912 22:53:01.613004
2913 22:53:01.613084 RX Delay -40 -> 252, step: 8
2914 22:53:01.613165 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2915 22:53:01.613246 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2916 22:53:01.613327 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2917 22:53:01.613408 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2918 22:53:01.613489 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2919 22:53:01.613609 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2920 22:53:01.613690 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2921 22:53:01.613771 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2922 22:53:01.613852 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2923 22:53:01.613933 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2924 22:53:01.614014 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2925 22:53:01.614095 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2926 22:53:01.614176 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2927 22:53:01.614256 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2928 22:53:01.614337 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2929 22:53:01.614426 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2930 22:53:01.614507 ==
2931 22:53:01.614592 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 22:53:01.614685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 22:53:01.614763 ==
2934 22:53:01.614822 DQS Delay:
2935 22:53:01.614898 DQS0 = 0, DQS1 = 0
2936 22:53:01.743587 DQM Delay:
2937 22:53:01.744207 DQM0 = 111, DQM1 = 103
2938 22:53:01.744782 DQ Delay:
2939 22:53:01.745269 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2940 22:53:01.745816 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2941 22:53:01.746182 DQ8 =91, DQ9 =87, DQ10 =107, DQ11 =95
2942 22:53:01.746582 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2943 22:53:01.747066
2944 22:53:01.747498
2945 22:53:01.747883 ==
2946 22:53:01.748285 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 22:53:01.748813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 22:53:01.749372 ==
2949 22:53:01.749868
2950 22:53:01.750284
2951 22:53:01.750663 TX Vref Scan disable
2952 22:53:01.751024 == TX Byte 0 ==
2953 22:53:01.751382 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2954 22:53:01.751739 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2955 22:53:01.752108 == TX Byte 1 ==
2956 22:53:01.752495 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2957 22:53:01.752897 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2958 22:53:01.753439 ==
2959 22:53:01.754005 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 22:53:01.754455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 22:53:01.754832 ==
2962 22:53:01.755207 TX Vref=22, minBit 5, minWin=26, winSum=433
2963 22:53:01.755594 TX Vref=24, minBit 2, minWin=26, winSum=433
2964 22:53:01.756120 TX Vref=26, minBit 5, minWin=26, winSum=439
2965 22:53:01.756706 TX Vref=28, minBit 1, minWin=27, winSum=447
2966 22:53:01.757231 TX Vref=30, minBit 1, minWin=27, winSum=443
2967 22:53:01.757776 TX Vref=32, minBit 13, minWin=26, winSum=441
2968 22:53:01.758266 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28
2969 22:53:01.758750
2970 22:53:01.759072 Final TX Range 1 Vref 28
2971 22:53:01.759416
2972 22:53:01.759852 ==
2973 22:53:01.760242 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 22:53:01.760620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 22:53:01.760940 ==
2976 22:53:01.761283
2977 22:53:01.761713
2978 22:53:01.762046 TX Vref Scan disable
2979 22:53:01.762398 == TX Byte 0 ==
2980 22:53:01.762865 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2981 22:53:01.763185 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2982 22:53:01.763569 == TX Byte 1 ==
2983 22:53:01.763907 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2984 22:53:01.764259 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2985 22:53:01.764616
2986 22:53:01.764984 [DATLAT]
2987 22:53:01.765310 Freq=1200, CH0 RK1
2988 22:53:01.765651
2989 22:53:01.765975 DATLAT Default: 0xd
2990 22:53:01.766320 0, 0xFFFF, sum = 0
2991 22:53:01.766578 1, 0xFFFF, sum = 0
2992 22:53:01.766843 2, 0xFFFF, sum = 0
2993 22:53:01.767447 3, 0xFFFF, sum = 0
2994 22:53:01.767797 4, 0xFFFF, sum = 0
2995 22:53:01.768134 5, 0xFFFF, sum = 0
2996 22:53:01.768503 6, 0xFFFF, sum = 0
2997 22:53:01.768825 7, 0xFFFF, sum = 0
2998 22:53:01.769144 8, 0xFFFF, sum = 0
2999 22:53:01.769478 9, 0xFFFF, sum = 0
3000 22:53:01.769773 10, 0xFFFF, sum = 0
3001 22:53:01.770011 11, 0xFFFF, sum = 0
3002 22:53:01.770245 12, 0x0, sum = 1
3003 22:53:01.770481 13, 0x0, sum = 2
3004 22:53:01.770637 14, 0x0, sum = 3
3005 22:53:01.770830 15, 0x0, sum = 4
3006 22:53:01.770981 best_step = 13
3007 22:53:01.771170
3008 22:53:01.771321 ==
3009 22:53:01.771497 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 22:53:01.771651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 22:53:01.771796 ==
3012 22:53:01.771988 RX Vref Scan: 0
3013 22:53:01.772137
3014 22:53:01.772341 RX Vref 0 -> 0, step: 1
3015 22:53:01.772491
3016 22:53:01.772680 RX Delay -29 -> 252, step: 4
3017 22:53:01.772832 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3018 22:53:01.773016 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3019 22:53:01.773171 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3020 22:53:01.773340 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3021 22:53:01.773602 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3022 22:53:01.773800 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3023 22:53:01.773951 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3024 22:53:01.774120 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3025 22:53:01.774279 iDelay=195, Bit 8, Center 92 (23 ~ 162) 140
3026 22:53:01.774426 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3027 22:53:01.774613 iDelay=195, Bit 10, Center 102 (35 ~ 170) 136
3028 22:53:01.774761 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3029 22:53:01.774929 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3030 22:53:01.775051 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3031 22:53:01.775169 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3032 22:53:01.775322 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3033 22:53:01.775441 ==
3034 22:53:01.775583 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 22:53:01.775709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 22:53:01.775826 ==
3037 22:53:01.775944 DQS Delay:
3038 22:53:01.776089 DQS0 = 0, DQS1 = 0
3039 22:53:01.776208 DQM Delay:
3040 22:53:01.776367 DQM0 = 111, DQM1 = 102
3041 22:53:01.776492 DQ Delay:
3042 22:53:01.776610 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3043 22:53:01.776752 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3044 22:53:01.776875 DQ8 =92, DQ9 =84, DQ10 =102, DQ11 =94
3045 22:53:01.776992 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3046 22:53:01.777132
3047 22:53:01.777255
3048 22:53:01.777370 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3049 22:53:01.777550 CH0 RK1: MR19=403, MR18=14FC
3050 22:53:01.777679 CH0_RK1: MR19=0x403, MR18=0x14FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3051 22:53:01.777799 [RxdqsGatingPostProcess] freq 1200
3052 22:53:01.777954 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3053 22:53:01.778100 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 22:53:01.778238 best DQS1 dly(2T, 0.5T) = (0, 12)
3055 22:53:01.778366 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 22:53:01.778502 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3057 22:53:01.778653 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 22:53:01.778773 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 22:53:01.778890 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 22:53:01.779043 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 22:53:01.779164 Pre-setting of DQS Precalculation
3062 22:53:01.779282 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3063 22:53:01.779434 ==
3064 22:53:01.779571 Dram Type= 6, Freq= 0, CH_1, rank 0
3065 22:53:01.779691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 22:53:01.779845 ==
3067 22:53:01.779945 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3068 22:53:01.780084 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3069 22:53:01.780193 [CA 0] Center 37 (7~67) winsize 61
3070 22:53:01.780291 [CA 1] Center 37 (7~68) winsize 62
3071 22:53:01.780389 [CA 2] Center 34 (4~64) winsize 61
3072 22:53:01.780514 [CA 3] Center 33 (3~64) winsize 62
3073 22:53:01.780614 [CA 4] Center 34 (4~64) winsize 61
3074 22:53:01.780711 [CA 5] Center 33 (3~63) winsize 61
3075 22:53:01.780809
3076 22:53:01.780929 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3077 22:53:01.781027
3078 22:53:01.781124 [CATrainingPosCal] consider 1 rank data
3079 22:53:01.781243 u2DelayCellTimex100 = 270/100 ps
3080 22:53:01.781346 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3081 22:53:01.781443 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3082 22:53:01.781553 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3083 22:53:01.781722 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3084 22:53:01.781875 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 22:53:01.782042 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3086 22:53:01.782192
3087 22:53:01.782356 CA PerBit enable=1, Macro0, CA PI delay=33
3088 22:53:01.782510
3089 22:53:01.782661 [CBTSetCACLKResult] CA Dly = 33
3090 22:53:01.782828 CS Dly: 6 (0~37)
3091 22:53:01.782978 ==
3092 22:53:01.783143 Dram Type= 6, Freq= 0, CH_1, rank 1
3093 22:53:01.783298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 22:53:01.783477 ==
3095 22:53:01.783586 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3096 22:53:01.783686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3097 22:53:01.783785 [CA 0] Center 37 (7~67) winsize 61
3098 22:53:01.783935 [CA 1] Center 37 (7~68) winsize 62
3099 22:53:01.784087 [CA 2] Center 34 (4~65) winsize 62
3100 22:53:01.784260 [CA 3] Center 33 (3~64) winsize 62
3101 22:53:01.784365 [CA 4] Center 34 (4~65) winsize 62
3102 22:53:01.784463 [CA 5] Center 32 (2~63) winsize 62
3103 22:53:01.784597
3104 22:53:01.784704 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3105 22:53:01.784802
3106 22:53:01.784904 [CATrainingPosCal] consider 2 rank data
3107 22:53:01.785015 u2DelayCellTimex100 = 270/100 ps
3108 22:53:01.785102 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3109 22:53:01.785186 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3110 22:53:01.785270 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3111 22:53:01.785381 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3112 22:53:01.785467 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 22:53:01.785558 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3114 22:53:01.785641
3115 22:53:01.785752 CA PerBit enable=1, Macro0, CA PI delay=33
3116 22:53:01.785839
3117 22:53:01.785922 [CBTSetCACLKResult] CA Dly = 33
3118 22:53:01.786006 CS Dly: 7 (0~39)
3119 22:53:01.786111
3120 22:53:01.786217 ----->DramcWriteLeveling(PI) begin...
3121 22:53:01.786305 ==
3122 22:53:01.786390 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 22:53:01.786721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 22:53:01.786826 ==
3125 22:53:01.786926 Write leveling (Byte 0): 25 => 25
3126 22:53:01.787012 Write leveling (Byte 1): 31 => 31
3127 22:53:01.787097 DramcWriteLeveling(PI) end<-----
3128 22:53:01.787180
3129 22:53:01.787324 ==
3130 22:53:01.787455 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 22:53:01.787598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 22:53:01.787731 ==
3133 22:53:01.787861 [Gating] SW mode calibration
3134 22:53:01.788006 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3135 22:53:01.788153 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3136 22:53:01.788285 0 15 0 | B1->B0 | 2f2f 2625 | 0 1 | (0 0) (0 0)
3137 22:53:01.788402 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 22:53:01.788488 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 22:53:01.788573 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 22:53:01.788656 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 22:53:01.788767 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 22:53:01.788853 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 22:53:01.788937 0 15 28 | B1->B0 | 2e2e 3131 | 0 1 | (1 0) (1 0)
3144 22:53:01.789021 1 0 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (1 0)
3145 22:53:01.789131 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 22:53:01.789217 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 22:53:01.789301 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 22:53:01.789383 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 22:53:01.789495 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 22:53:01.789600 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3151 22:53:01.789685 1 0 28 | B1->B0 | 3e3e 3a3a | 1 1 | (0 0) (0 0)
3152 22:53:01.789769 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 22:53:01.789886 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 22:53:01.789974 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 22:53:01.790048 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 22:53:01.790139 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 22:53:01.790258 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 22:53:01.790334 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 22:53:01.790409 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3160 22:53:01.790494 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 22:53:01.790588 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 22:53:01.790665 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 22:53:01.790739 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 22:53:01.790812 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:53:01.790907 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 22:53:01.790982 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:53:01.791055 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:53:01.791129 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:53:01.791218 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:53:01.791295 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:53:01.791368 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 22:53:01.791440 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 22:53:01.791513 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 22:53:01.791605 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3175 22:53:01.791681 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3176 22:53:01.791753 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 22:53:01.791826 Total UI for P1: 0, mck2ui 16
3178 22:53:01.791900 best dqsien dly found for B0: ( 1, 3, 28)
3179 22:53:01.791997 Total UI for P1: 0, mck2ui 16
3180 22:53:01.792073 best dqsien dly found for B1: ( 1, 3, 26)
3181 22:53:01.792159 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3182 22:53:01.792232 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3183 22:53:01.792307
3184 22:53:01.792397 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3185 22:53:01.792471 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3186 22:53:01.792544 [Gating] SW calibration Done
3187 22:53:01.792617 ==
3188 22:53:01.792700 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 22:53:01.792784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 22:53:01.792858 ==
3191 22:53:01.792931 RX Vref Scan: 0
3192 22:53:01.793004
3193 22:53:01.793124 RX Vref 0 -> 0, step: 1
3194 22:53:01.793239
3195 22:53:01.793363 RX Delay -40 -> 252, step: 8
3196 22:53:01.793481 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3197 22:53:01.793609 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3198 22:53:01.793732 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3199 22:53:01.793810 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3200 22:53:01.793884 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3201 22:53:01.793956 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3202 22:53:01.794030 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3203 22:53:01.794141 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3204 22:53:01.794217 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3205 22:53:01.794291 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3206 22:53:01.794364 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3207 22:53:01.794446 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3208 22:53:01.794530 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3209 22:53:01.794604 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3210 22:53:01.794678 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3211 22:53:01.794752 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3212 22:53:01.794847 ==
3213 22:53:01.794917 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 22:53:01.794983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 22:53:01.795049 ==
3216 22:53:01.795115 DQS Delay:
3217 22:53:01.795184 DQS0 = 0, DQS1 = 0
3218 22:53:01.795263 DQM Delay:
3219 22:53:01.795328 DQM0 = 115, DQM1 = 106
3220 22:53:01.795394 DQ Delay:
3221 22:53:01.795459 DQ0 =123, DQ1 =111, DQ2 =99, DQ3 =115
3222 22:53:01.795525 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3223 22:53:01.795604 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3224 22:53:01.795873 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3225 22:53:01.795961
3226 22:53:01.796031
3227 22:53:01.796100 ==
3228 22:53:01.796221 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 22:53:01.796340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 22:53:01.796411 ==
3231 22:53:01.796478
3232 22:53:01.796543
3233 22:53:01.796628 TX Vref Scan disable
3234 22:53:01.796696 == TX Byte 0 ==
3235 22:53:01.796762 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3236 22:53:01.796828 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3237 22:53:01.796893 == TX Byte 1 ==
3238 22:53:01.796975 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3239 22:53:01.797043 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3240 22:53:01.797108 ==
3241 22:53:01.797174 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 22:53:01.797239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 22:53:01.797306 ==
3244 22:53:01.797419 TX Vref=22, minBit 5, minWin=25, winSum=420
3245 22:53:01.797530 TX Vref=24, minBit 1, minWin=26, winSum=422
3246 22:53:01.797601 TX Vref=26, minBit 1, minWin=26, winSum=432
3247 22:53:01.797666 TX Vref=28, minBit 1, minWin=26, winSum=435
3248 22:53:01.797756 TX Vref=30, minBit 1, minWin=26, winSum=433
3249 22:53:01.797824 TX Vref=32, minBit 0, minWin=26, winSum=430
3250 22:53:01.797890 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 28
3251 22:53:01.797955
3252 22:53:01.798020 Final TX Range 1 Vref 28
3253 22:53:01.798108
3254 22:53:01.798185 ==
3255 22:53:01.798251 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 22:53:01.798317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 22:53:01.798383 ==
3258 22:53:01.798463
3259 22:53:01.798532
3260 22:53:01.798596 TX Vref Scan disable
3261 22:53:01.798661 == TX Byte 0 ==
3262 22:53:01.798726 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3263 22:53:01.798791 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3264 22:53:01.798877 == TX Byte 1 ==
3265 22:53:01.798943 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3266 22:53:01.799009 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3267 22:53:01.799074
3268 22:53:01.799138 [DATLAT]
3269 22:53:01.799218 Freq=1200, CH1 RK0
3270 22:53:01.799286
3271 22:53:01.799351 DATLAT Default: 0xd
3272 22:53:01.799417 0, 0xFFFF, sum = 0
3273 22:53:01.799484 1, 0xFFFF, sum = 0
3274 22:53:01.799549 2, 0xFFFF, sum = 0
3275 22:53:01.799632 3, 0xFFFF, sum = 0
3276 22:53:01.799700 4, 0xFFFF, sum = 0
3277 22:53:01.799766 5, 0xFFFF, sum = 0
3278 22:53:01.799841 6, 0xFFFF, sum = 0
3279 22:53:01.799911 7, 0xFFFF, sum = 0
3280 22:53:01.799989 8, 0xFFFF, sum = 0
3281 22:53:01.800050 9, 0xFFFF, sum = 0
3282 22:53:01.800113 10, 0xFFFF, sum = 0
3283 22:53:01.800198 11, 0xFFFF, sum = 0
3284 22:53:01.800261 12, 0x0, sum = 1
3285 22:53:01.800335 13, 0x0, sum = 2
3286 22:53:01.800398 14, 0x0, sum = 3
3287 22:53:01.800457 15, 0x0, sum = 4
3288 22:53:01.800517 best_step = 13
3289 22:53:01.800575
3290 22:53:01.800634 ==
3291 22:53:01.800707 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 22:53:01.800769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 22:53:01.800828 ==
3294 22:53:01.800887 RX Vref Scan: 1
3295 22:53:01.800946
3296 22:53:01.801004 Set Vref Range= 32 -> 127
3297 22:53:01.801070
3298 22:53:01.801135 RX Vref 32 -> 127, step: 1
3299 22:53:01.801193
3300 22:53:01.801251 RX Delay -21 -> 252, step: 4
3301 22:53:01.801309
3302 22:53:01.801367 Set Vref, RX VrefLevel [Byte0]: 32
3303 22:53:01.801426 [Byte1]: 32
3304 22:53:01.801530
3305 22:53:01.801593 Set Vref, RX VrefLevel [Byte0]: 33
3306 22:53:01.801652 [Byte1]: 33
3307 22:53:01.801710
3308 22:53:01.801781 Set Vref, RX VrefLevel [Byte0]: 34
3309 22:53:01.801858 [Byte1]: 34
3310 22:53:01.801918
3311 22:53:01.801977 Set Vref, RX VrefLevel [Byte0]: 35
3312 22:53:01.802035 [Byte1]: 35
3313 22:53:01.802096
3314 22:53:01.802162 Set Vref, RX VrefLevel [Byte0]: 36
3315 22:53:01.802240 [Byte1]: 36
3316 22:53:01.802300
3317 22:53:01.802358 Set Vref, RX VrefLevel [Byte0]: 37
3318 22:53:01.802416 [Byte1]: 37
3319 22:53:01.802474
3320 22:53:01.802532 Set Vref, RX VrefLevel [Byte0]: 38
3321 22:53:01.802609 [Byte1]: 38
3322 22:53:01.802668
3323 22:53:01.802727 Set Vref, RX VrefLevel [Byte0]: 39
3324 22:53:01.802785 [Byte1]: 39
3325 22:53:01.802855
3326 22:53:01.802914 Set Vref, RX VrefLevel [Byte0]: 40
3327 22:53:01.803007 [Byte1]: 40
3328 22:53:01.803098
3329 22:53:01.803190 Set Vref, RX VrefLevel [Byte0]: 41
3330 22:53:01.803281 [Byte1]: 41
3331 22:53:01.803364
3332 22:53:01.803424 Set Vref, RX VrefLevel [Byte0]: 42
3333 22:53:01.803482 [Byte1]: 42
3334 22:53:01.803540
3335 22:53:01.803598 Set Vref, RX VrefLevel [Byte0]: 43
3336 22:53:01.803658 [Byte1]: 43
3337 22:53:01.803734
3338 22:53:01.803794 Set Vref, RX VrefLevel [Byte0]: 44
3339 22:53:01.803853 [Byte1]: 44
3340 22:53:01.803911
3341 22:53:01.803969 Set Vref, RX VrefLevel [Byte0]: 45
3342 22:53:01.804027 [Byte1]: 45
3343 22:53:01.804115
3344 22:53:01.804214 Set Vref, RX VrefLevel [Byte0]: 46
3345 22:53:01.804305 [Byte1]: 46
3346 22:53:01.804394
3347 22:53:01.804494 Set Vref, RX VrefLevel [Byte0]: 47
3348 22:53:01.804586 [Byte1]: 47
3349 22:53:01.804676
3350 22:53:01.804767 Set Vref, RX VrefLevel [Byte0]: 48
3351 22:53:01.804863 [Byte1]: 48
3352 22:53:01.804918
3353 22:53:01.804972 Set Vref, RX VrefLevel [Byte0]: 49
3354 22:53:01.805025 [Byte1]: 49
3355 22:53:01.805078
3356 22:53:01.805131 Set Vref, RX VrefLevel [Byte0]: 50
3357 22:53:01.805192 [Byte1]: 50
3358 22:53:01.805250
3359 22:53:01.805303 Set Vref, RX VrefLevel [Byte0]: 51
3360 22:53:01.805356 [Byte1]: 51
3361 22:53:01.805409
3362 22:53:01.805461 Set Vref, RX VrefLevel [Byte0]: 52
3363 22:53:01.805520 [Byte1]: 52
3364 22:53:01.805586
3365 22:53:01.805642 Set Vref, RX VrefLevel [Byte0]: 53
3366 22:53:01.805696 [Byte1]: 53
3367 22:53:01.805748
3368 22:53:01.805813 Set Vref, RX VrefLevel [Byte0]: 54
3369 22:53:01.805865 [Byte1]: 54
3370 22:53:01.805917
3371 22:53:01.805986 Set Vref, RX VrefLevel [Byte0]: 55
3372 22:53:01.806039 [Byte1]: 55
3373 22:53:01.806095
3374 22:53:01.806159 Set Vref, RX VrefLevel [Byte0]: 56
3375 22:53:01.806266 [Byte1]: 56
3376 22:53:01.806365
3377 22:53:01.806427 Set Vref, RX VrefLevel [Byte0]: 57
3378 22:53:01.806482 [Byte1]: 57
3379 22:53:01.806535
3380 22:53:01.806587 Set Vref, RX VrefLevel [Byte0]: 58
3381 22:53:01.806639 [Byte1]: 58
3382 22:53:01.806691
3383 22:53:01.806743 Set Vref, RX VrefLevel [Byte0]: 59
3384 22:53:01.806804 [Byte1]: 59
3385 22:53:01.806862
3386 22:53:01.806913 Set Vref, RX VrefLevel [Byte0]: 60
3387 22:53:01.806966 [Byte1]: 60
3388 22:53:01.807017
3389 22:53:01.807068 Set Vref, RX VrefLevel [Byte0]: 61
3390 22:53:01.807120 [Byte1]: 61
3391 22:53:01.807180
3392 22:53:01.807432 Set Vref, RX VrefLevel [Byte0]: 62
3393 22:53:01.807490 [Byte1]: 62
3394 22:53:01.807544
3395 22:53:01.807612 Set Vref, RX VrefLevel [Byte0]: 63
3396 22:53:01.807665 [Byte1]: 63
3397 22:53:01.807717
3398 22:53:01.807769 Final RX Vref Byte 0 = 58 to rank0
3399 22:53:01.807821 Final RX Vref Byte 1 = 49 to rank0
3400 22:53:01.807873 Final RX Vref Byte 0 = 58 to rank1
3401 22:53:01.807925 Final RX Vref Byte 1 = 49 to rank1==
3402 22:53:01.807994 Dram Type= 6, Freq= 0, CH_1, rank 0
3403 22:53:01.808047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 22:53:01.808104 ==
3405 22:53:01.808171 DQS Delay:
3406 22:53:01.808224 DQS0 = 0, DQS1 = 0
3407 22:53:01.808286 DQM Delay:
3408 22:53:01.808355 DQM0 = 114, DQM1 = 105
3409 22:53:01.808409 DQ Delay:
3410 22:53:01.808461 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =112
3411 22:53:01.808513 DQ4 =112, DQ5 =122, DQ6 =122, DQ7 =112
3412 22:53:01.808565 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3413 22:53:01.808616 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =112
3414 22:53:01.808668
3415 22:53:01.808736
3416 22:53:01.808789 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3417 22:53:01.808842 CH1 RK0: MR19=303, MR18=ECF3
3418 22:53:01.808893 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3419 22:53:01.808946
3420 22:53:01.808998 ----->DramcWriteLeveling(PI) begin...
3421 22:53:01.809051 ==
3422 22:53:01.809118 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 22:53:01.809170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 22:53:01.809222 ==
3425 22:53:01.809274 Write leveling (Byte 0): 25 => 25
3426 22:53:01.809325 Write leveling (Byte 1): 27 => 27
3427 22:53:01.809377 DramcWriteLeveling(PI) end<-----
3428 22:53:01.809452
3429 22:53:01.809572 ==
3430 22:53:01.809654 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 22:53:01.809736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 22:53:01.809824 ==
3433 22:53:01.809908 [Gating] SW mode calibration
3434 22:53:01.809990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3435 22:53:01.810073 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3436 22:53:01.810165 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3437 22:53:01.810255 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 22:53:01.810337 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 22:53:01.810419 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 22:53:01.810500 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 22:53:01.810586 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3442 22:53:01.810641 0 15 24 | B1->B0 | 3434 2626 | 0 0 | (0 1) (0 0)
3443 22:53:01.810693 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3444 22:53:01.810745 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 22:53:01.810797 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 22:53:01.810849 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 22:53:01.810900 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 22:53:01.810965 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 22:53:01.811020 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3450 22:53:01.811071 1 0 24 | B1->B0 | 2a29 4545 | 1 0 | (1 1) (0 0)
3451 22:53:01.811123 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3452 22:53:01.811175 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 22:53:01.811226 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 22:53:01.811278 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 22:53:01.811347 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 22:53:01.811401 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 22:53:01.811453 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 22:53:01.811504 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3459 22:53:01.811556 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 22:53:01.811608 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 22:53:01.811659 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 22:53:01.811727 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 22:53:01.811780 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 22:53:01.811832 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 22:53:01.811884 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 22:53:01.811935 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 22:53:01.811986 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 22:53:01.812037 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 22:53:01.812110 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 22:53:01.812179 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 22:53:01.812232 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 22:53:01.812283 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 22:53:01.812335 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 22:53:01.812386 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3475 22:53:01.812448 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 22:53:01.812532 Total UI for P1: 0, mck2ui 16
3477 22:53:01.812614 best dqsien dly found for B0: ( 1, 3, 24)
3478 22:53:01.812695 Total UI for P1: 0, mck2ui 16
3479 22:53:01.812777 best dqsien dly found for B1: ( 1, 3, 24)
3480 22:53:01.812855 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3481 22:53:01.812910 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3482 22:53:01.812971
3483 22:53:01.813024 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3484 22:53:01.813076 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3485 22:53:01.813128 [Gating] SW calibration Done
3486 22:53:01.813180 ==
3487 22:53:01.813247 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 22:53:01.813301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 22:53:01.813353 ==
3490 22:53:01.813405 RX Vref Scan: 0
3491 22:53:01.813459
3492 22:53:01.813521 RX Vref 0 -> 0, step: 1
3493 22:53:01.813586
3494 22:53:01.813642 RX Delay -40 -> 252, step: 8
3495 22:53:01.813704 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3496 22:53:01.813757 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3497 22:53:01.813809 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3498 22:53:01.813861 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3499 22:53:01.813912 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3500 22:53:01.814173 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3501 22:53:01.814236 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3502 22:53:01.814315 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3503 22:53:01.814371 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3504 22:53:01.814423 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3505 22:53:01.814476 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3506 22:53:01.814528 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3507 22:53:01.814596 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3508 22:53:01.814649 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3509 22:53:01.814701 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3510 22:53:01.814752 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3511 22:53:01.814804 ==
3512 22:53:01.814872 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 22:53:01.814926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 22:53:01.814978 ==
3515 22:53:01.815030 DQS Delay:
3516 22:53:01.815082 DQS0 = 0, DQS1 = 0
3517 22:53:01.815134 DQM Delay:
3518 22:53:01.815196 DQM0 = 110, DQM1 = 107
3519 22:53:01.815252 DQ Delay:
3520 22:53:01.815304 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3521 22:53:01.815357 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =107
3522 22:53:01.815408 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3523 22:53:01.815460 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3524 22:53:01.815511
3525 22:53:01.815573
3526 22:53:01.815628 ==
3527 22:53:01.815680 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 22:53:01.815732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 22:53:01.815784 ==
3530 22:53:01.815836
3531 22:53:01.815888
3532 22:53:01.815951 TX Vref Scan disable
3533 22:53:01.816010 == TX Byte 0 ==
3534 22:53:01.816061 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3535 22:53:01.816113 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3536 22:53:01.816165 == TX Byte 1 ==
3537 22:53:01.816217 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3538 22:53:01.816278 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3539 22:53:01.816348 ==
3540 22:53:01.816431 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 22:53:01.816512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 22:53:01.816593 ==
3543 22:53:01.816674 TX Vref=22, minBit 9, minWin=25, winSum=418
3544 22:53:01.816765 TX Vref=24, minBit 8, minWin=26, winSum=427
3545 22:53:01.816847 TX Vref=26, minBit 7, minWin=26, winSum=428
3546 22:53:01.816929 TX Vref=28, minBit 9, minWin=26, winSum=432
3547 22:53:01.817010 TX Vref=30, minBit 8, minWin=26, winSum=433
3548 22:53:01.817100 TX Vref=32, minBit 1, minWin=25, winSum=429
3549 22:53:01.817184 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3550 22:53:01.817265
3551 22:53:01.817346 Final TX Range 1 Vref 30
3552 22:53:01.817428
3553 22:53:01.817522 ==
3554 22:53:01.817610 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 22:53:01.817663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 22:53:01.817716 ==
3557 22:53:01.817767
3558 22:53:01.817831
3559 22:53:01.817885 TX Vref Scan disable
3560 22:53:01.817938 == TX Byte 0 ==
3561 22:53:01.817989 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3562 22:53:01.818042 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3563 22:53:01.818093 == TX Byte 1 ==
3564 22:53:01.818145 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3565 22:53:01.818211 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3566 22:53:01.818265
3567 22:53:01.818316 [DATLAT]
3568 22:53:01.818368 Freq=1200, CH1 RK1
3569 22:53:01.818420
3570 22:53:01.818472 DATLAT Default: 0xd
3571 22:53:01.818524 0, 0xFFFF, sum = 0
3572 22:53:01.818592 1, 0xFFFF, sum = 0
3573 22:53:01.818648 2, 0xFFFF, sum = 0
3574 22:53:01.818700 3, 0xFFFF, sum = 0
3575 22:53:01.818752 4, 0xFFFF, sum = 0
3576 22:53:01.818805 5, 0xFFFF, sum = 0
3577 22:53:01.818856 6, 0xFFFF, sum = 0
3578 22:53:01.818908 7, 0xFFFF, sum = 0
3579 22:53:01.818976 8, 0xFFFF, sum = 0
3580 22:53:01.819030 9, 0xFFFF, sum = 0
3581 22:53:01.819083 10, 0xFFFF, sum = 0
3582 22:53:01.819135 11, 0xFFFF, sum = 0
3583 22:53:01.819188 12, 0x0, sum = 1
3584 22:53:01.819240 13, 0x0, sum = 2
3585 22:53:01.819293 14, 0x0, sum = 3
3586 22:53:01.819385 15, 0x0, sum = 4
3587 22:53:01.819477 best_step = 13
3588 22:53:01.819558
3589 22:53:01.819656 ==
3590 22:53:01.819739 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 22:53:01.819821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 22:53:01.819901 ==
3593 22:53:01.819991 RX Vref Scan: 0
3594 22:53:01.820072
3595 22:53:01.820152 RX Vref 0 -> 0, step: 1
3596 22:53:01.820241
3597 22:53:01.820323 RX Delay -21 -> 252, step: 4
3598 22:53:01.820404 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3599 22:53:01.820486 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3600 22:53:01.820571 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3601 22:53:01.820657 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3602 22:53:01.820738 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3603 22:53:01.820819 iDelay=195, Bit 5, Center 118 (43 ~ 194) 152
3604 22:53:01.820900 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3605 22:53:01.820989 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3606 22:53:01.821071 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3607 22:53:01.821151 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3608 22:53:01.821236 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3609 22:53:01.821339 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3610 22:53:01.821422 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3611 22:53:01.821503 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3612 22:53:01.821573 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3613 22:53:01.821632 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3614 22:53:01.821685 ==
3615 22:53:01.821738 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 22:53:01.821790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 22:53:01.821841 ==
3618 22:53:01.821893 DQS Delay:
3619 22:53:01.821956 DQS0 = 0, DQS1 = 0
3620 22:53:01.822011 DQM Delay:
3621 22:53:01.822064 DQM0 = 111, DQM1 = 108
3622 22:53:01.822116 DQ Delay:
3623 22:53:01.822168 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =110
3624 22:53:01.822220 DQ4 =108, DQ5 =118, DQ6 =122, DQ7 =110
3625 22:53:01.822271 DQ8 =94, DQ9 =102, DQ10 =110, DQ11 =102
3626 22:53:01.822335 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3627 22:53:01.822390
3628 22:53:01.822441
3629 22:53:01.822493 [DQSOSCAuto] RK1, (LSB)MR18= 0xf909, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3630 22:53:01.822545 CH1 RK1: MR19=304, MR18=F909
3631 22:53:01.822597 CH1_RK1: MR19=0x304, MR18=0xF909, DQSOSC=406, MR23=63, INC=39, DEC=26
3632 22:53:01.822650 [RxdqsGatingPostProcess] freq 1200
3633 22:53:01.822717 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3634 22:53:01.822770 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 22:53:01.822833 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 22:53:01.822885 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 22:53:01.822937 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 22:53:01.823181 best DQS0 dly(2T, 0.5T) = (0, 11)
3639 22:53:01.823246 best DQS1 dly(2T, 0.5T) = (0, 11)
3640 22:53:01.823312 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3641 22:53:01.823365 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3642 22:53:01.823428 Pre-setting of DQS Precalculation
3643 22:53:01.823484 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3644 22:53:01.823536 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3645 22:53:01.823589 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3646 22:53:01.823641
3647 22:53:01.823697
3648 22:53:01.823757 [Calibration Summary] 2400 Mbps
3649 22:53:01.823810 CH 0, Rank 0
3650 22:53:01.823862 SW Impedance : PASS
3651 22:53:01.823914 DUTY Scan : NO K
3652 22:53:01.823966 ZQ Calibration : PASS
3653 22:53:01.824018 Jitter Meter : NO K
3654 22:53:01.824082 CBT Training : PASS
3655 22:53:01.824136 Write leveling : PASS
3656 22:53:01.824188 RX DQS gating : PASS
3657 22:53:01.824239 RX DQ/DQS(RDDQC) : PASS
3658 22:53:01.824290 TX DQ/DQS : PASS
3659 22:53:01.824342 RX DATLAT : PASS
3660 22:53:01.824394 RX DQ/DQS(Engine): PASS
3661 22:53:01.824458 TX OE : NO K
3662 22:53:01.824541 All Pass.
3663 22:53:01.824621
3664 22:53:01.824702 CH 0, Rank 1
3665 22:53:01.824782 SW Impedance : PASS
3666 22:53:01.824872 DUTY Scan : NO K
3667 22:53:01.824953 ZQ Calibration : PASS
3668 22:53:01.825034 Jitter Meter : NO K
3669 22:53:01.825124 CBT Training : PASS
3670 22:53:01.825213 Write leveling : PASS
3671 22:53:01.825295 RX DQS gating : PASS
3672 22:53:01.825375 RX DQ/DQS(RDDQC) : PASS
3673 22:53:01.825456 TX DQ/DQS : PASS
3674 22:53:01.825580 RX DATLAT : PASS
3675 22:53:01.825637 RX DQ/DQS(Engine): PASS
3676 22:53:01.825689 TX OE : NO K
3677 22:53:01.825741 All Pass.
3678 22:53:01.825793
3679 22:53:01.825845 CH 1, Rank 0
3680 22:53:01.825897 SW Impedance : PASS
3681 22:53:01.825962 DUTY Scan : NO K
3682 22:53:01.826016 ZQ Calibration : PASS
3683 22:53:01.826068 Jitter Meter : NO K
3684 22:53:01.826120 CBT Training : PASS
3685 22:53:01.826171 Write leveling : PASS
3686 22:53:01.826222 RX DQS gating : PASS
3687 22:53:01.826273 RX DQ/DQS(RDDQC) : PASS
3688 22:53:01.826347 TX DQ/DQS : PASS
3689 22:53:01.826402 RX DATLAT : PASS
3690 22:53:01.826454 RX DQ/DQS(Engine): PASS
3691 22:53:01.826505 TX OE : NO K
3692 22:53:01.826557 All Pass.
3693 22:53:01.826609
3694 22:53:01.826660 CH 1, Rank 1
3695 22:53:01.826728 SW Impedance : PASS
3696 22:53:01.826781 DUTY Scan : NO K
3697 22:53:01.826834 ZQ Calibration : PASS
3698 22:53:01.826886 Jitter Meter : NO K
3699 22:53:01.826938 CBT Training : PASS
3700 22:53:01.826990 Write leveling : PASS
3701 22:53:01.827041 RX DQS gating : PASS
3702 22:53:01.827110 RX DQ/DQS(RDDQC) : PASS
3703 22:53:01.827163 TX DQ/DQS : PASS
3704 22:53:01.827215 RX DATLAT : PASS
3705 22:53:01.827265 RX DQ/DQS(Engine): PASS
3706 22:53:01.827317 TX OE : NO K
3707 22:53:01.827368 All Pass.
3708 22:53:01.827420
3709 22:53:01.827491 DramC Write-DBI off
3710 22:53:01.827557 PER_BANK_REFRESH: Hybrid Mode
3711 22:53:01.827610 TX_TRACKING: ON
3712 22:53:01.827661 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3713 22:53:01.827714 [FAST_K] Save calibration result to emmc
3714 22:53:01.827765 dramc_set_vcore_voltage set vcore to 650000
3715 22:53:01.827827 Read voltage for 600, 5
3716 22:53:01.827882 Vio18 = 0
3717 22:53:01.827934 Vcore = 650000
3718 22:53:01.827986 Vdram = 0
3719 22:53:01.828037 Vddq = 0
3720 22:53:01.828088 Vmddr = 0
3721 22:53:01.828140 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3722 22:53:01.828203 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3723 22:53:01.828258 MEM_TYPE=3, freq_sel=19
3724 22:53:01.828310 sv_algorithm_assistance_LP4_1600
3725 22:53:01.828362 ============ PULL DRAM RESETB DOWN ============
3726 22:53:01.828413 ========== PULL DRAM RESETB DOWN end =========
3727 22:53:01.828465 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3728 22:53:01.828516 ===================================
3729 22:53:01.828581 LPDDR4 DRAM CONFIGURATION
3730 22:53:01.828664 ===================================
3731 22:53:01.828745 EX_ROW_EN[0] = 0x0
3732 22:53:01.828826 EX_ROW_EN[1] = 0x0
3733 22:53:01.828907 LP4Y_EN = 0x0
3734 22:53:01.828995 WORK_FSP = 0x0
3735 22:53:01.829076 WL = 0x2
3736 22:53:01.829157 RL = 0x2
3737 22:53:01.829237 BL = 0x2
3738 22:53:01.829325 RPST = 0x0
3739 22:53:01.829407 RD_PRE = 0x0
3740 22:53:01.829488 WR_PRE = 0x1
3741 22:53:01.829595 WR_PST = 0x0
3742 22:53:01.829660 DBI_WR = 0x0
3743 22:53:01.829729 DBI_RD = 0x0
3744 22:53:01.829782 OTF = 0x1
3745 22:53:01.829835 ===================================
3746 22:53:01.829887 ===================================
3747 22:53:01.829939 ANA top config
3748 22:53:01.829991 ===================================
3749 22:53:01.830043 DLL_ASYNC_EN = 0
3750 22:53:01.830111 ALL_SLAVE_EN = 1
3751 22:53:01.830164 NEW_RANK_MODE = 1
3752 22:53:01.830216 DLL_IDLE_MODE = 1
3753 22:53:01.830267 LP45_APHY_COMB_EN = 1
3754 22:53:01.830319 TX_ODT_DIS = 1
3755 22:53:01.830370 NEW_8X_MODE = 1
3756 22:53:01.830422 ===================================
3757 22:53:01.830489 ===================================
3758 22:53:01.830541 data_rate = 1200
3759 22:53:01.830593 CKR = 1
3760 22:53:01.830645 DQ_P2S_RATIO = 8
3761 22:53:01.830697 ===================================
3762 22:53:01.830749 CA_P2S_RATIO = 8
3763 22:53:01.830800 DQ_CA_OPEN = 0
3764 22:53:01.830866 DQ_SEMI_OPEN = 0
3765 22:53:01.830918 CA_SEMI_OPEN = 0
3766 22:53:01.830970 CA_FULL_RATE = 0
3767 22:53:01.831031 DQ_CKDIV4_EN = 1
3768 22:53:01.831084 CA_CKDIV4_EN = 1
3769 22:53:01.831135 CA_PREDIV_EN = 0
3770 22:53:01.831199 PH8_DLY = 0
3771 22:53:01.831253 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3772 22:53:01.831305 DQ_AAMCK_DIV = 4
3773 22:53:01.831356 CA_AAMCK_DIV = 4
3774 22:53:01.831407 CA_ADMCK_DIV = 4
3775 22:53:01.831464 DQ_TRACK_CA_EN = 0
3776 22:53:01.831523 CA_PICK = 600
3777 22:53:01.831576 CA_MCKIO = 600
3778 22:53:01.831640 MCKIO_SEMI = 0
3779 22:53:01.831700 PLL_FREQ = 2288
3780 22:53:01.831751 DQ_UI_PI_RATIO = 32
3781 22:53:01.831805 CA_UI_PI_RATIO = 0
3782 22:53:01.831868 ===================================
3783 22:53:01.831921 ===================================
3784 22:53:01.832165 memory_type:LPDDR4
3785 22:53:01.832239 GP_NUM : 10
3786 22:53:01.832293 SRAM_EN : 1
3787 22:53:01.832345 MD32_EN : 0
3788 22:53:01.832397 ===================================
3789 22:53:01.832449 [ANA_INIT] >>>>>>>>>>>>>>
3790 22:53:01.832500 <<<<<< [CONFIGURE PHASE]: ANA_TX
3791 22:53:01.832556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3792 22:53:01.832644 ===================================
3793 22:53:01.832736 data_rate = 1200,PCW = 0X5800
3794 22:53:01.832817 ===================================
3795 22:53:01.832899 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3796 22:53:01.832990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 22:53:01.833072 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 22:53:01.833155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3799 22:53:01.833236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3800 22:53:01.833324 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3801 22:53:01.833407 [ANA_INIT] flow start
3802 22:53:01.833488 [ANA_INIT] PLL >>>>>>>>
3803 22:53:01.833621 [ANA_INIT] PLL <<<<<<<<
3804 22:53:01.833714 [ANA_INIT] MIDPI >>>>>>>>
3805 22:53:01.833769 [ANA_INIT] MIDPI <<<<<<<<
3806 22:53:01.833821 [ANA_INIT] DLL >>>>>>>>
3807 22:53:01.833873 [ANA_INIT] flow end
3808 22:53:01.833924 ============ LP4 DIFF to SE enter ============
3809 22:53:01.833976 ============ LP4 DIFF to SE exit ============
3810 22:53:01.834028 [ANA_INIT] <<<<<<<<<<<<<
3811 22:53:01.834097 [Flow] Enable top DCM control >>>>>
3812 22:53:01.834151 [Flow] Enable top DCM control <<<<<
3813 22:53:01.834203 Enable DLL master slave shuffle
3814 22:53:01.834255 ==============================================================
3815 22:53:01.834307 Gating Mode config
3816 22:53:01.834359 ==============================================================
3817 22:53:01.834412 Config description:
3818 22:53:01.834480 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3819 22:53:01.834535 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3820 22:53:01.834588 SELPH_MODE 0: By rank 1: By Phase
3821 22:53:01.834641 ==============================================================
3822 22:53:01.834693 GAT_TRACK_EN = 1
3823 22:53:01.834744 RX_GATING_MODE = 2
3824 22:53:01.834796 RX_GATING_TRACK_MODE = 2
3825 22:53:01.834863 SELPH_MODE = 1
3826 22:53:01.834916 PICG_EARLY_EN = 1
3827 22:53:01.834968 VALID_LAT_VALUE = 1
3828 22:53:01.835019 ==============================================================
3829 22:53:01.835071 Enter into Gating configuration >>>>
3830 22:53:01.835123 Exit from Gating configuration <<<<
3831 22:53:01.835174 Enter into DVFS_PRE_config >>>>>
3832 22:53:01.835241 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3833 22:53:01.835295 Exit from DVFS_PRE_config <<<<<
3834 22:53:01.835347 Enter into PICG configuration >>>>
3835 22:53:01.835399 Exit from PICG configuration <<<<
3836 22:53:01.835451 [RX_INPUT] configuration >>>>>
3837 22:53:01.835503 [RX_INPUT] configuration <<<<<
3838 22:53:01.835559 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3839 22:53:01.835634 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3840 22:53:01.835687 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 22:53:01.835740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 22:53:01.835791 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 22:53:01.835843 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 22:53:01.835895 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3845 22:53:01.835958 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3846 22:53:01.836013 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3847 22:53:01.836066 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3848 22:53:01.836118 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3849 22:53:01.836170 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3850 22:53:01.836232 ===================================
3851 22:53:01.836284 LPDDR4 DRAM CONFIGURATION
3852 22:53:01.836364 ===================================
3853 22:53:01.836446 EX_ROW_EN[0] = 0x0
3854 22:53:01.836527 EX_ROW_EN[1] = 0x0
3855 22:53:01.836607 LP4Y_EN = 0x0
3856 22:53:01.836693 WORK_FSP = 0x0
3857 22:53:01.836777 WL = 0x2
3858 22:53:01.836857 RL = 0x2
3859 22:53:01.836937 BL = 0x2
3860 22:53:01.837017 RPST = 0x0
3861 22:53:01.837115 RD_PRE = 0x0
3862 22:53:01.837197 WR_PRE = 0x1
3863 22:53:01.837278 WR_PST = 0x0
3864 22:53:01.837358 DBI_WR = 0x0
3865 22:53:01.837445 DBI_RD = 0x0
3866 22:53:01.837548 OTF = 0x1
3867 22:53:01.837620 ===================================
3868 22:53:01.837688 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3869 22:53:01.837741 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3870 22:53:01.837794 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3871 22:53:01.837863 ===================================
3872 22:53:01.837916 LPDDR4 DRAM CONFIGURATION
3873 22:53:01.837969 ===================================
3874 22:53:01.838020 EX_ROW_EN[0] = 0x10
3875 22:53:01.838072 EX_ROW_EN[1] = 0x0
3876 22:53:01.838123 LP4Y_EN = 0x0
3877 22:53:01.838175 WORK_FSP = 0x0
3878 22:53:01.838239 WL = 0x2
3879 22:53:01.838291 RL = 0x2
3880 22:53:01.838342 BL = 0x2
3881 22:53:01.838393 RPST = 0x0
3882 22:53:01.838445 RD_PRE = 0x0
3883 22:53:01.838496 WR_PRE = 0x1
3884 22:53:01.838548 WR_PST = 0x0
3885 22:53:01.838613 DBI_WR = 0x0
3886 22:53:01.838665 DBI_RD = 0x0
3887 22:53:01.838717 OTF = 0x1
3888 22:53:01.838768 ===================================
3889 22:53:01.838819 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3890 22:53:01.838873 nWR fixed to 30
3891 22:53:01.838925 [ModeRegInit_LP4] CH0 RK0
3892 22:53:01.838990 [ModeRegInit_LP4] CH0 RK1
3893 22:53:01.839235 [ModeRegInit_LP4] CH1 RK0
3894 22:53:01.839314 [ModeRegInit_LP4] CH1 RK1
3895 22:53:01.839371 match AC timing 17
3896 22:53:01.839424 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3897 22:53:01.839476 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3898 22:53:01.839529 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3899 22:53:01.839595 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3900 22:53:01.839660 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3901 22:53:01.839713 ==
3902 22:53:01.839766 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 22:53:01.839818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3904 22:53:01.839869 ==
3905 22:53:01.839921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3906 22:53:01.839991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3907 22:53:01.840044 [CA 0] Center 37 (7~67) winsize 61
3908 22:53:01.840096 [CA 1] Center 36 (6~67) winsize 62
3909 22:53:01.840147 [CA 2] Center 35 (5~65) winsize 61
3910 22:53:01.840199 [CA 3] Center 35 (5~65) winsize 61
3911 22:53:01.840251 [CA 4] Center 34 (4~65) winsize 62
3912 22:53:01.840301 [CA 5] Center 34 (4~64) winsize 61
3913 22:53:01.840368
3914 22:53:01.840420 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3915 22:53:01.840472
3916 22:53:01.840524 [CATrainingPosCal] consider 1 rank data
3917 22:53:01.840576 u2DelayCellTimex100 = 270/100 ps
3918 22:53:01.840628 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3919 22:53:01.840684 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3920 22:53:01.840745 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3921 22:53:01.840797 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3922 22:53:01.840849 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3923 22:53:01.840900 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3924 22:53:01.840952
3925 22:53:01.841003 CA PerBit enable=1, Macro0, CA PI delay=34
3926 22:53:01.841060
3927 22:53:01.841119 [CBTSetCACLKResult] CA Dly = 34
3928 22:53:02.108546 CS Dly: 7 (0~38)
3929 22:53:02.109056 ==
3930 22:53:02.109408 Dram Type= 6, Freq= 0, CH_0, rank 1
3931 22:53:02.109801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3932 22:53:02.110113 ==
3933 22:53:02.110432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3934 22:53:02.110749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3935 22:53:02.111070 [CA 0] Center 37 (7~67) winsize 61
3936 22:53:02.111372 [CA 1] Center 37 (7~67) winsize 61
3937 22:53:02.111654 [CA 2] Center 35 (5~65) winsize 61
3938 22:53:02.111953 [CA 3] Center 35 (5~65) winsize 61
3939 22:53:02.112256 [CA 4] Center 34 (4~65) winsize 62
3940 22:53:02.112538 [CA 5] Center 34 (3~65) winsize 63
3941 22:53:02.112827
3942 22:53:02.113129 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3943 22:53:02.113412
3944 22:53:02.113771 [CATrainingPosCal] consider 2 rank data
3945 22:53:02.114080 u2DelayCellTimex100 = 270/100 ps
3946 22:53:02.114357 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3947 22:53:02.114654 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3948 22:53:02.114957 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3949 22:53:02.115232 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3950 22:53:02.115528 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3951 22:53:02.115830 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3952 22:53:02.116118
3953 22:53:02.116395 CA PerBit enable=1, Macro0, CA PI delay=34
3954 22:53:02.116686
3955 22:53:02.116987 [CBTSetCACLKResult] CA Dly = 34
3956 22:53:02.117258 CS Dly: 7 (0~38)
3957 22:53:02.117579
3958 22:53:02.117884 ----->DramcWriteLeveling(PI) begin...
3959 22:53:02.118183 ==
3960 22:53:02.118462 Dram Type= 6, Freq= 0, CH_0, rank 0
3961 22:53:02.118765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 22:53:02.119053 ==
3963 22:53:02.119335 Write leveling (Byte 0): 32 => 32
3964 22:53:02.119631 Write leveling (Byte 1): 29 => 29
3965 22:53:02.119906 DramcWriteLeveling(PI) end<-----
3966 22:53:02.120195
3967 22:53:02.120492 ==
3968 22:53:02.120784 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 22:53:02.121107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 22:53:02.121400 ==
3971 22:53:02.121731 [Gating] SW mode calibration
3972 22:53:02.122009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3973 22:53:02.122308 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3974 22:53:02.122601 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 22:53:02.122879 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 22:53:02.123174 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 22:53:02.123547 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3978 22:53:02.123983 0 9 16 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (0 0)
3979 22:53:02.124299 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 22:53:02.124600 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 22:53:02.124874 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 22:53:02.125307 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 22:53:02.125788 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 22:53:02.126105 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 22:53:02.126388 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3986 22:53:02.126683 0 10 16 | B1->B0 | 2b2b 3737 | 1 1 | (0 0) (0 0)
3987 22:53:02.126977 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
3988 22:53:02.127254 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 22:53:02.127557 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 22:53:02.127848 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 22:53:02.128127 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 22:53:02.128421 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 22:53:02.128710 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 22:53:02.128986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 22:53:02.129273 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 22:53:02.129604 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 22:53:02.129874 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 22:53:02.130086 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 22:53:02.130279 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 22:53:02.130488 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 22:53:02.130690 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 22:53:02.131218 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 22:53:02.131452 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 22:53:02.131656 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 22:53:02.131867 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 22:53:02.132065 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 22:53:02.132281 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 22:53:02.132474 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 22:53:02.132751 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4010 22:53:02.133061 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 22:53:02.133366 Total UI for P1: 0, mck2ui 16
4012 22:53:02.133656 best dqsien dly found for B0: ( 0, 13, 12)
4013 22:53:02.133867 Total UI for P1: 0, mck2ui 16
4014 22:53:02.134074 best dqsien dly found for B1: ( 0, 13, 14)
4015 22:53:02.134274 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4016 22:53:02.134481 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4017 22:53:02.134679
4018 22:53:02.134884 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4019 22:53:02.135033 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4020 22:53:02.135188 [Gating] SW calibration Done
4021 22:53:02.135336 ==
4022 22:53:02.135482 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 22:53:02.135648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 22:53:02.135798 ==
4025 22:53:02.135956 RX Vref Scan: 0
4026 22:53:02.136105
4027 22:53:02.136251 RX Vref 0 -> 0, step: 1
4028 22:53:02.136411
4029 22:53:02.136558 RX Delay -230 -> 252, step: 16
4030 22:53:02.136715 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4031 22:53:02.136871 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4032 22:53:02.137053 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4033 22:53:02.137206 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4034 22:53:02.137350 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4035 22:53:02.137563 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4036 22:53:02.137717 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4037 22:53:02.137880 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4038 22:53:02.138027 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4039 22:53:02.138183 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4040 22:53:02.138331 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4041 22:53:02.138477 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4042 22:53:02.138640 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4043 22:53:02.138788 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4044 22:53:02.138942 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4045 22:53:02.139090 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4046 22:53:02.139235 ==
4047 22:53:02.139399 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 22:53:02.139546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 22:53:02.139704 ==
4050 22:53:02.139855 DQS Delay:
4051 22:53:02.139972 DQS0 = 0, DQS1 = 0
4052 22:53:02.140100 DQM Delay:
4053 22:53:02.140219 DQM0 = 39, DQM1 = 30
4054 22:53:02.140346 DQ Delay:
4055 22:53:02.140465 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4056 22:53:02.140582 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =49
4057 22:53:02.140706 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4058 22:53:02.140825 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4059 22:53:02.140942
4060 22:53:02.141065
4061 22:53:02.141183 ==
4062 22:53:02.141307 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 22:53:02.141429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 22:53:02.141562 ==
4065 22:53:02.141698
4066 22:53:02.141877
4067 22:53:02.142062 TX Vref Scan disable
4068 22:53:02.142244 == TX Byte 0 ==
4069 22:53:02.142436 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4070 22:53:02.142620 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4071 22:53:02.142805 == TX Byte 1 ==
4072 22:53:02.143007 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4073 22:53:02.143220 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4074 22:53:02.143405 ==
4075 22:53:02.143595 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 22:53:02.143780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 22:53:02.143915 ==
4078 22:53:02.144034
4079 22:53:02.144154
4080 22:53:02.144278 TX Vref Scan disable
4081 22:53:02.144395 == TX Byte 0 ==
4082 22:53:02.144511 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4083 22:53:02.144696 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4084 22:53:02.144852 == TX Byte 1 ==
4085 22:53:02.144963 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4086 22:53:02.145063 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4087 22:53:02.145159
4088 22:53:02.145265 [DATLAT]
4089 22:53:02.145362 Freq=600, CH0 RK0
4090 22:53:02.145461
4091 22:53:02.145580 DATLAT Default: 0x9
4092 22:53:02.145681 0, 0xFFFF, sum = 0
4093 22:53:02.145780 1, 0xFFFF, sum = 0
4094 22:53:02.145888 2, 0xFFFF, sum = 0
4095 22:53:02.145989 3, 0xFFFF, sum = 0
4096 22:53:02.146087 4, 0xFFFF, sum = 0
4097 22:53:02.146193 5, 0xFFFF, sum = 0
4098 22:53:02.146294 6, 0xFFFF, sum = 0
4099 22:53:02.146392 7, 0xFFFF, sum = 0
4100 22:53:02.146500 8, 0x0, sum = 1
4101 22:53:02.146599 9, 0x0, sum = 2
4102 22:53:02.146698 10, 0x0, sum = 3
4103 22:53:02.146804 11, 0x0, sum = 4
4104 22:53:02.146905 best_step = 9
4105 22:53:02.147003
4106 22:53:02.147110 ==
4107 22:53:02.147208 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 22:53:02.147306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 22:53:02.147409 ==
4110 22:53:02.147511 RX Vref Scan: 1
4111 22:53:02.147608
4112 22:53:02.147711 RX Vref 0 -> 0, step: 1
4113 22:53:02.147808
4114 22:53:02.147905 RX Delay -195 -> 252, step: 8
4115 22:53:02.148003
4116 22:53:02.148156 Set Vref, RX VrefLevel [Byte0]: 63
4117 22:53:02.148313 [Byte1]: 58
4118 22:53:02.148464
4119 22:53:02.148615 Final RX Vref Byte 0 = 63 to rank0
4120 22:53:02.148773 Final RX Vref Byte 1 = 58 to rank0
4121 22:53:02.148925 Final RX Vref Byte 0 = 63 to rank1
4122 22:53:02.149083 Final RX Vref Byte 1 = 58 to rank1==
4123 22:53:02.149236 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 22:53:02.149394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 22:53:02.149555 ==
4126 22:53:02.149664 DQS Delay:
4127 22:53:02.149765 DQS0 = 0, DQS1 = 0
4128 22:53:02.149864 DQM Delay:
4129 22:53:02.149948 DQM0 = 35, DQM1 = 28
4130 22:53:02.150038 DQ Delay:
4131 22:53:02.150123 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4132 22:53:02.150207 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =44
4133 22:53:02.150290 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4134 22:53:02.150374 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4135 22:53:02.150468
4136 22:53:02.150553
4137 22:53:02.150636 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4138 22:53:02.150731 CH0 RK0: MR19=808, MR18=3F3E
4139 22:53:02.150815 CH0_RK0: MR19=0x808, MR18=0x3F3E, DQSOSC=397, MR23=63, INC=166, DEC=110
4140 22:53:02.150900
4141 22:53:02.150992 ----->DramcWriteLeveling(PI) begin...
4142 22:53:02.151078 ==
4143 22:53:02.151162 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 22:53:02.151467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 22:53:02.151571 ==
4146 22:53:02.151658 Write leveling (Byte 0): 32 => 32
4147 22:53:02.151744 Write leveling (Byte 1): 31 => 31
4148 22:53:02.151835 DramcWriteLeveling(PI) end<-----
4149 22:53:02.151921
4150 22:53:02.152004 ==
4151 22:53:02.152087 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 22:53:02.152184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 22:53:02.152315 ==
4154 22:53:02.152449 [Gating] SW mode calibration
4155 22:53:02.152583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 22:53:02.152716 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 22:53:02.152852 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 22:53:02.152984 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 22:53:02.153110 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 22:53:02.153198 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4161 22:53:02.153282 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
4162 22:53:02.153367 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 22:53:02.153485 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 22:53:02.153592 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 22:53:02.153684 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 22:53:02.153771 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 22:53:02.153855 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4168 22:53:02.153939 0 10 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (0 0)
4169 22:53:02.154026 0 10 16 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
4170 22:53:02.154114 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 22:53:02.154198 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 22:53:02.154282 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 22:53:02.154372 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 22:53:02.154456 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 22:53:02.154539 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 22:53:02.154623 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4177 22:53:02.154717 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 22:53:02.154801 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 22:53:02.154888 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 22:53:02.154971 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 22:53:02.155045 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 22:53:02.155118 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 22:53:02.155197 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 22:53:02.155271 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 22:53:02.155344 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 22:53:02.155417 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 22:53:02.155489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 22:53:02.155571 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 22:53:02.155645 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 22:53:02.155718 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 22:53:02.155797 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 22:53:02.155873 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4193 22:53:02.155945 Total UI for P1: 0, mck2ui 16
4194 22:53:02.156020 best dqsien dly found for B0: ( 0, 13, 10)
4195 22:53:02.156124 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 22:53:02.156239 Total UI for P1: 0, mck2ui 16
4197 22:53:02.156354 best dqsien dly found for B1: ( 0, 13, 14)
4198 22:53:02.156472 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4199 22:53:02.156587 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4200 22:53:02.156705
4201 22:53:02.156820 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4202 22:53:02.156938 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4203 22:53:02.157063 [Gating] SW calibration Done
4204 22:53:02.157171 ==
4205 22:53:02.157266 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 22:53:02.157349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 22:53:02.157425 ==
4208 22:53:02.157500 RX Vref Scan: 0
4209 22:53:02.157586
4210 22:53:02.157667 RX Vref 0 -> 0, step: 1
4211 22:53:02.157743
4212 22:53:02.157817 RX Delay -230 -> 252, step: 16
4213 22:53:02.157891 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4214 22:53:02.157964 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4215 22:53:02.158043 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4216 22:53:02.158119 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4217 22:53:02.158192 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4218 22:53:02.158265 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4219 22:53:02.158338 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4220 22:53:02.158416 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4221 22:53:02.158490 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4222 22:53:02.158562 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4223 22:53:02.158635 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4224 22:53:02.158709 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4225 22:53:02.158787 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4226 22:53:02.158862 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4227 22:53:02.158934 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4228 22:53:02.159008 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4229 22:53:02.159089 ==
4230 22:53:02.159164 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 22:53:02.159237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 22:53:02.159311 ==
4233 22:53:02.159385 DQS Delay:
4234 22:53:02.159464 DQS0 = 0, DQS1 = 0
4235 22:53:02.159538 DQM Delay:
4236 22:53:02.159612 DQM0 = 35, DQM1 = 27
4237 22:53:02.159690 DQ Delay:
4238 22:53:02.159765 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4239 22:53:02.159848 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4240 22:53:02.159914 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4241 22:53:02.159984 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4242 22:53:02.160049
4243 22:53:02.160115
4244 22:53:02.160179 ==
4245 22:53:02.160245 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 22:53:02.160336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 22:53:02.160438 ==
4248 22:53:02.160542
4249 22:53:02.160642
4250 22:53:02.160743 TX Vref Scan disable
4251 22:53:02.160849 == TX Byte 0 ==
4252 22:53:02.160951 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4253 22:53:02.161261 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4254 22:53:02.161372 == TX Byte 1 ==
4255 22:53:02.161475 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4256 22:53:02.161590 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4257 22:53:02.161685 ==
4258 22:53:02.161754 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 22:53:02.161821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 22:53:02.161887 ==
4261 22:53:02.161962
4262 22:53:02.162028
4263 22:53:02.162094 TX Vref Scan disable
4264 22:53:02.162160 == TX Byte 0 ==
4265 22:53:02.162231 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4266 22:53:02.162297 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4267 22:53:02.162363 == TX Byte 1 ==
4268 22:53:02.162428 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4269 22:53:02.162493 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4270 22:53:02.162565
4271 22:53:02.162632 [DATLAT]
4272 22:53:02.162697 Freq=600, CH0 RK1
4273 22:53:02.162763
4274 22:53:02.162835 DATLAT Default: 0x9
4275 22:53:02.162901 0, 0xFFFF, sum = 0
4276 22:53:02.162968 1, 0xFFFF, sum = 0
4277 22:53:02.163039 2, 0xFFFF, sum = 0
4278 22:53:02.163108 3, 0xFFFF, sum = 0
4279 22:53:02.163175 4, 0xFFFF, sum = 0
4280 22:53:02.163241 5, 0xFFFF, sum = 0
4281 22:53:02.163311 6, 0xFFFF, sum = 0
4282 22:53:02.163379 7, 0xFFFF, sum = 0
4283 22:53:02.163445 8, 0x0, sum = 1
4284 22:53:02.163511 9, 0x0, sum = 2
4285 22:53:02.163576 10, 0x0, sum = 3
4286 22:53:02.163642 11, 0x0, sum = 4
4287 22:53:02.163714 best_step = 9
4288 22:53:02.163781
4289 22:53:02.163845 ==
4290 22:53:02.163916 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 22:53:02.164021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 22:53:02.164123 ==
4293 22:53:02.164228 RX Vref Scan: 0
4294 22:53:02.164328
4295 22:53:02.164429 RX Vref 0 -> 0, step: 1
4296 22:53:02.164532
4297 22:53:02.164634 RX Delay -195 -> 252, step: 8
4298 22:53:02.164736 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4299 22:53:02.164853 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4300 22:53:02.164945 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4301 22:53:02.165036 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4302 22:53:02.165131 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4303 22:53:02.165222 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4304 22:53:02.165313 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4305 22:53:02.165406 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4306 22:53:02.165499 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4307 22:53:02.165574 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4308 22:53:02.165634 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4309 22:53:02.165700 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4310 22:53:02.165759 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4311 22:53:02.165818 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4312 22:53:02.165877 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4313 22:53:02.165942 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4314 22:53:02.166001 ==
4315 22:53:02.166060 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 22:53:02.166119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 22:53:02.166181 ==
4318 22:53:02.166241 DQS Delay:
4319 22:53:02.166299 DQS0 = 0, DQS1 = 0
4320 22:53:02.166358 DQM Delay:
4321 22:53:02.166416 DQM0 = 33, DQM1 = 27
4322 22:53:02.166479 DQ Delay:
4323 22:53:02.166538 DQ0 =32, DQ1 =32, DQ2 =32, DQ3 =28
4324 22:53:02.166596 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4325 22:53:02.166654 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4326 22:53:02.166713 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4327 22:53:02.166771
4328 22:53:02.166834
4329 22:53:02.166892 [DQSOSCAuto] RK1, (LSB)MR18= 0x6636, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4330 22:53:02.166952 CH0 RK1: MR19=808, MR18=6636
4331 22:53:02.167010 CH0_RK1: MR19=0x808, MR18=0x6636, DQSOSC=390, MR23=63, INC=172, DEC=114
4332 22:53:02.167078 [RxdqsGatingPostProcess] freq 600
4333 22:53:02.167138 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 22:53:02.167197 Pre-setting of DQS Precalculation
4335 22:53:02.167256 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 22:53:02.167320 ==
4337 22:53:02.167380 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 22:53:02.167439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 22:53:02.167498 ==
4340 22:53:02.167568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 22:53:02.167661 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4342 22:53:02.167753 [CA 0] Center 36 (6~66) winsize 61
4343 22:53:02.167847 [CA 1] Center 35 (5~66) winsize 62
4344 22:53:02.167939 [CA 2] Center 34 (4~65) winsize 62
4345 22:53:02.168030 [CA 3] Center 34 (3~65) winsize 63
4346 22:53:02.168120 [CA 4] Center 34 (4~65) winsize 62
4347 22:53:02.168214 [CA 5] Center 34 (4~64) winsize 61
4348 22:53:02.168304
4349 22:53:02.168396 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4350 22:53:02.168489
4351 22:53:02.168580 [CATrainingPosCal] consider 1 rank data
4352 22:53:02.168674 u2DelayCellTimex100 = 270/100 ps
4353 22:53:02.168766 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4354 22:53:02.168857 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4355 22:53:02.168951 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4356 22:53:02.169043 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4357 22:53:02.169133 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4358 22:53:02.169228 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4359 22:53:02.169318
4360 22:53:02.169409 CA PerBit enable=1, Macro0, CA PI delay=34
4361 22:53:02.169505
4362 22:53:02.169582 [CBTSetCACLKResult] CA Dly = 34
4363 22:53:02.169643 CS Dly: 5 (0~36)
4364 22:53:02.169708 ==
4365 22:53:02.169767 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 22:53:02.169837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 22:53:02.169891 ==
4368 22:53:02.169944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 22:53:02.169998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4370 22:53:02.170059 [CA 0] Center 35 (5~66) winsize 62
4371 22:53:02.170113 [CA 1] Center 35 (5~66) winsize 62
4372 22:53:02.170166 [CA 2] Center 34 (4~65) winsize 62
4373 22:53:02.170219 [CA 3] Center 34 (4~65) winsize 62
4374 22:53:02.170272 [CA 4] Center 34 (4~65) winsize 62
4375 22:53:02.170330 [CA 5] Center 34 (3~65) winsize 63
4376 22:53:02.170383
4377 22:53:02.170436 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4378 22:53:02.170489
4379 22:53:02.170546 [CATrainingPosCal] consider 2 rank data
4380 22:53:02.170601 u2DelayCellTimex100 = 270/100 ps
4381 22:53:02.170653 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4382 22:53:02.170706 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4383 22:53:02.170759 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4384 22:53:02.170817 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 22:53:02.171068 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 22:53:02.171131 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4387 22:53:02.171185
4388 22:53:02.171238 CA PerBit enable=1, Macro0, CA PI delay=34
4389 22:53:02.171295
4390 22:53:02.171349 [CBTSetCACLKResult] CA Dly = 34
4391 22:53:02.171403 CS Dly: 5 (0~36)
4392 22:53:02.171456
4393 22:53:02.171509 ----->DramcWriteLeveling(PI) begin...
4394 22:53:02.171572 ==
4395 22:53:02.171656 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 22:53:02.171740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 22:53:02.171823 ==
4398 22:53:02.171909 Write leveling (Byte 0): 28 => 28
4399 22:53:02.171993 Write leveling (Byte 1): 31 => 31
4400 22:53:02.172078 DramcWriteLeveling(PI) end<-----
4401 22:53:02.172161
4402 22:53:02.172243 ==
4403 22:53:02.172329 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 22:53:02.172413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 22:53:02.172496 ==
4406 22:53:02.172578 [Gating] SW mode calibration
4407 22:53:02.172665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 22:53:02.172749 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 22:53:02.172833 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 22:53:02.172917 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 22:53:02.173001 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4412 22:53:02.173087 0 9 12 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 0)
4413 22:53:02.173170 0 9 16 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
4414 22:53:02.173253 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 22:53:02.173336 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 22:53:02.173421 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 22:53:02.173504 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 22:53:02.173596 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 22:53:02.173681 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 22:53:02.173765 0 10 12 | B1->B0 | 2929 3030 | 0 1 | (0 0) (0 0)
4421 22:53:02.173848 0 10 16 | B1->B0 | 3f3f 4040 | 0 0 | (0 0) (0 0)
4422 22:53:02.173928 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 22:53:02.173983 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 22:53:02.174036 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 22:53:02.174089 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 22:53:02.174142 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 22:53:02.174202 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 22:53:02.174255 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 22:53:02.174308 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4430 22:53:02.174361 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 22:53:02.174420 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 22:53:02.174504 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 22:53:02.174587 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 22:53:02.174672 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 22:53:02.174761 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 22:53:02.174856 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 22:53:02.174938 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 22:53:02.175026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 22:53:02.175109 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 22:53:02.175190 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 22:53:02.175271 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 22:53:02.175353 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 22:53:02.175438 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 22:53:02.175520 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:53:02.175601 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4446 22:53:02.175682 Total UI for P1: 0, mck2ui 16
4447 22:53:02.175764 best dqsien dly found for B1: ( 0, 13, 14)
4448 22:53:02.175823 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 22:53:02.175875 Total UI for P1: 0, mck2ui 16
4450 22:53:02.175928 best dqsien dly found for B0: ( 0, 13, 16)
4451 22:53:02.175980 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4452 22:53:02.176032 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4453 22:53:02.176083
4454 22:53:02.176136 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4455 22:53:02.176194 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4456 22:53:02.176246 [Gating] SW calibration Done
4457 22:53:02.176298 ==
4458 22:53:02.176350 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 22:53:02.176402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 22:53:02.176454 ==
4461 22:53:02.176507 RX Vref Scan: 0
4462 22:53:02.176586
4463 22:53:02.176670 RX Vref 0 -> 0, step: 1
4464 22:53:02.176767
4465 22:53:02.176825 RX Delay -230 -> 252, step: 16
4466 22:53:02.176879 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4467 22:53:02.176939 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4468 22:53:02.176992 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4469 22:53:02.177044 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4470 22:53:02.177096 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4471 22:53:02.177149 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4472 22:53:02.177201 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4473 22:53:02.177253 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4474 22:53:02.177329 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4475 22:53:02.177411 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4476 22:53:02.177492 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4477 22:53:02.177587 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4478 22:53:02.177640 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4479 22:53:02.177697 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4480 22:53:02.177750 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4481 22:53:02.177802 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4482 22:53:02.177854 ==
4483 22:53:02.177907 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 22:53:02.177959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 22:53:02.178012 ==
4486 22:53:02.178069 DQS Delay:
4487 22:53:02.178122 DQS0 = 0, DQS1 = 0
4488 22:53:02.178174 DQM Delay:
4489 22:53:02.178225 DQM0 = 38, DQM1 = 29
4490 22:53:02.178278 DQ Delay:
4491 22:53:02.178330 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4492 22:53:02.178577 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4493 22:53:02.178635 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4494 22:53:02.178689 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4495 22:53:02.178741
4496 22:53:02.178799
4497 22:53:02.178853 ==
4498 22:53:02.178905 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 22:53:02.178958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 22:53:02.179010 ==
4501 22:53:02.179068
4502 22:53:02.179120
4503 22:53:02.179171 TX Vref Scan disable
4504 22:53:02.179224 == TX Byte 0 ==
4505 22:53:02.179275 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 22:53:02.179328 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 22:53:02.179380 == TX Byte 1 ==
4508 22:53:02.179438 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4509 22:53:02.179491 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4510 22:53:02.179543 ==
4511 22:53:02.179596 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 22:53:02.179648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 22:53:02.179700 ==
4514 22:53:02.179752
4515 22:53:02.179825
4516 22:53:02.179906 TX Vref Scan disable
4517 22:53:02.179987 == TX Byte 0 ==
4518 22:53:02.180068 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4519 22:53:02.180152 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4520 22:53:02.180233 == TX Byte 1 ==
4521 22:53:02.180314 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4522 22:53:02.180397 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4523 22:53:02.180477
4524 22:53:02.180551 [DATLAT]
4525 22:53:02.180604 Freq=600, CH1 RK0
4526 22:53:02.180657
4527 22:53:02.180728 DATLAT Default: 0x9
4528 22:53:02.180787 0, 0xFFFF, sum = 0
4529 22:53:02.180866 1, 0xFFFF, sum = 0
4530 22:53:02.180965 2, 0xFFFF, sum = 0
4531 22:53:02.181049 3, 0xFFFF, sum = 0
4532 22:53:02.181133 4, 0xFFFF, sum = 0
4533 22:53:02.181215 5, 0xFFFF, sum = 0
4534 22:53:02.181301 6, 0xFFFF, sum = 0
4535 22:53:02.181384 7, 0xFFFF, sum = 0
4536 22:53:02.181466 8, 0x0, sum = 1
4537 22:53:02.181596 9, 0x0, sum = 2
4538 22:53:02.181682 10, 0x0, sum = 3
4539 22:53:02.181766 11, 0x0, sum = 4
4540 22:53:02.181849 best_step = 9
4541 22:53:02.181938
4542 22:53:02.181994 ==
4543 22:53:02.182053 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 22:53:02.182106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 22:53:02.182159 ==
4546 22:53:02.182211 RX Vref Scan: 1
4547 22:53:02.182263
4548 22:53:02.182314 RX Vref 0 -> 0, step: 1
4549 22:53:02.182366
4550 22:53:02.182432 RX Delay -195 -> 252, step: 8
4551 22:53:02.182514
4552 22:53:02.182595 Set Vref, RX VrefLevel [Byte0]: 58
4553 22:53:02.182675 [Byte1]: 49
4554 22:53:02.182730
4555 22:53:02.182786 Final RX Vref Byte 0 = 58 to rank0
4556 22:53:02.182840 Final RX Vref Byte 1 = 49 to rank0
4557 22:53:02.182892 Final RX Vref Byte 0 = 58 to rank1
4558 22:53:02.182944 Final RX Vref Byte 1 = 49 to rank1==
4559 22:53:02.182996 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 22:53:02.183048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 22:53:02.183100 ==
4562 22:53:02.183156 DQS Delay:
4563 22:53:02.183209 DQS0 = 0, DQS1 = 0
4564 22:53:02.183262 DQM Delay:
4565 22:53:02.183313 DQM0 = 39, DQM1 = 28
4566 22:53:02.183366 DQ Delay:
4567 22:53:02.183418 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4568 22:53:02.183471 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4569 22:53:02.183526 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4570 22:53:02.183579 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4571 22:53:02.183632
4572 22:53:02.183683
4573 22:53:02.183735 [DQSOSCAuto] RK0, (LSB)MR18= 0x202e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4574 22:53:02.183788 CH1 RK0: MR19=808, MR18=202E
4575 22:53:02.183840 CH1_RK0: MR19=0x808, MR18=0x202E, DQSOSC=401, MR23=63, INC=163, DEC=108
4576 22:53:02.183902
4577 22:53:02.183987 ----->DramcWriteLeveling(PI) begin...
4578 22:53:02.184069 ==
4579 22:53:02.184151 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 22:53:02.184232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 22:53:02.184316 ==
4582 22:53:02.184397 Write leveling (Byte 0): 30 => 30
4583 22:53:02.184478 Write leveling (Byte 1): 30 => 30
4584 22:53:02.184559 DramcWriteLeveling(PI) end<-----
4585 22:53:02.184639
4586 22:53:02.184697 ==
4587 22:53:02.184749 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 22:53:02.184801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 22:53:02.184853 ==
4590 22:53:02.184905 [Gating] SW mode calibration
4591 22:53:02.184958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4592 22:53:02.185010 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4593 22:53:02.185068 0 9 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
4594 22:53:02.185121 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 22:53:02.185173 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4596 22:53:02.185225 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (1 1)
4597 22:53:02.185277 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4598 22:53:02.185328 0 9 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4599 22:53:02.185380 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 22:53:02.185459 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 22:53:02.185574 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 22:53:02.185628 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 22:53:02.185680 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4604 22:53:02.185732 0 10 12 | B1->B0 | 3232 4040 | 0 0 | (0 0) (0 0)
4605 22:53:02.185789 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 22:53:02.185842 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 22:53:02.185903 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 22:53:02.185993 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 22:53:02.186049 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 22:53:02.186103 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 22:53:02.186159 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 22:53:02.186213 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4613 22:53:02.186265 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 22:53:02.186317 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 22:53:02.186368 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 22:53:02.186420 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 22:53:02.186472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 22:53:02.186527 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 22:53:02.186581 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 22:53:02.186632 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 22:53:02.186684 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 22:53:02.186736 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 22:53:02.186982 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 22:53:02.187045 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 22:53:02.187099 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 22:53:02.187151 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 22:53:02.187202 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4628 22:53:02.187254 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4629 22:53:02.187333 Total UI for P1: 0, mck2ui 16
4630 22:53:02.187415 best dqsien dly found for B0: ( 0, 13, 10)
4631 22:53:02.187498 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 22:53:02.187579 Total UI for P1: 0, mck2ui 16
4633 22:53:02.187663 best dqsien dly found for B1: ( 0, 13, 10)
4634 22:53:02.187745 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4635 22:53:02.187826 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4636 22:53:02.187906
4637 22:53:02.187988 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4638 22:53:02.188073 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4639 22:53:02.188155 [Gating] SW calibration Done
4640 22:53:02.188236 ==
4641 22:53:02.188317 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 22:53:02.188400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 22:53:02.188482 ==
4644 22:53:02.188563 RX Vref Scan: 0
4645 22:53:02.188644
4646 22:53:02.188724 RX Vref 0 -> 0, step: 1
4647 22:53:02.188800
4648 22:53:02.188854 RX Delay -230 -> 252, step: 16
4649 22:53:02.188906 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4650 22:53:02.188959 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4651 22:53:02.189011 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4652 22:53:02.189062 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4653 22:53:02.189114 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4654 22:53:02.189175 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4655 22:53:02.189257 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4656 22:53:02.189338 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4657 22:53:02.189419 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4658 22:53:02.189500 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4659 22:53:02.189599 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4660 22:53:02.189652 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4661 22:53:02.189704 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4662 22:53:02.189756 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4663 22:53:02.189807 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4664 22:53:02.189858 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4665 22:53:02.189914 ==
4666 22:53:02.189967 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 22:53:02.190019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 22:53:02.190071 ==
4669 22:53:02.190123 DQS Delay:
4670 22:53:02.190174 DQS0 = 0, DQS1 = 0
4671 22:53:02.190226 DQM Delay:
4672 22:53:02.190281 DQM0 = 38, DQM1 = 29
4673 22:53:02.190334 DQ Delay:
4674 22:53:02.190385 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4675 22:53:02.190437 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4676 22:53:02.190489 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4677 22:53:02.190541 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4678 22:53:02.190593
4679 22:53:02.190646
4680 22:53:02.190700 ==
4681 22:53:02.190752 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 22:53:02.190804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 22:53:02.190855 ==
4684 22:53:02.190907
4685 22:53:02.190958
4686 22:53:02.191009 TX Vref Scan disable
4687 22:53:02.191066 == TX Byte 0 ==
4688 22:53:02.191119 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4689 22:53:02.191171 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4690 22:53:02.191223 == TX Byte 1 ==
4691 22:53:02.191275 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4692 22:53:02.191327 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4693 22:53:02.191378 ==
4694 22:53:02.191436 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 22:53:02.191489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 22:53:02.191541 ==
4697 22:53:02.191593
4698 22:53:02.191644
4699 22:53:02.191695 TX Vref Scan disable
4700 22:53:02.191747 == TX Byte 0 ==
4701 22:53:02.191818 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4702 22:53:02.191900 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4703 22:53:02.191981 == TX Byte 1 ==
4704 22:53:02.192062 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4705 22:53:02.192144 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4706 22:53:02.192227
4707 22:53:02.192307 [DATLAT]
4708 22:53:02.192388 Freq=600, CH1 RK1
4709 22:53:02.192469
4710 22:53:02.192547 DATLAT Default: 0x9
4711 22:53:02.192601 0, 0xFFFF, sum = 0
4712 22:53:02.192654 1, 0xFFFF, sum = 0
4713 22:53:02.192707 2, 0xFFFF, sum = 0
4714 22:53:02.192759 3, 0xFFFF, sum = 0
4715 22:53:02.192812 4, 0xFFFF, sum = 0
4716 22:53:02.192864 5, 0xFFFF, sum = 0
4717 22:53:02.192920 6, 0xFFFF, sum = 0
4718 22:53:02.192973 7, 0xFFFF, sum = 0
4719 22:53:02.193026 8, 0x0, sum = 1
4720 22:53:02.193079 9, 0x0, sum = 2
4721 22:53:02.193132 10, 0x0, sum = 3
4722 22:53:02.193184 11, 0x0, sum = 4
4723 22:53:02.193237 best_step = 9
4724 22:53:02.193296
4725 22:53:02.193377 ==
4726 22:53:02.193458 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 22:53:02.193575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 22:53:02.193629 ==
4729 22:53:02.193689 RX Vref Scan: 0
4730 22:53:02.193742
4731 22:53:02.193794 RX Vref 0 -> 0, step: 1
4732 22:53:02.193846
4733 22:53:02.193898 RX Delay -195 -> 252, step: 8
4734 22:53:02.193950 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4735 22:53:02.194002 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4736 22:53:02.194060 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4737 22:53:02.194112 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4738 22:53:02.194164 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4739 22:53:02.194216 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4740 22:53:02.194268 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4741 22:53:02.194319 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4742 22:53:02.194371 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4743 22:53:02.194428 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4744 22:53:02.194481 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4745 22:53:02.194533 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4746 22:53:02.194585 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4747 22:53:02.194636 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4748 22:53:02.194688 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4749 22:53:02.194739 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4750 22:53:02.194798 ==
4751 22:53:02.194851 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 22:53:02.194903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 22:53:02.194955 ==
4754 22:53:02.195007 DQS Delay:
4755 22:53:02.195059 DQS0 = 0, DQS1 = 0
4756 22:53:02.195111 DQM Delay:
4757 22:53:02.195166 DQM0 = 37, DQM1 = 29
4758 22:53:02.195219 DQ Delay:
4759 22:53:02.195270 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4760 22:53:02.195513 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4761 22:53:02.195577 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4762 22:53:02.195630 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4763 22:53:02.195682
4764 22:53:02.195734
4765 22:53:02.195785 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4766 22:53:02.195838 CH1 RK1: MR19=808, MR18=3C5C
4767 22:53:02.195891 CH1_RK1: MR19=0x808, MR18=0x3C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4768 22:53:02.195948 [RxdqsGatingPostProcess] freq 600
4769 22:53:02.196000 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4770 22:53:02.196053 Pre-setting of DQS Precalculation
4771 22:53:02.196105 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4772 22:53:02.196157 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4773 22:53:02.196209 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4774 22:53:02.196261
4775 22:53:02.196317
4776 22:53:02.196369 [Calibration Summary] 1200 Mbps
4777 22:53:02.196420 CH 0, Rank 0
4778 22:53:02.196472 SW Impedance : PASS
4779 22:53:02.196524 DUTY Scan : NO K
4780 22:53:02.196575 ZQ Calibration : PASS
4781 22:53:02.196627 Jitter Meter : NO K
4782 22:53:02.196700 CBT Training : PASS
4783 22:53:02.196781 Write leveling : PASS
4784 22:53:02.196862 RX DQS gating : PASS
4785 22:53:02.196943 RX DQ/DQS(RDDQC) : PASS
4786 22:53:02.197025 TX DQ/DQS : PASS
4787 22:53:02.197108 RX DATLAT : PASS
4788 22:53:02.197188 RX DQ/DQS(Engine): PASS
4789 22:53:02.197269 TX OE : NO K
4790 22:53:02.197350 All Pass.
4791 22:53:02.197433
4792 22:53:02.197543 CH 0, Rank 1
4793 22:53:02.197612 SW Impedance : PASS
4794 22:53:02.197664 DUTY Scan : NO K
4795 22:53:02.197716 ZQ Calibration : PASS
4796 22:53:02.197769 Jitter Meter : NO K
4797 22:53:02.197824 CBT Training : PASS
4798 22:53:02.197876 Write leveling : PASS
4799 22:53:02.197928 RX DQS gating : PASS
4800 22:53:02.197979 RX DQ/DQS(RDDQC) : PASS
4801 22:53:02.198031 TX DQ/DQS : PASS
4802 22:53:02.198084 RX DATLAT : PASS
4803 22:53:02.198135 RX DQ/DQS(Engine): PASS
4804 22:53:02.198192 TX OE : NO K
4805 22:53:02.198244 All Pass.
4806 22:53:02.198295
4807 22:53:02.198347 CH 1, Rank 0
4808 22:53:02.198399 SW Impedance : PASS
4809 22:53:02.198450 DUTY Scan : NO K
4810 22:53:02.198501 ZQ Calibration : PASS
4811 22:53:02.198559 Jitter Meter : NO K
4812 22:53:02.198611 CBT Training : PASS
4813 22:53:02.198663 Write leveling : PASS
4814 22:53:02.198714 RX DQS gating : PASS
4815 22:53:02.198766 RX DQ/DQS(RDDQC) : PASS
4816 22:53:02.198818 TX DQ/DQS : PASS
4817 22:53:02.198870 RX DATLAT : PASS
4818 22:53:02.198927 RX DQ/DQS(Engine): PASS
4819 22:53:02.198980 TX OE : NO K
4820 22:53:02.199031 All Pass.
4821 22:53:02.199083
4822 22:53:02.199134 CH 1, Rank 1
4823 22:53:02.199186 SW Impedance : PASS
4824 22:53:02.199238 DUTY Scan : NO K
4825 22:53:02.199294 ZQ Calibration : PASS
4826 22:53:02.199347 Jitter Meter : NO K
4827 22:53:02.199399 CBT Training : PASS
4828 22:53:02.199451 Write leveling : PASS
4829 22:53:02.199502 RX DQS gating : PASS
4830 22:53:02.199559 RX DQ/DQS(RDDQC) : PASS
4831 22:53:02.199611 TX DQ/DQS : PASS
4832 22:53:02.199663 RX DATLAT : PASS
4833 22:53:02.199715 RX DQ/DQS(Engine): PASS
4834 22:53:02.199766 TX OE : NO K
4835 22:53:02.199817 All Pass.
4836 22:53:02.199869
4837 22:53:02.199926 DramC Write-DBI off
4838 22:53:02.199979 PER_BANK_REFRESH: Hybrid Mode
4839 22:53:02.200031 TX_TRACKING: ON
4840 22:53:02.200083 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4841 22:53:02.200137 [FAST_K] Save calibration result to emmc
4842 22:53:02.200189 dramc_set_vcore_voltage set vcore to 662500
4843 22:53:02.200241 Read voltage for 933, 3
4844 22:53:02.200300 Vio18 = 0
4845 22:53:02.200353 Vcore = 662500
4846 22:53:02.200405 Vdram = 0
4847 22:53:02.200456 Vddq = 0
4848 22:53:02.200507 Vmddr = 0
4849 22:53:02.200564 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4850 22:53:02.200616 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4851 22:53:02.200668 MEM_TYPE=3, freq_sel=17
4852 22:53:02.200720 sv_algorithm_assistance_LP4_1600
4853 22:53:02.200771 ============ PULL DRAM RESETB DOWN ============
4854 22:53:02.200824 ========== PULL DRAM RESETB DOWN end =========
4855 22:53:02.200876 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4856 22:53:02.200932 ===================================
4857 22:53:02.200985 LPDDR4 DRAM CONFIGURATION
4858 22:53:02.201036 ===================================
4859 22:53:02.201088 EX_ROW_EN[0] = 0x0
4860 22:53:02.201140 EX_ROW_EN[1] = 0x0
4861 22:53:02.201191 LP4Y_EN = 0x0
4862 22:53:02.201243 WORK_FSP = 0x0
4863 22:53:02.201301 WL = 0x3
4864 22:53:02.201353 RL = 0x3
4865 22:53:02.201404 BL = 0x2
4866 22:53:02.201458 RPST = 0x0
4867 22:53:02.201513 RD_PRE = 0x0
4868 22:53:02.201597 WR_PRE = 0x1
4869 22:53:02.201652 WR_PST = 0x0
4870 22:53:02.201704 DBI_WR = 0x0
4871 22:53:02.201756 DBI_RD = 0x0
4872 22:53:02.201807 OTF = 0x1
4873 22:53:02.201859 ===================================
4874 22:53:02.201911 ===================================
4875 22:53:02.201963 ANA top config
4876 22:53:02.202017 ===================================
4877 22:53:02.202070 DLL_ASYNC_EN = 0
4878 22:53:02.202121 ALL_SLAVE_EN = 1
4879 22:53:02.202173 NEW_RANK_MODE = 1
4880 22:53:02.202225 DLL_IDLE_MODE = 1
4881 22:53:02.202278 LP45_APHY_COMB_EN = 1
4882 22:53:02.202333 TX_ODT_DIS = 1
4883 22:53:02.202384 NEW_8X_MODE = 1
4884 22:53:02.202436 ===================================
4885 22:53:02.202489 ===================================
4886 22:53:02.202541 data_rate = 1866
4887 22:53:02.202592 CKR = 1
4888 22:53:02.202645 DQ_P2S_RATIO = 8
4889 22:53:02.202701 ===================================
4890 22:53:02.202752 CA_P2S_RATIO = 8
4891 22:53:02.202803 DQ_CA_OPEN = 0
4892 22:53:02.202855 DQ_SEMI_OPEN = 0
4893 22:53:02.202907 CA_SEMI_OPEN = 0
4894 22:53:02.202958 CA_FULL_RATE = 0
4895 22:53:02.203010 DQ_CKDIV4_EN = 1
4896 22:53:02.203066 CA_CKDIV4_EN = 1
4897 22:53:02.203117 CA_PREDIV_EN = 0
4898 22:53:02.203169 PH8_DLY = 0
4899 22:53:02.203220 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4900 22:53:02.203272 DQ_AAMCK_DIV = 4
4901 22:53:02.203323 CA_AAMCK_DIV = 4
4902 22:53:02.203374 CA_ADMCK_DIV = 4
4903 22:53:02.203431 DQ_TRACK_CA_EN = 0
4904 22:53:02.203675 CA_PICK = 933
4905 22:53:02.203733 CA_MCKIO = 933
4906 22:53:02.203790 MCKIO_SEMI = 0
4907 22:53:02.203844 PLL_FREQ = 3732
4908 22:53:02.203896 DQ_UI_PI_RATIO = 32
4909 22:53:02.203948 CA_UI_PI_RATIO = 0
4910 22:53:02.204000 ===================================
4911 22:53:02.204052 ===================================
4912 22:53:02.204104 memory_type:LPDDR4
4913 22:53:02.204159 GP_NUM : 10
4914 22:53:02.204212 SRAM_EN : 1
4915 22:53:02.204263 MD32_EN : 0
4916 22:53:02.204315 ===================================
4917 22:53:02.204367 [ANA_INIT] >>>>>>>>>>>>>>
4918 22:53:02.204418 <<<<<< [CONFIGURE PHASE]: ANA_TX
4919 22:53:02.204471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4920 22:53:02.204525 ===================================
4921 22:53:02.204579 data_rate = 1866,PCW = 0X8f00
4922 22:53:02.204631 ===================================
4923 22:53:02.204682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4924 22:53:02.351325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 22:53:02.351947 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 22:53:02.352472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4927 22:53:02.352952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4928 22:53:02.353307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4929 22:53:02.353653 [ANA_INIT] flow start
4930 22:53:02.353979 [ANA_INIT] PLL >>>>>>>>
4931 22:53:02.354294 [ANA_INIT] PLL <<<<<<<<
4932 22:53:02.354601 [ANA_INIT] MIDPI >>>>>>>>
4933 22:53:02.354903 [ANA_INIT] MIDPI <<<<<<<<
4934 22:53:02.355181 [ANA_INIT] DLL >>>>>>>>
4935 22:53:02.355480 [ANA_INIT] flow end
4936 22:53:02.355774 ============ LP4 DIFF to SE enter ============
4937 22:53:02.356075 ============ LP4 DIFF to SE exit ============
4938 22:53:02.356520 [ANA_INIT] <<<<<<<<<<<<<
4939 22:53:02.356832 [Flow] Enable top DCM control >>>>>
4940 22:53:02.357339 [Flow] Enable top DCM control <<<<<
4941 22:53:02.357820 Enable DLL master slave shuffle
4942 22:53:02.358261 ==============================================================
4943 22:53:02.358730 Gating Mode config
4944 22:53:02.359100 ==============================================================
4945 22:53:02.359392 Config description:
4946 22:53:02.359699 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4947 22:53:02.360131 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4948 22:53:02.360454 SELPH_MODE 0: By rank 1: By Phase
4949 22:53:02.360763 ==============================================================
4950 22:53:02.361070 GAT_TRACK_EN = 1
4951 22:53:02.361348 RX_GATING_MODE = 2
4952 22:53:02.361691 RX_GATING_TRACK_MODE = 2
4953 22:53:02.362000 SELPH_MODE = 1
4954 22:53:02.362299 PICG_EARLY_EN = 1
4955 22:53:02.362578 VALID_LAT_VALUE = 1
4956 22:53:02.362879 ==============================================================
4957 22:53:02.363291 Enter into Gating configuration >>>>
4958 22:53:02.363616 Exit from Gating configuration <<<<
4959 22:53:02.363928 Enter into DVFS_PRE_config >>>>>
4960 22:53:02.364230 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4961 22:53:02.364512 Exit from DVFS_PRE_config <<<<<
4962 22:53:02.364810 Enter into PICG configuration >>>>
4963 22:53:02.365110 Exit from PICG configuration <<<<
4964 22:53:02.365405 [RX_INPUT] configuration >>>>>
4965 22:53:02.365746 [RX_INPUT] configuration <<<<<
4966 22:53:02.366046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4967 22:53:02.366481 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4968 22:53:02.366769 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 22:53:02.367074 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 22:53:02.367377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 22:53:02.367675 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 22:53:02.367968 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4973 22:53:02.368240 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4974 22:53:02.368538 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4975 22:53:02.368835 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4976 22:53:02.369131 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4977 22:53:02.369426 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4978 22:53:02.369884 ===================================
4979 22:53:02.370089 LPDDR4 DRAM CONFIGURATION
4980 22:53:02.370304 ===================================
4981 22:53:02.370499 EX_ROW_EN[0] = 0x0
4982 22:53:02.370709 EX_ROW_EN[1] = 0x0
4983 22:53:02.370900 LP4Y_EN = 0x0
4984 22:53:02.371111 WORK_FSP = 0x0
4985 22:53:02.371320 WL = 0x3
4986 22:53:02.371514 RL = 0x3
4987 22:53:02.371721 BL = 0x2
4988 22:53:02.371913 RPST = 0x0
4989 22:53:02.372123 RD_PRE = 0x0
4990 22:53:02.372317 WR_PRE = 0x1
4991 22:53:02.372526 WR_PST = 0x0
4992 22:53:02.372717 DBI_WR = 0x0
4993 22:53:02.372925 DBI_RD = 0x0
4994 22:53:02.373126 OTF = 0x1
4995 22:53:02.373485 ===================================
4996 22:53:02.373743 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4997 22:53:02.373958 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4998 22:53:02.374156 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 22:53:02.374367 ===================================
5000 22:53:02.374564 LPDDR4 DRAM CONFIGURATION
5001 22:53:02.374776 ===================================
5002 22:53:02.374951 EX_ROW_EN[0] = 0x10
5003 22:53:02.375112 EX_ROW_EN[1] = 0x0
5004 22:53:02.375265 LP4Y_EN = 0x0
5005 22:53:02.375421 WORK_FSP = 0x0
5006 22:53:02.375569 WL = 0x3
5007 22:53:02.375712 RL = 0x3
5008 22:53:02.375873 BL = 0x2
5009 22:53:02.376017 RPST = 0x0
5010 22:53:02.376239 RD_PRE = 0x0
5011 22:53:02.376409 WR_PRE = 0x1
5012 22:53:02.376560 WR_PST = 0x0
5013 22:53:02.376985 DBI_WR = 0x0
5014 22:53:02.377171 DBI_RD = 0x0
5015 22:53:02.377326 OTF = 0x1
5016 22:53:02.377473 ===================================
5017 22:53:02.377667 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5018 22:53:02.377817 nWR fixed to 30
5019 22:53:02.377979 [ModeRegInit_LP4] CH0 RK0
5020 22:53:02.378125 [ModeRegInit_LP4] CH0 RK1
5021 22:53:02.378283 [ModeRegInit_LP4] CH1 RK0
5022 22:53:02.378428 [ModeRegInit_LP4] CH1 RK1
5023 22:53:02.378571 match AC timing 9
5024 22:53:02.378729 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5025 22:53:02.378875 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5026 22:53:02.379030 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5027 22:53:02.379178 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5028 22:53:02.379322 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5029 22:53:02.379482 ==
5030 22:53:02.379703 Dram Type= 6, Freq= 0, CH_0, rank 0
5031 22:53:02.379879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5032 22:53:02.379998 ==
5033 22:53:02.380115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5034 22:53:02.380245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5035 22:53:02.380363 [CA 0] Center 38 (8~69) winsize 62
5036 22:53:02.380479 [CA 1] Center 38 (8~68) winsize 61
5037 22:53:02.380609 [CA 2] Center 35 (5~65) winsize 61
5038 22:53:02.380726 [CA 3] Center 35 (5~65) winsize 61
5039 22:53:02.380856 [CA 4] Center 34 (4~65) winsize 62
5040 22:53:02.381039 [CA 5] Center 34 (3~65) winsize 63
5041 22:53:02.381226
5042 22:53:02.381398 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5043 22:53:02.381604
5044 22:53:02.381746 [CATrainingPosCal] consider 1 rank data
5045 22:53:02.381897 u2DelayCellTimex100 = 270/100 ps
5046 22:53:02.382021 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5047 22:53:02.382139 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5048 22:53:02.382270 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5049 22:53:02.382386 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5050 22:53:02.382528 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5051 22:53:02.382657 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
5052 22:53:02.382799
5053 22:53:02.382999 CA PerBit enable=1, Macro0, CA PI delay=34
5054 22:53:02.383204
5055 22:53:02.383387 [CBTSetCACLKResult] CA Dly = 34
5056 22:53:02.383578 CS Dly: 7 (0~38)
5057 22:53:02.383768 ==
5058 22:53:02.383964 Dram Type= 6, Freq= 0, CH_0, rank 1
5059 22:53:02.384147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 22:53:02.384286 ==
5061 22:53:02.384409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 22:53:02.384528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5063 22:53:02.384661 [CA 0] Center 38 (8~69) winsize 62
5064 22:53:02.384791 [CA 1] Center 38 (8~69) winsize 62
5065 22:53:02.384917 [CA 2] Center 35 (5~66) winsize 62
5066 22:53:02.385016 [CA 3] Center 35 (5~66) winsize 62
5067 22:53:02.385113 [CA 4] Center 34 (4~65) winsize 62
5068 22:53:02.385220 [CA 5] Center 33 (3~64) winsize 62
5069 22:53:02.385339
5070 22:53:02.385440 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5071 22:53:02.385552
5072 22:53:02.385667 [CATrainingPosCal] consider 2 rank data
5073 22:53:02.385774 u2DelayCellTimex100 = 270/100 ps
5074 22:53:02.385874 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5075 22:53:02.385933 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5076 22:53:02.385992 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5077 22:53:02.386053 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5078 22:53:02.386113 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5079 22:53:02.386202 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5080 22:53:02.386283
5081 22:53:02.386365 CA PerBit enable=1, Macro0, CA PI delay=33
5082 22:53:02.386444
5083 22:53:02.386506 [CBTSetCACLKResult] CA Dly = 33
5084 22:53:02.386592 CS Dly: 7 (0~38)
5085 22:53:02.386679
5086 22:53:02.386761 ----->DramcWriteLeveling(PI) begin...
5087 22:53:02.386847 ==
5088 22:53:02.386937 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 22:53:02.387020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 22:53:02.387075 ==
5091 22:53:02.387128 Write leveling (Byte 0): 28 => 28
5092 22:53:02.387187 Write leveling (Byte 1): 28 => 28
5093 22:53:02.387243 DramcWriteLeveling(PI) end<-----
5094 22:53:02.387303
5095 22:53:02.387388 ==
5096 22:53:02.387476 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 22:53:02.387557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 22:53:02.387638 ==
5099 22:53:02.387726 [Gating] SW mode calibration
5100 22:53:02.387809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5101 22:53:02.387893 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5102 22:53:02.387980 0 14 0 | B1->B0 | 2323 2f2f | 1 0 | (1 1) (0 0)
5103 22:53:02.388067 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5104 22:53:02.388150 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 22:53:02.388237 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 22:53:02.388319 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 22:53:02.388401 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 22:53:02.388488 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 22:53:02.388567 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5110 22:53:02.388628 0 15 0 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
5111 22:53:02.388687 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
5112 22:53:02.388741 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 22:53:02.388793 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 22:53:02.388845 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 22:53:02.388898 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 22:53:02.388956 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 22:53:02.389009 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5118 22:53:02.389061 1 0 0 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
5119 22:53:02.389119 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5120 22:53:02.389186 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 22:53:02.389243 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 22:53:02.389295 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 22:53:02.389347 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 22:53:02.389399 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 22:53:02.389651 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 22:53:02.389712 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5127 22:53:02.389767 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5128 22:53:02.389820 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 22:53:02.389873 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 22:53:02.389932 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 22:53:02.389984 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 22:53:02.390036 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 22:53:02.390088 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 22:53:02.390151 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 22:53:02.390226 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 22:53:02.390280 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 22:53:02.390332 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 22:53:02.390384 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 22:53:02.390443 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 22:53:02.390495 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 22:53:02.390547 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5142 22:53:02.390599 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5143 22:53:02.390651 Total UI for P1: 0, mck2ui 16
5144 22:53:02.390709 best dqsien dly found for B0: ( 1, 2, 28)
5145 22:53:02.390762 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5146 22:53:02.390814 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 22:53:02.390867 Total UI for P1: 0, mck2ui 16
5148 22:53:02.390924 best dqsien dly found for B1: ( 1, 3, 4)
5149 22:53:02.390977 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5150 22:53:02.391030 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5151 22:53:02.391082
5152 22:53:02.391134 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5153 22:53:02.391192 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5154 22:53:02.391245 [Gating] SW calibration Done
5155 22:53:02.391297 ==
5156 22:53:02.391350 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 22:53:02.391402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 22:53:02.391459 ==
5159 22:53:02.391511 RX Vref Scan: 0
5160 22:53:02.391563
5161 22:53:02.391615 RX Vref 0 -> 0, step: 1
5162 22:53:02.391672
5163 22:53:02.391725 RX Delay -80 -> 252, step: 8
5164 22:53:02.391777 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5165 22:53:02.391830 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5166 22:53:02.391881 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5167 22:53:02.391939 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5168 22:53:02.391991 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5169 22:53:02.392042 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5170 22:53:02.392094 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5171 22:53:02.392146 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5172 22:53:02.392204 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5173 22:53:02.392256 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5174 22:53:02.392308 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5175 22:53:02.392360 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5176 22:53:02.392412 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5177 22:53:02.392464 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5178 22:53:02.392521 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5179 22:53:02.392575 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5180 22:53:02.392627 ==
5181 22:53:02.392680 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 22:53:02.392731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 22:53:02.392788 ==
5184 22:53:02.392842 DQS Delay:
5185 22:53:02.392894 DQS0 = 0, DQS1 = 0
5186 22:53:02.392946 DQM Delay:
5187 22:53:02.392998 DQM0 = 94, DQM1 = 83
5188 22:53:02.393055 DQ Delay:
5189 22:53:02.393108 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5190 22:53:02.393160 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5191 22:53:02.393212 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5192 22:53:02.393264 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5193 22:53:02.393321
5194 22:53:02.393373
5195 22:53:02.393424 ==
5196 22:53:02.393476 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 22:53:02.393575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 22:53:02.393630 ==
5199 22:53:02.393682
5200 22:53:02.393734
5201 22:53:02.393785 TX Vref Scan disable
5202 22:53:02.393838 == TX Byte 0 ==
5203 22:53:02.393894 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5204 22:53:02.393947 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5205 22:53:02.393999 == TX Byte 1 ==
5206 22:53:02.394051 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5207 22:53:02.394103 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5208 22:53:02.394160 ==
5209 22:53:02.394213 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 22:53:02.394266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 22:53:02.394318 ==
5212 22:53:02.394369
5213 22:53:02.394426
5214 22:53:02.394478 TX Vref Scan disable
5215 22:53:02.394531 == TX Byte 0 ==
5216 22:53:02.394583 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5217 22:53:02.394635 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5218 22:53:02.394697 == TX Byte 1 ==
5219 22:53:02.394775 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5220 22:53:02.394860 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5221 22:53:02.394953
5222 22:53:02.395034 [DATLAT]
5223 22:53:02.395112 Freq=933, CH0 RK0
5224 22:53:02.395197
5225 22:53:02.395270 DATLAT Default: 0xd
5226 22:53:02.395325 0, 0xFFFF, sum = 0
5227 22:53:02.395380 1, 0xFFFF, sum = 0
5228 22:53:02.395434 2, 0xFFFF, sum = 0
5229 22:53:02.395487 3, 0xFFFF, sum = 0
5230 22:53:02.395547 4, 0xFFFF, sum = 0
5231 22:53:02.395601 5, 0xFFFF, sum = 0
5232 22:53:02.395654 6, 0xFFFF, sum = 0
5233 22:53:02.395707 7, 0xFFFF, sum = 0
5234 22:53:02.395759 8, 0xFFFF, sum = 0
5235 22:53:02.395818 9, 0xFFFF, sum = 0
5236 22:53:02.395871 10, 0x0, sum = 1
5237 22:53:02.395924 11, 0x0, sum = 2
5238 22:53:02.395977 12, 0x0, sum = 3
5239 22:53:02.396034 13, 0x0, sum = 4
5240 22:53:02.396088 best_step = 11
5241 22:53:02.396140
5242 22:53:02.396193 ==
5243 22:53:02.396245 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 22:53:02.396303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 22:53:02.396356 ==
5246 22:53:02.396408 RX Vref Scan: 1
5247 22:53:02.396460
5248 22:53:02.396511 RX Vref 0 -> 0, step: 1
5249 22:53:02.396564
5250 22:53:02.396616 RX Delay -69 -> 252, step: 4
5251 22:53:02.396673
5252 22:53:02.396725 Set Vref, RX VrefLevel [Byte0]: 63
5253 22:53:02.396778 [Byte1]: 58
5254 22:53:02.396830
5255 22:53:02.396882 Final RX Vref Byte 0 = 63 to rank0
5256 22:53:02.396934 Final RX Vref Byte 1 = 58 to rank0
5257 22:53:02.396986 Final RX Vref Byte 0 = 63 to rank1
5258 22:53:02.397043 Final RX Vref Byte 1 = 58 to rank1==
5259 22:53:02.397096 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 22:53:02.397339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 22:53:02.397403 ==
5262 22:53:02.397458 DQS Delay:
5263 22:53:02.397518 DQS0 = 0, DQS1 = 0
5264 22:53:02.397612 DQM Delay:
5265 22:53:02.397671 DQM0 = 95, DQM1 = 84
5266 22:53:02.397724 DQ Delay:
5267 22:53:02.397777 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5268 22:53:02.397829 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5269 22:53:02.397881 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =80
5270 22:53:02.397934 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =90
5271 22:53:02.397985
5272 22:53:02.398043
5273 22:53:02.398094 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5274 22:53:02.398148 CH0 RK0: MR19=505, MR18=1313
5275 22:53:02.398200 CH0_RK0: MR19=0x505, MR18=0x1313, DQSOSC=415, MR23=63, INC=62, DEC=41
5276 22:53:02.398252
5277 22:53:02.398304 ----->DramcWriteLeveling(PI) begin...
5278 22:53:02.398357 ==
5279 22:53:02.398414 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 22:53:02.398468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 22:53:02.398521 ==
5282 22:53:02.398573 Write leveling (Byte 0): 30 => 30
5283 22:53:02.398625 Write leveling (Byte 1): 29 => 29
5284 22:53:02.398677 DramcWriteLeveling(PI) end<-----
5285 22:53:02.398728
5286 22:53:02.398786 ==
5287 22:53:02.398838 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 22:53:02.398890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 22:53:02.398943 ==
5290 22:53:02.398995 [Gating] SW mode calibration
5291 22:53:02.399047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5292 22:53:02.399100 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5293 22:53:02.399157 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
5294 22:53:02.399209 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 22:53:02.399261 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 22:53:02.399312 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 22:53:02.399364 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 22:53:02.399415 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 22:53:02.399467 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5300 22:53:02.399522 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
5301 22:53:02.399575 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5302 22:53:02.399626 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 22:53:02.399703 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 22:53:02.399790 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 22:53:02.399874 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 22:53:02.399963 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 22:53:02.400042 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 22:53:02.400119 0 15 28 | B1->B0 | 2424 3838 | 0 1 | (0 0) (0 0)
5309 22:53:02.400196 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5310 22:53:02.400253 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 22:53:02.400313 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 22:53:02.400367 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 22:53:02.400419 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 22:53:02.400472 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 22:53:02.400525 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 22:53:02.400594 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5317 22:53:02.400653 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5318 22:53:02.400706 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 22:53:02.400758 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 22:53:02.400810 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 22:53:02.400862 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 22:53:02.400913 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 22:53:02.400964 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 22:53:02.401020 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 22:53:02.401073 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 22:53:02.401126 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 22:53:02.401200 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 22:53:02.401265 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 22:53:02.401317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 22:53:02.401369 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 22:53:02.401426 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5332 22:53:02.401477 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5333 22:53:02.401536 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 22:53:02.401589 Total UI for P1: 0, mck2ui 16
5335 22:53:02.401642 best dqsien dly found for B0: ( 1, 2, 26)
5336 22:53:02.401694 Total UI for P1: 0, mck2ui 16
5337 22:53:02.401746 best dqsien dly found for B1: ( 1, 2, 30)
5338 22:53:02.401804 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5339 22:53:02.401856 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5340 22:53:02.401907
5341 22:53:02.401959 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5342 22:53:02.402011 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5343 22:53:02.402063 [Gating] SW calibration Done
5344 22:53:02.402114 ==
5345 22:53:02.402172 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 22:53:02.402224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 22:53:02.402276 ==
5348 22:53:02.402327 RX Vref Scan: 0
5349 22:53:02.402379
5350 22:53:02.402430 RX Vref 0 -> 0, step: 1
5351 22:53:02.402482
5352 22:53:02.402539 RX Delay -80 -> 252, step: 8
5353 22:53:02.402591 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5354 22:53:02.402643 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5355 22:53:02.402695 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5356 22:53:02.402747 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5357 22:53:02.402798 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5358 22:53:02.402849 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5359 22:53:02.402905 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5360 22:53:02.402958 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5361 22:53:02.403009 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5362 22:53:02.403060 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5363 22:53:02.403111 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5364 22:53:02.403356 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5365 22:53:02.403416 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5366 22:53:02.403469 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5367 22:53:02.403521 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5368 22:53:02.403572 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5369 22:53:02.403624 ==
5370 22:53:02.403682 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 22:53:02.403734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 22:53:02.403786 ==
5373 22:53:02.403838 DQS Delay:
5374 22:53:02.403889 DQS0 = 0, DQS1 = 0
5375 22:53:02.403942 DQM Delay:
5376 22:53:02.403993 DQM0 = 91, DQM1 = 83
5377 22:53:02.404051 DQ Delay:
5378 22:53:02.404103 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5379 22:53:02.404155 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =107
5380 22:53:02.404207 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5381 22:53:02.404258 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5382 22:53:02.404316
5383 22:53:02.404368
5384 22:53:02.404418 ==
5385 22:53:02.404470 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 22:53:02.404522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 22:53:02.404574 ==
5388 22:53:02.404627
5389 22:53:02.404684
5390 22:53:02.404735 TX Vref Scan disable
5391 22:53:02.404787 == TX Byte 0 ==
5392 22:53:02.404839 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5393 22:53:02.404891 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5394 22:53:02.404942 == TX Byte 1 ==
5395 22:53:02.404994 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5396 22:53:02.405050 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5397 22:53:02.405103 ==
5398 22:53:02.405155 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 22:53:02.405207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 22:53:02.405258 ==
5401 22:53:02.405309
5402 22:53:02.405360
5403 22:53:02.405417 TX Vref Scan disable
5404 22:53:02.405469 == TX Byte 0 ==
5405 22:53:02.405546 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5406 22:53:02.405614 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5407 22:53:02.405666 == TX Byte 1 ==
5408 22:53:02.405740 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5409 22:53:02.405836 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5410 22:53:02.405921
5411 22:53:02.406003 [DATLAT]
5412 22:53:02.406081 Freq=933, CH0 RK1
5413 22:53:02.406164
5414 22:53:02.406245 DATLAT Default: 0xb
5415 22:53:02.406303 0, 0xFFFF, sum = 0
5416 22:53:02.406357 1, 0xFFFF, sum = 0
5417 22:53:02.406411 2, 0xFFFF, sum = 0
5418 22:53:02.406463 3, 0xFFFF, sum = 0
5419 22:53:02.406522 4, 0xFFFF, sum = 0
5420 22:53:02.406575 5, 0xFFFF, sum = 0
5421 22:53:02.406628 6, 0xFFFF, sum = 0
5422 22:53:02.406680 7, 0xFFFF, sum = 0
5423 22:53:02.406732 8, 0xFFFF, sum = 0
5424 22:53:02.406784 9, 0xFFFF, sum = 0
5425 22:53:02.406837 10, 0x0, sum = 1
5426 22:53:02.406893 11, 0x0, sum = 2
5427 22:53:02.406948 12, 0x0, sum = 3
5428 22:53:02.407000 13, 0x0, sum = 4
5429 22:53:02.407052 best_step = 11
5430 22:53:02.407103
5431 22:53:02.407155 ==
5432 22:53:02.407208 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 22:53:02.407259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 22:53:02.407317 ==
5435 22:53:02.407370 RX Vref Scan: 0
5436 22:53:02.407421
5437 22:53:02.407472 RX Vref 0 -> 0, step: 1
5438 22:53:02.407523
5439 22:53:02.407575 RX Delay -77 -> 252, step: 4
5440 22:53:02.407627 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5441 22:53:02.407684 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5442 22:53:02.407736 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5443 22:53:02.407787 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5444 22:53:02.407839 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5445 22:53:02.407890 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5446 22:53:02.407941 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5447 22:53:02.407993 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5448 22:53:02.408052 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5449 22:53:02.408104 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5450 22:53:02.408155 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5451 22:53:02.408207 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5452 22:53:02.408258 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5453 22:53:02.408310 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5454 22:53:02.408361 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5455 22:53:02.408418 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5456 22:53:02.408470 ==
5457 22:53:02.408523 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 22:53:02.408575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 22:53:02.408627 ==
5460 22:53:02.408679 DQS Delay:
5461 22:53:02.408730 DQS0 = 0, DQS1 = 0
5462 22:53:02.408787 DQM Delay:
5463 22:53:02.408839 DQM0 = 92, DQM1 = 85
5464 22:53:02.408891 DQ Delay:
5465 22:53:02.408942 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5466 22:53:02.408994 DQ4 =92, DQ5 =82, DQ6 =106, DQ7 =104
5467 22:53:02.409046 DQ8 =80, DQ9 =72, DQ10 =86, DQ11 =80
5468 22:53:02.409097 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5469 22:53:02.409153
5470 22:53:02.409242
5471 22:53:02.409293 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5472 22:53:02.409346 CH0 RK1: MR19=505, MR18=2D0F
5473 22:53:02.409398 CH0_RK1: MR19=0x505, MR18=0x2D0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5474 22:53:02.409456 [RxdqsGatingPostProcess] freq 933
5475 22:53:02.409516 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5476 22:53:02.409603 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 22:53:02.409655 best DQS1 dly(2T, 0.5T) = (0, 11)
5478 22:53:02.409713 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 22:53:02.409765 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5480 22:53:02.409817 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 22:53:02.409868 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 22:53:02.409924 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 22:53:02.409977 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 22:53:02.410028 Pre-setting of DQS Precalculation
5485 22:53:02.410080 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5486 22:53:02.410132 ==
5487 22:53:02.410191 Dram Type= 6, Freq= 0, CH_1, rank 0
5488 22:53:02.410243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 22:53:02.410295 ==
5490 22:53:02.410347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5491 22:53:02.410400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5492 22:53:02.410458 [CA 0] Center 37 (7~67) winsize 61
5493 22:53:02.410510 [CA 1] Center 37 (7~68) winsize 62
5494 22:53:02.410562 [CA 2] Center 34 (5~64) winsize 60
5495 22:53:02.410613 [CA 3] Center 34 (5~64) winsize 60
5496 22:53:02.410664 [CA 4] Center 34 (5~64) winsize 60
5497 22:53:02.410715 [CA 5] Center 34 (4~64) winsize 61
5498 22:53:02.410771
5499 22:53:02.410841 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5500 22:53:02.410894
5501 22:53:02.410946 [CATrainingPosCal] consider 1 rank data
5502 22:53:02.410999 u2DelayCellTimex100 = 270/100 ps
5503 22:53:02.411057 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5504 22:53:02.411304 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5505 22:53:02.411363 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5506 22:53:02.411417 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5507 22:53:02.411469 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5508 22:53:02.411522 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5509 22:53:02.411574
5510 22:53:02.411625 CA PerBit enable=1, Macro0, CA PI delay=34
5511 22:53:02.411683
5512 22:53:02.411736 [CBTSetCACLKResult] CA Dly = 34
5513 22:53:02.411788 CS Dly: 6 (0~37)
5514 22:53:02.411840 ==
5515 22:53:02.411892 Dram Type= 6, Freq= 0, CH_1, rank 1
5516 22:53:02.411943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 22:53:02.411996 ==
5518 22:53:02.412053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 22:53:02.412105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5520 22:53:02.412157 [CA 0] Center 38 (8~68) winsize 61
5521 22:53:02.412209 [CA 1] Center 38 (7~69) winsize 63
5522 22:53:02.412261 [CA 2] Center 35 (5~65) winsize 61
5523 22:53:02.412312 [CA 3] Center 34 (4~64) winsize 61
5524 22:53:02.412362 [CA 4] Center 35 (5~65) winsize 61
5525 22:53:02.412421 [CA 5] Center 33 (3~64) winsize 62
5526 22:53:02.412473
5527 22:53:02.412524 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5528 22:53:02.412575
5529 22:53:02.412626 [CATrainingPosCal] consider 2 rank data
5530 22:53:02.412677 u2DelayCellTimex100 = 270/100 ps
5531 22:53:02.412728 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5532 22:53:02.412785 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5533 22:53:02.412837 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5534 22:53:02.412888 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5535 22:53:02.412940 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5536 22:53:02.412991 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5537 22:53:02.413042
5538 22:53:02.413093 CA PerBit enable=1, Macro0, CA PI delay=34
5539 22:53:02.413150
5540 22:53:02.413241 [CBTSetCACLKResult] CA Dly = 34
5541 22:53:02.413293 CS Dly: 6 (0~38)
5542 22:53:02.413344
5543 22:53:02.413396 ----->DramcWriteLeveling(PI) begin...
5544 22:53:02.413448 ==
5545 22:53:02.413500 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 22:53:02.413596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 22:53:02.413650 ==
5548 22:53:02.413702 Write leveling (Byte 0): 28 => 28
5549 22:53:02.413754 Write leveling (Byte 1): 28 => 28
5550 22:53:02.413805 DramcWriteLeveling(PI) end<-----
5551 22:53:02.413856
5552 22:53:02.413913 ==
5553 22:53:02.413965 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 22:53:02.414017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 22:53:02.414069 ==
5556 22:53:02.414132 [Gating] SW mode calibration
5557 22:53:02.418919 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5558 22:53:02.425776 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5559 22:53:02.429296 0 14 0 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
5560 22:53:02.432083 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 22:53:02.439142 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 22:53:02.442602 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 22:53:02.445309 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 22:53:02.452346 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 22:53:02.455355 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 22:53:02.458796 0 14 28 | B1->B0 | 2f2f 3131 | 1 0 | (1 0) (1 0)
5567 22:53:02.465252 0 15 0 | B1->B0 | 2626 2424 | 0 0 | (1 1) (0 0)
5568 22:53:02.468609 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 22:53:02.472160 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 22:53:02.478851 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 22:53:02.481526 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 22:53:02.485175 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 22:53:02.491850 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 22:53:02.495239 0 15 28 | B1->B0 | 3333 3535 | 0 0 | (0 0) (0 0)
5575 22:53:02.498616 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 22:53:02.505096 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 22:53:02.508352 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 22:53:02.511698 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 22:53:02.518019 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 22:53:02.521500 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 22:53:02.525105 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 22:53:02.531393 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5583 22:53:02.534750 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5584 22:53:02.538088 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 22:53:02.545038 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 22:53:02.548433 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 22:53:02.551385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 22:53:02.558101 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 22:53:02.561453 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 22:53:02.564901 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 22:53:02.571585 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 22:53:02.574523 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 22:53:02.577820 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 22:53:02.584426 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 22:53:02.587968 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 22:53:02.591251 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 22:53:02.598010 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 22:53:02.601250 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5599 22:53:02.604677 Total UI for P1: 0, mck2ui 16
5600 22:53:02.607554 best dqsien dly found for B1: ( 1, 2, 26)
5601 22:53:02.611358 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5602 22:53:02.617629 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 22:53:02.618070 Total UI for P1: 0, mck2ui 16
5604 22:53:02.624372 best dqsien dly found for B0: ( 1, 2, 30)
5605 22:53:02.627663 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5606 22:53:02.630709 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5607 22:53:02.631181
5608 22:53:02.634044 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5609 22:53:02.637262 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5610 22:53:02.640590 [Gating] SW calibration Done
5611 22:53:02.641046 ==
5612 22:53:02.643978 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 22:53:02.647250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 22:53:02.647895 ==
5615 22:53:02.650676 RX Vref Scan: 0
5616 22:53:02.651131
5617 22:53:02.651602 RX Vref 0 -> 0, step: 1
5618 22:53:02.651932
5619 22:53:02.654007 RX Delay -80 -> 252, step: 8
5620 22:53:02.657152 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5621 22:53:02.663591 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5622 22:53:02.667064 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5623 22:53:02.670222 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5624 22:53:02.673753 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5625 22:53:02.677310 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5626 22:53:02.680673 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5627 22:53:02.687021 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5628 22:53:02.690254 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5629 22:53:02.693413 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5630 22:53:02.697254 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5631 22:53:02.700231 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5632 22:53:02.706816 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5633 22:53:02.710132 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5634 22:53:02.713639 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5635 22:53:02.716675 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5636 22:53:02.717200 ==
5637 22:53:02.720039 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 22:53:02.727128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 22:53:02.727568 ==
5640 22:53:02.727928 DQS Delay:
5641 22:53:02.728262 DQS0 = 0, DQS1 = 0
5642 22:53:02.729853 DQM Delay:
5643 22:53:02.730441 DQM0 = 94, DQM1 = 85
5644 22:53:02.732899 DQ Delay:
5645 22:53:02.736356 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5646 22:53:02.739766 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5647 22:53:02.743140 DQ8 =75, DQ9 =79, DQ10 =83, DQ11 =79
5648 22:53:02.746484 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5649 22:53:02.746572
5650 22:53:02.746636
5651 22:53:02.746695 ==
5652 22:53:02.749485 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 22:53:02.753054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 22:53:02.753122 ==
5655 22:53:02.753188
5656 22:53:02.753264
5657 22:53:02.756370 TX Vref Scan disable
5658 22:53:02.756443 == TX Byte 0 ==
5659 22:53:02.763050 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5660 22:53:02.766282 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5661 22:53:02.766369 == TX Byte 1 ==
5662 22:53:02.772629 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5663 22:53:02.776210 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5664 22:53:02.776326 ==
5665 22:53:02.779536 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 22:53:02.783208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 22:53:02.783322 ==
5668 22:53:02.783429
5669 22:53:02.786216
5670 22:53:02.786348 TX Vref Scan disable
5671 22:53:02.789746 == TX Byte 0 ==
5672 22:53:02.793036 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5673 22:53:02.796088 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5674 22:53:02.799304 == TX Byte 1 ==
5675 22:53:02.802688 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5676 22:53:02.805983 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5677 22:53:02.809114
5678 22:53:02.809214 [DATLAT]
5679 22:53:02.809312 Freq=933, CH1 RK0
5680 22:53:02.809397
5681 22:53:02.812395 DATLAT Default: 0xd
5682 22:53:02.812466 0, 0xFFFF, sum = 0
5683 22:53:02.815616 1, 0xFFFF, sum = 0
5684 22:53:02.815723 2, 0xFFFF, sum = 0
5685 22:53:02.819484 3, 0xFFFF, sum = 0
5686 22:53:02.819560 4, 0xFFFF, sum = 0
5687 22:53:02.822623 5, 0xFFFF, sum = 0
5688 22:53:02.825543 6, 0xFFFF, sum = 0
5689 22:53:02.825634 7, 0xFFFF, sum = 0
5690 22:53:02.829591 8, 0xFFFF, sum = 0
5691 22:53:02.829661 9, 0xFFFF, sum = 0
5692 22:53:02.832242 10, 0x0, sum = 1
5693 22:53:02.832309 11, 0x0, sum = 2
5694 22:53:02.835622 12, 0x0, sum = 3
5695 22:53:02.835691 13, 0x0, sum = 4
5696 22:53:02.835750 best_step = 11
5697 22:53:02.835806
5698 22:53:02.839104 ==
5699 22:53:02.842684 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 22:53:02.845417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 22:53:02.845544 ==
5702 22:53:02.845621 RX Vref Scan: 1
5703 22:53:02.845692
5704 22:53:02.849131 RX Vref 0 -> 0, step: 1
5705 22:53:02.849253
5706 22:53:02.852122 RX Delay -69 -> 252, step: 4
5707 22:53:02.852256
5708 22:53:02.855487 Set Vref, RX VrefLevel [Byte0]: 58
5709 22:53:02.858952 [Byte1]: 49
5710 22:53:02.859061
5711 22:53:02.862600 Final RX Vref Byte 0 = 58 to rank0
5712 22:53:02.865744 Final RX Vref Byte 1 = 49 to rank0
5713 22:53:02.869118 Final RX Vref Byte 0 = 58 to rank1
5714 22:53:02.872119 Final RX Vref Byte 1 = 49 to rank1==
5715 22:53:02.875591 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 22:53:02.879111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 22:53:02.881964 ==
5718 22:53:02.882155 DQS Delay:
5719 22:53:02.882310 DQS0 = 0, DQS1 = 0
5720 22:53:02.885339 DQM Delay:
5721 22:53:02.885609 DQM0 = 97, DQM1 = 87
5722 22:53:02.888935 DQ Delay:
5723 22:53:02.892435 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5724 22:53:02.895786 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5725 22:53:02.899242 DQ8 =78, DQ9 =80, DQ10 =86, DQ11 =82
5726 22:53:02.902419 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =92
5727 22:53:02.902848
5728 22:53:02.903182
5729 22:53:02.908801 [DQSOSCAuto] RK0, (LSB)MR18= 0xff07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5730 22:53:02.912209 CH1 RK0: MR19=405, MR18=FF07
5731 22:53:02.918574 CH1_RK0: MR19=0x405, MR18=0xFF07, DQSOSC=419, MR23=63, INC=61, DEC=41
5732 22:53:02.919021
5733 22:53:02.922269 ----->DramcWriteLeveling(PI) begin...
5734 22:53:02.922693 ==
5735 22:53:02.925566 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 22:53:02.928308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 22:53:02.928727 ==
5738 22:53:02.932190 Write leveling (Byte 0): 23 => 23
5739 22:53:02.935148 Write leveling (Byte 1): 29 => 29
5740 22:53:02.938514 DramcWriteLeveling(PI) end<-----
5741 22:53:02.938595
5742 22:53:02.938659 ==
5743 22:53:02.941463 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 22:53:02.944666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 22:53:02.944741 ==
5746 22:53:02.948597 [Gating] SW mode calibration
5747 22:53:02.954651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5748 22:53:02.961588 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5749 22:53:02.965238 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5750 22:53:02.971384 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 22:53:02.974775 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 22:53:02.978230 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 22:53:02.984689 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 22:53:02.987899 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 22:53:02.991384 0 14 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
5756 22:53:02.994875 0 14 28 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
5757 22:53:03.001571 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 22:53:03.004820 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 22:53:03.008416 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 22:53:03.014520 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 22:53:03.017700 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 22:53:03.021148 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 22:53:03.027936 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
5764 22:53:03.031246 0 15 28 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5765 22:53:03.034460 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 22:53:03.041442 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 22:53:03.044510 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 22:53:03.047835 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 22:53:03.054630 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 22:53:03.058089 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 22:53:03.060951 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5772 22:53:03.068032 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5773 22:53:03.070928 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 22:53:03.074389 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 22:53:03.081269 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 22:53:03.084211 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 22:53:03.087561 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 22:53:03.094373 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 22:53:03.097798 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 22:53:03.101579 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 22:53:03.108093 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 22:53:03.110824 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 22:53:03.114375 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 22:53:03.120904 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 22:53:03.124270 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 22:53:03.127449 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 22:53:03.134277 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5788 22:53:03.137869 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5789 22:53:03.140921 Total UI for P1: 0, mck2ui 16
5790 22:53:03.144616 best dqsien dly found for B0: ( 1, 2, 24)
5791 22:53:03.147630 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 22:53:03.150778 Total UI for P1: 0, mck2ui 16
5793 22:53:03.154209 best dqsien dly found for B1: ( 1, 2, 26)
5794 22:53:03.157442 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5795 22:53:03.160776 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5796 22:53:03.161262
5797 22:53:03.164037 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5798 22:53:03.170819 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5799 22:53:03.171328 [Gating] SW calibration Done
5800 22:53:03.171726 ==
5801 22:53:03.174278 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 22:53:03.180631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 22:53:03.181127 ==
5804 22:53:03.181661 RX Vref Scan: 0
5805 22:53:03.182008
5806 22:53:03.183993 RX Vref 0 -> 0, step: 1
5807 22:53:03.184455
5808 22:53:03.187555 RX Delay -80 -> 252, step: 8
5809 22:53:03.190411 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5810 22:53:03.193791 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5811 22:53:03.197088 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5812 22:53:03.203795 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5813 22:53:03.207361 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5814 22:53:03.210784 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5815 22:53:03.213934 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5816 22:53:03.217133 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5817 22:53:03.220858 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5818 22:53:03.227246 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5819 22:53:03.230407 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5820 22:53:03.233401 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5821 22:53:03.237100 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5822 22:53:03.240254 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5823 22:53:03.246848 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5824 22:53:03.250089 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5825 22:53:03.250622 ==
5826 22:53:03.253565 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 22:53:03.257005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 22:53:03.257593 ==
5829 22:53:03.257978 DQS Delay:
5830 22:53:03.260515 DQS0 = 0, DQS1 = 0
5831 22:53:03.260947 DQM Delay:
5832 22:53:03.263737 DQM0 = 93, DQM1 = 87
5833 22:53:03.264174 DQ Delay:
5834 22:53:03.267164 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5835 22:53:03.270331 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5836 22:53:03.273590 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5837 22:53:03.276811 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5838 22:53:03.277239
5839 22:53:03.277643
5840 22:53:03.278090 ==
5841 22:53:03.280272 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 22:53:03.286666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 22:53:03.287099 ==
5844 22:53:03.287451
5845 22:53:03.287775
5846 22:53:03.288076 TX Vref Scan disable
5847 22:53:03.290093 == TX Byte 0 ==
5848 22:53:03.293480 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5849 22:53:03.297020 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5850 22:53:03.300257 == TX Byte 1 ==
5851 22:53:03.303534 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5852 22:53:03.306946 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5853 22:53:03.310446 ==
5854 22:53:03.313153 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 22:53:03.316553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 22:53:03.317117 ==
5857 22:53:03.317463
5858 22:53:03.317906
5859 22:53:03.320076 TX Vref Scan disable
5860 22:53:03.320506 == TX Byte 0 ==
5861 22:53:03.326970 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5862 22:53:03.329815 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5863 22:53:03.330313 == TX Byte 1 ==
5864 22:53:03.336312 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5865 22:53:03.340079 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5866 22:53:03.340507
5867 22:53:03.340986 [DATLAT]
5868 22:53:03.343034 Freq=933, CH1 RK1
5869 22:53:03.343449
5870 22:53:03.343792 DATLAT Default: 0xb
5871 22:53:03.346541 0, 0xFFFF, sum = 0
5872 22:53:03.346967 1, 0xFFFF, sum = 0
5873 22:53:03.349464 2, 0xFFFF, sum = 0
5874 22:53:03.353395 3, 0xFFFF, sum = 0
5875 22:53:03.353868 4, 0xFFFF, sum = 0
5876 22:53:03.356646 5, 0xFFFF, sum = 0
5877 22:53:03.357082 6, 0xFFFF, sum = 0
5878 22:53:03.359762 7, 0xFFFF, sum = 0
5879 22:53:03.360195 8, 0xFFFF, sum = 0
5880 22:53:03.362993 9, 0xFFFF, sum = 0
5881 22:53:03.363425 10, 0x0, sum = 1
5882 22:53:03.366479 11, 0x0, sum = 2
5883 22:53:03.366912 12, 0x0, sum = 3
5884 22:53:03.369951 13, 0x0, sum = 4
5885 22:53:03.370532 best_step = 11
5886 22:53:03.370880
5887 22:53:03.371208 ==
5888 22:53:03.373264 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 22:53:03.376663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 22:53:03.377098 ==
5891 22:53:03.379694 RX Vref Scan: 0
5892 22:53:03.380121
5893 22:53:03.380490 RX Vref 0 -> 0, step: 1
5894 22:53:03.382989
5895 22:53:03.383415 RX Delay -69 -> 252, step: 4
5896 22:53:03.390835 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5897 22:53:03.394349 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5898 22:53:03.397240 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5899 22:53:03.400345 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5900 22:53:03.403958 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5901 22:53:03.410662 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5902 22:53:03.413575 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5903 22:53:03.416925 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5904 22:53:03.420469 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5905 22:53:03.423922 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5906 22:53:03.427332 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5907 22:53:03.433468 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5908 22:53:03.437019 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5909 22:53:03.440592 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5910 22:53:03.444479 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5911 22:53:03.446818 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5912 22:53:03.447390 ==
5913 22:53:03.450307 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 22:53:03.457013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 22:53:03.457472 ==
5916 22:53:03.458003 DQS Delay:
5917 22:53:03.460412 DQS0 = 0, DQS1 = 0
5918 22:53:03.460862 DQM Delay:
5919 22:53:03.461281 DQM0 = 91, DQM1 = 91
5920 22:53:03.463654 DQ Delay:
5921 22:53:03.467135 DQ0 =96, DQ1 =86, DQ2 =80, DQ3 =88
5922 22:53:03.470068 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =88
5923 22:53:03.473617 DQ8 =78, DQ9 =82, DQ10 =94, DQ11 =86
5924 22:53:03.476574 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =96
5925 22:53:03.476999
5926 22:53:03.477347
5927 22:53:03.483516 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5928 22:53:03.486644 CH1 RK1: MR19=505, MR18=B1F
5929 22:53:03.493632 CH1_RK1: MR19=0x505, MR18=0xB1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5930 22:53:03.496506 [RxdqsGatingPostProcess] freq 933
5931 22:53:03.500045 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5932 22:53:03.503544 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 22:53:03.506308 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 22:53:03.510238 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 22:53:03.513495 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 22:53:03.516530 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 22:53:03.519937 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 22:53:03.523276 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 22:53:03.526757 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 22:53:03.529645 Pre-setting of DQS Precalculation
5941 22:53:03.533118 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5942 22:53:03.543226 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5943 22:53:03.549496 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5944 22:53:03.550054
5945 22:53:03.550408
5946 22:53:03.552917 [Calibration Summary] 1866 Mbps
5947 22:53:03.553363 CH 0, Rank 0
5948 22:53:03.556735 SW Impedance : PASS
5949 22:53:03.557161 DUTY Scan : NO K
5950 22:53:03.559534 ZQ Calibration : PASS
5951 22:53:03.562863 Jitter Meter : NO K
5952 22:53:03.563418 CBT Training : PASS
5953 22:53:03.566430 Write leveling : PASS
5954 22:53:03.569727 RX DQS gating : PASS
5955 22:53:03.570342 RX DQ/DQS(RDDQC) : PASS
5956 22:53:03.572916 TX DQ/DQS : PASS
5957 22:53:03.576164 RX DATLAT : PASS
5958 22:53:03.576649 RX DQ/DQS(Engine): PASS
5959 22:53:03.579529 TX OE : NO K
5960 22:53:03.579969 All Pass.
5961 22:53:03.580344
5962 22:53:03.582995 CH 0, Rank 1
5963 22:53:03.583540 SW Impedance : PASS
5964 22:53:03.586043 DUTY Scan : NO K
5965 22:53:03.589489 ZQ Calibration : PASS
5966 22:53:03.590039 Jitter Meter : NO K
5967 22:53:03.592660 CBT Training : PASS
5968 22:53:03.595864 Write leveling : PASS
5969 22:53:03.596404 RX DQS gating : PASS
5970 22:53:03.599442 RX DQ/DQS(RDDQC) : PASS
5971 22:53:03.599874 TX DQ/DQS : PASS
5972 22:53:03.602468 RX DATLAT : PASS
5973 22:53:03.605830 RX DQ/DQS(Engine): PASS
5974 22:53:03.606263 TX OE : NO K
5975 22:53:03.609337 All Pass.
5976 22:53:03.609819
5977 22:53:03.610179 CH 1, Rank 0
5978 22:53:03.612643 SW Impedance : PASS
5979 22:53:03.613092 DUTY Scan : NO K
5980 22:53:03.615895 ZQ Calibration : PASS
5981 22:53:03.619089 Jitter Meter : NO K
5982 22:53:03.619530 CBT Training : PASS
5983 22:53:03.622992 Write leveling : PASS
5984 22:53:03.625874 RX DQS gating : PASS
5985 22:53:03.626308 RX DQ/DQS(RDDQC) : PASS
5986 22:53:03.629142 TX DQ/DQS : PASS
5987 22:53:03.632496 RX DATLAT : PASS
5988 22:53:03.632969 RX DQ/DQS(Engine): PASS
5989 22:53:03.635958 TX OE : NO K
5990 22:53:03.636469 All Pass.
5991 22:53:03.636895
5992 22:53:03.639366 CH 1, Rank 1
5993 22:53:03.639868 SW Impedance : PASS
5994 22:53:03.642936 DUTY Scan : NO K
5995 22:53:03.646105 ZQ Calibration : PASS
5996 22:53:03.646609 Jitter Meter : NO K
5997 22:53:03.649276 CBT Training : PASS
5998 22:53:03.652519 Write leveling : PASS
5999 22:53:03.653012 RX DQS gating : PASS
6000 22:53:03.655919 RX DQ/DQS(RDDQC) : PASS
6001 22:53:03.658737 TX DQ/DQS : PASS
6002 22:53:03.659253 RX DATLAT : PASS
6003 22:53:03.662125 RX DQ/DQS(Engine): PASS
6004 22:53:03.662594 TX OE : NO K
6005 22:53:03.665629 All Pass.
6006 22:53:03.666060
6007 22:53:03.666405 DramC Write-DBI off
6008 22:53:03.668852 PER_BANK_REFRESH: Hybrid Mode
6009 22:53:03.672231 TX_TRACKING: ON
6010 22:53:03.678988 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6011 22:53:03.682217 [FAST_K] Save calibration result to emmc
6012 22:53:03.688854 dramc_set_vcore_voltage set vcore to 650000
6013 22:53:03.689288 Read voltage for 400, 6
6014 22:53:03.689673 Vio18 = 0
6015 22:53:03.691903 Vcore = 650000
6016 22:53:03.692334 Vdram = 0
6017 22:53:03.692696 Vddq = 0
6018 22:53:03.695707 Vmddr = 0
6019 22:53:03.698738 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6020 22:53:03.705442 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6021 22:53:03.705648 MEM_TYPE=3, freq_sel=20
6022 22:53:03.708360 sv_algorithm_assistance_LP4_800
6023 22:53:03.714940 ============ PULL DRAM RESETB DOWN ============
6024 22:53:03.718471 ========== PULL DRAM RESETB DOWN end =========
6025 22:53:03.721737 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 22:53:03.725342 ===================================
6027 22:53:03.728255 LPDDR4 DRAM CONFIGURATION
6028 22:53:03.731476 ===================================
6029 22:53:03.735019 EX_ROW_EN[0] = 0x0
6030 22:53:03.735092 EX_ROW_EN[1] = 0x0
6031 22:53:03.738539 LP4Y_EN = 0x0
6032 22:53:03.738611 WORK_FSP = 0x0
6033 22:53:03.742145 WL = 0x2
6034 22:53:03.742217 RL = 0x2
6035 22:53:03.744644 BL = 0x2
6036 22:53:03.744716 RPST = 0x0
6037 22:53:03.747931 RD_PRE = 0x0
6038 22:53:03.748005 WR_PRE = 0x1
6039 22:53:03.751695 WR_PST = 0x0
6040 22:53:03.751793 DBI_WR = 0x0
6041 22:53:03.754591 DBI_RD = 0x0
6042 22:53:03.754662 OTF = 0x1
6043 22:53:03.758060 ===================================
6044 22:53:03.761312 ===================================
6045 22:53:03.764949 ANA top config
6046 22:53:03.768111 ===================================
6047 22:53:03.771614 DLL_ASYNC_EN = 0
6048 22:53:03.771711 ALL_SLAVE_EN = 1
6049 22:53:03.774812 NEW_RANK_MODE = 1
6050 22:53:03.778177 DLL_IDLE_MODE = 1
6051 22:53:03.781221 LP45_APHY_COMB_EN = 1
6052 22:53:03.781305 TX_ODT_DIS = 1
6053 22:53:03.784342 NEW_8X_MODE = 1
6054 22:53:03.787705 ===================================
6055 22:53:03.791033 ===================================
6056 22:53:03.794555 data_rate = 800
6057 22:53:03.797984 CKR = 1
6058 22:53:03.801406 DQ_P2S_RATIO = 4
6059 22:53:03.804378 ===================================
6060 22:53:03.807609 CA_P2S_RATIO = 4
6061 22:53:03.807723 DQ_CA_OPEN = 0
6062 22:53:03.811125 DQ_SEMI_OPEN = 1
6063 22:53:03.814433 CA_SEMI_OPEN = 1
6064 22:53:03.817903 CA_FULL_RATE = 0
6065 22:53:03.820963 DQ_CKDIV4_EN = 0
6066 22:53:03.824090 CA_CKDIV4_EN = 1
6067 22:53:03.824193 CA_PREDIV_EN = 0
6068 22:53:03.827522 PH8_DLY = 0
6069 22:53:03.831060 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6070 22:53:03.834042 DQ_AAMCK_DIV = 0
6071 22:53:03.837360 CA_AAMCK_DIV = 0
6072 22:53:03.841236 CA_ADMCK_DIV = 4
6073 22:53:03.841364 DQ_TRACK_CA_EN = 0
6074 22:53:03.844529 CA_PICK = 800
6075 22:53:03.847868 CA_MCKIO = 400
6076 22:53:03.850672 MCKIO_SEMI = 400
6077 22:53:03.853994 PLL_FREQ = 3016
6078 22:53:03.857707 DQ_UI_PI_RATIO = 32
6079 22:53:03.860913 CA_UI_PI_RATIO = 32
6080 22:53:03.864490 ===================================
6081 22:53:03.868060 ===================================
6082 22:53:03.868142 memory_type:LPDDR4
6083 22:53:03.871403 GP_NUM : 10
6084 22:53:03.874185 SRAM_EN : 1
6085 22:53:03.874272 MD32_EN : 0
6086 22:53:03.877568 ===================================
6087 22:53:03.880934 [ANA_INIT] >>>>>>>>>>>>>>
6088 22:53:03.884254 <<<<<< [CONFIGURE PHASE]: ANA_TX
6089 22:53:03.887721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6090 22:53:03.891242 ===================================
6091 22:53:03.894236 data_rate = 800,PCW = 0X7400
6092 22:53:03.897813 ===================================
6093 22:53:03.900741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6094 22:53:03.904279 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 22:53:03.917116 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 22:53:03.920486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6097 22:53:03.923731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6098 22:53:03.927090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6099 22:53:03.930763 [ANA_INIT] flow start
6100 22:53:03.934237 [ANA_INIT] PLL >>>>>>>>
6101 22:53:03.934336 [ANA_INIT] PLL <<<<<<<<
6102 22:53:03.937689 [ANA_INIT] MIDPI >>>>>>>>
6103 22:53:03.940787 [ANA_INIT] MIDPI <<<<<<<<
6104 22:53:03.940889 [ANA_INIT] DLL >>>>>>>>
6105 22:53:03.943800 [ANA_INIT] flow end
6106 22:53:03.947193 ============ LP4 DIFF to SE enter ============
6107 22:53:03.950440 ============ LP4 DIFF to SE exit ============
6108 22:53:03.953735 [ANA_INIT] <<<<<<<<<<<<<
6109 22:53:03.956976 [Flow] Enable top DCM control >>>>>
6110 22:53:03.960577 [Flow] Enable top DCM control <<<<<
6111 22:53:03.963841 Enable DLL master slave shuffle
6112 22:53:03.970493 ==============================================================
6113 22:53:03.970755 Gating Mode config
6114 22:53:03.977254 ==============================================================
6115 22:53:03.977603 Config description:
6116 22:53:03.987181 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6117 22:53:03.994003 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6118 22:53:04.000714 SELPH_MODE 0: By rank 1: By Phase
6119 22:53:04.003742 ==============================================================
6120 22:53:04.007174 GAT_TRACK_EN = 0
6121 22:53:04.010417 RX_GATING_MODE = 2
6122 22:53:04.014048 RX_GATING_TRACK_MODE = 2
6123 22:53:04.017290 SELPH_MODE = 1
6124 22:53:04.020341 PICG_EARLY_EN = 1
6125 22:53:04.023780 VALID_LAT_VALUE = 1
6126 22:53:04.029997 ==============================================================
6127 22:53:04.033632 Enter into Gating configuration >>>>
6128 22:53:04.036673 Exit from Gating configuration <<<<
6129 22:53:04.040159 Enter into DVFS_PRE_config >>>>>
6130 22:53:04.050148 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6131 22:53:04.053368 Exit from DVFS_PRE_config <<<<<
6132 22:53:04.056761 Enter into PICG configuration >>>>
6133 22:53:04.059723 Exit from PICG configuration <<<<
6134 22:53:04.063573 [RX_INPUT] configuration >>>>>
6135 22:53:04.064086 [RX_INPUT] configuration <<<<<
6136 22:53:04.070052 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6137 22:53:04.076517 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6138 22:53:04.083122 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 22:53:04.086481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 22:53:04.093240 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 22:53:04.099558 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 22:53:04.102979 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6143 22:53:04.106359 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6144 22:53:04.112518 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6145 22:53:04.116129 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6146 22:53:04.119216 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6147 22:53:04.125918 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 22:53:04.129254 ===================================
6149 22:53:04.129710 LPDDR4 DRAM CONFIGURATION
6150 22:53:04.132745 ===================================
6151 22:53:04.135843 EX_ROW_EN[0] = 0x0
6152 22:53:04.139256 EX_ROW_EN[1] = 0x0
6153 22:53:04.139690 LP4Y_EN = 0x0
6154 22:53:04.142355 WORK_FSP = 0x0
6155 22:53:04.142930 WL = 0x2
6156 22:53:04.145742 RL = 0x2
6157 22:53:04.146171 BL = 0x2
6158 22:53:04.149077 RPST = 0x0
6159 22:53:04.149685 RD_PRE = 0x0
6160 22:53:04.152398 WR_PRE = 0x1
6161 22:53:04.152823 WR_PST = 0x0
6162 22:53:04.155637 DBI_WR = 0x0
6163 22:53:04.156219 DBI_RD = 0x0
6164 22:53:04.158823 OTF = 0x1
6165 22:53:04.162369 ===================================
6166 22:53:04.165690 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6167 22:53:04.168971 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6168 22:53:04.175413 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 22:53:04.178730 ===================================
6170 22:53:04.179161 LPDDR4 DRAM CONFIGURATION
6171 22:53:04.182619 ===================================
6172 22:53:04.185475 EX_ROW_EN[0] = 0x10
6173 22:53:04.189107 EX_ROW_EN[1] = 0x0
6174 22:53:04.189580 LP4Y_EN = 0x0
6175 22:53:04.192465 WORK_FSP = 0x0
6176 22:53:04.192911 WL = 0x2
6177 22:53:04.195890 RL = 0x2
6178 22:53:04.196316 BL = 0x2
6179 22:53:04.199064 RPST = 0x0
6180 22:53:04.199503 RD_PRE = 0x0
6181 22:53:04.202297 WR_PRE = 0x1
6182 22:53:04.202735 WR_PST = 0x0
6183 22:53:04.205789 DBI_WR = 0x0
6184 22:53:04.206214 DBI_RD = 0x0
6185 22:53:04.209274 OTF = 0x1
6186 22:53:04.212017 ===================================
6187 22:53:04.218856 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6188 22:53:04.222213 nWR fixed to 30
6189 22:53:04.222653 [ModeRegInit_LP4] CH0 RK0
6190 22:53:04.225505 [ModeRegInit_LP4] CH0 RK1
6191 22:53:04.228875 [ModeRegInit_LP4] CH1 RK0
6192 22:53:04.232124 [ModeRegInit_LP4] CH1 RK1
6193 22:53:04.232548 match AC timing 19
6194 22:53:04.235521 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6195 22:53:04.242230 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6196 22:53:04.245470 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6197 22:53:04.248321 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6198 22:53:04.255322 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6199 22:53:04.255768 ==
6200 22:53:04.258526 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 22:53:04.261869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6202 22:53:04.262435 ==
6203 22:53:04.268486 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6204 22:53:04.275169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6205 22:53:04.278572 [CA 0] Center 36 (8~64) winsize 57
6206 22:53:04.279004 [CA 1] Center 36 (8~64) winsize 57
6207 22:53:04.281834 [CA 2] Center 36 (8~64) winsize 57
6208 22:53:04.285115 [CA 3] Center 36 (8~64) winsize 57
6209 22:53:04.288442 [CA 4] Center 36 (8~64) winsize 57
6210 22:53:04.291853 [CA 5] Center 36 (8~64) winsize 57
6211 22:53:04.292280
6212 22:53:04.295110 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6213 22:53:04.295611
6214 22:53:04.298619 [CATrainingPosCal] consider 1 rank data
6215 22:53:04.301399 u2DelayCellTimex100 = 270/100 ps
6216 22:53:04.305203 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 22:53:04.311586 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 22:53:04.314980 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 22:53:04.318430 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 22:53:04.321587 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 22:53:04.324844 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 22:53:04.325273
6223 22:53:04.328236 CA PerBit enable=1, Macro0, CA PI delay=36
6224 22:53:04.328675
6225 22:53:04.331684 [CBTSetCACLKResult] CA Dly = 36
6226 22:53:04.332097 CS Dly: 1 (0~32)
6227 22:53:04.334872 ==
6228 22:53:04.338174 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 22:53:04.341554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 22:53:04.342109 ==
6231 22:53:04.344947 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 22:53:04.351484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6233 22:53:04.354733 [CA 0] Center 36 (8~64) winsize 57
6234 22:53:04.357941 [CA 1] Center 36 (8~64) winsize 57
6235 22:53:04.361237 [CA 2] Center 36 (8~64) winsize 57
6236 22:53:04.364394 [CA 3] Center 36 (8~64) winsize 57
6237 22:53:04.367942 [CA 4] Center 36 (8~64) winsize 57
6238 22:53:04.371552 [CA 5] Center 36 (8~64) winsize 57
6239 22:53:04.372104
6240 22:53:04.374436 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6241 22:53:04.374882
6242 22:53:04.377559 [CATrainingPosCal] consider 2 rank data
6243 22:53:04.381111 u2DelayCellTimex100 = 270/100 ps
6244 22:53:04.384732 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 22:53:04.387611 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 22:53:04.391349 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 22:53:04.394454 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 22:53:04.400954 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 22:53:04.404594 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:53:04.405024
6251 22:53:04.408086 CA PerBit enable=1, Macro0, CA PI delay=36
6252 22:53:04.408636
6253 22:53:04.411797 [CBTSetCACLKResult] CA Dly = 36
6254 22:53:04.412226 CS Dly: 1 (0~32)
6255 22:53:04.412560
6256 22:53:04.414619 ----->DramcWriteLeveling(PI) begin...
6257 22:53:04.415059 ==
6258 22:53:04.418170 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 22:53:04.424036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 22:53:04.424482 ==
6261 22:53:04.427673 Write leveling (Byte 0): 40 => 8
6262 22:53:04.428107 Write leveling (Byte 1): 40 => 8
6263 22:53:04.431125 DramcWriteLeveling(PI) end<-----
6264 22:53:04.431567
6265 22:53:04.431901 ==
6266 22:53:04.434140 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 22:53:04.440923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 22:53:04.441341 ==
6269 22:53:04.444160 [Gating] SW mode calibration
6270 22:53:04.451002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 22:53:04.454169 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6272 22:53:04.461010 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 22:53:04.464377 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 22:53:04.467514 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 22:53:04.474048 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 22:53:04.477532 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 22:53:04.480936 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 22:53:04.487397 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 22:53:04.490751 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 22:53:04.494332 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 22:53:04.496956 Total UI for P1: 0, mck2ui 16
6282 22:53:04.500846 best dqsien dly found for B0: ( 0, 14, 24)
6283 22:53:04.503903 Total UI for P1: 0, mck2ui 16
6284 22:53:04.507523 best dqsien dly found for B1: ( 0, 14, 24)
6285 22:53:04.510423 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6286 22:53:04.514032 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6287 22:53:04.514477
6288 22:53:04.517418 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 22:53:04.523998 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 22:53:04.524473 [Gating] SW calibration Done
6291 22:53:04.527234 ==
6292 22:53:04.527661 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 22:53:04.534316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 22:53:04.534835 ==
6295 22:53:04.535192 RX Vref Scan: 0
6296 22:53:04.535528
6297 22:53:04.537235 RX Vref 0 -> 0, step: 1
6298 22:53:04.537698
6299 22:53:04.540089 RX Delay -410 -> 252, step: 16
6300 22:53:04.543753 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6301 22:53:04.547059 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6302 22:53:04.553446 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6303 22:53:04.556607 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6304 22:53:04.560234 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6305 22:53:04.563742 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6306 22:53:04.570006 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6307 22:53:04.573278 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6308 22:53:04.576463 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6309 22:53:04.579925 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6310 22:53:04.586550 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6311 22:53:04.589803 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6312 22:53:04.593504 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6313 22:53:04.600056 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6314 22:53:04.603102 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6315 22:53:04.606666 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6316 22:53:04.607100 ==
6317 22:53:04.609923 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 22:53:04.613188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 22:53:04.616318 ==
6320 22:53:04.616742 DQS Delay:
6321 22:53:04.617075 DQS0 = 59, DQS1 = 59
6322 22:53:04.619898 DQM Delay:
6323 22:53:04.620313 DQM0 = 18, DQM1 = 10
6324 22:53:04.623164 DQ Delay:
6325 22:53:04.626534 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6326 22:53:04.626952 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6327 22:53:04.629960 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6328 22:53:04.633030 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6329 22:53:04.633450
6330 22:53:04.633832
6331 22:53:04.636332 ==
6332 22:53:04.639786 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 22:53:04.642873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 22:53:04.643296 ==
6335 22:53:04.643628
6336 22:53:04.643936
6337 22:53:04.646329 TX Vref Scan disable
6338 22:53:04.646747 == TX Byte 0 ==
6339 22:53:04.649464 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 22:53:04.656334 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 22:53:04.656769 == TX Byte 1 ==
6342 22:53:04.659538 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 22:53:04.666172 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 22:53:04.666611 ==
6345 22:53:04.669478 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 22:53:04.672644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 22:53:04.673084 ==
6348 22:53:04.673435
6349 22:53:04.673810
6350 22:53:04.676327 TX Vref Scan disable
6351 22:53:04.676741 == TX Byte 0 ==
6352 22:53:04.679649 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 22:53:04.686484 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 22:53:04.686921 == TX Byte 1 ==
6355 22:53:04.689794 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 22:53:04.696236 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 22:53:04.696647
6358 22:53:04.696971 [DATLAT]
6359 22:53:04.697274 Freq=400, CH0 RK0
6360 22:53:04.697611
6361 22:53:04.699556 DATLAT Default: 0xf
6362 22:53:04.699965 0, 0xFFFF, sum = 0
6363 22:53:04.703063 1, 0xFFFF, sum = 0
6364 22:53:04.706388 2, 0xFFFF, sum = 0
6365 22:53:04.706836 3, 0xFFFF, sum = 0
6366 22:53:04.709676 4, 0xFFFF, sum = 0
6367 22:53:04.710093 5, 0xFFFF, sum = 0
6368 22:53:04.712826 6, 0xFFFF, sum = 0
6369 22:53:04.713254 7, 0xFFFF, sum = 0
6370 22:53:04.716269 8, 0xFFFF, sum = 0
6371 22:53:04.716686 9, 0xFFFF, sum = 0
6372 22:53:04.719695 10, 0xFFFF, sum = 0
6373 22:53:04.720113 11, 0xFFFF, sum = 0
6374 22:53:04.722451 12, 0xFFFF, sum = 0
6375 22:53:04.722871 13, 0x0, sum = 1
6376 22:53:04.725795 14, 0x0, sum = 2
6377 22:53:04.726211 15, 0x0, sum = 3
6378 22:53:04.729303 16, 0x0, sum = 4
6379 22:53:04.729852 best_step = 14
6380 22:53:04.730185
6381 22:53:04.730491 ==
6382 22:53:04.732812 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 22:53:04.735764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 22:53:04.739096 ==
6385 22:53:04.739509 RX Vref Scan: 1
6386 22:53:04.739830
6387 22:53:04.742471 RX Vref 0 -> 0, step: 1
6388 22:53:04.742882
6389 22:53:04.745701 RX Delay -359 -> 252, step: 8
6390 22:53:04.746115
6391 22:53:04.749072 Set Vref, RX VrefLevel [Byte0]: 63
6392 22:53:04.752113 [Byte1]: 58
6393 22:53:04.752524
6394 22:53:04.755564 Final RX Vref Byte 0 = 63 to rank0
6395 22:53:04.759033 Final RX Vref Byte 1 = 58 to rank0
6396 22:53:04.762437 Final RX Vref Byte 0 = 63 to rank1
6397 22:53:04.765886 Final RX Vref Byte 1 = 58 to rank1==
6398 22:53:04.768856 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 22:53:04.772105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 22:53:04.775743 ==
6401 22:53:04.776173 DQS Delay:
6402 22:53:04.776508 DQS0 = 60, DQS1 = 68
6403 22:53:04.778937 DQM Delay:
6404 22:53:04.779421 DQM0 = 14, DQM1 = 14
6405 22:53:04.782308 DQ Delay:
6406 22:53:04.785320 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6407 22:53:04.785838 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6408 22:53:04.788616 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6409 22:53:04.791866 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6410 22:53:04.792282
6411 22:53:04.792609
6412 22:53:04.801857 [DQSOSCAuto] RK0, (LSB)MR18= 0x8482, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6413 22:53:04.805352 CH0 RK0: MR19=C0C, MR18=8482
6414 22:53:04.812107 CH0_RK0: MR19=0xC0C, MR18=0x8482, DQSOSC=393, MR23=63, INC=382, DEC=254
6415 22:53:04.812656 ==
6416 22:53:04.815470 Dram Type= 6, Freq= 0, CH_0, rank 1
6417 22:53:04.818820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 22:53:04.819269 ==
6419 22:53:04.821948 [Gating] SW mode calibration
6420 22:53:04.828201 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 22:53:04.834728 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6422 22:53:04.838103 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 22:53:04.841460 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 22:53:04.848190 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 22:53:04.851536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 22:53:04.854849 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 22:53:04.861345 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 22:53:04.864660 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 22:53:04.868105 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 22:53:04.874688 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 22:53:04.875125 Total UI for P1: 0, mck2ui 16
6432 22:53:04.877954 best dqsien dly found for B0: ( 0, 14, 24)
6433 22:53:04.881145 Total UI for P1: 0, mck2ui 16
6434 22:53:04.884917 best dqsien dly found for B1: ( 0, 14, 24)
6435 22:53:04.890973 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6436 22:53:04.894531 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6437 22:53:04.894948
6438 22:53:04.897628 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 22:53:04.901067 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 22:53:04.904383 [Gating] SW calibration Done
6441 22:53:04.904795 ==
6442 22:53:04.907683 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 22:53:04.911162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 22:53:04.911579 ==
6445 22:53:04.913958 RX Vref Scan: 0
6446 22:53:04.914371
6447 22:53:04.914696 RX Vref 0 -> 0, step: 1
6448 22:53:04.915000
6449 22:53:04.917532 RX Delay -410 -> 252, step: 16
6450 22:53:04.924378 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6451 22:53:04.927474 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6452 22:53:04.930556 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6453 22:53:04.934288 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6454 22:53:04.940392 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6455 22:53:04.944140 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6456 22:53:04.946966 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6457 22:53:04.950454 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6458 22:53:04.957022 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6459 22:53:04.960751 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6460 22:53:04.963836 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6461 22:53:04.967291 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6462 22:53:04.973315 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6463 22:53:04.977167 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6464 22:53:04.980206 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6465 22:53:04.983424 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6466 22:53:04.986939 ==
6467 22:53:04.990171 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 22:53:04.993812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 22:53:04.994243 ==
6470 22:53:04.994576 DQS Delay:
6471 22:53:04.996833 DQS0 = 59, DQS1 = 59
6472 22:53:04.997246 DQM Delay:
6473 22:53:05.000075 DQM0 = 16, DQM1 = 10
6474 22:53:05.000559 DQ Delay:
6475 22:53:05.003915 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6476 22:53:05.006510 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6477 22:53:05.010022 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6478 22:53:05.013363 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6479 22:53:05.013819
6480 22:53:05.014147
6481 22:53:05.014449 ==
6482 22:53:05.016519 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 22:53:05.020068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 22:53:05.020487 ==
6485 22:53:05.020815
6486 22:53:05.021116
6487 22:53:05.023380 TX Vref Scan disable
6488 22:53:05.023795 == TX Byte 0 ==
6489 22:53:05.030062 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6490 22:53:05.032893 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6491 22:53:05.033314 == TX Byte 1 ==
6492 22:53:05.039834 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6493 22:53:05.043298 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6494 22:53:05.043751 ==
6495 22:53:05.046746 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 22:53:05.050164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 22:53:05.050856 ==
6498 22:53:05.053230
6499 22:53:05.053710
6500 22:53:05.054064 TX Vref Scan disable
6501 22:53:05.056463 == TX Byte 0 ==
6502 22:53:05.059583 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6503 22:53:05.062889 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6504 22:53:05.066064 == TX Byte 1 ==
6505 22:53:05.069707 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6506 22:53:05.073204 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6507 22:53:05.073695
6508 22:53:05.076400 [DATLAT]
6509 22:53:05.076831 Freq=400, CH0 RK1
6510 22:53:05.077178
6511 22:53:05.079720 DATLAT Default: 0xe
6512 22:53:05.080099 0, 0xFFFF, sum = 0
6513 22:53:05.082672 1, 0xFFFF, sum = 0
6514 22:53:05.083248 2, 0xFFFF, sum = 0
6515 22:53:05.085583 3, 0xFFFF, sum = 0
6516 22:53:05.085963 4, 0xFFFF, sum = 0
6517 22:53:05.089290 5, 0xFFFF, sum = 0
6518 22:53:05.089818 6, 0xFFFF, sum = 0
6519 22:53:05.092727 7, 0xFFFF, sum = 0
6520 22:53:05.093160 8, 0xFFFF, sum = 0
6521 22:53:05.096088 9, 0xFFFF, sum = 0
6522 22:53:05.096661 10, 0xFFFF, sum = 0
6523 22:53:05.098986 11, 0xFFFF, sum = 0
6524 22:53:05.102535 12, 0xFFFF, sum = 0
6525 22:53:05.102994 13, 0x0, sum = 1
6526 22:53:05.103453 14, 0x0, sum = 2
6527 22:53:05.106057 15, 0x0, sum = 3
6528 22:53:05.106500 16, 0x0, sum = 4
6529 22:53:05.109011 best_step = 14
6530 22:53:05.109594
6531 22:53:05.109965 ==
6532 22:53:05.112400 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 22:53:05.115939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 22:53:05.116500 ==
6535 22:53:05.119018 RX Vref Scan: 0
6536 22:53:05.119616
6537 22:53:05.120117 RX Vref 0 -> 0, step: 1
6538 22:53:05.120592
6539 22:53:05.122063 RX Delay -359 -> 252, step: 8
6540 22:53:05.130515 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6541 22:53:05.133882 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6542 22:53:05.137202 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6543 22:53:05.140494 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6544 22:53:05.147560 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6545 22:53:05.150577 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6546 22:53:05.154085 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6547 22:53:05.157340 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6548 22:53:05.164196 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6549 22:53:05.167631 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6550 22:53:05.170728 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6551 22:53:05.173955 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6552 22:53:05.180724 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6553 22:53:05.183576 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6554 22:53:05.186928 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6555 22:53:05.194067 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6556 22:53:05.194518 ==
6557 22:53:05.197313 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 22:53:05.200678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 22:53:05.201099 ==
6560 22:53:05.201433 DQS Delay:
6561 22:53:05.203499 DQS0 = 60, DQS1 = 68
6562 22:53:05.203914 DQM Delay:
6563 22:53:05.206971 DQM0 = 12, DQM1 = 14
6564 22:53:05.207388 DQ Delay:
6565 22:53:05.210298 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6566 22:53:05.213628 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6567 22:53:05.216967 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6568 22:53:05.220193 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6569 22:53:05.220609
6570 22:53:05.220939
6571 22:53:05.226817 [DQSOSCAuto] RK1, (LSB)MR18= 0xcd81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6572 22:53:05.230474 CH0 RK1: MR19=C0C, MR18=CD81
6573 22:53:05.236899 CH0_RK1: MR19=0xC0C, MR18=0xCD81, DQSOSC=384, MR23=63, INC=400, DEC=267
6574 22:53:05.240460 [RxdqsGatingPostProcess] freq 400
6575 22:53:05.246804 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6576 22:53:05.250167 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 22:53:05.250606 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 22:53:05.253461 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 22:53:05.256540 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 22:53:05.260051 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 22:53:05.263084 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 22:53:05.266674 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 22:53:05.269906 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 22:53:05.273309 Pre-setting of DQS Precalculation
6585 22:53:05.279711 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6586 22:53:05.280150 ==
6587 22:53:05.283119 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 22:53:05.286796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 22:53:05.287276 ==
6590 22:53:05.293503 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6591 22:53:05.296583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6592 22:53:05.299851 [CA 0] Center 36 (8~64) winsize 57
6593 22:53:05.303210 [CA 1] Center 36 (8~64) winsize 57
6594 22:53:05.307115 [CA 2] Center 36 (8~64) winsize 57
6595 22:53:05.309871 [CA 3] Center 36 (8~64) winsize 57
6596 22:53:05.313784 [CA 4] Center 36 (8~64) winsize 57
6597 22:53:05.316578 [CA 5] Center 36 (8~64) winsize 57
6598 22:53:05.317015
6599 22:53:05.320056 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6600 22:53:05.320493
6601 22:53:05.323206 [CATrainingPosCal] consider 1 rank data
6602 22:53:05.326333 u2DelayCellTimex100 = 270/100 ps
6603 22:53:05.330005 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 22:53:05.333344 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 22:53:05.336300 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 22:53:05.342671 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 22:53:05.346036 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 22:53:05.349432 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 22:53:05.349928
6610 22:53:05.353012 CA PerBit enable=1, Macro0, CA PI delay=36
6611 22:53:05.353449
6612 22:53:05.356071 [CBTSetCACLKResult] CA Dly = 36
6613 22:53:05.356586 CS Dly: 1 (0~32)
6614 22:53:05.357028 ==
6615 22:53:05.359319 Dram Type= 6, Freq= 0, CH_1, rank 1
6616 22:53:05.366068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 22:53:05.366507 ==
6618 22:53:05.369458 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 22:53:05.375944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6620 22:53:05.379371 [CA 0] Center 36 (8~64) winsize 57
6621 22:53:05.382571 [CA 1] Center 36 (8~64) winsize 57
6622 22:53:05.385845 [CA 2] Center 36 (8~64) winsize 57
6623 22:53:05.389224 [CA 3] Center 36 (8~64) winsize 57
6624 22:53:05.392713 [CA 4] Center 36 (8~64) winsize 57
6625 22:53:05.395524 [CA 5] Center 36 (8~64) winsize 57
6626 22:53:05.395944
6627 22:53:05.399483 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6628 22:53:05.399901
6629 22:53:05.402417 [CATrainingPosCal] consider 2 rank data
6630 22:53:05.405856 u2DelayCellTimex100 = 270/100 ps
6631 22:53:05.409015 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 22:53:05.412515 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 22:53:05.415537 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 22:53:05.418759 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 22:53:05.425357 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 22:53:05.428729 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:53:05.429168
6638 22:53:05.432253 CA PerBit enable=1, Macro0, CA PI delay=36
6639 22:53:05.432780
6640 22:53:05.435287 [CBTSetCACLKResult] CA Dly = 36
6641 22:53:05.435663 CS Dly: 1 (0~32)
6642 22:53:05.435985
6643 22:53:05.438803 ----->DramcWriteLeveling(PI) begin...
6644 22:53:05.439287 ==
6645 22:53:05.442092 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 22:53:05.448643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 22:53:05.449078 ==
6648 22:53:05.451944 Write leveling (Byte 0): 40 => 8
6649 22:53:05.452378 Write leveling (Byte 1): 40 => 8
6650 22:53:05.455269 DramcWriteLeveling(PI) end<-----
6651 22:53:05.455858
6652 22:53:05.458485 ==
6653 22:53:05.458948 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 22:53:05.465175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 22:53:05.465675 ==
6656 22:53:05.468421 [Gating] SW mode calibration
6657 22:53:05.474979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6658 22:53:05.478337 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6659 22:53:05.485071 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 22:53:05.488334 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 22:53:05.491682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 22:53:05.498042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 22:53:05.501778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 22:53:05.504647 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 22:53:05.511149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 22:53:05.514681 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 22:53:05.518024 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 22:53:05.521503 Total UI for P1: 0, mck2ui 16
6669 22:53:05.524466 best dqsien dly found for B0: ( 0, 14, 24)
6670 22:53:05.527611 Total UI for P1: 0, mck2ui 16
6671 22:53:05.531484 best dqsien dly found for B1: ( 0, 14, 24)
6672 22:53:05.534737 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6673 22:53:05.537606 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6674 22:53:05.538050
6675 22:53:05.544623 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 22:53:05.547716 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 22:53:05.548260 [Gating] SW calibration Done
6678 22:53:05.550865 ==
6679 22:53:05.554259 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 22:53:05.557429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 22:53:05.557879 ==
6682 22:53:05.558215 RX Vref Scan: 0
6683 22:53:05.558525
6684 22:53:05.560863 RX Vref 0 -> 0, step: 1
6685 22:53:05.561287
6686 22:53:05.564116 RX Delay -410 -> 252, step: 16
6687 22:53:05.567442 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6688 22:53:05.573859 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6689 22:53:05.577608 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6690 22:53:05.580609 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6691 22:53:05.583853 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6692 22:53:05.590297 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6693 22:53:05.593973 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6694 22:53:05.596966 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6695 22:53:05.600757 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6696 22:53:05.607029 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6697 22:53:05.610287 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6698 22:53:05.613786 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6699 22:53:05.617145 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6700 22:53:05.623638 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6701 22:53:05.627175 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6702 22:53:05.630106 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6703 22:53:05.630646 ==
6704 22:53:05.633484 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 22:53:05.640407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 22:53:05.640856 ==
6707 22:53:05.641302 DQS Delay:
6708 22:53:05.643692 DQS0 = 51, DQS1 = 67
6709 22:53:05.644198 DQM Delay:
6710 22:53:05.644537 DQM0 = 13, DQM1 = 18
6711 22:53:05.646963 DQ Delay:
6712 22:53:05.650175 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6713 22:53:05.653348 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6714 22:53:05.653795 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6715 22:53:05.656675 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6716 22:53:05.659896
6717 22:53:05.660311
6718 22:53:05.660639 ==
6719 22:53:05.663357 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 22:53:05.666757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 22:53:05.667176 ==
6722 22:53:05.667506
6723 22:53:05.667812
6724 22:53:05.670204 TX Vref Scan disable
6725 22:53:05.670637 == TX Byte 0 ==
6726 22:53:05.673068 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 22:53:05.679784 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 22:53:05.680252 == TX Byte 1 ==
6729 22:53:05.683385 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 22:53:05.689847 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 22:53:05.690294 ==
6732 22:53:05.692976 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 22:53:05.696121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 22:53:05.696606 ==
6735 22:53:05.697057
6736 22:53:05.697479
6737 22:53:05.699637 TX Vref Scan disable
6738 22:53:05.700177 == TX Byte 0 ==
6739 22:53:05.705920 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 22:53:05.709392 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 22:53:05.709865 == TX Byte 1 ==
6742 22:53:05.715779 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 22:53:05.719124 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 22:53:05.719559
6745 22:53:05.719909 [DATLAT]
6746 22:53:05.722603 Freq=400, CH1 RK0
6747 22:53:05.723058
6748 22:53:05.723412 DATLAT Default: 0xf
6749 22:53:05.726061 0, 0xFFFF, sum = 0
6750 22:53:05.726498 1, 0xFFFF, sum = 0
6751 22:53:05.729370 2, 0xFFFF, sum = 0
6752 22:53:05.729851 3, 0xFFFF, sum = 0
6753 22:53:05.732780 4, 0xFFFF, sum = 0
6754 22:53:05.733251 5, 0xFFFF, sum = 0
6755 22:53:05.735846 6, 0xFFFF, sum = 0
6756 22:53:05.736422 7, 0xFFFF, sum = 0
6757 22:53:05.739154 8, 0xFFFF, sum = 0
6758 22:53:05.739574 9, 0xFFFF, sum = 0
6759 22:53:05.742490 10, 0xFFFF, sum = 0
6760 22:53:05.745679 11, 0xFFFF, sum = 0
6761 22:53:05.746156 12, 0xFFFF, sum = 0
6762 22:53:05.746614 13, 0x0, sum = 1
6763 22:53:05.749288 14, 0x0, sum = 2
6764 22:53:05.749839 15, 0x0, sum = 3
6765 22:53:05.752459 16, 0x0, sum = 4
6766 22:53:05.752932 best_step = 14
6767 22:53:05.753367
6768 22:53:05.753835 ==
6769 22:53:05.756169 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 22:53:05.762502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 22:53:05.762959 ==
6772 22:53:05.763408 RX Vref Scan: 1
6773 22:53:05.763831
6774 22:53:05.765598 RX Vref 0 -> 0, step: 1
6775 22:53:05.766000
6776 22:53:05.769219 RX Delay -375 -> 252, step: 8
6777 22:53:05.769709
6778 22:53:05.772483 Set Vref, RX VrefLevel [Byte0]: 58
6779 22:53:05.775841 [Byte1]: 49
6780 22:53:05.779049
6781 22:53:05.779498 Final RX Vref Byte 0 = 58 to rank0
6782 22:53:05.782452 Final RX Vref Byte 1 = 49 to rank0
6783 22:53:05.785806 Final RX Vref Byte 0 = 58 to rank1
6784 22:53:05.789215 Final RX Vref Byte 1 = 49 to rank1==
6785 22:53:05.792560 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 22:53:05.799066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 22:53:05.799631 ==
6788 22:53:05.800117 DQS Delay:
6789 22:53:05.802269 DQS0 = 56, DQS1 = 68
6790 22:53:05.802704 DQM Delay:
6791 22:53:05.803205 DQM0 = 12, DQM1 = 14
6792 22:53:05.805727 DQ Delay:
6793 22:53:05.809146 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6794 22:53:05.809605 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6795 22:53:05.812407 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6796 22:53:05.815512 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6797 22:53:05.815918
6798 22:53:05.818616
6799 22:53:05.824887 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6800 22:53:05.828324 CH1 RK0: MR19=C0C, MR18=5B6E
6801 22:53:05.834869 CH1_RK0: MR19=0xC0C, MR18=0x5B6E, DQSOSC=395, MR23=63, INC=378, DEC=252
6802 22:53:05.834951 ==
6803 22:53:05.838170 Dram Type= 6, Freq= 0, CH_1, rank 1
6804 22:53:05.842080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 22:53:05.842158 ==
6806 22:53:05.845093 [Gating] SW mode calibration
6807 22:53:05.851539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6808 22:53:05.858085 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6809 22:53:05.861316 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 22:53:05.864829 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 22:53:05.871214 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 22:53:05.874551 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 22:53:05.878270 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 22:53:05.884423 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 22:53:05.887605 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 22:53:05.891085 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 22:53:05.897733 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 22:53:05.897810 Total UI for P1: 0, mck2ui 16
6819 22:53:05.904082 best dqsien dly found for B0: ( 0, 14, 24)
6820 22:53:05.904157 Total UI for P1: 0, mck2ui 16
6821 22:53:05.911183 best dqsien dly found for B1: ( 0, 14, 24)
6822 22:53:05.914319 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6823 22:53:05.917328 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6824 22:53:05.917425
6825 22:53:05.920930 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 22:53:05.924099 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 22:53:05.927612 [Gating] SW calibration Done
6828 22:53:05.927685 ==
6829 22:53:05.930589 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 22:53:05.933821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 22:53:05.933896 ==
6832 22:53:05.937517 RX Vref Scan: 0
6833 22:53:05.937624
6834 22:53:05.937704 RX Vref 0 -> 0, step: 1
6835 22:53:05.937784
6836 22:53:05.940769 RX Delay -410 -> 252, step: 16
6837 22:53:05.947433 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6838 22:53:05.950785 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6839 22:53:05.953597 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6840 22:53:05.956883 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6841 22:53:05.964045 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6842 22:53:05.967044 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6843 22:53:05.970428 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6844 22:53:05.973999 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6845 22:53:05.980507 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6846 22:53:05.983808 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6847 22:53:05.987253 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6848 22:53:05.990332 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6849 22:53:05.997241 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6850 22:53:06.000106 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6851 22:53:06.004046 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6852 22:53:06.010162 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6853 22:53:06.010240 ==
6854 22:53:06.013630 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 22:53:06.017155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 22:53:06.017256 ==
6857 22:53:06.017354 DQS Delay:
6858 22:53:06.020263 DQS0 = 59, DQS1 = 59
6859 22:53:06.020361 DQM Delay:
6860 22:53:06.023471 DQM0 = 19, DQM1 = 12
6861 22:53:06.023569 DQ Delay:
6862 22:53:06.026614 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6863 22:53:06.030015 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6864 22:53:06.033327 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6865 22:53:06.036508 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6866 22:53:06.036607
6867 22:53:06.036705
6868 22:53:06.036799 ==
6869 22:53:06.040182 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 22:53:06.043624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 22:53:06.043700 ==
6872 22:53:06.043779
6873 22:53:06.043854
6874 22:53:06.046660 TX Vref Scan disable
6875 22:53:06.046734 == TX Byte 0 ==
6876 22:53:06.053166 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6877 22:53:06.056949 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6878 22:53:06.059767 == TX Byte 1 ==
6879 22:53:06.063331 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6880 22:53:06.066348 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6881 22:53:06.066449 ==
6882 22:53:06.070099 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 22:53:06.073209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 22:53:06.073308 ==
6885 22:53:06.076642
6886 22:53:06.076715
6887 22:53:06.076795 TX Vref Scan disable
6888 22:53:06.079675 == TX Byte 0 ==
6889 22:53:06.083377 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6890 22:53:06.086263 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6891 22:53:06.089825 == TX Byte 1 ==
6892 22:53:06.093354 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6893 22:53:06.096247 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6894 22:53:06.096347
6895 22:53:06.100088 [DATLAT]
6896 22:53:06.100185 Freq=400, CH1 RK1
6897 22:53:06.100284
6898 22:53:06.103309 DATLAT Default: 0xe
6899 22:53:06.103405 0, 0xFFFF, sum = 0
6900 22:53:06.106365 1, 0xFFFF, sum = 0
6901 22:53:06.106440 2, 0xFFFF, sum = 0
6902 22:53:06.109749 3, 0xFFFF, sum = 0
6903 22:53:06.109825 4, 0xFFFF, sum = 0
6904 22:53:06.113154 5, 0xFFFF, sum = 0
6905 22:53:06.113257 6, 0xFFFF, sum = 0
6906 22:53:06.116462 7, 0xFFFF, sum = 0
6907 22:53:06.116561 8, 0xFFFF, sum = 0
6908 22:53:06.119346 9, 0xFFFF, sum = 0
6909 22:53:06.119420 10, 0xFFFF, sum = 0
6910 22:53:06.122718 11, 0xFFFF, sum = 0
6911 22:53:06.126141 12, 0xFFFF, sum = 0
6912 22:53:06.126216 13, 0x0, sum = 1
6913 22:53:06.126296 14, 0x0, sum = 2
6914 22:53:06.129441 15, 0x0, sum = 3
6915 22:53:06.129543 16, 0x0, sum = 4
6916 22:53:06.132595 best_step = 14
6917 22:53:06.132668
6918 22:53:06.132750 ==
6919 22:53:06.136374 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 22:53:06.139387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 22:53:06.139458 ==
6922 22:53:06.142579 RX Vref Scan: 0
6923 22:53:06.142653
6924 22:53:06.142712 RX Vref 0 -> 0, step: 1
6925 22:53:06.142768
6926 22:53:06.146065 RX Delay -359 -> 252, step: 8
6927 22:53:06.154065 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6928 22:53:06.157840 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6929 22:53:06.160929 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6930 22:53:06.167329 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6931 22:53:06.171040 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6932 22:53:06.173833 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6933 22:53:06.177414 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6934 22:53:06.183836 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6935 22:53:06.187280 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6936 22:53:06.190467 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6937 22:53:06.193771 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6938 22:53:06.200397 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6939 22:53:06.203821 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6940 22:53:06.207088 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6941 22:53:06.210500 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6942 22:53:06.217006 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6943 22:53:06.217083 ==
6944 22:53:06.220399 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 22:53:06.223614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 22:53:06.223689 ==
6947 22:53:06.223768 DQS Delay:
6948 22:53:06.227096 DQS0 = 60, DQS1 = 64
6949 22:53:06.227170 DQM Delay:
6950 22:53:06.230366 DQM0 = 13, DQM1 = 10
6951 22:53:06.230439 DQ Delay:
6952 22:53:06.233742 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6953 22:53:06.236962 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6954 22:53:06.240473 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6955 22:53:06.243889 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6956 22:53:06.243964
6957 22:53:06.244042
6958 22:53:06.250507 [DQSOSCAuto] RK1, (LSB)MR18= 0x7eae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 393 ps
6959 22:53:06.253778 CH1 RK1: MR19=C0C, MR18=7EAE
6960 22:53:06.260121 CH1_RK1: MR19=0xC0C, MR18=0x7EAE, DQSOSC=388, MR23=63, INC=392, DEC=261
6961 22:53:06.263928 [RxdqsGatingPostProcess] freq 400
6962 22:53:06.270353 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6963 22:53:06.273932 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 22:53:06.274013 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 22:53:06.276676 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 22:53:06.280107 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 22:53:06.283466 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 22:53:06.286456 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 22:53:06.290205 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 22:53:06.293212 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 22:53:06.296930 Pre-setting of DQS Precalculation
6972 22:53:06.303149 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6973 22:53:06.309630 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6974 22:53:06.316720 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6975 22:53:06.316800
6976 22:53:06.316880
6977 22:53:06.319529 [Calibration Summary] 800 Mbps
6978 22:53:06.319608 CH 0, Rank 0
6979 22:53:06.323311 SW Impedance : PASS
6980 22:53:06.326440 DUTY Scan : NO K
6981 22:53:06.326519 ZQ Calibration : PASS
6982 22:53:06.329937 Jitter Meter : NO K
6983 22:53:06.333252 CBT Training : PASS
6984 22:53:06.333327 Write leveling : PASS
6985 22:53:06.336491 RX DQS gating : PASS
6986 22:53:06.339778 RX DQ/DQS(RDDQC) : PASS
6987 22:53:06.339883 TX DQ/DQS : PASS
6988 22:53:06.343171 RX DATLAT : PASS
6989 22:53:06.346504 RX DQ/DQS(Engine): PASS
6990 22:53:06.346605 TX OE : NO K
6991 22:53:06.346705 All Pass.
6992 22:53:06.349366
6993 22:53:06.349467 CH 0, Rank 1
6994 22:53:06.352787 SW Impedance : PASS
6995 22:53:06.352926 DUTY Scan : NO K
6996 22:53:06.356185 ZQ Calibration : PASS
6997 22:53:06.356287 Jitter Meter : NO K
6998 22:53:06.359643 CBT Training : PASS
6999 22:53:06.362619 Write leveling : NO K
7000 22:53:06.362691 RX DQS gating : PASS
7001 22:53:06.366382 RX DQ/DQS(RDDQC) : PASS
7002 22:53:06.369693 TX DQ/DQS : PASS
7003 22:53:06.369763 RX DATLAT : PASS
7004 22:53:06.373076 RX DQ/DQS(Engine): PASS
7005 22:53:06.376105 TX OE : NO K
7006 22:53:06.376208 All Pass.
7007 22:53:06.376297
7008 22:53:06.376383 CH 1, Rank 0
7009 22:53:06.379443 SW Impedance : PASS
7010 22:53:06.383232 DUTY Scan : NO K
7011 22:53:06.383308 ZQ Calibration : PASS
7012 22:53:06.386345 Jitter Meter : NO K
7013 22:53:06.389788 CBT Training : PASS
7014 22:53:06.389891 Write leveling : PASS
7015 22:53:06.392825 RX DQS gating : PASS
7016 22:53:06.396200 RX DQ/DQS(RDDQC) : PASS
7017 22:53:06.396300 TX DQ/DQS : PASS
7018 22:53:06.399628 RX DATLAT : PASS
7019 22:53:06.399727 RX DQ/DQS(Engine): PASS
7020 22:53:06.403072 TX OE : NO K
7021 22:53:06.403150 All Pass.
7022 22:53:06.403246
7023 22:53:06.406151 CH 1, Rank 1
7024 22:53:06.406252 SW Impedance : PASS
7025 22:53:06.409653 DUTY Scan : NO K
7026 22:53:06.412966 ZQ Calibration : PASS
7027 22:53:06.413065 Jitter Meter : NO K
7028 22:53:06.415996 CBT Training : PASS
7029 22:53:06.419202 Write leveling : NO K
7030 22:53:06.419313 RX DQS gating : PASS
7031 22:53:06.422535 RX DQ/DQS(RDDQC) : PASS
7032 22:53:06.426047 TX DQ/DQS : PASS
7033 22:53:06.426159 RX DATLAT : PASS
7034 22:53:06.429335 RX DQ/DQS(Engine): PASS
7035 22:53:06.433092 TX OE : NO K
7036 22:53:06.433166 All Pass.
7037 22:53:06.433265
7038 22:53:06.433360 DramC Write-DBI off
7039 22:53:06.436257 PER_BANK_REFRESH: Hybrid Mode
7040 22:53:06.439690 TX_TRACKING: ON
7041 22:53:06.446351 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7042 22:53:06.449310 [FAST_K] Save calibration result to emmc
7043 22:53:06.455760 dramc_set_vcore_voltage set vcore to 725000
7044 22:53:06.455843 Read voltage for 1600, 0
7045 22:53:06.459118 Vio18 = 0
7046 22:53:06.459221 Vcore = 725000
7047 22:53:06.459320 Vdram = 0
7048 22:53:06.462503 Vddq = 0
7049 22:53:06.462581 Vmddr = 0
7050 22:53:06.465830 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7051 22:53:06.472436 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7052 22:53:06.475844 MEM_TYPE=3, freq_sel=13
7053 22:53:06.479095 sv_algorithm_assistance_LP4_3733
7054 22:53:06.482487 ============ PULL DRAM RESETB DOWN ============
7055 22:53:06.485500 ========== PULL DRAM RESETB DOWN end =========
7056 22:53:06.492239 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7057 22:53:06.495538 ===================================
7058 22:53:06.495630 LPDDR4 DRAM CONFIGURATION
7059 22:53:06.499032 ===================================
7060 22:53:06.502026 EX_ROW_EN[0] = 0x0
7061 22:53:06.502101 EX_ROW_EN[1] = 0x0
7062 22:53:06.505443 LP4Y_EN = 0x0
7063 22:53:06.505577 WORK_FSP = 0x1
7064 22:53:06.508720 WL = 0x5
7065 22:53:06.508793 RL = 0x5
7066 22:53:06.512304 BL = 0x2
7067 22:53:06.515650 RPST = 0x0
7068 22:53:06.515724 RD_PRE = 0x0
7069 22:53:06.518841 WR_PRE = 0x1
7070 22:53:06.518917 WR_PST = 0x1
7071 22:53:06.521960 DBI_WR = 0x0
7072 22:53:06.522033 DBI_RD = 0x0
7073 22:53:06.525503 OTF = 0x1
7074 22:53:06.528822 ===================================
7075 22:53:06.532279 ===================================
7076 22:53:06.532358 ANA top config
7077 22:53:06.535314 ===================================
7078 22:53:06.538942 DLL_ASYNC_EN = 0
7079 22:53:06.542347 ALL_SLAVE_EN = 0
7080 22:53:06.542421 NEW_RANK_MODE = 1
7081 22:53:06.545772 DLL_IDLE_MODE = 1
7082 22:53:06.548489 LP45_APHY_COMB_EN = 1
7083 22:53:06.551815 TX_ODT_DIS = 0
7084 22:53:06.551895 NEW_8X_MODE = 1
7085 22:53:06.555374 ===================================
7086 22:53:06.558627 ===================================
7087 22:53:06.562076 data_rate = 3200
7088 22:53:06.565441 CKR = 1
7089 22:53:06.568736 DQ_P2S_RATIO = 8
7090 22:53:06.572171 ===================================
7091 22:53:06.575381 CA_P2S_RATIO = 8
7092 22:53:06.578693 DQ_CA_OPEN = 0
7093 22:53:06.578767 DQ_SEMI_OPEN = 0
7094 22:53:06.581621 CA_SEMI_OPEN = 0
7095 22:53:06.584991 CA_FULL_RATE = 0
7096 22:53:06.588415 DQ_CKDIV4_EN = 0
7097 22:53:06.591724 CA_CKDIV4_EN = 0
7098 22:53:06.594867 CA_PREDIV_EN = 0
7099 22:53:06.598450 PH8_DLY = 12
7100 22:53:06.598525 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7101 22:53:06.601448 DQ_AAMCK_DIV = 4
7102 22:53:06.605018 CA_AAMCK_DIV = 4
7103 22:53:06.608456 CA_ADMCK_DIV = 4
7104 22:53:06.611517 DQ_TRACK_CA_EN = 0
7105 22:53:06.615052 CA_PICK = 1600
7106 22:53:06.615127 CA_MCKIO = 1600
7107 22:53:06.618188 MCKIO_SEMI = 0
7108 22:53:06.621705 PLL_FREQ = 3068
7109 22:53:06.624827 DQ_UI_PI_RATIO = 32
7110 22:53:06.628040 CA_UI_PI_RATIO = 0
7111 22:53:06.631533 ===================================
7112 22:53:06.634625 ===================================
7113 22:53:06.638054 memory_type:LPDDR4
7114 22:53:06.638129 GP_NUM : 10
7115 22:53:06.641179 SRAM_EN : 1
7116 22:53:06.644493 MD32_EN : 0
7117 22:53:06.647742 ===================================
7118 22:53:06.647819 [ANA_INIT] >>>>>>>>>>>>>>
7119 22:53:06.651458 <<<<<< [CONFIGURE PHASE]: ANA_TX
7120 22:53:06.654601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7121 22:53:06.657989 ===================================
7122 22:53:06.660902 data_rate = 3200,PCW = 0X7600
7123 22:53:06.664315 ===================================
7124 22:53:06.667730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7125 22:53:06.674276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 22:53:06.677627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 22:53:06.684770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7128 22:53:06.687619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7129 22:53:06.690914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7130 22:53:06.691008 [ANA_INIT] flow start
7131 22:53:06.694362 [ANA_INIT] PLL >>>>>>>>
7132 22:53:06.697772 [ANA_INIT] PLL <<<<<<<<
7133 22:53:06.697853 [ANA_INIT] MIDPI >>>>>>>>
7134 22:53:06.701130 [ANA_INIT] MIDPI <<<<<<<<
7135 22:53:06.704584 [ANA_INIT] DLL >>>>>>>>
7136 22:53:06.707870 [ANA_INIT] DLL <<<<<<<<
7137 22:53:06.707962 [ANA_INIT] flow end
7138 22:53:06.710927 ============ LP4 DIFF to SE enter ============
7139 22:53:06.717734 ============ LP4 DIFF to SE exit ============
7140 22:53:06.717862 [ANA_INIT] <<<<<<<<<<<<<
7141 22:53:06.721210 [Flow] Enable top DCM control >>>>>
7142 22:53:06.724413 [Flow] Enable top DCM control <<<<<
7143 22:53:06.727504 Enable DLL master slave shuffle
7144 22:53:06.734196 ==============================================================
7145 22:53:06.734382 Gating Mode config
7146 22:53:06.741095 ==============================================================
7147 22:53:06.744668 Config description:
7148 22:53:06.751010 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7149 22:53:06.761112 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7150 22:53:06.764081 SELPH_MODE 0: By rank 1: By Phase
7151 22:53:06.771148 ==============================================================
7152 22:53:06.774131 GAT_TRACK_EN = 1
7153 22:53:06.774568 RX_GATING_MODE = 2
7154 22:53:06.777390 RX_GATING_TRACK_MODE = 2
7155 22:53:06.781086 SELPH_MODE = 1
7156 22:53:06.783915 PICG_EARLY_EN = 1
7157 22:53:06.787324 VALID_LAT_VALUE = 1
7158 22:53:06.793962 ==============================================================
7159 22:53:06.797357 Enter into Gating configuration >>>>
7160 22:53:06.800789 Exit from Gating configuration <<<<
7161 22:53:06.804085 Enter into DVFS_PRE_config >>>>>
7162 22:53:06.814214 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7163 22:53:06.817355 Exit from DVFS_PRE_config <<<<<
7164 22:53:06.820566 Enter into PICG configuration >>>>
7165 22:53:06.823823 Exit from PICG configuration <<<<
7166 22:53:06.827207 [RX_INPUT] configuration >>>>>
7167 22:53:06.830573 [RX_INPUT] configuration <<<<<
7168 22:53:06.833991 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7169 22:53:06.840204 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7170 22:53:06.846989 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 22:53:06.853495 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 22:53:06.857062 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 22:53:06.863864 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 22:53:06.867197 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7175 22:53:06.873765 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7176 22:53:06.876959 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7177 22:53:06.880047 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7178 22:53:06.884060 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7179 22:53:06.890203 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 22:53:06.893589 ===================================
7181 22:53:06.894026 LPDDR4 DRAM CONFIGURATION
7182 22:53:06.896812 ===================================
7183 22:53:06.900164 EX_ROW_EN[0] = 0x0
7184 22:53:06.903116 EX_ROW_EN[1] = 0x0
7185 22:53:06.903554 LP4Y_EN = 0x0
7186 22:53:06.906447 WORK_FSP = 0x1
7187 22:53:06.906873 WL = 0x5
7188 22:53:06.909829 RL = 0x5
7189 22:53:06.910277 BL = 0x2
7190 22:53:06.913240 RPST = 0x0
7191 22:53:06.913703 RD_PRE = 0x0
7192 22:53:06.916634 WR_PRE = 0x1
7193 22:53:06.917060 WR_PST = 0x1
7194 22:53:06.919969 DBI_WR = 0x0
7195 22:53:06.920415 DBI_RD = 0x0
7196 22:53:06.923012 OTF = 0x1
7197 22:53:06.926721 ===================================
7198 22:53:06.930054 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7199 22:53:06.933125 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7200 22:53:06.939760 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 22:53:06.943215 ===================================
7202 22:53:06.943700 LPDDR4 DRAM CONFIGURATION
7203 22:53:06.946668 ===================================
7204 22:53:06.949668 EX_ROW_EN[0] = 0x10
7205 22:53:06.953074 EX_ROW_EN[1] = 0x0
7206 22:53:06.953592 LP4Y_EN = 0x0
7207 22:53:06.956522 WORK_FSP = 0x1
7208 22:53:06.956991 WL = 0x5
7209 22:53:06.959877 RL = 0x5
7210 22:53:06.960354 BL = 0x2
7211 22:53:06.962883 RPST = 0x0
7212 22:53:06.963394 RD_PRE = 0x0
7213 22:53:06.966271 WR_PRE = 0x1
7214 22:53:06.966742 WR_PST = 0x1
7215 22:53:06.969294 DBI_WR = 0x0
7216 22:53:06.969930 DBI_RD = 0x0
7217 22:53:06.972622 OTF = 0x1
7218 22:53:06.976105 ===================================
7219 22:53:06.982412 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7220 22:53:06.982844 ==
7221 22:53:06.985847 Dram Type= 6, Freq= 0, CH_0, rank 0
7222 22:53:06.989611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7223 22:53:06.990250 ==
7224 22:53:06.992871 [Duty_Offset_Calibration]
7225 22:53:06.993322 B0:2 B1:0 CA:3
7226 22:53:06.993730
7227 22:53:06.995898 [DutyScan_Calibration_Flow] k_type=0
7228 22:53:07.007152
7229 22:53:07.007567 ==CLK 0==
7230 22:53:07.010310 Final CLK duty delay cell = 0
7231 22:53:07.013720 [0] MAX Duty = 5031%(X100), DQS PI = 12
7232 22:53:07.017069 [0] MIN Duty = 4907%(X100), DQS PI = 6
7233 22:53:07.017488 [0] AVG Duty = 4969%(X100)
7234 22:53:07.020489
7235 22:53:07.023254 CH0 CLK Duty spec in!! Max-Min= 124%
7236 22:53:07.026485 [DutyScan_Calibration_Flow] ====Done====
7237 22:53:07.026903
7238 22:53:07.030008 [DutyScan_Calibration_Flow] k_type=1
7239 22:53:07.046846
7240 22:53:07.047422 ==DQS 0 ==
7241 22:53:07.050144 Final DQS duty delay cell = 0
7242 22:53:07.053479 [0] MAX Duty = 5094%(X100), DQS PI = 28
7243 22:53:07.056585 [0] MIN Duty = 4875%(X100), DQS PI = 48
7244 22:53:07.060112 [0] AVG Duty = 4984%(X100)
7245 22:53:07.060607
7246 22:53:07.061093 ==DQS 1 ==
7247 22:53:07.063296 Final DQS duty delay cell = 0
7248 22:53:07.066727 [0] MAX Duty = 5156%(X100), DQS PI = 34
7249 22:53:07.070011 [0] MIN Duty = 5031%(X100), DQS PI = 12
7250 22:53:07.073458 [0] AVG Duty = 5093%(X100)
7251 22:53:07.074047
7252 22:53:07.076984 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7253 22:53:07.077483
7254 22:53:07.079837 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7255 22:53:07.083396 [DutyScan_Calibration_Flow] ====Done====
7256 22:53:07.083892
7257 22:53:07.086506 [DutyScan_Calibration_Flow] k_type=3
7258 22:53:07.104927
7259 22:53:07.105437 ==DQM 0 ==
7260 22:53:07.108430 Final DQM duty delay cell = 0
7261 22:53:07.111253 [0] MAX Duty = 5156%(X100), DQS PI = 30
7262 22:53:07.114649 [0] MIN Duty = 4875%(X100), DQS PI = 0
7263 22:53:07.118342 [0] AVG Duty = 5015%(X100)
7264 22:53:07.118827
7265 22:53:07.119337 ==DQM 1 ==
7266 22:53:07.121484 Final DQM duty delay cell = 4
7267 22:53:07.124929 [4] MAX Duty = 5156%(X100), DQS PI = 0
7268 22:53:07.128303 [4] MIN Duty = 5000%(X100), DQS PI = 38
7269 22:53:07.131325 [4] AVG Duty = 5078%(X100)
7270 22:53:07.131816
7271 22:53:07.134708 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7272 22:53:07.135203
7273 22:53:07.137800 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7274 22:53:07.141632 [DutyScan_Calibration_Flow] ====Done====
7275 22:53:07.142123
7276 22:53:07.144395 [DutyScan_Calibration_Flow] k_type=2
7277 22:53:07.161201
7278 22:53:07.161659 ==DQ 0 ==
7279 22:53:07.164161 Final DQ duty delay cell = -4
7280 22:53:07.167800 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7281 22:53:07.171066 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7282 22:53:07.174325 [-4] AVG Duty = 4953%(X100)
7283 22:53:07.174775
7284 22:53:07.175224 ==DQ 1 ==
7285 22:53:07.177539 Final DQ duty delay cell = 0
7286 22:53:07.181080 [0] MAX Duty = 5156%(X100), DQS PI = 60
7287 22:53:07.184087 [0] MIN Duty = 5000%(X100), DQS PI = 16
7288 22:53:07.187593 [0] AVG Duty = 5078%(X100)
7289 22:53:07.188036
7290 22:53:07.190805 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7291 22:53:07.191256
7292 22:53:07.194037 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7293 22:53:07.197473 [DutyScan_Calibration_Flow] ====Done====
7294 22:53:07.198032 ==
7295 22:53:07.200357 Dram Type= 6, Freq= 0, CH_1, rank 0
7296 22:53:07.203883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 22:53:07.204406 ==
7298 22:53:07.207141 [Duty_Offset_Calibration]
7299 22:53:07.207508 B0:1 B1:-2 CA:1
7300 22:53:07.207831
7301 22:53:07.210526 [DutyScan_Calibration_Flow] k_type=0
7302 22:53:07.221261
7303 22:53:07.221489 ==CLK 0==
7304 22:53:07.224722 Final CLK duty delay cell = 0
7305 22:53:07.227954 [0] MAX Duty = 5062%(X100), DQS PI = 20
7306 22:53:07.231429 [0] MIN Duty = 4844%(X100), DQS PI = 4
7307 22:53:07.231614 [0] AVG Duty = 4953%(X100)
7308 22:53:07.234854
7309 22:53:07.235031 CH1 CLK Duty spec in!! Max-Min= 218%
7310 22:53:07.241637 [DutyScan_Calibration_Flow] ====Done====
7311 22:53:07.241824
7312 22:53:07.244642 [DutyScan_Calibration_Flow] k_type=1
7313 22:53:07.260393
7314 22:53:07.260628 ==DQS 0 ==
7315 22:53:07.263655 Final DQS duty delay cell = -4
7316 22:53:07.266985 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7317 22:53:07.270404 [-4] MIN Duty = 4813%(X100), DQS PI = 46
7318 22:53:07.274200 [-4] AVG Duty = 4891%(X100)
7319 22:53:07.274576
7320 22:53:07.274931 ==DQS 1 ==
7321 22:53:07.276925 Final DQS duty delay cell = 0
7322 22:53:07.280164 [0] MAX Duty = 5093%(X100), DQS PI = 60
7323 22:53:07.283675 [0] MIN Duty = 4844%(X100), DQS PI = 24
7324 22:53:07.287153 [0] AVG Duty = 4968%(X100)
7325 22:53:07.287566
7326 22:53:07.290461 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7327 22:53:07.290875
7328 22:53:07.293847 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7329 22:53:07.297091 [DutyScan_Calibration_Flow] ====Done====
7330 22:53:07.297503
7331 22:53:07.300369 [DutyScan_Calibration_Flow] k_type=3
7332 22:53:07.317675
7333 22:53:07.318129 ==DQM 0 ==
7334 22:53:07.321251 Final DQM duty delay cell = 0
7335 22:53:07.324559 [0] MAX Duty = 5031%(X100), DQS PI = 24
7336 22:53:07.327812 [0] MIN Duty = 4813%(X100), DQS PI = 54
7337 22:53:07.331137 [0] AVG Duty = 4922%(X100)
7338 22:53:07.331595
7339 22:53:07.331953 ==DQM 1 ==
7340 22:53:07.334253 Final DQM duty delay cell = 0
7341 22:53:07.337699 [0] MAX Duty = 5094%(X100), DQS PI = 36
7342 22:53:07.340947 [0] MIN Duty = 4875%(X100), DQS PI = 24
7343 22:53:07.344364 [0] AVG Duty = 4984%(X100)
7344 22:53:07.344778
7345 22:53:07.347819 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7346 22:53:07.348273
7347 22:53:07.350776 CH1 DQM 1 Duty spec in!! Max-Min= 219%
7348 22:53:07.354186 [DutyScan_Calibration_Flow] ====Done====
7349 22:53:07.354597
7350 22:53:07.357680 [DutyScan_Calibration_Flow] k_type=2
7351 22:53:07.374775
7352 22:53:07.375188 ==DQ 0 ==
7353 22:53:07.377925 Final DQ duty delay cell = 0
7354 22:53:07.381283 [0] MAX Duty = 5093%(X100), DQS PI = 20
7355 22:53:07.384713 [0] MIN Duty = 4907%(X100), DQS PI = 62
7356 22:53:07.388101 [0] AVG Duty = 5000%(X100)
7357 22:53:07.388516
7358 22:53:07.388841 ==DQ 1 ==
7359 22:53:07.391029 Final DQ duty delay cell = 0
7360 22:53:07.394419 [0] MAX Duty = 5156%(X100), DQS PI = 36
7361 22:53:07.397865 [0] MIN Duty = 4969%(X100), DQS PI = 24
7362 22:53:07.401159 [0] AVG Duty = 5062%(X100)
7363 22:53:07.401657
7364 22:53:07.404303 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7365 22:53:07.404717
7366 22:53:07.407604 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7367 22:53:07.410879 [DutyScan_Calibration_Flow] ====Done====
7368 22:53:07.414115 nWR fixed to 30
7369 22:53:07.414553 [ModeRegInit_LP4] CH0 RK0
7370 22:53:07.417708 [ModeRegInit_LP4] CH0 RK1
7371 22:53:07.421060 [ModeRegInit_LP4] CH1 RK0
7372 22:53:07.424322 [ModeRegInit_LP4] CH1 RK1
7373 22:53:07.424767 match AC timing 5
7374 22:53:07.431310 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7375 22:53:07.434295 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7376 22:53:07.437506 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7377 22:53:07.444329 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7378 22:53:07.447448 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7379 22:53:07.447894 [MiockJmeterHQA]
7380 22:53:07.448255
7381 22:53:07.450909 [DramcMiockJmeter] u1RxGatingPI = 0
7382 22:53:07.454059 0 : 4258, 4029
7383 22:53:07.454503 4 : 4252, 4027
7384 22:53:07.457615 8 : 4365, 4140
7385 22:53:07.458047 12 : 4253, 4026
7386 22:53:07.458399 16 : 4252, 4027
7387 22:53:07.461038 20 : 4363, 4137
7388 22:53:07.461476 24 : 4252, 4027
7389 22:53:07.463930 28 : 4253, 4027
7390 22:53:07.464358 32 : 4253, 4026
7391 22:53:07.467367 36 : 4255, 4029
7392 22:53:07.467810 40 : 4253, 4027
7393 22:53:07.471009 44 : 4252, 4027
7394 22:53:07.471427 48 : 4366, 4140
7395 22:53:07.471781 52 : 4254, 4029
7396 22:53:07.473827 56 : 4255, 4029
7397 22:53:07.474278 60 : 4252, 4027
7398 22:53:07.477387 64 : 4363, 4140
7399 22:53:07.477939 68 : 4250, 4027
7400 22:53:07.480701 72 : 4361, 4138
7401 22:53:07.481126 76 : 4250, 4027
7402 22:53:07.484052 80 : 4250, 4026
7403 22:53:07.484691 84 : 4250, 4027
7404 22:53:07.485260 88 : 4252, 4029
7405 22:53:07.487246 92 : 4249, 4027
7406 22:53:07.487848 96 : 4250, 4027
7407 22:53:07.490747 100 : 4363, 4140
7408 22:53:07.491348 104 : 4361, 3677
7409 22:53:07.494153 108 : 4250, 0
7410 22:53:07.494678 112 : 4250, 0
7411 22:53:07.495189 116 : 4250, 0
7412 22:53:07.496984 120 : 4361, 0
7413 22:53:07.497569 124 : 4250, 0
7414 22:53:07.500583 128 : 4250, 0
7415 22:53:07.501039 132 : 4360, 0
7416 22:53:07.501615 136 : 4361, 0
7417 22:53:07.503817 140 : 4250, 0
7418 22:53:07.504402 144 : 4250, 0
7419 22:53:07.506986 148 : 4250, 0
7420 22:53:07.507436 152 : 4250, 0
7421 22:53:07.507897 156 : 4252, 0
7422 22:53:07.510276 160 : 4250, 0
7423 22:53:07.510727 164 : 4250, 0
7424 22:53:07.513622 168 : 4252, 0
7425 22:53:07.514075 172 : 4250, 0
7426 22:53:07.514526 176 : 4250, 0
7427 22:53:07.516855 180 : 4252, 0
7428 22:53:07.517302 184 : 4360, 0
7429 22:53:07.517815 188 : 4361, 0
7430 22:53:07.520261 192 : 4363, 0
7431 22:53:07.520710 196 : 4250, 0
7432 22:53:07.523423 200 : 4250, 0
7433 22:53:07.523861 204 : 4250, 0
7434 22:53:07.524321 208 : 4252, 0
7435 22:53:07.526849 212 : 4250, 0
7436 22:53:07.527311 216 : 4250, 0
7437 22:53:07.530124 220 : 4252, 0
7438 22:53:07.530579 224 : 4361, 0
7439 22:53:07.531033 228 : 4250, 0
7440 22:53:07.533211 232 : 4250, 0
7441 22:53:07.533773 236 : 4360, 1206
7442 22:53:07.536318 240 : 4250, 4027
7443 22:53:07.536630 244 : 4250, 4027
7444 22:53:07.540259 248 : 4361, 4137
7445 22:53:07.540579 252 : 4361, 4138
7446 22:53:07.543051 256 : 4250, 4027
7447 22:53:07.543371 260 : 4363, 4140
7448 22:53:07.546605 264 : 4250, 4027
7449 22:53:07.546914 268 : 4250, 4027
7450 22:53:07.547230 272 : 4250, 4027
7451 22:53:07.549822 276 : 4252, 4029
7452 22:53:07.550130 280 : 4250, 4027
7453 22:53:07.553273 284 : 4250, 4027
7454 22:53:07.553695 288 : 4250, 4027
7455 22:53:07.556665 292 : 4253, 4029
7456 22:53:07.556973 296 : 4250, 4027
7457 22:53:07.559883 300 : 4360, 4137
7458 22:53:07.560254 304 : 4361, 4137
7459 22:53:07.563051 308 : 4250, 4027
7460 22:53:07.563381 312 : 4363, 4140
7461 22:53:07.566432 316 : 4250, 4027
7462 22:53:07.566743 320 : 4250, 4026
7463 22:53:07.569884 324 : 4250, 4027
7464 22:53:07.570322 328 : 4252, 4029
7465 22:53:07.570732 332 : 4250, 4027
7466 22:53:07.573123 336 : 4250, 4027
7467 22:53:07.573496 340 : 4250, 4027
7468 22:53:07.576291 344 : 4252, 4030
7469 22:53:07.576618 348 : 4250, 4027
7470 22:53:07.579627 352 : 4361, 4127
7471 22:53:07.579973 356 : 4361, 2750
7472 22:53:07.582957 360 : 4250, 1
7473 22:53:07.583274
7474 22:53:07.583583 MIOCK jitter meter ch=0
7475 22:53:07.583883
7476 22:53:07.586905 1T = (360-108) = 252 dly cells
7477 22:53:07.592882 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7478 22:53:07.593189 ==
7479 22:53:07.596280 Dram Type= 6, Freq= 0, CH_0, rank 0
7480 22:53:07.599663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7481 22:53:07.600002 ==
7482 22:53:07.606352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7483 22:53:07.609333 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7484 22:53:07.616411 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7485 22:53:07.619623 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7486 22:53:07.629331 [CA 0] Center 43 (13~74) winsize 62
7487 22:53:07.632981 [CA 1] Center 43 (13~74) winsize 62
7488 22:53:07.636189 [CA 2] Center 39 (10~68) winsize 59
7489 22:53:07.639648 [CA 3] Center 39 (10~68) winsize 59
7490 22:53:07.642850 [CA 4] Center 36 (7~66) winsize 60
7491 22:53:07.646319 [CA 5] Center 36 (7~66) winsize 60
7492 22:53:07.646753
7493 22:53:07.649644 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7494 22:53:07.650003
7495 22:53:07.655899 [CATrainingPosCal] consider 1 rank data
7496 22:53:07.656251 u2DelayCellTimex100 = 258/100 ps
7497 22:53:07.662601 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7498 22:53:07.665932 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7499 22:53:07.669087 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7500 22:53:07.672693 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7501 22:53:07.675855 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7502 22:53:07.679223 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7503 22:53:07.679555
7504 22:53:07.682788 CA PerBit enable=1, Macro0, CA PI delay=36
7505 22:53:07.683142
7506 22:53:07.685541 [CBTSetCACLKResult] CA Dly = 36
7507 22:53:07.689296 CS Dly: 11 (0~42)
7508 22:53:07.692774 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7509 22:53:07.695264 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7510 22:53:07.695680 ==
7511 22:53:07.699242 Dram Type= 6, Freq= 0, CH_0, rank 1
7512 22:53:07.705697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7513 22:53:07.706028 ==
7514 22:53:07.709077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7515 22:53:07.715575 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7516 22:53:07.719016 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7517 22:53:07.725365 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7518 22:53:07.733242 [CA 0] Center 43 (13~74) winsize 62
7519 22:53:07.736677 [CA 1] Center 43 (13~74) winsize 62
7520 22:53:07.739895 [CA 2] Center 39 (10~68) winsize 59
7521 22:53:07.743265 [CA 3] Center 39 (10~68) winsize 59
7522 22:53:07.746940 [CA 4] Center 36 (6~66) winsize 61
7523 22:53:07.750224 [CA 5] Center 36 (6~66) winsize 61
7524 22:53:07.750544
7525 22:53:07.753502 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7526 22:53:07.753833
7527 22:53:07.756900 [CATrainingPosCal] consider 2 rank data
7528 22:53:07.760321 u2DelayCellTimex100 = 258/100 ps
7529 22:53:07.766590 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7530 22:53:07.769848 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7531 22:53:07.773229 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7532 22:53:07.777109 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7533 22:53:07.780154 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7534 22:53:07.783159 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7535 22:53:07.783574
7536 22:53:07.786489 CA PerBit enable=1, Macro0, CA PI delay=36
7537 22:53:07.786904
7538 22:53:07.789800 [CBTSetCACLKResult] CA Dly = 36
7539 22:53:07.793208 CS Dly: 11 (0~43)
7540 22:53:07.796177 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7541 22:53:07.800003 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7542 22:53:07.800467
7543 22:53:07.803207 ----->DramcWriteLeveling(PI) begin...
7544 22:53:07.803629 ==
7545 22:53:07.806496 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 22:53:07.813200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 22:53:07.813659 ==
7548 22:53:07.816667 Write leveling (Byte 0): 35 => 35
7549 22:53:07.820051 Write leveling (Byte 1): 27 => 27
7550 22:53:07.822864 DramcWriteLeveling(PI) end<-----
7551 22:53:07.823264
7552 22:53:07.823690 ==
7553 22:53:07.826472 Dram Type= 6, Freq= 0, CH_0, rank 0
7554 22:53:07.829661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 22:53:07.830114 ==
7556 22:53:07.832989 [Gating] SW mode calibration
7557 22:53:07.839556 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7558 22:53:07.843236 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7559 22:53:07.849199 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 22:53:07.852929 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 22:53:07.855922 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 22:53:07.863119 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 22:53:07.866689 1 4 16 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
7564 22:53:07.869193 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7565 22:53:07.876083 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7566 22:53:07.879466 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 22:53:07.882295 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 22:53:07.889067 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 22:53:07.892698 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7570 22:53:07.895474 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 22:53:07.902609 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7572 22:53:07.905675 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7573 22:53:07.909063 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
7574 22:53:07.915915 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 22:53:07.919115 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 22:53:07.922047 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 22:53:07.928687 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 22:53:07.931829 1 6 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7579 22:53:07.935245 1 6 16 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7580 22:53:07.941922 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7581 22:53:07.945070 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7582 22:53:07.948857 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 22:53:07.955160 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 22:53:07.958409 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 22:53:07.962156 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 22:53:07.968560 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7587 22:53:07.971699 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7588 22:53:07.975449 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7589 22:53:07.982004 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7590 22:53:07.985031 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7591 22:53:07.988482 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 22:53:07.995216 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 22:53:07.998668 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 22:53:08.001831 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 22:53:08.008313 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 22:53:08.011451 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 22:53:08.014957 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 22:53:08.021333 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 22:53:08.024595 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 22:53:08.028036 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 22:53:08.034676 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 22:53:08.037969 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 22:53:08.041324 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7604 22:53:08.047965 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7605 22:53:08.048385 Total UI for P1: 0, mck2ui 16
7606 22:53:08.055141 best dqsien dly found for B0: ( 1, 9, 16)
7607 22:53:08.057848 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7608 22:53:08.061584 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7609 22:53:08.068202 1 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 22:53:08.068799 Total UI for P1: 0, mck2ui 16
7611 22:53:08.071358 best dqsien dly found for B1: ( 1, 9, 24)
7612 22:53:08.078056 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7613 22:53:08.081082 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7614 22:53:08.081617
7615 22:53:08.084507 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7616 22:53:08.088192 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7617 22:53:08.090860 [Gating] SW calibration Done
7618 22:53:08.091286 ==
7619 22:53:08.094565 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 22:53:08.097458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 22:53:08.097915 ==
7622 22:53:08.100945 RX Vref Scan: 0
7623 22:53:08.101458
7624 22:53:08.101873 RX Vref 0 -> 0, step: 1
7625 22:53:08.102217
7626 22:53:08.104442 RX Delay 0 -> 252, step: 8
7627 22:53:08.107630 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7628 22:53:08.113978 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7629 22:53:08.117607 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7630 22:53:08.121082 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7631 22:53:08.124256 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7632 22:53:08.127599 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7633 22:53:08.133774 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7634 22:53:08.137155 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7635 22:53:08.140491 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7636 22:53:08.144134 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7637 22:53:08.147650 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7638 22:53:08.154148 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7639 22:53:08.157397 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7640 22:53:08.160495 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7641 22:53:08.163569 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7642 22:53:08.170110 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7643 22:53:08.170727 ==
7644 22:53:08.173587 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 22:53:08.177249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 22:53:08.177897 ==
7647 22:53:08.178449 DQS Delay:
7648 22:53:08.180234 DQS0 = 0, DQS1 = 0
7649 22:53:08.180749 DQM Delay:
7650 22:53:08.183783 DQM0 = 128, DQM1 = 123
7651 22:53:08.184369 DQ Delay:
7652 22:53:08.187097 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7653 22:53:08.190051 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7654 22:53:08.193455 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7655 22:53:08.196717 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7656 22:53:08.197296
7657 22:53:08.197808
7658 22:53:08.199780 ==
7659 22:53:08.203668 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 22:53:08.206558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 22:53:08.206999 ==
7662 22:53:08.207575
7663 22:53:08.207915
7664 22:53:08.209948 TX Vref Scan disable
7665 22:53:08.210033 == TX Byte 0 ==
7666 22:53:08.212677 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7667 22:53:08.220187 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7668 22:53:08.220270 == TX Byte 1 ==
7669 22:53:08.226054 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7670 22:53:08.229336 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7671 22:53:08.229443 ==
7672 22:53:08.232653 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 22:53:08.235880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 22:53:08.235981 ==
7675 22:53:08.251451
7676 22:53:08.254826 TX Vref early break, caculate TX vref
7677 22:53:08.257980 TX Vref=16, minBit 8, minWin=21, winSum=355
7678 22:53:08.261276 TX Vref=18, minBit 4, minWin=22, winSum=366
7679 22:53:08.264779 TX Vref=20, minBit 8, minWin=22, winSum=376
7680 22:53:08.268314 TX Vref=22, minBit 8, minWin=23, winSum=384
7681 22:53:08.271265 TX Vref=24, minBit 8, minWin=23, winSum=397
7682 22:53:08.277846 TX Vref=26, minBit 4, minWin=24, winSum=402
7683 22:53:08.281351 TX Vref=28, minBit 4, minWin=24, winSum=402
7684 22:53:08.284600 TX Vref=30, minBit 4, minWin=24, winSum=397
7685 22:53:08.288082 TX Vref=32, minBit 9, minWin=22, winSum=387
7686 22:53:08.291243 TX Vref=34, minBit 8, minWin=22, winSum=381
7687 22:53:08.294521 TX Vref=36, minBit 8, minWin=21, winSum=369
7688 22:53:08.301227 [TxChooseVref] Worse bit 4, Min win 24, Win sum 402, Final Vref 26
7689 22:53:08.301307
7690 22:53:08.304343 Final TX Range 0 Vref 26
7691 22:53:08.304420
7692 22:53:08.304503 ==
7693 22:53:08.307703 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 22:53:08.311014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 22:53:08.311105 ==
7696 22:53:08.311197
7697 22:53:08.314363
7698 22:53:08.314454 TX Vref Scan disable
7699 22:53:08.320971 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7700 22:53:08.321075 == TX Byte 0 ==
7701 22:53:08.324716 u2DelayCellOfst[0]=15 cells (4 PI)
7702 22:53:08.327643 u2DelayCellOfst[1]=18 cells (5 PI)
7703 22:53:08.330991 u2DelayCellOfst[2]=11 cells (3 PI)
7704 22:53:08.334336 u2DelayCellOfst[3]=15 cells (4 PI)
7705 22:53:08.337622 u2DelayCellOfst[4]=7 cells (2 PI)
7706 22:53:08.341204 u2DelayCellOfst[5]=0 cells (0 PI)
7707 22:53:08.344225 u2DelayCellOfst[6]=22 cells (6 PI)
7708 22:53:08.347582 u2DelayCellOfst[7]=18 cells (5 PI)
7709 22:53:08.350840 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7710 22:53:08.354140 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7711 22:53:08.357544 == TX Byte 1 ==
7712 22:53:08.360685 u2DelayCellOfst[8]=0 cells (0 PI)
7713 22:53:08.364065 u2DelayCellOfst[9]=3 cells (1 PI)
7714 22:53:08.367728 u2DelayCellOfst[10]=11 cells (3 PI)
7715 22:53:08.368120 u2DelayCellOfst[11]=7 cells (2 PI)
7716 22:53:08.371073 u2DelayCellOfst[12]=15 cells (4 PI)
7717 22:53:08.374567 u2DelayCellOfst[13]=15 cells (4 PI)
7718 22:53:08.377619 u2DelayCellOfst[14]=18 cells (5 PI)
7719 22:53:08.380892 u2DelayCellOfst[15]=15 cells (4 PI)
7720 22:53:08.387666 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7721 22:53:08.390757 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7722 22:53:08.391198 DramC Write-DBI on
7723 22:53:08.394273 ==
7724 22:53:08.394710 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 22:53:08.400693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 22:53:08.401317 ==
7727 22:53:08.401889
7728 22:53:08.402416
7729 22:53:08.404063 TX Vref Scan disable
7730 22:53:08.404634 == TX Byte 0 ==
7731 22:53:08.410791 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7732 22:53:08.411325 == TX Byte 1 ==
7733 22:53:08.414195 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7734 22:53:08.417323 DramC Write-DBI off
7735 22:53:08.417893
7736 22:53:08.418324 [DATLAT]
7737 22:53:08.420435 Freq=1600, CH0 RK0
7738 22:53:08.420959
7739 22:53:08.421493 DATLAT Default: 0xf
7740 22:53:08.424065 0, 0xFFFF, sum = 0
7741 22:53:08.424590 1, 0xFFFF, sum = 0
7742 22:53:08.427017 2, 0xFFFF, sum = 0
7743 22:53:08.427514 3, 0xFFFF, sum = 0
7744 22:53:08.430400 4, 0xFFFF, sum = 0
7745 22:53:08.430951 5, 0xFFFF, sum = 0
7746 22:53:08.433749 6, 0xFFFF, sum = 0
7747 22:53:08.434254 7, 0xFFFF, sum = 0
7748 22:53:08.437472 8, 0xFFFF, sum = 0
7749 22:53:08.440757 9, 0xFFFF, sum = 0
7750 22:53:08.441306 10, 0xFFFF, sum = 0
7751 22:53:08.443548 11, 0xFFFF, sum = 0
7752 22:53:08.444090 12, 0xFFFF, sum = 0
7753 22:53:08.447025 13, 0xEFFF, sum = 0
7754 22:53:08.447519 14, 0x0, sum = 1
7755 22:53:08.450234 15, 0x0, sum = 2
7756 22:53:08.450708 16, 0x0, sum = 3
7757 22:53:08.454098 17, 0x0, sum = 4
7758 22:53:08.454588 best_step = 15
7759 22:53:08.454994
7760 22:53:08.455390 ==
7761 22:53:08.457699 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 22:53:08.460750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 22:53:08.461224 ==
7764 22:53:08.463692 RX Vref Scan: 1
7765 22:53:08.464246
7766 22:53:08.467149 Set Vref Range= 24 -> 127
7767 22:53:08.467689
7768 22:53:08.468246 RX Vref 24 -> 127, step: 1
7769 22:53:08.468759
7770 22:53:08.470450 RX Delay 11 -> 252, step: 4
7771 22:53:08.470966
7772 22:53:08.473707 Set Vref, RX VrefLevel [Byte0]: 24
7773 22:53:08.477096 [Byte1]: 24
7774 22:53:08.480206
7775 22:53:08.480822 Set Vref, RX VrefLevel [Byte0]: 25
7776 22:53:08.483752 [Byte1]: 25
7777 22:53:08.488313
7778 22:53:08.488835 Set Vref, RX VrefLevel [Byte0]: 26
7779 22:53:08.491251 [Byte1]: 26
7780 22:53:08.495303
7781 22:53:08.495799 Set Vref, RX VrefLevel [Byte0]: 27
7782 22:53:08.499034 [Byte1]: 27
7783 22:53:08.502972
7784 22:53:08.503450 Set Vref, RX VrefLevel [Byte0]: 28
7785 22:53:08.506716 [Byte1]: 28
7786 22:53:08.510631
7787 22:53:08.511174 Set Vref, RX VrefLevel [Byte0]: 29
7788 22:53:08.514082 [Byte1]: 29
7789 22:53:08.518677
7790 22:53:08.519129 Set Vref, RX VrefLevel [Byte0]: 30
7791 22:53:08.522006 [Byte1]: 30
7792 22:53:08.526144
7793 22:53:08.526643 Set Vref, RX VrefLevel [Byte0]: 31
7794 22:53:08.529297 [Byte1]: 31
7795 22:53:08.533821
7796 22:53:08.534245 Set Vref, RX VrefLevel [Byte0]: 32
7797 22:53:08.537178 [Byte1]: 32
7798 22:53:08.541186
7799 22:53:08.541722 Set Vref, RX VrefLevel [Byte0]: 33
7800 22:53:08.544429 [Byte1]: 33
7801 22:53:08.549069
7802 22:53:08.549490 Set Vref, RX VrefLevel [Byte0]: 34
7803 22:53:08.552442 [Byte1]: 34
7804 22:53:08.556746
7805 22:53:08.557160 Set Vref, RX VrefLevel [Byte0]: 35
7806 22:53:08.559930 [Byte1]: 35
7807 22:53:08.564387
7808 22:53:08.564936 Set Vref, RX VrefLevel [Byte0]: 36
7809 22:53:08.567535 [Byte1]: 36
7810 22:53:08.571566
7811 22:53:08.571991 Set Vref, RX VrefLevel [Byte0]: 37
7812 22:53:08.574922 [Byte1]: 37
7813 22:53:08.579315
7814 22:53:08.579735 Set Vref, RX VrefLevel [Byte0]: 38
7815 22:53:08.582409 [Byte1]: 38
7816 22:53:08.586984
7817 22:53:08.587485 Set Vref, RX VrefLevel [Byte0]: 39
7818 22:53:08.590035 [Byte1]: 39
7819 22:53:08.594342
7820 22:53:08.594830 Set Vref, RX VrefLevel [Byte0]: 40
7821 22:53:08.597973 [Byte1]: 40
7822 22:53:08.602078
7823 22:53:08.602560 Set Vref, RX VrefLevel [Byte0]: 41
7824 22:53:08.605669 [Byte1]: 41
7825 22:53:08.610099
7826 22:53:08.610554 Set Vref, RX VrefLevel [Byte0]: 42
7827 22:53:08.613237 [Byte1]: 42
7828 22:53:08.617590
7829 22:53:08.618033 Set Vref, RX VrefLevel [Byte0]: 43
7830 22:53:08.620526 [Byte1]: 43
7831 22:53:08.625540
7832 22:53:08.626111 Set Vref, RX VrefLevel [Byte0]: 44
7833 22:53:08.628188 [Byte1]: 44
7834 22:53:08.632556
7835 22:53:08.632992 Set Vref, RX VrefLevel [Byte0]: 45
7836 22:53:08.636047 [Byte1]: 45
7837 22:53:08.639979
7838 22:53:08.640418 Set Vref, RX VrefLevel [Byte0]: 46
7839 22:53:08.643503 [Byte1]: 46
7840 22:53:08.647780
7841 22:53:08.648232 Set Vref, RX VrefLevel [Byte0]: 47
7842 22:53:08.651336 [Byte1]: 47
7843 22:53:08.655873
7844 22:53:08.656356 Set Vref, RX VrefLevel [Byte0]: 48
7845 22:53:08.659052 [Byte1]: 48
7846 22:53:08.663240
7847 22:53:08.663672 Set Vref, RX VrefLevel [Byte0]: 49
7848 22:53:08.666780 [Byte1]: 49
7849 22:53:08.670601
7850 22:53:08.671084 Set Vref, RX VrefLevel [Byte0]: 50
7851 22:53:08.673930 [Byte1]: 50
7852 22:53:08.678251
7853 22:53:08.678673 Set Vref, RX VrefLevel [Byte0]: 51
7854 22:53:08.681561 [Byte1]: 51
7855 22:53:08.686016
7856 22:53:08.686508 Set Vref, RX VrefLevel [Byte0]: 52
7857 22:53:08.689555 [Byte1]: 52
7858 22:53:08.693952
7859 22:53:08.694387 Set Vref, RX VrefLevel [Byte0]: 53
7860 22:53:08.696437 [Byte1]: 53
7861 22:53:08.700779
7862 22:53:08.700860 Set Vref, RX VrefLevel [Byte0]: 54
7863 22:53:08.704188 [Byte1]: 54
7864 22:53:08.708649
7865 22:53:08.708735 Set Vref, RX VrefLevel [Byte0]: 55
7866 22:53:08.712040 [Byte1]: 55
7867 22:53:08.716129
7868 22:53:08.716205 Set Vref, RX VrefLevel [Byte0]: 56
7869 22:53:08.719142 [Byte1]: 56
7870 22:53:08.723442
7871 22:53:08.723539 Set Vref, RX VrefLevel [Byte0]: 57
7872 22:53:08.726986 [Byte1]: 57
7873 22:53:08.730968
7874 22:53:08.731039 Set Vref, RX VrefLevel [Byte0]: 58
7875 22:53:08.734761 [Byte1]: 58
7876 22:53:08.738857
7877 22:53:08.738936 Set Vref, RX VrefLevel [Byte0]: 59
7878 22:53:08.742256 [Byte1]: 59
7879 22:53:08.746287
7880 22:53:08.746388 Set Vref, RX VrefLevel [Byte0]: 60
7881 22:53:08.749635 [Byte1]: 60
7882 22:53:08.754024
7883 22:53:08.754094 Set Vref, RX VrefLevel [Byte0]: 61
7884 22:53:08.757052 [Byte1]: 61
7885 22:53:08.761752
7886 22:53:08.761825 Set Vref, RX VrefLevel [Byte0]: 62
7887 22:53:08.765136 [Byte1]: 62
7888 22:53:08.769056
7889 22:53:08.769154 Set Vref, RX VrefLevel [Byte0]: 63
7890 22:53:08.772859 [Byte1]: 63
7891 22:53:08.776714
7892 22:53:08.776784 Set Vref, RX VrefLevel [Byte0]: 64
7893 22:53:08.780160 [Byte1]: 64
7894 22:53:08.784716
7895 22:53:08.784786 Set Vref, RX VrefLevel [Byte0]: 65
7896 22:53:08.788016 [Byte1]: 65
7897 22:53:08.792451
7898 22:53:08.792526 Set Vref, RX VrefLevel [Byte0]: 66
7899 22:53:08.795156 [Byte1]: 66
7900 22:53:08.799714
7901 22:53:08.799812 Set Vref, RX VrefLevel [Byte0]: 67
7902 22:53:08.802923 [Byte1]: 67
7903 22:53:08.807113
7904 22:53:08.807230 Set Vref, RX VrefLevel [Byte0]: 68
7905 22:53:08.810657 [Byte1]: 68
7906 22:53:08.814990
7907 22:53:08.815134 Set Vref, RX VrefLevel [Byte0]: 69
7908 22:53:08.818736 [Byte1]: 69
7909 22:53:08.822738
7910 22:53:08.822871 Set Vref, RX VrefLevel [Byte0]: 70
7911 22:53:08.826112 [Byte1]: 70
7912 22:53:08.830191
7913 22:53:08.830375 Set Vref, RX VrefLevel [Byte0]: 71
7914 22:53:08.833632 [Byte1]: 71
7915 22:53:08.837919
7916 22:53:08.838136 Set Vref, RX VrefLevel [Byte0]: 72
7917 22:53:08.841134 [Byte1]: 72
7918 22:53:08.845761
7919 22:53:08.846101 Set Vref, RX VrefLevel [Byte0]: 73
7920 22:53:08.849422 [Byte1]: 73
7921 22:53:08.853192
7922 22:53:08.853700 Set Vref, RX VrefLevel [Byte0]: 74
7923 22:53:08.856391 [Byte1]: 74
7924 22:53:08.860794
7925 22:53:08.861220 Set Vref, RX VrefLevel [Byte0]: 75
7926 22:53:08.864613 [Byte1]: 75
7927 22:53:08.868394
7928 22:53:08.868839 Set Vref, RX VrefLevel [Byte0]: 76
7929 22:53:08.871633 [Byte1]: 76
7930 22:53:08.876160
7931 22:53:08.876601 Final RX Vref Byte 0 = 63 to rank0
7932 22:53:08.879503 Final RX Vref Byte 1 = 60 to rank0
7933 22:53:08.882931 Final RX Vref Byte 0 = 63 to rank1
7934 22:53:08.885861 Final RX Vref Byte 1 = 60 to rank1==
7935 22:53:08.889052 Dram Type= 6, Freq= 0, CH_0, rank 0
7936 22:53:08.895914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7937 22:53:08.896359 ==
7938 22:53:08.896711 DQS Delay:
7939 22:53:08.899251 DQS0 = 0, DQS1 = 0
7940 22:53:08.899729 DQM Delay:
7941 22:53:08.902631 DQM0 = 126, DQM1 = 119
7942 22:53:08.903229 DQ Delay:
7943 22:53:08.905954 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7944 22:53:08.908760 DQ4 =126, DQ5 =114, DQ6 =132, DQ7 =138
7945 22:53:08.912624 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7946 22:53:08.915460 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7947 22:53:08.915935
7948 22:53:08.916341
7949 22:53:08.916849
7950 22:53:08.919249 [DramC_TX_OE_Calibration] TA2
7951 22:53:08.922689 Original DQ_B0 (3 6) =30, OEN = 27
7952 22:53:08.925591 Original DQ_B1 (3 6) =30, OEN = 27
7953 22:53:08.928941 24, 0x0, End_B0=24 End_B1=24
7954 22:53:08.932242 25, 0x0, End_B0=25 End_B1=25
7955 22:53:08.932687 26, 0x0, End_B0=26 End_B1=26
7956 22:53:08.935547 27, 0x0, End_B0=27 End_B1=27
7957 22:53:08.938972 28, 0x0, End_B0=28 End_B1=28
7958 22:53:08.942047 29, 0x0, End_B0=29 End_B1=29
7959 22:53:08.942481 30, 0x0, End_B0=30 End_B1=30
7960 22:53:08.945466 31, 0x4141, End_B0=30 End_B1=30
7961 22:53:08.948690 Byte0 end_step=30 best_step=27
7962 22:53:08.951946 Byte1 end_step=30 best_step=27
7963 22:53:08.955390 Byte0 TX OE(2T, 0.5T) = (3, 3)
7964 22:53:08.958555 Byte1 TX OE(2T, 0.5T) = (3, 3)
7965 22:53:08.958991
7966 22:53:08.959343
7967 22:53:08.965350 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7968 22:53:08.968551 CH0 RK0: MR19=303, MR18=1212
7969 22:53:08.975269 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
7970 22:53:08.975702
7971 22:53:08.978493 ----->DramcWriteLeveling(PI) begin...
7972 22:53:08.978928 ==
7973 22:53:08.981804 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 22:53:08.984953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 22:53:08.985451 ==
7976 22:53:08.988418 Write leveling (Byte 0): 33 => 33
7977 22:53:08.991899 Write leveling (Byte 1): 27 => 27
7978 22:53:08.995314 DramcWriteLeveling(PI) end<-----
7979 22:53:08.995743
7980 22:53:08.996076 ==
7981 22:53:08.998712 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 22:53:09.001596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 22:53:09.002027 ==
7984 22:53:09.004938 [Gating] SW mode calibration
7985 22:53:09.011715 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7986 22:53:09.018958 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7987 22:53:09.021750 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 22:53:09.028344 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 22:53:09.031579 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7990 22:53:09.034815 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7991 22:53:09.041787 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7992 22:53:09.045121 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7993 22:53:09.048017 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 22:53:09.054800 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 22:53:09.057929 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 22:53:09.061484 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 22:53:09.068306 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7998 22:53:09.071442 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
7999 22:53:09.074711 1 5 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8000 22:53:09.081484 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8001 22:53:09.084906 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 22:53:09.088003 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 22:53:09.094361 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 22:53:09.098045 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 22:53:09.101036 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8006 22:53:09.107596 1 6 12 | B1->B0 | 2323 3c3b | 0 1 | (0 0) (0 0)
8007 22:53:09.111016 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8008 22:53:09.114510 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 22:53:09.120831 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 22:53:09.124261 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 22:53:09.127806 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 22:53:09.131165 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 22:53:09.137310 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8014 22:53:09.140579 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8015 22:53:09.143980 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8016 22:53:09.150758 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8017 22:53:09.154213 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8018 22:53:09.157395 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 22:53:09.163883 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 22:53:09.167302 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 22:53:09.170628 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 22:53:09.177022 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 22:53:09.180418 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 22:53:09.183653 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 22:53:09.190397 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 22:53:09.193708 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 22:53:09.196977 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 22:53:09.203659 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 22:53:09.207125 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8030 22:53:09.210362 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8031 22:53:09.217127 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8032 22:53:09.220367 Total UI for P1: 0, mck2ui 16
8033 22:53:09.223741 best dqsien dly found for B0: ( 1, 9, 10)
8034 22:53:09.226881 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8035 22:53:09.230350 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 22:53:09.233646 Total UI for P1: 0, mck2ui 16
8037 22:53:09.237137 best dqsien dly found for B1: ( 1, 9, 18)
8038 22:53:09.240674 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8039 22:53:09.243862 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8040 22:53:09.244281
8041 22:53:09.250024 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8042 22:53:09.253738 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8043 22:53:09.256836 [Gating] SW calibration Done
8044 22:53:09.257267 ==
8045 22:53:09.259839 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 22:53:09.263052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 22:53:09.263500 ==
8048 22:53:09.263860 RX Vref Scan: 0
8049 22:53:09.266828
8050 22:53:09.267254 RX Vref 0 -> 0, step: 1
8051 22:53:09.267590
8052 22:53:09.269967 RX Delay 0 -> 252, step: 8
8053 22:53:09.273357 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8054 22:53:09.276447 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8055 22:53:09.283426 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8056 22:53:09.286691 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8057 22:53:09.290110 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8058 22:53:09.293417 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8059 22:53:09.296311 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8060 22:53:09.303086 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8061 22:53:09.306460 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8062 22:53:09.309890 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8063 22:53:09.312962 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8064 22:53:09.316354 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8065 22:53:09.323263 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8066 22:53:09.326110 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8067 22:53:09.329613 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8068 22:53:09.332939 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8069 22:53:09.333377 ==
8070 22:53:09.336476 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 22:53:09.342881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 22:53:09.343317 ==
8073 22:53:09.343690 DQS Delay:
8074 22:53:09.344081 DQS0 = 0, DQS1 = 0
8075 22:53:09.346419 DQM Delay:
8076 22:53:09.346836 DQM0 = 127, DQM1 = 122
8077 22:53:09.349685 DQ Delay:
8078 22:53:09.353183 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8079 22:53:09.356109 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8080 22:53:09.359372 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8081 22:53:09.362754 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8082 22:53:09.363284
8083 22:53:09.363697
8084 22:53:09.364079 ==
8085 22:53:09.366045 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 22:53:09.369528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 22:53:09.372489 ==
8088 22:53:09.373116
8089 22:53:09.373605
8090 22:53:09.374028 TX Vref Scan disable
8091 22:53:09.375907 == TX Byte 0 ==
8092 22:53:09.379551 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8093 22:53:09.382570 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8094 22:53:09.386025 == TX Byte 1 ==
8095 22:53:09.389164 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8096 22:53:09.392647 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8097 22:53:09.395984 ==
8098 22:53:09.396484 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 22:53:09.402553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 22:53:09.403150 ==
8101 22:53:09.415528
8102 22:53:09.418837 TX Vref early break, caculate TX vref
8103 22:53:09.422149 TX Vref=16, minBit 0, minWin=22, winSum=366
8104 22:53:09.425197 TX Vref=18, minBit 0, minWin=22, winSum=371
8105 22:53:09.428546 TX Vref=20, minBit 9, minWin=22, winSum=381
8106 22:53:09.431885 TX Vref=22, minBit 8, minWin=23, winSum=389
8107 22:53:09.435110 TX Vref=24, minBit 4, minWin=24, winSum=398
8108 22:53:09.441625 TX Vref=26, minBit 8, minWin=24, winSum=406
8109 22:53:09.444804 TX Vref=28, minBit 8, minWin=24, winSum=408
8110 22:53:09.448550 TX Vref=30, minBit 8, minWin=24, winSum=405
8111 22:53:09.451914 TX Vref=32, minBit 8, minWin=23, winSum=396
8112 22:53:09.455075 TX Vref=34, minBit 8, minWin=22, winSum=385
8113 22:53:09.461864 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 28
8114 22:53:09.462312
8115 22:53:09.465042 Final TX Range 0 Vref 28
8116 22:53:09.465490
8117 22:53:09.465887 ==
8118 22:53:09.468400 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 22:53:09.471284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 22:53:09.471733 ==
8121 22:53:09.472082
8122 22:53:09.472535
8123 22:53:09.474901 TX Vref Scan disable
8124 22:53:09.481573 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8125 22:53:09.482008 == TX Byte 0 ==
8126 22:53:09.484649 u2DelayCellOfst[0]=15 cells (4 PI)
8127 22:53:09.488049 u2DelayCellOfst[1]=18 cells (5 PI)
8128 22:53:09.491591 u2DelayCellOfst[2]=7 cells (2 PI)
8129 22:53:09.494857 u2DelayCellOfst[3]=11 cells (3 PI)
8130 22:53:09.498211 u2DelayCellOfst[4]=7 cells (2 PI)
8131 22:53:09.501477 u2DelayCellOfst[5]=0 cells (0 PI)
8132 22:53:09.504405 u2DelayCellOfst[6]=18 cells (5 PI)
8133 22:53:09.507810 u2DelayCellOfst[7]=15 cells (4 PI)
8134 22:53:09.511058 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8135 22:53:09.514523 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8136 22:53:09.517649 == TX Byte 1 ==
8137 22:53:09.518069 u2DelayCellOfst[8]=0 cells (0 PI)
8138 22:53:09.521025 u2DelayCellOfst[9]=0 cells (0 PI)
8139 22:53:09.524447 u2DelayCellOfst[10]=11 cells (3 PI)
8140 22:53:09.527697 u2DelayCellOfst[11]=7 cells (2 PI)
8141 22:53:09.531030 u2DelayCellOfst[12]=15 cells (4 PI)
8142 22:53:09.534542 u2DelayCellOfst[13]=11 cells (3 PI)
8143 22:53:09.537813 u2DelayCellOfst[14]=15 cells (4 PI)
8144 22:53:09.541096 u2DelayCellOfst[15]=15 cells (4 PI)
8145 22:53:09.544071 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8146 22:53:09.551154 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8147 22:53:09.551584 DramC Write-DBI on
8148 22:53:09.551947 ==
8149 22:53:09.554546 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 22:53:09.560865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 22:53:09.561300 ==
8152 22:53:09.561728
8153 22:53:09.562066
8154 22:53:09.562389 TX Vref Scan disable
8155 22:53:09.564691 == TX Byte 0 ==
8156 22:53:09.568287 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8157 22:53:09.571350 == TX Byte 1 ==
8158 22:53:09.574718 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8159 22:53:09.578175 DramC Write-DBI off
8160 22:53:09.578603
8161 22:53:09.578939 [DATLAT]
8162 22:53:09.579277 Freq=1600, CH0 RK1
8163 22:53:09.579609
8164 22:53:09.581276 DATLAT Default: 0xf
8165 22:53:09.581758 0, 0xFFFF, sum = 0
8166 22:53:09.584667 1, 0xFFFF, sum = 0
8167 22:53:09.587824 2, 0xFFFF, sum = 0
8168 22:53:09.588247 3, 0xFFFF, sum = 0
8169 22:53:09.591196 4, 0xFFFF, sum = 0
8170 22:53:09.591633 5, 0xFFFF, sum = 0
8171 22:53:09.594411 6, 0xFFFF, sum = 0
8172 22:53:09.594859 7, 0xFFFF, sum = 0
8173 22:53:09.598017 8, 0xFFFF, sum = 0
8174 22:53:09.598457 9, 0xFFFF, sum = 0
8175 22:53:09.601147 10, 0xFFFF, sum = 0
8176 22:53:09.601745 11, 0xFFFF, sum = 0
8177 22:53:09.604515 12, 0xFFFF, sum = 0
8178 22:53:09.605072 13, 0xCFFF, sum = 0
8179 22:53:09.607800 14, 0x0, sum = 1
8180 22:53:09.608369 15, 0x0, sum = 2
8181 22:53:09.611172 16, 0x0, sum = 3
8182 22:53:09.611605 17, 0x0, sum = 4
8183 22:53:09.614440 best_step = 15
8184 22:53:09.614867
8185 22:53:09.615209 ==
8186 22:53:09.618176 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 22:53:09.621077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 22:53:09.621543 ==
8189 22:53:09.624381 RX Vref Scan: 0
8190 22:53:09.624802
8191 22:53:09.625142 RX Vref 0 -> 0, step: 1
8192 22:53:09.625473
8193 22:53:09.627665 RX Delay 3 -> 252, step: 4
8194 22:53:09.630901 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8195 22:53:09.638089 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8196 22:53:09.641010 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8197 22:53:09.644602 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8198 22:53:09.647946 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8199 22:53:09.651340 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8200 22:53:09.657760 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8201 22:53:09.661043 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8202 22:53:09.664442 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8203 22:53:09.667914 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8204 22:53:09.671204 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8205 22:53:09.678445 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8206 22:53:09.681134 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8207 22:53:09.684374 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8208 22:53:09.687717 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8209 22:53:09.691059 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8210 22:53:09.694316 ==
8211 22:53:09.694743 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 22:53:09.700740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 22:53:09.701176 ==
8214 22:53:09.701572 DQS Delay:
8215 22:53:09.704149 DQS0 = 0, DQS1 = 0
8216 22:53:09.704704 DQM Delay:
8217 22:53:09.707633 DQM0 = 124, DQM1 = 117
8218 22:53:09.708060 DQ Delay:
8219 22:53:09.711036 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8220 22:53:09.714265 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8221 22:53:09.717563 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8222 22:53:09.720859 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8223 22:53:09.721272
8224 22:53:09.721635
8225 22:53:09.721945
8226 22:53:09.724343 [DramC_TX_OE_Calibration] TA2
8227 22:53:09.727540 Original DQ_B0 (3 6) =30, OEN = 27
8228 22:53:09.730923 Original DQ_B1 (3 6) =30, OEN = 27
8229 22:53:09.734464 24, 0x0, End_B0=24 End_B1=24
8230 22:53:09.737203 25, 0x0, End_B0=25 End_B1=25
8231 22:53:09.737689 26, 0x0, End_B0=26 End_B1=26
8232 22:53:09.740506 27, 0x0, End_B0=27 End_B1=27
8233 22:53:09.744052 28, 0x0, End_B0=28 End_B1=28
8234 22:53:09.747279 29, 0x0, End_B0=29 End_B1=29
8235 22:53:09.750695 30, 0x0, End_B0=30 End_B1=30
8236 22:53:09.751157 31, 0x4141, End_B0=30 End_B1=30
8237 22:53:09.753889 Byte0 end_step=30 best_step=27
8238 22:53:09.757288 Byte1 end_step=30 best_step=27
8239 22:53:09.760399 Byte0 TX OE(2T, 0.5T) = (3, 3)
8240 22:53:09.763784 Byte1 TX OE(2T, 0.5T) = (3, 3)
8241 22:53:09.764214
8242 22:53:09.764560
8243 22:53:09.770516 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8244 22:53:09.773915 CH0 RK1: MR19=303, MR18=2210
8245 22:53:09.780274 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8246 22:53:09.783921 [RxdqsGatingPostProcess] freq 1600
8247 22:53:09.790222 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8248 22:53:09.790705 best DQS0 dly(2T, 0.5T) = (1, 1)
8249 22:53:09.793623 best DQS1 dly(2T, 0.5T) = (1, 1)
8250 22:53:09.797057 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8251 22:53:09.800140 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8252 22:53:09.803699 best DQS0 dly(2T, 0.5T) = (1, 1)
8253 22:53:09.806750 best DQS1 dly(2T, 0.5T) = (1, 1)
8254 22:53:09.809961 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8255 22:53:09.813473 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8256 22:53:09.816994 Pre-setting of DQS Precalculation
8257 22:53:09.820254 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8258 22:53:09.820964 ==
8259 22:53:09.823555 Dram Type= 6, Freq= 0, CH_1, rank 0
8260 22:53:09.830302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 22:53:09.830753 ==
8262 22:53:09.833483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8263 22:53:09.839959 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8264 22:53:09.843248 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8265 22:53:09.849578 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8266 22:53:09.857648 [CA 0] Center 41 (13~70) winsize 58
8267 22:53:09.861045 [CA 1] Center 42 (12~72) winsize 61
8268 22:53:09.864243 [CA 2] Center 37 (8~66) winsize 59
8269 22:53:09.867640 [CA 3] Center 36 (7~66) winsize 60
8270 22:53:09.871084 [CA 4] Center 37 (8~67) winsize 60
8271 22:53:09.874023 [CA 5] Center 36 (7~65) winsize 59
8272 22:53:09.874467
8273 22:53:09.877553 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8274 22:53:09.878066
8275 22:53:09.880907 [CATrainingPosCal] consider 1 rank data
8276 22:53:09.884281 u2DelayCellTimex100 = 258/100 ps
8277 22:53:09.891136 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8278 22:53:09.894069 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8279 22:53:09.897748 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8280 22:53:09.900570 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8281 22:53:09.903845 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8282 22:53:09.907854 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8283 22:53:09.908414
8284 22:53:09.910615 CA PerBit enable=1, Macro0, CA PI delay=36
8285 22:53:09.911046
8286 22:53:09.913984 [CBTSetCACLKResult] CA Dly = 36
8287 22:53:09.917450 CS Dly: 10 (0~41)
8288 22:53:09.920527 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8289 22:53:09.923770 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8290 22:53:09.924334 ==
8291 22:53:09.927324 Dram Type= 6, Freq= 0, CH_1, rank 1
8292 22:53:09.930356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 22:53:09.933832 ==
8294 22:53:09.937252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 22:53:09.940842 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 22:53:09.947144 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 22:53:09.953555 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 22:53:09.960923 [CA 0] Center 41 (12~71) winsize 60
8299 22:53:09.964263 [CA 1] Center 42 (12~72) winsize 61
8300 22:53:09.967446 [CA 2] Center 37 (8~67) winsize 60
8301 22:53:09.970902 [CA 3] Center 36 (7~66) winsize 60
8302 22:53:09.974066 [CA 4] Center 37 (8~67) winsize 60
8303 22:53:09.977562 [CA 5] Center 36 (6~66) winsize 61
8304 22:53:09.977996
8305 22:53:09.981128 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8306 22:53:09.981703
8307 22:53:09.984458 [CATrainingPosCal] consider 2 rank data
8308 22:53:09.987644 u2DelayCellTimex100 = 258/100 ps
8309 22:53:09.990728 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8310 22:53:09.997461 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8311 22:53:10.000738 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8312 22:53:10.004202 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8313 22:53:10.007509 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8314 22:53:10.010980 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8315 22:53:10.011417
8316 22:53:10.014131 CA PerBit enable=1, Macro0, CA PI delay=36
8317 22:53:10.014561
8318 22:53:10.017577 [CBTSetCACLKResult] CA Dly = 36
8319 22:53:10.021052 CS Dly: 10 (0~42)
8320 22:53:10.024056 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 22:53:10.027627 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 22:53:10.028183
8323 22:53:10.030684 ----->DramcWriteLeveling(PI) begin...
8324 22:53:10.031116 ==
8325 22:53:10.034043 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 22:53:10.040588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 22:53:10.041190 ==
8328 22:53:10.043611 Write leveling (Byte 0): 25 => 25
8329 22:53:10.044027 Write leveling (Byte 1): 28 => 28
8330 22:53:10.047385 DramcWriteLeveling(PI) end<-----
8331 22:53:10.047923
8332 22:53:10.048283 ==
8333 22:53:10.050599 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 22:53:10.057188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 22:53:10.057656 ==
8336 22:53:10.060722 [Gating] SW mode calibration
8337 22:53:10.066981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8338 22:53:10.070359 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8339 22:53:10.076983 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 22:53:10.080167 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 22:53:10.083275 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 22:53:10.090199 1 4 12 | B1->B0 | 2424 2323 | 1 0 | (1 1) (0 0)
8343 22:53:10.093600 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8344 22:53:10.097112 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 22:53:10.103141 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 22:53:10.106460 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 22:53:10.109867 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 22:53:10.116589 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 22:53:10.119467 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 22:53:10.122833 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8351 22:53:10.129569 1 5 16 | B1->B0 | 2525 2424 | 0 0 | (1 0) (1 0)
8352 22:53:10.132941 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 22:53:10.136431 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 22:53:10.143220 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 22:53:10.146025 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 22:53:10.149448 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 22:53:10.156033 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 22:53:10.159612 1 6 12 | B1->B0 | 2d2d 2626 | 1 0 | (0 0) (0 0)
8359 22:53:10.162747 1 6 16 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
8360 22:53:10.169318 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 22:53:10.172382 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 22:53:10.175804 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 22:53:10.182583 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 22:53:10.185683 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 22:53:10.189090 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 22:53:10.195910 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8367 22:53:10.198776 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8368 22:53:10.202014 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 22:53:10.208635 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 22:53:10.211995 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 22:53:10.215470 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 22:53:10.222026 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 22:53:10.225261 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 22:53:10.228481 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 22:53:10.235033 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 22:53:10.238829 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 22:53:10.242046 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 22:53:10.248794 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 22:53:10.252100 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 22:53:10.255372 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 22:53:10.262126 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 22:53:10.265179 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8383 22:53:10.268294 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8384 22:53:10.274815 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 22:53:10.275252 Total UI for P1: 0, mck2ui 16
8386 22:53:10.278266 best dqsien dly found for B0: ( 1, 9, 14)
8387 22:53:10.281649 Total UI for P1: 0, mck2ui 16
8388 22:53:10.284857 best dqsien dly found for B1: ( 1, 9, 14)
8389 22:53:10.288247 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8390 22:53:10.295104 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8391 22:53:10.295537
8392 22:53:10.298423 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8393 22:53:10.301447 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8394 22:53:10.304965 [Gating] SW calibration Done
8395 22:53:10.305492 ==
8396 22:53:10.307964 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 22:53:10.311750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 22:53:10.312281 ==
8399 22:53:10.315201 RX Vref Scan: 0
8400 22:53:10.315618
8401 22:53:10.316143 RX Vref 0 -> 0, step: 1
8402 22:53:10.316485
8403 22:53:10.317837 RX Delay 0 -> 252, step: 8
8404 22:53:10.321240 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8405 22:53:10.328230 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8406 22:53:10.331392 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8407 22:53:10.334615 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8408 22:53:10.337775 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8409 22:53:10.341345 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8410 22:53:10.348292 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8411 22:53:10.351272 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8412 22:53:10.354562 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8413 22:53:10.357904 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8414 22:53:10.361383 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8415 22:53:10.367605 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8416 22:53:10.371149 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8417 22:53:10.374489 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8418 22:53:10.377752 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8419 22:53:10.380979 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8420 22:53:10.384216 ==
8421 22:53:10.387359 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 22:53:10.390918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 22:53:10.391339 ==
8424 22:53:10.391664 DQS Delay:
8425 22:53:10.394344 DQS0 = 0, DQS1 = 0
8426 22:53:10.394759 DQM Delay:
8427 22:53:10.397793 DQM0 = 131, DQM1 = 126
8428 22:53:10.398257 DQ Delay:
8429 22:53:10.400880 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8430 22:53:10.404300 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8431 22:53:10.407563 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8432 22:53:10.411039 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8433 22:53:10.411503
8434 22:53:10.411853
8435 22:53:10.412402 ==
8436 22:53:10.413856 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 22:53:10.420659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 22:53:10.421194 ==
8439 22:53:10.421741
8440 22:53:10.422114
8441 22:53:10.422465 TX Vref Scan disable
8442 22:53:10.424478 == TX Byte 0 ==
8443 22:53:10.427854 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8444 22:53:10.434572 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8445 22:53:10.435092 == TX Byte 1 ==
8446 22:53:10.437821 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8447 22:53:10.444505 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8448 22:53:10.444950 ==
8449 22:53:10.447339 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 22:53:10.451060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 22:53:10.451616 ==
8452 22:53:10.464491
8453 22:53:10.467638 TX Vref early break, caculate TX vref
8454 22:53:10.470623 TX Vref=16, minBit 10, minWin=21, winSum=363
8455 22:53:10.473961 TX Vref=18, minBit 9, minWin=21, winSum=368
8456 22:53:10.477279 TX Vref=20, minBit 5, minWin=23, winSum=384
8457 22:53:10.480976 TX Vref=22, minBit 1, minWin=24, winSum=392
8458 22:53:10.484293 TX Vref=24, minBit 1, minWin=24, winSum=403
8459 22:53:10.490691 TX Vref=26, minBit 12, minWin=24, winSum=408
8460 22:53:10.493940 TX Vref=28, minBit 13, minWin=24, winSum=418
8461 22:53:10.497555 TX Vref=30, minBit 0, minWin=24, winSum=410
8462 22:53:10.500806 TX Vref=32, minBit 0, minWin=23, winSum=402
8463 22:53:10.503881 TX Vref=34, minBit 0, minWin=24, winSum=397
8464 22:53:10.510480 TX Vref=36, minBit 1, minWin=22, winSum=383
8465 22:53:10.514004 [TxChooseVref] Worse bit 13, Min win 24, Win sum 418, Final Vref 28
8466 22:53:10.514421
8467 22:53:10.517197 Final TX Range 0 Vref 28
8468 22:53:10.517651
8469 22:53:10.517983 ==
8470 22:53:10.521108 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 22:53:10.523588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 22:53:10.527373 ==
8473 22:53:10.527837
8474 22:53:10.528246
8475 22:53:10.528621 TX Vref Scan disable
8476 22:53:10.533633 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8477 22:53:10.534299 == TX Byte 0 ==
8478 22:53:10.537227 u2DelayCellOfst[0]=18 cells (5 PI)
8479 22:53:10.540445 u2DelayCellOfst[1]=11 cells (3 PI)
8480 22:53:10.543627 u2DelayCellOfst[2]=0 cells (0 PI)
8481 22:53:10.547241 u2DelayCellOfst[3]=3 cells (1 PI)
8482 22:53:10.550209 u2DelayCellOfst[4]=7 cells (2 PI)
8483 22:53:10.553638 u2DelayCellOfst[5]=22 cells (6 PI)
8484 22:53:10.557083 u2DelayCellOfst[6]=18 cells (5 PI)
8485 22:53:10.560262 u2DelayCellOfst[7]=7 cells (2 PI)
8486 22:53:10.563696 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8487 22:53:10.567114 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8488 22:53:10.570602 == TX Byte 1 ==
8489 22:53:10.573860 u2DelayCellOfst[8]=0 cells (0 PI)
8490 22:53:10.576693 u2DelayCellOfst[9]=3 cells (1 PI)
8491 22:53:10.580032 u2DelayCellOfst[10]=11 cells (3 PI)
8492 22:53:10.583400 u2DelayCellOfst[11]=3 cells (1 PI)
8493 22:53:10.583829 u2DelayCellOfst[12]=15 cells (4 PI)
8494 22:53:10.586615 u2DelayCellOfst[13]=18 cells (5 PI)
8495 22:53:10.590379 u2DelayCellOfst[14]=18 cells (5 PI)
8496 22:53:10.593325 u2DelayCellOfst[15]=18 cells (5 PI)
8497 22:53:10.600065 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8498 22:53:10.603559 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8499 22:53:10.603981 DramC Write-DBI on
8500 22:53:10.606998 ==
8501 22:53:10.607421 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 22:53:10.613232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 22:53:10.613697 ==
8504 22:53:10.614036
8505 22:53:10.614350
8506 22:53:10.616834 TX Vref Scan disable
8507 22:53:10.617305 == TX Byte 0 ==
8508 22:53:10.623389 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8509 22:53:10.623817 == TX Byte 1 ==
8510 22:53:10.626606 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8511 22:53:10.629926 DramC Write-DBI off
8512 22:53:10.630508
8513 22:53:10.630969 [DATLAT]
8514 22:53:10.633310 Freq=1600, CH1 RK0
8515 22:53:10.633782
8516 22:53:10.634119 DATLAT Default: 0xf
8517 22:53:10.636738 0, 0xFFFF, sum = 0
8518 22:53:10.637296 1, 0xFFFF, sum = 0
8519 22:53:10.639797 2, 0xFFFF, sum = 0
8520 22:53:10.640223 3, 0xFFFF, sum = 0
8521 22:53:10.643513 4, 0xFFFF, sum = 0
8522 22:53:10.644132 5, 0xFFFF, sum = 0
8523 22:53:10.646635 6, 0xFFFF, sum = 0
8524 22:53:10.647103 7, 0xFFFF, sum = 0
8525 22:53:10.649651 8, 0xFFFF, sum = 0
8526 22:53:10.650079 9, 0xFFFF, sum = 0
8527 22:53:10.653628 10, 0xFFFF, sum = 0
8528 22:53:10.656320 11, 0xFFFF, sum = 0
8529 22:53:10.656747 12, 0xFFFF, sum = 0
8530 22:53:10.659499 13, 0x8FFF, sum = 0
8531 22:53:10.659926 14, 0x0, sum = 1
8532 22:53:10.663143 15, 0x0, sum = 2
8533 22:53:10.663572 16, 0x0, sum = 3
8534 22:53:10.666668 17, 0x0, sum = 4
8535 22:53:10.667092 best_step = 15
8536 22:53:10.667426
8537 22:53:10.667735 ==
8538 22:53:10.669780 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 22:53:10.673182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 22:53:10.673641 ==
8541 22:53:10.676448 RX Vref Scan: 1
8542 22:53:10.677038
8543 22:53:10.679809 Set Vref Range= 24 -> 127
8544 22:53:10.680230
8545 22:53:10.680562 RX Vref 24 -> 127, step: 1
8546 22:53:10.680877
8547 22:53:10.682662 RX Delay 11 -> 252, step: 4
8548 22:53:10.683244
8549 22:53:10.686071 Set Vref, RX VrefLevel [Byte0]: 24
8550 22:53:10.689416 [Byte1]: 24
8551 22:53:10.692977
8552 22:53:10.693397 Set Vref, RX VrefLevel [Byte0]: 25
8553 22:53:10.696429 [Byte1]: 25
8554 22:53:10.700310
8555 22:53:10.700728 Set Vref, RX VrefLevel [Byte0]: 26
8556 22:53:10.704195 [Byte1]: 26
8557 22:53:10.708128
8558 22:53:10.708549 Set Vref, RX VrefLevel [Byte0]: 27
8559 22:53:10.711302 [Byte1]: 27
8560 22:53:10.716043
8561 22:53:10.716497 Set Vref, RX VrefLevel [Byte0]: 28
8562 22:53:10.719389 [Byte1]: 28
8563 22:53:10.723539
8564 22:53:10.723957 Set Vref, RX VrefLevel [Byte0]: 29
8565 22:53:10.726722 [Byte1]: 29
8566 22:53:10.731148
8567 22:53:10.731564 Set Vref, RX VrefLevel [Byte0]: 30
8568 22:53:10.734432 [Byte1]: 30
8569 22:53:10.738558
8570 22:53:10.739048 Set Vref, RX VrefLevel [Byte0]: 31
8571 22:53:10.741990 [Byte1]: 31
8572 22:53:10.746513
8573 22:53:10.746974 Set Vref, RX VrefLevel [Byte0]: 32
8574 22:53:10.749419 [Byte1]: 32
8575 22:53:10.753985
8576 22:53:10.754404 Set Vref, RX VrefLevel [Byte0]: 33
8577 22:53:10.757002 [Byte1]: 33
8578 22:53:10.761210
8579 22:53:10.761652 Set Vref, RX VrefLevel [Byte0]: 34
8580 22:53:10.764761 [Byte1]: 34
8581 22:53:10.769215
8582 22:53:10.769669 Set Vref, RX VrefLevel [Byte0]: 35
8583 22:53:10.772534 [Byte1]: 35
8584 22:53:10.776821
8585 22:53:10.777241 Set Vref, RX VrefLevel [Byte0]: 36
8586 22:53:10.780200 [Byte1]: 36
8587 22:53:10.784250
8588 22:53:10.784669 Set Vref, RX VrefLevel [Byte0]: 37
8589 22:53:10.787668 [Byte1]: 37
8590 22:53:10.792184
8591 22:53:10.792603 Set Vref, RX VrefLevel [Byte0]: 38
8592 22:53:10.795178 [Byte1]: 38
8593 22:53:10.799371
8594 22:53:10.799799 Set Vref, RX VrefLevel [Byte0]: 39
8595 22:53:10.802699 [Byte1]: 39
8596 22:53:10.806920
8597 22:53:10.807340 Set Vref, RX VrefLevel [Byte0]: 40
8598 22:53:10.810346 [Byte1]: 40
8599 22:53:10.814756
8600 22:53:10.815177 Set Vref, RX VrefLevel [Byte0]: 41
8601 22:53:10.817972 [Byte1]: 41
8602 22:53:10.822105
8603 22:53:10.822527 Set Vref, RX VrefLevel [Byte0]: 42
8604 22:53:10.825561 [Byte1]: 42
8605 22:53:10.829880
8606 22:53:10.830428 Set Vref, RX VrefLevel [Byte0]: 43
8607 22:53:10.833153 [Byte1]: 43
8608 22:53:10.837696
8609 22:53:10.838107 Set Vref, RX VrefLevel [Byte0]: 44
8610 22:53:10.841028 [Byte1]: 44
8611 22:53:10.845272
8612 22:53:10.845725 Set Vref, RX VrefLevel [Byte0]: 45
8613 22:53:10.848445 [Byte1]: 45
8614 22:53:10.852891
8615 22:53:10.853301 Set Vref, RX VrefLevel [Byte0]: 46
8616 22:53:10.856261 [Byte1]: 46
8617 22:53:10.860471
8618 22:53:10.860880 Set Vref, RX VrefLevel [Byte0]: 47
8619 22:53:10.863800 [Byte1]: 47
8620 22:53:10.867869
8621 22:53:10.868325 Set Vref, RX VrefLevel [Byte0]: 48
8622 22:53:10.871453 [Byte1]: 48
8623 22:53:10.875448
8624 22:53:10.875860 Set Vref, RX VrefLevel [Byte0]: 49
8625 22:53:10.878776 [Byte1]: 49
8626 22:53:10.882963
8627 22:53:10.883455 Set Vref, RX VrefLevel [Byte0]: 50
8628 22:53:10.886564 [Byte1]: 50
8629 22:53:10.890891
8630 22:53:10.891354 Set Vref, RX VrefLevel [Byte0]: 51
8631 22:53:10.894156 [Byte1]: 51
8632 22:53:10.898595
8633 22:53:10.898974 Set Vref, RX VrefLevel [Byte0]: 52
8634 22:53:10.901961 [Byte1]: 52
8635 22:53:10.906331
8636 22:53:10.906768 Set Vref, RX VrefLevel [Byte0]: 53
8637 22:53:10.909162 [Byte1]: 53
8638 22:53:10.913613
8639 22:53:10.914079 Set Vref, RX VrefLevel [Byte0]: 54
8640 22:53:10.917022 [Byte1]: 54
8641 22:53:10.921606
8642 22:53:10.922039 Set Vref, RX VrefLevel [Byte0]: 55
8643 22:53:10.924852 [Byte1]: 55
8644 22:53:10.928774
8645 22:53:10.929261 Set Vref, RX VrefLevel [Byte0]: 56
8646 22:53:10.932131 [Byte1]: 56
8647 22:53:10.936501
8648 22:53:10.936932 Set Vref, RX VrefLevel [Byte0]: 57
8649 22:53:10.939839 [Byte1]: 57
8650 22:53:10.944031
8651 22:53:10.944467 Set Vref, RX VrefLevel [Byte0]: 58
8652 22:53:10.947652 [Byte1]: 58
8653 22:53:10.951916
8654 22:53:10.952410 Set Vref, RX VrefLevel [Byte0]: 59
8655 22:53:10.955080 [Byte1]: 59
8656 22:53:10.959754
8657 22:53:10.960202 Set Vref, RX VrefLevel [Byte0]: 60
8658 22:53:10.962420 [Byte1]: 60
8659 22:53:10.966885
8660 22:53:10.967406 Set Vref, RX VrefLevel [Byte0]: 61
8661 22:53:10.970499 [Byte1]: 61
8662 22:53:10.974721
8663 22:53:10.975158 Set Vref, RX VrefLevel [Byte0]: 62
8664 22:53:10.977911 [Byte1]: 62
8665 22:53:10.982204
8666 22:53:10.982745 Set Vref, RX VrefLevel [Byte0]: 63
8667 22:53:10.985646 [Byte1]: 63
8668 22:53:10.989614
8669 22:53:10.990064 Set Vref, RX VrefLevel [Byte0]: 64
8670 22:53:10.993366 [Byte1]: 64
8671 22:53:10.997380
8672 22:53:10.997863 Set Vref, RX VrefLevel [Byte0]: 65
8673 22:53:11.000494 [Byte1]: 65
8674 22:53:11.004884
8675 22:53:11.005779 Set Vref, RX VrefLevel [Byte0]: 66
8676 22:53:11.008310 [Byte1]: 66
8677 22:53:11.012925
8678 22:53:11.013363 Set Vref, RX VrefLevel [Byte0]: 67
8679 22:53:11.016174 [Byte1]: 67
8680 22:53:11.020052
8681 22:53:11.020491 Set Vref, RX VrefLevel [Byte0]: 68
8682 22:53:11.023421 [Byte1]: 68
8683 22:53:11.027705
8684 22:53:11.028153 Set Vref, RX VrefLevel [Byte0]: 69
8685 22:53:11.031383 [Byte1]: 69
8686 22:53:11.035454
8687 22:53:11.035904 Set Vref, RX VrefLevel [Byte0]: 70
8688 22:53:11.038527 [Byte1]: 70
8689 22:53:11.043048
8690 22:53:11.043491 Set Vref, RX VrefLevel [Byte0]: 71
8691 22:53:11.046360 [Byte1]: 71
8692 22:53:11.050910
8693 22:53:11.051353 Set Vref, RX VrefLevel [Byte0]: 72
8694 22:53:11.054117 [Byte1]: 72
8695 22:53:11.058279
8696 22:53:11.058731 Set Vref, RX VrefLevel [Byte0]: 73
8697 22:53:11.061978 [Byte1]: 73
8698 22:53:11.065763
8699 22:53:11.066211 Final RX Vref Byte 0 = 57 to rank0
8700 22:53:11.069118 Final RX Vref Byte 1 = 52 to rank0
8701 22:53:11.072860 Final RX Vref Byte 0 = 57 to rank1
8702 22:53:11.075989 Final RX Vref Byte 1 = 52 to rank1==
8703 22:53:11.078940 Dram Type= 6, Freq= 0, CH_1, rank 0
8704 22:53:11.085809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 22:53:11.086409 ==
8706 22:53:11.086954 DQS Delay:
8707 22:53:11.087471 DQS0 = 0, DQS1 = 0
8708 22:53:11.089147 DQM Delay:
8709 22:53:11.089618 DQM0 = 131, DQM1 = 123
8710 22:53:11.092289 DQ Delay:
8711 22:53:11.096126 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =128
8712 22:53:11.099027 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8713 22:53:11.102373 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8714 22:53:11.105970 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8715 22:53:11.106402
8716 22:53:11.106747
8717 22:53:11.107053
8718 22:53:11.108830 [DramC_TX_OE_Calibration] TA2
8719 22:53:11.112172 Original DQ_B0 (3 6) =30, OEN = 27
8720 22:53:11.115446 Original DQ_B1 (3 6) =30, OEN = 27
8721 22:53:11.119495 24, 0x0, End_B0=24 End_B1=24
8722 22:53:11.119939 25, 0x0, End_B0=25 End_B1=25
8723 22:53:11.122141 26, 0x0, End_B0=26 End_B1=26
8724 22:53:11.125700 27, 0x0, End_B0=27 End_B1=27
8725 22:53:11.129062 28, 0x0, End_B0=28 End_B1=28
8726 22:53:11.132369 29, 0x0, End_B0=29 End_B1=29
8727 22:53:11.132846 30, 0x0, End_B0=30 End_B1=30
8728 22:53:11.135412 31, 0x4141, End_B0=30 End_B1=30
8729 22:53:11.138884 Byte0 end_step=30 best_step=27
8730 22:53:11.142275 Byte1 end_step=30 best_step=27
8731 22:53:11.145452 Byte0 TX OE(2T, 0.5T) = (3, 3)
8732 22:53:11.148649 Byte1 TX OE(2T, 0.5T) = (3, 3)
8733 22:53:11.149085
8734 22:53:11.149417
8735 22:53:11.155734 [DQSOSCAuto] RK0, (LSB)MR18= 0xb10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
8736 22:53:11.158491 CH1 RK0: MR19=303, MR18=B10
8737 22:53:11.165204 CH1_RK0: MR19=0x303, MR18=0xB10, DQSOSC=401, MR23=63, INC=22, DEC=15
8738 22:53:11.165691
8739 22:53:11.168447 ----->DramcWriteLeveling(PI) begin...
8740 22:53:11.168993 ==
8741 22:53:11.171902 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 22:53:11.175461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 22:53:11.176016 ==
8744 22:53:11.178399 Write leveling (Byte 0): 23 => 23
8745 22:53:11.181803 Write leveling (Byte 1): 27 => 27
8746 22:53:11.184926 DramcWriteLeveling(PI) end<-----
8747 22:53:11.185383
8748 22:53:11.185797 ==
8749 22:53:11.188711 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 22:53:11.191775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 22:53:11.192216 ==
8752 22:53:11.194987 [Gating] SW mode calibration
8753 22:53:11.201636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8754 22:53:11.208255 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8755 22:53:11.211601 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 22:53:11.218281 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 22:53:11.221542 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
8758 22:53:11.224758 1 4 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8759 22:53:11.231159 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 22:53:11.234591 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 22:53:11.238590 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 22:53:11.241206 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 22:53:11.248203 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 22:53:11.251506 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8765 22:53:11.254643 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 1)
8766 22:53:11.261338 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
8767 22:53:11.264662 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 22:53:11.267471 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 22:53:11.274687 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 22:53:11.277445 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 22:53:11.281138 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 22:53:11.287783 1 6 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8773 22:53:11.291162 1 6 8 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8774 22:53:11.294148 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8775 22:53:11.300645 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 22:53:11.303974 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 22:53:11.307629 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 22:53:11.314226 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 22:53:11.317430 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 22:53:11.320905 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 22:53:11.326927 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8782 22:53:11.330732 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8783 22:53:11.333586 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8784 22:53:11.340151 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 22:53:11.343666 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 22:53:11.347286 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 22:53:11.353717 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 22:53:11.356791 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 22:53:11.360228 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 22:53:11.366966 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 22:53:11.370354 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 22:53:11.373610 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 22:53:11.380190 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 22:53:11.383575 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 22:53:11.386807 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 22:53:11.393289 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 22:53:11.396602 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8798 22:53:11.400042 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8799 22:53:11.406650 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 22:53:11.409920 Total UI for P1: 0, mck2ui 16
8801 22:53:11.412963 best dqsien dly found for B0: ( 1, 9, 10)
8802 22:53:11.413393 Total UI for P1: 0, mck2ui 16
8803 22:53:11.419963 best dqsien dly found for B1: ( 1, 9, 12)
8804 22:53:11.423490 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8805 22:53:11.426623 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8806 22:53:11.427054
8807 22:53:11.429957 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8808 22:53:11.433285 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8809 22:53:11.436435 [Gating] SW calibration Done
8810 22:53:11.436864 ==
8811 22:53:11.439673 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 22:53:11.443143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 22:53:11.443581 ==
8814 22:53:11.445981 RX Vref Scan: 0
8815 22:53:11.446418
8816 22:53:11.446763 RX Vref 0 -> 0, step: 1
8817 22:53:11.449943
8818 22:53:11.450373 RX Delay 0 -> 252, step: 8
8819 22:53:11.456302 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8820 22:53:11.459365 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8821 22:53:11.462621 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8822 22:53:11.465891 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8823 22:53:11.469354 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8824 22:53:11.475990 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8825 22:53:11.478901 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8826 22:53:11.482638 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8827 22:53:11.485610 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8828 22:53:11.489029 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8829 22:53:11.495779 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8830 22:53:11.499179 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8831 22:53:11.502439 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8832 22:53:11.505340 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8833 22:53:11.508612 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8834 22:53:11.515400 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8835 22:53:11.515860 ==
8836 22:53:11.518962 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 22:53:11.522399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 22:53:11.522825 ==
8839 22:53:11.523159 DQS Delay:
8840 22:53:11.525178 DQS0 = 0, DQS1 = 0
8841 22:53:11.525650 DQM Delay:
8842 22:53:11.528784 DQM0 = 132, DQM1 = 127
8843 22:53:11.529212 DQ Delay:
8844 22:53:11.531981 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8845 22:53:11.535481 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8846 22:53:11.538777 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8847 22:53:11.545269 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8848 22:53:11.545743
8849 22:53:11.546091
8850 22:53:11.546412 ==
8851 22:53:11.548757 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 22:53:11.552045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 22:53:11.552484 ==
8854 22:53:11.552831
8855 22:53:11.553150
8856 22:53:11.555262 TX Vref Scan disable
8857 22:53:11.555698 == TX Byte 0 ==
8858 22:53:11.561912 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8859 22:53:11.565169 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8860 22:53:11.565691 == TX Byte 1 ==
8861 22:53:11.571805 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8862 22:53:11.574524 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8863 22:53:11.574951 ==
8864 22:53:11.577980 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 22:53:11.581355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 22:53:11.581936 ==
8867 22:53:11.596514
8868 22:53:11.599844 TX Vref early break, caculate TX vref
8869 22:53:11.603507 TX Vref=16, minBit 0, minWin=23, winSum=387
8870 22:53:11.606541 TX Vref=18, minBit 0, minWin=23, winSum=392
8871 22:53:11.610028 TX Vref=20, minBit 0, minWin=24, winSum=400
8872 22:53:11.612985 TX Vref=22, minBit 0, minWin=24, winSum=408
8873 22:53:11.616657 TX Vref=24, minBit 0, minWin=24, winSum=413
8874 22:53:11.622955 TX Vref=26, minBit 0, minWin=24, winSum=421
8875 22:53:11.626199 TX Vref=28, minBit 0, minWin=24, winSum=421
8876 22:53:11.629638 TX Vref=30, minBit 6, minWin=24, winSum=418
8877 22:53:11.633075 TX Vref=32, minBit 1, minWin=24, winSum=413
8878 22:53:11.636489 TX Vref=34, minBit 1, minWin=23, winSum=400
8879 22:53:11.639357 TX Vref=36, minBit 1, minWin=22, winSum=392
8880 22:53:11.645958 [TxChooseVref] Worse bit 0, Min win 24, Win sum 421, Final Vref 26
8881 22:53:11.646384
8882 22:53:11.649865 Final TX Range 0 Vref 26
8883 22:53:11.650289
8884 22:53:11.650621 ==
8885 22:53:11.652640 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 22:53:11.655832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 22:53:11.656404 ==
8888 22:53:11.656870
8889 22:53:11.659737
8890 22:53:11.660156 TX Vref Scan disable
8891 22:53:11.666287 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8892 22:53:11.666707 == TX Byte 0 ==
8893 22:53:11.669668 u2DelayCellOfst[0]=18 cells (5 PI)
8894 22:53:11.672857 u2DelayCellOfst[1]=11 cells (3 PI)
8895 22:53:11.676092 u2DelayCellOfst[2]=0 cells (0 PI)
8896 22:53:11.679438 u2DelayCellOfst[3]=7 cells (2 PI)
8897 22:53:11.682864 u2DelayCellOfst[4]=7 cells (2 PI)
8898 22:53:11.686223 u2DelayCellOfst[5]=22 cells (6 PI)
8899 22:53:11.689262 u2DelayCellOfst[6]=22 cells (6 PI)
8900 22:53:11.693007 u2DelayCellOfst[7]=7 cells (2 PI)
8901 22:53:11.695739 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8902 22:53:11.699690 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8903 22:53:11.702797 == TX Byte 1 ==
8904 22:53:11.706095 u2DelayCellOfst[8]=0 cells (0 PI)
8905 22:53:11.709201 u2DelayCellOfst[9]=7 cells (2 PI)
8906 22:53:11.709854 u2DelayCellOfst[10]=15 cells (4 PI)
8907 22:53:11.712618 u2DelayCellOfst[11]=7 cells (2 PI)
8908 22:53:11.715871 u2DelayCellOfst[12]=15 cells (4 PI)
8909 22:53:11.719458 u2DelayCellOfst[13]=18 cells (5 PI)
8910 22:53:11.722707 u2DelayCellOfst[14]=22 cells (6 PI)
8911 22:53:11.726043 u2DelayCellOfst[15]=18 cells (5 PI)
8912 22:53:11.732136 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 22:53:11.735263 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8914 22:53:11.735345 DramC Write-DBI on
8915 22:53:11.735409 ==
8916 22:53:11.738664 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 22:53:11.745384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 22:53:11.745467 ==
8919 22:53:11.745591
8920 22:53:11.745673
8921 22:53:11.745732 TX Vref Scan disable
8922 22:53:11.749212 == TX Byte 0 ==
8923 22:53:11.752443 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8924 22:53:11.755786 == TX Byte 1 ==
8925 22:53:11.759267 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8926 22:53:11.762522 DramC Write-DBI off
8927 22:53:11.762603
8928 22:53:11.762668 [DATLAT]
8929 22:53:11.762728 Freq=1600, CH1 RK1
8930 22:53:11.762786
8931 22:53:11.765745 DATLAT Default: 0xf
8932 22:53:11.765827 0, 0xFFFF, sum = 0
8933 22:53:11.769479 1, 0xFFFF, sum = 0
8934 22:53:11.772246 2, 0xFFFF, sum = 0
8935 22:53:11.772329 3, 0xFFFF, sum = 0
8936 22:53:11.776018 4, 0xFFFF, sum = 0
8937 22:53:11.776101 5, 0xFFFF, sum = 0
8938 22:53:11.779200 6, 0xFFFF, sum = 0
8939 22:53:11.779283 7, 0xFFFF, sum = 0
8940 22:53:11.782602 8, 0xFFFF, sum = 0
8941 22:53:11.782685 9, 0xFFFF, sum = 0
8942 22:53:11.785986 10, 0xFFFF, sum = 0
8943 22:53:11.786069 11, 0xFFFF, sum = 0
8944 22:53:11.789317 12, 0xFFFF, sum = 0
8945 22:53:11.789401 13, 0x8FFF, sum = 0
8946 22:53:11.792652 14, 0x0, sum = 1
8947 22:53:11.792735 15, 0x0, sum = 2
8948 22:53:11.795623 16, 0x0, sum = 3
8949 22:53:11.795706 17, 0x0, sum = 4
8950 22:53:11.798879 best_step = 15
8951 22:53:11.798960
8952 22:53:11.799024 ==
8953 22:53:11.802434 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 22:53:11.805750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 22:53:11.805832 ==
8956 22:53:11.808935 RX Vref Scan: 0
8957 22:53:11.809015
8958 22:53:11.809079 RX Vref 0 -> 0, step: 1
8959 22:53:11.809139
8960 22:53:11.812223 RX Delay 3 -> 252, step: 4
8961 22:53:11.815932 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8962 22:53:11.822485 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8963 22:53:11.825635 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8964 22:53:11.828541 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8965 22:53:11.832133 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8966 22:53:11.835691 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8967 22:53:11.841954 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8968 22:53:11.845303 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8969 22:53:11.848736 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8970 22:53:11.851861 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
8971 22:53:11.855369 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8972 22:53:11.862151 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8973 22:53:11.865114 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8974 22:53:11.868681 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8975 22:53:11.872009 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8976 22:53:11.878266 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8977 22:53:11.878543 ==
8978 22:53:11.882019 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 22:53:11.885401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 22:53:11.885786 ==
8981 22:53:11.886039 DQS Delay:
8982 22:53:11.888740 DQS0 = 0, DQS1 = 0
8983 22:53:11.889037 DQM Delay:
8984 22:53:11.892078 DQM0 = 129, DQM1 = 125
8985 22:53:11.892515 DQ Delay:
8986 22:53:11.895595 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
8987 22:53:11.898664 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =124
8988 22:53:11.901786 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
8989 22:53:11.905340 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =134
8990 22:53:11.905806
8991 22:53:11.908715
8992 22:53:11.909132
8993 22:53:11.909461 [DramC_TX_OE_Calibration] TA2
8994 22:53:11.912035 Original DQ_B0 (3 6) =30, OEN = 27
8995 22:53:11.915343 Original DQ_B1 (3 6) =30, OEN = 27
8996 22:53:11.918554 24, 0x0, End_B0=24 End_B1=24
8997 22:53:11.921591 25, 0x0, End_B0=25 End_B1=25
8998 22:53:11.925431 26, 0x0, End_B0=26 End_B1=26
8999 22:53:11.925889 27, 0x0, End_B0=27 End_B1=27
9000 22:53:11.928545 28, 0x0, End_B0=28 End_B1=28
9001 22:53:11.931838 29, 0x0, End_B0=29 End_B1=29
9002 22:53:11.934987 30, 0x0, End_B0=30 End_B1=30
9003 22:53:11.938267 31, 0x4545, End_B0=30 End_B1=30
9004 22:53:11.938848 Byte0 end_step=30 best_step=27
9005 22:53:11.941579 Byte1 end_step=30 best_step=27
9006 22:53:11.945165 Byte0 TX OE(2T, 0.5T) = (3, 3)
9007 22:53:11.948356 Byte1 TX OE(2T, 0.5T) = (3, 3)
9008 22:53:11.948778
9009 22:53:11.949107
9010 22:53:11.955153 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9011 22:53:11.958765 CH1 RK1: MR19=303, MR18=E1A
9012 22:53:11.964870 CH1_RK1: MR19=0x303, MR18=0xE1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9013 22:53:11.968331 [RxdqsGatingPostProcess] freq 1600
9014 22:53:11.974768 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9015 22:53:11.978261 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 22:53:11.978685 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 22:53:11.981282 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 22:53:11.984746 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 22:53:11.988428 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 22:53:11.991723 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 22:53:11.995077 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 22:53:11.997929 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 22:53:12.001292 Pre-setting of DQS Precalculation
9024 22:53:12.004723 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9025 22:53:12.014449 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9026 22:53:12.021041 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9027 22:53:12.021625
9028 22:53:12.021975
9029 22:53:12.024362 [Calibration Summary] 3200 Mbps
9030 22:53:12.024872 CH 0, Rank 0
9031 22:53:12.028079 SW Impedance : PASS
9032 22:53:12.028543 DUTY Scan : NO K
9033 22:53:12.031193 ZQ Calibration : PASS
9034 22:53:12.034384 Jitter Meter : NO K
9035 22:53:12.034967 CBT Training : PASS
9036 22:53:12.037652 Write leveling : PASS
9037 22:53:12.040939 RX DQS gating : PASS
9038 22:53:12.041357 RX DQ/DQS(RDDQC) : PASS
9039 22:53:12.044265 TX DQ/DQS : PASS
9040 22:53:12.047683 RX DATLAT : PASS
9041 22:53:12.048107 RX DQ/DQS(Engine): PASS
9042 22:53:12.050904 TX OE : PASS
9043 22:53:12.051327 All Pass.
9044 22:53:12.051657
9045 22:53:12.054147 CH 0, Rank 1
9046 22:53:12.054569 SW Impedance : PASS
9047 22:53:12.057397 DUTY Scan : NO K
9048 22:53:12.060910 ZQ Calibration : PASS
9049 22:53:12.061328 Jitter Meter : NO K
9050 22:53:12.064056 CBT Training : PASS
9051 22:53:12.067429 Write leveling : PASS
9052 22:53:12.067879 RX DQS gating : PASS
9053 22:53:12.070671 RX DQ/DQS(RDDQC) : PASS
9054 22:53:12.074003 TX DQ/DQS : PASS
9055 22:53:12.074424 RX DATLAT : PASS
9056 22:53:12.077671 RX DQ/DQS(Engine): PASS
9057 22:53:12.080647 TX OE : PASS
9058 22:53:12.081069 All Pass.
9059 22:53:12.081401
9060 22:53:12.081760 CH 1, Rank 0
9061 22:53:12.083900 SW Impedance : PASS
9062 22:53:12.087229 DUTY Scan : NO K
9063 22:53:12.087650 ZQ Calibration : PASS
9064 22:53:12.090747 Jitter Meter : NO K
9065 22:53:12.091201 CBT Training : PASS
9066 22:53:12.093956 Write leveling : PASS
9067 22:53:12.097377 RX DQS gating : PASS
9068 22:53:12.097838 RX DQ/DQS(RDDQC) : PASS
9069 22:53:12.100664 TX DQ/DQS : PASS
9070 22:53:12.103952 RX DATLAT : PASS
9071 22:53:12.104376 RX DQ/DQS(Engine): PASS
9072 22:53:12.107278 TX OE : PASS
9073 22:53:12.107700 All Pass.
9074 22:53:12.108030
9075 22:53:12.110238 CH 1, Rank 1
9076 22:53:12.110657 SW Impedance : PASS
9077 22:53:12.113968 DUTY Scan : NO K
9078 22:53:12.117403 ZQ Calibration : PASS
9079 22:53:12.117874 Jitter Meter : NO K
9080 22:53:12.120186 CBT Training : PASS
9081 22:53:12.123609 Write leveling : PASS
9082 22:53:12.124016 RX DQS gating : PASS
9083 22:53:12.127000 RX DQ/DQS(RDDQC) : PASS
9084 22:53:12.130435 TX DQ/DQS : PASS
9085 22:53:12.130799 RX DATLAT : PASS
9086 22:53:12.133548 RX DQ/DQS(Engine): PASS
9087 22:53:12.133980 TX OE : PASS
9088 22:53:12.137294 All Pass.
9089 22:53:12.137852
9090 22:53:12.138309 DramC Write-DBI on
9091 22:53:12.140686 PER_BANK_REFRESH: Hybrid Mode
9092 22:53:12.143944 TX_TRACKING: ON
9093 22:53:12.150511 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9094 22:53:12.160567 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9095 22:53:12.167146 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 22:53:12.170129 [FAST_K] Save calibration result to emmc
9097 22:53:12.173586 sync common calibartion params.
9098 22:53:12.174017 sync cbt_mode0:1, 1:1
9099 22:53:12.176979 dram_init: ddr_geometry: 2
9100 22:53:12.180105 dram_init: ddr_geometry: 2
9101 22:53:12.183454 dram_init: ddr_geometry: 2
9102 22:53:12.183964 0:dram_rank_size:100000000
9103 22:53:12.186686 1:dram_rank_size:100000000
9104 22:53:12.193227 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9105 22:53:12.193696 DFS_SHUFFLE_HW_MODE: ON
9106 22:53:12.200093 dramc_set_vcore_voltage set vcore to 725000
9107 22:53:12.200661 Read voltage for 1600, 0
9108 22:53:12.203357 Vio18 = 0
9109 22:53:12.203782 Vcore = 725000
9110 22:53:12.204116 Vdram = 0
9111 22:53:12.206634 Vddq = 0
9112 22:53:12.207097 Vmddr = 0
9113 22:53:12.209883 switch to 3200 Mbps bootup
9114 22:53:12.210342 [DramcRunTimeConfig]
9115 22:53:12.210854 PHYPLL
9116 22:53:12.213596 DPM_CONTROL_AFTERK: ON
9117 22:53:12.216536 PER_BANK_REFRESH: ON
9118 22:53:12.217155 REFRESH_OVERHEAD_REDUCTION: ON
9119 22:53:12.219791 CMD_PICG_NEW_MODE: OFF
9120 22:53:12.223142 XRTWTW_NEW_MODE: ON
9121 22:53:12.223565 XRTRTR_NEW_MODE: ON
9122 22:53:12.226336 TX_TRACKING: ON
9123 22:53:12.226757 RDSEL_TRACKING: OFF
9124 22:53:12.229803 DQS Precalculation for DVFS: ON
9125 22:53:12.230225 RX_TRACKING: OFF
9126 22:53:12.233137 HW_GATING DBG: ON
9127 22:53:12.233598 ZQCS_ENABLE_LP4: ON
9128 22:53:12.236450 RX_PICG_NEW_MODE: ON
9129 22:53:12.239873 TX_PICG_NEW_MODE: ON
9130 22:53:12.240341 ENABLE_RX_DCM_DPHY: ON
9131 22:53:12.242968 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9132 22:53:12.246517 DUMMY_READ_FOR_TRACKING: OFF
9133 22:53:12.249437 !!! SPM_CONTROL_AFTERK: OFF
9134 22:53:12.253115 !!! SPM could not control APHY
9135 22:53:12.253606 IMPEDANCE_TRACKING: ON
9136 22:53:12.256386 TEMP_SENSOR: ON
9137 22:53:12.256838 HW_SAVE_FOR_SR: OFF
9138 22:53:12.259574 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9139 22:53:12.262986 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9140 22:53:12.266254 Read ODT Tracking: ON
9141 22:53:12.266717 Refresh Rate DeBounce: ON
9142 22:53:12.269572 DFS_NO_QUEUE_FLUSH: ON
9143 22:53:12.272816 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9144 22:53:12.276132 ENABLE_DFS_RUNTIME_MRW: OFF
9145 22:53:12.276592 DDR_RESERVE_NEW_MODE: ON
9146 22:53:12.279263 MR_CBT_SWITCH_FREQ: ON
9147 22:53:12.282668 =========================
9148 22:53:12.300904 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9149 22:53:12.304084 dram_init: ddr_geometry: 2
9150 22:53:12.322646 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9151 22:53:12.325803 dram_init: dram init end (result: 0)
9152 22:53:12.332376 DRAM-K: Full calibration passed in 24551 msecs
9153 22:53:12.335837 MRC: failed to locate region type 0.
9154 22:53:12.336255 DRAM rank0 size:0x100000000,
9155 22:53:12.339008 DRAM rank1 size=0x100000000
9156 22:53:12.348907 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9157 22:53:12.355768 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9158 22:53:12.362113 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9159 22:53:12.368838 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9160 22:53:12.372374 DRAM rank0 size:0x100000000,
9161 22:53:12.375265 DRAM rank1 size=0x100000000
9162 22:53:12.375718 CBMEM:
9163 22:53:12.378770 IMD: root @ 0xfffff000 254 entries.
9164 22:53:12.381973 IMD: root @ 0xffffec00 62 entries.
9165 22:53:12.385302 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9166 22:53:12.388894 WARNING: RO_VPD is uninitialized or empty.
9167 22:53:12.395565 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9168 22:53:12.402660 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9169 22:53:12.415605 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9170 22:53:12.426984 BS: romstage times (exec / console): total (unknown) / 24018 ms
9171 22:53:12.427451
9172 22:53:12.427815
9173 22:53:12.436420 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9174 22:53:12.439970 ARM64: Exception handlers installed.
9175 22:53:12.443110 ARM64: Testing exception
9176 22:53:12.446444 ARM64: Done test exception
9177 22:53:12.447013 Enumerating buses...
9178 22:53:12.450105 Show all devs... Before device enumeration.
9179 22:53:12.452977 Root Device: enabled 1
9180 22:53:12.456215 CPU_CLUSTER: 0: enabled 1
9181 22:53:12.456648 CPU: 00: enabled 1
9182 22:53:12.459785 Compare with tree...
9183 22:53:12.460215 Root Device: enabled 1
9184 22:53:12.463337 CPU_CLUSTER: 0: enabled 1
9185 22:53:12.466500 CPU: 00: enabled 1
9186 22:53:12.466923 Root Device scanning...
9187 22:53:12.469724 scan_static_bus for Root Device
9188 22:53:12.473165 CPU_CLUSTER: 0 enabled
9189 22:53:12.476280 scan_static_bus for Root Device done
9190 22:53:12.479608 scan_bus: bus Root Device finished in 8 msecs
9191 22:53:12.480060 done
9192 22:53:12.486352 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9193 22:53:12.489615 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9194 22:53:12.496313 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9195 22:53:12.499692 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9196 22:53:12.502857 Allocating resources...
9197 22:53:12.506234 Reading resources...
9198 22:53:12.509654 Root Device read_resources bus 0 link: 0
9199 22:53:12.510081 DRAM rank0 size:0x100000000,
9200 22:53:12.512960 DRAM rank1 size=0x100000000
9201 22:53:12.516369 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9202 22:53:12.519789 CPU: 00 missing read_resources
9203 22:53:12.523136 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9204 22:53:12.529918 Root Device read_resources bus 0 link: 0 done
9205 22:53:12.530337 Done reading resources.
9206 22:53:12.536019 Show resources in subtree (Root Device)...After reading.
9207 22:53:12.539703 Root Device child on link 0 CPU_CLUSTER: 0
9208 22:53:12.542752 CPU_CLUSTER: 0 child on link 0 CPU: 00
9209 22:53:12.552484 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9210 22:53:12.552905 CPU: 00
9211 22:53:12.556035 Root Device assign_resources, bus 0 link: 0
9212 22:53:12.559440 CPU_CLUSTER: 0 missing set_resources
9213 22:53:12.565658 Root Device assign_resources, bus 0 link: 0 done
9214 22:53:12.566089 Done setting resources.
9215 22:53:12.572425 Show resources in subtree (Root Device)...After assigning values.
9216 22:53:12.575656 Root Device child on link 0 CPU_CLUSTER: 0
9217 22:53:12.579193 CPU_CLUSTER: 0 child on link 0 CPU: 00
9218 22:53:12.589102 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9219 22:53:12.589556 CPU: 00
9220 22:53:12.592316 Done allocating resources.
9221 22:53:12.595755 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9222 22:53:12.599211 Enabling resources...
9223 22:53:12.599624 done.
9224 22:53:12.605489 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9225 22:53:12.605951 Initializing devices...
9226 22:53:12.608942 Root Device init
9227 22:53:12.609359 init hardware done!
9228 22:53:12.612387 0x00000018: ctrlr->caps
9229 22:53:12.615679 52.000 MHz: ctrlr->f_max
9230 22:53:12.616120 0.400 MHz: ctrlr->f_min
9231 22:53:12.618568 0x40ff8080: ctrlr->voltages
9232 22:53:12.622477 sclk: 390625
9233 22:53:12.622934 Bus Width = 1
9234 22:53:12.623294 sclk: 390625
9235 22:53:12.625194 Bus Width = 1
9236 22:53:12.625702 Early init status = 3
9237 22:53:12.632033 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9238 22:53:12.635454 in-header: 03 fc 00 00 01 00 00 00
9239 22:53:12.635871 in-data: 00
9240 22:53:12.641973 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9241 22:53:12.645115 in-header: 03 fd 00 00 00 00 00 00
9242 22:53:12.648591 in-data:
9243 22:53:12.651944 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9244 22:53:12.655767 in-header: 03 fc 00 00 01 00 00 00
9245 22:53:12.658667 in-data: 00
9246 22:53:12.661967 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9247 22:53:12.667608 in-header: 03 fd 00 00 00 00 00 00
9248 22:53:12.670870 in-data:
9249 22:53:12.674360 [SSUSB] Setting up USB HOST controller...
9250 22:53:12.677554 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9251 22:53:12.680861 [SSUSB] phy power-on done.
9252 22:53:12.684342 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9253 22:53:12.690438 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9254 22:53:12.694026 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9255 22:53:12.700263 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9256 22:53:12.707327 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9257 22:53:12.713726 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9258 22:53:12.720673 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9259 22:53:12.727053 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9260 22:53:12.730482 SPM: binary array size = 0x9dc
9261 22:53:12.733717 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9262 22:53:12.740469 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9263 22:53:12.747654 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9264 22:53:12.750421 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9265 22:53:12.756737 configure_display: Starting display init
9266 22:53:12.790756 anx7625_power_on_init: Init interface.
9267 22:53:12.794236 anx7625_disable_pd_protocol: Disabled PD feature.
9268 22:53:12.796935 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9269 22:53:12.825069 anx7625_start_dp_work: Secure OCM version=00
9270 22:53:12.828345 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9271 22:53:12.843044 sp_tx_get_edid_block: EDID Block = 1
9272 22:53:12.945694 Extracted contents:
9273 22:53:12.949136 header: 00 ff ff ff ff ff ff 00
9274 22:53:12.952671 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9275 22:53:12.955594 version: 01 04
9276 22:53:12.958881 basic params: 95 1f 11 78 0a
9277 22:53:12.962304 chroma info: 76 90 94 55 54 90 27 21 50 54
9278 22:53:12.965683 established: 00 00 00
9279 22:53:12.972263 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9280 22:53:12.978512 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9281 22:53:12.981749 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9282 22:53:12.989007 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9283 22:53:12.994993 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9284 22:53:12.998546 extensions: 00
9285 22:53:12.999005 checksum: fb
9286 22:53:12.999369
9287 22:53:13.002067 Manufacturer: IVO Model 57d Serial Number 0
9288 22:53:13.005305 Made week 0 of 2020
9289 22:53:13.008750 EDID version: 1.4
9290 22:53:13.009212 Digital display
9291 22:53:13.011835 6 bits per primary color channel
9292 22:53:13.012304 DisplayPort interface
9293 22:53:13.015383 Maximum image size: 31 cm x 17 cm
9294 22:53:13.018580 Gamma: 220%
9295 22:53:13.019176 Check DPMS levels
9296 22:53:13.021928 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9297 22:53:13.028076 First detailed timing is preferred timing
9298 22:53:13.028555 Established timings supported:
9299 22:53:13.031442 Standard timings supported:
9300 22:53:13.034787 Detailed timings
9301 22:53:13.037880 Hex of detail: 383680a07038204018303c0035ae10000019
9302 22:53:13.044896 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9303 22:53:13.048108 0780 0798 07c8 0820 hborder 0
9304 22:53:13.051137 0438 043b 0447 0458 vborder 0
9305 22:53:13.054767 -hsync -vsync
9306 22:53:13.055227 Did detailed timing
9307 22:53:13.061247 Hex of detail: 000000000000000000000000000000000000
9308 22:53:13.064663 Manufacturer-specified data, tag 0
9309 22:53:13.067943 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9310 22:53:13.071120 ASCII string: InfoVision
9311 22:53:13.074626 Hex of detail: 000000fe00523134304e574635205248200a
9312 22:53:13.077733 ASCII string: R140NWF5 RH
9313 22:53:13.078212 Checksum
9314 22:53:13.081057 Checksum: 0xfb (valid)
9315 22:53:13.084410 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9316 22:53:13.087840 DSI data_rate: 832800000 bps
9317 22:53:13.094551 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9318 22:53:13.097956 anx7625_parse_edid: pixelclock(138800).
9319 22:53:13.100750 hactive(1920), hsync(48), hfp(24), hbp(88)
9320 22:53:13.104187 vactive(1080), vsync(12), vfp(3), vbp(17)
9321 22:53:13.107494 anx7625_dsi_config: config dsi.
9322 22:53:13.114039 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9323 22:53:13.127961 anx7625_dsi_config: success to config DSI
9324 22:53:13.131165 anx7625_dp_start: MIPI phy setup OK.
9325 22:53:13.134429 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9326 22:53:13.137394 mtk_ddp_mode_set invalid vrefresh 60
9327 22:53:13.140847 main_disp_path_setup
9328 22:53:13.141271 ovl_layer_smi_id_en
9329 22:53:13.143962 ovl_layer_smi_id_en
9330 22:53:13.144380 ccorr_config
9331 22:53:13.144715 aal_config
9332 22:53:13.147506 gamma_config
9333 22:53:13.147969 postmask_config
9334 22:53:13.150994 dither_config
9335 22:53:13.153940 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9336 22:53:13.160523 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9337 22:53:13.163693 Root Device init finished in 552 msecs
9338 22:53:13.167175 CPU_CLUSTER: 0 init
9339 22:53:13.173823 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9340 22:53:13.180451 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9341 22:53:13.181051 APU_MBOX 0x190000b0 = 0x10001
9342 22:53:13.183797 APU_MBOX 0x190001b0 = 0x10001
9343 22:53:13.186950 APU_MBOX 0x190005b0 = 0x10001
9344 22:53:13.190540 APU_MBOX 0x190006b0 = 0x10001
9345 22:53:13.196776 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9346 22:53:13.207055 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9347 22:53:13.219339 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9348 22:53:13.225506 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9349 22:53:13.237223 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9350 22:53:13.246353 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9351 22:53:13.249957 CPU_CLUSTER: 0 init finished in 81 msecs
9352 22:53:13.253547 Devices initialized
9353 22:53:13.256548 Show all devs... After init.
9354 22:53:13.257062 Root Device: enabled 1
9355 22:53:13.259980 CPU_CLUSTER: 0: enabled 1
9356 22:53:13.262863 CPU: 00: enabled 1
9357 22:53:13.266714 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9358 22:53:13.269419 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9359 22:53:13.272630 ELOG: NV offset 0x57f000 size 0x1000
9360 22:53:13.279443 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9361 22:53:13.286396 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9362 22:53:13.289576 ELOG: Event(17) added with size 13 at 2024-05-07 22:53:14 UTC
9363 22:53:13.296289 out: cmd=0x121: 03 db 21 01 00 00 00 00
9364 22:53:13.299390 in-header: 03 75 00 00 2c 00 00 00
9365 22:53:13.309070 in-data: ea 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9366 22:53:13.316015 ELOG: Event(A1) added with size 10 at 2024-05-07 22:53:14 UTC
9367 22:53:13.322929 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9368 22:53:13.329244 ELOG: Event(A0) added with size 9 at 2024-05-07 22:53:14 UTC
9369 22:53:13.332541 elog_add_boot_reason: Logged dev mode boot
9370 22:53:13.338990 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9371 22:53:13.339508 Finalize devices...
9372 22:53:13.342302 Devices finalized
9373 22:53:13.345603 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9374 22:53:13.349080 Writing coreboot table at 0xffe64000
9375 22:53:13.352603 0. 000000000010a000-0000000000113fff: RAMSTAGE
9376 22:53:13.358868 1. 0000000040000000-00000000400fffff: RAM
9377 22:53:13.362009 2. 0000000040100000-000000004032afff: RAMSTAGE
9378 22:53:13.365219 3. 000000004032b000-00000000545fffff: RAM
9379 22:53:13.368866 4. 0000000054600000-000000005465ffff: BL31
9380 22:53:13.371791 5. 0000000054660000-00000000ffe63fff: RAM
9381 22:53:13.378402 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9382 22:53:13.382284 7. 0000000100000000-000000023fffffff: RAM
9383 22:53:13.384993 Passing 5 GPIOs to payload:
9384 22:53:13.388320 NAME | PORT | POLARITY | VALUE
9385 22:53:13.395062 EC in RW | 0x000000aa | low | undefined
9386 22:53:13.398161 EC interrupt | 0x00000005 | low | undefined
9387 22:53:13.401548 TPM interrupt | 0x000000ab | high | undefined
9388 22:53:13.408216 SD card detect | 0x00000011 | high | undefined
9389 22:53:13.411301 speaker enable | 0x00000093 | high | undefined
9390 22:53:13.414926 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9391 22:53:13.418252 in-header: 03 f9 00 00 02 00 00 00
9392 22:53:13.421924 in-data: 02 00
9393 22:53:13.424753 ADC[4]: Raw value=893341 ID=7
9394 22:53:13.425236 ADC[3]: Raw value=213440 ID=1
9395 22:53:13.428118 RAM Code: 0x71
9396 22:53:13.431492 ADC[6]: Raw value=74722 ID=0
9397 22:53:13.431949 ADC[5]: Raw value=212330 ID=1
9398 22:53:13.434815 SKU Code: 0x1
9399 22:53:13.440933 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d956
9400 22:53:13.441358 coreboot table: 964 bytes.
9401 22:53:13.444822 IMD ROOT 0. 0xfffff000 0x00001000
9402 22:53:13.447653 IMD SMALL 1. 0xffffe000 0x00001000
9403 22:53:13.451086 RO MCACHE 2. 0xffffc000 0x00001104
9404 22:53:13.454315 CONSOLE 3. 0xfff7c000 0x00080000
9405 22:53:13.458039 FMAP 4. 0xfff7b000 0x00000452
9406 22:53:13.461432 TIME STAMP 5. 0xfff7a000 0x00000910
9407 22:53:13.464521 VBOOT WORK 6. 0xfff66000 0x00014000
9408 22:53:13.467624 RAMOOPS 7. 0xffe66000 0x00100000
9409 22:53:13.470921 COREBOOT 8. 0xffe64000 0x00002000
9410 22:53:13.474319 IMD small region:
9411 22:53:13.477780 IMD ROOT 0. 0xffffec00 0x00000400
9412 22:53:13.481002 VPD 1. 0xffffeb80 0x0000006c
9413 22:53:13.484436 MMC STATUS 2. 0xffffeb60 0x00000004
9414 22:53:13.487598 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9415 22:53:13.490815 Probing TPM: done!
9416 22:53:13.494174 Connected to device vid:did:rid of 1ae0:0028:00
9417 22:53:13.505421 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9418 22:53:13.508680 Initialized TPM device CR50 revision 0
9419 22:53:13.512459 Checking cr50 for pending updates
9420 22:53:13.516431 Reading cr50 TPM mode
9421 22:53:13.524788 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9422 22:53:13.531243 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9423 22:53:13.571536 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9424 22:53:13.574857 Checking segment from ROM address 0x40100000
9425 22:53:13.578261 Checking segment from ROM address 0x4010001c
9426 22:53:13.585227 Loading segment from ROM address 0x40100000
9427 22:53:13.585686 code (compression=0)
9428 22:53:13.591598 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9429 22:53:13.601544 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9430 22:53:13.601997 it's not compressed!
9431 22:53:13.608237 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9432 22:53:13.611952 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9433 22:53:13.632046 Loading segment from ROM address 0x4010001c
9434 22:53:13.632477 Entry Point 0x80000000
9435 22:53:13.635114 Loaded segments
9436 22:53:13.638731 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9437 22:53:13.645396 Jumping to boot code at 0x80000000(0xffe64000)
9438 22:53:13.652142 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9439 22:53:13.658459 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9440 22:53:13.666760 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9441 22:53:13.670005 Checking segment from ROM address 0x40100000
9442 22:53:13.672943 Checking segment from ROM address 0x4010001c
9443 22:53:13.679546 Loading segment from ROM address 0x40100000
9444 22:53:13.679967 code (compression=1)
9445 22:53:13.686196 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9446 22:53:13.696295 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9447 22:53:13.696718 using LZMA
9448 22:53:13.704913 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9449 22:53:13.711195 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9450 22:53:13.714782 Loading segment from ROM address 0x4010001c
9451 22:53:13.715204 Entry Point 0x54601000
9452 22:53:13.718243 Loaded segments
9453 22:53:13.721198 NOTICE: MT8192 bl31_setup
9454 22:53:13.728177 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9455 22:53:13.731504 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9456 22:53:13.734845 WARNING: region 0:
9457 22:53:13.738164 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 22:53:13.738587 WARNING: region 1:
9459 22:53:13.744909 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9460 22:53:13.748558 WARNING: region 2:
9461 22:53:13.751488 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9462 22:53:13.755037 WARNING: region 3:
9463 22:53:13.758163 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 22:53:13.761615 WARNING: region 4:
9465 22:53:13.768275 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 22:53:13.768697 WARNING: region 5:
9467 22:53:13.771736 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 22:53:13.775078 WARNING: region 6:
9469 22:53:13.778697 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 22:53:13.781640 WARNING: region 7:
9471 22:53:13.784972 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 22:53:13.791564 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9473 22:53:13.795375 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9474 22:53:13.798197 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9475 22:53:13.804826 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9476 22:53:13.808354 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9477 22:53:13.811516 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9478 22:53:13.818561 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9479 22:53:13.821585 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9480 22:53:13.828543 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9481 22:53:13.831540 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9482 22:53:13.835003 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9483 22:53:13.842076 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9484 22:53:13.845089 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9485 22:53:13.848527 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9486 22:53:13.855201 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9487 22:53:13.858101 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9488 22:53:13.861544 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9489 22:53:13.867906 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9490 22:53:13.871281 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9491 22:53:13.878269 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9492 22:53:13.881639 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9493 22:53:13.885055 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9494 22:53:13.891335 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9495 22:53:13.894731 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9496 22:53:13.901316 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9497 22:53:13.904741 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9498 22:53:13.908071 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9499 22:53:13.914714 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9500 22:53:13.918001 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9501 22:53:13.921385 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9502 22:53:13.927919 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9503 22:53:13.931259 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9504 22:53:13.934754 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9505 22:53:13.941416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9506 22:53:13.944822 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9507 22:53:13.947913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9508 22:53:13.951370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9509 22:53:13.958122 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9510 22:53:13.961383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9511 22:53:13.964748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9512 22:53:13.967932 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9513 22:53:13.974559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9514 22:53:13.977823 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9515 22:53:13.981196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9516 22:53:13.984689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9517 22:53:13.991277 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9518 22:53:13.994796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9519 22:53:13.997983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9520 22:53:14.004934 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9521 22:53:14.008234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9522 22:53:14.014925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9523 22:53:14.018362 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9524 22:53:14.021353 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9525 22:53:14.027791 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9526 22:53:14.031195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9527 22:53:14.037924 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9528 22:53:14.041319 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9529 22:53:14.044739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9530 22:53:14.051382 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9531 22:53:14.054877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9532 22:53:14.061441 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9533 22:53:14.064607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9534 22:53:14.071477 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9535 22:53:14.074756 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9536 22:53:14.081417 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9537 22:53:14.084566 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9538 22:53:14.088050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9539 22:53:14.094497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9540 22:53:14.098305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9541 22:53:14.104729 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9542 22:53:14.107980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9543 22:53:14.114396 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9544 22:53:14.117821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9545 22:53:14.121556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9546 22:53:14.127753 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9547 22:53:14.131402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9548 22:53:14.138011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9549 22:53:14.141374 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9550 22:53:14.148119 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9551 22:53:14.151462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9552 22:53:14.158173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9553 22:53:14.161486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9554 22:53:14.164839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9555 22:53:14.171427 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9556 22:53:14.174713 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9557 22:53:14.181367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9558 22:53:14.185063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9559 22:53:14.188046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9560 22:53:14.195174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9561 22:53:14.198310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9562 22:53:14.204689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9563 22:53:14.207802 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9564 22:53:14.214952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9565 22:53:14.218503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9566 22:53:14.224637 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9567 22:53:14.228597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9568 22:53:14.231468 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9569 22:53:14.234766 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9570 22:53:14.241762 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9571 22:53:14.244977 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9572 22:53:14.248790 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9573 22:53:14.254782 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9574 22:53:14.258260 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9575 22:53:14.261628 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9576 22:53:14.268406 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9577 22:53:14.271400 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9578 22:53:14.278443 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9579 22:53:14.281703 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9580 22:53:14.284836 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9581 22:53:14.291520 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9582 22:53:14.295307 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9583 22:53:14.298456 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9584 22:53:14.304916 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9585 22:53:14.308184 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9586 22:53:14.314897 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9587 22:53:14.318623 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9588 22:53:14.321748 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9589 22:53:14.328252 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9590 22:53:14.331930 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9591 22:53:14.334971 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9592 22:53:14.338315 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9593 22:53:14.344991 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9594 22:53:14.348559 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9595 22:53:14.351636 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9596 22:53:14.358514 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9597 22:53:14.361538 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9598 22:53:14.364843 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9599 22:53:14.371951 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9600 22:53:14.374938 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9601 22:53:14.381624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9602 22:53:14.385035 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9603 22:53:14.388422 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9604 22:53:14.394780 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9605 22:53:14.398058 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9606 22:53:14.401403 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9607 22:53:14.408186 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9608 22:53:14.411363 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9609 22:53:14.418262 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9610 22:53:14.421771 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9611 22:53:14.425304 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9612 22:53:14.431352 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9613 22:53:14.434718 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9614 22:53:14.441809 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9615 22:53:14.445260 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9616 22:53:14.448299 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9617 22:53:14.455167 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9618 22:53:14.458081 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9619 22:53:14.461614 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9620 22:53:14.468198 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9621 22:53:14.471453 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9622 22:53:14.478250 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9623 22:53:14.481490 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9624 22:53:14.484824 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9625 22:53:14.491599 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9626 22:53:14.494879 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9627 22:53:14.501458 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9628 22:53:14.504653 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9629 22:53:14.508148 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9630 22:53:14.514706 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9631 22:53:14.518098 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9632 22:53:14.521660 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9633 22:53:14.528315 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9634 22:53:14.531344 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9635 22:53:14.537917 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9636 22:53:14.541654 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9637 22:53:14.544663 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9638 22:53:14.551530 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9639 22:53:14.554829 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9640 22:53:14.561346 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9641 22:53:14.564519 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9642 22:53:14.568136 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9643 22:53:14.574686 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9644 22:53:14.578085 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9645 22:53:14.584391 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9646 22:53:14.587659 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9647 22:53:14.591047 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9648 22:53:14.598037 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9649 22:53:14.601298 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9650 22:53:14.608038 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9651 22:53:14.610826 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9652 22:53:14.614551 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9653 22:53:14.620887 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9654 22:53:14.624470 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9655 22:53:14.630843 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9656 22:53:14.634201 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9657 22:53:14.637470 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9658 22:53:14.644305 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9659 22:53:14.647472 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9660 22:53:14.654221 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9661 22:53:14.657771 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9662 22:53:14.660358 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9663 22:53:14.667481 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9664 22:53:14.670762 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9665 22:53:14.677428 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9666 22:53:14.680749 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9667 22:53:14.683831 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9668 22:53:14.690539 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9669 22:53:14.693769 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9670 22:53:14.700511 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9671 22:53:14.703700 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9672 22:53:14.710549 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9673 22:53:14.713966 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9674 22:53:14.716736 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9675 22:53:14.723795 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9676 22:53:14.727006 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9677 22:53:14.733705 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9678 22:53:14.736975 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9679 22:53:14.739912 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9680 22:53:14.746769 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9681 22:53:14.750177 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9682 22:53:14.756481 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9683 22:53:14.759753 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9684 22:53:14.766303 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9685 22:53:14.769770 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9686 22:53:14.773215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9687 22:53:14.779877 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9688 22:53:14.783296 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9689 22:53:14.789681 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9690 22:53:14.792956 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9691 22:53:14.799795 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9692 22:53:14.803181 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9693 22:53:14.806300 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9694 22:53:14.812852 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9695 22:53:14.816687 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9696 22:53:14.822854 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9697 22:53:14.826333 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9698 22:53:14.829857 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9699 22:53:14.836076 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9700 22:53:14.839387 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9701 22:53:14.845856 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9702 22:53:14.849287 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9703 22:53:14.852444 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9704 22:53:14.855893 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9705 22:53:14.859406 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9706 22:53:14.866125 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9707 22:53:14.869155 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9708 22:53:14.876290 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9709 22:53:14.879103 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9710 22:53:14.882285 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9711 22:53:14.889284 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9712 22:53:14.892272 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9713 22:53:14.898867 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9714 22:53:14.902120 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9715 22:53:14.905810 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9716 22:53:14.912284 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9717 22:53:14.915281 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9718 22:53:14.918684 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9719 22:53:14.925393 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9720 22:53:14.928828 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9721 22:53:14.932147 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9722 22:53:14.938833 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9723 22:53:14.941874 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9724 22:53:14.948446 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9725 22:53:14.951712 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9726 22:53:14.955567 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9727 22:53:14.962145 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9728 22:53:14.965158 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9729 22:53:14.968574 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9730 22:53:14.975497 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9731 22:53:14.978896 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9732 22:53:14.981860 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9733 22:53:14.988883 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9734 22:53:14.992023 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9735 22:53:14.995404 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9736 22:53:15.001887 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9737 22:53:15.005024 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9738 22:53:15.011677 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9739 22:53:15.015054 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9740 22:53:15.018639 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9741 22:53:15.021900 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9742 22:53:15.028523 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9743 22:53:15.032261 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9744 22:53:15.035274 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9745 22:53:15.038118 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9746 22:53:15.044744 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9747 22:53:15.048242 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9748 22:53:15.051557 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9749 22:53:15.054846 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9750 22:53:15.061607 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9751 22:53:15.064824 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9752 22:53:15.068096 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9753 22:53:15.074554 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9754 22:53:15.078131 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9755 22:53:15.081310 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9756 22:53:15.087978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9757 22:53:15.091281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9758 22:53:15.097976 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9759 22:53:15.101321 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9760 22:53:15.107782 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9761 22:53:15.111119 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9762 22:53:15.114700 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9763 22:53:15.121220 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9764 22:53:15.124232 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9765 22:53:15.130889 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9766 22:53:15.134270 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9767 22:53:15.137463 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9768 22:53:15.144122 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9769 22:53:15.147325 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9770 22:53:15.153951 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9771 22:53:15.157277 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9772 22:53:15.160635 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9773 22:53:15.167268 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9774 22:53:15.171253 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9775 22:53:15.177459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9776 22:53:15.180890 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9777 22:53:15.184278 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9778 22:53:15.190389 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9779 22:53:15.193795 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9780 22:53:15.200743 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9781 22:53:15.203717 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9782 22:53:15.210874 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9783 22:53:15.213678 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9784 22:53:15.216941 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9785 22:53:15.223580 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9786 22:53:15.226993 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9787 22:53:15.233795 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9788 22:53:15.237187 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9789 22:53:15.240417 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9790 22:53:15.247216 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9791 22:53:15.250206 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9792 22:53:15.257254 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9793 22:53:15.260651 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9794 22:53:15.263818 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9795 22:53:15.270526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9796 22:53:15.273922 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9797 22:53:15.280288 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9798 22:53:15.283682 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9799 22:53:15.286946 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9800 22:53:15.293743 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9801 22:53:15.296891 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9802 22:53:15.303402 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9803 22:53:15.306751 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9804 22:53:15.310386 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9805 22:53:15.316413 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9806 22:53:15.319865 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9807 22:53:15.326615 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9808 22:53:15.329689 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9809 22:53:15.333403 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9810 22:53:15.339702 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9811 22:53:15.343145 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9812 22:53:15.349862 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9813 22:53:15.353213 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9814 22:53:15.359441 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9815 22:53:15.362802 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9816 22:53:15.369687 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9817 22:53:15.372877 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9818 22:53:15.376265 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9819 22:53:15.382752 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9820 22:53:15.386260 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9821 22:53:15.392561 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9822 22:53:15.396068 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9823 22:53:15.399436 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9824 22:53:15.406391 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9825 22:53:15.409467 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9826 22:53:15.416045 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9827 22:53:15.419395 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9828 22:53:15.425840 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9829 22:53:15.429058 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9830 22:53:15.432456 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9831 22:53:15.439030 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9832 22:53:15.442257 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9833 22:53:15.448989 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9834 22:53:15.452406 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9835 22:53:15.458998 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9836 22:53:15.462502 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9837 22:53:15.465648 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9838 22:53:15.472501 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9839 22:53:15.475484 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9840 22:53:15.482395 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9841 22:53:15.485765 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9842 22:53:15.488855 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9843 22:53:15.496059 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9844 22:53:15.499685 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9845 22:53:15.505848 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9846 22:53:15.508701 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9847 22:53:15.515558 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9848 22:53:15.518965 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9849 22:53:15.525481 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9850 22:53:15.528943 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9851 22:53:15.532275 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9852 22:53:15.539048 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9853 22:53:15.542226 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9854 22:53:15.548805 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9855 22:53:15.551937 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9856 22:53:15.558861 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9857 22:53:15.562148 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9858 22:53:15.565113 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9859 22:53:15.572058 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9860 22:53:15.575171 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9861 22:53:15.581726 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9862 22:53:15.585044 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9863 22:53:15.592080 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9864 22:53:15.594957 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9865 22:53:15.601591 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9866 22:53:15.604883 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9867 22:53:15.608256 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9868 22:53:15.615418 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9869 22:53:15.618587 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9870 22:53:15.624923 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9871 22:53:15.628144 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9872 22:53:15.634884 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9873 22:53:15.638051 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9874 22:53:15.641431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9875 22:53:15.648131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9876 22:53:15.651240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9877 22:53:15.658011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9878 22:53:15.661429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9879 22:53:15.667995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9880 22:53:15.671462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9881 22:53:15.678000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9882 22:53:15.681139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9883 22:53:15.688272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9884 22:53:15.691062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9885 22:53:15.698127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9886 22:53:15.701447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9887 22:53:15.707678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9888 22:53:15.711047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9889 22:53:15.714652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9890 22:53:15.721332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9891 22:53:15.724684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9892 22:53:15.731412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9893 22:53:15.734750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9894 22:53:15.741098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9895 22:53:15.744530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9896 22:53:15.750831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9897 22:53:15.754127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9898 22:53:15.760779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9899 22:53:15.764447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9900 22:53:15.771022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9901 22:53:15.774596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9902 22:53:15.780951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9903 22:53:15.784372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9904 22:53:15.791067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9905 22:53:15.794331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9906 22:53:15.800736 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9907 22:53:15.800817 INFO: [APUAPC] vio 0
9908 22:53:15.808103 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9909 22:53:15.811302 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9910 22:53:15.814625 INFO: [APUAPC] D0_APC_0: 0x400510
9911 22:53:15.817933 INFO: [APUAPC] D0_APC_1: 0x0
9912 22:53:15.821348 INFO: [APUAPC] D0_APC_2: 0x1540
9913 22:53:15.824215 INFO: [APUAPC] D0_APC_3: 0x0
9914 22:53:15.828525 INFO: [APUAPC] D1_APC_0: 0xffffffff
9915 22:53:15.831616 INFO: [APUAPC] D1_APC_1: 0xffffffff
9916 22:53:15.834484 INFO: [APUAPC] D1_APC_2: 0x3fffff
9917 22:53:15.837866 INFO: [APUAPC] D1_APC_3: 0x0
9918 22:53:15.840735 INFO: [APUAPC] D2_APC_0: 0xffffffff
9919 22:53:15.844162 INFO: [APUAPC] D2_APC_1: 0xffffffff
9920 22:53:15.847523 INFO: [APUAPC] D2_APC_2: 0x3fffff
9921 22:53:15.850898 INFO: [APUAPC] D2_APC_3: 0x0
9922 22:53:15.854291 INFO: [APUAPC] D3_APC_0: 0xffffffff
9923 22:53:15.857548 INFO: [APUAPC] D3_APC_1: 0xffffffff
9924 22:53:15.860587 INFO: [APUAPC] D3_APC_2: 0x3fffff
9925 22:53:15.864372 INFO: [APUAPC] D3_APC_3: 0x0
9926 22:53:15.867249 INFO: [APUAPC] D4_APC_0: 0xffffffff
9927 22:53:15.870532 INFO: [APUAPC] D4_APC_1: 0xffffffff
9928 22:53:15.873792 INFO: [APUAPC] D4_APC_2: 0x3fffff
9929 22:53:15.877211 INFO: [APUAPC] D4_APC_3: 0x0
9930 22:53:15.880413 INFO: [APUAPC] D5_APC_0: 0xffffffff
9931 22:53:15.883761 INFO: [APUAPC] D5_APC_1: 0xffffffff
9932 22:53:15.886840 INFO: [APUAPC] D5_APC_2: 0x3fffff
9933 22:53:15.886921 INFO: [APUAPC] D5_APC_3: 0x0
9934 22:53:15.890671 INFO: [APUAPC] D6_APC_0: 0xffffffff
9935 22:53:15.897014 INFO: [APUAPC] D6_APC_1: 0xffffffff
9936 22:53:15.900546 INFO: [APUAPC] D6_APC_2: 0x3fffff
9937 22:53:15.900627 INFO: [APUAPC] D6_APC_3: 0x0
9938 22:53:15.903481 INFO: [APUAPC] D7_APC_0: 0xffffffff
9939 22:53:15.906936 INFO: [APUAPC] D7_APC_1: 0xffffffff
9940 22:53:15.910164 INFO: [APUAPC] D7_APC_2: 0x3fffff
9941 22:53:15.913626 INFO: [APUAPC] D7_APC_3: 0x0
9942 22:53:15.916726 INFO: [APUAPC] D8_APC_0: 0xffffffff
9943 22:53:15.920187 INFO: [APUAPC] D8_APC_1: 0xffffffff
9944 22:53:15.923557 INFO: [APUAPC] D8_APC_2: 0x3fffff
9945 22:53:15.927037 INFO: [APUAPC] D8_APC_3: 0x0
9946 22:53:15.930610 INFO: [APUAPC] D9_APC_0: 0xffffffff
9947 22:53:15.933334 INFO: [APUAPC] D9_APC_1: 0xffffffff
9948 22:53:15.936996 INFO: [APUAPC] D9_APC_2: 0x3fffff
9949 22:53:15.940017 INFO: [APUAPC] D9_APC_3: 0x0
9950 22:53:15.943493 INFO: [APUAPC] D10_APC_0: 0xffffffff
9951 22:53:15.946607 INFO: [APUAPC] D10_APC_1: 0xffffffff
9952 22:53:15.950161 INFO: [APUAPC] D10_APC_2: 0x3fffff
9953 22:53:15.953522 INFO: [APUAPC] D10_APC_3: 0x0
9954 22:53:15.956766 INFO: [APUAPC] D11_APC_0: 0xffffffff
9955 22:53:15.960476 INFO: [APUAPC] D11_APC_1: 0xffffffff
9956 22:53:15.963050 INFO: [APUAPC] D11_APC_2: 0x3fffff
9957 22:53:15.966910 INFO: [APUAPC] D11_APC_3: 0x0
9958 22:53:15.970045 INFO: [APUAPC] D12_APC_0: 0xffffffff
9959 22:53:15.973260 INFO: [APUAPC] D12_APC_1: 0xffffffff
9960 22:53:15.976869 INFO: [APUAPC] D12_APC_2: 0x3fffff
9961 22:53:15.980254 INFO: [APUAPC] D12_APC_3: 0x0
9962 22:53:15.983624 INFO: [APUAPC] D13_APC_0: 0xffffffff
9963 22:53:15.987012 INFO: [APUAPC] D13_APC_1: 0xffffffff
9964 22:53:15.990474 INFO: [APUAPC] D13_APC_2: 0x3fffff
9965 22:53:15.993776 INFO: [APUAPC] D13_APC_3: 0x0
9966 22:53:15.996991 INFO: [APUAPC] D14_APC_0: 0xffffffff
9967 22:53:16.000464 INFO: [APUAPC] D14_APC_1: 0xffffffff
9968 22:53:16.003604 INFO: [APUAPC] D14_APC_2: 0x3fffff
9969 22:53:16.007010 INFO: [APUAPC] D14_APC_3: 0x0
9970 22:53:16.010157 INFO: [APUAPC] D15_APC_0: 0xffffffff
9971 22:53:16.013136 INFO: [APUAPC] D15_APC_1: 0xffffffff
9972 22:53:16.016645 INFO: [APUAPC] D15_APC_2: 0x3fffff
9973 22:53:16.019885 INFO: [APUAPC] D15_APC_3: 0x0
9974 22:53:16.023288 INFO: [APUAPC] APC_CON: 0x4
9975 22:53:16.026770 INFO: [NOCDAPC] D0_APC_0: 0x0
9976 22:53:16.029961 INFO: [NOCDAPC] D0_APC_1: 0x0
9977 22:53:16.033357 INFO: [NOCDAPC] D1_APC_0: 0x0
9978 22:53:16.036889 INFO: [NOCDAPC] D1_APC_1: 0xfff
9979 22:53:16.039573 INFO: [NOCDAPC] D2_APC_0: 0x0
9980 22:53:16.043086 INFO: [NOCDAPC] D2_APC_1: 0xfff
9981 22:53:16.046343 INFO: [NOCDAPC] D3_APC_0: 0x0
9982 22:53:16.049853 INFO: [NOCDAPC] D3_APC_1: 0xfff
9983 22:53:16.050319 INFO: [NOCDAPC] D4_APC_0: 0x0
9984 22:53:16.053218 INFO: [NOCDAPC] D4_APC_1: 0xfff
9985 22:53:16.056370 INFO: [NOCDAPC] D5_APC_0: 0x0
9986 22:53:16.059624 INFO: [NOCDAPC] D5_APC_1: 0xfff
9987 22:53:16.062753 INFO: [NOCDAPC] D6_APC_0: 0x0
9988 22:53:16.066099 INFO: [NOCDAPC] D6_APC_1: 0xfff
9989 22:53:16.069562 INFO: [NOCDAPC] D7_APC_0: 0x0
9990 22:53:16.072731 INFO: [NOCDAPC] D7_APC_1: 0xfff
9991 22:53:16.076088 INFO: [NOCDAPC] D8_APC_0: 0x0
9992 22:53:16.079455 INFO: [NOCDAPC] D8_APC_1: 0xfff
9993 22:53:16.079871 INFO: [NOCDAPC] D9_APC_0: 0x0
9994 22:53:16.082903 INFO: [NOCDAPC] D9_APC_1: 0xfff
9995 22:53:16.086081 INFO: [NOCDAPC] D10_APC_0: 0x0
9996 22:53:16.089149 INFO: [NOCDAPC] D10_APC_1: 0xfff
9997 22:53:16.092722 INFO: [NOCDAPC] D11_APC_0: 0x0
9998 22:53:16.095947 INFO: [NOCDAPC] D11_APC_1: 0xfff
9999 22:53:16.099376 INFO: [NOCDAPC] D12_APC_0: 0x0
10000 22:53:16.102396 INFO: [NOCDAPC] D12_APC_1: 0xfff
10001 22:53:16.106106 INFO: [NOCDAPC] D13_APC_0: 0x0
10002 22:53:16.108990 INFO: [NOCDAPC] D13_APC_1: 0xfff
10003 22:53:16.112149 INFO: [NOCDAPC] D14_APC_0: 0x0
10004 22:53:16.116067 INFO: [NOCDAPC] D14_APC_1: 0xfff
10005 22:53:16.118981 INFO: [NOCDAPC] D15_APC_0: 0x0
10006 22:53:16.122381 INFO: [NOCDAPC] D15_APC_1: 0xfff
10007 22:53:16.125383 INFO: [NOCDAPC] APC_CON: 0x4
10008 22:53:16.128783 INFO: [APUAPC] set_apusys_apc done
10009 22:53:16.132454 INFO: [DEVAPC] devapc_init done
10010 22:53:16.135683 INFO: GICv3 without legacy support detected.
10011 22:53:16.139088 INFO: ARM GICv3 driver initialized in EL3
10012 22:53:16.142394 INFO: Maximum SPI INTID supported: 639
10013 22:53:16.145167 INFO: BL31: Initializing runtime services
10014 22:53:16.151784 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10015 22:53:16.155100 INFO: SPM: enable CPC mode
10016 22:53:16.158691 INFO: mcdi ready for mcusys-off-idle and system suspend
10017 22:53:16.165111 INFO: BL31: Preparing for EL3 exit to normal world
10018 22:53:16.168471 INFO: Entry point address = 0x80000000
10019 22:53:16.171883 INFO: SPSR = 0x8
10020 22:53:16.176066
10021 22:53:16.176526
10022 22:53:16.176880
10023 22:53:16.179450 Starting depthcharge on Spherion...
10024 22:53:16.179913
10025 22:53:16.180257 Wipe memory regions:
10026 22:53:16.180572
10027 22:53:16.182858 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10028 22:53:16.183488 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10029 22:53:16.183907 Setting prompt string to ['asurada:']
10030 22:53:16.184295 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10031 22:53:16.184979 [0x00000040000000, 0x00000054600000)
10032 22:53:16.305083
10033 22:53:16.305646 [0x00000054660000, 0x00000080000000)
10034 22:53:16.565801
10035 22:53:16.566328 [0x000000821a7280, 0x000000ffe64000)
10036 22:53:17.310831
10037 22:53:17.311377 [0x00000100000000, 0x00000240000000)
10038 22:53:19.201476
10039 22:53:19.204751 Initializing XHCI USB controller at 0x11200000.
10040 22:53:20.242297
10041 22:53:20.245060 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10042 22:53:20.245147
10043 22:53:20.245211
10044 22:53:20.245271
10045 22:53:20.245556 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 22:53:20.345875 asurada: tftpboot 192.168.201.1 13683715/tftp-deploy-x7een8un/kernel/image.itb 13683715/tftp-deploy-x7een8un/kernel/cmdline
10048 22:53:20.345999 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 22:53:20.346099 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10050 22:53:20.350189 tftpboot 192.168.201.1 13683715/tftp-deploy-x7een8un/kernel/image.itp-deploy-x7een8un/kernel/cmdline
10051 22:53:20.350274
10052 22:53:20.350339 Waiting for link
10053 22:53:20.511706
10054 22:53:20.511825 R8152: Initializing
10055 22:53:20.511892
10056 22:53:20.514324 Version 6 (ocp_data = 5c30)
10057 22:53:20.514406
10058 22:53:20.517439 R8152: Done initializing
10059 22:53:20.517571
10060 22:53:20.517637 Adding net device
10061 22:53:22.610069
10062 22:53:22.610582 done.
10063 22:53:22.610953
10064 22:53:22.611291 MAC: 00:24:32:30:78:ff
10065 22:53:22.611615
10066 22:53:22.613337 Sending DHCP discover... done.
10067 22:53:22.613896
10068 22:53:33.141709 Waiting for reply... R8152: Bulk read error 0xffffffbf
10069 22:53:33.142292
10070 22:53:33.144823 Receive failed.
10071 22:53:33.145278
10072 22:53:33.145677 done.
10073 22:53:33.146025
10074 22:53:33.147564 Sending DHCP request... done.
10075 22:53:33.148021
10076 22:53:33.155108 Waiting for reply... done.
10077 22:53:33.155673
10078 22:53:33.156039 My ip is 192.168.201.21
10079 22:53:33.156380
10080 22:53:33.158095 The DHCP server ip is 192.168.201.1
10081 22:53:33.158553
10082 22:53:33.164888 TFTP server IP predefined by user: 192.168.201.1
10083 22:53:33.165440
10084 22:53:33.171834 Bootfile predefined by user: 13683715/tftp-deploy-x7een8un/kernel/image.itb
10085 22:53:33.172398
10086 22:53:33.172765 Sending tftp read request... done.
10087 22:53:33.174429
10088 22:53:33.181139 Waiting for the transfer...
10089 22:53:33.181729
10090 22:53:33.889094 00000000 ################################################################
10091 22:53:33.889708
10092 22:53:34.624721 00080000 ################################################################
10093 22:53:34.625316
10094 22:53:35.334713 00100000 ################################################################
10095 22:53:35.335268
10096 22:53:35.985958 00180000 ################################################################
10097 22:53:35.986446
10098 22:53:36.621559 00200000 ################################################################
10099 22:53:36.621690
10100 22:53:37.206096 00280000 ################################################################
10101 22:53:37.206234
10102 22:53:37.772545 00300000 ################################################################
10103 22:53:37.772733
10104 22:53:38.351504 00380000 ################################################################
10105 22:53:38.351641
10106 22:53:38.920242 00400000 ################################################################
10107 22:53:38.920410
10108 22:53:39.469998 00480000 ################################################################
10109 22:53:39.470145
10110 22:53:40.014112 00500000 ################################################################
10111 22:53:40.014273
10112 22:53:40.567580 00580000 ################################################################
10113 22:53:40.567731
10114 22:53:41.129827 00600000 ################################################################
10115 22:53:41.129975
10116 22:53:41.689154 00680000 ################################################################
10117 22:53:41.689286
10118 22:53:42.247034 00700000 ################################################################
10119 22:53:42.247182
10120 22:53:42.811450 00780000 ################################################################
10121 22:53:42.811591
10122 22:53:43.370580 00800000 ################################################################
10123 22:53:43.370726
10124 22:53:43.935196 00880000 ################################################################
10125 22:53:43.935334
10126 22:53:44.524452 00900000 ################################################################
10127 22:53:44.524616
10128 22:53:45.117641 00980000 ################################################################
10129 22:53:45.117785
10130 22:53:45.691137 00a00000 ################################################################
10131 22:53:45.691273
10132 22:53:46.275376 00a80000 ################################################################
10133 22:53:46.275528
10134 22:53:46.863587 00b00000 ################################################################
10135 22:53:46.863735
10136 22:53:47.449705 00b80000 ################################################################
10137 22:53:47.449861
10138 22:53:48.061797 00c00000 ################################################################
10139 22:53:48.062245
10140 22:53:48.690900 00c80000 ################################################################
10141 22:53:48.691049
10142 22:53:49.224423 00d00000 ################################################################
10143 22:53:49.224572
10144 22:53:49.763823 00d80000 ################################################################
10145 22:53:49.763976
10146 22:53:50.338543 00e00000 ################################################################
10147 22:53:50.338729
10148 22:53:50.944579 00e80000 ################################################################
10149 22:53:50.944759
10150 22:53:51.541496 00f00000 ################################################################
10151 22:53:51.541681
10152 22:53:52.122176 00f80000 ################################################################
10153 22:53:52.122321
10154 22:53:52.722897 01000000 ################################################################
10155 22:53:52.723044
10156 22:53:53.311479 01080000 ################################################################
10157 22:53:53.311623
10158 22:53:53.909081 01100000 ################################################################
10159 22:53:53.909226
10160 22:53:54.506324 01180000 ################################################################
10161 22:53:54.506469
10162 22:53:55.085661 01200000 ################################################################
10163 22:53:55.085833
10164 22:53:55.683931 01280000 ################################################################
10165 22:53:55.684080
10166 22:53:56.276037 01300000 ################################################################
10167 22:53:56.276183
10168 22:53:56.874656 01380000 ################################################################
10169 22:53:56.874826
10170 22:53:57.475567 01400000 ################################################################
10171 22:53:57.475712
10172 22:53:58.059099 01480000 ################################################################
10173 22:53:58.059248
10174 22:53:58.655635 01500000 ################################################################
10175 22:53:58.655781
10176 22:53:59.258649 01580000 ################################################################
10177 22:53:59.258798
10178 22:53:59.837633 01600000 ################################################################
10179 22:53:59.837777
10180 22:54:00.412052 01680000 ################################################################
10181 22:54:00.412202
10182 22:54:00.954854 01700000 ################################################################
10183 22:54:00.955000
10184 22:54:01.495874 01780000 ################################################################
10185 22:54:01.496023
10186 22:54:02.064631 01800000 ################################################################
10187 22:54:02.064825
10188 22:54:02.649422 01880000 ################################################################
10189 22:54:02.649626
10190 22:54:03.241935 01900000 ################################################################
10191 22:54:03.242093
10192 22:54:03.834960 01980000 ################################################################
10193 22:54:03.835117
10194 22:54:04.427259 01a00000 ################################################################
10195 22:54:04.427421
10196 22:54:05.026906 01a80000 ################################################################
10197 22:54:05.027064
10198 22:54:05.617552 01b00000 ################################################################
10199 22:54:05.617708
10200 22:54:06.210063 01b80000 ################################################################
10201 22:54:06.210228
10202 22:54:06.804537 01c00000 ################################################################
10203 22:54:06.804696
10204 22:54:07.394911 01c80000 ################################################################
10205 22:54:07.395069
10206 22:54:07.992429 01d00000 ################################################################
10207 22:54:07.992589
10208 22:54:08.591693 01d80000 ################################################################
10209 22:54:08.591869
10210 22:54:09.180217 01e00000 ################################################################
10211 22:54:09.180371
10212 22:54:09.757838 01e80000 ################################################################
10213 22:54:09.757995
10214 22:54:10.346431 01f00000 ################################################################
10215 22:54:10.346582
10216 22:54:10.947171 01f80000 ################################################################
10217 22:54:10.947320
10218 22:54:11.532608 02000000 ################################################################
10219 22:54:11.532768
10220 22:54:12.129939 02080000 ################################################################
10221 22:54:12.130086
10222 22:54:12.724560 02100000 ################################################################
10223 22:54:12.724711
10224 22:54:13.300168 02180000 ################################################################
10225 22:54:13.300320
10226 22:54:13.869214 02200000 ################################################################
10227 22:54:13.869366
10228 22:54:14.476315 02280000 ################################################################
10229 22:54:14.476472
10230 22:54:15.088141 02300000 ################################################################
10231 22:54:15.088296
10232 22:54:15.749002 02380000 ################################################################
10233 22:54:15.749478
10234 22:54:16.458228 02400000 ################################################################
10235 22:54:16.458750
10236 22:54:17.176623 02480000 ################################################################
10237 22:54:17.177170
10238 22:54:17.814877 02500000 ################################################################
10239 22:54:17.815393
10240 22:54:18.526384 02580000 ################################################################
10241 22:54:18.526876
10242 22:54:19.196620 02600000 ################################################################
10243 22:54:19.197116
10244 22:54:19.848905 02680000 ################################################################
10245 22:54:19.849447
10246 22:54:20.494821 02700000 ################################################################
10247 22:54:20.495321
10248 22:54:21.089062 02780000 ################################################################
10249 22:54:21.089194
10250 22:54:21.702011 02800000 ################################################################
10251 22:54:21.702167
10252 22:54:22.263726 02880000 ################################################################
10253 22:54:22.263864
10254 22:54:22.842091 02900000 ################################################################
10255 22:54:22.842625
10256 22:54:23.477797 02980000 ################################################################
10257 22:54:23.478169
10258 22:54:24.095502 02a00000 ################################################################
10259 22:54:24.095638
10260 22:54:24.703559 02a80000 ################################################################
10261 22:54:24.703697
10262 22:54:25.238126 02b00000 ################################################################
10263 22:54:25.238271
10264 22:54:25.768646 02b80000 ################################################################
10265 22:54:25.768778
10266 22:54:26.322070 02c00000 ################################################################
10267 22:54:26.322233
10268 22:54:26.870184 02c80000 ################################################################
10269 22:54:26.870337
10270 22:54:27.420061 02d00000 ################################################################
10271 22:54:27.420221
10272 22:54:27.964704 02d80000 ################################################################
10273 22:54:27.964841
10274 22:54:28.528259 02e00000 ################################################################
10275 22:54:28.528392
10276 22:54:29.085221 02e80000 ################################################################
10277 22:54:29.085357
10278 22:54:29.630977 02f00000 ################################################################
10279 22:54:29.631116
10280 22:54:30.178403 02f80000 ################################################################
10281 22:54:30.178549
10282 22:54:30.735782 03000000 ################################################################
10283 22:54:30.735921
10284 22:54:31.287400 03080000 ################################################################
10285 22:54:31.287654
10286 22:54:31.836328 03100000 ################################################################
10287 22:54:31.836466
10288 22:54:32.393498 03180000 ################################################################
10289 22:54:32.393643
10290 22:54:32.942913 03200000 ################################################################
10291 22:54:32.943050
10292 22:54:33.495496 03280000 ################################################################
10293 22:54:33.495638
10294 22:54:34.034260 03300000 ################################################################
10295 22:54:34.034443
10296 22:54:34.588852 03380000 ################################################################
10297 22:54:34.588986
10298 22:54:35.137993 03400000 ################################################################
10299 22:54:35.138128
10300 22:54:35.681196 03480000 ################################################################
10301 22:54:35.681360
10302 22:54:36.232313 03500000 ################################################################
10303 22:54:36.232503
10304 22:54:36.787301 03580000 ################################################################
10305 22:54:36.787465
10306 22:54:37.321478 03600000 ################################################################
10307 22:54:37.321650
10308 22:54:37.856329 03680000 ################################################################
10309 22:54:37.856462
10310 22:54:38.400727 03700000 ################################################################
10311 22:54:38.400861
10312 22:54:38.949652 03780000 ################################################################
10313 22:54:38.949788
10314 22:54:39.495950 03800000 ################################################################
10315 22:54:39.496088
10316 22:54:40.026955 03880000 ################################################################
10317 22:54:40.027094
10318 22:54:40.582175 03900000 ################################################################
10319 22:54:40.582312
10320 22:54:41.237276 03980000 ################################################################
10321 22:54:41.237924
10322 22:54:41.899570 03a00000 ################################################################
10323 22:54:41.899711
10324 22:54:42.579749 03a80000 ################################################################
10325 22:54:42.580280
10326 22:54:43.202856 03b00000 ################################################################
10327 22:54:43.203021
10328 22:54:43.786325 03b80000 ################################################################
10329 22:54:43.786501
10330 22:54:44.325052 03c00000 ################################################################
10331 22:54:44.325233
10332 22:54:44.991573 03c80000 ################################################################
10333 22:54:44.991731
10334 22:54:45.624056 03d00000 ################################################################
10335 22:54:45.624631
10336 22:54:46.270681 03d80000 ################################################################
10337 22:54:46.270834
10338 22:54:46.935892 03e00000 ################################################################
10339 22:54:46.936619
10340 22:54:47.666970 03e80000 ################################################################
10341 22:54:47.667107
10342 22:54:48.352248 03f00000 ################################################################
10343 22:54:48.352956
10344 22:54:49.064297 03f80000 ################################################################
10345 22:54:49.065108
10346 22:54:49.769755 04000000 ################################################################
10347 22:54:49.770297
10348 22:54:50.476516 04080000 ################################################################
10349 22:54:50.477058
10350 22:54:51.191679 04100000 ################################################################
10351 22:54:51.192208
10352 22:54:51.894106 04180000 ################################################################
10353 22:54:51.894697
10354 22:54:52.556756 04200000 ################################################################
10355 22:54:52.557048
10356 22:54:53.239312 04280000 ################################################################
10357 22:54:53.239822
10358 22:54:53.959060 04300000 ################################################################
10359 22:54:53.959560
10360 22:54:54.676271 04380000 ################################################################
10361 22:54:54.676771
10362 22:54:55.312086 04400000 ################################################################
10363 22:54:55.312224
10364 22:54:55.938719 04480000 ################################################################
10365 22:54:55.938866
10366 22:54:56.551137 04500000 ################################################################
10367 22:54:56.551822
10368 22:54:57.200121 04580000 ################################################################
10369 22:54:57.200740
10370 22:54:57.851589 04600000 ################################################################
10371 22:54:57.851736
10372 22:54:58.054214 04680000 ##################### done.
10373 22:54:58.054709
10374 22:54:58.058198 The bootfile was 74096122 bytes long.
10375 22:54:58.058659
10376 22:54:58.060660 Sending tftp read request... done.
10377 22:54:58.061078
10378 22:54:58.064757 Waiting for the transfer...
10379 22:54:58.065252
10380 22:54:58.065726 00000000 # done.
10381 22:54:58.066216
10382 22:54:58.071280 Command line loaded dynamically from TFTP file: 13683715/tftp-deploy-x7een8un/kernel/cmdline
10383 22:54:58.071821
10384 22:54:58.087705 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10385 22:54:58.088141
10386 22:54:58.088475 Loading FIT.
10387 22:54:58.088790
10388 22:54:58.091190 Image ramdisk-1 has 60987273 bytes.
10389 22:54:58.091648
10390 22:54:58.094652 Image fdt-1 has 47258 bytes.
10391 22:54:58.095162
10392 22:54:58.098329 Image kernel-1 has 13059555 bytes.
10393 22:54:58.098696
10394 22:54:58.104883 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10395 22:54:58.105317
10396 22:54:58.124378 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10397 22:54:58.124708
10398 22:54:58.127887 Choosing best match conf-1 for compat google,spherion-rev2.
10399 22:54:58.132386
10400 22:54:58.137961 Connected to device vid:did:rid of 1ae0:0028:00
10401 22:54:58.143388
10402 22:54:58.147194 tpm_get_response: command 0x17b, return code 0x0
10403 22:54:58.147497
10404 22:54:58.150456 ec_init: CrosEC protocol v3 supported (256, 248)
10405 22:54:58.155425
10406 22:54:58.158419 tpm_cleanup: add release locality here.
10407 22:54:58.158720
10408 22:54:58.158957 Shutting down all USB controllers.
10409 22:54:58.161591
10410 22:54:58.161891 Removing current net device
10411 22:54:58.162130
10412 22:54:58.168362 Exiting depthcharge with code 4 at timestamp: 131278263
10413 22:54:58.168665
10414 22:54:58.172000 LZMA decompressing kernel-1 to 0x821a6718
10415 22:54:58.172302
10416 22:54:58.174886 LZMA decompressing kernel-1 to 0x40000000
10417 22:54:59.786944
10418 22:54:59.787512 jumping to kernel
10419 22:54:59.789793 end: 2.2.4 bootloader-commands (duration 00:01:44) [common]
10420 22:54:59.790384 start: 2.2.5 auto-login-action (timeout 00:02:42) [common]
10421 22:54:59.791031 Setting prompt string to ['Linux version [0-9]']
10422 22:54:59.791491 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10423 22:54:59.792058 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10424 22:54:59.868732
10425 22:54:59.871752 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10426 22:54:59.875339 start: 2.2.5.1 login-action (timeout 00:02:42) [common]
10427 22:54:59.875830 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10428 22:54:59.876189 Setting prompt string to []
10429 22:54:59.876583 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10430 22:54:59.876947 Using line separator: #'\n'#
10431 22:54:59.877248 No login prompt set.
10432 22:54:59.877572 Parsing kernel messages
10433 22:54:59.877857 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10434 22:54:59.878347 [login-action] Waiting for messages, (timeout 00:02:42)
10435 22:54:59.878665 Waiting using forced prompt support (timeout 00:01:21)
10436 22:54:59.895360 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10437 22:54:59.898914 [ 0.000000] random: crng init done
10438 22:54:59.905187 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10439 22:54:59.908712 [ 0.000000] efi: UEFI not found.
10440 22:54:59.915181 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10441 22:54:59.921830 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10442 22:54:59.931374 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10443 22:54:59.941632 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10444 22:54:59.948033 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10445 22:54:59.954315 [ 0.000000] printk: bootconsole [mtk8250] enabled
10446 22:54:59.961005 [ 0.000000] NUMA: No NUMA configuration found
10447 22:54:59.967782 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10448 22:54:59.970955 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10449 22:54:59.974352 [ 0.000000] Zone ranges:
10450 22:54:59.981182 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10451 22:54:59.984557 [ 0.000000] DMA32 empty
10452 22:54:59.991069 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10453 22:54:59.994353 [ 0.000000] Movable zone start for each node
10454 22:54:59.997706 [ 0.000000] Early memory node ranges
10455 22:55:00.004037 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10456 22:55:00.010996 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10457 22:55:00.017244 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10458 22:55:00.024262 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10459 22:55:00.027627 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10460 22:55:00.037195 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10461 22:55:00.093460 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10462 22:55:00.099470 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10463 22:55:00.106378 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10464 22:55:00.109916 [ 0.000000] psci: probing for conduit method from DT.
10465 22:55:00.116121 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10466 22:55:00.119594 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10467 22:55:00.125967 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10468 22:55:00.129443 [ 0.000000] psci: SMC Calling Convention v1.2
10469 22:55:00.136354 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10470 22:55:00.139177 [ 0.000000] Detected VIPT I-cache on CPU0
10471 22:55:00.146074 [ 0.000000] CPU features: detected: GIC system register CPU interface
10472 22:55:00.152835 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10473 22:55:00.158811 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10474 22:55:00.165640 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10475 22:55:00.175206 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10476 22:55:00.181933 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10477 22:55:00.185444 [ 0.000000] alternatives: applying boot alternatives
10478 22:55:00.192126 [ 0.000000] Fallback order for Node 0: 0
10479 22:55:00.198403 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10480 22:55:00.201895 [ 0.000000] Policy zone: Normal
10481 22:55:00.215690 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10482 22:55:00.225059 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10483 22:55:00.237145 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10484 22:55:00.246881 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10485 22:55:00.253724 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10486 22:55:00.257219 <6>[ 0.000000] software IO TLB: area num 8.
10487 22:55:00.313902 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10488 22:55:00.463916 <6>[ 0.000000] Memory: 7904632K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 448136K reserved, 32768K cma-reserved)
10489 22:55:00.470152 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10490 22:55:00.476997 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10491 22:55:00.479815 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10492 22:55:00.486829 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10493 22:55:00.493145 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10494 22:55:00.496386 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10495 22:55:00.506479 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10496 22:55:00.513303 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10497 22:55:00.519453 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10498 22:55:00.526430 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10499 22:55:00.529548 <6>[ 0.000000] GICv3: 608 SPIs implemented
10500 22:55:00.533078 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10501 22:55:00.539510 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10502 22:55:00.542948 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10503 22:55:00.549814 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10504 22:55:00.562485 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10505 22:55:00.575683 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10506 22:55:00.582480 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10507 22:55:00.590232 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10508 22:55:00.603183 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10509 22:55:00.609735 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10510 22:55:00.616729 <6>[ 0.009192] Console: colour dummy device 80x25
10511 22:55:00.626746 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10512 22:55:00.633283 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10513 22:55:00.636846 <6>[ 0.029225] LSM: Security Framework initializing
10514 22:55:00.643430 <6>[ 0.034162] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10515 22:55:00.653320 <6>[ 0.042023] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10516 22:55:00.659893 <6>[ 0.051458] cblist_init_generic: Setting adjustable number of callback queues.
10517 22:55:00.666937 <6>[ 0.058901] cblist_init_generic: Setting shift to 3 and lim to 1.
10518 22:55:00.676631 <6>[ 0.065239] cblist_init_generic: Setting adjustable number of callback queues.
10519 22:55:00.683093 <6>[ 0.072666] cblist_init_generic: Setting shift to 3 and lim to 1.
10520 22:55:00.686403 <6>[ 0.079106] rcu: Hierarchical SRCU implementation.
10521 22:55:00.693358 <6>[ 0.084122] rcu: Max phase no-delay instances is 1000.
10522 22:55:00.699686 <6>[ 0.091141] EFI services will not be available.
10523 22:55:00.703195 <6>[ 0.096096] smp: Bringing up secondary CPUs ...
10524 22:55:00.711277 <6>[ 0.101179] Detected VIPT I-cache on CPU1
10525 22:55:00.717455 <6>[ 0.101250] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10526 22:55:00.724101 <6>[ 0.101281] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10527 22:55:00.727522 <6>[ 0.101619] Detected VIPT I-cache on CPU2
10528 22:55:00.734196 <6>[ 0.101666] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10529 22:55:00.740811 <6>[ 0.101682] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10530 22:55:00.747282 <6>[ 0.101938] Detected VIPT I-cache on CPU3
10531 22:55:00.754071 <6>[ 0.101984] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10532 22:55:00.760915 <6>[ 0.101998] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10533 22:55:00.764021 <6>[ 0.102302] CPU features: detected: Spectre-v4
10534 22:55:00.770913 <6>[ 0.102309] CPU features: detected: Spectre-BHB
10535 22:55:00.774431 <6>[ 0.102314] Detected PIPT I-cache on CPU4
10536 22:55:00.780877 <6>[ 0.102374] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10537 22:55:00.787758 <6>[ 0.102391] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10538 22:55:00.793716 <6>[ 0.102687] Detected PIPT I-cache on CPU5
10539 22:55:00.800566 <6>[ 0.102751] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10540 22:55:00.807357 <6>[ 0.102767] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10541 22:55:00.810313 <6>[ 0.103049] Detected PIPT I-cache on CPU6
10542 22:55:00.817199 <6>[ 0.103115] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10543 22:55:00.823952 <6>[ 0.103131] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10544 22:55:00.830552 <6>[ 0.103429] Detected PIPT I-cache on CPU7
10545 22:55:00.836796 <6>[ 0.103495] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10546 22:55:00.843567 <6>[ 0.103511] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10547 22:55:00.847215 <6>[ 0.103560] smp: Brought up 1 node, 8 CPUs
10548 22:55:00.853928 <6>[ 0.244825] SMP: Total of 8 processors activated.
10549 22:55:00.856978 <6>[ 0.249745] CPU features: detected: 32-bit EL0 Support
10550 22:55:00.867124 <6>[ 0.255108] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10551 22:55:00.873670 <6>[ 0.263909] CPU features: detected: Common not Private translations
10552 22:55:00.876658 <6>[ 0.270384] CPU features: detected: CRC32 instructions
10553 22:55:00.883645 <6>[ 0.275736] CPU features: detected: RCpc load-acquire (LDAPR)
10554 22:55:00.890184 <6>[ 0.281733] CPU features: detected: LSE atomic instructions
10555 22:55:00.896645 <6>[ 0.287515] CPU features: detected: Privileged Access Never
10556 22:55:00.900135 <6>[ 0.293294] CPU features: detected: RAS Extension Support
10557 22:55:00.909944 <6>[ 0.298938] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10558 22:55:00.913364 <6>[ 0.306155] CPU: All CPU(s) started at EL2
10559 22:55:00.919626 <6>[ 0.310472] alternatives: applying system-wide alternatives
10560 22:55:00.928823 <6>[ 0.321302] devtmpfs: initialized
10561 22:55:00.944295 <6>[ 0.330176] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10562 22:55:00.950836 <6>[ 0.340139] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10563 22:55:00.957394 <6>[ 0.348374] pinctrl core: initialized pinctrl subsystem
10564 22:55:00.960281 <6>[ 0.355010] DMI not present or invalid.
10565 22:55:00.966787 <6>[ 0.359425] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10566 22:55:00.976904 <6>[ 0.366231] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10567 22:55:00.983353 <6>[ 0.373815] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10568 22:55:00.993335 <6>[ 0.382046] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10569 22:55:00.996814 <6>[ 0.390288] audit: initializing netlink subsys (disabled)
10570 22:55:01.006770 <5>[ 0.395983] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10571 22:55:01.013364 <6>[ 0.396678] thermal_sys: Registered thermal governor 'step_wise'
10572 22:55:01.019744 <6>[ 0.403948] thermal_sys: Registered thermal governor 'power_allocator'
10573 22:55:01.023117 <6>[ 0.410203] cpuidle: using governor menu
10574 22:55:01.029953 <6>[ 0.421161] NET: Registered PF_QIPCRTR protocol family
10575 22:55:01.036281 <6>[ 0.426637] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10576 22:55:01.043306 <6>[ 0.433740] ASID allocator initialised with 32768 entries
10577 22:55:01.046145 <6>[ 0.440310] Serial: AMBA PL011 UART driver
10578 22:55:01.056433 <4>[ 0.449021] Trying to register duplicate clock ID: 134
10579 22:55:01.114268 <6>[ 0.510382] KASLR enabled
10580 22:55:01.128597 <6>[ 0.518083] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10581 22:55:01.135405 <6>[ 0.525094] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10582 22:55:01.142276 <6>[ 0.531583] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10583 22:55:01.148681 <6>[ 0.538590] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10584 22:55:01.155551 <6>[ 0.545077] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10585 22:55:01.161778 <6>[ 0.552081] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10586 22:55:01.168795 <6>[ 0.558568] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10587 22:55:01.175064 <6>[ 0.565572] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10588 22:55:01.178605 <6>[ 0.573016] ACPI: Interpreter disabled.
10589 22:55:01.187429 <6>[ 0.579452] iommu: Default domain type: Translated
10590 22:55:01.193724 <6>[ 0.584567] iommu: DMA domain TLB invalidation policy: strict mode
10591 22:55:01.197138 <5>[ 0.591225] SCSI subsystem initialized
10592 22:55:01.203704 <6>[ 0.595473] usbcore: registered new interface driver usbfs
10593 22:55:01.210540 <6>[ 0.601204] usbcore: registered new interface driver hub
10594 22:55:01.213689 <6>[ 0.606756] usbcore: registered new device driver usb
10595 22:55:01.220768 <6>[ 0.612862] pps_core: LinuxPPS API ver. 1 registered
10596 22:55:01.230563 <6>[ 0.618056] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10597 22:55:01.233558 <6>[ 0.627398] PTP clock support registered
10598 22:55:01.236901 <6>[ 0.631638] EDAC MC: Ver: 3.0.0
10599 22:55:01.244429 <6>[ 0.636818] FPGA manager framework
10600 22:55:01.251005 <6>[ 0.640494] Advanced Linux Sound Architecture Driver Initialized.
10601 22:55:01.254687 <6>[ 0.647264] vgaarb: loaded
10602 22:55:01.261018 <6>[ 0.650422] clocksource: Switched to clocksource arch_sys_counter
10603 22:55:01.264437 <5>[ 0.656868] VFS: Disk quotas dquot_6.6.0
10604 22:55:01.271437 <6>[ 0.661055] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10605 22:55:01.274315 <6>[ 0.668242] pnp: PnP ACPI: disabled
10606 22:55:01.282891 <6>[ 0.674900] NET: Registered PF_INET protocol family
10607 22:55:01.292512 <6>[ 0.680489] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10608 22:55:01.304022 <6>[ 0.692795] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10609 22:55:01.313575 <6>[ 0.701609] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10610 22:55:01.320494 <6>[ 0.709577] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10611 22:55:01.330253 <6>[ 0.718276] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10612 22:55:01.337138 <6>[ 0.728026] TCP: Hash tables configured (established 65536 bind 65536)
10613 22:55:01.343432 <6>[ 0.734831] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10614 22:55:01.353378 <6>[ 0.742029] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10615 22:55:01.359295 <6>[ 0.749735] NET: Registered PF_UNIX/PF_LOCAL protocol family
10616 22:55:01.366064 <6>[ 0.755882] RPC: Registered named UNIX socket transport module.
10617 22:55:01.369727 <6>[ 0.762035] RPC: Registered udp transport module.
10618 22:55:01.375873 <6>[ 0.766968] RPC: Registered tcp transport module.
10619 22:55:01.382321 <6>[ 0.771899] RPC: Registered tcp NFSv4.1 backchannel transport module.
10620 22:55:01.385770 <6>[ 0.778565] PCI: CLS 0 bytes, default 64
10621 22:55:01.389250 <6>[ 0.782904] Unpacking initramfs...
10622 22:55:01.413275 <6>[ 0.802556] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10623 22:55:01.423039 <6>[ 0.811217] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10624 22:55:01.426581 <6>[ 0.820065] kvm [1]: IPA Size Limit: 40 bits
10625 22:55:01.433224 <6>[ 0.824590] kvm [1]: GICv3: no GICV resource entry
10626 22:55:01.436271 <6>[ 0.829612] kvm [1]: disabling GICv2 emulation
10627 22:55:01.442939 <6>[ 0.834295] kvm [1]: GIC system register CPU interface enabled
10628 22:55:01.446123 <6>[ 0.840462] kvm [1]: vgic interrupt IRQ18
10629 22:55:01.452806 <6>[ 0.844812] kvm [1]: VHE mode initialized successfully
10630 22:55:01.459786 <5>[ 0.851317] Initialise system trusted keyrings
10631 22:55:01.465990 <6>[ 0.856158] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10632 22:55:01.473764 <6>[ 0.866176] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10633 22:55:01.480855 <5>[ 0.872547] NFS: Registering the id_resolver key type
10634 22:55:01.483882 <5>[ 0.877846] Key type id_resolver registered
10635 22:55:01.490516 <5>[ 0.882260] Key type id_legacy registered
10636 22:55:01.496996 <6>[ 0.886540] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10637 22:55:01.504027 <6>[ 0.893461] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10638 22:55:01.510437 <6>[ 0.901159] 9p: Installing v9fs 9p2000 file system support
10639 22:55:01.546030 <5>[ 0.938420] Key type asymmetric registered
10640 22:55:01.549584 <5>[ 0.942750] Asymmetric key parser 'x509' registered
10641 22:55:01.559352 <6>[ 0.947914] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10642 22:55:01.562699 <6>[ 0.955548] io scheduler mq-deadline registered
10643 22:55:01.566058 <6>[ 0.960315] io scheduler kyber registered
10644 22:55:01.585004 <6>[ 0.977259] EINJ: ACPI disabled.
10645 22:55:01.617557 <4>[ 1.003220] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10646 22:55:01.627920 <4>[ 1.013883] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10647 22:55:01.642728 <6>[ 1.034861] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10648 22:55:01.650740 <6>[ 1.042956] printk: console [ttyS0] disabled
10649 22:55:01.678809 <6>[ 1.067585] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10650 22:55:01.685488 <6>[ 1.077058] printk: console [ttyS0] enabled
10651 22:55:01.688612 <6>[ 1.077058] printk: console [ttyS0] enabled
10652 22:55:01.695321 <6>[ 1.085956] printk: bootconsole [mtk8250] disabled
10653 22:55:01.698672 <6>[ 1.085956] printk: bootconsole [mtk8250] disabled
10654 22:55:01.705457 <6>[ 1.097013] SuperH (H)SCI(F) driver initialized
10655 22:55:01.708734 <6>[ 1.102279] msm_serial: driver initialized
10656 22:55:01.722110 <6>[ 1.111180] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10657 22:55:01.732321 <6>[ 1.119727] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10658 22:55:01.738858 <6>[ 1.128269] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10659 22:55:01.748792 <6>[ 1.136897] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10660 22:55:01.758499 <6>[ 1.145603] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10661 22:55:01.765299 <6>[ 1.154318] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10662 22:55:01.775031 <6>[ 1.162857] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10663 22:55:01.781404 <6>[ 1.171655] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10664 22:55:01.791287 <6>[ 1.180198] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10665 22:55:01.800674 <6>[ 1.195953] loop: module loaded
10666 22:55:01.809459 <6>[ 1.201865] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10667 22:55:01.832984 <4>[ 1.225121] mtk-pmic-keys: Failed to locate of_node [id: -1]
10668 22:55:01.839703 <6>[ 1.231902] megasas: 07.719.03.00-rc1
10669 22:55:01.848849 <6>[ 1.241335] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10670 22:55:01.861470 <6>[ 1.253794] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10671 22:55:01.878442 <6>[ 1.270509] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10672 22:55:01.934752 <6>[ 1.320504] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10673 22:55:04.074920 <6>[ 3.467649] Freeing initrd memory: 59552K
10674 22:55:04.087083 <6>[ 3.479244] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10675 22:55:04.098003 <6>[ 3.490100] tun: Universal TUN/TAP device driver, 1.6
10676 22:55:04.101067 <6>[ 3.496150] thunder_xcv, ver 1.0
10677 22:55:04.104386 <6>[ 3.499654] thunder_bgx, ver 1.0
10678 22:55:04.107882 <6>[ 3.503146] nicpf, ver 1.0
10679 22:55:04.118296 <6>[ 3.507151] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10680 22:55:04.121261 <6>[ 3.514627] hns3: Copyright (c) 2017 Huawei Corporation.
10681 22:55:04.127991 <6>[ 3.520212] hclge is initializing
10682 22:55:04.131377 <6>[ 3.523794] e1000: Intel(R) PRO/1000 Network Driver
10683 22:55:04.137781 <6>[ 3.528923] e1000: Copyright (c) 1999-2006 Intel Corporation.
10684 22:55:04.141165 <6>[ 3.534935] e1000e: Intel(R) PRO/1000 Network Driver
10685 22:55:04.148115 <6>[ 3.540150] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10686 22:55:04.154957 <6>[ 3.546338] igb: Intel(R) Gigabit Ethernet Network Driver
10687 22:55:04.161433 <6>[ 3.551988] igb: Copyright (c) 2007-2014 Intel Corporation.
10688 22:55:04.167685 <6>[ 3.557823] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10689 22:55:04.174497 <6>[ 3.564342] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10690 22:55:04.177719 <6>[ 3.570798] sky2: driver version 1.30
10691 22:55:04.184482 <6>[ 3.575717] usbcore: registered new device driver r8152-cfgselector
10692 22:55:04.190628 <6>[ 3.582249] usbcore: registered new interface driver r8152
10693 22:55:04.197716 <6>[ 3.588060] VFIO - User Level meta-driver version: 0.3
10694 22:55:04.204035 <6>[ 3.596286] usbcore: registered new interface driver usb-storage
10695 22:55:04.211050 <6>[ 3.602724] usbcore: registered new device driver onboard-usb-hub
10696 22:55:04.219774 <6>[ 3.611854] mt6397-rtc mt6359-rtc: registered as rtc0
10697 22:55:04.229027 <6>[ 3.617311] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:55:05 UTC (1715122505)
10698 22:55:04.232593 <6>[ 3.626873] i2c_dev: i2c /dev entries driver
10699 22:55:04.249418 <6>[ 3.638591] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10700 22:55:04.256424 <4>[ 3.647315] cpu cpu0: supply cpu not found, using dummy regulator
10701 22:55:04.262748 <4>[ 3.653736] cpu cpu1: supply cpu not found, using dummy regulator
10702 22:55:04.269066 <4>[ 3.660143] cpu cpu2: supply cpu not found, using dummy regulator
10703 22:55:04.275941 <4>[ 3.666556] cpu cpu3: supply cpu not found, using dummy regulator
10704 22:55:04.282585 <4>[ 3.672952] cpu cpu4: supply cpu not found, using dummy regulator
10705 22:55:04.289200 <4>[ 3.679359] cpu cpu5: supply cpu not found, using dummy regulator
10706 22:55:04.295885 <4>[ 3.685755] cpu cpu6: supply cpu not found, using dummy regulator
10707 22:55:04.302191 <4>[ 3.692153] cpu cpu7: supply cpu not found, using dummy regulator
10708 22:55:04.321275 <6>[ 3.713799] cpu cpu0: EM: created perf domain
10709 22:55:04.324434 <6>[ 3.718740] cpu cpu4: EM: created perf domain
10710 22:55:04.332136 <6>[ 3.724324] sdhci: Secure Digital Host Controller Interface driver
10711 22:55:04.338510 <6>[ 3.730757] sdhci: Copyright(c) Pierre Ossman
10712 22:55:04.344810 <6>[ 3.735713] Synopsys Designware Multimedia Card Interface Driver
10713 22:55:04.351684 <6>[ 3.742346] sdhci-pltfm: SDHCI platform and OF driver helper
10714 22:55:04.355021 <6>[ 3.742380] mmc0: CQHCI version 5.10
10715 22:55:04.361577 <6>[ 3.752609] ledtrig-cpu: registered to indicate activity on CPUs
10716 22:55:04.367951 <6>[ 3.759723] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10717 22:55:04.374841 <6>[ 3.766782] usbcore: registered new interface driver usbhid
10718 22:55:04.378143 <6>[ 3.772604] usbhid: USB HID core driver
10719 22:55:04.384956 <6>[ 3.776802] spi_master spi0: will run message pump with realtime priority
10720 22:55:04.427849 <6>[ 3.813993] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10721 22:55:04.447531 <6>[ 3.830013] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10722 22:55:04.455015 <6>[ 3.844657] cros-ec-spi spi0.0: Chrome EC device registered
10723 22:55:04.457896 <6>[ 3.850697] mmc0: Command Queue Engine enabled
10724 22:55:04.464602 <6>[ 3.855453] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10725 22:55:04.470806 <6>[ 3.863231] mmcblk0: mmc0:0001 DA4128 116 GiB
10726 22:55:04.479351 <6>[ 3.871969] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10727 22:55:04.486739 <6>[ 3.879076] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10728 22:55:04.493103 <6>[ 3.885227] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10729 22:55:04.503220 <6>[ 3.885362] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10730 22:55:04.509497 <6>[ 3.891385] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10731 22:55:04.512947 <6>[ 3.901124] NET: Registered PF_PACKET protocol family
10732 22:55:04.519194 <6>[ 3.911660] 9pnet: Installing 9P2000 support
10733 22:55:04.522574 <5>[ 3.916228] Key type dns_resolver registered
10734 22:55:04.529010 <6>[ 3.921203] registered taskstats version 1
10735 22:55:04.532643 <5>[ 3.925581] Loading compiled-in X.509 certificates
10736 22:55:04.563286 <4>[ 3.949303] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10737 22:55:04.572959 <4>[ 3.960089] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10738 22:55:04.579871 <3>[ 3.970686] debugfs: File 'uA_load' in directory '/' already present!
10739 22:55:04.586163 <3>[ 3.977400] debugfs: File 'min_uV' in directory '/' already present!
10740 22:55:04.592839 <3>[ 3.984009] debugfs: File 'max_uV' in directory '/' already present!
10741 22:55:04.599072 <3>[ 3.990615] debugfs: File 'constraint_flags' in directory '/' already present!
10742 22:55:04.613302 <6>[ 4.006082] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10743 22:55:04.620396 <6>[ 4.013236] xhci-mtk 11200000.usb: xHCI Host Controller
10744 22:55:04.626961 <6>[ 4.018775] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10745 22:55:04.637335 <6>[ 4.026707] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10746 22:55:04.644350 <6>[ 4.036142] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10747 22:55:04.651296 <6>[ 4.042247] xhci-mtk 11200000.usb: xHCI Host Controller
10748 22:55:04.657376 <6>[ 4.047734] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10749 22:55:04.663989 <6>[ 4.055465] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10750 22:55:04.671319 <6>[ 4.063270] hub 1-0:1.0: USB hub found
10751 22:55:04.674105 <6>[ 4.067290] hub 1-0:1.0: 1 port detected
10752 22:55:04.684886 <6>[ 4.071561] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10753 22:55:04.687565 <6>[ 4.080310] hub 2-0:1.0: USB hub found
10754 22:55:04.690639 <6>[ 4.084332] hub 2-0:1.0: 1 port detected
10755 22:55:04.699762 <6>[ 4.092312] mtk-msdc 11f70000.mmc: Got CD GPIO
10756 22:55:04.711164 <6>[ 4.100119] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10757 22:55:04.717483 <6>[ 4.108149] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10758 22:55:04.727822 <4>[ 4.116048] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10759 22:55:04.737843 <6>[ 4.125571] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10760 22:55:04.744401 <6>[ 4.133648] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10761 22:55:04.750432 <6>[ 4.141768] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10762 22:55:04.760198 <6>[ 4.149697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10763 22:55:04.767138 <6>[ 4.157515] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10764 22:55:04.777359 <6>[ 4.165333] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10765 22:55:04.786854 <6>[ 4.175772] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10766 22:55:04.793369 <6>[ 4.184156] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10767 22:55:04.804387 <6>[ 4.192496] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10768 22:55:04.810674 <6>[ 4.200836] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10769 22:55:04.820579 <6>[ 4.209174] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10770 22:55:04.827244 <6>[ 4.217513] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10771 22:55:04.837143 <6>[ 4.225853] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10772 22:55:04.843475 <6>[ 4.234191] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10773 22:55:04.853326 <6>[ 4.242532] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10774 22:55:04.860235 <6>[ 4.250871] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10775 22:55:04.869979 <6>[ 4.259208] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10776 22:55:04.879437 <6>[ 4.267546] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10777 22:55:04.886281 <6>[ 4.275884] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10778 22:55:04.896084 <6>[ 4.284222] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10779 22:55:04.902873 <6>[ 4.292559] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10780 22:55:04.909192 <6>[ 4.301326] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10781 22:55:04.916209 <6>[ 4.308504] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10782 22:55:04.922405 <6>[ 4.315275] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10783 22:55:04.932730 <6>[ 4.322032] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10784 22:55:04.939093 <6>[ 4.328969] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10785 22:55:04.945916 <6>[ 4.335815] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10786 22:55:04.955824 <6>[ 4.344944] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10787 22:55:04.966105 <6>[ 4.354063] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10788 22:55:04.975742 <6>[ 4.363357] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10789 22:55:04.986082 <6>[ 4.372824] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10790 22:55:04.992247 <6>[ 4.382292] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10791 22:55:05.002661 <6>[ 4.391412] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10792 22:55:05.012298 <6>[ 4.400878] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10793 22:55:05.022451 <6>[ 4.409998] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10794 22:55:05.031926 <6>[ 4.419292] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10795 22:55:05.041798 <6>[ 4.429452] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10796 22:55:05.052655 <6>[ 4.441787] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10797 22:55:05.081956 <6>[ 4.470955] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10798 22:55:05.110387 <6>[ 4.502134] hub 2-1:1.0: USB hub found
10799 22:55:05.113003 <6>[ 4.506615] hub 2-1:1.0: 3 ports detected
10800 22:55:05.122008 <6>[ 4.514093] hub 2-1:1.0: USB hub found
10801 22:55:05.125187 <6>[ 4.518521] hub 2-1:1.0: 3 ports detected
10802 22:55:05.233487 <6>[ 4.622668] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10803 22:55:05.388107 <6>[ 4.780511] hub 1-1:1.0: USB hub found
10804 22:55:05.391351 <6>[ 4.784934] hub 1-1:1.0: 4 ports detected
10805 22:55:05.399845 <6>[ 4.792615] hub 1-1:1.0: USB hub found
10806 22:55:05.403442 <6>[ 4.796996] hub 1-1:1.0: 4 ports detected
10807 22:55:05.473691 <6>[ 4.862910] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10808 22:55:05.582296 <6>[ 4.971386] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10809 22:55:05.619154 <4>[ 5.008082] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10810 22:55:05.628580 <4>[ 5.017177] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10811 22:55:05.667430 <6>[ 5.059690] r8152 2-1.3:1.0 eth0: v1.12.13
10812 22:55:05.725339 <6>[ 5.114710] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10813 22:55:05.858143 <6>[ 5.250674] hub 1-1.4:1.0: USB hub found
10814 22:55:05.861078 <6>[ 5.255346] hub 1-1.4:1.0: 2 ports detected
10815 22:55:05.871210 <6>[ 5.263872] hub 1-1.4:1.0: USB hub found
10816 22:55:05.874664 <6>[ 5.268508] hub 1-1.4:1.0: 2 ports detected
10817 22:55:06.173615 <6>[ 5.562713] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10818 22:55:06.365562 <6>[ 5.754733] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10819 22:55:07.312624 <6>[ 6.705454] r8152 2-1.3:1.0 eth0: carrier on
10820 22:55:09.429404 <5>[ 6.726545] Sending DHCP requests .., OK
10821 22:55:09.436242 <6>[ 8.826900] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10822 22:55:09.439069 <6>[ 8.835206] IP-Config: Complete:
10823 22:55:09.452386 <6>[ 8.838706] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10824 22:55:09.459368 <6>[ 8.849454] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10825 22:55:09.468935 <6>[ 8.858076] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10826 22:55:09.472199 <6>[ 8.858086] nameserver0=192.168.201.1
10827 22:55:09.475602 <6>[ 8.870245] clk: Disabling unused clocks
10828 22:55:09.479081 <6>[ 8.875743] ALSA device list:
10829 22:55:09.485981 <6>[ 8.879011] No soundcards found.
10830 22:55:09.493099 <6>[ 8.886336] Freeing unused kernel memory: 8512K
10831 22:55:09.496347 <6>[ 8.891279] Run /init as init process
10832 22:55:09.526260 <6>[ 8.919723] NET: Registered PF_INET6 protocol family
10833 22:55:09.532703 <6>[ 8.926137] Segment Routing with IPv6
10834 22:55:09.535800 <6>[ 8.930115] In-situ OAM (IOAM) with IPv6
10835 22:55:09.579310 <30>[ 8.946238] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10836 22:55:09.585976 <30>[ 8.979296] systemd[1]: Detected architecture arm64.
10837 22:55:09.586415
10838 22:55:09.592857 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10839 22:55:09.593294
10840 22:55:09.593806
10841 22:55:09.605488 <30>[ 8.998793] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10842 22:55:09.716164 <30>[ 9.106215] systemd[1]: Queued start job for default target graphical.target.
10843 22:55:09.746921 <30>[ 9.136723] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10844 22:55:09.753535 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10845 22:55:09.753971
10846 22:55:09.773418 <30>[ 9.163219] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10847 22:55:09.783445 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10848 22:55:09.783871
10849 22:55:09.801746 <30>[ 9.191196] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10850 22:55:09.811420 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10851 22:55:09.811846
10852 22:55:09.830874 <30>[ 9.220213] systemd[1]: Created slice user.slice - User and Session Slice.
10853 22:55:09.836779 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10854 22:55:09.837199
10855 22:55:09.860887 <30>[ 9.247304] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10856 22:55:09.867304 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10857 22:55:09.870686
10858 22:55:09.888291 <30>[ 9.274847] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10859 22:55:09.894961 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10860 22:55:09.895385
10861 22:55:09.923040 <30>[ 9.303178] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10862 22:55:09.933253 <30>[ 9.323053] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10863 22:55:09.939732 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10864 22:55:09.940147
10865 22:55:09.957325 <30>[ 9.347164] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10866 22:55:09.964126 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10867 22:55:09.967016
10868 22:55:09.985818 <30>[ 9.375202] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10869 22:55:09.995429 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10870 22:55:09.995852
10871 22:55:10.009940 <30>[ 9.403243] systemd[1]: Reached target paths.target - Path Units.
10872 22:55:10.017336 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10873 22:55:10.019940
10874 22:55:10.037482 <30>[ 9.427069] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10875 22:55:10.044103 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10876 22:55:10.044623
10877 22:55:10.057496 <30>[ 9.450702] systemd[1]: Reached target slices.target - Slice Units.
10878 22:55:10.067621 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10879 22:55:10.068267
10880 22:55:10.082421 <30>[ 9.474788] systemd[1]: Reached target swap.target - Swaps.
10881 22:55:10.088308 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10882 22:55:10.088735
10883 22:55:10.109313 <30>[ 9.499262] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10884 22:55:10.119444 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10885 22:55:10.119875
10886 22:55:10.137935 <30>[ 9.527692] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10887 22:55:10.147568 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10888 22:55:10.148045
10889 22:55:10.167491 <30>[ 9.556925] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10890 22:55:10.177416 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10891 22:55:10.178012
10892 22:55:10.193693 <30>[ 9.583411] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10893 22:55:10.203589 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10894 22:55:10.204141
10895 22:55:10.225358 <30>[ 9.615343] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10896 22:55:10.232314 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10897 22:55:10.232966
10898 22:55:10.249732 <30>[ 9.639369] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10899 22:55:10.259075 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10900 22:55:10.259514
10901 22:55:10.277597 <30>[ 9.667188] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10902 22:55:10.287397 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10903 22:55:10.287923
10904 22:55:10.345201 <30>[ 9.734970] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10905 22:55:10.351635 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10906 22:55:10.352055
10907 22:55:10.372763 <30>[ 9.762926] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10908 22:55:10.379470 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10909 22:55:10.379998
10910 22:55:10.401397 <30>[ 9.791078] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10911 22:55:10.407797 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10912 22:55:10.408252
10913 22:55:10.431869 <30>[ 9.815192] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10914 22:55:10.468813 <30>[ 9.859070] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10915 22:55:10.478775 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10916 22:55:10.478864
10917 22:55:10.501624 <30>[ 9.891942] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10918 22:55:10.508270 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10919 22:55:10.508352
10920 22:55:10.533947 <30>[ 9.923859] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10921 22:55:10.546663 Starting [0;1;39mmodpr<6>[ 9.934652] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10922 22:55:10.550355 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10923 22:55:10.550439
10924 22:55:10.573975 <30>[ 9.964063] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10925 22:55:10.580403 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10926 22:55:10.580487
10927 22:55:10.640772 <30>[ 10.031221] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10928 22:55:10.647590 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10929 22:55:10.651015
10930 22:55:10.673553 <30>[ 10.063602] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10931 22:55:10.679806 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10932 22:55:10.679890
10933 22:55:10.709318 <30>[ 10.099445] systemd[1]: Starting systemd-journald.service - Journal Service...
10934 22:55:10.715976 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10935 22:55:10.716058
10936 22:55:10.735120 <30>[ 10.125440] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10937 22:55:10.741940 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10938 22:55:10.742037
10939 22:55:10.766927 <30>[ 10.153672] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10940 22:55:10.773138 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10941 22:55:10.773222
10942 22:55:10.796807 <30>[ 10.187087] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10943 22:55:10.806849 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10944 22:55:10.806933
10945 22:55:10.827372 <30>[ 10.217783] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10946 22:55:10.834372 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10947 22:55:10.834455
10948 22:55:10.857136 <30>[ 10.247495] systemd[1]: Started systemd-journald.service - Journal Service.
10949 22:55:10.863648 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10950 22:55:10.863731
10951 22:55:10.882758 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10952 22:55:10.882842
10953 22:55:10.902162 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10954 22:55:10.902246
10955 22:55:10.921287 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10956 22:55:10.921369
10957 22:55:10.941469 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10958 22:55:10.941573
10959 22:55:10.962023 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10960 22:55:10.962106
10961 22:55:10.982050 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10962 22:55:10.982134
10963 22:55:11.002325 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10964 22:55:11.002461
10965 22:55:11.022960 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10966 22:55:11.023044
10967 22:55:11.043639 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10968 22:55:11.043720
10969 22:55:11.063245 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10970 22:55:11.063327
10971 22:55:11.082202 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10972 22:55:11.082286
10973 22:55:11.102948 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10974 22:55:11.103030
10975 22:55:11.109658 See 'systemctl status systemd-remount-fs.service' for details.
10976 22:55:11.109738
10977 22:55:11.119760 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10978 22:55:11.120181
10979 22:55:11.139213 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10980 22:55:11.139658
10981 22:55:11.206398 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10982 22:55:11.206942
10983 22:55:11.227701 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10984 22:55:11.228178
10985 22:55:11.242003 <46>[ 10.631862] systemd-journald[194]: Received client request to flush runtime journal.
10986 22:55:11.253705 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10987 22:55:11.254187
10988 22:55:11.281112 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10989 22:55:11.281647
10990 22:55:11.306014 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10991 22:55:11.306441
10992 22:55:11.331042 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10993 22:55:11.331475
10994 22:55:11.354182 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10995 22:55:11.354665
10996 22:55:11.378353 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10997 22:55:11.378786
10998 22:55:11.402527 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10999 22:55:11.403005
11000 22:55:11.422078 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11001 22:55:11.422837
11002 22:55:11.485912 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11003 22:55:11.486363
11004 22:55:11.519011 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11005 22:55:11.519480
11006 22:55:11.537787 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11007 22:55:11.538223
11008 22:55:11.556753 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11009 22:55:11.557220
11010 22:55:11.597260 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11011 22:55:11.597729
11012 22:55:11.617782 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11013 22:55:11.618221
11014 22:55:11.639863 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11015 22:55:11.640312
11016 22:55:11.690271 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11017 22:55:11.690724
11018 22:55:11.718986 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11019 22:55:11.719405
11020 22:55:11.740650 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11021 22:55:11.741173
11022 22:55:11.799726 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11023 22:55:11.799875
11024 22:55:11.824462 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11025 22:55:11.824655
11026 22:55:11.843272 <46>[ 11.237004] systemd-journald[194]: Time jumped backwards, rotating.
11027 22:55:11.866322 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11028 22:55:11.866405
11029 22:55:11.957667 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11030 22:55:11.958162
11031 22:55:11.974206 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11032 22:55:11.974795
11033 22:55:11.993591 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11034 22:55:11.994149
11035 22:55:12.014407 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11036 22:55:12.014568
11037 22:55:12.037152 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11038 22:55:12.037248
11039 22:55:12.054666 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11040 22:55:12.054764
11041 22:55:12.066848 <3>[ 11.457016] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11042 22:55:12.073210 <3>[ 11.465361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11043 22:55:12.084079 <3>[ 11.474100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11044 22:55:12.090186 <4>[ 11.479323] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11045 22:55:12.100431 <3>[ 11.485167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11046 22:55:12.109976 [[0;32m OK [<3>[ 11.497784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11047 22:55:12.117018 0m] Reached targ<4>[ 11.504278] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11048 22:55:12.126636 <3>[ 11.507275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11049 22:55:12.133365 et [0;1;39msock<6>[ 11.516433] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11050 22:55:12.143124 ets.target[0m -<3>[ 11.523990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11051 22:55:12.153289 <3>[ 11.523995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11052 22:55:12.159622 <3>[ 11.529857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11053 22:55:12.169711 <6>[ 11.533049] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11054 22:55:12.169792 Socket Units.
11055 22:55:12.169856
11056 22:55:12.179272 <3>[ 11.558772] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11057 22:55:12.186305 <6>[ 11.567421] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11058 22:55:12.186390
11059 22:55:12.196130 <3>[ 11.576805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11060 22:55:12.202691 <3>[ 11.593666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11061 22:55:12.208848 <6>[ 11.599509] mc: Linux media interface: v0.10
11062 22:55:12.222152 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - B<3>[ 11.611086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11063 22:55:12.229031 <3>[ 11.620502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11064 22:55:12.231909 asic System.
11065 22:55:12.231989
11066 22:55:12.238538 <3>[ 11.628594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11067 22:55:12.248798 <3>[ 11.637970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11068 22:55:12.255001 <3>[ 11.646049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11069 22:55:12.265079 <6>[ 11.654803] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11070 22:55:12.274793 <6>[ 11.664534] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11071 22:55:12.281660 <3>[ 11.671954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11072 22:55:12.298204 <4>[ 11.688299] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11073 22:55:12.304765 <4>[ 11.688299] Fallback method does not support PEC.
11074 22:55:12.324754 Starting [0;1;39mdbus.service[0m - D-Bus System Messa<6>[ 11.717088] videodev: Linux video capture interface: v2.00
11075 22:55:12.324842 ge Bus...
11076 22:55:12.324906
11077 22:55:12.340977 <6>[ 11.731232] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11078 22:55:12.347621 <3>[ 11.731675] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11079 22:55:12.357387 <6>[ 11.731755] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11080 22:55:12.364209 <6>[ 11.738475] pci_bus 0000:00: root bus resource [bus 00-ff]
11081 22:55:12.371105 <6>[ 11.763260] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11082 22:55:12.381012 <3>[ 11.768930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11083 22:55:12.391170 <6>[ 11.770483] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11084 22:55:12.397528 <6>[ 11.789114] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11085 22:55:12.404020 <6>[ 11.791269] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11086 22:55:12.415057 <6>[ 11.795386] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11087 22:55:12.421737 <3>[ 11.810689] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11088 22:55:12.428450 <6>[ 11.811963] pci 0000:00:00.0: supports D1 D2
11089 22:55:12.435000 <6>[ 11.825185] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11090 22:55:12.441255 <6>[ 11.827001] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11091 22:55:12.448286 <6>[ 11.833232] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11092 22:55:12.454577 <6>[ 11.841992] remoteproc remoteproc0: scp is available
11093 22:55:12.461366 <6>[ 11.847876] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11094 22:55:12.464559 <6>[ 11.851803] Bluetooth: Core ver 2.22
11095 22:55:12.471374 <6>[ 11.851871] NET: Registered PF_BLUETOOTH protocol family
11096 22:55:12.478226 <6>[ 11.851873] Bluetooth: HCI device and connection manager initialized
11097 22:55:12.481731 <6>[ 11.851882] Bluetooth: HCI socket layer initialized
11098 22:55:12.485217 <6>[ 11.851887] Bluetooth: L2CAP socket layer initialized
11099 22:55:12.492747 <6>[ 11.851897] Bluetooth: SCO socket layer initialized
11100 22:55:12.496245 <6>[ 11.852983] remoteproc remoteproc0: powering up scp
11101 22:55:12.505782 <6>[ 11.859221] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11102 22:55:12.512696 <6>[ 11.862988] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11103 22:55:12.519703 <6>[ 11.863012] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11104 22:55:12.526430 <6>[ 11.863928] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11105 22:55:12.539460 <6>[ 11.865176] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11106 22:55:12.543018 <6>[ 11.865352] usbcore: registered new interface driver uvcvideo
11107 22:55:12.552666 <6>[ 11.868622] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11108 22:55:12.559984 <3>[ 11.883683] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11109 22:55:12.566889 <6>[ 11.885649] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11110 22:55:12.576596 <3>[ 11.889950] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11111 22:55:12.586234 <3>[ 11.891520] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11112 22:55:12.590220 <6>[ 11.895995] pci 0000:01:00.0: supports D1 D2
11113 22:55:12.597287 <6>[ 11.896674] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11114 22:55:12.600664 <6>[ 11.897307] usbcore: registered new interface driver btusb
11115 22:55:12.614014 <4>[ 11.897879] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11116 22:55:12.620345 <3>[ 11.897900] Bluetooth: hci0: Failed to load firmware file (-2)
11117 22:55:12.623949 <3>[ 11.897906] Bluetooth: hci0: Failed to set up firmware (-2)
11118 22:55:12.634127 <4>[ 11.897913] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11119 22:55:12.643964 <3>[ 11.913465] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11120 22:55:12.650391 <6>[ 11.917442] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11121 22:55:12.657843 <6>[ 11.926664] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11122 22:55:12.667629 <3>[ 11.959591] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11123 22:55:12.674492 <6>[ 11.966675] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11124 22:55:12.684771 <3>[ 11.995629] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11125 22:55:12.691879 <6>[ 12.000820] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11126 22:55:12.698567 <6>[ 12.000845] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11127 22:55:12.705484 <6>[ 12.000852] remoteproc remoteproc0: remote processor scp is now up
11128 22:55:12.712810 <6>[ 12.000972] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11129 22:55:12.722344 <6>[ 12.000985] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11130 22:55:12.729263 <6>[ 12.000998] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11131 22:55:12.736491 <6>[ 12.019025] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11132 22:55:12.746209 <6>[ 12.023419] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11133 22:55:12.749665 <6>[ 12.023432] pci 0000:00:00.0: PCI bridge to [bus 01]
11134 22:55:12.760282 <6>[ 12.037213] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11135 22:55:12.766875 <6>[ 12.042626] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11136 22:55:12.773393 <6>[ 12.042821] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11137 22:55:12.783459 <3>[ 12.053876] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11138 22:55:12.786900 <6>[ 12.056890] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11139 22:55:12.797785 Startin<6>[ 12.187710] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11140 22:55:12.800468 g [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11141 22:55:12.800886
11142 22:55:12.823858 <5>[ 12.214374] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11143 22:55:12.851513 <5>[ 12.241948] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11144 22:55:12.858029 <5>[ 12.249392] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11145 22:55:12.868412 <4>[ 12.257947] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11146 22:55:12.874981 <6>[ 12.266853] cfg80211: failed to load regulatory.db
11147 22:55:12.881612 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11148 22:55:12.882036
11149 22:55:12.907436 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11150 22:55:12.907983
11151 22:55:12.930683 <6>[ 12.320604] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11152 22:55:12.936880 <6>[ 12.328193] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11153 22:55:12.946868 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11154 22:55:12.947432
11155 22:55:12.962156 <6>[ 12.355290] mt7921e 0000:01:00.0: ASIC revision: 79610010
11156 22:55:13.001476 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11157 22:55:13.002152
11158 22:55:13.025142 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11159 22:55:13.025592
11160 22:55:13.045595 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11161 22:55:13.046023
11162 22:55:13.064359 <6>[ 12.454644] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11163 22:55:13.067801 <6>[ 12.454644]
11164 22:55:13.077282 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11165 22:55:13.077977
11166 22:55:13.122428 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11167 22:55:13.123023
11168 22:55:13.143714 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11169 22:55:13.144276
11170 22:55:13.161725 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11171 22:55:13.162309
11172 22:55:13.177070 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11173 22:55:13.177724
11174 22:55:13.197353 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11175 22:55:13.197851
11176 22:55:13.241321 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11177 22:55:13.241496
11178 22:55:13.265031 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11179 22:55:13.265629
11180 22:55:13.284650 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11181 22:55:13.285103
11182 22:55:13.331662 <6>[ 12.722094] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11183 22:55:13.358559 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11184 22:55:13.359016
11185 22:55:13.378854 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11186 22:55:13.379315
11187 22:55:13.403887 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11188 22:55:13.404317
11189 22:55:13.446057
11190 22:55:13.446469
11191 22:55:13.449449 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11192 22:55:13.449943
11193 22:55:13.452333 debian-bookworm-arm64 login: root (automatic login)
11194 22:55:13.452718
11195 22:55:13.453052
11196 22:55:13.466436 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
11197 22:55:13.466884
11198 22:55:13.473265 The programs included with the Debian GNU/Linux system are free software;
11199 22:55:13.479324 the exact distribution terms for each program are described in the
11200 22:55:13.482954 individual files in /usr/share/doc/*/copyright.
11201 22:55:13.483370
11202 22:55:13.489834 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11203 22:55:13.492659 permitted by applicable law.
11204 22:55:13.494021 Matched prompt #10: / #
11206 22:55:13.495056 Setting prompt string to ['/ #']
11207 22:55:13.495470 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11209 22:55:13.496459 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11210 22:55:13.496890 start: 2.2.6 expect-shell-connection (timeout 00:02:28) [common]
11211 22:55:13.497245 Setting prompt string to ['/ #']
11212 22:55:13.497617 Forcing a shell prompt, looking for ['/ #']
11214 22:55:13.548416 / #
11215 22:55:13.548903 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11216 22:55:13.549260 Waiting using forced prompt support (timeout 00:02:30)
11217 22:55:13.554502
11218 22:55:13.555254 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11219 22:55:13.555734 start: 2.2.7 export-device-env (timeout 00:02:28) [common]
11220 22:55:13.556188 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11221 22:55:13.556618 end: 2.2 depthcharge-retry (duration 00:02:32) [common]
11222 22:55:13.557047 end: 2 depthcharge-action (duration 00:02:32) [common]
11223 22:55:13.557475 start: 3 lava-test-retry (timeout 00:07:03) [common]
11224 22:55:13.557949 start: 3.1 lava-test-shell (timeout 00:07:03) [common]
11225 22:55:13.558312 Using namespace: common
11227 22:55:13.659323 / # #
11228 22:55:13.659836 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11229 22:55:13.665611 #
11230 22:55:13.666319 Using /lava-13683715
11232 22:55:13.767328 / # export SHELL=/bin/sh
11233 22:55:13.773473 export SHELL=/bin/sh
11235 22:55:13.874904 / # . /lava-13683715/environment
11236 22:55:13.881393 . /lava-13683715/environment
11238 22:55:13.982994 / # /lava-13683715/bin/lava-test-runner /lava-13683715/0
11239 22:55:13.983644 Test shell timeout: 10s (minimum of the action and connection timeout)
11240 22:55:13.989463 /lava-13683715/bin/lava-test-runner /lava-13683715/0
11241 22:55:14.016084 + export TESTRUN_ID=0_igt-kms-me<8>[ 13.408647] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 13683715_1.5.2.3.1>
11242 22:55:14.016764 Received signal: <STARTRUN> 0_igt-kms-mediatek 13683715_1.5.2.3.1
11243 22:55:14.017129 Starting test lava.0_igt-kms-mediatek (13683715_1.5.2.3.1)
11244 22:55:14.017555 Skipping test definition patterns.
11245 22:55:14.019361 diatek
11246 22:55:14.022458 + cd /lava-13683715/0/tests/0_igt-kms-mediatek
11247 22:55:14.022874 + cat uuid
11248 22:55:14.026000 + UUID=13683715_1.5.2.3.1
11249 22:55:14.026415 + set +x
11250 22:55:14.042538 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_re<8>[ 13.436157] <LAVA_SIGNAL_TESTSET START core_auth>
11251 22:55:14.043220 Received signal: <TESTSET> START core_auth
11252 22:55:14.043575 Starting test_set core_auth
11253 22:55:14.052345 ad kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11254 22:55:14.061871 <14>[ 13.455669] [IGT] core_auth: executing
11255 22:55:14.068658 IGT-Version: 1.2<14>[ 13.460025] [IGT] core_auth: starting subtest getclient-simple
11256 22:55:14.078458 8-ga44ebfe (aarc<14>[ 13.467639] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11257 22:55:14.081997 h64) (Linux: 6.1<14>[ 13.476143] [IGT] core_auth: exiting, ret=0
11258 22:55:14.085158 .90-cip20 aarch64)
11259 22:55:14.095125 Using IGT_SRANDOM=1715122514 for randomisati<8>[ 13.486521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11260 22:55:14.095544 on
11261 22:55:14.096138 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11263 22:55:14.098534 Starting subtest: getclient-simple
11264 22:55:14.102012 Opened device: /dev/dri/card0
11265 22:55:14.108316 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11266 22:55:14.114876 <14>[ 13.507996] [IGT] core_auth: executing
11267 22:55:14.121540 IGT-Version: 1.2<14>[ 13.512404] [IGT] core_auth: starting subtest getclient-master-drop
11268 22:55:14.131622 8-ga44ebfe (aarc<14>[ 13.520486] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11269 22:55:14.138467 h64) (Linux: 6.1<14>[ 13.529166] [IGT] core_auth: exiting, ret=0
11270 22:55:14.139043 .90-cip20 aarch64)
11271 22:55:14.148417 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11273 22:55:14.151504 Using IGT_SRANDOM=1715122514 for randomisati<8>[ 13.539388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11274 22:55:14.151926 on
11275 22:55:14.154872 Starting subtest: getclient-master-drop
11276 22:55:14.158026 Opened device: /dev/dri/card0
11277 22:55:14.161182 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11278 22:55:14.168422 <14>[ 13.561964] [IGT] core_auth: executing
11279 22:55:14.175098 IGT-Version: 1.2<14>[ 13.566691] [IGT] core_auth: starting subtest basic-auth
11280 22:55:14.181354 8-ga44ebfe (aarc<14>[ 13.573589] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11281 22:55:14.188082 <14>[ 13.581325] [IGT] core_auth: exiting, ret=0
11282 22:55:14.191511 h64) (Linux: 6.1.90-cip20 aarch64)
11283 22:55:14.201297 Using IGT_SRANDOM=1715122514 for randomisati<8>[ 13.592026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11284 22:55:14.201780 on
11285 22:55:14.202375 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11287 22:55:14.208494 Opened devic<6>[ 13.600089] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11288 22:55:14.211589 e: /dev/dri/card0
11289 22:55:14.212256 Starting subtest: basic-auth
11290 22:55:14.217678 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11291 22:55:14.220639 <14>[ 13.614050] [IGT] core_auth: executing
11292 22:55:14.227564 IGT-Version: 1.2<14>[ 13.619682] [IGT] core_auth: starting subtest many-magics
11293 22:55:14.231055 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11294 22:55:14.244150 Using IGT_SRANDOM=1715122514 for randomisati<14>[ 13.633732] [IGT] core_auth: finished subtest many-magics, SUCCESS
11295 22:55:14.244264 on
11296 22:55:14.247644 Opened devic<14>[ 13.641668] [IGT] core_auth: exiting, ret=0
11297 22:55:14.250830 e: /dev/dri/card0
11298 22:55:14.253651 Starting subtest: many-magics
11299 22:55:14.264097 Reopening device failed after <8>[ 13.653701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11300 22:55:14.264171 1020 opens
11301 22:55:14.264409 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11303 22:55:14.270111 [1mSubtest many-mag<8>[ 13.663886] <LAVA_SIGNAL_TESTSET STOP>
11304 22:55:14.270185 ics: SUCCESS (0.007s)[0m
11305 22:55:14.270414 Received signal: <TESTSET> STOP
11306 22:55:14.270481 Closing test_set core_auth
11307 22:55:14.318764 <14>[ 13.712545] [IGT] core_getclient: executing
11308 22:55:14.325449 IGT-Version: 1.2<14>[ 13.717536] [IGT] core_getclient: exiting, ret=0
11309 22:55:14.328352 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11310 22:55:14.338724 Using IGT_SR<8>[ 13.728365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11311 22:55:14.339347 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11313 22:55:14.342067 ANDOM=1715122514 for randomisation
11314 22:55:14.342538 Opened device: /dev/dri/card0
11315 22:55:14.345705 SUCCESS (0.006s)
11316 22:55:14.369940 <14>[ 13.763546] [IGT] core_getstats: executing
11317 22:55:14.376710 IGT-Version: 1.2<14>[ 13.768367] [IGT] core_getstats: exiting, ret=0
11318 22:55:14.380012 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11319 22:55:14.389674 Using IGT_SR<8>[ 13.779119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11320 22:55:14.390330 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11322 22:55:14.392906 ANDOM=1715122514 for randomisation
11323 22:55:14.393334 Opened device: /dev/dri/card0
11324 22:55:14.396320 SUCCESS (0.006s)
11325 22:55:14.420281 <14>[ 13.813730] [IGT] core_getversion: executing
11326 22:55:14.427029 IGT-Version: 1.2<14>[ 13.818902] [IGT] core_getversion: exiting, ret=0
11327 22:55:14.430205 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11328 22:55:14.439888 Using IGT_SR<8>[ 13.829562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11329 22:55:14.440543 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11331 22:55:14.443136 ANDOM=1715122514 for randomisation
11332 22:55:14.446412 Opened device: /dev/dri/card0
11333 22:55:14.446792 SUCCESS (0.006s)
11334 22:55:14.484477 <14>[ 13.877919] [IGT] core_setmaster_vs_auth: executing
11335 22:55:14.491291 IGT-Version: 1.2<14>[ 13.883592] [IGT] core_setmaster_vs_auth: exiting, ret=0
11336 22:55:14.497663 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11337 22:55:14.504153 Using IGT_SR<8>[ 13.896005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11338 22:55:14.505056 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11340 22:55:14.507296 ANDOM=1715122514 for randomisation
11341 22:55:14.510620 Opened device: /dev/dri/card0
11342 22:55:14.514165 SUCCESS (0.007s)
11343 22:55:14.527842 <8>[ 13.921482] <LAVA_SIGNAL_TESTSET START drm_read>
11344 22:55:14.528541 Received signal: <TESTSET> START drm_read
11345 22:55:14.529035 Starting test_set drm_read
11346 22:55:14.546258 <14>[ 13.939726] [IGT] drm_read: executing
11347 22:55:14.553056 IGT-Version: 1.2<14>[ 13.944391] [IGT] drm_read: exiting, ret=77
11348 22:55:14.556255 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11349 22:55:14.566149 Using IGT_SRANDOM=1715122514<8>[ 13.956420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11350 22:55:14.566573 for randomisation
11351 22:55:14.567146 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11353 22:55:14.569068 Opened device: /dev/dri/card0
11354 22:55:14.576009 No KMS driver or no outputs, pipes: 16, outputs: 0
11355 22:55:14.579280 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11356 22:55:14.595191 <14>[ 13.988454] [IGT] drm_read: executing
11357 22:55:14.601479 IGT-Version: 1.2<14>[ 13.993294] [IGT] drm_read: exiting, ret=77
11358 22:55:14.604722 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11359 22:55:14.615013 Using IGT_SRANDOM=1715122514 for randomisati<8>[ 14.006000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11360 22:55:14.615436 on
11361 22:55:14.616019 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11363 22:55:14.617984 Opened device: /dev/dri/card0
11364 22:55:14.624686 No KMS driver or no outputs, pipes: 16, outputs: 0
11365 22:55:14.627568 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11366 22:55:14.636416 <14>[ 14.030118] [IGT] drm_read: executing
11367 22:55:14.643169 IGT-Version: 1.2<14>[ 14.034733] [IGT] drm_read: exiting, ret=77
11368 22:55:14.646305 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11369 22:55:14.656563 Using IGT_SRANDOM=1715122514 for randomisati<8>[ 14.047280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11370 22:55:14.656980 on
11371 22:55:14.657613 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11373 22:55:14.659675 Opened device: /dev/dri/card0
11374 22:55:14.663061 No KMS driver or no outputs, pipes: 16, outputs: 0
11375 22:55:14.669343 [1mSubtest empty-block: SKIP (0.000s)[0m
11376 22:55:14.684724 <14>[ 14.078340] [IGT] drm_read: executing
11377 22:55:14.691742 IGT-Version: 1.2<14>[ 14.083256] [IGT] drm_read: exiting, ret=77
11378 22:55:14.694489 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11379 22:55:14.697765 Using IGT_SRANDOM=1715122514 for randomisation
11380 22:55:14.707932 Opened devic<8>[ 14.097622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11381 22:55:14.708539 e: /dev/dri/card0
11382 22:55:14.709328 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11384 22:55:14.714197 No KMS driver or no outputs, pipes: 16, outputs: 0
11385 22:55:14.717754 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11386 22:55:14.736256 <14>[ 14.129783] [IGT] drm_read: executing
11387 22:55:14.742633 IGT-Version: 1.2<14>[ 14.134685] [IGT] drm_read: exiting, ret=77
11388 22:55:14.745998 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11389 22:55:14.752931 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11391 22:55:14.756052 Using IGT_SR<8>[ 14.145484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11392 22:55:14.756470 ANDOM=1715122514 for randomisation
11393 22:55:14.759320 Opened device: /dev/dri/card0
11394 22:55:14.766168 No KMS driver or no outputs, pipes: 16, outputs: 0
11395 22:55:14.769048 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11396 22:55:14.775860 <14>[ 14.169141] [IGT] drm_read: executing
11397 22:55:14.779009 IGT-Version: 1.2<14>[ 14.173695] [IGT] drm_read: exiting, ret=77
11398 22:55:14.785423 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11399 22:55:14.789056 Using IGT_SRANDOM=1715122514 for randomisation
11400 22:55:14.799282 Opened devic<8>[ 14.187591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11401 22:55:14.799706 e: /dev/dri/card0
11402 22:55:14.800294 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11404 22:55:14.805612 No KMS driver or no outputs, pipes: 16, outputs: 0
11405 22:55:14.809104 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11406 22:55:14.816780 <14>[ 14.210439] [IGT] drm_read: executing
11407 22:55:14.823314 IGT-Version: 1.2<14>[ 14.214925] [IGT] drm_read: exiting, ret=77
11408 22:55:14.826773 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11409 22:55:14.836615 Using IGT_SRANDOM=1715122514 for randomisati<8>[ 14.227861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11410 22:55:14.837034 on
11411 22:55:14.837617 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11413 22:55:14.843726 Opened devic<8>[ 14.237692] <LAVA_SIGNAL_TESTSET STOP>
11414 22:55:14.844145 e: /dev/dri/card0
11415 22:55:14.844721 Received signal: <TESTSET> STOP
11416 22:55:14.845050 Closing test_set drm_read
11417 22:55:14.850185 No KMS driver or no outputs, pipes: 16, outputs: 0
11418 22:55:14.853243 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11419 22:55:14.874972 <8>[ 14.268895] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11420 22:55:14.875643 Received signal: <TESTSET> START kms_addfb_basic
11421 22:55:14.875991 Starting test_set kms_addfb_basic
11422 22:55:14.903068 <14>[ 14.296611] [IGT] kms_addfb_basic: executing
11423 22:55:14.915976 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch6<14>[ 14.306166] [IGT] kms_addfb_basic: starting subtest unused-handle
11424 22:55:14.916397 4)
11425 22:55:14.922822 Using IGT_SR<14>[ 14.313658] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11426 22:55:14.926371 ANDOM=1715122514 for randomisation
11427 22:55:14.929186 Opened device: /dev/dri/card0
11428 22:55:14.932548 Starting subtest: unused-handle
11429 22:55:14.939375 [1mSubtest <14>[ 14.331346] [IGT] kms_addfb_basic: exiting, ret=0
11430 22:55:14.942681 unused-handle: SUCCESS (0.000s)[0m
11431 22:55:14.952716 Test requirement not met in function igt_re<8>[ 14.343945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11432 22:55:14.953395 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11434 22:55:14.955523 quire_intel, file ../lib/drmtest.c:880:
11435 22:55:14.959114 Test requirement: is_intel_device(fd)
11436 22:55:14.965713 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11437 22:55:14.969133 Test requirement: is_intel_device(fd)
11438 22:55:14.975459 No KMS driver or no outputs, pipes: 16, outputs: 0
11439 22:55:14.978977 <14>[ 14.374084] [IGT] kms_addfb_basic: executing
11440 22:55:14.991910 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch6<14>[ 14.383659] [IGT] kms_addfb_basic: starting subtest unused-pitches
11441 22:55:14.992328 4)
11442 22:55:15.002344 Using IGT_SR<14>[ 14.391280] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11443 22:55:15.005038 ANDOM=1715122514 for randomisation
11444 22:55:15.008882 Opened device: /dev/dri/card0
11445 22:55:15.009301 Starting subtest: unused-pitches
11446 22:55:15.015308 [1mSubtest<14>[ 14.408844] [IGT] kms_addfb_basic: exiting, ret=0
11447 22:55:15.018300 unused-pitches: SUCCESS (0.000s)[0m
11448 22:55:15.028963 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11450 22:55:15.031689 Test requirement not met in function igt_<8>[ 14.421422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11451 22:55:15.035187 require_intel, file ../lib/drmtest.c:880:
11452 22:55:15.038289 Test requirement: is_intel_device(fd)
11453 22:55:15.045037 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11454 22:55:15.051542 Test requi<14>[ 14.442835] [IGT] kms_addfb_basic: executing
11455 22:55:15.052203 rement: is_intel_device(fd)
11456 22:55:15.061589 No KMS driver or no outputs, pipes:<14>[ 14.453275] [IGT] kms_addfb_basic: starting subtest unused-offsets
11457 22:55:15.065050 16, outputs: 0
11458 22:55:15.071672 <14>[ 14.461069] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11459 22:55:15.072145
11460 22:55:15.078057 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11461 22:55:15.084712 Using IGT_SRANDOM=171512251<14>[ 14.477759] [IGT] kms_addfb_basic: exiting, ret=0
11462 22:55:15.087774 5 for randomisation
11463 22:55:15.088239 Opened device: /dev/dri/card0
11464 22:55:15.097752 Starting subtest: unused-off<8>[ 14.489566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11465 22:55:15.098215 sets
11466 22:55:15.098842 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11468 22:55:15.104485 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11469 22:55:15.110769 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11470 22:55:15.117806 Test requirement: is_intel_device(fd<14>[ 14.512201] [IGT] kms_addfb_basic: executing
11471 22:55:15.118278 )
11472 22:55:15.130988 Test requirement not met in function igt_require_intel, file <14>[ 14.521579] [IGT] kms_addfb_basic: starting subtest unused-modifier
11473 22:55:15.140504 ../lib/drmtest.c<14>[ 14.529489] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11474 22:55:15.140986 :880:
11475 22:55:15.143919 Test requirement: is_intel_device(fd)
11476 22:55:15.153972 No KMS driver or no outputs, pipes: 16, outputs: 0<14>[ 14.546222] [IGT] kms_addfb_basic: exiting, ret=0
11477 22:55:15.154459
11478 22:55:15.161107 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11479 22:55:15.166897 Using IGT_<8>[ 14.558345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11480 22:55:15.167654 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11482 22:55:15.170367 SRANDOM=1715122515 for randomisation
11483 22:55:15.173654 Opened device: /dev/dri/card0
11484 22:55:15.176784 Starting subtest: unused-modifier
11485 22:55:15.180254 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11486 22:55:15.187117 Test requirement not <14>[ 14.580699] [IGT] kms_addfb_basic: executing
11487 22:55:15.193504 met in function igt_require_intel, file ../lib/drmtest.c:880:
11488 22:55:15.200352 T<14>[ 14.590271] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11489 22:55:15.210025 est requirement:<14>[ 14.598513] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11490 22:55:15.210443 is_intel_device(fd)
11491 22:55:15.223244 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 14.615406] [IGT] kms_addfb_basic: exiting, ret=77
11492 22:55:15.223724 t.c:880:
11493 22:55:15.226437 Test requirement: is_intel_device(fd)
11494 22:55:15.236476 No KMS driver or no outputs, pi<8>[ 14.627308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11495 22:55:15.237217 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11497 22:55:15.239539 pes: 16, outputs: 0
11498 22:55:15.242736 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11499 22:55:15.249610 Using IGT_SRANDOM=1715122515 for randomisation
11500 22:55:15.250021 Opened device: /dev/dri/card0
11501 22:55:15.256310 Starting subtest: clobberred-modifier
11502 22:55:15.266602 Test requirement not met in function igt_require_i915, file ../li<14>[ 14.658239] [IGT] kms_addfb_basic: executing
11503 22:55:15.267024 b/drmtest.c:885:
11504 22:55:15.269490 Test requirement: is_i915_device(fd)
11505 22:55:15.279368 [1mSubt<14>[ 14.668685] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11506 22:55:15.289244 est clobberred-m<14>[ 14.677070] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11507 22:55:15.289754 odifier: SKIP (0.000s)[0m
11508 22:55:15.296443 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11509 22:55:15.302799 <14>[ 14.695614] [IGT] kms_addfb_basic: exiting, ret=77
11510 22:55:15.306123 Test requirement: is_intel_device(fd)
11511 22:55:15.319358 Test requirement not met in function igt_<8>[ 14.708152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11512 22:55:15.320040 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11514 22:55:15.322886 require_intel, file ../lib/drmtest.c:880:
11515 22:55:15.326215 Test requirement: is_intel_device(fd)
11516 22:55:15.329573 No KMS driver or no outputs, pipes: 16, outputs: 0
11517 22:55:15.335922 IGT-Version: 1.28-ga44ebfe<14>[ 14.730239] [IGT] kms_addfb_basic: executing
11518 22:55:15.339002 (aarch64) (Linux: 6.1.90-cip20 aarch64)
11519 22:55:15.349197 Using IGT_SRANDOM=1715<14>[ 14.739795] [IGT] kms_addfb_basic: starting subtest legacy-format
11520 22:55:15.352534 122515 for randomisation
11521 22:55:15.352955 Opened device: /dev/dri/card0
11522 22:55:15.362330 Startin<14>[ 14.752931] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11523 22:55:15.365614 g subtest: invalid-smem-bo-on-discrete
11524 22:55:15.376373 Test requirement not met in function igt_require_intel, <14>[ 14.768200] [IGT] kms_addfb_basic: exiting, ret=0
11525 22:55:15.378804 file ../lib/drmtest.c:880:
11526 22:55:15.382326 Test requirement: is_intel_device(fd)
11527 22:55:15.388878 [1mSubtest i<8>[ 14.780244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11528 22:55:15.389686 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11530 22:55:15.392612 nvalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11531 22:55:15.402245 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11532 22:55:15.405270 Test requirement: is_intel_device(fd)
11533 22:55:15.411672 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11534 22:55:15.418744 Test requirement: <14>[ 14.810496] [IGT] kms_addfb_basic: executing
11535 22:55:15.419253 is_intel_device(fd)
11536 22:55:15.425057 No KMS driver or no outputs, pipes: 16, outputs: 0
11537 22:55:15.431994 IGT-Version: 1.28-ga44e<14>[ 14.823455] [IGT] kms_addfb_basic: starting subtest no-handle
11538 22:55:15.441743 bfe (aarch64) (L<14>[ 14.830643] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11539 22:55:15.442215 inux: 6.1.90-cip20 aarch64)
11540 22:55:15.448359 Using IGT_SRANDOM=1715122515 for randomisation
11541 22:55:15.451541 Ope<14>[ 14.845230] [IGT] kms_addfb_basic: exiting, ret=0
11542 22:55:15.454950 ned device: /dev/dri/card0
11543 22:55:15.458297 Starting subtest: legacy-format
11544 22:55:15.464604 Successfully fuzzed<8>[ 14.857377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11545 22:55:15.465336 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11547 22:55:15.468255 10000 {bpp, depth} variations
11548 22:55:15.471790 [1mSubtest legacy-format: SUCCESS (0.005s)[0m
11549 22:55:15.481625 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11550 22:55:15.488232 Test requirement: is_intel_<14>[ 14.880561] [IGT] kms_addfb_basic: executing
11551 22:55:15.489014 device(fd)
11552 22:55:15.500955 Test requirement not met in function igt_require_intel, file ../lib/<14>[ 14.892400] [IGT] kms_addfb_basic: starting subtest basic
11553 22:55:15.501484 drmtest.c:880:
11554 22:55:15.507819 <14>[ 14.898846] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11555 22:55:15.511068 Test requirement: is_intel_device(fd)
11556 22:55:15.520912 No KMS driver or no outputs, pipes: 16, o<14>[ 14.912509] [IGT] kms_addfb_basic: exiting, ret=0
11557 22:55:15.521468 utputs: 0
11558 22:55:15.527306 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11559 22:55:15.534109 U<8>[ 14.925341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11560 22:55:15.534790 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11562 22:55:15.537475 sing IGT_SRANDOM=1715122515 for randomisation
11563 22:55:15.540556 Opened device: /dev/dri/card0
11564 22:55:15.544261 Starting subtest: no-handle
11565 22:55:15.547620 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11566 22:55:15.554016 Test requirement not met<14>[ 14.946408] [IGT] kms_addfb_basic: executing
11567 22:55:15.557052 in function igt_require_intel, file ../lib/drmtest.c:880:
11568 22:55:15.567429 Test requirement: is<14>[ 14.958622] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11569 22:55:15.573981 _intel_device(fd<14>[ 14.965316] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11570 22:55:15.574401 )
11571 22:55:15.587363 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c<14>[ 14.979738] [IGT] kms_addfb_basic: exiting, ret=0
11572 22:55:15.587889 :880:
11573 22:55:15.590142 Test requirement: is_intel_device(fd)
11574 22:55:15.600068 No KMS driver or no outputs, pipes<8>[ 14.992462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11575 22:55:15.600900 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11577 22:55:15.603439 : 16, outputs: 0
11578 22:55:15.607052 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11579 22:55:15.613789 Using IGT_SRANDOM=1715122515 for randomisation
11580 22:55:15.617445 Opened device: /dev/dri/card0
11581 22:55:15.617993 Starting subtest: basic
11582 22:55:15.619867 [1mSubtest basic: SUCCESS (0.000s)[0m
11583 22:55:15.630425 Test requirement not met in function igt_<14>[ 15.022455] [IGT] kms_addfb_basic: executing
11584 22:55:15.633688 require_intel, file ../lib/drmtest.c:880:
11585 22:55:15.636849 Test requirement: is_intel_device(fd)
11586 22:55:15.643587 Test requireme<14>[ 15.035401] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11587 22:55:15.653668 nt not met in fu<14>[ 15.042782] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11588 22:55:15.656857 nction igt_require_intel, file ../lib/drmtest.c:880:
11589 22:55:15.663446 Test requirement: is_intel<14>[ 15.057949] [IGT] kms_addfb_basic: exiting, ret=0
11590 22:55:15.666988 _device(fd)
11591 22:55:15.669846 No KMS driver or no outputs, pipes: 16, outputs: 0
11592 22:55:15.679706 IGT-Version: 1.<8>[ 15.070135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11593 22:55:15.680525 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11595 22:55:15.682710 28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11596 22:55:15.686159 Using IGT_SRANDOM=1715122515 for randomisation
11597 22:55:15.689613 Opened device: /dev/dri/card0
11598 22:55:15.692615 Starting subtest: bad-pitch-0
11599 22:55:15.696343 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11600 22:55:15.705882 Test requirement not met in function igt_require_intel, file .<14>[ 15.100684] [IGT] kms_addfb_basic: executing
11601 22:55:15.709562 ./lib/drmtest.c:880:
11602 22:55:15.712989 Test requirement: is_intel_device(fd)
11603 22:55:15.722419 Test requirement not met in functio<14>[ 15.112981] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11604 22:55:15.729315 n igt_require_in<14>[ 15.120420] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11605 22:55:15.732671 tel, file ../lib/drmtest.c:880:
11606 22:55:15.736026 Test requirement: is_intel_device(fd)
11607 22:55:15.742144 No KMS d<14>[ 15.135263] [IGT] kms_addfb_basic: exiting, ret=0
11608 22:55:15.745971 river or no outputs, pipes: 16, outputs: 0
11609 22:55:15.755602 IGT-Version: 1.28-ga<8>[ 15.146396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11610 22:55:15.756433 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11612 22:55:15.758432 44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11613 22:55:15.761965 Using IGT_SRANDOM=1715122515 for randomisation
11614 22:55:15.765422 Opened device: /dev/dri/card0
11615 22:55:15.768272 Starting subtest: bad-pitch-32
11616 22:55:15.775620 [1mSubtest bad-p<14>[ 15.167529] [IGT] kms_addfb_basic: executing
11617 22:55:15.778870 itch-32: SUCCESS (0.000s)[0m
11618 22:55:15.788485 Test requirement not met in function igt_require_<14>[ 15.180131] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11619 22:55:15.798250 intel, file ../l<14>[ 15.186970] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11620 22:55:15.798798 ib/drmtest.c:880:
11621 22:55:15.801336 Test requirement: is_intel_device(fd)
11622 22:55:15.808412 Test requirement not m<14>[ 15.201392] [IGT] kms_addfb_basic: exiting, ret=0
11623 22:55:15.814889 et in function igt_require_intel, file ../lib/drmtest.c:880:
11624 22:55:15.821738 Test requirement: <8>[ 15.214357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11625 22:55:15.822574 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11627 22:55:15.825305 is_intel_device(fd)
11628 22:55:15.828310 No KMS driver or no outputs, pipes: 16, outputs: 0
11629 22:55:15.834805 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11630 22:55:15.838404 Using IGT_SRANDOM=1715122515 for randomisation
11631 22:55:15.841884 Opened device: /dev/dri/card0
11632 22:55:15.844600 Starting subtest: bad-pitch-63
11633 22:55:15.851094 [1mSubtest bad-pitc<14>[ 15.244816] [IGT] kms_addfb_basic: executing
11634 22:55:15.854232 h-63: SUCCESS (0.000s)[0m
11635 22:55:15.864783 Test requirement not met in function igt_require_intel, file ../lib/<14>[ 15.257265] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11636 22:55:15.868128 drmtest.c:880:
11637 22:55:15.874451 <14>[ 15.264836] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11638 22:55:15.877731 Test requirement: is_intel_device(fd)
11639 22:55:15.887933 Test requirement not met in function igt_<14>[ 15.279915] [IGT] kms_addfb_basic: exiting, ret=0
11640 22:55:15.890905 require_intel, file ../lib/drmtest.c:880:
11641 22:55:15.901226 Test requirement: is_intel_device(fd)<8>[ 15.292160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11642 22:55:15.901834
11643 22:55:15.902487 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11645 22:55:15.903899 No KMS driver or no outputs, pipes: 16, outputs: 0
11646 22:55:15.910694 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11647 22:55:15.914021 Using IGT_SRANDOM=1715122515 for randomisation
11648 22:55:15.917427 Opened device: /dev/dri/card0
11649 22:55:15.920459 Starting subtest: bad-pitch-128
11650 22:55:15.930278 [1mSubtest bad-pitch-128: SUCCESS (0.<14>[ 15.322628] [IGT] kms_addfb_basic: executing
11651 22:55:15.930838 000s)[0m
11652 22:55:15.937184 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11653 22:55:15.943379 T<14>[ 15.335207] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11654 22:55:15.953975 est requirement:<14>[ 15.342767] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11655 22:55:15.954537 is_intel_device(fd)
11656 22:55:15.963454 Test requirement not met in function igt_require_intel, fi<14>[ 15.357828] [IGT] kms_addfb_basic: exiting, ret=0
11657 22:55:15.966623 le ../lib/drmtest.c:880:
11658 22:55:15.970193 Test requirement: is_intel_device(fd)
11659 22:55:15.980035 No KMS driver o<8>[ 15.370234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11660 22:55:15.980934 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11662 22:55:15.983436 r no outputs, pipes: 16, outputs: 0
11663 22:55:15.986716 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11664 22:55:15.993359 Using IGT_SRANDOM=1715122515 for randomisation
11665 22:55:15.999907 Opened device: /dev/dri<14>[ 15.391664] [IGT] kms_addfb_basic: executing
11666 22:55:16.000461 /card0
11667 22:55:16.003670 Starting subtest: bad-pitch-256
11668 22:55:16.012999 [1mSubtest bad-pitch-256: SUCCESS (0.0<14>[ 15.404287] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11669 22:55:16.013644 00s)[0m
11670 22:55:16.019410 Test r<14>[ 15.411099] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11671 22:55:16.026794 equirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11672 22:55:16.032883 Te<14>[ 15.425578] [IGT] kms_addfb_basic: exiting, ret=0
11673 22:55:16.036254 st requirement: is_intel_device(fd)
11674 22:55:16.045886 Test requirement not met in function igt_re<8>[ 15.438467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11675 22:55:16.046624 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11677 22:55:16.049394 quire_intel, file ../lib/drmtest.c:880:
11678 22:55:16.052581 Test requirement: is_intel_device(fd)
11679 22:55:16.059583 No KMS driver or no outputs, pipes: 16, outputs: 0
11680 22:55:16.066100 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11681 22:55:16.072441 Using IGT_SRANDOM=171512<14>[ 15.465046] [IGT] kms_addfb_basic: executing
11682 22:55:16.072982 2515 for randomisation
11683 22:55:16.075817 Opened device: /dev/dri/card0
11684 22:55:16.086087 Starting subtest: bad-pit<14>[ 15.476590] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11685 22:55:16.086502 ch-1024
11686 22:55:16.092064 [1mSub<14>[ 15.483694] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11687 22:55:16.098960 test bad-pitch-1024: SUCCESS (0.000s)[0m
11688 22:55:16.105391 Test requirement not met in function <14>[ 15.498302] [IGT] kms_addfb_basic: exiting, ret=0
11689 22:55:16.108913 igt_require_intel, file ../lib/drmtest.c:880:
11690 22:55:16.119215 Test requirement: is_intel_device<8>[ 15.510676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11691 22:55:16.119766 (fd)
11692 22:55:16.120447 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11694 22:55:16.128847 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11695 22:55:16.132080 Test requirement: is_intel_device(fd)
11696 22:55:16.138947 No KMS driver or no outputs, pipes: 16, outputs<14>[ 15.533465] [IGT] kms_addfb_basic: executing
11697 22:55:16.139505 : 0
11698 22:55:16.145340 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11699 22:55:16.155182 Using IGT_SRANDOM=1715122515 for random<14>[ 15.547340] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11700 22:55:16.158325 isation
11701 22:55:16.165361 Opened <14>[ 15.555578] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11702 22:55:16.168595 device: /dev/dri/card0
11703 22:55:16.175002 Starting subtest: bad-pi<14>[ 15.568746] [IGT] kms_addfb_basic: exiting, ret=0
11704 22:55:16.175458 tch-999
11705 22:55:16.181892 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11706 22:55:16.188600 Test requirement not m<8>[ 15.579952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11707 22:55:16.189641 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11709 22:55:16.195578 et in function igt_require_intel, file ../lib/drmtest.c:880:
11710 22:55:16.198444 Test requirement: is_intel_device(fd)
11711 22:55:16.208357 Test requirement not met in function igt_require_intel, file ../lib/drmtest<14>[ 15.603837] [IGT] kms_addfb_basic: executing
11712 22:55:16.211764 .c:880:
11713 22:55:16.215197 Test requirement: is_intel_device(fd)
11714 22:55:16.218446 No KMS driver or no outputs, pipes: 16, outputs: 0
11715 22:55:16.224958 IGT-Version:<14>[ 15.617161] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11716 22:55:16.235225 1.28-ga44ebfe (<14>[ 15.625409] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11717 22:55:16.239197 aarch64) (Linux: 6.1.90-cip20 aarch64)
11718 22:55:16.245076 Using IG<14>[ 15.638130] [IGT] kms_addfb_basic: exiting, ret=0
11719 22:55:16.248123 T_SRANDOM=1715122516 for randomisation
11720 22:55:16.251483 Opened device: /dev/dri/card0
11721 22:55:16.258209 Starting <8>[ 15.649805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11722 22:55:16.259048 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11724 22:55:16.261054 subtest: bad-pitch-65536
11725 22:55:16.264784 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11726 22:55:16.274807 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11727 22:55:16.278136 Test requiremen<14>[ 15.672089] [IGT] kms_addfb_basic: executing
11728 22:55:16.281007 t: is_intel_device(fd)
11729 22:55:16.287773 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11730 22:55:16.294092 Test<14>[ 15.686128] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11731 22:55:16.304224 requirement: is<14>[ 15.694690] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11732 22:55:16.307578 _intel_device(fd)
11733 22:55:16.314498 No KMS driver or no outputs, <14>[ 15.707789] [IGT] kms_addfb_basic: exiting, ret=0
11734 22:55:16.317453 pipes: 16, outputs: 0
11735 22:55:16.327827 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20<8>[ 15.719334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11736 22:55:16.328634 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11738 22:55:16.331154 aarch64)
11739 22:55:16.334287 Using IGT_SRANDOM=1715122516 for randomisation
11740 22:55:16.337502 Opened device: /dev/dri/card0
11741 22:55:16.340533 Starting subtest: invalid-get-prop-any
11742 22:55:16.347690 [1mSubtest invalid-get-prop-any: SUCCESS (0.0<14>[ 15.742145] [IGT] kms_addfb_basic: executing
11743 22:55:16.350378 00s)[0m
11744 22:55:16.357257 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11745 22:55:16.363545 Test requirement: <14>[ 15.756396] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11746 22:55:16.373992 is_intel_device(<14>[ 15.764253] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11747 22:55:16.374412 fd)
11748 22:55:16.383707 Test requirement not met in function igt_re<14>[ 15.777097] [IGT] kms_addfb_basic: exiting, ret=0
11749 22:55:16.387194 quire_intel, file ../lib/drmtest.c:880:
11750 22:55:16.389917 Test requirement: is_intel_device(fd)
11751 22:55:16.396801 <8>[ 15.788760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11752 22:55:16.397547 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11754 22:55:16.403582 No KMS driver or no outputs, pipes: 16, outputs: 0
11755 22:55:16.406590 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11756 22:55:16.413096 Using IGT_SRANDOM=1715122516 for randomisation
11757 22:55:16.416538 Opened device: /dev/dri/card0
11758 22:55:16.416950 Starting subtest: invalid-get-prop
11759 22:55:16.426629 [1mSubtest invalid-get-prop: SUCCESS<14>[ 15.819606] [IGT] kms_addfb_basic: executing
11760 22:55:16.427128 (0.000s)[0m
11761 22:55:16.433248 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11762 22:55:16.436540 Test requirement: is_intel_device(fd)
11763 22:55:16.446577 Test r<14>[ 15.836545] [IGT] kms_addfb_basic: starting subtest master-rmfb
11764 22:55:16.453548 equirement not m<14>[ 15.843934] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11765 22:55:16.459488 et in function igt_require_intel<14>[ 15.854554] [IGT] kms_addfb_basic: exiting, ret=0
11766 22:55:16.463341 , file ../lib/drmtest.c:880:
11767 22:55:16.466255 Test requirement: is_intel_device(fd)
11768 22:55:16.476235 No KMS driv<8>[ 15.866767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11769 22:55:16.477091 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11771 22:55:16.479636 er or no outputs, pipes: 16, outputs: 0
11772 22:55:16.486125 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11773 22:55:16.489574 Using IGT_SRANDOM=1715122516 for randomisation
11774 22:55:16.496282 Opened device: /dev<14>[ 15.888823] [IGT] kms_addfb_basic: executing
11775 22:55:16.496834 /dri/card0
11776 22:55:16.499289 Starting subtest: invalid-set-prop-any
11777 22:55:16.506313 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11778 22:55:16.515908 Test requirement not met in function<14>[ 15.906061] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11779 22:55:16.525865 igt_require_int<14>[ 15.913917] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11780 22:55:16.532810 el, file ../lib/<14>[ 15.923653] [IGT] kms_addfb_basic: exiting, ret=0
11781 22:55:16.533373 drmtest.c:880:
11782 22:55:16.535694 Test requirement: is_intel_device(fd)
11783 22:55:16.545620 Test requirement not met <8>[ 15.936475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11784 22:55:16.546462 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11786 22:55:16.552607 in function igt_require_intel, file ../lib/drmtest.c:880:
11787 22:55:16.555620 Test requirement: is_intel_device(fd)
11788 22:55:16.558832 No KMS driver or no outputs, pipes: 16, outputs: 0
11789 22:55:16.565716 IGT-Version: 1.28-ga44ebfe<14>[ 15.959870] [IGT] kms_addfb_basic: executing
11790 22:55:16.568875 (aarch64) (Linux: 6.1.90-cip20 aarch64)
11791 22:55:16.575617 Using IGT_SRANDOM=1715122516 for randomisation
11792 22:55:16.576167 Opened device: /dev/dri/card0
11793 22:55:16.585358 Starting subtest: inval<14>[ 15.977054] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11794 22:55:16.585957 id-set-prop
11795 22:55:16.592406 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11796 22:55:16.599032 Test requiremen<14>[ 15.990274] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11797 22:55:16.605589 t not met in fun<14>[ 15.999385] [IGT] kms_addfb_basic: exiting, ret=98
11798 22:55:16.611907 ction igt_require_intel, file ../lib/drmtest.c:880:
11799 22:55:16.622297 Test requirement: is_intel_<8>[ 16.012267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11800 22:55:16.622867 device(fd)
11801 22:55:16.623518 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11803 22:55:16.628435 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11804 22:55:16.632124 Test requirement: is_intel_device(fd)
11805 22:55:16.638397 No KMS driver or no outputs, pipes: 16, outputs: 0
11806 22:55:22.935740 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11807 22:55:22.936397 Using IGT_SRANDOM<14>[ 16.043279] [IGT] kms_addfb_basic: executing
11808 22:55:22.936922 =1715122516 for randomisation
11809 22:55:22.937426 Opened device: /dev/dri/card0
11810 22:55:22.937860 Starting subtest: master-rmfb
11811 22:55:22.938188 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11812 22:55:22.938571 Test requirement not met in function<14>[ 16.062543] [IGT] kms_addfb_basic: exiting, ret=77
11813 22:55:22.938910 igt_require_intel, file ../lib/drmtest.c:880:
11814 22:55:22.939215 Test requirement: is_intel_device(fd)
11815 22:55:22.939519 Test requ<8>[ 16.075897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11816 22:55:22.939982 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11817 22:55:22.940317 Test requirement: is_intel_device(fd)
11818 22:55:22.940622 No KMS driver or no outputs, pipes: 16, outputs: 0
11819 22:55:22.940928 IGT-Versio<14>[ 16.100035] [IGT] kms_addfb_basic: executing
11820 22:55:22.941228 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11821 22:55:22.941566 Using IGT_SRANDOM=1715122516 for randomisation
11822 22:55:22.941909 Opened device: /dev/dri/card0
11823 22:55:22.942275 Starting subtest: addfb<14>[ 16.118464] [IGT] kms_addfb_basic: exiting, ret=77
11824 22:55:22.942558 25-modifier-no-flag
11825 22:55:22.942882 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11826 22:55:22.943158 <8>[ 16.131397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11827 22:55:22.943450
11828 22:55:22.943734 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11829 22:55:22.944205 Test requirement: is_intel_device(fd)
11830 22:55:22.944698 Test requirement not met in function<14>[ 16.152927] [IGT] kms_addfb_basic: executing
11831 22:55:22.945049 igt_require_intel, file ../lib/drmtest.c:880:
11832 22:55:22.945324 Test requirement: is_intel_device(fd)
11833 22:55:22.945679 No KMS driver or no outputs, pipes: 16, outputs: 0
11834 22:55:22.945991 IGT-Version: 1.28-ga4<14>[ 16.171141] [IGT] kms_addfb_basic: exiting, ret=77
11835 22:55:22.946375 4ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11836 22:55:22.946663 Using IGT_SRANDOM=1715122516 for <8>[ 16.183580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11837 22:55:22.947085 randomisation
11838 22:55:22.947506 Opened device: /dev/dri/card0
11839 22:55:22.947952 Starting subtest: addfb25-bad-modifier
11840 22:55:22.948409 (kms_addfb_basic:441) CRITICAL: Test assertion failure function addfb25_tests, file ../tes<14>[ 16.207703] [IGT] kms_addfb_basic: executing
11841 22:55:22.948861 ts/kms_addfb_basic.c:714:
11842 22:55:22.949183 (kms_addfb_basic:441) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0<14>[ 16.226096] [IGT] kms_addfb_basic: exiting, ret=77
11843 22:55:22.949471 ) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11844 22:55:22.949840 (kms_ad<8>[ 16.238790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11845 22:55:22.950119 dfb_basic:441) CRITICAL: error: 0 != -1
11846 22:55:22.950387 Stack trace:
11847 22:55:22.950780 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11848 22:55:22.951063 #1 [<unknown>+0xd3744358]
11849 22:55:22.951442 #2 [<unknown>+0xd3745fbc]<14>[ 16.260220] [IGT] kms_addfb_basic: executing
11850 22:55:22.951778
11851 22:55:22.952083 #3 [<unknown>+0xd374156c]
11852 22:55:22.952357 #4 [__libc_init_first+0x80]
11853 22:55:22.952624 #5 [__libc_start_main+0x98]
11854 22:55:22.952890 #6 [<unknown>+0xd37415b0]
11855 22:55:22.953156 Subtest addfb25-bad-modifier failed.
11856 22:55:22.953426 <14>[ 16.278186] [IGT] kms_addfb_basic: exiting, ret=77
11857 22:55:22.953738 **** DEBUG ****
11858 22:55:22.954013 (kms_addfb_basic:441) ioctl_wrappers-DEBUG: Test requirement pa<8>[ 16.291246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11859 22:55:22.954327 ssed: igt_has_fb_modifiers(fd)
11860 22:55:22.954602 (kms_addfb_basic:441) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11861 22:55:22.954873 (kms_addfb_<14>[ 16.313101] [IGT] kms_addfb_basic: executing
11862 22:55:22.955146 basic:441) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2<14>[ 16.331029] [IGT] kms_addfb_basic: exiting, ret=77
11863 22:55:22.955430 )))) << ((0+8)+8)))), (&f)) == -1
11864 22:55:22.955699 (kms_addfb_basic:441) CRITICAL: error: 0 != -<8>[ 16.343570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11865 22:55:22.955971 1
11866 22:55:22.956242 (kms_addfb_basic:441) igt_core-INFO: Stack trace:
11867 22:55:22.956559 (kms_addfb_basic:441) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11868 22:55:22.956836 (kms_addfb_basic:441) igt_core-INFO: #1 [<unknown>+0xd3744358]
11869 22:55:22.957107 (kms_addfb_basic:441) igt_core-INFO: #2 [<unknown>+0xd3745fbc]
11870 22:55:22.957375 <14>[ 16.374966] [IGT] kms_addfb_basic: executing
11871 22:55:22.957820 (kms_addfb_basic:441) igt_core-INFO: #3 [<unknown>+0xd374156c]
11872 22:55:22.958260 (kms_addfb_basic:441) igt_core-INFO: #4 [__libc_init_first+0x80]
11873 22:55:22.958982 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11875 22:55:22.960463 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11877 22:55:22.961641 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11879 22:55:22.962613 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11881 22:55:22.963286 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11883 22:55:22.963935 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11885 22:55:22.964678 (kms_addfb_basic:441) igt_core-INFO: #5 <14>[ 16.394388] [IGT] kms_addfb_basic: exiting, ret=77
11886 22:55:22.964920 [__libc_start_main+0x98]
11887 22:55:22.965134 (kms_addfb_basic:441) igt_core-INFO: #6 [<unknown>+0<8>[ 16.407659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11888 22:55:22.965343 xd37415b0]
11889 22:55:22.965570 **** END ****
11890 22:55:22.965778 [1mSubtest addfb25-bad-modifier: FAIL (0.006s)[0m
11891 22:55:22.965971 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11892 22:55:22.966121 Test requirement: is_intel<14>[ 16.431711] [IGT] kms_addfb_basic: executing
11893 22:55:22.966268 _device(fd)
11894 22:55:22.966415 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11895 22:55:22.966561 Test requirement: is_intel_device(fd)
11896 22:55:22.966714 No KMS driver or no outp<14>[ 16.449335] [IGT] kms_addfb_basic: exiting, ret=77
11897 22:55:22.966861 uts, pipes: 16, outputs: 0
11898 22:55:22.967008 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-<8>[ 16.462251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11899 22:55:22.967155 cip20 aarch64)
11900 22:55:22.967299 Using IGT_SRANDOM=1715122516 for randomisation
11901 22:55:22.967443 Opened device: /dev/dri/card0
11902 22:55:22.967589 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880<14>[ 16.483430] [IGT] kms_addfb_basic: executing
11903 22:55:22.967735 :
11904 22:55:22.967878 Test requirement: is_intel_device(fd)
11905 22:55:22.968022 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11906 22:55:22.968167 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11907 22:55:22.968312 Test requirement: is_intel_device(fd)
11908 22:55:22.968455 No KMS driver or no outputs, pipes: 16, outputs: 0
11909 22:55:22.968600 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11910 22:55:22.968744 Using IGT_SRANDOM=1715122516 for randomisation
11911 22:55:22.968887 Opened device: /dev/dri/card0
11912 22:55:22.969031 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11913 22:55:22.969223 Test requirement: is_intel_device(fd)
11914 22:55:22.969369 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11915 22:55:22.969535 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11916 22:55:22.969814 Test requirement: is_intel_device(fd)
11917 22:55:22.969987 No KMS driver or no outputs, pipes: 16, outputs: 0
11918 22:55:22.970135 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11919 22:55:22.970282 Using IGT_SRANDOM=1715122516 for randomisation
11920 22:55:22.970485 Opened device: /dev/dri/card0
11921 22:55:22.970633 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11922 22:55:22.970805 Test requirement: is_intel_device(fd)
11923 22:55:22.970962 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11924 22:55:22.971079 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11925 22:55:22.971196 Test requirement: is_intel_device(fd)
11926 22:55:22.971312 No KMS driver or no outputs, pipes: 16, outputs: 0
11927 22:55:22.971443 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11928 22:55:22.971575 Using IGT_SRANDOM=1715122516 for randomisation
11929 22:55:22.971706 Opened device: /dev/dri/card0
11930 22:55:22.971823 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11931 22:55:22.971939 Test requirement: is_intel_device(fd)
11932 22:55:22.972083 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11933 22:55:22.972202 Test requirement: is_intel_device(fd)
11934 22:55:22.972317 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11935 22:55:22.972433 No KMS driver or no outputs, pipes: 16, outputs: 0
11936 22:55:22.972567 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11937 22:55:22.972685 Using IGT_SRANDOM=1715122516 for randomisation
11938 22:55:22.972800 Opened device: /dev/dri/card0
11939 22:55:22.972916 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11940 22:55:22.973032 Test requirement: is_intel_device(fd)
11941 22:55:22.973147 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11942 22:55:22.973280 Test requirement: is_intel_device(fd)
11943 22:55:22.973397 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11944 22:55:22.973527 No KMS driver or no outputs, pipes: 16, outputs: 0
11945 22:55:22.973650 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11946 22:55:22.973768 Using IGT_SRANDOM=1715122516 for randomisation
11947 22:55:22.973900 Opened device: /dev/dri/card0
11948 22:55:22.974034 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11949 22:55:22.974153 Test requirement: is_intel_device(fd)
11950 22:55:22.974283 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11951 22:55:22.974402 Test requirement: is_intel_device(fd)
11952 22:55:22.974517 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11953 22:55:22.974631 No KMS driver or no outputs, pipes: 16, outputs: 0
11954 22:55:22.974748 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11955 22:55:22.974878 Using IGT_SRANDOM=1715122516 for randomisation
11956 22:55:22.975022 Opened device: /dev/dri/card0
11957 22:55:22.975358 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11959 22:55:22.975786 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11961 22:55:22.976191 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11962 22:55:22.976309 Test requirement: is_intel_device(fd)
11963 22:55:22.976415 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11964 22:55:22.976518 Test requirement: is_intel_device(fd)
11965 22:55:22.976617 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11966 22:55:22.976746 No KMS driver or no outputs, pipes: 16, outputs: 0
11967 22:55:22.976848 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11968 22:55:22.976947 Using IGT_SRANDOM=1715122517 for randomisation
11969 22:55:22.977045 Opened device: /dev/dri/card0
11970 22:55:22.977156 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11971 22:55:22.977256 Test requirement: is_intel_device(fd)
11972 22:55:22.977354 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11973 22:55:22.977452 Test requirement: is_intel_device(fd)
11974 22:55:22.977566 No KMS driver or no outputs, pipes: 16, outputs: 0
11975 22:55:22.977681 [1mSubtest size-max: SKIP (0.000s)[0m
11976 22:55:22.977781 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11977 22:55:22.977880 Using IGT_SRANDOM=1715122517 for randomisation
11978 22:55:22.977978 Opened device: /dev/dri/card0
11979 22:55:22.978075 Test requirement not met in function igt_require_intel, file ..<14>[ 16.834279] [IGT] kms_addfb_basic: exiting, ret=77
11980 22:55:22.978174 /lib/drmtest.c:880:
11981 22:55:22.978282 Test requirement: is_intel_device(fd)
11982 22:55:22.978391 Test requirement not<8>[ 16.846703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11983 22:55:22.978492 met in function igt_require_intel, file ../lib/drmtest.c:880:
11984 22:55:22.978602 Test requirement: is_intel_device(fd)
11985 22:55:22.978700 No KMS driver or no outputs, pipes: 16, outputs: 0
11986 22:55:22.978812 [1mSubtest too-wide: SKIP (0.000s)[0m
11987 22:55:22.978911 <14>[ 16.876985] [IGT] kms_addfb_basic: executing
11988 22:55:22.979009 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
11989 22:55:22.979107 Using IGT_SRANDOM=1715122517 for randomisation
11990 22:55:22.979204 Opened device: /dev/dri/card0
11991 22:55:22.979300 Test requirement<14>[ 16.895815] [IGT] kms_addfb_basic: exiting, ret=77
11992 22:55:22.979398 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11993 22:55:22.979496 Test requirement: is_intel_d<8>[ 16.909608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11994 22:55:22.979607 evice(fd)
11995 22:55:22.979717 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11996 22:55:22.979817 Test requirement: is_intel_device(fd)
11997 22:55:22.979913 No KMS driver or no outputs, pipes: 16, outputs: 0
11998 22:55:22.980011 [1mSubtest too-high: SKIP (0.000s)[0m
11999 22:55:22.980107 <14>[ 16.939849] [IGT] kms_addfb_basic: executing
12000 22:55:22.980218 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12001 22:55:22.980339 Using IGT_SRANDOM=1715122517 for randomisation
12002 22:55:22.980438 Opened device: /dev/dri/card0
12003 22:55:22.980535 Test requirement<14>[ 16.958658] [IGT] kms_addfb_basic: exiting, ret=77
12004 22:55:22.980634 not met in function igt_require_intel, file ../lib/drmtest.c:880:
12005 22:55:22.980731 Test requirement: is_intel_d<8>[ 16.972568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
12006 22:55:22.980854 evice(fd)
12007 22:55:22.980962 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12008 22:55:22.981046 Test requirement: is_intel_device(fd)
12009 22:55:22.981130 No KMS driver or no output<14>[ 16.993978] [IGT] kms_addfb_basic: executing
12010 22:55:22.981214 s, pipes: 16, outputs: 0
12011 22:55:22.981300 [1mSubtest bo-too-small: SKIP (0.000s)[0m
12012 22:55:22.981394 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12013 22:55:22.981479 Using IGT_SRANDOM=171<14>[ 17.011426] [IGT] kms_addfb_basic: exiting, ret=77
12014 22:55:22.981603 5122517 for randomisation
12015 22:55:22.981691 Opened device: /dev/dri/card0
12016 22:55:22.981775 Test requirement not m<8>[ 17.024373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
12017 22:55:22.981860 et in function igt_require_intel, file ../lib/drmtest.c:880:
12018 22:55:22.981955 Test requirement: is_intel_device(fd)
12019 22:55:22.982041 Test requirement not met in function igt_require_intel, file ../lib/drmtest<14>[ 17.045902] [IGT] kms_addfb_basic: executing
12020 22:55:22.982126 .c:880:
12021 22:55:22.982211 Test requirement: is_intel_device(fd)
12022 22:55:22.982294 No KMS driver or no outputs, pipes: 16, outputs: 0
12023 22:55:22.982378 [1mSubtest small-bo: SKIP (0.000s)[0m
12024 22:55:22.982461 IGT<14>[ 17.063945] [IGT] kms_addfb_basic: exiting, ret=77
12025 22:55:22.982555 -Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12026 22:55:22.982641 Using IGT_SRAND<8>[ 17.075486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
12027 22:55:22.982737 OM=1715122517 for randomisation
12028 22:55:22.982821 Opened device: /dev/dri/card0
12029 22:55:22.982905 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12030 22:55:22.983025 Test require<14>[ 17.097560] [IGT] kms_addfb_basic: executing
12031 22:55:22.983112 ment: is_intel_device(fd)
12032 22:55:22.983195 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12033 22:55:22.983279 Test requirement: is_intel_device(fd)
12034 22:55:22.983555 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
12036 22:55:22.983854 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
12038 22:55:22.984153 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
12040 22:55:22.984435 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
12042 22:55:22.984730 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
12044 22:55:22.985075 No KMS dri<14>[ 17.115645] [IGT] kms_addfb_basic: exiting, ret=77
12045 22:55:22.985223 ver or no outputs, pipes: 16, outputs: 0
12046 22:55:22.985329 [1mSubtest bo-too-small-due-to-tiling<8>[ 17.128371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
12047 22:55:22.985423 : SKIP (0.000s)[0m
12048 22:55:22.985524 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12049 22:55:22.985615 Using IGT_SRANDOM=1715122517 for randomisation
12050 22:55:22.985715 Opened device: /dev/dri/card0
12051 22:55:22.985822 Test requirement not met<14>[ 17.153509] [IGT] kms_addfb_basic: executing
12052 22:55:22.985911 in function igt_require_intel, file ../lib/drmtest.c:880:
12053 22:55:22.986000 Test requirement: is_intel_device(fd)
12054 22:55:22.986075 Test requirement not met in function igt_require_intel, file <14>[ 17.170918] [IGT] kms_addfb_basic: exiting, ret=77
12055 22:55:22.986163 ../lib/drmtest.c:880:
12056 22:55:22.986238 Test requirement: is_intel_device(fd)
12057 22:55:22.986311 No KMS driver or n<8>[ 17.183634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
12058 22:55:22.986387 o outputs, pipes: 16, outputs: 0
12059 22:55:22.986461 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
12060 22:55:22.986535 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12061 22:55:22.986609 Usi<14>[ 17.205614] [IGT] kms_addfb_basic: executing
12062 22:55:22.986683 ng IGT_SRANDOM=1715122517 for randomisation
12063 22:55:22.986758 Opened device: /dev/dri/card0
12064 22:55:22.986842 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12065 22:55:22.986927 <14>[ 17.223659] [IGT] kms_addfb_basic: exiting, ret=77
12066 22:55:22.987002 Test requirement: is_intel_device(fd)
12067 22:55:22.987076 Test requirement not met in function igt_<8>[ 17.236303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
12068 22:55:22.987151 require_intel, file ../lib/drmtest.c:880:
12069 22:55:22.987224 Test requirement: is_intel_device(fd)
12070 22:55:22.987297 No KMS driver or no outputs, pipes: 16, outputs: 0
12071 22:55:22.987370 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
12072 22:55:22.987463 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12073 22:55:22.987537 Using IGT_SRAN<14>[ 17.268186] [IGT] kms_addfb_basic: executing
12074 22:55:22.987611 DOM=1715122517 for randomisation
12075 22:55:22.987684 Opened device: /dev/dri/card0
12076 22:55:22.987757 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12077 22:55:22.987831 Test requirement: is_intel_<14>[ 17.287548] [IGT] kms_addfb_basic: exiting, ret=77
12078 22:55:22.987904 device(fd)
12079 22:55:22.987977 Test requirement not met in function igt_require_intel, file ../lib/<8>[ 17.300779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
12080 22:55:22.988051 drmtest.c:880:
12081 22:55:22.988134 Test requirement<8>[ 17.309866] <LAVA_SIGNAL_TESTSET STOP>
12082 22:55:22.988219 : is_intel_device(fd)
12083 22:55:22.988312 No KMS driver or no outputs, pipes: 16, outputs: 0
12084 22:55:22.988388 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
12085 22:55:22.988461 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12086 22:55:22.988535 Using IGT_SRANDOM=1715122517 for randomisation
12087 22:55:22.988619 Opened device: /dev/dri/card0
12088 22:55:22.988693 Test requirement not met in function <8>[ 17.341752] <LAVA_SIGNAL_TESTSET START kms_atomic>
12089 22:55:22.988767 igt_require_intel, file ../lib/drmtest.c:880:
12090 22:55:22.988840 Test requirement: is_intel_device(fd)
12091 22:55:22.988913 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12092 22:55:22.988987 Test requirement: is_intel_device(fd)
12093 22:55:22.989060 No KMS driver or no outputs, pipes: 16, outputs<14>[ 17.369516] [IGT] kms_atomic: executing
12094 22:55:22.989134 : 0
12095 22:55:22.989210 [1mSubtest<14>[ 17.375104] [IGT] kms_atomic: exiting, ret=77
12096 22:55:22.989294 addfb25-4-tiled: SKIP (0.000s)[0m
12097 22:55:22.989379 IGT-Version: 1.28-ga44ebfe <8>[ 17.385734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
12098 22:55:22.989454 (aarch64) (Linux: 6.1.90-cip20 aarch64)
12099 22:55:22.989536 Using IGT_SRANDOM=1715122517 for randomisation
12100 22:55:22.989610 Opened device: /dev/dri/card0
12101 22:55:22.989683 No KMS driver or no outputs, pipes: 16, outputs: 0
12102 22:55:22.989769 [1m<14>[ 17.408087] [IGT] kms_atomic: executing
12103 22:55:22.989842 Subtest plane-ov<14>[ 17.413601] [IGT] kms_atomic: exiting, ret=77
12104 22:55:22.989914 erlay-legacy: SKIP (0.000s)[0m
12105 22:55:22.989988 IGT-Version: 1.28-ga44ebfe (aar<8>[ 17.424727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
12106 22:55:22.990061 ch64) (Linux: 6.1.90-cip20 aarch64)
12107 22:55:22.990134 Using IGT_SRANDOM=1715122518 for randomisation
12108 22:55:22.990207 Opened device: /dev/dri/card0
12109 22:55:22.990279 No KMS driver or no outputs, pipes: 16, outputs: 0
12110 22:55:22.990353 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
12111 22:55:22.990437 <14>[ 17.456029] [IGT] kms_atomic: executing
12112 22:55:22.990520 IGT-Version: 1.2<14>[ 17.460939] [IGT] kms_atomic: exiting, ret=77
12113 22:55:22.990605 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12114 22:55:22.990864 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
12116 22:55:22.991113 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
12118 22:55:22.991335 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
12120 22:55:22.991569 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
12122 22:55:22.991790 Received signal: <TESTSET> STOP
12123 22:55:22.991865 Closing test_set kms_addfb_basic
12124 22:55:22.991963 Received signal: <TESTSET> START kms_atomic
12125 22:55:22.992036 Starting test_set kms_atomic
12126 22:55:22.992143 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
12128 22:55:22.992363 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
12130 22:55:22.992592 Using IGT_SRANDOM=1715122518<8>[ 17.472975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
12131 22:55:22.992671 for randomisation
12132 22:55:22.992741 Opened device: /dev/dri/card0
12133 22:55:22.992829 No KMS driver or no outputs, pipes: 16, outputs: 0
12134 22:55:22.992898 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12135 22:55:22.992964 <14>[ 17.505468] [IGT] kms_atomic: executing
12136 22:55:22.993036 IGT-Version: 1.2<14>[ 17.510450] [IGT] kms_atomic: exiting, ret=77
12137 22:55:22.993117 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12138 22:55:22.993187 Using IGT_SRANDOM=1715122518<8>[ 17.522114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
12139 22:55:22.993254 for randomisation
12140 22:55:22.993319 Opened device: /dev/dri/card0
12141 22:55:22.993385 No KMS driver or no outputs, pipes: 16, outputs: 0
12142 22:55:22.993460 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
12143 22:55:22.993543 <14>[ 17.545116] [IGT] kms_atomic: executing
12144 22:55:22.993611 IGT-Version: 1.2<14>[ 17.549843] [IGT] kms_atomic: exiting, ret=77
12145 22:55:22.993676 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12146 22:55:22.993742 Using IGT_SRANDOM=1715122518<8>[ 17.562233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
12147 22:55:22.993808 for randomisation
12148 22:55:22.993873 Opened device: /dev/dri/card0
12149 22:55:22.993947 No KMS driver or no outputs, pipes: 16, outputs: 0
12150 22:55:22.994024 [1mSubtest test-only: SKIP (0.000s)[0m
12151 22:55:22.994090 <14>[ 17.582315] [IGT] kms_atomic: executing
12152 22:55:22.994156 IGT-Version: 1.2<14>[ 17.587056] [IGT] kms_atomic: exiting, ret=77
12153 22:55:22.994221 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12154 22:55:22.994288 Using IGT_SRANDOM=1715122518<8>[ 17.599232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
12155 22:55:22.994354 for randomisation
12156 22:55:22.994429 Opened device: /dev/dri/card0
12157 22:55:22.994494 No KMS driver or no outputs, pipes: 16, outputs: 0
12158 22:55:22.994560 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12159 22:55:22.994625 <14>[ 17.630724] [IGT] kms_atomic: executing
12160 22:55:22.994690 IGT-Version: 1.2<14>[ 17.635625] [IGT] kms_atomic: exiting, ret=77
12161 22:55:22.994756 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12162 22:55:22.994822 Using IGT_SRANDOM=1715122518 for randomisation
12163 22:55:22.994886 Opened devic<8>[ 17.650601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12164 22:55:22.994960 e: /dev/dri/card0
12165 22:55:22.995035 No KMS driver or no outputs, pipes: 16, outputs: 0
12166 22:55:22.995116 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
12167 22:55:22.995182 <14>[ 17.673288] [IGT] kms_atomic: executing
12168 22:55:22.995247 IGT-Version: 1.2<14>[ 17.677937] [IGT] kms_atomic: exiting, ret=77
12169 22:55:22.995312 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12170 22:55:22.995378 Using IGT_SRANDOM=1715122518<8>[ 17.690196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12171 22:55:22.995444 for randomisation
12172 22:55:22.995529 Opened device: /dev/dri/card0
12173 22:55:22.995596 No KMS driver or no outputs, pipes: 16, outputs: 0
12174 22:55:22.995663 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m<14>[ 17.712195] [IGT] kms_atomic: executing
12175 22:55:22.995728
12176 22:55:22.995793 IGT-Version: 1.2<14>[ 17.717491] [IGT] kms_atomic: exiting, ret=77
12177 22:55:22.995859 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12178 22:55:22.995936 Using IGT_SRANDOM=1715122518<8>[ 17.729730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12179 22:55:22.995995 for randomisation
12180 22:55:22.996053 Opened device: /dev/dri/card0
12181 22:55:22.996113 No KMS driver or no outputs, pipes: 16, outputs: 0
12182 22:55:22.996181 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12183 22:55:22.996248 <14>[ 17.752011] [IGT] kms_atomic: executing
12184 22:55:22.996308 IGT-Version: 1.2<14>[ 17.756633] [IGT] kms_atomic: exiting, ret=77
12185 22:55:22.996376 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12186 22:55:22.996437 Using IGT_SRANDOM=1715122518<8>[ 17.768819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12187 22:55:22.996496 for randomisation
12188 22:55:22.996554 Opened device: /dev/dri/card0
12189 22:55:22.996613 No KMS driver or no outputs, pipes: 16, outputs: 0
12190 22:55:22.996682 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12191 22:55:22.996740 <14>[ 17.800685] [IGT] kms_atomic: executing
12192 22:55:22.996799 IGT-Version: 1.2<14>[ 17.805660] [IGT] kms_atomic: exiting, ret=77
12193 22:55:22.996857 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12194 22:55:22.996917 Using IGT_SRANDOM=1715122518<8>[ 17.817333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12195 22:55:22.996976 for randomisation
12196 22:55:22.997034 Opened device: /dev/dri/card0
12197 22:55:22.997093 No KMS driver or no outputs, pipes: 16, outputs: 0
12198 22:55:22.997152 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
12199 22:55:22.997219 <14>[ 17.849323] [IGT] kms_atomic: executing
12200 22:55:22.997279 IGT-Version: 1.2<14>[ 17.854244] [IGT] kms_atomic: exiting, ret=77
12201 22:55:22.997337 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12202 22:55:22.997406 Using IGT_SRANDOM=1715122518<8>[ 17.865693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12203 22:55:22.997466 for randomisation
12204 22:55:22.997707 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
12206 22:55:22.997909 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
12208 22:55:22.998110 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
12210 22:55:22.998310 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12212 22:55:22.998527 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12214 22:55:22.998725 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12216 22:55:22.998935 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12218 22:55:22.999130 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12220 22:55:22.999326 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12222 22:55:22.999531 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12224 22:55:22.999755 Opened devic<8>[ 17.876515] <LAVA_SIGNAL_TESTSET STOP>
12225 22:55:22.999853 e: /dev/dri/card0
12226 22:55:22.999929 No KMS driver or no outputs, pipes: 16, outputs: 0
12227 22:55:22.999993 [1mSubtest atomic-plane-damage: SKIP (0.000s)[0m
12228 22:55:23.000055 <8>[ 17.907915] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12229 22:55:23.000117 <14>[ 17.936576] [IGT] kms_flip_event_leak: executing
12230 22:55:23.000178 IGT-Version: 1.2<14>[ 17.942273] [IGT] kms_flip_event_leak: exiting, ret=77
12231 22:55:23.000239 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12232 22:55:23.000300 Using IGT_SR<8>[ 17.953964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12233 22:55:23.000360 ANDOM=1715122518 for randomisati<8>[ 17.962674] <LAVA_SIGNAL_TESTSET STOP>
12234 22:55:23.000420 on
12235 22:55:23.000479 Opened device: /dev/dri/card0
12236 22:55:23.000538 No KMS driver or no outputs, pipes: 16, outputs: 0
12237 22:55:23.000598 [1mSubtest basic: SKIP (0.000s)[0m
12238 22:55:23.000658 <8>[ 17.994050] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12239 22:55:23.000736 <14>[ 18.021480] [IGT] kms_prop_blob: executing
12240 22:55:23.000796 IGT-Version: 1.2<14>[ 18.026808] [IGT] kms_prop_blob: starting subtest basic
12241 22:55:23.000855 8-ga44ebfe (aarc<14>[ 18.033452] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12242 22:55:23.000935 h64) (Linux: 6.1<14>[ 18.041257] [IGT] kms_prop_blob: exiting, ret=0
12243 22:55:23.000990 .90-cip20 aarch64)
12244 22:55:23.001045 Using IGT_SRANDOM=1715122518 for randomisation
12245 22:55:23.001108 Opened devic<8>[ 18.053541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12246 22:55:23.001163 e: /dev/dri/card0
12247 22:55:23.001215 Starting subtest: basic
12248 22:55:23.001269 [1mSubtest basic: SUCCESS (0.000s)[0m
12249 22:55:23.001323 <14>[ 18.074551] [IGT] kms_prop_blob: executing
12250 22:55:23.001377 IGT-Version: 1.2<14>[ 18.079437] [IGT] kms_prop_blob: starting subtest blob-prop-core
12251 22:55:23.001431 8-ga44ebfe (aarc<14>[ 18.087055] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12252 22:55:23.001486 h64) (Linux: 6.1<14>[ 18.095734] [IGT] kms_prop_blob: exiting, ret=0
12253 22:55:23.001550 .90-cip20 aarch64)
12254 22:55:23.001605 Using IGT_SRANDOM=1715122518 for randomisation
12255 22:55:23.001659 Opened devic<8>[ 18.108244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12256 22:55:23.001714 e: /dev/dri/card0
12257 22:55:23.001767 Starting subtest: blob-prop-core
12258 22:55:23.001830 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12259 22:55:23.001884 <14>[ 18.138909] [IGT] kms_prop_blob: executing
12260 22:55:23.001947 IGT-Version: 1.2<14>[ 18.144042] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12261 22:55:23.002010 8-ga44ebfe (aarc<14>[ 18.152060] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12262 22:55:23.002065 h64) (Linux: 6.1<14>[ 18.160896] [IGT] kms_prop_blob: exiting, ret=0
12263 22:55:23.002118 .90-cip20 aarch64)
12264 22:55:23.002172 Using IGT_SRANDOM=1715122518 for randomisation
12265 22:55:23.002225 Opened devic<8>[ 18.173665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12266 22:55:23.002279 e: /dev/dri/card0
12267 22:55:23.002332 Starting subtest: blob-prop-validate
12268 22:55:23.002385 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12269 22:55:23.002448 <14>[ 18.195683] [IGT] kms_prop_blob: executing
12270 22:55:23.002502 IGT-Version: 1.2<14>[ 18.200465] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12271 22:55:23.002555 8-ga44ebfe (aarc<14>[ 18.208476] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12272 22:55:23.002610 h64) (Linux: 6.1<14>[ 18.217325] [IGT] kms_prop_blob: exiting, ret=0
12273 22:55:23.002663 .90-cip20 aarch64)
12274 22:55:23.002717 Using IGT_SRANDOM=1715122518 for randomisation
12275 22:55:23.002770 Opened devic<8>[ 18.229643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12276 22:55:23.002824 e: /dev/dri/card0
12277 22:55:23.002886 Starting subtest: blob-prop-lifetime
12278 22:55:23.002939 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12279 22:55:23.002992 <14>[ 18.261237] [IGT] kms_prop_blob: executing
12280 22:55:23.003046 IGT-Version: 1.2<14>[ 18.266279] [IGT] kms_prop_blob: starting subtest blob-multiple
12281 22:55:23.003100 8-ga44ebfe (aarc<14>[ 18.273926] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12282 22:55:23.003154 h64) (Linux: 6.1<14>[ 18.282218] [IGT] kms_prop_blob: exiting, ret=0
12283 22:55:23.003208 .90-cip20 aarch64)
12284 22:55:23.003261 Using IGT_SRANDOM=1715122518 for randomisation
12285 22:55:23.003315 Opened device: /dev/dri/card<8>[ 18.296378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12286 22:55:23.003369 0
12287 22:55:23.003422 Starting subtest: blob-multiple
12288 22:55:23.003485 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12289 22:55:23.003539 <14>[ 18.317760] [IGT] kms_prop_blob: executing
12290 22:55:23.003592 IGT-Version: 1.2<14>[ 18.322633] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12291 22:55:23.003645 8-ga44ebfe (aarc<14>[ 18.330662] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12292 22:55:23.003700 h64) (Linux: 6.1<14>[ 18.339832] [IGT] kms_prop_blob: exiting, ret=0
12293 22:55:23.003753 .90-cip20 aarch64)
12294 22:55:23.003807 Using IGT_SRANDOM=1715122518 for randomisation
12295 22:55:23.003859 Opened devic<8>[ 18.352257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12296 22:55:23.004088 Received signal: <TESTSET> STOP
12297 22:55:23.004155 Closing test_set kms_atomic
12298 22:55:23.004237 Received signal: <TESTSET> START kms_flip_event_leak
12299 22:55:23.004295 Starting test_set kms_flip_event_leak
12300 22:55:23.004375 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12302 22:55:23.004554 Received signal: <TESTSET> STOP
12303 22:55:23.004613 Closing test_set kms_flip_event_leak
12304 22:55:23.004702 Received signal: <TESTSET> START kms_prop_blob
12305 22:55:23.004762 Starting test_set kms_prop_blob
12306 22:55:23.004841 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12308 22:55:23.005019 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12310 22:55:23.005199 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12312 22:55:23.005394 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12314 22:55:23.005581 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12316 22:55:23.005759 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12318 22:55:23.005988 e: /dev/dri/card0
12319 22:55:23.006062 Starting subtest: invalid-get-prop-any
12320 22:55:23.006117 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12321 22:55:23.006171 <14>[ 18.383681] [IGT] kms_prop_blob: executing
12322 22:55:23.006224 IGT-Version: 1.2<14>[ 18.388709] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12323 22:55:23.006277 8-ga44ebfe (aarc<14>[ 18.396435] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12324 22:55:23.006330 h64) (Linux: 6.1<14>[ 18.405174] [IGT] kms_prop_blob: exiting, ret=0
12325 22:55:23.006393 .90-cip20 aarch64)
12326 22:55:23.006488 Using IGT_SRANDOM=1715122518 for randomisation
12327 22:55:23.006540 Opened devic<8>[ 18.417250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12328 22:55:23.006594 e: /dev/dri/card0
12329 22:55:23.006646 Starting subtest: invalid-get-prop
12330 22:55:23.006697 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12331 22:55:23.006749 <14>[ 18.439872] [IGT] kms_prop_blob: executing
12332 22:55:23.006801 IGT-Version: 1.2<14>[ 18.444655] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12333 22:55:23.006854 8-ga44ebfe (aarc<14>[ 18.452732] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12334 22:55:23.006918 h64) (Linux: 6.1<14>[ 18.461785] [IGT] kms_prop_blob: exiting, ret=0
12335 22:55:23.006970 .90-cip20 aarch64)
12336 22:55:23.007022 Using IGT_SRANDOM=1715122519 for randomisation
12337 22:55:23.007073 Opened devic<8>[ 18.474228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12338 22:55:23.007126 e: /dev/dri/card0
12339 22:55:23.007177 Starting subtest: invalid-set-prop-any
12340 22:55:23.007229 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12341 22:55:23.007280 <14>[ 18.505912] [IGT] kms_prop_blob: executing
12342 22:55:23.007332 IGT-Version: 1.2<14>[ 18.511076] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12343 22:55:23.007384 8-ga44ebfe (aarc<14>[ 18.518721] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12344 22:55:23.007437 h64) (Linux: 6.1<14>[ 18.527451] [IGT] kms_prop_blob: exiting, ret=0
12345 22:55:23.007489 .90-cip20 aarch64)
12346 22:55:23.007551 Using IGT_SRANDOM=1715122519 for randomisation
12347 22:55:23.007603 Opened device: /dev/dri/card<8>[ 18.541435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12348 22:55:23.007655 0
12349 22:55:23.007708 Starting subtest: invalid-set<8>[ 18.551142] <LAVA_SIGNAL_TESTSET STOP>
12350 22:55:23.007763 -prop
12351 22:55:23.007827 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12352 22:55:23.007879 <8>[ 18.583446] <LAVA_SIGNAL_TESTSET START kms_setmode>
12353 22:55:23.007931 <14>[ 18.602762] [IGT] kms_setmode: executing
12354 22:55:23.007983 IGT-Version: 1.2<14>[ 18.607442] [IGT] kms_setmode: starting subtest basic
12355 22:55:23.008035 8-ga44ebfe (aarc<14>[ 18.614027] [IGT] kms_setmode: finished subtest basic, SKIP
12356 22:55:23.008088 h64) (Linux: 6.1<14>[ 18.621423] [IGT] kms_setmode: exiting, ret=77
12357 22:55:23.008149 .90-cip20 aarch64)
12358 22:55:23.008201 Using IGT_SRANDOM=1715122519 for randomisation
12359 22:55:23.008261 Opened devic<8>[ 18.633747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12360 22:55:23.008321 e: /dev/dri/card0
12361 22:55:23.008374 Starting subtest: basic
12362 22:55:23.008426 No dynamic tests executed.
12363 22:55:23.008478 [1mSubtest basic: SKIP (0.000s)[0m
12364 22:55:23.008530 <14>[ 18.664322] [IGT] kms_setmode: executing
12365 22:55:23.008582 IGT-Version: 1.2<14>[ 18.669613] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12366 22:55:23.008634 8-ga44ebfe (aarc<14>[ 18.677713] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12367 22:55:23.008687 h64) (Linux: 6.1<14>[ 18.686619] [IGT] kms_setmode: exiting, ret=77
12368 22:55:23.008739 .90-cip20 aarch64)
12369 22:55:23.008790 Using IGT_SRANDOM=1715122519 for randomisation
12370 22:55:23.008842 Opened devic<8>[ 18.699619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12371 22:55:23.008902 e: /dev/dri/card0
12372 22:55:23.008961 Starting subtest: basic-clone-single-crtc
12373 22:55:23.009013 No dynamic tests executed.
12374 22:55:23.009074 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12375 22:55:23.009126 <14>[ 18.723961] [IGT] kms_setmode: executing
12376 22:55:23.009177 IGT-Version: 1.2<14>[ 18.728605] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12377 22:55:23.009230 8-ga44ebfe (aarc<14>[ 18.736940] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12378 22:55:23.009283 h64) (Linux: 6.1<14>[ 18.746036] [IGT] kms_setmode: exiting, ret=77
12379 22:55:23.009334 .90-cip20 aarch64)
12380 22:55:23.009386 Using IGT_SRANDOM=1715122519 for randomisation
12381 22:55:23.009437 Opened devic<8>[ 18.758559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12382 22:55:23.009489 e: /dev/dri/card0
12383 22:55:23.009545 Starting subtest: invalid-clone-single-crtc
12384 22:55:23.009597 No dynamic tests executed.
12385 22:55:23.009649 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12386 22:55:23.009700 <14>[ 18.796625] [IGT] kms_setmode: executing
12387 22:55:23.009752 IGT-Version: 1.2<14>[ 18.801319] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12388 22:55:23.009807 8-ga44ebfe (aarc<14>[ 18.809921] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12389 22:55:23.010062 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12391 22:55:23.010252 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12393 22:55:23.010430 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12395 22:55:23.010604 Received signal: <TESTSET> STOP
12396 22:55:23.010664 Closing test_set kms_prop_blob
12397 22:55:23.010741 Received signal: <TESTSET> START kms_setmode
12398 22:55:23.010809 Starting test_set kms_setmode
12399 22:55:23.010895 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12401 22:55:23.011068 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12403 22:55:23.011240 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12405 22:55:23.011426 h64) (Linux: 6.1<14>[ 18.819290] [IGT] kms_setmode: exiting, ret=77
12406 22:55:23.011488 .90-cip20 aarch64)
12407 22:55:23.011545 Using IGT_SRANDOM=1715122519 for randomisati<8>[ 18.830752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12408 22:55:23.011600 on
12409 22:55:23.011654 Opened device: /dev/dri/card0
12410 22:55:23.011706 Starting subtest: invalid-clone-exclusive-crtc
12411 22:55:23.011759 No dynamic tests executed.
12412 22:55:23.011815 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12413 22:55:23.011881 <14>[ 18.856500] [IGT] kms_setmode: executing
12414 22:55:23.011934 IGT-Version: 1.2<14>[ 18.861277] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12415 22:55:23.011986 8-ga44ebfe (aarc<14>[ 18.869161] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12416 22:55:23.012040 h64) (Linux: 6.1<14>[ 18.877880] [IGT] kms_setmode: exiting, ret=77
12417 22:55:23.012092 .90-cip20 aarch64)
12418 22:55:23.012145 Using IGT_SRANDOM=1715122519 for randomisati<8>[ 18.888374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12419 22:55:23.012198 on
12420 22:55:23.012250 Opened device: /dev/dri/card0
12421 22:55:23.012302 Starting subtest: clone-exclusive-crtc
12422 22:55:23.012354 No dynamic tests executed.
12423 22:55:23.012407 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12424 22:55:23.012459 <14>[ 18.910338] [IGT] kms_setmode: executing
12425 22:55:23.012511 IGT-Version: 1.2<14>[ 18.915432] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12426 22:55:23.012564 8-ga44ebfe (aarc<14>[ 18.924495] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12427 22:55:23.012627 h64) (Linux: 6.1<14>[ 18.934505] [IGT] kms_setmode: exiting, ret=77
12428 22:55:23.012680 .90-cip20 aarch64)
12429 22:55:23.012732 Using IGT_SRANDOM=1715122519 for randomisati<8>[ 18.945618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12430 22:55:23.012784 on
12431 22:55:23.012836 Opened devic<8>[ 18.956189] <LAVA_SIGNAL_TESTSET STOP>
12432 22:55:23.012887 e: /dev/dri/card0
12433 22:55:23.012939 Starting subtest: invalid-clone-single-crtc-stealing
12434 22:55:23.012990 No dynamic tests executed.
12435 22:55:23.013042 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12436 22:55:23.013093 <8>[ 18.987016] <LAVA_SIGNAL_TESTSET START kms_vblank>
12437 22:55:23.013145 <14>[ 19.020288] [IGT] kms_vblank: executing
12438 22:55:23.013196 IGT-Version: 1.2<14>[ 19.025293] [IGT] kms_vblank: exiting, ret=77
12439 22:55:23.013257 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12440 22:55:23.013310 Using IGT_SRANDOM=1715122519<8>[ 19.036664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12441 22:55:23.013362 for randomisation
12442 22:55:23.013413 Opened device: /dev/dri/card0
12443 22:55:23.013465 No KMS driver or no outputs, pipes: 16, outputs: 0
12444 22:55:23.013523 [1mSubtest invalid: SKIP (0.000s)[0m
12445 22:55:23.013585 <14>[ 19.060843] [IGT] kms_vblank: executing
12446 22:55:23.013637 IGT-Version: 1.2<14>[ 19.065620] [IGT] kms_vblank: exiting, ret=77
12447 22:55:23.013689 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12448 22:55:23.013741 Using IGT_SRANDOM=1715122519<8>[ 19.077690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12449 22:55:23.013798 for randomisation
12450 22:55:23.013868 Opened device: /dev/dri/card0
12451 22:55:23.013938 No KMS driver or no outputs, pipes: 16, outputs: 0
12452 22:55:23.014027 [1mSubtest crtc-id: SKIP (0.000s)[0m
12453 22:55:23.014088 <14>[ 19.098699] [IGT] kms_vblank: executing
12454 22:55:23.014142 IGT-Version: 1.2<14>[ 19.103370] [IGT] kms_vblank: exiting, ret=77
12455 22:55:23.014195 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12456 22:55:23.014248 Using IGT_SRANDOM=1715122519 for randomisation
12457 22:55:23.014301 Opened devic<8>[ 19.117484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12458 22:55:23.014353 e: /dev/dri/card0
12459 22:55:23.014405 No KMS driver or no outputs, pipes: 16, outputs: 0
12460 22:55:23.014458 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12461 22:55:23.014509 <14>[ 19.149597] [IGT] kms_vblank: executing
12462 22:55:23.014571 IGT-Version: 1.2<14>[ 19.154568] [IGT] kms_vblank: exiting, ret=77
12463 22:55:23.014624 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12464 22:55:23.014685 Using IGT_SR<8>[ 19.165626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12465 22:55:23.014738 ANDOM=1715122519 for randomisation
12466 22:55:23.014789 Opened device: /dev/dri/card0
12467 22:55:23.014841 No KMS driver or no outputs, pipes: 16, outputs: 0
12468 22:55:23.014893 [1mSubtest query-idle: SKIP (0.000s)[0m
12469 22:55:23.014945 <14>[ 19.196551] [IGT] kms_vblank: executing
12470 22:55:23.014997 IGT-Version: 1.2<14>[ 19.201482] [IGT] kms_vblank: exiting, ret=77
12471 22:55:23.015048 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12472 22:55:23.015101 Using IGT_SRANDOM=1715122519<8>[ 19.213257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12473 22:55:23.015154 for randomisation
12474 22:55:23.015204 Opened device: /dev/dri/card0
12475 22:55:23.015256 No KMS driver or no outputs, pipes: 16, outputs: 0
12476 22:55:23.015308 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12477 22:55:23.015360 <14>[ 19.244063] [IGT] kms_vblank: executing
12478 22:55:23.015419 IGT-Version: 1.2<14>[ 19.249064] [IGT] kms_vblank: exiting, ret=77
12479 22:55:23.015473 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12480 22:55:23.015702 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12482 22:55:23.015924 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12484 22:55:23.016116 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12486 22:55:23.016293 Received signal: <TESTSET> STOP
12487 22:55:23.016362 Closing test_set kms_setmode
12488 22:55:23.016441 Received signal: <TESTSET> START kms_vblank
12489 22:55:23.016500 Starting test_set kms_vblank
12490 22:55:23.016575 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12492 22:55:23.016747 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12494 22:55:23.016919 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12496 22:55:23.017102 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12498 22:55:23.017313 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12500 22:55:23.017531 Using IGT_SRANDOM=1715122519<8>[ 19.260775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12501 22:55:23.017608 for randomisation
12502 22:55:23.017664 Opened device: /dev/dri/card0
12503 22:55:23.017719 No KMS driver or no outputs, pipes: 16, outputs: 0
12504 22:55:23.017774 [1mSubtest query-forked: SKIP (0.000s)[0m
12505 22:55:23.017828 <14>[ 19.291714] [IGT] kms_vblank: executing
12506 22:55:23.017881 IGT-Version: 1.2<14>[ 19.296694] [IGT] kms_vblank: exiting, ret=77
12507 22:55:23.017934 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12508 22:55:23.017988 Using IGT_SRANDOM=1715122519<8>[ 19.308214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12509 22:55:23.018042 for randomisation
12510 22:55:23.018093 Opened device: /dev/dri/card0
12511 22:55:23.018163 No KMS driver or no outputs, pipes: 16, outputs: 0
12512 22:55:23.018217 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12513 22:55:23.018269 <14>[ 19.339632] [IGT] kms_vblank: executing
12514 22:55:23.018323 IGT-Version: 1.2<14>[ 19.344609] [IGT] kms_vblank: exiting, ret=77
12515 22:55:23.018375 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12516 22:55:23.018428 Using IGT_SRANDOM=1715122519<8>[ 19.356349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12517 22:55:23.018480 for randomisation
12518 22:55:23.018531 Opened device: /dev/dri/card0
12519 22:55:23.018582 No KMS driver or no outputs, pipes: 16, outputs: 0
12520 22:55:23.018634 [1mSubtest query-busy: SKIP (0.000s)[0m
12521 22:55:23.018694 <14>[ 19.378615] [IGT] kms_vblank: executing
12522 22:55:23.018747 IGT-Version: 1.2<14>[ 19.383232] [IGT] kms_vblank: exiting, ret=77
12523 22:55:23.018807 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12524 22:55:23.018860 Using IGT_SRANDOM=1715122519<8>[ 19.395506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12525 22:55:23.018912 for randomisation
12526 22:55:23.018963 Opened device: /dev/dri/card0
12527 22:55:23.019015 No KMS driver or no outputs, pipes: 16, outputs: 0
12528 22:55:23.019067 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12529 22:55:23.019118 <14>[ 19.419537] [IGT] kms_vblank: executing
12530 22:55:23.019170 IGT-Version: 1.2<14>[ 19.424180] [IGT] kms_vblank: exiting, ret=77
12531 22:55:23.019222 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12532 22:55:23.019275 Using IGT_SRANDOM=1715122520<8>[ 19.436438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12533 22:55:23.019326 for randomisation
12534 22:55:23.019386 Opened device: /dev/dri/card0
12535 22:55:23.019446 No KMS driver or no outputs, pipes: 16, outputs: 0
12536 22:55:23.019500 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12537 22:55:23.019552 <14>[ 19.457682] [IGT] kms_vblank: executing
12538 22:55:23.019604 IGT-Version: 1.2<14>[ 19.462320] [IGT] kms_vblank: exiting, ret=77
12539 22:55:23.019655 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12540 22:55:23.019708 Using IGT_SRANDOM=1715122520<8>[ 19.474658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12541 22:55:23.019760 for randomisation
12542 22:55:23.019811 Opened device: /dev/dri/card0
12543 22:55:23.019863 No KMS driver or no outputs, pipes: 16, outputs: 0
12544 22:55:23.019914 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12545 22:55:23.019975 <14>[ 19.505849] [IGT] kms_vblank: executing
12546 22:55:23.020028 IGT-Version: 1.2<14>[ 19.510858] [IGT] kms_vblank: exiting, ret=77
12547 22:55:23.020081 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12548 22:55:23.020134 Using IGT_SRANDOM=1715122520 for randomisation
12549 22:55:23.020185 Opened devic<8>[ 19.525648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12550 22:55:23.020238 e: /dev/dri/card0
12551 22:55:23.020289 No KMS driver or no outputs, pipes: 16, outputs: 0
12552 22:55:23.020341 [1mSubtest wait-idle: SKIP (0.000s)[0m
12553 22:55:23.020393 <14>[ 19.557064] [IGT] kms_vblank: executing
12554 22:55:23.020445 IGT-Version: 1.2<14>[ 19.562035] [IGT] kms_vblank: exiting, ret=77
12555 22:55:23.020497 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12556 22:55:23.020558 Using IGT_SRANDOM=1715122520 for randomisation
12557 22:55:23.020619 Opened devic<8>[ 19.577236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12558 22:55:23.020672 e: /dev/dri/card0
12559 22:55:23.020724 No KMS driver or no outputs, pipes: 16, outputs: 0
12560 22:55:23.020776 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12561 22:55:23.020828 <14>[ 19.601466] [IGT] kms_vblank: executing
12562 22:55:23.020880 IGT-Version: 1.2<14>[ 19.606091] [IGT] kms_vblank: exiting, ret=77
12563 22:55:23.020932 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12564 22:55:23.020984 Using IGT_SRANDOM=1715122520<8>[ 19.618545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12565 22:55:23.021037 for randomisation
12566 22:55:23.021097 Opened device: /dev/dri/card0
12567 22:55:23.021149 No KMS driver or no outputs, pipes: 16, outputs: 0
12568 22:55:23.021202 [1mSubtest wait-forked: SKIP (0.000s)[0m
12569 22:55:23.021254 <14>[ 19.639166] [IGT] kms_vblank: executing
12570 22:55:23.021306 IGT-Version: 1.2<14>[ 19.643788] [IGT] kms_vblank: exiting, ret=77
12571 22:55:23.021358 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12572 22:55:23.021411 Using IGT_SRANDOM=1715122520<8>[ 19.655858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12573 22:55:23.021463 for randomisation
12574 22:55:23.021520 Opened device: /dev/dri/card0
12575 22:55:23.021614 No KMS driver or no outputs, pipes: 16, outputs: 0
12576 22:55:23.021841 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12578 22:55:23.022018 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12580 22:55:23.022205 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12582 22:55:23.022398 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12584 22:55:23.022575 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12586 22:55:23.022758 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12588 22:55:23.022943 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12590 22:55:23.023126 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12592 22:55:23.023301 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12594 22:55:23.023473 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12596 22:55:23.023656 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12597 22:55:23.023717 <14>[ 19.686862] [IGT] kms_vblank: executing
12598 22:55:23.023773 IGT-Version: 1.2<14>[ 19.691816] [IGT] kms_vblank: exiting, ret=77
12599 22:55:23.023837 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12600 22:55:23.023900 Using IGT_SRANDOM=1715122520 for randomisation
12601 22:55:23.023954 Opened devic<8>[ 19.706736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12602 22:55:23.024007 e: /dev/dri/card0
12603 22:55:23.024060 No KMS driver or no outputs, pipes: 16, outputs: 0
12604 22:55:23.024113 [1mSubtest wait-busy: SKIP (0.000s)[0m
12605 22:55:23.024164 <14>[ 19.728552] [IGT] kms_vblank: executing
12606 22:55:23.024216 IGT-Version: 1.2<14>[ 19.733192] [IGT] kms_vblank: exiting, ret=77
12607 22:55:23.024269 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12608 22:55:23.024332 Using IGT_SRANDOM=1715122520<8>[ 19.745500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12609 22:55:23.024392 for randomisation
12610 22:55:23.024453 Opened device: /dev/dri/card0
12611 22:55:23.024514 No KMS driver or no outputs, pipes: 16, outputs: 0
12612 22:55:23.024567 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12613 22:55:23.024619 <14>[ 19.775891] [IGT] kms_vblank: executing
12614 22:55:23.024670 IGT-Version: 1.2<14>[ 19.780827] [IGT] kms_vblank: exiting, ret=77
12615 22:55:23.024722 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12616 22:55:23.024774 Using IGT_SRANDOM=1715122520<8>[ 19.793275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12617 22:55:23.024826 for randomisation
12618 22:55:23.024886 Opened device: /dev/dri/card0
12619 22:55:23.024938 No KMS driver or no outputs, pipes: 16, outputs: 0
12620 22:55:23.024990 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12621 22:55:23.025057 <14>[ 19.823767] [IGT] kms_vblank: executing
12622 22:55:23.025111 IGT-Version: 1.2<14>[ 19.828761] [IGT] kms_vblank: exiting, ret=77
12623 22:55:23.025162 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12624 22:55:23.025215 Using IGT_SRANDOM=1715122520<8>[ 19.840501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12625 22:55:23.025268 for randomisation
12626 22:55:23.025318 Opened device: /dev/dri/card0
12627 22:55:23.025369 No KMS driver or no outputs, pipes: 16, outputs: 0
12628 22:55:23.025421 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12629 22:55:23.025472 <14>[ 19.862883] [IGT] kms_vblank: executing
12630 22:55:23.025560 IGT-Version: 1.2<14>[ 19.867514] [IGT] kms_vblank: exiting, ret=77
12631 22:55:23.025613 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12632 22:55:23.025666 Using IGT_SR<8>[ 19.878692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12633 22:55:23.025718 ANDOM=1715122520 for randomisation
12634 22:55:23.025779 Opened device: /dev/dri/card0
12635 22:55:23.025831 No KMS driver or no outputs, pipes: 16, outputs: 0
12636 22:55:23.025884 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12637 22:55:23.025936 <14>[ 19.902788] [IGT] kms_vblank: executing
12638 22:55:23.025987 IGT-Version: 1.2<14>[ 19.907618] [IGT] kms_vblank: exiting, ret=77
12639 22:55:23.026039 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12640 22:55:23.026092 Using IGT_SRANDOM=1715122520<8>[ 19.919721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12641 22:55:23.026144 for randomisation
12642 22:55:23.026194 Opened device: /dev/dri/card0
12643 22:55:23.026246 No KMS driver or no outputs, pipes: 16, outputs: 0
12644 22:55:23.026306 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12645 22:55:23.026373 <14>[ 19.951700] [IGT] kms_vblank: executing
12646 22:55:23.026425 IGT-Version: 1.2<14>[ 19.956711] [IGT] kms_vblank: exiting, ret=77
12647 22:55:23.026477 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12648 22:55:23.026530 Using IGT_SRANDOM=1715122520 for randomisation
12649 22:55:23.026582 Opened devic<8>[ 19.972011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12650 22:55:23.026634 e: /dev/dri/card0
12651 22:55:23.026685 No KMS driver or no outputs, pipes: 16, outputs: 0
12652 22:55:23.026738 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12653 22:55:23.026789 <14>[ 19.994284] [IGT] kms_vblank: executing
12654 22:55:23.026840 IGT-Version: 1.2<14>[ 19.998969] [IGT] kms_vblank: exiting, ret=77
12655 22:55:23.026891 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12656 22:55:23.026953 Using IGT_SRANDOM=1715122520<8>[ 20.010870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12657 22:55:23.027015 for randomisation
12658 22:55:23.027066 Opened device: /dev/dri/card0
12659 22:55:23.027126 No KMS driver or no outputs, pipes: 16, outputs: 0
12660 22:55:23.027178 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12661 22:55:23.027230 <14>[ 20.035245] [IGT] kms_vblank: executing
12662 22:55:23.027282 IGT-Version: 1.2<14>[ 20.040057] [IGT] kms_vblank: exiting, ret=77
12663 22:55:23.027333 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12664 22:55:23.027386 Using IGT_SRANDOM=1715122520<8>[ 20.052281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12665 22:55:23.027438 for randomisation
12666 22:55:23.027498 Opened device: /dev/dri/card0
12667 22:55:23.027558 No KMS driver or no outputs, pipes: 16, outputs: 0
12668 22:55:23.027611 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12669 22:55:23.027671 <14>[ 20.083768] [IGT] kms_vblank: executing
12670 22:55:23.027904 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12672 22:55:23.028089 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12674 22:55:23.028265 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12676 22:55:23.028439 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12678 22:55:23.028623 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12680 22:55:23.028799 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12682 22:55:23.028972 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12684 22:55:23.029155 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12686 22:55:23.029328 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12688 22:55:23.029506 IGT-Version: 1.2<14>[ 20.088779] [IGT] kms_vblank: exiting, ret=77
12689 22:55:23.029610 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12690 22:55:23.029668 Using IGT_SRANDOM=1715122520<8>[ 20.100107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12691 22:55:23.029722 for randomisation
12692 22:55:23.029776 Opened device: /dev/dri/card0
12693 22:55:23.029829 No KMS driver or no outputs, pipes: 16, outputs: 0
12694 22:55:23.029882 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12695 22:55:23.029944 <14>[ 20.123795] [IGT] kms_vblank: executing
12696 22:55:23.030005 IGT-Version: 1.2<14>[ 20.128566] [IGT] kms_vblank: exiting, ret=77
12697 22:55:23.030094 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12698 22:55:23.030174 Using IGT_SRANDOM=1715122520<8>[ 20.140830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12699 22:55:23.030230 for randomisation
12700 22:55:23.030283 Opened device: /dev/dri/card0
12701 22:55:23.030335 No KMS driver or no outputs, pipes: 16, outputs: 0
12702 22:55:23.030388 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12703 22:55:23.030441 <14>[ 20.172705] [IGT] kms_vblank: executing
12704 22:55:23.030502 IGT-Version: 1.2<14>[ 20.177693] [IGT] kms_vblank: exiting, ret=77
12705 22:55:23.030564 8-ga44ebfe (aarch64) (Linux: 6.1.90-cip20 aarch64)
12706 22:55:23.030618 Using IGT_SRANDOM=1715122520 for randomisati<8>[ 20.190339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12707 22:55:23.030671 on
12708 22:55:23.030723 Opened device: /dev/dri/card<8>[ 20.201509] <LAVA_SIGNAL_TESTSET STOP>
12709 22:55:23.030775 0
12710 22:55:23.030828 No KMS driver<8>[ 20.207595] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 13683715_1.5.2.3.1>
12711 22:55:23.030881 or no outputs, pipes: 16, outputs: 0
12712 22:55:23.030942 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12713 22:55:23.030995 + set +x
12714 22:55:23.031047 <LAVA_TEST_RUNNER EXIT>
12715 22:55:23.031276 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12717 22:55:23.031451 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12719 22:55:23.031703 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12721 22:55:23.031887 Received signal: <TESTSET> STOP
12722 22:55:23.031948 Closing test_set kms_vblank
12723 22:55:23.032026 Received signal: <ENDRUN> 0_igt-kms-mediatek 13683715_1.5.2.3.1
12724 22:55:23.032096 Ending use of test pattern.
12725 22:55:23.032150 Ending test lava.0_igt-kms-mediatek (13683715_1.5.2.3.1), duration 9.02
12727 22:55:23.032442 ok: lava_test_shell seems to have completed
12728 22:55:23.033994 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12729 22:55:23.034134 end: 3.1 lava-test-shell (duration 00:00:09) [common]
12730 22:55:23.034231 end: 3 lava-test-retry (duration 00:00:09) [common]
12731 22:55:23.034315 start: 4 finalize (timeout 00:06:54) [common]
12732 22:55:23.034417 start: 4.1 power-off (timeout 00:00:30) [common]
12733 22:55:23.034562 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
12734 22:55:23.116214 >> Command sent successfully.
12735 22:55:23.126118 Returned 0 in 0 seconds
12736 22:55:23.227442 end: 4.1 power-off (duration 00:00:00) [common]
12738 22:55:23.229123 start: 4.2 read-feedback (timeout 00:06:53) [common]
12739 22:55:23.230385 Listened to connection for namespace 'common' for up to 1s
12740 22:55:24.231142 Finalising connection for namespace 'common'
12741 22:55:24.231774 Disconnecting from shell: Finalise
12742 22:55:24.232150 / #
12743 22:55:24.333087 end: 4.2 read-feedback (duration 00:00:01) [common]
12744 22:55:24.333746 end: 4 finalize (duration 00:00:01) [common]
12745 22:55:24.334307 Cleaning after the job
12746 22:55:24.334765 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/ramdisk
12747 22:55:24.361666 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/kernel
12748 22:55:24.388548 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/dtb
12749 22:55:24.388809 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683715/tftp-deploy-x7een8un/modules
12750 22:55:24.395299 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683715
12751 22:55:24.501308 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683715
12752 22:55:24.501489 Job finished correctly