Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Warnings: 1
- Kernel Warnings: 89
- Errors: 0
- Kernel Errors: 49
- Boot result: PASS
1 22:48:30.119973 lava-dispatcher, installed at version: 2024.01
2 22:48:30.120211 start: 0 validate
3 22:48:30.120378 Start time: 2024-05-07 22:48:30.120367+00:00 (UTC)
4 22:48:30.120571 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:48:30.120722 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:48:30.372323 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:48:30.372504 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:48:30.631093 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:48:30.631332 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 22:48:59.572544 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:48:59.573266 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:49:00.077114 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:49:00.077780 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:49:05.099911 validate duration: 34.98
16 22:49:05.101037 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:49:05.101519 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:49:05.101952 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:49:05.102504 Not decompressing ramdisk as can be used compressed.
20 22:49:05.102941 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:49:05.103307 saving as /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/ramdisk/initrd.cpio.gz
22 22:49:05.103665 total size: 5628169 (5 MB)
23 22:49:05.425332 progress 0 % (0 MB)
24 22:49:05.427158 progress 5 % (0 MB)
25 22:49:05.428877 progress 10 % (0 MB)
26 22:49:05.430406 progress 15 % (0 MB)
27 22:49:05.432148 progress 20 % (1 MB)
28 22:49:05.433681 progress 25 % (1 MB)
29 22:49:05.435389 progress 30 % (1 MB)
30 22:49:05.437082 progress 35 % (1 MB)
31 22:49:05.438600 progress 40 % (2 MB)
32 22:49:05.440317 progress 45 % (2 MB)
33 22:49:05.469291 progress 50 % (2 MB)
34 22:49:05.471163 progress 55 % (2 MB)
35 22:49:05.472915 progress 60 % (3 MB)
36 22:49:05.474441 progress 65 % (3 MB)
37 22:49:05.476161 progress 70 % (3 MB)
38 22:49:05.477695 progress 75 % (4 MB)
39 22:49:05.479427 progress 80 % (4 MB)
40 22:49:05.480954 progress 85 % (4 MB)
41 22:49:05.482659 progress 90 % (4 MB)
42 22:49:05.484393 progress 95 % (5 MB)
43 22:49:05.485940 progress 100 % (5 MB)
44 22:49:05.486173 5 MB downloaded in 0.38 s (14.03 MB/s)
45 22:49:05.486350 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:49:05.486628 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:49:05.486727 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:49:05.486822 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:49:05.486972 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:49:05.487051 saving as /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/kernel/Image
52 22:49:05.487121 total size: 54682112 (52 MB)
53 22:49:05.487192 No compression specified
54 22:49:05.496859 progress 0 % (0 MB)
55 22:49:05.512267 progress 5 % (2 MB)
56 22:49:05.527783 progress 10 % (5 MB)
57 22:49:05.543434 progress 15 % (7 MB)
58 22:49:05.558989 progress 20 % (10 MB)
59 22:49:05.574693 progress 25 % (13 MB)
60 22:49:05.590177 progress 30 % (15 MB)
61 22:49:05.605835 progress 35 % (18 MB)
62 22:49:05.621208 progress 40 % (20 MB)
63 22:49:05.636503 progress 45 % (23 MB)
64 22:49:05.652068 progress 50 % (26 MB)
65 22:49:05.667383 progress 55 % (28 MB)
66 22:49:05.683098 progress 60 % (31 MB)
67 22:49:05.698441 progress 65 % (33 MB)
68 22:49:05.713924 progress 70 % (36 MB)
69 22:49:05.729183 progress 75 % (39 MB)
70 22:49:05.744639 progress 80 % (41 MB)
71 22:49:05.759992 progress 85 % (44 MB)
72 22:49:05.775342 progress 90 % (46 MB)
73 22:49:05.790752 progress 95 % (49 MB)
74 22:49:05.805919 progress 100 % (52 MB)
75 22:49:05.806223 52 MB downloaded in 0.32 s (163.43 MB/s)
76 22:49:05.806399 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:49:05.806666 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:49:05.806772 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:49:05.806873 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:49:05.807025 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 22:49:05.807106 saving as /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 22:49:05.807178 total size: 57695 (0 MB)
84 22:49:05.807258 No compression specified
85 22:49:05.808514 progress 56 % (0 MB)
86 22:49:05.808825 progress 100 % (0 MB)
87 22:49:05.809053 0 MB downloaded in 0.00 s (29.40 MB/s)
88 22:49:05.809193 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:49:05.809446 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:49:05.809541 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:49:05.809634 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:49:05.809763 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:49:05.809839 saving as /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/nfsrootfs/full.rootfs.tar
95 22:49:05.809907 total size: 120894716 (115 MB)
96 22:49:05.809979 Using unxz to decompress xz
97 22:49:05.814342 progress 0 % (0 MB)
98 22:49:06.201929 progress 5 % (5 MB)
99 22:49:06.603741 progress 10 % (11 MB)
100 22:49:06.994073 progress 15 % (17 MB)
101 22:49:07.358200 progress 20 % (23 MB)
102 22:49:07.683557 progress 25 % (28 MB)
103 22:49:08.081431 progress 30 % (34 MB)
104 22:49:08.456921 progress 35 % (40 MB)
105 22:49:08.642664 progress 40 % (46 MB)
106 22:49:08.842655 progress 45 % (51 MB)
107 22:49:09.188912 progress 50 % (57 MB)
108 22:49:09.603792 progress 55 % (63 MB)
109 22:49:09.987440 progress 60 % (69 MB)
110 22:49:10.376554 progress 65 % (74 MB)
111 22:49:10.763958 progress 70 % (80 MB)
112 22:49:11.165794 progress 75 % (86 MB)
113 22:49:11.556872 progress 80 % (92 MB)
114 22:49:11.939662 progress 85 % (98 MB)
115 22:49:12.336530 progress 90 % (103 MB)
116 22:49:12.697683 progress 95 % (109 MB)
117 22:49:13.089404 progress 100 % (115 MB)
118 22:49:13.095444 115 MB downloaded in 7.29 s (15.83 MB/s)
119 22:49:13.095764 end: 1.4.1 http-download (duration 00:00:07) [common]
121 22:49:13.096207 end: 1.4 download-retry (duration 00:00:07) [common]
122 22:49:13.096341 start: 1.5 download-retry (timeout 00:09:52) [common]
123 22:49:13.096471 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 22:49:13.096666 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:49:13.096774 saving as /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/modules/modules.tar
126 22:49:13.096875 total size: 8594396 (8 MB)
127 22:49:13.096980 Using unxz to decompress xz
128 22:49:13.349945 progress 0 % (0 MB)
129 22:49:13.371737 progress 5 % (0 MB)
130 22:49:13.399264 progress 10 % (0 MB)
131 22:49:13.426003 progress 15 % (1 MB)
132 22:49:13.452340 progress 20 % (1 MB)
133 22:49:13.479845 progress 25 % (2 MB)
134 22:49:13.506423 progress 30 % (2 MB)
135 22:49:13.532735 progress 35 % (2 MB)
136 22:49:13.560403 progress 40 % (3 MB)
137 22:49:13.588429 progress 45 % (3 MB)
138 22:49:13.616014 progress 50 % (4 MB)
139 22:49:13.643293 progress 55 % (4 MB)
140 22:49:13.671905 progress 60 % (4 MB)
141 22:49:13.699447 progress 65 % (5 MB)
142 22:49:13.726946 progress 70 % (5 MB)
143 22:49:13.753597 progress 75 % (6 MB)
144 22:49:13.781838 progress 80 % (6 MB)
145 22:49:13.810047 progress 85 % (6 MB)
146 22:49:13.841821 progress 90 % (7 MB)
147 22:49:13.873682 progress 95 % (7 MB)
148 22:49:13.902608 progress 100 % (8 MB)
149 22:49:13.908299 8 MB downloaded in 0.81 s (10.10 MB/s)
150 22:49:13.908580 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:49:13.908876 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:49:13.908980 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:49:13.909086 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:49:17.796606 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13683657/extract-nfsrootfs-slg4lw9x
156 22:49:17.796866 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 22:49:17.797031 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 22:49:17.797290 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3
159 22:49:17.797492 makedir: /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin
160 22:49:17.797654 makedir: /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/tests
161 22:49:17.797816 makedir: /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/results
162 22:49:17.797985 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-add-keys
163 22:49:17.798221 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-add-sources
164 22:49:17.798435 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-background-process-start
165 22:49:17.798628 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-background-process-stop
166 22:49:17.798809 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-common-functions
167 22:49:17.798988 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-echo-ipv4
168 22:49:17.799166 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-install-packages
169 22:49:17.799508 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-installed-packages
170 22:49:17.799654 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-os-build
171 22:49:17.799795 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-probe-channel
172 22:49:17.799936 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-probe-ip
173 22:49:17.800075 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-target-ip
174 22:49:17.800214 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-target-mac
175 22:49:17.800352 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-target-storage
176 22:49:17.800493 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-test-case
177 22:49:17.800633 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-test-event
178 22:49:17.800772 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-test-feedback
179 22:49:17.800910 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-test-raise
180 22:49:17.801047 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-test-reference
181 22:49:17.801185 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-test-runner
182 22:49:17.801323 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-test-set
183 22:49:17.801460 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-test-shell
184 22:49:17.805849 Updating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-add-keys (debian)
185 22:49:17.806180 Updating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-add-sources (debian)
186 22:49:17.806468 Updating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-install-packages (debian)
187 22:49:17.806759 Updating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-installed-packages (debian)
188 22:49:17.807037 Updating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/bin/lava-os-build (debian)
189 22:49:17.807284 Creating /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/environment
190 22:49:17.807406 LAVA metadata
191 22:49:17.807490 - LAVA_JOB_ID=13683657
192 22:49:17.807563 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:49:17.807755 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 22:49:17.807834 skipped lava-vland-overlay
195 22:49:17.807920 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:49:17.808013 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 22:49:17.808084 skipped lava-multinode-overlay
198 22:49:17.808164 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:49:17.808252 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 22:49:17.808340 Loading test definitions
201 22:49:17.808441 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 22:49:17.808522 Using /lava-13683657 at stage 0
203 22:49:17.808844 uuid=13683657_1.6.2.3.1 testdef=None
204 22:49:17.808944 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:49:17.809040 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 22:49:17.809548 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:49:17.809792 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 22:49:17.810414 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:49:17.810670 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 22:49:17.811397 runner path: /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/0/tests/0_timesync-off test_uuid 13683657_1.6.2.3.1
213 22:49:17.811578 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:49:17.811833 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 22:49:17.811914 Using /lava-13683657 at stage 0
217 22:49:17.812025 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:49:17.812124 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/0/tests/1_kselftest-alsa'
219 22:49:20.637832 Running '/usr/bin/git checkout kernelci.org
220 22:49:20.802247 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 22:49:20.803109 uuid=13683657_1.6.2.3.5 testdef=None
222 22:49:20.803318 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 22:49:20.803600 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 22:49:20.804468 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:49:20.804741 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 22:49:20.805845 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:49:20.806115 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 22:49:20.807155 runner path: /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/0/tests/1_kselftest-alsa test_uuid 13683657_1.6.2.3.5
232 22:49:20.807270 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 22:49:20.807345 BRANCH='cip'
234 22:49:20.807413 SKIPFILE='/dev/null'
235 22:49:20.807478 SKIP_INSTALL='True'
236 22:49:20.807543 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:49:20.807610 TST_CASENAME=''
238 22:49:20.807672 TST_CMDFILES='alsa'
239 22:49:20.807841 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:49:20.808163 Creating lava-test-runner.conf files
242 22:49:20.808263 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683657/lava-overlay-eetzpvh3/lava-13683657/0 for stage 0
243 22:49:20.808376 - 0_timesync-off
244 22:49:20.808460 - 1_kselftest-alsa
245 22:49:20.808571 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 22:49:20.808671 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 22:49:29.174812 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:49:29.174992 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 22:49:29.175099 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:49:29.175203 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 22:49:29.175313 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 22:49:29.357938 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:49:29.358382 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 22:49:29.358517 extracting modules file /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683657/extract-nfsrootfs-slg4lw9x
255 22:49:29.602638 extracting modules file /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683657/extract-overlay-ramdisk-_v0a1lg8/ramdisk
256 22:49:29.851793 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:49:29.852001 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 22:49:29.852140 [common] Applying overlay to NFS
259 22:49:29.852233 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683657/compress-overlay-8xc8pco4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683657/extract-nfsrootfs-slg4lw9x
260 22:49:30.880698 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:49:30.880895 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 22:49:30.881004 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:49:30.881106 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 22:49:30.881200 Building ramdisk /var/lib/lava/dispatcher/tmp/13683657/extract-overlay-ramdisk-_v0a1lg8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683657/extract-overlay-ramdisk-_v0a1lg8/ramdisk
265 22:49:31.258655 >> 130327 blocks
266 22:49:33.520319 rename /var/lib/lava/dispatcher/tmp/13683657/extract-overlay-ramdisk-_v0a1lg8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/ramdisk/ramdisk.cpio.gz
267 22:49:33.520831 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 22:49:33.520969 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 22:49:33.521091 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 22:49:33.521212 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/kernel/Image'
271 22:49:48.157718 Returned 0 in 14 seconds
272 22:49:48.258660 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/kernel/image.itb
273 22:49:48.684631 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:49:48.685047 output: Created: Tue May 7 23:49:48 2024
275 22:49:48.685133 output: Image 0 (kernel-1)
276 22:49:48.685206 output: Description:
277 22:49:48.685274 output: Created: Tue May 7 23:49:48 2024
278 22:49:48.685344 output: Type: Kernel Image
279 22:49:48.685413 output: Compression: lzma compressed
280 22:49:48.685480 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
281 22:49:48.685544 output: Architecture: AArch64
282 22:49:48.685611 output: OS: Linux
283 22:49:48.685676 output: Load Address: 0x00000000
284 22:49:48.685740 output: Entry Point: 0x00000000
285 22:49:48.685807 output: Hash algo: crc32
286 22:49:48.685873 output: Hash value: 727ee7c6
287 22:49:48.685941 output: Image 1 (fdt-1)
288 22:49:48.686004 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 22:49:48.686065 output: Created: Tue May 7 23:49:48 2024
290 22:49:48.686125 output: Type: Flat Device Tree
291 22:49:48.686185 output: Compression: uncompressed
292 22:49:48.686244 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 22:49:48.686303 output: Architecture: AArch64
294 22:49:48.686363 output: Hash algo: crc32
295 22:49:48.686422 output: Hash value: a9713552
296 22:49:48.686482 output: Image 2 (ramdisk-1)
297 22:49:48.686540 output: Description: unavailable
298 22:49:48.686599 output: Created: Tue May 7 23:49:48 2024
299 22:49:48.686657 output: Type: RAMDisk Image
300 22:49:48.686717 output: Compression: Unknown Compression
301 22:49:48.686776 output: Data Size: 18726583 Bytes = 18287.68 KiB = 17.86 MiB
302 22:49:48.686836 output: Architecture: AArch64
303 22:49:48.686896 output: OS: Linux
304 22:49:48.686955 output: Load Address: unavailable
305 22:49:48.687014 output: Entry Point: unavailable
306 22:49:48.687073 output: Hash algo: crc32
307 22:49:48.687132 output: Hash value: 45bb0ba5
308 22:49:48.687191 output: Default Configuration: 'conf-1'
309 22:49:48.687257 output: Configuration 0 (conf-1)
310 22:49:48.687316 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 22:49:48.687376 output: Kernel: kernel-1
312 22:49:48.687435 output: Init Ramdisk: ramdisk-1
313 22:49:48.687494 output: FDT: fdt-1
314 22:49:48.687554 output: Loadables: kernel-1
315 22:49:48.687613 output:
316 22:49:48.687843 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 22:49:48.687949 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 22:49:48.688065 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 22:49:48.688172 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 22:49:48.688265 No LXC device requested
321 22:49:48.688354 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:49:48.688453 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 22:49:48.688542 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:49:48.688624 Checking files for TFTP limit of 4294967296 bytes.
325 22:49:48.689183 end: 1 tftp-deploy (duration 00:00:44) [common]
326 22:49:48.689307 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:49:48.689415 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:49:48.689557 substitutions:
329 22:49:48.689641 - {DTB}: 13683657/tftp-deploy-59_93ml8/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 22:49:48.689718 - {INITRD}: 13683657/tftp-deploy-59_93ml8/ramdisk/ramdisk.cpio.gz
331 22:49:48.689786 - {KERNEL}: 13683657/tftp-deploy-59_93ml8/kernel/Image
332 22:49:48.689851 - {LAVA_MAC}: None
333 22:49:48.689915 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13683657/extract-nfsrootfs-slg4lw9x
334 22:49:48.689978 - {NFS_SERVER_IP}: 192.168.201.1
335 22:49:48.690040 - {PRESEED_CONFIG}: None
336 22:49:48.690101 - {PRESEED_LOCAL}: None
337 22:49:48.690162 - {RAMDISK}: 13683657/tftp-deploy-59_93ml8/ramdisk/ramdisk.cpio.gz
338 22:49:48.690224 - {ROOT_PART}: None
339 22:49:48.690284 - {ROOT}: None
340 22:49:48.690345 - {SERVER_IP}: 192.168.201.1
341 22:49:48.690405 - {TEE}: None
342 22:49:48.690466 Parsed boot commands:
343 22:49:48.690525 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:49:48.690720 Parsed boot commands: tftpboot 192.168.201.1 13683657/tftp-deploy-59_93ml8/kernel/image.itb 13683657/tftp-deploy-59_93ml8/kernel/cmdline
345 22:49:48.690821 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:49:48.690913 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:49:48.691015 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:49:48.691110 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:49:48.691191 Not connected, no need to disconnect.
350 22:49:48.691280 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:49:48.691369 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:49:48.691444 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-2'
353 22:49:48.695652 Setting prompt string to ['lava-test: # ']
354 22:49:48.696054 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:49:48.696171 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:49:48.696278 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:49:48.696383 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:49:48.696588 Calling: '/usr/local/bin/chromebook-reboot.sh' 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-2'
359 22:50:11.817981 Returned 0 in 23 seconds
360 22:50:11.918683 end: 2.2.2.1 pdu-reboot (duration 00:00:23) [common]
362 22:50:11.919044 end: 2.2.2 reset-device (duration 00:00:23) [common]
363 22:50:11.919151 start: 2.2.3 depthcharge-start (timeout 00:04:37) [common]
364 22:50:11.919259 Setting prompt string to 'Starting depthcharge on Juniper...'
365 22:50:11.919338 Changing prompt to 'Starting depthcharge on Juniper...'
366 22:50:11.919418 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 22:50:11.919740 [Enter `^Ec?' for help]
368 22:50:11.919833 [DL] 00000000 00000000 010701
369 22:50:11.919911
370 22:50:11.919981
371 22:50:11.920050 F0: 102B 0000
372 22:50:11.920116
373 22:50:11.920182 F3: 1006 0033 [0200]
374 22:50:11.920245
375 22:50:11.920307 F3: 4001 00E0 [0200]
376 22:50:11.920370
377 22:50:11.920432 F3: 0000 0000
378 22:50:11.920494
379 22:50:11.920555 V0: 0000 0000 [0001]
380 22:50:11.920616
381 22:50:11.920677 00: 1027 0002
382 22:50:11.920742
383 22:50:11.920808 01: 0000 0000
384 22:50:11.920871
385 22:50:11.920932 BP: 0C00 0251 [0000]
386 22:50:11.920993
387 22:50:11.921054 G0: 1182 0000
388 22:50:11.921115
389 22:50:11.921176 EC: 0004 0000 [0001]
390 22:50:11.921237
391 22:50:11.921297 S7: 0000 0000 [0000]
392 22:50:11.921358
393 22:50:11.921418 CC: 0000 0000 [0001]
394 22:50:11.921478
395 22:50:11.921538 T0: 0000 00DB [000F]
396 22:50:11.921600
397 22:50:11.921660 Jump to BL
398 22:50:11.921721
399 22:50:11.921781
400 22:50:11.921841
401 22:50:11.921901
402 22:50:11.921962 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
403 22:50:11.922029 ARM64: Exception handlers installed.
404 22:50:11.922091 ARM64: Testing exception
405 22:50:11.922151 ARM64: Done test exception
406 22:50:11.922213 WDT: Last reset was cold boot
407 22:50:11.922274 SPI0(PAD0) initialized at 992727 Hz
408 22:50:11.922335 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
409 22:50:11.922396 Manufacturer: ef
410 22:50:11.922456 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
411 22:50:11.922518 Probing TPM: . done!
412 22:50:11.922579 TPM ready after 0 ms
413 22:50:11.922641 Connected to device vid:did:rid of 1ae0:0028:00
414 22:50:11.922701 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.3.25/cr50_v1.9308_87_mp.398-afa1dd1
415 22:50:11.922763 Initialized TPM device CR50 revision 0
416 22:50:11.922835 tlcl_send_startup: Startup return code is 0
417 22:50:11.922899 TPM: setup succeeded
418 22:50:11.922960 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
419 22:50:11.923022 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
420 22:50:11.923084 in-header: 03 19 00 00 08 00 00 00
421 22:50:11.923144 in-data: a2 e0 47 00 13 00 00 00
422 22:50:11.923205 Chrome EC: UHEPI supported
423 22:50:11.923276 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
424 22:50:11.923339 in-header: 03 a1 00 00 08 00 00 00
425 22:50:11.923401 in-data: 84 60 60 10 00 00 00 00
426 22:50:11.923462 Phase 1
427 22:50:11.923523 FMAP: area GBB found @ 3f5000 (12032 bytes)
428 22:50:11.923586 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
429 22:50:11.923647 VB2:vb2_check_recovery() Recovery was requested manually
430 22:50:11.923708 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
431 22:50:11.923770 Recovery requested (1009000e)
432 22:50:11.923831 tlcl_extend: response is 0
433 22:50:11.923891 tlcl_extend: response is 0
434 22:50:11.923952
435 22:50:11.924013
436 22:50:11.924073 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
437 22:50:11.924136 ARM64: Exception handlers installed.
438 22:50:11.924197 ARM64: Testing exception
439 22:50:11.924257 ARM64: Done test exception
440 22:50:11.924318 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x926b, sec=0x2015
441 22:50:11.924379 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
442 22:50:11.924440 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
443 22:50:11.924502 [RTC]rtc_get_frequency_meter,134: input=0xf, output=863
444 22:50:11.924562 [RTC]rtc_get_frequency_meter,134: input=0x7, output=734
445 22:50:11.924623 [RTC]rtc_get_frequency_meter,134: input=0xb, output=799
446 22:50:11.924684 [RTC]rtc_get_frequency_meter,134: input=0x9, output=767
447 22:50:11.924744 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783
448 22:50:11.924804 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783
449 22:50:11.924865 [RTC]rtc_get_frequency_meter,134: input=0xb, output=798
450 22:50:11.924925 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x926b
451 22:50:11.924985 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
452 22:50:11.925045 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
453 22:50:11.925107 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
454 22:50:11.925167 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
455 22:50:11.925228 in-header: 03 19 00 00 08 00 00 00
456 22:50:11.925289 in-data: a2 e0 47 00 13 00 00 00
457 22:50:11.925350 Chrome EC: UHEPI supported
458 22:50:11.925410 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
459 22:50:11.925471 in-header: 03 a1 00 00 08 00 00 00
460 22:50:11.925532 in-data: 84 60 60 10 00 00 00 00
461 22:50:11.925593 Skip loading cached calibration data
462 22:50:11.925653 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
463 22:50:11.925714 in-header: 03 a1 00 00 08 00 00 00
464 22:50:11.925774 in-data: 84 60 60 10 00 00 00 00
465 22:50:11.925835 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
466 22:50:11.925897 in-header: 03 a1 00 00 08 00 00 00
467 22:50:11.925957 in-data: 84 60 60 10 00 00 00 00
468 22:50:11.926017 ADC[3]: Raw value=216472 ID=1
469 22:50:11.926078 Manufacturer: ef
470 22:50:11.926139 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
471 22:50:11.926200 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
472 22:50:11.926261 CBFS @ 21000 size 3d4000
473 22:50:11.926322 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
474 22:50:11.926382 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
475 22:50:11.926443 CBFS: Found @ offset 3c700 size 44
476 22:50:11.926504 DRAM-K: Full Calibration
477 22:50:11.926564 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
478 22:50:11.926625 CBFS @ 21000 size 3d4000
479 22:50:11.926688 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
480 22:50:11.926748 CBFS: Locating 'fallback/dram'
481 22:50:11.926809 CBFS: Found @ offset 24b00 size 12268
482 22:50:11.926869 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
483 22:50:11.926930 ddr_geometry: 1, config: 0x0
484 22:50:11.926991 header.status = 0x0
485 22:50:11.927051 header.magic = 0x44524d4b (expected: 0x44524d4b)
486 22:50:11.927111 header.version = 0x5 (expected: 0x5)
487 22:50:11.927367 header.size = 0x8f0 (expected: 0x8f0)
488 22:50:11.927491 header.config = 0x0
489 22:50:11.927613 header.flags = 0x0
490 22:50:11.927734 header.checksum = 0x0
491 22:50:11.927856 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
492 22:50:11.927979 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
493 22:50:11.928099 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
494 22:50:11.928205 ddr_geometry:1
495 22:50:11.928302 [EMI] new MDL number = 1
496 22:50:11.928400 dram_cbt_mode_extern: 0
497 22:50:11.928520 dram_cbt_mode [RK0]: 0, [RK1]: 0
498 22:50:11.928621 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
499 22:50:11.928716
500 22:50:11.928811
501 22:50:11.928906 [Bianco] ETT version 0.0.0.1
502 22:50:11.929001 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
503 22:50:11.929096
504 22:50:11.929191 vSetVcoreByFreq with vcore:762500, freq=1600
505 22:50:11.929288
506 22:50:11.929382 [DramcInit]
507 22:50:11.929477 AutoRefreshCKEOff AutoREF OFF
508 22:50:11.929571 DDRPhyPLLSetting-CKEOFF
509 22:50:11.929665 DDRPhyPLLSetting-CKEON
510 22:50:11.929758
511 22:50:11.929853 Enable WDQS
512 22:50:11.929947 [ModeRegInit_LP4] CH0 RK0
513 22:50:11.930041 Write Rank0 MR13 =0x18
514 22:50:11.930136 Write Rank0 MR12 =0x5d
515 22:50:11.930206 Write Rank0 MR1 =0x56
516 22:50:11.930274 Write Rank0 MR2 =0x1a
517 22:50:11.930341 Write Rank0 MR11 =0x0
518 22:50:11.930403 Write Rank0 MR22 =0x38
519 22:50:11.930463 Write Rank0 MR14 =0x5d
520 22:50:11.930524 Write Rank0 MR3 =0x30
521 22:50:11.930585 Write Rank0 MR13 =0x58
522 22:50:11.930645 Write Rank0 MR12 =0x5d
523 22:50:11.930705 Write Rank0 MR1 =0x56
524 22:50:11.930765 Write Rank0 MR2 =0x2d
525 22:50:11.930825 Write Rank0 MR11 =0x23
526 22:50:11.930886 Write Rank0 MR22 =0x34
527 22:50:11.930946 Write Rank0 MR14 =0x10
528 22:50:11.931006 Write Rank0 MR3 =0x30
529 22:50:11.931067 Write Rank0 MR13 =0xd8
530 22:50:11.931127 [ModeRegInit_LP4] CH0 RK1
531 22:50:11.931187 Write Rank1 MR13 =0x18
532 22:50:11.931260 Write Rank1 MR12 =0x5d
533 22:50:11.931322 Write Rank1 MR1 =0x56
534 22:50:11.931382 Write Rank1 MR2 =0x1a
535 22:50:11.931442 Write Rank1 MR11 =0x0
536 22:50:11.931503 Write Rank1 MR22 =0x38
537 22:50:11.931563 Write Rank1 MR14 =0x5d
538 22:50:11.931622 Write Rank1 MR3 =0x30
539 22:50:11.931682 Write Rank1 MR13 =0x58
540 22:50:11.931742 Write Rank1 MR12 =0x5d
541 22:50:11.931803 Write Rank1 MR1 =0x56
542 22:50:11.931862 Write Rank1 MR2 =0x2d
543 22:50:11.931923 Write Rank1 MR11 =0x23
544 22:50:11.931983 Write Rank1 MR22 =0x34
545 22:50:11.932043 Write Rank1 MR14 =0x10
546 22:50:11.932102 Write Rank1 MR3 =0x30
547 22:50:11.932162 Write Rank1 MR13 =0xd8
548 22:50:11.932225 [ModeRegInit_LP4] CH1 RK0
549 22:50:11.932288 Write Rank0 MR13 =0x18
550 22:50:11.932353 Write Rank0 MR12 =0x5d
551 22:50:11.932414 Write Rank0 MR1 =0x56
552 22:50:11.932475 Write Rank0 MR2 =0x1a
553 22:50:11.932541 Write Rank0 MR11 =0x0
554 22:50:11.932606 Write Rank0 MR22 =0x38
555 22:50:11.932666 Write Rank0 MR14 =0x5d
556 22:50:11.932726 Write Rank0 MR3 =0x30
557 22:50:11.932786 Write Rank0 MR13 =0x58
558 22:50:11.932847 Write Rank0 MR12 =0x5d
559 22:50:11.932907 Write Rank0 MR1 =0x56
560 22:50:11.932967 Write Rank0 MR2 =0x2d
561 22:50:11.933027 Write Rank0 MR11 =0x23
562 22:50:11.933086 Write Rank0 MR22 =0x34
563 22:50:11.933146 Write Rank0 MR14 =0x10
564 22:50:11.933206 Write Rank0 MR3 =0x30
565 22:50:11.933266 Write Rank0 MR13 =0xd8
566 22:50:11.933332 [ModeRegInit_LP4] CH1 RK1
567 22:50:11.933394 Write Rank1 MR13 =0x18
568 22:50:11.933454 Write Rank1 MR12 =0x5d
569 22:50:11.933515 Write Rank1 MR1 =0x56
570 22:50:11.933575 Write Rank1 MR2 =0x1a
571 22:50:11.933635 Write Rank1 MR11 =0x0
572 22:50:11.933695 Write Rank1 MR22 =0x38
573 22:50:11.933755 Write Rank1 MR14 =0x5d
574 22:50:11.933814 Write Rank1 MR3 =0x30
575 22:50:11.933875 Write Rank1 MR13 =0x58
576 22:50:11.933935 Write Rank1 MR12 =0x5d
577 22:50:11.933995 Write Rank1 MR1 =0x56
578 22:50:11.934055 Write Rank1 MR2 =0x2d
579 22:50:11.934115 Write Rank1 MR11 =0x23
580 22:50:11.934176 Write Rank1 MR22 =0x34
581 22:50:11.934236 Write Rank1 MR14 =0x10
582 22:50:11.934296 Write Rank1 MR3 =0x30
583 22:50:11.934355 Write Rank1 MR13 =0xd8
584 22:50:11.934415 match AC timing 3
585 22:50:11.934476 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
586 22:50:11.934538 [MiockJmeterHQA]
587 22:50:11.934599 vSetVcoreByFreq with vcore:762500, freq=1600
588 22:50:11.934660
589 22:50:11.934720 MIOCK jitter meter ch=0
590 22:50:11.934781
591 22:50:11.934841 1T = (102-18) = 84 dly cells
592 22:50:11.934907 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 744/100 ps
593 22:50:11.934969 vSetVcoreByFreq with vcore:725000, freq=1200
594 22:50:11.935030
595 22:50:11.935091 MIOCK jitter meter ch=0
596 22:50:11.935151
597 22:50:11.935211 1T = (97-17) = 80 dly cells
598 22:50:11.935284 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
599 22:50:11.935346 vSetVcoreByFreq with vcore:725000, freq=800
600 22:50:11.935406
601 22:50:11.935467 MIOCK jitter meter ch=0
602 22:50:11.935528
603 22:50:11.935589 1T = (97-17) = 80 dly cells
604 22:50:11.935652 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
605 22:50:11.935713 vSetVcoreByFreq with vcore:762500, freq=1600
606 22:50:11.935774 vSetVcoreByFreq with vcore:762500, freq=1600
607 22:50:11.935835
608 22:50:11.935898 K DRVP
609 22:50:11.935962 1. OCD DRVP=0 CALOUT=0
610 22:50:11.936030 1. OCD DRVP=1 CALOUT=0
611 22:50:11.936092 1. OCD DRVP=2 CALOUT=0
612 22:50:11.936154 1. OCD DRVP=3 CALOUT=0
613 22:50:11.936217 1. OCD DRVP=4 CALOUT=0
614 22:50:11.936279 1. OCD DRVP=5 CALOUT=0
615 22:50:11.936340 1. OCD DRVP=6 CALOUT=0
616 22:50:11.936409 1. OCD DRVP=7 CALOUT=0
617 22:50:11.936476 1. OCD DRVP=8 CALOUT=1
618 22:50:11.936540
619 22:50:11.936602 1. OCD DRVP calibration OK! DRVP=8
620 22:50:11.936665
621 22:50:11.936730
622 22:50:11.936792
623 22:50:11.936852 K ODTN
624 22:50:11.936913 3. OCD ODTN=0 ,CALOUT=1
625 22:50:11.936978 3. OCD ODTN=1 ,CALOUT=1
626 22:50:11.937040 3. OCD ODTN=2 ,CALOUT=1
627 22:50:11.937102 3. OCD ODTN=3 ,CALOUT=1
628 22:50:11.937164 3. OCD ODTN=4 ,CALOUT=1
629 22:50:11.937226 3. OCD ODTN=5 ,CALOUT=1
630 22:50:11.937288 3. OCD ODTN=6 ,CALOUT=1
631 22:50:11.937350 3. OCD ODTN=7 ,CALOUT=0
632 22:50:11.937412
633 22:50:11.937474 3. OCD ODTN calibration OK! ODTN=7
634 22:50:11.937537
635 22:50:11.937598 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
636 22:50:11.937659 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
637 22:50:11.937720 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
638 22:50:11.937781
639 22:50:11.937842 K DRVP
640 22:50:11.937902 1. OCD DRVP=0 CALOUT=0
641 22:50:11.937965 1. OCD DRVP=1 CALOUT=0
642 22:50:11.938027 1. OCD DRVP=2 CALOUT=0
643 22:50:11.938089 1. OCD DRVP=3 CALOUT=0
644 22:50:11.938151 1. OCD DRVP=4 CALOUT=0
645 22:50:11.938213 1. OCD DRVP=5 CALOUT=0
646 22:50:11.938275 1. OCD DRVP=6 CALOUT=0
647 22:50:11.938336 1. OCD DRVP=7 CALOUT=0
648 22:50:11.938398 1. OCD DRVP=8 CALOUT=0
649 22:50:11.938460 1. OCD DRVP=9 CALOUT=0
650 22:50:11.938522 1. OCD DRVP=10 CALOUT=1
651 22:50:11.938584
652 22:50:11.938842 1. OCD DRVP calibration OK! DRVP=10
653 22:50:11.938973
654 22:50:11.939095
655 22:50:11.939216
656 22:50:11.939345 K ODTN
657 22:50:11.939451 3. OCD ODTN=0 ,CALOUT=1
658 22:50:11.939552 3. OCD ODTN=1 ,CALOUT=1
659 22:50:11.939650 3. OCD ODTN=2 ,CALOUT=1
660 22:50:11.939748 3. OCD ODTN=3 ,CALOUT=1
661 22:50:11.939845 3. OCD ODTN=4 ,CALOUT=1
662 22:50:11.939949 3. OCD ODTN=5 ,CALOUT=1
663 22:50:11.940047 3. OCD ODTN=6 ,CALOUT=1
664 22:50:11.940114 3. OCD ODTN=7 ,CALOUT=1
665 22:50:11.940177 3. OCD ODTN=8 ,CALOUT=1
666 22:50:11.940240 3. OCD ODTN=9 ,CALOUT=1
667 22:50:11.940303 3. OCD ODTN=10 ,CALOUT=1
668 22:50:11.940370 3. OCD ODTN=11 ,CALOUT=1
669 22:50:11.940437 3. OCD ODTN=12 ,CALOUT=1
670 22:50:11.940500 3. OCD ODTN=13 ,CALOUT=1
671 22:50:11.940563 3. OCD ODTN=14 ,CALOUT=1
672 22:50:11.940626 3. OCD ODTN=15 ,CALOUT=0
673 22:50:11.940687
674 22:50:11.940749 3. OCD ODTN calibration OK! ODTN=15
675 22:50:11.940812
676 22:50:11.940874 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
677 22:50:11.940936 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
678 22:50:11.940997 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
679 22:50:11.941059
680 22:50:11.941119 [DramcInit]
681 22:50:11.941180 AutoRefreshCKEOff AutoREF OFF
682 22:50:11.941241 DDRPhyPLLSetting-CKEOFF
683 22:50:11.941302 DDRPhyPLLSetting-CKEON
684 22:50:11.941362
685 22:50:11.941423 Enable WDQS
686 22:50:11.941484 ==
687 22:50:11.941545 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
688 22:50:11.941606 fsp= 1, odt_onoff= 1, Byte mode= 0
689 22:50:11.941667 ==
690 22:50:11.941728 [Duty_Offset_Calibration]
691 22:50:11.941789
692 22:50:11.941849 ===========================
693 22:50:11.941911 B0:1 B1:-1 CA:0
694 22:50:11.941971 ==
695 22:50:11.942033 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
696 22:50:11.942094 fsp= 1, odt_onoff= 1, Byte mode= 0
697 22:50:11.942155 ==
698 22:50:11.942215 [Duty_Offset_Calibration]
699 22:50:11.942276
700 22:50:11.942337 ===========================
701 22:50:11.942398 B0:0 B1:0 CA:0
702 22:50:11.942458 [ModeRegInit_LP4] CH0 RK0
703 22:50:11.942519 Write Rank0 MR13 =0x18
704 22:50:11.942579 Write Rank0 MR12 =0x5d
705 22:50:11.942639 Write Rank0 MR1 =0x56
706 22:50:11.942700 Write Rank0 MR2 =0x1a
707 22:50:11.942761 Write Rank0 MR11 =0x0
708 22:50:11.942820 Write Rank0 MR22 =0x38
709 22:50:11.942880 Write Rank0 MR14 =0x5d
710 22:50:11.942940 Write Rank0 MR3 =0x30
711 22:50:11.943001 Write Rank0 MR13 =0x58
712 22:50:11.943060 Write Rank0 MR12 =0x5d
713 22:50:11.943121 Write Rank0 MR1 =0x56
714 22:50:11.943181 Write Rank0 MR2 =0x2d
715 22:50:11.943250 Write Rank0 MR11 =0x23
716 22:50:11.943312 Write Rank0 MR22 =0x34
717 22:50:11.943372 Write Rank0 MR14 =0x10
718 22:50:11.943433 Write Rank0 MR3 =0x30
719 22:50:11.943499 Write Rank0 MR13 =0xd8
720 22:50:11.943560 [ModeRegInit_LP4] CH0 RK1
721 22:50:11.943622 Write Rank1 MR13 =0x18
722 22:50:11.943682 Write Rank1 MR12 =0x5d
723 22:50:11.943743 Write Rank1 MR1 =0x56
724 22:50:11.943803 Write Rank1 MR2 =0x1a
725 22:50:11.943863 Write Rank1 MR11 =0x0
726 22:50:11.943923 Write Rank1 MR22 =0x38
727 22:50:11.944003 Write Rank1 MR14 =0x5d
728 22:50:11.944070 Write Rank1 MR3 =0x30
729 22:50:11.944136 Write Rank1 MR13 =0x58
730 22:50:11.944198 Write Rank1 MR12 =0x5d
731 22:50:11.944262 Write Rank1 MR1 =0x56
732 22:50:11.944330 Write Rank1 MR2 =0x2d
733 22:50:11.944420 Write Rank1 MR11 =0x23
734 22:50:11.944484 Write Rank1 MR22 =0x34
735 22:50:11.944546 Write Rank1 MR14 =0x10
736 22:50:11.944606 Write Rank1 MR3 =0x30
737 22:50:11.944667 Write Rank1 MR13 =0xd8
738 22:50:11.944727 [ModeRegInit_LP4] CH1 RK0
739 22:50:11.944788 Write Rank0 MR13 =0x18
740 22:50:11.944848 Write Rank0 MR12 =0x5d
741 22:50:11.944908 Write Rank0 MR1 =0x56
742 22:50:11.944969 Write Rank0 MR2 =0x1a
743 22:50:11.945029 Write Rank0 MR11 =0x0
744 22:50:11.945090 Write Rank0 MR22 =0x38
745 22:50:11.945150 Write Rank0 MR14 =0x5d
746 22:50:11.945210 Write Rank0 MR3 =0x30
747 22:50:11.945271 Write Rank0 MR13 =0x58
748 22:50:11.945331 Write Rank0 MR12 =0x5d
749 22:50:11.945392 Write Rank0 MR1 =0x56
750 22:50:11.945452 Write Rank0 MR2 =0x2d
751 22:50:11.945512 Write Rank0 MR11 =0x23
752 22:50:11.945572 Write Rank0 MR22 =0x34
753 22:50:11.945632 Write Rank0 MR14 =0x10
754 22:50:11.945692 Write Rank0 MR3 =0x30
755 22:50:11.945752 Write Rank0 MR13 =0xd8
756 22:50:11.945813 [ModeRegInit_LP4] CH1 RK1
757 22:50:11.945872 Write Rank1 MR13 =0x18
758 22:50:11.945932 Write Rank1 MR12 =0x5d
759 22:50:11.945992 Write Rank1 MR1 =0x56
760 22:50:11.946052 Write Rank1 MR2 =0x1a
761 22:50:11.946112 Write Rank1 MR11 =0x0
762 22:50:11.946171 Write Rank1 MR22 =0x38
763 22:50:11.946232 Write Rank1 MR14 =0x5d
764 22:50:11.946291 Write Rank1 MR3 =0x30
765 22:50:11.946351 Write Rank1 MR13 =0x58
766 22:50:11.946414 Write Rank1 MR12 =0x5d
767 22:50:11.946478 Write Rank1 MR1 =0x56
768 22:50:11.946538 Write Rank1 MR2 =0x2d
769 22:50:11.946598 Write Rank1 MR11 =0x23
770 22:50:11.946658 Write Rank1 MR22 =0x34
771 22:50:11.946719 Write Rank1 MR14 =0x10
772 22:50:11.946779 Write Rank1 MR3 =0x30
773 22:50:11.946839 Write Rank1 MR13 =0xd8
774 22:50:11.946900 match AC timing 3
775 22:50:11.946960 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
776 22:50:11.947022 DramC Write-DBI off
777 22:50:11.947081 DramC Read-DBI off
778 22:50:11.947149 Write Rank0 MR13 =0x59
779 22:50:11.947249 ==
780 22:50:11.947316 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
781 22:50:11.947378 fsp= 1, odt_onoff= 1, Byte mode= 0
782 22:50:11.947440 ==
783 22:50:11.947501 === u2Vref_new: 0x56 --> 0x2d
784 22:50:11.947563 === u2Vref_new: 0x58 --> 0x38
785 22:50:11.947624 === u2Vref_new: 0x5a --> 0x39
786 22:50:11.947685 === u2Vref_new: 0x5c --> 0x3c
787 22:50:11.947746 === u2Vref_new: 0x5e --> 0x3d
788 22:50:11.947807 === u2Vref_new: 0x60 --> 0xa0
789 22:50:11.947868 [CA 0] Center 34 (6~63) winsize 58
790 22:50:11.947935 [CA 1] Center 35 (7~63) winsize 57
791 22:50:11.948000 [CA 2] Center 28 (-1~58) winsize 60
792 22:50:11.948062 [CA 3] Center 23 (-4~51) winsize 56
793 22:50:11.948123 [CA 4] Center 24 (-4~52) winsize 57
794 22:50:11.948184 [CA 5] Center 29 (0~59) winsize 60
795 22:50:11.948245
796 22:50:11.948306 [CATrainingPosCal] consider 1 rank data
797 22:50:11.948367 u2DelayCellTimex100 = 744/100 ps
798 22:50:11.948428 CA0 delay=34 (6~63),Diff = 11 PI (14 cell)
799 22:50:11.948489 CA1 delay=35 (7~63),Diff = 12 PI (15 cell)
800 22:50:11.948550 CA2 delay=28 (-1~58),Diff = 5 PI (6 cell)
801 22:50:11.948611 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
802 22:50:11.948672 CA4 delay=24 (-4~52),Diff = 1 PI (1 cell)
803 22:50:11.948732 CA5 delay=29 (0~59),Diff = 6 PI (7 cell)
804 22:50:11.948793
805 22:50:11.948854 CA PerBit enable=1, Macro0, CA PI delay=23
806 22:50:11.948916 === u2Vref_new: 0x5c --> 0x3c
807 22:50:11.948976
808 22:50:11.949037 Vref(ca) range 1: 28
809 22:50:11.949097
810 22:50:11.949158 CS Dly= 8 (39-0-32)
811 22:50:11.949218 Write Rank0 MR13 =0xd8
812 22:50:11.949284 Write Rank0 MR13 =0xd8
813 22:50:11.949351 Write Rank0 MR12 =0x5c
814 22:50:11.949412 Write Rank1 MR13 =0x59
815 22:50:11.949473 ==
816 22:50:11.949759 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
817 22:50:11.949830 fsp= 1, odt_onoff= 1, Byte mode= 0
818 22:50:11.949893 ==
819 22:50:11.949955 === u2Vref_new: 0x56 --> 0x2d
820 22:50:11.950017 === u2Vref_new: 0x58 --> 0x38
821 22:50:11.950078 === u2Vref_new: 0x5a --> 0x39
822 22:50:11.950140 === u2Vref_new: 0x5c --> 0x3c
823 22:50:11.950201 === u2Vref_new: 0x5e --> 0x3d
824 22:50:11.950262 === u2Vref_new: 0x60 --> 0xa0
825 22:50:11.950323 [CA 0] Center 35 (8~63) winsize 56
826 22:50:11.950384 [CA 1] Center 35 (7~63) winsize 57
827 22:50:11.950445 [CA 2] Center 28 (-1~58) winsize 60
828 22:50:11.950505 [CA 3] Center 23 (-5~51) winsize 57
829 22:50:11.950565 [CA 4] Center 23 (-5~51) winsize 57
830 22:50:11.950626 [CA 5] Center 29 (0~59) winsize 60
831 22:50:11.950686
832 22:50:11.950748 [CATrainingPosCal] consider 2 rank data
833 22:50:11.950809 u2DelayCellTimex100 = 744/100 ps
834 22:50:11.950869 CA0 delay=35 (8~63),Diff = 12 PI (15 cell)
835 22:50:11.950930 CA1 delay=35 (7~63),Diff = 12 PI (15 cell)
836 22:50:11.950991 CA2 delay=28 (-1~58),Diff = 5 PI (6 cell)
837 22:50:11.951052 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
838 22:50:11.951112 CA4 delay=23 (-4~51),Diff = 0 PI (0 cell)
839 22:50:11.951173 CA5 delay=29 (0~59),Diff = 6 PI (7 cell)
840 22:50:11.951245
841 22:50:11.951308 CA PerBit enable=1, Macro0, CA PI delay=23
842 22:50:11.951370 === u2Vref_new: 0x5e --> 0x3d
843 22:50:11.951431
844 22:50:11.951492 Vref(ca) range 1: 30
845 22:50:11.951553
846 22:50:11.951614 CS Dly= 6 (37-0-32)
847 22:50:11.951675 Write Rank1 MR13 =0xd8
848 22:50:11.951735 Write Rank1 MR13 =0xd8
849 22:50:11.951795 Write Rank1 MR12 =0x5e
850 22:50:11.951856 [RankSwap] Rank num 2, (Multi 1), Rank 0
851 22:50:11.951917 Write Rank0 MR2 =0xad
852 22:50:11.951977 [Write Leveling]
853 22:50:11.952038 delay byte0 byte1 byte2 byte3
854 22:50:11.952099
855 22:50:11.952159 10 0 0
856 22:50:11.952221 11 0 0
857 22:50:11.952283 12 0 0
858 22:50:11.952345 13 0 0
859 22:50:11.952406 14 0 0
860 22:50:11.952467 15 0 0
861 22:50:11.952529 16 0 0
862 22:50:11.952591 17 0 0
863 22:50:11.952652 18 0 0
864 22:50:11.952713 19 0 0
865 22:50:11.952774 20 0 0
866 22:50:11.952836 21 0 0
867 22:50:11.952897 22 0 0
868 22:50:11.952959 23 0 0
869 22:50:11.953020 24 0 0
870 22:50:11.953081 25 0 0
871 22:50:11.953143 26 0 0
872 22:50:11.953204 27 0 ff
873 22:50:11.953266 28 0 ff
874 22:50:11.953328 29 0 ff
875 22:50:11.953389 30 0 ff
876 22:50:11.953451 31 ff ff
877 22:50:11.953512 32 ff ff
878 22:50:11.953573 33 ff ff
879 22:50:11.953635 34 ff ff
880 22:50:11.953695 35 ff ff
881 22:50:11.953757 36 ff ff
882 22:50:11.953819 37 ff ff
883 22:50:11.953881 pass bytecount = 0xff (0xff: all bytes pass)
884 22:50:11.953942
885 22:50:11.954003 DQS0 dly: 31
886 22:50:11.954063 DQS1 dly: 27
887 22:50:11.954123 Write Rank0 MR2 =0x2d
888 22:50:11.954185 [RankSwap] Rank num 2, (Multi 1), Rank 0
889 22:50:11.954246 Write Rank0 MR1 =0xd6
890 22:50:11.954306 [Gating]
891 22:50:11.954366 ==
892 22:50:11.954427 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
893 22:50:11.954488 fsp= 1, odt_onoff= 1, Byte mode= 0
894 22:50:11.954550 ==
895 22:50:11.954610 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
896 22:50:11.954673 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
897 22:50:11.954743 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(0 0)| 0
898 22:50:11.954845 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
899 22:50:11.954947 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
900 22:50:11.955014 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
901 22:50:11.955077 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
902 22:50:11.955139 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
903 22:50:11.955202 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
904 22:50:11.955272 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
905 22:50:11.955335 3 2 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
906 22:50:11.955397 3 2 12 |201 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
907 22:50:11.955460 3 2 16 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
908 22:50:11.955523 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
909 22:50:11.955585 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
910 22:50:11.955647 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
911 22:50:11.955708 3 3 0 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
912 22:50:11.955776 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
913 22:50:11.955838 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
914 22:50:11.955900 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
915 22:50:11.955963 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
916 22:50:11.956025 [Byte 0] Lead/lag Transition tap number (1)
917 22:50:11.956087 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
918 22:50:11.956173 [Byte 1] Lead/lag falling Transition (3, 3, 20)
919 22:50:11.956242 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
920 22:50:11.956305 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
921 22:50:11.956367 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
922 22:50:11.956429 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
923 22:50:11.956492 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
924 22:50:11.956553 3 4 12 |1413 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
925 22:50:11.956616 3 4 16 |3d3d 201 |(11 11)(11 11) |(1 1)(0 1)| 0
926 22:50:11.956678 3 4 20 |3d3d 303 |(11 11)(11 11) |(1 1)(1 1)| 0
927 22:50:11.956740 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 22:50:11.956803 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 22:50:11.956865 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 22:50:11.956927 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 22:50:11.956990 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 22:50:11.957051 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 22:50:11.957113 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 22:50:11.957175 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 22:50:11.957237 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
936 22:50:11.957299 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
937 22:50:11.957360 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
938 22:50:11.957422 [Byte 0] Lead/lag falling Transition (3, 6, 0)
939 22:50:11.957680 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
940 22:50:11.957750 [Byte 1] Lead/lag falling Transition (3, 6, 4)
941 22:50:11.957813 3 6 8 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
942 22:50:11.957876 [Byte 0] Lead/lag Transition tap number (3)
943 22:50:11.957936 3 6 12 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
944 22:50:11.957999 [Byte 1] Lead/lag Transition tap number (3)
945 22:50:11.958059 3 6 16 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
946 22:50:11.958121 [Byte 0]First pass (3, 6, 16)
947 22:50:11.958181 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 22:50:11.958244 [Byte 1]First pass (3, 6, 20)
949 22:50:11.958304 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 22:50:11.958366 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 22:50:11.958428 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 22:50:11.958490 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 22:50:11.958552 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 22:50:11.958613 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
955 22:50:11.958675 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
956 22:50:11.958736 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
957 22:50:11.958797 All bytes gating window > 1UI, Early break!
958 22:50:11.958858
959 22:50:11.958919 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
960 22:50:11.958980
961 22:50:11.959040 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
962 22:50:11.959101
963 22:50:11.959161
964 22:50:11.959230
965 22:50:11.959292 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
966 22:50:11.959354
967 22:50:11.959414 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
968 22:50:11.959475
969 22:50:11.959535
970 22:50:11.959595 Write Rank0 MR1 =0x56
971 22:50:11.959655
972 22:50:11.959716 best RODT dly(2T, 0.5T) = (2, 3)
973 22:50:11.959777
974 22:50:11.959871 best RODT dly(2T, 0.5T) = (2, 3)
975 22:50:11.959936 ==
976 22:50:11.959998 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
977 22:50:11.960061 fsp= 1, odt_onoff= 1, Byte mode= 0
978 22:50:11.960122 ==
979 22:50:11.960184 Start DQ dly to find pass range UseTestEngine =0
980 22:50:11.960245 x-axis: bit #, y-axis: DQ dly (-127~63)
981 22:50:11.960306 RX Vref Scan = 0
982 22:50:11.960366 -26, [0] xxxxxxxx xxxxxxxx [MSB]
983 22:50:11.960431 -25, [0] xxxxxxxx xxxxxxxx [MSB]
984 22:50:11.960493 -24, [0] xxxxxxxx xxxxxxxx [MSB]
985 22:50:11.960555 -23, [0] xxxxxxxx xxxxxxxx [MSB]
986 22:50:11.960617 -22, [0] xxxxxxxx xxxxxxxx [MSB]
987 22:50:11.960679 -21, [0] xxxxxxxx xxxxxxxx [MSB]
988 22:50:11.960740 -20, [0] xxxxxxxx xxxxxxxx [MSB]
989 22:50:11.960802 -19, [0] xxxxxxxx xxxxxxxx [MSB]
990 22:50:11.960864 -18, [0] xxxxxxxx xxxxxxxx [MSB]
991 22:50:11.960925 -17, [0] xxxxxxxx xxxxxxxx [MSB]
992 22:50:11.960990 -16, [0] xxxxxxxx xxxxxxxx [MSB]
993 22:50:11.961052 -15, [0] xxxxxxxx xxxxxxxx [MSB]
994 22:50:11.961114 -14, [0] xxxxxxxx xxxxxxxx [MSB]
995 22:50:11.961175 -13, [0] xxxxxxxx xxxxxxxx [MSB]
996 22:50:11.961237 -12, [0] xxxxxxxx xxxxxxxx [MSB]
997 22:50:11.961299 -11, [0] xxxxxxxx xxxxxxxx [MSB]
998 22:50:11.961360 -10, [0] xxxxxxxx xxxxxxxx [MSB]
999 22:50:11.961422 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1000 22:50:11.961484 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1001 22:50:11.961545 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1002 22:50:11.961607 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1003 22:50:11.961669 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1004 22:50:11.961731 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1005 22:50:11.961792 -3, [0] xxxxxxxx oxxxxxxx [MSB]
1006 22:50:11.961855 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1007 22:50:11.961916 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1008 22:50:11.961978 0, [0] xxxoxxxx ooxoooxx [MSB]
1009 22:50:11.962040 1, [0] xxxoxoxx ooxoooox [MSB]
1010 22:50:11.962102 2, [0] xxxoxoox ooxoooox [MSB]
1011 22:50:11.962166 3, [0] xxxoxoox ooxoooox [MSB]
1012 22:50:11.962229 4, [0] xxxoxoox ooxoooox [MSB]
1013 22:50:11.962291 5, [0] oxxooooo ooxooooo [MSB]
1014 22:50:11.962353 6, [0] ooxooooo ooxooooo [MSB]
1015 22:50:11.962414 7, [0] oooooooo ooxooooo [MSB]
1016 22:50:11.962477 32, [0] oooxoooo oooooooo [MSB]
1017 22:50:11.962538 33, [0] oooxoooo xooooooo [MSB]
1018 22:50:11.962599 34, [0] oooxoooo xooooooo [MSB]
1019 22:50:11.962661 35, [0] oooxoooo xxoxoooo [MSB]
1020 22:50:11.962723 36, [0] oooxoxoo xxoxxoxo [MSB]
1021 22:50:11.962785 37, [0] oooxoxxx xxoxxxxo [MSB]
1022 22:50:11.962846 38, [0] oooxoxxx xxoxxxxo [MSB]
1023 22:50:11.962907 39, [0] oooxoxxx xxoxxxxx [MSB]
1024 22:50:11.962969 40, [0] ooxxoxxx xxoxxxxx [MSB]
1025 22:50:11.963037 41, [0] xxxxxxxx xxoxxxxx [MSB]
1026 22:50:11.963102 42, [0] xxxxxxxx xxoxxxxx [MSB]
1027 22:50:11.963165 43, [0] xxxxxxxx xxxxxxxx [MSB]
1028 22:50:11.963233 iDelay=43, Bit 0, Center 22 (5 ~ 40) 36
1029 22:50:11.963296 iDelay=43, Bit 1, Center 23 (6 ~ 40) 35
1030 22:50:11.963356 iDelay=43, Bit 2, Center 23 (7 ~ 39) 33
1031 22:50:11.963417 iDelay=43, Bit 3, Center 14 (-2 ~ 31) 34
1032 22:50:11.963476 iDelay=43, Bit 4, Center 22 (5 ~ 40) 36
1033 22:50:11.963536 iDelay=43, Bit 5, Center 18 (1 ~ 35) 35
1034 22:50:11.963596 iDelay=43, Bit 6, Center 19 (2 ~ 36) 35
1035 22:50:11.963656 iDelay=43, Bit 7, Center 20 (5 ~ 36) 32
1036 22:50:11.963715 iDelay=43, Bit 8, Center 14 (-3 ~ 32) 36
1037 22:50:11.963775 iDelay=43, Bit 9, Center 17 (0 ~ 34) 35
1038 22:50:11.963835 iDelay=43, Bit 10, Center 25 (8 ~ 42) 35
1039 22:50:11.963895 iDelay=43, Bit 11, Center 16 (-2 ~ 34) 37
1040 22:50:11.963954 iDelay=43, Bit 12, Center 17 (0 ~ 35) 36
1041 22:50:11.964014 iDelay=43, Bit 13, Center 18 (0 ~ 36) 37
1042 22:50:11.964074 iDelay=43, Bit 14, Center 18 (1 ~ 35) 35
1043 22:50:11.964134 iDelay=43, Bit 15, Center 21 (5 ~ 38) 34
1044 22:50:11.964219 ==
1045 22:50:11.964287 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1046 22:50:11.964349 fsp= 1, odt_onoff= 1, Byte mode= 0
1047 22:50:11.964410 ==
1048 22:50:11.964470 DQS Delay:
1049 22:50:11.964530 DQS0 = 0, DQS1 = 0
1050 22:50:11.964594 DQM Delay:
1051 22:50:11.964654 DQM0 = 20, DQM1 = 18
1052 22:50:11.964714 DQ Delay:
1053 22:50:11.964774 DQ0 =22, DQ1 =23, DQ2 =23, DQ3 =14
1054 22:50:11.964834 DQ4 =22, DQ5 =18, DQ6 =19, DQ7 =20
1055 22:50:11.964894 DQ8 =14, DQ9 =17, DQ10 =25, DQ11 =16
1056 22:50:11.964955 DQ12 =17, DQ13 =18, DQ14 =18, DQ15 =21
1057 22:50:11.965015
1058 22:50:11.965075
1059 22:50:11.965135 DramC Write-DBI off
1060 22:50:11.965195 ==
1061 22:50:11.965256 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1062 22:50:11.965317 fsp= 1, odt_onoff= 1, Byte mode= 0
1063 22:50:11.965378 ==
1064 22:50:11.965437 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1065 22:50:11.965498
1066 22:50:11.965557 Begin, DQ Scan Range 923~1179
1067 22:50:11.965618
1068 22:50:11.965677
1069 22:50:11.965935 TX Vref Scan disable
1070 22:50:11.966006 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1071 22:50:11.966070 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1072 22:50:11.966132 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1073 22:50:11.966193 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1074 22:50:11.966255 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1075 22:50:11.966316 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1076 22:50:11.966376 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1077 22:50:11.966438 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1078 22:50:11.966499 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1079 22:50:11.966560 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1080 22:50:11.966621 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1081 22:50:11.966682 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1082 22:50:11.966743 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1083 22:50:11.966804 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1084 22:50:11.966865 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1085 22:50:11.966934 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1086 22:50:11.967033 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1087 22:50:11.967100 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1088 22:50:11.967161 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1089 22:50:11.967231 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1090 22:50:11.967295 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1091 22:50:11.967356 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1092 22:50:11.967417 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1093 22:50:11.967478 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1094 22:50:11.967539 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1095 22:50:11.967599 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1096 22:50:11.967660 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1097 22:50:11.967721 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1098 22:50:11.967782 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1099 22:50:11.967844 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1100 22:50:11.967905 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1101 22:50:11.967966 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1102 22:50:11.968027 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1103 22:50:11.968088 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1104 22:50:11.968149 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1105 22:50:11.968211 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1106 22:50:11.968286 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1107 22:50:11.968353 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1108 22:50:11.968415 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1109 22:50:11.968476 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1110 22:50:11.968537 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1111 22:50:11.968599 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1112 22:50:11.968659 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1113 22:50:11.968720 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1114 22:50:11.968781 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1115 22:50:11.968842 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1116 22:50:11.968903 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
1117 22:50:11.968963 970 |3 6 10|[0] xxxxxxxx ooxoxxxx [MSB]
1118 22:50:11.969024 971 |3 6 11|[0] xxxxxxxx ooxooxxx [MSB]
1119 22:50:11.969084 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1120 22:50:11.969145 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1121 22:50:11.969212 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1122 22:50:11.969280 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1123 22:50:11.969341 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1124 22:50:11.969402 977 |3 6 17|[0] xxxoxoox oooooooo [MSB]
1125 22:50:11.969463 978 |3 6 18|[0] xooooooo oooooooo [MSB]
1126 22:50:11.969524 990 |3 6 30|[0] oooooooo oooxoooo [MSB]
1127 22:50:11.969585 991 |3 6 31|[0] oooooooo xooxxxoo [MSB]
1128 22:50:11.969646 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1129 22:50:11.969707 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1130 22:50:11.969768 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1131 22:50:11.969829 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1132 22:50:11.969890 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1133 22:50:11.969950 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1134 22:50:11.970011 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1135 22:50:11.970072 Byte0, DQ PI dly=986, DQM PI dly= 986
1136 22:50:11.970131 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1137 22:50:11.970192
1138 22:50:11.970252 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1139 22:50:11.970313
1140 22:50:11.970372 Byte1, DQ PI dly=981, DQM PI dly= 981
1141 22:50:11.970432 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1142 22:50:11.970492
1143 22:50:11.970551 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1144 22:50:11.970611
1145 22:50:11.970671 ==
1146 22:50:11.970731 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1147 22:50:11.970791 fsp= 1, odt_onoff= 1, Byte mode= 0
1148 22:50:11.970852 ==
1149 22:50:11.970912 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1150 22:50:11.970972
1151 22:50:11.971031 Begin, DQ Scan Range 957~1021
1152 22:50:11.971091 Write Rank0 MR14 =0x0
1153 22:50:11.971150
1154 22:50:11.971209 CH=0, VrefRange= 0, VrefLevel = 0
1155 22:50:11.971279 TX Bit0 (982~993) 12 987, Bit8 (970~985) 16 977,
1156 22:50:11.971341 TX Bit1 (980~993) 14 986, Bit9 (973~987) 15 980,
1157 22:50:11.971401 TX Bit2 (981~994) 14 987, Bit10 (978~991) 14 984,
1158 22:50:11.971462 TX Bit3 (976~990) 15 983, Bit11 (972~984) 13 978,
1159 22:50:11.971522 TX Bit4 (980~992) 13 986, Bit12 (975~985) 11 980,
1160 22:50:11.971582 TX Bit5 (978~991) 14 984, Bit13 (976~985) 10 980,
1161 22:50:11.971642 TX Bit6 (978~991) 14 984, Bit14 (975~989) 15 982,
1162 22:50:11.971702 TX Bit7 (980~993) 14 986, Bit15 (977~991) 15 984,
1163 22:50:11.971762
1164 22:50:11.971821 Write Rank0 MR14 =0x2
1165 22:50:11.971880
1166 22:50:11.971939 CH=0, VrefRange= 0, VrefLevel = 2
1167 22:50:11.971999 TX Bit0 (982~994) 13 988, Bit8 (970~987) 18 978,
1168 22:50:11.972060 TX Bit1 (980~994) 15 987, Bit9 (973~988) 16 980,
1169 22:50:11.972120 TX Bit2 (981~995) 15 988, Bit10 (977~992) 16 984,
1170 22:50:11.972180 TX Bit3 (976~991) 16 983, Bit11 (971~985) 15 978,
1171 22:50:11.972241 TX Bit4 (979~993) 15 986, Bit12 (974~986) 13 980,
1172 22:50:11.972302 TX Bit5 (977~992) 16 984, Bit13 (975~986) 12 980,
1173 22:50:11.972362 TX Bit6 (978~992) 15 985, Bit14 (975~990) 16 982,
1174 22:50:11.972634 TX Bit7 (979~993) 15 986, Bit15 (977~992) 16 984,
1175 22:50:11.972764
1176 22:50:11.972871 Write Rank0 MR14 =0x4
1177 22:50:11.972971
1178 22:50:11.973035 CH=0, VrefRange= 0, VrefLevel = 4
1179 22:50:11.973098 TX Bit0 (982~994) 13 988, Bit8 (970~987) 18 978,
1180 22:50:11.973160 TX Bit1 (979~994) 16 986, Bit9 (972~989) 18 980,
1181 22:50:11.973222 TX Bit2 (981~996) 16 988, Bit10 (977~993) 17 985,
1182 22:50:11.973282 TX Bit3 (976~991) 16 983, Bit11 (971~986) 16 978,
1183 22:50:11.973357 TX Bit4 (979~993) 15 986, Bit12 (974~987) 14 980,
1184 22:50:11.973479 TX Bit5 (977~992) 16 984, Bit13 (975~987) 13 981,
1185 22:50:11.973598 TX Bit6 (978~992) 15 985, Bit14 (975~990) 16 982,
1186 22:50:11.973719 TX Bit7 (979~994) 16 986, Bit15 (977~993) 17 985,
1187 22:50:11.973836
1188 22:50:11.973935 Write Rank0 MR14 =0x6
1189 22:50:11.974029
1190 22:50:11.974122 CH=0, VrefRange= 0, VrefLevel = 6
1191 22:50:11.974217 TX Bit0 (981~996) 16 988, Bit8 (969~988) 20 978,
1192 22:50:11.974311 TX Bit1 (979~996) 18 987, Bit9 (973~989) 17 981,
1193 22:50:11.974406 TX Bit2 (981~996) 16 988, Bit10 (976~993) 18 984,
1194 22:50:11.974501 TX Bit3 (975~991) 17 983, Bit11 (970~987) 18 978,
1195 22:50:11.974595 TX Bit4 (979~994) 16 986, Bit12 (974~988) 15 981,
1196 22:50:11.974690 TX Bit5 (977~993) 17 985, Bit13 (974~988) 15 981,
1197 22:50:11.974784 TX Bit6 (978~993) 16 985, Bit14 (974~991) 18 982,
1198 22:50:11.974877 TX Bit7 (979~995) 17 987, Bit15 (976~994) 19 985,
1199 22:50:11.974941
1200 22:50:11.975002 Write Rank0 MR14 =0x8
1201 22:50:11.975062
1202 22:50:11.975123 CH=0, VrefRange= 0, VrefLevel = 8
1203 22:50:11.975183 TX Bit0 (981~997) 17 989, Bit8 (969~988) 20 978,
1204 22:50:11.975254 TX Bit1 (979~997) 19 988, Bit9 (972~989) 18 980,
1205 22:50:11.975316 TX Bit2 (980~998) 19 989, Bit10 (977~995) 19 986,
1206 22:50:11.975377 TX Bit3 (975~992) 18 983, Bit11 (970~988) 19 979,
1207 22:50:11.975438 TX Bit4 (978~995) 18 986, Bit12 (973~989) 17 981,
1208 22:50:11.975498 TX Bit5 (977~993) 17 985, Bit13 (974~989) 16 981,
1209 22:50:11.975559 TX Bit6 (977~994) 18 985, Bit14 (974~991) 18 982,
1210 22:50:11.975622 TX Bit7 (978~996) 19 987, Bit15 (976~995) 20 985,
1211 22:50:11.975683
1212 22:50:11.975751 Write Rank0 MR14 =0xa
1213 22:50:11.975813
1214 22:50:11.975873 CH=0, VrefRange= 0, VrefLevel = 10
1215 22:50:11.975933 TX Bit0 (980~998) 19 989, Bit8 (969~989) 21 979,
1216 22:50:11.975994 TX Bit1 (978~998) 21 988, Bit9 (971~990) 20 980,
1217 22:50:11.976054 TX Bit2 (979~998) 20 988, Bit10 (976~996) 21 986,
1218 22:50:11.976114 TX Bit3 (975~992) 18 983, Bit11 (970~988) 19 979,
1219 22:50:11.976175 TX Bit4 (978~996) 19 987, Bit12 (973~989) 17 981,
1220 22:50:11.976235 TX Bit5 (977~993) 17 985, Bit13 (973~989) 17 981,
1221 22:50:11.976294 TX Bit6 (977~994) 18 985, Bit14 (974~991) 18 982,
1222 22:50:11.976355 TX Bit7 (979~997) 19 988, Bit15 (976~996) 21 986,
1223 22:50:11.976414
1224 22:50:11.976473 Write Rank0 MR14 =0xc
1225 22:50:11.976533
1226 22:50:11.976592 CH=0, VrefRange= 0, VrefLevel = 12
1227 22:50:11.976652 TX Bit0 (980~998) 19 989, Bit8 (969~989) 21 979,
1228 22:50:11.976713 TX Bit1 (979~998) 20 988, Bit9 (970~990) 21 980,
1229 22:50:11.976773 TX Bit2 (979~999) 21 989, Bit10 (976~996) 21 986,
1230 22:50:11.976834 TX Bit3 (975~992) 18 983, Bit11 (970~989) 20 979,
1231 22:50:11.976894 TX Bit4 (978~997) 20 987, Bit12 (972~989) 18 980,
1232 22:50:11.976955 TX Bit5 (977~994) 18 985, Bit13 (973~989) 17 981,
1233 22:50:11.977022 TX Bit6 (977~995) 19 986, Bit14 (973~992) 20 982,
1234 22:50:11.977088 TX Bit7 (978~997) 20 987, Bit15 (976~996) 21 986,
1235 22:50:11.977149
1236 22:50:11.977209 Write Rank0 MR14 =0xe
1237 22:50:11.977269
1238 22:50:11.977328 CH=0, VrefRange= 0, VrefLevel = 14
1239 22:50:11.977394 TX Bit0 (980~999) 20 989, Bit8 (969~990) 22 979,
1240 22:50:11.977459 TX Bit1 (978~999) 22 988, Bit9 (970~991) 22 980,
1241 22:50:11.977521 TX Bit2 (979~999) 21 989, Bit10 (976~997) 22 986,
1242 22:50:11.977582 TX Bit3 (975~993) 19 984, Bit11 (969~989) 21 979,
1243 22:50:11.977642 TX Bit4 (978~998) 21 988, Bit12 (972~990) 19 981,
1244 22:50:11.977702 TX Bit5 (976~995) 20 985, Bit13 (972~990) 19 981,
1245 22:50:11.977761 TX Bit6 (977~996) 20 986, Bit14 (973~992) 20 982,
1246 22:50:11.977821 TX Bit7 (978~999) 22 988, Bit15 (976~996) 21 986,
1247 22:50:11.977881
1248 22:50:11.977941 Write Rank0 MR14 =0x10
1249 22:50:11.978000
1250 22:50:11.978060 CH=0, VrefRange= 0, VrefLevel = 16
1251 22:50:11.978120 TX Bit0 (979~999) 21 989, Bit8 (969~990) 22 979,
1252 22:50:11.978181 TX Bit1 (978~999) 22 988, Bit9 (970~991) 22 980,
1253 22:50:11.978242 TX Bit2 (978~999) 22 988, Bit10 (976~997) 22 986,
1254 22:50:11.978302 TX Bit3 (974~993) 20 983, Bit11 (969~989) 21 979,
1255 22:50:11.978362 TX Bit4 (977~998) 22 987, Bit12 (971~990) 20 980,
1256 22:50:11.978423 TX Bit5 (976~995) 20 985, Bit13 (971~990) 20 980,
1257 22:50:11.978483 TX Bit6 (977~997) 21 987, Bit14 (972~993) 22 982,
1258 22:50:11.978544 TX Bit7 (978~999) 22 988, Bit15 (976~997) 22 986,
1259 22:50:11.978604
1260 22:50:11.978663 Write Rank0 MR14 =0x12
1261 22:50:11.978723
1262 22:50:11.978782 CH=0, VrefRange= 0, VrefLevel = 18
1263 22:50:11.978843 TX Bit0 (979~1000) 22 989, Bit8 (968~991) 24 979,
1264 22:50:11.978904 TX Bit1 (978~999) 22 988, Bit9 (969~991) 23 980,
1265 22:50:11.978964 TX Bit2 (979~1000) 22 989, Bit10 (975~997) 23 986,
1266 22:50:11.979024 TX Bit3 (974~993) 20 983, Bit11 (969~990) 22 979,
1267 22:50:11.979085 TX Bit4 (977~998) 22 987, Bit12 (971~991) 21 981,
1268 22:50:11.979145 TX Bit5 (976~996) 21 986, Bit13 (971~991) 21 981,
1269 22:50:11.979205 TX Bit6 (976~998) 23 987, Bit14 (971~994) 24 982,
1270 22:50:11.979297 TX Bit7 (978~999) 22 988, Bit15 (975~997) 23 986,
1271 22:50:11.979359
1272 22:50:11.979419 Write Rank0 MR14 =0x14
1273 22:50:11.979485
1274 22:50:11.979544 CH=0, VrefRange= 0, VrefLevel = 20
1275 22:50:11.979604 TX Bit0 (978~1000) 23 989, Bit8 (968~991) 24 979,
1276 22:50:11.979665 TX Bit1 (977~999) 23 988, Bit9 (969~992) 24 980,
1277 22:50:11.979925 TX Bit2 (978~1000) 23 989, Bit10 (975~998) 24 986,
1278 22:50:11.979995 TX Bit3 (974~994) 21 984, Bit11 (969~990) 22 979,
1279 22:50:11.980058 TX Bit4 (977~999) 23 988, Bit12 (971~991) 21 981,
1280 22:50:11.980119 TX Bit5 (976~997) 22 986, Bit13 (971~991) 21 981,
1281 22:50:11.980179 TX Bit6 (976~998) 23 987, Bit14 (971~995) 25 983,
1282 22:50:11.980240 TX Bit7 (978~1000) 23 989, Bit15 (975~997) 23 986,
1283 22:50:11.980300
1284 22:50:11.980359 Write Rank0 MR14 =0x16
1285 22:50:11.980420
1286 22:50:11.980479 CH=0, VrefRange= 0, VrefLevel = 22
1287 22:50:11.980540 TX Bit0 (978~1000) 23 989, Bit8 (968~991) 24 979,
1288 22:50:11.980600 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1289 22:50:11.980661 TX Bit2 (978~1000) 23 989, Bit10 (975~998) 24 986,
1290 22:50:11.980722 TX Bit3 (973~994) 22 983, Bit11 (969~991) 23 980,
1291 22:50:11.980791 TX Bit4 (977~999) 23 988, Bit12 (970~992) 23 981,
1292 22:50:11.980852 TX Bit5 (976~997) 22 986, Bit13 (971~991) 21 981,
1293 22:50:11.980913 TX Bit6 (976~999) 24 987, Bit14 (971~995) 25 983,
1294 22:50:11.980973 TX Bit7 (977~1000) 24 988, Bit15 (975~997) 23 986,
1295 22:50:11.981033
1296 22:50:11.981092 Write Rank0 MR14 =0x18
1297 22:50:11.981152
1298 22:50:11.981211 CH=0, VrefRange= 0, VrefLevel = 24
1299 22:50:11.981272 TX Bit0 (978~1001) 24 989, Bit8 (968~991) 24 979,
1300 22:50:11.981333 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
1301 22:50:11.981393 TX Bit2 (978~1001) 24 989, Bit10 (975~998) 24 986,
1302 22:50:11.981454 TX Bit3 (973~995) 23 984, Bit11 (968~991) 24 979,
1303 22:50:11.981514 TX Bit4 (977~999) 23 988, Bit12 (970~992) 23 981,
1304 22:50:11.981574 TX Bit5 (975~998) 24 986, Bit13 (970~992) 23 981,
1305 22:50:11.981633 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1306 22:50:11.981694 TX Bit7 (977~1000) 24 988, Bit15 (975~998) 24 986,
1307 22:50:11.981754
1308 22:50:11.981813 Write Rank0 MR14 =0x1a
1309 22:50:11.981874
1310 22:50:11.981934 CH=0, VrefRange= 0, VrefLevel = 26
1311 22:50:11.981994 TX Bit0 (978~1001) 24 989, Bit8 (967~991) 25 979,
1312 22:50:11.982055 TX Bit1 (977~1000) 24 988, Bit9 (969~993) 25 981,
1313 22:50:11.982114 TX Bit2 (978~1001) 24 989, Bit10 (975~998) 24 986,
1314 22:50:11.982174 TX Bit3 (973~995) 23 984, Bit11 (968~991) 24 979,
1315 22:50:11.982234 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1316 22:50:11.982295 TX Bit5 (975~998) 24 986, Bit13 (970~992) 23 981,
1317 22:50:11.982355 TX Bit6 (975~999) 25 987, Bit14 (970~996) 27 983,
1318 22:50:11.982415 TX Bit7 (977~1001) 25 989, Bit15 (973~998) 26 985,
1319 22:50:11.982476
1320 22:50:11.982535 Write Rank0 MR14 =0x1c
1321 22:50:11.982595
1322 22:50:11.982655 CH=0, VrefRange= 0, VrefLevel = 28
1323 22:50:11.982715 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1324 22:50:11.982775 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1325 22:50:11.982836 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1326 22:50:11.982896 TX Bit3 (973~996) 24 984, Bit11 (968~992) 25 980,
1327 22:50:11.982956 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1328 22:50:11.983017 TX Bit5 (975~998) 24 986, Bit13 (970~993) 24 981,
1329 22:50:11.983077 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1330 22:50:11.983138 TX Bit7 (977~1001) 25 989, Bit15 (973~998) 26 985,
1331 22:50:11.983198
1332 22:50:11.983269 Write Rank0 MR14 =0x1e
1333 22:50:11.983330
1334 22:50:11.983389 CH=0, VrefRange= 0, VrefLevel = 30
1335 22:50:11.983449 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1336 22:50:11.983509 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1337 22:50:11.983568 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1338 22:50:11.983629 TX Bit3 (973~996) 24 984, Bit11 (968~992) 25 980,
1339 22:50:11.983689 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1340 22:50:11.983749 TX Bit5 (975~998) 24 986, Bit13 (970~993) 24 981,
1341 22:50:11.983809 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1342 22:50:11.983869 TX Bit7 (977~1001) 25 989, Bit15 (973~998) 26 985,
1343 22:50:11.983929
1344 22:50:11.983988 Write Rank0 MR14 =0x20
1345 22:50:11.984047
1346 22:50:11.984107 CH=0, VrefRange= 0, VrefLevel = 32
1347 22:50:11.984167 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1348 22:50:11.984228 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1349 22:50:11.984288 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1350 22:50:11.984348 TX Bit3 (973~996) 24 984, Bit11 (968~992) 25 980,
1351 22:50:11.984408 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1352 22:50:11.984467 TX Bit5 (975~998) 24 986, Bit13 (970~993) 24 981,
1353 22:50:11.984528 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1354 22:50:11.984588 TX Bit7 (977~1001) 25 989, Bit15 (973~998) 26 985,
1355 22:50:11.984648
1356 22:50:11.984707 Write Rank0 MR14 =0x22
1357 22:50:11.984767
1358 22:50:11.984827 CH=0, VrefRange= 0, VrefLevel = 34
1359 22:50:11.984887 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1360 22:50:11.984947 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1361 22:50:11.985007 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1362 22:50:11.985088 TX Bit3 (973~996) 24 984, Bit11 (968~992) 25 980,
1363 22:50:11.985151 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1364 22:50:11.985211 TX Bit5 (975~998) 24 986, Bit13 (970~993) 24 981,
1365 22:50:11.985270 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1366 22:50:11.985331 TX Bit7 (977~1001) 25 989, Bit15 (973~998) 26 985,
1367 22:50:11.985390
1368 22:50:11.985450 Write Rank0 MR14 =0x24
1369 22:50:11.985510
1370 22:50:11.985570 CH=0, VrefRange= 0, VrefLevel = 36
1371 22:50:11.985630 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1372 22:50:11.985690 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1373 22:50:11.985749 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1374 22:50:11.985810 TX Bit3 (973~996) 24 984, Bit11 (968~992) 25 980,
1375 22:50:11.985869 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1376 22:50:11.986126 TX Bit5 (975~998) 24 986, Bit13 (970~993) 24 981,
1377 22:50:11.986195 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1378 22:50:11.986257 TX Bit7 (977~1001) 25 989, Bit15 (973~998) 26 985,
1379 22:50:11.986317
1380 22:50:11.986377 Write Rank0 MR14 =0x26
1381 22:50:11.986436
1382 22:50:11.986495 CH=0, VrefRange= 0, VrefLevel = 38
1383 22:50:11.986556 TX Bit0 (978~1002) 25 990, Bit8 (968~991) 24 979,
1384 22:50:11.986616 TX Bit1 (977~1001) 25 989, Bit9 (969~993) 25 981,
1385 22:50:11.986676 TX Bit2 (978~1002) 25 990, Bit10 (974~998) 25 986,
1386 22:50:11.986736 TX Bit3 (973~996) 24 984, Bit11 (968~992) 25 980,
1387 22:50:11.986796 TX Bit4 (977~1000) 24 988, Bit12 (970~993) 24 981,
1388 22:50:11.986855 TX Bit5 (975~998) 24 986, Bit13 (970~993) 24 981,
1389 22:50:11.986916 TX Bit6 (976~999) 24 987, Bit14 (970~996) 27 983,
1390 22:50:11.986976 TX Bit7 (977~1001) 25 989, Bit15 (973~998) 26 985,
1391 22:50:11.987036
1392 22:50:11.987094
1393 22:50:11.987152 TX Vref found, early break! 368< 376
1394 22:50:11.987212 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
1395 22:50:11.987293 u1DelayCellOfst[0]=7 cells (6 PI)
1396 22:50:11.987353 u1DelayCellOfst[1]=6 cells (5 PI)
1397 22:50:11.987415 u1DelayCellOfst[2]=7 cells (6 PI)
1398 22:50:11.987475 u1DelayCellOfst[3]=0 cells (0 PI)
1399 22:50:11.987535 u1DelayCellOfst[4]=5 cells (4 PI)
1400 22:50:11.987594 u1DelayCellOfst[5]=2 cells (2 PI)
1401 22:50:11.987653 u1DelayCellOfst[6]=3 cells (3 PI)
1402 22:50:11.987712 u1DelayCellOfst[7]=6 cells (5 PI)
1403 22:50:11.987771 Byte0, DQ PI dly=984, DQM PI dly= 987
1404 22:50:11.987830 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1405 22:50:11.987889
1406 22:50:11.987949 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1407 22:50:11.988009
1408 22:50:11.988068 u1DelayCellOfst[8]=0 cells (0 PI)
1409 22:50:11.988128 u1DelayCellOfst[9]=2 cells (2 PI)
1410 22:50:11.988188 u1DelayCellOfst[10]=9 cells (7 PI)
1411 22:50:11.988247 u1DelayCellOfst[11]=1 cells (1 PI)
1412 22:50:11.988306 u1DelayCellOfst[12]=2 cells (2 PI)
1413 22:50:11.988366 u1DelayCellOfst[13]=2 cells (2 PI)
1414 22:50:11.988425 u1DelayCellOfst[14]=5 cells (4 PI)
1415 22:50:11.988484 u1DelayCellOfst[15]=7 cells (6 PI)
1416 22:50:11.988542 Byte1, DQ PI dly=979, DQM PI dly= 982
1417 22:50:11.988602 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1418 22:50:11.988662
1419 22:50:11.988722 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1420 22:50:11.988782
1421 22:50:11.988840 Write Rank0 MR14 =0x1c
1422 22:50:11.988899
1423 22:50:11.988959 Final TX Range 0 Vref 28
1424 22:50:11.989019
1425 22:50:11.989078 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1426 22:50:11.989138
1427 22:50:11.989196 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1428 22:50:11.989257 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1429 22:50:11.989323 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1430 22:50:11.989383 Write Rank0 MR3 =0xb0
1431 22:50:11.989449 DramC Write-DBI on
1432 22:50:11.989509 ==
1433 22:50:11.989569 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1434 22:50:11.989629 fsp= 1, odt_onoff= 1, Byte mode= 0
1435 22:50:11.989689 ==
1436 22:50:11.989748 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1437 22:50:11.989808
1438 22:50:11.989867 Begin, DQ Scan Range 702~766
1439 22:50:11.989926
1440 22:50:11.989984
1441 22:50:11.990044 TX Vref Scan disable
1442 22:50:11.990122 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1443 22:50:11.990185 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1444 22:50:11.990246 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1445 22:50:11.990307 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1446 22:50:11.990367 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1447 22:50:11.990428 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1448 22:50:11.990489 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1449 22:50:11.990550 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1450 22:50:11.990611 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1451 22:50:11.990672 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1452 22:50:11.990732 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1453 22:50:11.990793 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1454 22:50:11.990853 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1455 22:50:11.990914 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1456 22:50:11.990974 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1457 22:50:11.991035 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1458 22:50:11.991095 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1459 22:50:11.991156 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1460 22:50:11.991217 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1461 22:50:11.991287 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1462 22:50:11.991347 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1463 22:50:11.991408 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1464 22:50:11.991468 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1465 22:50:11.991528 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1466 22:50:11.991589 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1467 22:50:11.991650 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
1468 22:50:11.991710 Byte0, DQ PI dly=732, DQM PI dly= 732
1469 22:50:11.991771 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
1470 22:50:11.991830
1471 22:50:11.991889 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
1472 22:50:11.991949
1473 22:50:11.992009 Byte1, DQ PI dly=725, DQM PI dly= 725
1474 22:50:11.992068 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 21)
1475 22:50:11.992130
1476 22:50:11.992189 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 21)
1477 22:50:11.992249
1478 22:50:11.992308 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1479 22:50:11.992369 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1480 22:50:11.992435 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1481 22:50:11.992495 Write Rank0 MR3 =0x30
1482 22:50:11.992554 DramC Write-DBI off
1483 22:50:11.992614
1484 22:50:11.992673 [DATLAT]
1485 22:50:11.992732 Freq=1600, CH0 RK0, use_rxtx_scan=0
1486 22:50:11.992792
1487 22:50:11.992850 DATLAT Default: 0xf
1488 22:50:11.992910 7, 0xFFFF, sum=0
1489 22:50:11.992976 8, 0xFFFF, sum=0
1490 22:50:11.993044 9, 0xFFFF, sum=0
1491 22:50:11.993106 10, 0xFFFF, sum=0
1492 22:50:11.993174 11, 0xFFFF, sum=0
1493 22:50:11.993236 12, 0xFFFF, sum=0
1494 22:50:11.993296 13, 0xFFFF, sum=0
1495 22:50:11.993356 14, 0x0, sum=1
1496 22:50:11.993416 15, 0x0, sum=2
1497 22:50:11.993477 16, 0x0, sum=3
1498 22:50:11.993739 17, 0x0, sum=4
1499 22:50:11.993862 pattern=2 first_step=14 total pass=5 best_step=16
1500 22:50:11.993982 ==
1501 22:50:11.994102 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1502 22:50:11.994223 fsp= 1, odt_onoff= 1, Byte mode= 0
1503 22:50:11.994337 ==
1504 22:50:11.994441 Start DQ dly to find pass range UseTestEngine =1
1505 22:50:11.994520 x-axis: bit #, y-axis: DQ dly (-127~63)
1506 22:50:11.994583 RX Vref Scan = 1
1507 22:50:11.994643
1508 22:50:11.994703 RX Vref found, early break!
1509 22:50:11.994773
1510 22:50:11.994868 Final RX Vref 11, apply to both rank0 and 1
1511 22:50:11.994962 ==
1512 22:50:11.995056 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1513 22:50:11.995149 fsp= 1, odt_onoff= 1, Byte mode= 0
1514 22:50:11.995245 ==
1515 22:50:11.995308 DQS Delay:
1516 22:50:11.995368 DQS0 = 0, DQS1 = 0
1517 22:50:11.995429 DQM Delay:
1518 22:50:11.995489 DQM0 = 19, DQM1 = 17
1519 22:50:11.995552 DQ Delay:
1520 22:50:11.995614 DQ0 =22, DQ1 =22, DQ2 =23, DQ3 =14
1521 22:50:11.995673 DQ4 =22, DQ5 =17, DQ6 =18, DQ7 =20
1522 22:50:11.995732 DQ8 =13, DQ9 =17, DQ10 =23, DQ11 =15
1523 22:50:11.995792 DQ12 =17, DQ13 =16, DQ14 =18, DQ15 =20
1524 22:50:11.995851
1525 22:50:11.995910
1526 22:50:11.995969
1527 22:50:11.996027 [DramC_TX_OE_Calibration] TA2
1528 22:50:11.996087 Original DQ_B0 (3 6) =30, OEN = 27
1529 22:50:11.996147 Original DQ_B1 (3 6) =30, OEN = 27
1530 22:50:11.996207 23, 0x0, End_B0=23 End_B1=23
1531 22:50:11.996268 24, 0x0, End_B0=24 End_B1=24
1532 22:50:11.996328 25, 0x0, End_B0=25 End_B1=25
1533 22:50:11.996388 26, 0x0, End_B0=26 End_B1=26
1534 22:50:11.996449 27, 0x0, End_B0=27 End_B1=27
1535 22:50:11.996510 28, 0x0, End_B0=28 End_B1=28
1536 22:50:11.996573 29, 0x0, End_B0=29 End_B1=29
1537 22:50:11.996634 30, 0x0, End_B0=30 End_B1=30
1538 22:50:11.996699 31, 0xFFFF, End_B0=30 End_B1=30
1539 22:50:11.996760 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1540 22:50:11.996821 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1541 22:50:11.996899
1542 22:50:11.996959
1543 22:50:11.997019 Write Rank0 MR23 =0x3f
1544 22:50:11.997078 [DQSOSC]
1545 22:50:11.997137 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1c1, (MSB)MR19= 0x202, tDQSOscB0 = 446 ps tDQSOscB1 = 446 ps
1546 22:50:11.997198 CH0_RK0: MR19=0x202, MR18=0xC1C1, DQSOSC=446, MR23=63, INC=12, DEC=18
1547 22:50:11.997258 Write Rank0 MR23 =0x3f
1548 22:50:11.997317 [DQSOSC]
1549 22:50:11.997376 [DQSOSCAuto] RK0, (LSB)MR18= 0xbebe, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
1550 22:50:11.997437 CH0 RK0: MR19=202, MR18=BEBE
1551 22:50:11.997496 [RankSwap] Rank num 2, (Multi 1), Rank 1
1552 22:50:11.997555 Write Rank0 MR2 =0xad
1553 22:50:11.997621 [Write Leveling]
1554 22:50:11.997685 delay byte0 byte1 byte2 byte3
1555 22:50:11.997751
1556 22:50:11.997817 10 0 0
1557 22:50:11.997878 11 0 0
1558 22:50:11.997941 12 0 0
1559 22:50:11.998002 13 0 0
1560 22:50:11.998063 14 0 0
1561 22:50:11.998122 15 0 0
1562 22:50:11.998183 16 0 0
1563 22:50:11.998244 17 0 0
1564 22:50:11.998304 18 0 0
1565 22:50:11.998364 19 0 0
1566 22:50:11.998424 20 0 0
1567 22:50:11.998485 21 0 0
1568 22:50:11.998544 22 0 0
1569 22:50:11.998604 23 0 0
1570 22:50:11.998664 24 0 0
1571 22:50:11.998723 25 0 ff
1572 22:50:11.998784 26 0 ff
1573 22:50:11.998850 27 0 ff
1574 22:50:11.998949 28 ff ff
1575 22:50:11.999061 29 ff ff
1576 22:50:11.999163 30 ff ff
1577 22:50:11.999260 31 ff ff
1578 22:50:11.999324 32 ff ff
1579 22:50:11.999385 33 ff ff
1580 22:50:11.999449 34 ff ff
1581 22:50:11.999510 pass bytecount = 0xff (0xff: all bytes pass)
1582 22:50:11.999570
1583 22:50:11.999630 DQS0 dly: 28
1584 22:50:11.999692 DQS1 dly: 25
1585 22:50:11.999751 Write Rank0 MR2 =0x2d
1586 22:50:11.999811 [RankSwap] Rank num 2, (Multi 1), Rank 0
1587 22:50:11.999871 Write Rank1 MR1 =0xd6
1588 22:50:11.999931 [Gating]
1589 22:50:11.999990 ==
1590 22:50:12.000049 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1591 22:50:12.000109 fsp= 1, odt_onoff= 1, Byte mode= 0
1592 22:50:12.000169 ==
1593 22:50:12.000227 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1594 22:50:12.000293 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1595 22:50:12.000359 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1596 22:50:12.000421 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
1597 22:50:12.000482 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
1598 22:50:12.000543 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1599 22:50:12.000603 [Byte 1] Lead/lag falling Transition (3, 1, 20)
1600 22:50:12.000663 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1601 22:50:12.000725 [Byte 0] Lead/lag falling Transition (3, 1, 24)
1602 22:50:12.000800 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1603 22:50:12.000863 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1604 22:50:12.000924 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1605 22:50:12.000984 3 2 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1606 22:50:12.001044 3 2 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1607 22:50:12.001105 3 2 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1608 22:50:12.001166 [Byte 0] Lead/lag Transition tap number (7)
1609 22:50:12.001227 3 2 20 |2c2c 2c2b |(11 0)(11 11) |(0 0)(1 0)| 0
1610 22:50:12.001288 [Byte 1] Lead/lag Transition tap number (9)
1611 22:50:12.001348 3 2 24 |f0f 2c2c |(11 11)(11 0) |(0 0)(0 0)| 0
1612 22:50:12.001409 3 2 28 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
1613 22:50:12.001469 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1614 22:50:12.001529 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1615 22:50:12.001590 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1616 22:50:12.001650 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1617 22:50:12.001711 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1618 22:50:12.001771 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1619 22:50:12.001832 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1620 22:50:12.001892 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1621 22:50:12.001958 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1622 22:50:12.002024 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1623 22:50:12.002086 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1624 22:50:12.002152 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1625 22:50:12.002215 3 4 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1626 22:50:12.002275 3 4 20 |403 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1627 22:50:12.002538 3 4 24 |707 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1628 22:50:12.002631 3 4 28 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
1629 22:50:12.002730 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1630 22:50:12.002841 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1631 22:50:12.002950 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1632 22:50:12.003050 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1633 22:50:12.003147 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1634 22:50:12.003253 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1635 22:50:12.003352 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1636 22:50:12.003449 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1637 22:50:12.003544 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1638 22:50:12.003641 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1639 22:50:12.003737 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1640 22:50:12.003838 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1641 22:50:12.003905 [Byte 0] Lead/lag falling Transition (3, 6, 12)
1642 22:50:12.003966 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1643 22:50:12.004027 [Byte 0] Lead/lag Transition tap number (2)
1644 22:50:12.004087 [Byte 1] Lead/lag falling Transition (3, 6, 16)
1645 22:50:12.004147 3 6 20 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1646 22:50:12.004207 [Byte 1] Lead/lag Transition tap number (2)
1647 22:50:12.004267 3 6 24 |3030 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
1648 22:50:12.004332 3 6 28 |4646 a0a |(0 0)(11 11) |(0 0)(0 0)| 0
1649 22:50:12.004398 [Byte 0]First pass (3, 6, 28)
1650 22:50:12.004460 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1651 22:50:12.004525 [Byte 1]First pass (3, 7, 0)
1652 22:50:12.004584 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1653 22:50:12.004645 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1654 22:50:12.004706 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1655 22:50:12.004771 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1656 22:50:12.004851 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1657 22:50:12.004912 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1658 22:50:12.004974 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1659 22:50:12.005035 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1660 22:50:12.005095 All bytes gating window > 1UI, Early break!
1661 22:50:12.005155
1662 22:50:12.005215 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 16)
1663 22:50:12.005274
1664 22:50:12.005333 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
1665 22:50:12.005399
1666 22:50:12.005463
1667 22:50:12.005523
1668 22:50:12.005582 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
1669 22:50:12.005642
1670 22:50:12.005701 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
1671 22:50:12.005760
1672 22:50:12.005819
1673 22:50:12.005879 Write Rank1 MR1 =0x56
1674 22:50:12.005947
1675 22:50:12.006041 best RODT dly(2T, 0.5T) = (2, 3)
1676 22:50:12.006134
1677 22:50:12.006226 best RODT dly(2T, 0.5T) = (2, 3)
1678 22:50:12.006318 ==
1679 22:50:12.006397 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1680 22:50:12.006462 fsp= 1, odt_onoff= 1, Byte mode= 0
1681 22:50:12.006524 ==
1682 22:50:12.006584 Start DQ dly to find pass range UseTestEngine =0
1683 22:50:12.006643 x-axis: bit #, y-axis: DQ dly (-127~63)
1684 22:50:12.006702 RX Vref Scan = 0
1685 22:50:12.006761 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1686 22:50:12.006822 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1687 22:50:12.006883 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1688 22:50:12.006943 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1689 22:50:12.007004 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1690 22:50:12.007065 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1691 22:50:12.007125 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1692 22:50:12.007185 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1693 22:50:12.007253 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1694 22:50:12.007315 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1695 22:50:12.007375 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1696 22:50:12.007435 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1697 22:50:12.007495 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1698 22:50:12.007556 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1699 22:50:12.007616 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1700 22:50:12.007676 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1701 22:50:12.007736 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1702 22:50:12.007796 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1703 22:50:12.007856 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1704 22:50:12.007917 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1705 22:50:12.007977 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1706 22:50:12.008037 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1707 22:50:12.008097 -4, [0] xxxoxxxx oxxxxxxx [MSB]
1708 22:50:12.008157 -3, [0] xxxoxxxx oxxoxxxx [MSB]
1709 22:50:12.008217 -2, [0] xxxoxxxx ooxoooxx [MSB]
1710 22:50:12.008277 -1, [0] xxxoxoxx ooxoooxx [MSB]
1711 22:50:12.008337 0, [0] xxxoxoox ooxoooox [MSB]
1712 22:50:12.008398 1, [0] xxxooooo ooxoooox [MSB]
1713 22:50:12.008466 2, [0] xxxooooo ooxoooox [MSB]
1714 22:50:12.008533 3, [0] xxxooooo ooxooooo [MSB]
1715 22:50:12.008594 4, [0] oooooooo ooxooooo [MSB]
1716 22:50:12.008654 32, [0] oooxoooo oooooooo [MSB]
1717 22:50:12.008714 33, [0] oooxoooo oooooooo [MSB]
1718 22:50:12.008801 34, [0] oooxoooo xooooooo [MSB]
1719 22:50:12.008897 35, [0] oooxoooo xxoxoooo [MSB]
1720 22:50:12.008962 36, [0] oooxoxoo xxoxxooo [MSB]
1721 22:50:12.009024 37, [0] oooxoxxo xxoxxxxo [MSB]
1722 22:50:12.009085 38, [0] oooxoxxx xxoxxxxo [MSB]
1723 22:50:12.009145 39, [0] oooxoxxx xxoxxxxx [MSB]
1724 22:50:12.009206 40, [0] ooxxxxxx xxoxxxxx [MSB]
1725 22:50:12.009266 41, [0] xxxxxxxx xxoxxxxx [MSB]
1726 22:50:12.009326 42, [0] xxxxxxxx xxoxxxxx [MSB]
1727 22:50:12.009386 43, [0] xxxxxxxx xxxxxxxx [MSB]
1728 22:50:12.009446 iDelay=43, Bit 0, Center 22 (4 ~ 40) 37
1729 22:50:12.009506 iDelay=43, Bit 1, Center 22 (4 ~ 40) 37
1730 22:50:12.009565 iDelay=43, Bit 2, Center 21 (4 ~ 39) 36
1731 22:50:12.009625 iDelay=43, Bit 3, Center 13 (-4 ~ 31) 36
1732 22:50:12.009684 iDelay=43, Bit 4, Center 20 (1 ~ 39) 39
1733 22:50:12.009743 iDelay=43, Bit 5, Center 17 (-1 ~ 35) 37
1734 22:50:12.009801 iDelay=43, Bit 6, Center 18 (0 ~ 36) 37
1735 22:50:12.009860 iDelay=43, Bit 7, Center 19 (1 ~ 37) 37
1736 22:50:12.009919 iDelay=43, Bit 8, Center 14 (-4 ~ 33) 38
1737 22:50:12.009978 iDelay=43, Bit 9, Center 16 (-2 ~ 34) 37
1738 22:50:12.010037 iDelay=43, Bit 10, Center 23 (5 ~ 42) 38
1739 22:50:12.010097 iDelay=43, Bit 11, Center 15 (-3 ~ 34) 38
1740 22:50:12.010155 iDelay=43, Bit 12, Center 16 (-2 ~ 35) 38
1741 22:50:12.010411 iDelay=43, Bit 13, Center 17 (-2 ~ 36) 39
1742 22:50:12.010478 iDelay=43, Bit 14, Center 18 (0 ~ 36) 37
1743 22:50:12.010539 iDelay=43, Bit 15, Center 20 (3 ~ 38) 36
1744 22:50:12.010599 ==
1745 22:50:12.010658 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1746 22:50:12.010718 fsp= 1, odt_onoff= 1, Byte mode= 0
1747 22:50:12.010778 ==
1748 22:50:12.010838 DQS Delay:
1749 22:50:12.010897 DQS0 = 0, DQS1 = 0
1750 22:50:12.010956 DQM Delay:
1751 22:50:12.011016 DQM0 = 19, DQM1 = 17
1752 22:50:12.011081 DQ Delay:
1753 22:50:12.011141 DQ0 =22, DQ1 =22, DQ2 =21, DQ3 =13
1754 22:50:12.011201 DQ4 =20, DQ5 =17, DQ6 =18, DQ7 =19
1755 22:50:12.011272 DQ8 =14, DQ9 =16, DQ10 =23, DQ11 =15
1756 22:50:12.011332 DQ12 =16, DQ13 =17, DQ14 =18, DQ15 =20
1757 22:50:12.011391
1758 22:50:12.011450
1759 22:50:12.011510 DramC Write-DBI off
1760 22:50:12.011569 ==
1761 22:50:12.011629 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1762 22:50:12.011689 fsp= 1, odt_onoff= 1, Byte mode= 0
1763 22:50:12.011748 ==
1764 22:50:12.011807 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1765 22:50:12.011867
1766 22:50:12.011926 Begin, DQ Scan Range 921~1177
1767 22:50:12.011986
1768 22:50:12.012045
1769 22:50:12.012105 TX Vref Scan disable
1770 22:50:12.012164 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1771 22:50:12.012226 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1772 22:50:12.012287 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1773 22:50:12.012347 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1774 22:50:12.012407 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1775 22:50:12.012468 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1776 22:50:12.012530 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1777 22:50:12.012594 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1778 22:50:12.012655 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1779 22:50:12.012716 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1780 22:50:12.012777 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1781 22:50:12.012837 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1782 22:50:12.012897 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1783 22:50:12.012957 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1784 22:50:12.013018 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1785 22:50:12.013078 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1786 22:50:12.013139 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1787 22:50:12.013200 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1788 22:50:12.013259 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1789 22:50:12.013320 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1790 22:50:12.013379 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1791 22:50:12.013440 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1792 22:50:12.013501 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1793 22:50:12.013562 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1794 22:50:12.013622 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1795 22:50:12.013686 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1796 22:50:12.013752 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1797 22:50:12.013813 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1798 22:50:12.013873 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1799 22:50:12.013934 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1800 22:50:12.013994 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1801 22:50:12.014054 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1802 22:50:12.014114 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1803 22:50:12.014174 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1804 22:50:12.014235 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1805 22:50:12.014295 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1806 22:50:12.014355 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1807 22:50:12.014416 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1808 22:50:12.014476 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1809 22:50:12.014536 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1810 22:50:12.014598 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1811 22:50:12.014664 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1812 22:50:12.014725 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1813 22:50:12.014823 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1814 22:50:12.014919 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1815 22:50:12.015015 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1816 22:50:12.015115 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1817 22:50:12.015212 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1818 22:50:12.015285 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
1819 22:50:12.015347 970 |3 6 10|[0] xxxxxxxx oxxxxxxx [MSB]
1820 22:50:12.015407 971 |3 6 11|[0] xxxxxxxx oxxoxxxx [MSB]
1821 22:50:12.015468 972 |3 6 12|[0] xxxxxxxx ooxoxoxx [MSB]
1822 22:50:12.015528 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1823 22:50:12.015588 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1824 22:50:12.015649 975 |3 6 15|[0] xxxxxxxx ooxoooox [MSB]
1825 22:50:12.015709 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1826 22:50:12.015769 977 |3 6 17|[0] xxxoxoox oooooooo [MSB]
1827 22:50:12.015829 978 |3 6 18|[0] xoxooooo oooooooo [MSB]
1828 22:50:12.015890 990 |3 6 30|[0] oooooooo oooxoooo [MSB]
1829 22:50:12.015951 991 |3 6 31|[0] oooooooo oooxoooo [MSB]
1830 22:50:12.016012 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1831 22:50:12.016072 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1832 22:50:12.016133 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1833 22:50:12.016193 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1834 22:50:12.016254 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1835 22:50:12.016319 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1836 22:50:12.016385 998 |3 6 38|[0] oooxoxxo xxxxxxxx [MSB]
1837 22:50:12.016446 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1838 22:50:12.016507 Byte0, DQ PI dly=986, DQM PI dly= 986
1839 22:50:12.016567 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1840 22:50:12.016627
1841 22:50:12.016686 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1842 22:50:12.016746
1843 22:50:12.016805 Byte1, DQ PI dly=981, DQM PI dly= 981
1844 22:50:12.016864 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1845 22:50:12.016924
1846 22:50:12.016983 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1847 22:50:12.017043
1848 22:50:12.017102 ==
1849 22:50:12.017162 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1850 22:50:12.017222 fsp= 1, odt_onoff= 1, Byte mode= 0
1851 22:50:12.017282 ==
1852 22:50:12.017341 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1853 22:50:12.017401
1854 22:50:12.017460 Begin, DQ Scan Range 957~1021
1855 22:50:12.017519 Write Rank1 MR14 =0x0
1856 22:50:12.017579
1857 22:50:12.017638 CH=0, VrefRange= 0, VrefLevel = 0
1858 22:50:12.017702 TX Bit0 (982~993) 12 987, Bit8 (973~985) 13 979,
1859 22:50:12.017767 TX Bit1 (980~993) 14 986, Bit9 (975~986) 12 980,
1860 22:50:12.018035 TX Bit2 (983~992) 10 987, Bit10 (979~992) 14 985,
1861 22:50:12.018108 TX Bit3 (976~990) 15 983, Bit11 (974~983) 10 978,
1862 22:50:12.018169 TX Bit4 (980~992) 13 986, Bit12 (976~986) 11 981,
1863 22:50:12.018230 TX Bit5 (978~990) 13 984, Bit13 (975~988) 14 981,
1864 22:50:12.018290 TX Bit6 (978~991) 14 984, Bit14 (975~991) 17 983,
1865 22:50:12.018350 TX Bit7 (980~993) 14 986, Bit15 (978~992) 15 985,
1866 22:50:12.018411
1867 22:50:12.018471 Write Rank1 MR14 =0x2
1868 22:50:12.018531
1869 22:50:12.018591 CH=0, VrefRange= 0, VrefLevel = 2
1870 22:50:12.018651 TX Bit0 (982~993) 12 987, Bit8 (972~986) 15 979,
1871 22:50:12.018713 TX Bit1 (979~994) 16 986, Bit9 (975~987) 13 981,
1872 22:50:12.018777 TX Bit2 (982~993) 12 987, Bit10 (978~993) 16 985,
1873 22:50:12.018853 TX Bit3 (976~990) 15 983, Bit11 (974~984) 11 979,
1874 22:50:12.018948 TX Bit4 (979~993) 15 986, Bit12 (976~987) 12 981,
1875 22:50:12.019042 TX Bit5 (978~990) 13 984, Bit13 (975~989) 15 982,
1876 22:50:12.019135 TX Bit6 (978~992) 15 985, Bit14 (975~991) 17 983,
1877 22:50:12.019238 TX Bit7 (979~993) 15 986, Bit15 (978~992) 15 985,
1878 22:50:12.019303
1879 22:50:12.019363 Write Rank1 MR14 =0x4
1880 22:50:12.019423
1881 22:50:12.019482 CH=0, VrefRange= 0, VrefLevel = 4
1882 22:50:12.019542 TX Bit0 (981~994) 14 987, Bit8 (971~987) 17 979,
1883 22:50:12.019602 TX Bit1 (979~995) 17 987, Bit9 (975~988) 14 981,
1884 22:50:12.019662 TX Bit2 (982~993) 12 987, Bit10 (978~993) 16 985,
1885 22:50:12.019721 TX Bit3 (976~991) 16 983, Bit11 (974~985) 12 979,
1886 22:50:12.019781 TX Bit4 (979~994) 16 986, Bit12 (975~987) 13 981,
1887 22:50:12.019841 TX Bit5 (978~991) 14 984, Bit13 (974~989) 16 981,
1888 22:50:12.019900 TX Bit6 (978~992) 15 985, Bit14 (975~992) 18 983,
1889 22:50:12.019960 TX Bit7 (979~994) 16 986, Bit15 (978~992) 15 985,
1890 22:50:12.020019
1891 22:50:12.020078 Write Rank1 MR14 =0x6
1892 22:50:12.020137
1893 22:50:12.020196 CH=0, VrefRange= 0, VrefLevel = 6
1894 22:50:12.020260 TX Bit0 (981~995) 15 988, Bit8 (971~988) 18 979,
1895 22:50:12.020324 TX Bit1 (979~996) 18 987, Bit9 (974~989) 16 981,
1896 22:50:12.020386 TX Bit2 (981~994) 14 987, Bit10 (977~994) 18 985,
1897 22:50:12.020445 TX Bit3 (975~991) 17 983, Bit11 (973~986) 14 979,
1898 22:50:12.020505 TX Bit4 (979~995) 17 987, Bit12 (975~989) 15 982,
1899 22:50:12.020565 TX Bit5 (978~991) 14 984, Bit13 (974~989) 16 981,
1900 22:50:12.020626 TX Bit6 (978~993) 16 985, Bit14 (974~992) 19 983,
1901 22:50:12.020685 TX Bit7 (979~995) 17 987, Bit15 (976~994) 19 985,
1902 22:50:12.020745
1903 22:50:12.020805 Write Rank1 MR14 =0x8
1904 22:50:12.020864
1905 22:50:12.020922 CH=0, VrefRange= 0, VrefLevel = 8
1906 22:50:12.020982 TX Bit0 (981~996) 16 988, Bit8 (971~989) 19 980,
1907 22:50:12.021042 TX Bit1 (979~997) 19 988, Bit9 (974~989) 16 981,
1908 22:50:12.021103 TX Bit2 (981~995) 15 988, Bit10 (977~996) 20 986,
1909 22:50:12.021162 TX Bit3 (975~991) 17 983, Bit11 (973~987) 15 980,
1910 22:50:12.021222 TX Bit4 (979~996) 18 987, Bit12 (974~989) 16 981,
1911 22:50:12.021283 TX Bit5 (977~992) 16 984, Bit13 (974~990) 17 982,
1912 22:50:12.021343 TX Bit6 (977~994) 18 985, Bit14 (974~993) 20 983,
1913 22:50:12.021402 TX Bit7 (979~996) 18 987, Bit15 (977~994) 18 985,
1914 22:50:12.021462
1915 22:50:12.021522 Write Rank1 MR14 =0xa
1916 22:50:12.021581
1917 22:50:12.021640 CH=0, VrefRange= 0, VrefLevel = 10
1918 22:50:12.021699 TX Bit0 (980~997) 18 988, Bit8 (970~989) 20 979,
1919 22:50:12.021760 TX Bit1 (978~998) 21 988, Bit9 (974~990) 17 982,
1920 22:50:12.021826 TX Bit2 (980~996) 17 988, Bit10 (977~996) 20 986,
1921 22:50:12.021890 TX Bit3 (974~992) 19 983, Bit11 (972~988) 17 980,
1922 22:50:12.021952 TX Bit4 (978~996) 19 987, Bit12 (975~990) 16 982,
1923 22:50:12.022012 TX Bit5 (977~992) 16 984, Bit13 (974~990) 17 982,
1924 22:50:12.022072 TX Bit6 (977~994) 18 985, Bit14 (974~993) 20 983,
1925 22:50:12.022136 TX Bit7 (979~997) 19 988, Bit15 (976~996) 21 986,
1926 22:50:12.022228
1927 22:50:12.022321 Write Rank1 MR14 =0xc
1928 22:50:12.022413
1929 22:50:12.022506 CH=0, VrefRange= 0, VrefLevel = 12
1930 22:50:12.022599 TX Bit0 (979~998) 20 988, Bit8 (970~990) 21 980,
1931 22:50:12.022693 TX Bit1 (978~998) 21 988, Bit9 (973~990) 18 981,
1932 22:50:12.022787 TX Bit2 (980~997) 18 988, Bit10 (977~997) 21 987,
1933 22:50:12.022881 TX Bit3 (974~992) 19 983, Bit11 (972~989) 18 980,
1934 22:50:12.022975 TX Bit4 (978~997) 20 987, Bit12 (974~990) 17 982,
1935 22:50:12.023069 TX Bit5 (977~993) 17 985, Bit13 (973~991) 19 982,
1936 22:50:12.023162 TX Bit6 (977~995) 19 986, Bit14 (973~994) 22 983,
1937 22:50:12.023253 TX Bit7 (979~998) 20 988, Bit15 (976~996) 21 986,
1938 22:50:12.023317
1939 22:50:12.023381 Write Rank1 MR14 =0xe
1940 22:50:12.023443
1941 22:50:12.023509 CH=0, VrefRange= 0, VrefLevel = 14
1942 22:50:12.023570 TX Bit0 (979~998) 20 988, Bit8 (970~990) 21 980,
1943 22:50:12.023630 TX Bit1 (978~998) 21 988, Bit9 (973~990) 18 981,
1944 22:50:12.023690 TX Bit2 (979~998) 20 988, Bit10 (976~997) 22 986,
1945 22:50:12.023750 TX Bit3 (974~992) 19 983, Bit11 (971~989) 19 980,
1946 22:50:12.023810 TX Bit4 (978~998) 21 988, Bit12 (974~990) 17 982,
1947 22:50:12.023869 TX Bit5 (977~994) 18 985, Bit13 (973~991) 19 982,
1948 22:50:12.023929 TX Bit6 (977~996) 20 986, Bit14 (973~995) 23 984,
1949 22:50:12.023989 TX Bit7 (978~998) 21 988, Bit15 (976~997) 22 986,
1950 22:50:12.024048
1951 22:50:12.024107 Write Rank1 MR14 =0x10
1952 22:50:12.024166
1953 22:50:12.024225 CH=0, VrefRange= 0, VrefLevel = 16
1954 22:50:12.024284 TX Bit0 (979~999) 21 989, Bit8 (969~990) 22 979,
1955 22:50:12.024344 TX Bit1 (978~999) 22 988, Bit9 (973~991) 19 982,
1956 22:50:12.024404 TX Bit2 (979~998) 20 988, Bit10 (976~997) 22 986,
1957 22:50:12.024463 TX Bit3 (973~993) 21 983, Bit11 (971~990) 20 980,
1958 22:50:12.024523 TX Bit4 (978~998) 21 988, Bit12 (973~991) 19 982,
1959 22:50:12.024583 TX Bit5 (977~994) 18 985, Bit13 (972~992) 21 982,
1960 22:50:12.024839 TX Bit6 (977~997) 21 987, Bit14 (973~995) 23 984,
1961 22:50:12.024908 TX Bit7 (978~999) 22 988, Bit15 (976~997) 22 986,
1962 22:50:12.024969
1963 22:50:12.025029 Write Rank1 MR14 =0x12
1964 22:50:12.025088
1965 22:50:12.025147 CH=0, VrefRange= 0, VrefLevel = 18
1966 22:50:12.025207 TX Bit0 (979~999) 21 989, Bit8 (969~991) 23 980,
1967 22:50:12.025267 TX Bit1 (978~999) 22 988, Bit9 (972~991) 20 981,
1968 22:50:12.025326 TX Bit2 (979~999) 21 989, Bit10 (976~998) 23 987,
1969 22:50:12.025387 TX Bit3 (974~993) 20 983, Bit11 (970~990) 21 980,
1970 22:50:12.025447 TX Bit4 (978~999) 22 988, Bit12 (972~991) 20 981,
1971 22:50:12.025507 TX Bit5 (977~995) 19 986, Bit13 (972~992) 21 982,
1972 22:50:12.025567 TX Bit6 (977~998) 22 987, Bit14 (972~996) 25 984,
1973 22:50:12.025626 TX Bit7 (978~999) 22 988, Bit15 (976~998) 23 987,
1974 22:50:12.167950
1975 22:50:12.168120 Write Rank1 MR14 =0x14
1976 22:50:12.168228
1977 22:50:12.168329 CH=0, VrefRange= 0, VrefLevel = 20
1978 22:50:12.168432 TX Bit0 (979~1000) 22 989, Bit8 (969~991) 23 980,
1979 22:50:12.168536 TX Bit1 (978~1000) 23 989, Bit9 (971~991) 21 981,
1980 22:50:12.168622 TX Bit2 (979~999) 21 989, Bit10 (976~998) 23 987,
1981 22:50:12.168688 TX Bit3 (972~994) 23 983, Bit11 (970~990) 21 980,
1982 22:50:12.168752 TX Bit4 (977~999) 23 988, Bit12 (972~992) 21 982,
1983 22:50:12.168814 TX Bit5 (976~995) 20 985, Bit13 (972~992) 21 982,
1984 22:50:12.168877 TX Bit6 (976~998) 23 987, Bit14 (972~997) 26 984,
1985 22:50:12.168938 TX Bit7 (978~999) 22 988, Bit15 (976~998) 23 987,
1986 22:50:12.168999
1987 22:50:12.169059 Write Rank1 MR14 =0x16
1988 22:50:12.169120
1989 22:50:12.169180 CH=0, VrefRange= 0, VrefLevel = 22
1990 22:50:12.169240 TX Bit0 (979~1001) 23 990, Bit8 (969~991) 23 980,
1991 22:50:12.169301 TX Bit1 (978~1000) 23 989, Bit9 (971~992) 22 981,
1992 22:50:12.169368 TX Bit2 (978~999) 22 988, Bit10 (976~998) 23 987,
1993 22:50:12.169431 TX Bit3 (972~994) 23 983, Bit11 (969~991) 23 980,
1994 22:50:12.169496 TX Bit4 (977~999) 23 988, Bit12 (971~992) 22 981,
1995 22:50:12.169556 TX Bit5 (976~996) 21 986, Bit13 (971~994) 24 982,
1996 22:50:12.169617 TX Bit6 (976~999) 24 987, Bit14 (971~997) 27 984,
1997 22:50:12.169684 TX Bit7 (978~1000) 23 989, Bit15 (975~998) 24 986,
1998 22:50:12.169752
1999 22:50:12.169813 Write Rank1 MR14 =0x18
2000 22:50:12.169873
2001 22:50:12.169932 CH=0, VrefRange= 0, VrefLevel = 24
2002 22:50:12.169993 TX Bit0 (978~1000) 23 989, Bit8 (969~992) 24 980,
2003 22:50:12.170053 TX Bit1 (978~1000) 23 989, Bit9 (971~992) 22 981,
2004 22:50:12.170113 TX Bit2 (978~1000) 23 989, Bit10 (976~999) 24 987,
2005 22:50:12.170173 TX Bit3 (972~995) 24 983, Bit11 (969~991) 23 980,
2006 22:50:12.170233 TX Bit4 (977~1000) 24 988, Bit12 (971~993) 23 982,
2007 22:50:12.170293 TX Bit5 (976~997) 22 986, Bit13 (970~994) 25 982,
2008 22:50:12.170353 TX Bit6 (976~999) 24 987, Bit14 (971~997) 27 984,
2009 22:50:12.170413 TX Bit7 (978~1000) 23 989, Bit15 (975~998) 24 986,
2010 22:50:12.170473
2011 22:50:12.170532 Write Rank1 MR14 =0x1a
2012 22:50:12.170592
2013 22:50:12.170651 CH=0, VrefRange= 0, VrefLevel = 26
2014 22:50:12.170711 TX Bit0 (979~1001) 23 990, Bit8 (968~993) 26 980,
2015 22:50:12.170771 TX Bit1 (978~1001) 24 989, Bit9 (971~993) 23 982,
2016 22:50:12.170831 TX Bit2 (978~1001) 24 989, Bit10 (975~999) 25 987,
2017 22:50:12.170891 TX Bit3 (971~995) 25 983, Bit11 (969~992) 24 980,
2018 22:50:12.170950 TX Bit4 (977~1000) 24 988, Bit12 (971~994) 24 982,
2019 22:50:12.171010 TX Bit5 (975~998) 24 986, Bit13 (970~995) 26 982,
2020 22:50:12.171070 TX Bit6 (976~999) 24 987, Bit14 (970~998) 29 984,
2021 22:50:12.171129 TX Bit7 (977~1000) 24 988, Bit15 (975~998) 24 986,
2022 22:50:12.171189
2023 22:50:12.171258 Write Rank1 MR14 =0x1c
2024 22:50:12.171334
2025 22:50:12.171395 CH=0, VrefRange= 0, VrefLevel = 28
2026 22:50:12.171455 TX Bit0 (978~1002) 25 990, Bit8 (968~993) 26 980,
2027 22:50:12.171515 TX Bit1 (977~1001) 25 989, Bit9 (970~994) 25 982,
2028 22:50:12.171575 TX Bit2 (978~1000) 23 989, Bit10 (975~1000) 26 987,
2029 22:50:12.171636 TX Bit3 (971~996) 26 983, Bit11 (969~992) 24 980,
2030 22:50:12.171696 TX Bit4 (977~1000) 24 988, Bit12 (971~994) 24 982,
2031 22:50:12.171756 TX Bit5 (975~998) 24 986, Bit13 (970~995) 26 982,
2032 22:50:12.171816 TX Bit6 (976~1000) 25 988, Bit14 (971~997) 27 984,
2033 22:50:12.171881 TX Bit7 (977~1001) 25 989, Bit15 (975~999) 25 987,
2034 22:50:12.171948
2035 22:50:12.172008 Write Rank1 MR14 =0x1e
2036 22:50:12.172068
2037 22:50:12.172127 CH=0, VrefRange= 0, VrefLevel = 30
2038 22:50:12.172187 TX Bit0 (978~1002) 25 990, Bit8 (968~993) 26 980,
2039 22:50:12.172248 TX Bit1 (977~1001) 25 989, Bit9 (970~994) 25 982,
2040 22:50:12.172307 TX Bit2 (978~1002) 25 990, Bit10 (975~1000) 26 987,
2041 22:50:12.172368 TX Bit3 (971~995) 25 983, Bit11 (969~993) 25 981,
2042 22:50:12.172427 TX Bit4 (977~1001) 25 989, Bit12 (970~995) 26 982,
2043 22:50:12.172488 TX Bit5 (975~998) 24 986, Bit13 (970~994) 25 982,
2044 22:50:12.172547 TX Bit6 (976~1000) 25 988, Bit14 (971~997) 27 984,
2045 22:50:12.172607 TX Bit7 (977~1002) 26 989, Bit15 (974~999) 26 986,
2046 22:50:12.172667
2047 22:50:12.172730 Write Rank1 MR14 =0x20
2048 22:50:12.172791
2049 22:50:12.172854 CH=0, VrefRange= 0, VrefLevel = 32
2050 22:50:12.172915 TX Bit0 (978~1002) 25 990, Bit8 (968~993) 26 980,
2051 22:50:12.172976 TX Bit1 (977~1001) 25 989, Bit9 (970~994) 25 982,
2052 22:50:12.173036 TX Bit2 (978~1002) 25 990, Bit10 (975~1000) 26 987,
2053 22:50:12.173096 TX Bit3 (971~995) 25 983, Bit11 (969~993) 25 981,
2054 22:50:12.173156 TX Bit4 (977~1001) 25 989, Bit12 (970~995) 26 982,
2055 22:50:12.173215 TX Bit5 (975~998) 24 986, Bit13 (970~994) 25 982,
2056 22:50:12.173275 TX Bit6 (976~1000) 25 988, Bit14 (971~997) 27 984,
2057 22:50:12.173335 TX Bit7 (977~1002) 26 989, Bit15 (974~999) 26 986,
2058 22:50:12.173395
2059 22:50:12.173454 Write Rank1 MR14 =0x22
2060 22:50:12.173514
2061 22:50:12.173573 CH=0, VrefRange= 0, VrefLevel = 34
2062 22:50:12.173842 TX Bit0 (978~1002) 25 990, Bit8 (968~993) 26 980,
2063 22:50:12.173945 TX Bit1 (977~1001) 25 989, Bit9 (970~994) 25 982,
2064 22:50:12.174042 TX Bit2 (978~1002) 25 990, Bit10 (975~1000) 26 987,
2065 22:50:12.174137 TX Bit3 (971~995) 25 983, Bit11 (969~993) 25 981,
2066 22:50:12.174206 TX Bit4 (977~1001) 25 989, Bit12 (970~995) 26 982,
2067 22:50:12.174272 TX Bit5 (975~998) 24 986, Bit13 (970~994) 25 982,
2068 22:50:12.174334 TX Bit6 (976~1000) 25 988, Bit14 (971~997) 27 984,
2069 22:50:12.174395 TX Bit7 (977~1002) 26 989, Bit15 (974~999) 26 986,
2070 22:50:12.174455
2071 22:50:12.174515 Write Rank1 MR14 =0x24
2072 22:50:12.174575
2073 22:50:12.174635 CH=0, VrefRange= 0, VrefLevel = 36
2074 22:50:12.174694 TX Bit0 (978~1002) 25 990, Bit8 (968~993) 26 980,
2075 22:50:12.174754 TX Bit1 (977~1001) 25 989, Bit9 (970~994) 25 982,
2076 22:50:12.174815 TX Bit2 (978~1002) 25 990, Bit10 (975~1000) 26 987,
2077 22:50:12.174875 TX Bit3 (971~995) 25 983, Bit11 (969~993) 25 981,
2078 22:50:12.174935 TX Bit4 (977~1001) 25 989, Bit12 (970~995) 26 982,
2079 22:50:12.174995 TX Bit5 (975~998) 24 986, Bit13 (970~994) 25 982,
2080 22:50:12.175055 TX Bit6 (976~1000) 25 988, Bit14 (971~997) 27 984,
2081 22:50:12.175137 TX Bit7 (977~1002) 26 989, Bit15 (974~999) 26 986,
2082 22:50:12.175238
2083 22:50:12.175302
2084 22:50:12.175362 TX Vref found, early break! 381< 385
2085 22:50:12.175424 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2086 22:50:12.175484 u1DelayCellOfst[0]=9 cells (7 PI)
2087 22:50:12.175544 u1DelayCellOfst[1]=7 cells (6 PI)
2088 22:50:12.175604 u1DelayCellOfst[2]=9 cells (7 PI)
2089 22:50:12.175663 u1DelayCellOfst[3]=0 cells (0 PI)
2090 22:50:12.175730 u1DelayCellOfst[4]=7 cells (6 PI)
2091 22:50:12.175791 u1DelayCellOfst[5]=3 cells (3 PI)
2092 22:50:12.175854 u1DelayCellOfst[6]=6 cells (5 PI)
2093 22:50:12.175914 u1DelayCellOfst[7]=7 cells (6 PI)
2094 22:50:12.175973 Byte0, DQ PI dly=983, DQM PI dly= 986
2095 22:50:12.176037 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
2096 22:50:12.176102
2097 22:50:12.176163 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
2098 22:50:12.176224
2099 22:50:12.176283 u1DelayCellOfst[8]=0 cells (0 PI)
2100 22:50:12.176343 u1DelayCellOfst[9]=2 cells (2 PI)
2101 22:50:12.176403 u1DelayCellOfst[10]=9 cells (7 PI)
2102 22:50:12.176461 u1DelayCellOfst[11]=1 cells (1 PI)
2103 22:50:12.176521 u1DelayCellOfst[12]=2 cells (2 PI)
2104 22:50:12.176580 u1DelayCellOfst[13]=2 cells (2 PI)
2105 22:50:12.176640 u1DelayCellOfst[14]=5 cells (4 PI)
2106 22:50:12.176699 u1DelayCellOfst[15]=7 cells (6 PI)
2107 22:50:12.176758 Byte1, DQ PI dly=980, DQM PI dly= 983
2108 22:50:12.176818 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2109 22:50:12.176878
2110 22:50:12.176937 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2111 22:50:12.176998
2112 22:50:12.177057 Write Rank1 MR14 =0x1e
2113 22:50:12.177116
2114 22:50:12.177175 Final TX Range 0 Vref 30
2115 22:50:12.177234
2116 22:50:12.177293 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2117 22:50:12.177353
2118 22:50:12.177412 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2119 22:50:12.177472 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2120 22:50:12.177533 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2121 22:50:12.177592 Write Rank1 MR3 =0xb0
2122 22:50:12.177653 DramC Write-DBI on
2123 22:50:12.177711 ==
2124 22:50:12.177771 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2125 22:50:12.177831 fsp= 1, odt_onoff= 1, Byte mode= 0
2126 22:50:12.177891 ==
2127 22:50:12.177950 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2128 22:50:12.178010
2129 22:50:12.178069 Begin, DQ Scan Range 703~767
2130 22:50:12.178132
2131 22:50:12.178195
2132 22:50:12.178256 TX Vref Scan disable
2133 22:50:12.178316 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2134 22:50:12.178378 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2135 22:50:12.178439 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2136 22:50:12.178500 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2137 22:50:12.178561 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2138 22:50:12.178622 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2139 22:50:12.178682 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2140 22:50:12.178743 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2141 22:50:12.178804 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2142 22:50:12.178864 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2143 22:50:12.178928 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2144 22:50:12.178989 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2145 22:50:12.179050 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2146 22:50:12.179110 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2147 22:50:12.179171 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2148 22:50:12.179245 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2149 22:50:12.179313 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2150 22:50:12.179375 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2151 22:50:12.179436 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2152 22:50:12.179496 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2153 22:50:12.179557 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2154 22:50:12.179617 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2155 22:50:12.179678 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2156 22:50:12.179738 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
2157 22:50:12.179798 Byte0, DQ PI dly=732, DQM PI dly= 732
2158 22:50:12.179858 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
2159 22:50:12.179918
2160 22:50:12.179978 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
2161 22:50:12.180038
2162 22:50:12.180097 Byte1, DQ PI dly=726, DQM PI dly= 726
2163 22:50:12.180157 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 22)
2164 22:50:12.180217
2165 22:50:12.180280 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 22)
2166 22:50:12.180346
2167 22:50:12.180407 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2168 22:50:12.180468 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2169 22:50:12.180530 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2170 22:50:12.180592 Write Rank1 MR3 =0x30
2171 22:50:12.180652 DramC Write-DBI off
2172 22:50:12.180712
2173 22:50:12.180772 [DATLAT]
2174 22:50:12.180831 Freq=1600, CH0 RK1, use_rxtx_scan=0
2175 22:50:12.180892
2176 22:50:12.181152 DATLAT Default: 0x10
2177 22:50:12.181222 7, 0xFFFF, sum=0
2178 22:50:12.181286 8, 0xFFFF, sum=0
2179 22:50:12.181348 9, 0xFFFF, sum=0
2180 22:50:12.181409 10, 0xFFFF, sum=0
2181 22:50:12.181470 11, 0xFFFF, sum=0
2182 22:50:12.181531 12, 0xFFFF, sum=0
2183 22:50:12.181591 13, 0xFFFF, sum=0
2184 22:50:12.181652 14, 0x0, sum=1
2185 22:50:12.181712 15, 0x0, sum=2
2186 22:50:12.181772 16, 0x0, sum=3
2187 22:50:12.181833 17, 0x0, sum=4
2188 22:50:12.181893 pattern=2 first_step=14 total pass=5 best_step=16
2189 22:50:12.181960 ==
2190 22:50:12.182027 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2191 22:50:12.182090 fsp= 1, odt_onoff= 1, Byte mode= 0
2192 22:50:12.182150 ==
2193 22:50:12.182211 Start DQ dly to find pass range UseTestEngine =1
2194 22:50:12.182271 x-axis: bit #, y-axis: DQ dly (-127~63)
2195 22:50:12.182331 RX Vref Scan = 0
2196 22:50:12.182391 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2197 22:50:12.182453 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2198 22:50:12.182515 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2199 22:50:12.182577 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2200 22:50:12.182642 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2201 22:50:12.182705 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2202 22:50:12.182766 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2203 22:50:12.182827 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2204 22:50:12.182887 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2205 22:50:12.182948 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2206 22:50:12.183016 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2207 22:50:12.183079 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2208 22:50:12.183141 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2209 22:50:12.183202 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2210 22:50:12.183278 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2211 22:50:12.183340 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2212 22:50:12.183401 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2213 22:50:12.183463 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2214 22:50:12.183524 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2215 22:50:12.183585 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2216 22:50:12.183646 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2217 22:50:12.183707 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2218 22:50:12.183768 -4, [0] xxxxxxxx oxxxxxxx [MSB]
2219 22:50:12.183828 -3, [0] xxxxxxxx oxxxxxxx [MSB]
2220 22:50:12.183889 -2, [0] xxxoxxxx ooxoxxxx [MSB]
2221 22:50:12.183950 -1, [0] xxxoxoxx ooxoxoxx [MSB]
2222 22:50:12.184011 0, [0] xxxoxoxx ooxoooxx [MSB]
2223 22:50:12.184072 1, [0] xxxoxoox ooxoooox [MSB]
2224 22:50:12.184134 2, [0] xxxoxoox ooxoooox [MSB]
2225 22:50:12.184195 3, [0] oxxooooo ooxoooox [MSB]
2226 22:50:12.184256 4, [0] ooxooooo ooxooooo [MSB]
2227 22:50:12.184317 5, [0] oooooooo ooxooooo [MSB]
2228 22:50:12.184378 6, [0] oooooooo ooxooooo [MSB]
2229 22:50:12.184439 32, [0] oooxoooo oooooooo [MSB]
2230 22:50:12.184500 33, [0] oooxoooo xooxoooo [MSB]
2231 22:50:12.184561 34, [0] oooxoooo xooxxxoo [MSB]
2232 22:50:12.184622 35, [0] oooxoxoo xxoxxxoo [MSB]
2233 22:50:12.184683 36, [0] oooxoxxo xxoxxxoo [MSB]
2234 22:50:12.184743 37, [0] oooxoxxo xxoxxxxo [MSB]
2235 22:50:12.184804 38, [0] oooxoxxx xxoxxxxx [MSB]
2236 22:50:12.184865 39, [0] xxoxxxxx xxoxxxxx [MSB]
2237 22:50:12.184925 40, [0] xxoxxxxx xxxxxxxx [MSB]
2238 22:50:12.184986 41, [0] xxxxxxxx xxxxxxxx [MSB]
2239 22:50:12.185047 iDelay=41, Bit 0, Center 20 (3 ~ 38) 36
2240 22:50:12.185107 iDelay=41, Bit 1, Center 21 (4 ~ 38) 35
2241 22:50:12.185167 iDelay=41, Bit 2, Center 22 (5 ~ 40) 36
2242 22:50:12.185240 iDelay=41, Bit 3, Center 14 (-2 ~ 31) 34
2243 22:50:12.185789 iDelay=41, Bit 4, Center 20 (3 ~ 38) 36
2244 22:50:12.192251 iDelay=41, Bit 5, Center 16 (-1 ~ 34) 36
2245 22:50:12.195505 iDelay=41, Bit 6, Center 18 (1 ~ 35) 35
2246 22:50:12.198984 iDelay=41, Bit 7, Center 20 (3 ~ 37) 35
2247 22:50:12.202390 iDelay=41, Bit 8, Center 14 (-4 ~ 32) 37
2248 22:50:12.205505 iDelay=41, Bit 9, Center 16 (-2 ~ 34) 37
2249 22:50:12.208816 iDelay=41, Bit 10, Center 23 (7 ~ 39) 33
2250 22:50:12.212464 iDelay=41, Bit 11, Center 15 (-2 ~ 32) 35
2251 22:50:12.215111 iDelay=41, Bit 12, Center 16 (0 ~ 33) 34
2252 22:50:12.218815 iDelay=41, Bit 13, Center 16 (-1 ~ 33) 35
2253 22:50:12.225007 iDelay=41, Bit 14, Center 18 (1 ~ 36) 36
2254 22:50:12.228661 iDelay=41, Bit 15, Center 20 (4 ~ 37) 34
2255 22:50:12.228755 ==
2256 22:50:12.231672 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2257 22:50:12.234720 fsp= 1, odt_onoff= 1, Byte mode= 0
2258 22:50:12.234814 ==
2259 22:50:12.238001 DQS Delay:
2260 22:50:12.238093 DQS0 = 0, DQS1 = 0
2261 22:50:12.238167 DQM Delay:
2262 22:50:12.242081 DQM0 = 18, DQM1 = 17
2263 22:50:12.242175 DQ Delay:
2264 22:50:12.244606 DQ0 =20, DQ1 =21, DQ2 =22, DQ3 =14
2265 22:50:12.248097 DQ4 =20, DQ5 =16, DQ6 =18, DQ7 =20
2266 22:50:12.251543 DQ8 =14, DQ9 =16, DQ10 =23, DQ11 =15
2267 22:50:12.254490 DQ12 =16, DQ13 =16, DQ14 =18, DQ15 =20
2268 22:50:12.254583
2269 22:50:12.254656
2270 22:50:12.254725
2271 22:50:12.258115 [DramC_TX_OE_Calibration] TA2
2272 22:50:12.261240 Original DQ_B0 (3 6) =30, OEN = 27
2273 22:50:12.264737 Original DQ_B1 (3 6) =30, OEN = 27
2274 22:50:12.267901 23, 0x0, End_B0=23 End_B1=23
2275 22:50:12.271062 24, 0x0, End_B0=24 End_B1=24
2276 22:50:12.274179 25, 0x0, End_B0=25 End_B1=25
2277 22:50:12.274274 26, 0x0, End_B0=26 End_B1=26
2278 22:50:12.277703 27, 0x0, End_B0=27 End_B1=27
2279 22:50:12.280947 28, 0x0, End_B0=28 End_B1=28
2280 22:50:12.283849 29, 0x0, End_B0=29 End_B1=29
2281 22:50:12.283944 30, 0x0, End_B0=30 End_B1=30
2282 22:50:12.287197 31, 0xFFFF, End_B0=30 End_B1=30
2283 22:50:12.293889 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2284 22:50:12.300556 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2285 22:50:12.300651
2286 22:50:12.300724
2287 22:50:12.300792 Write Rank1 MR23 =0x3f
2288 22:50:12.304097 [DQSOSC]
2289 22:50:12.310146 [DQSOSCAuto] RK1, (LSB)MR18= 0xa4a4, (MSB)MR19= 0x202, tDQSOscB0 = 465 ps tDQSOscB1 = 465 ps
2290 22:50:12.316606 CH0_RK1: MR19=0x202, MR18=0xA4A4, DQSOSC=465, MR23=63, INC=11, DEC=17
2291 22:50:12.320225 Write Rank1 MR23 =0x3f
2292 22:50:12.320322 [DQSOSC]
2293 22:50:12.326765 [DQSOSCAuto] RK1, (LSB)MR18= 0xa5a5, (MSB)MR19= 0x202, tDQSOscB0 = 465 ps tDQSOscB1 = 465 ps
2294 22:50:12.329814 CH0 RK1: MR19=202, MR18=A5A5
2295 22:50:12.333170 [RxdqsGatingPostProcess] freq 1600
2296 22:50:12.339740 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2297 22:50:12.339834 Rank: 0
2298 22:50:12.342918 best DQS0 dly(2T, 0.5T) = (2, 6)
2299 22:50:12.345982 best DQS1 dly(2T, 0.5T) = (2, 6)
2300 22:50:12.349347 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2301 22:50:12.352738 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2302 22:50:12.352832 Rank: 1
2303 22:50:12.355906 best DQS0 dly(2T, 0.5T) = (2, 6)
2304 22:50:12.359382 best DQS1 dly(2T, 0.5T) = (2, 6)
2305 22:50:12.362720 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2306 22:50:12.365704 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2307 22:50:12.369152 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2308 22:50:12.372234 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2309 22:50:12.379209 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2310 22:50:12.379315 Write Rank0 MR13 =0x59
2311 22:50:12.379390 ==
2312 22:50:12.385224 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2313 22:50:12.388511 fsp= 1, odt_onoff= 1, Byte mode= 0
2314 22:50:12.388605 ==
2315 22:50:12.392421 === u2Vref_new: 0x56 --> 0x3a
2316 22:50:12.395067 === u2Vref_new: 0x58 --> 0x58
2317 22:50:12.398834 === u2Vref_new: 0x5a --> 0x5a
2318 22:50:12.401698 === u2Vref_new: 0x5c --> 0x78
2319 22:50:12.405198 === u2Vref_new: 0x5e --> 0x7a
2320 22:50:12.408253 === u2Vref_new: 0x60 --> 0x90
2321 22:50:12.411836 [CA 0] Center 38 (13~63) winsize 51
2322 22:50:12.414984 [CA 1] Center 37 (11~63) winsize 53
2323 22:50:12.418404 [CA 2] Center 34 (6~63) winsize 58
2324 22:50:12.421377 [CA 3] Center 34 (6~63) winsize 58
2325 22:50:12.424686 [CA 4] Center 34 (5~63) winsize 59
2326 22:50:12.424780 [CA 5] Center 28 (-1~57) winsize 59
2327 22:50:12.428133
2328 22:50:12.431243 [CATrainingPosCal] consider 1 rank data
2329 22:50:12.434606 u2DelayCellTimex100 = 744/100 ps
2330 22:50:12.437699 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2331 22:50:12.441279 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2332 22:50:12.444064 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2333 22:50:12.447551 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2334 22:50:12.451199 CA4 delay=34 (5~63),Diff = 6 PI (7 cell)
2335 22:50:12.453874 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2336 22:50:12.453969
2337 22:50:12.461160 CA PerBit enable=1, Macro0, CA PI delay=28
2338 22:50:12.461254 === u2Vref_new: 0x5c --> 0x78
2339 22:50:12.461330
2340 22:50:12.464167 Vref(ca) range 1: 28
2341 22:50:12.464261
2342 22:50:12.467133 CS Dly= 11 (42-0-32)
2343 22:50:12.467262 Write Rank0 MR13 =0xd8
2344 22:50:12.470540 Write Rank0 MR13 =0xd8
2345 22:50:12.473934 Write Rank0 MR12 =0x5c
2346 22:50:12.474051 Write Rank1 MR13 =0x59
2347 22:50:12.474162 ==
2348 22:50:12.480148 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2349 22:50:12.483667 fsp= 1, odt_onoff= 1, Byte mode= 0
2350 22:50:12.483762 ==
2351 22:50:12.486651 === u2Vref_new: 0x56 --> 0x3a
2352 22:50:12.490611 === u2Vref_new: 0x58 --> 0x58
2353 22:50:12.493483 === u2Vref_new: 0x5a --> 0x5a
2354 22:50:12.493581 === u2Vref_new: 0x5c --> 0x78
2355 22:50:12.496978 === u2Vref_new: 0x5e --> 0x7a
2356 22:50:12.500284 === u2Vref_new: 0x60 --> 0x90
2357 22:50:12.503654 [CA 0] Center 37 (11~63) winsize 53
2358 22:50:12.506908 [CA 1] Center 37 (11~63) winsize 53
2359 22:50:12.509987 [CA 2] Center 34 (5~63) winsize 59
2360 22:50:12.513205 [CA 3] Center 35 (7~63) winsize 57
2361 22:50:12.516490 [CA 4] Center 34 (5~63) winsize 59
2362 22:50:12.520020 [CA 5] Center 28 (-1~58) winsize 60
2363 22:50:12.520114
2364 22:50:12.523811 [CATrainingPosCal] consider 2 rank data
2365 22:50:12.526394 u2DelayCellTimex100 = 744/100 ps
2366 22:50:12.529874 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2367 22:50:12.532986 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2368 22:50:12.539569 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2369 22:50:12.542711 CA3 delay=35 (7~63),Diff = 7 PI (9 cell)
2370 22:50:12.546492 CA4 delay=34 (5~63),Diff = 6 PI (7 cell)
2371 22:50:12.549682 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2372 22:50:12.549772
2373 22:50:12.552952 CA PerBit enable=1, Macro0, CA PI delay=28
2374 22:50:12.556265 === u2Vref_new: 0x5e --> 0x7a
2375 22:50:12.556359
2376 22:50:12.559715 Vref(ca) range 1: 30
2377 22:50:12.559813
2378 22:50:12.559886 CS Dly= 10 (41-0-32)
2379 22:50:12.562403 Write Rank1 MR13 =0xd8
2380 22:50:12.565904 Write Rank1 MR13 =0xd8
2381 22:50:12.566006 Write Rank1 MR12 =0x5e
2382 22:50:12.568938 [RankSwap] Rank num 2, (Multi 1), Rank 0
2383 22:50:12.572703 Write Rank0 MR2 =0xad
2384 22:50:12.572822 [Write Leveling]
2385 22:50:12.575472 delay byte0 byte1 byte2 byte3
2386 22:50:12.575566
2387 22:50:12.579154 10 0 0
2388 22:50:12.579262 11 0 0
2389 22:50:12.582564 12 0 0
2390 22:50:12.582652 13 0 0
2391 22:50:12.582738 14 0 0
2392 22:50:12.585546 15 0 0
2393 22:50:12.585638 16 0 0
2394 22:50:12.588703 17 0 0
2395 22:50:12.588788 18 0 0
2396 22:50:12.592311 19 0 0
2397 22:50:12.592408 20 0 0
2398 22:50:12.592480 21 0 0
2399 22:50:12.595186 22 0 0
2400 22:50:12.595304 23 0 0
2401 22:50:12.598625 24 0 0
2402 22:50:12.598751 25 0 0
2403 22:50:12.598858 26 0 0
2404 22:50:12.601718 27 0 0
2405 22:50:12.601812 28 0 0
2406 22:50:12.604973 29 0 0
2407 22:50:12.605067 30 0 ff
2408 22:50:12.608317 31 0 ff
2409 22:50:12.608411 32 0 ff
2410 22:50:12.611596 33 0 ff
2411 22:50:12.611690 34 0 ff
2412 22:50:12.611764 35 ff ff
2413 22:50:12.614945 36 0 ff
2414 22:50:12.615038 37 ff ff
2415 22:50:12.618362 38 ff ff
2416 22:50:12.618455 39 ff ff
2417 22:50:12.621527 40 ff ff
2418 22:50:12.621626 41 ff ff
2419 22:50:12.624716 42 ff ff
2420 22:50:12.624810 43 ff ff
2421 22:50:12.628352 pass bytecount = 0xff (0xff: all bytes pass)
2422 22:50:12.628449
2423 22:50:12.631419 DQS0 dly: 37
2424 22:50:12.631511 DQS1 dly: 30
2425 22:50:12.634401 Write Rank0 MR2 =0x2d
2426 22:50:12.637707 [RankSwap] Rank num 2, (Multi 1), Rank 0
2427 22:50:12.641169 Write Rank0 MR1 =0xd6
2428 22:50:12.641262 [Gating]
2429 22:50:12.641335 ==
2430 22:50:12.644822 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2431 22:50:12.647497 fsp= 1, odt_onoff= 1, Byte mode= 0
2432 22:50:12.647590 ==
2433 22:50:12.654250 3 1 0 |2c2b 3737 |(11 11)(11 11) |(1 1)(1 1)| 0
2434 22:50:12.657606 3 1 4 |2c2b 3433 |(11 11)(11 11) |(1 1)(1 1)| 0
2435 22:50:12.660473 3 1 8 |2c2b 3636 |(11 11)(0 0) |(1 1)(1 1)| 0
2436 22:50:12.667105 3 1 12 |2c2b 3636 |(11 11)(10 10) |(1 1)(1 1)| 0
2437 22:50:12.670413 3 1 16 |2c2b a09 |(11 11)(11 11) |(1 0)(0 0)| 0
2438 22:50:12.673685 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
2439 22:50:12.680401 3 1 24 |2c2b 2e2d |(11 11)(11 11) |(1 0)(1 1)| 0
2440 22:50:12.683787 3 1 28 |2c2b 3535 |(11 11)(11 11) |(1 0)(1 1)| 0
2441 22:50:12.686824 [Byte 1] Lead/lag falling Transition (3, 1, 28)
2442 22:50:12.693784 3 2 0 |2c2b 505 |(11 11)(11 11) |(1 0)(0 1)| 0
2443 22:50:12.697211 3 2 4 |2c2b 3635 |(11 11)(11 11) |(1 0)(0 1)| 0
2444 22:50:12.699909 3 2 8 |2c2b 3434 |(11 11)(11 11) |(1 0)(0 1)| 0
2445 22:50:12.706364 3 2 12 |2c2b 3333 |(11 11)(11 11) |(1 0)(0 1)| 0
2446 22:50:12.709875 3 2 16 |707 3433 |(11 11)(11 11) |(0 0)(0 1)| 0
2447 22:50:12.713042 3 2 20 |3534 3332 |(11 11)(11 11) |(0 0)(0 1)| 0
2448 22:50:12.719473 3 2 24 |3534 1e1d |(11 11)(11 11) |(0 0)(1 1)| 0
2449 22:50:12.722887 [Byte 1] Lead/lag Transition tap number (1)
2450 22:50:12.725985 3 2 28 |3534 2a29 |(11 11)(11 11) |(0 0)(0 0)| 0
2451 22:50:12.729696 3 3 0 |3534 3b3b |(11 11)(11 11) |(0 0)(0 0)| 0
2452 22:50:12.735969 3 3 4 |3534 1413 |(11 11)(11 11) |(0 0)(1 1)| 0
2453 22:50:12.739392 3 3 8 |3534 3b3a |(11 11)(11 11) |(0 0)(0 0)| 0
2454 22:50:12.742518 3 3 12 |3534 3737 |(11 11)(11 11) |(1 1)(0 0)| 0
2455 22:50:12.749296 3 3 16 |3534 3b3a |(11 11)(11 11) |(1 1)(1 1)| 0
2456 22:50:12.752762 3 3 20 |3534 f0f |(11 11)(11 11) |(1 1)(1 1)| 0
2457 22:50:12.756011 [Byte 0] Lead/lag falling Transition (3, 3, 20)
2458 22:50:12.762231 3 3 24 |3534 1211 |(11 11)(11 11) |(0 1)(1 1)| 0
2459 22:50:12.765322 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2460 22:50:12.768819 [Byte 1] Lead/lag falling Transition (3, 3, 28)
2461 22:50:12.775371 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2462 22:50:12.778603 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2463 22:50:12.781918 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2464 22:50:12.788487 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2465 22:50:12.792040 3 4 16 |504 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2466 22:50:12.794949 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2467 22:50:12.801804 3 4 24 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2468 22:50:12.805143 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2469 22:50:12.807786 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2470 22:50:12.814569 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2471 22:50:12.818238 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2472 22:50:12.821150 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2473 22:50:12.827488 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2474 22:50:12.830968 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2475 22:50:12.834350 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2476 22:50:12.840828 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2477 22:50:12.844337 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2478 22:50:12.847786 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2479 22:50:12.854006 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2480 22:50:12.857524 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2481 22:50:12.860541 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2482 22:50:12.863889 [Byte 0] Lead/lag Transition tap number (2)
2483 22:50:12.870154 [Byte 1] Lead/lag falling Transition (3, 6, 12)
2484 22:50:12.873632 3 6 16 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2485 22:50:12.876840 [Byte 1] Lead/lag Transition tap number (2)
2486 22:50:12.880218 3 6 20 |2222 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
2487 22:50:12.887550 3 6 24 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
2488 22:50:12.890226 [Byte 0]First pass (3, 6, 24)
2489 22:50:12.893267 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2490 22:50:12.896593 [Byte 1]First pass (3, 6, 28)
2491 22:50:12.899582 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2492 22:50:12.902721 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2493 22:50:12.906338 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2494 22:50:12.909287 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2495 22:50:12.915692 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2496 22:50:12.919253 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2497 22:50:12.922646 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2498 22:50:12.925914 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2499 22:50:12.932150 All bytes gating window > 1UI, Early break!
2500 22:50:12.932252
2501 22:50:12.935749 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2502 22:50:12.935852
2503 22:50:12.938671 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 16)
2504 22:50:12.938772
2505 22:50:12.938850
2506 22:50:12.938927
2507 22:50:12.942202 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2508 22:50:12.942295
2509 22:50:12.948948 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
2510 22:50:12.949049
2511 22:50:12.949130
2512 22:50:12.949210 Write Rank0 MR1 =0x56
2513 22:50:12.949282
2514 22:50:12.951843 best RODT dly(2T, 0.5T) = (2, 3)
2515 22:50:12.951933
2516 22:50:12.955268 best RODT dly(2T, 0.5T) = (2, 3)
2517 22:50:12.955393 ==
2518 22:50:12.962118 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2519 22:50:12.965171 fsp= 1, odt_onoff= 1, Byte mode= 0
2520 22:50:12.965260 ==
2521 22:50:12.968443 Start DQ dly to find pass range UseTestEngine =0
2522 22:50:12.971859 x-axis: bit #, y-axis: DQ dly (-127~63)
2523 22:50:12.974913 RX Vref Scan = 0
2524 22:50:12.978277 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2525 22:50:12.978373 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2526 22:50:12.981682 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2527 22:50:12.985224 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2528 22:50:12.988084 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2529 22:50:12.991445 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2530 22:50:12.994783 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2531 22:50:12.997862 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2532 22:50:13.001361 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2533 22:50:13.004673 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2534 22:50:13.004768 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2535 22:50:13.007712 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2536 22:50:13.010918 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2537 22:50:13.014215 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2538 22:50:13.017513 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2539 22:50:13.020867 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2540 22:50:13.023923 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2541 22:50:13.027371 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2542 22:50:13.030701 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2543 22:50:13.030801 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2544 22:50:13.034133 -6, [0] xxxxxxxx xxxxxxxo [MSB]
2545 22:50:13.037470 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2546 22:50:13.040467 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2547 22:50:13.043565 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2548 22:50:13.047007 -2, [0] xxxxxxxx ooxxxxxo [MSB]
2549 22:50:13.050292 -1, [0] xxxxxxxx ooxxxxxo [MSB]
2550 22:50:13.053316 0, [0] xxxoxxxx ooxxxxxo [MSB]
2551 22:50:13.053411 1, [0] xxooxxxx ooxxxxxo [MSB]
2552 22:50:13.056703 2, [0] xxooxxxo oooxxxxo [MSB]
2553 22:50:13.060276 3, [0] xxooxxxo ooooxxoo [MSB]
2554 22:50:13.063515 4, [0] xooooxxo oooooooo [MSB]
2555 22:50:13.066426 5, [0] oooooxoo oooooooo [MSB]
2556 22:50:13.069920 6, [0] oooooxoo oooooooo [MSB]
2557 22:50:13.070016 32, [0] oooooooo ooooooox [MSB]
2558 22:50:13.073536 33, [0] oooooooo ooooooox [MSB]
2559 22:50:13.076825 34, [0] oooooooo ooooooox [MSB]
2560 22:50:13.079861 35, [0] ooxooooo oxooooox [MSB]
2561 22:50:13.082801 36, [0] ooxxoooo oxooooox [MSB]
2562 22:50:13.086396 37, [0] ooxxoooo xxooooox [MSB]
2563 22:50:13.089288 38, [0] ooxxoooo xxooooox [MSB]
2564 22:50:13.092721 39, [0] oxxxooox xxoxooox [MSB]
2565 22:50:13.092816 40, [0] oxxxxoox xxxxxoox [MSB]
2566 22:50:13.096053 41, [0] xxxxxoxx xxxxxxxx [MSB]
2567 22:50:13.099773 42, [0] xxxxxoxx xxxxxxxx [MSB]
2568 22:50:13.102971 43, [0] xxxxxxxx xxxxxxxx [MSB]
2569 22:50:13.105846 iDelay=43, Bit 0, Center 22 (5 ~ 40) 36
2570 22:50:13.109831 iDelay=43, Bit 1, Center 21 (4 ~ 38) 35
2571 22:50:13.112575 iDelay=43, Bit 2, Center 17 (1 ~ 34) 34
2572 22:50:13.115631 iDelay=43, Bit 3, Center 17 (0 ~ 35) 36
2573 22:50:13.119163 iDelay=43, Bit 4, Center 21 (4 ~ 39) 36
2574 22:50:13.125511 iDelay=43, Bit 5, Center 24 (7 ~ 42) 36
2575 22:50:13.128840 iDelay=43, Bit 6, Center 22 (5 ~ 40) 36
2576 22:50:13.132279 iDelay=43, Bit 7, Center 20 (2 ~ 38) 37
2577 22:50:13.135833 iDelay=43, Bit 8, Center 17 (-2 ~ 36) 39
2578 22:50:13.138895 iDelay=43, Bit 9, Center 16 (-2 ~ 34) 37
2579 22:50:13.142372 iDelay=43, Bit 10, Center 20 (2 ~ 39) 38
2580 22:50:13.145160 iDelay=43, Bit 11, Center 20 (3 ~ 38) 36
2581 22:50:13.148471 iDelay=43, Bit 12, Center 21 (4 ~ 39) 36
2582 22:50:13.151530 iDelay=43, Bit 13, Center 22 (4 ~ 40) 37
2583 22:50:13.154987 iDelay=43, Bit 14, Center 21 (3 ~ 40) 38
2584 22:50:13.161515 iDelay=43, Bit 15, Center 13 (-4 ~ 31) 36
2585 22:50:13.161613 ==
2586 22:50:13.165185 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2587 22:50:13.168539 fsp= 1, odt_onoff= 1, Byte mode= 0
2588 22:50:13.168635 ==
2589 22:50:13.171153 DQS Delay:
2590 22:50:13.171262 DQS0 = 0, DQS1 = 0
2591 22:50:13.171344 DQM Delay:
2592 22:50:13.174528 DQM0 = 20, DQM1 = 18
2593 22:50:13.174624 DQ Delay:
2594 22:50:13.178055 DQ0 =22, DQ1 =21, DQ2 =17, DQ3 =17
2595 22:50:13.181115 DQ4 =21, DQ5 =24, DQ6 =22, DQ7 =20
2596 22:50:13.184176 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =20
2597 22:50:13.187413 DQ12 =21, DQ13 =22, DQ14 =21, DQ15 =13
2598 22:50:13.187508
2599 22:50:13.187582
2600 22:50:13.191125 DramC Write-DBI off
2601 22:50:13.191223 ==
2602 22:50:13.194409 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2603 22:50:13.197207 fsp= 1, odt_onoff= 1, Byte mode= 0
2604 22:50:13.200539 ==
2605 22:50:13.203999 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2606 22:50:13.204093
2607 22:50:13.207422 Begin, DQ Scan Range 926~1182
2608 22:50:13.207515
2609 22:50:13.207589
2610 22:50:13.207657 TX Vref Scan disable
2611 22:50:13.210737 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2612 22:50:13.216962 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2613 22:50:13.220238 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2614 22:50:13.223808 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2615 22:50:13.227186 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2616 22:50:13.230045 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2617 22:50:13.233422 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2618 22:50:13.236834 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2619 22:50:13.240161 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2620 22:50:13.243073 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2621 22:50:13.246435 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2622 22:50:13.250034 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2623 22:50:13.253269 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2624 22:50:13.256712 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2625 22:50:13.262806 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2626 22:50:13.266176 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2627 22:50:13.269300 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2628 22:50:13.272695 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2629 22:50:13.276194 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2630 22:50:13.279673 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2631 22:50:13.282475 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2632 22:50:13.285745 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2633 22:50:13.289147 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2634 22:50:13.292538 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2635 22:50:13.295846 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2636 22:50:13.298697 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2637 22:50:13.305670 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2638 22:50:13.308466 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2639 22:50:13.311992 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2640 22:50:13.315561 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2641 22:50:13.318507 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2642 22:50:13.321695 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2643 22:50:13.325539 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2644 22:50:13.328869 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2645 22:50:13.331438 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2646 22:50:13.334888 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2647 22:50:13.337872 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2648 22:50:13.341407 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2649 22:50:13.344534 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2650 22:50:13.347894 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2651 22:50:13.351173 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2652 22:50:13.357661 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2653 22:50:13.361174 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2654 22:50:13.364466 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2655 22:50:13.367561 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2656 22:50:13.371225 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2657 22:50:13.373996 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2658 22:50:13.377692 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2659 22:50:13.381001 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2660 22:50:13.384420 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB]
2661 22:50:13.387135 976 |3 6 16|[0] xxxxxxxx ooxxxxxo [MSB]
2662 22:50:13.390310 977 |3 6 17|[0] xxxxxxxx oooxoxoo [MSB]
2663 22:50:13.393586 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2664 22:50:13.397205 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2665 22:50:13.400080 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
2666 22:50:13.406683 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
2667 22:50:13.410062 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
2668 22:50:13.413734 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
2669 22:50:13.417017 984 |3 6 24|[0] xooooxoo oooooooo [MSB]
2670 22:50:13.419818 992 |3 6 32|[0] oooooooo ooooooox [MSB]
2671 22:50:13.423090 993 |3 6 33|[0] oooooooo oxooooox [MSB]
2672 22:50:13.426461 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2673 22:50:13.429744 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2674 22:50:13.436644 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2675 22:50:13.439671 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2676 22:50:13.442776 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2677 22:50:13.446294 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2678 22:50:13.449538 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
2679 22:50:13.452929 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
2680 22:50:13.455921 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
2681 22:50:13.459552 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
2682 22:50:13.462748 1004 |3 6 44|[0] ooxxoooo xxxxxxxx [MSB]
2683 22:50:13.465715 1005 |3 6 45|[0] ooxxoooo xxxxxxxx [MSB]
2684 22:50:13.472358 1006 |3 6 46|[0] oxxxxoxx xxxxxxxx [MSB]
2685 22:50:13.475459 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2686 22:50:13.478638 Byte0, DQ PI dly=993, DQM PI dly= 993
2687 22:50:13.482186 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 33)
2688 22:50:13.482294
2689 22:50:13.485398 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 33)
2690 22:50:13.485493
2691 22:50:13.489071 Byte1, DQ PI dly=984, DQM PI dly= 984
2692 22:50:13.495137 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
2693 22:50:13.495263
2694 22:50:13.498291 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
2695 22:50:13.498386
2696 22:50:13.498460 ==
2697 22:50:13.504766 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2698 22:50:13.508211 fsp= 1, odt_onoff= 1, Byte mode= 0
2699 22:50:13.508311 ==
2700 22:50:13.511808 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2701 22:50:13.511902
2702 22:50:13.515127 Begin, DQ Scan Range 960~1024
2703 22:50:13.517909 Write Rank0 MR14 =0x0
2704 22:50:13.525081
2705 22:50:13.528447 CH=1, VrefRange= 0, VrefLevel = 0
2706 22:50:13.531334 TX Bit0 (987~1001) 15 994, Bit8 (977~991) 15 984,
2707 22:50:13.534898 TX Bit1 (985~1000) 16 992, Bit9 (977~989) 13 983,
2708 22:50:13.541237 TX Bit2 (984~998) 15 991, Bit10 (979~992) 14 985,
2709 22:50:13.544438 TX Bit3 (981~996) 16 988, Bit11 (982~992) 11 987,
2710 22:50:13.547772 TX Bit4 (985~999) 15 992, Bit12 (981~992) 12 986,
2711 22:50:13.554311 TX Bit5 (986~1001) 16 993, Bit13 (982~994) 13 988,
2712 22:50:13.557586 TX Bit6 (985~1000) 16 992, Bit14 (980~992) 13 986,
2713 22:50:13.564042 TX Bit7 (985~999) 15 992, Bit15 (976~984) 9 980,
2714 22:50:13.564136
2715 22:50:13.564210 Write Rank0 MR14 =0x2
2716 22:50:13.573816
2717 22:50:13.573908 CH=1, VrefRange= 0, VrefLevel = 2
2718 22:50:13.580384 TX Bit0 (986~1002) 17 994, Bit8 (977~991) 15 984,
2719 22:50:13.583839 TX Bit1 (985~1001) 17 993, Bit9 (977~990) 14 983,
2720 22:50:13.590470 TX Bit2 (984~998) 15 991, Bit10 (978~993) 16 985,
2721 22:50:13.593489 TX Bit3 (981~997) 17 989, Bit11 (981~992) 12 986,
2722 22:50:13.600242 TX Bit4 (984~1000) 17 992, Bit12 (979~993) 15 986,
2723 22:50:13.602999 TX Bit5 (986~1002) 17 994, Bit13 (982~994) 13 988,
2724 22:50:13.606460 TX Bit6 (985~1000) 16 992, Bit14 (979~992) 14 985,
2725 22:50:13.613170 TX Bit7 (985~1000) 16 992, Bit15 (976~986) 11 981,
2726 22:50:13.613265
2727 22:50:13.613338 Write Rank0 MR14 =0x4
2728 22:50:13.622851
2729 22:50:13.626297 CH=1, VrefRange= 0, VrefLevel = 4
2730 22:50:13.629493 TX Bit0 (986~1003) 18 994, Bit8 (977~992) 16 984,
2731 22:50:13.632630 TX Bit1 (985~1002) 18 993, Bit9 (976~990) 15 983,
2732 22:50:13.639568 TX Bit2 (983~999) 17 991, Bit10 (978~994) 17 986,
2733 22:50:13.642960 TX Bit3 (980~997) 18 988, Bit11 (981~993) 13 987,
2734 22:50:13.649374 TX Bit4 (984~1001) 18 992, Bit12 (979~993) 15 986,
2735 22:50:13.652777 TX Bit5 (986~1002) 17 994, Bit13 (981~995) 15 988,
2736 22:50:13.655669 TX Bit6 (985~1001) 17 993, Bit14 (979~993) 15 986,
2737 22:50:13.662337 TX Bit7 (985~1001) 17 993, Bit15 (976~986) 11 981,
2738 22:50:13.662431
2739 22:50:13.662504 Write Rank0 MR14 =0x6
2740 22:50:13.672657
2741 22:50:13.672781 CH=1, VrefRange= 0, VrefLevel = 6
2742 22:50:13.679133 TX Bit0 (986~1004) 19 995, Bit8 (977~992) 16 984,
2743 22:50:13.682463 TX Bit1 (984~1002) 19 993, Bit9 (976~991) 16 983,
2744 22:50:13.688592 TX Bit2 (983~1000) 18 991, Bit10 (978~994) 17 986,
2745 22:50:13.692397 TX Bit3 (980~998) 19 989, Bit11 (980~994) 15 987,
2746 22:50:13.698781 TX Bit4 (984~1001) 18 992, Bit12 (979~994) 16 986,
2747 22:50:13.701762 TX Bit5 (986~1003) 18 994, Bit13 (981~997) 17 989,
2748 22:50:13.705056 TX Bit6 (985~1002) 18 993, Bit14 (978~994) 17 986,
2749 22:50:13.711744 TX Bit7 (985~1001) 17 993, Bit15 (975~988) 14 981,
2750 22:50:13.711838
2751 22:50:13.711912 Write Rank0 MR14 =0x8
2752 22:50:13.722109
2753 22:50:13.722202 CH=1, VrefRange= 0, VrefLevel = 8
2754 22:50:13.728435 TX Bit0 (986~1005) 20 995, Bit8 (976~993) 18 984,
2755 22:50:13.731769 TX Bit1 (984~1003) 20 993, Bit9 (976~991) 16 983,
2756 22:50:13.738728 TX Bit2 (982~1000) 19 991, Bit10 (978~995) 18 986,
2757 22:50:13.741697 TX Bit3 (980~998) 19 989, Bit11 (979~995) 17 987,
2758 22:50:13.748131 TX Bit4 (984~1002) 19 993, Bit12 (978~995) 18 986,
2759 22:50:13.751927 TX Bit5 (985~1004) 20 994, Bit13 (980~997) 18 988,
2760 22:50:13.754890 TX Bit6 (985~1002) 18 993, Bit14 (978~994) 17 986,
2761 22:50:13.761155 TX Bit7 (984~1002) 19 993, Bit15 (975~989) 15 982,
2762 22:50:13.761253
2763 22:50:13.761327 Write Rank0 MR14 =0xa
2764 22:50:13.771699
2765 22:50:13.774950 CH=1, VrefRange= 0, VrefLevel = 10
2766 22:50:13.778129 TX Bit0 (985~1005) 21 995, Bit8 (976~993) 18 984,
2767 22:50:13.781683 TX Bit1 (984~1005) 22 994, Bit9 (976~991) 16 983,
2768 22:50:13.788098 TX Bit2 (983~1001) 19 992, Bit10 (977~996) 20 986,
2769 22:50:13.791358 TX Bit3 (979~999) 21 989, Bit11 (979~995) 17 987,
2770 22:50:13.797613 TX Bit4 (984~1003) 20 993, Bit12 (978~995) 18 986,
2771 22:50:13.801350 TX Bit5 (985~1005) 21 995, Bit13 (979~997) 19 988,
2772 22:50:13.804286 TX Bit6 (985~1003) 19 994, Bit14 (978~995) 18 986,
2773 22:50:13.810851 TX Bit7 (984~1003) 20 993, Bit15 (974~990) 17 982,
2774 22:50:13.810946
2775 22:50:13.811022 Write Rank0 MR14 =0xc
2776 22:50:13.821365
2777 22:50:13.824633 CH=1, VrefRange= 0, VrefLevel = 12
2778 22:50:13.828392 TX Bit0 (985~1005) 21 995, Bit8 (976~994) 19 985,
2779 22:50:13.830937 TX Bit1 (984~1005) 22 994, Bit9 (975~991) 17 983,
2780 22:50:13.837549 TX Bit2 (982~1002) 21 992, Bit10 (977~997) 21 987,
2781 22:50:13.840705 TX Bit3 (979~999) 21 989, Bit11 (979~996) 18 987,
2782 22:50:13.847728 TX Bit4 (983~1004) 22 993, Bit12 (978~997) 20 987,
2783 22:50:13.850700 TX Bit5 (985~1005) 21 995, Bit13 (979~997) 19 988,
2784 22:50:13.854132 TX Bit6 (984~1004) 21 994, Bit14 (977~996) 20 986,
2785 22:50:13.860942 TX Bit7 (984~1004) 21 994, Bit15 (975~990) 16 982,
2786 22:50:13.861036
2787 22:50:13.861109 Write Rank0 MR14 =0xe
2788 22:50:13.871428
2789 22:50:13.874917 CH=1, VrefRange= 0, VrefLevel = 14
2790 22:50:13.877922 TX Bit0 (985~1006) 22 995, Bit8 (975~994) 20 984,
2791 22:50:13.880982 TX Bit1 (984~1005) 22 994, Bit9 (975~992) 18 983,
2792 22:50:13.888839 TX Bit2 (982~1002) 21 992, Bit10 (977~997) 21 987,
2793 22:50:13.890775 TX Bit3 (979~999) 21 989, Bit11 (978~997) 20 987,
2794 22:50:13.897171 TX Bit4 (983~1004) 22 993, Bit12 (977~998) 22 987,
2795 22:50:13.900565 TX Bit5 (985~1005) 21 995, Bit13 (979~998) 20 988,
2796 22:50:13.903883 TX Bit6 (984~1005) 22 994, Bit14 (977~997) 21 987,
2797 22:50:13.910479 TX Bit7 (984~1004) 21 994, Bit15 (972~991) 20 981,
2798 22:50:13.910574
2799 22:50:13.913983 Write Rank0 MR14 =0x10
2800 22:50:13.921670
2801 22:50:13.924301 CH=1, VrefRange= 0, VrefLevel = 16
2802 22:50:13.927686 TX Bit0 (985~1006) 22 995, Bit8 (975~995) 21 985,
2803 22:50:13.931130 TX Bit1 (983~1005) 23 994, Bit9 (975~992) 18 983,
2804 22:50:13.937640 TX Bit2 (981~1003) 23 992, Bit10 (977~998) 22 987,
2805 22:50:13.940656 TX Bit3 (978~1000) 23 989, Bit11 (978~998) 21 988,
2806 22:50:13.947422 TX Bit4 (983~1005) 23 994, Bit12 (977~998) 22 987,
2807 22:50:13.950479 TX Bit5 (985~1006) 22 995, Bit13 (978~998) 21 988,
2808 22:50:13.953872 TX Bit6 (984~1005) 22 994, Bit14 (977~997) 21 987,
2809 22:50:13.960539 TX Bit7 (984~1005) 22 994, Bit15 (972~991) 20 981,
2810 22:50:13.960633
2811 22:50:13.963837 Write Rank0 MR14 =0x12
2812 22:50:13.971622
2813 22:50:13.974455 CH=1, VrefRange= 0, VrefLevel = 18
2814 22:50:13.977816 TX Bit0 (985~1006) 22 995, Bit8 (975~995) 21 985,
2815 22:50:13.981278 TX Bit1 (984~1005) 22 994, Bit9 (975~993) 19 984,
2816 22:50:13.988225 TX Bit2 (981~1003) 23 992, Bit10 (977~998) 22 987,
2817 22:50:13.991261 TX Bit3 (978~1000) 23 989, Bit11 (978~998) 21 988,
2818 22:50:13.997566 TX Bit4 (983~1005) 23 994, Bit12 (977~998) 22 987,
2819 22:50:14.000926 TX Bit5 (984~1006) 23 995, Bit13 (978~999) 22 988,
2820 22:50:14.003872 TX Bit6 (984~1005) 22 994, Bit14 (977~998) 22 987,
2821 22:50:14.010362 TX Bit7 (984~1005) 22 994, Bit15 (971~991) 21 981,
2822 22:50:14.010498
2823 22:50:14.013822 Write Rank0 MR14 =0x14
2824 22:50:14.021163
2825 22:50:14.024629 CH=1, VrefRange= 0, VrefLevel = 20
2826 22:50:14.027918 TX Bit0 (985~1006) 22 995, Bit8 (975~996) 22 985,
2827 22:50:14.030965 TX Bit1 (983~1006) 24 994, Bit9 (974~993) 20 983,
2828 22:50:14.037956 TX Bit2 (982~1004) 23 993, Bit10 (976~998) 23 987,
2829 22:50:14.040796 TX Bit3 (978~1000) 23 989, Bit11 (977~998) 22 987,
2830 22:50:14.047418 TX Bit4 (983~1005) 23 994, Bit12 (977~999) 23 988,
2831 22:50:14.051127 TX Bit5 (984~1006) 23 995, Bit13 (978~999) 22 988,
2832 22:50:14.054027 TX Bit6 (984~1005) 22 994, Bit14 (977~998) 22 987,
2833 22:50:14.060766 TX Bit7 (984~1005) 22 994, Bit15 (972~991) 20 981,
2834 22:50:14.060865
2835 22:50:14.063545 Write Rank0 MR14 =0x16
2836 22:50:14.071854
2837 22:50:14.074755 CH=1, VrefRange= 0, VrefLevel = 22
2838 22:50:14.078567 TX Bit0 (984~1007) 24 995, Bit8 (975~997) 23 986,
2839 22:50:14.081313 TX Bit1 (983~1006) 24 994, Bit9 (974~994) 21 984,
2840 22:50:14.087971 TX Bit2 (980~1005) 26 992, Bit10 (976~998) 23 987,
2841 22:50:14.091542 TX Bit3 (978~1001) 24 989, Bit11 (977~999) 23 988,
2842 22:50:14.097737 TX Bit4 (982~1006) 25 994, Bit12 (977~999) 23 988,
2843 22:50:14.101061 TX Bit5 (984~1006) 23 995, Bit13 (977~999) 23 988,
2844 22:50:14.104298 TX Bit6 (983~1006) 24 994, Bit14 (977~998) 22 987,
2845 22:50:14.110906 TX Bit7 (983~1006) 24 994, Bit15 (971~991) 21 981,
2846 22:50:14.111039
2847 22:50:14.113783 Write Rank0 MR14 =0x18
2848 22:50:14.121871
2849 22:50:14.125327 CH=1, VrefRange= 0, VrefLevel = 24
2850 22:50:14.128504 TX Bit0 (984~1007) 24 995, Bit8 (974~998) 25 986,
2851 22:50:14.131631 TX Bit1 (982~1006) 25 994, Bit9 (974~994) 21 984,
2852 22:50:14.138465 TX Bit2 (980~1005) 26 992, Bit10 (976~999) 24 987,
2853 22:50:14.141684 TX Bit3 (977~1002) 26 989, Bit11 (977~999) 23 988,
2854 22:50:14.148184 TX Bit4 (982~1006) 25 994, Bit12 (976~999) 24 987,
2855 22:50:14.151206 TX Bit5 (984~1007) 24 995, Bit13 (977~999) 23 988,
2856 22:50:14.154731 TX Bit6 (983~1006) 24 994, Bit14 (977~999) 23 988,
2857 22:50:14.160961 TX Bit7 (983~1006) 24 994, Bit15 (971~992) 22 981,
2858 22:50:14.161055
2859 22:50:14.164120 Write Rank0 MR14 =0x1a
2860 22:50:14.172296
2861 22:50:14.175357 CH=1, VrefRange= 0, VrefLevel = 26
2862 22:50:14.178758 TX Bit0 (984~1007) 24 995, Bit8 (974~998) 25 986,
2863 22:50:14.181955 TX Bit1 (983~1006) 24 994, Bit9 (973~995) 23 984,
2864 22:50:14.188166 TX Bit2 (980~1005) 26 992, Bit10 (976~999) 24 987,
2865 22:50:14.191748 TX Bit3 (977~1002) 26 989, Bit11 (977~999) 23 988,
2866 22:50:14.198192 TX Bit4 (982~1006) 25 994, Bit12 (976~1000) 25 988,
2867 22:50:14.201265 TX Bit5 (984~1007) 24 995, Bit13 (977~1000) 24 988,
2868 22:50:14.205063 TX Bit6 (983~1006) 24 994, Bit14 (976~999) 24 987,
2869 22:50:14.211034 TX Bit7 (982~1006) 25 994, Bit15 (970~992) 23 981,
2870 22:50:14.211139
2871 22:50:14.214155 Write Rank0 MR14 =0x1c
2872 22:50:14.222511
2873 22:50:14.225509 CH=1, VrefRange= 0, VrefLevel = 28
2874 22:50:14.228804 TX Bit0 (984~1008) 25 996, Bit8 (973~998) 26 985,
2875 22:50:14.232436 TX Bit1 (982~1006) 25 994, Bit9 (972~996) 25 984,
2876 22:50:14.238952 TX Bit2 (979~1005) 27 992, Bit10 (975~999) 25 987,
2877 22:50:14.242017 TX Bit3 (977~1003) 27 990, Bit11 (977~1000) 24 988,
2878 22:50:14.248741 TX Bit4 (982~1006) 25 994, Bit12 (976~999) 24 987,
2879 22:50:14.251644 TX Bit5 (984~1007) 24 995, Bit13 (977~1000) 24 988,
2880 22:50:14.255169 TX Bit6 (983~1006) 24 994, Bit14 (976~999) 24 987,
2881 22:50:14.261507 TX Bit7 (983~1006) 24 994, Bit15 (970~992) 23 981,
2882 22:50:14.261600
2883 22:50:14.265025 Write Rank0 MR14 =0x1e
2884 22:50:14.273089
2885 22:50:14.276197 CH=1, VrefRange= 0, VrefLevel = 30
2886 22:50:14.279670 TX Bit0 (984~1007) 24 995, Bit8 (973~997) 25 985,
2887 22:50:14.282627 TX Bit1 (982~1007) 26 994, Bit9 (972~996) 25 984,
2888 22:50:14.289302 TX Bit2 (980~1006) 27 993, Bit10 (976~999) 24 987,
2889 22:50:14.292672 TX Bit3 (977~1003) 27 990, Bit11 (977~1000) 24 988,
2890 22:50:14.299330 TX Bit4 (982~1006) 25 994, Bit12 (976~999) 24 987,
2891 22:50:14.302163 TX Bit5 (983~1007) 25 995, Bit13 (976~1000) 25 988,
2892 22:50:14.305603 TX Bit6 (982~1007) 26 994, Bit14 (976~999) 24 987,
2893 22:50:14.312642 TX Bit7 (982~1006) 25 994, Bit15 (970~993) 24 981,
2894 22:50:14.312739
2895 22:50:14.315479 Write Rank0 MR14 =0x20
2896 22:50:14.323241
2897 22:50:14.326488 CH=1, VrefRange= 0, VrefLevel = 32
2898 22:50:14.330307 TX Bit0 (983~1008) 26 995, Bit8 (974~997) 24 985,
2899 22:50:14.333293 TX Bit1 (982~1007) 26 994, Bit9 (972~995) 24 983,
2900 22:50:14.340215 TX Bit2 (979~1005) 27 992, Bit10 (975~999) 25 987,
2901 22:50:14.343327 TX Bit3 (977~1002) 26 989, Bit11 (976~1000) 25 988,
2902 22:50:14.349643 TX Bit4 (983~1006) 24 994, Bit12 (976~999) 24 987,
2903 22:50:14.352754 TX Bit5 (983~1007) 25 995, Bit13 (976~1000) 25 988,
2904 22:50:14.356716 TX Bit6 (982~1007) 26 994, Bit14 (976~999) 24 987,
2905 22:50:14.363015 TX Bit7 (982~1006) 25 994, Bit15 (969~993) 25 981,
2906 22:50:14.363112
2907 22:50:14.365595 Write Rank0 MR14 =0x22
2908 22:50:14.373973
2909 22:50:14.376984 CH=1, VrefRange= 0, VrefLevel = 34
2910 22:50:14.380810 TX Bit0 (983~1008) 26 995, Bit8 (974~997) 24 985,
2911 22:50:14.384028 TX Bit1 (982~1007) 26 994, Bit9 (972~995) 24 983,
2912 22:50:14.389964 TX Bit2 (979~1005) 27 992, Bit10 (975~999) 25 987,
2913 22:50:14.393261 TX Bit3 (977~1002) 26 989, Bit11 (976~1000) 25 988,
2914 22:50:14.399699 TX Bit4 (983~1006) 24 994, Bit12 (976~999) 24 987,
2915 22:50:14.403198 TX Bit5 (983~1007) 25 995, Bit13 (976~1000) 25 988,
2916 22:50:14.406243 TX Bit6 (982~1007) 26 994, Bit14 (976~999) 24 987,
2917 22:50:14.413401 TX Bit7 (982~1006) 25 994, Bit15 (969~993) 25 981,
2918 22:50:14.413504
2919 22:50:14.416310 Write Rank0 MR14 =0x24
2920 22:50:14.424169
2921 22:50:14.427790 CH=1, VrefRange= 0, VrefLevel = 36
2922 22:50:14.430492 TX Bit0 (983~1008) 26 995, Bit8 (974~997) 24 985,
2923 22:50:14.433831 TX Bit1 (982~1007) 26 994, Bit9 (972~995) 24 983,
2924 22:50:14.440378 TX Bit2 (979~1005) 27 992, Bit10 (975~999) 25 987,
2925 22:50:14.443818 TX Bit3 (977~1002) 26 989, Bit11 (976~1000) 25 988,
2926 22:50:14.450519 TX Bit4 (983~1006) 24 994, Bit12 (976~999) 24 987,
2927 22:50:14.453950 TX Bit5 (983~1007) 25 995, Bit13 (976~1000) 25 988,
2928 22:50:14.457101 TX Bit6 (982~1007) 26 994, Bit14 (976~999) 24 987,
2929 22:50:14.463732 TX Bit7 (982~1006) 25 994, Bit15 (969~993) 25 981,
2930 22:50:14.463826
2931 22:50:14.466517 Write Rank0 MR14 =0x26
2932 22:50:14.474852
2933 22:50:14.477658 CH=1, VrefRange= 0, VrefLevel = 38
2934 22:50:14.481421 TX Bit0 (983~1008) 26 995, Bit8 (974~997) 24 985,
2935 22:50:14.484369 TX Bit1 (982~1007) 26 994, Bit9 (972~995) 24 983,
2936 22:50:14.490684 TX Bit2 (979~1005) 27 992, Bit10 (975~999) 25 987,
2937 22:50:14.494037 TX Bit3 (977~1002) 26 989, Bit11 (976~1000) 25 988,
2938 22:50:14.500588 TX Bit4 (983~1006) 24 994, Bit12 (976~999) 24 987,
2939 22:50:14.503797 TX Bit5 (983~1007) 25 995, Bit13 (976~1000) 25 988,
2940 22:50:14.507239 TX Bit6 (982~1007) 26 994, Bit14 (976~999) 24 987,
2941 22:50:14.514031 TX Bit7 (982~1006) 25 994, Bit15 (969~993) 25 981,
2942 22:50:14.514130
2943 22:50:14.514210
2944 22:50:14.517111 TX Vref found, early break! 378< 380
2945 22:50:14.520473 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2946 22:50:14.523518 u1DelayCellOfst[0]=7 cells (6 PI)
2947 22:50:14.526873 u1DelayCellOfst[1]=6 cells (5 PI)
2948 22:50:14.530042 u1DelayCellOfst[2]=3 cells (3 PI)
2949 22:50:14.533525 u1DelayCellOfst[3]=0 cells (0 PI)
2950 22:50:14.537120 u1DelayCellOfst[4]=6 cells (5 PI)
2951 22:50:14.539959 u1DelayCellOfst[5]=7 cells (6 PI)
2952 22:50:14.543120 u1DelayCellOfst[6]=6 cells (5 PI)
2953 22:50:14.546611 u1DelayCellOfst[7]=6 cells (5 PI)
2954 22:50:14.549995 Byte0, DQ PI dly=989, DQM PI dly= 992
2955 22:50:14.553482 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
2956 22:50:14.553576
2957 22:50:14.559736 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
2958 22:50:14.559830
2959 22:50:14.559904 u1DelayCellOfst[8]=5 cells (4 PI)
2960 22:50:14.562888 u1DelayCellOfst[9]=2 cells (2 PI)
2961 22:50:14.566515 u1DelayCellOfst[10]=7 cells (6 PI)
2962 22:50:14.569626 u1DelayCellOfst[11]=9 cells (7 PI)
2963 22:50:14.573011 u1DelayCellOfst[12]=7 cells (6 PI)
2964 22:50:14.575978 u1DelayCellOfst[13]=9 cells (7 PI)
2965 22:50:14.579456 u1DelayCellOfst[14]=7 cells (6 PI)
2966 22:50:14.582964 u1DelayCellOfst[15]=0 cells (0 PI)
2967 22:50:14.585790 Byte1, DQ PI dly=981, DQM PI dly= 984
2968 22:50:14.589493 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
2969 22:50:14.592534
2970 22:50:14.595677 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
2971 22:50:14.595770
2972 22:50:14.595843 Write Rank0 MR14 =0x20
2973 22:50:14.598975
2974 22:50:14.599069 Final TX Range 0 Vref 32
2975 22:50:14.599143
2976 22:50:14.605509 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2977 22:50:14.605604
2978 22:50:14.612502 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2979 22:50:14.618423 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2980 22:50:14.628554 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2981 22:50:14.628648 Write Rank0 MR3 =0xb0
2982 22:50:14.631905 DramC Write-DBI on
2983 22:50:14.631998 ==
2984 22:50:14.635141 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2985 22:50:14.638737 fsp= 1, odt_onoff= 1, Byte mode= 0
2986 22:50:14.638830 ==
2987 22:50:14.644915 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2988 22:50:14.645009
2989 22:50:14.645082 Begin, DQ Scan Range 704~768
2990 22:50:14.648108
2991 22:50:14.648200
2992 22:50:14.648273 TX Vref Scan disable
2993 22:50:14.651661 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2994 22:50:14.654453 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2995 22:50:14.658027 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2996 22:50:14.660991 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2997 22:50:14.664840 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2998 22:50:14.670707 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2999 22:50:14.674506 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3000 22:50:14.677665 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3001 22:50:14.680955 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3002 22:50:14.683857 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3003 22:50:14.687473 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3004 22:50:14.690988 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3005 22:50:14.693722 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3006 22:50:14.697233 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3007 22:50:14.700588 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3008 22:50:14.704310 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3009 22:50:14.706967 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3010 22:50:14.710106 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3011 22:50:14.713979 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3012 22:50:14.720079 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3013 22:50:14.723537 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3014 22:50:14.726423 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3015 22:50:14.733535 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3016 22:50:14.736854 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3017 22:50:14.739759 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3018 22:50:14.743111 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3019 22:50:14.746370 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3020 22:50:14.749565 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3021 22:50:14.753225 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3022 22:50:14.756121 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3023 22:50:14.759337 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3024 22:50:14.762795 752 |2 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3025 22:50:14.766087 Byte0, DQ PI dly=738, DQM PI dly= 738
3026 22:50:14.772573 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 34)
3027 22:50:14.772662
3028 22:50:14.775756 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 34)
3029 22:50:14.775852
3030 22:50:14.779122 Byte1, DQ PI dly=729, DQM PI dly= 729
3031 22:50:14.782159 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25)
3032 22:50:14.782246
3033 22:50:14.788759 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25)
3034 22:50:14.788853
3035 22:50:14.795600 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3036 22:50:14.802163 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3037 22:50:14.808583 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3038 22:50:14.811877 Write Rank0 MR3 =0x30
3039 22:50:14.811979 DramC Write-DBI off
3040 22:50:14.812057
3041 22:50:14.815008 [DATLAT]
3042 22:50:14.818129 Freq=1600, CH1 RK0, use_rxtx_scan=0
3043 22:50:14.818220
3044 22:50:14.818294 DATLAT Default: 0xf
3045 22:50:14.821500 7, 0xFFFF, sum=0
3046 22:50:14.821592 8, 0xFFFF, sum=0
3047 22:50:14.825264 9, 0xFFFF, sum=0
3048 22:50:14.825353 10, 0xFFFF, sum=0
3049 22:50:14.828317 11, 0xFFFF, sum=0
3050 22:50:14.828400 12, 0xFFFF, sum=0
3051 22:50:14.831647 13, 0xFFFF, sum=0
3052 22:50:14.831741 14, 0x0, sum=1
3053 22:50:14.831817 15, 0x0, sum=2
3054 22:50:14.834791 16, 0x0, sum=3
3055 22:50:14.834885 17, 0x0, sum=4
3056 22:50:14.841177 pattern=2 first_step=14 total pass=5 best_step=16
3057 22:50:14.841271 ==
3058 22:50:14.844479 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3059 22:50:14.847633 fsp= 1, odt_onoff= 1, Byte mode= 0
3060 22:50:14.847717 ==
3061 22:50:14.854352 Start DQ dly to find pass range UseTestEngine =1
3062 22:50:14.857251 x-axis: bit #, y-axis: DQ dly (-127~63)
3063 22:50:14.857342 RX Vref Scan = 1
3064 22:50:14.965771
3065 22:50:14.965915 RX Vref found, early break!
3066 22:50:14.965993
3067 22:50:14.971743 Final RX Vref 11, apply to both rank0 and 1
3068 22:50:14.971847 ==
3069 22:50:14.975246 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3070 22:50:14.978523 fsp= 1, odt_onoff= 1, Byte mode= 0
3071 22:50:14.978611 ==
3072 22:50:14.981500 DQS Delay:
3073 22:50:14.981585 DQS0 = 0, DQS1 = 0
3074 22:50:14.981660 DQM Delay:
3075 22:50:14.984733 DQM0 = 20, DQM1 = 18
3076 22:50:14.984820 DQ Delay:
3077 22:50:14.988208 DQ0 =21, DQ1 =21, DQ2 =18, DQ3 =16
3078 22:50:14.991202 DQ4 =20, DQ5 =23, DQ6 =22, DQ7 =19
3079 22:50:14.994844 DQ8 =17, DQ9 =15, DQ10 =19, DQ11 =20
3080 22:50:14.997938 DQ12 =20, DQ13 =21, DQ14 =20, DQ15 =12
3081 22:50:14.998033
3082 22:50:14.998109
3083 22:50:14.998182
3084 22:50:15.001266 [DramC_TX_OE_Calibration] TA2
3085 22:50:15.004473 Original DQ_B0 (3 6) =30, OEN = 27
3086 22:50:15.007916 Original DQ_B1 (3 6) =30, OEN = 27
3087 22:50:15.011181 23, 0x0, End_B0=23 End_B1=23
3088 22:50:15.014810 24, 0x0, End_B0=24 End_B1=24
3089 22:50:15.014896 25, 0x0, End_B0=25 End_B1=25
3090 22:50:15.018063 26, 0x0, End_B0=26 End_B1=26
3091 22:50:15.020899 27, 0x0, End_B0=27 End_B1=27
3092 22:50:15.024359 28, 0x0, End_B0=28 End_B1=28
3093 22:50:15.027724 29, 0x0, End_B0=29 End_B1=29
3094 22:50:15.027821 30, 0x0, End_B0=30 End_B1=30
3095 22:50:15.031143 31, 0xFFFF, End_B0=30 End_B1=30
3096 22:50:15.037382 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3097 22:50:15.044199 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3098 22:50:15.044288
3099 22:50:15.044375
3100 22:50:15.044445 Write Rank0 MR23 =0x3f
3101 22:50:15.047439 [DQSOSC]
3102 22:50:15.053828 [DQSOSCAuto] RK0, (LSB)MR18= 0xb9b9, (MSB)MR19= 0x202, tDQSOscB0 = 451 ps tDQSOscB1 = 451 ps
3103 22:50:15.060498 CH1_RK0: MR19=0x202, MR18=0xB9B9, DQSOSC=451, MR23=63, INC=12, DEC=18
3104 22:50:15.063838 Write Rank0 MR23 =0x3f
3105 22:50:15.063933 [DQSOSC]
3106 22:50:15.070131 [DQSOSCAuto] RK0, (LSB)MR18= 0xb9b9, (MSB)MR19= 0x202, tDQSOscB0 = 451 ps tDQSOscB1 = 451 ps
3107 22:50:15.073087 CH1 RK0: MR19=202, MR18=B9B9
3108 22:50:15.076476 [RankSwap] Rank num 2, (Multi 1), Rank 1
3109 22:50:15.079919 Write Rank0 MR2 =0xad
3110 22:50:15.080017 [Write Leveling]
3111 22:50:15.082961 delay byte0 byte1 byte2 byte3
3112 22:50:15.083048
3113 22:50:15.086292 10 0 0
3114 22:50:15.086385 11 0 0
3115 22:50:15.089577 12 0 0
3116 22:50:15.089662 13 0 0
3117 22:50:15.089750 14 0 0
3118 22:50:15.093037 15 0 0
3119 22:50:15.093130 16 0 0
3120 22:50:15.096377 17 0 0
3121 22:50:15.096466 18 0 0
3122 22:50:15.096541 19 0 0
3123 22:50:15.099166 20 0 0
3124 22:50:15.099264 21 0 0
3125 22:50:15.102642 22 0 0
3126 22:50:15.102733 23 0 0
3127 22:50:15.106132 24 0 0
3128 22:50:15.106231 25 0 0
3129 22:50:15.106305 26 0 0
3130 22:50:15.109303 27 0 0
3131 22:50:15.109395 28 0 0
3132 22:50:15.112712 29 0 0
3133 22:50:15.112805 30 0 ff
3134 22:50:15.116034 31 0 ff
3135 22:50:15.116128 32 0 ff
3136 22:50:15.116204 33 0 ff
3137 22:50:15.118984 34 0 ff
3138 22:50:15.119076 35 ff ff
3139 22:50:15.122452 36 ff ff
3140 22:50:15.122543 37 ff ff
3141 22:50:15.125515 38 ff ff
3142 22:50:15.125605 39 ff ff
3143 22:50:15.128700 40 ff ff
3144 22:50:15.128794 41 ff ff
3145 22:50:15.132121 pass bytecount = 0xff (0xff: all bytes pass)
3146 22:50:15.135636
3147 22:50:15.135733 DQS0 dly: 35
3148 22:50:15.135807 DQS1 dly: 30
3149 22:50:15.138773 Write Rank0 MR2 =0x2d
3150 22:50:15.142588 [RankSwap] Rank num 2, (Multi 1), Rank 0
3151 22:50:15.145195 Write Rank1 MR1 =0xd6
3152 22:50:15.145279 [Gating]
3153 22:50:15.145353 ==
3154 22:50:15.148493 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3155 22:50:15.151633 fsp= 1, odt_onoff= 1, Byte mode= 0
3156 22:50:15.154925 ==
3157 22:50:15.158597 3 1 0 |2c2b 3636 |(11 11)(10 10) |(1 1)(0 0)| 0
3158 22:50:15.161426 3 1 4 |2c2b 3636 |(11 11)(11 11) |(1 1)(0 0)| 0
3159 22:50:15.168071 3 1 8 |2c2b 3635 |(11 11)(11 11) |(1 1)(1 1)| 0
3160 22:50:15.171083 3 1 12 |2c2b b0b |(11 11)(11 11) |(0 0)(0 0)| 0
3161 22:50:15.174510 3 1 16 |2c2b 3636 |(11 11)(11 11) |(1 1)(0 0)| 0
3162 22:50:15.178057 3 1 20 |2c2b 3636 |(11 11)(0 0) |(1 0)(1 1)| 0
3163 22:50:15.184415 3 1 24 |2c2b 3434 |(11 11)(11 11) |(1 0)(1 1)| 0
3164 22:50:15.187940 3 1 28 |2c2b 1c1b |(11 11)(11 11) |(1 0)(1 1)| 0
3165 22:50:15.191017 3 2 0 |2c2b 3434 |(11 11)(11 11) |(1 0)(0 1)| 0
3166 22:50:15.197643 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
3167 22:50:15.200930 3 2 8 |2c2b 808 |(11 11)(11 11) |(1 0)(0 1)| 0
3168 22:50:15.204315 3 2 12 |2c2b 3434 |(11 11)(0 0) |(1 0)(0 1)| 0
3169 22:50:15.210605 3 2 16 |2c2c 3534 |(11 0)(11 11) |(0 0)(0 1)| 0
3170 22:50:15.213998 3 2 20 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
3171 22:50:15.217026 3 2 24 |3534 e0e |(11 11)(11 11) |(0 0)(0 1)| 0
3172 22:50:15.224047 3 2 28 |3534 3c3c |(11 11)(11 11) |(0 0)(1 1)| 0
3173 22:50:15.227131 3 3 0 |3534 3d3d |(11 11)(0 0) |(0 0)(1 1)| 0
3174 22:50:15.230281 3 3 4 |3534 3c3c |(11 11)(11 11) |(0 0)(1 1)| 0
3175 22:50:15.236596 3 3 8 |3534 3a3a |(11 11)(10 10) |(0 0)(1 1)| 0
3176 22:50:15.239777 3 3 12 |3534 3b3b |(11 11)(11 11) |(0 0)(1 1)| 0
3177 22:50:15.243165 3 3 16 |3534 3b3a |(11 11)(11 11) |(1 1)(1 1)| 0
3178 22:50:15.250100 3 3 20 |3534 3b3b |(11 11)(11 11) |(1 1)(1 1)| 0
3179 22:50:15.252976 3 3 24 |3534 0 |(11 11)(11 11) |(1 1)(1 1)| 0
3180 22:50:15.256359 [Byte 0] Lead/lag falling Transition (3, 3, 24)
3181 22:50:15.259728 3 3 28 |3534 201 |(11 11)(11 11) |(0 1)(1 1)| 0
3182 22:50:15.266281 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3183 22:50:15.269415 [Byte 1] Lead/lag falling Transition (3, 4, 0)
3184 22:50:15.272793 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3185 22:50:15.279198 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3186 22:50:15.282283 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3187 22:50:15.285937 3 4 16 |201 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3188 22:50:15.293041 3 4 20 |403 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3189 22:50:15.295851 3 4 24 |3d3d b0a |(11 11)(11 11) |(1 1)(1 1)| 0
3190 22:50:15.298745 3 4 28 |3d3d 2121 |(11 11)(11 11) |(1 1)(1 1)| 0
3191 22:50:15.305351 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3192 22:50:15.308846 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3193 22:50:15.312361 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3194 22:50:15.318383 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3195 22:50:15.321848 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3196 22:50:15.325204 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3197 22:50:15.331732 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3198 22:50:15.335023 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3199 22:50:15.338323 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3200 22:50:15.344545 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3201 22:50:15.347935 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3202 22:50:15.351385 [Byte 0] Lead/lag falling Transition (3, 6, 8)
3203 22:50:15.357865 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3204 22:50:15.361607 [Byte 0] Lead/lag Transition tap number (2)
3205 22:50:15.364234 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3206 22:50:15.367644 [Byte 1] Lead/lag falling Transition (3, 6, 16)
3207 22:50:15.374230 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3208 22:50:15.377400 [Byte 1] Lead/lag Transition tap number (2)
3209 22:50:15.381063 3 6 24 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3210 22:50:15.384103 [Byte 0]First pass (3, 6, 24)
3211 22:50:15.387497 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3212 22:50:15.390432 [Byte 1]First pass (3, 6, 28)
3213 22:50:15.394336 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3214 22:50:15.397112 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3215 22:50:15.403798 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3216 22:50:15.407142 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3217 22:50:15.410170 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3218 22:50:15.414029 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3219 22:50:15.420400 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3220 22:50:15.423156 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3221 22:50:15.426821 All bytes gating window > 1UI, Early break!
3222 22:50:15.426915
3223 22:50:15.429856 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
3224 22:50:15.429938
3225 22:50:15.433044 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
3226 22:50:15.433137
3227 22:50:15.433218
3228 22:50:15.433290
3229 22:50:15.440109 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
3230 22:50:15.440199
3231 22:50:15.442823 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
3232 22:50:15.442911
3233 22:50:15.442989
3234 22:50:15.446725 Write Rank1 MR1 =0x56
3235 22:50:15.446822
3236 22:50:15.449352 best RODT dly(2T, 0.5T) = (2, 3)
3237 22:50:15.449450
3238 22:50:15.449522 best RODT dly(2T, 0.5T) = (2, 3)
3239 22:50:15.452757 ==
3240 22:50:15.456420 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3241 22:50:15.459582 fsp= 1, odt_onoff= 1, Byte mode= 0
3242 22:50:15.459678 ==
3243 22:50:15.462551 Start DQ dly to find pass range UseTestEngine =0
3244 22:50:15.469235 x-axis: bit #, y-axis: DQ dly (-127~63)
3245 22:50:15.469334 RX Vref Scan = 0
3246 22:50:15.472239 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3247 22:50:15.475747 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3248 22:50:15.479139 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3249 22:50:15.482728 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3250 22:50:15.482837 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3251 22:50:15.485315 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3252 22:50:15.488643 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3253 22:50:15.492166 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3254 22:50:15.495117 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3255 22:50:15.498541 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3256 22:50:15.501819 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3257 22:50:15.505281 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3258 22:50:15.508512 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3259 22:50:15.511879 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3260 22:50:15.511975 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3261 22:50:15.514958 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3262 22:50:15.518189 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3263 22:50:15.521791 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3264 22:50:15.524731 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3265 22:50:15.527969 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3266 22:50:15.531445 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3267 22:50:15.534917 -5, [0] xxxxxxxx xxxxxxxo [MSB]
3268 22:50:15.535022 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3269 22:50:15.537759 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3270 22:50:15.541344 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3271 22:50:15.544489 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3272 22:50:15.547825 0, [0] xxxoxxxx ooxxxxxo [MSB]
3273 22:50:15.551135 1, [0] xxxoxxxx ooxxxxxo [MSB]
3274 22:50:15.554463 2, [0] xxooxxxo oooxoxxo [MSB]
3275 22:50:15.554554 3, [0] oooooxxo oooooooo [MSB]
3276 22:50:15.557871 4, [0] oooooxxo oooooooo [MSB]
3277 22:50:15.560609 32, [0] oooooooo ooooooox [MSB]
3278 22:50:15.564272 33, [0] oooooooo ooooooox [MSB]
3279 22:50:15.567303 34, [0] oooooooo ooooooox [MSB]
3280 22:50:15.570257 35, [0] ooxxoooo oxooooox [MSB]
3281 22:50:15.574283 36, [0] ooxxoooo xxooooox [MSB]
3282 22:50:15.576975 37, [0] ooxxoooo xxooooox [MSB]
3283 22:50:15.577073 38, [0] ooxxoooo xxooooox [MSB]
3284 22:50:15.580393 39, [0] oxxxooox xxooooox [MSB]
3285 22:50:15.583827 40, [0] oxxxooox xxxxooox [MSB]
3286 22:50:15.586675 41, [0] xxxxxoxx xxxxxoox [MSB]
3287 22:50:15.590296 42, [0] xxxxxoxx xxxxxoxx [MSB]
3288 22:50:15.593434 43, [0] xxxxxxxx xxxxxxxx [MSB]
3289 22:50:15.596668 iDelay=43, Bit 0, Center 21 (3 ~ 40) 38
3290 22:50:15.599829 iDelay=43, Bit 1, Center 20 (3 ~ 38) 36
3291 22:50:15.603162 iDelay=43, Bit 2, Center 18 (2 ~ 34) 33
3292 22:50:15.606331 iDelay=43, Bit 3, Center 16 (-2 ~ 34) 37
3293 22:50:15.609672 iDelay=43, Bit 4, Center 21 (3 ~ 40) 38
3294 22:50:15.613006 iDelay=43, Bit 5, Center 23 (5 ~ 42) 38
3295 22:50:15.616363 iDelay=43, Bit 6, Center 22 (5 ~ 40) 36
3296 22:50:15.619480 iDelay=43, Bit 7, Center 20 (2 ~ 38) 37
3297 22:50:15.626001 iDelay=43, Bit 8, Center 17 (0 ~ 35) 36
3298 22:50:15.629163 iDelay=43, Bit 9, Center 16 (-1 ~ 34) 36
3299 22:50:15.632604 iDelay=43, Bit 10, Center 20 (2 ~ 39) 38
3300 22:50:15.636072 iDelay=43, Bit 11, Center 21 (3 ~ 39) 37
3301 22:50:15.639032 iDelay=43, Bit 12, Center 21 (2 ~ 40) 39
3302 22:50:15.642573 iDelay=43, Bit 13, Center 22 (3 ~ 42) 40
3303 22:50:15.645633 iDelay=43, Bit 14, Center 22 (3 ~ 41) 39
3304 22:50:15.648637 iDelay=43, Bit 15, Center 13 (-5 ~ 31) 37
3305 22:50:15.648728 ==
3306 22:50:15.655645 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3307 22:50:15.658585 fsp= 1, odt_onoff= 1, Byte mode= 0
3308 22:50:15.658687 ==
3309 22:50:15.658773 DQS Delay:
3310 22:50:15.661989 DQS0 = 0, DQS1 = 0
3311 22:50:15.662076 DQM Delay:
3312 22:50:15.665199 DQM0 = 20, DQM1 = 19
3313 22:50:15.665282 DQ Delay:
3314 22:50:15.668516 DQ0 =21, DQ1 =20, DQ2 =18, DQ3 =16
3315 22:50:15.671984 DQ4 =21, DQ5 =23, DQ6 =22, DQ7 =20
3316 22:50:15.674942 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =21
3317 22:50:15.678607 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =13
3318 22:50:15.678699
3319 22:50:15.678771
3320 22:50:15.681500 DramC Write-DBI off
3321 22:50:15.681587 ==
3322 22:50:15.685038 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3323 22:50:15.688419 fsp= 1, odt_onoff= 1, Byte mode= 0
3324 22:50:15.688501 ==
3325 22:50:15.694494 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3326 22:50:15.694591
3327 22:50:15.694667 Begin, DQ Scan Range 926~1182
3328 22:50:15.694742
3329 22:50:15.694807
3330 22:50:15.697888 TX Vref Scan disable
3331 22:50:15.701367 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3332 22:50:15.704501 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3333 22:50:15.707633 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3334 22:50:15.711187 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3335 22:50:15.714506 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3336 22:50:15.720918 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3337 22:50:15.724022 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3338 22:50:15.727587 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3339 22:50:15.731000 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3340 22:50:15.734214 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3341 22:50:15.737090 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3342 22:50:15.740729 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3343 22:50:15.743808 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3344 22:50:15.747051 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3345 22:50:15.750367 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3346 22:50:15.753856 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3347 22:50:15.757071 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3348 22:50:15.763486 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3349 22:50:15.766569 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3350 22:50:15.769974 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3351 22:50:15.773080 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3352 22:50:15.776817 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3353 22:50:15.779777 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3354 22:50:15.782920 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3355 22:50:15.786222 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3356 22:50:15.789877 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3357 22:50:15.793149 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3358 22:50:15.796048 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3359 22:50:15.799434 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3360 22:50:15.802900 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3361 22:50:15.809118 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3362 22:50:15.812469 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3363 22:50:15.815715 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3364 22:50:15.819137 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3365 22:50:15.822617 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3366 22:50:15.826071 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3367 22:50:15.828829 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3368 22:50:15.832106 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3369 22:50:15.835666 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3370 22:50:15.838630 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3371 22:50:15.842087 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3372 22:50:15.845449 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3373 22:50:15.848728 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3374 22:50:15.851978 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3375 22:50:15.855200 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3376 22:50:15.858317 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3377 22:50:15.864745 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3378 22:50:15.868063 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3379 22:50:15.871322 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3380 22:50:15.874706 975 |3 6 15|[0] xxxxxxxx xxxxxxxo [MSB]
3381 22:50:15.877996 976 |3 6 16|[0] xxxxxxxx ooxxxxxo [MSB]
3382 22:50:15.881418 977 |3 6 17|[0] xxxxxxxx oooxxxoo [MSB]
3383 22:50:15.884842 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
3384 22:50:15.888387 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
3385 22:50:15.891362 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
3386 22:50:15.894427 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
3387 22:50:15.897867 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
3388 22:50:15.900695 983 |3 6 23|[0] xooooxoo oooooooo [MSB]
3389 22:50:15.908740 992 |3 6 32|[0] oooooooo ooooooox [MSB]
3390 22:50:15.912037 993 |3 6 33|[0] oooooooo ooooooox [MSB]
3391 22:50:15.914981 994 |3 6 34|[0] oooooooo xxooooox [MSB]
3392 22:50:15.918448 995 |3 6 35|[0] oooooooo xxooooox [MSB]
3393 22:50:15.921887 996 |3 6 36|[0] oooooooo xxooooox [MSB]
3394 22:50:15.924756 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3395 22:50:15.928308 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3396 22:50:15.931353 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
3397 22:50:15.934815 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
3398 22:50:15.937962 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
3399 22:50:15.941134 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
3400 22:50:15.947749 1003 |3 6 43|[0] ooxxoooo xxxxxxxx [MSB]
3401 22:50:15.951136 1004 |3 6 44|[0] ooxxooox xxxxxxxx [MSB]
3402 22:50:15.954541 1005 |3 6 45|[0] ooxxooox xxxxxxxx [MSB]
3403 22:50:15.957531 1006 |3 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
3404 22:50:15.960789 Byte0, DQ PI dly=992, DQM PI dly= 992
3405 22:50:15.963917 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 32)
3406 22:50:15.964020
3407 22:50:15.970817 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 32)
3408 22:50:15.970910
3409 22:50:15.973778 Byte1, DQ PI dly=985, DQM PI dly= 985
3410 22:50:15.977363 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
3411 22:50:15.977455
3412 22:50:15.980208 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
3413 22:50:15.980294
3414 22:50:15.983643 ==
3415 22:50:15.987130 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3416 22:50:15.991117 fsp= 1, odt_onoff= 1, Byte mode= 0
3417 22:50:15.991209 ==
3418 22:50:15.993644 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3419 22:50:15.993734
3420 22:50:15.997111 Begin, DQ Scan Range 961~1025
3421 22:50:15.999966 Write Rank1 MR14 =0x0
3422 22:50:16.008031
3423 22:50:16.008134 CH=1, VrefRange= 0, VrefLevel = 0
3424 22:50:16.014500 TX Bit0 (985~1001) 17 993, Bit8 (979~990) 12 984,
3425 22:50:16.017772 TX Bit1 (985~999) 15 992, Bit9 (977~989) 13 983,
3426 22:50:16.024238 TX Bit2 (983~997) 15 990, Bit10 (979~993) 15 986,
3427 22:50:16.027777 TX Bit3 (981~993) 13 987, Bit11 (982~993) 12 987,
3428 22:50:16.030818 TX Bit4 (984~999) 16 991, Bit12 (983~991) 9 987,
3429 22:50:16.037136 TX Bit5 (986~1001) 16 993, Bit13 (982~994) 13 988,
3430 22:50:16.040535 TX Bit6 (985~999) 15 992, Bit14 (980~992) 13 986,
3431 22:50:16.046858 TX Bit7 (985~998) 14 991, Bit15 (976~985) 10 980,
3432 22:50:16.046945
3433 22:50:16.047026 Write Rank1 MR14 =0x2
3434 22:50:16.056344
3435 22:50:16.056435 CH=1, VrefRange= 0, VrefLevel = 2
3436 22:50:16.062758 TX Bit0 (985~1002) 18 993, Bit8 (979~990) 12 984,
3437 22:50:16.065978 TX Bit1 (984~1000) 17 992, Bit9 (977~990) 14 983,
3438 22:50:16.073346 TX Bit2 (983~998) 16 990, Bit10 (978~994) 17 986,
3439 22:50:16.076085 TX Bit3 (980~994) 15 987, Bit11 (980~994) 15 987,
3440 22:50:16.079153 TX Bit4 (984~1000) 17 992, Bit12 (983~992) 10 987,
3441 22:50:16.085913 TX Bit5 (985~1002) 18 993, Bit13 (981~995) 15 988,
3442 22:50:16.089160 TX Bit6 (985~1000) 16 992, Bit14 (979~992) 14 985,
3443 22:50:16.095584 TX Bit7 (985~998) 14 991, Bit15 (975~986) 12 980,
3444 22:50:16.095676
3445 22:50:16.095756 Write Rank1 MR14 =0x4
3446 22:50:16.105220
3447 22:50:16.108425 CH=1, VrefRange= 0, VrefLevel = 4
3448 22:50:16.111845 TX Bit0 (985~1003) 19 994, Bit8 (978~991) 14 984,
3449 22:50:16.115129 TX Bit1 (984~1000) 17 992, Bit9 (977~990) 14 983,
3450 22:50:16.121471 TX Bit2 (983~998) 16 990, Bit10 (978~994) 17 986,
3451 22:50:16.125093 TX Bit3 (979~996) 18 987, Bit11 (979~995) 17 987,
3452 22:50:16.131793 TX Bit4 (984~1001) 18 992, Bit12 (982~992) 11 987,
3453 22:50:16.135171 TX Bit5 (985~1002) 18 993, Bit13 (981~996) 16 988,
3454 22:50:16.137895 TX Bit6 (984~1001) 18 992, Bit14 (979~993) 15 986,
3455 22:50:16.144273 TX Bit7 (985~999) 15 992, Bit15 (975~987) 13 981,
3456 22:50:16.144369
3457 22:50:16.144448 Write Rank1 MR14 =0x6
3458 22:50:16.154532
3459 22:50:16.154632 CH=1, VrefRange= 0, VrefLevel = 6
3460 22:50:16.161238 TX Bit0 (985~1004) 20 994, Bit8 (978~991) 14 984,
3461 22:50:16.164606 TX Bit1 (984~1001) 18 992, Bit9 (977~991) 15 984,
3462 22:50:16.170906 TX Bit2 (982~999) 18 990, Bit10 (978~995) 18 986,
3463 22:50:16.174204 TX Bit3 (980~996) 17 988, Bit11 (979~996) 18 987,
3464 22:50:16.177855 TX Bit4 (984~1001) 18 992, Bit12 (981~993) 13 987,
3465 22:50:16.184176 TX Bit5 (985~1003) 19 994, Bit13 (980~997) 18 988,
3466 22:50:16.187175 TX Bit6 (984~1001) 18 992, Bit14 (979~994) 16 986,
3467 22:50:16.194071 TX Bit7 (984~1000) 17 992, Bit15 (974~989) 16 981,
3468 22:50:16.194165
3469 22:50:16.194238 Write Rank1 MR14 =0x8
3470 22:50:16.204232
3471 22:50:16.207731 CH=1, VrefRange= 0, VrefLevel = 8
3472 22:50:16.210599 TX Bit0 (985~1004) 20 994, Bit8 (977~991) 15 984,
3473 22:50:16.213971 TX Bit1 (984~1002) 19 993, Bit9 (977~991) 15 984,
3474 22:50:16.220374 TX Bit2 (982~999) 18 990, Bit10 (978~997) 20 987,
3475 22:50:16.223500 TX Bit3 (979~997) 19 988, Bit11 (979~997) 19 988,
3476 22:50:16.229861 TX Bit4 (983~1002) 20 992, Bit12 (979~994) 16 986,
3477 22:50:16.233089 TX Bit5 (984~1004) 21 994, Bit13 (980~998) 19 989,
3478 22:50:16.236633 TX Bit6 (984~1002) 19 993, Bit14 (978~995) 18 986,
3479 22:50:16.242877 TX Bit7 (984~1000) 17 992, Bit15 (974~990) 17 982,
3480 22:50:16.242977
3481 22:50:16.243058 Write Rank1 MR14 =0xa
3482 22:50:16.253756
3483 22:50:16.256406 CH=1, VrefRange= 0, VrefLevel = 10
3484 22:50:16.259869 TX Bit0 (985~1005) 21 995, Bit8 (977~992) 16 984,
3485 22:50:16.263079 TX Bit1 (984~1003) 20 993, Bit9 (977~991) 15 984,
3486 22:50:16.269861 TX Bit2 (982~1000) 19 991, Bit10 (977~997) 21 987,
3487 22:50:16.273092 TX Bit3 (979~997) 19 988, Bit11 (979~998) 20 988,
3488 22:50:16.279404 TX Bit4 (983~1003) 21 993, Bit12 (979~995) 17 987,
3489 22:50:16.282617 TX Bit5 (984~1004) 21 994, Bit13 (979~998) 20 988,
3490 22:50:16.286030 TX Bit6 (984~1003) 20 993, Bit14 (978~995) 18 986,
3491 22:50:16.292664 TX Bit7 (984~1001) 18 992, Bit15 (974~990) 17 982,
3492 22:50:16.292765
3493 22:50:16.292845 Write Rank1 MR14 =0xc
3494 22:50:16.302998
3495 22:50:16.305968 CH=1, VrefRange= 0, VrefLevel = 12
3496 22:50:16.309391 TX Bit0 (984~1005) 22 994, Bit8 (977~992) 16 984,
3497 22:50:16.312487 TX Bit1 (984~1004) 21 994, Bit9 (976~992) 17 984,
3498 22:50:16.319545 TX Bit2 (981~1001) 21 991, Bit10 (977~998) 22 987,
3499 22:50:16.322458 TX Bit3 (978~998) 21 988, Bit11 (978~998) 21 988,
3500 22:50:16.329318 TX Bit4 (983~1004) 22 993, Bit12 (979~996) 18 987,
3501 22:50:16.332228 TX Bit5 (984~1005) 22 994, Bit13 (979~998) 20 988,
3502 22:50:16.336233 TX Bit6 (984~1004) 21 994, Bit14 (977~996) 20 986,
3503 22:50:16.342182 TX Bit7 (983~1002) 20 992, Bit15 (974~991) 18 982,
3504 22:50:16.342276
3505 22:50:16.342349 Write Rank1 MR14 =0xe
3506 22:50:16.352321
3507 22:50:16.355831 CH=1, VrefRange= 0, VrefLevel = 14
3508 22:50:16.359367 TX Bit0 (984~1005) 22 994, Bit8 (977~993) 17 985,
3509 22:50:16.362648 TX Bit1 (983~1004) 22 993, Bit9 (976~992) 17 984,
3510 22:50:16.368937 TX Bit2 (980~1001) 22 990, Bit10 (977~998) 22 987,
3511 22:50:16.372353 TX Bit3 (978~998) 21 988, Bit11 (978~998) 21 988,
3512 22:50:16.378665 TX Bit4 (983~1004) 22 993, Bit12 (978~997) 20 987,
3513 22:50:16.381878 TX Bit5 (984~1005) 22 994, Bit13 (978~999) 22 988,
3514 22:50:16.385195 TX Bit6 (983~1004) 22 993, Bit14 (977~997) 21 987,
3515 22:50:16.392102 TX Bit7 (983~1002) 20 992, Bit15 (973~991) 19 982,
3516 22:50:16.392196
3517 22:50:16.392268 Write Rank1 MR14 =0x10
3518 22:50:16.402175
3519 22:50:16.405647 CH=1, VrefRange= 0, VrefLevel = 16
3520 22:50:16.408791 TX Bit0 (984~1005) 22 994, Bit8 (976~993) 18 984,
3521 22:50:16.412240 TX Bit1 (983~1005) 23 994, Bit9 (976~993) 18 984,
3522 22:50:16.418782 TX Bit2 (981~1002) 22 991, Bit10 (977~999) 23 988,
3523 22:50:16.421778 TX Bit3 (978~999) 22 988, Bit11 (978~999) 22 988,
3524 22:50:16.428822 TX Bit4 (982~1005) 24 993, Bit12 (978~997) 20 987,
3525 22:50:16.431508 TX Bit5 (984~1005) 22 994, Bit13 (978~999) 22 988,
3526 22:50:16.434880 TX Bit6 (983~1005) 23 994, Bit14 (977~998) 22 987,
3527 22:50:16.441170 TX Bit7 (984~1003) 20 993, Bit15 (973~991) 19 982,
3528 22:50:16.441264
3529 22:50:16.444661 Write Rank1 MR14 =0x12
3530 22:50:16.452064
3531 22:50:16.455410 CH=1, VrefRange= 0, VrefLevel = 18
3532 22:50:16.458937 TX Bit0 (984~1006) 23 995, Bit8 (976~994) 19 985,
3533 22:50:16.461763 TX Bit1 (983~1005) 23 994, Bit9 (975~993) 19 984,
3534 22:50:16.468560 TX Bit2 (980~1002) 23 991, Bit10 (977~999) 23 988,
3535 22:50:16.471700 TX Bit3 (978~999) 22 988, Bit11 (978~999) 22 988,
3536 22:50:16.478491 TX Bit4 (982~1005) 24 993, Bit12 (978~998) 21 988,
3537 22:50:16.481999 TX Bit5 (984~1005) 22 994, Bit13 (978~999) 22 988,
3538 22:50:16.484955 TX Bit6 (983~1005) 23 994, Bit14 (977~998) 22 987,
3539 22:50:16.491623 TX Bit7 (983~1004) 22 993, Bit15 (972~992) 21 982,
3540 22:50:16.491717
3541 22:50:16.491791 Write Rank1 MR14 =0x14
3542 22:50:16.502197
3543 22:50:16.505192 CH=1, VrefRange= 0, VrefLevel = 20
3544 22:50:16.508667 TX Bit0 (984~1006) 23 995, Bit8 (976~994) 19 985,
3545 22:50:16.511799 TX Bit1 (982~1005) 24 993, Bit9 (975~994) 20 984,
3546 22:50:16.518236 TX Bit2 (980~1003) 24 991, Bit10 (977~999) 23 988,
3547 22:50:16.521416 TX Bit3 (978~999) 22 988, Bit11 (977~999) 23 988,
3548 22:50:16.528351 TX Bit4 (982~1005) 24 993, Bit12 (978~998) 21 988,
3549 22:50:16.531357 TX Bit5 (983~1006) 24 994, Bit13 (978~999) 22 988,
3550 22:50:16.534869 TX Bit6 (982~1005) 24 993, Bit14 (977~999) 23 988,
3551 22:50:16.541668 TX Bit7 (983~1005) 23 994, Bit15 (971~992) 22 981,
3552 22:50:16.541767
3553 22:50:16.541840 Write Rank1 MR14 =0x16
3554 22:50:16.551659
3555 22:50:16.555383 CH=1, VrefRange= 0, VrefLevel = 22
3556 22:50:16.558421 TX Bit0 (983~1006) 24 994, Bit8 (975~996) 22 985,
3557 22:50:16.561788 TX Bit1 (982~1005) 24 993, Bit9 (974~994) 21 984,
3558 22:50:16.567895 TX Bit2 (979~1004) 26 991, Bit10 (976~999) 24 987,
3559 22:50:16.571201 TX Bit3 (978~1000) 23 989, Bit11 (977~999) 23 988,
3560 22:50:16.577741 TX Bit4 (981~1005) 25 993, Bit12 (978~999) 22 988,
3561 22:50:16.581345 TX Bit5 (983~1006) 24 994, Bit13 (978~1000) 23 989,
3562 22:50:16.584906 TX Bit6 (982~1005) 24 993, Bit14 (977~999) 23 988,
3563 22:50:16.591207 TX Bit7 (982~1005) 24 993, Bit15 (971~992) 22 981,
3564 22:50:16.591343
3565 22:50:16.593940 Write Rank1 MR14 =0x18
3566 22:50:16.601782
3567 22:50:16.605639 CH=1, VrefRange= 0, VrefLevel = 24
3568 22:50:16.608330 TX Bit0 (983~1006) 24 994, Bit8 (976~997) 22 986,
3569 22:50:16.611801 TX Bit1 (982~1006) 25 994, Bit9 (975~995) 21 985,
3570 22:50:16.618182 TX Bit2 (979~1005) 27 992, Bit10 (976~999) 24 987,
3571 22:50:16.622176 TX Bit3 (977~1000) 24 988, Bit11 (977~1000) 24 988,
3572 22:50:16.627955 TX Bit4 (981~1005) 25 993, Bit12 (977~999) 23 988,
3573 22:50:16.631166 TX Bit5 (983~1006) 24 994, Bit13 (977~1000) 24 988,
3574 22:50:16.634876 TX Bit6 (982~1006) 25 994, Bit14 (977~999) 23 988,
3575 22:50:16.641089 TX Bit7 (982~1005) 24 993, Bit15 (970~993) 24 981,
3576 22:50:16.641184
3577 22:50:16.644314 Write Rank1 MR14 =0x1a
3578 22:50:16.651969
3579 22:50:16.655454 CH=1, VrefRange= 0, VrefLevel = 26
3580 22:50:16.658944 TX Bit0 (983~1006) 24 994, Bit8 (975~997) 23 986,
3581 22:50:16.662105 TX Bit1 (981~1006) 26 993, Bit9 (974~995) 22 984,
3582 22:50:16.668739 TX Bit2 (979~1005) 27 992, Bit10 (976~1000) 25 988,
3583 22:50:16.671515 TX Bit3 (977~1001) 25 989, Bit11 (977~1000) 24 988,
3584 22:50:16.678375 TX Bit4 (981~1006) 26 993, Bit12 (977~999) 23 988,
3585 22:50:16.681965 TX Bit5 (982~1006) 25 994, Bit13 (977~1001) 25 989,
3586 22:50:16.684514 TX Bit6 (981~1006) 26 993, Bit14 (976~999) 24 987,
3587 22:50:16.691536 TX Bit7 (981~1006) 26 993, Bit15 (970~994) 25 982,
3588 22:50:16.691632
3589 22:50:16.694582 Write Rank1 MR14 =0x1c
3590 22:50:16.702207
3591 22:50:16.705937 CH=1, VrefRange= 0, VrefLevel = 28
3592 22:50:16.709351 TX Bit0 (983~1007) 25 995, Bit8 (975~997) 23 986,
3593 22:50:16.712149 TX Bit1 (981~1006) 26 993, Bit9 (974~996) 23 985,
3594 22:50:16.718655 TX Bit2 (978~1005) 28 991, Bit10 (976~1000) 25 988,
3595 22:50:16.722082 TX Bit3 (977~1001) 25 989, Bit11 (976~1000) 25 988,
3596 22:50:16.728453 TX Bit4 (980~1006) 27 993, Bit12 (977~999) 23 988,
3597 22:50:16.732024 TX Bit5 (982~1006) 25 994, Bit13 (977~1001) 25 989,
3598 22:50:16.738492 TX Bit6 (981~1006) 26 993, Bit14 (977~1000) 24 988,
3599 22:50:16.741954 TX Bit7 (981~1006) 26 993, Bit15 (970~994) 25 982,
3600 22:50:16.742042
3601 22:50:16.744778 Write Rank1 MR14 =0x1e
3602 22:50:16.752716
3603 22:50:16.755989 CH=1, VrefRange= 0, VrefLevel = 30
3604 22:50:16.759745 TX Bit0 (983~1007) 25 995, Bit8 (975~997) 23 986,
3605 22:50:16.762800 TX Bit1 (981~1006) 26 993, Bit9 (974~996) 23 985,
3606 22:50:16.769522 TX Bit2 (978~1005) 28 991, Bit10 (976~1000) 25 988,
3607 22:50:16.772364 TX Bit3 (977~1001) 25 989, Bit11 (976~1000) 25 988,
3608 22:50:16.779187 TX Bit4 (980~1006) 27 993, Bit12 (977~999) 23 988,
3609 22:50:16.782572 TX Bit5 (982~1006) 25 994, Bit13 (977~1001) 25 989,
3610 22:50:16.788802 TX Bit6 (981~1006) 26 993, Bit14 (977~1000) 24 988,
3611 22:50:16.792223 TX Bit7 (981~1006) 26 993, Bit15 (970~994) 25 982,
3612 22:50:16.792321
3613 22:50:16.795456 Write Rank1 MR14 =0x20
3614 22:50:16.803160
3615 22:50:16.806676 CH=1, VrefRange= 0, VrefLevel = 32
3616 22:50:16.809792 TX Bit0 (983~1007) 25 995, Bit8 (975~997) 23 986,
3617 22:50:16.813248 TX Bit1 (981~1006) 26 993, Bit9 (974~996) 23 985,
3618 22:50:16.819948 TX Bit2 (978~1005) 28 991, Bit10 (976~1000) 25 988,
3619 22:50:16.823329 TX Bit3 (977~1001) 25 989, Bit11 (976~1000) 25 988,
3620 22:50:16.829389 TX Bit4 (980~1006) 27 993, Bit12 (977~999) 23 988,
3621 22:50:16.833077 TX Bit5 (982~1006) 25 994, Bit13 (977~1001) 25 989,
3622 22:50:16.839372 TX Bit6 (981~1006) 26 993, Bit14 (977~1000) 24 988,
3623 22:50:16.842730 TX Bit7 (981~1006) 26 993, Bit15 (970~994) 25 982,
3624 22:50:16.842824
3625 22:50:16.846267 Write Rank1 MR14 =0x22
3626 22:50:16.854144
3627 22:50:16.857154 CH=1, VrefRange= 0, VrefLevel = 34
3628 22:50:16.860238 TX Bit0 (983~1007) 25 995, Bit8 (975~997) 23 986,
3629 22:50:16.863543 TX Bit1 (981~1006) 26 993, Bit9 (974~996) 23 985,
3630 22:50:16.870084 TX Bit2 (978~1005) 28 991, Bit10 (976~1000) 25 988,
3631 22:50:16.873742 TX Bit3 (977~1001) 25 989, Bit11 (976~1000) 25 988,
3632 22:50:16.880185 TX Bit4 (980~1006) 27 993, Bit12 (977~999) 23 988,
3633 22:50:16.883339 TX Bit5 (982~1006) 25 994, Bit13 (977~1001) 25 989,
3634 22:50:16.890277 TX Bit6 (981~1006) 26 993, Bit14 (977~1000) 24 988,
3635 22:50:16.893189 TX Bit7 (981~1006) 26 993, Bit15 (970~994) 25 982,
3636 22:50:16.893283
3637 22:50:16.896491 Write Rank1 MR14 =0x24
3638 22:50:16.904289
3639 22:50:16.907776 CH=1, VrefRange= 0, VrefLevel = 36
3640 22:50:16.910630 TX Bit0 (983~1007) 25 995, Bit8 (975~997) 23 986,
3641 22:50:16.914092 TX Bit1 (981~1006) 26 993, Bit9 (974~996) 23 985,
3642 22:50:16.920716 TX Bit2 (978~1005) 28 991, Bit10 (976~1000) 25 988,
3643 22:50:16.924292 TX Bit3 (977~1001) 25 989, Bit11 (976~1000) 25 988,
3644 22:50:16.930461 TX Bit4 (980~1006) 27 993, Bit12 (977~999) 23 988,
3645 22:50:16.933746 TX Bit5 (982~1006) 25 994, Bit13 (977~1001) 25 989,
3646 22:50:16.940209 TX Bit6 (981~1006) 26 993, Bit14 (977~1000) 24 988,
3647 22:50:16.943608 TX Bit7 (981~1006) 26 993, Bit15 (970~994) 25 982,
3648 22:50:16.943695
3649 22:50:16.943782
3650 22:50:16.946756 TX Vref found, early break! 377< 380
3651 22:50:16.950148 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
3652 22:50:16.953537 u1DelayCellOfst[0]=7 cells (6 PI)
3653 22:50:16.956870 u1DelayCellOfst[1]=5 cells (4 PI)
3654 22:50:16.959794 u1DelayCellOfst[2]=2 cells (2 PI)
3655 22:50:16.963102 u1DelayCellOfst[3]=0 cells (0 PI)
3656 22:50:16.966608 u1DelayCellOfst[4]=5 cells (4 PI)
3657 22:50:16.969721 u1DelayCellOfst[5]=6 cells (5 PI)
3658 22:50:16.972889 u1DelayCellOfst[6]=5 cells (4 PI)
3659 22:50:16.976123 u1DelayCellOfst[7]=5 cells (4 PI)
3660 22:50:16.979632 Byte0, DQ PI dly=989, DQM PI dly= 992
3661 22:50:16.982756 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
3662 22:50:16.982850
3663 22:50:16.989572 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
3664 22:50:16.989666
3665 22:50:16.993080 u1DelayCellOfst[8]=5 cells (4 PI)
3666 22:50:16.993172 u1DelayCellOfst[9]=3 cells (3 PI)
3667 22:50:16.995686 u1DelayCellOfst[10]=7 cells (6 PI)
3668 22:50:16.999139 u1DelayCellOfst[11]=7 cells (6 PI)
3669 22:50:17.002596 u1DelayCellOfst[12]=7 cells (6 PI)
3670 22:50:17.005930 u1DelayCellOfst[13]=9 cells (7 PI)
3671 22:50:17.008890 u1DelayCellOfst[14]=7 cells (6 PI)
3672 22:50:17.012178 u1DelayCellOfst[15]=0 cells (0 PI)
3673 22:50:17.015507 Byte1, DQ PI dly=982, DQM PI dly= 985
3674 22:50:17.021963 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
3675 22:50:17.022091
3676 22:50:17.025413 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
3677 22:50:17.025547
3678 22:50:17.028390 Write Rank1 MR14 =0x1c
3679 22:50:17.028480
3680 22:50:17.028559 Final TX Range 0 Vref 28
3681 22:50:17.028628
3682 22:50:17.034982 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3683 22:50:17.035074
3684 22:50:17.041810 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3685 22:50:17.048458 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3686 22:50:17.057905 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3687 22:50:17.058021 Write Rank1 MR3 =0xb0
3688 22:50:17.061486 DramC Write-DBI on
3689 22:50:17.061579 ==
3690 22:50:17.064817 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3691 22:50:17.067998 fsp= 1, odt_onoff= 1, Byte mode= 0
3692 22:50:17.068093 ==
3693 22:50:17.074378 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3694 22:50:17.074472
3695 22:50:17.077755 Begin, DQ Scan Range 705~769
3696 22:50:17.077848
3697 22:50:17.077921
3698 22:50:17.077989 TX Vref Scan disable
3699 22:50:17.081014 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3700 22:50:17.084390 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3701 22:50:17.087778 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3702 22:50:17.090656 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3703 22:50:17.097736 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3704 22:50:17.100486 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3705 22:50:17.104160 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3706 22:50:17.107164 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3707 22:50:17.110692 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3708 22:50:17.114009 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3709 22:50:17.116863 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3710 22:50:17.120414 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3711 22:50:17.123813 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3712 22:50:17.126847 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3713 22:50:17.129867 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3714 22:50:17.133276 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3715 22:50:17.136644 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3716 22:50:17.139950 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3717 22:50:17.146619 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3718 22:50:17.149796 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3719 22:50:17.156144 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3720 22:50:17.159613 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3721 22:50:17.162633 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3722 22:50:17.165939 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3723 22:50:17.169304 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3724 22:50:17.172361 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3725 22:50:17.175908 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3726 22:50:17.178781 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3727 22:50:17.182613 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3728 22:50:17.185347 Byte0, DQ PI dly=737, DQM PI dly= 737
3729 22:50:17.192773 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 33)
3730 22:50:17.192871
3731 22:50:17.195382 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 33)
3732 22:50:17.195472
3733 22:50:17.198857 Byte1, DQ PI dly=730, DQM PI dly= 730
3734 22:50:17.201853 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
3735 22:50:17.201980
3736 22:50:17.208697 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
3737 22:50:17.208791
3738 22:50:17.215226 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3739 22:50:17.221825 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3740 22:50:17.227902 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3741 22:50:17.231279 Write Rank1 MR3 =0x30
3742 22:50:17.231378 DramC Write-DBI off
3743 22:50:17.231456
3744 22:50:17.231530 [DATLAT]
3745 22:50:17.234518 Freq=1600, CH1 RK1, use_rxtx_scan=0
3746 22:50:17.238133
3747 22:50:17.238224 DATLAT Default: 0x10
3748 22:50:17.241123 7, 0xFFFF, sum=0
3749 22:50:17.241255 8, 0xFFFF, sum=0
3750 22:50:17.244520 9, 0xFFFF, sum=0
3751 22:50:17.244615 10, 0xFFFF, sum=0
3752 22:50:17.247740 11, 0xFFFF, sum=0
3753 22:50:17.247828 12, 0xFFFF, sum=0
3754 22:50:17.251055 13, 0xFFFF, sum=0
3755 22:50:17.251142 14, 0x0, sum=1
3756 22:50:17.251231 15, 0x0, sum=2
3757 22:50:17.254607 16, 0x0, sum=3
3758 22:50:17.254700 17, 0x0, sum=4
3759 22:50:17.261053 pattern=2 first_step=14 total pass=5 best_step=16
3760 22:50:17.261149 ==
3761 22:50:17.264460 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3762 22:50:17.267272 fsp= 1, odt_onoff= 1, Byte mode= 0
3763 22:50:17.267366 ==
3764 22:50:17.274078 Start DQ dly to find pass range UseTestEngine =1
3765 22:50:17.277152 x-axis: bit #, y-axis: DQ dly (-127~63)
3766 22:50:17.277245 RX Vref Scan = 0
3767 22:50:17.280719 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3768 22:50:17.283623 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3769 22:50:17.286996 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3770 22:50:17.290432 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3771 22:50:17.293897 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3772 22:50:17.293995 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3773 22:50:17.296636 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3774 22:50:17.300777 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3775 22:50:17.303647 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3776 22:50:17.306680 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3777 22:50:17.309866 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3778 22:50:17.313300 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3779 22:50:17.316724 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3780 22:50:17.320121 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3781 22:50:17.320220 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3782 22:50:17.322936 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3783 22:50:17.326376 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3784 22:50:17.329786 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3785 22:50:17.333210 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3786 22:50:17.336131 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3787 22:50:17.339681 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3788 22:50:17.343242 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3789 22:50:17.343339 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3790 22:50:17.346250 -3, [0] xxxxxxxx xoxxxxxo [MSB]
3791 22:50:17.349333 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3792 22:50:17.352814 -1, [0] xxxoxxxx ooxxxxxo [MSB]
3793 22:50:17.355697 0, [0] xxxoxxxx ooxxxxxo [MSB]
3794 22:50:17.358784 1, [0] xxxoxxxx ooxxxxxo [MSB]
3795 22:50:17.362124 2, [0] xxxoxxxx ooxxxxxo [MSB]
3796 22:50:17.362214 3, [0] xoooxxxo oooooxxo [MSB]
3797 22:50:17.365844 4, [0] oooooxxo oooooooo [MSB]
3798 22:50:17.368646 5, [0] oooooxxo oooooooo [MSB]
3799 22:50:17.373600 32, [0] oooooooo ooooooox [MSB]
3800 22:50:17.376411 33, [0] oooooooo ooooooox [MSB]
3801 22:50:17.379784 34, [0] oooxoooo oxooooox [MSB]
3802 22:50:17.383292 35, [0] ooxxoooo oxooooox [MSB]
3803 22:50:17.386467 36, [0] ooxxoooo xxooooox [MSB]
3804 22:50:17.389460 37, [0] ooxxoooo xxooooox [MSB]
3805 22:50:17.392804 38, [0] ooxxoooo xxooxoox [MSB]
3806 22:50:17.392893 39, [0] ooxxooox xxxxxoox [MSB]
3807 22:50:17.396266 40, [0] oxxxxoox xxxxxxox [MSB]
3808 22:50:17.399680 41, [0] xxxxxxxx xxxxxxxx [MSB]
3809 22:50:17.403058 iDelay=41, Bit 0, Center 22 (4 ~ 40) 37
3810 22:50:17.405966 iDelay=41, Bit 1, Center 21 (3 ~ 39) 37
3811 22:50:17.409287 iDelay=41, Bit 2, Center 18 (3 ~ 34) 32
3812 22:50:17.415728 iDelay=41, Bit 3, Center 15 (-2 ~ 33) 36
3813 22:50:17.419189 iDelay=41, Bit 4, Center 21 (4 ~ 39) 36
3814 22:50:17.422314 iDelay=41, Bit 5, Center 23 (6 ~ 40) 35
3815 22:50:17.425737 iDelay=41, Bit 6, Center 23 (6 ~ 40) 35
3816 22:50:17.429175 iDelay=41, Bit 7, Center 20 (3 ~ 38) 36
3817 22:50:17.432047 iDelay=41, Bit 8, Center 17 (-1 ~ 35) 37
3818 22:50:17.435613 iDelay=41, Bit 9, Center 15 (-3 ~ 33) 37
3819 22:50:17.438613 iDelay=41, Bit 10, Center 20 (3 ~ 38) 36
3820 22:50:17.441977 iDelay=41, Bit 11, Center 20 (3 ~ 38) 36
3821 22:50:17.445493 iDelay=41, Bit 12, Center 20 (3 ~ 37) 35
3822 22:50:17.448325 iDelay=41, Bit 13, Center 21 (4 ~ 39) 36
3823 22:50:17.454988 iDelay=41, Bit 14, Center 22 (4 ~ 40) 37
3824 22:50:17.458516 iDelay=41, Bit 15, Center 13 (-4 ~ 31) 36
3825 22:50:17.458608 ==
3826 22:50:17.461714 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3827 22:50:17.464862 fsp= 1, odt_onoff= 1, Byte mode= 0
3828 22:50:17.464965 ==
3829 22:50:17.468383 DQS Delay:
3830 22:50:17.468474 DQS0 = 0, DQS1 = 0
3831 22:50:17.471352 DQM Delay:
3832 22:50:17.471445 DQM0 = 20, DQM1 = 18
3833 22:50:17.471518 DQ Delay:
3834 22:50:17.475151 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =15
3835 22:50:17.478410 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =20
3836 22:50:17.481509 DQ8 =17, DQ9 =15, DQ10 =20, DQ11 =20
3837 22:50:17.484828 DQ12 =20, DQ13 =21, DQ14 =22, DQ15 =13
3838 22:50:17.484924
3839 22:50:17.485003
3840 22:50:17.485083
3841 22:50:17.488078 [DramC_TX_OE_Calibration] TA2
3842 22:50:17.491121 Original DQ_B0 (3 6) =30, OEN = 27
3843 22:50:17.494589 Original DQ_B1 (3 6) =30, OEN = 27
3844 22:50:17.497964 23, 0x0, End_B0=23 End_B1=23
3845 22:50:17.501194 24, 0x0, End_B0=24 End_B1=24
3846 22:50:17.504192 25, 0x0, End_B0=25 End_B1=25
3847 22:50:17.504290 26, 0x0, End_B0=26 End_B1=26
3848 22:50:17.507517 27, 0x0, End_B0=27 End_B1=27
3849 22:50:17.510950 28, 0x0, End_B0=28 End_B1=28
3850 22:50:17.514341 29, 0x0, End_B0=29 End_B1=29
3851 22:50:17.517361 30, 0x0, End_B0=30 End_B1=30
3852 22:50:17.517456 31, 0xFFFF, End_B0=30 End_B1=30
3853 22:50:17.523761 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3854 22:50:17.531016 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3855 22:50:17.531109
3856 22:50:17.531182
3857 22:50:17.533363 Write Rank1 MR23 =0x3f
3858 22:50:17.533456 [DQSOSC]
3859 22:50:17.540360 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0x202, tDQSOscB0 = 451 ps tDQSOscB1 = 451 ps
3860 22:50:17.546617 CH1_RK1: MR19=0x202, MR18=0xBABA, DQSOSC=451, MR23=63, INC=12, DEC=18
3861 22:50:17.549975 Write Rank1 MR23 =0x3f
3862 22:50:17.550067 [DQSOSC]
3863 22:50:17.556584 [DQSOSCAuto] RK1, (LSB)MR18= 0xb8b8, (MSB)MR19= 0x202, tDQSOscB0 = 452 ps tDQSOscB1 = 452 ps
3864 22:50:17.560193 CH1 RK1: MR19=202, MR18=B8B8
3865 22:50:17.563480 [RxdqsGatingPostProcess] freq 1600
3866 22:50:17.569814 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3867 22:50:17.569909 Rank: 0
3868 22:50:17.573148 best DQS0 dly(2T, 0.5T) = (2, 6)
3869 22:50:17.576318 best DQS1 dly(2T, 0.5T) = (2, 6)
3870 22:50:17.579544 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3871 22:50:17.582919 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3872 22:50:17.583012 Rank: 1
3873 22:50:17.586102 best DQS0 dly(2T, 0.5T) = (2, 6)
3874 22:50:17.589369 best DQS1 dly(2T, 0.5T) = (2, 6)
3875 22:50:17.592980 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3876 22:50:17.595666 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3877 22:50:17.599140 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3878 22:50:17.602730 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3879 22:50:17.609147 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3880 22:50:17.609243
3881 22:50:17.609316
3882 22:50:17.611978 [Calibration Summary] Freqency 1600
3883 22:50:17.612070 CH 0, Rank 0
3884 22:50:17.615183 All Pass.
3885 22:50:17.615298
3886 22:50:17.615372 CH 0, Rank 1
3887 22:50:17.615440 All Pass.
3888 22:50:17.615505
3889 22:50:17.618801 CH 1, Rank 0
3890 22:50:17.618892 All Pass.
3891 22:50:17.618964
3892 22:50:17.619034 CH 1, Rank 1
3893 22:50:17.622368 All Pass.
3894 22:50:17.622466
3895 22:50:17.628628 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3896 22:50:17.635428 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3897 22:50:17.641805 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3898 22:50:17.644959 Write Rank0 MR3 =0xb0
3899 22:50:17.651830 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3900 22:50:17.657963 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3901 22:50:17.664656 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3902 22:50:17.664749 Write Rank1 MR3 =0xb0
3903 22:50:17.671159 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3904 22:50:17.681209 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3905 22:50:17.687439 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3906 22:50:17.687562 Write Rank0 MR3 =0xb0
3907 22:50:17.693910 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3908 22:50:17.700528 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3909 22:50:17.710235 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3910 22:50:17.710331 Write Rank1 MR3 =0xb0
3911 22:50:17.713701 DramC Write-DBI on
3912 22:50:17.716876 [GetDramInforAfterCalByMRR] Vendor 6.
3913 22:50:17.720072 [GetDramInforAfterCalByMRR] Revision 505.
3914 22:50:17.720165 MR8 1111
3915 22:50:17.726661 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3916 22:50:17.726753 MR8 1111
3917 22:50:17.730135 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3918 22:50:17.733351 MR8 1111
3919 22:50:17.736415 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3920 22:50:17.736508 MR8 1111
3921 22:50:17.743068 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3922 22:50:17.753167 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3923 22:50:17.753260 Write Rank0 MR13 =0xd0
3924 22:50:17.756131 Write Rank1 MR13 =0xd0
3925 22:50:17.759703 Write Rank0 MR13 =0xd0
3926 22:50:17.759795 Write Rank1 MR13 =0xd0
3927 22:50:17.762911 Save calibration result to emmc
3928 22:50:17.763002
3929 22:50:17.763075
3930 22:50:17.766458 [DramcModeReg_Check] Freq_1600, FSP_1
3931 22:50:17.769239 FSP_1, CH_0, RK0
3932 22:50:17.769339 Write Rank0 MR13 =0xd8
3933 22:50:17.772627 MR12 = 0x5c (global = 0x5c) match
3934 22:50:17.776070 MR14 = 0x1c (global = 0x1c) match
3935 22:50:17.778973 FSP_1, CH_0, RK1
3936 22:50:17.779065 Write Rank1 MR13 =0xd8
3937 22:50:17.782466 MR12 = 0x5e (global = 0x5e) match
3938 22:50:17.786078 MR14 = 0x1e (global = 0x1e) match
3939 22:50:17.788826 FSP_1, CH_1, RK0
3940 22:50:17.788919 Write Rank0 MR13 =0xd8
3941 22:50:17.792248 MR12 = 0x5c (global = 0x5c) match
3942 22:50:17.795789 MR14 = 0x20 (global = 0x20) match
3943 22:50:17.798525 FSP_1, CH_1, RK1
3944 22:50:17.798618 Write Rank1 MR13 =0xd8
3945 22:50:17.802006 MR12 = 0x5e (global = 0x5e) match
3946 22:50:17.805406 MR14 = 0x1c (global = 0x1c) match
3947 22:50:17.805499
3948 22:50:17.812022 [MEM_TEST] 02: After DFS, before run time config
3949 22:50:17.822074 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3950 22:50:17.822168
3951 22:50:17.822240 [TA2_TEST]
3952 22:50:17.822307 === TA2 HW
3953 22:50:17.825160 TA2 PAT: XTALK
3954 22:50:17.828285 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3955 22:50:17.834904 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3956 22:50:17.837867 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3957 22:50:17.844637 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3958 22:50:17.844734
3959 22:50:17.844806
3960 22:50:17.844873 Settings after calibration
3961 22:50:17.844938
3962 22:50:17.848129 [DramcRunTimeConfig]
3963 22:50:17.851496 TransferPLLToSPMControl - MODE SW PHYPLL
3964 22:50:17.854615 TX_TRACKING: ON
3965 22:50:17.854738 RX_TRACKING: ON
3966 22:50:17.854841 HW_GATING: ON
3967 22:50:17.857746 HW_GATING DBG: OFF
3968 22:50:17.857847 ddr_geometry:1
3969 22:50:17.861192 ddr_geometry:1
3970 22:50:17.861283 ddr_geometry:1
3971 22:50:17.864380 ddr_geometry:1
3972 22:50:17.864472 ddr_geometry:1
3973 22:50:17.864543 ddr_geometry:1
3974 22:50:17.867564 ddr_geometry:1
3975 22:50:17.867656 ddr_geometry:1
3976 22:50:17.870859 High Freq DUMMY_READ_FOR_TRACKING: ON
3977 22:50:17.874189 ZQCS_ENABLE_LP4: OFF
3978 22:50:17.877686 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3979 22:50:17.881047 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3980 22:50:17.881138 SPM_CONTROL_AFTERK: ON
3981 22:50:17.883850 IMPEDANCE_TRACKING: ON
3982 22:50:17.887147 TEMP_SENSOR: ON
3983 22:50:17.887270 PER_BANK_REFRESH: ON
3984 22:50:17.890809 HW_SAVE_FOR_SR: ON
3985 22:50:17.893526 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3986 22:50:17.896987 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3987 22:50:17.900650 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3988 22:50:17.900742 Read ODT Tracking: ON
3989 22:50:17.903898 =========================
3990 22:50:17.903990
3991 22:50:17.904063 [TA2_TEST]
3992 22:50:17.906718 === TA2 HW
3993 22:50:17.910105 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3994 22:50:17.916727 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3995 22:50:17.920145 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3996 22:50:17.926679 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3997 22:50:17.926801
3998 22:50:17.929510 [MEM_TEST] 03: After run time config
3999 22:50:17.939619 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4000 22:50:17.942594 [complex_mem_test] start addr:0x40024000, len:131072
4001 22:50:18.147437 1st complex R/W mem test pass
4002 22:50:18.153560 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4003 22:50:18.157103 sync preloader write leveling
4004 22:50:18.160140 sync preloader cbt_mr12
4005 22:50:18.163179 sync preloader cbt_clk_dly
4006 22:50:18.163291 sync preloader cbt_cmd_dly
4007 22:50:18.166585 sync preloader cbt_cs
4008 22:50:18.169807 sync preloader cbt_ca_perbit_delay
4009 22:50:18.173107 sync preloader clk_delay
4010 22:50:18.173200 sync preloader dqs_delay
4011 22:50:18.176746 sync preloader u1Gating2T_Save
4012 22:50:18.180130 sync preloader u1Gating05T_Save
4013 22:50:18.183254 sync preloader u1Gatingfine_tune_Save
4014 22:50:18.186410 sync preloader u1Gatingucpass_count_Save
4015 22:50:18.189526 sync preloader u1TxWindowPerbitVref_Save
4016 22:50:18.192975 sync preloader u1TxCenter_min_Save
4017 22:50:18.196055 sync preloader u1TxCenter_max_Save
4018 22:50:18.199356 sync preloader u1Txwin_center_Save
4019 22:50:18.203244 sync preloader u1Txfirst_pass_Save
4020 22:50:18.206107 sync preloader u1Txlast_pass_Save
4021 22:50:18.209733 sync preloader u1RxDatlat_Save
4022 22:50:18.212337 sync preloader u1RxWinPerbitVref_Save
4023 22:50:18.216065 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4024 22:50:18.219496 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4025 22:50:18.222217 sync preloader delay_cell_unit
4026 22:50:18.228711 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4027 22:50:18.232077 sync preloader write leveling
4028 22:50:18.235241 sync preloader cbt_mr12
4029 22:50:18.235363 sync preloader cbt_clk_dly
4030 22:50:18.238514 sync preloader cbt_cmd_dly
4031 22:50:18.242019 sync preloader cbt_cs
4032 22:50:18.245482 sync preloader cbt_ca_perbit_delay
4033 22:50:18.245574 sync preloader clk_delay
4034 22:50:18.248715 sync preloader dqs_delay
4035 22:50:18.252132 sync preloader u1Gating2T_Save
4036 22:50:18.254895 sync preloader u1Gating05T_Save
4037 22:50:18.258870 sync preloader u1Gatingfine_tune_Save
4038 22:50:18.261651 sync preloader u1Gatingucpass_count_Save
4039 22:50:18.264889 sync preloader u1TxWindowPerbitVref_Save
4040 22:50:18.268334 sync preloader u1TxCenter_min_Save
4041 22:50:18.271197 sync preloader u1TxCenter_max_Save
4042 22:50:18.275059 sync preloader u1Txwin_center_Save
4043 22:50:18.278336 sync preloader u1Txfirst_pass_Save
4044 22:50:18.281175 sync preloader u1Txlast_pass_Save
4045 22:50:18.284661 sync preloader u1RxDatlat_Save
4046 22:50:18.287615 sync preloader u1RxWinPerbitVref_Save
4047 22:50:18.291502 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4048 22:50:18.294276 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4049 22:50:18.297712 sync preloader delay_cell_unit
4050 22:50:18.304447 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4051 22:50:18.307676 sync preloader write leveling
4052 22:50:18.311028 sync preloader cbt_mr12
4053 22:50:18.311150 sync preloader cbt_clk_dly
4054 22:50:18.313920 sync preloader cbt_cmd_dly
4055 22:50:18.317403 sync preloader cbt_cs
4056 22:50:18.320815 sync preloader cbt_ca_perbit_delay
4057 22:50:18.320906 sync preloader clk_delay
4058 22:50:18.323818 sync preloader dqs_delay
4059 22:50:18.327146 sync preloader u1Gating2T_Save
4060 22:50:18.330436 sync preloader u1Gating05T_Save
4061 22:50:18.333613 sync preloader u1Gatingfine_tune_Save
4062 22:50:18.337211 sync preloader u1Gatingucpass_count_Save
4063 22:50:18.340022 sync preloader u1TxWindowPerbitVref_Save
4064 22:50:18.343430 sync preloader u1TxCenter_min_Save
4065 22:50:18.346953 sync preloader u1TxCenter_max_Save
4066 22:50:18.349869 sync preloader u1Txwin_center_Save
4067 22:50:18.353243 sync preloader u1Txfirst_pass_Save
4068 22:50:18.356927 sync preloader u1Txlast_pass_Save
4069 22:50:18.357018 sync preloader u1RxDatlat_Save
4070 22:50:18.359624 sync preloader u1RxWinPerbitVref_Save
4071 22:50:18.366506 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4072 22:50:18.369758 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4073 22:50:18.372726 sync preloader delay_cell_unit
4074 22:50:18.376068 just_for_test_dump_coreboot_params dump all params
4075 22:50:18.379156 dump source = 0x0
4076 22:50:18.379275 dump params frequency:1600
4077 22:50:18.382951 dump params rank number:2
4078 22:50:18.383074
4079 22:50:18.385909 dump params write leveling
4080 22:50:18.389183 write leveling[0][0][0] = 0x1f
4081 22:50:18.392506 write leveling[0][0][1] = 0x1b
4082 22:50:18.395692 write leveling[0][1][0] = 0x1c
4083 22:50:18.395785 write leveling[0][1][1] = 0x19
4084 22:50:18.398798 write leveling[1][0][0] = 0x25
4085 22:50:18.402108 write leveling[1][0][1] = 0x1e
4086 22:50:18.405441 write leveling[1][1][0] = 0x23
4087 22:50:18.408723 write leveling[1][1][1] = 0x1e
4088 22:50:18.408817 dump params cbt_cs
4089 22:50:18.412084 cbt_cs[0][0] = 0x7
4090 22:50:18.412176 cbt_cs[0][1] = 0x7
4091 22:50:18.415401 cbt_cs[1][0] = 0xa
4092 22:50:18.415492 cbt_cs[1][1] = 0xa
4093 22:50:18.418921 dump params cbt_mr12
4094 22:50:18.421709 cbt_mr12[0][0] = 0x1c
4095 22:50:18.421815 cbt_mr12[0][1] = 0x1e
4096 22:50:18.425100 cbt_mr12[1][0] = 0x1c
4097 22:50:18.425192 cbt_mr12[1][1] = 0x1e
4098 22:50:18.428467 dump params tx window
4099 22:50:18.431574 tx_center_min[0][0][0] = 984
4100 22:50:18.435075 tx_center_max[0][0][0] = 990
4101 22:50:18.435198 tx_center_min[0][0][1] = 979
4102 22:50:18.438342 tx_center_max[0][0][1] = 986
4103 22:50:18.441637 tx_center_min[0][1][0] = 983
4104 22:50:18.444691 tx_center_max[0][1][0] = 990
4105 22:50:18.447935 tx_center_min[0][1][1] = 980
4106 22:50:18.448057 tx_center_max[0][1][1] = 987
4107 22:50:18.451500 tx_center_min[1][0][0] = 989
4108 22:50:18.454981 tx_center_max[1][0][0] = 995
4109 22:50:18.458224 tx_center_min[1][0][1] = 981
4110 22:50:18.461044 tx_center_max[1][0][1] = 988
4111 22:50:18.461136 tx_center_min[1][1][0] = 989
4112 22:50:18.464498 tx_center_max[1][1][0] = 995
4113 22:50:18.467770 tx_center_min[1][1][1] = 982
4114 22:50:18.471004 tx_center_max[1][1][1] = 989
4115 22:50:18.471096 dump params tx window
4116 22:50:18.473980 tx_win_center[0][0][0] = 990
4117 22:50:18.477654 tx_first_pass[0][0][0] = 978
4118 22:50:18.480835 tx_last_pass[0][0][0] = 1002
4119 22:50:18.483715 tx_win_center[0][0][1] = 989
4120 22:50:18.483808 tx_first_pass[0][0][1] = 977
4121 22:50:18.487440 tx_last_pass[0][0][1] = 1001
4122 22:50:18.490575 tx_win_center[0][0][2] = 990
4123 22:50:18.493571 tx_first_pass[0][0][2] = 978
4124 22:50:18.496904 tx_last_pass[0][0][2] = 1002
4125 22:50:18.496996 tx_win_center[0][0][3] = 984
4126 22:50:18.500779 tx_first_pass[0][0][3] = 973
4127 22:50:18.503639 tx_last_pass[0][0][3] = 996
4128 22:50:18.507116 tx_win_center[0][0][4] = 988
4129 22:50:18.509935 tx_first_pass[0][0][4] = 977
4130 22:50:18.510029 tx_last_pass[0][0][4] = 1000
4131 22:50:18.513445 tx_win_center[0][0][5] = 986
4132 22:50:18.516635 tx_first_pass[0][0][5] = 975
4133 22:50:18.520102 tx_last_pass[0][0][5] = 998
4134 22:50:18.523439 tx_win_center[0][0][6] = 987
4135 22:50:18.523531 tx_first_pass[0][0][6] = 976
4136 22:50:18.526811 tx_last_pass[0][0][6] = 999
4137 22:50:18.529705 tx_win_center[0][0][7] = 989
4138 22:50:18.533219 tx_first_pass[0][0][7] = 977
4139 22:50:18.536559 tx_last_pass[0][0][7] = 1001
4140 22:50:18.536652 tx_win_center[0][0][8] = 979
4141 22:50:18.539384 tx_first_pass[0][0][8] = 968
4142 22:50:18.542768 tx_last_pass[0][0][8] = 991
4143 22:50:18.546082 tx_win_center[0][0][9] = 981
4144 22:50:18.546204 tx_first_pass[0][0][9] = 969
4145 22:50:18.549356 tx_last_pass[0][0][9] = 993
4146 22:50:18.552925 tx_win_center[0][0][10] = 986
4147 22:50:18.555982 tx_first_pass[0][0][10] = 974
4148 22:50:18.559673 tx_last_pass[0][0][10] = 998
4149 22:50:18.562765 tx_win_center[0][0][11] = 980
4150 22:50:18.562857 tx_first_pass[0][0][11] = 968
4151 22:50:18.566146 tx_last_pass[0][0][11] = 992
4152 22:50:18.569503 tx_win_center[0][0][12] = 981
4153 22:50:18.572239 tx_first_pass[0][0][12] = 970
4154 22:50:18.575934 tx_last_pass[0][0][12] = 993
4155 22:50:18.576027 tx_win_center[0][0][13] = 981
4156 22:50:18.579490 tx_first_pass[0][0][13] = 970
4157 22:50:18.582093 tx_last_pass[0][0][13] = 993
4158 22:50:18.585787 tx_win_center[0][0][14] = 983
4159 22:50:18.589030 tx_first_pass[0][0][14] = 970
4160 22:50:18.589122 tx_last_pass[0][0][14] = 996
4161 22:50:18.591836 tx_win_center[0][0][15] = 985
4162 22:50:18.595512 tx_first_pass[0][0][15] = 973
4163 22:50:18.598879 tx_last_pass[0][0][15] = 998
4164 22:50:18.602176 tx_win_center[0][1][0] = 990
4165 22:50:18.605031 tx_first_pass[0][1][0] = 978
4166 22:50:18.605124 tx_last_pass[0][1][0] = 1002
4167 22:50:18.608425 tx_win_center[0][1][1] = 989
4168 22:50:18.611553 tx_first_pass[0][1][1] = 977
4169 22:50:18.614841 tx_last_pass[0][1][1] = 1001
4170 22:50:18.618151 tx_win_center[0][1][2] = 990
4171 22:50:18.618244 tx_first_pass[0][1][2] = 978
4172 22:50:18.621841 tx_last_pass[0][1][2] = 1002
4173 22:50:18.624756 tx_win_center[0][1][3] = 983
4174 22:50:18.627968 tx_first_pass[0][1][3] = 971
4175 22:50:18.628062 tx_last_pass[0][1][3] = 995
4176 22:50:18.631577 tx_win_center[0][1][4] = 989
4177 22:50:18.634314 tx_first_pass[0][1][4] = 977
4178 22:50:18.637723 tx_last_pass[0][1][4] = 1001
4179 22:50:18.641193 tx_win_center[0][1][5] = 986
4180 22:50:18.644676 tx_first_pass[0][1][5] = 975
4181 22:50:18.644769 tx_last_pass[0][1][5] = 998
4182 22:50:18.647487 tx_win_center[0][1][6] = 988
4183 22:50:18.651184 tx_first_pass[0][1][6] = 976
4184 22:50:18.654423 tx_last_pass[0][1][6] = 1000
4185 22:50:18.654516 tx_win_center[0][1][7] = 989
4186 22:50:18.657351 tx_first_pass[0][1][7] = 977
4187 22:50:18.660764 tx_last_pass[0][1][7] = 1002
4188 22:50:18.663957 tx_win_center[0][1][8] = 980
4189 22:50:18.667057 tx_first_pass[0][1][8] = 968
4190 22:50:18.667149 tx_last_pass[0][1][8] = 993
4191 22:50:18.670781 tx_win_center[0][1][9] = 982
4192 22:50:18.673629 tx_first_pass[0][1][9] = 970
4193 22:50:18.677190 tx_last_pass[0][1][9] = 994
4194 22:50:18.680289 tx_win_center[0][1][10] = 987
4195 22:50:18.680383 tx_first_pass[0][1][10] = 975
4196 22:50:18.683598 tx_last_pass[0][1][10] = 1000
4197 22:50:18.686688 tx_win_center[0][1][11] = 981
4198 22:50:18.690323 tx_first_pass[0][1][11] = 969
4199 22:50:18.693447 tx_last_pass[0][1][11] = 993
4200 22:50:18.696575 tx_win_center[0][1][12] = 982
4201 22:50:18.696671 tx_first_pass[0][1][12] = 970
4202 22:50:18.699782 tx_last_pass[0][1][12] = 995
4203 22:50:18.703625 tx_win_center[0][1][13] = 982
4204 22:50:18.706866 tx_first_pass[0][1][13] = 970
4205 22:50:18.709897 tx_last_pass[0][1][13] = 994
4206 22:50:18.709987 tx_win_center[0][1][14] = 984
4207 22:50:18.713337 tx_first_pass[0][1][14] = 971
4208 22:50:18.716163 tx_last_pass[0][1][14] = 997
4209 22:50:18.719803 tx_win_center[0][1][15] = 986
4210 22:50:18.722974 tx_first_pass[0][1][15] = 974
4211 22:50:18.726315 tx_last_pass[0][1][15] = 999
4212 22:50:18.726407 tx_win_center[1][0][0] = 995
4213 22:50:18.729687 tx_first_pass[1][0][0] = 983
4214 22:50:18.732662 tx_last_pass[1][0][0] = 1008
4215 22:50:18.736053 tx_win_center[1][0][1] = 994
4216 22:50:18.739130 tx_first_pass[1][0][1] = 982
4217 22:50:18.739248 tx_last_pass[1][0][1] = 1007
4218 22:50:18.742695 tx_win_center[1][0][2] = 992
4219 22:50:18.745835 tx_first_pass[1][0][2] = 979
4220 22:50:18.749124 tx_last_pass[1][0][2] = 1005
4221 22:50:18.749211 tx_win_center[1][0][3] = 989
4222 22:50:18.752375 tx_first_pass[1][0][3] = 977
4223 22:50:18.756094 tx_last_pass[1][0][3] = 1002
4224 22:50:18.758723 tx_win_center[1][0][4] = 994
4225 22:50:18.762229 tx_first_pass[1][0][4] = 983
4226 22:50:18.762322 tx_last_pass[1][0][4] = 1006
4227 22:50:18.765498 tx_win_center[1][0][5] = 995
4228 22:50:18.768597 tx_first_pass[1][0][5] = 983
4229 22:50:18.771898 tx_last_pass[1][0][5] = 1007
4230 22:50:18.775166 tx_win_center[1][0][6] = 994
4231 22:50:18.775296 tx_first_pass[1][0][6] = 982
4232 22:50:18.778361 tx_last_pass[1][0][6] = 1007
4233 22:50:18.781781 tx_win_center[1][0][7] = 994
4234 22:50:18.785050 tx_first_pass[1][0][7] = 982
4235 22:50:18.788511 tx_last_pass[1][0][7] = 1006
4236 22:50:18.788603 tx_win_center[1][0][8] = 985
4237 22:50:18.792017 tx_first_pass[1][0][8] = 974
4238 22:50:18.794830 tx_last_pass[1][0][8] = 997
4239 22:50:18.798547 tx_win_center[1][0][9] = 983
4240 22:50:18.801517 tx_first_pass[1][0][9] = 972
4241 22:50:18.801610 tx_last_pass[1][0][9] = 995
4242 22:50:18.805127 tx_win_center[1][0][10] = 987
4243 22:50:18.807913 tx_first_pass[1][0][10] = 975
4244 22:50:18.811544 tx_last_pass[1][0][10] = 999
4245 22:50:18.814604 tx_win_center[1][0][11] = 988
4246 22:50:18.818264 tx_first_pass[1][0][11] = 976
4247 22:50:18.818387 tx_last_pass[1][0][11] = 1000
4248 22:50:18.820926 tx_win_center[1][0][12] = 987
4249 22:50:18.824460 tx_first_pass[1][0][12] = 976
4250 22:50:18.827897 tx_last_pass[1][0][12] = 999
4251 22:50:18.830977 tx_win_center[1][0][13] = 988
4252 22:50:18.831100 tx_first_pass[1][0][13] = 976
4253 22:50:18.834324 tx_last_pass[1][0][13] = 1000
4254 22:50:18.837744 tx_win_center[1][0][14] = 987
4255 22:50:18.840647 tx_first_pass[1][0][14] = 976
4256 22:50:18.844074 tx_last_pass[1][0][14] = 999
4257 22:50:18.847014 tx_win_center[1][0][15] = 981
4258 22:50:18.847136 tx_first_pass[1][0][15] = 969
4259 22:50:18.850375 tx_last_pass[1][0][15] = 993
4260 22:50:18.854062 tx_win_center[1][1][0] = 995
4261 22:50:18.857009 tx_first_pass[1][1][0] = 983
4262 22:50:18.860432 tx_last_pass[1][1][0] = 1007
4263 22:50:18.860528 tx_win_center[1][1][1] = 993
4264 22:50:18.864154 tx_first_pass[1][1][1] = 981
4265 22:50:18.866821 tx_last_pass[1][1][1] = 1006
4266 22:50:18.870477 tx_win_center[1][1][2] = 991
4267 22:50:18.873586 tx_first_pass[1][1][2] = 978
4268 22:50:18.873679 tx_last_pass[1][1][2] = 1005
4269 22:50:18.876475 tx_win_center[1][1][3] = 989
4270 22:50:18.880199 tx_first_pass[1][1][3] = 977
4271 22:50:18.883681 tx_last_pass[1][1][3] = 1001
4272 22:50:18.886919 tx_win_center[1][1][4] = 993
4273 22:50:18.887016 tx_first_pass[1][1][4] = 980
4274 22:50:18.889852 tx_last_pass[1][1][4] = 1006
4275 22:50:18.892963 tx_win_center[1][1][5] = 994
4276 22:50:18.896506 tx_first_pass[1][1][5] = 982
4277 22:50:18.899859 tx_last_pass[1][1][5] = 1006
4278 22:50:18.899951 tx_win_center[1][1][6] = 993
4279 22:50:18.902944 tx_first_pass[1][1][6] = 981
4280 22:50:18.906102 tx_last_pass[1][1][6] = 1006
4281 22:50:18.909257 tx_win_center[1][1][7] = 993
4282 22:50:18.912819 tx_first_pass[1][1][7] = 981
4283 22:50:18.912912 tx_last_pass[1][1][7] = 1006
4284 22:50:18.915950 tx_win_center[1][1][8] = 986
4285 22:50:18.919496 tx_first_pass[1][1][8] = 975
4286 22:50:18.922538 tx_last_pass[1][1][8] = 997
4287 22:50:18.922631 tx_win_center[1][1][9] = 985
4288 22:50:18.926340 tx_first_pass[1][1][9] = 974
4289 22:50:18.929160 tx_last_pass[1][1][9] = 996
4290 22:50:18.932379 tx_win_center[1][1][10] = 988
4291 22:50:18.935987 tx_first_pass[1][1][10] = 976
4292 22:50:18.939135 tx_last_pass[1][1][10] = 1000
4293 22:50:18.939261 tx_win_center[1][1][11] = 988
4294 22:50:18.941932 tx_first_pass[1][1][11] = 976
4295 22:50:18.945851 tx_last_pass[1][1][11] = 1000
4296 22:50:18.948637 tx_win_center[1][1][12] = 988
4297 22:50:18.952385 tx_first_pass[1][1][12] = 977
4298 22:50:18.952478 tx_last_pass[1][1][12] = 999
4299 22:50:18.955042 tx_win_center[1][1][13] = 989
4300 22:50:18.958591 tx_first_pass[1][1][13] = 977
4301 22:50:18.961801 tx_last_pass[1][1][13] = 1001
4302 22:50:18.964988 tx_win_center[1][1][14] = 988
4303 22:50:18.968501 tx_first_pass[1][1][14] = 977
4304 22:50:18.968603 tx_last_pass[1][1][14] = 1000
4305 22:50:18.971816 tx_win_center[1][1][15] = 982
4306 22:50:18.974730 tx_first_pass[1][1][15] = 970
4307 22:50:18.978162 tx_last_pass[1][1][15] = 994
4308 22:50:18.978255 dump params rx window
4309 22:50:18.981796 rx_firspass[0][0][0] = 7
4310 22:50:18.984650 rx_lastpass[0][0][0] = 37
4311 22:50:18.988132 rx_firspass[0][0][1] = 8
4312 22:50:18.988223 rx_lastpass[0][0][1] = 36
4313 22:50:18.991429 rx_firspass[0][0][2] = 5
4314 22:50:18.994683 rx_lastpass[0][0][2] = 39
4315 22:50:18.994805 rx_firspass[0][0][3] = -3
4316 22:50:18.997814 rx_lastpass[0][0][3] = 31
4317 22:50:19.001331 rx_firspass[0][0][4] = 6
4318 22:50:19.004316 rx_lastpass[0][0][4] = 36
4319 22:50:19.004407 rx_firspass[0][0][5] = 3
4320 22:50:19.007621 rx_lastpass[0][0][5] = 33
4321 22:50:19.011084 rx_firspass[0][0][6] = 3
4322 22:50:19.011208 rx_lastpass[0][0][6] = 33
4323 22:50:19.013960 rx_firspass[0][0][7] = 4
4324 22:50:19.017824 rx_lastpass[0][0][7] = 36
4325 22:50:19.020607 rx_firspass[0][0][8] = -2
4326 22:50:19.020699 rx_lastpass[0][0][8] = 30
4327 22:50:19.023879 rx_firspass[0][0][9] = 1
4328 22:50:19.027180 rx_lastpass[0][0][9] = 32
4329 22:50:19.027319 rx_firspass[0][0][10] = 8
4330 22:50:19.030563 rx_lastpass[0][0][10] = 37
4331 22:50:19.034242 rx_firspass[0][0][11] = 0
4332 22:50:19.036874 rx_lastpass[0][0][11] = 30
4333 22:50:19.036986 rx_firspass[0][0][12] = 3
4334 22:50:19.040707 rx_lastpass[0][0][12] = 31
4335 22:50:19.043981 rx_firspass[0][0][13] = 1
4336 22:50:19.046849 rx_lastpass[0][0][13] = 31
4337 22:50:19.046942 rx_firspass[0][0][14] = 0
4338 22:50:19.050396 rx_lastpass[0][0][14] = 35
4339 22:50:19.053299 rx_firspass[0][0][15] = 3
4340 22:50:19.056599 rx_lastpass[0][0][15] = 36
4341 22:50:19.056692 rx_firspass[0][1][0] = 3
4342 22:50:19.060045 rx_lastpass[0][1][0] = 38
4343 22:50:19.063163 rx_firspass[0][1][1] = 4
4344 22:50:19.063280 rx_lastpass[0][1][1] = 38
4345 22:50:19.066711 rx_firspass[0][1][2] = 5
4346 22:50:19.070193 rx_lastpass[0][1][2] = 40
4347 22:50:19.073332 rx_firspass[0][1][3] = -2
4348 22:50:19.073424 rx_lastpass[0][1][3] = 31
4349 22:50:19.076199 rx_firspass[0][1][4] = 3
4350 22:50:19.079958 rx_lastpass[0][1][4] = 38
4351 22:50:19.080050 rx_firspass[0][1][5] = -1
4352 22:50:19.083030 rx_lastpass[0][1][5] = 34
4353 22:50:19.085917 rx_firspass[0][1][6] = 1
4354 22:50:19.089238 rx_lastpass[0][1][6] = 35
4355 22:50:19.089330 rx_firspass[0][1][7] = 3
4356 22:50:19.092656 rx_lastpass[0][1][7] = 37
4357 22:50:19.096182 rx_firspass[0][1][8] = -4
4358 22:50:19.096279 rx_lastpass[0][1][8] = 32
4359 22:50:19.099660 rx_firspass[0][1][9] = -2
4360 22:50:19.102652 rx_lastpass[0][1][9] = 34
4361 22:50:19.105873 rx_firspass[0][1][10] = 7
4362 22:50:19.105995 rx_lastpass[0][1][10] = 39
4363 22:50:19.109626 rx_firspass[0][1][11] = -2
4364 22:50:19.112226 rx_lastpass[0][1][11] = 32
4365 22:50:19.115912 rx_firspass[0][1][12] = 0
4366 22:50:19.116004 rx_lastpass[0][1][12] = 33
4367 22:50:19.119119 rx_firspass[0][1][13] = -1
4368 22:50:19.122656 rx_lastpass[0][1][13] = 33
4369 22:50:19.125486 rx_firspass[0][1][14] = 1
4370 22:50:19.125577 rx_lastpass[0][1][14] = 36
4371 22:50:19.128995 rx_firspass[0][1][15] = 4
4372 22:50:19.132179 rx_lastpass[0][1][15] = 37
4373 22:50:19.132271 rx_firspass[1][0][0] = 6
4374 22:50:19.135057 rx_lastpass[1][0][0] = 36
4375 22:50:19.138556 rx_firspass[1][0][1] = 5
4376 22:50:19.141787 rx_lastpass[1][0][1] = 36
4377 22:50:19.141894 rx_firspass[1][0][2] = 1
4378 22:50:19.145285 rx_lastpass[1][0][2] = 34
4379 22:50:19.148424 rx_firspass[1][0][3] = 1
4380 22:50:19.148515 rx_lastpass[1][0][3] = 30
4381 22:50:19.151809 rx_firspass[1][0][4] = 5
4382 22:50:19.155154 rx_lastpass[1][0][4] = 35
4383 22:50:19.157960 rx_firspass[1][0][5] = 9
4384 22:50:19.158052 rx_lastpass[1][0][5] = 38
4385 22:50:19.161273 rx_firspass[1][0][6] = 6
4386 22:50:19.164653 rx_lastpass[1][0][6] = 38
4387 22:50:19.164744 rx_firspass[1][0][7] = 5
4388 22:50:19.168079 rx_lastpass[1][0][7] = 34
4389 22:50:19.171575 rx_firspass[1][0][8] = 1
4390 22:50:19.174449 rx_lastpass[1][0][8] = 33
4391 22:50:19.174535 rx_firspass[1][0][9] = 0
4392 22:50:19.177854 rx_lastpass[1][0][9] = 31
4393 22:50:19.181281 rx_firspass[1][0][10] = 3
4394 22:50:19.181373 rx_lastpass[1][0][10] = 35
4395 22:50:19.184473 rx_firspass[1][0][11] = 4
4396 22:50:19.187441 rx_lastpass[1][0][11] = 36
4397 22:50:19.191053 rx_firspass[1][0][12] = 6
4398 22:50:19.191177 rx_lastpass[1][0][12] = 34
4399 22:50:19.194111 rx_firspass[1][0][13] = 6
4400 22:50:19.197601 rx_lastpass[1][0][13] = 35
4401 22:50:19.200457 rx_firspass[1][0][14] = 5
4402 22:50:19.200579 rx_lastpass[1][0][14] = 36
4403 22:50:19.204127 rx_firspass[1][0][15] = -3
4404 22:50:19.207324 rx_lastpass[1][0][15] = 29
4405 22:50:19.210502 rx_firspass[1][1][0] = 4
4406 22:50:19.210593 rx_lastpass[1][1][0] = 40
4407 22:50:19.213657 rx_firspass[1][1][1] = 3
4408 22:50:19.217170 rx_lastpass[1][1][1] = 39
4409 22:50:19.217262 rx_firspass[1][1][2] = 3
4410 22:50:19.220471 rx_lastpass[1][1][2] = 34
4411 22:50:19.223890 rx_firspass[1][1][3] = -2
4412 22:50:19.227088 rx_lastpass[1][1][3] = 33
4413 22:50:19.227209 rx_firspass[1][1][4] = 4
4414 22:50:19.230249 rx_lastpass[1][1][4] = 39
4415 22:50:19.233685 rx_firspass[1][1][5] = 6
4416 22:50:19.233777 rx_lastpass[1][1][5] = 40
4417 22:50:19.236671 rx_firspass[1][1][6] = 6
4418 22:50:19.239735 rx_lastpass[1][1][6] = 40
4419 22:50:19.243512 rx_firspass[1][1][7] = 3
4420 22:50:19.243608 rx_lastpass[1][1][7] = 38
4421 22:50:19.246482 rx_firspass[1][1][8] = -1
4422 22:50:19.249633 rx_lastpass[1][1][8] = 35
4423 22:50:19.249725 rx_firspass[1][1][9] = -3
4424 22:50:19.253329 rx_lastpass[1][1][9] = 33
4425 22:50:19.256429 rx_firspass[1][1][10] = 3
4426 22:50:19.259717 rx_lastpass[1][1][10] = 38
4427 22:50:19.259838 rx_firspass[1][1][11] = 3
4428 22:50:19.262835 rx_lastpass[1][1][11] = 38
4429 22:50:19.266295 rx_firspass[1][1][12] = 3
4430 22:50:19.269637 rx_lastpass[1][1][12] = 37
4431 22:50:19.269727 rx_firspass[1][1][13] = 4
4432 22:50:19.272504 rx_lastpass[1][1][13] = 39
4433 22:50:19.276023 rx_firspass[1][1][14] = 4
4434 22:50:19.279022 rx_lastpass[1][1][14] = 40
4435 22:50:19.279114 rx_firspass[1][1][15] = -4
4436 22:50:19.282302 rx_lastpass[1][1][15] = 31
4437 22:50:19.285727 dump params clk_delay
4438 22:50:19.285819 clk_delay[0] = -1
4439 22:50:19.289066 clk_delay[1] = 0
4440 22:50:19.289157 dump params dqs_delay
4441 22:50:19.292513 dqs_delay[0][0] = -1
4442 22:50:19.292605 dqs_delay[0][1] = 0
4443 22:50:19.295909 dqs_delay[1][0] = 0
4444 22:50:19.296035 dqs_delay[1][1] = -1
4445 22:50:19.298660 dump params delay_cell_unit = 744
4446 22:50:19.302002 dump source = 0x0
4447 22:50:19.305462 dump params frequency:1200
4448 22:50:19.305554 dump params rank number:2
4449 22:50:19.305626
4450 22:50:19.308781 dump params write leveling
4451 22:50:19.311904 write leveling[0][0][0] = 0x0
4452 22:50:19.314936 write leveling[0][0][1] = 0x0
4453 22:50:19.318664 write leveling[0][1][0] = 0x0
4454 22:50:19.318755 write leveling[0][1][1] = 0x0
4455 22:50:19.321633 write leveling[1][0][0] = 0x0
4456 22:50:19.324950 write leveling[1][0][1] = 0x0
4457 22:50:19.328527 write leveling[1][1][0] = 0x0
4458 22:50:19.331927 write leveling[1][1][1] = 0x0
4459 22:50:19.332018 dump params cbt_cs
4460 22:50:19.334726 cbt_cs[0][0] = 0x0
4461 22:50:19.334847 cbt_cs[0][1] = 0x0
4462 22:50:19.338110 cbt_cs[1][0] = 0x0
4463 22:50:19.338201 cbt_cs[1][1] = 0x0
4464 22:50:19.341554 dump params cbt_mr12
4465 22:50:19.344952 cbt_mr12[0][0] = 0x0
4466 22:50:19.345043 cbt_mr12[0][1] = 0x0
4467 22:50:19.347647 cbt_mr12[1][0] = 0x0
4468 22:50:19.347738 cbt_mr12[1][1] = 0x0
4469 22:50:19.351429 dump params tx window
4470 22:50:19.354673 tx_center_min[0][0][0] = 0
4471 22:50:19.354764 tx_center_max[0][0][0] = 0
4472 22:50:19.357603 tx_center_min[0][0][1] = 0
4473 22:50:19.360875 tx_center_max[0][0][1] = 0
4474 22:50:19.364187 tx_center_min[0][1][0] = 0
4475 22:50:19.364309 tx_center_max[0][1][0] = 0
4476 22:50:19.367823 tx_center_min[0][1][1] = 0
4477 22:50:19.370797 tx_center_max[0][1][1] = 0
4478 22:50:19.373999 tx_center_min[1][0][0] = 0
4479 22:50:19.374091 tx_center_max[1][0][0] = 0
4480 22:50:19.377626 tx_center_min[1][0][1] = 0
4481 22:50:19.380471 tx_center_max[1][0][1] = 0
4482 22:50:19.383970 tx_center_min[1][1][0] = 0
4483 22:50:19.384100 tx_center_max[1][1][0] = 0
4484 22:50:19.387032 tx_center_min[1][1][1] = 0
4485 22:50:19.390246 tx_center_max[1][1][1] = 0
4486 22:50:19.390338 dump params tx window
4487 22:50:19.393682 tx_win_center[0][0][0] = 0
4488 22:50:19.397252 tx_first_pass[0][0][0] = 0
4489 22:50:19.400414 tx_last_pass[0][0][0] = 0
4490 22:50:19.400506 tx_win_center[0][0][1] = 0
4491 22:50:19.403564 tx_first_pass[0][0][1] = 0
4492 22:50:19.406890 tx_last_pass[0][0][1] = 0
4493 22:50:19.410201 tx_win_center[0][0][2] = 0
4494 22:50:19.410308 tx_first_pass[0][0][2] = 0
4495 22:50:19.413470 tx_last_pass[0][0][2] = 0
4496 22:50:19.416356 tx_win_center[0][0][3] = 0
4497 22:50:19.420034 tx_first_pass[0][0][3] = 0
4498 22:50:19.420127 tx_last_pass[0][0][3] = 0
4499 22:50:19.423359 tx_win_center[0][0][4] = 0
4500 22:50:19.426486 tx_first_pass[0][0][4] = 0
4501 22:50:19.429571 tx_last_pass[0][0][4] = 0
4502 22:50:19.429693 tx_win_center[0][0][5] = 0
4503 22:50:19.432958 tx_first_pass[0][0][5] = 0
4504 22:50:19.436636 tx_last_pass[0][0][5] = 0
4505 22:50:19.436730 tx_win_center[0][0][6] = 0
4506 22:50:19.439435 tx_first_pass[0][0][6] = 0
4507 22:50:19.442936 tx_last_pass[0][0][6] = 0
4508 22:50:19.446279 tx_win_center[0][0][7] = 0
4509 22:50:19.446375 tx_first_pass[0][0][7] = 0
4510 22:50:19.449761 tx_last_pass[0][0][7] = 0
4511 22:50:19.452555 tx_win_center[0][0][8] = 0
4512 22:50:19.455953 tx_first_pass[0][0][8] = 0
4513 22:50:19.456045 tx_last_pass[0][0][8] = 0
4514 22:50:19.459139 tx_win_center[0][0][9] = 0
4515 22:50:19.462226 tx_first_pass[0][0][9] = 0
4516 22:50:19.465937 tx_last_pass[0][0][9] = 0
4517 22:50:19.466029 tx_win_center[0][0][10] = 0
4518 22:50:19.468899 tx_first_pass[0][0][10] = 0
4519 22:50:19.472055 tx_last_pass[0][0][10] = 0
4520 22:50:19.475927 tx_win_center[0][0][11] = 0
4521 22:50:19.476020 tx_first_pass[0][0][11] = 0
4522 22:50:19.478939 tx_last_pass[0][0][11] = 0
4523 22:50:19.482059 tx_win_center[0][0][12] = 0
4524 22:50:19.485237 tx_first_pass[0][0][12] = 0
4525 22:50:19.485325 tx_last_pass[0][0][12] = 0
4526 22:50:19.489053 tx_win_center[0][0][13] = 0
4527 22:50:19.491956 tx_first_pass[0][0][13] = 0
4528 22:50:19.495355 tx_last_pass[0][0][13] = 0
4529 22:50:19.495447 tx_win_center[0][0][14] = 0
4530 22:50:19.498803 tx_first_pass[0][0][14] = 0
4531 22:50:19.501685 tx_last_pass[0][0][14] = 0
4532 22:50:19.505182 tx_win_center[0][0][15] = 0
4533 22:50:19.508604 tx_first_pass[0][0][15] = 0
4534 22:50:19.508697 tx_last_pass[0][0][15] = 0
4535 22:50:19.511413 tx_win_center[0][1][0] = 0
4536 22:50:19.514792 tx_first_pass[0][1][0] = 0
4537 22:50:19.518112 tx_last_pass[0][1][0] = 0
4538 22:50:19.518205 tx_win_center[0][1][1] = 0
4539 22:50:19.521620 tx_first_pass[0][1][1] = 0
4540 22:50:19.524779 tx_last_pass[0][1][1] = 0
4541 22:50:19.524872 tx_win_center[0][1][2] = 0
4542 22:50:19.528103 tx_first_pass[0][1][2] = 0
4543 22:50:19.531454 tx_last_pass[0][1][2] = 0
4544 22:50:19.534837 tx_win_center[0][1][3] = 0
4545 22:50:19.534930 tx_first_pass[0][1][3] = 0
4546 22:50:19.537749 tx_last_pass[0][1][3] = 0
4547 22:50:19.540917 tx_win_center[0][1][4] = 0
4548 22:50:19.544289 tx_first_pass[0][1][4] = 0
4549 22:50:19.544381 tx_last_pass[0][1][4] = 0
4550 22:50:19.547609 tx_win_center[0][1][5] = 0
4551 22:50:19.551052 tx_first_pass[0][1][5] = 0
4552 22:50:19.554491 tx_last_pass[0][1][5] = 0
4553 22:50:19.554584 tx_win_center[0][1][6] = 0
4554 22:50:19.557810 tx_first_pass[0][1][6] = 0
4555 22:50:19.560700 tx_last_pass[0][1][6] = 0
4556 22:50:19.563945 tx_win_center[0][1][7] = 0
4557 22:50:19.564038 tx_first_pass[0][1][7] = 0
4558 22:50:19.567370 tx_last_pass[0][1][7] = 0
4559 22:50:19.570764 tx_win_center[0][1][8] = 0
4560 22:50:19.570857 tx_first_pass[0][1][8] = 0
4561 22:50:19.573879 tx_last_pass[0][1][8] = 0
4562 22:50:19.576952 tx_win_center[0][1][9] = 0
4563 22:50:19.580646 tx_first_pass[0][1][9] = 0
4564 22:50:19.580740 tx_last_pass[0][1][9] = 0
4565 22:50:19.583651 tx_win_center[0][1][10] = 0
4566 22:50:19.587017 tx_first_pass[0][1][10] = 0
4567 22:50:19.590468 tx_last_pass[0][1][10] = 0
4568 22:50:19.590565 tx_win_center[0][1][11] = 0
4569 22:50:19.593632 tx_first_pass[0][1][11] = 0
4570 22:50:19.596783 tx_last_pass[0][1][11] = 0
4571 22:50:19.600118 tx_win_center[0][1][12] = 0
4572 22:50:19.603723 tx_first_pass[0][1][12] = 0
4573 22:50:19.603816 tx_last_pass[0][1][12] = 0
4574 22:50:19.606714 tx_win_center[0][1][13] = 0
4575 22:50:19.609550 tx_first_pass[0][1][13] = 0
4576 22:50:19.612890 tx_last_pass[0][1][13] = 0
4577 22:50:19.612986 tx_win_center[0][1][14] = 0
4578 22:50:19.616486 tx_first_pass[0][1][14] = 0
4579 22:50:19.619979 tx_last_pass[0][1][14] = 0
4580 22:50:19.622777 tx_win_center[0][1][15] = 0
4581 22:50:19.622900 tx_first_pass[0][1][15] = 0
4582 22:50:19.626261 tx_last_pass[0][1][15] = 0
4583 22:50:19.629713 tx_win_center[1][0][0] = 0
4584 22:50:19.632785 tx_first_pass[1][0][0] = 0
4585 22:50:19.632879 tx_last_pass[1][0][0] = 0
4586 22:50:19.636113 tx_win_center[1][0][1] = 0
4587 22:50:19.639444 tx_first_pass[1][0][1] = 0
4588 22:50:19.642929 tx_last_pass[1][0][1] = 0
4589 22:50:19.643021 tx_win_center[1][0][2] = 0
4590 22:50:19.646146 tx_first_pass[1][0][2] = 0
4591 22:50:19.649202 tx_last_pass[1][0][2] = 0
4592 22:50:19.652557 tx_win_center[1][0][3] = 0
4593 22:50:19.652650 tx_first_pass[1][0][3] = 0
4594 22:50:19.655350 tx_last_pass[1][0][3] = 0
4595 22:50:19.658780 tx_win_center[1][0][4] = 0
4596 22:50:19.662243 tx_first_pass[1][0][4] = 0
4597 22:50:19.662336 tx_last_pass[1][0][4] = 0
4598 22:50:19.665187 tx_win_center[1][0][5] = 0
4599 22:50:19.668648 tx_first_pass[1][0][5] = 0
4600 22:50:19.668741 tx_last_pass[1][0][5] = 0
4601 22:50:19.672190 tx_win_center[1][0][6] = 0
4602 22:50:19.675666 tx_first_pass[1][0][6] = 0
4603 22:50:19.678687 tx_last_pass[1][0][6] = 0
4604 22:50:19.678780 tx_win_center[1][0][7] = 0
4605 22:50:19.682002 tx_first_pass[1][0][7] = 0
4606 22:50:19.685218 tx_last_pass[1][0][7] = 0
4607 22:50:19.688659 tx_win_center[1][0][8] = 0
4608 22:50:19.688752 tx_first_pass[1][0][8] = 0
4609 22:50:19.692001 tx_last_pass[1][0][8] = 0
4610 22:50:19.695147 tx_win_center[1][0][9] = 0
4611 22:50:19.698245 tx_first_pass[1][0][9] = 0
4612 22:50:19.698338 tx_last_pass[1][0][9] = 0
4613 22:50:19.701616 tx_win_center[1][0][10] = 0
4614 22:50:19.704900 tx_first_pass[1][0][10] = 0
4615 22:50:19.707899 tx_last_pass[1][0][10] = 0
4616 22:50:19.708017 tx_win_center[1][0][11] = 0
4617 22:50:19.711412 tx_first_pass[1][0][11] = 0
4618 22:50:19.714697 tx_last_pass[1][0][11] = 0
4619 22:50:19.718191 tx_win_center[1][0][12] = 0
4620 22:50:19.718284 tx_first_pass[1][0][12] = 0
4621 22:50:19.720995 tx_last_pass[1][0][12] = 0
4622 22:50:19.724334 tx_win_center[1][0][13] = 0
4623 22:50:19.727781 tx_first_pass[1][0][13] = 0
4624 22:50:19.727874 tx_last_pass[1][0][13] = 0
4625 22:50:19.730798 tx_win_center[1][0][14] = 0
4626 22:50:19.734077 tx_first_pass[1][0][14] = 0
4627 22:50:19.737594 tx_last_pass[1][0][14] = 0
4628 22:50:19.737686 tx_win_center[1][0][15] = 0
4629 22:50:19.741296 tx_first_pass[1][0][15] = 0
4630 22:50:19.744016 tx_last_pass[1][0][15] = 0
4631 22:50:19.747345 tx_win_center[1][1][0] = 0
4632 22:50:19.750470 tx_first_pass[1][1][0] = 0
4633 22:50:19.750562 tx_last_pass[1][1][0] = 0
4634 22:50:19.753892 tx_win_center[1][1][1] = 0
4635 22:50:19.756915 tx_first_pass[1][1][1] = 0
4636 22:50:19.757008 tx_last_pass[1][1][1] = 0
4637 22:50:19.760386 tx_win_center[1][1][2] = 0
4638 22:50:19.763506 tx_first_pass[1][1][2] = 0
4639 22:50:19.766810 tx_last_pass[1][1][2] = 0
4640 22:50:19.766903 tx_win_center[1][1][3] = 0
4641 22:50:19.770023 tx_first_pass[1][1][3] = 0
4642 22:50:19.773842 tx_last_pass[1][1][3] = 0
4643 22:50:19.776687 tx_win_center[1][1][4] = 0
4644 22:50:19.776781 tx_first_pass[1][1][4] = 0
4645 22:50:19.780038 tx_last_pass[1][1][4] = 0
4646 22:50:19.783215 tx_win_center[1][1][5] = 0
4647 22:50:19.786711 tx_first_pass[1][1][5] = 0
4648 22:50:19.786804 tx_last_pass[1][1][5] = 0
4649 22:50:19.789780 tx_win_center[1][1][6] = 0
4650 22:50:19.793129 tx_first_pass[1][1][6] = 0
4651 22:50:19.793223 tx_last_pass[1][1][6] = 0
4652 22:50:19.796422 tx_win_center[1][1][7] = 0
4653 22:50:19.799483 tx_first_pass[1][1][7] = 0
4654 22:50:19.803004 tx_last_pass[1][1][7] = 0
4655 22:50:19.803097 tx_win_center[1][1][8] = 0
4656 22:50:19.806377 tx_first_pass[1][1][8] = 0
4657 22:50:19.809417 tx_last_pass[1][1][8] = 0
4658 22:50:19.812626 tx_win_center[1][1][9] = 0
4659 22:50:19.812720 tx_first_pass[1][1][9] = 0
4660 22:50:19.815919 tx_last_pass[1][1][9] = 0
4661 22:50:19.819213 tx_win_center[1][1][10] = 0
4662 22:50:19.822680 tx_first_pass[1][1][10] = 0
4663 22:50:19.822792 tx_last_pass[1][1][10] = 0
4664 22:50:19.825668 tx_win_center[1][1][11] = 0
4665 22:50:19.828720 tx_first_pass[1][1][11] = 0
4666 22:50:19.832091 tx_last_pass[1][1][11] = 0
4667 22:50:19.832184 tx_win_center[1][1][12] = 0
4668 22:50:19.835663 tx_first_pass[1][1][12] = 0
4669 22:50:19.839170 tx_last_pass[1][1][12] = 0
4670 22:50:19.841849 tx_win_center[1][1][13] = 0
4671 22:50:19.845589 tx_first_pass[1][1][13] = 0
4672 22:50:19.845674 tx_last_pass[1][1][13] = 0
4673 22:50:19.848534 tx_win_center[1][1][14] = 0
4674 22:50:19.851837 tx_first_pass[1][1][14] = 0
4675 22:50:19.855165 tx_last_pass[1][1][14] = 0
4676 22:50:19.855283 tx_win_center[1][1][15] = 0
4677 22:50:19.858639 tx_first_pass[1][1][15] = 0
4678 22:50:19.861718 tx_last_pass[1][1][15] = 0
4679 22:50:19.865183 dump params rx window
4680 22:50:19.865276 rx_firspass[0][0][0] = 0
4681 22:50:19.868518 rx_lastpass[0][0][0] = 0
4682 22:50:19.871476 rx_firspass[0][0][1] = 0
4683 22:50:19.871568 rx_lastpass[0][0][1] = 0
4684 22:50:19.874980 rx_firspass[0][0][2] = 0
4685 22:50:19.878018 rx_lastpass[0][0][2] = 0
4686 22:50:19.878111 rx_firspass[0][0][3] = 0
4687 22:50:19.881139 rx_lastpass[0][0][3] = 0
4688 22:50:19.884787 rx_firspass[0][0][4] = 0
4689 22:50:19.887901 rx_lastpass[0][0][4] = 0
4690 22:50:19.887993 rx_firspass[0][0][5] = 0
4691 22:50:19.891110 rx_lastpass[0][0][5] = 0
4692 22:50:19.894152 rx_firspass[0][0][6] = 0
4693 22:50:19.894244 rx_lastpass[0][0][6] = 0
4694 22:50:19.897625 rx_firspass[0][0][7] = 0
4695 22:50:19.900875 rx_lastpass[0][0][7] = 0
4696 22:50:19.900968 rx_firspass[0][0][8] = 0
4697 22:50:19.904095 rx_lastpass[0][0][8] = 0
4698 22:50:19.907602 rx_firspass[0][0][9] = 0
4699 22:50:19.907694 rx_lastpass[0][0][9] = 0
4700 22:50:19.910899 rx_firspass[0][0][10] = 0
4701 22:50:19.913707 rx_lastpass[0][0][10] = 0
4702 22:50:19.917127 rx_firspass[0][0][11] = 0
4703 22:50:19.917220 rx_lastpass[0][0][11] = 0
4704 22:50:19.920632 rx_firspass[0][0][12] = 0
4705 22:50:19.924219 rx_lastpass[0][0][12] = 0
4706 22:50:19.927435 rx_firspass[0][0][13] = 0
4707 22:50:19.927527 rx_lastpass[0][0][13] = 0
4708 22:50:19.930380 rx_firspass[0][0][14] = 0
4709 22:50:19.933684 rx_lastpass[0][0][14] = 0
4710 22:50:19.933776 rx_firspass[0][0][15] = 0
4711 22:50:19.937302 rx_lastpass[0][0][15] = 0
4712 22:50:19.940346 rx_firspass[0][1][0] = 0
4713 22:50:19.943564 rx_lastpass[0][1][0] = 0
4714 22:50:19.943657 rx_firspass[0][1][1] = 0
4715 22:50:19.946917 rx_lastpass[0][1][1] = 0
4716 22:50:19.949839 rx_firspass[0][1][2] = 0
4717 22:50:19.949931 rx_lastpass[0][1][2] = 0
4718 22:50:19.953195 rx_firspass[0][1][3] = 0
4719 22:50:19.956809 rx_lastpass[0][1][3] = 0
4720 22:50:19.956901 rx_firspass[0][1][4] = 0
4721 22:50:19.959672 rx_lastpass[0][1][4] = 0
4722 22:50:19.963164 rx_firspass[0][1][5] = 0
4723 22:50:19.966064 rx_lastpass[0][1][5] = 0
4724 22:50:19.966156 rx_firspass[0][1][6] = 0
4725 22:50:19.969583 rx_lastpass[0][1][6] = 0
4726 22:50:19.972719 rx_firspass[0][1][7] = 0
4727 22:50:19.972812 rx_lastpass[0][1][7] = 0
4728 22:50:19.976162 rx_firspass[0][1][8] = 0
4729 22:50:19.979776 rx_lastpass[0][1][8] = 0
4730 22:50:19.979868 rx_firspass[0][1][9] = 0
4731 22:50:19.982614 rx_lastpass[0][1][9] = 0
4732 22:50:19.986030 rx_firspass[0][1][10] = 0
4733 22:50:19.989654 rx_lastpass[0][1][10] = 0
4734 22:50:19.989776 rx_firspass[0][1][11] = 0
4735 22:50:19.992861 rx_lastpass[0][1][11] = 0
4736 22:50:19.996180 rx_firspass[0][1][12] = 0
4737 22:50:19.996272 rx_lastpass[0][1][12] = 0
4738 22:50:19.998827 rx_firspass[0][1][13] = 0
4739 22:50:20.002587 rx_lastpass[0][1][13] = 0
4740 22:50:20.005387 rx_firspass[0][1][14] = 0
4741 22:50:20.005479 rx_lastpass[0][1][14] = 0
4742 22:50:20.009146 rx_firspass[0][1][15] = 0
4743 22:50:20.012637 rx_lastpass[0][1][15] = 0
4744 22:50:20.015298 rx_firspass[1][0][0] = 0
4745 22:50:20.015415 rx_lastpass[1][0][0] = 0
4746 22:50:20.018638 rx_firspass[1][0][1] = 0
4747 22:50:20.022223 rx_lastpass[1][0][1] = 0
4748 22:50:20.022316 rx_firspass[1][0][2] = 0
4749 22:50:20.025312 rx_lastpass[1][0][2] = 0
4750 22:50:20.028701 rx_firspass[1][0][3] = 0
4751 22:50:20.028794 rx_lastpass[1][0][3] = 0
4752 22:50:20.032100 rx_firspass[1][0][4] = 0
4753 22:50:20.034923 rx_lastpass[1][0][4] = 0
4754 22:50:20.035015 rx_firspass[1][0][5] = 0
4755 22:50:20.038128 rx_lastpass[1][0][5] = 0
4756 22:50:20.041460 rx_firspass[1][0][6] = 0
4757 22:50:20.045003 rx_lastpass[1][0][6] = 0
4758 22:50:20.045096 rx_firspass[1][0][7] = 0
4759 22:50:20.048417 rx_lastpass[1][0][7] = 0
4760 22:50:20.051146 rx_firspass[1][0][8] = 0
4761 22:50:20.051269 rx_lastpass[1][0][8] = 0
4762 22:50:20.054732 rx_firspass[1][0][9] = 0
4763 22:50:20.058005 rx_lastpass[1][0][9] = 0
4764 22:50:20.058098 rx_firspass[1][0][10] = 0
4765 22:50:20.061466 rx_lastpass[1][0][10] = 0
4766 22:50:20.064694 rx_firspass[1][0][11] = 0
4767 22:50:20.067998 rx_lastpass[1][0][11] = 0
4768 22:50:20.068091 rx_firspass[1][0][12] = 0
4769 22:50:20.070933 rx_lastpass[1][0][12] = 0
4770 22:50:20.074468 rx_firspass[1][0][13] = 0
4771 22:50:20.077872 rx_lastpass[1][0][13] = 0
4772 22:50:20.077965 rx_firspass[1][0][14] = 0
4773 22:50:20.080689 rx_lastpass[1][0][14] = 0
4774 22:50:20.084461 rx_firspass[1][0][15] = 0
4775 22:50:20.084554 rx_lastpass[1][0][15] = 0
4776 22:50:20.087357 rx_firspass[1][1][0] = 0
4777 22:50:20.090470 rx_lastpass[1][1][0] = 0
4778 22:50:20.093784 rx_firspass[1][1][1] = 0
4779 22:50:20.093896 rx_lastpass[1][1][1] = 0
4780 22:50:20.097392 rx_firspass[1][1][2] = 0
4781 22:50:20.100362 rx_lastpass[1][1][2] = 0
4782 22:50:20.100455 rx_firspass[1][1][3] = 0
4783 22:50:20.104062 rx_lastpass[1][1][3] = 0
4784 22:50:20.107462 rx_firspass[1][1][4] = 0
4785 22:50:20.107555 rx_lastpass[1][1][4] = 0
4786 22:50:20.110337 rx_firspass[1][1][5] = 0
4787 22:50:20.113980 rx_lastpass[1][1][5] = 0
4788 22:50:20.116699 rx_firspass[1][1][6] = 0
4789 22:50:20.116792 rx_lastpass[1][1][6] = 0
4790 22:50:20.120131 rx_firspass[1][1][7] = 0
4791 22:50:20.123654 rx_lastpass[1][1][7] = 0
4792 22:50:20.123746 rx_firspass[1][1][8] = 0
4793 22:50:20.126490 rx_lastpass[1][1][8] = 0
4794 22:50:20.129778 rx_firspass[1][1][9] = 0
4795 22:50:20.129871 rx_lastpass[1][1][9] = 0
4796 22:50:20.133112 rx_firspass[1][1][10] = 0
4797 22:50:20.136710 rx_lastpass[1][1][10] = 0
4798 22:50:20.139957 rx_firspass[1][1][11] = 0
4799 22:50:20.140049 rx_lastpass[1][1][11] = 0
4800 22:50:20.142833 rx_firspass[1][1][12] = 0
4801 22:50:20.146128 rx_lastpass[1][1][12] = 0
4802 22:50:20.146243 rx_firspass[1][1][13] = 0
4803 22:50:20.149809 rx_lastpass[1][1][13] = 0
4804 22:50:20.153379 rx_firspass[1][1][14] = 0
4805 22:50:20.156154 rx_lastpass[1][1][14] = 0
4806 22:50:20.156246 rx_firspass[1][1][15] = 0
4807 22:50:20.159508 rx_lastpass[1][1][15] = 0
4808 22:50:20.162490 dump params clk_delay
4809 22:50:20.162582 clk_delay[0] = 0
4810 22:50:20.166098 clk_delay[1] = 0
4811 22:50:20.166190 dump params dqs_delay
4812 22:50:20.169496 dqs_delay[0][0] = 0
4813 22:50:20.169589 dqs_delay[0][1] = 0
4814 22:50:20.172303 dqs_delay[1][0] = 0
4815 22:50:20.172405 dqs_delay[1][1] = 0
4816 22:50:20.175772 dump params delay_cell_unit = 744
4817 22:50:20.179196 dump source = 0x0
4818 22:50:20.182664 dump params frequency:800
4819 22:50:20.182756 dump params rank number:2
4820 22:50:20.182829
4821 22:50:20.185714 dump params write leveling
4822 22:50:20.188801 write leveling[0][0][0] = 0x0
4823 22:50:20.192108 write leveling[0][0][1] = 0x0
4824 22:50:20.195454 write leveling[0][1][0] = 0x0
4825 22:50:20.195546 write leveling[0][1][1] = 0x0
4826 22:50:20.198469 write leveling[1][0][0] = 0x0
4827 22:50:20.201717 write leveling[1][0][1] = 0x0
4828 22:50:20.204936 write leveling[1][1][0] = 0x0
4829 22:50:20.208438 write leveling[1][1][1] = 0x0
4830 22:50:20.208531 dump params cbt_cs
4831 22:50:20.211749 cbt_cs[0][0] = 0x0
4832 22:50:20.211870 cbt_cs[0][1] = 0x0
4833 22:50:20.214905 cbt_cs[1][0] = 0x0
4834 22:50:20.214997 cbt_cs[1][1] = 0x0
4835 22:50:20.218525 dump params cbt_mr12
4836 22:50:20.218624 cbt_mr12[0][0] = 0x0
4837 22:50:20.221695 cbt_mr12[0][1] = 0x0
4838 22:50:20.225059 cbt_mr12[1][0] = 0x0
4839 22:50:20.225151 cbt_mr12[1][1] = 0x0
4840 22:50:20.228014 dump params tx window
4841 22:50:20.231240 tx_center_min[0][0][0] = 0
4842 22:50:20.231333 tx_center_max[0][0][0] = 0
4843 22:50:20.234424 tx_center_min[0][0][1] = 0
4844 22:50:20.237894 tx_center_max[0][0][1] = 0
4845 22:50:20.241373 tx_center_min[0][1][0] = 0
4846 22:50:20.241465 tx_center_max[0][1][0] = 0
4847 22:50:20.244453 tx_center_min[0][1][1] = 0
4848 22:50:20.247520 tx_center_max[0][1][1] = 0
4849 22:50:20.250716 tx_center_min[1][0][0] = 0
4850 22:50:20.250808 tx_center_max[1][0][0] = 0
4851 22:50:20.254536 tx_center_min[1][0][1] = 0
4852 22:50:20.257255 tx_center_max[1][0][1] = 0
4853 22:50:20.260898 tx_center_min[1][1][0] = 0
4854 22:50:20.260995 tx_center_max[1][1][0] = 0
4855 22:50:20.264342 tx_center_min[1][1][1] = 0
4856 22:50:20.267415 tx_center_max[1][1][1] = 0
4857 22:50:20.267508 dump params tx window
4858 22:50:20.270238 tx_win_center[0][0][0] = 0
4859 22:50:20.274208 tx_first_pass[0][0][0] = 0
4860 22:50:20.277066 tx_last_pass[0][0][0] = 0
4861 22:50:20.277159 tx_win_center[0][0][1] = 0
4862 22:50:20.280482 tx_first_pass[0][0][1] = 0
4863 22:50:20.283440 tx_last_pass[0][0][1] = 0
4864 22:50:20.286756 tx_win_center[0][0][2] = 0
4865 22:50:20.286849 tx_first_pass[0][0][2] = 0
4866 22:50:20.290258 tx_last_pass[0][0][2] = 0
4867 22:50:20.293072 tx_win_center[0][0][3] = 0
4868 22:50:20.296410 tx_first_pass[0][0][3] = 0
4869 22:50:20.296506 tx_last_pass[0][0][3] = 0
4870 22:50:20.300199 tx_win_center[0][0][4] = 0
4871 22:50:20.303333 tx_first_pass[0][0][4] = 0
4872 22:50:20.306455 tx_last_pass[0][0][4] = 0
4873 22:50:20.306548 tx_win_center[0][0][5] = 0
4874 22:50:20.309468 tx_first_pass[0][0][5] = 0
4875 22:50:20.312941 tx_last_pass[0][0][5] = 0
4876 22:50:20.313036 tx_win_center[0][0][6] = 0
4877 22:50:20.316461 tx_first_pass[0][0][6] = 0
4878 22:50:20.319818 tx_last_pass[0][0][6] = 0
4879 22:50:20.322924 tx_win_center[0][0][7] = 0
4880 22:50:20.323047 tx_first_pass[0][0][7] = 0
4881 22:50:20.326104 tx_last_pass[0][0][7] = 0
4882 22:50:20.329423 tx_win_center[0][0][8] = 0
4883 22:50:20.332474 tx_first_pass[0][0][8] = 0
4884 22:50:20.332567 tx_last_pass[0][0][8] = 0
4885 22:50:20.336540 tx_win_center[0][0][9] = 0
4886 22:50:20.339061 tx_first_pass[0][0][9] = 0
4887 22:50:20.342490 tx_last_pass[0][0][9] = 0
4888 22:50:20.342586 tx_win_center[0][0][10] = 0
4889 22:50:20.345789 tx_first_pass[0][0][10] = 0
4890 22:50:20.349388 tx_last_pass[0][0][10] = 0
4891 22:50:20.352355 tx_win_center[0][0][11] = 0
4892 22:50:20.352448 tx_first_pass[0][0][11] = 0
4893 22:50:20.355384 tx_last_pass[0][0][11] = 0
4894 22:50:20.358761 tx_win_center[0][0][12] = 0
4895 22:50:20.362000 tx_first_pass[0][0][12] = 0
4896 22:50:20.362093 tx_last_pass[0][0][12] = 0
4897 22:50:20.365476 tx_win_center[0][0][13] = 0
4898 22:50:20.368834 tx_first_pass[0][0][13] = 0
4899 22:50:20.371669 tx_last_pass[0][0][13] = 0
4900 22:50:20.375060 tx_win_center[0][0][14] = 0
4901 22:50:20.375186 tx_first_pass[0][0][14] = 0
4902 22:50:20.378715 tx_last_pass[0][0][14] = 0
4903 22:50:20.381419 tx_win_center[0][0][15] = 0
4904 22:50:20.385160 tx_first_pass[0][0][15] = 0
4905 22:50:20.385284 tx_last_pass[0][0][15] = 0
4906 22:50:20.388597 tx_win_center[0][1][0] = 0
4907 22:50:20.391922 tx_first_pass[0][1][0] = 0
4908 22:50:20.394736 tx_last_pass[0][1][0] = 0
4909 22:50:20.394829 tx_win_center[0][1][1] = 0
4910 22:50:20.398120 tx_first_pass[0][1][1] = 0
4911 22:50:20.401459 tx_last_pass[0][1][1] = 0
4912 22:50:20.404347 tx_win_center[0][1][2] = 0
4913 22:50:20.404440 tx_first_pass[0][1][2] = 0
4914 22:50:20.407882 tx_last_pass[0][1][2] = 0
4915 22:50:20.411369 tx_win_center[0][1][3] = 0
4916 22:50:20.411462 tx_first_pass[0][1][3] = 0
4917 22:50:20.414821 tx_last_pass[0][1][3] = 0
4918 22:50:20.417446 tx_win_center[0][1][4] = 0
4919 22:50:20.420877 tx_first_pass[0][1][4] = 0
4920 22:50:20.420970 tx_last_pass[0][1][4] = 0
4921 22:50:20.424141 tx_win_center[0][1][5] = 0
4922 22:50:20.427120 tx_first_pass[0][1][5] = 0
4923 22:50:20.430591 tx_last_pass[0][1][5] = 0
4924 22:50:20.430684 tx_win_center[0][1][6] = 0
4925 22:50:20.434125 tx_first_pass[0][1][6] = 0
4926 22:50:20.436952 tx_last_pass[0][1][6] = 0
4927 22:50:20.440409 tx_win_center[0][1][7] = 0
4928 22:50:20.440503 tx_first_pass[0][1][7] = 0
4929 22:50:20.443835 tx_last_pass[0][1][7] = 0
4930 22:50:20.447059 tx_win_center[0][1][8] = 0
4931 22:50:20.450529 tx_first_pass[0][1][8] = 0
4932 22:50:20.450622 tx_last_pass[0][1][8] = 0
4933 22:50:20.453842 tx_win_center[0][1][9] = 0
4934 22:50:20.456744 tx_first_pass[0][1][9] = 0
4935 22:50:20.456837 tx_last_pass[0][1][9] = 0
4936 22:50:20.460119 tx_win_center[0][1][10] = 0
4937 22:50:20.463550 tx_first_pass[0][1][10] = 0
4938 22:50:20.466967 tx_last_pass[0][1][10] = 0
4939 22:50:20.469953 tx_win_center[0][1][11] = 0
4940 22:50:20.470045 tx_first_pass[0][1][11] = 0
4941 22:50:20.473493 tx_last_pass[0][1][11] = 0
4942 22:50:20.476329 tx_win_center[0][1][12] = 0
4943 22:50:20.479760 tx_first_pass[0][1][12] = 0
4944 22:50:20.479883 tx_last_pass[0][1][12] = 0
4945 22:50:20.483022 tx_win_center[0][1][13] = 0
4946 22:50:20.485935 tx_first_pass[0][1][13] = 0
4947 22:50:20.489554 tx_last_pass[0][1][13] = 0
4948 22:50:20.489647 tx_win_center[0][1][14] = 0
4949 22:50:20.493471 tx_first_pass[0][1][14] = 0
4950 22:50:20.496718 tx_last_pass[0][1][14] = 0
4951 22:50:20.499422 tx_win_center[0][1][15] = 0
4952 22:50:20.502373 tx_first_pass[0][1][15] = 0
4953 22:50:20.502466 tx_last_pass[0][1][15] = 0
4954 22:50:20.505822 tx_win_center[1][0][0] = 0
4955 22:50:20.509143 tx_first_pass[1][0][0] = 0
4956 22:50:20.509237 tx_last_pass[1][0][0] = 0
4957 22:50:20.512507 tx_win_center[1][0][1] = 0
4958 22:50:20.516037 tx_first_pass[1][0][1] = 0
4959 22:50:20.518839 tx_last_pass[1][0][1] = 0
4960 22:50:20.518962 tx_win_center[1][0][2] = 0
4961 22:50:20.522431 tx_first_pass[1][0][2] = 0
4962 22:50:20.525608 tx_last_pass[1][0][2] = 0
4963 22:50:20.528865 tx_win_center[1][0][3] = 0
4964 22:50:20.528961 tx_first_pass[1][0][3] = 0
4965 22:50:20.532204 tx_last_pass[1][0][3] = 0
4966 22:50:20.535032 tx_win_center[1][0][4] = 0
4967 22:50:20.538841 tx_first_pass[1][0][4] = 0
4968 22:50:20.538934 tx_last_pass[1][0][4] = 0
4969 22:50:20.541777 tx_win_center[1][0][5] = 0
4970 22:50:20.545140 tx_first_pass[1][0][5] = 0
4971 22:50:20.548644 tx_last_pass[1][0][5] = 0
4972 22:50:20.548737 tx_win_center[1][0][6] = 0
4973 22:50:20.551761 tx_first_pass[1][0][6] = 0
4974 22:50:20.555117 tx_last_pass[1][0][6] = 0
4975 22:50:20.555210 tx_win_center[1][0][7] = 0
4976 22:50:20.557996 tx_first_pass[1][0][7] = 0
4977 22:50:20.561476 tx_last_pass[1][0][7] = 0
4978 22:50:20.565122 tx_win_center[1][0][8] = 0
4979 22:50:20.565215 tx_first_pass[1][0][8] = 0
4980 22:50:20.568251 tx_last_pass[1][0][8] = 0
4981 22:50:20.571383 tx_win_center[1][0][9] = 0
4982 22:50:20.574593 tx_first_pass[1][0][9] = 0
4983 22:50:20.574688 tx_last_pass[1][0][9] = 0
4984 22:50:20.577838 tx_win_center[1][0][10] = 0
4985 22:50:20.581305 tx_first_pass[1][0][10] = 0
4986 22:50:20.584219 tx_last_pass[1][0][10] = 0
4987 22:50:20.584314 tx_win_center[1][0][11] = 0
4988 22:50:20.587539 tx_first_pass[1][0][11] = 0
4989 22:50:20.591110 tx_last_pass[1][0][11] = 0
4990 22:50:20.594062 tx_win_center[1][0][12] = 0
4991 22:50:20.594157 tx_first_pass[1][0][12] = 0
4992 22:50:20.597421 tx_last_pass[1][0][12] = 0
4993 22:50:20.600934 tx_win_center[1][0][13] = 0
4994 22:50:20.604014 tx_first_pass[1][0][13] = 0
4995 22:50:20.607533 tx_last_pass[1][0][13] = 0
4996 22:50:20.607628 tx_win_center[1][0][14] = 0
4997 22:50:20.611136 tx_first_pass[1][0][14] = 0
4998 22:50:20.613674 tx_last_pass[1][0][14] = 0
4999 22:50:20.617103 tx_win_center[1][0][15] = 0
5000 22:50:20.617197 tx_first_pass[1][0][15] = 0
5001 22:50:20.620774 tx_last_pass[1][0][15] = 0
5002 22:50:20.623883 tx_win_center[1][1][0] = 0
5003 22:50:20.627352 tx_first_pass[1][1][0] = 0
5004 22:50:20.627446 tx_last_pass[1][1][0] = 0
5005 22:50:20.630132 tx_win_center[1][1][1] = 0
5006 22:50:20.633609 tx_first_pass[1][1][1] = 0
5007 22:50:20.637047 tx_last_pass[1][1][1] = 0
5008 22:50:20.637141 tx_win_center[1][1][2] = 0
5009 22:50:20.639931 tx_first_pass[1][1][2] = 0
5010 22:50:20.643462 tx_last_pass[1][1][2] = 0
5011 22:50:20.643556 tx_win_center[1][1][3] = 0
5012 22:50:20.646588 tx_first_pass[1][1][3] = 0
5013 22:50:20.649890 tx_last_pass[1][1][3] = 0
5014 22:50:20.653736 tx_win_center[1][1][4] = 0
5015 22:50:20.653830 tx_first_pass[1][1][4] = 0
5016 22:50:20.656467 tx_last_pass[1][1][4] = 0
5017 22:50:20.659920 tx_win_center[1][1][5] = 0
5018 22:50:20.663033 tx_first_pass[1][1][5] = 0
5019 22:50:20.663162 tx_last_pass[1][1][5] = 0
5020 22:50:20.666248 tx_win_center[1][1][6] = 0
5021 22:50:20.669726 tx_first_pass[1][1][6] = 0
5022 22:50:20.673055 tx_last_pass[1][1][6] = 0
5023 22:50:20.673153 tx_win_center[1][1][7] = 0
5024 22:50:20.675957 tx_first_pass[1][1][7] = 0
5025 22:50:20.679658 tx_last_pass[1][1][7] = 0
5026 22:50:20.682470 tx_win_center[1][1][8] = 0
5027 22:50:20.682572 tx_first_pass[1][1][8] = 0
5028 22:50:20.685926 tx_last_pass[1][1][8] = 0
5029 22:50:20.689267 tx_win_center[1][1][9] = 0
5030 22:50:20.692712 tx_first_pass[1][1][9] = 0
5031 22:50:20.692806 tx_last_pass[1][1][9] = 0
5032 22:50:20.695553 tx_win_center[1][1][10] = 0
5033 22:50:20.699090 tx_first_pass[1][1][10] = 0
5034 22:50:20.702104 tx_last_pass[1][1][10] = 0
5035 22:50:20.702222 tx_win_center[1][1][11] = 0
5036 22:50:20.705304 tx_first_pass[1][1][11] = 0
5037 22:50:20.708842 tx_last_pass[1][1][11] = 0
5038 22:50:20.712328 tx_win_center[1][1][12] = 0
5039 22:50:20.712423 tx_first_pass[1][1][12] = 0
5040 22:50:20.715650 tx_last_pass[1][1][12] = 0
5041 22:50:20.718644 tx_win_center[1][1][13] = 0
5042 22:50:20.722309 tx_first_pass[1][1][13] = 0
5043 22:50:20.722403 tx_last_pass[1][1][13] = 0
5044 22:50:20.725006 tx_win_center[1][1][14] = 0
5045 22:50:20.728391 tx_first_pass[1][1][14] = 0
5046 22:50:20.731953 tx_last_pass[1][1][14] = 0
5047 22:50:20.732047 tx_win_center[1][1][15] = 0
5048 22:50:20.734732 tx_first_pass[1][1][15] = 0
5049 22:50:20.738071 tx_last_pass[1][1][15] = 0
5050 22:50:20.741661 dump params rx window
5051 22:50:20.741754 rx_firspass[0][0][0] = 0
5052 22:50:20.745163 rx_lastpass[0][0][0] = 0
5053 22:50:20.747936 rx_firspass[0][0][1] = 0
5054 22:50:20.748029 rx_lastpass[0][0][1] = 0
5055 22:50:20.751379 rx_firspass[0][0][2] = 0
5056 22:50:20.754453 rx_lastpass[0][0][2] = 0
5057 22:50:20.754552 rx_firspass[0][0][3] = 0
5058 22:50:20.757726 rx_lastpass[0][0][3] = 0
5059 22:50:20.760908 rx_firspass[0][0][4] = 0
5060 22:50:20.764311 rx_lastpass[0][0][4] = 0
5061 22:50:20.764404 rx_firspass[0][0][5] = 0
5062 22:50:20.767552 rx_lastpass[0][0][5] = 0
5063 22:50:20.771110 rx_firspass[0][0][6] = 0
5064 22:50:20.771204 rx_lastpass[0][0][6] = 0
5065 22:50:20.774077 rx_firspass[0][0][7] = 0
5066 22:50:20.777417 rx_lastpass[0][0][7] = 0
5067 22:50:20.777511 rx_firspass[0][0][8] = 0
5068 22:50:20.780723 rx_lastpass[0][0][8] = 0
5069 22:50:20.784157 rx_firspass[0][0][9] = 0
5070 22:50:20.787493 rx_lastpass[0][0][9] = 0
5071 22:50:20.787587 rx_firspass[0][0][10] = 0
5072 22:50:20.791011 rx_lastpass[0][0][10] = 0
5073 22:50:20.793921 rx_firspass[0][0][11] = 0
5074 22:50:20.794015 rx_lastpass[0][0][11] = 0
5075 22:50:20.797019 rx_firspass[0][0][12] = 0
5076 22:50:20.800657 rx_lastpass[0][0][12] = 0
5077 22:50:20.803855 rx_firspass[0][0][13] = 0
5078 22:50:20.803948 rx_lastpass[0][0][13] = 0
5079 22:50:20.806736 rx_firspass[0][0][14] = 0
5080 22:50:20.810089 rx_lastpass[0][0][14] = 0
5081 22:50:20.810183 rx_firspass[0][0][15] = 0
5082 22:50:20.813415 rx_lastpass[0][0][15] = 0
5083 22:50:20.817005 rx_firspass[0][1][0] = 0
5084 22:50:20.820086 rx_lastpass[0][1][0] = 0
5085 22:50:20.820180 rx_firspass[0][1][1] = 0
5086 22:50:20.823397 rx_lastpass[0][1][1] = 0
5087 22:50:20.826700 rx_firspass[0][1][2] = 0
5088 22:50:20.826796 rx_lastpass[0][1][2] = 0
5089 22:50:20.830706 rx_firspass[0][1][3] = 0
5090 22:50:20.833298 rx_lastpass[0][1][3] = 0
5091 22:50:20.833392 rx_firspass[0][1][4] = 0
5092 22:50:20.836458 rx_lastpass[0][1][4] = 0
5093 22:50:20.839673 rx_firspass[0][1][5] = 0
5094 22:50:20.843088 rx_lastpass[0][1][5] = 0
5095 22:50:20.843181 rx_firspass[0][1][6] = 0
5096 22:50:20.846365 rx_lastpass[0][1][6] = 0
5097 22:50:20.849681 rx_firspass[0][1][7] = 0
5098 22:50:20.849774 rx_lastpass[0][1][7] = 0
5099 22:50:20.853251 rx_firspass[0][1][8] = 0
5100 22:50:20.856334 rx_lastpass[0][1][8] = 0
5101 22:50:20.856427 rx_firspass[0][1][9] = 0
5102 22:50:20.859137 rx_lastpass[0][1][9] = 0
5103 22:50:20.862428 rx_firspass[0][1][10] = 0
5104 22:50:20.865942 rx_lastpass[0][1][10] = 0
5105 22:50:20.866036 rx_firspass[0][1][11] = 0
5106 22:50:20.868957 rx_lastpass[0][1][11] = 0
5107 22:50:20.872535 rx_firspass[0][1][12] = 0
5108 22:50:20.875648 rx_lastpass[0][1][12] = 0
5109 22:50:20.875771 rx_firspass[0][1][13] = 0
5110 22:50:20.879019 rx_lastpass[0][1][13] = 0
5111 22:50:20.882368 rx_firspass[0][1][14] = 0
5112 22:50:20.882462 rx_lastpass[0][1][14] = 0
5113 22:50:20.885556 rx_firspass[0][1][15] = 0
5114 22:50:20.888666 rx_lastpass[0][1][15] = 0
5115 22:50:20.892104 rx_firspass[1][0][0] = 0
5116 22:50:20.892198 rx_lastpass[1][0][0] = 0
5117 22:50:20.895102 rx_firspass[1][0][1] = 0
5118 22:50:20.898701 rx_lastpass[1][0][1] = 0
5119 22:50:20.898794 rx_firspass[1][0][2] = 0
5120 22:50:20.902008 rx_lastpass[1][0][2] = 0
5121 22:50:20.905046 rx_firspass[1][0][3] = 0
5122 22:50:20.905139 rx_lastpass[1][0][3] = 0
5123 22:50:20.908242 rx_firspass[1][0][4] = 0
5124 22:50:20.911620 rx_lastpass[1][0][4] = 0
5125 22:50:20.915095 rx_firspass[1][0][5] = 0
5126 22:50:20.915231 rx_lastpass[1][0][5] = 0
5127 22:50:20.918026 rx_firspass[1][0][6] = 0
5128 22:50:20.921495 rx_lastpass[1][0][6] = 0
5129 22:50:20.921617 rx_firspass[1][0][7] = 0
5130 22:50:20.925043 rx_lastpass[1][0][7] = 0
5131 22:50:20.927971 rx_firspass[1][0][8] = 0
5132 22:50:20.928092 rx_lastpass[1][0][8] = 0
5133 22:50:20.931124 rx_firspass[1][0][9] = 0
5134 22:50:20.934546 rx_lastpass[1][0][9] = 0
5135 22:50:20.938267 rx_firspass[1][0][10] = 0
5136 22:50:20.938387 rx_lastpass[1][0][10] = 0
5137 22:50:20.941046 rx_firspass[1][0][11] = 0
5138 22:50:20.944351 rx_lastpass[1][0][11] = 0
5139 22:50:20.944470 rx_firspass[1][0][12] = 0
5140 22:50:20.947494 rx_lastpass[1][0][12] = 0
5141 22:50:20.951008 rx_firspass[1][0][13] = 0
5142 22:50:20.954447 rx_lastpass[1][0][13] = 0
5143 22:50:20.954572 rx_firspass[1][0][14] = 0
5144 22:50:20.957408 rx_lastpass[1][0][14] = 0
5145 22:50:20.960997 rx_firspass[1][0][15] = 0
5146 22:50:20.964060 rx_lastpass[1][0][15] = 0
5147 22:50:20.964179 rx_firspass[1][1][0] = 0
5148 22:50:20.967486 rx_lastpass[1][1][0] = 0
5149 22:50:20.970261 rx_firspass[1][1][1] = 0
5150 22:50:20.970387 rx_lastpass[1][1][1] = 0
5151 22:50:20.973470 rx_firspass[1][1][2] = 0
5152 22:50:20.977197 rx_lastpass[1][1][2] = 0
5153 22:50:20.977329 rx_firspass[1][1][3] = 0
5154 22:50:20.980261 rx_lastpass[1][1][3] = 0
5155 22:50:20.983630 rx_firspass[1][1][4] = 0
5156 22:50:20.983759 rx_lastpass[1][1][4] = 0
5157 22:50:20.987099 rx_firspass[1][1][5] = 0
5158 22:50:20.990213 rx_lastpass[1][1][5] = 0
5159 22:50:20.993393 rx_firspass[1][1][6] = 0
5160 22:50:20.993520 rx_lastpass[1][1][6] = 0
5161 22:50:20.996608 rx_firspass[1][1][7] = 0
5162 22:50:21.000007 rx_lastpass[1][1][7] = 0
5163 22:50:21.000160 rx_firspass[1][1][8] = 0
5164 22:50:21.003602 rx_lastpass[1][1][8] = 0
5165 22:50:21.006438 rx_firspass[1][1][9] = 0
5166 22:50:21.006581 rx_lastpass[1][1][9] = 0
5167 22:50:21.009640 rx_firspass[1][1][10] = 0
5168 22:50:21.012964 rx_lastpass[1][1][10] = 0
5169 22:50:21.016542 rx_firspass[1][1][11] = 0
5170 22:50:21.016660 rx_lastpass[1][1][11] = 0
5171 22:50:21.019837 rx_firspass[1][1][12] = 0
5172 22:50:21.022590 rx_lastpass[1][1][12] = 0
5173 22:50:21.025972 rx_firspass[1][1][13] = 0
5174 22:50:21.026105 rx_lastpass[1][1][13] = 0
5175 22:50:21.029737 rx_firspass[1][1][14] = 0
5176 22:50:21.032724 rx_lastpass[1][1][14] = 0
5177 22:50:21.032846 rx_firspass[1][1][15] = 0
5178 22:50:21.035869 rx_lastpass[1][1][15] = 0
5179 22:50:21.039289 dump params clk_delay
5180 22:50:21.039411 clk_delay[0] = 0
5181 22:50:21.042782 clk_delay[1] = 0
5182 22:50:21.042894 dump params dqs_delay
5183 22:50:21.046067 dqs_delay[0][0] = 0
5184 22:50:21.046189 dqs_delay[0][1] = 0
5185 22:50:21.048881 dqs_delay[1][0] = 0
5186 22:50:21.052987 dqs_delay[1][1] = 0
5187 22:50:21.053104 dump params delay_cell_unit = 744
5188 22:50:21.055622 mt_set_emi_preloader end
5189 22:50:21.062345 [mt_mem_init] dram size: 0x100000000, rank number: 2
5190 22:50:21.065206 [complex_mem_test] start addr:0x40000000, len:20480
5191 22:50:21.102285 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5192 22:50:21.108310 [complex_mem_test] start addr:0x80000000, len:20480
5193 22:50:21.144122 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5194 22:50:21.150633 [complex_mem_test] start addr:0xc0000000, len:20480
5195 22:50:21.186388 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5196 22:50:21.193305 [complex_mem_test] start addr:0x56000000, len:8192
5197 22:50:21.209671 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5198 22:50:21.209812 ddr_geometry:1
5199 22:50:21.216391 [complex_mem_test] start addr:0x80000000, len:8192
5200 22:50:21.233775 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5201 22:50:21.237091 dram_init: dram init end (result: 0)
5202 22:50:21.243376 Successfully loaded DRAM blobs and ran DRAM calibration
5203 22:50:21.253196 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5204 22:50:21.253314 CBMEM:
5205 22:50:21.256483 IMD: root @ 00000000fffff000 254 entries.
5206 22:50:21.259673 IMD: root @ 00000000ffffec00 62 entries.
5207 22:50:21.266339 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5208 22:50:21.272993 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5209 22:50:21.275969 in-header: 03 a1 00 00 08 00 00 00
5210 22:50:21.279635 in-data: 84 60 60 10 00 00 00 00
5211 22:50:21.282636 Chrome EC: clear events_b mask to 0x0000000020004000
5212 22:50:21.289170 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5213 22:50:21.293455 in-header: 03 fd 00 00 00 00 00 00
5214 22:50:21.296503 in-data:
5215 22:50:21.299830 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5216 22:50:21.303102 CBFS @ 21000 size 3d4000
5217 22:50:21.306251 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5218 22:50:21.309373 CBFS: Locating 'fallback/ramstage'
5219 22:50:21.312999 CBFS: Found @ offset 10d40 size d563
5220 22:50:21.335661 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5221 22:50:21.347809 Accumulated console time in romstage 13538 ms
5222 22:50:21.347943
5223 22:50:21.348052
5224 22:50:21.357538 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5225 22:50:21.360460 ARM64: Exception handlers installed.
5226 22:50:21.360584 ARM64: Testing exception
5227 22:50:21.364293 ARM64: Done test exception
5228 22:50:21.367078 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5229 22:50:21.370263 Manufacturer: ef
5230 22:50:21.376951 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5231 22:50:21.380470 WARNING: RO_VPD is uninitialized or empty.
5232 22:50:21.383372 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5233 22:50:21.387212 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5234 22:50:21.397621 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
5235 22:50:21.401009 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5236 22:50:21.406938 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5237 22:50:21.407033 Enumerating buses...
5238 22:50:21.413280 Show all devs... Before device enumeration.
5239 22:50:21.413414 Root Device: enabled 1
5240 22:50:21.416793 CPU_CLUSTER: 0: enabled 1
5241 22:50:21.419838 CPU: 00: enabled 1
5242 22:50:21.419934 Compare with tree...
5243 22:50:21.423542 Root Device: enabled 1
5244 22:50:21.426250 CPU_CLUSTER: 0: enabled 1
5245 22:50:21.426374 CPU: 00: enabled 1
5246 22:50:21.429937 Root Device scanning...
5247 22:50:21.433211 root_dev_scan_bus for Root Device
5248 22:50:21.433305 CPU_CLUSTER: 0 enabled
5249 22:50:21.436396 root_dev_scan_bus for Root Device done
5250 22:50:21.442813 scan_bus: scanning of bus Root Device took 10690 usecs
5251 22:50:21.442933 done
5252 22:50:21.446130 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5253 22:50:21.449741 Allocating resources...
5254 22:50:21.452783 Reading resources...
5255 22:50:21.456316 Root Device read_resources bus 0 link: 0
5256 22:50:21.459633 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5257 22:50:21.462595 CPU: 00 missing read_resources
5258 22:50:21.466246 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5259 22:50:21.468929 Root Device read_resources bus 0 link: 0 done
5260 22:50:21.472311 Done reading resources.
5261 22:50:21.479164 Show resources in subtree (Root Device)...After reading.
5262 22:50:21.482264 Root Device child on link 0 CPU_CLUSTER: 0
5263 22:50:21.485700 CPU_CLUSTER: 0 child on link 0 CPU: 00
5264 22:50:21.492009 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5265 22:50:21.495301 CPU: 00
5266 22:50:21.495395 Setting resources...
5267 22:50:21.502005 Root Device assign_resources, bus 0 link: 0
5268 22:50:21.505499 CPU_CLUSTER: 0 missing set_resources
5269 22:50:21.508612 Root Device assign_resources, bus 0 link: 0
5270 22:50:21.508728 Done setting resources.
5271 22:50:21.515023 Show resources in subtree (Root Device)...After assigning values.
5272 22:50:21.518491 Root Device child on link 0 CPU_CLUSTER: 0
5273 22:50:21.522342 CPU_CLUSTER: 0 child on link 0 CPU: 00
5274 22:50:21.531213 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5275 22:50:21.531359 CPU: 00
5276 22:50:21.534611 Done allocating resources.
5277 22:50:21.541540 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5278 22:50:21.541672 Enabling resources...
5279 22:50:21.541782 done.
5280 22:50:21.547954 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5281 22:50:21.548078 Initializing devices...
5282 22:50:21.551431 Root Device init ...
5283 22:50:21.554215 mainboard_init: Starting display init.
5284 22:50:21.557791 ADC[4]: Raw value=76192 ID=0
5285 22:50:21.579663 anx7625_power_on_init: Init interface.
5286 22:50:21.583100 anx7625_disable_pd_protocol: Disabled PD feature.
5287 22:50:21.589882 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5288 22:50:21.646895 anx7625_start_dp_work: Secure OCM version=00
5289 22:50:21.650178 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5290 22:50:21.670632 sp_tx_get_edid_block: EDID Block = 1
5291 22:50:21.784580 Extracted contents:
5292 22:50:21.787617 header: 00 ff ff ff ff ff ff 00
5293 22:50:21.790928 serial number: 06 af 5c 14 00 00 00 00 00 1a
5294 22:50:21.794612 version: 01 04
5295 22:50:21.797660 basic params: 95 1a 0e 78 02
5296 22:50:21.800969 chroma info: 99 85 95 55 56 92 28 22 50 54
5297 22:50:21.804244 established: 00 00 00
5298 22:50:21.810477 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5299 22:50:21.817514 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5300 22:50:21.823795 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5301 22:50:21.826859 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5302 22:50:21.833452 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5303 22:50:21.836731 extensions: 00
5304 22:50:21.836816 checksum: ae
5305 22:50:21.836910
5306 22:50:21.843468 Manufacturer: AUO Model 145c Serial Number 0
5307 22:50:21.843598 Made week 0 of 2016
5308 22:50:21.846664 EDID version: 1.4
5309 22:50:21.846790 Digital display
5310 22:50:21.849937 6 bits per primary color channel
5311 22:50:21.853159 DisplayPort interface
5312 22:50:21.856262 Maximum image size: 26 cm x 14 cm
5313 22:50:21.856388 Gamma: 220%
5314 22:50:21.856497 Check DPMS levels
5315 22:50:21.859704 Supported color formats: RGB 4:4:4
5316 22:50:21.866457 First detailed timing is preferred timing
5317 22:50:21.866581 Established timings supported:
5318 22:50:21.870081 Standard timings supported:
5319 22:50:21.872834 Detailed timings
5320 22:50:21.876253 Hex of detail: ce1d56ea50001a3030204600009010000018
5321 22:50:21.883155 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5322 22:50:21.885756 0556 0586 05a6 0640 hborder 0
5323 22:50:21.889453 0300 0304 030a 031a vborder 0
5324 22:50:21.892654 -hsync -vsync
5325 22:50:21.892746 Did detailed timing
5326 22:50:21.899454 Hex of detail: 0000000f0000000000000000000000000020
5327 22:50:21.902275 Manufacturer-specified data, tag 15
5328 22:50:21.905759 Hex of detail: 000000fe0041554f0a202020202020202020
5329 22:50:21.909206 ASCII string: AUO
5330 22:50:21.911935 Hex of detail: 000000fe004231313658414230312e34200a
5331 22:50:21.915071 ASCII string: B116XAB01.4
5332 22:50:21.915196 Checksum
5333 22:50:21.918782 Checksum: 0xae (valid)
5334 22:50:21.921893 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5335 22:50:21.925190 DSI data_rate: 457800000 bps
5336 22:50:21.932001 anx7625_parse_edid: set default k value to 0x3d for panel
5337 22:50:21.934967 anx7625_parse_edid: pixelclock(76300).
5338 22:50:21.938363 hactive(1366), hsync(32), hfp(48), hbp(154)
5339 22:50:21.941730 vactive(768), vsync(6), vfp(4), vbp(16)
5340 22:50:21.944677 anx7625_dsi_config: config dsi.
5341 22:50:21.953265 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5342 22:50:21.973605 anx7625_dsi_config: success to config DSI
5343 22:50:21.977242 anx7625_dp_start: MIPI phy setup OK.
5344 22:50:21.980117 [SSUSB] Setting up USB HOST controller...
5345 22:50:21.983426 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5346 22:50:21.986912 [SSUSB] phy power-on done.
5347 22:50:21.990355 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5348 22:50:21.993419 in-header: 03 fc 01 00 00 00 00 00
5349 22:50:21.993546 in-data:
5350 22:50:22.000302 handle_proto3_response: EC response with error code: 1
5351 22:50:22.000392 SPM: pcm index = 1
5352 22:50:22.006993 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5353 22:50:22.007113 CBFS @ 21000 size 3d4000
5354 22:50:22.013065 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5355 22:50:22.016974 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5356 22:50:22.019839 CBFS: Found @ offset 1e7c0 size 1026
5357 22:50:22.027354 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5358 22:50:22.030225 SPM: binary array size = 2988
5359 22:50:22.033835 SPM: version = pcm_allinone_v1.17.2_20180829
5360 22:50:22.037162 SPM binary loaded in 32 msecs
5361 22:50:22.045260 spm_kick_im_to_fetch: ptr = 000000004021eec2
5362 22:50:22.048742 spm_kick_im_to_fetch: len = 2988
5363 22:50:22.048861 SPM: spm_kick_pcm_to_run
5364 22:50:22.052072 SPM: spm_kick_pcm_to_run done
5365 22:50:22.055134 SPM: spm_init done in 52 msecs
5366 22:50:22.058825 Root Device init finished in 505638 usecs
5367 22:50:22.061931 CPU_CLUSTER: 0 init ...
5368 22:50:22.071333 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5369 22:50:22.074723 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5370 22:50:22.077851 CBFS @ 21000 size 3d4000
5371 22:50:22.081219 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5372 22:50:22.084591 CBFS: Locating 'sspm.bin'
5373 22:50:22.088009 CBFS: Found @ offset 208c0 size 41cb
5374 22:50:22.098692 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5375 22:50:22.106405 CPU_CLUSTER: 0 init finished in 42804 usecs
5376 22:50:22.106534 Devices initialized
5377 22:50:22.109846 Show all devs... After init.
5378 22:50:22.113240 Root Device: enabled 1
5379 22:50:22.113365 CPU_CLUSTER: 0: enabled 1
5380 22:50:22.116080 CPU: 00: enabled 1
5381 22:50:22.119499 BS: BS_DEV_INIT times (ms): entry 0 run 235 exit 0
5382 22:50:22.125921 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5383 22:50:22.129570 ELOG: NV offset 0x558000 size 0x1000
5384 22:50:22.132406 read SPI 0x558000 0x1000: 1258 us, 3255 KB/s, 26.040 Mbps
5385 22:50:22.139157 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5386 22:50:22.145560 ELOG: Event(17) added with size 13 at 2024-05-07 22:50:22 UTC
5387 22:50:22.148800 out: cmd=0x121: 03 db 21 01 00 00 00 00
5388 22:50:22.152114 in-header: 03 09 00 00 2c 00 00 00
5389 22:50:22.165344 in-data: 02 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 43 a0 07 00 06 80 00 00 7d a4 38 00 06 80 00 00 8e bf 07 00 06 80 00 00 d8 8f 53 00
5390 22:50:22.168585 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5391 22:50:22.171804 in-header: 03 19 00 00 08 00 00 00
5392 22:50:22.174931 in-data: a2 e0 47 00 13 00 00 00
5393 22:50:22.178867 Chrome EC: UHEPI supported
5394 22:50:22.185110 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5395 22:50:22.188289 in-header: 03 e1 00 00 08 00 00 00
5396 22:50:22.191484 in-data: 84 20 60 10 00 00 00 00
5397 22:50:22.194373 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5398 22:50:22.201209 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5399 22:50:22.204601 in-header: 03 e1 00 00 08 00 00 00
5400 22:50:22.208055 in-data: 84 20 60 10 00 00 00 00
5401 22:50:22.214114 ELOG: Event(A1) added with size 10 at 2024-05-07 22:50:22 UTC
5402 22:50:22.220651 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5403 22:50:22.224343 ELOG: Event(A0) added with size 9 at 2024-05-07 22:50:22 UTC
5404 22:50:22.230570 elog_add_boot_reason: Logged dev mode boot
5405 22:50:22.230657 Finalize devices...
5406 22:50:22.233677 Devices finalized
5407 22:50:22.237392 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5408 22:50:22.240485 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5409 22:50:22.246598 ELOG: Event(91) added with size 10 at 2024-05-07 22:50:22 UTC
5410 22:50:22.250002 Writing coreboot table at 0xffeda000
5411 22:50:22.253394 0. 0000000000114000-000000000011efff: RAMSTAGE
5412 22:50:22.260196 1. 0000000040000000-000000004023cfff: RAMSTAGE
5413 22:50:22.263432 2. 000000004023d000-00000000545fffff: RAM
5414 22:50:22.266671 3. 0000000054600000-000000005465ffff: BL31
5415 22:50:22.269906 4. 0000000054660000-00000000ffed9fff: RAM
5416 22:50:22.276151 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5417 22:50:22.279617 6. 0000000100000000-000000013fffffff: RAM
5418 22:50:22.283068 Passing 5 GPIOs to payload:
5419 22:50:22.286124 NAME | PORT | POLARITY | VALUE
5420 22:50:22.292928 write protect | 0x00000096 | low | high
5421 22:50:22.296782 EC in RW | 0x000000b1 | high | undefined
5422 22:50:22.299350 EC interrupt | 0x00000097 | low | undefined
5423 22:50:22.305793 TPM interrupt | 0x00000099 | high | undefined
5424 22:50:22.309158 speaker enable | 0x000000af | high | undefined
5425 22:50:22.312378 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5426 22:50:22.316050 in-header: 03 f7 00 00 02 00 00 00
5427 22:50:22.318851 in-data: 04 00
5428 22:50:22.318964 Board ID: 4
5429 22:50:22.322202 ADC[3]: Raw value=215404 ID=1
5430 22:50:22.322299 RAM code: 1
5431 22:50:22.325521 SKU ID: 16
5432 22:50:22.328889 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5433 22:50:22.332260 CBFS @ 21000 size 3d4000
5434 22:50:22.335459 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5435 22:50:22.341896 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 1f4a
5436 22:50:22.345043 coreboot table: 940 bytes.
5437 22:50:22.348255 IMD ROOT 0. 00000000fffff000 00001000
5438 22:50:22.351551 IMD SMALL 1. 00000000ffffe000 00001000
5439 22:50:22.355162 CONSOLE 2. 00000000fffde000 00020000
5440 22:50:22.357960 FMAP 3. 00000000fffdd000 0000047c
5441 22:50:22.361440 TIME STAMP 4. 00000000fffdc000 00000910
5442 22:50:22.368356 RAMOOPS 5. 00000000ffedc000 00100000
5443 22:50:22.371098 COREBOOT 6. 00000000ffeda000 00002000
5444 22:50:22.371206 IMD small region:
5445 22:50:22.374536 IMD ROOT 0. 00000000ffffec00 00000400
5446 22:50:22.378040 VBOOT WORK 1. 00000000ffffeb00 00000100
5447 22:50:22.384810 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5448 22:50:22.387922 VPD 3. 00000000ffffea60 0000006c
5449 22:50:22.391243 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5450 22:50:22.397349 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5451 22:50:22.400614 in-header: 03 e1 00 00 08 00 00 00
5452 22:50:22.404012 in-data: 84 20 60 10 00 00 00 00
5453 22:50:22.411176 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5454 22:50:22.411289 CBFS @ 21000 size 3d4000
5455 22:50:22.417414 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5456 22:50:22.420412 CBFS: Locating 'fallback/payload'
5457 22:50:22.427912 CBFS: Found @ offset dc040 size 439a0
5458 22:50:22.515979 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5459 22:50:22.519152 Checking segment from ROM address 0x0000000040003a00
5460 22:50:22.525773 Checking segment from ROM address 0x0000000040003a1c
5461 22:50:22.528995 Loading segment from ROM address 0x0000000040003a00
5462 22:50:22.532261 code (compression=0)
5463 22:50:22.542035 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5464 22:50:22.548600 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5465 22:50:22.551799 it's not compressed!
5466 22:50:22.555276 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5467 22:50:22.561520 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5468 22:50:22.570140 Loading segment from ROM address 0x0000000040003a1c
5469 22:50:22.573297 Entry Point 0x0000000080000000
5470 22:50:22.573428 Loaded segments
5471 22:50:22.580185 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5472 22:50:22.583798 Jumping to boot code at 0000000080000000(00000000ffeda000)
5473 22:50:22.592793 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5474 22:50:22.599467 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5475 22:50:22.599565 CBFS @ 21000 size 3d4000
5476 22:50:22.606270 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5477 22:50:22.609668 CBFS: Locating 'fallback/bl31'
5478 22:50:22.612528 CBFS: Found @ offset 36dc0 size 5820
5479 22:50:22.623918 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5480 22:50:22.627406 Checking segment from ROM address 0x0000000040003a00
5481 22:50:22.634111 Checking segment from ROM address 0x0000000040003a1c
5482 22:50:22.636907 Loading segment from ROM address 0x0000000040003a00
5483 22:50:22.640357 code (compression=1)
5484 22:50:22.650162 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5485 22:50:22.656648 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5486 22:50:22.656771 using LZMA
5487 22:50:22.666029 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5488 22:50:22.672729 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5489 22:50:22.675552 Loading segment from ROM address 0x0000000040003a1c
5490 22:50:22.678994 Entry Point 0x0000000054601000
5491 22:50:22.679117 Loaded segments
5492 22:50:22.682224 NOTICE: MT8183 bl31_setup
5493 22:50:22.689638 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5494 22:50:22.693047 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5495 22:50:22.696282 INFO: [DEVAPC] dump DEVAPC registers:
5496 22:50:22.706196 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5497 22:50:22.712439 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5498 22:50:22.722780 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5499 22:50:22.729188 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5500 22:50:22.738510 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5501 22:50:22.745487 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5502 22:50:22.754848 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5503 22:50:22.761569 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5504 22:50:22.771525 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5505 22:50:22.778065 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5506 22:50:22.787453 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5507 22:50:22.794439 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5508 22:50:22.803951 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5509 22:50:22.810341 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5510 22:50:22.817153 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5511 22:50:22.826915 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5512 22:50:22.833847 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5513 22:50:22.840165 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5514 22:50:22.847014 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5515 22:50:22.856345 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5516 22:50:22.862850 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5517 22:50:22.869386 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5518 22:50:22.872613 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5519 22:50:22.876248 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5520 22:50:22.879509 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5521 22:50:22.882926 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5522 22:50:22.886229 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5523 22:50:22.892594 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5524 22:50:22.896123 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5525 22:50:22.899062 WARNING: region 0:
5526 22:50:22.902168 WARNING: apc:0x168, sa:0x0, ea:0xfff
5527 22:50:22.905806 WARNING: region 1:
5528 22:50:22.909145 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5529 22:50:22.909268 WARNING: region 2:
5530 22:50:22.912313 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5531 22:50:22.915481 WARNING: region 3:
5532 22:50:22.918819 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5533 22:50:22.922040 WARNING: region 4:
5534 22:50:22.925529 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5535 22:50:22.925658 WARNING: region 5:
5536 22:50:22.928376 WARNING: apc:0x0, sa:0x0, ea:0x0
5537 22:50:22.931824 WARNING: region 6:
5538 22:50:22.935550 WARNING: apc:0x0, sa:0x0, ea:0x0
5539 22:50:22.935669 WARNING: region 7:
5540 22:50:22.938511 WARNING: apc:0x0, sa:0x0, ea:0x0
5541 22:50:22.944984 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5542 22:50:22.948484 INFO: SPM: enable SPMC mode
5543 22:50:22.951297 NOTICE: spm_boot_init() start
5544 22:50:22.955268 NOTICE: spm_boot_init() end
5545 22:50:22.957977 INFO: BL31: Initializing runtime services
5546 22:50:22.964685 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5547 22:50:22.968209 INFO: BL31: Preparing for EL3 exit to normal world
5548 22:50:22.971530 INFO: Entry point address = 0x80000000
5549 22:50:22.974330 INFO: SPSR = 0x8
5550 22:50:22.995911
5551 22:50:22.996042
5552 22:50:22.996151
5553 22:50:22.999472 Starting depthcharge on Juniper...
5554 22:50:22.999595
5555 22:50:23.000212 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5556 22:50:23.000364 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
5557 22:50:23.000497 Setting prompt string to ['jacuzzi:']
5558 22:50:23.000628 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:26)
5559 22:50:23.002545 vboot_handoff: creating legacy vboot_handoff structure
5560 22:50:23.002667
5561 22:50:23.005901 ec_init(0): CrosEC protocol v3 supported (544, 544)
5562 22:50:23.008998
5563 22:50:23.009117 Wipe memory regions:
5564 22:50:23.009235
5565 22:50:23.012534 [0x00000040000000, 0x00000054600000)
5566 22:50:23.055659
5567 22:50:23.055799 [0x00000054660000, 0x00000080000000)
5568 22:50:23.147001
5569 22:50:23.147165 [0x000000811994a0, 0x000000ffeda000)
5570 22:50:23.406214
5571 22:50:23.406414 [0x00000100000000, 0x00000140000000)
5572 22:50:23.539118
5573 22:50:23.542007 Initializing XHCI USB controller at 0x11200000.
5574 22:50:23.565071
5575 22:50:23.568347 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5576 22:50:23.568466
5577 22:50:23.568576
5578 22:50:23.568680
5579 22:50:23.569021 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5581 22:50:23.669418 jacuzzi: tftpboot 192.168.201.1 13683657/tftp-deploy-59_93ml8/kernel/image.itb 13683657/tftp-deploy-59_93ml8/kernel/cmdline
5582 22:50:23.669610 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5583 22:50:23.669744 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
5584 22:50:23.673620 tftpboot 192.168.201.1 13683657/tftp-deploy-59_93ml8/kernel/image.itp-deploy-59_93ml8/kernel/cmdline
5585 22:50:23.673760
5586 22:50:23.673868 Waiting for link
5587 22:50:24.078966
5588 22:50:24.079154 R8152: Initializing
5589 22:50:24.079265
5590 22:50:24.082775 Version 9 (ocp_data = 6010)
5591 22:50:24.082897
5592 22:50:24.085805 R8152: Done initializing
5593 22:50:24.085925
5594 22:50:24.086031 Adding net device
5595 22:50:24.471440
5596 22:50:24.471629 done.
5597 22:50:24.471760
5598 22:50:24.471876 MAC: 00:e0:4c:78:85:cb
5599 22:50:24.471992
5600 22:50:24.474309 Sending DHCP discover... done.
5601 22:50:24.474439
5602 22:50:24.477698 Waiting for reply... done.
5603 22:50:24.477832
5604 22:50:24.481255 Sending DHCP request... done.
5605 22:50:24.481381
5606 22:50:24.486195 Waiting for reply... done.
5607 22:50:24.486328
5608 22:50:24.486439 My ip is 192.168.201.22
5609 22:50:24.486558
5610 22:50:24.489379 The DHCP server ip is 192.168.201.1
5611 22:50:24.489494
5612 22:50:24.495842 TFTP server IP predefined by user: 192.168.201.1
5613 22:50:24.495973
5614 22:50:24.502125 Bootfile predefined by user: 13683657/tftp-deploy-59_93ml8/kernel/image.itb
5615 22:50:24.502256
5616 22:50:24.505647 Sending tftp read request... done.
5617 22:50:24.505777
5618 22:50:24.509644 Waiting for the transfer...
5619 22:50:24.509774
5620 22:50:24.765501 00000000 ################################################################
5621 22:50:24.765696
5622 22:50:25.022603 00080000 ################################################################
5623 22:50:25.022796
5624 22:50:25.279833 00100000 ################################################################
5625 22:50:25.280015
5626 22:50:25.536532 00180000 ################################################################
5627 22:50:25.536732
5628 22:50:25.793790 00200000 ################################################################
5629 22:50:25.793980
5630 22:50:26.051739 00280000 ################################################################
5631 22:50:26.051897
5632 22:50:26.310282 00300000 ################################################################
5633 22:50:26.310447
5634 22:50:26.568946 00380000 ################################################################
5635 22:50:26.569138
5636 22:50:26.826286 00400000 ################################################################
5637 22:50:26.826441
5638 22:50:27.083160 00480000 ################################################################
5639 22:50:27.083324
5640 22:50:27.340483 00500000 ################################################################
5641 22:50:27.340632
5642 22:50:27.597608 00580000 ################################################################
5643 22:50:27.597761
5644 22:50:27.855129 00600000 ################################################################
5645 22:50:27.855290
5646 22:50:28.117574 00680000 ################################################################
5647 22:50:28.117728
5648 22:50:28.383333 00700000 ################################################################
5649 22:50:28.383481
5650 22:50:28.655588 00780000 ################################################################
5651 22:50:28.655774
5652 22:50:28.914898 00800000 ################################################################
5653 22:50:28.915050
5654 22:50:29.174133 00880000 ################################################################
5655 22:50:29.174286
5656 22:50:29.442142 00900000 ################################################################
5657 22:50:29.442298
5658 22:50:29.718853 00980000 ################################################################
5659 22:50:29.719005
5660 22:50:29.981610 00a00000 ################################################################
5661 22:50:29.981766
5662 22:50:30.246037 00a80000 ################################################################
5663 22:50:30.246187
5664 22:50:30.503640 00b00000 ################################################################
5665 22:50:30.503790
5666 22:50:30.766032 00b80000 ################################################################
5667 22:50:30.766182
5668 22:50:31.025909 00c00000 ################################################################
5669 22:50:31.026048
5670 22:50:31.283668 00c80000 ################################################################
5671 22:50:31.283817
5672 22:50:31.543136 00d00000 ################################################################
5673 22:50:31.543293
5674 22:50:31.805004 00d80000 ################################################################
5675 22:50:31.805148
5676 22:50:32.077368 00e00000 ################################################################
5677 22:50:32.077520
5678 22:50:32.367089 00e80000 ################################################################
5679 22:50:32.367268
5680 22:50:32.632949 00f00000 ################################################################
5681 22:50:32.633101
5682 22:50:32.912786 00f80000 ################################################################
5683 22:50:32.912933
5684 22:50:33.173732 01000000 ################################################################
5685 22:50:33.173875
5686 22:50:33.429705 01080000 ################################################################
5687 22:50:33.429888
5688 22:50:33.689176 01100000 ################################################################
5689 22:50:33.689327
5690 22:50:33.963989 01180000 ################################################################
5691 22:50:33.964135
5692 22:50:34.224584 01200000 ################################################################
5693 22:50:34.224730
5694 22:50:34.494391 01280000 ################################################################
5695 22:50:34.494534
5696 22:50:34.754147 01300000 ################################################################
5697 22:50:34.754333
5698 22:50:35.016957 01380000 ################################################################
5699 22:50:35.017103
5700 22:50:35.292692 01400000 ################################################################
5701 22:50:35.292847
5702 22:50:35.562522 01480000 ################################################################
5703 22:50:35.562682
5704 22:50:35.835327 01500000 ################################################################
5705 22:50:35.835474
5706 22:50:36.097673 01580000 ################################################################
5707 22:50:36.097832
5708 22:50:36.363083 01600000 ################################################################
5709 22:50:36.363240
5710 22:50:36.636944 01680000 ################################################################
5711 22:50:36.637099
5712 22:50:36.900510 01700000 ################################################################
5713 22:50:36.900665
5714 22:50:37.163886 01780000 ################################################################
5715 22:50:37.164045
5716 22:50:37.433559 01800000 ################################################################
5717 22:50:37.433719
5718 22:50:37.706471 01880000 ################################################################
5719 22:50:37.706619
5720 22:50:37.987268 01900000 ################################################################
5721 22:50:37.987416
5722 22:50:38.259803 01980000 ################################################################
5723 22:50:38.259951
5724 22:50:38.525901 01a00000 ################################################################
5725 22:50:38.526054
5726 22:50:38.781957 01a80000 ################################################################
5727 22:50:38.782107
5728 22:50:39.052343 01b00000 ################################################################
5729 22:50:39.052513
5730 22:50:39.315649 01b80000 ################################################################
5731 22:50:39.315828
5732 22:50:39.586130 01c00000 ################################################################
5733 22:50:39.586323
5734 22:50:39.850623 01c80000 ################################################################
5735 22:50:39.850779
5736 22:50:40.112780 01d00000 ################################################################
5737 22:50:40.112967
5738 22:50:40.378749 01d80000 ################################################################
5739 22:50:40.378942
5740 22:50:40.572002 01e00000 ################################################ done.
5741 22:50:40.572186
5742 22:50:40.575405 The bootfile was 31845882 bytes long.
5743 22:50:40.575509
5744 22:50:40.578646 Sending tftp read request... done.
5745 22:50:40.578763
5746 22:50:40.582249 Waiting for the transfer...
5747 22:50:40.582366
5748 22:50:40.582484 00000000 # done.
5749 22:50:40.582594
5750 22:50:40.591653 Command line loaded dynamically from TFTP file: 13683657/tftp-deploy-59_93ml8/kernel/cmdline
5751 22:50:40.591774
5752 22:50:40.618494 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683657/extract-nfsrootfs-slg4lw9x,tcp,hard ip=dhcp tftpserverip=192.168.201.1
5753 22:50:40.618642
5754 22:50:40.618755 Loading FIT.
5755 22:50:40.618873
5756 22:50:40.621082 Image ramdisk-1 has 18726583 bytes.
5757 22:50:40.621200
5758 22:50:40.624518 Image fdt-1 has 57695 bytes.
5759 22:50:40.624646
5760 22:50:40.627823 Image kernel-1 has 13059555 bytes.
5761 22:50:40.627939
5762 22:50:40.634104 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5763 22:50:40.634231
5764 22:50:40.647776 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5765 22:50:40.647900
5766 22:50:40.654189 Choosing best match conf-1 for compat google,juniper-sku16.
5767 22:50:40.654310
5768 22:50:40.661623 Connected to device vid:did:rid of 1ae0:0028:00
5769 22:50:40.668757
5770 22:50:40.671911 tpm_get_response: command 0x17b, return code 0x0
5771 22:50:40.672020
5772 22:50:40.675791 tpm_cleanup: add release locality here.
5773 22:50:40.675915
5774 22:50:40.678773 Shutting down all USB controllers.
5775 22:50:40.678887
5776 22:50:40.681531 Removing current net device
5777 22:50:40.681656
5778 22:50:40.684836 Exiting depthcharge with code 4 at timestamp: 34850260
5779 22:50:40.684958
5780 22:50:40.692091 LZMA decompressing kernel-1 to 0x80193568
5781 22:50:40.692195
5782 22:50:40.695546 LZMA decompressing kernel-1 to 0x40000000
5783 22:50:42.552850
5784 22:50:42.553024 jumping to kernel
5785 22:50:42.553967 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
5786 22:50:42.554122 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
5787 22:50:42.554241 Setting prompt string to ['Linux version [0-9]']
5788 22:50:42.554356 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5789 22:50:42.554474 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5790 22:50:42.628051
5791 22:50:42.631298 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5792 22:50:42.634566 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
5793 22:50:42.634707 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5794 22:50:42.634824 Setting prompt string to []
5795 22:50:42.634952 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5796 22:50:42.635070 Using line separator: #'\n'#
5797 22:50:42.635177 No login prompt set.
5798 22:50:42.635299 Parsing kernel messages
5799 22:50:42.635398 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5800 22:50:42.635610 [login-action] Waiting for messages, (timeout 00:04:06)
5801 22:50:42.635725 Waiting using forced prompt support (timeout 00:02:03)
5802 22:50:42.654279 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
5803 22:50:42.657720 [ 0.000000] random: crng init done
5804 22:50:42.664457 [ 0.000000] Machine model: Google juniper sku16 board
5805 22:50:42.667147 [ 0.000000] efi: UEFI not found.
5806 22:50:42.674038 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5807 22:50:42.683752 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5808 22:50:42.690582 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5809 22:50:42.693579 [ 0.000000] printk: bootconsole [mtk8250] enabled
5810 22:50:42.703048 [ 0.000000] NUMA: No NUMA configuration found
5811 22:50:42.709309 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5812 22:50:42.716222 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5813 22:50:42.716357 [ 0.000000] Zone ranges:
5814 22:50:42.722533 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5815 22:50:42.725864 [ 0.000000] DMA32 empty
5816 22:50:42.732653 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5817 22:50:42.735326 [ 0.000000] Movable zone start for each node
5818 22:50:42.741987 [ 0.000000] Early memory node ranges
5819 22:50:42.745249 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5820 22:50:42.751905 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5821 22:50:42.758471 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5822 22:50:42.764935 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5823 22:50:42.771907 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5824 22:50:42.778095 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5825 22:50:42.795299 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5826 22:50:42.801781 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5827 22:50:42.808475 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5828 22:50:42.812037 [ 0.000000] psci: probing for conduit method from DT.
5829 22:50:42.818107 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5830 22:50:42.821833 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5831 22:50:42.828123 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5832 22:50:42.831432 [ 0.000000] psci: SMC Calling Convention v1.1
5833 22:50:42.838083 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5834 22:50:42.841338 [ 0.000000] Detected VIPT I-cache on CPU0
5835 22:50:42.848185 [ 0.000000] CPU features: detected: GIC system register CPU interface
5836 22:50:42.854510 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5837 22:50:42.861564 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5838 22:50:42.867391 [ 0.000000] CPU features: detected: ARM erratum 845719
5839 22:50:42.870902 [ 0.000000] alternatives: applying boot alternatives
5840 22:50:42.877454 [ 0.000000] Fallback order for Node 0: 0
5841 22:50:42.884267 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5842 22:50:42.887068 [ 0.000000] Policy zone: Normal
5843 22:50:42.913345 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683657/extract-nfsrootfs-slg4lw9x,tcp,hard ip=dhcp tftpserverip=192.168.201.1
5844 22:50:42.926524 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5845 22:50:42.932722 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5846 22:50:42.943067 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5847 22:50:42.949223 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5848 22:50:42.952724 <6>[ 0.000000] software IO TLB: area num 8.
5849 22:50:42.978556 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5850 22:50:43.036256 <6>[ 0.000000] Memory: 3896912K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 261552K reserved, 32768K cma-reserved)
5851 22:50:43.043540 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5852 22:50:43.049575 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5853 22:50:43.052398 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5854 22:50:43.058898 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5855 22:50:43.065924 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5856 22:50:43.072231 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5857 22:50:43.078885 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5858 22:50:43.085164 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5859 22:50:43.091953 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5860 22:50:43.101635 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5861 22:50:43.108303 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5862 22:50:43.111674 <6>[ 0.000000] GICv3: 640 SPIs implemented
5863 22:50:43.114521 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5864 22:50:43.121220 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5865 22:50:43.124702 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5866 22:50:43.130836 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5867 22:50:43.144108 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5868 22:50:43.157457 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5869 22:50:43.163787 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5870 22:50:43.173284 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5871 22:50:43.186889 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5872 22:50:43.193157 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5873 22:50:43.200647 <6>[ 0.009476] Console: colour dummy device 80x25
5874 22:50:43.203539 <6>[ 0.014514] printk: console [tty1] enabled
5875 22:50:43.216933 <6>[ 0.018904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5876 22:50:43.220266 <6>[ 0.029368] pid_max: default: 32768 minimum: 301
5877 22:50:43.226552 <6>[ 0.034250] LSM: Security Framework initializing
5878 22:50:43.233108 <6>[ 0.039165] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5879 22:50:43.239583 <6>[ 0.046789] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5880 22:50:43.246310 <4>[ 0.055655] cacheinfo: Unable to detect cache hierarchy for CPU 0
5881 22:50:43.256584 <6>[ 0.062284] cblist_init_generic: Setting adjustable number of callback queues.
5882 22:50:43.263008 <6>[ 0.069730] cblist_init_generic: Setting shift to 3 and lim to 1.
5883 22:50:43.269325 <6>[ 0.076084] cblist_init_generic: Setting adjustable number of callback queues.
5884 22:50:43.275889 <6>[ 0.083528] cblist_init_generic: Setting shift to 3 and lim to 1.
5885 22:50:43.279172 <6>[ 0.089927] rcu: Hierarchical SRCU implementation.
5886 22:50:43.285433 <6>[ 0.094952] rcu: Max phase no-delay instances is 1000.
5887 22:50:43.293881 <6>[ 0.102889] EFI services will not be available.
5888 22:50:43.296788 <6>[ 0.107840] smp: Bringing up secondary CPUs ...
5889 22:50:43.307597 <6>[ 0.113070] Detected VIPT I-cache on CPU1
5890 22:50:43.314271 <4>[ 0.113115] cacheinfo: Unable to detect cache hierarchy for CPU 1
5891 22:50:43.320910 <6>[ 0.113124] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5892 22:50:43.327327 <6>[ 0.113156] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5893 22:50:43.330765 <6>[ 0.113736] Detected VIPT I-cache on CPU2
5894 22:50:43.336898 <4>[ 0.113770] cacheinfo: Unable to detect cache hierarchy for CPU 2
5895 22:50:43.343334 <6>[ 0.113775] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5896 22:50:43.350297 <6>[ 0.113788] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5897 22:50:43.356653 <6>[ 0.114232] Detected VIPT I-cache on CPU3
5898 22:50:43.363094 <4>[ 0.114263] cacheinfo: Unable to detect cache hierarchy for CPU 3
5899 22:50:43.369428 <6>[ 0.114268] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5900 22:50:43.376464 <6>[ 0.114279] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5901 22:50:43.379142 <6>[ 0.114852] CPU features: detected: Spectre-v2
5902 22:50:43.386242 <6>[ 0.114862] CPU features: detected: Spectre-BHB
5903 22:50:43.389169 <6>[ 0.114867] CPU features: detected: ARM erratum 858921
5904 22:50:43.396236 <6>[ 0.114872] Detected VIPT I-cache on CPU4
5905 22:50:43.402132 <4>[ 0.114919] cacheinfo: Unable to detect cache hierarchy for CPU 4
5906 22:50:43.409087 <6>[ 0.114927] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5907 22:50:43.415283 <6>[ 0.114935] arch_timer: Enabling local workaround for ARM erratum 858921
5908 22:50:43.422114 <6>[ 0.114946] arch_timer: CPU4: Trapping CNTVCT access
5909 22:50:43.428619 <6>[ 0.114953] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5910 22:50:43.431530 <6>[ 0.115439] Detected VIPT I-cache on CPU5
5911 22:50:43.437998 <4>[ 0.115479] cacheinfo: Unable to detect cache hierarchy for CPU 5
5912 22:50:43.444832 <6>[ 0.115485] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5913 22:50:43.451682 <6>[ 0.115492] arch_timer: Enabling local workaround for ARM erratum 858921
5914 22:50:43.457833 <6>[ 0.115498] arch_timer: CPU5: Trapping CNTVCT access
5915 22:50:43.464535 <6>[ 0.115503] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5916 22:50:43.467641 <6>[ 0.116039] Detected VIPT I-cache on CPU6
5917 22:50:43.474446 <4>[ 0.116085] cacheinfo: Unable to detect cache hierarchy for CPU 6
5918 22:50:43.480637 <6>[ 0.116091] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5919 22:50:43.487443 <6>[ 0.116099] arch_timer: Enabling local workaround for ARM erratum 858921
5920 22:50:43.493658 <6>[ 0.116105] arch_timer: CPU6: Trapping CNTVCT access
5921 22:50:43.500484 <6>[ 0.116110] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5922 22:50:43.503242 <6>[ 0.116639] Detected VIPT I-cache on CPU7
5923 22:50:43.510129 <4>[ 0.116683] cacheinfo: Unable to detect cache hierarchy for CPU 7
5924 22:50:43.519832 <6>[ 0.116689] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5925 22:50:43.526268 <6>[ 0.116696] arch_timer: Enabling local workaround for ARM erratum 858921
5926 22:50:43.529723 <6>[ 0.116702] arch_timer: CPU7: Trapping CNTVCT access
5927 22:50:43.536541 <6>[ 0.116708] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5928 22:50:43.542818 <6>[ 0.116755] smp: Brought up 1 node, 8 CPUs
5929 22:50:43.546020 <6>[ 0.355614] SMP: Total of 8 processors activated.
5930 22:50:43.552481 <6>[ 0.360550] CPU features: detected: 32-bit EL0 Support
5931 22:50:43.555701 <6>[ 0.365921] CPU features: detected: 32-bit EL1 Support
5932 22:50:43.562517 <6>[ 0.371287] CPU features: detected: CRC32 instructions
5933 22:50:43.565487 <6>[ 0.376713] CPU: All CPU(s) started at EL2
5934 22:50:43.572150 <6>[ 0.381051] alternatives: applying system-wide alternatives
5935 22:50:43.579799 <6>[ 0.389045] devtmpfs: initialized
5936 22:50:43.595913 <6>[ 0.398051] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5937 22:50:43.602146 <6>[ 0.408000] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5938 22:50:43.608316 <6>[ 0.415726] pinctrl core: initialized pinctrl subsystem
5939 22:50:43.611713 <6>[ 0.422835] DMI not present or invalid.
5940 22:50:43.618218 <6>[ 0.427201] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5941 22:50:43.628318 <6>[ 0.434117] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5942 22:50:43.634578 <6>[ 0.441646] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5943 22:50:43.644430 <6>[ 0.449896] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5944 22:50:43.650884 <6>[ 0.458076] audit: initializing netlink subsys (disabled)
5945 22:50:43.657529 <5>[ 0.463779] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5946 22:50:43.664159 <6>[ 0.464745] thermal_sys: Registered thermal governor 'step_wise'
5947 22:50:43.670636 <6>[ 0.471745] thermal_sys: Registered thermal governor 'power_allocator'
5948 22:50:43.674304 <6>[ 0.478040] cpuidle: using governor menu
5949 22:50:43.680631 <6>[ 0.489000] NET: Registered PF_QIPCRTR protocol family
5950 22:50:43.687100 <6>[ 0.494497] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5951 22:50:43.693614 <6>[ 0.501594] ASID allocator initialised with 32768 entries
5952 22:50:43.700144 <6>[ 0.508355] Serial: AMBA PL011 UART driver
5953 22:50:43.709605 <4>[ 0.518778] Trying to register duplicate clock ID: 113
5954 22:50:43.769036 <6>[ 0.575052] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5955 22:50:43.783663 <6>[ 0.589400] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5956 22:50:43.787108 <6>[ 0.599158] KASLR enabled
5957 22:50:43.801561 <6>[ 0.607181] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5958 22:50:43.807765 <6>[ 0.614183] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5959 22:50:43.814581 <6>[ 0.620660] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5960 22:50:43.820679 <6>[ 0.627651] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5961 22:50:43.827424 <6>[ 0.634124] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5962 22:50:43.833701 <6>[ 0.641113] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5963 22:50:43.840694 <6>[ 0.647586] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5964 22:50:43.847121 <6>[ 0.654575] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5965 22:50:43.853504 <6>[ 0.662145] ACPI: Interpreter disabled.
5966 22:50:43.860804 <6>[ 0.670114] iommu: Default domain type: Translated
5967 22:50:43.867329 <6>[ 0.675220] iommu: DMA domain TLB invalidation policy: strict mode
5968 22:50:43.870655 <5>[ 0.681849] SCSI subsystem initialized
5969 22:50:43.877350 <6>[ 0.686266] usbcore: registered new interface driver usbfs
5970 22:50:43.883964 <6>[ 0.691994] usbcore: registered new interface driver hub
5971 22:50:43.887406 <6>[ 0.697536] usbcore: registered new device driver usb
5972 22:50:43.894842 <6>[ 0.703834] pps_core: LinuxPPS API ver. 1 registered
5973 22:50:43.904809 <6>[ 0.709019] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5974 22:50:43.907869 <6>[ 0.718344] PTP clock support registered
5975 22:50:43.910900 <6>[ 0.722596] EDAC MC: Ver: 3.0.0
5976 22:50:43.919312 <6>[ 0.728243] FPGA manager framework
5977 22:50:43.925767 <6>[ 0.731927] Advanced Linux Sound Architecture Driver Initialized.
5978 22:50:43.928816 <6>[ 0.738676] vgaarb: loaded
5979 22:50:43.935423 <6>[ 0.741803] clocksource: Switched to clocksource arch_sys_counter
5980 22:50:43.938621 <5>[ 0.748231] VFS: Disk quotas dquot_6.6.0
5981 22:50:43.944985 <6>[ 0.752405] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5982 22:50:43.948042 <6>[ 0.759581] pnp: PnP ACPI: disabled
5983 22:50:43.957549 <6>[ 0.766419] NET: Registered PF_INET protocol family
5984 22:50:43.963460 <6>[ 0.771653] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5985 22:50:43.976253 <6>[ 0.781566] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5986 22:50:43.985367 <6>[ 0.790319] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5987 22:50:43.991732 <6>[ 0.798269] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5988 22:50:43.998687 <6>[ 0.806501] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5989 22:50:44.008658 <6>[ 0.814598] TCP: Hash tables configured (established 32768 bind 32768)
5990 22:50:44.015160 <6>[ 0.821425] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5991 22:50:44.021679 <6>[ 0.828395] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5992 22:50:44.028407 <6>[ 0.835873] NET: Registered PF_UNIX/PF_LOCAL protocol family
5993 22:50:44.034936 <6>[ 0.841969] RPC: Registered named UNIX socket transport module.
5994 22:50:44.038028 <6>[ 0.848113] RPC: Registered udp transport module.
5995 22:50:44.044927 <6>[ 0.853037] RPC: Registered tcp transport module.
5996 22:50:44.051145 <6>[ 0.857959] RPC: Registered tcp NFSv4.1 backchannel transport module.
5997 22:50:44.054279 <6>[ 0.864611] PCI: CLS 0 bytes, default 64
5998 22:50:44.057599 <6>[ 0.868860] Unpacking initramfs...
5999 22:50:44.067852 <6>[ 0.872917] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6000 22:50:44.077244 <6>[ 0.881625] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6001 22:50:44.080559 <6>[ 0.890529] kvm [1]: IPA Size Limit: 40 bits
6002 22:50:44.088128 <6>[ 0.896853] kvm [1]: vgic-v2@c420000
6003 22:50:44.094425 <6>[ 0.900676] kvm [1]: GIC system register CPU interface enabled
6004 22:50:44.097565 <6>[ 0.906856] kvm [1]: vgic interrupt IRQ18
6005 22:50:44.104112 <6>[ 0.911224] kvm [1]: Hyp mode initialized successfully
6006 22:50:44.107324 <5>[ 0.917516] Initialise system trusted keyrings
6007 22:50:44.113791 <6>[ 0.922286] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6008 22:50:44.123332 <6>[ 0.932252] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6009 22:50:44.129361 <5>[ 0.938671] NFS: Registering the id_resolver key type
6010 22:50:44.132791 <5>[ 0.943978] Key type id_resolver registered
6011 22:50:44.139392 <5>[ 0.948388] Key type id_legacy registered
6012 22:50:44.145934 <6>[ 0.952682] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6013 22:50:44.152346 <6>[ 0.959596] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6014 22:50:44.158706 <6>[ 0.967324] 9p: Installing v9fs 9p2000 file system support
6015 22:50:44.187109 <5>[ 0.996157] Key type asymmetric registered
6016 22:50:44.190258 <5>[ 1.000492] Asymmetric key parser 'x509' registered
6017 22:50:44.200304 <6>[ 1.005639] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6018 22:50:44.203051 <6>[ 1.013245] io scheduler mq-deadline registered
6019 22:50:44.206216 <6>[ 1.017998] io scheduler kyber registered
6020 22:50:44.229413 <6>[ 1.038702] EINJ: ACPI disabled.
6021 22:50:44.236114 <4>[ 1.042463] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6022 22:50:44.273972 <6>[ 1.083051] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6023 22:50:44.281907 <6>[ 1.091529] printk: console [ttyS0] disabled
6024 22:50:44.310285 <6>[ 1.116180] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6025 22:50:44.316626 <6>[ 1.125648] printk: console [ttyS0] enabled
6026 22:50:44.319865 <6>[ 1.125648] printk: console [ttyS0] enabled
6027 22:50:44.326599 <6>[ 1.134567] printk: bootconsole [mtk8250] disabled
6028 22:50:44.329811 <6>[ 1.134567] printk: bootconsole [mtk8250] disabled
6029 22:50:44.359759 <6>[ 1.165419] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6030 22:50:44.365810 <6>[ 1.175064] serial serial0: tty port ttyS1 registered
6031 22:50:44.372514 <6>[ 1.181632] SuperH (H)SCI(F) driver initialized
6032 22:50:44.375843 <6>[ 1.187120] msm_serial: driver initialized
6033 22:50:44.391431 <6>[ 1.197446] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6034 22:50:44.401352 <6>[ 1.206045] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6035 22:50:44.407634 <6>[ 1.214618] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6036 22:50:44.417966 <6>[ 1.223184] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6037 22:50:44.427789 <6>[ 1.231836] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6038 22:50:44.433927 <6>[ 1.240496] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6039 22:50:44.443985 <6>[ 1.249236] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6040 22:50:44.453817 <6>[ 1.257974] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6041 22:50:44.460229 <6>[ 1.266536] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6042 22:50:44.469694 <6>[ 1.275336] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6043 22:50:44.478340 <4>[ 1.287719] cacheinfo: Unable to detect cache hierarchy for CPU 0
6044 22:50:44.487634 <6>[ 1.297034] loop: module loaded
6045 22:50:44.499419 <6>[ 1.308898] vsim1: Bringing 1800000uV into 2700000-2700000uV
6046 22:50:44.517282 <6>[ 1.326790] megasas: 07.719.03.00-rc1
6047 22:50:44.526199 <6>[ 1.335546] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6048 22:50:44.540030 <6>[ 1.349172] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6049 22:50:44.556751 <6>[ 1.365746] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6050 22:50:44.616764 <6>[ 1.419447] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.3.25/cr50_v1.9308_87_mp.398-a
6051 22:50:44.684955 <6>[ 1.494178] Freeing initrd memory: 18284K
6052 22:50:44.700040 <4>[ 1.506010] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6053 22:50:44.706794 <4>[ 1.515241] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.1.90-cip20 #1
6054 22:50:44.713203 <4>[ 1.521940] Hardware name: Google juniper sku16 board (DT)
6055 22:50:44.716672 <4>[ 1.527679] Call trace:
6056 22:50:44.719794 <4>[ 1.530379] dump_backtrace.part.0+0xe0/0xf0
6057 22:50:44.723236 <4>[ 1.534916] show_stack+0x18/0x30
6058 22:50:44.729857 <4>[ 1.538488] dump_stack_lvl+0x68/0x84
6059 22:50:44.732864 <4>[ 1.542408] dump_stack+0x18/0x34
6060 22:50:44.736166 <4>[ 1.545978] sysfs_warn_dup+0x64/0x80
6061 22:50:44.739238 <4>[ 1.549899] sysfs_do_create_link_sd+0xf0/0x100
6062 22:50:44.746067 <4>[ 1.554686] sysfs_create_link+0x20/0x40
6063 22:50:44.749435 <4>[ 1.558866] bus_add_device+0x68/0x10c
6064 22:50:44.752622 <4>[ 1.562872] device_add+0x340/0x7ac
6065 22:50:44.755604 <4>[ 1.566616] of_device_add+0x44/0x60
6066 22:50:44.762250 <4>[ 1.570450] of_platform_device_create_pdata+0x90/0x120
6067 22:50:44.765738 <4>[ 1.575931] of_platform_bus_create+0x170/0x370
6068 22:50:44.772078 <4>[ 1.580718] of_platform_populate+0x50/0xfc
6069 22:50:44.775463 <4>[ 1.585157] parse_mtd_partitions+0x1dc/0x510
6070 22:50:44.782148 <4>[ 1.589770] mtd_device_parse_register+0xf8/0x2e0
6071 22:50:44.785576 <4>[ 1.594728] spi_nor_probe+0x21c/0x2f0
6072 22:50:44.788476 <4>[ 1.598733] spi_mem_probe+0x6c/0xb0
6073 22:50:44.791711 <4>[ 1.602565] spi_probe+0x84/0xe4
6074 22:50:44.795595 <4>[ 1.606047] really_probe+0xbc/0x2e0
6075 22:50:44.802062 <4>[ 1.609877] __driver_probe_device+0x78/0x11c
6076 22:50:44.805231 <4>[ 1.614489] driver_probe_device+0xd8/0x160
6077 22:50:44.808551 <4>[ 1.618927] __device_attach_driver+0xb8/0x134
6078 22:50:44.815178 <4>[ 1.623625] bus_for_each_drv+0x78/0xd0
6079 22:50:44.818110 <4>[ 1.627716] __device_attach+0xa8/0x1c0
6080 22:50:44.821478 <4>[ 1.631806] device_initial_probe+0x14/0x20
6081 22:50:44.824972 <4>[ 1.636243] bus_probe_device+0x9c/0xa4
6082 22:50:44.831406 <4>[ 1.640333] device_add+0x3ac/0x7ac
6083 22:50:44.834844 <4>[ 1.644075] __spi_add_device+0x78/0x120
6084 22:50:44.837865 <4>[ 1.648253] spi_add_device+0x40/0x7c
6085 22:50:44.844775 <4>[ 1.652170] spi_register_controller+0x610/0xad0
6086 22:50:44.847722 <4>[ 1.657043] devm_spi_register_controller+0x4c/0xa4
6087 22:50:44.850903 <4>[ 1.662175] mtk_spi_probe+0x3f8/0x650
6088 22:50:44.857586 <4>[ 1.666179] platform_probe+0x68/0xe0
6089 22:50:44.861027 <4>[ 1.670097] really_probe+0xbc/0x2e0
6090 22:50:44.864219 <4>[ 1.673927] __driver_probe_device+0x78/0x11c
6091 22:50:44.868194 <4>[ 1.678538] driver_probe_device+0xd8/0x160
6092 22:50:44.874035 <4>[ 1.682975] __driver_attach+0x94/0x19c
6093 22:50:44.877161 <4>[ 1.687066] bus_for_each_dev+0x70/0xd0
6094 22:50:44.880367 <4>[ 1.691156] driver_attach+0x24/0x30
6095 22:50:44.883873 <4>[ 1.694985] bus_add_driver+0x154/0x20c
6096 22:50:44.890490 <4>[ 1.699075] driver_register+0x78/0x130
6097 22:50:44.893826 <4>[ 1.703166] __platform_driver_register+0x28/0x34
6098 22:50:44.897271 <4>[ 1.708125] mtk_spi_driver_init+0x1c/0x28
6099 22:50:44.903144 <4>[ 1.712479] do_one_initcall+0x50/0x1d0
6100 22:50:44.906501 <4>[ 1.716570] kernel_init_freeable+0x21c/0x288
6101 22:50:44.910183 <4>[ 1.721182] kernel_init+0x24/0x12c
6102 22:50:44.913516 <4>[ 1.724927] ret_from_fork+0x10/0x20
6103 22:50:44.924941 <6>[ 1.733840] tun: Universal TUN/TAP device driver, 1.6
6104 22:50:44.928013 <6>[ 1.740127] thunder_xcv, ver 1.0
6105 22:50:44.934606 <6>[ 1.743644] thunder_bgx, ver 1.0
6106 22:50:44.934703 <6>[ 1.747149] nicpf, ver 1.0
6107 22:50:44.945664 <6>[ 1.751514] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6108 22:50:44.949176 <6>[ 1.758997] hns3: Copyright (c) 2017 Huawei Corporation.
6109 22:50:44.955373 <6>[ 1.764596] hclge is initializing
6110 22:50:44.958713 <6>[ 1.768187] e1000: Intel(R) PRO/1000 Network Driver
6111 22:50:44.965279 <6>[ 1.773324] e1000: Copyright (c) 1999-2006 Intel Corporation.
6112 22:50:44.972169 <6>[ 1.779351] e1000e: Intel(R) PRO/1000 Network Driver
6113 22:50:44.975330 <6>[ 1.784572] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6114 22:50:44.981750 <6>[ 1.790764] igb: Intel(R) Gigabit Ethernet Network Driver
6115 22:50:44.988422 <6>[ 1.796421] igb: Copyright (c) 2007-2014 Intel Corporation.
6116 22:50:44.994795 <6>[ 1.802266] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6117 22:50:45.001382 <6>[ 1.808789] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6118 22:50:45.004358 <6>[ 1.815343] sky2: driver version 1.30
6119 22:50:45.011757 <6>[ 1.820597] usbcore: registered new device driver r8152-cfgselector
6120 22:50:45.017797 <6>[ 1.827141] usbcore: registered new interface driver r8152
6121 22:50:45.024522 <6>[ 1.832982] VFIO - User Level meta-driver version: 0.3
6122 22:50:45.031898 <6>[ 1.840838] mtu3 11201000.usb: uwk - reg:0x420, version:101
6123 22:50:45.038345 <4>[ 1.846712] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6124 22:50:45.044745 <6>[ 1.853984] mtu3 11201000.usb: dr_mode: 1, drd: auto
6125 22:50:45.051469 <6>[ 1.859209] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6126 22:50:45.054583 <6>[ 1.865391] mtu3 11201000.usb: usb3-drd: 0
6127 22:50:45.065327 <6>[ 1.870921] mtu3 11201000.usb: xHCI platform device register success...
6128 22:50:45.071620 <4>[ 1.879609] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6129 22:50:45.078226 <6>[ 1.887557] xhci-mtk 11200000.usb: xHCI Host Controller
6130 22:50:45.088261 <6>[ 1.893059] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6131 22:50:45.091402 <6>[ 1.900795] xhci-mtk 11200000.usb: USB3 root hub has no ports
6132 22:50:45.101055 <6>[ 1.906803] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6133 22:50:45.107698 <6>[ 1.916227] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6134 22:50:45.114362 <6>[ 1.922308] xhci-mtk 11200000.usb: xHCI Host Controller
6135 22:50:45.120728 <6>[ 1.927796] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6136 22:50:45.127500 <6>[ 1.935453] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6137 22:50:45.130801 <6>[ 1.942267] hub 1-0:1.0: USB hub found
6138 22:50:45.137374 <6>[ 1.946296] hub 1-0:1.0: 1 port detected
6139 22:50:45.147061 <6>[ 1.951618] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6140 22:50:45.150670 <6>[ 1.960248] hub 2-0:1.0: USB hub found
6141 22:50:45.157084 <3>[ 1.964304] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6142 22:50:45.163411 <6>[ 1.972206] usbcore: registered new interface driver usb-storage
6143 22:50:45.170059 <6>[ 1.978817] usbcore: registered new device driver onboard-usb-hub
6144 22:50:45.183916 <4>[ 1.989919] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6145 22:50:45.192800 <6>[ 2.002164] mt6397-rtc mt6358-rtc: registered as rtc0
6146 22:50:45.202809 <6>[ 2.007644] mt6397-rtc mt6358-rtc: setting system clock to 2024-05-07T22:50:45 UTC (1715122245)
6147 22:50:45.209266 <6>[ 2.017535] i2c_dev: i2c /dev entries driver
6148 22:50:45.219465 <6>[ 2.023991] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6149 22:50:45.225627 <6>[ 2.032314] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6150 22:50:45.232032 <6>[ 2.041216] i2c 4-0058: Fixed dependency cycle(s) with /panel
6151 22:50:45.238522 <6>[ 2.047249] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6152 22:50:45.248764 <3>[ 2.054717] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6153 22:50:45.265883 <6>[ 2.071781] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6154 22:50:45.273807 <6>[ 2.083230] cpu cpu0: EM: created perf domain
6155 22:50:45.287199 <6>[ 2.088659] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6156 22:50:45.290732 <6>[ 2.099932] cpu cpu4: EM: created perf domain
6157 22:50:45.298114 <6>[ 2.106842] sdhci: Secure Digital Host Controller Interface driver
6158 22:50:45.304176 <6>[ 2.113373] sdhci: Copyright(c) Pierre Ossman
6159 22:50:45.310886 <6>[ 2.118803] Synopsys Designware Multimedia Card Interface Driver
6160 22:50:45.317454 <6>[ 2.119207] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6161 22:50:45.324140 <6>[ 2.125926] sdhci-pltfm: SDHCI platform and OF driver helper
6162 22:50:45.331009 <6>[ 2.139455] ledtrig-cpu: registered to indicate activity on CPUs
6163 22:50:45.338151 <6>[ 2.147201] usbcore: registered new interface driver usbhid
6164 22:50:45.344746 <6>[ 2.153041] usbhid: USB HID core driver
6165 22:50:45.351576 <6>[ 2.157305] spi_master spi2: will run message pump with realtime priority
6166 22:50:45.359070 <4>[ 2.157308] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6167 22:50:45.365324 <4>[ 2.171566] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6168 22:50:45.378205 <6>[ 2.175959] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6169 22:50:45.395160 <6>[ 2.194143] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6170 22:50:45.401381 <4>[ 2.204482] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6171 22:50:45.408216 <6>[ 2.215294] cros-ec-spi spi2.0: Chrome EC device registered
6172 22:50:45.414625 <4>[ 2.222800] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6173 22:50:45.427296 <4>[ 2.233294] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6174 22:50:45.434064 <4>[ 2.242472] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6175 22:50:45.446794 <6>[ 2.252599] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6176 22:50:45.467171 <6>[ 2.276292] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6177 22:50:45.474858 <6>[ 2.284005] mmc0: new HS400 MMC card at address 0001
6178 22:50:45.481117 <6>[ 2.290611] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6179 22:50:45.491150 <6>[ 2.300587] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6180 22:50:45.498918 <6>[ 2.308347] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6181 22:50:45.509203 <6>[ 2.309588] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6182 22:50:45.512294 <6>[ 2.314832] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6183 22:50:45.525648 <6>[ 2.326385] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6184 22:50:45.535055 <6>[ 2.326679] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6185 22:50:45.541999 <6>[ 2.328397] NET: Registered PF_PACKET protocol family
6186 22:50:45.551983 <6>[ 2.339811] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6187 22:50:45.555405 <6>[ 2.350555] 9pnet: Installing 9P2000 support
6188 22:50:45.561618 <6>[ 2.355787] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6189 22:50:45.568322 <5>[ 2.365700] Key type dns_resolver registered
6190 22:50:45.574379 <6>[ 2.370307] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6191 22:50:45.577925 <6>[ 2.377746] registered taskstats version 1
6192 22:50:45.584662 <5>[ 2.392450] Loading compiled-in X.509 certificates
6193 22:50:45.623051 <3>[ 2.429189] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6194 22:50:45.655017 <4>[ 2.457544] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6195 22:50:45.664738 <6>[ 2.468143] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6196 22:50:45.677837 <6>[ 2.480730] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6197 22:50:45.691136 <3>[ 2.491990] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6198 22:50:45.705080 <3>[ 2.507572] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6199 22:50:45.714423 <3>[ 2.520597] debugfs: File 'Playback' in directory 'dapm' already present!
6200 22:50:45.721616 <3>[ 2.527657] debugfs: File 'Capture' in directory 'dapm' already present!
6201 22:50:45.734607 <6>[ 2.537038] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input4
6202 22:50:45.741530 <6>[ 2.550872] hub 1-1:1.0: USB hub found
6203 22:50:45.748357 <6>[ 2.553943] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6204 22:50:45.754762 <6>[ 2.555332] hub 1-1:1.0: 3 ports detected
6205 22:50:45.761305 <6>[ 2.563403] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6206 22:50:45.771511 <6>[ 2.576192] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6207 22:50:45.777466 <6>[ 2.584712] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6208 22:50:45.787698 <6>[ 2.593231] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6209 22:50:45.797251 <6>[ 2.601750] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6210 22:50:45.803794 <6>[ 2.610267] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6211 22:50:45.810446 <6>[ 2.619506] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6212 22:50:45.817639 <6>[ 2.627028] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6213 22:50:45.825019 <6>[ 2.634374] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6214 22:50:45.835724 <6>[ 2.641648] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6215 22:50:45.842288 <6>[ 2.649055] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6216 22:50:45.848878 <6>[ 2.657309] panfrost 13040000.gpu: clock rate = 511999970
6217 22:50:45.858425 <6>[ 2.662999] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6218 22:50:45.868164 <6>[ 2.673021] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6219 22:50:45.874940 <6>[ 2.681033] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6220 22:50:45.887583 <6>[ 2.689465] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6221 22:50:45.894527 <6>[ 2.701543] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6222 22:50:45.906324 <6>[ 2.712348] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6223 22:50:45.916396 <6>[ 2.720965] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6224 22:50:45.925872 <6>[ 2.730117] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6225 22:50:45.935789 <6>[ 2.739248] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6226 22:50:45.942649 <6>[ 2.748373] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6227 22:50:45.952024 <6>[ 2.757674] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6228 22:50:45.961967 <6>[ 2.766975] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6229 22:50:45.971762 <6>[ 2.776448] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6230 22:50:45.981449 <6>[ 2.785920] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6231 22:50:45.991203 <6>[ 2.795049] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6232 22:50:46.061435 <6>[ 2.867124] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6233 22:50:46.070853 <6>[ 2.876021] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6234 22:50:46.082484 <6>[ 2.888342] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6235 22:50:46.099768 <6>[ 2.905811] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6236 22:50:46.770171 <6>[ 3.090303] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6237 22:50:46.779663 <4>[ 3.207018] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6238 22:50:46.786238 <4>[ 3.207036] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6239 22:50:46.793224 <6>[ 3.248104] r8152 1-1.2:1.0 eth0: v1.12.13
6240 22:50:46.799763 <6>[ 3.325831] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6241 22:50:46.805982 <6>[ 3.559378] Console: switching to colour frame buffer device 170x48
6242 22:50:46.815437 <6>[ 3.620035] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6243 22:50:46.831845 <6>[ 3.637911] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input5
6244 22:50:46.838481 <6>[ 3.646154] input: volume-buttons as /devices/platform/volume-buttons/input/input6
6245 22:50:48.066783 <6>[ 4.875545] r8152 1-1.2:1.0 eth0: carrier on
6246 22:50:50.280829 <5>[ 4.897938] Sending DHCP requests .., OK
6247 22:50:50.287172 <6>[ 7.094194] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.22
6248 22:50:50.290606 <6>[ 7.102635] IP-Config: Complete:
6249 22:50:50.304385 <6>[ 7.106210] device=eth0, hwaddr=00:e0:4c:78:85:cb, ipaddr=192.168.201.22, mask=255.255.255.0, gw=192.168.201.1
6250 22:50:50.313616 <6>[ 7.117111] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2, domain=lava-rack, nis-domain=(none)
6251 22:50:50.319779 <6>[ 7.126593] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6252 22:50:50.323048 <6>[ 7.126603] nameserver0=192.168.201.1
6253 22:50:50.329967 <6>[ 7.138918] clk: Disabling unused clocks
6254 22:50:50.333189 <6>[ 7.144016] ALSA device list:
6255 22:50:50.341739 <6>[ 7.150981] #0: mt8183_mt6358_ts3a227_max98357
6256 22:50:50.353046 <6>[ 7.162427] Freeing unused kernel memory: 8512K
6257 22:50:50.361163 <6>[ 7.169973] Run /init as init process
6258 22:50:50.372169 Loading, please wait...
6259 22:50:50.407601 Starting systemd-udevd version 252.22-1~deb12u1
6260 22:50:50.407692
6261 22:50:50.729291 <3>[ 7.538173] thermal_sys: Failed to find 'trips' node
6262 22:50:50.739461 <3>[ 7.545351] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6263 22:50:50.749136 <3>[ 7.554632] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6264 22:50:50.762542 <3>[ 7.563395] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6265 22:50:50.768939 <4>[ 7.564974] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6266 22:50:50.775690 <3>[ 7.574977] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6267 22:50:50.781677 <3>[ 7.585369] thermal_sys: Failed to find 'trips' node
6268 22:50:50.791956 <3>[ 7.589443] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6269 22:50:50.798311 <3>[ 7.594564] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6270 22:50:50.809198 <4>[ 7.594940] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6271 22:50:50.815359 <4>[ 7.595039] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6272 22:50:50.822328 <5>[ 7.595995] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6273 22:50:50.831710 <3>[ 7.605516] elan_i2c 2-0015: Error applying setting, reverse things back
6274 22:50:50.838652 <5>[ 7.619683] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6275 22:50:50.844806 <3>[ 7.622067] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6276 22:50:50.854881 <5>[ 7.629767] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6277 22:50:50.864908 <3>[ 7.631933] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6278 22:50:50.870811 <3>[ 7.631949] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6279 22:50:50.881002 <3>[ 7.631954] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6280 22:50:50.884247 <6>[ 7.634556] mc: Linux media interface: v0.10
6281 22:50:50.894373 <3>[ 7.637130] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6282 22:50:50.904485 <3>[ 7.637157] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6283 22:50:50.913870 <3>[ 7.637165] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6284 22:50:50.920775 <3>[ 7.637176] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6285 22:50:50.932224 <3>[ 7.637184] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6286 22:50:50.942190 <4>[ 7.637359] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6287 22:50:50.952103 <3>[ 7.638350] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6288 22:50:50.961606 <4>[ 7.644381] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6289 22:50:50.972340 <6>[ 7.664111] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6290 22:50:50.979402 <6>[ 7.668713] cfg80211: failed to load regulatory.db
6291 22:50:50.989027 <6>[ 7.669324] cs_system_cfg: CoreSight Configuration manager initialised
6292 22:50:50.995918 <6>[ 7.683059] videodev: Linux video capture interface: v2.00
6293 22:50:51.005139 <6>[ 7.727029] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6294 22:50:51.044849 <6>[ 7.850452] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6295 22:50:51.047664 <3>[ 7.851106] mtk-scp 10500000.scp: invalid resource
6296 22:50:51.057774 <6>[ 7.858867] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6297 22:50:51.063990 <6>[ 7.863558] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6298 22:50:51.071968 <6>[ 7.865299] Bluetooth: Core ver 2.22
6299 22:50:51.075016 <6>[ 7.865352] NET: Registered PF_BLUETOOTH protocol family
6300 22:50:51.086451 <6>[ 7.865356] Bluetooth: HCI device and connection manager initialized
6301 22:50:51.089551 <6>[ 7.865372] Bluetooth: HCI socket layer initialized
6302 22:50:51.096098 <6>[ 7.865379] Bluetooth: L2CAP socket layer initialized
6303 22:50:51.099506 <6>[ 7.865409] Bluetooth: SCO socket layer initialized
6304 22:50:51.109008 <6>[ 7.878980] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6305 22:50:51.115807 <6>[ 7.884561] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6306 22:50:51.122633 <6>[ 7.890388] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6307 22:50:51.131820 <6>[ 7.890516] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6308 22:50:51.138467 <6>[ 7.893822] remoteproc remoteproc0: scp is available
6309 22:50:51.144579 <6>[ 7.893926] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6310 22:50:51.154922 <6>[ 7.894302] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6311 22:50:51.164934 <6>[ 7.898924] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6312 22:50:51.168226 <6>[ 7.904555] Bluetooth: HCI UART driver ver 2.3
6313 22:50:51.177807 <4>[ 7.904579] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6314 22:50:51.181173 <6>[ 7.904591] remoteproc remoteproc0: powering up scp
6315 22:50:51.190852 <4>[ 7.904626] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6316 22:50:51.197191 <3>[ 7.904634] remoteproc remoteproc0: request_firmware failed: -2
6317 22:50:51.204299 <6>[ 7.909338] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6318 22:50:51.210691 <6>[ 7.914430] Bluetooth: HCI UART protocol H4 registered
6319 22:50:51.216874 <6>[ 7.915537] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6320 22:50:51.226915 <6>[ 7.922382] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6321 22:50:51.233640 <6>[ 7.928946] Bluetooth: HCI UART protocol LL registered
6322 22:50:51.240382 <6>[ 7.928970] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6323 22:50:51.253421 <6>[ 7.929533] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6324 22:50:51.256752 <6>[ 7.929652] usbcore: registered new interface driver uvcvideo
6325 22:50:51.270057 Begin: Loading e<6>[ 7.967109] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6326 22:50:51.276623 ssential drivers<6>[ 7.969714] Bluetooth: HCI UART protocol Three-wire (H5) registered
6327 22:50:51.279678 ... done.
6328 22:50:51.286404 Begi<6>[ 7.977414] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6329 22:50:51.293147 n: Running /scri<6>[ 7.983224] Bluetooth: HCI UART protocol Broadcom registered
6330 22:50:51.306101 pts/init-premoun<6>[ 7.990800] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6331 22:50:51.309593 t ... done.
6332 22:50:51.312584 Beg<6>[ 7.996100] Bluetooth: HCI UART protocol QCA registered
6333 22:50:51.318993 in: Mounting roo<6>[ 7.997089] Bluetooth: hci0: setting up ROME/QCA6390
6334 22:50:51.332484 t file system ..<4>[ 8.042125] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6335 22:50:51.335496 <4>[ 8.042125] Fallback method does not support PEC.
6336 22:50:51.341957 . Begin: Running<6>[ 8.046783] Bluetooth: HCI UART protocol Marvell registered
6337 22:50:51.352271 /scripts/nfs-to<3>[ 8.059154] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6338 22:50:51.355343 p ... done.
6339 22:50:51.365892 Begin: Running /scripts/nfs-premoun<6>[ 8.169175] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6340 22:50:51.375166 t ... Waiting up<3>[ 8.177553] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6341 22:50:51.378626 to 60 secs for any ethernet to become available
6342 22:50:51.381802 Device /sys/class/net/eth0 found
6343 22:50:51.381894 done.
6344 22:50:51.388555 Begin: Waiting up to 180 secs for any network device to become available ... done.
6345 22:50:51.400198 <3>[ 8.209216] Bluetooth: hci0: Frame reassembly failed (-84)
6346 22:50:51.417564 IP-Config: eth0 hardware address 00:e0:4c:78:85:cb mtu 1500 DHCP
6347 22:50:51.424557 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6348 22:50:51.431172 address: 192.168.201.22 broadcast: 192.168.201.255 netmask: 255.255.255.0
6349 22:50:51.437932 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6350 22:50:51.444285 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-2
6351 22:50:51.451248 domain : lava-rack
6352 22:50:51.454473 rootserver: 192.168.201.1 rootpath:
6353 22:50:51.457303 filename :
6354 22:50:51.586276 done.
6355 22:50:51.593266 Begin: Running /scripts/nfs-bottom ... done.
6356 22:50:51.614044 Begin: Running /scripts/init-bottom ... done.
6357 22:50:51.683134 <6>[ 8.492170] Bluetooth: hci0: QCA Product ID :0x00000008
6358 22:50:51.692246 <6>[ 8.501461] Bluetooth: hci0: QCA SOC Version :0x00000044
6359 22:50:51.701474 <6>[ 8.510601] Bluetooth: hci0: QCA ROM Version :0x00000302
6360 22:50:51.710666 <6>[ 8.519719] Bluetooth: hci0: QCA Patch Version:0x00000111
6361 22:50:51.717195 <6>[ 8.519729] Bluetooth: hci0: QCA controller version 0x00440302
6362 22:50:51.729630 <6>[ 8.519737] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6363 22:50:51.739429 <4>[ 8.520505] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6364 22:50:51.753733 <3>[ 8.559569] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6365 22:50:51.761037 <3>[ 8.570156] Bluetooth: hci0: QCA Failed to download patch (-2)
6366 22:50:51.791137 <6>[ 8.596707] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6367 22:50:51.877688 <4>[ 8.682882] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6368 22:50:51.897116 <4>[ 8.702985] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6369 22:50:51.912463 <4>[ 8.718102] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6370 22:50:51.922189 <4>[ 8.731478] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6371 22:50:52.921822 <6>[ 9.730634] NET: Registered PF_INET6 protocol family
6372 22:50:52.933796 <6>[ 9.742728] Segment Routing with IPv6
6373 22:50:52.942213 <6>[ 9.751086] In-situ OAM (IOAM) with IPv6
6374 22:50:53.116856 <30>[ 9.896746] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6375 22:50:53.135432 <30>[ 9.944000] systemd[1]: Detected architecture arm64.
6376 22:50:53.146144
6377 22:50:53.149289 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6378 22:50:53.149382
6379 22:50:53.149455
6380 22:50:53.177768 <30>[ 9.986779] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6381 22:50:54.111011 <30>[ 10.916708] systemd[1]: Queued start job for default target graphical.target.
6382 22:50:54.156909 <30>[ 10.962837] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6383 22:50:54.169614 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6384 22:50:54.169714
6385 22:50:54.190166 <30>[ 10.996216] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6386 22:50:54.203983 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6387 22:50:54.204084
6388 22:50:54.222238 <30>[ 11.028216] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6389 22:50:54.236790 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6390 22:50:54.236888
6391 22:50:54.253601 <30>[ 11.059379] systemd[1]: Created slice user.slice - User and Session Slice.
6392 22:50:54.266200 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6393 22:50:54.266331
6394 22:50:54.287864 <30>[ 11.090403] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6395 22:50:54.300706 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6396 22:50:54.300801
6397 22:50:54.319635 <30>[ 11.122226] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6398 22:50:54.331966 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6399 22:50:54.332073
6400 22:50:54.358449 <30>[ 11.154178] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6401 22:50:54.377437 <30>[ 11.183295] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6402 22:50:54.385107 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6403 22:50:54.388317
6404 22:50:54.404630 <30>[ 11.210004] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6405 22:50:54.417194 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6406 22:50:54.417288
6407 22:50:54.432700 <30>[ 11.238036] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6408 22:50:54.445969 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6409 22:50:54.446063
6410 22:50:54.460899 <30>[ 11.270096] systemd[1]: Reached target paths.target - Path Units.
6411 22:50:54.475227 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6412 22:50:54.475324
6413 22:50:54.492222 <30>[ 11.298015] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6414 22:50:54.504526 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6415 22:50:54.504622
6416 22:50:54.520157 <30>[ 11.326098] systemd[1]: Reached target slices.target - Slice Units.
6417 22:50:54.531621 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6418 22:50:54.531714
6419 22:50:54.544877 <30>[ 11.354027] systemd[1]: Reached target swap.target - Swaps.
6420 22:50:54.555587 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6421 22:50:54.555680
6422 22:50:54.576349 <30>[ 11.382032] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6423 22:50:54.589453 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6424 22:50:54.589552
6425 22:50:54.608600 <30>[ 11.414432] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6426 22:50:54.622387 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6427 22:50:54.622481
6428 22:50:54.643035 <30>[ 11.448908] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6429 22:50:54.656416 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6430 22:50:54.656514
6431 22:50:54.673724 <30>[ 11.479636] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6432 22:50:54.687912 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6433 22:50:54.688007
6434 22:50:54.704773 <30>[ 11.510724] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6435 22:50:54.716818 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6436 22:50:54.716912
6437 22:50:54.738150 <30>[ 11.543671] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6438 22:50:54.751463 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6439 22:50:54.751558
6440 22:50:54.770867 <30>[ 11.576376] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6441 22:50:54.784138 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6442 22:50:54.784235
6443 22:50:54.800787 <30>[ 11.606558] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6444 22:50:54.813628 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6445 22:50:54.813729
6446 22:50:54.865120 <30>[ 11.670352] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6447 22:50:54.877374 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6448 22:50:54.877532
6449 22:50:54.890126 <30>[ 11.695906] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6450 22:50:54.902571 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6451 22:50:54.902947
6452 22:50:54.964891 <30>[ 11.770462] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6453 22:50:54.978364 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6454 22:50:54.978822
6455 22:50:55.004571 <30>[ 11.802898] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6456 22:50:55.053297 <30>[ 11.858807] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6457 22:50:55.067675 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6458 22:50:55.068223
6459 22:50:55.091455 <30>[ 11.896841] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6460 22:50:55.103881 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6461 22:50:55.104321
6462 22:50:55.126115 <30>[ 11.931722] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6463 22:50:55.137706 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6464 22:50:55.138141
6465 22:50:55.185926 <30>[ 11.990714] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6466 22:50:55.195185 <6>[ 11.991046] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6467 22:50:55.209465 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6468 22:50:55.209956
6469 22:50:55.235441 <30>[ 12.040458] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6470 22:50:55.247847 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6471 22:50:55.248418
6472 22:50:55.297819 <30>[ 12.102759] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6473 22:50:55.310714 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6474 22:50:55.311251
6475 22:50:55.335952 <30>[ 12.140917] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6476 22:50:55.346836 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6477 22:50:55.347396
6478 22:50:55.371172 <6>[ 12.180130] fuse: init (API version 7.37)
6479 22:50:55.421539 <30>[ 12.227017] systemd[1]: Starting systemd-journald.service - Journal Service...
6480 22:50:55.434637 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6481 22:50:55.435153
6482 22:50:55.456273 <30>[ 12.261789] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6483 22:50:55.467352 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6484 22:50:55.467937
6485 22:50:55.493522 <30>[ 12.296178] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6486 22:50:55.506185 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6487 22:50:55.506357
6488 22:50:55.532893 <30>[ 12.338355] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6489 22:50:55.547654 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6490 22:50:55.548153
6491 22:50:55.570489 <30>[ 12.376119] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6492 22:50:55.583654 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6493 22:50:55.584280
6494 22:50:55.610233 <30>[ 12.415215] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6495 22:50:55.620337 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6496 22:50:55.620909
6497 22:50:55.637646 <30>[ 12.442884] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6498 22:50:55.647750 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6499 22:50:55.648224
6500 22:50:55.662077 <3>[ 12.467297] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6501 22:50:55.672699 <30>[ 12.476549] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6502 22:50:55.679148 <3>[ 12.483633] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6503 22:50:55.690239 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6504 22:50:55.690819
6505 22:50:55.699874 <3>[ 12.504136] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6506 22:50:55.713847 <30>[ 12.519026] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6507 22:50:55.723966 <3>[ 12.519156] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6508 22:50:55.740809 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static D<3>[ 12.544518] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6509 22:50:55.741350 evice Nodes.
6510 22:50:55.741695
6511 22:50:55.755801 <3>[ 12.560641] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6512 22:50:55.766445 <30>[ 12.570622] systemd[1]: modprobe@configfs.service: Deactivated successfully.
6513 22:50:55.772797 <3>[ 12.576340] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6514 22:50:55.780025 <30>[ 12.578579] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
6515 22:50:55.789662 <3>[ 12.591949] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6516 22:50:55.805563 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6517 22:50:55.806097
6518 22:50:55.821295 <30>[ 12.626633] systemd[1]: Started systemd-journald.service - Journal Service.
6519 22:50:55.830961 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6520 22:50:55.831532
6521 22:50:55.852619 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6522 22:50:55.853152
6523 22:50:55.872248 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6524 22:50:55.872793
6525 22:50:55.892186 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6526 22:50:55.892717
6527 22:50:55.915021 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6528 22:50:55.915576
6529 22:50:55.935561 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6530 22:50:55.936140
6531 22:50:55.954485 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6532 22:50:55.954999
6533 22:50:55.978002 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6534 22:50:55.978649
6535 22:50:55.998026 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6536 22:50:55.998597
6537 22:50:56.019463 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6538 22:50:56.019974
6539 22:50:56.061792 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6540 22:50:56.062345
6541 22:50:56.084131 <4>[ 12.882604] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6542 22:50:56.095211 <3>[ 12.900394] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6543 22:50:56.101792 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6544 22:50:56.102397
6545 22:50:56.130984 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6546 22:50:56.131672
6547 22:50:56.157095 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6548 22:50:56.157667
6549 22:50:56.191913 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables..<46>[ 12.996620] systemd-journald[320]: Received client request to flush runtime journal.
6550 22:50:56.192441 .
6551 22:50:56.192789
6552 22:50:56.245842 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6553 22:50:56.246460
6554 22:50:56.531004 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6555 22:50:56.531168
6556 22:50:56.550597 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6557 22:50:56.550723
6558 22:50:56.570533 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6559 22:50:56.570627
6560 22:50:56.591763 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6561 22:50:56.591898
6562 22:50:56.974025 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6563 22:50:56.974202
6564 22:50:57.643160 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6565 22:50:57.643335
6566 22:50:57.667537 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6567 22:50:57.667984
6568 22:50:57.709696 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6569 22:50:57.710192
6570 22:50:57.812510 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6571 22:50:57.813011
6572 22:50:57.833446 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6573 22:50:57.833941
6574 22:50:57.849337 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6575 22:50:57.849858
6576 22:50:57.910743 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6577 22:50:57.911282
6578 22:50:57.941651 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6579 22:50:57.942088
6580 22:50:58.245382 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6581 22:50:58.245554
6582 22:50:58.262151 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6583 22:50:58.262464
6584 22:50:58.325391 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6585 22:50:58.325891
6586 22:50:58.485398 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6587 22:50:58.486060
6588 22:50:58.507853 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6589 22:50:58.508560
6590 22:50:58.567524 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6591 22:50:58.568167
6592 22:50:58.598215 <4>[ 15.406394] power_supply_show_property: 4 callbacks suppressed
6593 22:50:58.609563 <3>[ 15.406409] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6594 22:50:58.619068 <3>[ 15.418111] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6595 22:50:58.635617 <3>[ 15.440179] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6596 22:50:58.651190 <3>[ 15.456354] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6597 22:50:58.666138 <3>[ 15.471046] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6598 22:50:58.682669 <3>[ 15.487375] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6599 22:50:58.699620 <3>[ 15.504578] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6600 22:50:58.715970 <3>[ 15.520835] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6601 22:50:58.731593 <3>[ 15.536785] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6602 22:50:58.747411 <3>[ 15.552596] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6603 22:50:58.775469 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6604 22:50:58.775897
6605 22:50:58.797051 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6606 22:50:58.797555
6607 22:50:58.813544 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6608 22:50:58.813965
6609 22:50:58.862853 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6610 22:50:58.862957
6611 22:50:58.930540 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6612 22:50:58.930681
6613 22:50:58.951822 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6614 22:50:58.951923
6615 22:50:59.044579 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6616 22:50:59.045207
6617 22:50:59.089917 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6618 22:50:59.090548
6619 22:50:59.120781 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6620 22:50:59.121268
6621 22:50:59.147298 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6622 22:50:59.147770
6623 22:50:59.174355 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6624 22:50:59.174931
6625 22:50:59.198250 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6626 22:50:59.198747
6627 22:50:59.218787 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6628 22:50:59.219384
6629 22:50:59.240472 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6630 22:50:59.240965
6631 22:50:59.260354 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6632 22:50:59.260849
6633 22:50:59.280406 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6634 22:50:59.280894
6635 22:50:59.295538 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6636 22:50:59.298693
6637 22:50:59.313340 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6638 22:50:59.313869
6639 22:50:59.329583 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6640 22:50:59.330141
6641 22:50:59.352087 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6642 22:50:59.352570
6643 22:50:59.371863 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6644 22:50:59.372349
6645 22:50:59.389898 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6646 22:50:59.390500
6647 22:50:59.428341 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6648 22:50:59.428879
6649 22:50:59.449031 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6650 22:50:59.449557
6651 22:50:59.465357 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6652 22:50:59.465845
6653 22:50:59.480839 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6654 22:50:59.481323
6655 22:50:59.499842 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6656 22:50:59.500337
6657 22:50:59.517281 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6658 22:50:59.517809
6659 22:50:59.533202 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6660 22:50:59.533715
6661 22:50:59.581989 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6662 22:50:59.582863
6663 22:50:59.604294 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6664 22:50:59.607382
6665 22:50:59.658256 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6666 22:50:59.658891
6667 22:50:59.778292 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6668 22:50:59.778787
6669 22:50:59.805051 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6670 22:50:59.805630
6671 22:50:59.827705 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6672 22:50:59.828184
6673 22:50:59.847342 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6674 22:50:59.847778
6675 22:50:59.958005 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6676 22:50:59.958477
6677 22:51:00.005631 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6678 22:51:00.005772
6679 22:51:00.064118 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6680 22:51:00.064472
6681 22:51:00.089471 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6682 22:51:00.089980
6683 22:51:00.110438 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6684 22:51:00.110973
6685 22:51:00.148543 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6686 22:51:00.149038
6687 22:51:00.172690 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6688 22:51:00.173184
6689 22:51:00.196705 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6690 22:51:00.197247
6691 22:51:00.215439 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6692 22:51:00.215951
6693 22:51:00.260576 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6694 22:51:00.261137
6695 22:51:00.317014 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6696 22:51:00.317207
6697 22:51:00.408992
6698 22:51:00.409140
6699 22:51:00.412838 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6700 22:51:00.412927
6701 22:51:00.415932 debian-bookworm-arm64 login: root (automatic login)
6702 22:51:00.416027
6703 22:51:00.416101
6704 22:51:00.701981 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
6705 22:51:00.702162
6706 22:51:00.707986 The programs included with the Debian GNU/Linux system are free software;
6707 22:51:00.714702 the exact distribution terms for each program are described in the
6708 22:51:00.717948 individual files in /usr/share/doc/*/copyright.
6709 22:51:00.718065
6710 22:51:00.724410 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6711 22:51:00.727485 permitted by applicable law.
6712 22:51:01.901582 Matched prompt #10: / #
6714 22:51:01.902729 Setting prompt string to ['/ #']
6715 22:51:01.903168 end: 2.2.5.1 login-action (duration 00:00:19) [common]
6717 22:51:01.904213 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
6718 22:51:01.904657 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
6719 22:51:01.905124 Setting prompt string to ['/ #']
6720 22:51:01.905518 Forcing a shell prompt, looking for ['/ #']
6722 22:51:01.956576 / #
6723 22:51:01.957175 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6724 22:51:01.957581 Waiting using forced prompt support (timeout 00:02:30)
6725 22:51:01.962696
6726 22:51:01.963624 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6727 22:51:01.964318 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
6729 22:51:02.065738 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683657/extract-nfsrootfs-slg4lw9x'
6730 22:51:02.072201 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683657/extract-nfsrootfs-slg4lw9x'
6732 22:51:02.173647 / # export NFS_SERVER_IP='192.168.201.1'
6733 22:51:02.180389 export NFS_SERVER_IP='192.168.201.1'
6734 22:51:02.181273 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6735 22:51:02.181806 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
6736 22:51:02.182623 end: 2 depthcharge-action (duration 00:01:13) [common]
6737 22:51:02.183161 start: 3 lava-test-retry (timeout 00:08:03) [common]
6738 22:51:02.183729 start: 3.1 lava-test-shell (timeout 00:08:03) [common]
6739 22:51:02.184128 Using namespace: common
6741 22:51:02.285438 / # #
6742 22:51:02.286119 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6743 22:51:02.292075 #
6744 22:51:02.292910 Using /lava-13683657
6746 22:51:02.394126 / # export SHELL=/bin/bash
6747 22:51:02.400475 export SHELL=/bin/bash
6749 22:51:02.502121 / # . /lava-13683657/environment
6750 22:51:02.508480 . /lava-13683657/environment
6752 22:51:02.616452 / # /lava-13683657/bin/lava-test-runner /lava-13683657/0
6753 22:51:02.617093 Test shell timeout: 10s (minimum of the action and connection timeout)
6754 22:51:02.623570 /lava-13683657/bin/lava-test-runner /lava-13683657/0
6755 22:51:02.861334 + export TESTRUN_ID=0_timesync-off
6756 22:51:02.864548 + TESTRUN_ID=0_timesync-off
6757 22:51:02.868278 + cd /lava-13683657/0/tests/0_timesync-off
6758 22:51:02.870941 ++ cat uuid
6759 22:51:02.871035 + UUID=13683657_1.6.2.3.1
6760 22:51:02.874716 + set +x
6761 22:51:02.877473 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13683657_1.6.2.3.1>
6762 22:51:02.877750 Received signal: <STARTRUN> 0_timesync-off 13683657_1.6.2.3.1
6763 22:51:02.877835 Starting test lava.0_timesync-off (13683657_1.6.2.3.1)
6764 22:51:02.877931 Skipping test definition patterns.
6765 22:51:02.880982 + systemctl stop systemd-timesyncd
6766 22:51:02.960845 + set +x
6767 22:51:02.964031 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13683657_1.6.2.3.1>
6768 22:51:02.964716 Received signal: <ENDRUN> 0_timesync-off 13683657_1.6.2.3.1
6769 22:51:02.965111 Ending use of test pattern.
6770 22:51:02.965435 Ending test lava.0_timesync-off (13683657_1.6.2.3.1), duration 0.09
6772 22:51:03.050913 + export TESTRUN_ID=1_kselftest-alsa
6773 22:51:03.051659 + TESTRUN_ID=1_kselftest-alsa
6774 22:51:03.057363 + cd /lava-13683657/0/tests/1_kselftest-alsa
6775 22:51:03.057836 ++ cat uuid
6776 22:51:03.063333 + UUID=13683657_1.6.2.3.5
6777 22:51:03.063818 + set +x
6778 22:51:03.070026 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 13683657_1.6.2.3.5>
6779 22:51:03.070743 Received signal: <STARTRUN> 1_kselftest-alsa 13683657_1.6.2.3.5
6780 22:51:03.071105 Starting test lava.1_kselftest-alsa (13683657_1.6.2.3.5)
6781 22:51:03.071580 Skipping test definition patterns.
6782 22:51:03.073409 + cd ./automated/linux/kselftest/
6783 22:51:03.099178 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6784 22:51:03.151469 INFO: install_deps skipped
6785 22:51:03.659965 --2024-05-07 22:51:03-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6786 22:51:03.666685 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6787 22:51:03.791209 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6788 22:51:03.920162 HTTP request sent, awaiting response... 200 OK
6789 22:51:03.923448 Length: 1651624 (1.6M) [application/octet-stream]
6790 22:51:03.926845 Saving to: 'kselftest_armhf.tar.gz'
6791 22:51:03.927374
6792 22:51:03.927717
6793 22:51:04.179058 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6794 22:51:04.436351 kselftest_armhf.tar 2%[ ] 47.81K 189KB/s
6795 22:51:04.741170 kselftest_armhf.tar 13%[=> ] 214.67K 426KB/s
6796 22:51:04.872766 kselftest_armhf.tar 50%[=========> ] 819.89K 1022KB/s
6797 22:51:04.879524 kselftest_armhf.tar 100%[===================>] 1.57M 1.69MB/s in 0.9s
6798 22:51:04.879994
6799 22:51:05.024736 2024-05-07 22:51:05 (1.69 MB/s) - 'kselftest_armhf.tar.gz' saved [1651624/1651624]
6800 22:51:05.025027
6801 22:51:09.257239 skiplist:
6802 22:51:09.260763 ========================================
6803 22:51:09.263827 ========================================
6804 22:51:09.311342 alsa:mixer-test
6805 22:51:09.329615 ============== Tests to run ===============
6806 22:51:09.329750 alsa:mixer-test
6807 22:51:09.332826 ===========End Tests to run ===============
6808 22:51:09.336120 shardfile-alsa pass
6809 22:51:09.449325 <12>[ 26.257552] kselftest: Running tests in alsa
6810 22:51:09.462522 TAP version 13
6811 22:51:09.479186 1..1
6812 22:51:09.497064 # selftests: alsa: mixer-test
6813 22:51:09.590450 <6>[ 26.392295] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6814 22:51:09.603543 <6>[ 26.404588] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6815 22:51:09.616435 <6>[ 26.416823] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6816 22:51:09.626123 <6>[ 26.429030] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6817 22:51:09.639072 <6>[ 26.441298] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6818 22:51:09.652082 <6>[ 26.453481] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6819 22:51:09.662009 <6>[ 26.464825] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6820 22:51:09.674736 <6>[ 26.476162] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6821 22:51:09.684765 <6>[ 26.487495] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6822 22:51:09.697732 <6>[ 26.498829] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6823 22:51:09.707590 <6>[ 26.510166] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6824 22:51:09.720736 <6>[ 26.521497] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6825 22:51:09.730328 <6>[ 26.532832] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6826 22:51:09.739990 <6>[ 26.544165] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6827 22:51:09.753266 <6>[ 26.555496] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6828 22:51:09.763048 <6>[ 26.566847] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6829 22:51:09.776415 <6>[ 26.578182] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6830 22:51:09.785933 <6>[ 26.589545] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6831 22:51:09.798923 <6>[ 26.600883] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6832 22:51:09.808630 <6>[ 26.612225] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6833 22:51:09.822097 <6>[ 26.623571] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6834 22:51:09.831561 <6>[ 26.634929] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6835 22:51:09.844756 <6>[ 26.646294] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6836 22:51:09.854509 <6>[ 26.657670] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6837 22:51:09.867347 <6>[ 26.669039] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6838 22:51:09.877284 <6>[ 26.680423] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6839 22:51:09.890568 # TAP version 13<6>[ 26.691805] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6840 22:51:09.890681
6841 22:51:09.890756 # 1..658
6842 22:51:09.903593 # ok<6>[ 26.704465] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6843 22:51:09.913653 <6>[ 26.717134] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6844 22:51:09.926399 <6>[ 26.728469] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6845 22:51:09.926521 1 get_value.0.93
6846 22:51:09.929517 # ok 2 name.0.93
6847 22:51:09.933177 # ok 3 write_default.0.93
6848 22:51:09.933272 # ok 4 write_valid.0.93
6849 22:51:09.936037 # ok 5 write_invalid.0.93
6850 22:51:09.939828 # ok 6 event_missing.0.93
6851 22:51:09.942598 # ok 7 event_spurious.0.93
6852 22:51:09.942691 # ok 8 get_value.0.92
6853 22:51:09.946233 # ok 9 name.0.92
6854 22:51:09.946326 # ok 10 write_default.0.92
6855 22:51:09.948987 # ok 11 write_valid.0.92
6856 22:51:09.952254 # ok 12 write_invalid.0.92
6857 22:51:09.955667 # ok 13 event_missing.0.92
6858 22:51:09.955795 # ok 14 event_spurious.0.92
6859 22:51:09.959687 # ok 15 get_value.0.91
6860 22:51:09.962994 # ok 16 name.0.91
6861 22:51:09.963170 # ok 17 write_default.0.91
6862 22:51:09.965906 # ok 18 write_valid.0.91
6863 22:51:09.968997 # ok 19 write_invalid.0.91
6864 22:51:09.972433 # ok 20 event_missing.0.91
6865 22:51:09.976137 # ok 21 event_spurious.0.91
6866 22:51:09.976563 # ok 22 get_value.0.90
6867 22:51:09.979652 # ok 23 name.0.90
6868 22:51:09.982427 # ok 24 write_default.0.90
6869 22:51:09.986104 # ok 25 write_valid.0.90
6870 22:51:09.986630 # ok 26 write_invalid.0.90
6871 22:51:09.988846 # ok 27 event_missing.0.90
6872 22:51:09.992375 # ok 28 event_spurious.0.90
6873 22:51:09.995605 # ok 29 get_value.0.89
6874 22:51:09.996127 # ok 30 name.0.89
6875 22:51:09.998752 # ok 31 write_default.0.89
6876 22:51:10.002422 # ok 32 write_valid.0.89
6877 22:51:10.002951 # ok 33 write_invalid.0.89
6878 22:51:10.006079 # ok 34 event_missing.0.89
6879 22:51:10.008713 # ok 35 event_spurious.0.89
6880 22:51:10.011917 # ok 36 get_value.0.88
6881 22:51:10.012625 # ok 37 name.0.88
6882 22:51:10.015612 # ok 38 write_default.0.88
6883 22:51:10.018393 # # Spurious event generated for AIF Out Mux
6884 22:51:10.025178 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6885 22:51:10.028106 # # Spurious event generated for AIF Out Mux
6886 22:51:10.031175 # not ok 39 write_valid.0.88
6887 22:51:10.031638 # ok 40 write_invalid.0.88
6888 22:51:10.034666 # ok 41 event_missing.0.88
6889 22:51:10.037989 # not ok 42 event_spurious.0.88
6890 22:51:10.041281 # ok 43 get_value.0.87
6891 22:51:10.041808 # ok 44 name.0.87
6892 22:51:10.044536 # ok 45 write_default.0.87
6893 22:51:10.047744 # ok 46 write_valid.0.87
6894 22:51:10.051420 # ok 47 write_invalid.0.87
6895 22:51:10.051948 # ok 48 event_missing.0.87
6896 22:51:10.054733 # ok 49 event_spurious.0.87
6897 22:51:10.057665 # ok 50 get_value.0.86
6898 22:51:10.058191 # ok 51 name.0.86
6899 22:51:10.060776 # ok 52 write_default.0.86
6900 22:51:10.067867 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6901 22:51:10.070573 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6902 22:51:10.074032 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6903 22:51:10.077377 # not ok 53 write_valid.0.86
6904 22:51:10.080539 # ok 54 write_invalid.0.86
6905 22:51:10.083991 # ok 55 event_missing.0.86
6906 22:51:10.084418 # ok 56 event_spurious.0.86
6907 22:51:10.087538 # ok 57 get_value.0.85
6908 22:51:10.090504 # ok 58 name.0.85
6909 22:51:10.091031 # ok 59 write_default.0.85
6910 22:51:10.097141 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6911 22:51:10.100103 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6912 22:51:10.106869 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6913 22:51:10.110005 # not ok 60 write_valid.0.85
6914 22:51:10.110534 # ok 61 write_invalid.0.85
6915 22:51:10.112942 # ok 62 event_missing.0.85
6916 22:51:10.116268 # ok 63 event_spurious.0.85
6917 22:51:10.119504 # ok 64 get_value.0.84
6918 22:51:10.119936 # ok 65 name.0.84
6919 22:51:10.123372 # ok 66 write_default.0.84
6920 22:51:10.126508 # ok 67 write_valid.0.84
6921 22:51:10.126938 # ok 68 write_invalid.0.84
6922 22:51:10.129322 # ok 69 event_missing.0.84
6923 22:51:10.132623 # ok 70 event_spurious.0.84
6924 22:51:10.135785 # ok 71 get_value.0.83
6925 22:51:10.136214 # ok 72 name.0.83
6926 22:51:10.139190 # ok 73 write_default.0.83
6927 22:51:10.142809 # ok 74 write_valid.0.83
6928 22:51:10.143374 # ok 75 write_invalid.0.83
6929 22:51:10.145529 # ok 76 event_missing.0.83
6930 22:51:10.148643 # ok 77 event_spurious.0.83
6931 22:51:10.151927 # ok 78 get_value.0.82
6932 22:51:10.152361 # ok 79 name.0.82
6933 22:51:10.155969 # # Headset Jack is not writeable
6934 22:51:10.158680 # ok 80 # SKIP write_default.0.82
6935 22:51:10.162021 # # Headset Jack is not writeable
6936 22:51:10.165443 # ok 81 # SKIP write_valid.0.82
6937 22:51:10.167990 # # Headset Jack is not writeable
6938 22:51:10.171372 # ok 82 # SKIP write_invalid.0.82
6939 22:51:10.174985 # ok 83 event_missing.0.82
6940 22:51:10.175466 # ok 84 event_spurious.0.82
6941 22:51:10.178321 # ok 85 get_value.0.81
6942 22:51:10.181298 # ok 86 name.0.81
6943 22:51:10.181727 # ok 87 write_default.0.81
6944 22:51:10.188037 # # No event generated for Wake-on-Voice Phase2 Switch
6945 22:51:10.191120 # # No event generated for Wake-on-Voice Phase2 Switch
6946 22:51:10.194148 # ok 88 write_valid.0.81
6947 22:51:10.201101 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6948 22:51:10.204052 # # No event generated for Wake-on-Voice Phase2 Switch
6949 22:51:10.207281 # not ok 89 write_invalid.0.81
6950 22:51:10.211101 # not ok 90 event_missing.0.81
6951 22:51:10.214078 # ok 91 event_spurious.0.81
6952 22:51:10.214321 # ok 92 get_value.0.80
6953 22:51:10.217063 # ok 93 name.0.80
6954 22:51:10.220620 # ok 94 write_default.0.80
6955 22:51:10.220789 # ok 95 write_valid.0.80
6956 22:51:10.223711 # ok 96 write_invalid.0.80
6957 22:51:10.226519 # ok 97 event_missing.0.80
6958 22:51:10.230237 # ok 98 event_spurious.0.80
6959 22:51:10.232885 # # Handset Volume.0 value -13 less than minimum 0
6960 22:51:10.236701 # not ok 99 get_value.0.79
6961 22:51:10.240024 # ok 100 name.0.79
6962 22:51:10.243051 # # snd_ctl_elem_write() failed: Invalid argument
6963 22:51:10.246384 # not ok 101 write_default.0.79
6964 22:51:10.249625 # # snd_ctl_elem_write() failed: Invalid argument
6965 22:51:10.252529 # not ok 102 write_valid.0.79
6966 22:51:10.256139 # # snd_ctl_elem_write() failed: Invalid argument
6967 22:51:10.259727 # not ok 103 write_invalid.0.79
6968 22:51:10.262843 # ok 104 event_missing.0.79
6969 22:51:10.266262 # ok 105 event_spurious.0.79
6970 22:51:10.269508 # # Lineout Volume.0 value -13 less than minimum 0
6971 22:51:10.275624 # # Lineout Volume.1 value -13 less than minimum 0
6972 22:51:10.276103 # not ok 106 get_value.0.78
6973 22:51:10.278984 # ok 107 name.0.78
6974 22:51:10.282447 # # snd_ctl_elem_write() failed: Invalid argument
6975 22:51:10.286889 # not ok 108 write_default.0.78
6976 22:51:10.292724 # # snd_ctl_elem_write() failed: Invalid argument
6977 22:51:10.295912 # not ok 109 write_valid.0.78
6978 22:51:10.299032 # # snd_ctl_elem_write() failed: Invalid argument
6979 22:51:10.302669 # not ok 110 write_invalid.0.78
6980 22:51:10.306054 # ok 111 event_missing.0.78
6981 22:51:10.306590 # ok 112 event_spurious.0.78
6982 22:51:10.311889 # # Headphone Volume.0 value -13 less than minimum 0
6983 22:51:10.315179 # # Headphone Volume.1 value -13 less than minimum 0
6984 22:51:10.318182 # not ok 113 get_value.0.77
6985 22:51:10.321561 # ok 114 name.0.77
6986 22:51:10.324752 # # snd_ctl_elem_write() failed: Invalid argument
6987 22:51:10.327943 # not ok 115 write_default.0.77
6988 22:51:10.331406 # # snd_ctl_elem_write() failed: Invalid argument
6989 22:51:10.335010 # not ok 116 write_valid.0.77
6990 22:51:10.341164 # # snd_ctl_elem_write() failed: Invalid argument
6991 22:51:10.344756 # not ok 117 write_invalid.0.77
6992 22:51:10.345193 # ok 118 event_missing.0.77
6993 22:51:10.347918 # ok 119 event_spurious.0.77
6994 22:51:10.350779 # ok 120 get_value.0.76
6995 22:51:10.358059 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6996 22:51:10.361464 # not ok 121 name.0.76
6997 22:51:10.361998 # ok 122 write_default.0.76
6998 22:51:10.364532 # ok 123 write_valid.0.76
6999 22:51:10.367332 # ok 124 write_invalid.0.76
7000 22:51:10.370509 # ok 125 event_missing.0.76
7001 22:51:10.373993 # ok 126 event_spurious.0.76
7002 22:51:10.374426 # ok 127 get_value.0.75
7003 22:51:10.380197 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
7004 22:51:10.383527 # not ok 128 name.0.75
7005 22:51:10.386824 # ok 129 write_default.0.75
7006 22:51:10.389760 # ok 130 write_valid.0.75
7007 22:51:10.390244 # ok 131 write_invalid.0.75
7008 22:51:10.393238 # ok 132 event_missing.0.75
7009 22:51:10.396726 # ok 133 event_spurious.0.75
7010 22:51:10.399531 # ok 134 get_value.0.74
7011 22:51:10.406117 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
7012 22:51:10.406552 # not ok 135 name.0.74
7013 22:51:10.409828 # ok 136 write_default.0.74
7014 22:51:10.413163 # ok 137 write_valid.0.74
7015 22:51:10.416373 # ok 138 write_invalid.0.74
7016 22:51:10.419191 # ok 139 event_missing.0.74
7017 22:51:10.419664 # ok 140 event_spurious.0.74
7018 22:51:10.422827 # ok 141 get_value.0.73
7019 22:51:10.429161 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
7020 22:51:10.432114 # not ok 142 name.0.73
7021 22:51:10.435643 # ok 143 write_default.0.73
7022 22:51:10.436079 # ok 144 write_valid.0.73
7023 22:51:10.438576 # ok 145 write_invalid.0.73
7024 22:51:10.442114 # ok 146 event_missing.0.73
7025 22:51:10.445556 # ok 147 event_spurious.0.73
7026 22:51:10.449529 # ok 148 get_value.0.72
7027 22:51:10.454881 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
7028 22:51:10.455437 # not ok 149 name.0.72
7029 22:51:10.459013 # ok 150 write_default.0.72
7030 22:51:10.462026 # ok 151 write_valid.0.72
7031 22:51:10.465092 # ok 152 write_invalid.0.72
7032 22:51:10.465524 # ok 153 event_missing.0.72
7033 22:51:10.468793 # ok 154 event_spurious.0.72
7034 22:51:10.471738 # ok 155 get_value.0.71
7035 22:51:10.479065 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7036 22:51:10.479622 # not ok 156 name.0.71
7037 22:51:10.482640 # ok 157 write_default.0.71
7038 22:51:10.485055 # ok 158 write_valid.0.71
7039 22:51:10.488266 # ok 159 write_invalid.0.71
7040 22:51:10.488697 # ok 160 event_missing.0.71
7041 22:51:10.491897 # ok 161 event_spurious.0.71
7042 22:51:10.494995 # ok 162 get_value.0.70
7043 22:51:10.501514 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
7044 22:51:10.502046 # not ok 163 name.0.70
7045 22:51:10.504752 # ok 164 write_default.0.70
7046 22:51:10.507852 # ok 165 write_valid.0.70
7047 22:51:10.511245 # ok 166 write_invalid.0.70
7048 22:51:10.511682 # ok 167 event_missing.0.70
7049 22:51:10.514011 # ok 168 event_spurious.0.70
7050 22:51:10.517304 # ok 169 get_value.0.69
7051 22:51:10.524014 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
7052 22:51:10.527349 # not ok 170 name.0.69
7053 22:51:10.527888 # ok 171 write_default.0.69
7054 22:51:10.530240 # ok 172 write_valid.0.69
7055 22:51:10.533823 # ok 173 write_invalid.0.69
7056 22:51:10.537103 # ok 174 event_missing.0.69
7057 22:51:10.540227 # ok 175 event_spurious.0.69
7058 22:51:10.540656 # ok 176 get_value.0.68
7059 22:51:10.546905 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
7060 22:51:10.550452 # not ok 177 name.0.68
7061 22:51:10.554131 # ok 178 write_default.0.68
7062 22:51:10.554668 # ok 179 write_valid.0.68
7063 22:51:10.556424 # ok 180 write_invalid.0.68
7064 22:51:10.560053 # ok 181 event_missing.0.68
7065 22:51:10.562942 # ok 182 event_spurious.0.68
7066 22:51:10.563410 # ok 183 get_value.0.67
7067 22:51:10.569791 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
7068 22:51:10.573473 # not ok 184 name.0.67
7069 22:51:10.576136 # ok 185 write_default.0.67
7070 22:51:10.580176 # ok 186 write_valid.0.67
7071 22:51:10.580713 # ok 187 write_invalid.0.67
7072 22:51:10.582508 # ok 188 event_missing.0.67
7073 22:51:10.586012 # ok 189 event_spurious.0.67
7074 22:51:10.589876 # ok 190 get_value.0.66
7075 22:51:10.595693 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
7076 22:51:10.596234 # not ok 191 name.0.66
7077 22:51:10.599455 # ok 192 write_default.0.66
7078 22:51:10.602673 # ok 193 write_valid.0.66
7079 22:51:10.606097 # ok 194 write_invalid.0.66
7080 22:51:10.606634 # ok 195 event_missing.0.66
7081 22:51:10.608941 # ok 196 event_spurious.0.66
7082 22:51:10.612003 # ok 197 get_value.0.65
7083 22:51:10.618776 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
7084 22:51:10.619352 # not ok 198 name.0.65
7085 22:51:10.621826 # ok 199 write_default.0.65
7086 22:51:10.625052 # ok 200 write_valid.0.65
7087 22:51:10.628371 # ok 201 write_invalid.0.65
7088 22:51:10.631578 # ok 202 event_missing.0.65
7089 22:51:10.632202 # ok 203 event_spurious.0.65
7090 22:51:10.634942 # ok 204 get_value.0.64
7091 22:51:10.642162 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
7092 22:51:10.644928 # not ok 205 name.0.64
7093 22:51:10.647814 # ok 206 write_default.0.64
7094 22:51:10.648279 # ok 207 write_valid.0.64
7095 22:51:10.651154 # ok 208 write_invalid.0.64
7096 22:51:10.654232 # ok 209 event_missing.0.64
7097 22:51:10.658268 # ok 210 event_spurious.0.64
7098 22:51:10.658699 # ok 211 get_value.0.63
7099 22:51:10.667522 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
7100 22:51:10.668067 # not ok 212 name.0.63
7101 22:51:10.670744 # ok 213 write_default.0.63
7102 22:51:10.674235 # ok 214 write_valid.0.63
7103 22:51:10.674763 # ok 215 write_invalid.0.63
7104 22:51:10.676973 # ok 216 event_missing.0.63
7105 22:51:10.680803 # ok 217 event_spurious.0.63
7106 22:51:10.683495 # ok 218 get_value.0.62
7107 22:51:10.690957 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7108 22:51:10.691524 # not ok 219 name.0.62
7109 22:51:10.693317 # ok 220 write_default.0.62
7110 22:51:10.696715 # ok 221 write_valid.0.62
7111 22:51:10.700293 # ok 222 write_invalid.0.62
7112 22:51:10.703744 # ok 223 event_missing.0.62
7113 22:51:10.704280 # ok 224 event_spurious.0.62
7114 22:51:10.706820 # ok 225 get_value.0.61
7115 22:51:10.712936 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7116 22:51:10.716304 # not ok 226 name.0.61
7117 22:51:10.719902 # ok 227 write_default.0.61
7118 22:51:10.720333 # ok 228 write_valid.0.61
7119 22:51:10.722967 # ok 229 write_invalid.0.61
7120 22:51:10.726092 # ok 230 event_missing.0.61
7121 22:51:10.729146 # ok 231 event_spurious.0.61
7122 22:51:10.729581 # ok 232 get_value.0.60
7123 22:51:10.735514 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
7124 22:51:10.739149 # not ok 233 name.0.60
7125 22:51:10.742974 # ok 234 write_default.0.60
7126 22:51:10.746086 # ok 235 write_valid.0.60
7127 22:51:10.746612 # ok 236 write_invalid.0.60
7128 22:51:10.748928 # ok 237 event_missing.0.60
7129 22:51:10.751840 # ok 238 event_spurious.0.60
7130 22:51:10.755194 # ok 239 get_value.0.59
7131 22:51:10.761748 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
7132 22:51:10.762259 # not ok 240 name.0.59
7133 22:51:10.765931 # ok 241 write_default.0.59
7134 22:51:10.768856 # ok 242 write_valid.0.59
7135 22:51:10.771589 # ok 243 write_invalid.0.59
7136 22:51:10.772024 # ok 244 event_missing.0.59
7137 22:51:10.775000 # ok 245 event_spurious.0.59
7138 22:51:10.778769 # ok 246 get_value.0.58
7139 22:51:10.785198 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
7140 22:51:10.785803 # not ok 247 name.0.58
7141 22:51:10.787924 # ok 248 write_default.0.58
7142 22:51:10.791083 # ok 249 write_valid.0.58
7143 22:51:10.794424 # ok 250 write_invalid.0.58
7144 22:51:10.798115 # ok 251 event_missing.0.58
7145 22:51:10.798655 # ok 252 event_spurious.0.58
7146 22:51:10.801571 # ok 253 get_value.0.57
7147 22:51:10.807381 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
7148 22:51:10.811126 # not ok 254 name.0.57
7149 22:51:10.811712 # ok 255 write_default.0.57
7150 22:51:10.814488 # ok 256 write_valid.0.57
7151 22:51:10.817386 # ok 257 write_invalid.0.57
7152 22:51:10.820832 # ok 258 event_missing.0.57
7153 22:51:10.824943 # ok 259 event_spurious.0.57
7154 22:51:10.825377 # ok 260 get_value.0.56
7155 22:51:10.830528 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
7156 22:51:10.833801 # not ok 261 name.0.56
7157 22:51:10.837125 # ok 262 write_default.0.56
7158 22:51:10.837554 # ok 263 write_valid.0.56
7159 22:51:10.840477 # ok 264 write_invalid.0.56
7160 22:51:10.843514 # ok 265 event_missing.0.56
7161 22:51:10.846684 # ok 266 event_spurious.0.56
7162 22:51:10.847214 # ok 267 get_value.0.55
7163 22:51:10.853062 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
7164 22:51:10.856631 # not ok 268 name.0.55
7165 22:51:10.860071 # ok 269 write_default.0.55
7166 22:51:10.860609 # ok 270 write_valid.0.55
7167 22:51:10.862984 # ok 271 write_invalid.0.55
7168 22:51:10.866186 # ok 272 event_missing.0.55
7169 22:51:10.870349 # ok 273 event_spurious.0.55
7170 22:51:10.870886 # ok 274 get_value.0.54
7171 22:51:10.876844 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
7172 22:51:10.879316 # not ok 275 name.0.54
7173 22:51:10.883330 # ok 276 write_default.0.54
7174 22:51:10.883875 # ok 277 write_valid.0.54
7175 22:51:10.885460 # ok 278 write_invalid.0.54
7176 22:51:10.888777 # ok 279 event_missing.0.54
7177 22:51:10.891997 # ok 280 event_spurious.0.54
7178 22:51:10.892437 # ok 281 get_value.0.53
7179 22:51:10.898753 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
7180 22:51:10.902653 # not ok 282 name.0.53
7181 22:51:10.905622 # ok 283 write_default.0.53
7182 22:51:10.906185 # ok 284 write_valid.0.53
7183 22:51:10.909129 # ok 285 write_invalid.0.53
7184 22:51:10.912014 # ok 286 event_missing.0.53
7185 22:51:10.915469 # ok 287 event_spurious.0.53
7186 22:51:10.916001 # ok 288 get_value.0.52
7187 22:51:10.921690 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
7188 22:51:10.925037 # not ok 289 name.0.52
7189 22:51:10.927803 # ok 290 write_default.0.52
7190 22:51:10.928268 # ok 291 write_valid.0.52
7191 22:51:10.931112 # ok 292 write_invalid.0.52
7192 22:51:10.934646 # ok 293 event_missing.0.52
7193 22:51:10.937593 # ok 294 event_spurious.0.52
7194 22:51:10.938038 # ok 295 get_value.0.51
7195 22:51:10.944512 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
7196 22:51:10.947300 # not ok 296 name.0.51
7197 22:51:10.950702 # ok 297 write_default.0.51
7198 22:51:10.954497 # ok 298 write_valid.0.51
7199 22:51:10.955085 # ok 299 write_invalid.0.51
7200 22:51:10.957230 # ok 300 event_missing.0.51
7201 22:51:10.960535 # ok 301 event_spurious.0.51
7202 22:51:10.963593 # ok 302 get_value.0.50
7203 22:51:10.970386 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
7204 22:51:10.970833 # not ok 303 name.0.50
7205 22:51:10.973986 # ok 304 write_default.0.50
7206 22:51:10.977158 # ok 305 write_valid.0.50
7207 22:51:10.980309 # ok 306 write_invalid.0.50
7208 22:51:10.980848 # ok 307 event_missing.0.50
7209 22:51:10.983586 # ok 308 event_spurious.0.50
7210 22:51:10.986825 # ok 309 get_value.0.49
7211 22:51:10.993179 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
7212 22:51:10.993706 # not ok 310 name.0.49
7213 22:51:10.997242 # ok 311 write_default.0.49
7214 22:51:11.000158 # ok 312 write_valid.0.49
7215 22:51:11.003585 # ok 313 write_invalid.0.49
7216 22:51:11.004122 # ok 314 event_missing.0.49
7217 22:51:11.006523 # ok 315 event_spurious.0.49
7218 22:51:11.010234 # ok 316 get_value.0.48
7219 22:51:11.017201 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
7220 22:51:11.017790 # not ok 317 name.0.48
7221 22:51:11.019723 # ok 318 write_default.0.48
7222 22:51:11.022380 # ok 319 write_valid.0.48
7223 22:51:11.026984 # ok 320 write_invalid.0.48
7224 22:51:11.030042 # ok 321 event_missing.0.48
7225 22:51:11.030488 # ok 322 event_spurious.0.48
7226 22:51:11.032439 # ok 323 get_value.0.47
7227 22:51:11.039208 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
7228 22:51:11.042299 # not ok 324 name.0.47
7229 22:51:11.042766 # ok 325 write_default.0.47
7230 22:51:11.045698 # ok 326 write_valid.0.47
7231 22:51:11.049067 # ok 327 write_invalid.0.47
7232 22:51:11.052343 # ok 328 event_missing.0.47
7233 22:51:11.052835 # ok 329 event_spurious.0.47
7234 22:51:11.055201 # ok 330 get_value.0.46
7235 22:51:11.062090 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
7236 22:51:11.065562 # not ok 331 name.0.46
7237 22:51:11.066082 # ok 332 write_default.0.46
7238 22:51:11.068849 # ok 333 write_valid.0.46
7239 22:51:11.072127 # ok 334 write_invalid.0.46
7240 22:51:11.075732 # ok 335 event_missing.0.46
7241 22:51:11.078999 # ok 336 event_spurious.0.46
7242 22:51:11.079560 # ok 337 get_value.0.45
7243 22:51:11.085239 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
7244 22:51:11.088496 # not ok 338 name.0.45
7245 22:51:11.089015 # ok 339 write_default.0.45
7246 22:51:11.091740 # ok 340 write_valid.0.45
7247 22:51:11.095059 # ok 341 write_invalid.0.45
7248 22:51:11.098443 # ok 342 event_missing.0.45
7249 22:51:11.101435 # ok 343 event_spurious.0.45
7250 22:51:11.101952 # ok 344 get_value.0.44
7251 22:51:11.108302 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
7252 22:51:11.111318 # not ok 345 name.0.44
7253 22:51:11.114621 # ok 346 write_default.0.44
7254 22:51:11.115294 # ok 347 write_valid.0.44
7255 22:51:11.122102 # ok 348 write_invalid.0.44
7256 22:51:11.122704 # ok 349 event_missing.0.44
7257 22:51:11.123850 # ok 350 event_spurious.0.44
7258 22:51:11.124233 # ok 351 get_value.0.43
7259 22:51:11.130574 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
7260 22:51:11.134078 # not ok 352 name.0.43
7261 22:51:11.137661 # ok 353 write_default.0.43
7262 22:51:11.138195 # ok 354 write_valid.0.43
7263 22:51:11.140929 # ok 355 write_invalid.0.43
7264 22:51:11.143598 # ok 356 event_missing.0.43
7265 22:51:11.147291 # ok 357 event_spurious.0.43
7266 22:51:11.147721 # ok 358 get_value.0.42
7267 22:51:11.153762 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
7268 22:51:11.157129 # not ok 359 name.0.42
7269 22:51:11.160331 # ok 360 write_default.0.42
7270 22:51:11.160859 # ok 361 write_valid.0.42
7271 22:51:11.163921 # ok 362 write_invalid.0.42
7272 22:51:11.166982 # ok 363 event_missing.0.42
7273 22:51:11.170613 # ok 364 event_spurious.0.42
7274 22:51:11.171172 # ok 365 get_value.0.41
7275 22:51:11.176812 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
7276 22:51:11.179850 # not ok 366 name.0.41
7277 22:51:11.183454 # ok 367 write_default.0.41
7278 22:51:11.183881 # ok 368 write_valid.0.41
7279 22:51:11.186327 # ok 369 write_invalid.0.41
7280 22:51:11.189731 # ok 370 event_missing.0.41
7281 22:51:11.193313 # ok 371 event_spurious.0.41
7282 22:51:11.195985 # ok 372 get_value.0.40
7283 22:51:11.200133 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
7284 22:51:11.203456 # not ok 373 name.0.40
7285 22:51:11.206451 # ok 374 write_default.0.40
7286 22:51:11.209590 # ok 375 write_valid.0.40
7287 22:51:11.210025 # ok 376 write_invalid.0.40
7288 22:51:11.212536 # ok 377 event_missing.0.40
7289 22:51:11.216584 # ok 378 event_spurious.0.40
7290 22:51:11.219652 # ok 379 get_value.0.39
7291 22:51:11.225790 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7292 22:51:11.226227 # not ok 380 name.0.39
7293 22:51:11.228997 # ok 381 write_default.0.39
7294 22:51:11.232325 # ok 382 write_valid.0.39
7295 22:51:11.235810 # ok 383 write_invalid.0.39
7296 22:51:11.236236 # ok 384 event_missing.0.39
7297 22:51:11.238747 # ok 385 event_spurious.0.39
7298 22:51:11.241971 # ok 386 get_value.0.38
7299 22:51:11.248711 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7300 22:51:11.252045 # not ok 387 name.0.38
7301 22:51:11.252470 # ok 388 write_default.0.38
7302 22:51:11.255244 # ok 389 write_valid.0.38
7303 22:51:11.258538 # ok 390 write_invalid.0.38
7304 22:51:11.262132 # ok 391 event_missing.0.38
7305 22:51:11.262662 # ok 392 event_spurious.0.38
7306 22:51:11.264987 # ok 393 get_value.0.37
7307 22:51:11.271318 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7308 22:51:11.274851 # not ok 394 name.0.37
7309 22:51:11.277921 # ok 395 write_default.0.37
7310 22:51:11.278351 # ok 396 write_valid.0.37
7311 22:51:11.281591 # ok 397 write_invalid.0.37
7312 22:51:11.284443 # ok 398 event_missing.0.37
7313 22:51:11.287697 # ok 399 event_spurious.0.37
7314 22:51:11.288128 # ok 400 get_value.0.36
7315 22:51:11.293981 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7316 22:51:11.297358 # not ok 401 name.0.36
7317 22:51:11.300562 # ok 402 write_default.0.36
7318 22:51:11.303672 # ok 403 write_valid.0.36
7319 22:51:11.304102 # ok 404 write_invalid.0.36
7320 22:51:11.307336 # ok 405 event_missing.0.36
7321 22:51:11.310154 # ok 406 event_spurious.0.36
7322 22:51:11.313349 # ok 407 get_value.0.35
7323 22:51:11.320187 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7324 22:51:11.320821 # not ok 408 name.0.35
7325 22:51:11.324382 # ok 409 write_default.0.35
7326 22:51:11.326883 # ok 410 write_valid.0.35
7327 22:51:11.330267 # ok 411 write_invalid.0.35
7328 22:51:11.333353 # ok 412 event_missing.0.35
7329 22:51:11.333795 # ok 413 event_spurious.0.35
7330 22:51:11.336234 # ok 414 get_value.0.34
7331 22:51:11.343066 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7332 22:51:11.346583 # not ok 415 name.0.34
7333 22:51:11.347119 # ok 416 write_default.0.34
7334 22:51:11.349356 # ok 417 write_valid.0.34
7335 22:51:11.352716 # ok 418 write_invalid.0.34
7336 22:51:11.355902 # ok 419 event_missing.0.34
7337 22:51:11.360690 # ok 420 event_spurious.0.34
7338 22:51:11.361153 # ok 421 get_value.0.33
7339 22:51:11.365648 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7340 22:51:11.369153 # not ok 422 name.0.33
7341 22:51:11.372350 # ok 423 write_default.0.33
7342 22:51:11.372900 # ok 424 write_valid.0.33
7343 22:51:11.375603 # ok 425 write_invalid.0.33
7344 22:51:11.379107 # ok 426 event_missing.0.33
7345 22:51:11.382775 # ok 427 event_spurious.0.33
7346 22:51:11.383378 # ok 428 get_value.0.32
7347 22:51:11.388753 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7348 22:51:11.391954 # not ok 429 name.0.32
7349 22:51:11.395390 # ok 430 write_default.0.32
7350 22:51:11.399595 # ok 431 write_valid.0.32
7351 22:51:11.400121 # ok 432 write_invalid.0.32
7352 22:51:11.401614 # ok 433 event_missing.0.32
7353 22:51:11.405307 # ok 434 event_spurious.0.32
7354 22:51:11.408512 # ok 435 get_value.0.31
7355 22:51:11.415052 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7356 22:51:11.415683 # not ok 436 name.0.31
7357 22:51:11.418112 # ok 437 write_default.0.31
7358 22:51:11.421908 # ok 438 write_valid.0.31
7359 22:51:11.424613 # ok 439 write_invalid.0.31
7360 22:51:11.425044 # ok 440 event_missing.0.31
7361 22:51:11.427804 # ok 441 event_spurious.0.31
7362 22:51:11.430922 # ok 442 get_value.0.30
7363 22:51:11.437768 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7364 22:51:11.441106 # not ok 443 name.0.30
7365 22:51:11.441626 # ok 444 write_default.0.30
7366 22:51:11.444711 # ok 445 write_valid.0.30
7367 22:51:11.447393 # ok 446 write_invalid.0.30
7368 22:51:11.450993 # ok 447 event_missing.0.30
7369 22:51:11.453989 # ok 448 event_spurious.0.30
7370 22:51:11.454425 # ok 449 get_value.0.29
7371 22:51:11.457471 # ok 450 name.0.29
7372 22:51:11.460357 # ok 451 write_default.0.29
7373 22:51:11.460790 # ok 452 write_valid.0.29
7374 22:51:11.464123 # ok 453 write_invalid.0.29
7375 22:51:11.466961 # ok 454 event_missing.0.29
7376 22:51:11.470605 # ok 455 event_spurious.0.29
7377 22:51:11.471127 # ok 456 get_value.0.28
7378 22:51:11.473625 # ok 457 name.0.28
7379 22:51:11.477359 # ok 458 write_default.0.28
7380 22:51:11.479903 # ok 459 write_valid.0.28
7381 22:51:11.480333 # ok 460 write_invalid.0.28
7382 22:51:11.483839 # ok 461 event_missing.0.28
7383 22:51:11.486870 # ok 462 event_spurious.0.28
7384 22:51:11.489884 # ok 463 get_value.0.27
7385 22:51:11.490319 # ok 464 name.0.27
7386 22:51:11.492981 # ok 465 write_default.0.27
7387 22:51:11.496782 # ok 466 write_valid.0.27
7388 22:51:11.497308 # ok 467 write_invalid.0.27
7389 22:51:11.499901 # ok 468 event_missing.0.27
7390 22:51:11.503621 # ok 469 event_spurious.0.27
7391 22:51:11.506407 # ok 470 get_value.0.26
7392 22:51:11.506934 # ok 471 name.0.26
7393 22:51:11.509802 # ok 472 write_default.0.26
7394 22:51:11.513241 # ok 473 write_valid.0.26
7395 22:51:11.516332 # ok 474 write_invalid.0.26
7396 22:51:11.516987 # ok 475 event_missing.0.26
7397 22:51:11.518867 # ok 476 event_spurious.0.26
7398 22:51:11.522407 # ok 477 get_value.0.25
7399 22:51:11.522926 # ok 478 name.0.25
7400 22:51:11.525871 # ok 479 write_default.0.25
7401 22:51:11.528802 # ok 480 write_valid.0.25
7402 22:51:11.532464 # ok 481 write_invalid.0.25
7403 22:51:11.535343 # ok 482 event_missing.0.25
7404 22:51:11.535779 # ok 483 event_spurious.0.25
7405 22:51:11.538805 # ok 484 get_value.0.24
7406 22:51:11.541978 # ok 485 name.0.24
7407 22:51:11.542413 # ok 486 write_default.0.24
7408 22:51:11.545527 # ok 487 write_valid.0.24
7409 22:51:11.548668 # ok 488 write_invalid.0.24
7410 22:51:11.552441 # ok 489 event_missing.0.24
7411 22:51:11.554694 # ok 490 event_spurious.0.24
7412 22:51:11.555271 # ok 491 get_value.0.23
7413 22:51:11.558567 # ok 492 name.0.23
7414 22:51:11.561424 # ok 493 write_default.0.23
7415 22:51:11.561875 # ok 494 write_valid.0.23
7416 22:51:11.565347 # ok 495 write_invalid.0.23
7417 22:51:11.568528 # ok 496 event_missing.0.23
7418 22:51:11.571770 # ok 497 event_spurious.0.23
7419 22:51:11.572301 # ok 498 get_value.0.22
7420 22:51:11.574584 # ok 499 name.0.22
7421 22:51:11.578161 # ok 500 write_default.0.22
7422 22:51:11.581149 # ok 501 write_valid.0.22
7423 22:51:11.581583 # ok 502 write_invalid.0.22
7424 22:51:11.584870 # ok 503 event_missing.0.22
7425 22:51:11.587692 # ok 504 event_spurious.0.22
7426 22:51:11.591178 # ok 505 get_value.0.21
7427 22:51:11.597684 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7428 22:51:11.598207 # not ok 506 name.0.21
7429 22:51:11.600909 # ok 507 write_default.0.21
7430 22:51:11.604109 # ok 508 write_valid.0.21
7431 22:51:11.607078 # ok 509 write_invalid.0.21
7432 22:51:11.607577 # ok 510 event_missing.0.21
7433 22:51:11.610428 # ok 511 event_spurious.0.21
7434 22:51:11.613939 # ok 512 get_value.0.20
7435 22:51:11.620915 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7436 22:51:11.623867 # not ok 513 name.0.20
7437 22:51:11.624299 # ok 514 write_default.0.20
7438 22:51:11.627453 # ok 515 write_valid.0.20
7439 22:51:11.630486 # ok 516 write_invalid.0.20
7440 22:51:11.634295 # ok 517 event_missing.0.20
7441 22:51:11.634733 # ok 518 event_spurious.0.20
7442 22:51:11.637186 # ok 519 get_value.0.19
7443 22:51:11.643466 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7444 22:51:11.646742 # not ok 520 name.0.19
7445 22:51:11.647174 # ok 521 write_default.0.19
7446 22:51:11.650326 # ok 522 write_valid.0.19
7447 22:51:11.653300 # ok 523 write_invalid.0.19
7448 22:51:11.656737 # ok 524 event_missing.0.19
7449 22:51:11.657167 # ok 525 event_spurious.0.19
7450 22:51:11.660112 # ok 526 get_value.0.18
7451 22:51:11.666903 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7452 22:51:11.670146 # not ok 527 name.0.18
7453 22:51:11.670677 # ok 528 write_default.0.18
7454 22:51:11.673174 # ok 529 write_valid.0.18
7455 22:51:11.676188 # ok 530 write_invalid.0.18
7456 22:51:11.679853 # ok 531 event_missing.0.18
7457 22:51:11.680282 # ok 532 event_spurious.0.18
7458 22:51:11.682953 # ok 533 get_value.0.17
7459 22:51:11.689755 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7460 22:51:11.690195 # not ok 534 name.0.17
7461 22:51:11.692928 # ok 535 write_default.0.17
7462 22:51:11.696081 # ok 536 write_valid.0.17
7463 22:51:11.698926 # ok 537 write_invalid.0.17
7464 22:51:11.699399 # ok 538 event_missing.0.17
7465 22:51:11.702201 # ok 539 event_spurious.0.17
7466 22:51:11.705784 # ok 540 get_value.0.16
7467 22:51:11.712701 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7468 22:51:11.713234 # not ok 541 name.0.16
7469 22:51:11.715397 # ok 542 write_default.0.16
7470 22:51:11.719322 # ok 543 write_valid.0.16
7471 22:51:11.722353 # ok 544 write_invalid.0.16
7472 22:51:11.722887 # ok 545 event_missing.0.16
7473 22:51:11.725087 # ok 546 event_spurious.0.16
7474 22:51:11.728833 # ok 547 get_value.0.15
7475 22:51:11.734957 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7476 22:51:11.735513 # not ok 548 name.0.15
7477 22:51:11.739013 # ok 549 write_default.0.15
7478 22:51:11.742239 # ok 550 write_valid.0.15
7479 22:51:11.745344 # ok 551 write_invalid.0.15
7480 22:51:11.745868 # ok 552 event_missing.0.15
7481 22:51:11.748725 # ok 553 event_spurious.0.15
7482 22:51:11.751549 # ok 554 get_value.0.14
7483 22:51:11.757954 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7484 22:51:11.761558 # not ok 555 name.0.14
7485 22:51:11.762082 # ok 556 write_default.0.14
7486 22:51:11.764812 # ok 557 write_valid.0.14
7487 22:51:11.768191 # ok 558 write_invalid.0.14
7488 22:51:11.770880 # ok 559 event_missing.0.14
7489 22:51:11.774393 # ok 560 event_spurious.0.14
7490 22:51:11.774784 # ok 561 get_value.0.13
7491 22:51:11.781152 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7492 22:51:11.784155 # not ok 562 name.0.13
7493 22:51:11.784584 # ok 563 write_default.0.13
7494 22:51:11.787929 # ok 564 write_valid.0.13
7495 22:51:11.790497 # ok 565 write_invalid.0.13
7496 22:51:11.794095 # ok 566 event_missing.0.13
7497 22:51:11.797516 # ok 567 event_spurious.0.13
7498 22:51:11.798041 # ok 568 get_value.0.12
7499 22:51:11.803641 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7500 22:51:11.806953 # not ok 569 name.0.12
7501 22:51:11.810494 # ok 570 write_default.0.12
7502 22:51:11.811018 # ok 571 write_valid.0.12
7503 22:51:11.813109 # ok 572 write_invalid.0.12
7504 22:51:11.816471 # ok 573 event_missing.0.12
7505 22:51:11.819757 # ok 574 event_spurious.0.12
7506 22:51:11.823203 # ok 575 get_value.0.11
7507 22:51:11.826566 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7508 22:51:11.829881 # not ok 576 name.0.11
7509 22:51:11.832801 # ok 577 write_default.0.11
7510 22:51:11.835898 # ok 578 write_valid.0.11
7511 22:51:11.836327 # ok 579 write_invalid.0.11
7512 22:51:11.840127 # ok 580 event_missing.0.11
7513 22:51:11.843305 # ok 581 event_spurious.0.11
7514 22:51:11.846500 # ok 582 get_value.0.10
7515 22:51:11.852597 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7516 22:51:11.853132 # not ok 583 name.0.10
7517 22:51:11.855911 # ok 584 write_default.0.10
7518 22:51:11.858853 # ok 585 write_valid.0.10
7519 22:51:11.862456 # ok 586 write_invalid.0.10
7520 22:51:11.862986 # ok 587 event_missing.0.10
7521 22:51:11.865800 # ok 588 event_spurious.0.10
7522 22:51:11.869006 # ok 589 get_value.0.9
7523 22:51:11.875575 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7524 22:51:11.876106 # not ok 590 name.0.9
7525 22:51:11.878682 # ok 591 write_default.0.9
7526 22:51:11.882239 # ok 592 write_valid.0.9
7527 22:51:11.882782 # ok 593 write_invalid.0.9
7528 22:51:11.885215 # ok 594 event_missing.0.9
7529 22:51:11.888435 # ok 595 event_spurious.0.9
7530 22:51:11.891463 # ok 596 get_value.0.8
7531 22:51:11.895262 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7532 22:51:11.898017 # not ok 597 name.0.8
7533 22:51:11.902223 # ok 598 write_default.0.8
7534 22:51:11.902745 # ok 599 write_valid.0.8
7535 22:51:11.904832 # ok 600 write_invalid.0.8
7536 22:51:11.907680 # ok 601 event_missing.0.8
7537 22:51:11.911360 # ok 602 event_spurious.0.8
7538 22:51:11.911884 # ok 603 get_value.0.7
7539 22:51:11.917453 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7540 22:51:11.921365 # not ok 604 name.0.7
7541 22:51:11.921888 # ok 605 write_default.0.7
7542 22:51:11.924135 # ok 606 write_valid.0.7
7543 22:51:11.927558 # ok 607 write_invalid.0.7
7544 22:51:11.930604 # ok 608 event_missing.0.7
7545 22:51:11.931070 # ok 609 event_spurious.0.7
7546 22:51:11.934193 # ok 610 get_value.0.6
7547 22:51:11.940374 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7548 22:51:11.943725 # not ok 611 name.0.6
7549 22:51:11.944152 # ok 612 write_default.0.6
7550 22:51:11.947608 # ok 613 write_valid.0.6
7551 22:51:11.950368 # ok 614 write_invalid.0.6
7552 22:51:11.954434 # ok 615 event_missing.0.6
7553 22:51:11.954960 # ok 616 event_spurious.0.6
7554 22:51:11.956655 # ok 617 get_value.0.5
7555 22:51:11.959935 # ok 618 name.0.5
7556 22:51:11.960362 # ok 619 write_default.0.5
7557 22:51:11.963534 # # No event generated for MTKAIF_DMIC
7558 22:51:11.967395 # # No event generated for MTKAIF_DMIC
7559 22:51:11.970388 # ok 620 write_valid.0.5
7560 22:51:11.973278 # ok 621 write_invalid.0.5
7561 22:51:11.976764 # not ok 622 event_missing.0.5
7562 22:51:11.979591 # ok 623 event_spurious.0.5
7563 22:51:11.980023 # ok 624 get_value.0.4
7564 22:51:11.983178 # ok 625 name.0.4
7565 22:51:11.986598 # ok 626 write_default.0.4
7566 22:51:11.989338 # # No event generated for I2S5_HD_Mux
7567 22:51:11.993160 # # No event generated for I2S5_HD_Mux
7568 22:51:11.993594 # ok 627 write_valid.0.4
7569 22:51:11.995804 # ok 628 write_invalid.0.4
7570 22:51:11.999013 # not ok 629 event_missing.0.4
7571 22:51:12.001804 # ok 630 event_spurious.0.4
7572 22:51:12.001891 # ok 631 get_value.0.3
7573 22:51:12.005585 # ok 632 name.0.3
7574 22:51:12.008359 # ok 633 write_default.0.3
7575 22:51:12.012111 # # No event generated for I2S3_HD_Mux
7576 22:51:12.014916 # # No event generated for I2S3_HD_Mux
7577 22:51:12.018441 # ok 634 write_valid.0.3
7578 22:51:12.018527 # ok 635 write_invalid.0.3
7579 22:51:12.022005 # not ok 636 event_missing.0.3
7580 22:51:12.025021 # ok 637 event_spurious.0.3
7581 22:51:12.028179 # ok 638 get_value.0.2
7582 22:51:12.028293 # ok 639 name.0.2
7583 22:51:12.031783 # ok 640 write_default.0.2
7584 22:51:12.035342 # # No event generated for I2S2_HD_Mux
7585 22:51:12.038326 # # No event generated for I2S2_HD_Mux
7586 22:51:12.041427 # ok 641 write_valid.0.2
7587 22:51:12.044236 # ok 642 write_invalid.0.2
7588 22:51:12.044321 # not ok 643 event_missing.0.2
7589 22:51:12.047654 # ok 644 event_spurious.0.2
7590 22:51:12.050931 # ok 645 get_value.0.1
7591 22:51:12.051015 # ok 646 name.0.1
7592 22:51:12.054480 # ok 647 write_default.0.1
7593 22:51:12.057547 # # No event generated for I2S1_HD_Mux
7594 22:51:12.060901 # # No event generated for I2S1_HD_Mux
7595 22:51:12.064180 # ok 648 write_valid.0.1
7596 22:51:12.067445 # ok 649 write_invalid.0.1
7597 22:51:12.067608 # not ok 650 event_missing.0.1
7598 22:51:12.071174 # ok 651 event_spurious.0.1
7599 22:51:12.074548 # ok 652 get_value.0.0
7600 22:51:12.074708 # ok 653 name.0.0
7601 22:51:12.077432 # ok 654 write_default.0.0
7602 22:51:12.081006 # # No event generated for I2S0_HD_Mux
7603 22:51:12.083796 # # No event generated for I2S0_HD_Mux
7604 22:51:12.087392 # ok 655 write_valid.0.0
7605 22:51:12.090458 # ok 656 write_invalid.0.0
7606 22:51:12.090679 # not ok 657 event_missing.0.0
7607 22:51:12.093889 # ok 658 event_spurious.0.0
7608 22:51:12.100097 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7609 22:51:12.103682 ok 1 selftests: alsa: mixer-test
7610 22:51:13.705636 alsa_mixer-test_get_value_0_93 pass
7611 22:51:13.708566 alsa_mixer-test_name_0_93 pass
7612 22:51:13.711707 alsa_mixer-test_write_default_0_93 pass
7613 22:51:13.715030 alsa_mixer-test_write_valid_0_93 pass
7614 22:51:13.721451 alsa_mixer-test_write_invalid_0_93 pass
7615 22:51:13.724941 alsa_mixer-test_event_missing_0_93 pass
7616 22:51:13.727719 alsa_mixer-test_event_spurious_0_93 pass
7617 22:51:13.731572 alsa_mixer-test_get_value_0_92 pass
7618 22:51:13.734634 alsa_mixer-test_name_0_92 pass
7619 22:51:13.737867 alsa_mixer-test_write_default_0_92 pass
7620 22:51:13.741699 alsa_mixer-test_write_valid_0_92 pass
7621 22:51:13.744480 alsa_mixer-test_write_invalid_0_92 pass
7622 22:51:13.747803 alsa_mixer-test_event_missing_0_92 pass
7623 22:51:13.751211 alsa_mixer-test_event_spurious_0_92 pass
7624 22:51:13.754405 alsa_mixer-test_get_value_0_91 pass
7625 22:51:13.757645 alsa_mixer-test_name_0_91 pass
7626 22:51:13.761244 alsa_mixer-test_write_default_0_91 pass
7627 22:51:13.764030 alsa_mixer-test_write_valid_0_91 pass
7628 22:51:13.767333 alsa_mixer-test_write_invalid_0_91 pass
7629 22:51:13.771335 alsa_mixer-test_event_missing_0_91 pass
7630 22:51:13.774561 alsa_mixer-test_event_spurious_0_91 pass
7631 22:51:13.777326 alsa_mixer-test_get_value_0_90 pass
7632 22:51:13.780295 alsa_mixer-test_name_0_90 pass
7633 22:51:13.783739 alsa_mixer-test_write_default_0_90 pass
7634 22:51:13.789974 alsa_mixer-test_write_valid_0_90 pass
7635 22:51:13.793037 alsa_mixer-test_write_invalid_0_90 pass
7636 22:51:13.796556 alsa_mixer-test_event_missing_0_90 pass
7637 22:51:13.800971 alsa_mixer-test_event_spurious_0_90 pass
7638 22:51:13.803263 alsa_mixer-test_get_value_0_89 pass
7639 22:51:13.806625 alsa_mixer-test_name_0_89 pass
7640 22:51:13.810116 alsa_mixer-test_write_default_0_89 pass
7641 22:51:13.812995 alsa_mixer-test_write_valid_0_89 pass
7642 22:51:13.816722 alsa_mixer-test_write_invalid_0_89 pass
7643 22:51:13.819664 alsa_mixer-test_event_missing_0_89 pass
7644 22:51:13.826314 alsa_mixer-test_event_spurious_0_89 pass
7645 22:51:13.829472 alsa_mixer-test_get_value_0_88 pass
7646 22:51:13.829896 alsa_mixer-test_name_0_88 pass
7647 22:51:13.836080 alsa_mixer-test_write_default_0_88 pass
7648 22:51:13.839724 alsa_mixer-test_write_valid_0_88 fail
7649 22:51:13.842809 alsa_mixer-test_write_invalid_0_88 pass
7650 22:51:13.845769 alsa_mixer-test_event_missing_0_88 pass
7651 22:51:13.848955 alsa_mixer-test_event_spurious_0_88 fail
7652 22:51:13.851798 alsa_mixer-test_get_value_0_87 pass
7653 22:51:13.855386 alsa_mixer-test_name_0_87 pass
7654 22:51:13.858703 alsa_mixer-test_write_default_0_87 pass
7655 22:51:13.862282 alsa_mixer-test_write_valid_0_87 pass
7656 22:51:13.864901 alsa_mixer-test_write_invalid_0_87 pass
7657 22:51:13.868928 alsa_mixer-test_event_missing_0_87 pass
7658 22:51:13.874833 alsa_mixer-test_event_spurious_0_87 pass
7659 22:51:13.877703 alsa_mixer-test_get_value_0_86 pass
7660 22:51:13.881396 alsa_mixer-test_name_0_86 pass
7661 22:51:13.884699 alsa_mixer-test_write_default_0_86 pass
7662 22:51:13.888112 alsa_mixer-test_write_valid_0_86 fail
7663 22:51:13.891010 alsa_mixer-test_write_invalid_0_86 pass
7664 22:51:13.894136 alsa_mixer-test_event_missing_0_86 pass
7665 22:51:13.897400 alsa_mixer-test_event_spurious_0_86 pass
7666 22:51:13.900859 alsa_mixer-test_get_value_0_85 pass
7667 22:51:13.903995 alsa_mixer-test_name_0_85 pass
7668 22:51:13.906986 alsa_mixer-test_write_default_0_85 pass
7669 22:51:13.910561 alsa_mixer-test_write_valid_0_85 fail
7670 22:51:13.917174 alsa_mixer-test_write_invalid_0_85 pass
7671 22:51:13.920406 alsa_mixer-test_event_missing_0_85 pass
7672 22:51:13.923206 alsa_mixer-test_event_spurious_0_85 pass
7673 22:51:13.926564 alsa_mixer-test_get_value_0_84 pass
7674 22:51:13.929790 alsa_mixer-test_name_0_84 pass
7675 22:51:13.933169 alsa_mixer-test_write_default_0_84 pass
7676 22:51:13.936478 alsa_mixer-test_write_valid_0_84 pass
7677 22:51:13.939852 alsa_mixer-test_write_invalid_0_84 pass
7678 22:51:13.943367 alsa_mixer-test_event_missing_0_84 pass
7679 22:51:13.946200 alsa_mixer-test_event_spurious_0_84 pass
7680 22:51:13.949468 alsa_mixer-test_get_value_0_83 pass
7681 22:51:13.952467 alsa_mixer-test_name_0_83 pass
7682 22:51:13.956089 alsa_mixer-test_write_default_0_83 pass
7683 22:51:13.959055 alsa_mixer-test_write_valid_0_83 pass
7684 22:51:13.965844 alsa_mixer-test_write_invalid_0_83 pass
7685 22:51:13.969075 alsa_mixer-test_event_missing_0_83 pass
7686 22:51:13.972552 alsa_mixer-test_event_spurious_0_83 pass
7687 22:51:13.975612 alsa_mixer-test_get_value_0_82 pass
7688 22:51:13.979051 alsa_mixer-test_name_0_82 pass
7689 22:51:13.982274 alsa_mixer-test_write_default_0_82 skip
7690 22:51:13.985147 alsa_mixer-test_write_valid_0_82 skip
7691 22:51:13.988529 alsa_mixer-test_write_invalid_0_82 skip
7692 22:51:13.991585 alsa_mixer-test_event_missing_0_82 pass
7693 22:51:13.995083 alsa_mixer-test_event_spurious_0_82 pass
7694 22:51:13.999101 alsa_mixer-test_get_value_0_81 pass
7695 22:51:14.001869 alsa_mixer-test_name_0_81 pass
7696 22:51:14.005146 alsa_mixer-test_write_default_0_81 pass
7697 22:51:14.011735 alsa_mixer-test_write_valid_0_81 pass
7698 22:51:14.015059 alsa_mixer-test_write_invalid_0_81 fail
7699 22:51:14.017872 alsa_mixer-test_event_missing_0_81 fail
7700 22:51:14.021661 alsa_mixer-test_event_spurious_0_81 pass
7701 22:51:14.024347 alsa_mixer-test_get_value_0_80 pass
7702 22:51:14.027785 alsa_mixer-test_name_0_80 pass
7703 22:51:14.030984 alsa_mixer-test_write_default_0_80 pass
7704 22:51:14.034248 alsa_mixer-test_write_valid_0_80 pass
7705 22:51:14.037278 alsa_mixer-test_write_invalid_0_80 pass
7706 22:51:14.040456 alsa_mixer-test_event_missing_0_80 pass
7707 22:51:14.044412 alsa_mixer-test_event_spurious_0_80 pass
7708 22:51:14.047920 alsa_mixer-test_get_value_0_79 fail
7709 22:51:14.050542 alsa_mixer-test_name_0_79 pass
7710 22:51:14.053718 alsa_mixer-test_write_default_0_79 fail
7711 22:51:14.060571 alsa_mixer-test_write_valid_0_79 fail
7712 22:51:14.064053 alsa_mixer-test_write_invalid_0_79 fail
7713 22:51:14.066735 alsa_mixer-test_event_missing_0_79 pass
7714 22:51:14.070605 alsa_mixer-test_event_spurious_0_79 pass
7715 22:51:14.073879 alsa_mixer-test_get_value_0_78 fail
7716 22:51:14.076756 alsa_mixer-test_name_0_78 pass
7717 22:51:14.079971 alsa_mixer-test_write_default_0_78 fail
7718 22:51:14.083529 alsa_mixer-test_write_valid_0_78 fail
7719 22:51:14.086220 alsa_mixer-test_write_invalid_0_78 fail
7720 22:51:14.089504 alsa_mixer-test_event_missing_0_78 pass
7721 22:51:14.096430 alsa_mixer-test_event_spurious_0_78 pass
7722 22:51:14.099453 alsa_mixer-test_get_value_0_77 fail
7723 22:51:14.099878 alsa_mixer-test_name_0_77 pass
7724 22:51:14.105841 alsa_mixer-test_write_default_0_77 fail
7725 22:51:14.109699 alsa_mixer-test_write_valid_0_77 fail
7726 22:51:14.113000 alsa_mixer-test_write_invalid_0_77 fail
7727 22:51:14.115494 alsa_mixer-test_event_missing_0_77 pass
7728 22:51:14.119988 alsa_mixer-test_event_spurious_0_77 pass
7729 22:51:14.122300 alsa_mixer-test_get_value_0_76 pass
7730 22:51:14.125941 alsa_mixer-test_name_0_76 fail
7731 22:51:14.128815 alsa_mixer-test_write_default_0_76 pass
7732 22:51:14.131896 alsa_mixer-test_write_valid_0_76 pass
7733 22:51:14.135720 alsa_mixer-test_write_invalid_0_76 pass
7734 22:51:14.138702 alsa_mixer-test_event_missing_0_76 pass
7735 22:51:14.142621 alsa_mixer-test_event_spurious_0_76 pass
7736 22:51:14.145109 alsa_mixer-test_get_value_0_75 pass
7737 22:51:14.148345 alsa_mixer-test_name_0_75 fail
7738 22:51:14.154704 alsa_mixer-test_write_default_0_75 pass
7739 22:51:14.157913 alsa_mixer-test_write_valid_0_75 pass
7740 22:51:14.161251 alsa_mixer-test_write_invalid_0_75 pass
7741 22:51:14.165032 alsa_mixer-test_event_missing_0_75 pass
7742 22:51:14.168646 alsa_mixer-test_event_spurious_0_75 pass
7743 22:51:14.171156 alsa_mixer-test_get_value_0_74 pass
7744 22:51:14.174806 alsa_mixer-test_name_0_74 fail
7745 22:51:14.177730 alsa_mixer-test_write_default_0_74 pass
7746 22:51:14.180959 alsa_mixer-test_write_valid_0_74 pass
7747 22:51:14.184241 alsa_mixer-test_write_invalid_0_74 pass
7748 22:51:14.188056 alsa_mixer-test_event_missing_0_74 pass
7749 22:51:14.191088 alsa_mixer-test_event_spurious_0_74 pass
7750 22:51:14.194547 alsa_mixer-test_get_value_0_73 pass
7751 22:51:14.197817 alsa_mixer-test_name_0_73 fail
7752 22:51:14.201153 alsa_mixer-test_write_default_0_73 pass
7753 22:51:14.203890 alsa_mixer-test_write_valid_0_73 pass
7754 22:51:14.210558 alsa_mixer-test_write_invalid_0_73 pass
7755 22:51:14.214182 alsa_mixer-test_event_missing_0_73 pass
7756 22:51:14.217331 alsa_mixer-test_event_spurious_0_73 pass
7757 22:51:14.220245 alsa_mixer-test_get_value_0_72 pass
7758 22:51:14.223306 alsa_mixer-test_name_0_72 fail
7759 22:51:14.226684 alsa_mixer-test_write_default_0_72 pass
7760 22:51:14.230256 alsa_mixer-test_write_valid_0_72 pass
7761 22:51:14.233316 alsa_mixer-test_write_invalid_0_72 pass
7762 22:51:14.236628 alsa_mixer-test_event_missing_0_72 pass
7763 22:51:14.239822 alsa_mixer-test_event_spurious_0_72 pass
7764 22:51:14.242952 alsa_mixer-test_get_value_0_71 pass
7765 22:51:14.246165 alsa_mixer-test_name_0_71 fail
7766 22:51:14.249782 alsa_mixer-test_write_default_0_71 pass
7767 22:51:14.252947 alsa_mixer-test_write_valid_0_71 pass
7768 22:51:14.259288 alsa_mixer-test_write_invalid_0_71 pass
7769 22:51:14.262418 alsa_mixer-test_event_missing_0_71 pass
7770 22:51:14.266326 alsa_mixer-test_event_spurious_0_71 pass
7771 22:51:14.268813 alsa_mixer-test_get_value_0_70 pass
7772 22:51:14.272400 alsa_mixer-test_name_0_70 fail
7773 22:51:14.275388 alsa_mixer-test_write_default_0_70 pass
7774 22:51:14.279729 alsa_mixer-test_write_valid_0_70 pass
7775 22:51:14.282005 alsa_mixer-test_write_invalid_0_70 pass
7776 22:51:14.285476 alsa_mixer-test_event_missing_0_70 pass
7777 22:51:14.288820 alsa_mixer-test_event_spurious_0_70 pass
7778 22:51:14.292234 alsa_mixer-test_get_value_0_69 pass
7779 22:51:14.295001 alsa_mixer-test_name_0_69 fail
7780 22:51:14.301725 alsa_mixer-test_write_default_0_69 pass
7781 22:51:14.304551 alsa_mixer-test_write_valid_0_69 pass
7782 22:51:14.307898 alsa_mixer-test_write_invalid_0_69 pass
7783 22:51:14.311888 alsa_mixer-test_event_missing_0_69 pass
7784 22:51:14.314594 alsa_mixer-test_event_spurious_0_69 pass
7785 22:51:14.318611 alsa_mixer-test_get_value_0_68 pass
7786 22:51:14.320968 alsa_mixer-test_name_0_68 fail
7787 22:51:14.324519 alsa_mixer-test_write_default_0_68 pass
7788 22:51:14.327468 alsa_mixer-test_write_valid_0_68 pass
7789 22:51:14.331059 alsa_mixer-test_write_invalid_0_68 pass
7790 22:51:14.334166 alsa_mixer-test_event_missing_0_68 pass
7791 22:51:14.340602 alsa_mixer-test_event_spurious_0_68 pass
7792 22:51:14.343791 alsa_mixer-test_get_value_0_67 pass
7793 22:51:14.344216 alsa_mixer-test_name_0_67 fail
7794 22:51:14.350170 alsa_mixer-test_write_default_0_67 pass
7795 22:51:14.353738 alsa_mixer-test_write_valid_0_67 pass
7796 22:51:14.356955 alsa_mixer-test_write_invalid_0_67 pass
7797 22:51:14.360158 alsa_mixer-test_event_missing_0_67 pass
7798 22:51:14.363323 alsa_mixer-test_event_spurious_0_67 pass
7799 22:51:14.366778 alsa_mixer-test_get_value_0_66 pass
7800 22:51:14.370783 alsa_mixer-test_name_0_66 fail
7801 22:51:14.372920 alsa_mixer-test_write_default_0_66 pass
7802 22:51:14.376458 alsa_mixer-test_write_valid_0_66 pass
7803 22:51:14.379556 alsa_mixer-test_write_invalid_0_66 pass
7804 22:51:14.386764 alsa_mixer-test_event_missing_0_66 pass
7805 22:51:14.390145 alsa_mixer-test_event_spurious_0_66 pass
7806 22:51:14.392856 alsa_mixer-test_get_value_0_65 pass
7807 22:51:14.396300 alsa_mixer-test_name_0_65 fail
7808 22:51:14.398968 alsa_mixer-test_write_default_0_65 pass
7809 22:51:14.402111 alsa_mixer-test_write_valid_0_65 pass
7810 22:51:14.405229 alsa_mixer-test_write_invalid_0_65 pass
7811 22:51:14.408894 alsa_mixer-test_event_missing_0_65 pass
7812 22:51:14.412106 alsa_mixer-test_event_spurious_0_65 pass
7813 22:51:14.415874 alsa_mixer-test_get_value_0_64 pass
7814 22:51:14.418884 alsa_mixer-test_name_0_64 fail
7815 22:51:14.422714 alsa_mixer-test_write_default_0_64 pass
7816 22:51:14.425315 alsa_mixer-test_write_valid_0_64 pass
7817 22:51:14.428399 alsa_mixer-test_write_invalid_0_64 pass
7818 22:51:14.435492 alsa_mixer-test_event_missing_0_64 pass
7819 22:51:14.438275 alsa_mixer-test_event_spurious_0_64 pass
7820 22:51:14.442403 alsa_mixer-test_get_value_0_63 pass
7821 22:51:14.444919 alsa_mixer-test_name_0_63 fail
7822 22:51:14.448396 alsa_mixer-test_write_default_0_63 pass
7823 22:51:14.451269 alsa_mixer-test_write_valid_0_63 pass
7824 22:51:14.455260 alsa_mixer-test_write_invalid_0_63 pass
7825 22:51:14.457536 alsa_mixer-test_event_missing_0_63 pass
7826 22:51:14.461103 alsa_mixer-test_event_spurious_0_63 pass
7827 22:51:14.464335 alsa_mixer-test_get_value_0_62 pass
7828 22:51:14.467399 alsa_mixer-test_name_0_62 fail
7829 22:51:14.471109 alsa_mixer-test_write_default_0_62 pass
7830 22:51:14.474136 alsa_mixer-test_write_valid_0_62 pass
7831 22:51:14.477456 alsa_mixer-test_write_invalid_0_62 pass
7832 22:51:14.483919 alsa_mixer-test_event_missing_0_62 pass
7833 22:51:14.487496 alsa_mixer-test_event_spurious_0_62 pass
7834 22:51:14.490518 alsa_mixer-test_get_value_0_61 pass
7835 22:51:14.493709 alsa_mixer-test_name_0_61 fail
7836 22:51:14.497578 alsa_mixer-test_write_default_0_61 pass
7837 22:51:14.500510 alsa_mixer-test_write_valid_0_61 pass
7838 22:51:14.503796 alsa_mixer-test_write_invalid_0_61 pass
7839 22:51:14.507153 alsa_mixer-test_event_missing_0_61 pass
7840 22:51:14.510658 alsa_mixer-test_event_spurious_0_61 pass
7841 22:51:14.513938 alsa_mixer-test_get_value_0_60 pass
7842 22:51:14.516964 alsa_mixer-test_name_0_60 fail
7843 22:51:14.520538 alsa_mixer-test_write_default_0_60 pass
7844 22:51:14.523779 alsa_mixer-test_write_valid_0_60 pass
7845 22:51:14.526907 alsa_mixer-test_write_invalid_0_60 pass
7846 22:51:14.529630 alsa_mixer-test_event_missing_0_60 pass
7847 22:51:14.536340 alsa_mixer-test_event_spurious_0_60 pass
7848 22:51:14.539737 alsa_mixer-test_get_value_0_59 pass
7849 22:51:14.543132 alsa_mixer-test_name_0_59 fail
7850 22:51:14.546747 alsa_mixer-test_write_default_0_59 pass
7851 22:51:14.549960 alsa_mixer-test_write_valid_0_59 pass
7852 22:51:14.552649 alsa_mixer-test_write_invalid_0_59 pass
7853 22:51:14.556292 alsa_mixer-test_event_missing_0_59 pass
7854 22:51:14.559830 alsa_mixer-test_event_spurious_0_59 pass
7855 22:51:14.562462 alsa_mixer-test_get_value_0_58 pass
7856 22:51:14.565875 alsa_mixer-test_name_0_58 fail
7857 22:51:14.568961 alsa_mixer-test_write_default_0_58 pass
7858 22:51:14.572511 alsa_mixer-test_write_valid_0_58 pass
7859 22:51:14.575860 alsa_mixer-test_write_invalid_0_58 pass
7860 22:51:14.578703 alsa_mixer-test_event_missing_0_58 pass
7861 22:51:14.585579 alsa_mixer-test_event_spurious_0_58 pass
7862 22:51:14.588711 alsa_mixer-test_get_value_0_57 pass
7863 22:51:14.591981 alsa_mixer-test_name_0_57 fail
7864 22:51:14.595312 alsa_mixer-test_write_default_0_57 pass
7865 22:51:14.598125 alsa_mixer-test_write_valid_0_57 pass
7866 22:51:14.601533 alsa_mixer-test_write_invalid_0_57 pass
7867 22:51:14.605475 alsa_mixer-test_event_missing_0_57 pass
7868 22:51:14.608898 alsa_mixer-test_event_spurious_0_57 pass
7869 22:51:14.611271 alsa_mixer-test_get_value_0_56 pass
7870 22:51:14.615840 alsa_mixer-test_name_0_56 fail
7871 22:51:14.617666 alsa_mixer-test_write_default_0_56 pass
7872 22:51:14.621418 alsa_mixer-test_write_valid_0_56 pass
7873 22:51:14.624606 alsa_mixer-test_write_invalid_0_56 pass
7874 22:51:14.627629 alsa_mixer-test_event_missing_0_56 pass
7875 22:51:14.634306 alsa_mixer-test_event_spurious_0_56 pass
7876 22:51:14.637243 alsa_mixer-test_get_value_0_55 pass
7877 22:51:14.640866 alsa_mixer-test_name_0_55 fail
7878 22:51:14.643811 alsa_mixer-test_write_default_0_55 pass
7879 22:51:14.647206 alsa_mixer-test_write_valid_0_55 pass
7880 22:51:14.650506 alsa_mixer-test_write_invalid_0_55 pass
7881 22:51:14.653751 alsa_mixer-test_event_missing_0_55 pass
7882 22:51:14.656718 alsa_mixer-test_event_spurious_0_55 pass
7883 22:51:14.660240 alsa_mixer-test_get_value_0_54 pass
7884 22:51:14.663299 alsa_mixer-test_name_0_54 fail
7885 22:51:14.666980 alsa_mixer-test_write_default_0_54 pass
7886 22:51:14.670293 alsa_mixer-test_write_valid_0_54 pass
7887 22:51:14.673040 alsa_mixer-test_write_invalid_0_54 pass
7888 22:51:14.676717 alsa_mixer-test_event_missing_0_54 pass
7889 22:51:14.683178 alsa_mixer-test_event_spurious_0_54 pass
7890 22:51:14.686536 alsa_mixer-test_get_value_0_53 pass
7891 22:51:14.689537 alsa_mixer-test_name_0_53 fail
7892 22:51:14.693272 alsa_mixer-test_write_default_0_53 pass
7893 22:51:14.696396 alsa_mixer-test_write_valid_0_53 pass
7894 22:51:14.699536 alsa_mixer-test_write_invalid_0_53 pass
7895 22:51:14.703376 alsa_mixer-test_event_missing_0_53 pass
7896 22:51:14.706131 alsa_mixer-test_event_spurious_0_53 pass
7897 22:51:14.709380 alsa_mixer-test_get_value_0_52 pass
7898 22:51:14.713008 alsa_mixer-test_name_0_52 fail
7899 22:51:14.716197 alsa_mixer-test_write_default_0_52 pass
7900 22:51:14.719684 alsa_mixer-test_write_valid_0_52 pass
7901 22:51:14.722324 alsa_mixer-test_write_invalid_0_52 pass
7902 22:51:14.728695 alsa_mixer-test_event_missing_0_52 pass
7903 22:51:14.732139 alsa_mixer-test_event_spurious_0_52 pass
7904 22:51:14.735042 alsa_mixer-test_get_value_0_51 pass
7905 22:51:14.738069 alsa_mixer-test_name_0_51 fail
7906 22:51:14.741339 alsa_mixer-test_write_default_0_51 pass
7907 22:51:14.745821 alsa_mixer-test_write_valid_0_51 pass
7908 22:51:14.748394 alsa_mixer-test_write_invalid_0_51 pass
7909 22:51:14.751183 alsa_mixer-test_event_missing_0_51 pass
7910 22:51:14.754417 alsa_mixer-test_event_spurious_0_51 pass
7911 22:51:14.757703 alsa_mixer-test_get_value_0_50 pass
7912 22:51:14.760995 alsa_mixer-test_name_0_50 fail
7913 22:51:14.764749 alsa_mixer-test_write_default_0_50 pass
7914 22:51:14.767510 alsa_mixer-test_write_valid_0_50 pass
7915 22:51:14.771129 alsa_mixer-test_write_invalid_0_50 pass
7916 22:51:14.777685 alsa_mixer-test_event_missing_0_50 pass
7917 22:51:14.780792 alsa_mixer-test_event_spurious_0_50 pass
7918 22:51:14.784051 alsa_mixer-test_get_value_0_49 pass
7919 22:51:14.787740 alsa_mixer-test_name_0_49 fail
7920 22:51:14.790629 alsa_mixer-test_write_default_0_49 pass
7921 22:51:14.793385 alsa_mixer-test_write_valid_0_49 pass
7922 22:51:14.797178 alsa_mixer-test_write_invalid_0_49 pass
7923 22:51:14.799866 alsa_mixer-test_event_missing_0_49 pass
7924 22:51:14.803533 alsa_mixer-test_event_spurious_0_49 pass
7925 22:51:14.806710 alsa_mixer-test_get_value_0_48 pass
7926 22:51:14.810378 alsa_mixer-test_name_0_48 fail
7927 22:51:14.813372 alsa_mixer-test_write_default_0_48 pass
7928 22:51:14.816500 alsa_mixer-test_write_valid_0_48 pass
7929 22:51:14.820185 alsa_mixer-test_write_invalid_0_48 pass
7930 22:51:14.826742 alsa_mixer-test_event_missing_0_48 pass
7931 22:51:14.829181 alsa_mixer-test_event_spurious_0_48 pass
7932 22:51:14.832652 alsa_mixer-test_get_value_0_47 pass
7933 22:51:14.836039 alsa_mixer-test_name_0_47 fail
7934 22:51:14.839334 alsa_mixer-test_write_default_0_47 pass
7935 22:51:14.842341 alsa_mixer-test_write_valid_0_47 pass
7936 22:51:14.845675 alsa_mixer-test_write_invalid_0_47 pass
7937 22:51:14.848957 alsa_mixer-test_event_missing_0_47 pass
7938 22:51:14.852043 alsa_mixer-test_event_spurious_0_47 pass
7939 22:51:14.855451 alsa_mixer-test_get_value_0_46 pass
7940 22:51:14.858509 alsa_mixer-test_name_0_46 fail
7941 22:51:14.862681 alsa_mixer-test_write_default_0_46 pass
7942 22:51:14.865623 alsa_mixer-test_write_valid_0_46 pass
7943 22:51:14.871992 alsa_mixer-test_write_invalid_0_46 pass
7944 22:51:14.874615 alsa_mixer-test_event_missing_0_46 pass
7945 22:51:14.878095 alsa_mixer-test_event_spurious_0_46 pass
7946 22:51:14.881672 alsa_mixer-test_get_value_0_45 pass
7947 22:51:14.884371 alsa_mixer-test_name_0_45 fail
7948 22:51:14.887989 alsa_mixer-test_write_default_0_45 pass
7949 22:51:14.891305 alsa_mixer-test_write_valid_0_45 pass
7950 22:51:14.894830 alsa_mixer-test_write_invalid_0_45 pass
7951 22:51:14.897952 alsa_mixer-test_event_missing_0_45 pass
7952 22:51:14.901739 alsa_mixer-test_event_spurious_0_45 pass
7953 22:51:14.904500 alsa_mixer-test_get_value_0_44 pass
7954 22:51:14.907121 alsa_mixer-test_name_0_44 fail
7955 22:51:14.910919 alsa_mixer-test_write_default_0_44 pass
7956 22:51:14.917514 alsa_mixer-test_write_valid_0_44 pass
7957 22:51:14.921098 alsa_mixer-test_write_invalid_0_44 pass
7958 22:51:14.923834 alsa_mixer-test_event_missing_0_44 pass
7959 22:51:14.927356 alsa_mixer-test_event_spurious_0_44 pass
7960 22:51:14.930384 alsa_mixer-test_get_value_0_43 pass
7961 22:51:14.933712 alsa_mixer-test_name_0_43 fail
7962 22:51:14.936873 alsa_mixer-test_write_default_0_43 pass
7963 22:51:14.940437 alsa_mixer-test_write_valid_0_43 pass
7964 22:51:14.943488 alsa_mixer-test_write_invalid_0_43 pass
7965 22:51:14.946594 alsa_mixer-test_event_missing_0_43 pass
7966 22:51:14.950318 alsa_mixer-test_event_spurious_0_43 pass
7967 22:51:14.953515 alsa_mixer-test_get_value_0_42 pass
7968 22:51:14.956546 alsa_mixer-test_name_0_42 fail
7969 22:51:14.963020 alsa_mixer-test_write_default_0_42 pass
7970 22:51:14.966681 alsa_mixer-test_write_valid_0_42 pass
7971 22:51:14.969482 alsa_mixer-test_write_invalid_0_42 pass
7972 22:51:14.972877 alsa_mixer-test_event_missing_0_42 pass
7973 22:51:14.976422 alsa_mixer-test_event_spurious_0_42 pass
7974 22:51:14.979390 alsa_mixer-test_get_value_0_41 pass
7975 22:51:14.983374 alsa_mixer-test_name_0_41 fail
7976 22:51:14.985780 alsa_mixer-test_write_default_0_41 pass
7977 22:51:14.988951 alsa_mixer-test_write_valid_0_41 pass
7978 22:51:14.992194 alsa_mixer-test_write_invalid_0_41 pass
7979 22:51:14.995561 alsa_mixer-test_event_missing_0_41 pass
7980 22:51:15.001933 alsa_mixer-test_event_spurious_0_41 pass
7981 22:51:15.005136 alsa_mixer-test_get_value_0_40 pass
7982 22:51:15.005561 alsa_mixer-test_name_0_40 fail
7983 22:51:15.011914 alsa_mixer-test_write_default_0_40 pass
7984 22:51:15.015370 alsa_mixer-test_write_valid_0_40 pass
7985 22:51:15.018366 alsa_mixer-test_write_invalid_0_40 pass
7986 22:51:15.022022 alsa_mixer-test_event_missing_0_40 pass
7987 22:51:15.025333 alsa_mixer-test_event_spurious_0_40 pass
7988 22:51:15.028443 alsa_mixer-test_get_value_0_39 pass
7989 22:51:15.031625 alsa_mixer-test_name_0_39 fail
7990 22:51:15.035108 alsa_mixer-test_write_default_0_39 pass
7991 22:51:15.037746 alsa_mixer-test_write_valid_0_39 pass
7992 22:51:15.041380 alsa_mixer-test_write_invalid_0_39 pass
7993 22:51:15.044782 alsa_mixer-test_event_missing_0_39 pass
7994 22:51:15.051500 alsa_mixer-test_event_spurious_0_39 pass
7995 22:51:15.054680 alsa_mixer-test_get_value_0_38 pass
7996 22:51:15.055203 alsa_mixer-test_name_0_38 fail
7997 22:51:15.061240 alsa_mixer-test_write_default_0_38 pass
7998 22:51:15.063649 alsa_mixer-test_write_valid_0_38 pass
7999 22:51:15.067750 alsa_mixer-test_write_invalid_0_38 pass
8000 22:51:15.070793 alsa_mixer-test_event_missing_0_38 pass
8001 22:51:15.074040 alsa_mixer-test_event_spurious_0_38 pass
8002 22:51:15.077006 alsa_mixer-test_get_value_0_37 pass
8003 22:51:15.080924 alsa_mixer-test_name_0_37 fail
8004 22:51:15.083902 alsa_mixer-test_write_default_0_37 pass
8005 22:51:15.086987 alsa_mixer-test_write_valid_0_37 pass
8006 22:51:15.090143 alsa_mixer-test_write_invalid_0_37 pass
8007 22:51:15.093340 alsa_mixer-test_event_missing_0_37 pass
8008 22:51:15.100101 alsa_mixer-test_event_spurious_0_37 pass
8009 22:51:15.103049 alsa_mixer-test_get_value_0_36 pass
8010 22:51:15.106118 alsa_mixer-test_name_0_36 fail
8011 22:51:15.110065 alsa_mixer-test_write_default_0_36 pass
8012 22:51:15.112770 alsa_mixer-test_write_valid_0_36 pass
8013 22:51:15.116740 alsa_mixer-test_write_invalid_0_36 pass
8014 22:51:15.119564 alsa_mixer-test_event_missing_0_36 pass
8015 22:51:15.122765 alsa_mixer-test_event_spurious_0_36 pass
8016 22:51:15.126405 alsa_mixer-test_get_value_0_35 pass
8017 22:51:15.128759 alsa_mixer-test_name_0_35 fail
8018 22:51:15.132946 alsa_mixer-test_write_default_0_35 pass
8019 22:51:15.135667 alsa_mixer-test_write_valid_0_35 pass
8020 22:51:15.138897 alsa_mixer-test_write_invalid_0_35 pass
8021 22:51:15.145388 alsa_mixer-test_event_missing_0_35 pass
8022 22:51:15.149762 alsa_mixer-test_event_spurious_0_35 pass
8023 22:51:15.151850 alsa_mixer-test_get_value_0_34 pass
8024 22:51:15.154994 alsa_mixer-test_name_0_34 fail
8025 22:51:15.158426 alsa_mixer-test_write_default_0_34 pass
8026 22:51:15.161390 alsa_mixer-test_write_valid_0_34 pass
8027 22:51:15.165605 alsa_mixer-test_write_invalid_0_34 pass
8028 22:51:15.168643 alsa_mixer-test_event_missing_0_34 pass
8029 22:51:15.171456 alsa_mixer-test_event_spurious_0_34 pass
8030 22:51:15.174451 alsa_mixer-test_get_value_0_33 pass
8031 22:51:15.177964 alsa_mixer-test_name_0_33 fail
8032 22:51:15.181348 alsa_mixer-test_write_default_0_33 pass
8033 22:51:15.184170 alsa_mixer-test_write_valid_0_33 pass
8034 22:51:15.190902 alsa_mixer-test_write_invalid_0_33 pass
8035 22:51:15.193957 alsa_mixer-test_event_missing_0_33 pass
8036 22:51:15.197978 alsa_mixer-test_event_spurious_0_33 pass
8037 22:51:15.200792 alsa_mixer-test_get_value_0_32 pass
8038 22:51:15.203715 alsa_mixer-test_name_0_32 fail
8039 22:51:15.207248 alsa_mixer-test_write_default_0_32 pass
8040 22:51:15.210477 alsa_mixer-test_write_valid_0_32 pass
8041 22:51:15.213966 alsa_mixer-test_write_invalid_0_32 pass
8042 22:51:15.217048 alsa_mixer-test_event_missing_0_32 pass
8043 22:51:15.220665 alsa_mixer-test_event_spurious_0_32 pass
8044 22:51:15.223122 alsa_mixer-test_get_value_0_31 pass
8045 22:51:15.226783 alsa_mixer-test_name_0_31 fail
8046 22:51:15.229976 alsa_mixer-test_write_default_0_31 pass
8047 22:51:15.233365 alsa_mixer-test_write_valid_0_31 pass
8048 22:51:15.237409 alsa_mixer-test_write_invalid_0_31 pass
8049 22:51:15.240006 alsa_mixer-test_event_missing_0_31 pass
8050 22:51:15.246695 alsa_mixer-test_event_spurious_0_31 pass
8051 22:51:15.249929 alsa_mixer-test_get_value_0_30 pass
8052 22:51:15.250354 alsa_mixer-test_name_0_30 fail
8053 22:51:15.256418 alsa_mixer-test_write_default_0_30 pass
8054 22:51:15.259663 alsa_mixer-test_write_valid_0_30 pass
8055 22:51:15.262263 alsa_mixer-test_write_invalid_0_30 pass
8056 22:51:15.266101 alsa_mixer-test_event_missing_0_30 pass
8057 22:51:15.269538 alsa_mixer-test_event_spurious_0_30 pass
8058 22:51:15.272196 alsa_mixer-test_get_value_0_29 pass
8059 22:51:15.275622 alsa_mixer-test_name_0_29 pass
8060 22:51:15.279103 alsa_mixer-test_write_default_0_29 pass
8061 22:51:15.282052 alsa_mixer-test_write_valid_0_29 pass
8062 22:51:15.285445 alsa_mixer-test_write_invalid_0_29 pass
8063 22:51:15.288754 alsa_mixer-test_event_missing_0_29 pass
8064 22:51:15.295273 alsa_mixer-test_event_spurious_0_29 pass
8065 22:51:15.298298 alsa_mixer-test_get_value_0_28 pass
8066 22:51:15.301989 alsa_mixer-test_name_0_28 pass
8067 22:51:15.305234 alsa_mixer-test_write_default_0_28 pass
8068 22:51:15.308152 alsa_mixer-test_write_valid_0_28 pass
8069 22:51:15.311922 alsa_mixer-test_write_invalid_0_28 pass
8070 22:51:15.314889 alsa_mixer-test_event_missing_0_28 pass
8071 22:51:15.317879 alsa_mixer-test_event_spurious_0_28 pass
8072 22:51:15.321288 alsa_mixer-test_get_value_0_27 pass
8073 22:51:15.324466 alsa_mixer-test_name_0_27 pass
8074 22:51:15.327567 alsa_mixer-test_write_default_0_27 pass
8075 22:51:15.330655 alsa_mixer-test_write_valid_0_27 pass
8076 22:51:15.334170 alsa_mixer-test_write_invalid_0_27 pass
8077 22:51:15.340439 alsa_mixer-test_event_missing_0_27 pass
8078 22:51:15.343907 alsa_mixer-test_event_spurious_0_27 pass
8079 22:51:15.347125 alsa_mixer-test_get_value_0_26 pass
8080 22:51:15.350579 alsa_mixer-test_name_0_26 pass
8081 22:51:15.353585 alsa_mixer-test_write_default_0_26 pass
8082 22:51:15.357352 alsa_mixer-test_write_valid_0_26 pass
8083 22:51:15.360260 alsa_mixer-test_write_invalid_0_26 pass
8084 22:51:15.363671 alsa_mixer-test_event_missing_0_26 pass
8085 22:51:15.366975 alsa_mixer-test_event_spurious_0_26 pass
8086 22:51:15.370225 alsa_mixer-test_get_value_0_25 pass
8087 22:51:15.373498 alsa_mixer-test_name_0_25 pass
8088 22:51:15.376661 alsa_mixer-test_write_default_0_25 pass
8089 22:51:15.379995 alsa_mixer-test_write_valid_0_25 pass
8090 22:51:15.386612 alsa_mixer-test_write_invalid_0_25 pass
8091 22:51:15.389333 alsa_mixer-test_event_missing_0_25 pass
8092 22:51:15.392753 alsa_mixer-test_event_spurious_0_25 pass
8093 22:51:15.396199 alsa_mixer-test_get_value_0_24 pass
8094 22:51:15.399601 alsa_mixer-test_name_0_24 pass
8095 22:51:15.402819 alsa_mixer-test_write_default_0_24 pass
8096 22:51:15.406170 alsa_mixer-test_write_valid_0_24 pass
8097 22:51:15.409763 alsa_mixer-test_write_invalid_0_24 pass
8098 22:51:15.412405 alsa_mixer-test_event_missing_0_24 pass
8099 22:51:15.415862 alsa_mixer-test_event_spurious_0_24 pass
8100 22:51:15.419283 alsa_mixer-test_get_value_0_23 pass
8101 22:51:15.422134 alsa_mixer-test_name_0_23 pass
8102 22:51:15.425950 alsa_mixer-test_write_default_0_23 pass
8103 22:51:15.428671 alsa_mixer-test_write_valid_0_23 pass
8104 22:51:15.435446 alsa_mixer-test_write_invalid_0_23 pass
8105 22:51:15.438277 alsa_mixer-test_event_missing_0_23 pass
8106 22:51:15.441670 alsa_mixer-test_event_spurious_0_23 pass
8107 22:51:15.445258 alsa_mixer-test_get_value_0_22 pass
8108 22:51:15.448343 alsa_mixer-test_name_0_22 pass
8109 22:51:15.451357 alsa_mixer-test_write_default_0_22 pass
8110 22:51:15.454783 alsa_mixer-test_write_valid_0_22 pass
8111 22:51:15.457962 alsa_mixer-test_write_invalid_0_22 pass
8112 22:51:15.461163 alsa_mixer-test_event_missing_0_22 pass
8113 22:51:15.464576 alsa_mixer-test_event_spurious_0_22 pass
8114 22:51:15.468222 alsa_mixer-test_get_value_0_21 pass
8115 22:51:15.470777 alsa_mixer-test_name_0_21 fail
8116 22:51:15.474511 alsa_mixer-test_write_default_0_21 pass
8117 22:51:15.480509 alsa_mixer-test_write_valid_0_21 pass
8118 22:51:15.483817 alsa_mixer-test_write_invalid_0_21 pass
8119 22:51:15.487195 alsa_mixer-test_event_missing_0_21 pass
8120 22:51:15.490577 alsa_mixer-test_event_spurious_0_21 pass
8121 22:51:15.493610 alsa_mixer-test_get_value_0_20 pass
8122 22:51:15.497325 alsa_mixer-test_name_0_20 fail
8123 22:51:15.500648 alsa_mixer-test_write_default_0_20 pass
8124 22:51:15.503359 alsa_mixer-test_write_valid_0_20 pass
8125 22:51:15.507010 alsa_mixer-test_write_invalid_0_20 pass
8126 22:51:15.510271 alsa_mixer-test_event_missing_0_20 pass
8127 22:51:15.513522 alsa_mixer-test_event_spurious_0_20 pass
8128 22:51:15.517038 alsa_mixer-test_get_value_0_19 pass
8129 22:51:15.520503 alsa_mixer-test_name_0_19 fail
8130 22:51:15.523359 alsa_mixer-test_write_default_0_19 pass
8131 22:51:15.530416 alsa_mixer-test_write_valid_0_19 pass
8132 22:51:15.532806 alsa_mixer-test_write_invalid_0_19 pass
8133 22:51:15.536625 alsa_mixer-test_event_missing_0_19 pass
8134 22:51:15.539604 alsa_mixer-test_event_spurious_0_19 pass
8135 22:51:15.542613 alsa_mixer-test_get_value_0_18 pass
8136 22:51:15.545796 alsa_mixer-test_name_0_18 fail
8137 22:51:15.549027 alsa_mixer-test_write_default_0_18 pass
8138 22:51:15.553020 alsa_mixer-test_write_valid_0_18 pass
8139 22:51:15.555299 alsa_mixer-test_write_invalid_0_18 pass
8140 22:51:15.559611 alsa_mixer-test_event_missing_0_18 pass
8141 22:51:15.565176 alsa_mixer-test_event_spurious_0_18 pass
8142 22:51:15.569222 alsa_mixer-test_get_value_0_17 pass
8143 22:51:15.569756 alsa_mixer-test_name_0_17 fail
8144 22:51:15.575538 alsa_mixer-test_write_default_0_17 pass
8145 22:51:15.579406 alsa_mixer-test_write_valid_0_17 pass
8146 22:51:15.581958 alsa_mixer-test_write_invalid_0_17 pass
8147 22:51:15.585260 alsa_mixer-test_event_missing_0_17 pass
8148 22:51:15.588641 alsa_mixer-test_event_spurious_0_17 pass
8149 22:51:15.592005 alsa_mixer-test_get_value_0_16 pass
8150 22:51:15.594679 alsa_mixer-test_name_0_16 fail
8151 22:51:15.598419 alsa_mixer-test_write_default_0_16 pass
8152 22:51:15.601237 alsa_mixer-test_write_valid_0_16 pass
8153 22:51:15.604216 alsa_mixer-test_write_invalid_0_16 pass
8154 22:51:15.607860 alsa_mixer-test_event_missing_0_16 pass
8155 22:51:15.614571 alsa_mixer-test_event_spurious_0_16 pass
8156 22:51:15.617950 alsa_mixer-test_get_value_0_15 pass
8157 22:51:15.620631 alsa_mixer-test_name_0_15 fail
8158 22:51:15.623750 alsa_mixer-test_write_default_0_15 pass
8159 22:51:15.627698 alsa_mixer-test_write_valid_0_15 pass
8160 22:51:15.630753 alsa_mixer-test_write_invalid_0_15 pass
8161 22:51:15.633800 alsa_mixer-test_event_missing_0_15 pass
8162 22:51:15.637308 alsa_mixer-test_event_spurious_0_15 pass
8163 22:51:15.640258 alsa_mixer-test_get_value_0_14 pass
8164 22:51:15.643572 alsa_mixer-test_name_0_14 fail
8165 22:51:15.646938 alsa_mixer-test_write_default_0_14 pass
8166 22:51:15.650433 alsa_mixer-test_write_valid_0_14 pass
8167 22:51:15.653192 alsa_mixer-test_write_invalid_0_14 pass
8168 22:51:15.656676 alsa_mixer-test_event_missing_0_14 pass
8169 22:51:15.660441 alsa_mixer-test_event_spurious_0_14 pass
8170 22:51:15.663338 alsa_mixer-test_get_value_0_13 pass
8171 22:51:15.666791 alsa_mixer-test_name_0_13 fail
8172 22:51:15.670675 alsa_mixer-test_write_default_0_13 pass
8173 22:51:15.673493 alsa_mixer-test_write_valid_0_13 pass
8174 22:51:15.676495 alsa_mixer-test_write_invalid_0_13 pass
8175 22:51:15.679839 alsa_mixer-test_event_missing_0_13 pass
8176 22:51:15.686168 alsa_mixer-test_event_spurious_0_13 pass
8177 22:51:15.689536 alsa_mixer-test_get_value_0_12 pass
8178 22:51:15.690099 alsa_mixer-test_name_0_12 fail
8179 22:51:15.696086 alsa_mixer-test_write_default_0_12 pass
8180 22:51:15.699617 alsa_mixer-test_write_valid_0_12 pass
8181 22:51:15.702838 alsa_mixer-test_write_invalid_0_12 pass
8182 22:51:15.706091 alsa_mixer-test_event_missing_0_12 pass
8183 22:51:15.709491 alsa_mixer-test_event_spurious_0_12 pass
8184 22:51:15.712535 alsa_mixer-test_get_value_0_11 pass
8185 22:51:15.715858 alsa_mixer-test_name_0_11 fail
8186 22:51:15.718966 alsa_mixer-test_write_default_0_11 pass
8187 22:51:15.722523 alsa_mixer-test_write_valid_0_11 pass
8188 22:51:15.726430 alsa_mixer-test_write_invalid_0_11 pass
8189 22:51:15.729173 alsa_mixer-test_event_missing_0_11 pass
8190 22:51:15.731957 alsa_mixer-test_event_spurious_0_11 pass
8191 22:51:15.735352 alsa_mixer-test_get_value_0_10 pass
8192 22:51:15.738585 alsa_mixer-test_name_0_10 fail
8193 22:51:15.741674 alsa_mixer-test_write_default_0_10 pass
8194 22:51:15.745475 alsa_mixer-test_write_valid_0_10 pass
8195 22:51:15.748167 alsa_mixer-test_write_invalid_0_10 pass
8196 22:51:15.751849 alsa_mixer-test_event_missing_0_10 pass
8197 22:51:15.754786 alsa_mixer-test_event_spurious_0_10 pass
8198 22:51:15.758543 alsa_mixer-test_get_value_0_9 pass
8199 22:51:15.761434 alsa_mixer-test_name_0_9 fail
8200 22:51:15.764774 alsa_mixer-test_write_default_0_9 pass
8201 22:51:15.767821 alsa_mixer-test_write_valid_0_9 pass
8202 22:51:15.771860 alsa_mixer-test_write_invalid_0_9 pass
8203 22:51:15.774871 alsa_mixer-test_event_missing_0_9 pass
8204 22:51:15.777814 alsa_mixer-test_event_spurious_0_9 pass
8205 22:51:15.781145 alsa_mixer-test_get_value_0_8 pass
8206 22:51:15.784485 alsa_mixer-test_name_0_8 fail
8207 22:51:15.787722 alsa_mixer-test_write_default_0_8 pass
8208 22:51:15.790909 alsa_mixer-test_write_valid_0_8 pass
8209 22:51:15.793919 alsa_mixer-test_write_invalid_0_8 pass
8210 22:51:15.797091 alsa_mixer-test_event_missing_0_8 pass
8211 22:51:15.803738 alsa_mixer-test_event_spurious_0_8 pass
8212 22:51:15.806844 alsa_mixer-test_get_value_0_7 pass
8213 22:51:15.807342 alsa_mixer-test_name_0_7 fail
8214 22:51:15.810122 alsa_mixer-test_write_default_0_7 pass
8215 22:51:15.813799 alsa_mixer-test_write_valid_0_7 pass
8216 22:51:15.820304 alsa_mixer-test_write_invalid_0_7 pass
8217 22:51:15.824031 alsa_mixer-test_event_missing_0_7 pass
8218 22:51:15.827384 alsa_mixer-test_event_spurious_0_7 pass
8219 22:51:15.829924 alsa_mixer-test_get_value_0_6 pass
8220 22:51:15.830350 alsa_mixer-test_name_0_6 fail
8221 22:51:15.836473 alsa_mixer-test_write_default_0_6 pass
8222 22:51:15.840006 alsa_mixer-test_write_valid_0_6 pass
8223 22:51:15.843633 alsa_mixer-test_write_invalid_0_6 pass
8224 22:51:15.846330 alsa_mixer-test_event_missing_0_6 pass
8225 22:51:15.849705 alsa_mixer-test_event_spurious_0_6 pass
8226 22:51:15.852850 alsa_mixer-test_get_value_0_5 pass
8227 22:51:15.857072 alsa_mixer-test_name_0_5 pass
8228 22:51:15.859439 alsa_mixer-test_write_default_0_5 pass
8229 22:51:15.862777 alsa_mixer-test_write_valid_0_5 pass
8230 22:51:15.865936 alsa_mixer-test_write_invalid_0_5 pass
8231 22:51:15.869640 alsa_mixer-test_event_missing_0_5 fail
8232 22:51:15.872638 alsa_mixer-test_event_spurious_0_5 pass
8233 22:51:15.875811 alsa_mixer-test_get_value_0_4 pass
8234 22:51:15.879050 alsa_mixer-test_name_0_4 pass
8235 22:51:15.882228 alsa_mixer-test_write_default_0_4 pass
8236 22:51:15.885783 alsa_mixer-test_write_valid_0_4 pass
8237 22:51:15.888551 alsa_mixer-test_write_invalid_0_4 pass
8238 22:51:15.892255 alsa_mixer-test_event_missing_0_4 fail
8239 22:51:15.895183 alsa_mixer-test_event_spurious_0_4 pass
8240 22:51:15.898233 alsa_mixer-test_get_value_0_3 pass
8241 22:51:15.901715 alsa_mixer-test_name_0_3 pass
8242 22:51:15.905158 alsa_mixer-test_write_default_0_3 pass
8243 22:51:15.908508 alsa_mixer-test_write_valid_0_3 pass
8244 22:51:15.911499 alsa_mixer-test_write_invalid_0_3 pass
8245 22:51:15.915246 alsa_mixer-test_event_missing_0_3 fail
8246 22:51:15.918099 alsa_mixer-test_event_spurious_0_3 pass
8247 22:51:15.921451 alsa_mixer-test_get_value_0_2 pass
8248 22:51:15.924332 alsa_mixer-test_name_0_2 pass
8249 22:51:15.928386 alsa_mixer-test_write_default_0_2 pass
8250 22:51:15.931011 alsa_mixer-test_write_valid_0_2 pass
8251 22:51:15.934478 alsa_mixer-test_write_invalid_0_2 pass
8252 22:51:15.937970 alsa_mixer-test_event_missing_0_2 fail
8253 22:51:15.940624 alsa_mixer-test_event_spurious_0_2 pass
8254 22:51:15.944087 alsa_mixer-test_get_value_0_1 pass
8255 22:51:15.947275 alsa_mixer-test_name_0_1 pass
8256 22:51:15.950719 alsa_mixer-test_write_default_0_1 pass
8257 22:51:15.953468 alsa_mixer-test_write_valid_0_1 pass
8258 22:51:15.956576 alsa_mixer-test_write_invalid_0_1 pass
8259 22:51:15.960141 alsa_mixer-test_event_missing_0_1 fail
8260 22:51:15.963356 alsa_mixer-test_event_spurious_0_1 pass
8261 22:51:15.966955 alsa_mixer-test_get_value_0_0 pass
8262 22:51:15.970600 alsa_mixer-test_name_0_0 pass
8263 22:51:15.973686 alsa_mixer-test_write_default_0_0 pass
8264 22:51:15.976394 alsa_mixer-test_write_valid_0_0 pass
8265 22:51:15.979847 alsa_mixer-test_write_invalid_0_0 pass
8266 22:51:15.983018 alsa_mixer-test_event_missing_0_0 fail
8267 22:51:15.986571 alsa_mixer-test_event_spurious_0_0 pass
8268 22:51:15.990212 alsa_mixer-test pass
8269 22:51:15.993299 + ../../utils/send-to-lava.sh ./output/result.txt
8270 22:51:16.000079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
8271 22:51:16.000798 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
8273 22:51:16.006748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
8274 22:51:16.007436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
8276 22:51:16.012859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
8277 22:51:16.013541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
8279 22:51:16.019386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
8280 22:51:16.020101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
8282 22:51:16.064096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
8283 22:51:16.064788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
8285 22:51:16.116572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
8286 22:51:16.116966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
8288 22:51:16.164669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
8289 22:51:16.165026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
8291 22:51:16.217203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
8292 22:51:16.217507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
8294 22:51:16.274272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
8295 22:51:16.274954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
8297 22:51:16.328798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
8298 22:51:16.329570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
8300 22:51:16.386051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
8301 22:51:16.386757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
8303 22:51:16.437022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
8304 22:51:16.437717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
8306 22:51:16.488639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
8307 22:51:16.489358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8309 22:51:16.544963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8310 22:51:16.545658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8312 22:51:16.599837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8313 22:51:16.600533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8315 22:51:16.651487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8316 22:51:16.651887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8318 22:51:16.698174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8319 22:51:16.698868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8321 22:51:16.753231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8322 22:51:16.753971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8324 22:51:16.809046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8325 22:51:16.809725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8327 22:51:16.863162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8328 22:51:16.863477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8330 22:51:16.913279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8331 22:51:16.913957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8333 22:51:16.963366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8334 22:51:16.963867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8336 22:51:17.016056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8337 22:51:17.016747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8339 22:51:17.063829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8340 22:51:17.064121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8342 22:51:17.113292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8343 22:51:17.113968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8345 22:51:17.158279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8346 22:51:17.158681 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8348 22:51:17.204697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8349 22:51:17.204983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8351 22:51:17.249898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8352 22:51:17.250582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8354 22:51:17.302018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8355 22:51:17.302720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8357 22:51:17.354462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8358 22:51:17.355145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8360 22:51:17.405887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8361 22:51:17.406182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8363 22:51:17.457876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8364 22:51:17.458568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8366 22:51:17.509836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8367 22:51:17.510522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8369 22:51:17.560107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8370 22:51:17.560807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8372 22:51:17.610061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8373 22:51:17.610757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8375 22:51:17.661321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8376 22:51:17.662023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8378 22:51:17.714261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8379 22:51:17.715019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8381 22:51:17.765443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8382 22:51:17.766151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8384 22:51:17.824537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8385 22:51:17.825244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8387 22:51:17.881086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8388 22:51:17.881778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8390 22:51:17.939009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8391 22:51:17.939745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8393 22:51:17.995145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8394 22:51:17.995879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8396 22:51:18.042220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8397 22:51:18.042914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8399 22:51:18.096496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8400 22:51:18.097196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8402 22:51:18.145074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8403 22:51:18.145833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8405 22:51:18.201933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8406 22:51:18.202689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8408 22:51:18.253734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8409 22:51:18.254655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8411 22:51:18.307808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8412 22:51:18.308568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8414 22:51:18.359737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8415 22:51:18.360435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8417 22:51:18.412953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8418 22:51:18.413642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8420 22:51:18.470272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8421 22:51:18.471040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8423 22:51:18.524675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8424 22:51:18.525370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8426 22:51:18.583679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8427 22:51:18.584428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8429 22:51:18.638450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8430 22:51:18.639300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8432 22:51:18.693445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8433 22:51:18.694201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8435 22:51:18.745250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8436 22:51:18.746045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8438 22:51:18.793361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8439 22:51:18.794069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8441 22:51:18.842710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8442 22:51:18.843416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8444 22:51:18.893712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8445 22:51:18.894410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8447 22:51:18.951661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8448 22:51:18.952446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8450 22:51:19.006215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8451 22:51:19.006914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8453 22:51:19.060929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8454 22:51:19.061688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8456 22:51:19.113761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8457 22:51:19.114468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8459 22:51:19.168429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8460 22:51:19.169125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8462 22:51:19.223925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8463 22:51:19.224621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8465 22:51:19.278206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8466 22:51:19.278932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8468 22:51:19.333790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8469 22:51:19.334083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8471 22:51:19.382921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8472 22:51:19.383641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8474 22:51:19.434810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8475 22:51:19.435106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8477 22:51:19.485098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8478 22:51:19.485370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8480 22:51:19.530180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8481 22:51:19.530469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8483 22:51:19.585504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8484 22:51:19.585816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8486 22:51:19.630118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8487 22:51:19.630391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8489 22:51:19.679946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8490 22:51:19.680219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8492 22:51:19.731084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8493 22:51:19.731389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8495 22:51:19.777254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8496 22:51:19.777531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8498 22:51:19.822396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8499 22:51:19.823080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8501 22:51:19.873909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8502 22:51:19.874614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8504 22:51:19.933091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8505 22:51:19.933867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8507 22:51:19.982905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8508 22:51:19.983637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8510 22:51:20.043538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8511 22:51:20.044284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8513 22:51:20.094299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8514 22:51:20.094999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8516 22:51:20.146998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8517 22:51:20.147766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8519 22:51:20.201211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8520 22:51:20.201931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8522 22:51:20.257771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8523 22:51:20.258505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8525 22:51:20.311279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8526 22:51:20.311974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8528 22:51:20.365097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8529 22:51:20.365885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8531 22:51:20.422475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8532 22:51:20.423163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8534 22:51:20.478154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8535 22:51:20.479053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8537 22:51:20.532261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8538 22:51:20.532962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8540 22:51:20.584617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8541 22:51:20.585316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8543 22:51:20.640687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8544 22:51:20.641383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8546 22:51:20.696869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8547 22:51:20.697612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8549 22:51:20.750409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8550 22:51:20.751130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8552 22:51:20.810742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8553 22:51:20.811435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8555 22:51:20.863896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8556 22:51:20.864588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8558 22:51:20.919321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8559 22:51:20.920014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8561 22:51:20.974443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8562 22:51:20.975139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8564 22:51:21.029705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8565 22:51:21.030424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8567 22:51:21.075319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8568 22:51:21.075610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8570 22:51:21.116969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8571 22:51:21.117250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8573 22:51:21.162323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8574 22:51:21.163136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8576 22:51:21.213619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8577 22:51:21.214356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8579 22:51:21.267930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8580 22:51:21.268666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8582 22:51:21.320633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8583 22:51:21.321367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8585 22:51:21.369452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8586 22:51:21.370251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8588 22:51:21.427449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8589 22:51:21.428228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8591 22:51:21.476382 <6>[ 38.288025] vaux18: disabling
8592 22:51:21.480415 <6>[ 38.291572] vio28: disabling
8593 22:51:21.486757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8594 22:51:21.487448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8596 22:51:21.548082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8597 22:51:21.548903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8599 22:51:21.608099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8600 22:51:21.608845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8602 22:51:21.665929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8603 22:51:21.666621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8605 22:51:21.728964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8606 22:51:21.729795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8608 22:51:21.788232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8609 22:51:21.788931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8611 22:51:21.849745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8612 22:51:21.850492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8614 22:51:21.903656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8615 22:51:21.904026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8617 22:51:21.959509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8618 22:51:21.960314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8620 22:51:22.009898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8621 22:51:22.010236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8623 22:51:22.056630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8624 22:51:22.056978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8626 22:51:22.107151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8627 22:51:22.107548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8629 22:51:22.156065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8630 22:51:22.156452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8632 22:51:22.207226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8633 22:51:22.207503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8635 22:51:22.254217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8636 22:51:22.254567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8638 22:51:22.303849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8639 22:51:22.304226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8641 22:51:22.355302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8642 22:51:22.355619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8644 22:51:22.402250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8645 22:51:22.402526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8647 22:51:22.441088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8648 22:51:22.441440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8650 22:51:22.488874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8651 22:51:22.489577 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8653 22:51:22.542992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8654 22:51:22.543363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8656 22:51:22.591035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8657 22:51:22.591414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8659 22:51:22.639851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8660 22:51:22.640203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8662 22:51:22.686254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8663 22:51:22.686532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8665 22:51:22.733668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8666 22:51:22.734055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8668 22:51:22.779205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8669 22:51:22.779510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8671 22:51:22.825185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8672 22:51:22.825468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8674 22:51:22.870346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8675 22:51:22.870637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8677 22:51:22.915158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8678 22:51:22.915512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8680 22:51:22.962612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8681 22:51:22.962900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8683 22:51:23.012691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8684 22:51:23.012988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8686 22:51:23.062176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8687 22:51:23.062518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8689 22:51:23.113566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8690 22:51:23.113943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8692 22:51:23.162340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8693 22:51:23.162696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8695 22:51:23.207689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8696 22:51:23.207990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8698 22:51:23.258848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8699 22:51:23.259565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8701 22:51:23.310058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8702 22:51:23.310843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8704 22:51:23.359925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8705 22:51:23.360607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8707 22:51:23.403342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8708 22:51:23.404024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8710 22:51:23.453179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8711 22:51:23.453449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8713 22:51:23.498602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8714 22:51:23.498948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8716 22:51:23.544098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8717 22:51:23.544807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8719 22:51:23.591203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8720 22:51:23.591492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8722 22:51:23.643499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8723 22:51:23.643780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8725 22:51:23.694510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8726 22:51:23.694853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8728 22:51:23.745102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8729 22:51:23.745816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8731 22:51:23.796522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8732 22:51:23.796809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8734 22:51:23.837638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8735 22:51:23.837908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8737 22:51:23.882054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8738 22:51:23.882398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8740 22:51:23.924730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8741 22:51:23.925011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8743 22:51:23.976355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8744 22:51:23.977048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8746 22:51:24.032466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8747 22:51:24.033237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8749 22:51:24.088819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8750 22:51:24.089590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8752 22:51:24.143766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8753 22:51:24.144456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8755 22:51:24.198313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8756 22:51:24.199004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8758 22:51:24.251641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8759 22:51:24.252325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8761 22:51:24.303922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8762 22:51:24.304611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8764 22:51:24.354061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8765 22:51:24.354748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8767 22:51:24.405173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8768 22:51:24.406024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8770 22:51:24.461316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8771 22:51:24.461997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8773 22:51:24.511810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8774 22:51:24.512495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8776 22:51:24.565609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8777 22:51:24.566309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8779 22:51:24.616376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8780 22:51:24.617071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8782 22:51:24.668433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8783 22:51:24.669205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8785 22:51:24.725044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8786 22:51:24.725769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8788 22:51:24.775570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8789 22:51:24.776396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8791 22:51:24.828765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8792 22:51:24.829461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8794 22:51:24.884199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8795 22:51:24.884910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8797 22:51:24.938919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8798 22:51:24.939751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8800 22:51:24.993944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8801 22:51:24.994350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8803 22:51:25.035931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8804 22:51:25.036616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8806 22:51:25.083790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8807 22:51:25.084081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8809 22:51:25.136534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8810 22:51:25.137222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8812 22:51:25.192135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8813 22:51:25.192839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8815 22:51:25.250177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8816 22:51:25.250867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8818 22:51:25.305579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8819 22:51:25.306376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8821 22:51:25.365344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8822 22:51:25.366041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8824 22:51:25.416610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8825 22:51:25.417317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8827 22:51:25.476194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8828 22:51:25.477106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8830 22:51:25.531763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8831 22:51:25.532534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8833 22:51:25.585377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8834 22:51:25.586132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8836 22:51:25.644456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8837 22:51:25.645137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8839 22:51:25.699278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8840 22:51:25.699966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8842 22:51:25.752694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8843 22:51:25.753466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8845 22:51:25.804479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8846 22:51:25.805165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8848 22:51:25.861949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8849 22:51:25.862736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8851 22:51:25.914420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8852 22:51:25.915149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8854 22:51:25.968805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8855 22:51:25.969495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8857 22:51:26.022639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8858 22:51:26.023332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8860 22:51:26.074972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8861 22:51:26.075689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8863 22:51:26.119422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8864 22:51:26.120250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8866 22:51:26.169016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8867 22:51:26.169299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8869 22:51:26.220093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8870 22:51:26.220778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8872 22:51:26.274137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8873 22:51:26.274943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8875 22:51:26.327427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8876 22:51:26.328201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8878 22:51:26.388388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8879 22:51:26.389228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8881 22:51:26.442569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8882 22:51:26.443291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8884 22:51:26.496450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8885 22:51:26.497228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8887 22:51:26.552205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8889 22:51:26.554557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8890 22:51:26.609536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8891 22:51:26.610227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8893 22:51:26.664784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8894 22:51:26.665477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8896 22:51:26.723338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8897 22:51:26.724032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8899 22:51:26.779348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8900 22:51:26.780043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8902 22:51:26.834511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8903 22:51:26.835189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8905 22:51:26.887932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8906 22:51:26.888673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8908 22:51:26.937281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8909 22:51:26.938006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8911 22:51:26.990180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8912 22:51:26.990879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8914 22:51:27.045119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8915 22:51:27.045947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8917 22:51:27.094779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8918 22:51:27.095089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8920 22:51:27.139365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8921 22:51:27.140099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8923 22:51:27.187500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8924 22:51:27.187918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8926 22:51:27.231048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8927 22:51:27.231365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8929 22:51:27.277085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8930 22:51:27.277801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8932 22:51:27.335130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8933 22:51:27.335452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8935 22:51:27.382945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8936 22:51:27.383382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8938 22:51:27.431965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8939 22:51:27.432323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8941 22:51:27.483512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8942 22:51:27.483814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8944 22:51:27.536879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8945 22:51:27.537232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8947 22:51:27.583635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8948 22:51:27.583931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8950 22:51:27.636418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8951 22:51:27.637236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8953 22:51:27.687785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8954 22:51:27.688119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8956 22:51:27.744658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8957 22:51:27.745063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8959 22:51:27.791788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8960 22:51:27.792067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8962 22:51:27.836983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8963 22:51:27.837271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8965 22:51:27.885822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8966 22:51:27.886097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8968 22:51:27.932446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8969 22:51:27.932964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8971 22:51:27.984772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8972 22:51:27.985506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8974 22:51:28.039660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8975 22:51:28.040045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8977 22:51:28.086530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8978 22:51:28.086834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8980 22:51:28.137216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8981 22:51:28.137498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8983 22:51:28.185038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8984 22:51:28.185740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8986 22:51:28.235169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8987 22:51:28.236078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8989 22:51:28.281628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8990 22:51:28.281906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8992 22:51:28.323743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8994 22:51:28.326638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8995 22:51:28.375848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8996 22:51:28.376183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8998 22:51:28.426754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8999 22:51:28.427442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
9001 22:51:28.481586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
9002 22:51:28.482376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
9004 22:51:28.530683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
9005 22:51:28.531394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
9007 22:51:28.581113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
9008 22:51:28.581889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
9010 22:51:28.636851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
9011 22:51:28.637678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
9013 22:51:28.683396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
9014 22:51:28.683676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
9016 22:51:28.731816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
9017 22:51:28.732124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
9019 22:51:28.778964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
9020 22:51:28.779321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
9022 22:51:28.828171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
9023 22:51:28.828449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
9025 22:51:28.873408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
9026 22:51:28.873677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
9028 22:51:28.919132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
9029 22:51:28.919440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
9031 22:51:28.963354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
9032 22:51:28.963626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
9034 22:51:29.005818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
9035 22:51:29.006586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
9037 22:51:29.055446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
9038 22:51:29.055820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
9040 22:51:29.108776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
9041 22:51:29.109531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
9043 22:51:29.165665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
9044 22:51:29.166467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
9046 22:51:29.219452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
9047 22:51:29.220166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
9049 22:51:29.278176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
9050 22:51:29.278942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
9052 22:51:29.329873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
9053 22:51:29.330176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
9055 22:51:29.374696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
9056 22:51:29.374988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
9058 22:51:29.422995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
9059 22:51:29.423298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
9061 22:51:29.468360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
9062 22:51:29.468628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
9064 22:51:29.513159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
9065 22:51:29.513428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
9067 22:51:29.557034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
9068 22:51:29.557309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
9070 22:51:29.602640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
9071 22:51:29.602915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
9073 22:51:29.651154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
9074 22:51:29.652051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
9076 22:51:29.700414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
9077 22:51:29.701193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
9079 22:51:29.752695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
9080 22:51:29.753506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
9082 22:51:29.807812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
9083 22:51:29.808132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
9085 22:51:29.854793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
9086 22:51:29.855141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
9088 22:51:29.900625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
9089 22:51:29.900908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
9091 22:51:29.945038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
9092 22:51:29.945381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
9094 22:51:29.994233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
9095 22:51:29.994609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
9097 22:51:30.035386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
9098 22:51:30.035711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
9100 22:51:30.086305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
9101 22:51:30.086632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
9103 22:51:30.126789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
9104 22:51:30.127117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
9106 22:51:30.169223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
9107 22:51:30.169561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
9109 22:51:30.213154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
9110 22:51:30.213481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
9112 22:51:30.258186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
9113 22:51:30.258959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
9115 22:51:30.302210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
9116 22:51:30.302614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
9118 22:51:30.346244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
9119 22:51:30.346610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
9121 22:51:30.396332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
9122 22:51:30.396677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
9124 22:51:30.441095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
9125 22:51:30.441364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
9127 22:51:30.488281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
9128 22:51:30.488565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
9130 22:51:30.532502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
9131 22:51:30.532942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
9133 22:51:30.580915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
9134 22:51:30.581319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
9136 22:51:30.632285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
9137 22:51:30.632580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
9139 22:51:30.672491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
9140 22:51:30.672850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
9142 22:51:30.720909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
9143 22:51:30.721239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
9145 22:51:30.762237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
9146 22:51:30.762543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
9148 22:51:30.804027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
9149 22:51:30.804807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
9151 22:51:30.850406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
9152 22:51:30.850680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
9154 22:51:30.896852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
9155 22:51:30.897139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
9157 22:51:30.947582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
9158 22:51:30.948412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
9160 22:51:30.994697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
9161 22:51:30.995026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
9163 22:51:31.045062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
9164 22:51:31.045469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
9166 22:51:31.095781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
9167 22:51:31.096064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
9169 22:51:31.143360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
9170 22:51:31.143713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
9172 22:51:31.186978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
9173 22:51:31.187243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
9175 22:51:31.228502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
9176 22:51:31.228827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
9178 22:51:31.275351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
9179 22:51:31.275649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
9181 22:51:31.319397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
9182 22:51:31.320076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
9184 22:51:31.374632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
9185 22:51:31.374966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
9187 22:51:31.420629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
9188 22:51:31.420924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
9190 22:51:31.471709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
9191 22:51:31.471996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
9193 22:51:31.515657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
9194 22:51:31.515964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
9196 22:51:31.556744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
9197 22:51:31.557057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
9199 22:51:31.597911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
9200 22:51:31.598221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
9202 22:51:31.635996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
9203 22:51:31.636303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
9205 22:51:31.678677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
9206 22:51:31.678985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
9208 22:51:31.718944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
9209 22:51:31.719247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
9211 22:51:31.760452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
9212 22:51:31.760767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
9214 22:51:31.801108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
9215 22:51:31.801422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
9217 22:51:31.842640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
9218 22:51:31.842946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
9220 22:51:31.883429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
9221 22:51:31.883814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
9223 22:51:31.919117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
9224 22:51:31.919460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
9226 22:51:31.963589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
9227 22:51:31.963921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
9229 22:51:32.001891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
9230 22:51:32.002221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
9232 22:51:32.044255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
9233 22:51:32.044587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
9235 22:51:32.090169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
9236 22:51:32.090500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
9238 22:51:32.133827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
9239 22:51:32.134160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
9241 22:51:32.176938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
9242 22:51:32.177282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
9244 22:51:32.218298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
9245 22:51:32.218637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
9247 22:51:32.261650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
9248 22:51:32.261983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
9250 22:51:32.304217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
9251 22:51:32.304551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
9253 22:51:32.344739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
9254 22:51:32.345067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
9256 22:51:32.384164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
9257 22:51:32.384511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
9259 22:51:32.430292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
9260 22:51:32.430627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
9262 22:51:32.471963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
9263 22:51:32.472299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
9265 22:51:32.512882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
9266 22:51:32.513212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
9268 22:51:32.554603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
9269 22:51:32.554933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
9271 22:51:32.595849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
9272 22:51:32.596209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
9274 22:51:32.640312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
9275 22:51:32.640646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
9277 22:51:32.684329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
9278 22:51:32.684663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
9280 22:51:32.726852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
9281 22:51:32.727192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
9283 22:51:32.767598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
9284 22:51:32.767931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
9286 22:51:32.803591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
9287 22:51:32.803914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
9289 22:51:32.848118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
9290 22:51:32.848453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
9292 22:51:32.889496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
9293 22:51:32.889826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
9295 22:51:32.930362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
9296 22:51:32.930702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
9298 22:51:32.972929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
9299 22:51:32.973261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
9301 22:51:33.017220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
9302 22:51:33.017599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
9304 22:51:33.058753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
9305 22:51:33.059120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
9307 22:51:33.098587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
9308 22:51:33.098946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9310 22:51:33.144702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9311 22:51:33.145040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9313 22:51:33.187328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9314 22:51:33.187664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9316 22:51:33.228292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9317 22:51:33.228627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9319 22:51:33.268068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9320 22:51:33.268396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9322 22:51:33.307604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9323 22:51:33.307954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9325 22:51:33.349484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9326 22:51:33.349818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9328 22:51:33.388358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9329 22:51:33.388701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9331 22:51:33.435147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9332 22:51:33.435503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9334 22:51:33.477811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9335 22:51:33.478147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9337 22:51:33.521802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9338 22:51:33.522128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9340 22:51:33.565733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9341 22:51:33.566050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9343 22:51:33.608448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9344 22:51:33.608772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9346 22:51:33.652270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9347 22:51:33.652590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9349 22:51:33.688921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9350 22:51:33.689251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9352 22:51:33.731232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9353 22:51:33.731574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9355 22:51:33.772427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9356 22:51:33.772770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9358 22:51:33.816224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9359 22:51:33.816565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9361 22:51:33.858960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9362 22:51:33.859298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9364 22:51:33.902810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9365 22:51:33.903140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9367 22:51:33.944444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9368 22:51:33.944774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9370 22:51:33.981715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9371 22:51:33.982052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9373 22:51:34.025866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9374 22:51:34.026201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9376 22:51:34.067632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9377 22:51:34.067951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9379 22:51:34.111636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9380 22:51:34.111968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9382 22:51:34.151925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9383 22:51:34.152262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9385 22:51:34.195032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9386 22:51:34.195369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9388 22:51:34.240357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9389 22:51:34.240694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9391 22:51:34.280872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9392 22:51:34.281202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9394 22:51:34.326764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9395 22:51:34.327097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9397 22:51:34.372856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9398 22:51:34.373184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9400 22:51:34.415593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9401 22:51:34.415948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9403 22:51:34.456130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9404 22:51:34.456439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9406 22:51:34.497540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9407 22:51:34.497857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9409 22:51:34.534889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9410 22:51:34.535190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9412 22:51:34.574615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9413 22:51:34.574923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9415 22:51:34.620031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9416 22:51:34.620347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9418 22:51:34.661490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9419 22:51:34.661813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9421 22:51:34.702059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9422 22:51:34.702394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9424 22:51:34.746345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9425 22:51:34.746693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9427 22:51:34.789271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9428 22:51:34.789587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9430 22:51:34.832402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9431 22:51:34.832741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9433 22:51:34.876265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9434 22:51:34.876608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9436 22:51:34.917557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9437 22:51:34.917909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9439 22:51:34.959370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9440 22:51:34.959706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9442 22:51:34.998665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9443 22:51:34.998996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9445 22:51:35.039428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9446 22:51:35.039795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9448 22:51:35.083845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9449 22:51:35.084155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9451 22:51:35.124720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9452 22:51:35.125046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9454 22:51:35.163683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9455 22:51:35.164015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9457 22:51:35.208699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9458 22:51:35.209007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9460 22:51:35.252733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9461 22:51:35.253024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9463 22:51:35.298072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9464 22:51:35.298389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9466 22:51:35.338880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9467 22:51:35.339187 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9469 22:51:35.383144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9470 22:51:35.383479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9472 22:51:35.425179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9473 22:51:35.425488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9475 22:51:35.461766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9476 22:51:35.462087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9478 22:51:35.509936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9479 22:51:35.510280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9481 22:51:35.551535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9482 22:51:35.551865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9484 22:51:35.596188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9485 22:51:35.596545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9487 22:51:35.640718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9488 22:51:35.641054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9490 22:51:35.679529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9491 22:51:35.679861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9493 22:51:35.724417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9494 22:51:35.724796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9496 22:51:35.762047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9497 22:51:35.762371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9499 22:51:35.807510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9500 22:51:35.807816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9502 22:51:35.852511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9503 22:51:35.852818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9505 22:51:35.896953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9506 22:51:35.897298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9508 22:51:35.941945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9509 22:51:35.942258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9511 22:51:35.985823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9512 22:51:35.986141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9514 22:51:36.023559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9515 22:51:36.023872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9517 22:51:36.058860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9518 22:51:36.059152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9520 22:51:36.104705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9521 22:51:36.105050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9523 22:51:36.148806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9524 22:51:36.149123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9526 22:51:36.193683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9527 22:51:36.194008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9529 22:51:36.236587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9530 22:51:36.236909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9532 22:51:36.277364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9533 22:51:36.277683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9535 22:51:36.316245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9536 22:51:36.316553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9538 22:51:36.354940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9539 22:51:36.355245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9541 22:51:36.405254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9542 22:51:36.405566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9544 22:51:36.453664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9545 22:51:36.453987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9547 22:51:36.493724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9548 22:51:36.494039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9550 22:51:36.531093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9551 22:51:36.531412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9553 22:51:36.571876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9554 22:51:36.572177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9556 22:51:36.611825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9557 22:51:36.612128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9559 22:51:36.650464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9560 22:51:36.650798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9562 22:51:36.697477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9563 22:51:36.697808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9565 22:51:36.739432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9566 22:51:36.739767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9568 22:51:36.782586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9569 22:51:36.782945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9571 22:51:36.822785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9572 22:51:36.823105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9574 22:51:36.867894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9575 22:51:36.868202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9577 22:51:36.910004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9578 22:51:36.910308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9580 22:51:36.949425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9581 22:51:36.949735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9583 22:51:36.998720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9584 22:51:36.999031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9586 22:51:37.044333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9587 22:51:37.044647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9589 22:51:37.085775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9590 22:51:37.086092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9592 22:51:37.133000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9593 22:51:37.133310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9595 22:51:37.171570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9596 22:51:37.171864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9598 22:51:37.212048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9599 22:51:37.212352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9601 22:51:37.247866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9602 22:51:37.248168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9604 22:51:37.288300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9605 22:51:37.288600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9607 22:51:37.328492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9608 22:51:37.328813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9610 22:51:37.373102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9611 22:51:37.373405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9613 22:51:37.415766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9614 22:51:37.416183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9616 22:51:37.456933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9617 22:51:37.457265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9619 22:51:37.497544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9620 22:51:37.497871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9622 22:51:37.533685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9623 22:51:37.533995 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9625 22:51:37.576171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9626 22:51:37.576494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9628 22:51:37.619723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9629 22:51:37.620055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9631 22:51:37.665176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9632 22:51:37.665500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9634 22:51:37.706669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9635 22:51:37.706998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9637 22:51:37.751232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9638 22:51:37.751561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9640 22:51:37.794786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9641 22:51:37.795103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9643 22:51:37.835635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9644 22:51:37.835962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9646 22:51:37.877970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9647 22:51:37.878297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9649 22:51:37.917322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9650 22:51:37.917645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9652 22:51:37.957633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9653 22:51:37.957954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9655 22:51:38.000100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9656 22:51:38.000422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9658 22:51:38.042135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9659 22:51:38.042462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9661 22:51:38.082240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9662 22:51:38.082562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9664 22:51:38.126160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9665 22:51:38.126482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9667 22:51:38.170999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9668 22:51:38.171344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9670 22:51:38.219006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9671 22:51:38.219344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9673 22:51:38.263235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9674 22:51:38.263564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9676 22:51:38.309575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9677 22:51:38.309898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9679 22:51:38.350022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9680 22:51:38.350344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9682 22:51:38.391995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9683 22:51:38.392312 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9685 22:51:38.430339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9686 22:51:38.430657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9688 22:51:38.473052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9689 22:51:38.473365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9691 22:51:38.516772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9692 22:51:38.517088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9694 22:51:38.557759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9695 22:51:38.558066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9697 22:51:38.598078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9698 22:51:38.598385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9700 22:51:38.636129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9701 22:51:38.636444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9703 22:51:38.676340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9704 22:51:38.676697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9706 22:51:38.719234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9707 22:51:38.719560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9709 22:51:38.761931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9710 22:51:38.762246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9712 22:51:38.799670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9713 22:51:38.799980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9715 22:51:38.841984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9716 22:51:38.842296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9718 22:51:38.886905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9719 22:51:38.887232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9721 22:51:38.930694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9722 22:51:38.931008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9724 22:51:38.973558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9725 22:51:38.973875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9727 22:51:39.009722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9728 22:51:39.010017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9730 22:51:39.055035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9731 22:51:39.055330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9733 22:51:39.096262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9734 22:51:39.096629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9736 22:51:39.137192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9737 22:51:39.137484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9739 22:51:39.174208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9740 22:51:39.174534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9742 22:51:39.213018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9743 22:51:39.213352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9745 22:51:39.253296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9746 22:51:39.253582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9748 22:51:39.291593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9749 22:51:39.291931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9751 22:51:39.337396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9752 22:51:39.337755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9754 22:51:39.377004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9755 22:51:39.377333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9757 22:51:39.416559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9758 22:51:39.416923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9760 22:51:39.455131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9761 22:51:39.455466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9763 22:51:39.496874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9764 22:51:39.497217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9766 22:51:39.539088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9767 22:51:39.539441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9769 22:51:39.576504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9770 22:51:39.576845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9772 22:51:39.623521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9773 22:51:39.623865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9775 22:51:39.661814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9776 22:51:39.662134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9778 22:51:39.703378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9779 22:51:39.703714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9781 22:51:39.752174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9782 22:51:39.752509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9784 22:51:39.799709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9785 22:51:39.800046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9787 22:51:39.844507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9788 22:51:39.844846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9790 22:51:39.881429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9791 22:51:39.881768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9793 22:51:39.928634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9794 22:51:39.928972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9796 22:51:39.968964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9797 22:51:39.969286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9799 22:51:40.005958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9800 22:51:40.006239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9802 22:51:40.039127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9803 22:51:40.039437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9805 22:51:40.081819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9806 22:51:40.082098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9808 22:51:40.123495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9809 22:51:40.123781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9811 22:51:40.163496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9812 22:51:40.163802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9814 22:51:40.204894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9815 22:51:40.205167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9817 22:51:40.241590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9818 22:51:40.241907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9820 22:51:40.277699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9821 22:51:40.277998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9823 22:51:40.316855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9824 22:51:40.317201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9826 22:51:40.351688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9827 22:51:40.352001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9829 22:51:40.392091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9830 22:51:40.392452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9832 22:51:40.425325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9833 22:51:40.425703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9835 22:51:40.466075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9836 22:51:40.466511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9838 22:51:40.502282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9839 22:51:40.502705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9841 22:51:40.539245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9842 22:51:40.539668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9844 22:51:40.579636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9845 22:51:40.580090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9847 22:51:40.621007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9848 22:51:40.621347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9850 22:51:40.656547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9851 22:51:40.656879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9853 22:51:40.686920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9854 22:51:40.687247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9856 22:51:40.729806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9857 22:51:40.730156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9859 22:51:40.766283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9860 22:51:40.766635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9862 22:51:40.799893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9863 22:51:40.800234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9865 22:51:40.840400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9866 22:51:40.840739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9868 22:51:40.882218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9869 22:51:40.882557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9871 22:51:40.921186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9872 22:51:40.921526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9874 22:51:40.957043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9875 22:51:40.957384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9877 22:51:41.000904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9878 22:51:41.001246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9880 22:51:41.042274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9881 22:51:41.042616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9883 22:51:41.088735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9884 22:51:41.089075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9886 22:51:41.130255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9887 22:51:41.130597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9889 22:51:41.170096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9890 22:51:41.170472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9892 22:51:41.211310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9893 22:51:41.211648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9895 22:51:41.247248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9896 22:51:41.247584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9898 22:51:41.294423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9899 22:51:41.294755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9901 22:51:41.333973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9902 22:51:41.334300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9904 22:51:41.375953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9905 22:51:41.376270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9907 22:51:41.416667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9908 22:51:41.417010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9910 22:51:41.456055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9911 22:51:41.456397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9913 22:51:41.491535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9914 22:51:41.491869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9916 22:51:41.524649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9917 22:51:41.524961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9919 22:51:41.567173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9920 22:51:41.567545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9922 22:51:41.606017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9923 22:51:41.606329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9925 22:51:41.649405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9926 22:51:41.649715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9928 22:51:41.694446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9929 22:51:41.694762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9931 22:51:41.733960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9932 22:51:41.734272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9934 22:51:41.772558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9935 22:51:41.772861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9937 22:51:41.810899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9938 22:51:41.811239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9940 22:51:41.854841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9941 22:51:41.855179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9943 22:51:41.898439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9944 22:51:41.898800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9946 22:51:41.938794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9947 22:51:41.939129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9949 22:51:41.981993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9950 22:51:41.982322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9952 22:51:42.027538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9953 22:51:42.027902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9955 22:51:42.070425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9956 22:51:42.070763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9958 22:51:42.103638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9959 22:51:42.103970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9961 22:51:42.150567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9962 22:51:42.150897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9964 22:51:42.195901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9965 22:51:42.196248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9967 22:51:42.239917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9968 22:51:42.240234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9970 22:51:42.277869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9971 22:51:42.278207 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9973 22:51:42.318969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9974 22:51:42.319297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9976 22:51:42.358423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9977 22:51:42.358730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9979 22:51:42.394660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9980 22:51:42.395002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9982 22:51:42.442847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9983 22:51:42.443205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9985 22:51:42.496213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9986 22:51:42.496883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9988 22:51:42.549116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9989 22:51:42.549427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9991 22:51:42.591026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9992 22:51:42.591703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9994 22:51:42.641226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9995 22:51:42.641798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9997 22:51:42.693913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9998 22:51:42.694497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
10000 22:51:42.744526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
10001 22:51:42.745093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
10003 22:51:42.797888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
10004 22:51:42.798530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
10006 22:51:42.851454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
10007 22:51:42.852065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
10009 22:51:42.901008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
10010 22:51:42.901344 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
10012 22:51:42.945519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
10013 22:51:42.945860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
10015 22:51:42.991418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
10016 22:51:42.991718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
10018 22:51:43.036152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
10019 22:51:43.036468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
10021 22:51:43.077002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
10022 22:51:43.077296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
10024 22:51:43.127683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
10025 22:51:43.128000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
10027 22:51:43.176092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
10028 22:51:43.176397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
10030 22:51:43.220628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
10031 22:51:43.220940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
10033 22:51:43.264675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
10034 22:51:43.264983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
10036 22:51:43.312145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
10037 22:51:43.312453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
10039 22:51:43.359240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
10040 22:51:43.359580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
10042 22:51:43.402038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
10043 22:51:43.402399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
10045 22:51:43.449999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
10046 22:51:43.450342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
10048 22:51:43.494364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
10049 22:51:43.494663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
10051 22:51:43.536977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
10052 22:51:43.537301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
10054 22:51:43.582345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
10055 22:51:43.582680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
10057 22:51:43.630832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
10058 22:51:43.631178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
10060 22:51:43.675885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
10061 22:51:43.676238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
10063 22:51:43.715755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
10064 22:51:43.716063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
10066 22:51:43.763694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
10067 22:51:43.764071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
10069 22:51:43.806021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
10070 22:51:43.806371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
10072 22:51:43.849857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
10073 22:51:43.850179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
10075 22:51:43.895609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
10076 22:51:43.895960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
10078 22:51:43.938827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
10079 22:51:43.939195 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
10081 22:51:43.980203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
10082 22:51:43.980537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
10084 22:51:44.033016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
10085 22:51:44.033976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
10087 22:51:44.084127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
10088 22:51:44.084497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
10090 22:51:44.127653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
10091 22:51:44.128033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
10093 22:51:44.170961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
10094 22:51:44.171337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
10096 22:51:44.216646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
10097 22:51:44.217027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
10099 22:51:44.262008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
10100 22:51:44.262388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
10102 22:51:44.304743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
10103 22:51:44.305071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
10105 22:51:44.344730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
10106 22:51:44.345033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
10108 22:51:44.394596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
10109 22:51:44.394884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
10111 22:51:44.438750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
10112 22:51:44.439068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
10114 22:51:44.479865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
10115 22:51:44.480179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
10117 22:51:44.524241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
10118 22:51:44.524528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
10120 22:51:44.570725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
10121 22:51:44.571013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
10123 22:51:44.615853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
10124 22:51:44.616130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
10126 22:51:44.656213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
10127 22:51:44.656491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
10129 22:51:44.701245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
10130 22:51:44.701530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
10132 22:51:44.745684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
10133 22:51:44.745961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
10135 22:51:44.793252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
10136 22:51:44.793530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
10138 22:51:44.836983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
10139 22:51:44.837276 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
10141 22:51:44.876136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
10142 22:51:44.876410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
10144 22:51:44.912529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
10145 22:51:44.912811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
10147 22:51:44.951133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
10148 22:51:44.951460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
10150 22:51:44.995344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
10151 22:51:44.995632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
10153 22:51:45.036875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
10154 22:51:45.037167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
10156 22:51:45.082694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
10157 22:51:45.082973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
10159 22:51:45.126136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
10160 22:51:45.126420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
10162 22:51:45.171450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
10163 22:51:45.171731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
10165 22:51:45.215849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
10166 22:51:45.216133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
10168 22:51:45.260524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
10169 22:51:45.260819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
10171 22:51:45.310578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
10172 22:51:45.310861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
10174 22:51:45.357330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
10175 22:51:45.357620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
10177 22:51:45.403088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
10178 22:51:45.403374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
10180 22:51:45.446015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
10181 22:51:45.446298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
10183 22:51:45.490627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
10184 22:51:45.490905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
10186 22:51:45.536343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
10187 22:51:45.536629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
10189 22:51:45.580368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
10190 22:51:45.580654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
10192 22:51:45.628804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
10193 22:51:45.629129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
10195 22:51:45.673042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
10196 22:51:45.673331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
10198 22:51:45.715230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
10199 22:51:45.715504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
10201 22:51:45.754818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
10202 22:51:45.755093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
10204 22:51:45.796543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
10205 22:51:45.796827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
10207 22:51:45.840655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
10208 22:51:45.840932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
10210 22:51:45.875124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
10211 22:51:45.875411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
10213 22:51:45.918339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
10214 22:51:45.918631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
10216 22:51:45.962284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
10217 22:51:45.962604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
10219 22:51:45.999831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
10220 22:51:46.000106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
10222 22:51:46.041016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
10223 22:51:46.041313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
10225 22:51:46.082369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
10226 22:51:46.082650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
10228 22:51:46.123734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
10229 22:51:46.124018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
10231 22:51:46.162316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
10232 22:51:46.162603 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
10234 22:51:46.205419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
10235 22:51:46.205729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
10237 22:51:46.246985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
10238 22:51:46.247249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
10240 22:51:46.285920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
10241 22:51:46.286200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
10243 22:51:46.325241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
10244 22:51:46.325511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
10246 22:51:46.364450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
10247 22:51:46.364726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
10249 22:51:46.406231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10250 22:51:46.406361 + set +x
10251 22:51:46.406613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10253 22:51:46.412679 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 13683657_1.6.2.3.5>
10254 22:51:46.412946 Received signal: <ENDRUN> 1_kselftest-alsa 13683657_1.6.2.3.5
10255 22:51:46.413029 Ending use of test pattern.
10256 22:51:46.413100 Ending test lava.1_kselftest-alsa (13683657_1.6.2.3.5), duration 43.34
10258 22:51:46.415967 <LAVA_TEST_RUNNER EXIT>
10259 22:51:46.416235 ok: lava_test_shell seems to have completed
10260 22:51:46.420011 alsa_mixer-test: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_valid_0_93: pass
shardfile-alsa: pass
10261 22:51:46.420379 end: 3.1 lava-test-shell (duration 00:00:44) [common]
10262 22:51:46.420479 end: 3 lava-test-retry (duration 00:00:44) [common]
10263 22:51:46.420578 start: 4 finalize (timeout 00:07:19) [common]
10264 22:51:46.420677 start: 4.1 power-off (timeout 00:00:30) [common]
10265 22:51:46.420854 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2' '--port=1' '--command=off'
10266 22:51:47.505021 >> Command sent successfully.
10267 22:51:47.507545 Returned 0 in 1 seconds
10268 22:51:47.607958 end: 4.1 power-off (duration 00:00:01) [common]
10270 22:51:47.608291 start: 4.2 read-feedback (timeout 00:07:17) [common]
10271 22:51:47.608590 Listened to connection for namespace 'common' for up to 1s
10272 22:51:48.608605 Finalising connection for namespace 'common'
10273 22:51:48.608810 Disconnecting from shell: Finalise
10274 22:51:48.608918 / #
10275 22:51:48.709267 end: 4.2 read-feedback (duration 00:00:01) [common]
10276 22:51:48.709444 end: 4 finalize (duration 00:00:02) [common]
10277 22:51:48.709593 Cleaning after the job
10278 22:51:48.709716 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/ramdisk
10279 22:51:48.712168 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/kernel
10280 22:51:48.723498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/dtb
10281 22:51:48.723697 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/nfsrootfs
10282 22:51:48.791458 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683657/tftp-deploy-59_93ml8/modules
10283 22:51:48.797390 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683657
10284 22:51:49.425454 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683657
10285 22:51:49.425653 Job finished correctly