Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 40
- Boot result: PASS
1 22:56:18.828516 lava-dispatcher, installed at version: 2024.01
2 22:56:18.828714 start: 0 validate
3 22:56:18.828844 Start time: 2024-05-07 22:56:18.828835+00:00 (UTC)
4 22:56:18.828965 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:56:18.829090 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:56:19.104671 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:56:19.105320 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:56:19.365566 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:56:19.366205 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:56:19.626427 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:56:19.627120 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:56:19.878915 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:56:19.879087 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:56:20.145267 validate duration: 1.32
16 22:56:20.146390 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:56:20.146870 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:56:20.147302 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:56:20.147867 Not decompressing ramdisk as can be used compressed.
20 22:56:20.148474 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:56:20.148817 saving as /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/ramdisk/initrd.cpio.gz
22 22:56:20.149169 total size: 5628169 (5 MB)
23 22:56:20.153951 progress 0 % (0 MB)
24 22:56:20.162251 progress 5 % (0 MB)
25 22:56:20.168870 progress 10 % (0 MB)
26 22:56:20.173060 progress 15 % (0 MB)
27 22:56:20.177055 progress 20 % (1 MB)
28 22:56:20.180181 progress 25 % (1 MB)
29 22:56:20.183107 progress 30 % (1 MB)
30 22:56:20.185892 progress 35 % (1 MB)
31 22:56:20.188059 progress 40 % (2 MB)
32 22:56:20.190524 progress 45 % (2 MB)
33 22:56:20.192430 progress 50 % (2 MB)
34 22:56:20.194541 progress 55 % (2 MB)
35 22:56:20.196546 progress 60 % (3 MB)
36 22:56:20.198242 progress 65 % (3 MB)
37 22:56:20.200143 progress 70 % (3 MB)
38 22:56:20.201704 progress 75 % (4 MB)
39 22:56:20.203397 progress 80 % (4 MB)
40 22:56:20.204922 progress 85 % (4 MB)
41 22:56:20.206539 progress 90 % (4 MB)
42 22:56:20.208097 progress 95 % (5 MB)
43 22:56:20.209501 progress 100 % (5 MB)
44 22:56:20.209711 5 MB downloaded in 0.06 s (88.63 MB/s)
45 22:56:20.209869 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:56:20.210118 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:56:20.210207 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:56:20.210293 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:56:20.210431 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:56:20.210513 saving as /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/kernel/Image
52 22:56:20.210576 total size: 54682112 (52 MB)
53 22:56:20.210638 No compression specified
54 22:56:20.211754 progress 0 % (0 MB)
55 22:56:20.225334 progress 5 % (2 MB)
56 22:56:20.239222 progress 10 % (5 MB)
57 22:56:20.253261 progress 15 % (7 MB)
58 22:56:20.267174 progress 20 % (10 MB)
59 22:56:20.280898 progress 25 % (13 MB)
60 22:56:20.294577 progress 30 % (15 MB)
61 22:56:20.308516 progress 35 % (18 MB)
62 22:56:20.322089 progress 40 % (20 MB)
63 22:56:20.335714 progress 45 % (23 MB)
64 22:56:20.349745 progress 50 % (26 MB)
65 22:56:20.363410 progress 55 % (28 MB)
66 22:56:20.377441 progress 60 % (31 MB)
67 22:56:20.391476 progress 65 % (33 MB)
68 22:56:20.405351 progress 70 % (36 MB)
69 22:56:20.419011 progress 75 % (39 MB)
70 22:56:20.432999 progress 80 % (41 MB)
71 22:56:20.447053 progress 85 % (44 MB)
72 22:56:20.460781 progress 90 % (46 MB)
73 22:56:20.474237 progress 95 % (49 MB)
74 22:56:20.487648 progress 100 % (52 MB)
75 22:56:20.487865 52 MB downloaded in 0.28 s (188.07 MB/s)
76 22:56:20.488074 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:56:20.488307 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:56:20.488392 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:56:20.488479 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:56:20.488646 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:56:20.488722 saving as /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/dtb/mt8192-asurada-spherion-r0.dtb
83 22:56:20.488816 total size: 47258 (0 MB)
84 22:56:20.488913 No compression specified
85 22:56:20.490005 progress 69 % (0 MB)
86 22:56:20.490292 progress 100 % (0 MB)
87 22:56:20.490474 0 MB downloaded in 0.00 s (27.23 MB/s)
88 22:56:20.490594 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:56:20.490824 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:56:20.490908 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:56:20.490988 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:56:20.491103 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:56:20.491170 saving as /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/nfsrootfs/full.rootfs.tar
95 22:56:20.491230 total size: 120894716 (115 MB)
96 22:56:20.491291 Using unxz to decompress xz
97 22:56:20.495568 progress 0 % (0 MB)
98 22:56:20.838343 progress 5 % (5 MB)
99 22:56:21.188468 progress 10 % (11 MB)
100 22:56:21.533817 progress 15 % (17 MB)
101 22:56:21.859078 progress 20 % (23 MB)
102 22:56:22.147917 progress 25 % (28 MB)
103 22:56:22.508987 progress 30 % (34 MB)
104 22:56:22.853367 progress 35 % (40 MB)
105 22:56:23.019766 progress 40 % (46 MB)
106 22:56:23.197506 progress 45 % (51 MB)
107 22:56:23.508439 progress 50 % (57 MB)
108 22:56:23.890493 progress 55 % (63 MB)
109 22:56:24.245374 progress 60 % (69 MB)
110 22:56:24.600708 progress 65 % (74 MB)
111 22:56:24.957807 progress 70 % (80 MB)
112 22:56:25.327946 progress 75 % (86 MB)
113 22:56:25.679887 progress 80 % (92 MB)
114 22:56:26.022784 progress 85 % (98 MB)
115 22:56:26.380196 progress 90 % (103 MB)
116 22:56:26.712285 progress 95 % (109 MB)
117 22:56:27.075532 progress 100 % (115 MB)
118 22:56:27.081037 115 MB downloaded in 6.59 s (17.50 MB/s)
119 22:56:27.081301 end: 1.4.1 http-download (duration 00:00:07) [common]
121 22:56:27.081579 end: 1.4 download-retry (duration 00:00:07) [common]
122 22:56:27.081670 start: 1.5 download-retry (timeout 00:09:53) [common]
123 22:56:27.081762 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 22:56:27.081911 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:56:27.081982 saving as /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/modules/modules.tar
126 22:56:27.082046 total size: 8594396 (8 MB)
127 22:56:27.082115 Using unxz to decompress xz
128 22:56:27.086135 progress 0 % (0 MB)
129 22:56:27.105217 progress 5 % (0 MB)
130 22:56:27.130143 progress 10 % (0 MB)
131 22:56:27.154596 progress 15 % (1 MB)
132 22:56:27.178241 progress 20 % (1 MB)
133 22:56:27.202870 progress 25 % (2 MB)
134 22:56:27.226566 progress 30 % (2 MB)
135 22:56:27.250490 progress 35 % (2 MB)
136 22:56:27.275347 progress 40 % (3 MB)
137 22:56:27.300966 progress 45 % (3 MB)
138 22:56:27.325735 progress 50 % (4 MB)
139 22:56:27.350331 progress 55 % (4 MB)
140 22:56:27.375786 progress 60 % (4 MB)
141 22:56:27.400565 progress 65 % (5 MB)
142 22:56:27.426579 progress 70 % (5 MB)
143 22:56:27.451206 progress 75 % (6 MB)
144 22:56:27.476419 progress 80 % (6 MB)
145 22:56:27.501776 progress 85 % (6 MB)
146 22:56:27.530281 progress 90 % (7 MB)
147 22:56:27.559121 progress 95 % (7 MB)
148 22:56:27.585197 progress 100 % (8 MB)
149 22:56:27.590331 8 MB downloaded in 0.51 s (16.13 MB/s)
150 22:56:27.590580 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:56:27.590854 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:56:27.590950 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 22:56:27.591047 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 22:56:31.075116 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13683713/extract-nfsrootfs-x5eqj7ae
156 22:56:31.075319 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:56:31.075421 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 22:56:31.075633 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5
159 22:56:31.075766 makedir: /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin
160 22:56:31.075870 makedir: /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/tests
161 22:56:31.075990 makedir: /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/results
162 22:56:31.076108 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-add-keys
163 22:56:31.076256 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-add-sources
164 22:56:31.076388 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-background-process-start
165 22:56:31.076518 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-background-process-stop
166 22:56:31.076648 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-common-functions
167 22:56:31.076775 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-echo-ipv4
168 22:56:31.076902 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-install-packages
169 22:56:31.077028 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-installed-packages
170 22:56:31.077154 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-os-build
171 22:56:31.077278 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-probe-channel
172 22:56:31.077403 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-probe-ip
173 22:56:31.077527 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-target-ip
174 22:56:31.077651 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-target-mac
175 22:56:31.077775 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-target-storage
176 22:56:31.077902 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-test-case
177 22:56:31.078029 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-test-event
178 22:56:31.078153 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-test-feedback
179 22:56:31.078276 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-test-raise
180 22:56:31.078402 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-test-reference
181 22:56:31.078527 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-test-runner
182 22:56:31.078653 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-test-set
183 22:56:31.078778 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-test-shell
184 22:56:31.078905 Updating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-add-keys (debian)
185 22:56:31.079054 Updating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-add-sources (debian)
186 22:56:31.079195 Updating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-install-packages (debian)
187 22:56:31.079333 Updating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-installed-packages (debian)
188 22:56:31.079470 Updating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/bin/lava-os-build (debian)
189 22:56:31.079590 Creating /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/environment
190 22:56:31.079686 LAVA metadata
191 22:56:31.079756 - LAVA_JOB_ID=13683713
192 22:56:31.079819 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:56:31.079920 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 22:56:31.080140 skipped lava-vland-overlay
195 22:56:31.080218 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:56:31.080299 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 22:56:31.080362 skipped lava-multinode-overlay
198 22:56:31.080435 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:56:31.080515 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 22:56:31.080589 Loading test definitions
201 22:56:31.080678 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 22:56:31.080749 Using /lava-13683713 at stage 0
203 22:56:31.081029 uuid=13683713_1.6.2.3.1 testdef=None
204 22:56:31.081119 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:56:31.081204 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 22:56:31.081655 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:56:31.081881 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 22:56:31.082430 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:56:31.082661 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 22:56:31.083200 runner path: /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/0/tests/0_timesync-off test_uuid 13683713_1.6.2.3.1
213 22:56:31.083357 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:56:31.083584 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 22:56:31.083657 Using /lava-13683713 at stage 0
217 22:56:31.083754 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:56:31.083842 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/0/tests/1_kselftest-alsa'
219 22:56:33.012244 Running '/usr/bin/git checkout kernelci.org
220 22:56:33.023859 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 22:56:33.024634 uuid=13683713_1.6.2.3.5 testdef=None
222 22:56:33.024796 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 22:56:33.025050 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 22:56:33.025807 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:56:33.026044 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 22:56:33.027022 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:56:33.027263 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 22:56:33.028232 runner path: /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/0/tests/1_kselftest-alsa test_uuid 13683713_1.6.2.3.5
232 22:56:33.028325 BOARD='mt8192-asurada-spherion-r0'
233 22:56:33.028391 BRANCH='cip'
234 22:56:33.028453 SKIPFILE='/dev/null'
235 22:56:33.028513 SKIP_INSTALL='True'
236 22:56:33.028570 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:56:33.028630 TST_CASENAME=''
238 22:56:33.028686 TST_CMDFILES='alsa'
239 22:56:33.028827 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:56:33.029038 Creating lava-test-runner.conf files
242 22:56:33.029103 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683713/lava-overlay-ipo4vho5/lava-13683713/0 for stage 0
243 22:56:33.029196 - 0_timesync-off
244 22:56:33.029275 - 1_kselftest-alsa
245 22:56:33.029372 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 22:56:33.029462 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 22:56:40.578974 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:56:40.579136 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 22:56:40.579237 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:56:40.579337 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 22:56:40.579427 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 22:56:40.742325 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:56:40.742716 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 22:56:40.742827 extracting modules file /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683713/extract-nfsrootfs-x5eqj7ae
255 22:56:40.958386 extracting modules file /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683713/extract-overlay-ramdisk-bsofj9x1/ramdisk
256 22:56:41.182479 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:56:41.182650 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 22:56:41.182754 [common] Applying overlay to NFS
259 22:56:41.182827 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683713/compress-overlay-qtd_opnz/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683713/extract-nfsrootfs-x5eqj7ae
260 22:56:42.115311 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:56:42.115469 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 22:56:42.115569 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:56:42.115664 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 22:56:42.115746 Building ramdisk /var/lib/lava/dispatcher/tmp/13683713/extract-overlay-ramdisk-bsofj9x1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683713/extract-overlay-ramdisk-bsofj9x1/ramdisk
265 22:56:42.448390 >> 130327 blocks
266 22:56:44.506469 rename /var/lib/lava/dispatcher/tmp/13683713/extract-overlay-ramdisk-bsofj9x1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/ramdisk/ramdisk.cpio.gz
267 22:56:44.507013 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:56:44.507171 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 22:56:44.507279 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 22:56:44.507418 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/kernel/Image'
271 22:56:58.294074 Returned 0 in 13 seconds
272 22:56:58.394990 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/kernel/image.itb
273 22:56:58.771818 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:56:58.772246 output: Created: Tue May 7 23:56:58 2024
275 22:56:58.772329 output: Image 0 (kernel-1)
276 22:56:58.772395 output: Description:
277 22:56:58.772478 output: Created: Tue May 7 23:56:58 2024
278 22:56:58.772540 output: Type: Kernel Image
279 22:56:58.772603 output: Compression: lzma compressed
280 22:56:58.772662 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
281 22:56:58.772721 output: Architecture: AArch64
282 22:56:58.772778 output: OS: Linux
283 22:56:58.772837 output: Load Address: 0x00000000
284 22:56:58.772896 output: Entry Point: 0x00000000
285 22:56:58.772954 output: Hash algo: crc32
286 22:56:58.773008 output: Hash value: 727ee7c6
287 22:56:58.773066 output: Image 1 (fdt-1)
288 22:56:58.773124 output: Description: mt8192-asurada-spherion-r0
289 22:56:58.773179 output: Created: Tue May 7 23:56:58 2024
290 22:56:58.773234 output: Type: Flat Device Tree
291 22:56:58.773288 output: Compression: uncompressed
292 22:56:58.773342 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 22:56:58.773396 output: Architecture: AArch64
294 22:56:58.773449 output: Hash algo: crc32
295 22:56:58.773502 output: Hash value: 0f8e4d2e
296 22:56:58.773555 output: Image 2 (ramdisk-1)
297 22:56:58.773608 output: Description: unavailable
298 22:56:58.773662 output: Created: Tue May 7 23:56:58 2024
299 22:56:58.773716 output: Type: RAMDisk Image
300 22:56:58.773770 output: Compression: Unknown Compression
301 22:56:58.773824 output: Data Size: 18728790 Bytes = 18289.83 KiB = 17.86 MiB
302 22:56:58.773879 output: Architecture: AArch64
303 22:56:58.773932 output: OS: Linux
304 22:56:58.773986 output: Load Address: unavailable
305 22:56:58.774039 output: Entry Point: unavailable
306 22:56:58.774093 output: Hash algo: crc32
307 22:56:58.774146 output: Hash value: 562c9e9a
308 22:56:58.774216 output: Default Configuration: 'conf-1'
309 22:56:58.774306 output: Configuration 0 (conf-1)
310 22:56:58.774392 output: Description: mt8192-asurada-spherion-r0
311 22:56:58.774481 output: Kernel: kernel-1
312 22:56:58.774563 output: Init Ramdisk: ramdisk-1
313 22:56:58.774636 output: FDT: fdt-1
314 22:56:58.774693 output: Loadables: kernel-1
315 22:56:58.774750 output:
316 22:56:58.774958 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 22:56:58.775064 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 22:56:58.775172 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 22:56:58.775265 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 22:56:58.775350 No LXC device requested
321 22:56:58.775432 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:56:58.775518 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 22:56:58.775596 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:56:58.775667 Checking files for TFTP limit of 4294967296 bytes.
325 22:56:58.776214 end: 1 tftp-deploy (duration 00:00:39) [common]
326 22:56:58.776326 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:56:58.776483 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:56:58.776615 substitutions:
329 22:56:58.776686 - {DTB}: 13683713/tftp-deploy-vrtot5ad/dtb/mt8192-asurada-spherion-r0.dtb
330 22:56:58.776752 - {INITRD}: 13683713/tftp-deploy-vrtot5ad/ramdisk/ramdisk.cpio.gz
331 22:56:58.776813 - {KERNEL}: 13683713/tftp-deploy-vrtot5ad/kernel/Image
332 22:56:58.776873 - {LAVA_MAC}: None
333 22:56:58.776932 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13683713/extract-nfsrootfs-x5eqj7ae
334 22:56:58.776990 - {NFS_SERVER_IP}: 192.168.201.1
335 22:56:58.777047 - {PRESEED_CONFIG}: None
336 22:56:58.777103 - {PRESEED_LOCAL}: None
337 22:56:58.777159 - {RAMDISK}: 13683713/tftp-deploy-vrtot5ad/ramdisk/ramdisk.cpio.gz
338 22:56:58.777216 - {ROOT_PART}: None
339 22:56:58.777271 - {ROOT}: None
340 22:56:58.777328 - {SERVER_IP}: 192.168.201.1
341 22:56:58.777384 - {TEE}: None
342 22:56:58.777440 Parsed boot commands:
343 22:56:58.777496 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:56:58.777677 Parsed boot commands: tftpboot 192.168.201.1 13683713/tftp-deploy-vrtot5ad/kernel/image.itb 13683713/tftp-deploy-vrtot5ad/kernel/cmdline
345 22:56:58.777766 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:56:58.777856 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:56:58.777951 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:56:58.778039 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:56:58.778113 Not connected, no need to disconnect.
350 22:56:58.778188 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:56:58.778274 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:56:58.778342 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 22:56:58.782504 Setting prompt string to ['lava-test: # ']
354 22:56:58.782874 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:56:58.782985 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:56:58.783100 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:56:58.783211 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:56:58.783417 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 22:57:03.916217 >> Command sent successfully.
360 22:57:03.918714 Returned 0 in 5 seconds
361 22:57:04.019121 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:57:04.019478 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:57:04.019584 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:57:04.019679 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:57:04.019745 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:57:04.019816 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:57:04.020129 [Enter `^Ec?' for help]
369 22:57:04.191686
370 22:57:04.191841
371 22:57:04.191916 F0: 102B 0000
372 22:57:04.192030
373 22:57:04.192098 F3: 1001 0000 [0200]
374 22:57:04.192159
375 22:57:04.195132 F3: 1001 0000
376 22:57:04.195218
377 22:57:04.195289 F7: 102D 0000
378 22:57:04.195354
379 22:57:04.195415 F1: 0000 0000
380 22:57:04.195476
381 22:57:04.199238 V0: 0000 0000 [0001]
382 22:57:04.199327
383 22:57:04.199396 00: 0007 8000
384 22:57:04.199464
385 22:57:04.203255 01: 0000 0000
386 22:57:04.203342
387 22:57:04.203410 BP: 0C00 0209 [0000]
388 22:57:04.203474
389 22:57:04.203535 G0: 1182 0000
390 22:57:04.203595
391 22:57:04.206637 EC: 0000 0021 [4000]
392 22:57:04.206723
393 22:57:04.206791 S7: 0000 0000 [0000]
394 22:57:04.206855
395 22:57:04.210533 CC: 0000 0000 [0001]
396 22:57:04.210618
397 22:57:04.210686 T0: 0000 0040 [010F]
398 22:57:04.213684
399 22:57:04.213769 Jump to BL
400 22:57:04.213838
401 22:57:04.238138
402 22:57:04.238284
403 22:57:04.238357
404 22:57:04.245275 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:57:04.249178 ARM64: Exception handlers installed.
406 22:57:04.253114 ARM64: Testing exception
407 22:57:04.256771 ARM64: Done test exception
408 22:57:04.264442 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:57:04.271936 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:57:04.278779 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:57:04.288558 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:57:04.295837 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:57:04.305643 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:57:04.316387 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:57:04.322971 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:57:04.340596 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:57:04.344114 WDT: Last reset was cold boot
418 22:57:04.347403 SPI1(PAD0) initialized at 2873684 Hz
419 22:57:04.351248 SPI5(PAD0) initialized at 992727 Hz
420 22:57:04.354351 VBOOT: Loading verstage.
421 22:57:04.360901 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:57:04.364830 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:57:04.367947 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:57:04.371232 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:57:04.378113 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:57:04.384877 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:57:04.395712 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 22:57:04.395804
429 22:57:04.395873
430 22:57:04.406484 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:57:04.409632 ARM64: Exception handlers installed.
432 22:57:04.409774 ARM64: Testing exception
433 22:57:04.413001 ARM64: Done test exception
434 22:57:04.416953 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:57:04.423165 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:57:04.436987 Probing TPM: . done!
437 22:57:04.437081 TPM ready after 0 ms
438 22:57:04.443977 Connected to device vid:did:rid of 1ae0:0028:00
439 22:57:04.451146 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 22:57:04.510851 Initialized TPM device CR50 revision 0
441 22:57:04.522686 tlcl_send_startup: Startup return code is 0
442 22:57:04.522805 TPM: setup succeeded
443 22:57:04.534104 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:57:04.543227 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:57:04.555193 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:57:04.564814 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:57:04.569257 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:57:04.572713 in-header: 03 07 00 00 08 00 00 00
449 22:57:04.576741 in-data: aa e4 47 04 13 02 00 00
450 22:57:04.576866 Chrome EC: UHEPI supported
451 22:57:04.583275 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:57:04.588170 in-header: 03 95 00 00 08 00 00 00
453 22:57:04.591646 in-data: 18 20 20 08 00 00 00 00
454 22:57:04.591734 Phase 1
455 22:57:04.598677 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:57:04.602341 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:57:04.609757 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:57:04.613240 Recovery requested (1009000e)
459 22:57:04.620836 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:57:04.626106 tlcl_extend: response is 0
461 22:57:04.635649 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:57:04.640933 tlcl_extend: response is 0
463 22:57:04.648126 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:57:04.668428 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 22:57:04.674711 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:57:04.674805
467 22:57:04.674875
468 22:57:04.685088 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:57:04.688335 ARM64: Exception handlers installed.
470 22:57:04.691561 ARM64: Testing exception
471 22:57:04.691652 ARM64: Done test exception
472 22:57:04.713430 pmic_efuse_setting: Set efuses in 11 msecs
473 22:57:04.717066 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:57:04.723935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:57:04.727279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:57:04.730880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:57:04.738019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:57:04.741435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:57:04.745806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:57:04.753112 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:57:04.756822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:57:04.760261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:57:04.767891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:57:04.771673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:57:04.774978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:57:04.778873 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:57:04.786303 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:57:04.793870 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:57:04.797162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:57:04.804899 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:57:04.808726 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:57:04.815865 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:57:04.819766 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:57:04.827387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:57:04.830498 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:57:04.838034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:57:04.842505 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:57:04.849394 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:57:04.853082 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:57:04.856557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:57:04.864333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:57:04.867911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:57:04.871184 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:57:04.878607 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:57:04.882354 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:57:04.886017 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:57:04.893748 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:57:04.897197 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:57:04.904177 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:57:04.908144 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:57:04.912067 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:57:04.915898 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:57:04.922681 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:57:04.926638 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:57:04.930456 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:57:04.933800 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:57:04.937917 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:57:04.945293 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:57:04.948695 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:57:04.952639 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:57:04.956107 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:57:04.960393 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:57:04.963207 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:57:04.967093 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:57:04.978649 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:57:04.985861 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:57:04.989802 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:57:04.996708 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:57:05.007466 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:57:05.011503 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:57:05.014845 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:57:05.018269 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:57:05.027351 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 22:57:05.033866 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:57:05.037926 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 22:57:05.041270 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:57:05.051428 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 22:57:05.061298 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 22:57:05.070007 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 22:57:05.080054 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 22:57:05.088913 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 22:57:05.098824 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 22:57:05.108429 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 22:57:05.111772 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 22:57:05.119075 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 22:57:05.123449 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:57:05.126520 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 22:57:05.130441 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:57:05.134044 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 22:57:05.137098 ADC[4]: Raw value=905465 ID=7
551 22:57:05.141063 ADC[3]: Raw value=213441 ID=1
552 22:57:05.141149 RAM Code: 0x71
553 22:57:05.144908 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:57:05.152090 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:57:05.159491 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 22:57:05.167239 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 22:57:05.171205 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:57:05.175198 in-header: 03 07 00 00 08 00 00 00
559 22:57:05.175282 in-data: aa e4 47 04 13 02 00 00
560 22:57:05.178504 Chrome EC: UHEPI supported
561 22:57:05.185653 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:57:05.189472 in-header: 03 95 00 00 08 00 00 00
563 22:57:05.193176 in-data: 18 20 20 08 00 00 00 00
564 22:57:05.196494 MRC: failed to locate region type 0.
565 22:57:05.200327 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:57:05.204308 DRAM-K: Running full calibration
567 22:57:05.212094 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 22:57:05.212179 header.status = 0x0
569 22:57:05.215387 header.version = 0x6 (expected: 0x6)
570 22:57:05.219435 header.size = 0xd00 (expected: 0xd00)
571 22:57:05.222927 header.flags = 0x0
572 22:57:05.226296 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:57:05.245799 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 22:57:05.252763 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:57:05.256811 dram_init: ddr_geometry: 2
576 22:57:05.256899 [EMI] MDL number = 2
577 22:57:05.261144 [EMI] Get MDL freq = 0
578 22:57:05.261230 dram_init: ddr_type: 0
579 22:57:05.264997 is_discrete_lpddr4: 1
580 22:57:05.265081 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:57:05.265149
582 22:57:05.265212
583 22:57:05.268995 [Bian_co] ETT version 0.0.0.1
584 22:57:05.272810 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 22:57:05.272896
586 22:57:05.279447 dramc_set_vcore_voltage set vcore to 650000
587 22:57:05.279535 Read voltage for 800, 4
588 22:57:05.279616 Vio18 = 0
589 22:57:05.283190 Vcore = 650000
590 22:57:05.283274 Vdram = 0
591 22:57:05.283342 Vddq = 0
592 22:57:05.286583 Vmddr = 0
593 22:57:05.286668 dram_init: config_dvfs: 1
594 22:57:05.293983 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:57:05.297872 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:57:05.301490 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 22:57:05.305422 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 22:57:05.308699 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 22:57:05.312032 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 22:57:05.315452 MEM_TYPE=3, freq_sel=18
601 22:57:05.318681 sv_algorithm_assistance_LP4_1600
602 22:57:05.322000 ============ PULL DRAM RESETB DOWN ============
603 22:57:05.325280 ========== PULL DRAM RESETB DOWN end =========
604 22:57:05.332577 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:57:05.336519 ===================================
606 22:57:05.336631 LPDDR4 DRAM CONFIGURATION
607 22:57:05.340187 ===================================
608 22:57:05.343654 EX_ROW_EN[0] = 0x0
609 22:57:05.343739 EX_ROW_EN[1] = 0x0
610 22:57:05.347516 LP4Y_EN = 0x0
611 22:57:05.347601 WORK_FSP = 0x0
612 22:57:05.347668 WL = 0x2
613 22:57:05.350757 RL = 0x2
614 22:57:05.350841 BL = 0x2
615 22:57:05.354726 RPST = 0x0
616 22:57:05.354809 RD_PRE = 0x0
617 22:57:05.357921 WR_PRE = 0x1
618 22:57:05.361068 WR_PST = 0x0
619 22:57:05.361153 DBI_WR = 0x0
620 22:57:05.364295 DBI_RD = 0x0
621 22:57:05.364380 OTF = 0x1
622 22:57:05.368448 ===================================
623 22:57:05.371780 ===================================
624 22:57:05.371865 ANA top config
625 22:57:05.375336 ===================================
626 22:57:05.378689 DLL_ASYNC_EN = 0
627 22:57:05.382097 ALL_SLAVE_EN = 1
628 22:57:05.382181 NEW_RANK_MODE = 1
629 22:57:05.385681 DLL_IDLE_MODE = 1
630 22:57:05.388867 LP45_APHY_COMB_EN = 1
631 22:57:05.392296 TX_ODT_DIS = 1
632 22:57:05.395424 NEW_8X_MODE = 1
633 22:57:05.395537 ===================================
634 22:57:05.399264 ===================================
635 22:57:05.402966 data_rate = 1600
636 22:57:05.405921 CKR = 1
637 22:57:05.409185 DQ_P2S_RATIO = 8
638 22:57:05.412608 ===================================
639 22:57:05.415825 CA_P2S_RATIO = 8
640 22:57:05.419261 DQ_CA_OPEN = 0
641 22:57:05.419346 DQ_SEMI_OPEN = 0
642 22:57:05.422647 CA_SEMI_OPEN = 0
643 22:57:05.425740 CA_FULL_RATE = 0
644 22:57:05.429116 DQ_CKDIV4_EN = 1
645 22:57:05.433103 CA_CKDIV4_EN = 1
646 22:57:05.433188 CA_PREDIV_EN = 0
647 22:57:05.436292 PH8_DLY = 0
648 22:57:05.439858 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:57:05.443025 DQ_AAMCK_DIV = 4
650 22:57:05.445932 CA_AAMCK_DIV = 4
651 22:57:05.449460 CA_ADMCK_DIV = 4
652 22:57:05.449545 DQ_TRACK_CA_EN = 0
653 22:57:05.452632 CA_PICK = 800
654 22:57:05.456155 CA_MCKIO = 800
655 22:57:05.459892 MCKIO_SEMI = 0
656 22:57:05.463900 PLL_FREQ = 3068
657 22:57:05.467803 DQ_UI_PI_RATIO = 32
658 22:57:05.467888 CA_UI_PI_RATIO = 0
659 22:57:05.471173 ===================================
660 22:57:05.474604 ===================================
661 22:57:05.478617 memory_type:LPDDR4
662 22:57:05.478855 GP_NUM : 10
663 22:57:05.482204 SRAM_EN : 1
664 22:57:05.482351 MD32_EN : 0
665 22:57:05.486186 ===================================
666 22:57:05.489762 [ANA_INIT] >>>>>>>>>>>>>>
667 22:57:05.493317 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:57:05.497014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:57:05.497181 ===================================
670 22:57:05.500404 data_rate = 1600,PCW = 0X7600
671 22:57:05.503803 ===================================
672 22:57:05.506817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:57:05.513862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:57:05.520275 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:57:05.523571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:57:05.526960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:57:05.530520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:57:05.533876 [ANA_INIT] flow start
679 22:57:05.534029 [ANA_INIT] PLL >>>>>>>>
680 22:57:05.537128 [ANA_INIT] PLL <<<<<<<<
681 22:57:05.540361 [ANA_INIT] MIDPI >>>>>>>>
682 22:57:05.540502 [ANA_INIT] MIDPI <<<<<<<<
683 22:57:05.543580 [ANA_INIT] DLL >>>>>>>>
684 22:57:05.547103 [ANA_INIT] flow end
685 22:57:05.550242 ============ LP4 DIFF to SE enter ============
686 22:57:05.553552 ============ LP4 DIFF to SE exit ============
687 22:57:05.556846 [ANA_INIT] <<<<<<<<<<<<<
688 22:57:05.560537 [Flow] Enable top DCM control >>>>>
689 22:57:05.563602 [Flow] Enable top DCM control <<<<<
690 22:57:05.567071 Enable DLL master slave shuffle
691 22:57:05.570354 ==============================================================
692 22:57:05.573719 Gating Mode config
693 22:57:05.580208 ==============================================================
694 22:57:05.580351 Config description:
695 22:57:05.590461 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:57:05.597633 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:57:05.600782 SELPH_MODE 0: By rank 1: By Phase
698 22:57:05.607147 ==============================================================
699 22:57:05.610544 GAT_TRACK_EN = 1
700 22:57:05.613948 RX_GATING_MODE = 2
701 22:57:05.616963 RX_GATING_TRACK_MODE = 2
702 22:57:05.620510 SELPH_MODE = 1
703 22:57:05.623577 PICG_EARLY_EN = 1
704 22:57:05.623718 VALID_LAT_VALUE = 1
705 22:57:05.630253 ==============================================================
706 22:57:05.633692 Enter into Gating configuration >>>>
707 22:57:05.636855 Exit from Gating configuration <<<<
708 22:57:05.640696 Enter into DVFS_PRE_config >>>>>
709 22:57:05.650367 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:57:05.653531 Exit from DVFS_PRE_config <<<<<
711 22:57:05.656909 Enter into PICG configuration >>>>
712 22:57:05.660592 Exit from PICG configuration <<<<
713 22:57:05.663724 [RX_INPUT] configuration >>>>>
714 22:57:05.666867 [RX_INPUT] configuration <<<<<
715 22:57:05.670253 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:57:05.677224 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:57:05.683782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:57:05.690302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:57:05.696827 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:57:05.703917 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:57:05.707268 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:57:05.710755 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:57:05.713857 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:57:05.717201 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:57:05.724270 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:57:05.727555 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:57:05.730631 ===================================
728 22:57:05.733852 LPDDR4 DRAM CONFIGURATION
729 22:57:05.737313 ===================================
730 22:57:05.737398 EX_ROW_EN[0] = 0x0
731 22:57:05.740564 EX_ROW_EN[1] = 0x0
732 22:57:05.740648 LP4Y_EN = 0x0
733 22:57:05.743798 WORK_FSP = 0x0
734 22:57:05.743882 WL = 0x2
735 22:57:05.747129 RL = 0x2
736 22:57:05.747212 BL = 0x2
737 22:57:05.750448 RPST = 0x0
738 22:57:05.750532 RD_PRE = 0x0
739 22:57:05.754036 WR_PRE = 0x1
740 22:57:05.754121 WR_PST = 0x0
741 22:57:05.757327 DBI_WR = 0x0
742 22:57:05.757411 DBI_RD = 0x0
743 22:57:05.761085 OTF = 0x1
744 22:57:05.764225 ===================================
745 22:57:05.767586 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:57:05.771186 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:57:05.777497 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:57:05.780860 ===================================
749 22:57:05.780946 LPDDR4 DRAM CONFIGURATION
750 22:57:05.784605 ===================================
751 22:57:05.787470 EX_ROW_EN[0] = 0x10
752 22:57:05.791487 EX_ROW_EN[1] = 0x0
753 22:57:05.791571 LP4Y_EN = 0x0
754 22:57:05.794544 WORK_FSP = 0x0
755 22:57:05.794629 WL = 0x2
756 22:57:05.797974 RL = 0x2
757 22:57:05.798058 BL = 0x2
758 22:57:05.801166 RPST = 0x0
759 22:57:05.801251 RD_PRE = 0x0
760 22:57:05.804648 WR_PRE = 0x1
761 22:57:05.804732 WR_PST = 0x0
762 22:57:05.807845 DBI_WR = 0x0
763 22:57:05.807929 DBI_RD = 0x0
764 22:57:05.811280 OTF = 0x1
765 22:57:05.813988 ===================================
766 22:57:05.821001 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:57:05.824260 nWR fixed to 40
768 22:57:05.824347 [ModeRegInit_LP4] CH0 RK0
769 22:57:05.827557 [ModeRegInit_LP4] CH0 RK1
770 22:57:05.830638 [ModeRegInit_LP4] CH1 RK0
771 22:57:05.830724 [ModeRegInit_LP4] CH1 RK1
772 22:57:05.833971 match AC timing 13
773 22:57:05.837774 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 22:57:05.840960 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:57:05.847743 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:57:05.850950 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:57:05.857644 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:57:05.857743 [EMI DOE] emi_dcm 0
779 22:57:05.860945 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:57:05.864161 ==
781 22:57:05.867486 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:57:05.871033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 22:57:05.871136 ==
784 22:57:05.874423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:57:05.881194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:57:05.890714 [CA 0] Center 36 (6~67) winsize 62
787 22:57:05.893926 [CA 1] Center 36 (6~67) winsize 62
788 22:57:05.897412 [CA 2] Center 34 (4~65) winsize 62
789 22:57:05.901194 [CA 3] Center 34 (4~64) winsize 61
790 22:57:05.904348 [CA 4] Center 33 (3~64) winsize 62
791 22:57:05.907607 [CA 5] Center 32 (2~62) winsize 61
792 22:57:05.907693
793 22:57:05.910957 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 22:57:05.911044
795 22:57:05.914575 [CATrainingPosCal] consider 1 rank data
796 22:57:05.917805 u2DelayCellTimex100 = 270/100 ps
797 22:57:05.920657 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 22:57:05.924066 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 22:57:05.930776 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 22:57:05.934076 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 22:57:05.937309 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 22:57:05.941410 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 22:57:05.941496
804 22:57:05.944663 CA PerBit enable=1, Macro0, CA PI delay=32
805 22:57:05.944748
806 22:57:05.947935 [CBTSetCACLKResult] CA Dly = 32
807 22:57:05.948057 CS Dly: 4 (0~35)
808 22:57:05.948125 ==
809 22:57:05.951227 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:57:05.957709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:57:05.957830 ==
812 22:57:05.960981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:57:05.967235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:57:05.976781 [CA 0] Center 36 (6~67) winsize 62
815 22:57:05.980374 [CA 1] Center 36 (6~67) winsize 62
816 22:57:05.983573 [CA 2] Center 34 (4~65) winsize 62
817 22:57:05.987367 [CA 3] Center 34 (3~65) winsize 63
818 22:57:05.990554 [CA 4] Center 33 (3~64) winsize 62
819 22:57:05.993800 [CA 5] Center 32 (2~63) winsize 62
820 22:57:05.993897
821 22:57:05.996934 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 22:57:05.997020
823 22:57:06.000126 [CATrainingPosCal] consider 2 rank data
824 22:57:06.003319 u2DelayCellTimex100 = 270/100 ps
825 22:57:06.006823 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 22:57:06.010332 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 22:57:06.016983 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 22:57:06.020752 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 22:57:06.023923 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
830 22:57:06.026937 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 22:57:06.027023
832 22:57:06.030567 CA PerBit enable=1, Macro0, CA PI delay=32
833 22:57:06.030655
834 22:57:06.033731 [CBTSetCACLKResult] CA Dly = 32
835 22:57:06.033823 CS Dly: 5 (0~37)
836 22:57:06.033892
837 22:57:06.037192 ----->DramcWriteLeveling(PI) begin...
838 22:57:06.040643 ==
839 22:57:06.040730 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:57:06.048216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 22:57:06.048323 ==
842 22:57:06.048393 Write leveling (Byte 0): 33 => 33
843 22:57:06.052319 Write leveling (Byte 1): 31 => 31
844 22:57:06.055601 DramcWriteLeveling(PI) end<-----
845 22:57:06.055699
846 22:57:06.055767 ==
847 22:57:06.059075 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:57:06.062382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 22:57:06.062472 ==
850 22:57:06.065550 [Gating] SW mode calibration
851 22:57:06.071947 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:57:06.079237 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:57:06.082439 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:57:06.088671 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 22:57:06.092383 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 22:57:06.095598 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:57:06.099307 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:57:06.105480 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:57:06.108930 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:57:06.112842 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:57:06.118807 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:57:06.122225 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:57:06.125495 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:57:06.132500 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:57:06.135729 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:57:06.138819 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:57:06.145693 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:57:06.149021 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:57:06.152325 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 22:57:06.159141 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
871 22:57:06.162523 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 22:57:06.165769 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
873 22:57:06.172225 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:57:06.175971 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:57:06.179367 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:57:06.185581 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:57:06.188887 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:57:06.192087 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:57:06.195751 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
880 22:57:06.202488 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 22:57:06.206120 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:57:06.209141 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:57:06.215687 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:57:06.219082 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:57:06.222462 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 22:57:06.229125 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
887 22:57:06.232763 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (1 1) (0 0)
888 22:57:06.235935 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
889 22:57:06.242460 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:57:06.246326 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:57:06.249492 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:57:06.256081 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:57:06.259324 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 22:57:06.262416 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 22:57:06.266010 0 11 8 | B1->B0 | 2d2d 3b3b | 0 0 | (0 0) (0 0)
896 22:57:06.272785 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
897 22:57:06.276084 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:57:06.279430 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:57:06.285690 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:57:06.289875 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:57:06.292924 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 22:57:06.299063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 22:57:06.302520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 22:57:06.305725 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:57:06.312340 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:57:06.316173 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:57:06.318963 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:57:06.326022 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:57:06.329389 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:57:06.332734 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:57:06.339124 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:57:06.343002 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:57:06.345996 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:57:06.352379 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:57:06.355628 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:57:06.359049 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:57:06.362332 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:57:06.369506 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 22:57:06.372909 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 22:57:06.376167 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 22:57:06.379276 Total UI for P1: 0, mck2ui 16
922 22:57:06.382717 best dqsien dly found for B0: ( 0, 14, 6)
923 22:57:06.386028 Total UI for P1: 0, mck2ui 16
924 22:57:06.389324 best dqsien dly found for B1: ( 0, 14, 10)
925 22:57:06.393019 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 22:57:06.396441 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 22:57:06.396525
928 22:57:06.400553 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 22:57:06.406493 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 22:57:06.406578 [Gating] SW calibration Done
931 22:57:06.406645 ==
932 22:57:06.410611 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:57:06.416971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:57:06.417055 ==
935 22:57:06.417122 RX Vref Scan: 0
936 22:57:06.417184
937 22:57:06.420450 RX Vref 0 -> 0, step: 1
938 22:57:06.420534
939 22:57:06.423570 RX Delay -130 -> 252, step: 16
940 22:57:06.427189 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 22:57:06.430402 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 22:57:06.433905 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 22:57:06.437053 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 22:57:06.443882 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 22:57:06.446845 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 22:57:06.450228 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 22:57:06.453424 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 22:57:06.457351 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
949 22:57:06.463791 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
950 22:57:06.466672 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 22:57:06.469954 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 22:57:06.473247 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 22:57:06.476617 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 22:57:06.483587 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 22:57:06.486707 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 22:57:06.486797 ==
957 22:57:06.490129 Dram Type= 6, Freq= 0, CH_0, rank 0
958 22:57:06.493384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 22:57:06.493468 ==
960 22:57:06.497122 DQS Delay:
961 22:57:06.497207 DQS0 = 0, DQS1 = 0
962 22:57:06.497327 DQM Delay:
963 22:57:06.500221 DQM0 = 89, DQM1 = 81
964 22:57:06.500305 DQ Delay:
965 22:57:06.503643 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 22:57:06.506905 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 22:57:06.510345 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
968 22:57:06.513632 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
969 22:57:06.513743
970 22:57:06.513839
971 22:57:06.513930 ==
972 22:57:06.516961 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:57:06.523348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:57:06.523434 ==
975 22:57:06.523538
976 22:57:06.523637
977 22:57:06.523729 TX Vref Scan disable
978 22:57:06.527093 == TX Byte 0 ==
979 22:57:06.530752 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 22:57:06.533724 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 22:57:06.537059 == TX Byte 1 ==
982 22:57:06.540435 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 22:57:06.543598 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 22:57:06.547137 ==
985 22:57:06.550242 Dram Type= 6, Freq= 0, CH_0, rank 0
986 22:57:06.553694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 22:57:06.553793 ==
988 22:57:06.566333 TX Vref=22, minBit 10, minWin=27, winSum=449
989 22:57:06.569404 TX Vref=24, minBit 8, minWin=27, winSum=448
990 22:57:06.572948 TX Vref=26, minBit 4, minWin=28, winSum=454
991 22:57:06.576506 TX Vref=28, minBit 8, minWin=28, winSum=459
992 22:57:06.579467 TX Vref=30, minBit 8, minWin=28, winSum=461
993 22:57:06.582869 TX Vref=32, minBit 5, minWin=28, winSum=456
994 22:57:06.589383 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
995 22:57:06.589469
996 22:57:06.593059 Final TX Range 1 Vref 30
997 22:57:06.593147
998 22:57:06.593213 ==
999 22:57:06.596386 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 22:57:06.599536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 22:57:06.599622 ==
1002 22:57:06.599688
1003 22:57:06.599751
1004 22:57:06.603449 TX Vref Scan disable
1005 22:57:06.606846 == TX Byte 0 ==
1006 22:57:06.610199 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 22:57:06.613417 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 22:57:06.616588 == TX Byte 1 ==
1009 22:57:06.620013 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 22:57:06.622999 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 22:57:06.623087
1012 22:57:06.626327 [DATLAT]
1013 22:57:06.626411 Freq=800, CH0 RK0
1014 22:57:06.626479
1015 22:57:06.629551 DATLAT Default: 0xa
1016 22:57:06.629636 0, 0xFFFF, sum = 0
1017 22:57:06.632928 1, 0xFFFF, sum = 0
1018 22:57:06.633015 2, 0xFFFF, sum = 0
1019 22:57:06.636252 3, 0xFFFF, sum = 0
1020 22:57:06.636338 4, 0xFFFF, sum = 0
1021 22:57:06.639617 5, 0xFFFF, sum = 0
1022 22:57:06.639706 6, 0xFFFF, sum = 0
1023 22:57:06.642847 7, 0xFFFF, sum = 0
1024 22:57:06.642937 8, 0xFFFF, sum = 0
1025 22:57:06.646899 9, 0x0, sum = 1
1026 22:57:06.646991 10, 0x0, sum = 2
1027 22:57:06.649988 11, 0x0, sum = 3
1028 22:57:06.650072 12, 0x0, sum = 4
1029 22:57:06.653022 best_step = 10
1030 22:57:06.653105
1031 22:57:06.653171 ==
1032 22:57:06.656244 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 22:57:06.659475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 22:57:06.659560 ==
1035 22:57:06.663317 RX Vref Scan: 1
1036 22:57:06.663400
1037 22:57:06.663466 Set Vref Range= 32 -> 127
1038 22:57:06.663528
1039 22:57:06.666500 RX Vref 32 -> 127, step: 1
1040 22:57:06.666582
1041 22:57:06.669949 RX Delay -79 -> 252, step: 8
1042 22:57:06.670032
1043 22:57:06.672859 Set Vref, RX VrefLevel [Byte0]: 32
1044 22:57:06.676509 [Byte1]: 32
1045 22:57:06.676592
1046 22:57:06.679936 Set Vref, RX VrefLevel [Byte0]: 33
1047 22:57:06.683182 [Byte1]: 33
1048 22:57:06.686522
1049 22:57:06.686605 Set Vref, RX VrefLevel [Byte0]: 34
1050 22:57:06.689788 [Byte1]: 34
1051 22:57:06.694096
1052 22:57:06.694185 Set Vref, RX VrefLevel [Byte0]: 35
1053 22:57:06.697443 [Byte1]: 35
1054 22:57:06.702080
1055 22:57:06.702196 Set Vref, RX VrefLevel [Byte0]: 36
1056 22:57:06.705054 [Byte1]: 36
1057 22:57:06.709954
1058 22:57:06.710075 Set Vref, RX VrefLevel [Byte0]: 37
1059 22:57:06.712595 [Byte1]: 37
1060 22:57:06.716869
1061 22:57:06.720138 Set Vref, RX VrefLevel [Byte0]: 38
1062 22:57:06.720262 [Byte1]: 38
1063 22:57:06.724866
1064 22:57:06.724958 Set Vref, RX VrefLevel [Byte0]: 39
1065 22:57:06.727558 [Byte1]: 39
1066 22:57:06.732285
1067 22:57:06.732372 Set Vref, RX VrefLevel [Byte0]: 40
1068 22:57:06.735661 [Byte1]: 40
1069 22:57:06.739756
1070 22:57:06.739863 Set Vref, RX VrefLevel [Byte0]: 41
1071 22:57:06.742430 [Byte1]: 41
1072 22:57:06.746785
1073 22:57:06.746870 Set Vref, RX VrefLevel [Byte0]: 42
1074 22:57:06.750312 [Byte1]: 42
1075 22:57:06.754167
1076 22:57:06.754276 Set Vref, RX VrefLevel [Byte0]: 43
1077 22:57:06.757438 [Byte1]: 43
1078 22:57:06.762196
1079 22:57:06.762282 Set Vref, RX VrefLevel [Byte0]: 44
1080 22:57:06.765137 [Byte1]: 44
1081 22:57:06.769329
1082 22:57:06.769413 Set Vref, RX VrefLevel [Byte0]: 45
1083 22:57:06.773093 [Byte1]: 45
1084 22:57:06.777090
1085 22:57:06.777175 Set Vref, RX VrefLevel [Byte0]: 46
1086 22:57:06.780988 [Byte1]: 46
1087 22:57:06.785045
1088 22:57:06.785130 Set Vref, RX VrefLevel [Byte0]: 47
1089 22:57:06.787902 [Byte1]: 47
1090 22:57:06.792082
1091 22:57:06.792163 Set Vref, RX VrefLevel [Byte0]: 48
1092 22:57:06.795256 [Byte1]: 48
1093 22:57:06.800051
1094 22:57:06.800133 Set Vref, RX VrefLevel [Byte0]: 49
1095 22:57:06.803329 [Byte1]: 49
1096 22:57:06.807264
1097 22:57:06.807347 Set Vref, RX VrefLevel [Byte0]: 50
1098 22:57:06.810540 [Byte1]: 50
1099 22:57:06.814886
1100 22:57:06.814968 Set Vref, RX VrefLevel [Byte0]: 51
1101 22:57:06.818126 [Byte1]: 51
1102 22:57:06.822110
1103 22:57:06.822218 Set Vref, RX VrefLevel [Byte0]: 52
1104 22:57:06.825452 [Byte1]: 52
1105 22:57:06.829919
1106 22:57:06.830000 Set Vref, RX VrefLevel [Byte0]: 53
1107 22:57:06.833286 [Byte1]: 53
1108 22:57:06.837224
1109 22:57:06.837306 Set Vref, RX VrefLevel [Byte0]: 54
1110 22:57:06.840978 [Byte1]: 54
1111 22:57:06.845548
1112 22:57:06.845636 Set Vref, RX VrefLevel [Byte0]: 55
1113 22:57:06.848261 [Byte1]: 55
1114 22:57:06.852317
1115 22:57:06.852409 Set Vref, RX VrefLevel [Byte0]: 56
1116 22:57:06.855603 [Byte1]: 56
1117 22:57:06.860217
1118 22:57:06.860305 Set Vref, RX VrefLevel [Byte0]: 57
1119 22:57:06.863160 [Byte1]: 57
1120 22:57:06.867433
1121 22:57:06.867524 Set Vref, RX VrefLevel [Byte0]: 58
1122 22:57:06.871097 [Byte1]: 58
1123 22:57:06.874913
1124 22:57:06.875000 Set Vref, RX VrefLevel [Byte0]: 59
1125 22:57:06.878350 [Byte1]: 59
1126 22:57:06.882976
1127 22:57:06.883062 Set Vref, RX VrefLevel [Byte0]: 60
1128 22:57:06.886099 [Byte1]: 60
1129 22:57:06.890592
1130 22:57:06.890675 Set Vref, RX VrefLevel [Byte0]: 61
1131 22:57:06.893548 [Byte1]: 61
1132 22:57:06.898271
1133 22:57:06.898356 Set Vref, RX VrefLevel [Byte0]: 62
1134 22:57:06.901510 [Byte1]: 62
1135 22:57:06.905412
1136 22:57:06.905495 Set Vref, RX VrefLevel [Byte0]: 63
1137 22:57:06.908802 [Byte1]: 63
1138 22:57:06.912705
1139 22:57:06.912789 Set Vref, RX VrefLevel [Byte0]: 64
1140 22:57:06.916695 [Byte1]: 64
1141 22:57:06.920546
1142 22:57:06.920634 Set Vref, RX VrefLevel [Byte0]: 65
1143 22:57:06.923677 [Byte1]: 65
1144 22:57:06.927854
1145 22:57:06.927968 Set Vref, RX VrefLevel [Byte0]: 66
1146 22:57:06.931232 [Byte1]: 66
1147 22:57:06.935731
1148 22:57:06.935818 Set Vref, RX VrefLevel [Byte0]: 67
1149 22:57:06.938833 [Byte1]: 67
1150 22:57:06.943025
1151 22:57:06.943110 Set Vref, RX VrefLevel [Byte0]: 68
1152 22:57:06.946607 [Byte1]: 68
1153 22:57:06.950843
1154 22:57:06.950928 Set Vref, RX VrefLevel [Byte0]: 69
1155 22:57:06.953775 [Byte1]: 69
1156 22:57:06.958351
1157 22:57:06.958434 Set Vref, RX VrefLevel [Byte0]: 70
1158 22:57:06.961563 [Byte1]: 70
1159 22:57:06.965931
1160 22:57:06.966015 Set Vref, RX VrefLevel [Byte0]: 71
1161 22:57:06.969036 [Byte1]: 71
1162 22:57:06.973161
1163 22:57:06.973245 Set Vref, RX VrefLevel [Byte0]: 72
1164 22:57:06.976910 [Byte1]: 72
1165 22:57:06.980750
1166 22:57:06.980833 Set Vref, RX VrefLevel [Byte0]: 73
1167 22:57:06.984048 [Byte1]: 73
1168 22:57:06.988529
1169 22:57:06.988611 Set Vref, RX VrefLevel [Byte0]: 74
1170 22:57:06.991928 [Byte1]: 74
1171 22:57:06.996153
1172 22:57:06.996236 Set Vref, RX VrefLevel [Byte0]: 75
1173 22:57:06.999222 [Byte1]: 75
1174 22:57:07.003563
1175 22:57:07.003646 Set Vref, RX VrefLevel [Byte0]: 76
1176 22:57:07.006919 [Byte1]: 76
1177 22:57:07.011519
1178 22:57:07.011601 Set Vref, RX VrefLevel [Byte0]: 77
1179 22:57:07.014071 [Byte1]: 77
1180 22:57:07.018763
1181 22:57:07.018845 Final RX Vref Byte 0 = 60 to rank0
1182 22:57:07.021851 Final RX Vref Byte 1 = 62 to rank0
1183 22:57:07.025603 Final RX Vref Byte 0 = 60 to rank1
1184 22:57:07.028984 Final RX Vref Byte 1 = 62 to rank1==
1185 22:57:07.032292 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 22:57:07.038847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 22:57:07.038930 ==
1188 22:57:07.038996 DQS Delay:
1189 22:57:07.039058 DQS0 = 0, DQS1 = 0
1190 22:57:07.042369 DQM Delay:
1191 22:57:07.042451 DQM0 = 92, DQM1 = 84
1192 22:57:07.045460 DQ Delay:
1193 22:57:07.048724 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1194 22:57:07.048810 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1195 22:57:07.052248 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1196 22:57:07.055175 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1197 22:57:07.058487
1198 22:57:07.058597
1199 22:57:07.065697 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1200 22:57:07.068632 CH0 RK0: MR19=606, MR18=4C42
1201 22:57:07.075656 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1202 22:57:07.075739
1203 22:57:07.078965 ----->DramcWriteLeveling(PI) begin...
1204 22:57:07.079048 ==
1205 22:57:07.082095 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 22:57:07.085827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 22:57:07.085910 ==
1208 22:57:07.088690 Write leveling (Byte 0): 33 => 33
1209 22:57:07.092359 Write leveling (Byte 1): 30 => 30
1210 22:57:07.095459 DramcWriteLeveling(PI) end<-----
1211 22:57:07.095542
1212 22:57:07.095607 ==
1213 22:57:07.098656 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 22:57:07.102404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 22:57:07.102521 ==
1216 22:57:07.105944 [Gating] SW mode calibration
1217 22:57:07.153050 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 22:57:07.153410 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 22:57:07.153487 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 22:57:07.153553 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 22:57:07.153616 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1222 22:57:07.153675 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:57:07.154108 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:57:07.154727 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:57:07.154804 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:57:07.155663 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:57:07.169011 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:57:07.169300 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:57:07.172267 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:57:07.172352 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:57:07.175682 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:57:07.179404 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:57:07.182577 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 22:57:07.189150 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:57:07.192320 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:57:07.195944 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1237 22:57:07.202355 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1238 22:57:07.205508 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:57:07.208701 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:57:07.215618 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:57:07.219161 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:57:07.222285 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 22:57:07.228837 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 22:57:07.232486 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 22:57:07.235114 0 9 8 | B1->B0 | 2f2f 2929 | 1 0 | (1 1) (1 1)
1246 22:57:07.241895 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 22:57:07.245399 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 22:57:07.248643 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 22:57:07.255924 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 22:57:07.259218 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 22:57:07.261800 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 22:57:07.268982 0 10 4 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 1)
1253 22:57:07.271869 0 10 8 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
1254 22:57:07.275367 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 22:57:07.278607 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 22:57:07.286565 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 22:57:07.289840 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 22:57:07.293218 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 22:57:07.296803 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 22:57:07.303562 0 11 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1261 22:57:07.307198 0 11 8 | B1->B0 | 3939 3939 | 1 0 | (0 0) (0 0)
1262 22:57:07.310931 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 22:57:07.314225 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 22:57:07.321416 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 22:57:07.324324 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 22:57:07.327727 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 22:57:07.334513 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 22:57:07.337861 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 22:57:07.340862 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 22:57:07.347793 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 22:57:07.350790 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 22:57:07.354507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 22:57:07.360936 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 22:57:07.364151 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 22:57:07.367810 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 22:57:07.374490 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 22:57:07.377312 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 22:57:07.381011 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 22:57:07.383931 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 22:57:07.390602 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 22:57:07.394363 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 22:57:07.397420 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 22:57:07.404162 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 22:57:07.407738 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 22:57:07.410755 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1286 22:57:07.417442 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1287 22:57:07.421040 Total UI for P1: 0, mck2ui 16
1288 22:57:07.424301 best dqsien dly found for B0: ( 0, 14, 8)
1289 22:57:07.427843 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 22:57:07.430697 Total UI for P1: 0, mck2ui 16
1291 22:57:07.434033 best dqsien dly found for B1: ( 0, 14, 10)
1292 22:57:07.437951 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1293 22:57:07.441289 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1294 22:57:07.441371
1295 22:57:07.444414 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 22:57:07.447610 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1297 22:57:07.451527 [Gating] SW calibration Done
1298 22:57:07.451609 ==
1299 22:57:07.454306 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 22:57:07.458162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 22:57:07.458245 ==
1302 22:57:07.460786 RX Vref Scan: 0
1303 22:57:07.460867
1304 22:57:07.464796 RX Vref 0 -> 0, step: 1
1305 22:57:07.464878
1306 22:57:07.464943 RX Delay -130 -> 252, step: 16
1307 22:57:07.471292 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1308 22:57:07.474418 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1309 22:57:07.478001 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1310 22:57:07.481485 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1311 22:57:07.484461 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1312 22:57:07.491611 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1313 22:57:07.494543 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1314 22:57:07.498054 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1315 22:57:07.501283 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1316 22:57:07.504287 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1317 22:57:07.511095 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1318 22:57:07.514144 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1319 22:57:07.517503 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1320 22:57:07.521455 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1321 22:57:07.524563 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1322 22:57:07.531136 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1323 22:57:07.531218 ==
1324 22:57:07.534656 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 22:57:07.537869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 22:57:07.537951 ==
1327 22:57:07.538017 DQS Delay:
1328 22:57:07.541169 DQS0 = 0, DQS1 = 0
1329 22:57:07.541255 DQM Delay:
1330 22:57:07.544577 DQM0 = 93, DQM1 = 82
1331 22:57:07.544659 DQ Delay:
1332 22:57:07.547589 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1333 22:57:07.550990 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =109
1334 22:57:07.554716 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1335 22:57:07.557875 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1336 22:57:07.557957
1337 22:57:07.558023
1338 22:57:07.558085 ==
1339 22:57:07.561166 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 22:57:07.564566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 22:57:07.564672 ==
1342 22:57:07.564739
1343 22:57:07.567929
1344 22:57:07.568052 TX Vref Scan disable
1345 22:57:07.571249 == TX Byte 0 ==
1346 22:57:07.574565 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1347 22:57:07.577755 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1348 22:57:07.581548 == TX Byte 1 ==
1349 22:57:07.584657 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1350 22:57:07.587720 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1351 22:57:07.587801 ==
1352 22:57:07.591137 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 22:57:07.597478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 22:57:07.597561 ==
1355 22:57:07.610260 TX Vref=22, minBit 8, minWin=27, winSum=448
1356 22:57:07.613316 TX Vref=24, minBit 1, minWin=28, winSum=455
1357 22:57:07.616390 TX Vref=26, minBit 8, minWin=28, winSum=458
1358 22:57:07.619843 TX Vref=28, minBit 1, minWin=28, winSum=455
1359 22:57:07.623167 TX Vref=30, minBit 7, minWin=28, winSum=456
1360 22:57:07.626572 TX Vref=32, minBit 2, minWin=28, winSum=453
1361 22:57:07.633706 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 26
1362 22:57:07.633788
1363 22:57:07.636600 Final TX Range 1 Vref 26
1364 22:57:07.636682
1365 22:57:07.636746 ==
1366 22:57:07.640254 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 22:57:07.643586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 22:57:07.643689 ==
1369 22:57:07.643770
1370 22:57:07.643832
1371 22:57:07.646932 TX Vref Scan disable
1372 22:57:07.650043 == TX Byte 0 ==
1373 22:57:07.653294 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1374 22:57:07.656560 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1375 22:57:07.660077 == TX Byte 1 ==
1376 22:57:07.663423 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1377 22:57:07.666952 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1378 22:57:07.667035
1379 22:57:07.670215 [DATLAT]
1380 22:57:07.670297 Freq=800, CH0 RK1
1381 22:57:07.670363
1382 22:57:07.673618 DATLAT Default: 0xa
1383 22:57:07.673701 0, 0xFFFF, sum = 0
1384 22:57:07.676856 1, 0xFFFF, sum = 0
1385 22:57:07.676940 2, 0xFFFF, sum = 0
1386 22:57:07.680211 3, 0xFFFF, sum = 0
1387 22:57:07.680296 4, 0xFFFF, sum = 0
1388 22:57:07.683314 5, 0xFFFF, sum = 0
1389 22:57:07.683398 6, 0xFFFF, sum = 0
1390 22:57:07.686978 7, 0xFFFF, sum = 0
1391 22:57:07.687062 8, 0xFFFF, sum = 0
1392 22:57:07.690296 9, 0x0, sum = 1
1393 22:57:07.690380 10, 0x0, sum = 2
1394 22:57:07.693652 11, 0x0, sum = 3
1395 22:57:07.693739 12, 0x0, sum = 4
1396 22:57:07.696854 best_step = 10
1397 22:57:07.696936
1398 22:57:07.697002 ==
1399 22:57:07.700236 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 22:57:07.703620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 22:57:07.703703 ==
1402 22:57:07.706516 RX Vref Scan: 0
1403 22:57:07.706599
1404 22:57:07.706667 RX Vref 0 -> 0, step: 1
1405 22:57:07.706728
1406 22:57:07.710150 RX Delay -79 -> 252, step: 8
1407 22:57:07.716962 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1408 22:57:07.720367 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1409 22:57:07.723485 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1410 22:57:07.726856 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1411 22:57:07.730439 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1412 22:57:07.733558 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1413 22:57:07.740459 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1414 22:57:07.743784 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1415 22:57:07.747126 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1416 22:57:07.750451 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1417 22:57:07.753659 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1418 22:57:07.760448 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1419 22:57:07.763932 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1420 22:57:07.767284 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1421 22:57:07.770159 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1422 22:57:07.773639 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1423 22:57:07.777026 ==
1424 22:57:07.777108 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 22:57:07.784407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 22:57:07.784490 ==
1427 22:57:07.784557 DQS Delay:
1428 22:57:07.787656 DQS0 = 0, DQS1 = 0
1429 22:57:07.787739 DQM Delay:
1430 22:57:07.790463 DQM0 = 92, DQM1 = 83
1431 22:57:07.790546 DQ Delay:
1432 22:57:07.793647 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1433 22:57:07.797592 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1434 22:57:07.800965 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1435 22:57:07.804334 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1436 22:57:07.804418
1437 22:57:07.804484
1438 22:57:07.810914 [DQSOSCAuto] RK1, (LSB)MR18= 0x4213, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1439 22:57:07.814045 CH0 RK1: MR19=606, MR18=4213
1440 22:57:07.820980 CH0_RK1: MR19=0x606, MR18=0x4213, DQSOSC=393, MR23=63, INC=95, DEC=63
1441 22:57:07.824130 [RxdqsGatingPostProcess] freq 800
1442 22:57:07.827444 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 22:57:07.831164 Pre-setting of DQS Precalculation
1444 22:57:07.837519 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 22:57:07.837606 ==
1446 22:57:07.840950 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 22:57:07.844178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 22:57:07.844262 ==
1449 22:57:07.851179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 22:57:07.856951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 22:57:07.864732 [CA 0] Center 36 (6~67) winsize 62
1452 22:57:07.868111 [CA 1] Center 37 (6~68) winsize 63
1453 22:57:07.871995 [CA 2] Center 35 (4~66) winsize 63
1454 22:57:07.874763 [CA 3] Center 34 (4~65) winsize 62
1455 22:57:07.878381 [CA 4] Center 35 (5~65) winsize 61
1456 22:57:07.881829 [CA 5] Center 34 (4~65) winsize 62
1457 22:57:07.881912
1458 22:57:07.884998 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1459 22:57:07.885082
1460 22:57:07.888447 [CATrainingPosCal] consider 1 rank data
1461 22:57:07.891566 u2DelayCellTimex100 = 270/100 ps
1462 22:57:07.895224 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 22:57:07.898615 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1464 22:57:07.901930 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1465 22:57:07.908778 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 22:57:07.912098 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1467 22:57:07.915456 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 22:57:07.915539
1469 22:57:07.918643 CA PerBit enable=1, Macro0, CA PI delay=34
1470 22:57:07.918753
1471 22:57:07.921864 [CBTSetCACLKResult] CA Dly = 34
1472 22:57:07.921951 CS Dly: 5 (0~36)
1473 22:57:07.922018 ==
1474 22:57:07.925438 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 22:57:07.931927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 22:57:07.932018 ==
1477 22:57:07.935267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 22:57:07.941755 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 22:57:07.951371 [CA 0] Center 36 (6~67) winsize 62
1480 22:57:07.955811 [CA 1] Center 37 (6~68) winsize 63
1481 22:57:07.959272 [CA 2] Center 35 (5~66) winsize 62
1482 22:57:07.962909 [CA 3] Center 34 (4~65) winsize 62
1483 22:57:07.966557 [CA 4] Center 35 (5~66) winsize 62
1484 22:57:07.966640 [CA 5] Center 34 (4~65) winsize 62
1485 22:57:07.966707
1486 22:57:07.970226 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1487 22:57:07.970309
1488 22:57:07.974669 [CATrainingPosCal] consider 2 rank data
1489 22:57:07.978007 u2DelayCellTimex100 = 270/100 ps
1490 22:57:07.981856 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 22:57:07.985151 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1492 22:57:07.988563 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1493 22:57:07.991790 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 22:57:07.995282 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1495 22:57:08.002352 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 22:57:08.002435
1497 22:57:08.004987 CA PerBit enable=1, Macro0, CA PI delay=34
1498 22:57:08.005070
1499 22:57:08.009087 [CBTSetCACLKResult] CA Dly = 34
1500 22:57:08.009170 CS Dly: 6 (0~39)
1501 22:57:08.009237
1502 22:57:08.012107 ----->DramcWriteLeveling(PI) begin...
1503 22:57:08.012233 ==
1504 22:57:08.015445 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 22:57:08.018835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 22:57:08.022306 ==
1507 22:57:08.022389 Write leveling (Byte 0): 29 => 29
1508 22:57:08.025521 Write leveling (Byte 1): 27 => 27
1509 22:57:08.028602 DramcWriteLeveling(PI) end<-----
1510 22:57:08.028711
1511 22:57:08.028796 ==
1512 22:57:08.031916 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 22:57:08.038884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 22:57:08.038968 ==
1515 22:57:08.039034 [Gating] SW mode calibration
1516 22:57:08.048719 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 22:57:08.051962 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 22:57:08.055635 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 22:57:08.062186 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1520 22:57:08.065520 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:57:08.068763 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:57:08.075493 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:57:08.079186 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:57:08.082503 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:57:08.088924 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:57:08.092106 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:57:08.095632 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:57:08.102080 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:57:08.105734 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:57:08.109368 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:57:08.115428 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:57:08.118885 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:57:08.122185 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:57:08.125523 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 22:57:08.132150 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1536 22:57:08.135617 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:57:08.139264 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:57:08.145871 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:57:08.148959 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:57:08.152691 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 22:57:08.158862 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 22:57:08.162224 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 22:57:08.165348 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1544 22:57:08.172434 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1545 22:57:08.175896 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 22:57:08.179012 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 22:57:08.186052 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 22:57:08.189039 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 22:57:08.192398 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 22:57:08.199321 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 22:57:08.202719 0 10 4 | B1->B0 | 3131 2d2d | 0 0 | (0 0) (0 0)
1552 22:57:08.205783 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1553 22:57:08.209372 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 22:57:08.215829 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 22:57:08.219153 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 22:57:08.222849 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 22:57:08.229379 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 22:57:08.232815 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 22:57:08.236302 0 11 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (0 0)
1560 22:57:08.242758 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1561 22:57:08.246189 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 22:57:08.249221 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 22:57:08.255840 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 22:57:08.258865 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 22:57:08.262567 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 22:57:08.269154 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 22:57:08.272379 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1568 22:57:08.275751 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 22:57:08.282247 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 22:57:08.286030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 22:57:08.289303 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 22:57:08.292502 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 22:57:08.299605 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 22:57:08.302384 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 22:57:08.305775 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 22:57:08.312655 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 22:57:08.315989 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 22:57:08.319484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 22:57:08.326230 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 22:57:08.329824 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 22:57:08.332908 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 22:57:08.339782 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 22:57:08.343080 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 22:57:08.346379 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 22:57:08.349580 Total UI for P1: 0, mck2ui 16
1586 22:57:08.352727 best dqsien dly found for B0: ( 0, 14, 4)
1587 22:57:08.356151 Total UI for P1: 0, mck2ui 16
1588 22:57:08.359253 best dqsien dly found for B1: ( 0, 14, 4)
1589 22:57:08.362979 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1590 22:57:08.366546 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1591 22:57:08.366629
1592 22:57:08.369442 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 22:57:08.372653 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1594 22:57:08.375991 [Gating] SW calibration Done
1595 22:57:08.376075 ==
1596 22:57:08.380065 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 22:57:08.386508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 22:57:08.386591 ==
1599 22:57:08.386657 RX Vref Scan: 0
1600 22:57:08.386719
1601 22:57:08.389412 RX Vref 0 -> 0, step: 1
1602 22:57:08.389495
1603 22:57:08.393436 RX Delay -130 -> 252, step: 16
1604 22:57:08.396558 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1605 22:57:08.399504 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1606 22:57:08.402831 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1607 22:57:08.406717 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1608 22:57:08.413036 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1609 22:57:08.416268 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1610 22:57:08.419994 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1611 22:57:08.423107 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1612 22:57:08.426257 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1613 22:57:08.429969 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1614 22:57:08.436722 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1615 22:57:08.440077 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1616 22:57:08.443234 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1617 22:57:08.446432 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1618 22:57:08.453522 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1619 22:57:08.456591 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1620 22:57:08.456674 ==
1621 22:57:08.459843 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 22:57:08.463122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 22:57:08.463220 ==
1624 22:57:08.463287 DQS Delay:
1625 22:57:08.466501 DQS0 = 0, DQS1 = 0
1626 22:57:08.466585 DQM Delay:
1627 22:57:08.470144 DQM0 = 92, DQM1 = 87
1628 22:57:08.470227 DQ Delay:
1629 22:57:08.473360 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1630 22:57:08.476733 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1631 22:57:08.479841 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1632 22:57:08.483346 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1633 22:57:08.483430
1634 22:57:08.483496
1635 22:57:08.483556 ==
1636 22:57:08.486799 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 22:57:08.489880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 22:57:08.493317 ==
1639 22:57:08.493400
1640 22:57:08.493465
1641 22:57:08.493526 TX Vref Scan disable
1642 22:57:08.496596 == TX Byte 0 ==
1643 22:57:08.499818 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1644 22:57:08.503754 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1645 22:57:08.506938 == TX Byte 1 ==
1646 22:57:08.510279 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1647 22:57:08.513526 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1648 22:57:08.516579 ==
1649 22:57:08.516662 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 22:57:08.523534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 22:57:08.523621 ==
1652 22:57:08.536074 TX Vref=22, minBit 3, minWin=25, winSum=436
1653 22:57:08.539306 TX Vref=24, minBit 2, minWin=27, winSum=443
1654 22:57:08.542459 TX Vref=26, minBit 0, minWin=27, winSum=446
1655 22:57:08.546058 TX Vref=28, minBit 1, minWin=27, winSum=448
1656 22:57:08.549224 TX Vref=30, minBit 1, minWin=27, winSum=450
1657 22:57:08.552571 TX Vref=32, minBit 1, minWin=27, winSum=449
1658 22:57:08.559144 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
1659 22:57:08.559228
1660 22:57:08.563637 Final TX Range 1 Vref 30
1661 22:57:08.563720
1662 22:57:08.563785 ==
1663 22:57:08.566734 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 22:57:08.569550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 22:57:08.569635 ==
1666 22:57:08.569702
1667 22:57:08.569763
1668 22:57:08.572846 TX Vref Scan disable
1669 22:57:08.575939 == TX Byte 0 ==
1670 22:57:08.579934 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1671 22:57:08.583454 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1672 22:57:08.586213 == TX Byte 1 ==
1673 22:57:08.589541 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1674 22:57:08.592738 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1675 22:57:08.592821
1676 22:57:08.596280 [DATLAT]
1677 22:57:08.596364 Freq=800, CH1 RK0
1678 22:57:08.596430
1679 22:57:08.599709 DATLAT Default: 0xa
1680 22:57:08.599792 0, 0xFFFF, sum = 0
1681 22:57:08.602807 1, 0xFFFF, sum = 0
1682 22:57:08.602925 2, 0xFFFF, sum = 0
1683 22:57:08.606342 3, 0xFFFF, sum = 0
1684 22:57:08.606429 4, 0xFFFF, sum = 0
1685 22:57:08.609399 5, 0xFFFF, sum = 0
1686 22:57:08.609486 6, 0xFFFF, sum = 0
1687 22:57:08.612655 7, 0xFFFF, sum = 0
1688 22:57:08.612756 8, 0xFFFF, sum = 0
1689 22:57:08.616079 9, 0x0, sum = 1
1690 22:57:08.616163 10, 0x0, sum = 2
1691 22:57:08.619838 11, 0x0, sum = 3
1692 22:57:08.619921 12, 0x0, sum = 4
1693 22:57:08.623107 best_step = 10
1694 22:57:08.623190
1695 22:57:08.623255 ==
1696 22:57:08.626396 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 22:57:08.629772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 22:57:08.629856 ==
1699 22:57:08.629922 RX Vref Scan: 1
1700 22:57:08.633054
1701 22:57:08.633136 Set Vref Range= 32 -> 127
1702 22:57:08.633235
1703 22:57:08.636251 RX Vref 32 -> 127, step: 1
1704 22:57:08.636334
1705 22:57:08.639697 RX Delay -79 -> 252, step: 8
1706 22:57:08.639806
1707 22:57:08.643081 Set Vref, RX VrefLevel [Byte0]: 32
1708 22:57:08.646274 [Byte1]: 32
1709 22:57:08.646358
1710 22:57:08.649381 Set Vref, RX VrefLevel [Byte0]: 33
1711 22:57:08.653145 [Byte1]: 33
1712 22:57:08.653227
1713 22:57:08.656570 Set Vref, RX VrefLevel [Byte0]: 34
1714 22:57:08.659147 [Byte1]: 34
1715 22:57:08.663462
1716 22:57:08.663544 Set Vref, RX VrefLevel [Byte0]: 35
1717 22:57:08.667238 [Byte1]: 35
1718 22:57:08.671286
1719 22:57:08.671368 Set Vref, RX VrefLevel [Byte0]: 36
1720 22:57:08.674134 [Byte1]: 36
1721 22:57:08.678568
1722 22:57:08.678650 Set Vref, RX VrefLevel [Byte0]: 37
1723 22:57:08.681825 [Byte1]: 37
1724 22:57:08.686343
1725 22:57:08.686425 Set Vref, RX VrefLevel [Byte0]: 38
1726 22:57:08.689075 [Byte1]: 38
1727 22:57:08.693828
1728 22:57:08.693910 Set Vref, RX VrefLevel [Byte0]: 39
1729 22:57:08.696461 [Byte1]: 39
1730 22:57:08.701134
1731 22:57:08.701217 Set Vref, RX VrefLevel [Byte0]: 40
1732 22:57:08.704436 [Byte1]: 40
1733 22:57:08.708522
1734 22:57:08.708605 Set Vref, RX VrefLevel [Byte0]: 41
1735 22:57:08.712167 [Byte1]: 41
1736 22:57:08.716372
1737 22:57:08.716456 Set Vref, RX VrefLevel [Byte0]: 42
1738 22:57:08.719179 [Byte1]: 42
1739 22:57:08.723903
1740 22:57:08.724030 Set Vref, RX VrefLevel [Byte0]: 43
1741 22:57:08.727127 [Byte1]: 43
1742 22:57:08.731015
1743 22:57:08.731112 Set Vref, RX VrefLevel [Byte0]: 44
1744 22:57:08.735041 [Byte1]: 44
1745 22:57:08.738926
1746 22:57:08.739035 Set Vref, RX VrefLevel [Byte0]: 45
1747 22:57:08.742191 [Byte1]: 45
1748 22:57:08.746127
1749 22:57:08.746237 Set Vref, RX VrefLevel [Byte0]: 46
1750 22:57:08.750067 [Byte1]: 46
1751 22:57:08.753910
1752 22:57:08.753995 Set Vref, RX VrefLevel [Byte0]: 47
1753 22:57:08.757242 [Byte1]: 47
1754 22:57:08.761250
1755 22:57:08.761336 Set Vref, RX VrefLevel [Byte0]: 48
1756 22:57:08.764679 [Byte1]: 48
1757 22:57:08.768956
1758 22:57:08.769041 Set Vref, RX VrefLevel [Byte0]: 49
1759 22:57:08.772221 [Byte1]: 49
1760 22:57:08.776670
1761 22:57:08.776756 Set Vref, RX VrefLevel [Byte0]: 50
1762 22:57:08.780123 [Byte1]: 50
1763 22:57:08.783998
1764 22:57:08.784084 Set Vref, RX VrefLevel [Byte0]: 51
1765 22:57:08.787556 [Byte1]: 51
1766 22:57:08.791328
1767 22:57:08.791414 Set Vref, RX VrefLevel [Byte0]: 52
1768 22:57:08.795085 [Byte1]: 52
1769 22:57:08.799190
1770 22:57:08.799314 Set Vref, RX VrefLevel [Byte0]: 53
1771 22:57:08.802097 [Byte1]: 53
1772 22:57:08.806844
1773 22:57:08.806925 Set Vref, RX VrefLevel [Byte0]: 54
1774 22:57:08.810073 [Byte1]: 54
1775 22:57:08.814076
1776 22:57:08.814158 Set Vref, RX VrefLevel [Byte0]: 55
1777 22:57:08.817664 [Byte1]: 55
1778 22:57:08.821939
1779 22:57:08.822024 Set Vref, RX VrefLevel [Byte0]: 56
1780 22:57:08.825254 [Byte1]: 56
1781 22:57:08.829496
1782 22:57:08.829596 Set Vref, RX VrefLevel [Byte0]: 57
1783 22:57:08.832528 [Byte1]: 57
1784 22:57:08.836831
1785 22:57:08.836940 Set Vref, RX VrefLevel [Byte0]: 58
1786 22:57:08.840397 [Byte1]: 58
1787 22:57:08.844355
1788 22:57:08.844440 Set Vref, RX VrefLevel [Byte0]: 59
1789 22:57:08.847455 [Byte1]: 59
1790 22:57:08.851855
1791 22:57:08.851988 Set Vref, RX VrefLevel [Byte0]: 60
1792 22:57:08.855370 [Byte1]: 60
1793 22:57:08.859909
1794 22:57:08.860049 Set Vref, RX VrefLevel [Byte0]: 61
1795 22:57:08.862971 [Byte1]: 61
1796 22:57:08.866872
1797 22:57:08.866957 Set Vref, RX VrefLevel [Byte0]: 62
1798 22:57:08.870235 [Byte1]: 62
1799 22:57:08.874777
1800 22:57:08.874863 Set Vref, RX VrefLevel [Byte0]: 63
1801 22:57:08.878030 [Byte1]: 63
1802 22:57:08.881876
1803 22:57:08.881962 Set Vref, RX VrefLevel [Byte0]: 64
1804 22:57:08.885819 [Byte1]: 64
1805 22:57:08.889729
1806 22:57:08.889814 Set Vref, RX VrefLevel [Byte0]: 65
1807 22:57:08.892943 [Byte1]: 65
1808 22:57:08.897449
1809 22:57:08.897534 Set Vref, RX VrefLevel [Byte0]: 66
1810 22:57:08.900731 [Byte1]: 66
1811 22:57:08.904779
1812 22:57:08.904865 Set Vref, RX VrefLevel [Byte0]: 67
1813 22:57:08.908172 [Byte1]: 67
1814 22:57:08.912664
1815 22:57:08.912749 Set Vref, RX VrefLevel [Byte0]: 68
1816 22:57:08.915408 [Byte1]: 68
1817 22:57:08.920281
1818 22:57:08.920366 Set Vref, RX VrefLevel [Byte0]: 69
1819 22:57:08.923557 [Byte1]: 69
1820 22:57:08.927389
1821 22:57:08.927474 Set Vref, RX VrefLevel [Byte0]: 70
1822 22:57:08.930525 [Byte1]: 70
1823 22:57:08.934938
1824 22:57:08.935023 Set Vref, RX VrefLevel [Byte0]: 71
1825 22:57:08.938183 [Byte1]: 71
1826 22:57:08.942532
1827 22:57:08.942617 Set Vref, RX VrefLevel [Byte0]: 72
1828 22:57:08.945687 [Byte1]: 72
1829 22:57:08.949913
1830 22:57:08.949998 Final RX Vref Byte 0 = 54 to rank0
1831 22:57:08.953405 Final RX Vref Byte 1 = 58 to rank0
1832 22:57:08.956626 Final RX Vref Byte 0 = 54 to rank1
1833 22:57:08.959846 Final RX Vref Byte 1 = 58 to rank1==
1834 22:57:08.963569 Dram Type= 6, Freq= 0, CH_1, rank 0
1835 22:57:08.966925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 22:57:08.969885 ==
1837 22:57:08.969971 DQS Delay:
1838 22:57:08.970057 DQS0 = 0, DQS1 = 0
1839 22:57:08.973729 DQM Delay:
1840 22:57:08.973815 DQM0 = 94, DQM1 = 90
1841 22:57:08.977125 DQ Delay:
1842 22:57:08.980326 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1843 22:57:08.983479 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1844 22:57:08.983565 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1845 22:57:08.990102 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1846 22:57:08.990188
1847 22:57:08.990274
1848 22:57:08.996722 [DQSOSCAuto] RK0, (LSB)MR18= 0x304d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1849 22:57:09.000621 CH1 RK0: MR19=606, MR18=304D
1850 22:57:09.006599 CH1_RK0: MR19=0x606, MR18=0x304D, DQSOSC=390, MR23=63, INC=97, DEC=64
1851 22:57:09.006685
1852 22:57:09.010472 ----->DramcWriteLeveling(PI) begin...
1853 22:57:09.010559 ==
1854 22:57:09.013273 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 22:57:09.017086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 22:57:09.017173 ==
1857 22:57:09.020588 Write leveling (Byte 0): 28 => 28
1858 22:57:09.023586 Write leveling (Byte 1): 29 => 29
1859 22:57:09.027110 DramcWriteLeveling(PI) end<-----
1860 22:57:09.027198
1861 22:57:09.027284 ==
1862 22:57:09.030297 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 22:57:09.033523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 22:57:09.033609 ==
1865 22:57:09.037178 [Gating] SW mode calibration
1866 22:57:09.043508 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1867 22:57:09.050607 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1868 22:57:09.053781 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1869 22:57:09.056975 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1870 22:57:09.063393 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:57:09.067001 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 22:57:09.070459 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 22:57:09.076612 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 22:57:09.080352 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 22:57:09.083567 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 22:57:09.090468 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:57:09.093682 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 22:57:09.097028 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 22:57:09.100424 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:57:09.106924 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:57:09.110238 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:57:09.116778 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:57:09.120068 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:57:09.123277 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1885 22:57:09.126723 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1886 22:57:09.133245 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:57:09.136935 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:57:09.139822 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:57:09.147060 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:57:09.150045 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:57:09.153022 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:57:09.159760 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:57:09.163403 0 9 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1894 22:57:09.166740 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1895 22:57:09.173382 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 22:57:09.176633 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 22:57:09.180167 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 22:57:09.186700 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 22:57:09.189717 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 22:57:09.193004 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1901 22:57:09.199928 0 10 4 | B1->B0 | 2626 2f2f | 0 0 | (1 1) (1 0)
1902 22:57:09.203653 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1903 22:57:09.206917 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:57:09.213387 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:57:09.216672 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 22:57:09.219797 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 22:57:09.226568 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 22:57:09.229653 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1909 22:57:09.233486 0 11 4 | B1->B0 | 3939 2424 | 0 1 | (0 0) (0 0)
1910 22:57:09.236337 0 11 8 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
1911 22:57:09.243102 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 22:57:09.246802 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 22:57:09.249834 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 22:57:09.256388 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 22:57:09.259710 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 22:57:09.262944 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 22:57:09.270050 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1918 22:57:09.273057 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 22:57:09.276559 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 22:57:09.283405 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 22:57:09.286686 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 22:57:09.289843 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 22:57:09.296942 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 22:57:09.300315 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 22:57:09.303695 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 22:57:09.309949 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 22:57:09.313614 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 22:57:09.316464 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 22:57:09.319872 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 22:57:09.326836 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 22:57:09.330121 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 22:57:09.333556 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1933 22:57:09.340104 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1934 22:57:09.343446 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 22:57:09.346528 Total UI for P1: 0, mck2ui 16
1936 22:57:09.350471 best dqsien dly found for B0: ( 0, 14, 4)
1937 22:57:09.353774 Total UI for P1: 0, mck2ui 16
1938 22:57:09.357009 best dqsien dly found for B1: ( 0, 14, 2)
1939 22:57:09.360109 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1940 22:57:09.363843 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1941 22:57:09.363925
1942 22:57:09.366912 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 22:57:09.370278 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1944 22:57:09.373479 [Gating] SW calibration Done
1945 22:57:09.373563 ==
1946 22:57:09.376607 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 22:57:09.379924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 22:57:09.380069 ==
1949 22:57:09.383655 RX Vref Scan: 0
1950 22:57:09.383742
1951 22:57:09.387047 RX Vref 0 -> 0, step: 1
1952 22:57:09.387134
1953 22:57:09.387199 RX Delay -130 -> 252, step: 16
1954 22:57:09.393849 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1955 22:57:09.397134 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1956 22:57:09.400258 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1957 22:57:09.403781 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1958 22:57:09.407135 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1959 22:57:09.413617 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1960 22:57:09.417000 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1961 22:57:09.420078 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1962 22:57:09.423286 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1963 22:57:09.426858 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1964 22:57:09.433688 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1965 22:57:09.437030 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1966 22:57:09.439903 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1967 22:57:09.443250 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1968 22:57:09.446657 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1969 22:57:09.453481 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1970 22:57:09.453573 ==
1971 22:57:09.456723 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 22:57:09.460181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 22:57:09.460264 ==
1974 22:57:09.460331 DQS Delay:
1975 22:57:09.463292 DQS0 = 0, DQS1 = 0
1976 22:57:09.463374 DQM Delay:
1977 22:57:09.467069 DQM0 = 91, DQM1 = 88
1978 22:57:09.467151 DQ Delay:
1979 22:57:09.470054 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1980 22:57:09.473608 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1981 22:57:09.476886 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1982 22:57:09.480201 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1983 22:57:09.480290
1984 22:57:09.480356
1985 22:57:09.480454 ==
1986 22:57:09.483546 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 22:57:09.486841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 22:57:09.490191 ==
1989 22:57:09.490275
1990 22:57:09.490339
1991 22:57:09.490399 TX Vref Scan disable
1992 22:57:09.493895 == TX Byte 0 ==
1993 22:57:09.496951 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1994 22:57:09.500381 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1995 22:57:09.503868 == TX Byte 1 ==
1996 22:57:09.507222 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 22:57:09.511117 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 22:57:09.511203 ==
1999 22:57:09.513567 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 22:57:09.519894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 22:57:09.520038 ==
2002 22:57:09.532443 TX Vref=22, minBit 0, minWin=27, winSum=445
2003 22:57:09.535721 TX Vref=24, minBit 0, minWin=27, winSum=447
2004 22:57:09.538936 TX Vref=26, minBit 2, minWin=27, winSum=450
2005 22:57:09.542252 TX Vref=28, minBit 1, minWin=27, winSum=449
2006 22:57:09.545602 TX Vref=30, minBit 2, minWin=27, winSum=451
2007 22:57:09.551899 TX Vref=32, minBit 2, minWin=27, winSum=450
2008 22:57:09.555544 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
2009 22:57:09.555698
2010 22:57:09.558754 Final TX Range 1 Vref 30
2011 22:57:09.558888
2012 22:57:09.558964 ==
2013 22:57:09.562410 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 22:57:09.565230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 22:57:09.565391 ==
2016 22:57:09.568481
2017 22:57:09.568653
2018 22:57:09.568757 TX Vref Scan disable
2019 22:57:09.572566 == TX Byte 0 ==
2020 22:57:09.575224 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2021 22:57:09.578656 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2022 22:57:09.582183 == TX Byte 1 ==
2023 22:57:09.585804 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 22:57:09.588623 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 22:57:09.591992
2026 22:57:09.592094 [DATLAT]
2027 22:57:09.592182 Freq=800, CH1 RK1
2028 22:57:09.592263
2029 22:57:09.595990 DATLAT Default: 0xa
2030 22:57:09.596091 0, 0xFFFF, sum = 0
2031 22:57:09.599067 1, 0xFFFF, sum = 0
2032 22:57:09.599172 2, 0xFFFF, sum = 0
2033 22:57:09.602138 3, 0xFFFF, sum = 0
2034 22:57:09.602230 4, 0xFFFF, sum = 0
2035 22:57:09.605365 5, 0xFFFF, sum = 0
2036 22:57:09.605456 6, 0xFFFF, sum = 0
2037 22:57:09.609167 7, 0xFFFF, sum = 0
2038 22:57:09.609258 8, 0xFFFF, sum = 0
2039 22:57:09.612382 9, 0x0, sum = 1
2040 22:57:09.612471 10, 0x0, sum = 2
2041 22:57:09.615570 11, 0x0, sum = 3
2042 22:57:09.615658 12, 0x0, sum = 4
2043 22:57:09.619099 best_step = 10
2044 22:57:09.619187
2045 22:57:09.619275 ==
2046 22:57:09.622575 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 22:57:09.625495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 22:57:09.625586 ==
2049 22:57:09.628777 RX Vref Scan: 0
2050 22:57:09.628872
2051 22:57:09.628949 RX Vref 0 -> 0, step: 1
2052 22:57:09.629012
2053 22:57:09.632684 RX Delay -79 -> 252, step: 8
2054 22:57:09.638690 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2055 22:57:09.642069 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2056 22:57:09.645319 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2057 22:57:09.648608 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2058 22:57:09.652446 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2059 22:57:09.655896 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2060 22:57:09.662431 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2061 22:57:09.665618 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2062 22:57:09.668962 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2063 22:57:09.672420 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2064 22:57:09.675731 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2065 22:57:09.682514 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2066 22:57:09.686368 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2067 22:57:09.689073 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2068 22:57:09.692466 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2069 22:57:09.695879 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2070 22:57:09.696000 ==
2071 22:57:09.699149 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 22:57:09.705689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 22:57:09.705791 ==
2074 22:57:09.705862 DQS Delay:
2075 22:57:09.709444 DQS0 = 0, DQS1 = 0
2076 22:57:09.709529 DQM Delay:
2077 22:57:09.709595 DQM0 = 97, DQM1 = 90
2078 22:57:09.712374 DQ Delay:
2079 22:57:09.715508 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2080 22:57:09.718965 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2081 22:57:09.722470 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2082 22:57:09.725805 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2083 22:57:09.725893
2084 22:57:09.725961
2085 22:57:09.732540 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
2086 22:57:09.735819 CH1 RK1: MR19=606, MR18=4B14
2087 22:57:09.742629 CH1_RK1: MR19=0x606, MR18=0x4B14, DQSOSC=391, MR23=63, INC=96, DEC=64
2088 22:57:09.746012 [RxdqsGatingPostProcess] freq 800
2089 22:57:09.749359 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 22:57:09.752560 Pre-setting of DQS Precalculation
2091 22:57:09.759198 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 22:57:09.765804 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 22:57:09.772267 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 22:57:09.772376
2095 22:57:09.772466
2096 22:57:09.776105 [Calibration Summary] 1600 Mbps
2097 22:57:09.776218 CH 0, Rank 0
2098 22:57:09.779250 SW Impedance : PASS
2099 22:57:09.782475 DUTY Scan : NO K
2100 22:57:09.782563 ZQ Calibration : PASS
2101 22:57:09.785721 Jitter Meter : NO K
2102 22:57:09.788936 CBT Training : PASS
2103 22:57:09.789024 Write leveling : PASS
2104 22:57:09.792647 RX DQS gating : PASS
2105 22:57:09.795724 RX DQ/DQS(RDDQC) : PASS
2106 22:57:09.795812 TX DQ/DQS : PASS
2107 22:57:09.799011 RX DATLAT : PASS
2108 22:57:09.799098 RX DQ/DQS(Engine): PASS
2109 22:57:09.802628 TX OE : NO K
2110 22:57:09.802742 All Pass.
2111 22:57:09.802848
2112 22:57:09.805856 CH 0, Rank 1
2113 22:57:09.805942 SW Impedance : PASS
2114 22:57:09.809463 DUTY Scan : NO K
2115 22:57:09.812836 ZQ Calibration : PASS
2116 22:57:09.812924 Jitter Meter : NO K
2117 22:57:09.816014 CBT Training : PASS
2118 22:57:09.819394 Write leveling : PASS
2119 22:57:09.819487 RX DQS gating : PASS
2120 22:57:09.822597 RX DQ/DQS(RDDQC) : PASS
2121 22:57:09.825764 TX DQ/DQS : PASS
2122 22:57:09.825855 RX DATLAT : PASS
2123 22:57:09.829502 RX DQ/DQS(Engine): PASS
2124 22:57:09.832810 TX OE : NO K
2125 22:57:09.832902 All Pass.
2126 22:57:09.832968
2127 22:57:09.833029 CH 1, Rank 0
2128 22:57:09.835995 SW Impedance : PASS
2129 22:57:09.839365 DUTY Scan : NO K
2130 22:57:09.839450 ZQ Calibration : PASS
2131 22:57:09.842405 Jitter Meter : NO K
2132 22:57:09.842494 CBT Training : PASS
2133 22:57:09.845824 Write leveling : PASS
2134 22:57:09.849312 RX DQS gating : PASS
2135 22:57:09.849400 RX DQ/DQS(RDDQC) : PASS
2136 22:57:09.852659 TX DQ/DQS : PASS
2137 22:57:09.855890 RX DATLAT : PASS
2138 22:57:09.856032 RX DQ/DQS(Engine): PASS
2139 22:57:09.858958 TX OE : NO K
2140 22:57:09.859041 All Pass.
2141 22:57:09.859106
2142 22:57:09.862439 CH 1, Rank 1
2143 22:57:09.862523 SW Impedance : PASS
2144 22:57:09.865745 DUTY Scan : NO K
2145 22:57:09.869052 ZQ Calibration : PASS
2146 22:57:09.869136 Jitter Meter : NO K
2147 22:57:09.872781 CBT Training : PASS
2148 22:57:09.875947 Write leveling : PASS
2149 22:57:09.876071 RX DQS gating : PASS
2150 22:57:09.879251 RX DQ/DQS(RDDQC) : PASS
2151 22:57:09.882555 TX DQ/DQS : PASS
2152 22:57:09.882640 RX DATLAT : PASS
2153 22:57:09.885914 RX DQ/DQS(Engine): PASS
2154 22:57:09.885997 TX OE : NO K
2155 22:57:09.889062 All Pass.
2156 22:57:09.889148
2157 22:57:09.889213 DramC Write-DBI off
2158 22:57:09.892364 PER_BANK_REFRESH: Hybrid Mode
2159 22:57:09.895646 TX_TRACKING: ON
2160 22:57:09.899460 [GetDramInforAfterCalByMRR] Vendor 6.
2161 22:57:09.902744 [GetDramInforAfterCalByMRR] Revision 606.
2162 22:57:09.905962 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 22:57:09.906053 MR0 0x3b3b
2164 22:57:09.906120 MR8 0x5151
2165 22:57:09.913015 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 22:57:09.913106
2167 22:57:09.913173 MR0 0x3b3b
2168 22:57:09.913234 MR8 0x5151
2169 22:57:09.916043 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 22:57:09.916127
2171 22:57:09.925720 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 22:57:09.929166 [FAST_K] Save calibration result to emmc
2173 22:57:09.932402 [FAST_K] Save calibration result to emmc
2174 22:57:09.936264 dram_init: config_dvfs: 1
2175 22:57:09.939205 dramc_set_vcore_voltage set vcore to 662500
2176 22:57:09.943105 Read voltage for 1200, 2
2177 22:57:09.943195 Vio18 = 0
2178 22:57:09.943261 Vcore = 662500
2179 22:57:09.946402 Vdram = 0
2180 22:57:09.946489 Vddq = 0
2181 22:57:09.946555 Vmddr = 0
2182 22:57:09.952586 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 22:57:09.956260 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 22:57:09.959953 MEM_TYPE=3, freq_sel=15
2185 22:57:09.962854 sv_algorithm_assistance_LP4_1600
2186 22:57:09.966116 ============ PULL DRAM RESETB DOWN ============
2187 22:57:09.969272 ========== PULL DRAM RESETB DOWN end =========
2188 22:57:09.976400 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 22:57:09.979611 ===================================
2190 22:57:09.979702 LPDDR4 DRAM CONFIGURATION
2191 22:57:09.982849 ===================================
2192 22:57:09.985920 EX_ROW_EN[0] = 0x0
2193 22:57:09.989378 EX_ROW_EN[1] = 0x0
2194 22:57:09.989467 LP4Y_EN = 0x0
2195 22:57:09.992737 WORK_FSP = 0x0
2196 22:57:09.992822 WL = 0x4
2197 22:57:09.996134 RL = 0x4
2198 22:57:09.996226 BL = 0x2
2199 22:57:09.999234 RPST = 0x0
2200 22:57:09.999317 RD_PRE = 0x0
2201 22:57:10.003107 WR_PRE = 0x1
2202 22:57:10.003201 WR_PST = 0x0
2203 22:57:10.006309 DBI_WR = 0x0
2204 22:57:10.006396 DBI_RD = 0x0
2205 22:57:10.009718 OTF = 0x1
2206 22:57:10.012883 ===================================
2207 22:57:10.016380 ===================================
2208 22:57:10.016467 ANA top config
2209 22:57:10.019306 ===================================
2210 22:57:10.022624 DLL_ASYNC_EN = 0
2211 22:57:10.025983 ALL_SLAVE_EN = 0
2212 22:57:10.029641 NEW_RANK_MODE = 1
2213 22:57:10.029740 DLL_IDLE_MODE = 1
2214 22:57:10.032901 LP45_APHY_COMB_EN = 1
2215 22:57:10.035856 TX_ODT_DIS = 1
2216 22:57:10.039165 NEW_8X_MODE = 1
2217 22:57:10.042496 ===================================
2218 22:57:10.045754 ===================================
2219 22:57:10.049162 data_rate = 2400
2220 22:57:10.049252 CKR = 1
2221 22:57:10.052514 DQ_P2S_RATIO = 8
2222 22:57:10.056274 ===================================
2223 22:57:10.059607 CA_P2S_RATIO = 8
2224 22:57:10.062783 DQ_CA_OPEN = 0
2225 22:57:10.066188 DQ_SEMI_OPEN = 0
2226 22:57:10.066281 CA_SEMI_OPEN = 0
2227 22:57:10.069392 CA_FULL_RATE = 0
2228 22:57:10.072656 DQ_CKDIV4_EN = 0
2229 22:57:10.076148 CA_CKDIV4_EN = 0
2230 22:57:10.079180 CA_PREDIV_EN = 0
2231 22:57:10.082750 PH8_DLY = 17
2232 22:57:10.082846 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 22:57:10.086341 DQ_AAMCK_DIV = 4
2234 22:57:10.089651 CA_AAMCK_DIV = 4
2235 22:57:10.092627 CA_ADMCK_DIV = 4
2236 22:57:10.096600 DQ_TRACK_CA_EN = 0
2237 22:57:10.100085 CA_PICK = 1200
2238 22:57:10.102660 CA_MCKIO = 1200
2239 22:57:10.102747 MCKIO_SEMI = 0
2240 22:57:10.106660 PLL_FREQ = 2366
2241 22:57:10.109500 DQ_UI_PI_RATIO = 32
2242 22:57:10.112865 CA_UI_PI_RATIO = 0
2243 22:57:10.116255 ===================================
2244 22:57:10.119478 ===================================
2245 22:57:10.122602 memory_type:LPDDR4
2246 22:57:10.122690 GP_NUM : 10
2247 22:57:10.126224 SRAM_EN : 1
2248 22:57:10.126312 MD32_EN : 0
2249 22:57:10.129638 ===================================
2250 22:57:10.132807 [ANA_INIT] >>>>>>>>>>>>>>
2251 22:57:10.136059 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 22:57:10.139741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 22:57:10.142761 ===================================
2254 22:57:10.146411 data_rate = 2400,PCW = 0X5b00
2255 22:57:10.149776 ===================================
2256 22:57:10.152928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 22:57:10.159693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 22:57:10.162947 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 22:57:10.169275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 22:57:10.172758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 22:57:10.176368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 22:57:10.176483 [ANA_INIT] flow start
2263 22:57:10.179430 [ANA_INIT] PLL >>>>>>>>
2264 22:57:10.182758 [ANA_INIT] PLL <<<<<<<<
2265 22:57:10.182848 [ANA_INIT] MIDPI >>>>>>>>
2266 22:57:10.186064 [ANA_INIT] MIDPI <<<<<<<<
2267 22:57:10.189134 [ANA_INIT] DLL >>>>>>>>
2268 22:57:10.189223 [ANA_INIT] DLL <<<<<<<<
2269 22:57:10.192707 [ANA_INIT] flow end
2270 22:57:10.196332 ============ LP4 DIFF to SE enter ============
2271 22:57:10.199236 ============ LP4 DIFF to SE exit ============
2272 22:57:10.202617 [ANA_INIT] <<<<<<<<<<<<<
2273 22:57:10.205892 [Flow] Enable top DCM control >>>>>
2274 22:57:10.209488 [Flow] Enable top DCM control <<<<<
2275 22:57:10.212905 Enable DLL master slave shuffle
2276 22:57:10.219270 ==============================================================
2277 22:57:10.219385 Gating Mode config
2278 22:57:10.226457 ==============================================================
2279 22:57:10.226571 Config description:
2280 22:57:10.236318 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 22:57:10.242556 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 22:57:10.249108 SELPH_MODE 0: By rank 1: By Phase
2283 22:57:10.252518 ==============================================================
2284 22:57:10.256493 GAT_TRACK_EN = 1
2285 22:57:10.259857 RX_GATING_MODE = 2
2286 22:57:10.262578 RX_GATING_TRACK_MODE = 2
2287 22:57:10.266390 SELPH_MODE = 1
2288 22:57:10.269204 PICG_EARLY_EN = 1
2289 22:57:10.272904 VALID_LAT_VALUE = 1
2290 22:57:10.276293 ==============================================================
2291 22:57:10.282775 Enter into Gating configuration >>>>
2292 22:57:10.282882 Exit from Gating configuration <<<<
2293 22:57:10.285969 Enter into DVFS_PRE_config >>>>>
2294 22:57:10.299239 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 22:57:10.303015 Exit from DVFS_PRE_config <<<<<
2296 22:57:10.306262 Enter into PICG configuration >>>>
2297 22:57:10.309649 Exit from PICG configuration <<<<
2298 22:57:10.309739 [RX_INPUT] configuration >>>>>
2299 22:57:10.312979 [RX_INPUT] configuration <<<<<
2300 22:57:10.319582 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 22:57:10.323231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 22:57:10.329341 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 22:57:10.336624 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 22:57:10.342830 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 22:57:10.349948 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 22:57:10.353398 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 22:57:10.356227 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 22:57:10.359649 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 22:57:10.366335 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 22:57:10.369572 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 22:57:10.373025 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 22:57:10.376267 ===================================
2313 22:57:10.379970 LPDDR4 DRAM CONFIGURATION
2314 22:57:10.383409 ===================================
2315 22:57:10.383512 EX_ROW_EN[0] = 0x0
2316 22:57:10.386594 EX_ROW_EN[1] = 0x0
2317 22:57:10.389851 LP4Y_EN = 0x0
2318 22:57:10.389937 WORK_FSP = 0x0
2319 22:57:10.393219 WL = 0x4
2320 22:57:10.393303 RL = 0x4
2321 22:57:10.396293 BL = 0x2
2322 22:57:10.396377 RPST = 0x0
2323 22:57:10.399880 RD_PRE = 0x0
2324 22:57:10.399984 WR_PRE = 0x1
2325 22:57:10.402842 WR_PST = 0x0
2326 22:57:10.402934 DBI_WR = 0x0
2327 22:57:10.406636 DBI_RD = 0x0
2328 22:57:10.406726 OTF = 0x1
2329 22:57:10.409371 ===================================
2330 22:57:10.413565 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 22:57:10.419461 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 22:57:10.422762 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 22:57:10.426527 ===================================
2334 22:57:10.429473 LPDDR4 DRAM CONFIGURATION
2335 22:57:10.433130 ===================================
2336 22:57:10.433234 EX_ROW_EN[0] = 0x10
2337 22:57:10.436596 EX_ROW_EN[1] = 0x0
2338 22:57:10.436684 LP4Y_EN = 0x0
2339 22:57:10.439999 WORK_FSP = 0x0
2340 22:57:10.440099 WL = 0x4
2341 22:57:10.443315 RL = 0x4
2342 22:57:10.446455 BL = 0x2
2343 22:57:10.446543 RPST = 0x0
2344 22:57:10.449560 RD_PRE = 0x0
2345 22:57:10.449649 WR_PRE = 0x1
2346 22:57:10.453179 WR_PST = 0x0
2347 22:57:10.453265 DBI_WR = 0x0
2348 22:57:10.456432 DBI_RD = 0x0
2349 22:57:10.456517 OTF = 0x1
2350 22:57:10.459886 ===================================
2351 22:57:10.466230 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 22:57:10.466363 ==
2353 22:57:10.469777 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 22:57:10.472946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 22:57:10.473085 ==
2356 22:57:10.476200 [Duty_Offset_Calibration]
2357 22:57:10.476349 B0:2 B1:1 CA:1
2358 22:57:10.479700
2359 22:57:10.483456 [DutyScan_Calibration_Flow] k_type=0
2360 22:57:10.490618
2361 22:57:10.490798 ==CLK 0==
2362 22:57:10.493986 Final CLK duty delay cell = 0
2363 22:57:10.497351 [0] MAX Duty = 5218%(X100), DQS PI = 24
2364 22:57:10.500574 [0] MIN Duty = 4875%(X100), DQS PI = 0
2365 22:57:10.500678 [0] AVG Duty = 5046%(X100)
2366 22:57:10.504234
2367 22:57:10.504348 CH0 CLK Duty spec in!! Max-Min= 343%
2368 22:57:10.510526 [DutyScan_Calibration_Flow] ====Done====
2369 22:57:10.510629
2370 22:57:10.514100 [DutyScan_Calibration_Flow] k_type=1
2371 22:57:10.529740
2372 22:57:10.529892 ==DQS 0 ==
2373 22:57:10.532839 Final DQS duty delay cell = -4
2374 22:57:10.536127 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2375 22:57:10.539328 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2376 22:57:10.542673 [-4] AVG Duty = 4937%(X100)
2377 22:57:10.542762
2378 22:57:10.542828 ==DQS 1 ==
2379 22:57:10.546599 Final DQS duty delay cell = 0
2380 22:57:10.549601 [0] MAX Duty = 5156%(X100), DQS PI = 0
2381 22:57:10.552981 [0] MIN Duty = 5000%(X100), DQS PI = 32
2382 22:57:10.553072 [0] AVG Duty = 5078%(X100)
2383 22:57:10.556104
2384 22:57:10.559514 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2385 22:57:10.559601
2386 22:57:10.563186 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2387 22:57:10.566215 [DutyScan_Calibration_Flow] ====Done====
2388 22:57:10.566302
2389 22:57:10.569309 [DutyScan_Calibration_Flow] k_type=3
2390 22:57:10.586023
2391 22:57:10.586173 ==DQM 0 ==
2392 22:57:10.589782 Final DQM duty delay cell = 0
2393 22:57:10.592773 [0] MAX Duty = 5156%(X100), DQS PI = 30
2394 22:57:10.595915 [0] MIN Duty = 4907%(X100), DQS PI = 58
2395 22:57:10.596050 [0] AVG Duty = 5031%(X100)
2396 22:57:10.599731
2397 22:57:10.599816 ==DQM 1 ==
2398 22:57:10.602983 Final DQM duty delay cell = 0
2399 22:57:10.606346 [0] MAX Duty = 5093%(X100), DQS PI = 0
2400 22:57:10.609624 [0] MIN Duty = 5031%(X100), DQS PI = 36
2401 22:57:10.609713 [0] AVG Duty = 5062%(X100)
2402 22:57:10.612675
2403 22:57:10.616639 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2404 22:57:10.616728
2405 22:57:10.619725 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2406 22:57:10.622721 [DutyScan_Calibration_Flow] ====Done====
2407 22:57:10.622816
2408 22:57:10.626215 [DutyScan_Calibration_Flow] k_type=2
2409 22:57:10.642689
2410 22:57:10.642842 ==DQ 0 ==
2411 22:57:10.645955 Final DQ duty delay cell = 0
2412 22:57:10.649368 [0] MAX Duty = 5062%(X100), DQS PI = 32
2413 22:57:10.652466 [0] MIN Duty = 4844%(X100), DQS PI = 62
2414 22:57:10.652555 [0] AVG Duty = 4953%(X100)
2415 22:57:10.652622
2416 22:57:10.655732 ==DQ 1 ==
2417 22:57:10.659678 Final DQ duty delay cell = 0
2418 22:57:10.662983 [0] MAX Duty = 5093%(X100), DQS PI = 24
2419 22:57:10.666129 [0] MIN Duty = 4907%(X100), DQS PI = 36
2420 22:57:10.666222 [0] AVG Duty = 5000%(X100)
2421 22:57:10.666289
2422 22:57:10.669520 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2423 22:57:10.669606
2424 22:57:10.672807 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2425 22:57:10.679480 [DutyScan_Calibration_Flow] ====Done====
2426 22:57:10.679580 ==
2427 22:57:10.682772 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 22:57:10.686392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 22:57:10.686481 ==
2430 22:57:10.689252 [Duty_Offset_Calibration]
2431 22:57:10.689360 B0:1 B1:0 CA:0
2432 22:57:10.689426
2433 22:57:10.692740 [DutyScan_Calibration_Flow] k_type=0
2434 22:57:10.701570
2435 22:57:10.701678 ==CLK 0==
2436 22:57:10.705291 Final CLK duty delay cell = -4
2437 22:57:10.708508 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2438 22:57:10.711947 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2439 22:57:10.715394 [-4] AVG Duty = 4953%(X100)
2440 22:57:10.715486
2441 22:57:10.718549 CH1 CLK Duty spec in!! Max-Min= 156%
2442 22:57:10.721946 [DutyScan_Calibration_Flow] ====Done====
2443 22:57:10.722035
2444 22:57:10.725141 [DutyScan_Calibration_Flow] k_type=1
2445 22:57:10.741520
2446 22:57:10.741671 ==DQS 0 ==
2447 22:57:10.744641 Final DQS duty delay cell = 0
2448 22:57:10.748501 [0] MAX Duty = 5094%(X100), DQS PI = 26
2449 22:57:10.751688 [0] MIN Duty = 4844%(X100), DQS PI = 0
2450 22:57:10.751783 [0] AVG Duty = 4969%(X100)
2451 22:57:10.755115
2452 22:57:10.755199 ==DQS 1 ==
2453 22:57:10.758262 Final DQS duty delay cell = 0
2454 22:57:10.761434 [0] MAX Duty = 5187%(X100), DQS PI = 20
2455 22:57:10.764822 [0] MIN Duty = 4969%(X100), DQS PI = 10
2456 22:57:10.764909 [0] AVG Duty = 5078%(X100)
2457 22:57:10.768499
2458 22:57:10.771743 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2459 22:57:10.771840
2460 22:57:10.774946 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2461 22:57:10.778263 [DutyScan_Calibration_Flow] ====Done====
2462 22:57:10.778349
2463 22:57:10.781678 [DutyScan_Calibration_Flow] k_type=3
2464 22:57:10.798323
2465 22:57:10.798470 ==DQM 0 ==
2466 22:57:10.801640 Final DQM duty delay cell = 0
2467 22:57:10.804822 [0] MAX Duty = 5156%(X100), DQS PI = 6
2468 22:57:10.808197 [0] MIN Duty = 5031%(X100), DQS PI = 0
2469 22:57:10.808290 [0] AVG Duty = 5093%(X100)
2470 22:57:10.808356
2471 22:57:10.811432 ==DQM 1 ==
2472 22:57:10.815174 Final DQM duty delay cell = 0
2473 22:57:10.818507 [0] MAX Duty = 5031%(X100), DQS PI = 26
2474 22:57:10.821555 [0] MIN Duty = 4875%(X100), DQS PI = 36
2475 22:57:10.821688 [0] AVG Duty = 4953%(X100)
2476 22:57:10.821755
2477 22:57:10.825217 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2478 22:57:10.828372
2479 22:57:10.831540 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2480 22:57:10.834593 [DutyScan_Calibration_Flow] ====Done====
2481 22:57:10.834683
2482 22:57:10.838082 [DutyScan_Calibration_Flow] k_type=2
2483 22:57:10.853930
2484 22:57:10.854082 ==DQ 0 ==
2485 22:57:10.857167 Final DQ duty delay cell = -4
2486 22:57:10.860585 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2487 22:57:10.863710 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2488 22:57:10.866922 [-4] AVG Duty = 4984%(X100)
2489 22:57:10.867038
2490 22:57:10.867149 ==DQ 1 ==
2491 22:57:10.870339 Final DQ duty delay cell = 0
2492 22:57:10.873829 [0] MAX Duty = 5125%(X100), DQS PI = 20
2493 22:57:10.877240 [0] MIN Duty = 4969%(X100), DQS PI = 12
2494 22:57:10.877350 [0] AVG Duty = 5047%(X100)
2495 22:57:10.880430
2496 22:57:10.883743 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2497 22:57:10.883832
2498 22:57:10.886931 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2499 22:57:10.890186 [DutyScan_Calibration_Flow] ====Done====
2500 22:57:10.894088 nWR fixed to 30
2501 22:57:10.894177 [ModeRegInit_LP4] CH0 RK0
2502 22:57:10.897350 [ModeRegInit_LP4] CH0 RK1
2503 22:57:10.900672 [ModeRegInit_LP4] CH1 RK0
2504 22:57:10.903946 [ModeRegInit_LP4] CH1 RK1
2505 22:57:10.904081 match AC timing 7
2506 22:57:10.910593 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 22:57:10.914008 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 22:57:10.916826 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 22:57:10.923944 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 22:57:10.927238 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 22:57:10.927339 ==
2512 22:57:10.930499 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 22:57:10.933677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 22:57:10.933766 ==
2515 22:57:10.940796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 22:57:10.946912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 22:57:10.954231 [CA 0] Center 39 (8~70) winsize 63
2518 22:57:10.957641 [CA 1] Center 39 (8~70) winsize 63
2519 22:57:10.960599 [CA 2] Center 35 (4~66) winsize 63
2520 22:57:10.963887 [CA 3] Center 34 (4~65) winsize 62
2521 22:57:10.967548 [CA 4] Center 33 (3~64) winsize 62
2522 22:57:10.971313 [CA 5] Center 32 (3~62) winsize 60
2523 22:57:10.971406
2524 22:57:10.974435 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2525 22:57:10.974521
2526 22:57:10.977737 [CATrainingPosCal] consider 1 rank data
2527 22:57:10.981032 u2DelayCellTimex100 = 270/100 ps
2528 22:57:10.984226 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2529 22:57:10.987775 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2530 22:57:10.993880 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2531 22:57:10.997603 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2532 22:57:11.000976 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2533 22:57:11.003939 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2534 22:57:11.004054
2535 22:57:11.007671 CA PerBit enable=1, Macro0, CA PI delay=32
2536 22:57:11.007762
2537 22:57:11.010772 [CBTSetCACLKResult] CA Dly = 32
2538 22:57:11.010860 CS Dly: 6 (0~37)
2539 22:57:11.010927 ==
2540 22:57:11.013800 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 22:57:11.020533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 22:57:11.020634 ==
2543 22:57:11.023878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 22:57:11.030522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2545 22:57:11.039703 [CA 0] Center 38 (8~69) winsize 62
2546 22:57:11.042954 [CA 1] Center 38 (8~69) winsize 62
2547 22:57:11.046694 [CA 2] Center 35 (4~66) winsize 63
2548 22:57:11.049731 [CA 3] Center 34 (4~65) winsize 62
2549 22:57:11.053395 [CA 4] Center 33 (3~63) winsize 61
2550 22:57:11.056671 [CA 5] Center 32 (3~62) winsize 60
2551 22:57:11.056764
2552 22:57:11.059913 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2553 22:57:11.060082
2554 22:57:11.063164 [CATrainingPosCal] consider 2 rank data
2555 22:57:11.066478 u2DelayCellTimex100 = 270/100 ps
2556 22:57:11.069869 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2557 22:57:11.073606 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2558 22:57:11.080251 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2559 22:57:11.082961 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2560 22:57:11.086984 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2561 22:57:11.090280 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2562 22:57:11.090378
2563 22:57:11.092944 CA PerBit enable=1, Macro0, CA PI delay=32
2564 22:57:11.093032
2565 22:57:11.096785 [CBTSetCACLKResult] CA Dly = 32
2566 22:57:11.096873 CS Dly: 6 (0~38)
2567 22:57:11.096961
2568 22:57:11.099945 ----->DramcWriteLeveling(PI) begin...
2569 22:57:11.103230 ==
2570 22:57:11.106345 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 22:57:11.110087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 22:57:11.110180 ==
2573 22:57:11.113122 Write leveling (Byte 0): 33 => 33
2574 22:57:11.116391 Write leveling (Byte 1): 31 => 31
2575 22:57:11.120205 DramcWriteLeveling(PI) end<-----
2576 22:57:11.120293
2577 22:57:11.120381 ==
2578 22:57:11.123101 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 22:57:11.126496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 22:57:11.126588 ==
2581 22:57:11.130449 [Gating] SW mode calibration
2582 22:57:11.136462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 22:57:11.139964 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 22:57:11.146471 0 15 0 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
2585 22:57:11.149803 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2586 22:57:11.153111 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 22:57:11.159895 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 22:57:11.162945 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 22:57:11.166400 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 22:57:11.173237 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2591 22:57:11.176420 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2592 22:57:11.179911 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2593 22:57:11.186452 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 22:57:11.189741 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 22:57:11.193128 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 22:57:11.200207 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 22:57:11.203567 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 22:57:11.206893 1 0 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2599 22:57:11.213183 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2600 22:57:11.217114 1 1 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
2601 22:57:11.219881 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 22:57:11.223110 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 22:57:11.229689 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 22:57:11.233523 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 22:57:11.236433 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 22:57:11.243536 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 22:57:11.246559 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 22:57:11.249981 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 22:57:11.256553 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 22:57:11.259841 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 22:57:11.263126 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 22:57:11.269975 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 22:57:11.273557 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 22:57:11.277018 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 22:57:11.283587 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 22:57:11.286616 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 22:57:11.290281 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 22:57:11.293782 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 22:57:11.300303 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 22:57:11.303476 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 22:57:11.307068 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 22:57:11.313941 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 22:57:11.317092 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 22:57:11.320253 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 22:57:11.323495 Total UI for P1: 0, mck2ui 16
2626 22:57:11.327505 best dqsien dly found for B0: ( 1, 3, 26)
2627 22:57:11.330338 Total UI for P1: 0, mck2ui 16
2628 22:57:11.334268 best dqsien dly found for B1: ( 1, 3, 30)
2629 22:57:11.337517 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2630 22:57:11.340805 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2631 22:57:11.340919
2632 22:57:11.347078 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2633 22:57:11.350574 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2634 22:57:11.350667 [Gating] SW calibration Done
2635 22:57:11.353919 ==
2636 22:57:11.357371 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 22:57:11.360477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 22:57:11.360575 ==
2639 22:57:11.360642 RX Vref Scan: 0
2640 22:57:11.360704
2641 22:57:11.363540 RX Vref 0 -> 0, step: 1
2642 22:57:11.363624
2643 22:57:11.366667 RX Delay -40 -> 252, step: 8
2644 22:57:11.370020 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2645 22:57:11.374120 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2646 22:57:11.377237 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2647 22:57:11.383937 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2648 22:57:11.386864 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2649 22:57:11.390382 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2650 22:57:11.393651 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2651 22:57:11.397133 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2652 22:57:11.403876 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2653 22:57:11.406878 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2654 22:57:11.410380 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2655 22:57:11.413727 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2656 22:57:11.417455 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2657 22:57:11.424544 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2658 22:57:11.427761 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2659 22:57:11.430196 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2660 22:57:11.430436 ==
2661 22:57:11.434051 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 22:57:11.437332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 22:57:11.437512 ==
2664 22:57:11.440657 DQS Delay:
2665 22:57:11.440831 DQS0 = 0, DQS1 = 0
2666 22:57:11.443752 DQM Delay:
2667 22:57:11.443942 DQM0 = 121, DQM1 = 113
2668 22:57:11.444080 DQ Delay:
2669 22:57:11.447047 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2670 22:57:11.453845 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2671 22:57:11.457016 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2672 22:57:11.460410 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2673 22:57:11.460547
2674 22:57:11.460647
2675 22:57:11.460742 ==
2676 22:57:11.463718 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 22:57:11.467174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 22:57:11.467268 ==
2679 22:57:11.467338
2680 22:57:11.467399
2681 22:57:11.470410 TX Vref Scan disable
2682 22:57:11.473584 == TX Byte 0 ==
2683 22:57:11.476914 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2684 22:57:11.480246 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2685 22:57:11.483613 == TX Byte 1 ==
2686 22:57:11.486996 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2687 22:57:11.490309 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2688 22:57:11.490433 ==
2689 22:57:11.493720 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 22:57:11.497351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 22:57:11.497502 ==
2692 22:57:11.510085 TX Vref=22, minBit 7, minWin=24, winSum=403
2693 22:57:11.513439 TX Vref=24, minBit 0, minWin=25, winSum=409
2694 22:57:11.516940 TX Vref=26, minBit 4, minWin=25, winSum=416
2695 22:57:11.519875 TX Vref=28, minBit 10, minWin=25, winSum=420
2696 22:57:11.523566 TX Vref=30, minBit 0, minWin=26, winSum=424
2697 22:57:11.526524 TX Vref=32, minBit 0, minWin=26, winSum=420
2698 22:57:11.533334 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2699 22:57:11.533454
2700 22:57:11.536639 Final TX Range 1 Vref 30
2701 22:57:11.536740
2702 22:57:11.536840 ==
2703 22:57:11.540406 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 22:57:11.543252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 22:57:11.543353 ==
2706 22:57:11.543422
2707 22:57:11.546842
2708 22:57:11.547007 TX Vref Scan disable
2709 22:57:11.550480 == TX Byte 0 ==
2710 22:57:11.553628 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2711 22:57:11.557064 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2712 22:57:11.560415 == TX Byte 1 ==
2713 22:57:11.563769 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2714 22:57:11.566923 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2715 22:57:11.567047
2716 22:57:11.570319 [DATLAT]
2717 22:57:11.570405 Freq=1200, CH0 RK0
2718 22:57:11.570469
2719 22:57:11.573915 DATLAT Default: 0xd
2720 22:57:11.574018 0, 0xFFFF, sum = 0
2721 22:57:11.577067 1, 0xFFFF, sum = 0
2722 22:57:11.577147 2, 0xFFFF, sum = 0
2723 22:57:11.580059 3, 0xFFFF, sum = 0
2724 22:57:11.580150 4, 0xFFFF, sum = 0
2725 22:57:11.583833 5, 0xFFFF, sum = 0
2726 22:57:11.583986 6, 0xFFFF, sum = 0
2727 22:57:11.587260 7, 0xFFFF, sum = 0
2728 22:57:11.587346 8, 0xFFFF, sum = 0
2729 22:57:11.590657 9, 0xFFFF, sum = 0
2730 22:57:11.590772 10, 0xFFFF, sum = 0
2731 22:57:11.593791 11, 0xFFFF, sum = 0
2732 22:57:11.593876 12, 0x0, sum = 1
2733 22:57:11.597215 13, 0x0, sum = 2
2734 22:57:11.597311 14, 0x0, sum = 3
2735 22:57:11.600421 15, 0x0, sum = 4
2736 22:57:11.600536 best_step = 13
2737 22:57:11.600612
2738 22:57:11.600675 ==
2739 22:57:11.603516 Dram Type= 6, Freq= 0, CH_0, rank 0
2740 22:57:11.610625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2741 22:57:11.610795 ==
2742 22:57:11.610916 RX Vref Scan: 1
2743 22:57:11.611023
2744 22:57:11.613904 Set Vref Range= 32 -> 127
2745 22:57:11.613994
2746 22:57:11.617418 RX Vref 32 -> 127, step: 1
2747 22:57:11.617529
2748 22:57:11.620795 RX Delay -13 -> 252, step: 4
2749 22:57:11.620882
2750 22:57:11.620947 Set Vref, RX VrefLevel [Byte0]: 32
2751 22:57:11.624073 [Byte1]: 32
2752 22:57:11.628694
2753 22:57:11.628789 Set Vref, RX VrefLevel [Byte0]: 33
2754 22:57:11.631909 [Byte1]: 33
2755 22:57:11.636362
2756 22:57:11.636456 Set Vref, RX VrefLevel [Byte0]: 34
2757 22:57:11.639585 [Byte1]: 34
2758 22:57:11.644495
2759 22:57:11.644590 Set Vref, RX VrefLevel [Byte0]: 35
2760 22:57:11.647410 [Byte1]: 35
2761 22:57:11.651881
2762 22:57:11.652014 Set Vref, RX VrefLevel [Byte0]: 36
2763 22:57:11.655197 [Byte1]: 36
2764 22:57:11.659744
2765 22:57:11.659837 Set Vref, RX VrefLevel [Byte0]: 37
2766 22:57:11.663574 [Byte1]: 37
2767 22:57:11.667696
2768 22:57:11.667790 Set Vref, RX VrefLevel [Byte0]: 38
2769 22:57:11.671517 [Byte1]: 38
2770 22:57:11.675707
2771 22:57:11.675803 Set Vref, RX VrefLevel [Byte0]: 39
2772 22:57:11.679377 [Byte1]: 39
2773 22:57:11.683656
2774 22:57:11.683767 Set Vref, RX VrefLevel [Byte0]: 40
2775 22:57:11.686663 [Byte1]: 40
2776 22:57:11.691447
2777 22:57:11.691544 Set Vref, RX VrefLevel [Byte0]: 41
2778 22:57:11.694751 [Byte1]: 41
2779 22:57:11.699241
2780 22:57:11.699344 Set Vref, RX VrefLevel [Byte0]: 42
2781 22:57:11.702717 [Byte1]: 42
2782 22:57:11.707635
2783 22:57:11.707735 Set Vref, RX VrefLevel [Byte0]: 43
2784 22:57:11.710346 [Byte1]: 43
2785 22:57:11.715006
2786 22:57:11.715134 Set Vref, RX VrefLevel [Byte0]: 44
2787 22:57:11.718343 [Byte1]: 44
2788 22:57:11.723506
2789 22:57:11.723623 Set Vref, RX VrefLevel [Byte0]: 45
2790 22:57:11.726316 [Byte1]: 45
2791 22:57:11.730869
2792 22:57:11.730969 Set Vref, RX VrefLevel [Byte0]: 46
2793 22:57:11.734072 [Byte1]: 46
2794 22:57:11.739161
2795 22:57:11.739274 Set Vref, RX VrefLevel [Byte0]: 47
2796 22:57:11.742552 [Byte1]: 47
2797 22:57:11.746988
2798 22:57:11.747103 Set Vref, RX VrefLevel [Byte0]: 48
2799 22:57:11.750137 [Byte1]: 48
2800 22:57:11.754377
2801 22:57:11.754503 Set Vref, RX VrefLevel [Byte0]: 49
2802 22:57:11.757790 [Byte1]: 49
2803 22:57:11.762316
2804 22:57:11.762408 Set Vref, RX VrefLevel [Byte0]: 50
2805 22:57:11.766111 [Byte1]: 50
2806 22:57:11.770426
2807 22:57:11.770566 Set Vref, RX VrefLevel [Byte0]: 51
2808 22:57:11.773942 [Byte1]: 51
2809 22:57:11.778465
2810 22:57:11.778557 Set Vref, RX VrefLevel [Byte0]: 52
2811 22:57:11.781265 [Byte1]: 52
2812 22:57:11.785989
2813 22:57:11.786083 Set Vref, RX VrefLevel [Byte0]: 53
2814 22:57:11.789371 [Byte1]: 53
2815 22:57:11.793950
2816 22:57:11.794089 Set Vref, RX VrefLevel [Byte0]: 54
2817 22:57:11.797214 [Byte1]: 54
2818 22:57:11.801995
2819 22:57:11.802118 Set Vref, RX VrefLevel [Byte0]: 55
2820 22:57:11.804982 [Byte1]: 55
2821 22:57:11.810011
2822 22:57:11.810116 Set Vref, RX VrefLevel [Byte0]: 56
2823 22:57:11.813271 [Byte1]: 56
2824 22:57:11.818067
2825 22:57:11.818177 Set Vref, RX VrefLevel [Byte0]: 57
2826 22:57:11.821271 [Byte1]: 57
2827 22:57:11.825995
2828 22:57:11.826106 Set Vref, RX VrefLevel [Byte0]: 58
2829 22:57:11.829190 [Byte1]: 58
2830 22:57:11.833884
2831 22:57:11.833986 Set Vref, RX VrefLevel [Byte0]: 59
2832 22:57:11.836469 [Byte1]: 59
2833 22:57:11.841759
2834 22:57:11.841910 Set Vref, RX VrefLevel [Byte0]: 60
2835 22:57:11.844747 [Byte1]: 60
2836 22:57:11.849537
2837 22:57:11.849625 Set Vref, RX VrefLevel [Byte0]: 61
2838 22:57:11.852907 [Byte1]: 61
2839 22:57:11.857378
2840 22:57:11.857489 Set Vref, RX VrefLevel [Byte0]: 62
2841 22:57:11.860532 [Byte1]: 62
2842 22:57:11.864944
2843 22:57:11.865059 Set Vref, RX VrefLevel [Byte0]: 63
2844 22:57:11.868120 [Byte1]: 63
2845 22:57:11.873358
2846 22:57:11.873471 Set Vref, RX VrefLevel [Byte0]: 64
2847 22:57:11.875982 [Byte1]: 64
2848 22:57:11.881318
2849 22:57:11.883931 Set Vref, RX VrefLevel [Byte0]: 65
2850 22:57:11.884074 [Byte1]: 65
2851 22:57:11.889048
2852 22:57:11.889174 Set Vref, RX VrefLevel [Byte0]: 66
2853 22:57:11.892044 [Byte1]: 66
2854 22:57:11.896454
2855 22:57:11.896551 Set Vref, RX VrefLevel [Byte0]: 67
2856 22:57:11.899683 [Byte1]: 67
2857 22:57:11.904556
2858 22:57:11.904655 Set Vref, RX VrefLevel [Byte0]: 68
2859 22:57:11.907563 [Byte1]: 68
2860 22:57:11.912391
2861 22:57:11.912490 Set Vref, RX VrefLevel [Byte0]: 69
2862 22:57:11.915520 [Byte1]: 69
2863 22:57:11.920180
2864 22:57:11.920275 Set Vref, RX VrefLevel [Byte0]: 70
2865 22:57:11.923437 [Byte1]: 70
2866 22:57:11.928227
2867 22:57:11.928325 Final RX Vref Byte 0 = 55 to rank0
2868 22:57:11.931639 Final RX Vref Byte 1 = 55 to rank0
2869 22:57:11.934868 Final RX Vref Byte 0 = 55 to rank1
2870 22:57:11.938121 Final RX Vref Byte 1 = 55 to rank1==
2871 22:57:11.941826 Dram Type= 6, Freq= 0, CH_0, rank 0
2872 22:57:11.948405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 22:57:11.948519 ==
2874 22:57:11.948610 DQS Delay:
2875 22:57:11.948674 DQS0 = 0, DQS1 = 0
2876 22:57:11.951417 DQM Delay:
2877 22:57:11.951501 DQM0 = 120, DQM1 = 113
2878 22:57:11.955418 DQ Delay:
2879 22:57:11.957939 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2880 22:57:11.961677 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2881 22:57:11.964998 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2882 22:57:11.968159 DQ12 =120, DQ13 =116, DQ14 =126, DQ15 =122
2883 22:57:11.968276
2884 22:57:11.968370
2885 22:57:11.975196 [DQSOSCAuto] RK0, (LSB)MR18= 0x130d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2886 22:57:11.978509 CH0 RK0: MR19=404, MR18=130D
2887 22:57:11.985169 CH0_RK0: MR19=0x404, MR18=0x130D, DQSOSC=402, MR23=63, INC=40, DEC=27
2888 22:57:11.985325
2889 22:57:11.988298 ----->DramcWriteLeveling(PI) begin...
2890 22:57:11.988401 ==
2891 22:57:11.991992 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 22:57:11.995111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 22:57:11.998422 ==
2894 22:57:11.998556 Write leveling (Byte 0): 33 => 33
2895 22:57:12.001918 Write leveling (Byte 1): 28 => 28
2896 22:57:12.004929 DramcWriteLeveling(PI) end<-----
2897 22:57:12.005042
2898 22:57:12.005111 ==
2899 22:57:12.008327 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 22:57:12.011778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 22:57:12.015212 ==
2902 22:57:12.015344 [Gating] SW mode calibration
2903 22:57:12.025216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2904 22:57:12.028936 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2905 22:57:12.031884 0 15 0 | B1->B0 | 3131 2b2b | 1 1 | (1 1) (1 1)
2906 22:57:12.038598 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 22:57:12.041805 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 22:57:12.045470 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 22:57:12.051805 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 22:57:12.055136 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 22:57:12.058613 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 22:57:12.065214 0 15 28 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (1 0)
2913 22:57:12.068626 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2914 22:57:12.071879 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 22:57:12.079038 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 22:57:12.082103 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 22:57:12.085447 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 22:57:12.088840 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 22:57:12.095467 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 22:57:12.098591 1 0 28 | B1->B0 | 3c3c 3939 | 1 1 | (0 0) (0 0)
2921 22:57:12.102006 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 22:57:12.108758 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 22:57:12.112188 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 22:57:12.115317 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 22:57:12.121916 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 22:57:12.125329 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 22:57:12.129023 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 22:57:12.135626 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2929 22:57:12.138712 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2930 22:57:12.142384 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 22:57:12.148898 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 22:57:12.152268 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 22:57:12.156112 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 22:57:12.161929 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 22:57:12.165704 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 22:57:12.169137 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 22:57:12.175141 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 22:57:12.178653 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 22:57:12.182082 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 22:57:12.185738 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 22:57:12.192200 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 22:57:12.195547 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 22:57:12.198749 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 22:57:12.205777 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2945 22:57:12.208827 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2946 22:57:12.212172 Total UI for P1: 0, mck2ui 16
2947 22:57:12.215452 best dqsien dly found for B1: ( 1, 3, 28)
2948 22:57:12.259663 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 22:57:12.260360 Total UI for P1: 0, mck2ui 16
2950 22:57:12.260806 best dqsien dly found for B0: ( 1, 3, 30)
2951 22:57:12.261216 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2952 22:57:12.261614 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2953 22:57:12.261908
2954 22:57:12.262175 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2955 22:57:12.262475 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2956 22:57:12.262730 [Gating] SW calibration Done
2957 22:57:12.262990 ==
2958 22:57:12.263275 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 22:57:12.263544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 22:57:12.263861 ==
2961 22:57:12.264551 RX Vref Scan: 0
2962 22:57:12.265064
2963 22:57:12.265373 RX Vref 0 -> 0, step: 1
2964 22:57:12.266007
2965 22:57:12.267125 RX Delay -40 -> 252, step: 8
2966 22:57:12.268366 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2967 22:57:12.269164 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2968 22:57:12.270110 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2969 22:57:12.275909 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2970 22:57:12.279270 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2971 22:57:12.282980 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2972 22:57:12.285848 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2973 22:57:12.289310 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2974 22:57:12.292860 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2975 22:57:12.299143 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2976 22:57:12.302648 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2977 22:57:12.305976 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2978 22:57:12.309270 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2979 22:57:12.312464 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2980 22:57:12.319194 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2981 22:57:12.322458 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2982 22:57:12.322558 ==
2983 22:57:12.326325 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 22:57:12.329469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 22:57:12.329562 ==
2986 22:57:12.332814 DQS Delay:
2987 22:57:12.332903 DQS0 = 0, DQS1 = 0
2988 22:57:12.332970 DQM Delay:
2989 22:57:12.336243 DQM0 = 122, DQM1 = 113
2990 22:57:12.336404 DQ Delay:
2991 22:57:12.339315 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2992 22:57:12.342887 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2993 22:57:12.346382 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
2994 22:57:12.352649 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2995 22:57:12.352762
2996 22:57:12.352829
2997 22:57:12.352889 ==
2998 22:57:12.355888 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 22:57:12.359310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 22:57:12.359398 ==
3001 22:57:12.359465
3002 22:57:12.359525
3003 22:57:12.362366 TX Vref Scan disable
3004 22:57:12.362456 == TX Byte 0 ==
3005 22:57:12.369591 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3006 22:57:12.372922 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3007 22:57:12.373092 == TX Byte 1 ==
3008 22:57:12.379223 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3009 22:57:12.382627 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3010 22:57:12.382831 ==
3011 22:57:12.386295 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 22:57:12.389236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 22:57:12.389446 ==
3014 22:57:12.402782 TX Vref=22, minBit 1, minWin=25, winSum=412
3015 22:57:12.405863 TX Vref=24, minBit 2, minWin=25, winSum=418
3016 22:57:12.409523 TX Vref=26, minBit 13, minWin=25, winSum=420
3017 22:57:12.412422 TX Vref=28, minBit 1, minWin=26, winSum=424
3018 22:57:12.415673 TX Vref=30, minBit 1, minWin=26, winSum=425
3019 22:57:12.422675 TX Vref=32, minBit 12, minWin=25, winSum=424
3020 22:57:12.425875 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 30
3021 22:57:12.425978
3022 22:57:12.429253 Final TX Range 1 Vref 30
3023 22:57:12.429346
3024 22:57:12.429413 ==
3025 22:57:12.432252 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 22:57:12.436177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 22:57:12.436330 ==
3028 22:57:12.439555
3029 22:57:12.439721
3030 22:57:12.439825 TX Vref Scan disable
3031 22:57:12.442137 == TX Byte 0 ==
3032 22:57:12.446094 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3033 22:57:12.449248 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3034 22:57:12.452601 == TX Byte 1 ==
3035 22:57:12.455566 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3036 22:57:12.458845 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3037 22:57:12.462395
3038 22:57:12.462569 [DATLAT]
3039 22:57:12.462648 Freq=1200, CH0 RK1
3040 22:57:12.462711
3041 22:57:12.465676 DATLAT Default: 0xd
3042 22:57:12.465865 0, 0xFFFF, sum = 0
3043 22:57:12.468847 1, 0xFFFF, sum = 0
3044 22:57:12.469050 2, 0xFFFF, sum = 0
3045 22:57:12.472223 3, 0xFFFF, sum = 0
3046 22:57:12.475604 4, 0xFFFF, sum = 0
3047 22:57:12.475769 5, 0xFFFF, sum = 0
3048 22:57:12.478957 6, 0xFFFF, sum = 0
3049 22:57:12.479092 7, 0xFFFF, sum = 0
3050 22:57:12.482439 8, 0xFFFF, sum = 0
3051 22:57:12.482560 9, 0xFFFF, sum = 0
3052 22:57:12.485444 10, 0xFFFF, sum = 0
3053 22:57:12.485597 11, 0xFFFF, sum = 0
3054 22:57:12.488904 12, 0x0, sum = 1
3055 22:57:12.489041 13, 0x0, sum = 2
3056 22:57:12.492141 14, 0x0, sum = 3
3057 22:57:12.492327 15, 0x0, sum = 4
3058 22:57:12.492435 best_step = 13
3059 22:57:12.492534
3060 22:57:12.495683 ==
3061 22:57:12.499343 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 22:57:12.502715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 22:57:12.502897 ==
3064 22:57:12.503006 RX Vref Scan: 0
3065 22:57:12.503072
3066 22:57:12.506046 RX Vref 0 -> 0, step: 1
3067 22:57:12.506178
3068 22:57:12.508971 RX Delay -13 -> 252, step: 4
3069 22:57:12.512886 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3070 22:57:12.519293 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3071 22:57:12.522351 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3072 22:57:12.525875 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3073 22:57:12.528886 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3074 22:57:12.532031 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3075 22:57:12.535544 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3076 22:57:12.542435 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3077 22:57:12.545428 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3078 22:57:12.548772 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3079 22:57:12.552558 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3080 22:57:12.555508 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3081 22:57:12.562190 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3082 22:57:12.565672 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3083 22:57:12.568817 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3084 22:57:12.572144 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3085 22:57:12.572239 ==
3086 22:57:12.576172 Dram Type= 6, Freq= 0, CH_0, rank 1
3087 22:57:12.582676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 22:57:12.582880 ==
3089 22:57:12.583000 DQS Delay:
3090 22:57:12.585952 DQS0 = 0, DQS1 = 0
3091 22:57:12.586086 DQM Delay:
3092 22:57:12.588785 DQM0 = 121, DQM1 = 111
3093 22:57:12.588917 DQ Delay:
3094 22:57:12.592537 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3095 22:57:12.595893 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3096 22:57:12.599343 DQ8 =102, DQ9 =100, DQ10 =110, DQ11 =104
3097 22:57:12.601894 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3098 22:57:12.602055
3099 22:57:12.602160
3100 22:57:12.612308 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3101 22:57:12.612494 CH0 RK1: MR19=403, MR18=DEE
3102 22:57:12.619055 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3103 22:57:12.622815 [RxdqsGatingPostProcess] freq 1200
3104 22:57:12.628858 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3105 22:57:12.632291 best DQS0 dly(2T, 0.5T) = (0, 11)
3106 22:57:12.635944 best DQS1 dly(2T, 0.5T) = (0, 11)
3107 22:57:12.638849 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3108 22:57:12.642527 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3109 22:57:12.642741 best DQS0 dly(2T, 0.5T) = (0, 11)
3110 22:57:12.645770 best DQS1 dly(2T, 0.5T) = (0, 11)
3111 22:57:12.648891 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3112 22:57:12.652749 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3113 22:57:12.655859 Pre-setting of DQS Precalculation
3114 22:57:12.662608 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3115 22:57:12.662730 ==
3116 22:57:12.665819 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 22:57:12.669179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 22:57:12.669275 ==
3119 22:57:12.675842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 22:57:12.679534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3121 22:57:12.689341 [CA 0] Center 37 (7~68) winsize 62
3122 22:57:12.692410 [CA 1] Center 37 (7~68) winsize 62
3123 22:57:12.695614 [CA 2] Center 34 (4~65) winsize 62
3124 22:57:12.699075 [CA 3] Center 34 (4~64) winsize 61
3125 22:57:12.702451 [CA 4] Center 34 (4~64) winsize 61
3126 22:57:12.705739 [CA 5] Center 33 (3~63) winsize 61
3127 22:57:12.705830
3128 22:57:12.709177 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3129 22:57:12.709267
3130 22:57:12.712778 [CATrainingPosCal] consider 1 rank data
3131 22:57:12.715193 u2DelayCellTimex100 = 270/100 ps
3132 22:57:12.719225 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3133 22:57:12.722044 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 22:57:12.729136 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3135 22:57:12.732348 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 22:57:12.735777 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3137 22:57:12.739124 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3138 22:57:12.739214
3139 22:57:12.742240 CA PerBit enable=1, Macro0, CA PI delay=33
3140 22:57:12.742327
3141 22:57:12.745530 [CBTSetCACLKResult] CA Dly = 33
3142 22:57:12.745624 CS Dly: 8 (0~39)
3143 22:57:12.745693 ==
3144 22:57:12.749160 Dram Type= 6, Freq= 0, CH_1, rank 1
3145 22:57:12.755419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 22:57:12.755528 ==
3147 22:57:12.759314 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3148 22:57:12.765703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3149 22:57:12.774761 [CA 0] Center 37 (7~68) winsize 62
3150 22:57:12.777994 [CA 1] Center 37 (7~68) winsize 62
3151 22:57:12.781516 [CA 2] Center 35 (5~65) winsize 61
3152 22:57:12.784496 [CA 3] Center 35 (5~65) winsize 61
3153 22:57:12.788061 [CA 4] Center 34 (4~65) winsize 62
3154 22:57:12.790957 [CA 5] Center 34 (4~64) winsize 61
3155 22:57:12.791046
3156 22:57:12.794510 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3157 22:57:12.794596
3158 22:57:12.797909 [CATrainingPosCal] consider 2 rank data
3159 22:57:12.801229 u2DelayCellTimex100 = 270/100 ps
3160 22:57:12.804739 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3161 22:57:12.808148 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3162 22:57:12.814625 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3163 22:57:12.817874 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3164 22:57:12.821449 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3165 22:57:12.824696 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3166 22:57:12.824792
3167 22:57:12.827962 CA PerBit enable=1, Macro0, CA PI delay=33
3168 22:57:12.828079
3169 22:57:12.831019 [CBTSetCACLKResult] CA Dly = 33
3170 22:57:12.831106 CS Dly: 8 (0~40)
3171 22:57:12.831173
3172 22:57:12.834538 ----->DramcWriteLeveling(PI) begin...
3173 22:57:12.838103 ==
3174 22:57:12.841367 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 22:57:12.844255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 22:57:12.844346 ==
3177 22:57:12.847784 Write leveling (Byte 0): 27 => 27
3178 22:57:12.850969 Write leveling (Byte 1): 27 => 27
3179 22:57:12.854180 DramcWriteLeveling(PI) end<-----
3180 22:57:12.854270
3181 22:57:12.854337 ==
3182 22:57:12.858219 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 22:57:12.860943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 22:57:12.861029 ==
3185 22:57:12.864256 [Gating] SW mode calibration
3186 22:57:12.871241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3187 22:57:12.874375 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3188 22:57:12.881033 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 22:57:12.884590 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 22:57:12.887622 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 22:57:12.894473 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 22:57:12.898006 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 22:57:12.900917 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 22:57:12.907928 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
3195 22:57:12.911217 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 22:57:12.914406 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 22:57:12.921112 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 22:57:12.924474 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 22:57:12.927834 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 22:57:12.934361 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 22:57:12.937622 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3202 22:57:12.940880 1 0 24 | B1->B0 | 3434 4242 | 1 0 | (0 0) (0 0)
3203 22:57:12.947605 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 22:57:12.951326 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 22:57:12.954358 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 22:57:12.961101 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 22:57:12.964439 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 22:57:12.967517 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 22:57:12.970776 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 22:57:12.977817 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3211 22:57:12.980937 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3212 22:57:12.984216 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 22:57:12.991303 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 22:57:12.994770 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 22:57:12.997912 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 22:57:13.004877 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 22:57:13.007814 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 22:57:13.011254 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 22:57:13.018078 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 22:57:13.020887 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 22:57:13.024586 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 22:57:13.030961 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 22:57:13.034255 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 22:57:13.037372 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 22:57:13.044373 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 22:57:13.047592 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3227 22:57:13.050919 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3228 22:57:13.058143 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 22:57:13.058294 Total UI for P1: 0, mck2ui 16
3230 22:57:13.060704 best dqsien dly found for B0: ( 1, 3, 26)
3231 22:57:13.064172 Total UI for P1: 0, mck2ui 16
3232 22:57:13.067479 best dqsien dly found for B1: ( 1, 3, 26)
3233 22:57:13.071444 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3234 22:57:13.078160 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3235 22:57:13.078270
3236 22:57:13.081262 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3237 22:57:13.084535 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3238 22:57:13.087697 [Gating] SW calibration Done
3239 22:57:13.087812 ==
3240 22:57:13.090998 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 22:57:13.094536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 22:57:13.094649 ==
3243 22:57:13.094751 RX Vref Scan: 0
3244 22:57:13.097824
3245 22:57:13.097935 RX Vref 0 -> 0, step: 1
3246 22:57:13.098034
3247 22:57:13.101120 RX Delay -40 -> 252, step: 8
3248 22:57:13.104220 iDelay=200, Bit 0, Center 127 (56 ~ 199) 144
3249 22:57:13.107560 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3250 22:57:13.114448 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3251 22:57:13.117791 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3252 22:57:13.121490 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3253 22:57:13.124882 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3254 22:57:13.127693 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3255 22:57:13.131495 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3256 22:57:13.138057 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3257 22:57:13.141489 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3258 22:57:13.144567 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3259 22:57:13.147927 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3260 22:57:13.151695 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3261 22:57:13.158600 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3262 22:57:13.161455 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3263 22:57:13.164725 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3264 22:57:13.164818 ==
3265 22:57:13.168232 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 22:57:13.172086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 22:57:13.172181 ==
3268 22:57:13.174825 DQS Delay:
3269 22:57:13.174909 DQS0 = 0, DQS1 = 0
3270 22:57:13.178288 DQM Delay:
3271 22:57:13.178376 DQM0 = 121, DQM1 = 116
3272 22:57:13.178444 DQ Delay:
3273 22:57:13.181503 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119
3274 22:57:13.188538 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3275 22:57:13.191602 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3276 22:57:13.194848 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3277 22:57:13.194947
3278 22:57:13.195017
3279 22:57:13.195078 ==
3280 22:57:13.198306 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 22:57:13.202188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 22:57:13.202296 ==
3283 22:57:13.202394
3284 22:57:13.202487
3285 22:57:13.205452 TX Vref Scan disable
3286 22:57:13.208643 == TX Byte 0 ==
3287 22:57:13.212129 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3288 22:57:13.215555 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3289 22:57:13.218725 == TX Byte 1 ==
3290 22:57:13.221544 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3291 22:57:13.225270 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3292 22:57:13.225354 ==
3293 22:57:13.228601 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 22:57:13.232164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 22:57:13.232279 ==
3296 22:57:13.244757 TX Vref=22, minBit 9, minWin=25, winSum=413
3297 22:57:13.247842 TX Vref=24, minBit 9, minWin=24, winSum=415
3298 22:57:13.251550 TX Vref=26, minBit 9, minWin=25, winSum=422
3299 22:57:13.254950 TX Vref=28, minBit 9, minWin=25, winSum=427
3300 22:57:13.257681 TX Vref=30, minBit 10, minWin=25, winSum=429
3301 22:57:13.264916 TX Vref=32, minBit 10, minWin=26, winSum=428
3302 22:57:13.268369 [TxChooseVref] Worse bit 10, Min win 26, Win sum 428, Final Vref 32
3303 22:57:13.268492
3304 22:57:13.271150 Final TX Range 1 Vref 32
3305 22:57:13.271265
3306 22:57:13.271358 ==
3307 22:57:13.274736 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 22:57:13.278313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 22:57:13.281181 ==
3310 22:57:13.281264
3311 22:57:13.281360
3312 22:57:13.281423 TX Vref Scan disable
3313 22:57:13.284653 == TX Byte 0 ==
3314 22:57:13.287570 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3315 22:57:13.291560 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3316 22:57:13.294751 == TX Byte 1 ==
3317 22:57:13.297950 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3318 22:57:13.301615 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3319 22:57:13.304964
3320 22:57:13.305052 [DATLAT]
3321 22:57:13.305117 Freq=1200, CH1 RK0
3322 22:57:13.305178
3323 22:57:13.308238 DATLAT Default: 0xd
3324 22:57:13.308322 0, 0xFFFF, sum = 0
3325 22:57:13.311393 1, 0xFFFF, sum = 0
3326 22:57:13.311485 2, 0xFFFF, sum = 0
3327 22:57:13.314504 3, 0xFFFF, sum = 0
3328 22:57:13.314593 4, 0xFFFF, sum = 0
3329 22:57:13.318378 5, 0xFFFF, sum = 0
3330 22:57:13.318513 6, 0xFFFF, sum = 0
3331 22:57:13.321689 7, 0xFFFF, sum = 0
3332 22:57:13.324987 8, 0xFFFF, sum = 0
3333 22:57:13.325106 9, 0xFFFF, sum = 0
3334 22:57:13.328171 10, 0xFFFF, sum = 0
3335 22:57:13.328268 11, 0xFFFF, sum = 0
3336 22:57:13.331510 12, 0x0, sum = 1
3337 22:57:13.331607 13, 0x0, sum = 2
3338 22:57:13.334719 14, 0x0, sum = 3
3339 22:57:13.334817 15, 0x0, sum = 4
3340 22:57:13.334888 best_step = 13
3341 22:57:13.334963
3342 22:57:13.337980 ==
3343 22:57:13.341071 Dram Type= 6, Freq= 0, CH_1, rank 0
3344 22:57:13.344633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3345 22:57:13.344726 ==
3346 22:57:13.344792 RX Vref Scan: 1
3347 22:57:13.344854
3348 22:57:13.347855 Set Vref Range= 32 -> 127
3349 22:57:13.347932
3350 22:57:13.351196 RX Vref 32 -> 127, step: 1
3351 22:57:13.351272
3352 22:57:13.354988 RX Delay -5 -> 252, step: 4
3353 22:57:13.355077
3354 22:57:13.358005 Set Vref, RX VrefLevel [Byte0]: 32
3355 22:57:13.361363 [Byte1]: 32
3356 22:57:13.361456
3357 22:57:13.364859 Set Vref, RX VrefLevel [Byte0]: 33
3358 22:57:13.367995 [Byte1]: 33
3359 22:57:13.368089
3360 22:57:13.371592 Set Vref, RX VrefLevel [Byte0]: 34
3361 22:57:13.374855 [Byte1]: 34
3362 22:57:13.378910
3363 22:57:13.379005 Set Vref, RX VrefLevel [Byte0]: 35
3364 22:57:13.382110 [Byte1]: 35
3365 22:57:13.386663
3366 22:57:13.386758 Set Vref, RX VrefLevel [Byte0]: 36
3367 22:57:13.389609 [Byte1]: 36
3368 22:57:13.394453
3369 22:57:13.394545 Set Vref, RX VrefLevel [Byte0]: 37
3370 22:57:13.397808 [Byte1]: 37
3371 22:57:13.402256
3372 22:57:13.402352 Set Vref, RX VrefLevel [Byte0]: 38
3373 22:57:13.405275 [Byte1]: 38
3374 22:57:13.410212
3375 22:57:13.410315 Set Vref, RX VrefLevel [Byte0]: 39
3376 22:57:13.413436 [Byte1]: 39
3377 22:57:13.418153
3378 22:57:13.418245 Set Vref, RX VrefLevel [Byte0]: 40
3379 22:57:13.421664 [Byte1]: 40
3380 22:57:13.426186
3381 22:57:13.426275 Set Vref, RX VrefLevel [Byte0]: 41
3382 22:57:13.428675 [Byte1]: 41
3383 22:57:13.434214
3384 22:57:13.434318 Set Vref, RX VrefLevel [Byte0]: 42
3385 22:57:13.436695 [Byte1]: 42
3386 22:57:13.441862
3387 22:57:13.441955 Set Vref, RX VrefLevel [Byte0]: 43
3388 22:57:13.445001 [Byte1]: 43
3389 22:57:13.449827
3390 22:57:13.449924 Set Vref, RX VrefLevel [Byte0]: 44
3391 22:57:13.452878 [Byte1]: 44
3392 22:57:13.457040
3393 22:57:13.457132 Set Vref, RX VrefLevel [Byte0]: 45
3394 22:57:13.460965 [Byte1]: 45
3395 22:57:13.465252
3396 22:57:13.465348 Set Vref, RX VrefLevel [Byte0]: 46
3397 22:57:13.468730 [Byte1]: 46
3398 22:57:13.473054
3399 22:57:13.473150 Set Vref, RX VrefLevel [Byte0]: 47
3400 22:57:13.476330 [Byte1]: 47
3401 22:57:13.481041
3402 22:57:13.481135 Set Vref, RX VrefLevel [Byte0]: 48
3403 22:57:13.484235 [Byte1]: 48
3404 22:57:13.488622
3405 22:57:13.488713 Set Vref, RX VrefLevel [Byte0]: 49
3406 22:57:13.492336 [Byte1]: 49
3407 22:57:13.496435
3408 22:57:13.496529 Set Vref, RX VrefLevel [Byte0]: 50
3409 22:57:13.499841 [Byte1]: 50
3410 22:57:13.504427
3411 22:57:13.504523 Set Vref, RX VrefLevel [Byte0]: 51
3412 22:57:13.507425 [Byte1]: 51
3413 22:57:13.512237
3414 22:57:13.512339 Set Vref, RX VrefLevel [Byte0]: 52
3415 22:57:13.515397 [Byte1]: 52
3416 22:57:13.519895
3417 22:57:13.519995 Set Vref, RX VrefLevel [Byte0]: 53
3418 22:57:13.523401 [Byte1]: 53
3419 22:57:13.527963
3420 22:57:13.528062 Set Vref, RX VrefLevel [Byte0]: 54
3421 22:57:13.531072 [Byte1]: 54
3422 22:57:13.535590
3423 22:57:13.535689 Set Vref, RX VrefLevel [Byte0]: 55
3424 22:57:13.539299 [Byte1]: 55
3425 22:57:13.543770
3426 22:57:13.543865 Set Vref, RX VrefLevel [Byte0]: 56
3427 22:57:13.546675 [Byte1]: 56
3428 22:57:13.551194
3429 22:57:13.551293 Set Vref, RX VrefLevel [Byte0]: 57
3430 22:57:13.554938 [Byte1]: 57
3431 22:57:13.559275
3432 22:57:13.559368 Set Vref, RX VrefLevel [Byte0]: 58
3433 22:57:13.562680 [Byte1]: 58
3434 22:57:13.567444
3435 22:57:13.567533 Set Vref, RX VrefLevel [Byte0]: 59
3436 22:57:13.570130 [Byte1]: 59
3437 22:57:13.574872
3438 22:57:13.574964 Set Vref, RX VrefLevel [Byte0]: 60
3439 22:57:13.577941 [Byte1]: 60
3440 22:57:13.582724
3441 22:57:13.582836 Set Vref, RX VrefLevel [Byte0]: 61
3442 22:57:13.585991 [Byte1]: 61
3443 22:57:13.590642
3444 22:57:13.590745 Set Vref, RX VrefLevel [Byte0]: 62
3445 22:57:13.593841 [Byte1]: 62
3446 22:57:13.598850
3447 22:57:13.598951 Set Vref, RX VrefLevel [Byte0]: 63
3448 22:57:13.602070 [Byte1]: 63
3449 22:57:13.606059
3450 22:57:13.606150 Set Vref, RX VrefLevel [Byte0]: 64
3451 22:57:13.609806 [Byte1]: 64
3452 22:57:13.614515
3453 22:57:13.614616 Set Vref, RX VrefLevel [Byte0]: 65
3454 22:57:13.617769 [Byte1]: 65
3455 22:57:13.622218
3456 22:57:13.622310 Set Vref, RX VrefLevel [Byte0]: 66
3457 22:57:13.625337 [Byte1]: 66
3458 22:57:13.630226
3459 22:57:13.630330 Set Vref, RX VrefLevel [Byte0]: 67
3460 22:57:13.632920 [Byte1]: 67
3461 22:57:13.637506
3462 22:57:13.637602 Final RX Vref Byte 0 = 53 to rank0
3463 22:57:13.641185 Final RX Vref Byte 1 = 53 to rank0
3464 22:57:13.644607 Final RX Vref Byte 0 = 53 to rank1
3465 22:57:13.647876 Final RX Vref Byte 1 = 53 to rank1==
3466 22:57:13.651003 Dram Type= 6, Freq= 0, CH_1, rank 0
3467 22:57:13.654768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 22:57:13.657763 ==
3469 22:57:13.657857 DQS Delay:
3470 22:57:13.657924 DQS0 = 0, DQS1 = 0
3471 22:57:13.661502 DQM Delay:
3472 22:57:13.661588 DQM0 = 120, DQM1 = 117
3473 22:57:13.664664 DQ Delay:
3474 22:57:13.668120 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3475 22:57:13.671671 DQ4 =120, DQ5 =130, DQ6 =128, DQ7 =120
3476 22:57:13.674807 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3477 22:57:13.678030 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3478 22:57:13.678118
3479 22:57:13.678183
3480 22:57:13.684412 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3481 22:57:13.687941 CH1 RK0: MR19=404, MR18=114
3482 22:57:13.694496 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3483 22:57:13.694608
3484 22:57:13.698254 ----->DramcWriteLeveling(PI) begin...
3485 22:57:13.698348 ==
3486 22:57:13.701417 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 22:57:13.704694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 22:57:13.704785 ==
3489 22:57:13.708107 Write leveling (Byte 0): 25 => 25
3490 22:57:13.711303 Write leveling (Byte 1): 28 => 28
3491 22:57:13.714676 DramcWriteLeveling(PI) end<-----
3492 22:57:13.714769
3493 22:57:13.714837 ==
3494 22:57:13.718108 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 22:57:13.721381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 22:57:13.724775 ==
3497 22:57:13.724863 [Gating] SW mode calibration
3498 22:57:13.731303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3499 22:57:13.738408 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3500 22:57:13.741657 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 22:57:13.747834 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 22:57:13.751481 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 22:57:13.755005 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 22:57:13.761281 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 22:57:13.764514 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3506 22:57:13.767652 0 15 24 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
3507 22:57:13.774859 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3508 22:57:13.778399 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 22:57:13.781865 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 22:57:13.787903 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 22:57:13.791169 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 22:57:13.794330 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 22:57:13.801128 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3514 22:57:13.805132 1 0 24 | B1->B0 | 3c3c 2525 | 0 0 | (1 1) (0 0)
3515 22:57:13.808190 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 22:57:13.811342 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 22:57:13.818107 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 22:57:13.821262 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 22:57:13.824408 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 22:57:13.831140 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 22:57:13.834637 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3522 22:57:13.837905 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3523 22:57:13.844664 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3524 22:57:13.847884 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 22:57:13.851533 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 22:57:13.857431 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 22:57:13.861435 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 22:57:13.864598 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 22:57:13.871121 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 22:57:13.874464 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 22:57:13.877432 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 22:57:13.884297 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 22:57:13.887856 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 22:57:13.891089 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 22:57:13.897799 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 22:57:13.900944 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 22:57:13.904180 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3538 22:57:13.910918 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3539 22:57:13.913929 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3540 22:57:13.917624 Total UI for P1: 0, mck2ui 16
3541 22:57:13.920755 best dqsien dly found for B1: ( 1, 3, 22)
3542 22:57:13.924270 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 22:57:13.927387 Total UI for P1: 0, mck2ui 16
3544 22:57:13.930900 best dqsien dly found for B0: ( 1, 3, 28)
3545 22:57:13.934126 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3546 22:57:13.937509 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3547 22:57:13.937607
3548 22:57:13.941033 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3549 22:57:13.947507 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3550 22:57:13.947607 [Gating] SW calibration Done
3551 22:57:13.947674 ==
3552 22:57:13.950545 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 22:57:13.957297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 22:57:13.957404 ==
3555 22:57:13.957472 RX Vref Scan: 0
3556 22:57:13.957533
3557 22:57:13.960808 RX Vref 0 -> 0, step: 1
3558 22:57:13.960898
3559 22:57:13.963901 RX Delay -40 -> 252, step: 8
3560 22:57:13.967116 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3561 22:57:13.970658 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3562 22:57:13.974168 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3563 22:57:13.980350 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3564 22:57:13.983583 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3565 22:57:13.986647 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3566 22:57:13.990216 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3567 22:57:13.993245 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3568 22:57:14.000057 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3569 22:57:14.003502 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3570 22:57:14.006558 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3571 22:57:14.010410 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3572 22:57:14.013320 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3573 22:57:14.019985 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3574 22:57:14.023633 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3575 22:57:14.026900 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3576 22:57:14.026991 ==
3577 22:57:14.029959 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 22:57:14.033417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 22:57:14.036499 ==
3580 22:57:14.036592 DQS Delay:
3581 22:57:14.036657 DQS0 = 0, DQS1 = 0
3582 22:57:14.040124 DQM Delay:
3583 22:57:14.040238 DQM0 = 122, DQM1 = 117
3584 22:57:14.043583 DQ Delay:
3585 22:57:14.046940 DQ0 =127, DQ1 =119, DQ2 =107, DQ3 =119
3586 22:57:14.049757 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3587 22:57:14.053503 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3588 22:57:14.056311 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3589 22:57:14.056408
3590 22:57:14.056480
3591 22:57:14.056541 ==
3592 22:57:14.059587 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 22:57:14.063232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 22:57:14.063353 ==
3595 22:57:14.063450
3596 22:57:14.066297
3597 22:57:14.066415 TX Vref Scan disable
3598 22:57:14.070288 == TX Byte 0 ==
3599 22:57:14.073020 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3600 22:57:14.076379 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3601 22:57:14.079727 == TX Byte 1 ==
3602 22:57:14.083172 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3603 22:57:14.086440 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3604 22:57:14.086561 ==
3605 22:57:14.089666 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 22:57:14.096459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 22:57:14.096564 ==
3608 22:57:14.106745 TX Vref=22, minBit 1, minWin=25, winSum=417
3609 22:57:14.110159 TX Vref=24, minBit 10, minWin=25, winSum=423
3610 22:57:14.113518 TX Vref=26, minBit 8, minWin=26, winSum=431
3611 22:57:14.116839 TX Vref=28, minBit 2, minWin=26, winSum=434
3612 22:57:14.120144 TX Vref=30, minBit 2, minWin=26, winSum=435
3613 22:57:14.126614 TX Vref=32, minBit 9, minWin=26, winSum=433
3614 22:57:14.130000 [TxChooseVref] Worse bit 2, Min win 26, Win sum 435, Final Vref 30
3615 22:57:14.130103
3616 22:57:14.133683 Final TX Range 1 Vref 30
3617 22:57:14.133807
3618 22:57:14.133908 ==
3619 22:57:14.136588 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 22:57:14.139659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 22:57:14.143212 ==
3622 22:57:14.143340
3623 22:57:14.143442
3624 22:57:14.143535 TX Vref Scan disable
3625 22:57:14.147240 == TX Byte 0 ==
3626 22:57:14.149871 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3627 22:57:14.153318 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3628 22:57:14.156591 == TX Byte 1 ==
3629 22:57:14.160024 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3630 22:57:14.163378 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3631 22:57:14.166999
3632 22:57:14.167115 [DATLAT]
3633 22:57:14.167216 Freq=1200, CH1 RK1
3634 22:57:14.167312
3635 22:57:14.170159 DATLAT Default: 0xd
3636 22:57:14.170267 0, 0xFFFF, sum = 0
3637 22:57:14.173564 1, 0xFFFF, sum = 0
3638 22:57:14.173652 2, 0xFFFF, sum = 0
3639 22:57:14.176799 3, 0xFFFF, sum = 0
3640 22:57:14.176891 4, 0xFFFF, sum = 0
3641 22:57:14.180080 5, 0xFFFF, sum = 0
3642 22:57:14.183532 6, 0xFFFF, sum = 0
3643 22:57:14.183627 7, 0xFFFF, sum = 0
3644 22:57:14.186387 8, 0xFFFF, sum = 0
3645 22:57:14.186474 9, 0xFFFF, sum = 0
3646 22:57:14.189972 10, 0xFFFF, sum = 0
3647 22:57:14.190060 11, 0xFFFF, sum = 0
3648 22:57:14.193216 12, 0x0, sum = 1
3649 22:57:14.193304 13, 0x0, sum = 2
3650 22:57:14.196741 14, 0x0, sum = 3
3651 22:57:14.196838 15, 0x0, sum = 4
3652 22:57:14.196907 best_step = 13
3653 22:57:14.200015
3654 22:57:14.200100 ==
3655 22:57:14.203239 Dram Type= 6, Freq= 0, CH_1, rank 1
3656 22:57:14.206569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3657 22:57:14.206659 ==
3658 22:57:14.206727 RX Vref Scan: 0
3659 22:57:14.206788
3660 22:57:14.209793 RX Vref 0 -> 0, step: 1
3661 22:57:14.209879
3662 22:57:14.213309 RX Delay -5 -> 252, step: 4
3663 22:57:14.216581 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3664 22:57:14.223130 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3665 22:57:14.226509 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3666 22:57:14.230084 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3667 22:57:14.233267 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3668 22:57:14.236507 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3669 22:57:14.239985 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3670 22:57:14.246666 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3671 22:57:14.249705 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3672 22:57:14.253479 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3673 22:57:14.256284 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3674 22:57:14.263130 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3675 22:57:14.266569 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3676 22:57:14.269893 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3677 22:57:14.273069 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3678 22:57:14.276539 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3679 22:57:14.279788 ==
3680 22:57:14.279882 Dram Type= 6, Freq= 0, CH_1, rank 1
3681 22:57:14.286815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3682 22:57:14.286923 ==
3683 22:57:14.286990 DQS Delay:
3684 22:57:14.290138 DQS0 = 0, DQS1 = 0
3685 22:57:14.290224 DQM Delay:
3686 22:57:14.292867 DQM0 = 120, DQM1 = 118
3687 22:57:14.292964 DQ Delay:
3688 22:57:14.296248 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3689 22:57:14.299829 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3690 22:57:14.303257 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3691 22:57:14.306345 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3692 22:57:14.306438
3693 22:57:14.306535
3694 22:57:14.316208 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3695 22:57:14.316335 CH1 RK1: MR19=403, MR18=13F1
3696 22:57:14.322934 CH1_RK1: MR19=0x403, MR18=0x13F1, DQSOSC=402, MR23=63, INC=40, DEC=27
3697 22:57:14.326283 [RxdqsGatingPostProcess] freq 1200
3698 22:57:14.332548 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3699 22:57:14.336512 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 22:57:14.339416 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 22:57:14.342619 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 22:57:14.345797 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 22:57:14.349473 best DQS0 dly(2T, 0.5T) = (0, 11)
3704 22:57:14.353002 best DQS1 dly(2T, 0.5T) = (0, 11)
3705 22:57:14.356231 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3706 22:57:14.359556 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3707 22:57:14.359705 Pre-setting of DQS Precalculation
3708 22:57:14.366026 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3709 22:57:14.372530 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3710 22:57:14.379161 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3711 22:57:14.379315
3712 22:57:14.379423
3713 22:57:14.382427 [Calibration Summary] 2400 Mbps
3714 22:57:14.385867 CH 0, Rank 0
3715 22:57:14.385952 SW Impedance : PASS
3716 22:57:14.388991 DUTY Scan : NO K
3717 22:57:14.392810 ZQ Calibration : PASS
3718 22:57:14.392896 Jitter Meter : NO K
3719 22:57:14.395584 CBT Training : PASS
3720 22:57:14.398978 Write leveling : PASS
3721 22:57:14.399168 RX DQS gating : PASS
3722 22:57:14.402380 RX DQ/DQS(RDDQC) : PASS
3723 22:57:14.406248 TX DQ/DQS : PASS
3724 22:57:14.406371 RX DATLAT : PASS
3725 22:57:14.409372 RX DQ/DQS(Engine): PASS
3726 22:57:14.409485 TX OE : NO K
3727 22:57:14.412183 All Pass.
3728 22:57:14.412297
3729 22:57:14.412391 CH 0, Rank 1
3730 22:57:14.415411 SW Impedance : PASS
3731 22:57:14.415561 DUTY Scan : NO K
3732 22:57:14.419240 ZQ Calibration : PASS
3733 22:57:14.422116 Jitter Meter : NO K
3734 22:57:14.422208 CBT Training : PASS
3735 22:57:14.425665 Write leveling : PASS
3736 22:57:14.428871 RX DQS gating : PASS
3737 22:57:14.428982 RX DQ/DQS(RDDQC) : PASS
3738 22:57:14.432659 TX DQ/DQS : PASS
3739 22:57:14.435677 RX DATLAT : PASS
3740 22:57:14.435768 RX DQ/DQS(Engine): PASS
3741 22:57:14.438937 TX OE : NO K
3742 22:57:14.439022 All Pass.
3743 22:57:14.439087
3744 22:57:14.442248 CH 1, Rank 0
3745 22:57:14.442331 SW Impedance : PASS
3746 22:57:14.445566 DUTY Scan : NO K
3747 22:57:14.449049 ZQ Calibration : PASS
3748 22:57:14.449133 Jitter Meter : NO K
3749 22:57:14.452187 CBT Training : PASS
3750 22:57:14.456123 Write leveling : PASS
3751 22:57:14.456211 RX DQS gating : PASS
3752 22:57:14.458901 RX DQ/DQS(RDDQC) : PASS
3753 22:57:14.462263 TX DQ/DQS : PASS
3754 22:57:14.462348 RX DATLAT : PASS
3755 22:57:14.465375 RX DQ/DQS(Engine): PASS
3756 22:57:14.465485 TX OE : NO K
3757 22:57:14.468506 All Pass.
3758 22:57:14.468594
3759 22:57:14.468660 CH 1, Rank 1
3760 22:57:14.471871 SW Impedance : PASS
3761 22:57:14.471976 DUTY Scan : NO K
3762 22:57:14.475542 ZQ Calibration : PASS
3763 22:57:14.478456 Jitter Meter : NO K
3764 22:57:14.478539 CBT Training : PASS
3765 22:57:14.481788 Write leveling : PASS
3766 22:57:14.485483 RX DQS gating : PASS
3767 22:57:14.485575 RX DQ/DQS(RDDQC) : PASS
3768 22:57:14.488284 TX DQ/DQS : PASS
3769 22:57:14.491924 RX DATLAT : PASS
3770 22:57:14.492045 RX DQ/DQS(Engine): PASS
3771 22:57:14.495209 TX OE : NO K
3772 22:57:14.495300 All Pass.
3773 22:57:14.495368
3774 22:57:14.498368 DramC Write-DBI off
3775 22:57:14.502057 PER_BANK_REFRESH: Hybrid Mode
3776 22:57:14.502146 TX_TRACKING: ON
3777 22:57:14.511928 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3778 22:57:14.515068 [FAST_K] Save calibration result to emmc
3779 22:57:14.518577 dramc_set_vcore_voltage set vcore to 650000
3780 22:57:14.521665 Read voltage for 600, 5
3781 22:57:14.521752 Vio18 = 0
3782 22:57:14.521818 Vcore = 650000
3783 22:57:14.525420 Vdram = 0
3784 22:57:14.525504 Vddq = 0
3785 22:57:14.525570 Vmddr = 0
3786 22:57:14.531730 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3787 22:57:14.535337 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3788 22:57:14.538502 MEM_TYPE=3, freq_sel=19
3789 22:57:14.542172 sv_algorithm_assistance_LP4_1600
3790 22:57:14.545546 ============ PULL DRAM RESETB DOWN ============
3791 22:57:14.548900 ========== PULL DRAM RESETB DOWN end =========
3792 22:57:14.555478 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3793 22:57:14.558655 ===================================
3794 22:57:14.558752 LPDDR4 DRAM CONFIGURATION
3795 22:57:14.561536 ===================================
3796 22:57:14.565603 EX_ROW_EN[0] = 0x0
3797 22:57:14.568453 EX_ROW_EN[1] = 0x0
3798 22:57:14.568540 LP4Y_EN = 0x0
3799 22:57:14.571682 WORK_FSP = 0x0
3800 22:57:14.571775 WL = 0x2
3801 22:57:14.575295 RL = 0x2
3802 22:57:14.575380 BL = 0x2
3803 22:57:14.578044 RPST = 0x0
3804 22:57:14.578129 RD_PRE = 0x0
3805 22:57:14.581630 WR_PRE = 0x1
3806 22:57:14.581713 WR_PST = 0x0
3807 22:57:14.584838 DBI_WR = 0x0
3808 22:57:14.584921 DBI_RD = 0x0
3809 22:57:14.588312 OTF = 0x1
3810 22:57:14.591321 ===================================
3811 22:57:14.595094 ===================================
3812 22:57:14.595213 ANA top config
3813 22:57:14.598168 ===================================
3814 22:57:14.601411 DLL_ASYNC_EN = 0
3815 22:57:14.604912 ALL_SLAVE_EN = 1
3816 22:57:14.608308 NEW_RANK_MODE = 1
3817 22:57:14.608397 DLL_IDLE_MODE = 1
3818 22:57:14.611418 LP45_APHY_COMB_EN = 1
3819 22:57:14.614864 TX_ODT_DIS = 1
3820 22:57:14.617777 NEW_8X_MODE = 1
3821 22:57:14.621078 ===================================
3822 22:57:14.624336 ===================================
3823 22:57:14.627561 data_rate = 1200
3824 22:57:14.630916 CKR = 1
3825 22:57:14.631030 DQ_P2S_RATIO = 8
3826 22:57:14.634767 ===================================
3827 22:57:14.637690 CA_P2S_RATIO = 8
3828 22:57:14.641403 DQ_CA_OPEN = 0
3829 22:57:14.644408 DQ_SEMI_OPEN = 0
3830 22:57:14.647326 CA_SEMI_OPEN = 0
3831 22:57:14.651170 CA_FULL_RATE = 0
3832 22:57:14.651260 DQ_CKDIV4_EN = 1
3833 22:57:14.654492 CA_CKDIV4_EN = 1
3834 22:57:14.657869 CA_PREDIV_EN = 0
3835 22:57:14.661092 PH8_DLY = 0
3836 22:57:14.664638 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3837 22:57:14.667338 DQ_AAMCK_DIV = 4
3838 22:57:14.667424 CA_AAMCK_DIV = 4
3839 22:57:14.671081 CA_ADMCK_DIV = 4
3840 22:57:14.674470 DQ_TRACK_CA_EN = 0
3841 22:57:14.677622 CA_PICK = 600
3842 22:57:14.680693 CA_MCKIO = 600
3843 22:57:14.684248 MCKIO_SEMI = 0
3844 22:57:14.684338 PLL_FREQ = 2288
3845 22:57:14.687249 DQ_UI_PI_RATIO = 32
3846 22:57:14.690806 CA_UI_PI_RATIO = 0
3847 22:57:14.693864 ===================================
3848 22:57:14.697881 ===================================
3849 22:57:14.701182 memory_type:LPDDR4
3850 22:57:14.704064 GP_NUM : 10
3851 22:57:14.704150 SRAM_EN : 1
3852 22:57:14.707214 MD32_EN : 0
3853 22:57:14.710928 ===================================
3854 22:57:14.711022 [ANA_INIT] >>>>>>>>>>>>>>
3855 22:57:14.713870 <<<<<< [CONFIGURE PHASE]: ANA_TX
3856 22:57:14.717638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3857 22:57:14.720844 ===================================
3858 22:57:14.724061 data_rate = 1200,PCW = 0X5800
3859 22:57:14.727139 ===================================
3860 22:57:14.730258 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3861 22:57:14.737439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3862 22:57:14.743611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 22:57:14.747184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3864 22:57:14.750501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3865 22:57:14.753606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3866 22:57:14.757400 [ANA_INIT] flow start
3867 22:57:14.757500 [ANA_INIT] PLL >>>>>>>>
3868 22:57:14.760779 [ANA_INIT] PLL <<<<<<<<
3869 22:57:14.763870 [ANA_INIT] MIDPI >>>>>>>>
3870 22:57:14.764020 [ANA_INIT] MIDPI <<<<<<<<
3871 22:57:14.767400 [ANA_INIT] DLL >>>>>>>>
3872 22:57:14.770083 [ANA_INIT] flow end
3873 22:57:14.773985 ============ LP4 DIFF to SE enter ============
3874 22:57:14.776859 ============ LP4 DIFF to SE exit ============
3875 22:57:14.780708 [ANA_INIT] <<<<<<<<<<<<<
3876 22:57:14.783392 [Flow] Enable top DCM control >>>>>
3877 22:57:14.786777 [Flow] Enable top DCM control <<<<<
3878 22:57:14.790445 Enable DLL master slave shuffle
3879 22:57:14.793686 ==============================================================
3880 22:57:14.796985 Gating Mode config
3881 22:57:14.803556 ==============================================================
3882 22:57:14.803665 Config description:
3883 22:57:14.813761 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3884 22:57:14.820372 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3885 22:57:14.823760 SELPH_MODE 0: By rank 1: By Phase
3886 22:57:14.830411 ==============================================================
3887 22:57:14.833720 GAT_TRACK_EN = 1
3888 22:57:14.836978 RX_GATING_MODE = 2
3889 22:57:14.840499 RX_GATING_TRACK_MODE = 2
3890 22:57:14.843735 SELPH_MODE = 1
3891 22:57:14.846948 PICG_EARLY_EN = 1
3892 22:57:14.850145 VALID_LAT_VALUE = 1
3893 22:57:14.853613 ==============================================================
3894 22:57:14.856803 Enter into Gating configuration >>>>
3895 22:57:14.860159 Exit from Gating configuration <<<<
3896 22:57:14.863496 Enter into DVFS_PRE_config >>>>>
3897 22:57:14.873383 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3898 22:57:14.877193 Exit from DVFS_PRE_config <<<<<
3899 22:57:14.880236 Enter into PICG configuration >>>>
3900 22:57:14.883711 Exit from PICG configuration <<<<
3901 22:57:14.886989 [RX_INPUT] configuration >>>>>
3902 22:57:14.890416 [RX_INPUT] configuration <<<<<
3903 22:57:14.897078 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3904 22:57:14.900241 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3905 22:57:14.906925 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 22:57:14.913657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 22:57:14.919796 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 22:57:14.926706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 22:57:14.929835 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3910 22:57:14.933155 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3911 22:57:14.937101 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3912 22:57:14.943135 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3913 22:57:14.946574 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3914 22:57:14.950128 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 22:57:14.953101 ===================================
3916 22:57:14.956397 LPDDR4 DRAM CONFIGURATION
3917 22:57:14.960202 ===================================
3918 22:57:14.960293 EX_ROW_EN[0] = 0x0
3919 22:57:14.963266 EX_ROW_EN[1] = 0x0
3920 22:57:14.966731 LP4Y_EN = 0x0
3921 22:57:14.966815 WORK_FSP = 0x0
3922 22:57:14.970078 WL = 0x2
3923 22:57:14.970161 RL = 0x2
3924 22:57:14.972916 BL = 0x2
3925 22:57:14.973027 RPST = 0x0
3926 22:57:14.976411 RD_PRE = 0x0
3927 22:57:14.976494 WR_PRE = 0x1
3928 22:57:14.979893 WR_PST = 0x0
3929 22:57:14.979984 DBI_WR = 0x0
3930 22:57:14.983507 DBI_RD = 0x0
3931 22:57:14.983591 OTF = 0x1
3932 22:57:14.986485 ===================================
3933 22:57:14.989869 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3934 22:57:14.996461 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3935 22:57:14.999701 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3936 22:57:15.003105 ===================================
3937 22:57:15.006468 LPDDR4 DRAM CONFIGURATION
3938 22:57:15.009796 ===================================
3939 22:57:15.009885 EX_ROW_EN[0] = 0x10
3940 22:57:15.012993 EX_ROW_EN[1] = 0x0
3941 22:57:15.013077 LP4Y_EN = 0x0
3942 22:57:15.016580 WORK_FSP = 0x0
3943 22:57:15.016665 WL = 0x2
3944 22:57:15.019511 RL = 0x2
3945 22:57:15.019596 BL = 0x2
3946 22:57:15.022996 RPST = 0x0
3947 22:57:15.026852 RD_PRE = 0x0
3948 22:57:15.026943 WR_PRE = 0x1
3949 22:57:15.029934 WR_PST = 0x0
3950 22:57:15.030019 DBI_WR = 0x0
3951 22:57:15.032993 DBI_RD = 0x0
3952 22:57:15.033079 OTF = 0x1
3953 22:57:15.036088 ===================================
3954 22:57:15.042988 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3955 22:57:15.046719 nWR fixed to 30
3956 22:57:15.050057 [ModeRegInit_LP4] CH0 RK0
3957 22:57:15.050146 [ModeRegInit_LP4] CH0 RK1
3958 22:57:15.053249 [ModeRegInit_LP4] CH1 RK0
3959 22:57:15.056406 [ModeRegInit_LP4] CH1 RK1
3960 22:57:15.056493 match AC timing 17
3961 22:57:15.063445 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3962 22:57:15.066564 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3963 22:57:15.069898 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3964 22:57:15.076763 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3965 22:57:15.080162 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3966 22:57:15.080259 ==
3967 22:57:15.083292 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 22:57:15.086432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 22:57:15.086519 ==
3970 22:57:15.093396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3971 22:57:15.099942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3972 22:57:15.103289 [CA 0] Center 35 (5~66) winsize 62
3973 22:57:15.106505 [CA 1] Center 35 (5~66) winsize 62
3974 22:57:15.109754 [CA 2] Center 33 (3~64) winsize 62
3975 22:57:15.113125 [CA 3] Center 33 (2~64) winsize 63
3976 22:57:15.116524 [CA 4] Center 33 (2~64) winsize 63
3977 22:57:15.119678 [CA 5] Center 32 (2~63) winsize 62
3978 22:57:15.119769
3979 22:57:15.122690 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3980 22:57:15.122776
3981 22:57:15.126458 [CATrainingPosCal] consider 1 rank data
3982 22:57:15.129269 u2DelayCellTimex100 = 270/100 ps
3983 22:57:15.132495 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3984 22:57:15.135830 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3985 22:57:15.139184 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3986 22:57:15.142910 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3987 22:57:15.145847 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3988 22:57:15.152981 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3989 22:57:15.153096
3990 22:57:15.156085 CA PerBit enable=1, Macro0, CA PI delay=32
3991 22:57:15.156176
3992 22:57:15.159209 [CBTSetCACLKResult] CA Dly = 32
3993 22:57:15.159293 CS Dly: 5 (0~36)
3994 22:57:15.159358 ==
3995 22:57:15.162793 Dram Type= 6, Freq= 0, CH_0, rank 1
3996 22:57:19.789117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 22:57:19.789308 ==
3998 22:57:19.789422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3999 22:57:19.789487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4000 22:57:19.789548 [CA 0] Center 35 (5~66) winsize 62
4001 22:57:19.789606 [CA 1] Center 35 (5~66) winsize 62
4002 22:57:19.789662 [CA 2] Center 34 (3~65) winsize 63
4003 22:57:19.789717 [CA 3] Center 33 (3~64) winsize 62
4004 22:57:19.789772 [CA 4] Center 32 (2~63) winsize 62
4005 22:57:19.789826 [CA 5] Center 32 (2~63) winsize 62
4006 22:57:19.789880
4007 22:57:19.789934 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4008 22:57:19.789988
4009 22:57:19.790040 [CATrainingPosCal] consider 2 rank data
4010 22:57:19.790093 u2DelayCellTimex100 = 270/100 ps
4011 22:57:19.790146 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4012 22:57:19.790199 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4013 22:57:19.790251 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4014 22:57:19.790303 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4015 22:57:19.790356 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4016 22:57:19.790408 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4017 22:57:19.790460
4018 22:57:19.790512 CA PerBit enable=1, Macro0, CA PI delay=32
4019 22:57:19.790564
4020 22:57:19.790615 [CBTSetCACLKResult] CA Dly = 32
4021 22:57:19.790667 CS Dly: 5 (0~36)
4022 22:57:19.790719
4023 22:57:19.790772 ----->DramcWriteLeveling(PI) begin...
4024 22:57:19.790825 ==
4025 22:57:19.790878 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 22:57:19.790930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 22:57:19.790983 ==
4028 22:57:19.791034 Write leveling (Byte 0): 35 => 35
4029 22:57:19.791087 Write leveling (Byte 1): 33 => 33
4030 22:57:19.791139 DramcWriteLeveling(PI) end<-----
4031 22:57:19.791191
4032 22:57:19.791242 ==
4033 22:57:19.791294 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 22:57:19.791346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 22:57:19.791399 ==
4036 22:57:19.791451 [Gating] SW mode calibration
4037 22:57:19.791503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4038 22:57:19.791556 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4039 22:57:19.791608 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 22:57:19.791661 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 22:57:19.791713 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4042 22:57:19.791765 0 9 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
4043 22:57:19.791817 0 9 16 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
4044 22:57:19.791869 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 22:57:19.791922 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 22:57:19.792005 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 22:57:19.792073 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 22:57:19.792126 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 22:57:19.792178 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4050 22:57:19.792231 0 10 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
4051 22:57:19.792283 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
4052 22:57:19.792336 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 22:57:19.792388 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 22:57:19.792440 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 22:57:19.792492 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 22:57:19.792544 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 22:57:19.792596 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 22:57:19.792648 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4059 22:57:19.792700 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4060 22:57:19.792752 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 22:57:19.792804 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 22:57:19.792857 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 22:57:19.792908 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 22:57:19.792961 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 22:57:19.793013 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 22:57:19.793066 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 22:57:19.793118 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 22:57:19.793173 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 22:57:19.793272 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 22:57:19.793396 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 22:57:19.793454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 22:57:19.793508 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 22:57:19.793560 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 22:57:19.793613 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4075 22:57:19.793666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4076 22:57:19.793718 Total UI for P1: 0, mck2ui 16
4077 22:57:19.793772 best dqsien dly found for B0: ( 0, 13, 12)
4078 22:57:19.793824 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 22:57:19.793877 Total UI for P1: 0, mck2ui 16
4080 22:57:19.793930 best dqsien dly found for B1: ( 0, 13, 14)
4081 22:57:19.793983 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4082 22:57:19.794035 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4083 22:57:19.794087
4084 22:57:19.794140 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4085 22:57:19.794192 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4086 22:57:19.794244 [Gating] SW calibration Done
4087 22:57:19.794297 ==
4088 22:57:19.794349 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 22:57:19.794401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 22:57:19.794454 ==
4091 22:57:19.794506 RX Vref Scan: 0
4092 22:57:19.794559
4093 22:57:19.794612 RX Vref 0 -> 0, step: 1
4094 22:57:19.794664
4095 22:57:19.794716 RX Delay -230 -> 252, step: 16
4096 22:57:19.794769 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4097 22:57:19.794822 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4098 22:57:19.794874 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4099 22:57:19.794927 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4100 22:57:19.794980 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4101 22:57:19.795230 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4102 22:57:19.795289 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4103 22:57:19.795343 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4104 22:57:19.795396 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4105 22:57:19.795449 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4106 22:57:19.795502 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4107 22:57:19.795555 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4108 22:57:19.795608 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4109 22:57:19.795660 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4110 22:57:19.795713 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4111 22:57:19.795765 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4112 22:57:19.795818 ==
4113 22:57:19.795871 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 22:57:19.795924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 22:57:19.796018 ==
4116 22:57:19.796072 DQS Delay:
4117 22:57:19.796124 DQS0 = 0, DQS1 = 0
4118 22:57:19.796177 DQM Delay:
4119 22:57:19.796230 DQM0 = 50, DQM1 = 45
4120 22:57:19.796282 DQ Delay:
4121 22:57:19.796335 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4122 22:57:19.796388 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4123 22:57:19.796441 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4124 22:57:19.796494 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4125 22:57:19.796547
4126 22:57:19.796599
4127 22:57:19.796651 ==
4128 22:57:19.796704 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 22:57:19.796757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 22:57:19.796810 ==
4131 22:57:19.796862
4132 22:57:19.796914
4133 22:57:19.796966 TX Vref Scan disable
4134 22:57:19.797019 == TX Byte 0 ==
4135 22:57:19.797072 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4136 22:57:19.797125 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4137 22:57:19.797216 == TX Byte 1 ==
4138 22:57:19.797272 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4139 22:57:19.797325 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4140 22:57:19.797378 ==
4141 22:57:19.797449 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 22:57:19.797515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 22:57:19.797567 ==
4144 22:57:19.797620
4145 22:57:19.797672
4146 22:57:19.797724 TX Vref Scan disable
4147 22:57:19.797776 == TX Byte 0 ==
4148 22:57:19.797828 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4149 22:57:19.797881 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4150 22:57:19.797934 == TX Byte 1 ==
4151 22:57:19.797987 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4152 22:57:19.798039 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4153 22:57:19.798092
4154 22:57:19.798144 [DATLAT]
4155 22:57:19.798197 Freq=600, CH0 RK0
4156 22:57:19.798249
4157 22:57:19.798302 DATLAT Default: 0x9
4158 22:57:19.798354 0, 0xFFFF, sum = 0
4159 22:57:19.798408 1, 0xFFFF, sum = 0
4160 22:57:19.798462 2, 0xFFFF, sum = 0
4161 22:57:19.798515 3, 0xFFFF, sum = 0
4162 22:57:19.798569 4, 0xFFFF, sum = 0
4163 22:57:19.798622 5, 0xFFFF, sum = 0
4164 22:57:19.798676 6, 0xFFFF, sum = 0
4165 22:57:19.798730 7, 0xFFFF, sum = 0
4166 22:57:19.798783 8, 0x0, sum = 1
4167 22:57:19.798837 9, 0x0, sum = 2
4168 22:57:19.798891 10, 0x0, sum = 3
4169 22:57:19.798944 11, 0x0, sum = 4
4170 22:57:19.798998 best_step = 9
4171 22:57:19.799050
4172 22:57:19.799102 ==
4173 22:57:19.799155 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 22:57:19.799208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 22:57:19.799261 ==
4176 22:57:19.799313 RX Vref Scan: 1
4177 22:57:19.799366
4178 22:57:19.799418 RX Vref 0 -> 0, step: 1
4179 22:57:19.799471
4180 22:57:19.799523 RX Delay -163 -> 252, step: 8
4181 22:57:19.799575
4182 22:57:19.799627 Set Vref, RX VrefLevel [Byte0]: 55
4183 22:57:19.799680 [Byte1]: 55
4184 22:57:19.799732
4185 22:57:19.799784 Final RX Vref Byte 0 = 55 to rank0
4186 22:57:19.799837 Final RX Vref Byte 1 = 55 to rank0
4187 22:57:19.799890 Final RX Vref Byte 0 = 55 to rank1
4188 22:57:19.799942 Final RX Vref Byte 1 = 55 to rank1==
4189 22:57:19.800037 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 22:57:19.800091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 22:57:19.800144 ==
4192 22:57:19.800196 DQS Delay:
4193 22:57:19.800249 DQS0 = 0, DQS1 = 0
4194 22:57:19.800302 DQM Delay:
4195 22:57:19.800354 DQM0 = 53, DQM1 = 45
4196 22:57:19.800424 DQ Delay:
4197 22:57:19.800493 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4198 22:57:19.800545 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4199 22:57:19.800598 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4200 22:57:19.800651 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4201 22:57:19.800703
4202 22:57:19.800755
4203 22:57:19.800807 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4204 22:57:19.800861 CH0 RK0: MR19=808, MR18=6D60
4205 22:57:19.800913 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4206 22:57:19.800965
4207 22:57:19.801018 ----->DramcWriteLeveling(PI) begin...
4208 22:57:19.801072 ==
4209 22:57:19.801123 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 22:57:19.801209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 22:57:19.801292 ==
4212 22:57:19.801406 Write leveling (Byte 0): 34 => 34
4213 22:57:19.801459 Write leveling (Byte 1): 31 => 31
4214 22:57:19.801511 DramcWriteLeveling(PI) end<-----
4215 22:57:19.801564
4216 22:57:19.801616 ==
4217 22:57:19.801668 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 22:57:19.801721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 22:57:19.801774 ==
4220 22:57:19.801827 [Gating] SW mode calibration
4221 22:57:19.801880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4222 22:57:19.801933 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4223 22:57:19.801986 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 22:57:19.802040 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 22:57:19.802093 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 22:57:19.802145 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
4227 22:57:19.802198 0 9 16 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (1 0)
4228 22:57:19.802250 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 22:57:19.802303 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 22:57:19.802356 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 22:57:19.802408 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 22:57:19.802461 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 22:57:19.802513 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 22:57:19.802566 0 10 12 | B1->B0 | 2929 2424 | 1 1 | (0 0) (0 0)
4235 22:57:19.802619 0 10 16 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
4236 22:57:19.802672 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 22:57:19.802724 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 22:57:19.802776 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 22:57:19.803021 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 22:57:19.803082 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 22:57:19.803153 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 22:57:19.803209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4243 22:57:19.803263 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 22:57:19.803318 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 22:57:19.803372 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 22:57:19.803440 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 22:57:19.803494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 22:57:19.803546 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 22:57:19.803599 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 22:57:19.803668 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 22:57:19.803723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 22:57:19.803813 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 22:57:19.803899 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 22:57:19.803996 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 22:57:19.804054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 22:57:19.804114 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 22:57:19.804214 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4258 22:57:19.804270 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4259 22:57:19.804371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 22:57:19.804428 Total UI for P1: 0, mck2ui 16
4261 22:57:19.804482 best dqsien dly found for B0: ( 0, 13, 12)
4262 22:57:19.804568 Total UI for P1: 0, mck2ui 16
4263 22:57:19.804622 best dqsien dly found for B1: ( 0, 13, 14)
4264 22:57:19.804676 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4265 22:57:19.804729 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4266 22:57:19.804783
4267 22:57:19.804835 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4268 22:57:19.804888 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4269 22:57:19.804941 [Gating] SW calibration Done
4270 22:57:19.804994 ==
4271 22:57:19.805092 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 22:57:19.805177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 22:57:19.805256 ==
4274 22:57:19.805328 RX Vref Scan: 0
4275 22:57:19.805381
4276 22:57:19.805474 RX Vref 0 -> 0, step: 1
4277 22:57:19.805530
4278 22:57:19.805583 RX Delay -230 -> 252, step: 16
4279 22:57:19.805663 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4280 22:57:19.805763 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4281 22:57:19.805847 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4282 22:57:19.805930 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4283 22:57:19.806013 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4284 22:57:19.806096 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4285 22:57:19.806179 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4286 22:57:19.806263 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4287 22:57:19.806346 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4288 22:57:19.806429 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4289 22:57:19.806511 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4290 22:57:19.806594 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4291 22:57:19.806678 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4292 22:57:19.806761 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4293 22:57:19.806858 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4294 22:57:19.806956 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4295 22:57:19.807038 ==
4296 22:57:19.807121 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 22:57:19.807241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 22:57:19.807308 ==
4299 22:57:19.807397 DQS Delay:
4300 22:57:19.807484 DQS0 = 0, DQS1 = 0
4301 22:57:19.807567 DQM Delay:
4302 22:57:19.807651 DQM0 = 50, DQM1 = 42
4303 22:57:19.807733 DQ Delay:
4304 22:57:19.807817 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4305 22:57:19.807900 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4306 22:57:19.808003 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4307 22:57:19.808073 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4308 22:57:19.808127
4309 22:57:19.808180
4310 22:57:19.808233 ==
4311 22:57:19.808285 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 22:57:19.808338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 22:57:19.808392 ==
4314 22:57:19.808444
4315 22:57:19.808497
4316 22:57:19.808550 TX Vref Scan disable
4317 22:57:19.808603 == TX Byte 0 ==
4318 22:57:19.808655 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4319 22:57:19.808709 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4320 22:57:19.808762 == TX Byte 1 ==
4321 22:57:19.808815 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4322 22:57:19.808868 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4323 22:57:19.808920 ==
4324 22:57:19.808973 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 22:57:19.809025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 22:57:19.809078 ==
4327 22:57:19.809131
4328 22:57:19.809203
4329 22:57:19.809270 TX Vref Scan disable
4330 22:57:19.809323 == TX Byte 0 ==
4331 22:57:19.809376 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4332 22:57:19.809429 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4333 22:57:19.809481 == TX Byte 1 ==
4334 22:57:19.809533 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4335 22:57:19.809586 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4336 22:57:19.809639
4337 22:57:19.809692 [DATLAT]
4338 22:57:19.809744 Freq=600, CH0 RK1
4339 22:57:19.809797
4340 22:57:19.809849 DATLAT Default: 0x9
4341 22:57:19.809902 0, 0xFFFF, sum = 0
4342 22:57:19.809956 1, 0xFFFF, sum = 0
4343 22:57:19.810010 2, 0xFFFF, sum = 0
4344 22:57:19.810064 3, 0xFFFF, sum = 0
4345 22:57:19.810118 4, 0xFFFF, sum = 0
4346 22:57:19.810171 5, 0xFFFF, sum = 0
4347 22:57:19.810225 6, 0xFFFF, sum = 0
4348 22:57:19.810278 7, 0xFFFF, sum = 0
4349 22:57:19.810331 8, 0x0, sum = 1
4350 22:57:19.810384 9, 0x0, sum = 2
4351 22:57:19.810438 10, 0x0, sum = 3
4352 22:57:19.810491 11, 0x0, sum = 4
4353 22:57:19.810544 best_step = 9
4354 22:57:19.810597
4355 22:57:19.810649 ==
4356 22:57:19.810702 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 22:57:19.810754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 22:57:19.810808 ==
4359 22:57:19.810860 RX Vref Scan: 0
4360 22:57:19.810912
4361 22:57:19.810964 RX Vref 0 -> 0, step: 1
4362 22:57:19.811017
4363 22:57:19.811088 RX Delay -163 -> 252, step: 8
4364 22:57:19.811143 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4365 22:57:19.811196 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4366 22:57:19.811248 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4367 22:57:19.811301 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4368 22:57:19.811354 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4369 22:57:19.811603 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4370 22:57:19.811661 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4371 22:57:19.811715 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4372 22:57:19.811768 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4373 22:57:19.811821 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4374 22:57:19.811873 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4375 22:57:19.811925 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4376 22:57:19.812013 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4377 22:57:19.812081 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4378 22:57:19.812133 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4379 22:57:19.812186 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4380 22:57:19.812238 ==
4381 22:57:19.812290 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 22:57:19.812343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 22:57:19.812396 ==
4384 22:57:19.812448 DQS Delay:
4385 22:57:19.812500 DQS0 = 0, DQS1 = 0
4386 22:57:19.812552 DQM Delay:
4387 22:57:19.812604 DQM0 = 53, DQM1 = 46
4388 22:57:19.812656 DQ Delay:
4389 22:57:19.812708 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4390 22:57:19.812761 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4391 22:57:19.812813 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4392 22:57:19.812865 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4393 22:57:19.812916
4394 22:57:19.812968
4395 22:57:19.813020 [DQSOSCAuto] RK1, (LSB)MR18= 0x6021, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4396 22:57:19.813073 CH0 RK1: MR19=808, MR18=6021
4397 22:57:19.813125 CH0_RK1: MR19=0x808, MR18=0x6021, DQSOSC=391, MR23=63, INC=171, DEC=114
4398 22:57:19.813178 [RxdqsGatingPostProcess] freq 600
4399 22:57:19.813230 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4400 22:57:19.813285 Pre-setting of DQS Precalculation
4401 22:57:19.813339 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4402 22:57:19.813391 ==
4403 22:57:19.813444 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 22:57:19.813496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 22:57:19.813549 ==
4406 22:57:19.813601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4407 22:57:19.813654 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4408 22:57:19.813706 [CA 0] Center 35 (5~66) winsize 62
4409 22:57:19.813759 [CA 1] Center 35 (5~66) winsize 62
4410 22:57:19.813810 [CA 2] Center 34 (4~65) winsize 62
4411 22:57:19.813862 [CA 3] Center 34 (3~65) winsize 63
4412 22:57:19.813914 [CA 4] Center 34 (4~65) winsize 62
4413 22:57:19.813966 [CA 5] Center 33 (3~64) winsize 62
4414 22:57:19.814018
4415 22:57:19.814070 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4416 22:57:19.814122
4417 22:57:19.814174 [CATrainingPosCal] consider 1 rank data
4418 22:57:19.814226 u2DelayCellTimex100 = 270/100 ps
4419 22:57:19.814279 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4420 22:57:19.814331 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4421 22:57:19.814383 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4422 22:57:19.814436 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4423 22:57:19.814488 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 22:57:19.814540 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 22:57:19.814592
4426 22:57:19.814644 CA PerBit enable=1, Macro0, CA PI delay=33
4427 22:57:19.814696
4428 22:57:19.814748 [CBTSetCACLKResult] CA Dly = 33
4429 22:57:19.814800 CS Dly: 6 (0~37)
4430 22:57:19.814853 ==
4431 22:57:19.814905 Dram Type= 6, Freq= 0, CH_1, rank 1
4432 22:57:19.814957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 22:57:19.815014 ==
4434 22:57:19.815073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4435 22:57:19.815126 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4436 22:57:19.815179 [CA 0] Center 36 (5~67) winsize 63
4437 22:57:19.815231 [CA 1] Center 36 (5~67) winsize 63
4438 22:57:19.815283 [CA 2] Center 35 (4~66) winsize 63
4439 22:57:19.815336 [CA 3] Center 34 (4~65) winsize 62
4440 22:57:19.815389 [CA 4] Center 34 (4~65) winsize 62
4441 22:57:19.815441 [CA 5] Center 34 (3~65) winsize 63
4442 22:57:19.815492
4443 22:57:19.815544 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4444 22:57:19.815596
4445 22:57:19.815647 [CATrainingPosCal] consider 2 rank data
4446 22:57:19.815699 u2DelayCellTimex100 = 270/100 ps
4447 22:57:19.815751 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4448 22:57:19.815803 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4449 22:57:19.815855 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4450 22:57:19.815907 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4451 22:57:19.815966 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4452 22:57:19.816054 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4453 22:57:19.816107
4454 22:57:19.816159 CA PerBit enable=1, Macro0, CA PI delay=33
4455 22:57:19.816211
4456 22:57:19.816263 [CBTSetCACLKResult] CA Dly = 33
4457 22:57:19.816315 CS Dly: 6 (0~38)
4458 22:57:19.816367
4459 22:57:19.816419 ----->DramcWriteLeveling(PI) begin...
4460 22:57:19.816472 ==
4461 22:57:19.816524 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 22:57:19.816576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 22:57:19.816629 ==
4464 22:57:19.816681 Write leveling (Byte 0): 30 => 30
4465 22:57:19.816733 Write leveling (Byte 1): 30 => 30
4466 22:57:19.816785 DramcWriteLeveling(PI) end<-----
4467 22:57:19.816837
4468 22:57:19.816888 ==
4469 22:57:19.816940 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 22:57:19.816993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 22:57:19.817045 ==
4472 22:57:19.817097 [Gating] SW mode calibration
4473 22:57:19.817150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4474 22:57:19.817214 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4475 22:57:19.817300 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4476 22:57:19.817400 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 22:57:19.817484 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 22:57:19.817536 0 9 12 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
4479 22:57:19.817590 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 22:57:19.817643 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 22:57:19.817695 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 22:57:19.817747 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 22:57:19.817799 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 22:57:19.817852 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 22:57:19.817904 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4486 22:57:19.818156 0 10 12 | B1->B0 | 3737 3e3e | 1 0 | (0 0) (0 0)
4487 22:57:19.818220 0 10 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4488 22:57:19.818275 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 22:57:19.818328 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 22:57:19.818381 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 22:57:19.818434 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 22:57:19.818487 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 22:57:19.818539 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 22:57:19.818591 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4495 22:57:19.818643 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 22:57:19.818695 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 22:57:19.818747 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 22:57:19.818800 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 22:57:19.818852 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 22:57:19.818904 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 22:57:19.818957 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 22:57:19.819009 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 22:57:19.819062 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 22:57:19.819113 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 22:57:19.819166 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 22:57:19.819219 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 22:57:19.819271 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 22:57:19.819322 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 22:57:19.819375 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 22:57:19.819427 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4511 22:57:19.819479 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 22:57:19.819532 Total UI for P1: 0, mck2ui 16
4513 22:57:19.819585 best dqsien dly found for B0: ( 0, 13, 12)
4514 22:57:19.819638 Total UI for P1: 0, mck2ui 16
4515 22:57:19.819690 best dqsien dly found for B1: ( 0, 13, 12)
4516 22:57:19.819742 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4517 22:57:19.819795 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4518 22:57:19.819847
4519 22:57:19.819898 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4520 22:57:19.819951 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4521 22:57:19.820075 [Gating] SW calibration Done
4522 22:57:19.820158 ==
4523 22:57:19.820241 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 22:57:19.820307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 22:57:19.820362 ==
4526 22:57:19.820414 RX Vref Scan: 0
4527 22:57:19.820467
4528 22:57:19.820519 RX Vref 0 -> 0, step: 1
4529 22:57:19.820571
4530 22:57:19.820622 RX Delay -230 -> 252, step: 16
4531 22:57:19.820674 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4532 22:57:19.820727 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4533 22:57:19.820779 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4534 22:57:19.820831 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4535 22:57:19.820883 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4536 22:57:19.820935 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4537 22:57:19.820986 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4538 22:57:19.821038 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4539 22:57:19.821090 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4540 22:57:19.821143 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4541 22:57:19.821253 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4542 22:57:19.821341 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4543 22:57:19.821397 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4544 22:57:19.821451 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4545 22:57:19.821504 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4546 22:57:19.821556 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4547 22:57:19.821608 ==
4548 22:57:19.821661 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 22:57:19.821714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 22:57:19.821768 ==
4551 22:57:19.821820 DQS Delay:
4552 22:57:19.821872 DQS0 = 0, DQS1 = 0
4553 22:57:19.821924 DQM Delay:
4554 22:57:19.821977 DQM0 = 47, DQM1 = 46
4555 22:57:19.822029 DQ Delay:
4556 22:57:19.822081 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4557 22:57:19.822133 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4558 22:57:19.822185 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4559 22:57:19.822237 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4560 22:57:19.822288
4561 22:57:19.822340
4562 22:57:19.822392 ==
4563 22:57:19.822444 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 22:57:19.822496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 22:57:19.822548 ==
4566 22:57:19.822600
4567 22:57:19.822651
4568 22:57:19.822703 TX Vref Scan disable
4569 22:57:19.822755 == TX Byte 0 ==
4570 22:57:19.822807 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4571 22:57:19.822860 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4572 22:57:19.822912 == TX Byte 1 ==
4573 22:57:19.822964 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4574 22:57:19.823016 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4575 22:57:19.823068 ==
4576 22:57:19.823120 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 22:57:19.823172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 22:57:19.823225 ==
4579 22:57:19.823277
4580 22:57:19.823329
4581 22:57:19.823380 TX Vref Scan disable
4582 22:57:19.823432 == TX Byte 0 ==
4583 22:57:19.823484 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4584 22:57:19.823536 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4585 22:57:19.823588 == TX Byte 1 ==
4586 22:57:19.823639 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4587 22:57:19.823691 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4588 22:57:19.823743
4589 22:57:19.823795 [DATLAT]
4590 22:57:19.823846 Freq=600, CH1 RK0
4591 22:57:19.823898
4592 22:57:19.823950 DATLAT Default: 0x9
4593 22:57:19.824078 0, 0xFFFF, sum = 0
4594 22:57:19.824133 1, 0xFFFF, sum = 0
4595 22:57:19.824187 2, 0xFFFF, sum = 0
4596 22:57:19.824239 3, 0xFFFF, sum = 0
4597 22:57:19.824292 4, 0xFFFF, sum = 0
4598 22:57:19.824345 5, 0xFFFF, sum = 0
4599 22:57:19.824397 6, 0xFFFF, sum = 0
4600 22:57:19.824450 7, 0xFFFF, sum = 0
4601 22:57:19.824503 8, 0x0, sum = 1
4602 22:57:19.824555 9, 0x0, sum = 2
4603 22:57:19.824609 10, 0x0, sum = 3
4604 22:57:19.824661 11, 0x0, sum = 4
4605 22:57:19.824715 best_step = 9
4606 22:57:19.824767
4607 22:57:19.824819 ==
4608 22:57:19.824871 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 22:57:19.824923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 22:57:19.824975 ==
4611 22:57:19.825027 RX Vref Scan: 1
4612 22:57:19.825078
4613 22:57:19.825130 RX Vref 0 -> 0, step: 1
4614 22:57:19.825182
4615 22:57:19.825233 RX Delay -163 -> 252, step: 8
4616 22:57:19.825481
4617 22:57:19.825539 Set Vref, RX VrefLevel [Byte0]: 53
4618 22:57:19.825592 [Byte1]: 53
4619 22:57:19.825645
4620 22:57:19.825697 Final RX Vref Byte 0 = 53 to rank0
4621 22:57:19.825750 Final RX Vref Byte 1 = 53 to rank0
4622 22:57:19.825803 Final RX Vref Byte 0 = 53 to rank1
4623 22:57:19.825855 Final RX Vref Byte 1 = 53 to rank1==
4624 22:57:19.825907 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 22:57:19.825959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 22:57:19.826012 ==
4627 22:57:19.826064 DQS Delay:
4628 22:57:19.826116 DQS0 = 0, DQS1 = 0
4629 22:57:19.826168 DQM Delay:
4630 22:57:19.826220 DQM0 = 48, DQM1 = 45
4631 22:57:19.826272 DQ Delay:
4632 22:57:19.826323 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4633 22:57:19.826375 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4634 22:57:19.826426 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4635 22:57:19.826478 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4636 22:57:19.826530
4637 22:57:19.826582
4638 22:57:19.826634 [DQSOSCAuto] RK0, (LSB)MR18= 0x466c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4639 22:57:19.826687 CH1 RK0: MR19=808, MR18=466C
4640 22:57:19.826740 CH1_RK0: MR19=0x808, MR18=0x466C, DQSOSC=389, MR23=63, INC=173, DEC=115
4641 22:57:19.826792
4642 22:57:19.826845 ----->DramcWriteLeveling(PI) begin...
4643 22:57:19.826897 ==
4644 22:57:19.826949 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 22:57:19.827002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 22:57:19.827054 ==
4647 22:57:19.827105 Write leveling (Byte 0): 32 => 32
4648 22:57:19.827157 Write leveling (Byte 1): 32 => 32
4649 22:57:19.827209 DramcWriteLeveling(PI) end<-----
4650 22:57:19.827261
4651 22:57:19.827312 ==
4652 22:57:19.827364 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 22:57:19.827416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 22:57:19.827468 ==
4655 22:57:19.827520 [Gating] SW mode calibration
4656 22:57:19.827572 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4657 22:57:19.827625 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4658 22:57:19.827678 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4659 22:57:19.827730 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 22:57:19.827782 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4661 22:57:19.827834 0 9 12 | B1->B0 | 2e2e 2f2f | 1 1 | (1 0) (1 0)
4662 22:57:19.827886 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 22:57:19.827938 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 22:57:19.828036 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 22:57:19.828089 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 22:57:19.828142 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 22:57:19.828194 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 22:57:19.828246 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 22:57:19.828299 0 10 12 | B1->B0 | 3838 3535 | 1 1 | (0 0) (0 0)
4670 22:57:19.828351 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 22:57:19.828403 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 22:57:19.828456 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 22:57:19.828508 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 22:57:19.828562 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 22:57:19.828614 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 22:57:19.828666 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4677 22:57:19.828718 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4678 22:57:19.828770 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 22:57:19.828822 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 22:57:19.828874 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 22:57:19.828926 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 22:57:19.828978 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 22:57:19.829031 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 22:57:19.829083 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 22:57:19.829135 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 22:57:19.829187 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 22:57:19.829239 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 22:57:19.829295 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 22:57:19.829347 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 22:57:19.829399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 22:57:19.829451 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 22:57:19.829503 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4693 22:57:19.829555 Total UI for P1: 0, mck2ui 16
4694 22:57:19.829607 best dqsien dly found for B1: ( 0, 13, 6)
4695 22:57:19.829660 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4696 22:57:19.829712 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 22:57:19.829764 Total UI for P1: 0, mck2ui 16
4698 22:57:19.829817 best dqsien dly found for B0: ( 0, 13, 10)
4699 22:57:19.829869 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4700 22:57:19.829921 best DQS1 dly(MCK, UI, PI) = (0, 13, 6)
4701 22:57:19.829974
4702 22:57:19.830026 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4703 22:57:19.830079 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 6)
4704 22:57:19.830130 [Gating] SW calibration Done
4705 22:57:19.830183 ==
4706 22:57:19.830235 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 22:57:19.830288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 22:57:19.830339 ==
4709 22:57:19.830391 RX Vref Scan: 0
4710 22:57:19.830444
4711 22:57:19.830496 RX Vref 0 -> 0, step: 1
4712 22:57:19.830548
4713 22:57:19.830600 RX Delay -230 -> 252, step: 16
4714 22:57:19.830652 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4715 22:57:19.830705 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4716 22:57:19.830757 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4717 22:57:19.830809 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4718 22:57:19.830861 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4719 22:57:19.830913 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4720 22:57:19.830964 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4721 22:57:19.831016 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4722 22:57:19.831068 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4723 22:57:19.831315 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4724 22:57:19.831374 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4725 22:57:19.831428 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4726 22:57:19.831480 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4727 22:57:19.831533 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4728 22:57:19.831585 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4729 22:57:19.831638 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4730 22:57:19.831690 ==
4731 22:57:19.831742 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 22:57:19.831794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 22:57:19.831847 ==
4734 22:57:19.831899 DQS Delay:
4735 22:57:19.831951 DQS0 = 0, DQS1 = 0
4736 22:57:19.832050 DQM Delay:
4737 22:57:19.832102 DQM0 = 49, DQM1 = 48
4738 22:57:19.832155 DQ Delay:
4739 22:57:19.832207 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4740 22:57:19.832260 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4741 22:57:19.832312 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4742 22:57:19.832364 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4743 22:57:19.832416
4744 22:57:19.832467
4745 22:57:19.832518 ==
4746 22:57:19.832571 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 22:57:19.832623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 22:57:19.832676 ==
4749 22:57:19.832727
4750 22:57:19.832780
4751 22:57:19.832832 TX Vref Scan disable
4752 22:57:19.832885 == TX Byte 0 ==
4753 22:57:19.832937 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4754 22:57:19.832990 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4755 22:57:19.833042 == TX Byte 1 ==
4756 22:57:19.833095 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4757 22:57:19.833147 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4758 22:57:19.833199 ==
4759 22:57:19.833251 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 22:57:19.833304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 22:57:19.833356 ==
4762 22:57:19.833408
4763 22:57:19.833460
4764 22:57:19.833511 TX Vref Scan disable
4765 22:57:19.833563 == TX Byte 0 ==
4766 22:57:19.833615 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4767 22:57:19.833667 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4768 22:57:19.833720 == TX Byte 1 ==
4769 22:57:19.833772 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4770 22:57:19.833824 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4771 22:57:19.833876
4772 22:57:19.833927 [DATLAT]
4773 22:57:19.833979 Freq=600, CH1 RK1
4774 22:57:19.834031
4775 22:57:19.834082 DATLAT Default: 0x9
4776 22:57:19.834134 0, 0xFFFF, sum = 0
4777 22:57:19.834187 1, 0xFFFF, sum = 0
4778 22:57:19.834240 2, 0xFFFF, sum = 0
4779 22:57:19.834292 3, 0xFFFF, sum = 0
4780 22:57:19.834345 4, 0xFFFF, sum = 0
4781 22:57:19.834398 5, 0xFFFF, sum = 0
4782 22:57:19.834450 6, 0xFFFF, sum = 0
4783 22:57:19.834502 7, 0xFFFF, sum = 0
4784 22:57:19.834555 8, 0x0, sum = 1
4785 22:57:19.834609 9, 0x0, sum = 2
4786 22:57:19.834661 10, 0x0, sum = 3
4787 22:57:19.834713 11, 0x0, sum = 4
4788 22:57:19.834766 best_step = 9
4789 22:57:19.834818
4790 22:57:19.834869 ==
4791 22:57:19.834921 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 22:57:19.834973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 22:57:19.835026 ==
4794 22:57:19.835078 RX Vref Scan: 0
4795 22:57:19.835130
4796 22:57:19.835182 RX Vref 0 -> 0, step: 1
4797 22:57:19.835235
4798 22:57:19.835286 RX Delay -163 -> 252, step: 8
4799 22:57:19.835337 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4800 22:57:19.835390 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4801 22:57:19.835442 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4802 22:57:19.835494 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4803 22:57:19.835546 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4804 22:57:19.835598 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4805 22:57:19.835650 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4806 22:57:19.835701 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4807 22:57:19.835753 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4808 22:57:19.835805 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4809 22:57:19.835857 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4810 22:57:19.835909 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4811 22:57:19.835970 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4812 22:57:19.836058 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4813 22:57:19.836110 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4814 22:57:19.836162 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4815 22:57:19.836214 ==
4816 22:57:19.836266 Dram Type= 6, Freq= 0, CH_1, rank 1
4817 22:57:19.836318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4818 22:57:19.836371 ==
4819 22:57:19.836422 DQS Delay:
4820 22:57:19.836474 DQS0 = 0, DQS1 = 0
4821 22:57:19.836526 DQM Delay:
4822 22:57:19.836579 DQM0 = 49, DQM1 = 46
4823 22:57:19.836630 DQ Delay:
4824 22:57:19.836682 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4825 22:57:19.836734 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4826 22:57:19.836786 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4827 22:57:19.836838 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4828 22:57:19.836890
4829 22:57:19.836941
4830 22:57:19.836992 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4831 22:57:19.837046 CH1 RK1: MR19=808, MR18=6C23
4832 22:57:19.837098 CH1_RK1: MR19=0x808, MR18=0x6C23, DQSOSC=389, MR23=63, INC=173, DEC=115
4833 22:57:19.837152 [RxdqsGatingPostProcess] freq 600
4834 22:57:19.837205 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4835 22:57:19.837257 Pre-setting of DQS Precalculation
4836 22:57:19.837309 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4837 22:57:19.837362 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4838 22:57:19.837415 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4839 22:57:19.837467
4840 22:57:19.837519
4841 22:57:19.837570 [Calibration Summary] 1200 Mbps
4842 22:57:19.837622 CH 0, Rank 0
4843 22:57:19.837674 SW Impedance : PASS
4844 22:57:19.837726 DUTY Scan : NO K
4845 22:57:19.837778 ZQ Calibration : PASS
4846 22:57:19.837830 Jitter Meter : NO K
4847 22:57:19.837882 CBT Training : PASS
4848 22:57:19.837934 Write leveling : PASS
4849 22:57:19.837986 RX DQS gating : PASS
4850 22:57:19.838038 RX DQ/DQS(RDDQC) : PASS
4851 22:57:19.838090 TX DQ/DQS : PASS
4852 22:57:19.838142 RX DATLAT : PASS
4853 22:57:19.838193 RX DQ/DQS(Engine): PASS
4854 22:57:19.838245 TX OE : NO K
4855 22:57:19.838298 All Pass.
4856 22:57:19.838349
4857 22:57:19.838401 CH 0, Rank 1
4858 22:57:19.838453 SW Impedance : PASS
4859 22:57:19.838505 DUTY Scan : NO K
4860 22:57:19.838557 ZQ Calibration : PASS
4861 22:57:19.838609 Jitter Meter : NO K
4862 22:57:19.838661 CBT Training : PASS
4863 22:57:19.838712 Write leveling : PASS
4864 22:57:19.838764 RX DQS gating : PASS
4865 22:57:19.838816 RX DQ/DQS(RDDQC) : PASS
4866 22:57:19.838868 TX DQ/DQS : PASS
4867 22:57:19.838920 RX DATLAT : PASS
4868 22:57:19.839166 RX DQ/DQS(Engine): PASS
4869 22:57:19.839229 TX OE : NO K
4870 22:57:19.839283 All Pass.
4871 22:57:19.839335
4872 22:57:19.839387 CH 1, Rank 0
4873 22:57:19.839439 SW Impedance : PASS
4874 22:57:19.839492 DUTY Scan : NO K
4875 22:57:19.839545 ZQ Calibration : PASS
4876 22:57:19.839598 Jitter Meter : NO K
4877 22:57:19.839649 CBT Training : PASS
4878 22:57:19.839701 Write leveling : PASS
4879 22:57:19.839753 RX DQS gating : PASS
4880 22:57:19.839805 RX DQ/DQS(RDDQC) : PASS
4881 22:57:19.839857 TX DQ/DQS : PASS
4882 22:57:19.839909 RX DATLAT : PASS
4883 22:57:19.839993 RX DQ/DQS(Engine): PASS
4884 22:57:19.840062 TX OE : NO K
4885 22:57:19.840115 All Pass.
4886 22:57:19.840167
4887 22:57:19.840219 CH 1, Rank 1
4888 22:57:19.840271 SW Impedance : PASS
4889 22:57:19.840323 DUTY Scan : NO K
4890 22:57:19.840374 ZQ Calibration : PASS
4891 22:57:19.840426 Jitter Meter : NO K
4892 22:57:19.840478 CBT Training : PASS
4893 22:57:19.840530 Write leveling : PASS
4894 22:57:19.840582 RX DQS gating : PASS
4895 22:57:19.840634 RX DQ/DQS(RDDQC) : PASS
4896 22:57:19.840686 TX DQ/DQS : PASS
4897 22:57:19.840738 RX DATLAT : PASS
4898 22:57:19.840790 RX DQ/DQS(Engine): PASS
4899 22:57:19.840842 TX OE : NO K
4900 22:57:19.840894 All Pass.
4901 22:57:19.840946
4902 22:57:19.840998 DramC Write-DBI off
4903 22:57:19.841050 PER_BANK_REFRESH: Hybrid Mode
4904 22:57:19.841102 TX_TRACKING: ON
4905 22:57:19.841155 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4906 22:57:19.841208 [FAST_K] Save calibration result to emmc
4907 22:57:19.841260 dramc_set_vcore_voltage set vcore to 662500
4908 22:57:19.841312 Read voltage for 933, 3
4909 22:57:19.841375 Vio18 = 0
4910 22:57:19.841429 Vcore = 662500
4911 22:57:19.841481 Vdram = 0
4912 22:57:19.841533 Vddq = 0
4913 22:57:19.841585 Vmddr = 0
4914 22:57:19.841637 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4915 22:57:19.841690 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4916 22:57:19.841743 MEM_TYPE=3, freq_sel=17
4917 22:57:19.841796 sv_algorithm_assistance_LP4_1600
4918 22:57:19.841848 ============ PULL DRAM RESETB DOWN ============
4919 22:57:19.841901 ========== PULL DRAM RESETB DOWN end =========
4920 22:57:19.841954 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4921 22:57:19.842006 ===================================
4922 22:57:19.842059 LPDDR4 DRAM CONFIGURATION
4923 22:57:19.842111 ===================================
4924 22:57:19.842163 EX_ROW_EN[0] = 0x0
4925 22:57:19.842215 EX_ROW_EN[1] = 0x0
4926 22:57:19.842267 LP4Y_EN = 0x0
4927 22:57:19.842320 WORK_FSP = 0x0
4928 22:57:19.842372 WL = 0x3
4929 22:57:19.842423 RL = 0x3
4930 22:57:19.842475 BL = 0x2
4931 22:57:19.842527 RPST = 0x0
4932 22:57:19.842578 RD_PRE = 0x0
4933 22:57:19.842630 WR_PRE = 0x1
4934 22:57:19.842682 WR_PST = 0x0
4935 22:57:19.842733 DBI_WR = 0x0
4936 22:57:19.842785 DBI_RD = 0x0
4937 22:57:19.842837 OTF = 0x1
4938 22:57:19.842889 ===================================
4939 22:57:19.842942 ===================================
4940 22:57:19.842995 ANA top config
4941 22:57:19.843047 ===================================
4942 22:57:19.843099 DLL_ASYNC_EN = 0
4943 22:57:19.843150 ALL_SLAVE_EN = 1
4944 22:57:19.843203 NEW_RANK_MODE = 1
4945 22:57:19.843255 DLL_IDLE_MODE = 1
4946 22:57:19.843307 LP45_APHY_COMB_EN = 1
4947 22:57:19.843359 TX_ODT_DIS = 1
4948 22:57:19.843441 NEW_8X_MODE = 1
4949 22:57:19.843499 ===================================
4950 22:57:19.843569 ===================================
4951 22:57:19.843675 data_rate = 1866
4952 22:57:19.843730 CKR = 1
4953 22:57:19.843810 DQ_P2S_RATIO = 8
4954 22:57:19.843893 ===================================
4955 22:57:19.844007 CA_P2S_RATIO = 8
4956 22:57:19.844063 DQ_CA_OPEN = 0
4957 22:57:19.844117 DQ_SEMI_OPEN = 0
4958 22:57:19.844169 CA_SEMI_OPEN = 0
4959 22:57:19.844221 CA_FULL_RATE = 0
4960 22:57:19.844273 DQ_CKDIV4_EN = 1
4961 22:57:19.844325 CA_CKDIV4_EN = 1
4962 22:57:19.844377 CA_PREDIV_EN = 0
4963 22:57:19.844429 PH8_DLY = 0
4964 22:57:19.844481 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4965 22:57:19.844533 DQ_AAMCK_DIV = 4
4966 22:57:19.844585 CA_AAMCK_DIV = 4
4967 22:57:19.844638 CA_ADMCK_DIV = 4
4968 22:57:19.844690 DQ_TRACK_CA_EN = 0
4969 22:57:19.844742 CA_PICK = 933
4970 22:57:19.844794 CA_MCKIO = 933
4971 22:57:19.844846 MCKIO_SEMI = 0
4972 22:57:19.844898 PLL_FREQ = 3732
4973 22:57:19.844950 DQ_UI_PI_RATIO = 32
4974 22:57:19.845002 CA_UI_PI_RATIO = 0
4975 22:57:19.845055 ===================================
4976 22:57:19.845107 ===================================
4977 22:57:19.845160 memory_type:LPDDR4
4978 22:57:19.845212 GP_NUM : 10
4979 22:57:19.845264 SRAM_EN : 1
4980 22:57:19.845335 MD32_EN : 0
4981 22:57:19.845389 ===================================
4982 22:57:19.845442 [ANA_INIT] >>>>>>>>>>>>>>
4983 22:57:19.845509 <<<<<< [CONFIGURE PHASE]: ANA_TX
4984 22:57:19.845575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4985 22:57:19.845629 ===================================
4986 22:57:19.845683 data_rate = 1866,PCW = 0X8f00
4987 22:57:19.845736 ===================================
4988 22:57:19.845788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4989 22:57:19.845842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4990 22:57:19.845895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4991 22:57:19.845947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4992 22:57:19.845999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4993 22:57:19.846051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4994 22:57:20.120935 [ANA_INIT] flow start
4995 22:57:20.121107 [ANA_INIT] PLL >>>>>>>>
4996 22:57:20.121205 [ANA_INIT] PLL <<<<<<<<
4997 22:57:20.121295 [ANA_INIT] MIDPI >>>>>>>>
4998 22:57:20.121383 [ANA_INIT] MIDPI <<<<<<<<
4999 22:57:20.121469 [ANA_INIT] DLL >>>>>>>>
5000 22:57:20.121554 [ANA_INIT] flow end
5001 22:57:20.121638 ============ LP4 DIFF to SE enter ============
5002 22:57:20.121750 ============ LP4 DIFF to SE exit ============
5003 22:57:20.121865 [ANA_INIT] <<<<<<<<<<<<<
5004 22:57:20.121925 [Flow] Enable top DCM control >>>>>
5005 22:57:20.121980 [Flow] Enable top DCM control <<<<<
5006 22:57:20.122290 Enable DLL master slave shuffle
5007 22:57:20.122353 ==============================================================
5008 22:57:20.122411 Gating Mode config
5009 22:57:20.122466 ==============================================================
5010 22:57:20.122522 Config description:
5011 22:57:20.122576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5012 22:57:20.122630 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5013 22:57:20.122685 SELPH_MODE 0: By rank 1: By Phase
5014 22:57:20.122738 ==============================================================
5015 22:57:20.122792 GAT_TRACK_EN = 1
5016 22:57:20.122845 RX_GATING_MODE = 2
5017 22:57:20.122898 RX_GATING_TRACK_MODE = 2
5018 22:57:20.122950 SELPH_MODE = 1
5019 22:57:20.123003 PICG_EARLY_EN = 1
5020 22:57:20.123055 VALID_LAT_VALUE = 1
5021 22:57:20.123108 ==============================================================
5022 22:57:20.123161 Enter into Gating configuration >>>>
5023 22:57:20.123214 Exit from Gating configuration <<<<
5024 22:57:20.123266 Enter into DVFS_PRE_config >>>>>
5025 22:57:20.123320 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5026 22:57:20.123374 Exit from DVFS_PRE_config <<<<<
5027 22:57:20.123427 Enter into PICG configuration >>>>
5028 22:57:20.123479 Exit from PICG configuration <<<<
5029 22:57:20.123532 [RX_INPUT] configuration >>>>>
5030 22:57:20.123584 [RX_INPUT] configuration <<<<<
5031 22:57:20.123637 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5032 22:57:20.123689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5033 22:57:20.123743 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 22:57:20.123796 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 22:57:20.123848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 22:57:20.123900 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 22:57:20.123953 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5038 22:57:20.124046 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5039 22:57:20.124099 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5040 22:57:20.124152 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5041 22:57:20.124204 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5042 22:57:20.124257 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5043 22:57:20.124309 ===================================
5044 22:57:20.124362 LPDDR4 DRAM CONFIGURATION
5045 22:57:20.124414 ===================================
5046 22:57:20.124466 EX_ROW_EN[0] = 0x0
5047 22:57:20.124519 EX_ROW_EN[1] = 0x0
5048 22:57:20.124571 LP4Y_EN = 0x0
5049 22:57:20.124623 WORK_FSP = 0x0
5050 22:57:20.124675 WL = 0x3
5051 22:57:20.124728 RL = 0x3
5052 22:57:20.124780 BL = 0x2
5053 22:57:20.124832 RPST = 0x0
5054 22:57:20.124884 RD_PRE = 0x0
5055 22:57:20.124935 WR_PRE = 0x1
5056 22:57:20.124988 WR_PST = 0x0
5057 22:57:20.125039 DBI_WR = 0x0
5058 22:57:20.125091 DBI_RD = 0x0
5059 22:57:20.125143 OTF = 0x1
5060 22:57:20.125196 ===================================
5061 22:57:20.125249 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5062 22:57:20.125302 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5063 22:57:20.125355 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5064 22:57:20.125408 ===================================
5065 22:57:20.125460 LPDDR4 DRAM CONFIGURATION
5066 22:57:20.125513 ===================================
5067 22:57:20.125566 EX_ROW_EN[0] = 0x10
5068 22:57:20.125650 EX_ROW_EN[1] = 0x0
5069 22:57:20.125702 LP4Y_EN = 0x0
5070 22:57:20.125754 WORK_FSP = 0x0
5071 22:57:20.125807 WL = 0x3
5072 22:57:20.125858 RL = 0x3
5073 22:57:20.125911 BL = 0x2
5074 22:57:20.125962 RPST = 0x0
5075 22:57:20.126014 RD_PRE = 0x0
5076 22:57:20.126066 WR_PRE = 0x1
5077 22:57:20.126118 WR_PST = 0x0
5078 22:57:20.126169 DBI_WR = 0x0
5079 22:57:20.126221 DBI_RD = 0x0
5080 22:57:20.126272 OTF = 0x1
5081 22:57:20.126325 ===================================
5082 22:57:20.126377 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5083 22:57:20.126430 nWR fixed to 30
5084 22:57:20.126483 [ModeRegInit_LP4] CH0 RK0
5085 22:57:20.126535 [ModeRegInit_LP4] CH0 RK1
5086 22:57:20.126587 [ModeRegInit_LP4] CH1 RK0
5087 22:57:20.126638 [ModeRegInit_LP4] CH1 RK1
5088 22:57:20.126690 match AC timing 9
5089 22:57:20.126742 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5090 22:57:20.126795 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5091 22:57:20.126848 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5092 22:57:20.126901 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5093 22:57:20.126954 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5094 22:57:20.127006 ==
5095 22:57:20.127058 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 22:57:20.127111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 22:57:20.127164 ==
5098 22:57:20.127216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 22:57:20.127268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5100 22:57:20.127321 [CA 0] Center 37 (6~68) winsize 63
5101 22:57:20.127374 [CA 1] Center 37 (7~68) winsize 62
5102 22:57:20.127426 [CA 2] Center 34 (4~65) winsize 62
5103 22:57:20.127479 [CA 3] Center 34 (3~65) winsize 63
5104 22:57:20.127531 [CA 4] Center 33 (3~64) winsize 62
5105 22:57:20.127583 [CA 5] Center 32 (2~62) winsize 61
5106 22:57:20.127636
5107 22:57:20.127725 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5108 22:57:20.127808
5109 22:57:20.127891 [CATrainingPosCal] consider 1 rank data
5110 22:57:20.127996 u2DelayCellTimex100 = 270/100 ps
5111 22:57:20.128097 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5112 22:57:20.128151 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5113 22:57:20.128205 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5114 22:57:20.128258 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5115 22:57:20.128505 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5116 22:57:20.128565 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5117 22:57:20.128620
5118 22:57:20.128673 CA PerBit enable=1, Macro0, CA PI delay=32
5119 22:57:20.128727
5120 22:57:20.128780 [CBTSetCACLKResult] CA Dly = 32
5121 22:57:20.128833 CS Dly: 5 (0~36)
5122 22:57:20.128886 ==
5123 22:57:20.128939 Dram Type= 6, Freq= 0, CH_0, rank 1
5124 22:57:20.128992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 22:57:20.129046 ==
5126 22:57:20.129116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5127 22:57:20.129184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5128 22:57:20.129237 [CA 0] Center 37 (6~68) winsize 63
5129 22:57:20.129290 [CA 1] Center 37 (6~68) winsize 63
5130 22:57:20.129343 [CA 2] Center 34 (4~65) winsize 62
5131 22:57:20.129396 [CA 3] Center 34 (4~65) winsize 62
5132 22:57:20.129449 [CA 4] Center 33 (3~63) winsize 61
5133 22:57:20.129502 [CA 5] Center 32 (2~62) winsize 61
5134 22:57:20.129554
5135 22:57:20.129607 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5136 22:57:20.129660
5137 22:57:20.129713 [CATrainingPosCal] consider 2 rank data
5138 22:57:20.129766 u2DelayCellTimex100 = 270/100 ps
5139 22:57:20.129819 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5140 22:57:20.129872 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5141 22:57:20.129925 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5142 22:57:20.129978 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5143 22:57:20.130030 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5144 22:57:20.130083 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5145 22:57:20.130135
5146 22:57:20.130187 CA PerBit enable=1, Macro0, CA PI delay=32
5147 22:57:20.130240
5148 22:57:20.130293 [CBTSetCACLKResult] CA Dly = 32
5149 22:57:20.130346 CS Dly: 5 (0~37)
5150 22:57:20.130399
5151 22:57:20.130451 ----->DramcWriteLeveling(PI) begin...
5152 22:57:20.130504 ==
5153 22:57:20.130557 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 22:57:20.130609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 22:57:20.130662 ==
5156 22:57:20.130715 Write leveling (Byte 0): 33 => 33
5157 22:57:20.130768 Write leveling (Byte 1): 32 => 32
5158 22:57:20.130821 DramcWriteLeveling(PI) end<-----
5159 22:57:20.130873
5160 22:57:20.130925 ==
5161 22:57:20.130978 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 22:57:20.131031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 22:57:20.131083 ==
5164 22:57:20.131136 [Gating] SW mode calibration
5165 22:57:20.131189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5166 22:57:20.131243 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5167 22:57:20.131296 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5168 22:57:20.131349 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 22:57:20.131402 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 22:57:20.131455 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 22:57:20.131508 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 22:57:20.131561 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 22:57:20.131614 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5174 22:57:20.131723 0 14 28 | B1->B0 | 3434 2626 | 0 0 | (0 1) (0 0)
5175 22:57:20.131809 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (1 0)
5176 22:57:20.131892 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 22:57:20.131996 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 22:57:20.132067 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 22:57:20.132121 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 22:57:20.132174 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 22:57:20.132228 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5182 22:57:20.132280 0 15 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5183 22:57:20.132334 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5184 22:57:20.132386 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 22:57:20.132439 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 22:57:20.132492 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 22:57:20.132546 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 22:57:20.132599 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 22:57:20.132652 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 22:57:20.132705 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5191 22:57:20.132758 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5192 22:57:20.132810 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 22:57:20.132863 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 22:57:20.132915 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 22:57:20.132968 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 22:57:20.133021 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 22:57:20.133074 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 22:57:20.133127 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 22:57:20.133180 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 22:57:20.133233 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 22:57:20.133286 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 22:57:20.133339 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 22:57:20.133392 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 22:57:20.133445 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 22:57:20.133498 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5206 22:57:20.133550 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5207 22:57:20.133603 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 22:57:20.133658 Total UI for P1: 0, mck2ui 16
5209 22:57:20.133715 best dqsien dly found for B0: ( 1, 2, 26)
5210 22:57:20.133770 Total UI for P1: 0, mck2ui 16
5211 22:57:20.133823 best dqsien dly found for B1: ( 1, 2, 30)
5212 22:57:20.133875 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5213 22:57:20.133928 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5214 22:57:20.133981
5215 22:57:20.134034 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5216 22:57:20.134087 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5217 22:57:20.134139 [Gating] SW calibration Done
5218 22:57:20.134193 ==
5219 22:57:20.134245 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 22:57:20.134487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 22:57:20.134551 ==
5222 22:57:20.134607 RX Vref Scan: 0
5223 22:57:20.134661
5224 22:57:20.134714 RX Vref 0 -> 0, step: 1
5225 22:57:20.134767
5226 22:57:20.134820 RX Delay -80 -> 252, step: 8
5227 22:57:20.134873 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5228 22:57:20.134926 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5229 22:57:20.134980 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5230 22:57:20.135033 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5231 22:57:20.135086 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5232 22:57:20.135139 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5233 22:57:20.135192 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5234 22:57:20.135245 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5235 22:57:20.135298 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5236 22:57:20.135351 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5237 22:57:20.135405 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5238 22:57:20.135457 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5239 22:57:20.135511 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5240 22:57:20.135569 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5241 22:57:20.135637 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5242 22:57:20.135732 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5243 22:57:20.135814 ==
5244 22:57:20.135898 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 22:57:20.136001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 22:57:20.136072 ==
5247 22:57:20.136126 DQS Delay:
5248 22:57:20.136180 DQS0 = 0, DQS1 = 0
5249 22:57:20.136233 DQM Delay:
5250 22:57:20.136286 DQM0 = 104, DQM1 = 94
5251 22:57:20.136339 DQ Delay:
5252 22:57:20.136392 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5253 22:57:20.136445 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5254 22:57:20.136498 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5255 22:57:20.136551 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5256 22:57:20.136604
5257 22:57:20.136657
5258 22:57:20.136709 ==
5259 22:57:20.136762 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 22:57:20.136815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 22:57:20.136868 ==
5262 22:57:20.136921
5263 22:57:20.136973
5264 22:57:20.137026 TX Vref Scan disable
5265 22:57:20.137079 == TX Byte 0 ==
5266 22:57:20.137131 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5267 22:57:20.137185 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5268 22:57:20.137238 == TX Byte 1 ==
5269 22:57:20.137291 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5270 22:57:20.137344 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5271 22:57:20.137397 ==
5272 22:57:20.137450 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 22:57:20.137503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 22:57:20.137556 ==
5275 22:57:20.137609
5276 22:57:20.137662
5277 22:57:20.137714 TX Vref Scan disable
5278 22:57:20.137767 == TX Byte 0 ==
5279 22:57:20.137820 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5280 22:57:20.137874 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5281 22:57:20.137926 == TX Byte 1 ==
5282 22:57:20.137979 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5283 22:57:20.138033 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5284 22:57:20.138085
5285 22:57:20.138137 [DATLAT]
5286 22:57:20.138189 Freq=933, CH0 RK0
5287 22:57:20.138242
5288 22:57:20.138295 DATLAT Default: 0xd
5289 22:57:20.138347 0, 0xFFFF, sum = 0
5290 22:57:20.138402 1, 0xFFFF, sum = 0
5291 22:57:20.138456 2, 0xFFFF, sum = 0
5292 22:57:20.138509 3, 0xFFFF, sum = 0
5293 22:57:20.138564 4, 0xFFFF, sum = 0
5294 22:57:20.138617 5, 0xFFFF, sum = 0
5295 22:57:20.138671 6, 0xFFFF, sum = 0
5296 22:57:20.138725 7, 0xFFFF, sum = 0
5297 22:57:20.138778 8, 0xFFFF, sum = 0
5298 22:57:20.138832 9, 0xFFFF, sum = 0
5299 22:57:20.138885 10, 0x0, sum = 1
5300 22:57:20.138938 11, 0x0, sum = 2
5301 22:57:20.138997 12, 0x0, sum = 3
5302 22:57:20.139055 13, 0x0, sum = 4
5303 22:57:20.139109 best_step = 11
5304 22:57:20.139162
5305 22:57:20.139215 ==
5306 22:57:20.139268 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 22:57:20.139321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 22:57:20.139374 ==
5309 22:57:20.139427 RX Vref Scan: 1
5310 22:57:20.139479
5311 22:57:20.139532 RX Vref 0 -> 0, step: 1
5312 22:57:20.139585
5313 22:57:20.139662 RX Delay -53 -> 252, step: 4
5314 22:57:20.139745
5315 22:57:20.139844 Set Vref, RX VrefLevel [Byte0]: 55
5316 22:57:20.139929 [Byte1]: 55
5317 22:57:20.140031
5318 22:57:20.140086 Final RX Vref Byte 0 = 55 to rank0
5319 22:57:20.140140 Final RX Vref Byte 1 = 55 to rank0
5320 22:57:20.140193 Final RX Vref Byte 0 = 55 to rank1
5321 22:57:20.140247 Final RX Vref Byte 1 = 55 to rank1==
5322 22:57:20.140301 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 22:57:20.140354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 22:57:20.140408 ==
5325 22:57:20.140486 DQS Delay:
5326 22:57:20.140542 DQS0 = 0, DQS1 = 0
5327 22:57:20.140596 DQM Delay:
5328 22:57:20.140659 DQM0 = 104, DQM1 = 98
5329 22:57:20.140715 DQ Delay:
5330 22:57:20.140768 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =104
5331 22:57:20.140821 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5332 22:57:20.140874 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5333 22:57:20.140928 DQ12 =102, DQ13 =102, DQ14 =108, DQ15 =104
5334 22:57:20.140981
5335 22:57:20.141034
5336 22:57:20.141087 [DQSOSCAuto] RK0, (LSB)MR18= 0x3027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5337 22:57:20.141141 CH0 RK0: MR19=505, MR18=3027
5338 22:57:20.141195 CH0_RK0: MR19=0x505, MR18=0x3027, DQSOSC=406, MR23=63, INC=65, DEC=43
5339 22:57:20.141248
5340 22:57:20.141300 ----->DramcWriteLeveling(PI) begin...
5341 22:57:20.141354 ==
5342 22:57:20.141407 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 22:57:20.141460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 22:57:20.141513 ==
5345 22:57:20.141566 Write leveling (Byte 0): 31 => 31
5346 22:57:20.141634 Write leveling (Byte 1): 30 => 30
5347 22:57:20.141689 DramcWriteLeveling(PI) end<-----
5348 22:57:20.141741
5349 22:57:20.141802 ==
5350 22:57:20.141877 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 22:57:20.141984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 22:57:20.142046 ==
5353 22:57:20.142100 [Gating] SW mode calibration
5354 22:57:20.142154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5355 22:57:20.142208 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5356 22:57:20.142263 0 14 0 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
5357 22:57:20.142317 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 22:57:20.142370 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 22:57:20.142423 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 22:57:20.142476 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 22:57:20.142529 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 22:57:20.142596 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
5363 22:57:20.142650 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
5364 22:57:20.142910 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (1 0) (1 0)
5365 22:57:20.142980 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 22:57:20.143036 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 22:57:20.143090 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 22:57:20.143142 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 22:57:20.143195 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 22:57:20.143248 0 15 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5371 22:57:20.143301 0 15 28 | B1->B0 | 3636 3837 | 0 1 | (0 0) (0 0)
5372 22:57:20.143353 1 0 0 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
5373 22:57:20.143406 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 22:57:20.143458 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 22:57:20.143510 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 22:57:20.143563 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 22:57:20.143615 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 22:57:20.143667 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 22:57:20.143720 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5380 22:57:20.143772 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5381 22:57:20.143825 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 22:57:20.143877 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 22:57:20.143929 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 22:57:20.144011 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 22:57:20.144079 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 22:57:20.144132 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 22:57:20.144185 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 22:57:20.144237 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 22:57:20.144289 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 22:57:20.144342 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 22:57:20.144394 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 22:57:20.144447 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 22:57:20.144499 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 22:57:20.144553 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5395 22:57:20.144606 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5396 22:57:20.144658 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5397 22:57:20.144710 Total UI for P1: 0, mck2ui 16
5398 22:57:20.144763 best dqsien dly found for B1: ( 1, 2, 28)
5399 22:57:20.144816 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 22:57:20.144869 Total UI for P1: 0, mck2ui 16
5401 22:57:20.144922 best dqsien dly found for B0: ( 1, 2, 28)
5402 22:57:20.144974 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5403 22:57:20.145026 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5404 22:57:20.145079
5405 22:57:20.145131 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5406 22:57:20.145183 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5407 22:57:20.145235 [Gating] SW calibration Done
5408 22:57:20.145287 ==
5409 22:57:20.145340 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 22:57:20.145392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 22:57:20.145445 ==
5412 22:57:20.145497 RX Vref Scan: 0
5413 22:57:20.145550
5414 22:57:20.145602 RX Vref 0 -> 0, step: 1
5415 22:57:20.145654
5416 22:57:20.145707 RX Delay -80 -> 252, step: 8
5417 22:57:20.145759 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5418 22:57:20.145812 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5419 22:57:20.145865 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5420 22:57:20.145917 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5421 22:57:20.145970 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5422 22:57:20.146022 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5423 22:57:20.146074 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5424 22:57:20.146132 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5425 22:57:20.146189 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5426 22:57:20.146242 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5427 22:57:20.146294 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5428 22:57:20.146346 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5429 22:57:20.146399 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5430 22:57:20.146452 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5431 22:57:20.146505 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5432 22:57:20.146558 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5433 22:57:20.146611 ==
5434 22:57:20.146664 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 22:57:20.146716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 22:57:20.146769 ==
5437 22:57:20.146822 DQS Delay:
5438 22:57:20.146874 DQS0 = 0, DQS1 = 0
5439 22:57:20.146927 DQM Delay:
5440 22:57:20.146979 DQM0 = 104, DQM1 = 95
5441 22:57:20.147031 DQ Delay:
5442 22:57:20.147084 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5443 22:57:20.147136 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5444 22:57:20.147188 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5445 22:57:20.147241 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5446 22:57:20.147293
5447 22:57:20.147345
5448 22:57:20.147397 ==
5449 22:57:20.147449 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 22:57:20.147502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 22:57:20.147555 ==
5452 22:57:20.147607
5453 22:57:20.147658
5454 22:57:20.147710 TX Vref Scan disable
5455 22:57:20.147761 == TX Byte 0 ==
5456 22:57:20.147813 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5457 22:57:20.147865 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5458 22:57:20.147918 == TX Byte 1 ==
5459 22:57:20.148002 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5460 22:57:20.148070 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5461 22:57:20.148123 ==
5462 22:57:20.148176 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 22:57:20.148229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 22:57:20.148282 ==
5465 22:57:20.148333
5466 22:57:20.148385
5467 22:57:20.148437 TX Vref Scan disable
5468 22:57:20.148489 == TX Byte 0 ==
5469 22:57:20.148542 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5470 22:57:20.148594 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5471 22:57:20.148647 == TX Byte 1 ==
5472 22:57:20.148699 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5473 22:57:20.148752 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5474 22:57:20.148805
5475 22:57:20.148858 [DATLAT]
5476 22:57:20.148909 Freq=933, CH0 RK1
5477 22:57:20.148962
5478 22:57:20.149014 DATLAT Default: 0xb
5479 22:57:20.149066 0, 0xFFFF, sum = 0
5480 22:57:20.149120 1, 0xFFFF, sum = 0
5481 22:57:20.149173 2, 0xFFFF, sum = 0
5482 22:57:20.149421 3, 0xFFFF, sum = 0
5483 22:57:20.149480 4, 0xFFFF, sum = 0
5484 22:57:20.149534 5, 0xFFFF, sum = 0
5485 22:57:20.149587 6, 0xFFFF, sum = 0
5486 22:57:20.149640 7, 0xFFFF, sum = 0
5487 22:57:20.149694 8, 0xFFFF, sum = 0
5488 22:57:20.149747 9, 0xFFFF, sum = 0
5489 22:57:20.149800 10, 0x0, sum = 1
5490 22:57:20.149854 11, 0x0, sum = 2
5491 22:57:20.149907 12, 0x0, sum = 3
5492 22:57:20.149960 13, 0x0, sum = 4
5493 22:57:20.150013 best_step = 11
5494 22:57:20.150066
5495 22:57:20.150118 ==
5496 22:57:20.150170 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 22:57:20.150223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 22:57:20.150276 ==
5499 22:57:20.150329 RX Vref Scan: 0
5500 22:57:20.150381
5501 22:57:20.150433 RX Vref 0 -> 0, step: 1
5502 22:57:20.150485
5503 22:57:20.150537 RX Delay -45 -> 252, step: 4
5504 22:57:20.150589 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5505 22:57:20.150642 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5506 22:57:20.150695 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5507 22:57:20.150747 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5508 22:57:20.150799 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5509 22:57:20.150851 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5510 22:57:20.150903 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5511 22:57:20.150956 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5512 22:57:20.151008 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5513 22:57:20.151061 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5514 22:57:20.151113 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5515 22:57:20.151165 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5516 22:57:20.151219 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5517 22:57:20.151271 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5518 22:57:20.151323 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5519 22:57:20.151376 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5520 22:57:20.151428 ==
5521 22:57:20.151480 Dram Type= 6, Freq= 0, CH_0, rank 1
5522 22:57:20.151533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 22:57:20.151585 ==
5524 22:57:20.151637 DQS Delay:
5525 22:57:20.151689 DQS0 = 0, DQS1 = 0
5526 22:57:20.151741 DQM Delay:
5527 22:57:20.151793 DQM0 = 104, DQM1 = 95
5528 22:57:20.151845 DQ Delay:
5529 22:57:20.151897 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =102
5530 22:57:20.151950 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5531 22:57:20.152047 DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =88
5532 22:57:20.152101 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5533 22:57:20.152153
5534 22:57:20.152205
5535 22:57:20.152258 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5536 22:57:20.152312 CH0 RK1: MR19=505, MR18=2A02
5537 22:57:20.152365 CH0_RK1: MR19=0x505, MR18=0x2A02, DQSOSC=408, MR23=63, INC=65, DEC=43
5538 22:57:20.152419 [RxdqsGatingPostProcess] freq 933
5539 22:57:20.152470 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5540 22:57:20.152523 best DQS0 dly(2T, 0.5T) = (0, 10)
5541 22:57:20.152576 best DQS1 dly(2T, 0.5T) = (0, 10)
5542 22:57:20.152628 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5543 22:57:20.152679 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5544 22:57:20.152731 best DQS0 dly(2T, 0.5T) = (0, 10)
5545 22:57:20.152783 best DQS1 dly(2T, 0.5T) = (0, 10)
5546 22:57:20.152835 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5547 22:57:20.152887 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5548 22:57:20.152939 Pre-setting of DQS Precalculation
5549 22:57:20.152991 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5550 22:57:20.153043 ==
5551 22:57:20.153095 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 22:57:20.153147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 22:57:20.153199 ==
5554 22:57:20.153251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 22:57:20.153304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5556 22:57:20.153357 [CA 0] Center 36 (6~67) winsize 62
5557 22:57:20.153409 [CA 1] Center 37 (6~68) winsize 63
5558 22:57:20.153461 [CA 2] Center 34 (4~65) winsize 62
5559 22:57:20.153514 [CA 3] Center 34 (4~65) winsize 62
5560 22:57:20.153565 [CA 4] Center 34 (4~64) winsize 61
5561 22:57:20.153618 [CA 5] Center 33 (3~64) winsize 62
5562 22:57:20.153670
5563 22:57:20.153722 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5564 22:57:20.153774
5565 22:57:20.153826 [CATrainingPosCal] consider 1 rank data
5566 22:57:20.153878 u2DelayCellTimex100 = 270/100 ps
5567 22:57:20.153930 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5568 22:57:20.153983 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5569 22:57:20.154035 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5570 22:57:20.154088 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5571 22:57:20.154140 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5572 22:57:20.154191 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5573 22:57:20.154243
5574 22:57:20.154295 CA PerBit enable=1, Macro0, CA PI delay=33
5575 22:57:20.154347
5576 22:57:20.154398 [CBTSetCACLKResult] CA Dly = 33
5577 22:57:20.154451 CS Dly: 7 (0~38)
5578 22:57:20.154503 ==
5579 22:57:20.154555 Dram Type= 6, Freq= 0, CH_1, rank 1
5580 22:57:20.154607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 22:57:20.154660 ==
5582 22:57:20.154712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5583 22:57:20.154765 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5584 22:57:20.154817 [CA 0] Center 37 (6~68) winsize 63
5585 22:57:20.154869 [CA 1] Center 37 (7~68) winsize 62
5586 22:57:20.154922 [CA 2] Center 35 (4~66) winsize 63
5587 22:57:20.154974 [CA 3] Center 34 (4~65) winsize 62
5588 22:57:20.155026 [CA 4] Center 34 (4~65) winsize 62
5589 22:57:20.155078 [CA 5] Center 34 (4~64) winsize 61
5590 22:57:20.155130
5591 22:57:20.155182 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5592 22:57:20.155234
5593 22:57:20.155286 [CATrainingPosCal] consider 2 rank data
5594 22:57:20.155339 u2DelayCellTimex100 = 270/100 ps
5595 22:57:20.155392 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5596 22:57:20.155444 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5597 22:57:20.155496 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5598 22:57:20.155549 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5599 22:57:20.155601 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5600 22:57:20.155653 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5601 22:57:20.155705
5602 22:57:20.155757 CA PerBit enable=1, Macro0, CA PI delay=34
5603 22:57:20.155810
5604 22:57:20.155862 [CBTSetCACLKResult] CA Dly = 34
5605 22:57:20.155914 CS Dly: 7 (0~39)
5606 22:57:20.155989
5607 22:57:20.156056 ----->DramcWriteLeveling(PI) begin...
5608 22:57:20.156110 ==
5609 22:57:20.156163 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 22:57:20.156405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 22:57:20.156464 ==
5612 22:57:20.156518 Write leveling (Byte 0): 26 => 26
5613 22:57:20.156572 Write leveling (Byte 1): 27 => 27
5614 22:57:20.156624 DramcWriteLeveling(PI) end<-----
5615 22:57:20.156677
5616 22:57:20.156730 ==
5617 22:57:20.156782 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 22:57:20.156834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 22:57:20.156887 ==
5620 22:57:20.156939 [Gating] SW mode calibration
5621 22:57:20.156992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5622 22:57:20.157045 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5623 22:57:20.157098 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 22:57:20.157151 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 22:57:20.157204 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 22:57:20.157256 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 22:57:20.157312 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 22:57:20.157365 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 22:57:20.157417 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
5630 22:57:20.157469 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5631 22:57:20.157522 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 22:57:20.157575 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 22:57:20.157627 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 22:57:20.157679 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 22:57:20.157732 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 22:57:20.157784 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 22:57:20.157836 0 15 24 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
5638 22:57:20.157888 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
5639 22:57:20.157940 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 22:57:20.157992 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 22:57:20.158044 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 22:57:20.158096 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 22:57:20.158148 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 22:57:20.158200 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 22:57:20.158252 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5646 22:57:20.158305 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5647 22:57:20.158357 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 22:57:20.158410 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 22:57:20.158462 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 22:57:20.158514 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 22:57:20.158566 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 22:57:20.158618 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 22:57:20.158671 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 22:57:20.158723 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 22:57:20.158775 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 22:57:20.158827 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 22:57:20.158879 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 22:57:20.158932 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 22:57:20.158984 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 22:57:20.159035 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5661 22:57:20.159088 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5662 22:57:20.159140 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5663 22:57:20.159191 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 22:57:20.159244 Total UI for P1: 0, mck2ui 16
5665 22:57:20.159296 best dqsien dly found for B0: ( 1, 2, 28)
5666 22:57:20.159350 Total UI for P1: 0, mck2ui 16
5667 22:57:20.159402 best dqsien dly found for B1: ( 1, 2, 24)
5668 22:57:20.159455 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5669 22:57:20.159507 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5670 22:57:20.159560
5671 22:57:20.159611 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5672 22:57:20.159664 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5673 22:57:20.159717 [Gating] SW calibration Done
5674 22:57:20.159769 ==
5675 22:57:20.159857 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 22:57:20.159941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 22:57:20.160038 ==
5678 22:57:20.160092 RX Vref Scan: 0
5679 22:57:20.160144
5680 22:57:20.160197 RX Vref 0 -> 0, step: 1
5681 22:57:20.160249
5682 22:57:20.160301 RX Delay -80 -> 252, step: 8
5683 22:57:20.160353 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5684 22:57:20.160406 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5685 22:57:20.160458 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5686 22:57:20.160511 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5687 22:57:20.160563 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5688 22:57:20.160614 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5689 22:57:20.160666 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5690 22:57:20.160719 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5691 22:57:20.160771 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5692 22:57:20.160822 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5693 22:57:20.160874 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5694 22:57:20.160927 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5695 22:57:20.160979 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5696 22:57:20.161030 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5697 22:57:20.161082 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5698 22:57:20.161134 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5699 22:57:20.161186 ==
5700 22:57:20.161238 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 22:57:20.161291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 22:57:20.161343 ==
5703 22:57:20.161396 DQS Delay:
5704 22:57:20.161447 DQS0 = 0, DQS1 = 0
5705 22:57:20.161501 DQM Delay:
5706 22:57:20.161553 DQM0 = 103, DQM1 = 98
5707 22:57:20.161605 DQ Delay:
5708 22:57:20.161657 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =103
5709 22:57:20.161709 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =107
5710 22:57:20.161761 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5711 22:57:20.161814 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =103
5712 22:57:20.161866
5713 22:57:20.161917
5714 22:57:20.161969 ==
5715 22:57:20.162217 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 22:57:20.162281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 22:57:20.162335 ==
5718 22:57:20.162388
5719 22:57:20.162440
5720 22:57:20.162491 TX Vref Scan disable
5721 22:57:20.162543 == TX Byte 0 ==
5722 22:57:20.162596 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5723 22:57:20.162649 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5724 22:57:20.162702 == TX Byte 1 ==
5725 22:57:20.162754 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5726 22:57:20.162807 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5727 22:57:20.162859 ==
5728 22:57:20.162923 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 22:57:20.169214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 22:57:20.169297 ==
5731 22:57:20.169362
5732 22:57:20.169421
5733 22:57:20.169478 TX Vref Scan disable
5734 22:57:20.173490 == TX Byte 0 ==
5735 22:57:20.176901 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5736 22:57:20.183151 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5737 22:57:20.183233 == TX Byte 1 ==
5738 22:57:20.186739 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5739 22:57:20.193391 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5740 22:57:20.193474
5741 22:57:20.193538 [DATLAT]
5742 22:57:20.193597 Freq=933, CH1 RK0
5743 22:57:20.193663
5744 22:57:20.196687 DATLAT Default: 0xd
5745 22:57:20.196768 0, 0xFFFF, sum = 0
5746 22:57:20.200549 1, 0xFFFF, sum = 0
5747 22:57:20.200632 2, 0xFFFF, sum = 0
5748 22:57:20.203404 3, 0xFFFF, sum = 0
5749 22:57:20.203486 4, 0xFFFF, sum = 0
5750 22:57:20.206721 5, 0xFFFF, sum = 0
5751 22:57:20.210264 6, 0xFFFF, sum = 0
5752 22:57:20.210348 7, 0xFFFF, sum = 0
5753 22:57:20.213548 8, 0xFFFF, sum = 0
5754 22:57:20.213631 9, 0xFFFF, sum = 0
5755 22:57:20.217022 10, 0x0, sum = 1
5756 22:57:20.217104 11, 0x0, sum = 2
5757 22:57:20.217170 12, 0x0, sum = 3
5758 22:57:20.219995 13, 0x0, sum = 4
5759 22:57:20.220092 best_step = 11
5760 22:57:20.220156
5761 22:57:20.223657 ==
5762 22:57:20.223739 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 22:57:20.230072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 22:57:20.230157 ==
5765 22:57:20.230223 RX Vref Scan: 1
5766 22:57:20.230284
5767 22:57:20.233657 RX Vref 0 -> 0, step: 1
5768 22:57:20.233739
5769 22:57:20.236423 RX Delay -45 -> 252, step: 4
5770 22:57:20.236532
5771 22:57:20.239565 Set Vref, RX VrefLevel [Byte0]: 53
5772 22:57:20.243302 [Byte1]: 53
5773 22:57:20.243419
5774 22:57:20.246288 Final RX Vref Byte 0 = 53 to rank0
5775 22:57:20.250048 Final RX Vref Byte 1 = 53 to rank0
5776 22:57:20.253274 Final RX Vref Byte 0 = 53 to rank1
5777 22:57:20.256546 Final RX Vref Byte 1 = 53 to rank1==
5778 22:57:20.259886 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 22:57:20.262961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 22:57:20.263045 ==
5781 22:57:20.266151 DQS Delay:
5782 22:57:20.266234 DQS0 = 0, DQS1 = 0
5783 22:57:20.269395 DQM Delay:
5784 22:57:20.269478 DQM0 = 103, DQM1 = 99
5785 22:57:20.273106 DQ Delay:
5786 22:57:20.276282 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5787 22:57:20.279671 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5788 22:57:20.282906 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =94
5789 22:57:20.286123 DQ12 =104, DQ13 =104, DQ14 =106, DQ15 =108
5790 22:57:20.286206
5791 22:57:20.286271
5792 22:57:20.292792 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5793 22:57:20.295951 CH1 RK0: MR19=505, MR18=1B32
5794 22:57:20.302977 CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43
5795 22:57:20.303060
5796 22:57:20.306318 ----->DramcWriteLeveling(PI) begin...
5797 22:57:20.306402 ==
5798 22:57:20.309635 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 22:57:20.312986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 22:57:20.313070 ==
5801 22:57:20.315807 Write leveling (Byte 0): 26 => 26
5802 22:57:20.319678 Write leveling (Byte 1): 26 => 26
5803 22:57:20.323006 DramcWriteLeveling(PI) end<-----
5804 22:57:20.323088
5805 22:57:20.323152 ==
5806 22:57:20.325735 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 22:57:20.328963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 22:57:20.332415 ==
5809 22:57:20.332496 [Gating] SW mode calibration
5810 22:57:20.339148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5811 22:57:20.345835 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5812 22:57:20.348852 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 22:57:20.355759 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 22:57:20.359432 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 22:57:20.362788 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 22:57:20.369473 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 22:57:20.372724 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 22:57:20.375817 0 14 24 | B1->B0 | 2b2b 3030 | 0 0 | (1 0) (0 1)
5819 22:57:20.382372 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5820 22:57:20.386329 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 22:57:20.389512 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 22:57:20.392824 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 22:57:20.399270 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 22:57:20.402328 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 22:57:20.406181 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 22:57:20.412682 0 15 24 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
5827 22:57:20.415780 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5828 22:57:20.419051 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 22:57:20.425659 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 22:57:20.429044 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 22:57:20.432483 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 22:57:20.439239 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 22:57:20.442435 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 22:57:20.445409 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5835 22:57:20.452376 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5836 22:57:20.455520 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 22:57:20.459021 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 22:57:20.465446 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 22:57:20.468610 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 22:57:20.471843 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 22:57:20.478696 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 22:57:20.481779 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 22:57:20.485164 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 22:57:20.491683 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 22:57:20.495040 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 22:57:20.498161 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 22:57:20.505012 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 22:57:20.508763 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 22:57:20.511748 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 22:57:20.518243 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5851 22:57:20.521849 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 22:57:20.525557 Total UI for P1: 0, mck2ui 16
5853 22:57:20.528730 best dqsien dly found for B0: ( 1, 2, 24)
5854 22:57:20.531869 Total UI for P1: 0, mck2ui 16
5855 22:57:20.535040 best dqsien dly found for B1: ( 1, 2, 24)
5856 22:57:20.538284 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5857 22:57:20.541703 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5858 22:57:20.541786
5859 22:57:20.544621 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5860 22:57:20.547868 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5861 22:57:20.551608 [Gating] SW calibration Done
5862 22:57:20.551692 ==
5863 22:57:20.554811 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 22:57:20.558177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 22:57:20.561283 ==
5866 22:57:20.561439 RX Vref Scan: 0
5867 22:57:20.561539
5868 22:57:20.565082 RX Vref 0 -> 0, step: 1
5869 22:57:20.565166
5870 22:57:20.565231 RX Delay -80 -> 252, step: 8
5871 22:57:20.571569 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5872 22:57:20.574843 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5873 22:57:20.578504 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5874 22:57:20.581822 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5875 22:57:20.584793 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5876 22:57:20.588323 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5877 22:57:20.594916 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5878 22:57:20.598287 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5879 22:57:20.601331 iDelay=208, Bit 8, Center 95 (8 ~ 183) 176
5880 22:57:20.604546 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5881 22:57:20.608306 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5882 22:57:20.611410 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5883 22:57:20.618214 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5884 22:57:20.621595 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5885 22:57:20.624814 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5886 22:57:20.627909 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5887 22:57:20.628059 ==
5888 22:57:20.631260 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 22:57:20.638323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 22:57:20.638412 ==
5891 22:57:20.638479 DQS Delay:
5892 22:57:20.641549 DQS0 = 0, DQS1 = 0
5893 22:57:20.641632 DQM Delay:
5894 22:57:20.641697 DQM0 = 103, DQM1 = 100
5895 22:57:20.644742 DQ Delay:
5896 22:57:20.647939 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5897 22:57:20.651250 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5898 22:57:20.654361 DQ8 =95, DQ9 =91, DQ10 =99, DQ11 =95
5899 22:57:20.658261 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5900 22:57:20.658345
5901 22:57:20.658410
5902 22:57:20.658471 ==
5903 22:57:20.661648 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 22:57:20.664678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 22:57:20.664761 ==
5906 22:57:20.664830
5907 22:57:20.664898
5908 22:57:20.667950 TX Vref Scan disable
5909 22:57:20.671136 == TX Byte 0 ==
5910 22:57:20.675013 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5911 22:57:20.678210 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5912 22:57:20.681331 == TX Byte 1 ==
5913 22:57:20.684528 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5914 22:57:20.687760 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5915 22:57:20.687849 ==
5916 22:57:20.691245 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 22:57:20.698198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 22:57:20.698282 ==
5919 22:57:20.698348
5920 22:57:20.698409
5921 22:57:20.698468 TX Vref Scan disable
5922 22:57:20.701767 == TX Byte 0 ==
5923 22:57:20.704907 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5924 22:57:20.711801 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5925 22:57:20.711885 == TX Byte 1 ==
5926 22:57:20.714830 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5927 22:57:20.721639 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5928 22:57:20.721723
5929 22:57:20.721789 [DATLAT]
5930 22:57:20.721849 Freq=933, CH1 RK1
5931 22:57:20.721909
5932 22:57:20.725240 DATLAT Default: 0xb
5933 22:57:20.725323 0, 0xFFFF, sum = 0
5934 22:57:20.728013 1, 0xFFFF, sum = 0
5935 22:57:20.728098 2, 0xFFFF, sum = 0
5936 22:57:20.731898 3, 0xFFFF, sum = 0
5937 22:57:20.734808 4, 0xFFFF, sum = 0
5938 22:57:20.734918 5, 0xFFFF, sum = 0
5939 22:57:20.737800 6, 0xFFFF, sum = 0
5940 22:57:20.737884 7, 0xFFFF, sum = 0
5941 22:57:20.741611 8, 0xFFFF, sum = 0
5942 22:57:20.741695 9, 0xFFFF, sum = 0
5943 22:57:20.744757 10, 0x0, sum = 1
5944 22:57:20.744841 11, 0x0, sum = 2
5945 22:57:20.744908 12, 0x0, sum = 3
5946 22:57:20.748112 13, 0x0, sum = 4
5947 22:57:20.748198 best_step = 11
5948 22:57:20.748264
5949 22:57:20.751160 ==
5950 22:57:20.754889 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 22:57:20.758235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 22:57:20.758373 ==
5953 22:57:20.758502 RX Vref Scan: 0
5954 22:57:20.758611
5955 22:57:20.761466 RX Vref 0 -> 0, step: 1
5956 22:57:20.761574
5957 22:57:20.764646 RX Delay -45 -> 252, step: 4
5958 22:57:20.768250 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5959 22:57:20.774639 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5960 22:57:20.777763 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5961 22:57:20.781443 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5962 22:57:20.784690 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5963 22:57:20.787886 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5964 22:57:20.794732 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5965 22:57:20.797858 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5966 22:57:20.801121 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5967 22:57:20.804836 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5968 22:57:20.808048 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5969 22:57:20.811303 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5970 22:57:20.817916 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5971 22:57:20.821462 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5972 22:57:20.824322 iDelay=203, Bit 14, Center 104 (19 ~ 190) 172
5973 22:57:20.827980 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5974 22:57:20.828076 ==
5975 22:57:20.831048 Dram Type= 6, Freq= 0, CH_1, rank 1
5976 22:57:20.838086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5977 22:57:20.838173 ==
5978 22:57:20.838238 DQS Delay:
5979 22:57:20.841247 DQS0 = 0, DQS1 = 0
5980 22:57:20.841328 DQM Delay:
5981 22:57:20.841392 DQM0 = 104, DQM1 = 98
5982 22:57:20.844861 DQ Delay:
5983 22:57:20.847727 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5984 22:57:20.851062 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =102
5985 22:57:20.854334 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
5986 22:57:20.857982 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =106
5987 22:57:21.263799
5988 22:57:21.263944
5989 22:57:21.264258 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5990 22:57:21.264356 CH1 RK1: MR19=505, MR18=2E01
5991 22:57:21.264417 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5992 22:57:21.264475 [RxdqsGatingPostProcess] freq 933
5993 22:57:21.264532 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5994 22:57:21.264587 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 22:57:21.264642 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 22:57:21.264697 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 22:57:21.264751 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 22:57:21.264804 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 22:57:21.264872 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 22:57:21.264926 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 22:57:21.264980 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 22:57:21.265034 Pre-setting of DQS Precalculation
6003 22:57:21.265088 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6004 22:57:21.265143 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6005 22:57:21.265198 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6006 22:57:21.265252
6007 22:57:21.265320
6008 22:57:21.265372 [Calibration Summary] 1866 Mbps
6009 22:57:21.265425 CH 0, Rank 0
6010 22:57:21.265493 SW Impedance : PASS
6011 22:57:21.265547 DUTY Scan : NO K
6012 22:57:21.265601 ZQ Calibration : PASS
6013 22:57:21.265658 Jitter Meter : NO K
6014 22:57:21.265763 CBT Training : PASS
6015 22:57:21.265860 Write leveling : PASS
6016 22:57:21.265947 RX DQS gating : PASS
6017 22:57:21.266002 RX DQ/DQS(RDDQC) : PASS
6018 22:57:21.266055 TX DQ/DQS : PASS
6019 22:57:21.266109 RX DATLAT : PASS
6020 22:57:21.266162 RX DQ/DQS(Engine): PASS
6021 22:57:21.266214 TX OE : NO K
6022 22:57:21.266282 All Pass.
6023 22:57:21.266349
6024 22:57:21.266417 CH 0, Rank 1
6025 22:57:21.266484 SW Impedance : PASS
6026 22:57:21.266536 DUTY Scan : NO K
6027 22:57:21.266605 ZQ Calibration : PASS
6028 22:57:21.266659 Jitter Meter : NO K
6029 22:57:21.266713 CBT Training : PASS
6030 22:57:21.266766 Write leveling : PASS
6031 22:57:21.266848 RX DQS gating : PASS
6032 22:57:21.266902 RX DQ/DQS(RDDQC) : PASS
6033 22:57:21.266968 TX DQ/DQS : PASS
6034 22:57:21.267020 RX DATLAT : PASS
6035 22:57:21.267072 RX DQ/DQS(Engine): PASS
6036 22:57:21.267124 TX OE : NO K
6037 22:57:21.267177 All Pass.
6038 22:57:21.267246
6039 22:57:21.267299 CH 1, Rank 0
6040 22:57:21.267352 SW Impedance : PASS
6041 22:57:21.267418 DUTY Scan : NO K
6042 22:57:21.267471 ZQ Calibration : PASS
6043 22:57:21.267523 Jitter Meter : NO K
6044 22:57:21.267591 CBT Training : PASS
6045 22:57:21.267676 Write leveling : PASS
6046 22:57:21.267802 RX DQS gating : PASS
6047 22:57:21.267887 RX DQ/DQS(RDDQC) : PASS
6048 22:57:21.267997 TX DQ/DQS : PASS
6049 22:57:21.268054 RX DATLAT : PASS
6050 22:57:21.268107 RX DQ/DQS(Engine): PASS
6051 22:57:21.268176 TX OE : NO K
6052 22:57:21.268244 All Pass.
6053 22:57:21.268297
6054 22:57:21.268365 CH 1, Rank 1
6055 22:57:21.268430 SW Impedance : PASS
6056 22:57:21.268483 DUTY Scan : NO K
6057 22:57:21.268535 ZQ Calibration : PASS
6058 22:57:21.268587 Jitter Meter : NO K
6059 22:57:21.268639 CBT Training : PASS
6060 22:57:21.268692 Write leveling : PASS
6061 22:57:21.268776 RX DQS gating : PASS
6062 22:57:21.268828 RX DQ/DQS(RDDQC) : PASS
6063 22:57:21.268880 TX DQ/DQS : PASS
6064 22:57:21.268945 RX DATLAT : PASS
6065 22:57:21.269012 RX DQ/DQS(Engine): PASS
6066 22:57:21.269064 TX OE : NO K
6067 22:57:21.269116 All Pass.
6068 22:57:21.269168
6069 22:57:21.269220 DramC Write-DBI off
6070 22:57:21.269272 PER_BANK_REFRESH: Hybrid Mode
6071 22:57:21.269325 TX_TRACKING: ON
6072 22:57:21.269377 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6073 22:57:21.269431 [FAST_K] Save calibration result to emmc
6074 22:57:21.269483 dramc_set_vcore_voltage set vcore to 650000
6075 22:57:21.269552 Read voltage for 400, 6
6076 22:57:21.269605 Vio18 = 0
6077 22:57:21.269658 Vcore = 650000
6078 22:57:21.269711 Vdram = 0
6079 22:57:21.269764 Vddq = 0
6080 22:57:21.269817 Vmddr = 0
6081 22:57:21.269870 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6082 22:57:21.269925 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6083 22:57:21.269979 MEM_TYPE=3, freq_sel=20
6084 22:57:21.270046 sv_algorithm_assistance_LP4_800
6085 22:57:21.270098 ============ PULL DRAM RESETB DOWN ============
6086 22:57:21.270152 ========== PULL DRAM RESETB DOWN end =========
6087 22:57:21.270205 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6088 22:57:21.270285 ===================================
6089 22:57:21.270337 LPDDR4 DRAM CONFIGURATION
6090 22:57:21.270389 ===================================
6091 22:57:21.270455 EX_ROW_EN[0] = 0x0
6092 22:57:21.270522 EX_ROW_EN[1] = 0x0
6093 22:57:21.270574 LP4Y_EN = 0x0
6094 22:57:21.270627 WORK_FSP = 0x0
6095 22:57:21.270695 WL = 0x2
6096 22:57:21.270761 RL = 0x2
6097 22:57:21.270812 BL = 0x2
6098 22:57:21.270864 RPST = 0x0
6099 22:57:21.270916 RD_PRE = 0x0
6100 22:57:21.270968 WR_PRE = 0x1
6101 22:57:21.271020 WR_PST = 0x0
6102 22:57:21.271071 DBI_WR = 0x0
6103 22:57:21.271123 DBI_RD = 0x0
6104 22:57:21.271175 OTF = 0x1
6105 22:57:21.271228 ===================================
6106 22:57:21.271279 ===================================
6107 22:57:21.271331 ANA top config
6108 22:57:21.271383 ===================================
6109 22:57:21.271436 DLL_ASYNC_EN = 0
6110 22:57:21.271487 ALL_SLAVE_EN = 1
6111 22:57:21.271539 NEW_RANK_MODE = 1
6112 22:57:21.271591 DLL_IDLE_MODE = 1
6113 22:57:21.271644 LP45_APHY_COMB_EN = 1
6114 22:57:21.271726 TX_ODT_DIS = 1
6115 22:57:21.271869 NEW_8X_MODE = 1
6116 22:57:21.271962 ===================================
6117 22:57:21.272034 ===================================
6118 22:57:21.272088 data_rate = 800
6119 22:57:21.272141 CKR = 1
6120 22:57:21.272194 DQ_P2S_RATIO = 4
6121 22:57:21.272246 ===================================
6122 22:57:21.272299 CA_P2S_RATIO = 4
6123 22:57:21.272351 DQ_CA_OPEN = 0
6124 22:57:21.272403 DQ_SEMI_OPEN = 1
6125 22:57:21.272456 CA_SEMI_OPEN = 1
6126 22:57:21.272508 CA_FULL_RATE = 0
6127 22:57:21.272560 DQ_CKDIV4_EN = 0
6128 22:57:21.272612 CA_CKDIV4_EN = 1
6129 22:57:21.272664 CA_PREDIV_EN = 0
6130 22:57:21.272716 PH8_DLY = 0
6131 22:57:21.272966 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6132 22:57:21.273028 DQ_AAMCK_DIV = 0
6133 22:57:21.273082 CA_AAMCK_DIV = 0
6134 22:57:21.273135 CA_ADMCK_DIV = 4
6135 22:57:21.273188 DQ_TRACK_CA_EN = 0
6136 22:57:21.273241 CA_PICK = 800
6137 22:57:21.273293 CA_MCKIO = 400
6138 22:57:21.273346 MCKIO_SEMI = 400
6139 22:57:21.273398 PLL_FREQ = 3016
6140 22:57:21.273451 DQ_UI_PI_RATIO = 32
6141 22:57:21.273503 CA_UI_PI_RATIO = 32
6142 22:57:21.273556 ===================================
6143 22:57:21.273608 ===================================
6144 22:57:21.273661 memory_type:LPDDR4
6145 22:57:21.273714 GP_NUM : 10
6146 22:57:21.273767 SRAM_EN : 1
6147 22:57:21.273820 MD32_EN : 0
6148 22:57:21.273873 ===================================
6149 22:57:21.273926 [ANA_INIT] >>>>>>>>>>>>>>
6150 22:57:21.273979 <<<<<< [CONFIGURE PHASE]: ANA_TX
6151 22:57:21.274032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6152 22:57:21.274097 ===================================
6153 22:57:21.276180 data_rate = 800,PCW = 0X7400
6154 22:57:21.279953 ===================================
6155 22:57:21.283402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6156 22:57:21.286766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 22:57:21.299355 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 22:57:21.303287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6159 22:57:21.306549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6160 22:57:21.309259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6161 22:57:21.312956 [ANA_INIT] flow start
6162 22:57:21.313039 [ANA_INIT] PLL >>>>>>>>
6163 22:57:21.316154 [ANA_INIT] PLL <<<<<<<<
6164 22:57:21.319296 [ANA_INIT] MIDPI >>>>>>>>
6165 22:57:21.323020 [ANA_INIT] MIDPI <<<<<<<<
6166 22:57:21.323103 [ANA_INIT] DLL >>>>>>>>
6167 22:57:21.326325 [ANA_INIT] flow end
6168 22:57:21.329521 ============ LP4 DIFF to SE enter ============
6169 22:57:21.332735 ============ LP4 DIFF to SE exit ============
6170 22:57:21.335854 [ANA_INIT] <<<<<<<<<<<<<
6171 22:57:21.339156 [Flow] Enable top DCM control >>>>>
6172 22:57:21.343185 [Flow] Enable top DCM control <<<<<
6173 22:57:21.346076 Enable DLL master slave shuffle
6174 22:57:21.352657 ==============================================================
6175 22:57:21.352743 Gating Mode config
6176 22:57:21.359059 ==============================================================
6177 22:57:21.359143 Config description:
6178 22:57:21.369470 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6179 22:57:21.376221 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6180 22:57:21.382324 SELPH_MODE 0: By rank 1: By Phase
6181 22:57:21.385655 ==============================================================
6182 22:57:21.389164 GAT_TRACK_EN = 0
6183 22:57:21.392553 RX_GATING_MODE = 2
6184 22:57:21.395964 RX_GATING_TRACK_MODE = 2
6185 22:57:21.399083 SELPH_MODE = 1
6186 22:57:21.402903 PICG_EARLY_EN = 1
6187 22:57:21.406026 VALID_LAT_VALUE = 1
6188 22:57:21.409400 ==============================================================
6189 22:57:21.415943 Enter into Gating configuration >>>>
6190 22:57:21.419096 Exit from Gating configuration <<<<
6191 22:57:21.419179 Enter into DVFS_PRE_config >>>>>
6192 22:57:21.432700 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6193 22:57:21.435731 Exit from DVFS_PRE_config <<<<<
6194 22:57:21.439238 Enter into PICG configuration >>>>
6195 22:57:21.441994 Exit from PICG configuration <<<<
6196 22:57:21.442077 [RX_INPUT] configuration >>>>>
6197 22:57:21.445337 [RX_INPUT] configuration <<<<<
6198 22:57:21.452384 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6199 22:57:21.455804 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6200 22:57:21.462611 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6201 22:57:21.469162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6202 22:57:21.475671 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6203 22:57:21.482337 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6204 22:57:21.485570 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6205 22:57:21.489151 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6206 22:57:21.495641 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6207 22:57:21.498593 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6208 22:57:21.502314 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6209 22:57:21.505933 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6210 22:57:21.508600 ===================================
6211 22:57:21.511934 LPDDR4 DRAM CONFIGURATION
6212 22:57:21.515251 ===================================
6213 22:57:21.518680 EX_ROW_EN[0] = 0x0
6214 22:57:21.518764 EX_ROW_EN[1] = 0x0
6215 22:57:21.521997 LP4Y_EN = 0x0
6216 22:57:21.522159 WORK_FSP = 0x0
6217 22:57:21.524993 WL = 0x2
6218 22:57:21.525112 RL = 0x2
6219 22:57:21.528930 BL = 0x2
6220 22:57:21.529006 RPST = 0x0
6221 22:57:21.532215 RD_PRE = 0x0
6222 22:57:21.532301 WR_PRE = 0x1
6223 22:57:21.535663 WR_PST = 0x0
6224 22:57:21.535745 DBI_WR = 0x0
6225 22:57:21.538561 DBI_RD = 0x0
6226 22:57:21.541813 OTF = 0x1
6227 22:57:21.545013 ===================================
6228 22:57:21.548535 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6229 22:57:21.551551 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6230 22:57:21.555297 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6231 22:57:21.558527 ===================================
6232 22:57:21.561889 LPDDR4 DRAM CONFIGURATION
6233 22:57:21.565296 ===================================
6234 22:57:21.568470 EX_ROW_EN[0] = 0x10
6235 22:57:21.568553 EX_ROW_EN[1] = 0x0
6236 22:57:21.571634 LP4Y_EN = 0x0
6237 22:57:21.571742 WORK_FSP = 0x0
6238 22:57:21.575286 WL = 0x2
6239 22:57:21.575368 RL = 0x2
6240 22:57:21.578346 BL = 0x2
6241 22:57:21.578455 RPST = 0x0
6242 22:57:21.581507 RD_PRE = 0x0
6243 22:57:21.581590 WR_PRE = 0x1
6244 22:57:21.585239 WR_PST = 0x0
6245 22:57:21.585325 DBI_WR = 0x0
6246 22:57:21.588339 DBI_RD = 0x0
6247 22:57:21.588445 OTF = 0x1
6248 22:57:21.591472 ===================================
6249 22:57:21.598412 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6250 22:57:21.603058 nWR fixed to 30
6251 22:57:21.606296 [ModeRegInit_LP4] CH0 RK0
6252 22:57:21.606482 [ModeRegInit_LP4] CH0 RK1
6253 22:57:21.609734 [ModeRegInit_LP4] CH1 RK0
6254 22:57:21.612903 [ModeRegInit_LP4] CH1 RK1
6255 22:57:21.612987 match AC timing 19
6256 22:57:21.619444 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6257 22:57:21.622713 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6258 22:57:21.626485 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6259 22:57:21.632768 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6260 22:57:21.636196 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6261 22:57:21.636281 ==
6262 22:57:21.639583 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 22:57:21.642849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 22:57:21.642933 ==
6265 22:57:21.649364 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6266 22:57:21.656298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6267 22:57:21.659703 [CA 0] Center 36 (8~64) winsize 57
6268 22:57:21.662836 [CA 1] Center 36 (8~64) winsize 57
6269 22:57:21.665999 [CA 2] Center 36 (8~64) winsize 57
6270 22:57:21.666082 [CA 3] Center 36 (8~64) winsize 57
6271 22:57:21.669766 [CA 4] Center 36 (8~64) winsize 57
6272 22:57:21.672762 [CA 5] Center 36 (8~64) winsize 57
6273 22:57:21.672848
6274 22:57:21.679468 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6275 22:57:21.679554
6276 22:57:21.683221 [CATrainingPosCal] consider 1 rank data
6277 22:57:21.686276 u2DelayCellTimex100 = 270/100 ps
6278 22:57:21.689698 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 22:57:21.692865 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 22:57:21.696053 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 22:57:21.699870 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 22:57:21.702867 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 22:57:21.706155 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 22:57:21.706237
6285 22:57:21.709931 CA PerBit enable=1, Macro0, CA PI delay=36
6286 22:57:21.710013
6287 22:57:21.712654 [CBTSetCACLKResult] CA Dly = 36
6288 22:57:21.716320 CS Dly: 1 (0~32)
6289 22:57:21.716402 ==
6290 22:57:21.719562 Dram Type= 6, Freq= 0, CH_0, rank 1
6291 22:57:21.722745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 22:57:21.722828 ==
6293 22:57:21.729741 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6294 22:57:21.733137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6295 22:57:21.736341 [CA 0] Center 36 (8~64) winsize 57
6296 22:57:21.739399 [CA 1] Center 36 (8~64) winsize 57
6297 22:57:21.742821 [CA 2] Center 36 (8~64) winsize 57
6298 22:57:21.745896 [CA 3] Center 36 (8~64) winsize 57
6299 22:57:21.749316 [CA 4] Center 36 (8~64) winsize 57
6300 22:57:21.752597 [CA 5] Center 36 (8~64) winsize 57
6301 22:57:21.752679
6302 22:57:21.756035 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6303 22:57:21.756118
6304 22:57:21.759251 [CATrainingPosCal] consider 2 rank data
6305 22:57:21.762835 u2DelayCellTimex100 = 270/100 ps
6306 22:57:21.765892 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 22:57:21.769494 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 22:57:21.772527 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 22:57:21.779314 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 22:57:21.782707 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 22:57:21.785725 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 22:57:21.785810
6313 22:57:21.788985 CA PerBit enable=1, Macro0, CA PI delay=36
6314 22:57:21.789071
6315 22:57:21.792735 [CBTSetCACLKResult] CA Dly = 36
6316 22:57:21.792819 CS Dly: 1 (0~32)
6317 22:57:21.792885
6318 22:57:21.795685 ----->DramcWriteLeveling(PI) begin...
6319 22:57:21.795769 ==
6320 22:57:21.798900 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 22:57:21.805946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 22:57:21.806032 ==
6323 22:57:21.809342 Write leveling (Byte 0): 40 => 8
6324 22:57:21.812449 Write leveling (Byte 1): 40 => 8
6325 22:57:21.812532 DramcWriteLeveling(PI) end<-----
6326 22:57:21.815475
6327 22:57:21.815561 ==
6328 22:57:21.819031 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 22:57:21.822541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 22:57:21.822626 ==
6331 22:57:21.825887 [Gating] SW mode calibration
6332 22:57:21.832209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6333 22:57:21.835300 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6334 22:57:21.842442 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 22:57:21.845646 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 22:57:21.849028 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 22:57:21.855454 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 22:57:21.858693 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 22:57:21.862070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 22:57:21.868727 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 22:57:21.872608 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 22:57:21.875674 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 22:57:21.879077 Total UI for P1: 0, mck2ui 16
6344 22:57:21.882606 best dqsien dly found for B0: ( 0, 14, 24)
6345 22:57:21.885332 Total UI for P1: 0, mck2ui 16
6346 22:57:21.888856 best dqsien dly found for B1: ( 0, 14, 24)
6347 22:57:21.892131 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6348 22:57:21.895347 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6349 22:57:21.895431
6350 22:57:21.901647 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 22:57:21.905954 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 22:57:21.908469 [Gating] SW calibration Done
6353 22:57:21.908566 ==
6354 22:57:21.911582 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 22:57:21.914975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 22:57:21.915087 ==
6357 22:57:21.915182 RX Vref Scan: 0
6358 22:57:21.915271
6359 22:57:21.918691 RX Vref 0 -> 0, step: 1
6360 22:57:21.918788
6361 22:57:21.922307 RX Delay -410 -> 252, step: 16
6362 22:57:21.924910 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6363 22:57:21.931679 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6364 22:57:21.935219 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6365 22:57:21.938406 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6366 22:57:21.941594 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6367 22:57:21.948129 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6368 22:57:21.951700 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6369 22:57:21.955004 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6370 22:57:21.958192 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6371 22:57:21.964816 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6372 22:57:21.968580 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6373 22:57:21.971704 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6374 22:57:21.974678 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6375 22:57:21.981561 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6376 22:57:21.984816 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6377 22:57:21.988052 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6378 22:57:21.988134 ==
6379 22:57:21.991786 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 22:57:21.994742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 22:57:21.997971 ==
6382 22:57:21.998053 DQS Delay:
6383 22:57:21.998118 DQS0 = 27, DQS1 = 35
6384 22:57:22.001687 DQM Delay:
6385 22:57:22.001769 DQM0 = 10, DQM1 = 11
6386 22:57:22.004966 DQ Delay:
6387 22:57:22.005047 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6388 22:57:22.008081 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6389 22:57:22.011269 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6390 22:57:22.014817 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6391 22:57:22.014899
6392 22:57:22.014963
6393 22:57:22.015022 ==
6394 22:57:22.017782 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 22:57:22.024632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 22:57:22.024769 ==
6397 22:57:22.024850
6398 22:57:22.024912
6399 22:57:22.028102 TX Vref Scan disable
6400 22:57:22.028184 == TX Byte 0 ==
6401 22:57:22.031264 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 22:57:22.034525 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 22:57:22.038126 == TX Byte 1 ==
6404 22:57:22.041110 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 22:57:22.044359 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 22:57:22.047682 ==
6407 22:57:22.050962 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 22:57:22.054420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 22:57:22.054504 ==
6410 22:57:22.054570
6411 22:57:22.054630
6412 22:57:22.057543 TX Vref Scan disable
6413 22:57:22.057625 == TX Byte 0 ==
6414 22:57:22.061536 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 22:57:22.068050 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 22:57:22.068134 == TX Byte 1 ==
6417 22:57:22.071357 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 22:57:22.078291 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 22:57:22.078374
6420 22:57:22.078439 [DATLAT]
6421 22:57:22.078499 Freq=400, CH0 RK0
6422 22:57:22.078557
6423 22:57:22.081214 DATLAT Default: 0xf
6424 22:57:22.081295 0, 0xFFFF, sum = 0
6425 22:57:22.084073 1, 0xFFFF, sum = 0
6426 22:57:22.084157 2, 0xFFFF, sum = 0
6427 22:57:22.087479 3, 0xFFFF, sum = 0
6428 22:57:22.090893 4, 0xFFFF, sum = 0
6429 22:57:22.090976 5, 0xFFFF, sum = 0
6430 22:57:22.094532 6, 0xFFFF, sum = 0
6431 22:57:22.094614 7, 0xFFFF, sum = 0
6432 22:57:22.097753 8, 0xFFFF, sum = 0
6433 22:57:22.097840 9, 0xFFFF, sum = 0
6434 22:57:22.101349 10, 0xFFFF, sum = 0
6435 22:57:22.101432 11, 0xFFFF, sum = 0
6436 22:57:22.104619 12, 0xFFFF, sum = 0
6437 22:57:22.104703 13, 0x0, sum = 1
6438 22:57:22.107676 14, 0x0, sum = 2
6439 22:57:22.107758 15, 0x0, sum = 3
6440 22:57:22.111031 16, 0x0, sum = 4
6441 22:57:22.111114 best_step = 14
6442 22:57:22.111179
6443 22:57:22.111238 ==
6444 22:57:22.114717 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 22:57:22.117675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 22:57:22.117758 ==
6447 22:57:22.120832 RX Vref Scan: 1
6448 22:57:22.120914
6449 22:57:22.124307 RX Vref 0 -> 0, step: 1
6450 22:57:22.124389
6451 22:57:22.128009 RX Delay -311 -> 252, step: 8
6452 22:57:22.128093
6453 22:57:22.128158 Set Vref, RX VrefLevel [Byte0]: 55
6454 22:57:22.131200 [Byte1]: 55
6455 22:57:22.136425
6456 22:57:22.136507 Final RX Vref Byte 0 = 55 to rank0
6457 22:57:22.139548 Final RX Vref Byte 1 = 55 to rank0
6458 22:57:22.143372 Final RX Vref Byte 0 = 55 to rank1
6459 22:57:22.146550 Final RX Vref Byte 1 = 55 to rank1==
6460 22:57:22.149631 Dram Type= 6, Freq= 0, CH_0, rank 0
6461 22:57:22.156541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 22:57:22.156633 ==
6463 22:57:22.156703 DQS Delay:
6464 22:57:22.156769 DQS0 = 28, DQS1 = 36
6465 22:57:22.159784 DQM Delay:
6466 22:57:22.159866 DQM0 = 10, DQM1 = 13
6467 22:57:22.163065 DQ Delay:
6468 22:57:22.166276 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6469 22:57:22.166360 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6470 22:57:22.169391 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6471 22:57:22.173100 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6472 22:57:22.173188
6473 22:57:22.173254
6474 22:57:22.182944 [DQSOSCAuto] RK0, (LSB)MR18= 0xcab6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6475 22:57:22.186130 CH0 RK0: MR19=C0C, MR18=CAB6
6476 22:57:22.192862 CH0_RK0: MR19=0xC0C, MR18=0xCAB6, DQSOSC=384, MR23=63, INC=400, DEC=267
6477 22:57:22.192950 ==
6478 22:57:22.195927 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 22:57:22.199916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 22:57:22.200039 ==
6481 22:57:22.202855 [Gating] SW mode calibration
6482 22:57:22.209519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6483 22:57:22.215731 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6484 22:57:22.219612 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 22:57:22.223113 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 22:57:22.226207 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 22:57:22.232870 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 22:57:22.236244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 22:57:22.239179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 22:57:22.246201 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 22:57:22.249512 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 22:57:22.252361 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 22:57:22.255758 Total UI for P1: 0, mck2ui 16
6494 22:57:22.259689 best dqsien dly found for B0: ( 0, 14, 24)
6495 22:57:22.262672 Total UI for P1: 0, mck2ui 16
6496 22:57:22.266264 best dqsien dly found for B1: ( 0, 14, 24)
6497 22:57:22.269291 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6498 22:57:22.272994 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6499 22:57:22.276068
6500 22:57:22.279143 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 22:57:22.282654 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 22:57:22.286079 [Gating] SW calibration Done
6503 22:57:22.286163 ==
6504 22:57:22.289628 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 22:57:22.292672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 22:57:22.292756 ==
6507 22:57:22.292822 RX Vref Scan: 0
6508 22:57:22.292883
6509 22:57:22.295790 RX Vref 0 -> 0, step: 1
6510 22:57:22.295872
6511 22:57:22.299036 RX Delay -410 -> 252, step: 16
6512 22:57:22.302342 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6513 22:57:22.309349 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6514 22:57:22.312412 iDelay=230, Bit 2, Center -11 (-234 ~ 213) 448
6515 22:57:22.316382 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6516 22:57:22.319095 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6517 22:57:22.325948 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6518 22:57:22.328944 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6519 22:57:22.332800 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6520 22:57:22.335568 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6521 22:57:22.342405 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6522 22:57:22.345667 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6523 22:57:22.348901 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6524 22:57:22.352168 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6525 22:57:22.358992 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6526 22:57:22.362427 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6527 22:57:22.365545 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6528 22:57:22.365627 ==
6529 22:57:22.368730 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 22:57:22.371659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 22:57:22.375478 ==
6532 22:57:22.375589 DQS Delay:
6533 22:57:22.375657 DQS0 = 19, DQS1 = 35
6534 22:57:22.378749 DQM Delay:
6535 22:57:22.378834 DQM0 = 10, DQM1 = 16
6536 22:57:22.382037 DQ Delay:
6537 22:57:22.382118 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6538 22:57:22.385283 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6539 22:57:22.388387 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =8
6540 22:57:22.391679 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6541 22:57:22.391760
6542 22:57:22.391824
6543 22:57:22.395365 ==
6544 22:57:22.398597 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 22:57:22.401647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 22:57:22.401729 ==
6547 22:57:22.401793
6548 22:57:22.401852
6549 22:57:22.405063 TX Vref Scan disable
6550 22:57:22.405145 == TX Byte 0 ==
6551 22:57:22.408640 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6552 22:57:22.414941 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6553 22:57:22.415024 == TX Byte 1 ==
6554 22:57:22.418353 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6555 22:57:22.422044 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6556 22:57:22.425065 ==
6557 22:57:22.428477 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 22:57:22.431800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 22:57:22.431884 ==
6560 22:57:22.431949
6561 22:57:22.432046
6562 22:57:22.435124 TX Vref Scan disable
6563 22:57:22.435205 == TX Byte 0 ==
6564 22:57:22.438339 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6565 22:57:22.444789 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6566 22:57:22.444871 == TX Byte 1 ==
6567 22:57:22.448496 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6568 22:57:22.455026 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6569 22:57:22.455110
6570 22:57:22.455175 [DATLAT]
6571 22:57:22.455236 Freq=400, CH0 RK1
6572 22:57:22.455295
6573 22:57:22.457947 DATLAT Default: 0xe
6574 22:57:22.458028 0, 0xFFFF, sum = 0
6575 22:57:22.461359 1, 0xFFFF, sum = 0
6576 22:57:22.464989 2, 0xFFFF, sum = 0
6577 22:57:22.465072 3, 0xFFFF, sum = 0
6578 22:57:22.468247 4, 0xFFFF, sum = 0
6579 22:57:22.468330 5, 0xFFFF, sum = 0
6580 22:57:22.471476 6, 0xFFFF, sum = 0
6581 22:57:22.471559 7, 0xFFFF, sum = 0
6582 22:57:22.474627 8, 0xFFFF, sum = 0
6583 22:57:22.474711 9, 0xFFFF, sum = 0
6584 22:57:22.478166 10, 0xFFFF, sum = 0
6585 22:57:22.478250 11, 0xFFFF, sum = 0
6586 22:57:22.481219 12, 0xFFFF, sum = 0
6587 22:57:22.481313 13, 0x0, sum = 1
6588 22:57:22.484848 14, 0x0, sum = 2
6589 22:57:22.484950 15, 0x0, sum = 3
6590 22:57:22.487896 16, 0x0, sum = 4
6591 22:57:22.488015 best_step = 14
6592 22:57:22.488109
6593 22:57:22.488198 ==
6594 22:57:22.491029 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 22:57:22.494845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 22:57:22.497614 ==
6597 22:57:22.497695 RX Vref Scan: 0
6598 22:57:22.497760
6599 22:57:22.501236 RX Vref 0 -> 0, step: 1
6600 22:57:22.501317
6601 22:57:22.504438 RX Delay -311 -> 252, step: 8
6602 22:57:22.507649 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6603 22:57:22.514546 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6604 22:57:22.517702 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6605 22:57:22.521004 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6606 22:57:22.527411 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6607 22:57:22.530951 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6608 22:57:22.534471 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6609 22:57:22.537411 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6610 22:57:22.541005 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6611 22:57:22.547736 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6612 22:57:22.550490 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6613 22:57:22.554080 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6614 22:57:22.560474 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6615 22:57:22.564189 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6616 22:57:22.567540 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6617 22:57:22.571177 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6618 22:57:22.571259 ==
6619 22:57:22.573942 Dram Type= 6, Freq= 0, CH_0, rank 1
6620 22:57:22.580997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 22:57:22.581080 ==
6622 22:57:22.581145 DQS Delay:
6623 22:57:22.584164 DQS0 = 24, DQS1 = 32
6624 22:57:22.584246 DQM Delay:
6625 22:57:22.584311 DQM0 = 8, DQM1 = 9
6626 22:57:22.587733 DQ Delay:
6627 22:57:22.590614 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6628 22:57:22.590703 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6629 22:57:22.594601 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6630 22:57:22.597110 DQ12 =12, DQ13 =12, DQ14 =16, DQ15 =16
6631 22:57:22.597191
6632 22:57:22.597256
6633 22:57:22.607378 [DQSOSCAuto] RK1, (LSB)MR18= 0xb959, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6634 22:57:22.610853 CH0 RK1: MR19=C0C, MR18=B959
6635 22:57:22.617216 CH0_RK1: MR19=0xC0C, MR18=0xB959, DQSOSC=386, MR23=63, INC=396, DEC=264
6636 22:57:22.620962 [RxdqsGatingPostProcess] freq 400
6637 22:57:22.624230 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6638 22:57:22.627239 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 22:57:22.630596 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 22:57:22.633737 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 22:57:22.637461 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 22:57:22.640323 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 22:57:22.643950 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 22:57:22.647238 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 22:57:22.650580 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 22:57:22.653697 Pre-setting of DQS Precalculation
6647 22:57:22.657351 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6648 22:57:22.657439 ==
6649 22:57:22.660618 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 22:57:22.664133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 22:57:22.666881 ==
6652 22:57:22.670339 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6653 22:57:22.676798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6654 22:57:22.680735 [CA 0] Center 36 (8~64) winsize 57
6655 22:57:22.684106 [CA 1] Center 36 (8~64) winsize 57
6656 22:57:22.687290 [CA 2] Center 36 (8~64) winsize 57
6657 22:57:22.690503 [CA 3] Center 36 (8~64) winsize 57
6658 22:57:22.693892 [CA 4] Center 36 (8~64) winsize 57
6659 22:57:22.697177 [CA 5] Center 36 (8~64) winsize 57
6660 22:57:22.697259
6661 22:57:22.700495 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6662 22:57:22.700577
6663 22:57:22.703561 [CATrainingPosCal] consider 1 rank data
6664 22:57:22.706791 u2DelayCellTimex100 = 270/100 ps
6665 22:57:22.710528 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 22:57:22.713793 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 22:57:22.716712 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 22:57:22.720682 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 22:57:22.723699 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 22:57:22.726791 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 22:57:22.726878
6672 22:57:22.730047 CA PerBit enable=1, Macro0, CA PI delay=36
6673 22:57:22.733455
6674 22:57:22.733537 [CBTSetCACLKResult] CA Dly = 36
6675 22:57:22.737103 CS Dly: 1 (0~32)
6676 22:57:22.737185 ==
6677 22:57:22.739930 Dram Type= 6, Freq= 0, CH_1, rank 1
6678 22:57:22.743276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 22:57:22.743359 ==
6680 22:57:22.750560 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6681 22:57:22.757442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6682 22:57:22.760161 [CA 0] Center 36 (8~64) winsize 57
6683 22:57:22.763734 [CA 1] Center 36 (8~64) winsize 57
6684 22:57:22.764123 [CA 2] Center 36 (8~64) winsize 57
6685 22:57:22.767323 [CA 3] Center 36 (8~64) winsize 57
6686 22:57:22.770804 [CA 4] Center 36 (8~64) winsize 57
6687 22:57:22.773846 [CA 5] Center 36 (8~64) winsize 57
6688 22:57:22.774182
6689 22:57:22.777023 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6690 22:57:22.780375
6691 22:57:22.783385 [CATrainingPosCal] consider 2 rank data
6692 22:57:22.783712 u2DelayCellTimex100 = 270/100 ps
6693 22:57:22.790574 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 22:57:22.793476 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 22:57:22.797328 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 22:57:22.800617 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 22:57:22.803850 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 22:57:22.807051 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 22:57:22.807380
6700 22:57:22.810005 CA PerBit enable=1, Macro0, CA PI delay=36
6701 22:57:22.810365
6702 22:57:22.813327 [CBTSetCACLKResult] CA Dly = 36
6703 22:57:22.816716 CS Dly: 1 (0~32)
6704 22:57:22.816805
6705 22:57:22.820133 ----->DramcWriteLeveling(PI) begin...
6706 22:57:22.820229 ==
6707 22:57:22.823249 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 22:57:22.826740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 22:57:22.826845 ==
6710 22:57:22.830084 Write leveling (Byte 0): 40 => 8
6711 22:57:22.833191 Write leveling (Byte 1): 40 => 8
6712 22:57:22.836410 DramcWriteLeveling(PI) end<-----
6713 22:57:22.836625
6714 22:57:22.836734 ==
6715 22:57:22.840169 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 22:57:22.843369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 22:57:22.843525 ==
6718 22:57:22.846239 [Gating] SW mode calibration
6719 22:57:22.853122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6720 22:57:22.860007 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6721 22:57:22.863253 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 22:57:22.866100 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 22:57:22.872936 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 22:57:22.876094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 22:57:22.879409 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 22:57:22.886474 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 22:57:22.890050 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 22:57:22.892662 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 22:57:22.899868 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 22:57:22.899983 Total UI for P1: 0, mck2ui 16
6731 22:57:22.903281 best dqsien dly found for B0: ( 0, 14, 24)
6732 22:57:22.906625 Total UI for P1: 0, mck2ui 16
6733 22:57:22.909511 best dqsien dly found for B1: ( 0, 14, 24)
6734 22:57:22.916608 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6735 22:57:22.919517 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6736 22:57:22.919674
6737 22:57:22.922575 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 22:57:22.926119 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 22:57:22.929516 [Gating] SW calibration Done
6740 22:57:22.929656 ==
6741 22:57:22.932281 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 22:57:22.935781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 22:57:22.935930 ==
6744 22:57:22.939089 RX Vref Scan: 0
6745 22:57:22.939172
6746 22:57:22.939238 RX Vref 0 -> 0, step: 1
6747 22:57:22.939299
6748 22:57:22.942416 RX Delay -410 -> 252, step: 16
6749 22:57:22.949105 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6750 22:57:22.952604 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6751 22:57:22.956429 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6752 22:57:22.959378 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6753 22:57:22.965644 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6754 22:57:22.969530 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6755 22:57:22.972977 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6756 22:57:22.975900 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6757 22:57:22.979558 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6758 22:57:22.985872 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6759 22:57:22.989279 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6760 22:57:22.992533 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6761 22:57:22.998761 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6762 22:57:23.002425 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6763 22:57:23.005873 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6764 22:57:23.009301 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6765 22:57:23.009384 ==
6766 22:57:23.012633 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 22:57:23.019085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 22:57:23.019194 ==
6769 22:57:23.019290 DQS Delay:
6770 22:57:23.022076 DQS0 = 35, DQS1 = 35
6771 22:57:23.022165 DQM Delay:
6772 22:57:23.025650 DQM0 = 18, DQM1 = 13
6773 22:57:23.025732 DQ Delay:
6774 22:57:23.029145 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6775 22:57:23.032363 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6776 22:57:23.035580 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6777 22:57:23.038688 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6778 22:57:23.038805
6779 22:57:23.038900
6780 22:57:23.038962 ==
6781 22:57:23.042172 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 22:57:23.045638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 22:57:23.045748 ==
6784 22:57:23.045841
6785 22:57:23.045945
6786 22:57:23.048434 TX Vref Scan disable
6787 22:57:23.048516 == TX Byte 0 ==
6788 22:57:23.055003 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 22:57:23.058836 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 22:57:23.058920 == TX Byte 1 ==
6791 22:57:23.065535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 22:57:23.068220 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 22:57:23.068330 ==
6794 22:57:23.071920 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 22:57:23.075247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 22:57:23.075332 ==
6797 22:57:23.075398
6798 22:57:23.075458
6799 22:57:23.078366 TX Vref Scan disable
6800 22:57:23.078475 == TX Byte 0 ==
6801 22:57:23.085386 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 22:57:23.088621 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 22:57:23.088705 == TX Byte 1 ==
6804 22:57:23.095118 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 22:57:23.098309 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 22:57:23.098400
6807 22:57:23.098466 [DATLAT]
6808 22:57:23.101407 Freq=400, CH1 RK0
6809 22:57:23.101489
6810 22:57:23.101553 DATLAT Default: 0xf
6811 22:57:23.105116 0, 0xFFFF, sum = 0
6812 22:57:23.105200 1, 0xFFFF, sum = 0
6813 22:57:23.108446 2, 0xFFFF, sum = 0
6814 22:57:23.108529 3, 0xFFFF, sum = 0
6815 22:57:23.111398 4, 0xFFFF, sum = 0
6816 22:57:23.111481 5, 0xFFFF, sum = 0
6817 22:57:23.114868 6, 0xFFFF, sum = 0
6818 22:57:23.114951 7, 0xFFFF, sum = 0
6819 22:57:23.118202 8, 0xFFFF, sum = 0
6820 22:57:23.118285 9, 0xFFFF, sum = 0
6821 22:57:23.121604 10, 0xFFFF, sum = 0
6822 22:57:23.124974 11, 0xFFFF, sum = 0
6823 22:57:23.125058 12, 0xFFFF, sum = 0
6824 22:57:23.127889 13, 0x0, sum = 1
6825 22:57:23.128025 14, 0x0, sum = 2
6826 22:57:23.131693 15, 0x0, sum = 3
6827 22:57:23.131777 16, 0x0, sum = 4
6828 22:57:23.131843 best_step = 14
6829 22:57:23.131903
6830 22:57:23.135005 ==
6831 22:57:23.137909 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 22:57:23.141243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 22:57:23.141325 ==
6834 22:57:23.141391 RX Vref Scan: 1
6835 22:57:23.141451
6836 22:57:23.144799 RX Vref 0 -> 0, step: 1
6837 22:57:23.144880
6838 22:57:23.148474 RX Delay -311 -> 252, step: 8
6839 22:57:23.148557
6840 22:57:23.151737 Set Vref, RX VrefLevel [Byte0]: 53
6841 22:57:23.155105 [Byte1]: 53
6842 22:57:23.158073
6843 22:57:23.158155 Final RX Vref Byte 0 = 53 to rank0
6844 22:57:23.161646 Final RX Vref Byte 1 = 53 to rank0
6845 22:57:23.164933 Final RX Vref Byte 0 = 53 to rank1
6846 22:57:23.168259 Final RX Vref Byte 1 = 53 to rank1==
6847 22:57:23.171539 Dram Type= 6, Freq= 0, CH_1, rank 0
6848 22:57:23.178088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 22:57:23.178181 ==
6850 22:57:23.178292 DQS Delay:
6851 22:57:23.181356 DQS0 = 32, DQS1 = 32
6852 22:57:23.181445 DQM Delay:
6853 22:57:23.181510 DQM0 = 14, DQM1 = 10
6854 22:57:23.184564 DQ Delay:
6855 22:57:23.188137 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6856 22:57:23.191301 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =16
6857 22:57:23.191378 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6858 22:57:23.194447 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6859 22:57:23.198068
6860 22:57:23.198142
6861 22:57:23.205059 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6862 22:57:23.208092 CH1 RK0: MR19=C0C, MR18=93CC
6863 22:57:23.214689 CH1_RK0: MR19=0xC0C, MR18=0x93CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6864 22:57:23.214771 ==
6865 22:57:23.217816 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 22:57:23.221460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 22:57:23.221575 ==
6868 22:57:23.224687 [Gating] SW mode calibration
6869 22:57:23.231035 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6870 22:57:23.238489 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6871 22:57:23.241077 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6872 22:57:23.244865 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 22:57:23.250893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 22:57:23.254274 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 22:57:23.257758 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 22:57:23.264519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 22:57:23.267815 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 22:57:23.271077 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 22:57:23.278045 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 22:57:23.278217 Total UI for P1: 0, mck2ui 16
6881 22:57:23.281288 best dqsien dly found for B0: ( 0, 14, 24)
6882 22:57:23.284320 Total UI for P1: 0, mck2ui 16
6883 22:57:23.287989 best dqsien dly found for B1: ( 0, 14, 24)
6884 22:57:23.294165 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6885 22:57:23.297342 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6886 22:57:23.297478
6887 22:57:23.300901 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 22:57:23.304564 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 22:57:23.307951 [Gating] SW calibration Done
6890 22:57:23.308187 ==
6891 22:57:23.310645 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 22:57:23.314269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 22:57:23.314571 ==
6894 22:57:23.317450 RX Vref Scan: 0
6895 22:57:23.317690
6896 22:57:23.317879 RX Vref 0 -> 0, step: 1
6897 22:57:23.318099
6898 22:57:23.320748 RX Delay -410 -> 252, step: 16
6899 22:57:23.324253 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6900 22:57:23.330941 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6901 22:57:23.334351 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6902 22:57:23.338257 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6903 22:57:23.341370 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6904 22:57:23.347880 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6905 22:57:23.351449 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6906 22:57:23.355102 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6907 22:57:23.357988 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6908 22:57:23.364678 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6909 22:57:23.368055 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6910 22:57:23.371540 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6911 22:57:23.374826 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6912 22:57:23.380928 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6913 22:57:23.384615 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6914 22:57:23.388028 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6915 22:57:23.388432 ==
6916 22:57:23.391341 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 22:57:23.397998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 22:57:23.398510 ==
6919 22:57:23.398932 DQS Delay:
6920 22:57:23.400897 DQS0 = 27, DQS1 = 35
6921 22:57:23.401295 DQM Delay:
6922 22:57:23.401698 DQM0 = 11, DQM1 = 15
6923 22:57:23.404599 DQ Delay:
6924 22:57:23.407501 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6925 22:57:23.407905 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6926 22:57:23.411110 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6927 22:57:23.414534 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6928 22:57:23.415051
6929 22:57:23.415474
6930 22:57:23.417495 ==
6931 22:57:23.421025 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 22:57:23.424068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 22:57:23.424586 ==
6934 22:57:23.425007
6935 22:57:23.425460
6936 22:57:23.427460 TX Vref Scan disable
6937 22:57:23.427858 == TX Byte 0 ==
6938 22:57:23.430992 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6939 22:57:23.437547 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6940 22:57:23.437940 == TX Byte 1 ==
6941 22:57:23.440810 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6942 22:57:23.447373 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6943 22:57:23.447951 ==
6944 22:57:23.450647 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 22:57:23.453738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 22:57:23.454142 ==
6947 22:57:23.454544
6948 22:57:23.454924
6949 22:57:23.457259 TX Vref Scan disable
6950 22:57:23.457693 == TX Byte 0 ==
6951 22:57:23.460545 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6952 22:57:23.466957 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6953 22:57:23.467359 == TX Byte 1 ==
6954 22:57:23.470475 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6955 22:57:23.477281 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6956 22:57:23.477783
6957 22:57:23.478197 [DATLAT]
6958 22:57:23.478580 Freq=400, CH1 RK1
6959 22:57:23.478952
6960 22:57:23.480438 DATLAT Default: 0xe
6961 22:57:23.483953 0, 0xFFFF, sum = 0
6962 22:57:23.484515 1, 0xFFFF, sum = 0
6963 22:57:23.486922 2, 0xFFFF, sum = 0
6964 22:57:23.487327 3, 0xFFFF, sum = 0
6965 22:57:23.490367 4, 0xFFFF, sum = 0
6966 22:57:23.490887 5, 0xFFFF, sum = 0
6967 22:57:23.494234 6, 0xFFFF, sum = 0
6968 22:57:23.494742 7, 0xFFFF, sum = 0
6969 22:57:23.497077 8, 0xFFFF, sum = 0
6970 22:57:23.497475 9, 0xFFFF, sum = 0
6971 22:57:23.500800 10, 0xFFFF, sum = 0
6972 22:57:23.501321 11, 0xFFFF, sum = 0
6973 22:57:23.503863 12, 0xFFFF, sum = 0
6974 22:57:23.504334 13, 0x0, sum = 1
6975 22:57:23.507023 14, 0x0, sum = 2
6976 22:57:23.507428 15, 0x0, sum = 3
6977 22:57:23.510551 16, 0x0, sum = 4
6978 22:57:23.511064 best_step = 14
6979 22:57:23.511482
6980 22:57:23.511859 ==
6981 22:57:23.513461 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 22:57:23.520190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 22:57:23.520596 ==
6984 22:57:23.520997 RX Vref Scan: 0
6985 22:57:23.521376
6986 22:57:23.523387 RX Vref 0 -> 0, step: 1
6987 22:57:23.523780
6988 22:57:23.526489 RX Delay -311 -> 252, step: 8
6989 22:57:23.533191 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6990 22:57:23.536854 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6991 22:57:23.540515 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6992 22:57:23.543555 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6993 22:57:23.550014 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6994 22:57:23.553631 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6995 22:57:23.557165 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6996 22:57:23.560211 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6997 22:57:23.563265 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6998 22:57:23.569734 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6999 22:57:23.572988 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7000 22:57:23.576063 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7001 22:57:23.583616 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7002 22:57:23.586258 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7003 22:57:23.589580 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7004 22:57:23.593355 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7005 22:57:23.596507 ==
7006 22:57:23.596901 Dram Type= 6, Freq= 0, CH_1, rank 1
7007 22:57:23.603437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7008 22:57:23.603933 ==
7009 22:57:23.604299 DQS Delay:
7010 22:57:23.606050 DQS0 = 28, DQS1 = 32
7011 22:57:23.606537 DQM Delay:
7012 22:57:23.609414 DQM0 = 10, DQM1 = 11
7013 22:57:23.609903 DQ Delay:
7014 22:57:23.613315 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7015 22:57:23.616363 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7016 22:57:23.619832 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7017 22:57:23.622792 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7018 22:57:23.623224
7019 22:57:23.623562
7020 22:57:23.629514 [DQSOSCAuto] RK1, (LSB)MR18= 0xc051, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
7021 22:57:23.632491 CH1 RK1: MR19=C0C, MR18=C051
7022 22:57:23.639548 CH1_RK1: MR19=0xC0C, MR18=0xC051, DQSOSC=386, MR23=63, INC=396, DEC=264
7023 22:57:23.642375 [RxdqsGatingPostProcess] freq 400
7024 22:57:23.645978 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7025 22:57:23.649557 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 22:57:23.652779 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 22:57:23.656403 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 22:57:23.659805 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 22:57:23.662373 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 22:57:23.665876 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 22:57:23.669262 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 22:57:23.672444 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 22:57:23.675819 Pre-setting of DQS Precalculation
7034 22:57:23.678946 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7035 22:57:23.688984 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7036 22:57:23.695883 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7037 22:57:23.696532
7038 22:57:23.697026
7039 22:57:23.698885 [Calibration Summary] 800 Mbps
7040 22:57:23.699292 CH 0, Rank 0
7041 22:57:23.702282 SW Impedance : PASS
7042 22:57:23.702880 DUTY Scan : NO K
7043 22:57:23.705698 ZQ Calibration : PASS
7044 22:57:23.709057 Jitter Meter : NO K
7045 22:57:23.709444 CBT Training : PASS
7046 22:57:23.712402 Write leveling : PASS
7047 22:57:23.715499 RX DQS gating : PASS
7048 22:57:23.716067 RX DQ/DQS(RDDQC) : PASS
7049 22:57:23.718531 TX DQ/DQS : PASS
7050 22:57:23.722453 RX DATLAT : PASS
7051 22:57:23.722962 RX DQ/DQS(Engine): PASS
7052 22:57:23.725454 TX OE : NO K
7053 22:57:23.725866 All Pass.
7054 22:57:23.726180
7055 22:57:23.728776 CH 0, Rank 1
7056 22:57:23.729263 SW Impedance : PASS
7057 22:57:23.731911 DUTY Scan : NO K
7058 22:57:23.732329 ZQ Calibration : PASS
7059 22:57:23.735772 Jitter Meter : NO K
7060 22:57:23.739020 CBT Training : PASS
7061 22:57:23.739514 Write leveling : NO K
7062 22:57:23.742457 RX DQS gating : PASS
7063 22:57:23.745970 RX DQ/DQS(RDDQC) : PASS
7064 22:57:23.746465 TX DQ/DQS : PASS
7065 22:57:23.749244 RX DATLAT : PASS
7066 22:57:23.752213 RX DQ/DQS(Engine): PASS
7067 22:57:23.752598 TX OE : NO K
7068 22:57:23.755946 All Pass.
7069 22:57:23.756490
7070 22:57:23.756805 CH 1, Rank 0
7071 22:57:23.758917 SW Impedance : PASS
7072 22:57:23.759459 DUTY Scan : NO K
7073 22:57:23.761880 ZQ Calibration : PASS
7074 22:57:23.765769 Jitter Meter : NO K
7075 22:57:23.766156 CBT Training : PASS
7076 22:57:23.768802 Write leveling : PASS
7077 22:57:23.772487 RX DQS gating : PASS
7078 22:57:23.773107 RX DQ/DQS(RDDQC) : PASS
7079 22:57:23.775696 TX DQ/DQS : PASS
7080 22:57:23.776248 RX DATLAT : PASS
7081 22:57:23.778750 RX DQ/DQS(Engine): PASS
7082 22:57:23.782036 TX OE : NO K
7083 22:57:23.782443 All Pass.
7084 22:57:23.782753
7085 22:57:23.783041 CH 1, Rank 1
7086 22:57:23.785290 SW Impedance : PASS
7087 22:57:23.788566 DUTY Scan : NO K
7088 22:57:23.788955 ZQ Calibration : PASS
7089 22:57:23.792254 Jitter Meter : NO K
7090 22:57:23.795513 CBT Training : PASS
7091 22:57:23.796031 Write leveling : NO K
7092 22:57:23.798836 RX DQS gating : PASS
7093 22:57:23.801922 RX DQ/DQS(RDDQC) : PASS
7094 22:57:23.802573 TX DQ/DQS : PASS
7095 22:57:23.805822 RX DATLAT : PASS
7096 22:57:23.808977 RX DQ/DQS(Engine): PASS
7097 22:57:23.809366 TX OE : NO K
7098 22:57:23.809676 All Pass.
7099 22:57:23.812094
7100 22:57:23.812582 DramC Write-DBI off
7101 22:57:23.815901 PER_BANK_REFRESH: Hybrid Mode
7102 22:57:23.816460 TX_TRACKING: ON
7103 22:57:23.825469 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7104 22:57:23.829110 [FAST_K] Save calibration result to emmc
7105 22:57:23.832431 dramc_set_vcore_voltage set vcore to 725000
7106 22:57:23.835340 Read voltage for 1600, 0
7107 22:57:23.835725 Vio18 = 0
7108 22:57:23.839120 Vcore = 725000
7109 22:57:23.839648 Vdram = 0
7110 22:57:23.840037 Vddq = 0
7111 22:57:23.840440 Vmddr = 0
7112 22:57:23.845797 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7113 22:57:23.852248 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7114 22:57:23.852640 MEM_TYPE=3, freq_sel=13
7115 22:57:23.855540 sv_algorithm_assistance_LP4_3733
7116 22:57:23.858999 ============ PULL DRAM RESETB DOWN ============
7117 22:57:23.865503 ========== PULL DRAM RESETB DOWN end =========
7118 22:57:23.868780 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7119 22:57:23.872464 ===================================
7120 22:57:23.875243 LPDDR4 DRAM CONFIGURATION
7121 22:57:23.878497 ===================================
7122 22:57:23.878887 EX_ROW_EN[0] = 0x0
7123 22:57:23.881924 EX_ROW_EN[1] = 0x0
7124 22:57:23.882310 LP4Y_EN = 0x0
7125 22:57:23.884834 WORK_FSP = 0x1
7126 22:57:23.888511 WL = 0x5
7127 22:57:23.889108 RL = 0x5
7128 22:57:23.892093 BL = 0x2
7129 22:57:23.892480 RPST = 0x0
7130 22:57:23.895353 RD_PRE = 0x0
7131 22:57:23.895738 WR_PRE = 0x1
7132 22:57:23.898959 WR_PST = 0x1
7133 22:57:23.899453 DBI_WR = 0x0
7134 22:57:23.901986 DBI_RD = 0x0
7135 22:57:23.902376 OTF = 0x1
7136 22:57:23.905323 ===================================
7137 22:57:23.908866 ===================================
7138 22:57:23.909363 ANA top config
7139 22:57:23.912101 ===================================
7140 22:57:23.915293 DLL_ASYNC_EN = 0
7141 22:57:23.918423 ALL_SLAVE_EN = 0
7142 22:57:23.922132 NEW_RANK_MODE = 1
7143 22:57:23.925293 DLL_IDLE_MODE = 1
7144 22:57:23.925714 LP45_APHY_COMB_EN = 1
7145 22:57:23.928599 TX_ODT_DIS = 0
7146 22:57:23.931844 NEW_8X_MODE = 1
7147 22:57:23.935188 ===================================
7148 22:57:23.938354 ===================================
7149 22:57:23.941425 data_rate = 3200
7150 22:57:23.945471 CKR = 1
7151 22:57:23.948449 DQ_P2S_RATIO = 8
7152 22:57:23.951448 ===================================
7153 22:57:23.952166 CA_P2S_RATIO = 8
7154 22:57:23.955098 DQ_CA_OPEN = 0
7155 22:57:23.958535 DQ_SEMI_OPEN = 0
7156 22:57:23.961480 CA_SEMI_OPEN = 0
7157 22:57:23.964902 CA_FULL_RATE = 0
7158 22:57:23.965326 DQ_CKDIV4_EN = 0
7159 22:57:23.968661 CA_CKDIV4_EN = 0
7160 22:57:23.971420 CA_PREDIV_EN = 0
7161 22:57:23.975164 PH8_DLY = 12
7162 22:57:23.977864 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7163 22:57:23.981846 DQ_AAMCK_DIV = 4
7164 22:57:23.985004 CA_AAMCK_DIV = 4
7165 22:57:23.985427 CA_ADMCK_DIV = 4
7166 22:57:23.988373 DQ_TRACK_CA_EN = 0
7167 22:57:23.991733 CA_PICK = 1600
7168 22:57:23.994901 CA_MCKIO = 1600
7169 22:57:23.998391 MCKIO_SEMI = 0
7170 22:57:24.001879 PLL_FREQ = 3068
7171 22:57:24.005222 DQ_UI_PI_RATIO = 32
7172 22:57:24.005779 CA_UI_PI_RATIO = 0
7173 22:57:24.008050 ===================================
7174 22:57:24.012061 ===================================
7175 22:57:24.015381 memory_type:LPDDR4
7176 22:57:24.018370 GP_NUM : 10
7177 22:57:24.018798 SRAM_EN : 1
7178 22:57:24.021496 MD32_EN : 0
7179 22:57:24.024673 ===================================
7180 22:57:24.027771 [ANA_INIT] >>>>>>>>>>>>>>
7181 22:57:24.030967 <<<<<< [CONFIGURE PHASE]: ANA_TX
7182 22:57:24.034505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7183 22:57:24.038199 ===================================
7184 22:57:24.038637 data_rate = 3200,PCW = 0X7600
7185 22:57:24.041486 ===================================
7186 22:57:24.044631 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7187 22:57:24.051481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 22:57:24.057999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 22:57:24.061267 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7190 22:57:24.064247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7191 22:57:24.067943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7192 22:57:24.071191 [ANA_INIT] flow start
7193 22:57:24.074367 [ANA_INIT] PLL >>>>>>>>
7194 22:57:24.074795 [ANA_INIT] PLL <<<<<<<<
7195 22:57:24.077523 [ANA_INIT] MIDPI >>>>>>>>
7196 22:57:24.080646 [ANA_INIT] MIDPI <<<<<<<<
7197 22:57:24.081090 [ANA_INIT] DLL >>>>>>>>
7198 22:57:24.083725 [ANA_INIT] DLL <<<<<<<<
7199 22:57:24.087292 [ANA_INIT] flow end
7200 22:57:24.090709 ============ LP4 DIFF to SE enter ============
7201 22:57:24.094273 ============ LP4 DIFF to SE exit ============
7202 22:57:24.097573 [ANA_INIT] <<<<<<<<<<<<<
7203 22:57:24.100501 [Flow] Enable top DCM control >>>>>
7204 22:57:24.104124 [Flow] Enable top DCM control <<<<<
7205 22:57:24.107614 Enable DLL master slave shuffle
7206 22:57:24.111164 ==============================================================
7207 22:57:24.114284 Gating Mode config
7208 22:57:24.120934 ==============================================================
7209 22:57:24.121656 Config description:
7210 22:57:24.131356 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7211 22:57:24.137478 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7212 22:57:24.140616 SELPH_MODE 0: By rank 1: By Phase
7213 22:57:24.147081 ==============================================================
7214 22:57:24.150466 GAT_TRACK_EN = 1
7215 22:57:24.153621 RX_GATING_MODE = 2
7216 22:57:24.157144 RX_GATING_TRACK_MODE = 2
7217 22:57:24.160621 SELPH_MODE = 1
7218 22:57:24.164056 PICG_EARLY_EN = 1
7219 22:57:24.166904 VALID_LAT_VALUE = 1
7220 22:57:24.170109 ==============================================================
7221 22:57:24.173775 Enter into Gating configuration >>>>
7222 22:57:24.176940 Exit from Gating configuration <<<<
7223 22:57:24.180060 Enter into DVFS_PRE_config >>>>>
7224 22:57:24.194448 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7225 22:57:24.195000 Exit from DVFS_PRE_config <<<<<
7226 22:57:24.196669 Enter into PICG configuration >>>>
7227 22:57:24.200714 Exit from PICG configuration <<<<
7228 22:57:24.203529 [RX_INPUT] configuration >>>>>
7229 22:57:24.207128 [RX_INPUT] configuration <<<<<
7230 22:57:24.213234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7231 22:57:24.216633 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7232 22:57:24.223278 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7233 22:57:24.230645 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7234 22:57:24.236946 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7235 22:57:24.243543 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7236 22:57:24.246822 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7237 22:57:24.249997 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7238 22:57:24.253103 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7239 22:57:24.260153 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7240 22:57:24.264036 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7241 22:57:24.266929 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7242 22:57:24.269947 ===================================
7243 22:57:24.273540 LPDDR4 DRAM CONFIGURATION
7244 22:57:24.276444 ===================================
7245 22:57:24.276873 EX_ROW_EN[0] = 0x0
7246 22:57:24.280044 EX_ROW_EN[1] = 0x0
7247 22:57:24.283007 LP4Y_EN = 0x0
7248 22:57:24.283431 WORK_FSP = 0x1
7249 22:57:24.286522 WL = 0x5
7250 22:57:24.286942 RL = 0x5
7251 22:57:24.290053 BL = 0x2
7252 22:57:24.290582 RPST = 0x0
7253 22:57:24.293100 RD_PRE = 0x0
7254 22:57:24.293524 WR_PRE = 0x1
7255 22:57:24.296590 WR_PST = 0x1
7256 22:57:24.297015 DBI_WR = 0x0
7257 22:57:24.300244 DBI_RD = 0x0
7258 22:57:24.300774 OTF = 0x1
7259 22:57:24.303503 ===================================
7260 22:57:24.306675 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7261 22:57:24.313437 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7262 22:57:24.316380 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7263 22:57:24.320024 ===================================
7264 22:57:24.322613 LPDDR4 DRAM CONFIGURATION
7265 22:57:24.326669 ===================================
7266 22:57:24.327234 EX_ROW_EN[0] = 0x10
7267 22:57:24.329900 EX_ROW_EN[1] = 0x0
7268 22:57:24.333164 LP4Y_EN = 0x0
7269 22:57:24.333629 WORK_FSP = 0x1
7270 22:57:24.336129 WL = 0x5
7271 22:57:24.336553 RL = 0x5
7272 22:57:24.339200 BL = 0x2
7273 22:57:24.339634 RPST = 0x0
7274 22:57:24.342589 RD_PRE = 0x0
7275 22:57:24.343015 WR_PRE = 0x1
7276 22:57:24.346047 WR_PST = 0x1
7277 22:57:24.346469 DBI_WR = 0x0
7278 22:57:24.349094 DBI_RD = 0x0
7279 22:57:24.349514 OTF = 0x1
7280 22:57:24.352220 ===================================
7281 22:57:24.359618 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7282 22:57:24.360195 ==
7283 22:57:24.362402 Dram Type= 6, Freq= 0, CH_0, rank 0
7284 22:57:24.365459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 22:57:24.369541 ==
7286 22:57:24.370068 [Duty_Offset_Calibration]
7287 22:57:24.372495 B0:2 B1:1 CA:1
7288 22:57:24.372920
7289 22:57:24.375569 [DutyScan_Calibration_Flow] k_type=0
7290 22:57:24.384402
7291 22:57:24.384915 ==CLK 0==
7292 22:57:24.387840 Final CLK duty delay cell = 0
7293 22:57:24.391622 [0] MAX Duty = 5187%(X100), DQS PI = 22
7294 22:57:24.394513 [0] MIN Duty = 4876%(X100), DQS PI = 48
7295 22:57:24.398119 [0] AVG Duty = 5031%(X100)
7296 22:57:24.398641
7297 22:57:24.401531 CH0 CLK Duty spec in!! Max-Min= 311%
7298 22:57:24.405035 [DutyScan_Calibration_Flow] ====Done====
7299 22:57:24.405557
7300 22:57:24.407751 [DutyScan_Calibration_Flow] k_type=1
7301 22:57:24.424126
7302 22:57:24.424655 ==DQS 0 ==
7303 22:57:24.427169 Final DQS duty delay cell = -4
7304 22:57:24.431101 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7305 22:57:24.433652 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7306 22:57:24.437010 [-4] AVG Duty = 4891%(X100)
7307 22:57:24.437533
7308 22:57:24.437868 ==DQS 1 ==
7309 22:57:24.440462 Final DQS duty delay cell = 0
7310 22:57:24.444131 [0] MAX Duty = 5187%(X100), DQS PI = 20
7311 22:57:24.446668 [0] MIN Duty = 5031%(X100), DQS PI = 52
7312 22:57:24.450704 [0] AVG Duty = 5109%(X100)
7313 22:57:24.451158
7314 22:57:24.454130 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7315 22:57:24.454718
7316 22:57:24.457056 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7317 22:57:24.460186 [DutyScan_Calibration_Flow] ====Done====
7318 22:57:24.460730
7319 22:57:24.463885 [DutyScan_Calibration_Flow] k_type=3
7320 22:57:24.480843
7321 22:57:24.481310 ==DQM 0 ==
7322 22:57:24.483711 Final DQM duty delay cell = 0
7323 22:57:24.486823 [0] MAX Duty = 5187%(X100), DQS PI = 26
7324 22:57:24.490170 [0] MIN Duty = 4875%(X100), DQS PI = 60
7325 22:57:24.493421 [0] AVG Duty = 5031%(X100)
7326 22:57:24.493860
7327 22:57:24.494302 ==DQM 1 ==
7328 22:57:24.497156 Final DQM duty delay cell = -4
7329 22:57:24.500543 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7330 22:57:24.503723 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7331 22:57:24.506696 [-4] AVG Duty = 4922%(X100)
7332 22:57:24.507119
7333 22:57:24.510589 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7334 22:57:24.511013
7335 22:57:24.513669 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7336 22:57:24.517157 [DutyScan_Calibration_Flow] ====Done====
7337 22:57:24.517738
7338 22:57:24.520184 [DutyScan_Calibration_Flow] k_type=2
7339 22:57:24.538016
7340 22:57:24.538454 ==DQ 0 ==
7341 22:57:24.541494 Final DQ duty delay cell = 0
7342 22:57:24.544946 [0] MAX Duty = 5062%(X100), DQS PI = 26
7343 22:57:24.548091 [0] MIN Duty = 4907%(X100), DQS PI = 0
7344 22:57:24.548522 [0] AVG Duty = 4984%(X100)
7345 22:57:24.548892
7346 22:57:24.551401 ==DQ 1 ==
7347 22:57:24.554853 Final DQ duty delay cell = 0
7348 22:57:24.558221 [0] MAX Duty = 5156%(X100), DQS PI = 22
7349 22:57:24.561424 [0] MIN Duty = 4907%(X100), DQS PI = 34
7350 22:57:24.561868 [0] AVG Duty = 5031%(X100)
7351 22:57:24.562223
7352 22:57:24.564622 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7353 22:57:24.567866
7354 22:57:24.571624 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7355 22:57:24.574245 [DutyScan_Calibration_Flow] ====Done====
7356 22:57:24.574802 ==
7357 22:57:24.577708 Dram Type= 6, Freq= 0, CH_1, rank 0
7358 22:57:24.581288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7359 22:57:24.581712 ==
7360 22:57:24.584296 [Duty_Offset_Calibration]
7361 22:57:24.584714 B0:1 B1:0 CA:0
7362 22:57:24.585044
7363 22:57:24.587832 [DutyScan_Calibration_Flow] k_type=0
7364 22:57:24.597410
7365 22:57:24.597841 ==CLK 0==
7366 22:57:24.600746 Final CLK duty delay cell = -4
7367 22:57:24.603939 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7368 22:57:24.607349 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7369 22:57:24.610454 [-4] AVG Duty = 4922%(X100)
7370 22:57:24.610680
7371 22:57:24.614206 CH1 CLK Duty spec in!! Max-Min= 156%
7372 22:57:24.616843 [DutyScan_Calibration_Flow] ====Done====
7373 22:57:24.617152
7374 22:57:24.620616 [DutyScan_Calibration_Flow] k_type=1
7375 22:57:24.637455
7376 22:57:24.637709 ==DQS 0 ==
7377 22:57:24.640643 Final DQS duty delay cell = 0
7378 22:57:24.644234 [0] MAX Duty = 5094%(X100), DQS PI = 22
7379 22:57:24.647892 [0] MIN Duty = 4844%(X100), DQS PI = 48
7380 22:57:24.651088 [0] AVG Duty = 4969%(X100)
7381 22:57:24.651443
7382 22:57:24.651725 ==DQS 1 ==
7383 22:57:24.654496 Final DQS duty delay cell = 0
7384 22:57:24.657275 [0] MAX Duty = 5249%(X100), DQS PI = 16
7385 22:57:24.661223 [0] MIN Duty = 4969%(X100), DQS PI = 8
7386 22:57:24.661689 [0] AVG Duty = 5109%(X100)
7387 22:57:24.663828
7388 22:57:24.667734 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7389 22:57:24.668189
7390 22:57:24.670868 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7391 22:57:24.674306 [DutyScan_Calibration_Flow] ====Done====
7392 22:57:24.674830
7393 22:57:24.677081 [DutyScan_Calibration_Flow] k_type=3
7394 22:57:24.694788
7395 22:57:24.695307 ==DQM 0 ==
7396 22:57:24.697695 Final DQM duty delay cell = 0
7397 22:57:24.701002 [0] MAX Duty = 5218%(X100), DQS PI = 18
7398 22:57:24.704610 [0] MIN Duty = 4969%(X100), DQS PI = 48
7399 22:57:24.707375 [0] AVG Duty = 5093%(X100)
7400 22:57:24.707841
7401 22:57:24.708246 ==DQM 1 ==
7402 22:57:24.710888 Final DQM duty delay cell = 0
7403 22:57:24.713999 [0] MAX Duty = 5093%(X100), DQS PI = 16
7404 22:57:24.717326 [0] MIN Duty = 4907%(X100), DQS PI = 50
7405 22:57:24.720977 [0] AVG Duty = 5000%(X100)
7406 22:57:24.721534
7407 22:57:24.724238 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7408 22:57:24.724661
7409 22:57:24.727228 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7410 22:57:24.730897 [DutyScan_Calibration_Flow] ====Done====
7411 22:57:24.731316
7412 22:57:24.733946 [DutyScan_Calibration_Flow] k_type=2
7413 22:57:24.750675
7414 22:57:24.751195 ==DQ 0 ==
7415 22:57:24.753869 Final DQ duty delay cell = -4
7416 22:57:24.756958 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7417 22:57:24.760281 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7418 22:57:24.763743 [-4] AVG Duty = 4968%(X100)
7419 22:57:24.764380
7420 22:57:24.764721 ==DQ 1 ==
7421 22:57:24.767032 Final DQ duty delay cell = 0
7422 22:57:24.770344 [0] MAX Duty = 5124%(X100), DQS PI = 16
7423 22:57:24.773599 [0] MIN Duty = 4938%(X100), DQS PI = 8
7424 22:57:24.777693 [0] AVG Duty = 5031%(X100)
7425 22:57:24.778219
7426 22:57:24.780469 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7427 22:57:24.780891
7428 22:57:24.783633 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7429 22:57:24.786698 [DutyScan_Calibration_Flow] ====Done====
7430 22:57:24.790008 nWR fixed to 30
7431 22:57:24.793628 [ModeRegInit_LP4] CH0 RK0
7432 22:57:24.794151 [ModeRegInit_LP4] CH0 RK1
7433 22:57:24.796855 [ModeRegInit_LP4] CH1 RK0
7434 22:57:24.800539 [ModeRegInit_LP4] CH1 RK1
7435 22:57:24.801062 match AC timing 5
7436 22:57:24.806795 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7437 22:57:24.810417 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7438 22:57:24.813487 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7439 22:57:24.820199 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7440 22:57:24.823367 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7441 22:57:24.823786 [MiockJmeterHQA]
7442 22:57:24.824196
7443 22:57:24.826923 [DramcMiockJmeter] u1RxGatingPI = 0
7444 22:57:24.829999 0 : 4255, 4029
7445 22:57:24.830448 4 : 4252, 4027
7446 22:57:24.833258 8 : 4363, 4137
7447 22:57:24.833679 12 : 4252, 4027
7448 22:57:24.836588 16 : 4253, 4026
7449 22:57:24.837139 20 : 4363, 4138
7450 22:57:24.837723 24 : 4363, 4138
7451 22:57:24.839710 28 : 4252, 4027
7452 22:57:24.840241 32 : 4255, 4029
7453 22:57:24.843096 36 : 4252, 4027
7454 22:57:24.843703 40 : 4360, 4137
7455 22:57:24.846209 44 : 4253, 4027
7456 22:57:24.846673 48 : 4361, 4138
7457 22:57:24.849377 52 : 4250, 4026
7458 22:57:24.849806 56 : 4250, 4027
7459 22:57:24.850148 60 : 4250, 4027
7460 22:57:24.852745 64 : 4255, 4032
7461 22:57:24.853175 68 : 4361, 4138
7462 22:57:24.856021 72 : 4249, 4027
7463 22:57:24.856451 76 : 4361, 4137
7464 22:57:24.859396 80 : 4250, 4027
7465 22:57:24.859824 84 : 4250, 4026
7466 22:57:24.862459 88 : 4250, 77
7467 22:57:24.862886 92 : 4253, 0
7468 22:57:24.863224 96 : 4250, 0
7469 22:57:24.866455 100 : 4250, 0
7470 22:57:24.866882 104 : 4361, 0
7471 22:57:24.867223 108 : 4250, 0
7472 22:57:24.869703 112 : 4250, 0
7473 22:57:24.870238 116 : 4361, 0
7474 22:57:24.872560 120 : 4361, 0
7475 22:57:24.872989 124 : 4250, 0
7476 22:57:24.873349 128 : 4250, 0
7477 22:57:24.876038 132 : 4250, 0
7478 22:57:24.876488 136 : 4250, 0
7479 22:57:24.879048 140 : 4251, 0
7480 22:57:24.879476 144 : 4250, 0
7481 22:57:24.879823 148 : 4250, 0
7482 22:57:24.882697 152 : 4360, 0
7483 22:57:24.883129 156 : 4250, 0
7484 22:57:24.883521 160 : 4250, 0
7485 22:57:24.885798 164 : 4250, 0
7486 22:57:24.886266 168 : 4360, 0
7487 22:57:24.889497 172 : 4361, 0
7488 22:57:24.889931 176 : 4250, 0
7489 22:57:24.890275 180 : 4250, 0
7490 22:57:24.893025 184 : 4250, 0
7491 22:57:24.893562 188 : 4250, 0
7492 22:57:24.896418 192 : 4250, 0
7493 22:57:24.896855 196 : 4250, 0
7494 22:57:24.897203 200 : 4252, 0
7495 22:57:24.900037 204 : 4361, 1244
7496 22:57:24.900573 208 : 4250, 3986
7497 22:57:24.903404 212 : 4363, 4140
7498 22:57:24.903943 216 : 4250, 4026
7499 22:57:24.906536 220 : 4250, 4027
7500 22:57:24.907156 224 : 4250, 4027
7501 22:57:24.909988 228 : 4250, 4027
7502 22:57:24.910532 232 : 4250, 4027
7503 22:57:24.912460 236 : 4250, 4027
7504 22:57:24.912893 240 : 4250, 4027
7505 22:57:24.913242 244 : 4250, 4027
7506 22:57:24.915632 248 : 4250, 4027
7507 22:57:24.916099 252 : 4361, 4138
7508 22:57:24.919558 256 : 4361, 4137
7509 22:57:24.920019 260 : 4248, 4024
7510 22:57:24.922618 264 : 4361, 4137
7511 22:57:24.923054 268 : 4361, 4138
7512 22:57:24.926020 272 : 4249, 4027
7513 22:57:24.926453 276 : 4250, 4026
7514 22:57:24.929162 280 : 4250, 4027
7515 22:57:24.929598 284 : 4250, 4027
7516 22:57:24.932452 288 : 4250, 4027
7517 22:57:24.932886 292 : 4253, 4026
7518 22:57:24.935699 296 : 4250, 4027
7519 22:57:24.936179 300 : 4250, 4027
7520 22:57:24.936530 304 : 4361, 4138
7521 22:57:24.939084 308 : 4361, 4096
7522 22:57:24.939607 312 : 4250, 1983
7523 22:57:24.940179
7524 22:57:24.942640 MIOCK jitter meter ch=0
7525 22:57:24.943073
7526 22:57:24.945662 1T = (312-88) = 224 dly cells
7527 22:57:24.952929 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7528 22:57:24.953453 ==
7529 22:57:24.956159 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 22:57:24.959471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 22:57:24.959901 ==
7532 22:57:24.966130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7533 22:57:24.968753 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7534 22:57:24.972037 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7535 22:57:24.978773 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7536 22:57:24.988399 [CA 0] Center 43 (13~74) winsize 62
7537 22:57:24.991515 [CA 1] Center 43 (13~74) winsize 62
7538 22:57:24.994536 [CA 2] Center 38 (9~68) winsize 60
7539 22:57:24.997923 [CA 3] Center 38 (8~68) winsize 61
7540 22:57:25.001497 [CA 4] Center 36 (7~66) winsize 60
7541 22:57:25.004974 [CA 5] Center 36 (7~65) winsize 59
7542 22:57:25.005523
7543 22:57:25.007949 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7544 22:57:25.008593
7545 22:57:25.011664 [CATrainingPosCal] consider 1 rank data
7546 22:57:25.014447 u2DelayCellTimex100 = 290/100 ps
7547 22:57:25.018285 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7548 22:57:25.024997 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7549 22:57:25.028086 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7550 22:57:25.031421 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7551 22:57:25.034489 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7552 22:57:25.037659 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7553 22:57:25.038087
7554 22:57:25.040893 CA PerBit enable=1, Macro0, CA PI delay=36
7555 22:57:25.041322
7556 22:57:25.044734 [CBTSetCACLKResult] CA Dly = 36
7557 22:57:25.047674 CS Dly: 9 (0~40)
7558 22:57:25.051070 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7559 22:57:25.054408 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7560 22:57:25.054945 ==
7561 22:57:25.057446 Dram Type= 6, Freq= 0, CH_0, rank 1
7562 22:57:25.061276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 22:57:25.064514 ==
7564 22:57:25.067685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7565 22:57:25.070878 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7566 22:57:25.077722 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7567 22:57:25.081402 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7568 22:57:25.091515 [CA 0] Center 42 (12~73) winsize 62
7569 22:57:25.094577 [CA 1] Center 42 (12~73) winsize 62
7570 22:57:25.098202 [CA 2] Center 38 (8~68) winsize 61
7571 22:57:25.101494 [CA 3] Center 38 (8~68) winsize 61
7572 22:57:25.104614 [CA 4] Center 36 (6~66) winsize 61
7573 22:57:25.107623 [CA 5] Center 35 (5~65) winsize 61
7574 22:57:25.108101
7575 22:57:25.111114 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7576 22:57:25.111540
7577 22:57:25.114289 [CATrainingPosCal] consider 2 rank data
7578 22:57:25.117954 u2DelayCellTimex100 = 290/100 ps
7579 22:57:25.121805 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7580 22:57:25.128261 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7581 22:57:25.131452 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7582 22:57:25.134718 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7583 22:57:25.137930 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7584 22:57:25.141083 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7585 22:57:25.141510
7586 22:57:25.144632 CA PerBit enable=1, Macro0, CA PI delay=36
7587 22:57:25.145056
7588 22:57:25.147765 [CBTSetCACLKResult] CA Dly = 36
7589 22:57:25.151342 CS Dly: 9 (0~41)
7590 22:57:25.154691 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7591 22:57:25.157856 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7592 22:57:25.158397
7593 22:57:25.160943 ----->DramcWriteLeveling(PI) begin...
7594 22:57:25.161377 ==
7595 22:57:25.164127 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 22:57:25.167485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 22:57:25.170802 ==
7598 22:57:25.171244 Write leveling (Byte 0): 36 => 36
7599 22:57:25.174264 Write leveling (Byte 1): 25 => 25
7600 22:57:25.177749 DramcWriteLeveling(PI) end<-----
7601 22:57:25.178284
7602 22:57:25.178629 ==
7603 22:57:25.181084 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 22:57:25.187593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 22:57:25.188119 ==
7606 22:57:25.188471 [Gating] SW mode calibration
7607 22:57:25.197749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7608 22:57:25.201016 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7609 22:57:25.208146 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 22:57:25.211322 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 22:57:25.214679 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7612 22:57:25.217467 1 4 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7613 22:57:25.224118 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7614 22:57:25.227798 1 4 20 | B1->B0 | 3333 3535 | 1 1 | (1 1) (1 1)
7615 22:57:25.230834 1 4 24 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
7616 22:57:25.237404 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7617 22:57:25.240879 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7618 22:57:25.244036 1 5 4 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7619 22:57:25.250713 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7620 22:57:25.254009 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7621 22:57:25.257658 1 5 16 | B1->B0 | 3333 2828 | 0 0 | (0 1) (0 0)
7622 22:57:25.264355 1 5 20 | B1->B0 | 2626 2424 | 0 0 | (1 0) (0 0)
7623 22:57:25.267668 1 5 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7624 22:57:25.271096 1 5 28 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7625 22:57:25.277839 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7626 22:57:25.280875 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 22:57:25.284285 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7628 22:57:25.290977 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7629 22:57:25.294112 1 6 16 | B1->B0 | 2525 4645 | 0 1 | (0 0) (0 0)
7630 22:57:25.297757 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 22:57:25.304316 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 22:57:25.307591 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7633 22:57:25.310977 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 22:57:25.317172 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 22:57:25.320500 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 22:57:25.323657 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7637 22:57:25.330865 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7638 22:57:25.333952 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7639 22:57:25.337293 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 22:57:25.340414 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 22:57:25.346866 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 22:57:25.350762 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 22:57:25.354161 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 22:57:25.360432 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 22:57:25.363897 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 22:57:25.367150 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 22:57:25.373682 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 22:57:25.377103 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 22:57:25.380516 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 22:57:25.387337 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 22:57:25.390407 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7652 22:57:25.393968 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7653 22:57:25.400777 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7654 22:57:25.401302 Total UI for P1: 0, mck2ui 16
7655 22:57:25.407358 best dqsien dly found for B0: ( 1, 9, 10)
7656 22:57:25.410498 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 22:57:25.414020 Total UI for P1: 0, mck2ui 16
7658 22:57:25.417175 best dqsien dly found for B1: ( 1, 9, 18)
7659 22:57:25.420485 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7660 22:57:25.423580 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7661 22:57:25.424064
7662 22:57:25.426908 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7663 22:57:25.430569 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7664 22:57:25.433854 [Gating] SW calibration Done
7665 22:57:25.434378 ==
7666 22:57:25.436991 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 22:57:25.440393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 22:57:25.443496 ==
7669 22:57:25.443915 RX Vref Scan: 0
7670 22:57:25.444296
7671 22:57:25.447025 RX Vref 0 -> 0, step: 1
7672 22:57:25.447563
7673 22:57:25.447906 RX Delay 0 -> 252, step: 8
7674 22:57:25.453540 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7675 22:57:25.456998 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7676 22:57:25.460580 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7677 22:57:25.463539 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7678 22:57:25.466806 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7679 22:57:25.473444 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7680 22:57:25.476555 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7681 22:57:25.480275 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7682 22:57:25.483436 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7683 22:57:25.486828 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7684 22:57:25.493345 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7685 22:57:25.496747 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7686 22:57:25.500287 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7687 22:57:25.503363 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7688 22:57:25.506633 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7689 22:57:25.513806 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7690 22:57:25.514328 ==
7691 22:57:25.517043 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 22:57:25.520119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 22:57:25.520663 ==
7694 22:57:25.521006 DQS Delay:
7695 22:57:25.523662 DQS0 = 0, DQS1 = 0
7696 22:57:25.524211 DQM Delay:
7697 22:57:25.526982 DQM0 = 137, DQM1 = 131
7698 22:57:25.527400 DQ Delay:
7699 22:57:25.530120 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7700 22:57:25.533116 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7701 22:57:25.537104 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7702 22:57:25.539878 DQ12 =139, DQ13 =139, DQ14 =143, DQ15 =135
7703 22:57:25.543217
7704 22:57:25.543636
7705 22:57:25.544011 ==
7706 22:57:25.546610 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 22:57:25.550384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 22:57:25.550922 ==
7709 22:57:25.551266
7710 22:57:25.551578
7711 22:57:25.553106 TX Vref Scan disable
7712 22:57:25.553530 == TX Byte 0 ==
7713 22:57:25.559838 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7714 22:57:25.562717 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7715 22:57:25.563139 == TX Byte 1 ==
7716 22:57:25.569548 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7717 22:57:25.572899 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7718 22:57:25.573322 ==
7719 22:57:25.576310 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 22:57:25.579850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 22:57:25.580457 ==
7722 22:57:25.594862
7723 22:57:25.597787 TX Vref early break, caculate TX vref
7724 22:57:25.601083 TX Vref=16, minBit 7, minWin=22, winSum=380
7725 22:57:25.604564 TX Vref=18, minBit 1, minWin=23, winSum=386
7726 22:57:25.607790 TX Vref=20, minBit 1, minWin=23, winSum=400
7727 22:57:25.611229 TX Vref=22, minBit 4, minWin=24, winSum=408
7728 22:57:25.614214 TX Vref=24, minBit 0, minWin=25, winSum=418
7729 22:57:25.620786 TX Vref=26, minBit 0, minWin=25, winSum=423
7730 22:57:25.623896 TX Vref=28, minBit 0, minWin=25, winSum=420
7731 22:57:25.627059 TX Vref=30, minBit 0, minWin=24, winSum=412
7732 22:57:25.630808 TX Vref=32, minBit 0, minWin=24, winSum=401
7733 22:57:25.634297 TX Vref=34, minBit 2, minWin=23, winSum=394
7734 22:57:25.640556 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
7735 22:57:25.640669
7736 22:57:25.644078 Final TX Range 0 Vref 26
7737 22:57:25.644201
7738 22:57:25.644297 ==
7739 22:57:25.647624 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 22:57:25.651029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 22:57:25.651248 ==
7742 22:57:25.651368
7743 22:57:25.651473
7744 22:57:25.654316 TX Vref Scan disable
7745 22:57:25.661305 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7746 22:57:25.661565 == TX Byte 0 ==
7747 22:57:25.664270 u2DelayCellOfst[0]=10 cells (3 PI)
7748 22:57:25.667536 u2DelayCellOfst[1]=13 cells (4 PI)
7749 22:57:25.671000 u2DelayCellOfst[2]=6 cells (2 PI)
7750 22:57:25.674072 u2DelayCellOfst[3]=6 cells (2 PI)
7751 22:57:25.677793 u2DelayCellOfst[4]=6 cells (2 PI)
7752 22:57:25.680675 u2DelayCellOfst[5]=0 cells (0 PI)
7753 22:57:25.681065 u2DelayCellOfst[6]=16 cells (5 PI)
7754 22:57:25.684042 u2DelayCellOfst[7]=16 cells (5 PI)
7755 22:57:25.690831 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7756 22:57:25.694467 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7757 22:57:25.694987 == TX Byte 1 ==
7758 22:57:25.697553 u2DelayCellOfst[8]=0 cells (0 PI)
7759 22:57:25.701090 u2DelayCellOfst[9]=0 cells (0 PI)
7760 22:57:25.704265 u2DelayCellOfst[10]=3 cells (1 PI)
7761 22:57:25.707815 u2DelayCellOfst[11]=0 cells (0 PI)
7762 22:57:25.710991 u2DelayCellOfst[12]=6 cells (2 PI)
7763 22:57:25.714449 u2DelayCellOfst[13]=6 cells (2 PI)
7764 22:57:25.717794 u2DelayCellOfst[14]=10 cells (3 PI)
7765 22:57:25.721051 u2DelayCellOfst[15]=6 cells (2 PI)
7766 22:57:25.723978 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7767 22:57:25.727295 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7768 22:57:25.730739 DramC Write-DBI on
7769 22:57:25.731229 ==
7770 22:57:25.734249 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 22:57:25.737703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 22:57:25.738131 ==
7773 22:57:25.738469
7774 22:57:25.738781
7775 22:57:25.740523 TX Vref Scan disable
7776 22:57:25.743617 == TX Byte 0 ==
7777 22:57:25.747138 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7778 22:57:25.750398 == TX Byte 1 ==
7779 22:57:25.754051 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7780 22:57:25.754596 DramC Write-DBI off
7781 22:57:25.755114
7782 22:57:25.757003 [DATLAT]
7783 22:57:25.757438 Freq=1600, CH0 RK0
7784 22:57:25.757776
7785 22:57:25.760590 DATLAT Default: 0xf
7786 22:57:25.761014 0, 0xFFFF, sum = 0
7787 22:57:25.764036 1, 0xFFFF, sum = 0
7788 22:57:25.764469 2, 0xFFFF, sum = 0
7789 22:57:25.767249 3, 0xFFFF, sum = 0
7790 22:57:25.767678 4, 0xFFFF, sum = 0
7791 22:57:25.770248 5, 0xFFFF, sum = 0
7792 22:57:25.770672 6, 0xFFFF, sum = 0
7793 22:57:25.774276 7, 0xFFFF, sum = 0
7794 22:57:25.774702 8, 0xFFFF, sum = 0
7795 22:57:25.777299 9, 0xFFFF, sum = 0
7796 22:57:25.780718 10, 0xFFFF, sum = 0
7797 22:57:25.781148 11, 0xFFFF, sum = 0
7798 22:57:25.783863 12, 0xFFFF, sum = 0
7799 22:57:25.784347 13, 0xFFFF, sum = 0
7800 22:57:25.787316 14, 0x0, sum = 1
7801 22:57:25.787750 15, 0x0, sum = 2
7802 22:57:25.790330 16, 0x0, sum = 3
7803 22:57:25.790761 17, 0x0, sum = 4
7804 22:57:25.791109 best_step = 15
7805 22:57:25.791429
7806 22:57:25.794141 ==
7807 22:57:25.797212 Dram Type= 6, Freq= 0, CH_0, rank 0
7808 22:57:25.800730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7809 22:57:25.801160 ==
7810 22:57:25.801503 RX Vref Scan: 1
7811 22:57:25.801823
7812 22:57:25.804021 Set Vref Range= 24 -> 127
7813 22:57:25.804446
7814 22:57:25.807300 RX Vref 24 -> 127, step: 1
7815 22:57:25.807725
7816 22:57:25.810430 RX Delay 27 -> 252, step: 4
7817 22:57:25.810856
7818 22:57:25.813746 Set Vref, RX VrefLevel [Byte0]: 24
7819 22:57:25.817475 [Byte1]: 24
7820 22:57:25.817994
7821 22:57:25.820501 Set Vref, RX VrefLevel [Byte0]: 25
7822 22:57:25.823731 [Byte1]: 25
7823 22:57:25.824198
7824 22:57:25.827073 Set Vref, RX VrefLevel [Byte0]: 26
7825 22:57:25.830352 [Byte1]: 26
7826 22:57:25.833668
7827 22:57:25.834095 Set Vref, RX VrefLevel [Byte0]: 27
7828 22:57:25.837187 [Byte1]: 27
7829 22:57:25.841473
7830 22:57:25.841902 Set Vref, RX VrefLevel [Byte0]: 28
7831 22:57:25.844601 [Byte1]: 28
7832 22:57:25.849010
7833 22:57:25.849526 Set Vref, RX VrefLevel [Byte0]: 29
7834 22:57:25.852281 [Byte1]: 29
7835 22:57:25.856127
7836 22:57:25.856553 Set Vref, RX VrefLevel [Byte0]: 30
7837 22:57:25.859362 [Byte1]: 30
7838 22:57:25.863675
7839 22:57:25.864165 Set Vref, RX VrefLevel [Byte0]: 31
7840 22:57:25.867206 [Byte1]: 31
7841 22:57:25.871140
7842 22:57:25.871577 Set Vref, RX VrefLevel [Byte0]: 32
7843 22:57:25.874256 [Byte1]: 32
7844 22:57:25.878592
7845 22:57:25.879172 Set Vref, RX VrefLevel [Byte0]: 33
7846 22:57:25.881837 [Byte1]: 33
7847 22:57:25.886108
7848 22:57:25.886528 Set Vref, RX VrefLevel [Byte0]: 34
7849 22:57:25.889837 [Byte1]: 34
7850 22:57:25.894203
7851 22:57:25.894716 Set Vref, RX VrefLevel [Byte0]: 35
7852 22:57:25.897086 [Byte1]: 35
7853 22:57:25.902119
7854 22:57:25.902641 Set Vref, RX VrefLevel [Byte0]: 36
7855 22:57:25.905101 [Byte1]: 36
7856 22:57:25.909415
7857 22:57:25.909945 Set Vref, RX VrefLevel [Byte0]: 37
7858 22:57:25.912454 [Byte1]: 37
7859 22:57:25.916465
7860 22:57:25.916913 Set Vref, RX VrefLevel [Byte0]: 38
7861 22:57:25.920111 [Byte1]: 38
7862 22:57:25.924411
7863 22:57:25.924830 Set Vref, RX VrefLevel [Byte0]: 39
7864 22:57:25.927707 [Byte1]: 39
7865 22:57:25.932041
7866 22:57:25.932559 Set Vref, RX VrefLevel [Byte0]: 40
7867 22:57:25.935093 [Byte1]: 40
7868 22:57:25.939010
7869 22:57:25.939427 Set Vref, RX VrefLevel [Byte0]: 41
7870 22:57:25.942580 [Byte1]: 41
7871 22:57:25.947004
7872 22:57:25.947422 Set Vref, RX VrefLevel [Byte0]: 42
7873 22:57:25.950329 [Byte1]: 42
7874 22:57:25.954160
7875 22:57:25.954582 Set Vref, RX VrefLevel [Byte0]: 43
7876 22:57:25.957356 [Byte1]: 43
7877 22:57:25.962182
7878 22:57:25.962698 Set Vref, RX VrefLevel [Byte0]: 44
7879 22:57:25.965359 [Byte1]: 44
7880 22:57:25.969440
7881 22:57:25.969965 Set Vref, RX VrefLevel [Byte0]: 45
7882 22:57:25.972784 [Byte1]: 45
7883 22:57:25.976515
7884 22:57:25.976930 Set Vref, RX VrefLevel [Byte0]: 46
7885 22:57:25.980256 [Byte1]: 46
7886 22:57:25.984528
7887 22:57:25.985048 Set Vref, RX VrefLevel [Byte0]: 47
7888 22:57:25.987729 [Byte1]: 47
7889 22:57:25.991951
7890 22:57:25.992412 Set Vref, RX VrefLevel [Byte0]: 48
7891 22:57:25.995233 [Byte1]: 48
7892 22:57:25.999561
7893 22:57:26.000021 Set Vref, RX VrefLevel [Byte0]: 49
7894 22:57:26.002595 [Byte1]: 49
7895 22:57:26.006957
7896 22:57:26.007378 Set Vref, RX VrefLevel [Byte0]: 50
7897 22:57:26.009929 [Byte1]: 50
7898 22:57:26.014544
7899 22:57:26.015059 Set Vref, RX VrefLevel [Byte0]: 51
7900 22:57:26.017775 [Byte1]: 51
7901 22:57:26.021904
7902 22:57:26.022323 Set Vref, RX VrefLevel [Byte0]: 52
7903 22:57:26.025061 [Byte1]: 52
7904 22:57:26.029447
7905 22:57:26.029868 Set Vref, RX VrefLevel [Byte0]: 53
7906 22:57:26.032912 [Byte1]: 53
7907 22:57:26.037622
7908 22:57:26.038141 Set Vref, RX VrefLevel [Byte0]: 54
7909 22:57:26.040367 [Byte1]: 54
7910 22:57:26.044830
7911 22:57:26.045249 Set Vref, RX VrefLevel [Byte0]: 55
7912 22:57:26.048149 [Byte1]: 55
7913 22:57:26.052455
7914 22:57:26.053000 Set Vref, RX VrefLevel [Byte0]: 56
7915 22:57:26.055132 [Byte1]: 56
7916 22:57:26.059951
7917 22:57:26.060401 Set Vref, RX VrefLevel [Byte0]: 57
7918 22:57:26.062720 [Byte1]: 57
7919 22:57:26.067361
7920 22:57:26.067795 Set Vref, RX VrefLevel [Byte0]: 58
7921 22:57:26.070660 [Byte1]: 58
7922 22:57:26.075056
7923 22:57:26.075581 Set Vref, RX VrefLevel [Byte0]: 59
7924 22:57:26.078229 [Byte1]: 59
7925 22:57:26.082273
7926 22:57:26.082794 Set Vref, RX VrefLevel [Byte0]: 60
7927 22:57:26.085466 [Byte1]: 60
7928 22:57:26.090066
7929 22:57:26.090487 Set Vref, RX VrefLevel [Byte0]: 61
7930 22:57:26.093063 [Byte1]: 61
7931 22:57:26.097719
7932 22:57:26.098240 Set Vref, RX VrefLevel [Byte0]: 62
7933 22:57:26.100784 [Byte1]: 62
7934 22:57:26.105066
7935 22:57:26.105589 Set Vref, RX VrefLevel [Byte0]: 63
7936 22:57:26.107992 [Byte1]: 63
7937 22:57:26.112614
7938 22:57:26.113050 Set Vref, RX VrefLevel [Byte0]: 64
7939 22:57:26.116115 [Byte1]: 64
7940 22:57:26.119687
7941 22:57:26.120163 Set Vref, RX VrefLevel [Byte0]: 65
7942 22:57:26.123346 [Byte1]: 65
7943 22:57:26.127663
7944 22:57:26.128123 Set Vref, RX VrefLevel [Byte0]: 66
7945 22:57:26.130564 [Byte1]: 66
7946 22:57:26.134651
7947 22:57:26.135143 Set Vref, RX VrefLevel [Byte0]: 67
7948 22:57:26.138383 [Byte1]: 67
7949 22:57:26.142413
7950 22:57:26.142827 Set Vref, RX VrefLevel [Byte0]: 68
7951 22:57:26.145811 [Byte1]: 68
7952 22:57:26.150333
7953 22:57:26.150937 Set Vref, RX VrefLevel [Byte0]: 69
7954 22:57:26.153242 [Byte1]: 69
7955 22:57:26.157666
7956 22:57:26.158082 Set Vref, RX VrefLevel [Byte0]: 70
7957 22:57:26.160851 [Byte1]: 70
7958 22:57:26.165221
7959 22:57:26.165644 Set Vref, RX VrefLevel [Byte0]: 71
7960 22:57:26.168527 [Byte1]: 71
7961 22:57:26.172542
7962 22:57:26.173029 Set Vref, RX VrefLevel [Byte0]: 72
7963 22:57:26.175754 [Byte1]: 72
7964 22:57:26.180539
7965 22:57:26.181072 Final RX Vref Byte 0 = 57 to rank0
7966 22:57:26.183504 Final RX Vref Byte 1 = 61 to rank0
7967 22:57:26.186816 Final RX Vref Byte 0 = 57 to rank1
7968 22:57:26.190234 Final RX Vref Byte 1 = 61 to rank1==
7969 22:57:26.193612 Dram Type= 6, Freq= 0, CH_0, rank 0
7970 22:57:26.200267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 22:57:26.200924 ==
7972 22:57:26.201349 DQS Delay:
7973 22:57:26.202940 DQS0 = 0, DQS1 = 0
7974 22:57:26.203367 DQM Delay:
7975 22:57:26.203706 DQM0 = 134, DQM1 = 127
7976 22:57:26.207391 DQ Delay:
7977 22:57:26.209705 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7978 22:57:26.213193 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7979 22:57:26.216713 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7980 22:57:26.220084 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7981 22:57:26.220618
7982 22:57:26.220958
7983 22:57:26.221275
7984 22:57:26.222948 [DramC_TX_OE_Calibration] TA2
7985 22:57:26.226791 Original DQ_B0 (3 6) =30, OEN = 27
7986 22:57:26.230118 Original DQ_B1 (3 6) =30, OEN = 27
7987 22:57:26.232876 24, 0x0, End_B0=24 End_B1=24
7988 22:57:26.233311 25, 0x0, End_B0=25 End_B1=25
7989 22:57:26.236493 26, 0x0, End_B0=26 End_B1=26
7990 22:57:26.240234 27, 0x0, End_B0=27 End_B1=27
7991 22:57:26.243301 28, 0x0, End_B0=28 End_B1=28
7992 22:57:26.246506 29, 0x0, End_B0=29 End_B1=29
7993 22:57:26.246941 30, 0x0, End_B0=30 End_B1=30
7994 22:57:26.249929 31, 0x4141, End_B0=30 End_B1=30
7995 22:57:26.253272 Byte0 end_step=30 best_step=27
7996 22:57:26.256338 Byte1 end_step=30 best_step=27
7997 22:57:26.260083 Byte0 TX OE(2T, 0.5T) = (3, 3)
7998 22:57:26.263212 Byte1 TX OE(2T, 0.5T) = (3, 3)
7999 22:57:26.263637
8000 22:57:26.264008
8001 22:57:26.269524 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
8002 22:57:26.273213 CH0 RK0: MR19=303, MR18=2521
8003 22:57:26.279396 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
8004 22:57:26.279826
8005 22:57:26.282649 ----->DramcWriteLeveling(PI) begin...
8006 22:57:26.283080 ==
8007 22:57:26.285966 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 22:57:26.289661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 22:57:26.290091 ==
8010 22:57:26.292524 Write leveling (Byte 0): 35 => 35
8011 22:57:26.296346 Write leveling (Byte 1): 26 => 26
8012 22:57:26.299649 DramcWriteLeveling(PI) end<-----
8013 22:57:26.300224
8014 22:57:26.300598 ==
8015 22:57:26.302455 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 22:57:26.306740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 22:57:26.307357 ==
8018 22:57:26.309402 [Gating] SW mode calibration
8019 22:57:26.315993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8020 22:57:26.323058 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8021 22:57:26.326582 1 4 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8022 22:57:26.333112 1 4 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8023 22:57:26.336121 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 22:57:26.339948 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8025 22:57:26.342748 1 4 16 | B1->B0 | 3333 3636 | 1 1 | (1 1) (1 1)
8026 22:57:26.349682 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 22:57:26.353199 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8028 22:57:26.356164 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8029 22:57:26.362423 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8030 22:57:26.365724 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8031 22:57:26.369486 1 5 8 | B1->B0 | 3434 3737 | 1 0 | (1 0) (0 1)
8032 22:57:26.376068 1 5 12 | B1->B0 | 3434 2f2e | 1 1 | (1 0) (1 0)
8033 22:57:26.379376 1 5 16 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (1 0)
8034 22:57:26.382584 1 5 20 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8035 22:57:26.388872 1 5 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8036 22:57:26.392428 1 5 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8037 22:57:26.395821 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8038 22:57:26.402635 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
8039 22:57:26.405910 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8040 22:57:26.408999 1 6 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8041 22:57:26.415837 1 6 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
8042 22:57:26.418902 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 22:57:26.422211 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8044 22:57:26.428906 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8045 22:57:26.432061 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 22:57:26.436361 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 22:57:26.442065 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 22:57:26.445315 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8049 22:57:26.448928 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8050 22:57:26.455721 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 22:57:26.458865 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 22:57:26.462170 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 22:57:26.468568 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 22:57:26.471940 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 22:57:26.475308 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 22:57:26.482435 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 22:57:26.485231 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 22:57:26.488191 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 22:57:26.495410 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 22:57:26.498401 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 22:57:26.501705 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 22:57:26.505638 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 22:57:26.511660 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 22:57:26.515138 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8065 22:57:26.518409 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8066 22:57:26.521773 Total UI for P1: 0, mck2ui 16
8067 22:57:26.524949 best dqsien dly found for B1: ( 1, 9, 12)
8068 22:57:26.532064 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 22:57:26.535917 Total UI for P1: 0, mck2ui 16
8070 22:57:26.538793 best dqsien dly found for B0: ( 1, 9, 14)
8071 22:57:26.542079 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8072 22:57:26.545040 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8073 22:57:26.545463
8074 22:57:26.548489 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8075 22:57:26.552031 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8076 22:57:26.555411 [Gating] SW calibration Done
8077 22:57:26.555835 ==
8078 22:57:26.558445 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 22:57:26.562177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 22:57:26.562606 ==
8081 22:57:26.565190 RX Vref Scan: 0
8082 22:57:26.565614
8083 22:57:26.565952 RX Vref 0 -> 0, step: 1
8084 22:57:26.566263
8085 22:57:26.569069 RX Delay 0 -> 252, step: 8
8086 22:57:26.571831 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8087 22:57:26.578437 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8088 22:57:26.581766 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8089 22:57:26.585038 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8090 22:57:26.588455 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8091 22:57:26.591928 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8092 22:57:26.598002 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8093 22:57:26.601360 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8094 22:57:26.605156 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8095 22:57:26.608408 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8096 22:57:26.615126 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8097 22:57:26.618771 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8098 22:57:26.621467 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8099 22:57:26.624733 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8100 22:57:26.628165 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8101 22:57:26.634458 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8102 22:57:26.635008 ==
8103 22:57:26.637872 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 22:57:26.641313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 22:57:26.641736 ==
8106 22:57:26.642070 DQS Delay:
8107 22:57:26.644685 DQS0 = 0, DQS1 = 0
8108 22:57:26.645106 DQM Delay:
8109 22:57:26.648133 DQM0 = 137, DQM1 = 128
8110 22:57:26.648625 DQ Delay:
8111 22:57:26.651314 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8112 22:57:26.654528 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8113 22:57:26.657509 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8114 22:57:26.660897 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8115 22:57:26.661344
8116 22:57:26.661716
8117 22:57:26.664610 ==
8118 22:57:26.667750 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 22:57:26.671159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 22:57:26.671584 ==
8121 22:57:26.671918
8122 22:57:26.672312
8123 22:57:26.674416 TX Vref Scan disable
8124 22:57:26.674836 == TX Byte 0 ==
8125 22:57:26.677884 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8126 22:57:26.684012 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8127 22:57:26.684443 == TX Byte 1 ==
8128 22:57:26.691001 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8129 22:57:26.694143 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8130 22:57:26.694628 ==
8131 22:57:26.697548 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 22:57:26.700666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 22:57:26.701090 ==
8134 22:57:26.715664
8135 22:57:26.718994 TX Vref early break, caculate TX vref
8136 22:57:26.722378 TX Vref=16, minBit 1, minWin=23, winSum=388
8137 22:57:26.725107 TX Vref=18, minBit 0, minWin=24, winSum=395
8138 22:57:26.728881 TX Vref=20, minBit 1, minWin=24, winSum=409
8139 22:57:26.731995 TX Vref=22, minBit 1, minWin=24, winSum=414
8140 22:57:26.735432 TX Vref=24, minBit 3, minWin=25, winSum=423
8141 22:57:26.742184 TX Vref=26, minBit 0, minWin=26, winSum=428
8142 22:57:26.745403 TX Vref=28, minBit 0, minWin=25, winSum=425
8143 22:57:26.748462 TX Vref=30, minBit 0, minWin=25, winSum=416
8144 22:57:26.751702 TX Vref=32, minBit 0, minWin=25, winSum=412
8145 22:57:26.755389 TX Vref=34, minBit 4, minWin=24, winSum=404
8146 22:57:26.761508 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8147 22:57:26.762069
8148 22:57:26.764961 Final TX Range 0 Vref 26
8149 22:57:26.765386
8150 22:57:26.765816 ==
8151 22:57:26.768385 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 22:57:26.771746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 22:57:26.772246 ==
8154 22:57:26.772623
8155 22:57:26.772963
8156 22:57:26.775067 TX Vref Scan disable
8157 22:57:26.781125 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8158 22:57:26.781739 == TX Byte 0 ==
8159 22:57:26.784584 u2DelayCellOfst[0]=13 cells (4 PI)
8160 22:57:26.787909 u2DelayCellOfst[1]=16 cells (5 PI)
8161 22:57:26.791020 u2DelayCellOfst[2]=13 cells (4 PI)
8162 22:57:26.794737 u2DelayCellOfst[3]=13 cells (4 PI)
8163 22:57:26.797626 u2DelayCellOfst[4]=10 cells (3 PI)
8164 22:57:26.801179 u2DelayCellOfst[5]=0 cells (0 PI)
8165 22:57:26.804460 u2DelayCellOfst[6]=16 cells (5 PI)
8166 22:57:26.808007 u2DelayCellOfst[7]=16 cells (5 PI)
8167 22:57:26.811062 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8168 22:57:26.814338 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8169 22:57:26.817736 == TX Byte 1 ==
8170 22:57:26.821441 u2DelayCellOfst[8]=3 cells (1 PI)
8171 22:57:26.821676 u2DelayCellOfst[9]=0 cells (0 PI)
8172 22:57:26.824542 u2DelayCellOfst[10]=6 cells (2 PI)
8173 22:57:26.827680 u2DelayCellOfst[11]=3 cells (1 PI)
8174 22:57:26.831293 u2DelayCellOfst[12]=10 cells (3 PI)
8175 22:57:26.834340 u2DelayCellOfst[13]=13 cells (4 PI)
8176 22:57:26.838097 u2DelayCellOfst[14]=16 cells (5 PI)
8177 22:57:26.841050 u2DelayCellOfst[15]=10 cells (3 PI)
8178 22:57:26.844477 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8179 22:57:26.851445 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8180 22:57:26.851871 DramC Write-DBI on
8181 22:57:26.852214 ==
8182 22:57:26.855132 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 22:57:26.858408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 22:57:26.861713 ==
8185 22:57:26.862238
8186 22:57:26.862573
8187 22:57:26.862886 TX Vref Scan disable
8188 22:57:26.864855 == TX Byte 0 ==
8189 22:57:26.868118 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8190 22:57:26.871469 == TX Byte 1 ==
8191 22:57:26.875196 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8192 22:57:26.878466 DramC Write-DBI off
8193 22:57:26.878984
8194 22:57:26.879319 [DATLAT]
8195 22:57:26.879630 Freq=1600, CH0 RK1
8196 22:57:26.879928
8197 22:57:26.881641 DATLAT Default: 0xf
8198 22:57:26.884698 0, 0xFFFF, sum = 0
8199 22:57:26.885251 1, 0xFFFF, sum = 0
8200 22:57:26.887835 2, 0xFFFF, sum = 0
8201 22:57:26.888303 3, 0xFFFF, sum = 0
8202 22:57:26.891000 4, 0xFFFF, sum = 0
8203 22:57:26.891461 5, 0xFFFF, sum = 0
8204 22:57:26.894196 6, 0xFFFF, sum = 0
8205 22:57:26.894624 7, 0xFFFF, sum = 0
8206 22:57:26.897554 8, 0xFFFF, sum = 0
8207 22:57:26.898015 9, 0xFFFF, sum = 0
8208 22:57:26.901162 10, 0xFFFF, sum = 0
8209 22:57:26.901592 11, 0xFFFF, sum = 0
8210 22:57:26.904510 12, 0xFFFF, sum = 0
8211 22:57:26.904943 13, 0xFFFF, sum = 0
8212 22:57:26.907726 14, 0x0, sum = 1
8213 22:57:26.908119 15, 0x0, sum = 2
8214 22:57:26.911090 16, 0x0, sum = 3
8215 22:57:26.911320 17, 0x0, sum = 4
8216 22:57:26.914297 best_step = 15
8217 22:57:26.914527
8218 22:57:26.914707 ==
8219 22:57:26.917718 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 22:57:26.920781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 22:57:26.920935 ==
8222 22:57:26.923969 RX Vref Scan: 0
8223 22:57:26.924131
8224 22:57:26.924255 RX Vref 0 -> 0, step: 1
8225 22:57:26.924396
8226 22:57:26.927604 RX Delay 19 -> 252, step: 4
8227 22:57:26.934151 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8228 22:57:26.936962 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8229 22:57:26.940812 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8230 22:57:26.943653 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8231 22:57:26.946856 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8232 22:57:26.953575 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8233 22:57:26.957088 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8234 22:57:26.960108 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8235 22:57:26.963792 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8236 22:57:26.966929 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8237 22:57:26.973352 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8238 22:57:26.976646 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8239 22:57:26.979876 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8240 22:57:26.983853 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8241 22:57:26.986824 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8242 22:57:26.993200 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8243 22:57:26.993286 ==
8244 22:57:26.996806 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 22:57:27.000562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 22:57:27.000723 ==
8247 22:57:27.000800 DQS Delay:
8248 22:57:27.003686 DQS0 = 0, DQS1 = 0
8249 22:57:27.003810 DQM Delay:
8250 22:57:27.007250 DQM0 = 134, DQM1 = 127
8251 22:57:27.007410 DQ Delay:
8252 22:57:27.010416 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8253 22:57:27.013484 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8254 22:57:27.016530 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8255 22:57:27.020053 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8256 22:57:27.020239
8257 22:57:27.023276
8258 22:57:27.023453
8259 22:57:27.023546 [DramC_TX_OE_Calibration] TA2
8260 22:57:27.026474 Original DQ_B0 (3 6) =30, OEN = 27
8261 22:57:27.029723 Original DQ_B1 (3 6) =30, OEN = 27
8262 22:57:27.033110 24, 0x0, End_B0=24 End_B1=24
8263 22:57:27.036693 25, 0x0, End_B0=25 End_B1=25
8264 22:57:27.040409 26, 0x0, End_B0=26 End_B1=26
8265 22:57:27.040573 27, 0x0, End_B0=27 End_B1=27
8266 22:57:27.043530 28, 0x0, End_B0=28 End_B1=28
8267 22:57:27.046818 29, 0x0, End_B0=29 End_B1=29
8268 22:57:27.050311 30, 0x0, End_B0=30 End_B1=30
8269 22:57:27.053337 31, 0x4141, End_B0=30 End_B1=30
8270 22:57:27.053633 Byte0 end_step=30 best_step=27
8271 22:57:27.056640 Byte1 end_step=30 best_step=27
8272 22:57:27.059857 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 22:57:27.063659 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 22:57:27.063977
8275 22:57:27.064218
8276 22:57:27.070160 [DQSOSCAuto] RK1, (LSB)MR18= 0x2009, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8277 22:57:27.073156 CH0 RK1: MR19=303, MR18=2009
8278 22:57:27.080461 CH0_RK1: MR19=0x303, MR18=0x2009, DQSOSC=393, MR23=63, INC=23, DEC=15
8279 22:57:27.083419 [RxdqsGatingPostProcess] freq 1600
8280 22:57:27.089751 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 22:57:27.094005 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 22:57:27.094526 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 22:57:27.096548 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 22:57:27.100518 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 22:57:27.103625 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 22:57:27.107226 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 22:57:27.109963 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 22:57:27.113953 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 22:57:27.117065 Pre-setting of DQS Precalculation
8290 22:57:27.120391 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 22:57:27.123552 ==
8292 22:57:27.127033 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 22:57:27.130102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 22:57:27.130523 ==
8295 22:57:27.133320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 22:57:27.140350 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 22:57:27.143111 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 22:57:27.150203 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 22:57:27.157992 [CA 0] Center 42 (13~72) winsize 60
8300 22:57:27.161340 [CA 1] Center 42 (12~72) winsize 61
8301 22:57:27.164216 [CA 2] Center 39 (10~68) winsize 59
8302 22:57:27.167494 [CA 3] Center 38 (9~67) winsize 59
8303 22:57:27.170998 [CA 4] Center 38 (9~68) winsize 60
8304 22:57:27.174166 [CA 5] Center 37 (8~67) winsize 60
8305 22:57:27.174597
8306 22:57:27.177538 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8307 22:57:27.177965
8308 22:57:27.181327 [CATrainingPosCal] consider 1 rank data
8309 22:57:27.184503 u2DelayCellTimex100 = 290/100 ps
8310 22:57:27.191075 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8311 22:57:27.194141 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8312 22:57:27.197426 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8313 22:57:27.200771 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8314 22:57:27.204188 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8315 22:57:27.206863 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8316 22:57:27.207090
8317 22:57:27.210763 CA PerBit enable=1, Macro0, CA PI delay=37
8318 22:57:27.211091
8319 22:57:27.213837 [CBTSetCACLKResult] CA Dly = 37
8320 22:57:27.217039 CS Dly: 11 (0~42)
8321 22:57:27.220325 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 22:57:27.224216 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 22:57:27.224417 ==
8324 22:57:27.227494 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 22:57:27.234001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 22:57:27.234151 ==
8327 22:57:27.237227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 22:57:27.240435 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 22:57:27.247099 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 22:57:27.253807 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 22:57:27.260940 [CA 0] Center 42 (13~72) winsize 60
8332 22:57:27.264892 [CA 1] Center 42 (12~72) winsize 61
8333 22:57:27.267458 [CA 2] Center 38 (9~68) winsize 60
8334 22:57:27.271585 [CA 3] Center 37 (8~67) winsize 60
8335 22:57:27.274319 [CA 4] Center 38 (9~68) winsize 60
8336 22:57:27.277843 [CA 5] Center 37 (8~67) winsize 60
8337 22:57:27.278079
8338 22:57:27.281145 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8339 22:57:27.281374
8340 22:57:27.284307 [CATrainingPosCal] consider 2 rank data
8341 22:57:27.287622 u2DelayCellTimex100 = 290/100 ps
8342 22:57:27.291596 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8343 22:57:27.298042 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8344 22:57:27.301102 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8345 22:57:27.305145 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8346 22:57:27.308096 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8347 22:57:27.311914 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8348 22:57:27.312480
8349 22:57:27.314567 CA PerBit enable=1, Macro0, CA PI delay=37
8350 22:57:27.315078
8351 22:57:27.317996 [CBTSetCACLKResult] CA Dly = 37
8352 22:57:27.321686 CS Dly: 12 (0~45)
8353 22:57:27.324972 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 22:57:27.327883 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 22:57:27.328336
8356 22:57:27.331297 ----->DramcWriteLeveling(PI) begin...
8357 22:57:27.331757 ==
8358 22:57:27.334505 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 22:57:27.338126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 22:57:27.340735 ==
8361 22:57:27.344716 Write leveling (Byte 0): 26 => 26
8362 22:57:27.345135 Write leveling (Byte 1): 29 => 29
8363 22:57:27.347714 DramcWriteLeveling(PI) end<-----
8364 22:57:27.348165
8365 22:57:27.348498 ==
8366 22:57:27.351153 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 22:57:27.357861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 22:57:27.358284 ==
8369 22:57:27.360977 [Gating] SW mode calibration
8370 22:57:27.367679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 22:57:27.371386 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 22:57:27.377577 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 22:57:27.380749 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 22:57:27.384476 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8375 22:57:27.390847 1 4 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
8376 22:57:27.394068 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 22:57:27.397579 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 22:57:27.401076 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 22:57:27.407617 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 22:57:27.410914 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 22:57:27.414191 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 22:57:27.421047 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8383 22:57:27.424159 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8384 22:57:27.427085 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 22:57:27.434335 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 22:57:27.437644 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 22:57:27.440795 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 22:57:27.447325 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 22:57:27.450901 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 22:57:27.453948 1 6 8 | B1->B0 | 2525 3939 | 0 0 | (0 0) (0 0)
8391 22:57:27.461140 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8392 22:57:27.464086 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 22:57:27.467761 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 22:57:27.474241 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 22:57:27.477943 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 22:57:27.480747 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 22:57:27.487034 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 22:57:27.490580 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8399 22:57:27.494644 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8400 22:57:27.500583 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 22:57:27.503882 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 22:57:27.507710 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 22:57:27.514051 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 22:57:27.517359 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 22:57:27.520441 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 22:57:27.524265 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 22:57:27.531123 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 22:57:27.534190 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 22:57:27.537513 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 22:57:27.543629 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 22:57:27.547004 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 22:57:27.550220 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 22:57:27.556824 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 22:57:27.560107 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 22:57:27.563695 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8416 22:57:27.570196 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 22:57:27.573360 Total UI for P1: 0, mck2ui 16
8418 22:57:27.577036 best dqsien dly found for B0: ( 1, 9, 10)
8419 22:57:27.580332 Total UI for P1: 0, mck2ui 16
8420 22:57:27.583756 best dqsien dly found for B1: ( 1, 9, 10)
8421 22:57:27.586987 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8422 22:57:27.590403 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8423 22:57:27.590964
8424 22:57:27.593147 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8425 22:57:27.596804 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8426 22:57:27.600062 [Gating] SW calibration Done
8427 22:57:27.600580 ==
8428 22:57:27.603384 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 22:57:27.606899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 22:57:27.607426 ==
8431 22:57:27.609980 RX Vref Scan: 0
8432 22:57:27.610501
8433 22:57:27.613371 RX Vref 0 -> 0, step: 1
8434 22:57:27.613793
8435 22:57:27.614133 RX Delay 0 -> 252, step: 8
8436 22:57:27.620111 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8437 22:57:27.623461 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8438 22:57:27.626582 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8439 22:57:27.629609 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8440 22:57:27.633244 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8441 22:57:27.639692 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8442 22:57:27.642878 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8443 22:57:27.646244 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8444 22:57:27.649658 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8445 22:57:27.652755 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8446 22:57:27.656717 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8447 22:57:27.663096 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8448 22:57:27.666391 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8449 22:57:27.669468 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8450 22:57:27.673266 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8451 22:57:27.679702 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8452 22:57:27.680285 ==
8453 22:57:27.683038 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 22:57:27.686326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 22:57:27.686788 ==
8456 22:57:27.687141 DQS Delay:
8457 22:57:27.689988 DQS0 = 0, DQS1 = 0
8458 22:57:27.690504 DQM Delay:
8459 22:57:27.693084 DQM0 = 136, DQM1 = 133
8460 22:57:27.693504 DQ Delay:
8461 22:57:27.696620 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8462 22:57:27.699703 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8463 22:57:27.702936 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8464 22:57:27.706437 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8465 22:57:27.706861
8466 22:57:27.707199
8467 22:57:27.709375 ==
8468 22:57:27.709797 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 22:57:27.716374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 22:57:27.716897 ==
8471 22:57:27.717239
8472 22:57:27.717551
8473 22:57:27.719398 TX Vref Scan disable
8474 22:57:27.719818 == TX Byte 0 ==
8475 22:57:27.722767 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8476 22:57:27.729746 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8477 22:57:27.730285 == TX Byte 1 ==
8478 22:57:27.732510 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8479 22:57:27.739192 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8480 22:57:27.739720 ==
8481 22:57:27.742612 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 22:57:27.745556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 22:57:27.745982 ==
8484 22:57:27.759147
8485 22:57:27.762343 TX Vref early break, caculate TX vref
8486 22:57:27.765211 TX Vref=16, minBit 6, minWin=22, winSum=373
8487 22:57:27.768367 TX Vref=18, minBit 0, minWin=23, winSum=385
8488 22:57:27.772289 TX Vref=20, minBit 1, minWin=23, winSum=394
8489 22:57:27.775434 TX Vref=22, minBit 6, minWin=24, winSum=404
8490 22:57:27.778696 TX Vref=24, minBit 0, minWin=25, winSum=412
8491 22:57:27.785723 TX Vref=26, minBit 1, minWin=25, winSum=424
8492 22:57:27.788788 TX Vref=28, minBit 1, minWin=25, winSum=424
8493 22:57:27.791995 TX Vref=30, minBit 0, minWin=25, winSum=418
8494 22:57:27.795434 TX Vref=32, minBit 0, minWin=24, winSum=411
8495 22:57:27.799091 TX Vref=34, minBit 0, minWin=23, winSum=401
8496 22:57:27.805504 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26
8497 22:57:27.806034
8498 22:57:27.808800 Final TX Range 0 Vref 26
8499 22:57:27.809307
8500 22:57:27.809824 ==
8501 22:57:27.811526 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 22:57:27.815466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 22:57:27.816128 ==
8504 22:57:27.816485
8505 22:57:27.816881
8506 22:57:27.818462 TX Vref Scan disable
8507 22:57:27.825396 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8508 22:57:27.825970 == TX Byte 0 ==
8509 22:57:27.828668 u2DelayCellOfst[0]=13 cells (4 PI)
8510 22:57:27.831296 u2DelayCellOfst[1]=10 cells (3 PI)
8511 22:57:27.834637 u2DelayCellOfst[2]=0 cells (0 PI)
8512 22:57:27.838630 u2DelayCellOfst[3]=6 cells (2 PI)
8513 22:57:27.841474 u2DelayCellOfst[4]=6 cells (2 PI)
8514 22:57:27.844613 u2DelayCellOfst[5]=16 cells (5 PI)
8515 22:57:27.848000 u2DelayCellOfst[6]=16 cells (5 PI)
8516 22:57:27.848438 u2DelayCellOfst[7]=6 cells (2 PI)
8517 22:57:27.855169 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8518 22:57:27.858107 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8519 22:57:27.861513 == TX Byte 1 ==
8520 22:57:27.862034 u2DelayCellOfst[8]=0 cells (0 PI)
8521 22:57:27.865673 u2DelayCellOfst[9]=3 cells (1 PI)
8522 22:57:27.867987 u2DelayCellOfst[10]=13 cells (4 PI)
8523 22:57:27.871438 u2DelayCellOfst[11]=6 cells (2 PI)
8524 22:57:27.874524 u2DelayCellOfst[12]=16 cells (5 PI)
8525 22:57:27.878459 u2DelayCellOfst[13]=16 cells (5 PI)
8526 22:57:27.882047 u2DelayCellOfst[14]=16 cells (5 PI)
8527 22:57:27.885132 u2DelayCellOfst[15]=16 cells (5 PI)
8528 22:57:27.887812 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8529 22:57:27.895004 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8530 22:57:27.895523 DramC Write-DBI on
8531 22:57:27.895861 ==
8532 22:57:27.898129 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 22:57:27.901296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 22:57:27.904502 ==
8535 22:57:27.904926
8536 22:57:27.905260
8537 22:57:27.905572 TX Vref Scan disable
8538 22:57:27.908409 == TX Byte 0 ==
8539 22:57:27.911582 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8540 22:57:27.914900 == TX Byte 1 ==
8541 22:57:27.917981 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8542 22:57:27.921366 DramC Write-DBI off
8543 22:57:27.921886
8544 22:57:27.922225 [DATLAT]
8545 22:57:27.922535 Freq=1600, CH1 RK0
8546 22:57:27.922837
8547 22:57:27.924458 DATLAT Default: 0xf
8548 22:57:27.924881 0, 0xFFFF, sum = 0
8549 22:57:27.927582 1, 0xFFFF, sum = 0
8550 22:57:27.931484 2, 0xFFFF, sum = 0
8551 22:57:27.931912 3, 0xFFFF, sum = 0
8552 22:57:27.934423 4, 0xFFFF, sum = 0
8553 22:57:27.934867 5, 0xFFFF, sum = 0
8554 22:57:27.938105 6, 0xFFFF, sum = 0
8555 22:57:27.938639 7, 0xFFFF, sum = 0
8556 22:57:27.941407 8, 0xFFFF, sum = 0
8557 22:57:27.941836 9, 0xFFFF, sum = 0
8558 22:57:27.944597 10, 0xFFFF, sum = 0
8559 22:57:27.945134 11, 0xFFFF, sum = 0
8560 22:57:27.947874 12, 0xFFFF, sum = 0
8561 22:57:27.948336 13, 0xFFFF, sum = 0
8562 22:57:27.951154 14, 0x0, sum = 1
8563 22:57:27.951598 15, 0x0, sum = 2
8564 22:57:27.954752 16, 0x0, sum = 3
8565 22:57:27.955179 17, 0x0, sum = 4
8566 22:57:27.957762 best_step = 15
8567 22:57:27.958183
8568 22:57:27.958517 ==
8569 22:57:27.961411 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 22:57:27.964530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 22:57:27.964956 ==
8572 22:57:27.968056 RX Vref Scan: 1
8573 22:57:27.968489
8574 22:57:27.968920 Set Vref Range= 24 -> 127
8575 22:57:27.969330
8576 22:57:27.971430 RX Vref 24 -> 127, step: 1
8577 22:57:27.971888
8578 22:57:27.974609 RX Delay 27 -> 252, step: 4
8579 22:57:27.975102
8580 22:57:27.977926 Set Vref, RX VrefLevel [Byte0]: 24
8581 22:57:27.981336 [Byte1]: 24
8582 22:57:27.981771
8583 22:57:27.984494 Set Vref, RX VrefLevel [Byte0]: 25
8584 22:57:27.987571 [Byte1]: 25
8585 22:57:27.988080
8586 22:57:27.991168 Set Vref, RX VrefLevel [Byte0]: 26
8587 22:57:27.994331 [Byte1]: 26
8588 22:57:27.998383
8589 22:57:27.998915 Set Vref, RX VrefLevel [Byte0]: 27
8590 22:57:28.001739 [Byte1]: 27
8591 22:57:28.006251
8592 22:57:28.006781 Set Vref, RX VrefLevel [Byte0]: 28
8593 22:57:28.009592 [Byte1]: 28
8594 22:57:28.013091
8595 22:57:28.013525 Set Vref, RX VrefLevel [Byte0]: 29
8596 22:57:28.016488 [Byte1]: 29
8597 22:57:28.020687
8598 22:57:28.021125 Set Vref, RX VrefLevel [Byte0]: 30
8599 22:57:28.024312 [Byte1]: 30
8600 22:57:28.028066
8601 22:57:28.028488 Set Vref, RX VrefLevel [Byte0]: 31
8602 22:57:28.031612 [Byte1]: 31
8603 22:57:28.036095
8604 22:57:28.036518 Set Vref, RX VrefLevel [Byte0]: 32
8605 22:57:28.039210 [Byte1]: 32
8606 22:57:28.043921
8607 22:57:28.044588 Set Vref, RX VrefLevel [Byte0]: 33
8608 22:57:28.046447 [Byte1]: 33
8609 22:57:28.050805
8610 22:57:28.051420 Set Vref, RX VrefLevel [Byte0]: 34
8611 22:57:28.054858 [Byte1]: 34
8612 22:57:28.058824
8613 22:57:28.059345 Set Vref, RX VrefLevel [Byte0]: 35
8614 22:57:28.062042 [Byte1]: 35
8615 22:57:28.066192
8616 22:57:28.066619 Set Vref, RX VrefLevel [Byte0]: 36
8617 22:57:28.069434 [Byte1]: 36
8618 22:57:28.073717
8619 22:57:28.074232 Set Vref, RX VrefLevel [Byte0]: 37
8620 22:57:28.076785 [Byte1]: 37
8621 22:57:28.080818
8622 22:57:28.081278 Set Vref, RX VrefLevel [Byte0]: 38
8623 22:57:28.084437 [Byte1]: 38
8624 22:57:28.088643
8625 22:57:28.089064 Set Vref, RX VrefLevel [Byte0]: 39
8626 22:57:28.091844 [Byte1]: 39
8627 22:57:28.096664
8628 22:57:28.097178 Set Vref, RX VrefLevel [Byte0]: 40
8629 22:57:28.099761 [Byte1]: 40
8630 22:57:28.104025
8631 22:57:28.104542 Set Vref, RX VrefLevel [Byte0]: 41
8632 22:57:28.107217 [Byte1]: 41
8633 22:57:28.111935
8634 22:57:28.112555 Set Vref, RX VrefLevel [Byte0]: 42
8635 22:57:28.114480 [Byte1]: 42
8636 22:57:28.119197
8637 22:57:28.119757 Set Vref, RX VrefLevel [Byte0]: 43
8638 22:57:28.122223 [Byte1]: 43
8639 22:57:28.126456
8640 22:57:28.126922 Set Vref, RX VrefLevel [Byte0]: 44
8641 22:57:28.129465 [Byte1]: 44
8642 22:57:28.134077
8643 22:57:28.134496 Set Vref, RX VrefLevel [Byte0]: 45
8644 22:57:28.137160 [Byte1]: 45
8645 22:57:28.141409
8646 22:57:28.141932 Set Vref, RX VrefLevel [Byte0]: 46
8647 22:57:28.144578 [Byte1]: 46
8648 22:57:28.148778
8649 22:57:28.149295 Set Vref, RX VrefLevel [Byte0]: 47
8650 22:57:28.152116 [Byte1]: 47
8651 22:57:28.156312
8652 22:57:28.156809 Set Vref, RX VrefLevel [Byte0]: 48
8653 22:57:28.159515 [Byte1]: 48
8654 22:57:28.164157
8655 22:57:28.164669 Set Vref, RX VrefLevel [Byte0]: 49
8656 22:57:28.167948 [Byte1]: 49
8657 22:57:28.171316
8658 22:57:28.171737 Set Vref, RX VrefLevel [Byte0]: 50
8659 22:57:28.174764 [Byte1]: 50
8660 22:57:28.178962
8661 22:57:28.179384 Set Vref, RX VrefLevel [Byte0]: 51
8662 22:57:28.182045 [Byte1]: 51
8663 22:57:28.187000
8664 22:57:28.187522 Set Vref, RX VrefLevel [Byte0]: 52
8665 22:57:28.190062 [Byte1]: 52
8666 22:57:28.193804
8667 22:57:28.194226 Set Vref, RX VrefLevel [Byte0]: 53
8668 22:57:28.197592 [Byte1]: 53
8669 22:57:28.201685
8670 22:57:28.202230 Set Vref, RX VrefLevel [Byte0]: 54
8671 22:57:28.204640 [Byte1]: 54
8672 22:57:28.209018
8673 22:57:28.209535 Set Vref, RX VrefLevel [Byte0]: 55
8674 22:57:28.212649 [Byte1]: 55
8675 22:57:28.216456
8676 22:57:28.216877 Set Vref, RX VrefLevel [Byte0]: 56
8677 22:57:28.219882 [Byte1]: 56
8678 22:57:28.224624
8679 22:57:28.225045 Set Vref, RX VrefLevel [Byte0]: 57
8680 22:57:28.227172 [Byte1]: 57
8681 22:57:28.232104
8682 22:57:28.232619 Set Vref, RX VrefLevel [Byte0]: 58
8683 22:57:28.235277 [Byte1]: 58
8684 22:57:28.239513
8685 22:57:28.240072 Set Vref, RX VrefLevel [Byte0]: 59
8686 22:57:28.242793 [Byte1]: 59
8687 22:57:28.247098
8688 22:57:28.247520 Set Vref, RX VrefLevel [Byte0]: 60
8689 22:57:28.249975 [Byte1]: 60
8690 22:57:28.254569
8691 22:57:28.255163 Set Vref, RX VrefLevel [Byte0]: 61
8692 22:57:28.257464 [Byte1]: 61
8693 22:57:28.261557
8694 22:57:28.261979 Set Vref, RX VrefLevel [Byte0]: 62
8695 22:57:28.264951 [Byte1]: 62
8696 22:57:28.269218
8697 22:57:28.269654 Set Vref, RX VrefLevel [Byte0]: 63
8698 22:57:28.272466 [Byte1]: 63
8699 22:57:28.277534
8700 22:57:28.278056 Set Vref, RX VrefLevel [Byte0]: 64
8701 22:57:28.279911 [Byte1]: 64
8702 22:57:28.284551
8703 22:57:28.284975 Set Vref, RX VrefLevel [Byte0]: 65
8704 22:57:28.287756 [Byte1]: 65
8705 22:57:28.292059
8706 22:57:28.292481 Set Vref, RX VrefLevel [Byte0]: 66
8707 22:57:28.295527 [Byte1]: 66
8708 22:57:28.299462
8709 22:57:28.299883 Set Vref, RX VrefLevel [Byte0]: 67
8710 22:57:28.302595 [Byte1]: 67
8711 22:57:28.307483
8712 22:57:28.308039 Set Vref, RX VrefLevel [Byte0]: 68
8713 22:57:28.310489 [Byte1]: 68
8714 22:57:28.314180
8715 22:57:28.314605 Set Vref, RX VrefLevel [Byte0]: 69
8716 22:57:28.318229 [Byte1]: 69
8717 22:57:28.322298
8718 22:57:28.322724 Set Vref, RX VrefLevel [Byte0]: 70
8719 22:57:28.325227 [Byte1]: 70
8720 22:57:28.329383
8721 22:57:28.329816 Set Vref, RX VrefLevel [Byte0]: 71
8722 22:57:28.333202 [Byte1]: 71
8723 22:57:28.337227
8724 22:57:28.337649 Set Vref, RX VrefLevel [Byte0]: 72
8725 22:57:28.340652 [Byte1]: 72
8726 22:57:28.344579
8727 22:57:28.345049 Set Vref, RX VrefLevel [Byte0]: 73
8728 22:57:28.347774 [Byte1]: 73
8729 22:57:28.352368
8730 22:57:28.352787 Set Vref, RX VrefLevel [Byte0]: 74
8731 22:57:28.355859 [Byte1]: 74
8732 22:57:28.359851
8733 22:57:28.360429 Final RX Vref Byte 0 = 57 to rank0
8734 22:57:28.362903 Final RX Vref Byte 1 = 56 to rank0
8735 22:57:28.366040 Final RX Vref Byte 0 = 57 to rank1
8736 22:57:28.369760 Final RX Vref Byte 1 = 56 to rank1==
8737 22:57:28.372765 Dram Type= 6, Freq= 0, CH_1, rank 0
8738 22:57:28.379669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 22:57:28.380150 ==
8740 22:57:28.380497 DQS Delay:
8741 22:57:28.380815 DQS0 = 0, DQS1 = 0
8742 22:57:28.383005 DQM Delay:
8743 22:57:28.383426 DQM0 = 134, DQM1 = 131
8744 22:57:28.386426 DQ Delay:
8745 22:57:28.389947 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8746 22:57:28.392883 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8747 22:57:28.396170 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8748 22:57:28.399554 DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140
8749 22:57:28.400072
8750 22:57:28.400526
8751 22:57:28.400957
8752 22:57:28.402771 [DramC_TX_OE_Calibration] TA2
8753 22:57:28.406737 Original DQ_B0 (3 6) =30, OEN = 27
8754 22:57:28.410246 Original DQ_B1 (3 6) =30, OEN = 27
8755 22:57:28.413330 24, 0x0, End_B0=24 End_B1=24
8756 22:57:28.413757 25, 0x0, End_B0=25 End_B1=25
8757 22:57:28.416556 26, 0x0, End_B0=26 End_B1=26
8758 22:57:28.419629 27, 0x0, End_B0=27 End_B1=27
8759 22:57:28.423151 28, 0x0, End_B0=28 End_B1=28
8760 22:57:28.423677 29, 0x0, End_B0=29 End_B1=29
8761 22:57:28.426354 30, 0x0, End_B0=30 End_B1=30
8762 22:57:28.429338 31, 0x4141, End_B0=30 End_B1=30
8763 22:57:28.433240 Byte0 end_step=30 best_step=27
8764 22:57:28.436567 Byte1 end_step=30 best_step=27
8765 22:57:28.440217 Byte0 TX OE(2T, 0.5T) = (3, 3)
8766 22:57:28.440735 Byte1 TX OE(2T, 0.5T) = (3, 3)
8767 22:57:28.441077
8768 22:57:28.442929
8769 22:57:28.449531 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8770 22:57:28.452868 CH1 RK0: MR19=303, MR18=1623
8771 22:57:28.459836 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8772 22:57:28.460406
8773 22:57:28.462850 ----->DramcWriteLeveling(PI) begin...
8774 22:57:28.463280 ==
8775 22:57:28.466584 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 22:57:28.469804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 22:57:28.470331 ==
8778 22:57:28.472722 Write leveling (Byte 0): 26 => 26
8779 22:57:28.476482 Write leveling (Byte 1): 29 => 29
8780 22:57:28.479674 DramcWriteLeveling(PI) end<-----
8781 22:57:28.480247
8782 22:57:28.480592 ==
8783 22:57:28.482892 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 22:57:28.486178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 22:57:28.486609 ==
8786 22:57:28.489199 [Gating] SW mode calibration
8787 22:57:28.496072 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8788 22:57:28.502732 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8789 22:57:28.506061 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 22:57:28.509774 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 22:57:28.515904 1 4 8 | B1->B0 | 2f2e 2323 | 1 0 | (0 0) (0 0)
8792 22:57:28.519363 1 4 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
8793 22:57:28.522683 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 22:57:28.529287 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 22:57:28.532723 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 22:57:28.535743 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 22:57:28.543009 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 22:57:28.546139 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8799 22:57:28.549165 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
8800 22:57:28.555933 1 5 12 | B1->B0 | 2626 3030 | 0 1 | (0 0) (1 0)
8801 22:57:28.559001 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 22:57:28.562402 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 22:57:28.569075 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 22:57:28.572296 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 22:57:28.576401 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 22:57:28.583113 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 22:57:28.585540 1 6 8 | B1->B0 | 3939 2424 | 0 0 | (0 0) (0 0)
8808 22:57:28.588821 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8809 22:57:28.595934 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 22:57:28.599258 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 22:57:28.602457 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 22:57:28.606183 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 22:57:28.612707 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 22:57:28.616272 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 22:57:28.619525 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8816 22:57:28.625753 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8817 22:57:28.629096 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8818 22:57:28.632286 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 22:57:28.639066 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 22:57:28.642542 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 22:57:28.646038 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 22:57:28.652306 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 22:57:28.655876 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 22:57:28.659160 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 22:57:28.665745 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 22:57:28.669243 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 22:57:28.672462 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 22:57:28.679132 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 22:57:28.682686 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 22:57:28.685653 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8831 22:57:28.688833 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8832 22:57:28.696198 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8833 22:57:28.699608 Total UI for P1: 0, mck2ui 16
8834 22:57:28.703047 best dqsien dly found for B1: ( 1, 9, 6)
8835 22:57:28.706133 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 22:57:28.709401 Total UI for P1: 0, mck2ui 16
8837 22:57:28.712504 best dqsien dly found for B0: ( 1, 9, 12)
8838 22:57:28.715881 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8839 22:57:28.719644 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8840 22:57:28.720207
8841 22:57:28.722868 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8842 22:57:28.726154 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8843 22:57:28.729148 [Gating] SW calibration Done
8844 22:57:28.729654 ==
8845 22:57:28.732605 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 22:57:28.739392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 22:57:28.739919 ==
8848 22:57:28.740315 RX Vref Scan: 0
8849 22:57:28.740632
8850 22:57:28.742566 RX Vref 0 -> 0, step: 1
8851 22:57:28.742988
8852 22:57:28.746122 RX Delay 0 -> 252, step: 8
8853 22:57:28.749099 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8854 22:57:28.751789 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8855 22:57:28.755524 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8856 22:57:28.758840 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8857 22:57:28.765466 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8858 22:57:28.768705 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8859 22:57:28.771793 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8860 22:57:28.775324 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8861 22:57:28.778408 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8862 22:57:28.785167 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8863 22:57:28.788202 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8864 22:57:28.791580 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8865 22:57:28.795324 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8866 22:57:28.801507 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8867 22:57:28.805296 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8868 22:57:28.808540 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8869 22:57:28.808965 ==
8870 22:57:28.811727 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 22:57:28.815172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 22:57:28.815690 ==
8873 22:57:28.818414 DQS Delay:
8874 22:57:28.818838 DQS0 = 0, DQS1 = 0
8875 22:57:28.821455 DQM Delay:
8876 22:57:28.821973 DQM0 = 136, DQM1 = 133
8877 22:57:28.822314 DQ Delay:
8878 22:57:28.825238 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8879 22:57:28.831286 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8880 22:57:28.834962 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8881 22:57:28.838370 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8882 22:57:28.838818
8883 22:57:28.839228
8884 22:57:28.839554 ==
8885 22:57:28.841696 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 22:57:28.845344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 22:57:28.845773 ==
8888 22:57:28.846163
8889 22:57:28.846497
8890 22:57:28.848335 TX Vref Scan disable
8891 22:57:28.851607 == TX Byte 0 ==
8892 22:57:28.854815 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8893 22:57:28.858165 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8894 22:57:28.861416 == TX Byte 1 ==
8895 22:57:28.864772 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8896 22:57:28.868054 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8897 22:57:28.868486 ==
8898 22:57:28.871498 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 22:57:28.874685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 22:57:28.878022 ==
8901 22:57:28.890300
8902 22:57:28.893739 TX Vref early break, caculate TX vref
8903 22:57:28.896654 TX Vref=16, minBit 0, minWin=22, winSum=384
8904 22:57:28.900320 TX Vref=18, minBit 0, minWin=24, winSum=393
8905 22:57:28.903416 TX Vref=20, minBit 0, minWin=23, winSum=400
8906 22:57:28.906718 TX Vref=22, minBit 0, minWin=24, winSum=410
8907 22:57:28.910381 TX Vref=24, minBit 0, minWin=25, winSum=416
8908 22:57:28.916855 TX Vref=26, minBit 0, minWin=25, winSum=421
8909 22:57:28.920108 TX Vref=28, minBit 0, minWin=25, winSum=423
8910 22:57:28.923607 TX Vref=30, minBit 6, minWin=25, winSum=419
8911 22:57:28.926829 TX Vref=32, minBit 1, minWin=25, winSum=411
8912 22:57:28.929765 TX Vref=34, minBit 0, minWin=24, winSum=402
8913 22:57:28.932997 TX Vref=36, minBit 0, minWin=24, winSum=394
8914 22:57:28.940018 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8915 22:57:28.940447
8916 22:57:28.943176 Final TX Range 0 Vref 28
8917 22:57:28.943607
8918 22:57:28.943947 ==
8919 22:57:28.946607 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 22:57:28.949864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 22:57:28.950292 ==
8922 22:57:28.950803
8923 22:57:28.952808
8924 22:57:28.953234 TX Vref Scan disable
8925 22:57:28.959741 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8926 22:57:28.960272 == TX Byte 0 ==
8927 22:57:28.962994 u2DelayCellOfst[0]=16 cells (5 PI)
8928 22:57:28.966224 u2DelayCellOfst[1]=10 cells (3 PI)
8929 22:57:28.969642 u2DelayCellOfst[2]=0 cells (0 PI)
8930 22:57:28.972825 u2DelayCellOfst[3]=6 cells (2 PI)
8931 22:57:28.976139 u2DelayCellOfst[4]=10 cells (3 PI)
8932 22:57:28.979489 u2DelayCellOfst[5]=16 cells (5 PI)
8933 22:57:28.982995 u2DelayCellOfst[6]=16 cells (5 PI)
8934 22:57:28.986420 u2DelayCellOfst[7]=6 cells (2 PI)
8935 22:57:28.989350 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8936 22:57:28.992918 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8937 22:57:28.996256 == TX Byte 1 ==
8938 22:57:28.999561 u2DelayCellOfst[8]=0 cells (0 PI)
8939 22:57:29.002857 u2DelayCellOfst[9]=3 cells (1 PI)
8940 22:57:29.003391 u2DelayCellOfst[10]=10 cells (3 PI)
8941 22:57:29.006759 u2DelayCellOfst[11]=3 cells (1 PI)
8942 22:57:29.009811 u2DelayCellOfst[12]=16 cells (5 PI)
8943 22:57:29.013184 u2DelayCellOfst[13]=16 cells (5 PI)
8944 22:57:29.015911 u2DelayCellOfst[14]=16 cells (5 PI)
8945 22:57:29.019786 u2DelayCellOfst[15]=16 cells (5 PI)
8946 22:57:29.026349 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8947 22:57:29.029784 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8948 22:57:29.030241 DramC Write-DBI on
8949 22:57:29.030577 ==
8950 22:57:29.032990 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 22:57:29.038850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 22:57:29.039335 ==
8953 22:57:29.039830
8954 22:57:29.040348
8955 22:57:29.040663 TX Vref Scan disable
8956 22:57:29.043596 == TX Byte 0 ==
8957 22:57:29.046612 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8958 22:57:29.049801 == TX Byte 1 ==
8959 22:57:29.053536 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8960 22:57:29.056355 DramC Write-DBI off
8961 22:57:29.056797
8962 22:57:29.057244 [DATLAT]
8963 22:57:29.057717 Freq=1600, CH1 RK1
8964 22:57:29.058129
8965 22:57:29.060250 DATLAT Default: 0xf
8966 22:57:29.060795 0, 0xFFFF, sum = 0
8967 22:57:29.063557 1, 0xFFFF, sum = 0
8968 22:57:29.066798 2, 0xFFFF, sum = 0
8969 22:57:29.067254 3, 0xFFFF, sum = 0
8970 22:57:29.069661 4, 0xFFFF, sum = 0
8971 22:57:29.070094 5, 0xFFFF, sum = 0
8972 22:57:29.073802 6, 0xFFFF, sum = 0
8973 22:57:29.074341 7, 0xFFFF, sum = 0
8974 22:57:29.076887 8, 0xFFFF, sum = 0
8975 22:57:29.077321 9, 0xFFFF, sum = 0
8976 22:57:29.080259 10, 0xFFFF, sum = 0
8977 22:57:29.080695 11, 0xFFFF, sum = 0
8978 22:57:29.083843 12, 0xFFFF, sum = 0
8979 22:57:29.084418 13, 0xFFFF, sum = 0
8980 22:57:29.087260 14, 0x0, sum = 1
8981 22:57:29.087797 15, 0x0, sum = 2
8982 22:57:29.089517 16, 0x0, sum = 3
8983 22:57:29.089964 17, 0x0, sum = 4
8984 22:57:29.093298 best_step = 15
8985 22:57:29.093932
8986 22:57:29.094360 ==
8987 22:57:29.096452 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 22:57:29.100317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 22:57:29.100855 ==
8990 22:57:29.102988 RX Vref Scan: 0
8991 22:57:29.103412
8992 22:57:29.103750 RX Vref 0 -> 0, step: 1
8993 22:57:29.104121
8994 22:57:29.106720 RX Delay 19 -> 252, step: 4
8995 22:57:29.109917 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8996 22:57:29.116604 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8997 22:57:29.119738 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8998 22:57:29.123542 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8999 22:57:29.126268 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9000 22:57:29.130044 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9001 22:57:29.133243 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9002 22:57:29.139935 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9003 22:57:29.143476 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9004 22:57:29.146559 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9005 22:57:29.149662 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9006 22:57:29.152894 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9007 22:57:29.160234 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9008 22:57:29.163198 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9009 22:57:29.166718 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9010 22:57:29.169405 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9011 22:57:29.169874 ==
9012 22:57:29.172575 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 22:57:29.179653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 22:57:29.180282 ==
9015 22:57:29.180660 DQS Delay:
9016 22:57:29.182813 DQS0 = 0, DQS1 = 0
9017 22:57:29.183277 DQM Delay:
9018 22:57:29.186058 DQM0 = 134, DQM1 = 131
9019 22:57:29.186522 DQ Delay:
9020 22:57:29.189442 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9021 22:57:29.192803 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9022 22:57:29.196338 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9023 22:57:29.199575 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
9024 22:57:29.200022
9025 22:57:29.200360
9026 22:57:29.200669
9027 22:57:29.203008 [DramC_TX_OE_Calibration] TA2
9028 22:57:29.206734 Original DQ_B0 (3 6) =30, OEN = 27
9029 22:57:29.209596 Original DQ_B1 (3 6) =30, OEN = 27
9030 22:57:29.213462 24, 0x0, End_B0=24 End_B1=24
9031 22:57:29.213997 25, 0x0, End_B0=25 End_B1=25
9032 22:57:29.216321 26, 0x0, End_B0=26 End_B1=26
9033 22:57:29.219824 27, 0x0, End_B0=27 End_B1=27
9034 22:57:29.222878 28, 0x0, End_B0=28 End_B1=28
9035 22:57:29.226464 29, 0x0, End_B0=29 End_B1=29
9036 22:57:29.226991 30, 0x0, End_B0=30 End_B1=30
9037 22:57:29.229361 31, 0x4545, End_B0=30 End_B1=30
9038 22:57:29.232945 Byte0 end_step=30 best_step=27
9039 22:57:29.236258 Byte1 end_step=30 best_step=27
9040 22:57:29.239694 Byte0 TX OE(2T, 0.5T) = (3, 3)
9041 22:57:29.243223 Byte1 TX OE(2T, 0.5T) = (3, 3)
9042 22:57:29.243745
9043 22:57:29.244138
9044 22:57:29.249730 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9045 22:57:29.252625 CH1 RK1: MR19=303, MR18=250A
9046 22:57:29.260163 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
9047 22:57:29.262291 [RxdqsGatingPostProcess] freq 1600
9048 22:57:29.265898 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9049 22:57:29.269623 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 22:57:29.272614 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 22:57:29.275915 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 22:57:29.279248 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 22:57:29.282656 best DQS0 dly(2T, 0.5T) = (1, 1)
9054 22:57:29.286721 best DQS1 dly(2T, 0.5T) = (1, 1)
9055 22:57:29.289535 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9056 22:57:29.292356 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9057 22:57:29.295936 Pre-setting of DQS Precalculation
9058 22:57:29.299227 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9059 22:57:29.305716 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9060 22:57:29.315516 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9061 22:57:29.316058
9062 22:57:29.316508
9063 22:57:29.318946 [Calibration Summary] 3200 Mbps
9064 22:57:29.319389 CH 0, Rank 0
9065 22:57:29.322639 SW Impedance : PASS
9066 22:57:29.323182 DUTY Scan : NO K
9067 22:57:29.326025 ZQ Calibration : PASS
9068 22:57:29.326530 Jitter Meter : NO K
9069 22:57:29.329041 CBT Training : PASS
9070 22:57:29.332096 Write leveling : PASS
9071 22:57:29.332539 RX DQS gating : PASS
9072 22:57:29.335432 RX DQ/DQS(RDDQC) : PASS
9073 22:57:29.339385 TX DQ/DQS : PASS
9074 22:57:29.339899 RX DATLAT : PASS
9075 22:57:29.342141 RX DQ/DQS(Engine): PASS
9076 22:57:29.345544 TX OE : PASS
9077 22:57:29.345974 All Pass.
9078 22:57:29.346314
9079 22:57:29.346628 CH 0, Rank 1
9080 22:57:29.348819 SW Impedance : PASS
9081 22:57:29.352212 DUTY Scan : NO K
9082 22:57:29.352639 ZQ Calibration : PASS
9083 22:57:29.355507 Jitter Meter : NO K
9084 22:57:29.359017 CBT Training : PASS
9085 22:57:29.359567 Write leveling : PASS
9086 22:57:29.361988 RX DQS gating : PASS
9087 22:57:29.365850 RX DQ/DQS(RDDQC) : PASS
9088 22:57:29.366269 TX DQ/DQS : PASS
9089 22:57:29.368979 RX DATLAT : PASS
9090 22:57:29.369521 RX DQ/DQS(Engine): PASS
9091 22:57:29.372317 TX OE : PASS
9092 22:57:29.372747 All Pass.
9093 22:57:29.373090
9094 22:57:29.375379 CH 1, Rank 0
9095 22:57:29.375805 SW Impedance : PASS
9096 22:57:29.379031 DUTY Scan : NO K
9097 22:57:29.382182 ZQ Calibration : PASS
9098 22:57:29.382612 Jitter Meter : NO K
9099 22:57:29.385675 CBT Training : PASS
9100 22:57:29.388845 Write leveling : PASS
9101 22:57:29.389273 RX DQS gating : PASS
9102 22:57:29.392277 RX DQ/DQS(RDDQC) : PASS
9103 22:57:29.395373 TX DQ/DQS : PASS
9104 22:57:29.395804 RX DATLAT : PASS
9105 22:57:29.398712 RX DQ/DQS(Engine): PASS
9106 22:57:29.402465 TX OE : PASS
9107 22:57:29.403022 All Pass.
9108 22:57:29.403365
9109 22:57:29.403678 CH 1, Rank 1
9110 22:57:29.405511 SW Impedance : PASS
9111 22:57:29.408906 DUTY Scan : NO K
9112 22:57:29.409328 ZQ Calibration : PASS
9113 22:57:29.412237 Jitter Meter : NO K
9114 22:57:29.415509 CBT Training : PASS
9115 22:57:29.416083 Write leveling : PASS
9116 22:57:29.418455 RX DQS gating : PASS
9117 22:57:29.422121 RX DQ/DQS(RDDQC) : PASS
9118 22:57:29.422556 TX DQ/DQS : PASS
9119 22:57:29.425052 RX DATLAT : PASS
9120 22:57:29.425474 RX DQ/DQS(Engine): PASS
9121 22:57:29.428635 TX OE : PASS
9122 22:57:29.429054 All Pass.
9123 22:57:29.429388
9124 22:57:29.432033 DramC Write-DBI on
9125 22:57:29.434908 PER_BANK_REFRESH: Hybrid Mode
9126 22:57:29.435335 TX_TRACKING: ON
9127 22:57:29.445193 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9128 22:57:29.451930 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9129 22:57:29.461512 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9130 22:57:29.465725 [FAST_K] Save calibration result to emmc
9131 22:57:29.466252 sync common calibartion params.
9132 22:57:29.468076 sync cbt_mode0:1, 1:1
9133 22:57:29.472359 dram_init: ddr_geometry: 2
9134 22:57:29.475027 dram_init: ddr_geometry: 2
9135 22:57:29.475590 dram_init: ddr_geometry: 2
9136 22:57:29.478127 0:dram_rank_size:100000000
9137 22:57:29.481592 1:dram_rank_size:100000000
9138 22:57:29.485381 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9139 22:57:29.487935 DFS_SHUFFLE_HW_MODE: ON
9140 22:57:29.492321 dramc_set_vcore_voltage set vcore to 725000
9141 22:57:29.495181 Read voltage for 1600, 0
9142 22:57:29.495893 Vio18 = 0
9143 22:57:29.498532 Vcore = 725000
9144 22:57:29.499096 Vdram = 0
9145 22:57:29.499472 Vddq = 0
9146 22:57:29.499819 Vmddr = 0
9147 22:57:29.501888 switch to 3200 Mbps bootup
9148 22:57:29.505046 [DramcRunTimeConfig]
9149 22:57:29.505612 PHYPLL
9150 22:57:29.508467 DPM_CONTROL_AFTERK: ON
9151 22:57:29.508936 PER_BANK_REFRESH: ON
9152 22:57:29.511443 REFRESH_OVERHEAD_REDUCTION: ON
9153 22:57:29.514869 CMD_PICG_NEW_MODE: OFF
9154 22:57:29.515434 XRTWTW_NEW_MODE: ON
9155 22:57:29.517949 XRTRTR_NEW_MODE: ON
9156 22:57:29.518417 TX_TRACKING: ON
9157 22:57:29.521379 RDSEL_TRACKING: OFF
9158 22:57:29.524587 DQS Precalculation for DVFS: ON
9159 22:57:29.525060 RX_TRACKING: OFF
9160 22:57:29.528005 HW_GATING DBG: ON
9161 22:57:29.528601 ZQCS_ENABLE_LP4: ON
9162 22:57:29.531136 RX_PICG_NEW_MODE: ON
9163 22:57:29.531604 TX_PICG_NEW_MODE: ON
9164 22:57:29.534749 ENABLE_RX_DCM_DPHY: ON
9165 22:57:29.538066 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9166 22:57:29.540900 DUMMY_READ_FOR_TRACKING: OFF
9167 22:57:29.541372 !!! SPM_CONTROL_AFTERK: OFF
9168 22:57:29.544912 !!! SPM could not control APHY
9169 22:57:29.547748 IMPEDANCE_TRACKING: ON
9170 22:57:29.548251 TEMP_SENSOR: ON
9171 22:57:29.551375 HW_SAVE_FOR_SR: OFF
9172 22:57:29.554578 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9173 22:57:29.557576 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9174 22:57:29.558003 Read ODT Tracking: ON
9175 22:57:29.561098 Refresh Rate DeBounce: ON
9176 22:57:29.564088 DFS_NO_QUEUE_FLUSH: ON
9177 22:57:29.568048 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9178 22:57:29.568582 ENABLE_DFS_RUNTIME_MRW: OFF
9179 22:57:29.571338 DDR_RESERVE_NEW_MODE: ON
9180 22:57:29.574032 MR_CBT_SWITCH_FREQ: ON
9181 22:57:29.574461 =========================
9182 22:57:29.594202 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9183 22:57:29.597566 dram_init: ddr_geometry: 2
9184 22:57:29.616386 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9185 22:57:29.619277 dram_init: dram init end (result: 0)
9186 22:57:29.625791 DRAM-K: Full calibration passed in 24409 msecs
9187 22:57:29.629134 MRC: failed to locate region type 0.
9188 22:57:29.629711 DRAM rank0 size:0x100000000,
9189 22:57:29.632527 DRAM rank1 size=0x100000000
9190 22:57:29.642517 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9191 22:57:29.649149 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9192 22:57:29.656158 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9193 22:57:29.662748 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9194 22:57:29.665806 DRAM rank0 size:0x100000000,
9195 22:57:29.668843 DRAM rank1 size=0x100000000
9196 22:57:29.669313 CBMEM:
9197 22:57:29.672286 IMD: root @ 0xfffff000 254 entries.
9198 22:57:29.676193 IMD: root @ 0xffffec00 62 entries.
9199 22:57:29.678722 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9200 22:57:29.685347 WARNING: RO_VPD is uninitialized or empty.
9201 22:57:29.688785 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9202 22:57:29.696044 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9203 22:57:29.708601 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9204 22:57:29.720266 BS: romstage times (exec / console): total (unknown) / 23949 ms
9205 22:57:29.720846
9206 22:57:29.721217
9207 22:57:29.730580 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9208 22:57:29.733653 ARM64: Exception handlers installed.
9209 22:57:29.736677 ARM64: Testing exception
9210 22:57:29.740742 ARM64: Done test exception
9211 22:57:29.741337 Enumerating buses...
9212 22:57:29.743509 Show all devs... Before device enumeration.
9213 22:57:29.746775 Root Device: enabled 1
9214 22:57:29.750278 CPU_CLUSTER: 0: enabled 1
9215 22:57:29.750759 CPU: 00: enabled 1
9216 22:57:29.753624 Compare with tree...
9217 22:57:29.754127 Root Device: enabled 1
9218 22:57:29.756643 CPU_CLUSTER: 0: enabled 1
9219 22:57:29.759895 CPU: 00: enabled 1
9220 22:57:29.760360 Root Device scanning...
9221 22:57:29.763471 scan_static_bus for Root Device
9222 22:57:29.766602 CPU_CLUSTER: 0 enabled
9223 22:57:29.770076 scan_static_bus for Root Device done
9224 22:57:29.773126 scan_bus: bus Root Device finished in 8 msecs
9225 22:57:29.773563 done
9226 22:57:29.780129 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9227 22:57:29.783647 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9228 22:57:29.790142 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9229 22:57:29.793596 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9230 22:57:29.796740 Allocating resources...
9231 22:57:29.800093 Reading resources...
9232 22:57:29.803387 Root Device read_resources bus 0 link: 0
9233 22:57:29.803913 DRAM rank0 size:0x100000000,
9234 22:57:29.806746 DRAM rank1 size=0x100000000
9235 22:57:29.809600 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9236 22:57:29.813286 CPU: 00 missing read_resources
9237 22:57:29.819648 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9238 22:57:29.822708 Root Device read_resources bus 0 link: 0 done
9239 22:57:29.823136 Done reading resources.
9240 22:57:29.829715 Show resources in subtree (Root Device)...After reading.
9241 22:57:29.832954 Root Device child on link 0 CPU_CLUSTER: 0
9242 22:57:29.836066 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 22:57:29.846315 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 22:57:29.846836 CPU: 00
9245 22:57:29.849818 Root Device assign_resources, bus 0 link: 0
9246 22:57:29.852967 CPU_CLUSTER: 0 missing set_resources
9247 22:57:29.859784 Root Device assign_resources, bus 0 link: 0 done
9248 22:57:29.860244 Done setting resources.
9249 22:57:29.866060 Show resources in subtree (Root Device)...After assigning values.
9250 22:57:29.869194 Root Device child on link 0 CPU_CLUSTER: 0
9251 22:57:29.872938 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 22:57:29.882353 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 22:57:29.882804 CPU: 00
9254 22:57:29.885546 Done allocating resources.
9255 22:57:29.889057 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9256 22:57:29.892304 Enabling resources...
9257 22:57:29.892733 done.
9258 22:57:29.898896 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9259 22:57:29.899317 Initializing devices...
9260 22:57:29.902434 Root Device init
9261 22:57:29.902850 init hardware done!
9262 22:57:29.905626 0x00000018: ctrlr->caps
9263 22:57:29.909359 52.000 MHz: ctrlr->f_max
9264 22:57:29.909785 0.400 MHz: ctrlr->f_min
9265 22:57:29.912788 0x40ff8080: ctrlr->voltages
9266 22:57:29.915626 sclk: 390625
9267 22:57:29.916184 Bus Width = 1
9268 22:57:29.916531 sclk: 390625
9269 22:57:29.919521 Bus Width = 1
9270 22:57:29.920032 Early init status = 3
9271 22:57:29.926081 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9272 22:57:29.929140 in-header: 03 fc 00 00 01 00 00 00
9273 22:57:29.929561 in-data: 00
9274 22:57:29.935788 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9275 22:57:29.939346 in-header: 03 fd 00 00 00 00 00 00
9276 22:57:29.943656 in-data:
9277 22:57:29.946297 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 22:57:29.950874 in-header: 03 fc 00 00 01 00 00 00
9279 22:57:29.953650 in-data: 00
9280 22:57:29.957323 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9281 22:57:29.962712 in-header: 03 fd 00 00 00 00 00 00
9282 22:57:29.966305 in-data:
9283 22:57:29.969071 [SSUSB] Setting up USB HOST controller...
9284 22:57:29.972812 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9285 22:57:29.976156 [SSUSB] phy power-on done.
9286 22:57:29.979008 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9287 22:57:29.985674 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9288 22:57:29.989109 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9289 22:57:29.996326 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9290 22:57:30.002558 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9291 22:57:30.009568 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9292 22:57:30.016450 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9293 22:57:30.022852 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9294 22:57:30.026254 SPM: binary array size = 0x9dc
9295 22:57:30.029453 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9296 22:57:30.035906 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9297 22:57:30.042644 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9298 22:57:30.045929 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9299 22:57:30.052545 configure_display: Starting display init
9300 22:57:30.086450 anx7625_power_on_init: Init interface.
9301 22:57:30.089390 anx7625_disable_pd_protocol: Disabled PD feature.
9302 22:57:30.093092 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9303 22:57:30.120979 anx7625_start_dp_work: Secure OCM version=00
9304 22:57:30.123622 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9305 22:57:30.138944 sp_tx_get_edid_block: EDID Block = 1
9306 22:57:30.241404 Extracted contents:
9307 22:57:30.244509 header: 00 ff ff ff ff ff ff 00
9308 22:57:30.247896 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9309 22:57:30.251317 version: 01 04
9310 22:57:30.254529 basic params: 95 1f 11 78 0a
9311 22:57:30.258108 chroma info: 76 90 94 55 54 90 27 21 50 54
9312 22:57:30.261098 established: 00 00 00
9313 22:57:30.267725 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9314 22:57:30.270928 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9315 22:57:30.277364 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9316 22:57:30.283703 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9317 22:57:30.290956 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9318 22:57:30.294152 extensions: 00
9319 22:57:30.294587 checksum: fb
9320 22:57:30.294945
9321 22:57:30.297373 Manufacturer: IVO Model 57d Serial Number 0
9322 22:57:30.300417 Made week 0 of 2020
9323 22:57:30.300847 EDID version: 1.4
9324 22:57:30.304351 Digital display
9325 22:57:30.307057 6 bits per primary color channel
9326 22:57:30.307494 DisplayPort interface
9327 22:57:30.310910 Maximum image size: 31 cm x 17 cm
9328 22:57:30.314231 Gamma: 220%
9329 22:57:30.314750 Check DPMS levels
9330 22:57:30.317864 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9331 22:57:30.324324 First detailed timing is preferred timing
9332 22:57:30.324753 Established timings supported:
9333 22:57:30.327374 Standard timings supported:
9334 22:57:30.330425 Detailed timings
9335 22:57:30.333612 Hex of detail: 383680a07038204018303c0035ae10000019
9336 22:57:30.336659 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9337 22:57:30.343849 0780 0798 07c8 0820 hborder 0
9338 22:57:30.347567 0438 043b 0447 0458 vborder 0
9339 22:57:30.350001 -hsync -vsync
9340 22:57:30.350429 Did detailed timing
9341 22:57:30.357169 Hex of detail: 000000000000000000000000000000000000
9342 22:57:30.359952 Manufacturer-specified data, tag 0
9343 22:57:30.363805 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9344 22:57:30.367113 ASCII string: InfoVision
9345 22:57:30.370436 Hex of detail: 000000fe00523134304e574635205248200a
9346 22:57:30.373873 ASCII string: R140NWF5 RH
9347 22:57:30.374332 Checksum
9348 22:57:30.377010 Checksum: 0xfb (valid)
9349 22:57:30.380107 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9350 22:57:30.383162 DSI data_rate: 832800000 bps
9351 22:57:30.390589 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9352 22:57:30.393135 anx7625_parse_edid: pixelclock(138800).
9353 22:57:30.396692 hactive(1920), hsync(48), hfp(24), hbp(88)
9354 22:57:30.399893 vactive(1080), vsync(12), vfp(3), vbp(17)
9355 22:57:30.403400 anx7625_dsi_config: config dsi.
9356 22:57:30.409789 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9357 22:57:30.422940 anx7625_dsi_config: success to config DSI
9358 22:57:30.426780 anx7625_dp_start: MIPI phy setup OK.
9359 22:57:30.429842 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9360 22:57:30.433268 mtk_ddp_mode_set invalid vrefresh 60
9361 22:57:30.436709 main_disp_path_setup
9362 22:57:30.437130 ovl_layer_smi_id_en
9363 22:57:30.439688 ovl_layer_smi_id_en
9364 22:57:30.440146 ccorr_config
9365 22:57:30.440484 aal_config
9366 22:57:30.443012 gamma_config
9367 22:57:30.443461 postmask_config
9368 22:57:30.446490 dither_config
9369 22:57:30.449561 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9370 22:57:30.456576 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9371 22:57:30.460099 Root Device init finished in 554 msecs
9372 22:57:30.460526 CPU_CLUSTER: 0 init
9373 22:57:30.470021 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9374 22:57:30.473151 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9375 22:57:30.476618 APU_MBOX 0x190000b0 = 0x10001
9376 22:57:30.479903 APU_MBOX 0x190001b0 = 0x10001
9377 22:57:30.482569 APU_MBOX 0x190005b0 = 0x10001
9378 22:57:30.486373 APU_MBOX 0x190006b0 = 0x10001
9379 22:57:30.489695 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9380 22:57:30.502546 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9381 22:57:30.514572 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9382 22:57:30.521050 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9383 22:57:30.532322 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9384 22:57:30.541745 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9385 22:57:30.545229 CPU_CLUSTER: 0 init finished in 81 msecs
9386 22:57:30.548986 Devices initialized
9387 22:57:30.551523 Show all devs... After init.
9388 22:57:30.551943 Root Device: enabled 1
9389 22:57:30.555385 CPU_CLUSTER: 0: enabled 1
9390 22:57:30.558243 CPU: 00: enabled 1
9391 22:57:30.561410 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9392 22:57:30.565464 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9393 22:57:30.568381 ELOG: NV offset 0x57f000 size 0x1000
9394 22:57:30.574889 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9395 22:57:30.581651 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9396 22:57:30.585236 ELOG: Event(17) added with size 13 at 2024-05-07 22:53:07 UTC
9397 22:57:30.588301 out: cmd=0x121: 03 db 21 01 00 00 00 00
9398 22:57:30.591855 in-header: 03 10 00 00 2c 00 00 00
9399 22:57:30.605292 in-data: 4f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9400 22:57:30.612197 ELOG: Event(A1) added with size 10 at 2024-05-07 22:53:07 UTC
9401 22:57:30.619086 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9402 22:57:30.625813 ELOG: Event(A0) added with size 9 at 2024-05-07 22:53:07 UTC
9403 22:57:30.628431 elog_add_boot_reason: Logged dev mode boot
9404 22:57:30.631707 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9405 22:57:30.635042 Finalize devices...
9406 22:57:30.635562 Devices finalized
9407 22:57:30.641883 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9408 22:57:30.645374 Writing coreboot table at 0xffe64000
9409 22:57:30.648313 0. 000000000010a000-0000000000113fff: RAMSTAGE
9410 22:57:30.652237 1. 0000000040000000-00000000400fffff: RAM
9411 22:57:30.655776 2. 0000000040100000-000000004032afff: RAMSTAGE
9412 22:57:30.661920 3. 000000004032b000-00000000545fffff: RAM
9413 22:57:30.664714 4. 0000000054600000-000000005465ffff: BL31
9414 22:57:30.668726 5. 0000000054660000-00000000ffe63fff: RAM
9415 22:57:30.675467 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9416 22:57:30.678488 7. 0000000100000000-000000023fffffff: RAM
9417 22:57:30.678979 Passing 5 GPIOs to payload:
9418 22:57:30.684885 NAME | PORT | POLARITY | VALUE
9419 22:57:30.687823 EC in RW | 0x000000aa | low | undefined
9420 22:57:30.694782 EC interrupt | 0x00000005 | low | undefined
9421 22:57:30.698147 TPM interrupt | 0x000000ab | high | undefined
9422 22:57:30.701708 SD card detect | 0x00000011 | high | undefined
9423 22:57:30.708243 speaker enable | 0x00000093 | high | undefined
9424 22:57:30.711350 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9425 22:57:30.714463 in-header: 03 f9 00 00 02 00 00 00
9426 22:57:30.714959 in-data: 02 00
9427 22:57:30.718287 ADC[4]: Raw value=904357 ID=7
9428 22:57:30.721462 ADC[3]: Raw value=213810 ID=1
9429 22:57:30.724512 RAM Code: 0x71
9430 22:57:30.724935 ADC[6]: Raw value=75701 ID=0
9431 22:57:30.728098 ADC[5]: Raw value=213072 ID=1
9432 22:57:30.731076 SKU Code: 0x1
9433 22:57:30.734789 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 27a6
9434 22:57:30.737778 coreboot table: 964 bytes.
9435 22:57:30.741269 IMD ROOT 0. 0xfffff000 0x00001000
9436 22:57:30.744549 IMD SMALL 1. 0xffffe000 0x00001000
9437 22:57:30.747764 RO MCACHE 2. 0xffffc000 0x00001104
9438 22:57:30.751295 CONSOLE 3. 0xfff7c000 0x00080000
9439 22:57:30.754268 FMAP 4. 0xfff7b000 0x00000452
9440 22:57:30.757985 TIME STAMP 5. 0xfff7a000 0x00000910
9441 22:57:30.761321 VBOOT WORK 6. 0xfff66000 0x00014000
9442 22:57:30.764077 RAMOOPS 7. 0xffe66000 0x00100000
9443 22:57:30.767402 COREBOOT 8. 0xffe64000 0x00002000
9444 22:57:30.767830 IMD small region:
9445 22:57:30.770684 IMD ROOT 0. 0xffffec00 0x00000400
9446 22:57:30.774064 VPD 1. 0xffffeb80 0x0000006c
9447 22:57:30.780595 MMC STATUS 2. 0xffffeb60 0x00000004
9448 22:57:30.784063 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9449 22:57:30.787753 Probing TPM: done!
9450 22:57:30.791649 Connected to device vid:did:rid of 1ae0:0028:00
9451 22:57:30.801200 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9452 22:57:30.804267 Initialized TPM device CR50 revision 0
9453 22:57:30.808197 Checking cr50 for pending updates
9454 22:57:30.811827 Reading cr50 TPM mode
9455 22:57:30.820343 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9456 22:57:30.827064 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9457 22:57:30.867124 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9458 22:57:30.870800 Checking segment from ROM address 0x40100000
9459 22:57:30.874261 Checking segment from ROM address 0x4010001c
9460 22:57:30.880823 Loading segment from ROM address 0x40100000
9461 22:57:30.881293 code (compression=0)
9462 22:57:30.887627 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9463 22:57:30.897210 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9464 22:57:30.897950 it's not compressed!
9465 22:57:30.904275 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9466 22:57:30.907337 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9467 22:57:30.927156 Loading segment from ROM address 0x4010001c
9468 22:57:30.927588 Entry Point 0x80000000
9469 22:57:30.931158 Loaded segments
9470 22:57:30.934468 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9471 22:57:30.940993 Jumping to boot code at 0x80000000(0xffe64000)
9472 22:57:30.947626 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9473 22:57:30.954055 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9474 22:57:30.961910 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9475 22:57:30.965046 Checking segment from ROM address 0x40100000
9476 22:57:30.968665 Checking segment from ROM address 0x4010001c
9477 22:57:30.975741 Loading segment from ROM address 0x40100000
9478 22:57:30.976334 code (compression=1)
9479 22:57:30.981754 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9480 22:57:30.991901 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9481 22:57:30.992454 using LZMA
9482 22:57:31.000328 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9483 22:57:31.006669 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9484 22:57:31.010706 Loading segment from ROM address 0x4010001c
9485 22:57:31.011200 Entry Point 0x54601000
9486 22:57:31.014057 Loaded segments
9487 22:57:31.017318 NOTICE: MT8192 bl31_setup
9488 22:57:31.023813 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9489 22:57:31.027017 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9490 22:57:31.030948 WARNING: region 0:
9491 22:57:31.034168 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 22:57:31.034656 WARNING: region 1:
9493 22:57:31.040819 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9494 22:57:31.044116 WARNING: region 2:
9495 22:57:31.047611 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9496 22:57:31.050573 WARNING: region 3:
9497 22:57:31.053900 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9498 22:57:31.057029 WARNING: region 4:
9499 22:57:31.063897 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 22:57:31.064444 WARNING: region 5:
9501 22:57:31.067208 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 22:57:31.070921 WARNING: region 6:
9503 22:57:31.073712 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 22:57:31.077440 WARNING: region 7:
9505 22:57:31.080450 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 22:57:31.087461 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9507 22:57:31.090674 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9508 22:57:31.093894 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9509 22:57:31.100457 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9510 22:57:31.103784 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9511 22:57:31.107070 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9512 22:57:31.114242 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9513 22:57:31.117616 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9514 22:57:31.123909 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9515 22:57:31.127334 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9516 22:57:31.130815 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9517 22:57:31.137597 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9518 22:57:31.140265 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9519 22:57:31.143730 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9520 22:57:31.150887 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9521 22:57:31.154312 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9522 22:57:31.157600 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9523 22:57:31.164208 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9524 22:57:31.167269 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9525 22:57:31.174267 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9526 22:57:31.177493 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9527 22:57:31.180638 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9528 22:57:31.187319 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9529 22:57:31.190774 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9530 22:57:31.196987 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9531 22:57:31.200866 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9532 22:57:31.203925 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9533 22:57:31.210850 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9534 22:57:31.214008 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9535 22:57:31.217706 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9536 22:57:31.223883 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9537 22:57:31.227058 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9538 22:57:31.233710 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9539 22:57:31.237327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9540 22:57:31.240314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9541 22:57:31.243917 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9542 22:57:31.246978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9543 22:57:31.253715 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9544 22:57:31.257766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9545 22:57:31.260608 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9546 22:57:31.263880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9547 22:57:31.270533 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9548 22:57:31.273927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9549 22:57:31.277784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9550 22:57:31.281076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9551 22:57:31.287518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9552 22:57:31.291246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9553 22:57:31.294068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9554 22:57:31.300689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9555 22:57:31.303851 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9556 22:57:31.310374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9557 22:57:31.313997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9558 22:57:31.317167 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9559 22:57:31.323947 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9560 22:57:31.327514 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9561 22:57:31.333748 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9562 22:57:31.337517 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9563 22:57:31.340582 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9564 22:57:31.347488 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9565 22:57:31.350637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9566 22:57:31.357451 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9567 22:57:31.361123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9568 22:57:31.367483 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9569 22:57:31.370848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9570 22:57:31.377519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9571 22:57:31.380625 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9572 22:57:31.383869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9573 22:57:31.390751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9574 22:57:31.393984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9575 22:57:31.400681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9576 22:57:31.403868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9577 22:57:31.411313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9578 22:57:31.414508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9579 22:57:31.417508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9580 22:57:31.423940 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9581 22:57:31.427798 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9582 22:57:31.433979 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9583 22:57:31.437780 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9584 22:57:31.444370 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9585 22:57:31.448100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9586 22:57:31.451254 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9587 22:57:31.458054 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9588 22:57:31.461376 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9589 22:57:31.467056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9590 22:57:31.470954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9591 22:57:31.477347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9592 22:57:31.480574 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9593 22:57:31.484253 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9594 22:57:31.490704 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9595 22:57:31.494351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9596 22:57:31.500719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9597 22:57:31.504129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9598 22:57:31.510913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9599 22:57:31.514980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9600 22:57:31.517615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9601 22:57:31.524760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9602 22:57:31.528030 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9603 22:57:31.531525 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9604 22:57:31.537678 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9605 22:57:31.541151 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9606 22:57:31.544792 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9607 22:57:31.551298 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9608 22:57:31.554461 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9609 22:57:31.557674 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9610 22:57:31.564653 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9611 22:57:31.568098 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9612 22:57:31.571569 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9613 22:57:31.577719 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9614 22:57:31.581014 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9615 22:57:31.587743 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9616 22:57:31.591344 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9617 22:57:31.594458 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9618 22:57:31.601444 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9619 22:57:31.604407 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9620 22:57:31.611473 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9621 22:57:31.615304 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9622 22:57:31.617835 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9623 22:57:31.624968 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9624 22:57:31.628270 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9625 22:57:31.631507 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9626 22:57:31.634731 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9627 22:57:31.640876 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9628 22:57:31.644531 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9629 22:57:31.648028 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9630 22:57:31.650934 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9631 22:57:31.658382 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9632 22:57:31.661229 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9633 22:57:31.667887 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9634 22:57:31.671728 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9635 22:57:31.675162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9636 22:57:31.681556 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9637 22:57:31.685084 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9638 22:57:31.688076 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9639 22:57:31.694843 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9640 22:57:31.698394 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9641 22:57:31.705207 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9642 22:57:31.707777 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9643 22:57:31.712086 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9644 22:57:31.718476 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9645 22:57:31.721348 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9646 22:57:31.728031 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9647 22:57:31.731502 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9648 22:57:31.734728 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9649 22:57:31.740906 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9650 22:57:31.744547 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9651 22:57:31.748465 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9652 22:57:31.754356 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9653 22:57:31.758311 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9654 22:57:31.765426 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9655 22:57:31.768042 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9656 22:57:31.771295 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9657 22:57:31.777657 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9658 22:57:31.781060 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9659 22:57:31.787667 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9660 22:57:31.791255 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9661 22:57:31.794953 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9662 22:57:31.801155 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9663 22:57:31.804712 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9664 22:57:31.808383 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9665 22:57:31.815047 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9666 22:57:31.818174 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9667 22:57:31.825122 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9668 22:57:31.828447 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9669 22:57:31.831224 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9670 22:57:31.838315 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9671 22:57:31.841093 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9672 22:57:31.848528 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9673 22:57:31.851584 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9674 22:57:31.854603 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9675 22:57:31.861611 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9676 22:57:31.864794 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9677 22:57:31.871529 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9678 22:57:31.875015 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9679 22:57:31.877704 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9680 22:57:31.884738 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9681 22:57:31.888014 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9682 22:57:31.891183 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9683 22:57:31.897818 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9684 22:57:31.901875 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9685 22:57:31.908078 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9686 22:57:31.911598 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9687 22:57:31.914886 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9688 22:57:31.921510 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9689 22:57:31.924484 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9690 22:57:31.931498 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9691 22:57:31.934970 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9692 22:57:31.938337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9693 22:57:31.944878 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9694 22:57:31.948018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9695 22:57:31.954159 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9696 22:57:31.957752 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9697 22:57:31.961121 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9698 22:57:31.967741 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9699 22:57:31.971169 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9700 22:57:31.977839 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9701 22:57:31.980879 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9702 22:57:31.987707 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9703 22:57:31.990575 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9704 22:57:31.994319 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9705 22:57:32.000860 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9706 22:57:32.004047 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9707 22:57:32.010943 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9708 22:57:32.014139 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9709 22:57:32.018017 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9710 22:57:32.024456 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9711 22:57:32.027536 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9712 22:57:32.034118 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9713 22:57:32.037280 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9714 22:57:32.044141 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9715 22:57:32.047645 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9716 22:57:32.050964 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9717 22:57:32.057632 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9718 22:57:32.060900 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9719 22:57:32.067440 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9720 22:57:32.070483 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9721 22:57:32.073700 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9722 22:57:32.080703 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9723 22:57:32.084043 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9724 22:57:32.090830 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9725 22:57:32.094315 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9726 22:57:32.100950 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9727 22:57:32.103920 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9728 22:57:32.107319 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9729 22:57:32.113518 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9730 22:57:32.117221 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9731 22:57:32.123862 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9732 22:57:32.127426 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9733 22:57:32.130222 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9734 22:57:32.137312 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9735 22:57:32.140234 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9736 22:57:32.143680 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9737 22:57:32.146783 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9738 22:57:32.154315 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9739 22:57:32.156913 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9740 22:57:32.160080 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9741 22:57:32.166960 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9742 22:57:32.170198 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9743 22:57:32.176761 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9744 22:57:32.179983 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9745 22:57:32.183569 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9746 22:57:32.190214 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9747 22:57:32.193344 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9748 22:57:32.196564 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9749 22:57:32.203281 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9750 22:57:32.206921 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9751 22:57:32.210165 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9752 22:57:32.217046 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9753 22:57:32.220342 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9754 22:57:32.223787 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9755 22:57:32.229944 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9756 22:57:32.233297 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9757 22:57:32.240095 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9758 22:57:32.243303 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9759 22:57:32.246442 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9760 22:57:32.252987 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9761 22:57:32.256389 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9762 22:57:32.259816 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9763 22:57:32.266450 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9764 22:57:32.270064 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9765 22:57:32.273209 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9766 22:57:32.279604 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9767 22:57:32.283248 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9768 22:57:32.290204 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9769 22:57:32.293639 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9770 22:57:32.296789 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9771 22:57:32.303553 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9772 22:57:32.306868 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9773 22:57:32.309516 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9774 22:57:32.316744 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9775 22:57:32.319860 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9776 22:57:32.322989 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9777 22:57:32.326323 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9778 22:57:32.333174 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9779 22:57:32.336378 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9780 22:57:32.340218 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9781 22:57:32.342877 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9782 22:57:32.346861 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9783 22:57:32.353338 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9784 22:57:32.356281 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9785 22:57:32.360009 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9786 22:57:32.366520 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9787 22:57:32.369859 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9788 22:57:32.372944 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9789 22:57:32.379506 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9790 22:57:32.382824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9791 22:57:32.389309 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9792 22:57:32.392565 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9793 22:57:32.396012 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9794 22:57:32.402658 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9795 22:57:32.406229 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9796 22:57:32.412498 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9797 22:57:32.416205 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9798 22:57:32.419447 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9799 22:57:32.425611 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9800 22:57:32.429417 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9801 22:57:32.435860 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9802 22:57:32.439066 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9803 22:57:32.442692 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9804 22:57:32.449624 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9805 22:57:32.452902 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9806 22:57:32.459752 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9807 22:57:32.463027 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9808 22:57:32.465934 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9809 22:57:32.472653 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9810 22:57:32.476046 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9811 22:57:32.482489 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9812 22:57:32.485798 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9813 22:57:32.489157 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9814 22:57:32.495606 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9815 22:57:32.498833 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9816 22:57:32.505779 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9817 22:57:32.508648 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9818 22:57:32.515317 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9819 22:57:32.518862 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9820 22:57:32.522026 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9821 22:57:32.528938 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9822 22:57:32.532385 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9823 22:57:32.538735 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9824 22:57:32.541989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9825 22:57:32.545978 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9826 22:57:32.552142 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9827 22:57:32.555376 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9828 22:57:32.562576 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9829 22:57:32.565894 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9830 22:57:32.568855 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9831 22:57:32.575333 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9832 22:57:32.578575 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9833 22:57:32.585312 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9834 22:57:32.588300 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9835 22:57:32.592031 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9836 22:57:32.598020 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9837 22:57:32.602345 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9838 22:57:32.608962 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9839 22:57:32.611863 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9840 22:57:32.618801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9841 22:57:32.621353 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9842 22:57:32.625124 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9843 22:57:32.631867 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9844 22:57:32.635257 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9845 22:57:32.641530 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9846 22:57:32.644961 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9847 22:57:32.648100 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9848 22:57:32.655108 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9849 22:57:32.658354 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9850 22:57:32.664918 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9851 22:57:32.668471 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9852 22:57:32.671627 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9853 22:57:32.678593 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9854 22:57:32.682041 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9855 22:57:32.688406 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9856 22:57:32.692144 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9857 22:57:32.698566 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9858 22:57:32.701362 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9859 22:57:32.704761 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9860 22:57:32.711114 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9861 22:57:32.714825 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9862 22:57:32.721423 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9863 22:57:32.724748 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9864 22:57:32.728804 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9865 22:57:32.735010 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9866 22:57:32.738085 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9867 22:57:32.745016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9868 22:57:32.747925 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9869 22:57:32.754893 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9870 22:57:32.758185 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9871 22:57:32.761471 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9872 22:57:32.768218 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9873 22:57:32.771665 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9874 22:57:32.778182 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9875 22:57:32.781183 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9876 22:57:32.787797 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9877 22:57:32.791384 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9878 22:57:32.797509 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9879 22:57:32.801316 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9880 22:57:32.804699 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9881 22:57:32.811267 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9882 22:57:32.814752 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9883 22:57:32.821369 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9884 22:57:32.824624 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9885 22:57:32.831279 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9886 22:57:32.834094 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9887 22:57:32.837796 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9888 22:57:32.844215 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9889 22:57:32.847695 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9890 22:57:32.854433 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9891 22:57:32.857624 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9892 22:57:32.863850 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9893 22:57:32.867327 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9894 22:57:32.870293 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9895 22:57:32.877353 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9896 22:57:32.880212 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9897 22:57:32.886982 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9898 22:57:32.889974 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9899 22:57:32.897086 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9900 22:57:32.900539 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9901 22:57:32.903885 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9902 22:57:32.910300 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9903 22:57:32.913875 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9904 22:57:32.920233 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9905 22:57:32.923526 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9906 22:57:32.930375 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9907 22:57:32.933486 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9908 22:57:32.936757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9909 22:57:32.943771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9910 22:57:32.947333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9911 22:57:32.953678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9912 22:57:32.957185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9913 22:57:32.963626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9914 22:57:32.967071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9915 22:57:32.973639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9916 22:57:32.976889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9917 22:57:32.983152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9918 22:57:32.986778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9919 22:57:32.993399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9920 22:57:32.996375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9921 22:57:33.002921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9922 22:57:33.006539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9923 22:57:33.009648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9924 22:57:33.016252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9925 22:57:33.019917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9926 22:57:33.026655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9927 22:57:33.029817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9928 22:57:33.036640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9929 22:57:33.040027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9930 22:57:33.046915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9931 22:57:33.049805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9932 22:57:33.056643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9933 22:57:33.059706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9934 22:57:33.066282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9935 22:57:33.070154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9936 22:57:33.076669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9937 22:57:33.079994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9938 22:57:33.086563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9939 22:57:33.089760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9940 22:57:33.096280 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9941 22:57:33.096412 INFO: [APUAPC] vio 0
9942 22:57:33.103017 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9943 22:57:33.106957 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9944 22:57:33.109965 INFO: [APUAPC] D0_APC_0: 0x400510
9945 22:57:33.113144 INFO: [APUAPC] D0_APC_1: 0x0
9946 22:57:33.116168 INFO: [APUAPC] D0_APC_2: 0x1540
9947 22:57:33.119749 INFO: [APUAPC] D0_APC_3: 0x0
9948 22:57:33.123261 INFO: [APUAPC] D1_APC_0: 0xffffffff
9949 22:57:33.126142 INFO: [APUAPC] D1_APC_1: 0xffffffff
9950 22:57:33.130126 INFO: [APUAPC] D1_APC_2: 0x3fffff
9951 22:57:33.132794 INFO: [APUAPC] D1_APC_3: 0x0
9952 22:57:33.136904 INFO: [APUAPC] D2_APC_0: 0xffffffff
9953 22:57:33.139413 INFO: [APUAPC] D2_APC_1: 0xffffffff
9954 22:57:33.143343 INFO: [APUAPC] D2_APC_2: 0x3fffff
9955 22:57:33.146060 INFO: [APUAPC] D2_APC_3: 0x0
9956 22:57:33.150053 INFO: [APUAPC] D3_APC_0: 0xffffffff
9957 22:57:33.153257 INFO: [APUAPC] D3_APC_1: 0xffffffff
9958 22:57:33.156789 INFO: [APUAPC] D3_APC_2: 0x3fffff
9959 22:57:33.160094 INFO: [APUAPC] D3_APC_3: 0x0
9960 22:57:33.163045 INFO: [APUAPC] D4_APC_0: 0xffffffff
9961 22:57:33.166320 INFO: [APUAPC] D4_APC_1: 0xffffffff
9962 22:57:33.169555 INFO: [APUAPC] D4_APC_2: 0x3fffff
9963 22:57:33.169640 INFO: [APUAPC] D4_APC_3: 0x0
9964 22:57:33.173024 INFO: [APUAPC] D5_APC_0: 0xffffffff
9965 22:57:33.179555 INFO: [APUAPC] D5_APC_1: 0xffffffff
9966 22:57:33.182918 INFO: [APUAPC] D5_APC_2: 0x3fffff
9967 22:57:33.183017 INFO: [APUAPC] D5_APC_3: 0x0
9968 22:57:33.186449 INFO: [APUAPC] D6_APC_0: 0xffffffff
9969 22:57:33.189692 INFO: [APUAPC] D6_APC_1: 0xffffffff
9970 22:57:33.193029 INFO: [APUAPC] D6_APC_2: 0x3fffff
9971 22:57:33.196224 INFO: [APUAPC] D6_APC_3: 0x0
9972 22:57:33.199369 INFO: [APUAPC] D7_APC_0: 0xffffffff
9973 22:57:33.202858 INFO: [APUAPC] D7_APC_1: 0xffffffff
9974 22:57:33.206057 INFO: [APUAPC] D7_APC_2: 0x3fffff
9975 22:57:33.209268 INFO: [APUAPC] D7_APC_3: 0x0
9976 22:57:33.212492 INFO: [APUAPC] D8_APC_0: 0xffffffff
9977 22:57:33.215839 INFO: [APUAPC] D8_APC_1: 0xffffffff
9978 22:57:33.219868 INFO: [APUAPC] D8_APC_2: 0x3fffff
9979 22:57:33.223034 INFO: [APUAPC] D8_APC_3: 0x0
9980 22:57:33.226126 INFO: [APUAPC] D9_APC_0: 0xffffffff
9981 22:57:33.229293 INFO: [APUAPC] D9_APC_1: 0xffffffff
9982 22:57:33.233131 INFO: [APUAPC] D9_APC_2: 0x3fffff
9983 22:57:33.236205 INFO: [APUAPC] D9_APC_3: 0x0
9984 22:57:33.238948 INFO: [APUAPC] D10_APC_0: 0xffffffff
9985 22:57:33.242352 INFO: [APUAPC] D10_APC_1: 0xffffffff
9986 22:57:33.246244 INFO: [APUAPC] D10_APC_2: 0x3fffff
9987 22:57:33.249689 INFO: [APUAPC] D10_APC_3: 0x0
9988 22:57:33.253016 INFO: [APUAPC] D11_APC_0: 0xffffffff
9989 22:57:33.255676 INFO: [APUAPC] D11_APC_1: 0xffffffff
9990 22:57:33.258905 INFO: [APUAPC] D11_APC_2: 0x3fffff
9991 22:57:33.262807 INFO: [APUAPC] D11_APC_3: 0x0
9992 22:57:33.266162 INFO: [APUAPC] D12_APC_0: 0xffffffff
9993 22:57:33.269521 INFO: [APUAPC] D12_APC_1: 0xffffffff
9994 22:57:33.272844 INFO: [APUAPC] D12_APC_2: 0x3fffff
9995 22:57:33.276219 INFO: [APUAPC] D12_APC_3: 0x0
9996 22:57:33.279451 INFO: [APUAPC] D13_APC_0: 0xffffffff
9997 22:57:33.282676 INFO: [APUAPC] D13_APC_1: 0xffffffff
9998 22:57:33.285920 INFO: [APUAPC] D13_APC_2: 0x3fffff
9999 22:57:33.289270 INFO: [APUAPC] D13_APC_3: 0x0
10000 22:57:33.292479 INFO: [APUAPC] D14_APC_0: 0xffffffff
10001 22:57:33.295966 INFO: [APUAPC] D14_APC_1: 0xffffffff
10002 22:57:33.298780 INFO: [APUAPC] D14_APC_2: 0x3fffff
10003 22:57:33.302296 INFO: [APUAPC] D14_APC_3: 0x0
10004 22:57:33.305660 INFO: [APUAPC] D15_APC_0: 0xffffffff
10005 22:57:33.309249 INFO: [APUAPC] D15_APC_1: 0xffffffff
10006 22:57:33.312308 INFO: [APUAPC] D15_APC_2: 0x3fffff
10007 22:57:33.315816 INFO: [APUAPC] D15_APC_3: 0x0
10008 22:57:33.318969 INFO: [APUAPC] APC_CON: 0x4
10009 22:57:33.322324 INFO: [NOCDAPC] D0_APC_0: 0x0
10010 22:57:33.325765 INFO: [NOCDAPC] D0_APC_1: 0x0
10011 22:57:33.329014 INFO: [NOCDAPC] D1_APC_0: 0x0
10012 22:57:33.332797 INFO: [NOCDAPC] D1_APC_1: 0xfff
10013 22:57:33.332881 INFO: [NOCDAPC] D2_APC_0: 0x0
10014 22:57:33.336277 INFO: [NOCDAPC] D2_APC_1: 0xfff
10015 22:57:33.339324 INFO: [NOCDAPC] D3_APC_0: 0x0
10016 22:57:33.342611 INFO: [NOCDAPC] D3_APC_1: 0xfff
10017 22:57:33.345770 INFO: [NOCDAPC] D4_APC_0: 0x0
10018 22:57:33.348781 INFO: [NOCDAPC] D4_APC_1: 0xfff
10019 22:57:33.352373 INFO: [NOCDAPC] D5_APC_0: 0x0
10020 22:57:33.355484 INFO: [NOCDAPC] D5_APC_1: 0xfff
10021 22:57:33.359021 INFO: [NOCDAPC] D6_APC_0: 0x0
10022 22:57:33.361852 INFO: [NOCDAPC] D6_APC_1: 0xfff
10023 22:57:33.365119 INFO: [NOCDAPC] D7_APC_0: 0x0
10024 22:57:33.368546 INFO: [NOCDAPC] D7_APC_1: 0xfff
10025 22:57:33.368629 INFO: [NOCDAPC] D8_APC_0: 0x0
10026 22:57:33.371984 INFO: [NOCDAPC] D8_APC_1: 0xfff
10027 22:57:33.375249 INFO: [NOCDAPC] D9_APC_0: 0x0
10028 22:57:33.378543 INFO: [NOCDAPC] D9_APC_1: 0xfff
10029 22:57:33.381892 INFO: [NOCDAPC] D10_APC_0: 0x0
10030 22:57:33.385058 INFO: [NOCDAPC] D10_APC_1: 0xfff
10031 22:57:33.388346 INFO: [NOCDAPC] D11_APC_0: 0x0
10032 22:57:33.391797 INFO: [NOCDAPC] D11_APC_1: 0xfff
10033 22:57:33.395192 INFO: [NOCDAPC] D12_APC_0: 0x0
10034 22:57:33.398324 INFO: [NOCDAPC] D12_APC_1: 0xfff
10035 22:57:33.402123 INFO: [NOCDAPC] D13_APC_0: 0x0
10036 22:57:33.405033 INFO: [NOCDAPC] D13_APC_1: 0xfff
10037 22:57:33.408819 INFO: [NOCDAPC] D14_APC_0: 0x0
10038 22:57:33.411866 INFO: [NOCDAPC] D14_APC_1: 0xfff
10039 22:57:33.412011 INFO: [NOCDAPC] D15_APC_0: 0x0
10040 22:57:33.415165 INFO: [NOCDAPC] D15_APC_1: 0xfff
10041 22:57:33.418345 INFO: [NOCDAPC] APC_CON: 0x4
10042 22:57:33.421737 INFO: [APUAPC] set_apusys_apc done
10043 22:57:33.424871 INFO: [DEVAPC] devapc_init done
10044 22:57:33.428595 INFO: GICv3 without legacy support detected.
10045 22:57:33.435022 INFO: ARM GICv3 driver initialized in EL3
10046 22:57:33.438150 INFO: Maximum SPI INTID supported: 639
10047 22:57:33.441370 INFO: BL31: Initializing runtime services
10048 22:57:33.448111 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10049 22:57:33.451534 INFO: SPM: enable CPC mode
10050 22:57:33.454679 INFO: mcdi ready for mcusys-off-idle and system suspend
10051 22:57:33.461316 INFO: BL31: Preparing for EL3 exit to normal world
10052 22:57:33.464866 INFO: Entry point address = 0x80000000
10053 22:57:33.464950 INFO: SPSR = 0x8
10054 22:57:33.471354
10055 22:57:33.471443
10056 22:57:33.471515
10057 22:57:33.474812 Starting depthcharge on Spherion...
10058 22:57:33.474885
10059 22:57:33.474946 Wipe memory regions:
10060 22:57:33.475010
10061 22:57:33.475677 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10062 22:57:33.475781 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10063 22:57:33.475869 Setting prompt string to ['asurada:']
10064 22:57:33.475961 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10065 22:57:33.477927 [0x00000040000000, 0x00000054600000)
10066 22:57:33.600002
10067 22:57:33.600124 [0x00000054660000, 0x00000080000000)
10068 22:57:33.860868
10069 22:57:33.861011 [0x000000821a7280, 0x000000ffe64000)
10070 22:57:34.605546
10071 22:57:34.605714 [0x00000100000000, 0x00000240000000)
10072 22:57:36.496130
10073 22:57:36.499352 Initializing XHCI USB controller at 0x11200000.
10074 22:57:37.537095
10075 22:57:37.540527 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10076 22:57:37.540641
10077 22:57:37.540735
10078 22:57:37.540840
10079 22:57:37.541160 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10081 22:57:37.641599 asurada: tftpboot 192.168.201.1 13683713/tftp-deploy-vrtot5ad/kernel/image.itb 13683713/tftp-deploy-vrtot5ad/kernel/cmdline
10082 22:57:37.641724 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10083 22:57:37.641826 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10084 22:57:37.646148 tftpboot 192.168.201.1 13683713/tftp-deploy-vrtot5ad/kernel/image.ittp-deploy-vrtot5ad/kernel/cmdline
10085 22:57:37.646230
10086 22:57:37.646312 Waiting for link
10087 22:57:37.806071
10088 22:57:37.806234 R8152: Initializing
10089 22:57:37.806340
10090 22:57:37.809284 Version 9 (ocp_data = 6010)
10091 22:57:37.809357
10092 22:57:37.812796 R8152: Done initializing
10093 22:57:37.812885
10094 22:57:37.812952 Adding net device
10095 22:57:39.758851
10096 22:57:39.758997 done.
10097 22:57:39.759068
10098 22:57:39.759131 MAC: 00:e0:4c:78:7a:aa
10099 22:57:39.759191
10100 22:57:39.762440 Sending DHCP discover... done.
10101 22:57:39.762525
10102 22:57:39.765832 Waiting for reply... done.
10103 22:57:39.765915
10104 22:57:39.769048 Sending DHCP request... done.
10105 22:57:39.769132
10106 22:57:39.769198 Waiting for reply... done.
10107 22:57:39.769261
10108 22:57:39.772452 My ip is 192.168.201.12
10109 22:57:39.772536
10110 22:57:39.775938 The DHCP server ip is 192.168.201.1
10111 22:57:39.776031
10112 22:57:39.779087 TFTP server IP predefined by user: 192.168.201.1
10113 22:57:39.779170
10114 22:57:39.785136 Bootfile predefined by user: 13683713/tftp-deploy-vrtot5ad/kernel/image.itb
10115 22:57:39.785220
10116 22:57:39.789108 Sending tftp read request... done.
10117 22:57:39.789191
10118 22:57:39.792274 Waiting for the transfer...
10119 22:57:39.792357
10120 22:57:40.055593 00000000 ################################################################
10121 22:57:40.055741
10122 22:57:40.307549 00080000 ################################################################
10123 22:57:40.307699
10124 22:57:40.559240 00100000 ################################################################
10125 22:57:40.559387
10126 22:57:40.815500 00180000 ################################################################
10127 22:57:40.815656
10128 22:57:41.066031 00200000 ################################################################
10129 22:57:41.066177
10130 22:57:41.320765 00280000 ################################################################
10131 22:57:41.320916
10132 22:57:41.570421 00300000 ################################################################
10133 22:57:41.570564
10134 22:57:41.828985 00380000 ################################################################
10135 22:57:41.829149
10136 22:57:42.080975 00400000 ################################################################
10137 22:57:42.081122
10138 22:57:42.330240 00480000 ################################################################
10139 22:57:42.330388
10140 22:57:42.578942 00500000 ################################################################
10141 22:57:42.579081
10142 22:57:42.829384 00580000 ################################################################
10143 22:57:42.829532
10144 22:57:43.085027 00600000 ################################################################
10145 22:57:43.085173
10146 22:57:43.339725 00680000 ################################################################
10147 22:57:43.339906
10148 22:57:43.595024 00700000 ################################################################
10149 22:57:43.595172
10150 22:57:43.848547 00780000 ################################################################
10151 22:57:43.848714
10152 22:57:44.097571 00800000 ################################################################
10153 22:57:44.097729
10154 22:57:44.347372 00880000 ################################################################
10155 22:57:44.347502
10156 22:57:44.608520 00900000 ################################################################
10157 22:57:44.608664
10158 22:57:44.869101 00980000 ################################################################
10159 22:57:44.869243
10160 22:57:45.128863 00a00000 ################################################################
10161 22:57:45.128999
10162 22:57:45.381692 00a80000 ################################################################
10163 22:57:45.381865
10164 22:57:45.629522 00b00000 ################################################################
10165 22:57:45.629667
10166 22:57:45.877848 00b80000 ################################################################
10167 22:57:45.878023
10168 22:57:46.129516 00c00000 ################################################################
10169 22:57:46.129656
10170 22:57:46.379493 00c80000 ################################################################
10171 22:57:46.379662
10172 22:57:46.626970 00d00000 ################################################################
10173 22:57:46.627144
10174 22:57:46.875361 00d80000 ################################################################
10175 22:57:46.875509
10176 22:57:47.126102 00e00000 ################################################################
10177 22:57:47.126251
10178 22:57:47.373986 00e80000 ################################################################
10179 22:57:47.374155
10180 22:57:47.622348 00f00000 ################################################################
10181 22:57:47.622493
10182 22:57:47.871270 00f80000 ################################################################
10183 22:57:47.871446
10184 22:57:48.129628 01000000 ################################################################
10185 22:57:48.129793
10186 22:57:48.375238 01080000 ################################################################
10187 22:57:48.375390
10188 22:57:48.632359 01100000 ################################################################
10189 22:57:48.632500
10190 22:57:48.888921 01180000 ################################################################
10191 22:57:48.889060
10192 22:57:49.153892 01200000 ################################################################
10193 22:57:49.154043
10194 22:57:49.447786 01280000 ################################################################
10195 22:57:49.447933
10196 22:57:49.736992 01300000 ################################################################
10197 22:57:49.737138
10198 22:57:50.011087 01380000 ################################################################
10199 22:57:50.011232
10200 22:57:50.290194 01400000 ################################################################
10201 22:57:50.290345
10202 22:57:50.573066 01480000 ################################################################
10203 22:57:50.573213
10204 22:57:50.858526 01500000 ################################################################
10205 22:57:50.858663
10206 22:57:51.141232 01580000 ################################################################
10207 22:57:51.141398
10208 22:57:51.419543 01600000 ################################################################
10209 22:57:51.419680
10210 22:57:51.667953 01680000 ################################################################
10211 22:57:51.668125
10212 22:57:51.917576 01700000 ################################################################
10213 22:57:51.917714
10214 22:57:52.168590 01780000 ################################################################
10215 22:57:52.168725
10216 22:57:52.417761 01800000 ################################################################
10217 22:57:52.417899
10218 22:57:52.666730 01880000 ################################################################
10219 22:57:52.666864
10220 22:57:52.930024 01900000 ################################################################
10221 22:57:52.930163
10222 22:57:53.179991 01980000 ################################################################
10223 22:57:53.180131
10224 22:57:53.429976 01a00000 ################################################################
10225 22:57:53.430115
10226 22:57:53.679619 01a80000 ################################################################
10227 22:57:53.679757
10228 22:57:53.939036 01b00000 ################################################################
10229 22:57:53.939170
10230 22:57:54.204550 01b80000 ################################################################
10231 22:57:54.204683
10232 22:57:54.453285 01c00000 ################################################################
10233 22:57:54.453427
10234 22:57:54.702403 01c80000 ################################################################
10235 22:57:54.702545
10236 22:57:54.951604 01d00000 ################################################################
10237 22:57:54.951750
10238 22:57:55.201754 01d80000 ################################################################
10239 22:57:55.201896
10240 22:57:55.380839 01e00000 ############################################### done.
10241 22:57:55.380969
10242 22:57:55.384170 The bootfile was 31837638 bytes long.
10243 22:57:55.384262
10244 22:57:55.387714 Sending tftp read request... done.
10245 22:57:55.387804
10246 22:57:55.390922 Waiting for the transfer...
10247 22:57:55.391121
10248 22:57:55.391213 00000000 # done.
10249 22:57:55.391294
10250 22:57:55.400987 Command line loaded dynamically from TFTP file: 13683713/tftp-deploy-vrtot5ad/kernel/cmdline
10251 22:57:55.401187
10252 22:57:55.420551 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683713/extract-nfsrootfs-x5eqj7ae,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10253 22:57:55.420824
10254 22:57:55.424448 Loading FIT.
10255 22:57:55.424882
10256 22:57:55.427523 Image ramdisk-1 has 18728790 bytes.
10257 22:57:55.428008
10258 22:57:55.430987 Image fdt-1 has 47258 bytes.
10259 22:57:55.431412
10260 22:57:55.434227 Image kernel-1 has 13059555 bytes.
10261 22:57:55.434759
10262 22:57:55.440950 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10263 22:57:55.441535
10264 22:57:55.461036 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10265 22:57:55.461626
10266 22:57:55.463685 Choosing best match conf-1 for compat google,spherion-rev2.
10267 22:57:55.468664
10268 22:57:55.473178 Connected to device vid:did:rid of 1ae0:0028:00
10269 22:57:55.481791
10270 22:57:55.484795 tpm_get_response: command 0x17b, return code 0x0
10271 22:57:55.485270
10272 22:57:55.487936 ec_init: CrosEC protocol v3 supported (256, 248)
10273 22:57:55.493725
10274 22:57:55.496843 tpm_cleanup: add release locality here.
10275 22:57:55.497422
10276 22:57:55.497800 Shutting down all USB controllers.
10277 22:57:55.499777
10278 22:57:55.500295 Removing current net device
10279 22:57:55.500673
10280 22:57:55.506501 Exiting depthcharge with code 4 at timestamp: 51264093
10281 22:57:55.506975
10282 22:57:55.509262 LZMA decompressing kernel-1 to 0x821a6718
10283 22:57:55.509736
10284 22:57:55.512833 LZMA decompressing kernel-1 to 0x40000000
10285 22:57:57.124408
10286 22:57:57.124981 jumping to kernel
10287 22:57:57.126787 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10288 22:57:57.127332 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10289 22:57:57.127752 Setting prompt string to ['Linux version [0-9]']
10290 22:57:57.128187 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10291 22:57:57.128574 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10292 22:57:57.206224
10293 22:57:57.209446 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10294 22:57:57.213311 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10295 22:57:57.213963 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10296 22:57:57.214379 Setting prompt string to []
10297 22:57:57.214817 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10298 22:57:57.215226 Using line separator: #'\n'#
10299 22:57:57.215598 No login prompt set.
10300 22:57:57.216037 Parsing kernel messages
10301 22:57:57.216370 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10302 22:57:57.216951 [login-action] Waiting for messages, (timeout 00:04:02)
10303 22:57:57.217325 Waiting using forced prompt support (timeout 00:02:01)
10304 22:57:57.232096 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10305 22:57:57.235848 [ 0.000000] random: crng init done
10306 22:57:57.243126 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10307 22:57:57.245603 [ 0.000000] efi: UEFI not found.
10308 22:57:57.252438 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10309 22:57:57.259045 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10310 22:57:57.269198 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10311 22:57:57.279037 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10312 22:57:57.285727 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10313 22:57:57.289193 [ 0.000000] printk: bootconsole [mtk8250] enabled
10314 22:57:57.297964 [ 0.000000] NUMA: No NUMA configuration found
10315 22:57:57.304833 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10316 22:57:57.311588 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10317 22:57:57.312211 [ 0.000000] Zone ranges:
10318 22:57:57.317802 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10319 22:57:57.321600 [ 0.000000] DMA32 empty
10320 22:57:57.328003 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10321 22:57:57.331273 [ 0.000000] Movable zone start for each node
10322 22:57:57.334703 [ 0.000000] Early memory node ranges
10323 22:57:57.341172 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10324 22:57:57.348190 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10325 22:57:57.354578 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10326 22:57:57.360846 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10327 22:57:57.368229 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10328 22:57:57.374127 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10329 22:57:57.430455 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10330 22:57:57.437162 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10331 22:57:57.443674 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10332 22:57:57.446996 [ 0.000000] psci: probing for conduit method from DT.
10333 22:57:57.454323 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10334 22:57:57.457526 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10335 22:57:57.463612 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10336 22:57:57.467582 [ 0.000000] psci: SMC Calling Convention v1.2
10337 22:57:57.473829 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10338 22:57:57.476941 [ 0.000000] Detected VIPT I-cache on CPU0
10339 22:57:57.483884 [ 0.000000] CPU features: detected: GIC system register CPU interface
10340 22:57:57.490792 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10341 22:57:57.497122 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10342 22:57:57.503802 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10343 22:57:57.510638 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10344 22:57:57.517173 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10345 22:57:57.523293 [ 0.000000] alternatives: applying boot alternatives
10346 22:57:57.529994 [ 0.000000] Fallback order for Node 0: 0
10347 22:57:57.536619 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10348 22:57:57.539922 [ 0.000000] Policy zone: Normal
10349 22:57:57.563528 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683713/extract-nfsrootfs-x5eqj7ae,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10350 22:57:57.573287 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10351 22:57:57.583586 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10352 22:57:57.594078 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10353 22:57:57.600333 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10354 22:57:57.603539 <6>[ 0.000000] software IO TLB: area num 8.
10355 22:57:57.660256 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10356 22:57:57.809517 <6>[ 0.000000] Memory: 7945900K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406868K reserved, 32768K cma-reserved)
10357 22:57:57.817002 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10358 22:57:57.822835 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10359 22:57:57.826851 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10360 22:57:57.833014 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10361 22:57:57.839477 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10362 22:57:57.843457 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10363 22:57:57.853464 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10364 22:57:57.860101 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10365 22:57:57.863339 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10366 22:57:57.870800 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10367 22:57:57.874120 <6>[ 0.000000] GICv3: 608 SPIs implemented
10368 22:57:57.880417 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10369 22:57:57.883913 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10370 22:57:57.887077 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10371 22:57:57.897527 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10372 22:57:57.907189 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10373 22:57:57.920449 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10374 22:57:57.927301 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10375 22:57:57.936433 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10376 22:57:57.949184 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10377 22:57:57.956220 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10378 22:57:57.962372 <6>[ 0.009175] Console: colour dummy device 80x25
10379 22:57:57.972538 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10380 22:57:57.979182 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10381 22:57:57.982672 <6>[ 0.029221] LSM: Security Framework initializing
10382 22:57:57.989269 <6>[ 0.034120] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10383 22:57:57.999270 <6>[ 0.041932] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10384 22:57:58.005630 <6>[ 0.051232] cblist_init_generic: Setting adjustable number of callback queues.
10385 22:57:58.012833 <6>[ 0.058675] cblist_init_generic: Setting shift to 3 and lim to 1.
10386 22:57:58.019526 <6>[ 0.065014] cblist_init_generic: Setting adjustable number of callback queues.
10387 22:57:58.025708 <6>[ 0.072441] cblist_init_generic: Setting shift to 3 and lim to 1.
10388 22:57:58.032416 <6>[ 0.078844] rcu: Hierarchical SRCU implementation.
10389 22:57:58.039537 <6>[ 0.083858] rcu: Max phase no-delay instances is 1000.
10390 22:57:58.045728 <6>[ 0.090879] EFI services will not be available.
10391 22:57:58.048512 <6>[ 0.095835] smp: Bringing up secondary CPUs ...
10392 22:57:58.056796 <6>[ 0.100859] Detected VIPT I-cache on CPU1
10393 22:57:58.063569 <6>[ 0.100918] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10394 22:57:58.070420 <6>[ 0.100942] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10395 22:57:58.073508 <6>[ 0.101257] Detected VIPT I-cache on CPU2
10396 22:57:58.080603 <6>[ 0.101304] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10397 22:57:58.086946 <6>[ 0.101319] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10398 22:57:58.093025 <6>[ 0.101577] Detected VIPT I-cache on CPU3
10399 22:57:58.099917 <6>[ 0.101624] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10400 22:57:58.106369 <6>[ 0.101637] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10401 22:57:58.109689 <6>[ 0.101942] CPU features: detected: Spectre-v4
10402 22:57:58.116177 <6>[ 0.101948] CPU features: detected: Spectre-BHB
10403 22:57:58.119686 <6>[ 0.101953] Detected PIPT I-cache on CPU4
10404 22:57:58.126343 <6>[ 0.102011] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10405 22:57:58.132981 <6>[ 0.102028] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10406 22:57:58.140358 <6>[ 0.102321] Detected PIPT I-cache on CPU5
10407 22:57:58.146261 <6>[ 0.102383] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10408 22:57:58.152816 <6>[ 0.102400] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10409 22:57:58.156364 <6>[ 0.102682] Detected PIPT I-cache on CPU6
10410 22:57:58.163150 <6>[ 0.102750] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10411 22:57:58.169388 <6>[ 0.102765] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10412 22:57:58.176335 <6>[ 0.103061] Detected PIPT I-cache on CPU7
10413 22:57:58.183100 <6>[ 0.103126] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10414 22:57:58.189239 <6>[ 0.103142] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10415 22:57:58.192506 <6>[ 0.103189] smp: Brought up 1 node, 8 CPUs
10416 22:57:58.199601 <6>[ 0.244558] SMP: Total of 8 processors activated.
10417 22:57:58.202717 <6>[ 0.249478] CPU features: detected: 32-bit EL0 Support
10418 22:57:58.212510 <6>[ 0.254841] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10419 22:57:58.219267 <6>[ 0.263641] CPU features: detected: Common not Private translations
10420 22:57:58.222808 <6>[ 0.270157] CPU features: detected: CRC32 instructions
10421 22:57:58.229483 <6>[ 0.275542] CPU features: detected: RCpc load-acquire (LDAPR)
10422 22:57:58.235843 <6>[ 0.281538] CPU features: detected: LSE atomic instructions
10423 22:57:58.242166 <6>[ 0.287320] CPU features: detected: Privileged Access Never
10424 22:57:58.245483 <6>[ 0.293100] CPU features: detected: RAS Extension Support
10425 22:57:58.255816 <6>[ 0.298709] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10426 22:57:58.259229 <6>[ 0.305973] CPU: All CPU(s) started at EL2
10427 22:57:58.265311 <6>[ 0.310290] alternatives: applying system-wide alternatives
10428 22:57:58.274803 <6>[ 0.321101] devtmpfs: initialized
10429 22:57:58.286973 <6>[ 0.330123] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10430 22:57:58.297513 <6>[ 0.340085] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10431 22:57:58.303794 <6>[ 0.348116] pinctrl core: initialized pinctrl subsystem
10432 22:57:58.306885 <6>[ 0.354768] DMI not present or invalid.
10433 22:57:58.313571 <6>[ 0.359187] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10434 22:57:58.323682 <6>[ 0.366056] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10435 22:57:58.330464 <6>[ 0.373646] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10436 22:57:58.340326 <6>[ 0.381869] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10437 22:57:58.343505 <6>[ 0.390113] audit: initializing netlink subsys (disabled)
10438 22:57:58.353278 <5>[ 0.395807] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10439 22:57:58.359898 <6>[ 0.396515] thermal_sys: Registered thermal governor 'step_wise'
10440 22:57:58.367052 <6>[ 0.403775] thermal_sys: Registered thermal governor 'power_allocator'
10441 22:57:58.369946 <6>[ 0.410031] cpuidle: using governor menu
10442 22:57:58.373577 <6>[ 0.420992] NET: Registered PF_QIPCRTR protocol family
10443 22:57:58.383260 <6>[ 0.426483] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10444 22:57:58.386384 <6>[ 0.433585] ASID allocator initialised with 32768 entries
10445 22:57:58.393612 <6>[ 0.440167] Serial: AMBA PL011 UART driver
10446 22:57:58.402273 <4>[ 0.448900] Trying to register duplicate clock ID: 134
10447 22:57:58.462002 <6>[ 0.512099] KASLR enabled
10448 22:57:58.476207 <6>[ 0.519862] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10449 22:57:58.483040 <6>[ 0.526876] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10450 22:57:58.489740 <6>[ 0.533366] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10451 22:57:58.496050 <6>[ 0.540371] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10452 22:57:58.502985 <6>[ 0.546859] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10453 22:57:58.509554 <6>[ 0.553864] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10454 22:57:58.516241 <6>[ 0.560350] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10455 22:57:58.523075 <6>[ 0.567355] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10456 22:57:58.526058 <6>[ 0.574874] ACPI: Interpreter disabled.
10457 22:57:58.534828 <6>[ 0.581309] iommu: Default domain type: Translated
10458 22:57:58.541995 <6>[ 0.586421] iommu: DMA domain TLB invalidation policy: strict mode
10459 22:57:58.545118 <5>[ 0.593079] SCSI subsystem initialized
10460 22:57:58.551734 <6>[ 0.597250] usbcore: registered new interface driver usbfs
10461 22:57:58.557962 <6>[ 0.602984] usbcore: registered new interface driver hub
10462 22:57:58.561249 <6>[ 0.608536] usbcore: registered new device driver usb
10463 22:57:58.567837 <6>[ 0.614635] pps_core: LinuxPPS API ver. 1 registered
10464 22:57:58.577857 <6>[ 0.619828] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10465 22:57:58.581208 <6>[ 0.629177] PTP clock support registered
10466 22:57:58.584473 <6>[ 0.633419] EDAC MC: Ver: 3.0.0
10467 22:57:58.591843 <6>[ 0.638551] FPGA manager framework
10468 22:57:58.598095 <6>[ 0.642237] Advanced Linux Sound Architecture Driver Initialized.
10469 22:57:58.601315 <6>[ 0.649022] vgaarb: loaded
10470 22:57:58.608225 <6>[ 0.652188] clocksource: Switched to clocksource arch_sys_counter
10471 22:57:58.611336 <5>[ 0.658630] VFS: Disk quotas dquot_6.6.0
10472 22:57:58.617991 <6>[ 0.662815] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10473 22:57:58.621243 <6>[ 0.670004] pnp: PnP ACPI: disabled
10474 22:57:58.629413 <6>[ 0.676706] NET: Registered PF_INET protocol family
10475 22:57:58.639686 <6>[ 0.682291] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10476 22:57:58.650960 <6>[ 0.694627] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10477 22:57:58.660742 <6>[ 0.703443] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10478 22:57:58.667106 <6>[ 0.711413] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10479 22:57:58.673779 <6>[ 0.720110] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10480 22:57:58.686237 <6>[ 0.729860] TCP: Hash tables configured (established 65536 bind 65536)
10481 22:57:58.692736 <6>[ 0.736725] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10482 22:57:58.699424 <6>[ 0.743922] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10483 22:57:58.706078 <6>[ 0.751624] NET: Registered PF_UNIX/PF_LOCAL protocol family
10484 22:57:58.712342 <6>[ 0.757772] RPC: Registered named UNIX socket transport module.
10485 22:57:58.716374 <6>[ 0.763929] RPC: Registered udp transport module.
10486 22:57:58.722759 <6>[ 0.768861] RPC: Registered tcp transport module.
10487 22:57:58.729299 <6>[ 0.773795] RPC: Registered tcp NFSv4.1 backchannel transport module.
10488 22:57:58.733291 <6>[ 0.780462] PCI: CLS 0 bytes, default 64
10489 22:57:58.735911 <6>[ 0.784758] Unpacking initramfs...
10490 22:57:58.746079 <6>[ 0.788819] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10491 22:57:58.752308 <6>[ 0.797491] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10492 22:57:58.759553 <6>[ 0.806328] kvm [1]: IPA Size Limit: 40 bits
10493 22:57:58.762435 <6>[ 0.810856] kvm [1]: GICv3: no GICV resource entry
10494 22:57:58.769519 <6>[ 0.815875] kvm [1]: disabling GICv2 emulation
10495 22:57:58.776023 <6>[ 0.820565] kvm [1]: GIC system register CPU interface enabled
10496 22:57:58.779026 <6>[ 0.826725] kvm [1]: vgic interrupt IRQ18
10497 22:57:58.785461 <6>[ 0.831076] kvm [1]: VHE mode initialized successfully
10498 22:57:58.788926 <5>[ 0.837535] Initialise system trusted keyrings
10499 22:57:58.795539 <6>[ 0.842349] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10500 22:57:58.805487 <6>[ 0.852430] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10501 22:57:58.812153 <5>[ 0.858864] NFS: Registering the id_resolver key type
10502 22:57:58.815353 <5>[ 0.864171] Key type id_resolver registered
10503 22:57:58.822347 <5>[ 0.868585] Key type id_legacy registered
10504 22:57:58.828920 <6>[ 0.872866] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10505 22:57:58.835677 <6>[ 0.879788] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10506 22:57:58.841924 <6>[ 0.887516] 9p: Installing v9fs 9p2000 file system support
10507 22:57:58.877800 <5>[ 0.924356] Key type asymmetric registered
10508 22:57:58.881334 <5>[ 0.928687] Asymmetric key parser 'x509' registered
10509 22:57:58.891022 <6>[ 0.933834] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10510 22:57:58.894448 <6>[ 0.941448] io scheduler mq-deadline registered
10511 22:57:58.897933 <6>[ 0.946210] io scheduler kyber registered
10512 22:57:58.916572 <6>[ 0.963375] EINJ: ACPI disabled.
10513 22:57:58.949623 <4>[ 0.989702] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10514 22:57:58.959646 <4>[ 1.000340] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10515 22:57:58.974899 <6>[ 1.021527] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10516 22:57:58.983303 <6>[ 1.029583] printk: console [ttyS0] disabled
10517 22:57:59.011481 <6>[ 1.054213] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10518 22:57:59.017882 <6>[ 1.063686] printk: console [ttyS0] enabled
10519 22:57:59.020717 <6>[ 1.063686] printk: console [ttyS0] enabled
10520 22:57:59.027644 <6>[ 1.072581] printk: bootconsole [mtk8250] disabled
10521 22:57:59.030827 <6>[ 1.072581] printk: bootconsole [mtk8250] disabled
10522 22:57:59.037688 <6>[ 1.083844] SuperH (H)SCI(F) driver initialized
10523 22:57:59.040491 <6>[ 1.089128] msm_serial: driver initialized
10524 22:57:59.055040 <6>[ 1.098159] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10525 22:57:59.065055 <6>[ 1.106706] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10526 22:57:59.071363 <6>[ 1.115248] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10527 22:57:59.081328 <6>[ 1.123877] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10528 22:57:59.088113 <6>[ 1.132583] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10529 22:57:59.097945 <6>[ 1.141297] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10530 22:57:59.108139 <6>[ 1.149844] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10531 22:57:59.114553 <6>[ 1.158652] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10532 22:57:59.124875 <6>[ 1.167198] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10533 22:57:59.136541 <6>[ 1.183146] loop: module loaded
10534 22:57:59.143442 <6>[ 1.189191] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10535 22:57:59.166220 <4>[ 1.212602] mtk-pmic-keys: Failed to locate of_node [id: -1]
10536 22:57:59.173182 <6>[ 1.219517] megasas: 07.719.03.00-rc1
10537 22:57:59.182392 <6>[ 1.229222] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10538 22:57:59.189479 <6>[ 1.235591] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10539 22:57:59.205778 <6>[ 1.252383] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10540 22:57:59.263083 <6>[ 1.302544] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10541 22:57:59.571389 <6>[ 1.617870] Freeing initrd memory: 18284K
10542 22:57:59.582958 <6>[ 1.629639] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10543 22:57:59.593985 <6>[ 1.640588] tun: Universal TUN/TAP device driver, 1.6
10544 22:57:59.597156 <6>[ 1.646648] thunder_xcv, ver 1.0
10545 22:57:59.600566 <6>[ 1.650157] thunder_bgx, ver 1.0
10546 22:57:59.603908 <6>[ 1.653652] nicpf, ver 1.0
10547 22:57:59.614708 <6>[ 1.657676] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10548 22:57:59.617606 <6>[ 1.665155] hns3: Copyright (c) 2017 Huawei Corporation.
10549 22:57:59.621119 <6>[ 1.670747] hclge is initializing
10550 22:57:59.627928 <6>[ 1.674323] e1000: Intel(R) PRO/1000 Network Driver
10551 22:57:59.634130 <6>[ 1.679452] e1000: Copyright (c) 1999-2006 Intel Corporation.
10552 22:57:59.637363 <6>[ 1.685467] e1000e: Intel(R) PRO/1000 Network Driver
10553 22:57:59.644238 <6>[ 1.690682] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10554 22:57:59.650769 <6>[ 1.696872] igb: Intel(R) Gigabit Ethernet Network Driver
10555 22:57:59.657730 <6>[ 1.702522] igb: Copyright (c) 2007-2014 Intel Corporation.
10556 22:57:59.663706 <6>[ 1.708359] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10557 22:57:59.670468 <6>[ 1.714878] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10558 22:57:59.674349 <6>[ 1.721343] sky2: driver version 1.30
10559 22:57:59.680506 <6>[ 1.726285] usbcore: registered new device driver r8152-cfgselector
10560 22:57:59.687399 <6>[ 1.732820] usbcore: registered new interface driver r8152
10561 22:57:59.691061 <6>[ 1.738640] VFIO - User Level meta-driver version: 0.3
10562 22:57:59.700376 <6>[ 1.746889] usbcore: registered new interface driver usb-storage
10563 22:57:59.707447 <6>[ 1.753334] usbcore: registered new device driver onboard-usb-hub
10564 22:57:59.715598 <6>[ 1.762503] mt6397-rtc mt6359-rtc: registered as rtc0
10565 22:57:59.725811 <6>[ 1.767965] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:53:36 UTC (1715122416)
10566 22:57:59.729147 <6>[ 1.777532] i2c_dev: i2c /dev entries driver
10567 22:57:59.746416 <6>[ 1.789477] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10568 22:57:59.752509 <4>[ 1.798205] cpu cpu0: supply cpu not found, using dummy regulator
10569 22:57:59.759600 <4>[ 1.804633] cpu cpu1: supply cpu not found, using dummy regulator
10570 22:57:59.765953 <4>[ 1.811039] cpu cpu2: supply cpu not found, using dummy regulator
10571 22:57:59.772677 <4>[ 1.817443] cpu cpu3: supply cpu not found, using dummy regulator
10572 22:57:59.780043 <4>[ 1.823843] cpu cpu4: supply cpu not found, using dummy regulator
10573 22:57:59.786346 <4>[ 1.830257] cpu cpu5: supply cpu not found, using dummy regulator
10574 22:57:59.793247 <4>[ 1.836657] cpu cpu6: supply cpu not found, using dummy regulator
10575 22:57:59.796238 <4>[ 1.843056] cpu cpu7: supply cpu not found, using dummy regulator
10576 22:57:59.817120 <6>[ 1.863691] cpu cpu0: EM: created perf domain
10577 22:57:59.820546 <6>[ 1.868641] cpu cpu4: EM: created perf domain
10578 22:57:59.827469 <6>[ 1.874276] sdhci: Secure Digital Host Controller Interface driver
10579 22:57:59.833878 <6>[ 1.880717] sdhci: Copyright(c) Pierre Ossman
10580 22:57:59.840795 <6>[ 1.885682] Synopsys Designware Multimedia Card Interface Driver
10581 22:57:59.847154 <6>[ 1.892325] sdhci-pltfm: SDHCI platform and OF driver helper
10582 22:57:59.851094 <6>[ 1.892420] mmc0: CQHCI version 5.10
10583 22:57:59.857710 <6>[ 1.902594] ledtrig-cpu: registered to indicate activity on CPUs
10584 22:57:59.864109 <6>[ 1.909673] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10585 22:57:59.870778 <6>[ 1.916724] usbcore: registered new interface driver usbhid
10586 22:57:59.874226 <6>[ 1.922546] usbhid: USB HID core driver
10587 22:57:59.881191 <6>[ 1.926753] spi_master spi0: will run message pump with realtime priority
10588 22:57:59.923889 <6>[ 1.963964] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10589 22:57:59.939306 <6>[ 1.978802] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10590 22:57:59.945654 <6>[ 1.992348] mmc0: Command Queue Engine enabled
10591 22:57:59.952597 <6>[ 1.997137] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10592 22:57:59.959635 <6>[ 2.004025] cros-ec-spi spi0.0: Chrome EC device registered
10593 22:57:59.962566 <6>[ 2.004549] mmcblk0: mmc0:0001 DA4128 116 GiB
10594 22:57:59.972610 <6>[ 2.019581] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10595 22:57:59.980384 <6>[ 2.027045] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10596 22:57:59.986839 <6>[ 2.032950] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10597 22:57:59.993611 <6>[ 2.038980] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10598 22:58:00.003647 <6>[ 2.043596] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10599 22:58:00.010187 <6>[ 2.056076] NET: Registered PF_PACKET protocol family
10600 22:58:00.013399 <6>[ 2.061491] 9pnet: Installing 9P2000 support
10601 22:58:00.020065 <5>[ 2.066056] Key type dns_resolver registered
10602 22:58:00.023658 <6>[ 2.071052] registered taskstats version 1
10603 22:58:00.030227 <5>[ 2.075435] Loading compiled-in X.509 certificates
10604 22:58:00.058952 <4>[ 2.098921] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10605 22:58:00.069461 <4>[ 2.109662] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10606 22:58:00.075839 <3>[ 2.120320] debugfs: File 'uA_load' in directory '/' already present!
10607 22:58:00.082970 <3>[ 2.127041] debugfs: File 'min_uV' in directory '/' already present!
10608 22:58:00.089328 <3>[ 2.133655] debugfs: File 'max_uV' in directory '/' already present!
10609 22:58:00.096173 <3>[ 2.140270] debugfs: File 'constraint_flags' in directory '/' already present!
10610 22:58:00.108426 <6>[ 2.155249] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10611 22:58:00.115694 <6>[ 2.162174] xhci-mtk 11200000.usb: xHCI Host Controller
10612 22:58:00.122344 <6>[ 2.167674] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10613 22:58:00.132497 <6>[ 2.175519] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10614 22:58:00.138616 <6>[ 2.184931] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10615 22:58:00.146012 <6>[ 2.190990] xhci-mtk 11200000.usb: xHCI Host Controller
10616 22:58:00.151901 <6>[ 2.196466] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10617 22:58:00.158792 <6>[ 2.204111] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10618 22:58:00.165288 <6>[ 2.211734] hub 1-0:1.0: USB hub found
10619 22:58:00.168554 <6>[ 2.215760] hub 1-0:1.0: 1 port detected
10620 22:58:00.174981 <6>[ 2.220034] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10621 22:58:00.181951 <6>[ 2.228593] hub 2-0:1.0: USB hub found
10622 22:58:00.184845 <6>[ 2.232610] hub 2-0:1.0: 1 port detected
10623 22:58:00.193418 <6>[ 2.240683] mtk-msdc 11f70000.mmc: Got CD GPIO
10624 22:58:00.204563 <6>[ 2.247917] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10625 22:58:00.211016 <6>[ 2.255946] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10626 22:58:00.220645 <4>[ 2.263989] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10627 22:58:00.230521 <6>[ 2.273528] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10628 22:58:00.237548 <6>[ 2.281631] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10629 22:58:00.244416 <6>[ 2.289841] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10630 22:58:00.254540 <6>[ 2.297796] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10631 22:58:00.260801 <6>[ 2.305618] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10632 22:58:00.270493 <6>[ 2.313434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10633 22:58:00.280559 <6>[ 2.323872] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10634 22:58:00.287128 <6>[ 2.332254] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10635 22:58:00.297306 <6>[ 2.340591] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10636 22:58:00.303866 <6>[ 2.348928] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10637 22:58:00.313911 <6>[ 2.357266] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10638 22:58:00.320856 <6>[ 2.365605] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10639 22:58:00.330513 <6>[ 2.373943] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10640 22:58:00.337011 <6>[ 2.382281] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10641 22:58:00.346889 <6>[ 2.390618] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10642 22:58:00.353797 <6>[ 2.398956] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10643 22:58:00.363694 <6>[ 2.407294] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10644 22:58:00.370195 <6>[ 2.415632] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10645 22:58:00.380301 <6>[ 2.423969] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10646 22:58:00.386755 <6>[ 2.432310] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10647 22:58:00.396671 <6>[ 2.440648] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10648 22:58:00.403660 <6>[ 2.449398] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10649 22:58:00.410013 <6>[ 2.456557] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10650 22:58:00.416382 <6>[ 2.463330] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10651 22:58:00.423277 <6>[ 2.470088] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10652 22:58:00.433157 <6>[ 2.477025] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10653 22:58:00.439666 <6>[ 2.483876] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10654 22:58:00.450024 <6>[ 2.493007] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10655 22:58:00.459790 <6>[ 2.502126] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10656 22:58:00.469589 <6>[ 2.511425] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10657 22:58:00.479885 <6>[ 2.520906] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10658 22:58:00.486005 <6>[ 2.530374] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10659 22:58:00.496282 <6>[ 2.539495] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10660 22:58:00.506818 <6>[ 2.548962] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10661 22:58:00.516381 <6>[ 2.558080] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10662 22:58:00.526019 <6>[ 2.567375] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10663 22:58:00.535947 <6>[ 2.577535] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10664 22:58:00.545867 <6>[ 2.588969] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10665 22:58:00.552404 <6>[ 2.598151] Trying to probe devices needed for running init ...
10666 22:58:00.600373 <6>[ 2.644459] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10667 22:58:00.755520 <6>[ 2.802335] hub 1-1:1.0: USB hub found
10668 22:58:00.758458 <6>[ 2.806840] hub 1-1:1.0: 4 ports detected
10669 22:58:00.767995 <6>[ 2.815364] hub 1-1:1.0: USB hub found
10670 22:58:00.771135 <6>[ 2.819780] hub 1-1:1.0: 4 ports detected
10671 22:58:00.880629 <6>[ 2.924814] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10672 22:58:00.906834 <6>[ 2.954007] hub 2-1:1.0: USB hub found
10673 22:58:00.910207 <6>[ 2.958506] hub 2-1:1.0: 3 ports detected
10674 22:58:00.919305 <6>[ 2.966643] hub 2-1:1.0: USB hub found
10675 22:58:00.922715 <6>[ 2.971202] hub 2-1:1.0: 3 ports detected
10676 22:58:01.096513 <6>[ 3.140519] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10677 22:58:01.229294 <6>[ 3.276360] hub 1-1.4:1.0: USB hub found
10678 22:58:01.232476 <6>[ 3.281025] hub 1-1.4:1.0: 2 ports detected
10679 22:58:01.241527 <6>[ 3.288897] hub 1-1.4:1.0: USB hub found
10680 22:58:01.245069 <6>[ 3.293512] hub 1-1.4:1.0: 2 ports detected
10681 22:58:01.308439 <6>[ 3.352601] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10682 22:58:01.417420 <6>[ 3.461146] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10683 22:58:01.452737 <4>[ 3.496701] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10684 22:58:01.462815 <4>[ 3.505791] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10685 22:58:01.506904 <6>[ 3.554109] r8152 2-1.3:1.0 eth0: v1.12.13
10686 22:58:01.540619 <6>[ 3.584509] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10687 22:58:01.732288 <6>[ 3.776319] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10688 22:58:03.192601 <6>[ 5.240232] r8152 2-1.3:1.0 eth0: carrier on
10689 22:58:03.237005 <5>[ 5.268293] Sending DHCP requests ., OK
10690 22:58:03.243696 <6>[ 5.288555] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10691 22:58:03.246798 <6>[ 5.296842] IP-Config: Complete:
10692 22:58:03.260188 <6>[ 5.300342] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10693 22:58:03.266435 <6>[ 5.311063] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10694 22:58:03.273555 <6>[ 5.319688] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10695 22:58:03.279730 <6>[ 5.319697] nameserver0=192.168.201.1
10696 22:58:03.283162 <6>[ 5.331870] clk: Disabling unused clocks
10697 22:58:03.287049 <6>[ 5.337454] ALSA device list:
10698 22:58:03.292849 <6>[ 5.340724] No soundcards found.
10699 22:58:03.300853 <6>[ 5.348090] Freeing unused kernel memory: 8512K
10700 22:58:03.303989 <6>[ 5.353073] Run /init as init process
10701 22:58:03.312736 Loading, please wait...
10702 22:58:03.339442 Starting systemd-udevd version 252.22-1~deb12u1
10703 22:58:03.339567
10704 22:58:03.605827 <6>[ 5.649832] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10705 22:58:03.612577 <6>[ 5.652608] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10706 22:58:03.622310 <6>[ 5.657551] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10707 22:58:03.632290 <6>[ 5.674719] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10708 22:58:03.640647 <6>[ 5.688026] mc: Linux media interface: v0.10
10709 22:58:03.647235 <6>[ 5.689247] remoteproc remoteproc0: scp is available
10710 22:58:03.650415 <6>[ 5.698511] remoteproc remoteproc0: powering up scp
10711 22:58:03.660235 <3>[ 5.698957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 22:58:03.667322 <6>[ 5.700348] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10713 22:58:03.673944 <6>[ 5.703904] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10714 22:58:03.680332 <6>[ 5.713525] videodev: Linux video capture interface: v2.00
10715 22:58:03.683666 <6>[ 5.714280] Bluetooth: Core ver 2.22
10716 22:58:03.693628 <3>[ 5.714358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 22:58:03.700290 <6>[ 5.714433] NET: Registered PF_BLUETOOTH protocol family
10718 22:58:03.703639 <6>[ 5.714437] Bluetooth: HCI device and connection manager initialized
10719 22:58:03.710226 <6>[ 5.714469] Bluetooth: HCI socket layer initialized
10720 22:58:03.717512 <6>[ 5.714476] Bluetooth: L2CAP socket layer initialized
10721 22:58:03.720397 <6>[ 5.714501] Bluetooth: SCO socket layer initialized
10722 22:58:03.727546 <3>[ 5.714794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 22:58:03.737726 <3>[ 5.714923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 22:58:03.744687 <3>[ 5.714932] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 22:58:03.754756 <3>[ 5.714938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 22:58:03.761539 <3>[ 5.714945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 22:58:03.771163 <3>[ 5.714950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 22:58:03.777622 <3>[ 5.714986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 22:58:03.784245 <3>[ 5.715030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 22:58:03.794077 <3>[ 5.715033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 22:58:03.800495 <3>[ 5.715036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 22:58:03.811106 <3>[ 5.715057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 22:58:03.818446 <3>[ 5.715060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 22:58:03.824530 <3>[ 5.715063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 22:58:03.834603 <3>[ 5.715066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 22:58:03.841232 <3>[ 5.715068] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 22:58:03.851491 <3>[ 5.715083] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 22:58:03.854763 <6>[ 5.719512] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10739 22:58:03.864349 <4>[ 5.747115] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10740 22:58:03.871045 <4>[ 5.754712] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10741 22:58:03.877906 <4>[ 5.754712] Fallback method does not support PEC.
10742 22:58:03.884332 <4>[ 5.758007] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10743 22:58:03.894702 <3>[ 5.783297] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10744 22:58:03.901235 <6>[ 5.811103] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10745 22:58:03.911542 <6>[ 5.816897] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10746 22:58:03.914727 <6>[ 5.822111] pci_bus 0000:00: root bus resource [bus 00-ff]
10747 22:58:03.924533 <6>[ 5.830639] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10748 22:58:03.931119 <6>[ 5.838254] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10749 22:58:03.941328 <6>[ 5.838258] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10750 22:58:03.947755 <6>[ 5.838290] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10751 22:58:03.957596 <3>[ 5.864862] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10752 22:58:03.963866 <6>[ 5.870663] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10753 22:58:03.971077 <6>[ 5.876913] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10754 22:58:03.980571 <6>[ 5.876950] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10755 22:58:03.987493 <6>[ 5.876958] remoteproc remoteproc0: remote processor scp is now up
10756 22:58:03.994042 <6>[ 5.901506] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10757 22:58:04.000836 <6>[ 5.903006] pci 0000:00:00.0: supports D1 D2
10758 22:58:04.007411 <6>[ 5.938724] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10759 22:58:04.013819 <6>[ 5.945594] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10760 22:58:04.023766 <6>[ 5.947100] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10761 22:58:04.030522 <6>[ 5.955997] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10762 22:58:04.037088 <6>[ 5.962723] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10763 22:58:04.043538 <6>[ 5.963782] usbcore: registered new interface driver btusb
10764 22:58:04.049960 <6>[ 5.968645] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10765 22:58:04.060345 <4>[ 5.968953] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10766 22:58:04.066624 <3>[ 5.968971] Bluetooth: hci0: Failed to load firmware file (-2)
10767 22:58:04.072973 <3>[ 5.968976] Bluetooth: hci0: Failed to set up firmware (-2)
10768 22:58:04.083377 <4>[ 5.968984] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10769 22:58:04.089919 <6>[ 5.977405] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10770 22:58:04.103419 <6>[ 5.985893] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10771 22:58:04.109437 <6>[ 5.994434] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10772 22:58:04.116248 <6>[ 5.994924] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10773 22:58:04.122423 <6>[ 6.000861] usbcore: registered new interface driver uvcvideo
10774 22:58:04.128989 <6>[ 6.009514] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10775 22:58:04.135895 <6>[ 6.183586] pci 0000:01:00.0: supports D1 D2
10776 22:58:04.142492 <6>[ 6.188105] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10777 22:58:04.159633 <6>[ 6.204223] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10778 22:58:04.166432 <6>[ 6.211117] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10779 22:58:04.173454 <6>[ 6.219196] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10780 22:58:04.183033 <6>[ 6.227194] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10781 22:58:04.189903 <6>[ 6.235194] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10782 22:58:04.199896 <6>[ 6.243195] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10783 22:58:04.203200 <6>[ 6.251194] pci 0000:00:00.0: PCI bridge to [bus 01]
10784 22:58:04.212913 <6>[ 6.256411] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10785 22:58:04.219243 <6>[ 6.264513] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10786 22:58:04.226530 <6>[ 6.271345] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10787 22:58:04.232488 <6>[ 6.278108] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10788 22:58:04.246642 <5>[ 6.291214] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10789 22:58:04.270084 <5>[ 6.314238] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10790 22:58:04.276254 <5>[ 6.321632] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10791 22:58:04.286232 <4>[ 6.330090] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10792 22:58:04.289664 <6>[ 6.338975] cfg80211: failed to load regulatory.db
10793 22:58:04.335021 <6>[ 6.379317] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10794 22:58:04.341884 <6>[ 6.386820] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10795 22:58:04.365569 <6>[ 6.413529] mt7921e 0000:01:00.0: ASIC revision: 79610010
10796 22:58:04.468172 <6>[ 6.512568] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10797 22:58:04.471810 <6>[ 6.512568]
10798 22:58:04.485811 Begin: Loading essential drivers ... done.
10799 22:58:04.489357 Begin: Running /scripts/init-premount ... done.
10800 22:58:04.496135 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10801 22:58:04.505706 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10802 22:58:04.509282 Device /sys/class/net/eth0 found
10803 22:58:04.509370 done.
10804 22:58:04.515854 Begin: Waiting up to 180 secs for any network device to become available ... done.
10805 22:58:04.557191 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10806 22:58:04.563628 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10807 22:58:04.569934 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10808 22:58:04.576822 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10809 22:58:04.583500 host : mt8192-asurada-spherion-r0-cbg-0
10810 22:58:04.590072 domain : lava-rack
10811 22:58:04.593151 rootserver: 192.168.201.1 rootpath:
10812 22:58:04.593236 filename :
10813 22:58:04.730123 done.
10814 22:58:04.739943 <6>[ 6.782901] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10815 22:58:04.743536 Begin: Running /scripts/nfs-bottom ... done.
10816 22:58:04.761362 Begin: Running /scripts/init-bottom ... done.
10817 22:58:06.071768 <6>[ 8.119902] NET: Registered PF_INET6 protocol family
10818 22:58:06.079717 <6>[ 8.127395] Segment Routing with IPv6
10819 22:58:06.083044 <6>[ 8.131390] In-situ OAM (IOAM) with IPv6
10820 22:58:06.248721 <30>[ 8.270465] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10821 22:58:06.255772 <30>[ 8.303589] systemd[1]: Detected architecture arm64.
10822 22:58:06.264089
10823 22:58:06.266862 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10824 22:58:06.266949
10825 22:58:06.267015
10826 22:58:06.294456 <30>[ 8.342188] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10827 22:58:07.220815 <30>[ 9.265439] systemd[1]: Queued start job for default target graphical.target.
10828 22:58:07.269008 <30>[ 9.313492] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10829 22:58:07.275555 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10830 22:58:07.275670
10831 22:58:07.297455 <30>[ 9.342237] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10832 22:58:07.307330 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10833 22:58:07.307443
10834 22:58:07.325305 <30>[ 9.370224] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10835 22:58:07.335550 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10836 22:58:07.335656
10837 22:58:07.353247 <30>[ 9.397819] systemd[1]: Created slice user.slice - User and Session Slice.
10838 22:58:07.359600 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10839 22:58:07.359691
10840 22:58:07.383696 <30>[ 9.425339] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10841 22:58:07.394165 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10842 22:58:07.394279
10843 22:58:07.411459 <30>[ 9.452719] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10844 22:58:07.417609 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10845 22:58:07.417709
10846 22:58:07.446142 <30>[ 9.481123] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10847 22:58:07.456358 <30>[ 9.501020] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10848 22:58:07.462944 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10849 22:58:07.463037
10850 22:58:07.479823 <30>[ 9.524477] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10851 22:58:07.486075 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10852 22:58:07.486169
10853 22:58:07.503520 <30>[ 9.548542] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10854 22:58:07.513758 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10855 22:58:07.513863
10856 22:58:07.528733 <30>[ 9.576594] systemd[1]: Reached target paths.target - Path Units.
10857 22:58:07.534924 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10858 22:58:07.538097
10859 22:58:07.556369 <30>[ 9.600931] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10860 22:58:07.562557 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10861 22:58:07.562654
10862 22:58:07.576207 <30>[ 9.624468] systemd[1]: Reached target slices.target - Slice Units.
10863 22:58:07.586512 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10864 22:58:07.586604
10865 22:58:07.600796 <30>[ 9.648974] systemd[1]: Reached target swap.target - Swaps.
10866 22:58:07.607642 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10867 22:58:07.607732
10868 22:58:07.628271 <30>[ 9.672980] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10869 22:58:07.638026 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10870 22:58:07.638127
10871 22:58:07.656451 <30>[ 9.700972] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10872 22:58:07.666241 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10873 22:58:07.666345
10874 22:58:07.685603 <30>[ 9.730538] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10875 22:58:07.695477 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10876 22:58:07.695582
10877 22:58:07.712980 <30>[ 9.757760] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10878 22:58:07.723262 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10879 22:58:07.723358
10880 22:58:07.740511 <30>[ 9.785083] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10881 22:58:07.746833 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10882 22:58:07.746920
10883 22:58:07.765494 <30>[ 9.809889] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10884 22:58:07.774953 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10885 22:58:07.775042
10886 22:58:07.794885 <30>[ 9.839528] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10887 22:58:07.804579 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10888 22:58:07.804672
10889 22:58:07.820124 <30>[ 9.864954] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10890 22:58:07.830169 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10891 22:58:07.830260
10892 22:58:07.884102 <30>[ 9.928730] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10893 22:58:07.890704 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10894 22:58:07.890801
10895 22:58:07.912194 <30>[ 9.957194] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10896 22:58:07.919102 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10897 22:58:07.919195
10898 22:58:07.967860 <30>[ 10.012865] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10899 22:58:07.974465 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10900 22:58:07.974564
10901 22:58:08.003000 <30>[ 10.041040] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10902 22:58:08.017485 <30>[ 10.062506] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10903 22:58:08.027269 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10904 22:58:08.027371
10905 22:58:08.049233 <30>[ 10.094140] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10906 22:58:08.055725 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10907 22:58:08.055814
10908 22:58:08.111915 <30>[ 10.156950] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10909 22:58:08.118727 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10910 22:58:08.118824
10911 22:58:08.145454 <30>[ 10.190258] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10912 22:58:08.158725 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 10.202394] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10913 22:58:08.162080 l Module drm...
10914 22:58:08.162160
10915 22:58:08.182379 <30>[ 10.226851] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10916 22:58:08.188661 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10917 22:58:08.191886
10918 22:58:08.248255 <30>[ 10.293251] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10919 22:58:08.255310 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10920 22:58:08.255419
10921 22:58:08.281458 <30>[ 10.326302] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10922 22:58:08.287892 Startin<6>[ 10.335272] fuse: init (API version 7.37)
10923 22:58:08.294557 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10924 22:58:08.294637
10925 22:58:08.336432 <30>[ 10.381418] systemd[1]: Starting systemd-journald.service - Journal Service...
10926 22:58:08.343295 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10927 22:58:08.343380
10928 22:58:08.374686 <30>[ 10.419592] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10929 22:58:08.381186 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10930 22:58:08.381274
10931 22:58:08.407736 <30>[ 10.449261] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10932 22:58:08.414512 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10933 22:58:08.414601
10934 22:58:08.437298 <30>[ 10.481673] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10935 22:58:08.446909 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10936 22:58:08.446997
10937 22:58:08.468992 <30>[ 10.513375] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10938 22:58:08.485814 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices..<3>[ 10.528881] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 22:58:08.485909 .
10940 22:58:08.486001
10941 22:58:08.510121 <30>[ 10.554659] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10942 22:58:08.517015 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10943 22:58:08.517109
10944 22:58:08.526888 <3>[ 10.569494] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 22:58:08.536776 <30>[ 10.581036] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10946 22:58:08.543518 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10947 22:58:08.543602
10948 22:58:08.560182 <30>[ 10.605322] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10949 22:58:08.567405 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10950 22:58:08.567490
10951 22:58:08.585849 <3>[ 10.630600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 22:58:08.595491 <30>[ 10.640587] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10953 22:58:08.605715 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10954 22:58:08.605800
10955 22:58:08.624915 <30>[ 10.669422] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10956 22:58:08.631571 <30>[ 10.677278] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10957 22:58:08.641093 <3>[ 10.685977] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 22:58:08.651076 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10959 22:58:08.651164
10960 22:58:08.669560 <30>[ 10.714257] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10961 22:58:08.676604 <30>[ 10.722412] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10962 22:58:08.686004 [[0;32m OK [<3>[ 10.731240] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 22:58:08.696086 0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10964 22:58:08.696179
10965 22:58:08.713054 <30>[ 10.757786] systemd[1]: modprobe@drm.service: Deactivated successfully.
10966 22:58:08.719682 <3>[ 10.762054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 22:58:08.729906 <30>[ 10.765419] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10968 22:58:08.736212 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10969 22:58:08.736293
10970 22:58:08.750558 <3>[ 10.795410] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 22:58:08.761628 <30>[ 10.806172] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10972 22:58:08.772434 <30>[ 10.814465] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10973 22:58:08.782339 [[0;32m OK [<3>[ 10.824823] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 22:58:08.788586 0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10975 22:58:08.788673
10976 22:58:08.810476 <30>[ 10.854958] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10977 22:58:08.816961 <3>[ 10.855078] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 22:58:08.826790 <30>[ 10.862950] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10979 22:58:08.833169 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10980 22:58:08.833247
10981 22:58:08.850185 <3>[ 10.894804] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 22:58:08.856786 <3>[ 10.895614] power_supply sbs-5-000b: driver failed to report `status' property: -6
10983 22:58:08.874289 <4>[ 10.911427] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10984 22:58:08.880963 <30>[ 10.913096] systemd[1]: modprobe@loop.service: Deactivated successfully.
10985 22:58:08.891413 <3>[ 10.924165] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 22:58:08.898452 <3>[ 10.927056] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10987 22:58:08.904937 <3>[ 10.944745] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 22:58:08.915089 <30>[ 10.951432] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10989 22:58:08.921284 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10990 22:58:08.921365
10991 22:58:08.936861 <3>[ 10.981917] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 22:58:08.947081 <30>[ 10.991779] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10993 22:58:08.953717 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10994 22:58:08.953799
10995 22:58:08.968902 <3>[ 11.013458] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 22:58:08.981903 <30>[ 11.023158] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10997 22:58:08.988765 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10998 22:58:08.988847
10999 22:58:09.001138 <3>[ 11.046032] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 22:58:09.011123 <30>[ 11.055741] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
11001 22:58:09.021133 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11002 22:58:09.021220
11003 22:58:09.040541 <30>[ 11.085252] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
11004 22:58:09.047603 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11005 22:58:09.047690
11006 22:58:09.069339 <30>[ 11.113680] systemd[1]: Reached target network-pre.target - Preparation for Network.
11007 22:58:09.075607 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11008 22:58:09.075692
11009 22:58:09.140326 <30>[ 11.184944] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
11010 22:58:09.146931 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11011 22:58:09.147027
11012 22:58:09.173152 <30>[ 11.217637] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
11013 22:58:09.179653 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11014 22:58:09.179738
11015 22:58:09.203159 <30>[ 11.244719] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
11016 22:58:09.220043 <30>[ 11.258369] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
11017 22:58:09.264517 <30>[ 11.309228] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
11018 22:58:09.270950 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11019 22:58:09.271043
11020 22:58:09.297251 <30>[ 11.338531] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
11021 22:58:09.309211 <30>[ 11.353956] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
11022 22:58:09.315302 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11023 22:58:09.315387
11024 22:58:09.343076 <30>[ 11.387768] systemd[1]: Starting systemd-sysusers.service - Create System Users...
11025 22:58:09.349993 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11026 22:58:09.350094
11027 22:58:09.379412 <30>[ 11.424354] systemd[1]: Started systemd-journald.service - Journal Service.
11028 22:58:09.386121 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11029 22:58:09.386274
11030 22:58:09.409163 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11031 22:58:09.409327
11032 22:58:09.428252 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11033 22:58:09.428403
11034 22:58:09.449226 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11035 22:58:09.449382
11036 22:58:09.468924 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11037 22:58:09.469046
11038 22:58:09.489548 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11039 22:58:09.489675
11040 22:58:09.541157 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11041 22:58:09.541292
11042 22:58:09.563839 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11043 22:58:09.564007
11044 22:58:09.593010 <46>[ 11.637766] systemd-journald[305]: Received client request to flush runtime journal.
11045 22:58:10.360687 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11046 22:58:10.360835
11047 22:58:10.380070 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11048 22:58:10.380219
11049 22:58:10.399979 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11050 22:58:10.400140
11051 22:58:10.700425 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11052 22:58:10.700574
11053 22:58:11.000548 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11054 22:58:11.000696
11055 22:58:11.042238 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11056 22:58:11.042413
11057 22:58:11.174091 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11058 22:58:11.174240
11059 22:58:11.239689 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11060 22:58:11.239846
11061 22:58:11.274302 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11062 22:58:11.274423
11063 22:58:11.578385 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11064 22:58:11.578611
11065 22:58:11.588045 <6>[ 13.636717] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11066 22:58:11.629295 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11067 22:58:11.629839
11068 22:58:11.690552 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11069 22:58:11.690694
11070 22:58:11.733098 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11071 22:58:11.733235
11072 22:58:11.789439 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11073 22:58:11.792667
11074 22:58:11.817215 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11075 22:58:11.817330
11076 22:58:11.841318 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11077 22:58:11.841459
11078 22:58:11.864201 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11079 22:58:11.864310
11080 22:58:11.887792 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11081 22:58:11.887934
11082 22:58:11.911447 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11083 22:58:11.911588
11084 22:58:11.968687 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11085 22:58:11.968809
11086 22:58:11.993590 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11087 22:58:11.993739
11088 22:58:12.032673 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11089 22:58:12.032784
11090 22:58:12.110783 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11091 22:58:12.110923
11092 22:58:12.134000 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11093 22:58:12.134130
11094 22:58:12.155593 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11095 22:58:12.155732
11096 22:58:12.176178 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11097 22:58:12.176290
11098 22:58:12.201575 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11099 22:58:12.201679
11100 22:58:12.222689 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11101 22:58:12.222779
11102 22:58:12.240399 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11103 22:58:12.240489
11104 22:58:12.259907 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11105 22:58:12.260036
11106 22:58:12.280442 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11107 22:58:12.280579
11108 22:58:12.298564 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11109 22:58:12.298669
11110 22:58:12.316923 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11111 22:58:12.317027
11112 22:58:12.335648 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11113 22:58:12.335765
11114 22:58:12.353186 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11115 22:58:12.353289
11116 22:58:12.410837 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11117 22:58:12.411027
11118 22:58:12.503876 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11119 22:58:12.504038
11120 22:58:12.601549 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11121 22:58:12.601700
11122 22:58:12.623088 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11123 22:58:12.623189
11124 22:58:12.777942 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11125 22:58:12.778089
11126 22:58:12.827282 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11127 22:58:12.827432
11128 22:58:12.851961 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11129 22:58:12.852115
11130 22:58:12.863047 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11131 22:58:12.863226
11132 22:58:12.886311 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11133 22:58:12.886474
11134 22:58:12.912448 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11135 22:58:12.912710
11136 22:58:12.933706 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11137 22:58:12.933805
11138 22:58:12.955733 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11139 22:58:12.955867
11140 22:58:12.975094 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11141 22:58:12.975206
11142 22:58:13.042304 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11143 22:58:13.042462
11144 22:58:13.083048 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11145 22:58:13.083199
11146 22:58:13.138003
11147 22:58:13.138147
11148 22:58:13.141059 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11149 22:58:13.141144
11150 22:58:13.144216 debian-bookworm-arm64 login: root (automatic login)
11151 22:58:13.144302
11152 22:58:13.144369
11153 22:58:13.422932 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
11154 22:58:13.423102
11155 22:58:13.429841 The programs included with the Debian GNU/Linux system are free software;
11156 22:58:13.436258 the exact distribution terms for each program are described in the
11157 22:58:13.439670 individual files in /usr/share/doc/*/copyright.
11158 22:58:13.439770
11159 22:58:13.446809 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11160 22:58:13.449402 permitted by applicable law.
11161 22:58:14.305550 Matched prompt #10: / #
11163 22:58:14.305959 Setting prompt string to ['/ #']
11164 22:58:14.306110 end: 2.2.5.1 login-action (duration 00:00:17) [common]
11166 22:58:14.306434 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
11167 22:58:14.306582 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
11168 22:58:14.306699 Setting prompt string to ['/ #']
11169 22:58:14.306799 Forcing a shell prompt, looking for ['/ #']
11171 22:58:14.357080 / #
11172 22:58:14.357231 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11173 22:58:14.357342 Waiting using forced prompt support (timeout 00:02:30)
11174 22:58:14.361999
11175 22:58:14.362310 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11176 22:58:14.362444 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
11178 22:58:14.462819 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683713/extract-nfsrootfs-x5eqj7ae'
11179 22:58:14.468480 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683713/extract-nfsrootfs-x5eqj7ae'
11181 22:58:14.569094 / # export NFS_SERVER_IP='192.168.201.1'
11182 22:58:14.575313 export NFS_SERVER_IP='192.168.201.1'
11183 22:58:14.575604 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11184 22:58:14.575707 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
11185 22:58:14.575808 end: 2 depthcharge-action (duration 00:01:16) [common]
11186 22:58:14.575899 start: 3 lava-test-retry (timeout 00:08:06) [common]
11187 22:58:14.576000 start: 3.1 lava-test-shell (timeout 00:08:06) [common]
11188 22:58:14.576079 Using namespace: common
11190 22:58:14.676427 / # #
11191 22:58:14.676585 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11192 22:58:14.682925 #
11193 22:58:14.683193 Using /lava-13683713
11195 22:58:14.783504 / # export SHELL=/bin/bash
11196 22:58:14.790328 export SHELL=/bin/bash
11198 22:58:14.890860 / # . /lava-13683713/environment
11199 22:58:14.896732 . /lava-13683713/environment
11201 22:58:15.001495 / # /lava-13683713/bin/lava-test-runner /lava-13683713/0
11202 22:58:15.001622 Test shell timeout: 10s (minimum of the action and connection timeout)
11203 22:58:15.007508 /lava-13683713/bin/lava-test-runner /lava-13683713/0
11204 22:58:15.199934 + export TESTRUN_ID=0_timesync-off
11205 22:58:15.203045 + TESTRUN_ID=0_timesync-off
11206 22:58:15.206843 + cd /lava-13683713/0/tests/0_timesync-off
11207 22:58:15.209879 ++ cat uuid
11208 22:58:15.209967 + UUID=13683713_1.6.2.3.1
11209 22:58:15.213304 + set +x
11210 22:58:15.216289 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13683713_1.6.2.3.1>
11211 22:58:15.216557 Received signal: <STARTRUN> 0_timesync-off 13683713_1.6.2.3.1
11212 22:58:15.216665 Starting test lava.0_timesync-off (13683713_1.6.2.3.1)
11213 22:58:15.216777 Skipping test definition patterns.
11214 22:58:15.219801 + systemctl stop systemd-timesyncd
11215 22:58:15.283667 + set +x
11216 22:58:15.286960 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13683713_1.6.2.3.1>
11217 22:58:15.287225 Received signal: <ENDRUN> 0_timesync-off 13683713_1.6.2.3.1
11218 22:58:15.287317 Ending use of test pattern.
11219 22:58:15.287393 Ending test lava.0_timesync-off (13683713_1.6.2.3.1), duration 0.07
11221 22:58:15.341425 + export TESTRUN_ID=1_kselftest-alsa
11222 22:58:15.344223 + TESTRUN_ID=1_kselftest-alsa
11223 22:58:15.347674 + cd /lava-13683713/0/tests/1_kselftest-alsa
11224 22:58:15.351397 ++ cat uuid
11225 22:58:15.354474 + UUID=13683713_1.6.2.3.5
11226 22:58:15.354561 + set +x
11227 22:58:15.357673 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 13683713_1.6.2.3.5>
11228 22:58:15.357935 Received signal: <STARTRUN> 1_kselftest-alsa 13683713_1.6.2.3.5
11229 22:58:15.358015 Starting test lava.1_kselftest-alsa (13683713_1.6.2.3.5)
11230 22:58:15.358124 Skipping test definition patterns.
11231 22:58:15.361112 + cd ./automated/linux/kselftest/
11232 22:58:15.387433 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11233 22:58:15.414087 INFO: install_deps skipped
11234 22:58:15.895572 --2024-05-07 22:53:52-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11235 22:58:15.901836 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11236 22:58:16.020178 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11237 22:58:16.144707 HTTP request sent, awaiting response... 200 OK
11238 22:58:16.147873 Length: 1651624 (1.6M) [application/octet-stream]
11239 22:58:16.151158 Saving to: 'kselftest_armhf.tar.gz'
11240 22:58:16.151244
11241 22:58:16.151331
11242 22:58:16.392917 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11243 22:58:16.641445 kselftest_armhf.tar 2%[ ] 47.81K 198KB/s
11244 22:58:16.936758 kselftest_armhf.tar 13%[=> ] 217.50K 448KB/s
11245 22:58:17.066023 kselftest_armhf.tar 51%[=========> ] 824.13K 1.04MB/s
11246 22:58:17.072504 kselftest_armhf.tar 100%[===================>] 1.57M 1.75MB/s in 0.9s
11247 22:58:17.072624
11248 22:58:17.217167 2024-05-07 22:53:53 (1.75 MB/s) - 'kselftest_armhf.tar.gz' saved [1651624/1651624]
11249 22:58:17.217356
11250 22:58:21.119403 skiplist:
11251 22:58:21.122753 ========================================
11252 22:58:21.126070 ========================================
11253 22:58:21.166407 alsa:mixer-test
11254 22:58:21.186326 ============== Tests to run ===============
11255 22:58:21.186463 alsa:mixer-test
11256 22:58:21.189653 ===========End Tests to run ===============
11257 22:58:21.193275 shardfile-alsa pass
11258 22:58:21.288742 <12>[ 23.338189] kselftest: Running tests in alsa
11259 22:58:21.297810 TAP version 13
11260 22:58:21.310200 1..1
11261 22:58:21.323078 # selftests: alsa: mixer-test
11262 22:58:21.813709 # TAP version 13
11263 22:58:21.813863 # 1..0
11264 22:58:21.819836 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11265 22:58:21.823048 ok 1 selftests: alsa: mixer-test
11266 22:58:23.247301 alsa_mixer-test pass
11267 22:58:23.325419 + ../../utils/send-to-lava.sh ./output/result.txt
11268 22:58:23.381697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11269 22:58:23.382068 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11271 22:58:23.423610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11272 22:58:23.423775 + set +x
11273 22:58:23.424054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11275 22:58:23.430193 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 13683713_1.6.2.3.5>
11276 22:58:23.430478 Received signal: <ENDRUN> 1_kselftest-alsa 13683713_1.6.2.3.5
11277 22:58:23.430583 Ending use of test pattern.
11278 22:58:23.430673 Ending test lava.1_kselftest-alsa (13683713_1.6.2.3.5), duration 8.07
11280 22:58:23.433384 <LAVA_TEST_RUNNER EXIT>
11281 22:58:23.433664 ok: lava_test_shell seems to have completed
11282 22:58:23.433804 alsa_mixer-test: pass
shardfile-alsa: pass
11283 22:58:23.433926 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11284 22:58:23.434049 end: 3 lava-test-retry (duration 00:00:09) [common]
11285 22:58:23.434172 start: 4 finalize (timeout 00:07:57) [common]
11286 22:58:23.434298 start: 4.1 power-off (timeout 00:00:30) [common]
11287 22:58:23.434533 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11288 22:58:23.510526 >> Command sent successfully.
11289 22:58:23.512799 Returned 0 in 0 seconds
11290 22:58:23.613206 end: 4.1 power-off (duration 00:00:00) [common]
11292 22:58:23.613653 start: 4.2 read-feedback (timeout 00:07:57) [common]
11293 22:58:23.613980 Listened to connection for namespace 'common' for up to 1s
11294 22:58:24.614895 Finalising connection for namespace 'common'
11295 22:58:24.615118 Disconnecting from shell: Finalise
11296 22:58:24.615235 / #
11297 22:58:24.715580 end: 4.2 read-feedback (duration 00:00:01) [common]
11298 22:58:24.715827 end: 4 finalize (duration 00:00:01) [common]
11299 22:58:24.716057 Cleaning after the job
11300 22:58:24.716253 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/ramdisk
11301 22:58:24.719222 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/kernel
11302 22:58:24.730628 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/dtb
11303 22:58:24.730977 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/nfsrootfs
11304 22:58:24.794470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683713/tftp-deploy-vrtot5ad/modules
11305 22:58:24.800304 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683713
11306 22:58:25.352664 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683713
11307 22:58:25.352849 Job finished correctly