Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
1 22:51:57.300942 lava-dispatcher, installed at version: 2024.01
2 22:51:57.301151 start: 0 validate
3 22:51:57.301279 Start time: 2024-05-07 22:51:57.301271+00:00 (UTC)
4 22:51:57.301414 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:51:57.301545 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:51:57.553723 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:51:57.553895 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:51:57.812655 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:51:57.812818 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:51:58.071491 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:51:58.071670 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:51:58.328868 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:51:58.329052 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:51:58.579844 validate duration: 1.28
16 22:51:58.580117 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:51:58.580211 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:51:58.580294 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:51:58.580418 Not decompressing ramdisk as can be used compressed.
20 22:51:58.580501 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:51:58.580563 saving as /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/ramdisk/initrd.cpio.gz
22 22:51:58.580629 total size: 5628169 (5 MB)
23 22:51:58.581784 progress 0 % (0 MB)
24 22:51:58.583545 progress 5 % (0 MB)
25 22:51:58.585068 progress 10 % (0 MB)
26 22:51:58.586474 progress 15 % (0 MB)
27 22:51:58.588027 progress 20 % (1 MB)
28 22:51:58.589505 progress 25 % (1 MB)
29 22:51:58.591149 progress 30 % (1 MB)
30 22:51:58.592646 progress 35 % (1 MB)
31 22:51:58.593979 progress 40 % (2 MB)
32 22:51:58.595608 progress 45 % (2 MB)
33 22:51:58.596948 progress 50 % (2 MB)
34 22:51:58.598500 progress 55 % (2 MB)
35 22:51:58.600060 progress 60 % (3 MB)
36 22:51:58.601400 progress 65 % (3 MB)
37 22:51:58.602960 progress 70 % (3 MB)
38 22:51:58.604307 progress 75 % (4 MB)
39 22:51:58.605791 progress 80 % (4 MB)
40 22:51:58.607252 progress 85 % (4 MB)
41 22:51:58.608748 progress 90 % (4 MB)
42 22:51:58.610318 progress 95 % (5 MB)
43 22:51:58.611709 progress 100 % (5 MB)
44 22:51:58.611919 5 MB downloaded in 0.03 s (171.55 MB/s)
45 22:51:58.612075 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:51:58.612312 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:51:58.612398 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:51:58.612482 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:51:58.612619 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:51:58.612687 saving as /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/kernel/Image
52 22:51:58.612749 total size: 54682112 (52 MB)
53 22:51:58.612811 No compression specified
54 22:51:58.613957 progress 0 % (0 MB)
55 22:51:58.628064 progress 5 % (2 MB)
56 22:51:58.641958 progress 10 % (5 MB)
57 22:51:58.655934 progress 15 % (7 MB)
58 22:51:58.669830 progress 20 % (10 MB)
59 22:51:58.683670 progress 25 % (13 MB)
60 22:51:58.697372 progress 30 % (15 MB)
61 22:51:58.711260 progress 35 % (18 MB)
62 22:51:58.725075 progress 40 % (20 MB)
63 22:51:58.738999 progress 45 % (23 MB)
64 22:51:58.752962 progress 50 % (26 MB)
65 22:51:58.766839 progress 55 % (28 MB)
66 22:51:58.780724 progress 60 % (31 MB)
67 22:51:58.794364 progress 65 % (33 MB)
68 22:51:58.808205 progress 70 % (36 MB)
69 22:51:58.821869 progress 75 % (39 MB)
70 22:51:58.835870 progress 80 % (41 MB)
71 22:51:58.849996 progress 85 % (44 MB)
72 22:51:58.863846 progress 90 % (46 MB)
73 22:51:58.878078 progress 95 % (49 MB)
74 22:51:58.891683 progress 100 % (52 MB)
75 22:51:58.891939 52 MB downloaded in 0.28 s (186.79 MB/s)
76 22:51:58.892092 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:51:58.892323 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:51:58.892408 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:51:58.892496 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:51:58.892631 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:51:58.892699 saving as /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/dtb/mt8192-asurada-spherion-r0.dtb
83 22:51:58.892759 total size: 47258 (0 MB)
84 22:51:58.892820 No compression specified
85 22:51:58.893911 progress 69 % (0 MB)
86 22:51:58.894212 progress 100 % (0 MB)
87 22:51:58.894368 0 MB downloaded in 0.00 s (28.06 MB/s)
88 22:51:58.894489 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:51:58.894708 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:51:58.894792 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:51:58.894875 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:51:58.894989 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:51:58.895056 saving as /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/nfsrootfs/full.rootfs.tar
95 22:51:58.895116 total size: 120894716 (115 MB)
96 22:51:58.895177 Using unxz to decompress xz
97 22:51:58.899181 progress 0 % (0 MB)
98 22:51:59.241395 progress 5 % (5 MB)
99 22:51:59.592772 progress 10 % (11 MB)
100 22:51:59.940981 progress 15 % (17 MB)
101 22:52:00.280280 progress 20 % (23 MB)
102 22:52:00.575814 progress 25 % (28 MB)
103 22:52:00.929085 progress 30 % (34 MB)
104 22:52:01.262883 progress 35 % (40 MB)
105 22:52:01.428346 progress 40 % (46 MB)
106 22:52:01.603903 progress 45 % (51 MB)
107 22:52:01.915988 progress 50 % (57 MB)
108 22:52:02.285492 progress 55 % (63 MB)
109 22:52:02.626810 progress 60 % (69 MB)
110 22:52:02.962453 progress 65 % (74 MB)
111 22:52:03.296790 progress 70 % (80 MB)
112 22:52:03.644385 progress 75 % (86 MB)
113 22:52:03.980350 progress 80 % (92 MB)
114 22:52:04.311171 progress 85 % (98 MB)
115 22:52:04.658354 progress 90 % (103 MB)
116 22:52:04.980775 progress 95 % (109 MB)
117 22:52:05.328042 progress 100 % (115 MB)
118 22:52:05.333518 115 MB downloaded in 6.44 s (17.91 MB/s)
119 22:52:05.333799 end: 1.4.1 http-download (duration 00:00:06) [common]
121 22:52:05.334099 end: 1.4 download-retry (duration 00:00:06) [common]
122 22:52:05.334190 start: 1.5 download-retry (timeout 00:09:53) [common]
123 22:52:05.334276 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 22:52:05.334422 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:52:05.334488 saving as /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/modules/modules.tar
126 22:52:05.334549 total size: 8594396 (8 MB)
127 22:52:05.334612 Using unxz to decompress xz
128 22:52:05.338716 progress 0 % (0 MB)
129 22:52:05.357203 progress 5 % (0 MB)
130 22:52:05.381125 progress 10 % (0 MB)
131 22:52:05.404732 progress 15 % (1 MB)
132 22:52:05.427177 progress 20 % (1 MB)
133 22:52:05.451626 progress 25 % (2 MB)
134 22:52:05.474637 progress 30 % (2 MB)
135 22:52:05.497755 progress 35 % (2 MB)
136 22:52:05.522522 progress 40 % (3 MB)
137 22:52:05.547563 progress 45 % (3 MB)
138 22:52:05.571474 progress 50 % (4 MB)
139 22:52:05.595110 progress 55 % (4 MB)
140 22:52:05.619951 progress 60 % (4 MB)
141 22:52:05.644558 progress 65 % (5 MB)
142 22:52:05.668970 progress 70 % (5 MB)
143 22:52:05.692109 progress 75 % (6 MB)
144 22:52:05.716468 progress 80 % (6 MB)
145 22:52:05.741193 progress 85 % (6 MB)
146 22:52:05.769464 progress 90 % (7 MB)
147 22:52:05.797274 progress 95 % (7 MB)
148 22:52:05.822393 progress 100 % (8 MB)
149 22:52:05.827373 8 MB downloaded in 0.49 s (16.63 MB/s)
150 22:52:05.827643 end: 1.5.1 http-download (duration 00:00:00) [common]
152 22:52:05.827907 end: 1.5 download-retry (duration 00:00:00) [common]
153 22:52:05.828000 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 22:52:05.828094 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 22:52:09.210235 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13683711/extract-nfsrootfs-_8ka395z
156 22:52:09.210427 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:52:09.210532 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 22:52:09.210699 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj
159 22:52:09.210827 makedir: /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin
160 22:52:09.210928 makedir: /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/tests
161 22:52:09.211025 makedir: /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/results
162 22:52:09.211128 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-add-keys
163 22:52:09.211271 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-add-sources
164 22:52:09.211400 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-background-process-start
165 22:52:09.211527 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-background-process-stop
166 22:52:09.211653 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-common-functions
167 22:52:09.211777 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-echo-ipv4
168 22:52:09.211902 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-install-packages
169 22:52:09.212027 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-installed-packages
170 22:52:09.212152 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-os-build
171 22:52:09.212276 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-probe-channel
172 22:52:09.212400 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-probe-ip
173 22:52:09.212524 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-target-ip
174 22:52:09.212648 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-target-mac
175 22:52:09.212771 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-target-storage
176 22:52:09.212941 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-test-case
177 22:52:09.213068 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-test-event
178 22:52:09.213192 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-test-feedback
179 22:52:09.213315 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-test-raise
180 22:52:09.213438 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-test-reference
181 22:52:09.213562 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-test-runner
182 22:52:09.213684 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-test-set
183 22:52:09.213805 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-test-shell
184 22:52:09.213929 Updating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-add-keys (debian)
185 22:52:09.214126 Updating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-add-sources (debian)
186 22:52:09.214264 Updating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-install-packages (debian)
187 22:52:09.214399 Updating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-installed-packages (debian)
188 22:52:09.214533 Updating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/bin/lava-os-build (debian)
189 22:52:09.214651 Creating /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/environment
190 22:52:09.214745 LAVA metadata
191 22:52:09.214814 - LAVA_JOB_ID=13683711
192 22:52:09.214876 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:52:09.214975 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 22:52:09.215041 skipped lava-vland-overlay
195 22:52:09.215114 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:52:09.215191 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 22:52:09.215263 skipped lava-multinode-overlay
198 22:52:09.215335 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:52:09.215412 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 22:52:09.215484 Loading test definitions
201 22:52:09.215569 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 22:52:09.215639 Using /lava-13683711 at stage 0
203 22:52:09.215917 uuid=13683711_1.6.2.3.1 testdef=None
204 22:52:09.216004 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:52:09.216086 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 22:52:09.216535 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:52:09.216753 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 22:52:09.217297 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:52:09.217523 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 22:52:09.218146 runner path: /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/0/tests/0_timesync-off test_uuid 13683711_1.6.2.3.1
213 22:52:09.218304 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:52:09.218623 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 22:52:09.218696 Using /lava-13683711 at stage 0
217 22:52:09.218792 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:52:09.218877 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/0/tests/1_kselftest-arm64'
219 22:52:11.324088 Running '/usr/bin/git checkout kernelci.org
220 22:52:11.470019 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 22:52:11.470800 uuid=13683711_1.6.2.3.5 testdef=None
222 22:52:11.470954 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 22:52:11.471201 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 22:52:11.471931 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:52:11.472156 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 22:52:11.473094 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:52:11.473321 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 22:52:11.474302 runner path: /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/0/tests/1_kselftest-arm64 test_uuid 13683711_1.6.2.3.5
232 22:52:11.474392 BOARD='mt8192-asurada-spherion-r0'
233 22:52:11.474455 BRANCH='cip'
234 22:52:11.474514 SKIPFILE='/dev/null'
235 22:52:11.474571 SKIP_INSTALL='True'
236 22:52:11.474628 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:52:11.474687 TST_CASENAME=''
238 22:52:11.474742 TST_CMDFILES='arm64'
239 22:52:11.474879 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:52:11.475083 Creating lava-test-runner.conf files
242 22:52:11.475146 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683711/lava-overlay-l5d830gj/lava-13683711/0 for stage 0
243 22:52:11.475235 - 0_timesync-off
244 22:52:11.475303 - 1_kselftest-arm64
245 22:52:11.475399 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 22:52:11.475484 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 22:52:19.041423 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:52:19.041582 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 22:52:19.041675 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:52:19.041799 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 22:52:19.041932 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 22:52:19.206290 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:52:19.206684 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 22:52:19.206794 extracting modules file /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683711/extract-nfsrootfs-_8ka395z
255 22:52:19.419852 extracting modules file /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683711/extract-overlay-ramdisk-sn41gcoe/ramdisk
256 22:52:19.637576 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:52:19.637745 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 22:52:19.637837 [common] Applying overlay to NFS
259 22:52:19.637907 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683711/compress-overlay-6wqs7uda/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683711/extract-nfsrootfs-_8ka395z
260 22:52:20.548527 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:52:20.548699 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 22:52:20.548800 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:52:20.548888 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 22:52:20.548969 Building ramdisk /var/lib/lava/dispatcher/tmp/13683711/extract-overlay-ramdisk-sn41gcoe/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683711/extract-overlay-ramdisk-sn41gcoe/ramdisk
265 22:52:20.896279 >> 130327 blocks
266 22:52:22.909845 rename /var/lib/lava/dispatcher/tmp/13683711/extract-overlay-ramdisk-sn41gcoe/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/ramdisk/ramdisk.cpio.gz
267 22:52:22.910302 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:52:22.910423 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 22:52:22.910528 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 22:52:22.910631 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/kernel/Image'
271 22:52:35.976524 Returned 0 in 13 seconds
272 22:52:36.077218 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/kernel/image.itb
273 22:52:36.449413 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:52:36.449801 output: Created: Tue May 7 23:52:36 2024
275 22:52:36.449878 output: Image 0 (kernel-1)
276 22:52:36.449942 output: Description:
277 22:52:36.450007 output: Created: Tue May 7 23:52:36 2024
278 22:52:36.450110 output: Type: Kernel Image
279 22:52:36.450171 output: Compression: lzma compressed
280 22:52:36.450231 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
281 22:52:36.450289 output: Architecture: AArch64
282 22:52:36.450346 output: OS: Linux
283 22:52:36.450404 output: Load Address: 0x00000000
284 22:52:36.450463 output: Entry Point: 0x00000000
285 22:52:36.450519 output: Hash algo: crc32
286 22:52:36.450576 output: Hash value: 727ee7c6
287 22:52:36.450630 output: Image 1 (fdt-1)
288 22:52:36.450686 output: Description: mt8192-asurada-spherion-r0
289 22:52:36.450739 output: Created: Tue May 7 23:52:36 2024
290 22:52:36.450792 output: Type: Flat Device Tree
291 22:52:36.450845 output: Compression: uncompressed
292 22:52:36.450897 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 22:52:36.450950 output: Architecture: AArch64
294 22:52:36.451003 output: Hash algo: crc32
295 22:52:36.451055 output: Hash value: 0f8e4d2e
296 22:52:36.451109 output: Image 2 (ramdisk-1)
297 22:52:36.451161 output: Description: unavailable
298 22:52:36.451214 output: Created: Tue May 7 23:52:36 2024
299 22:52:36.451267 output: Type: RAMDisk Image
300 22:52:36.451319 output: Compression: Unknown Compression
301 22:52:36.451372 output: Data Size: 18724700 Bytes = 18285.84 KiB = 17.86 MiB
302 22:52:36.451424 output: Architecture: AArch64
303 22:52:36.451476 output: OS: Linux
304 22:52:36.451528 output: Load Address: unavailable
305 22:52:36.451580 output: Entry Point: unavailable
306 22:52:36.451632 output: Hash algo: crc32
307 22:52:36.451684 output: Hash value: 2879e9cf
308 22:52:36.451737 output: Default Configuration: 'conf-1'
309 22:52:36.451789 output: Configuration 0 (conf-1)
310 22:52:36.451841 output: Description: mt8192-asurada-spherion-r0
311 22:52:36.451893 output: Kernel: kernel-1
312 22:52:36.451945 output: Init Ramdisk: ramdisk-1
313 22:52:36.451998 output: FDT: fdt-1
314 22:52:36.452050 output: Loadables: kernel-1
315 22:52:36.452103 output:
316 22:52:36.452303 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 22:52:36.452402 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 22:52:36.452504 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 22:52:36.452606 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 22:52:36.452687 No LXC device requested
321 22:52:36.452766 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:52:36.452852 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 22:52:36.452930 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:52:36.452999 Checking files for TFTP limit of 4294967296 bytes.
325 22:52:36.453497 end: 1 tftp-deploy (duration 00:00:38) [common]
326 22:52:36.453603 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:52:36.453694 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:52:36.453827 substitutions:
329 22:52:36.453897 - {DTB}: 13683711/tftp-deploy-rojg5qzj/dtb/mt8192-asurada-spherion-r0.dtb
330 22:52:36.453963 - {INITRD}: 13683711/tftp-deploy-rojg5qzj/ramdisk/ramdisk.cpio.gz
331 22:52:36.454044 - {KERNEL}: 13683711/tftp-deploy-rojg5qzj/kernel/Image
332 22:52:36.454119 - {LAVA_MAC}: None
333 22:52:36.454177 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13683711/extract-nfsrootfs-_8ka395z
334 22:52:36.454233 - {NFS_SERVER_IP}: 192.168.201.1
335 22:52:36.454288 - {PRESEED_CONFIG}: None
336 22:52:36.454343 - {PRESEED_LOCAL}: None
337 22:52:36.454397 - {RAMDISK}: 13683711/tftp-deploy-rojg5qzj/ramdisk/ramdisk.cpio.gz
338 22:52:36.454451 - {ROOT_PART}: None
339 22:52:36.454505 - {ROOT}: None
340 22:52:36.454558 - {SERVER_IP}: 192.168.201.1
341 22:52:36.454613 - {TEE}: None
342 22:52:36.454666 Parsed boot commands:
343 22:52:36.454719 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:52:36.454898 Parsed boot commands: tftpboot 192.168.201.1 13683711/tftp-deploy-rojg5qzj/kernel/image.itb 13683711/tftp-deploy-rojg5qzj/kernel/cmdline
345 22:52:36.454985 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:52:36.455068 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:52:36.455159 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:52:36.455241 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:52:36.455311 Not connected, no need to disconnect.
350 22:52:36.455383 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:52:36.455462 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:52:36.455530 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 22:52:36.459493 Setting prompt string to ['lava-test: # ']
354 22:52:36.459877 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:52:36.459982 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:52:36.460074 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:52:36.460167 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:52:36.460369 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 22:52:41.595785 >> Command sent successfully.
360 22:52:41.598573 Returned 0 in 5 seconds
361 22:52:41.698983 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:52:41.699334 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:52:41.699436 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:52:41.699524 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:52:41.699595 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:52:41.699662 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:52:41.699927 [Enter `^Ec?' for help]
369 22:52:41.884541
370 22:52:41.884676
371 22:52:41.884745 F0: 102B 0000
372 22:52:41.884808
373 22:52:41.884867 F3: 1001 0000 [0200]
374 22:52:41.884924
375 22:52:41.887766 F3: 1001 0000
376 22:52:41.887875
377 22:52:41.887945 F7: 102D 0000
378 22:52:41.888014
379 22:52:41.888075 F1: 0000 0000
380 22:52:41.891653
381 22:52:41.891726 V0: 0000 0000 [0001]
382 22:52:41.891791
383 22:52:41.891853 00: 0007 8000
384 22:52:41.891914
385 22:52:41.895175 01: 0000 0000
386 22:52:41.895249
387 22:52:41.895315 BP: 0C00 0209 [0000]
388 22:52:41.895375
389 22:52:41.898746 G0: 1182 0000
390 22:52:41.898818
391 22:52:41.898879 EC: 0000 0021 [4000]
392 22:52:41.898936
393 22:52:41.902508 S7: 0000 0000 [0000]
394 22:52:41.902587
395 22:52:41.902650 CC: 0000 0000 [0001]
396 22:52:41.902709
397 22:52:41.905572 T0: 0000 0040 [010F]
398 22:52:41.905644
399 22:52:41.905708 Jump to BL
400 22:52:41.905766
401 22:52:41.931381
402 22:52:41.931465
403 22:52:41.931531
404 22:52:41.938009 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:52:41.941847 ARM64: Exception handlers installed.
406 22:52:41.945269 ARM64: Testing exception
407 22:52:41.948894 ARM64: Done test exception
408 22:52:41.955833 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:52:41.967090 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:52:41.973800 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:52:41.983493 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:52:41.990365 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:52:41.997579 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:52:42.007433 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:52:42.014409 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:52:42.033875 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:52:42.037059 WDT: Last reset was cold boot
418 22:52:42.040575 SPI1(PAD0) initialized at 2873684 Hz
419 22:52:42.043550 SPI5(PAD0) initialized at 992727 Hz
420 22:52:42.047550 VBOOT: Loading verstage.
421 22:52:42.054014 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:52:42.057211 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:52:42.060226 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:52:42.063699 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:52:42.071165 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:52:42.077752 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:52:42.088969 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 22:52:42.089048
429 22:52:42.089113
430 22:52:42.098742 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:52:42.102241 ARM64: Exception handlers installed.
432 22:52:42.105472 ARM64: Testing exception
433 22:52:42.105547 ARM64: Done test exception
434 22:52:42.112125 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:52:42.115585 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:52:42.129991 Probing TPM: . done!
437 22:52:42.130090 TPM ready after 0 ms
438 22:52:42.136985 Connected to device vid:did:rid of 1ae0:0028:00
439 22:52:42.143717 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 22:52:42.147507 Initialized TPM device CR50 revision 0
441 22:52:42.206914 tlcl_send_startup: Startup return code is 0
442 22:52:42.207019 TPM: setup succeeded
443 22:52:42.217595 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:52:42.226762 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:52:42.236176 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:52:42.245182 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:52:42.248443 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:52:42.251882 in-header: 03 07 00 00 08 00 00 00
449 22:52:42.255210 in-data: aa e4 47 04 13 02 00 00
450 22:52:42.258279 Chrome EC: UHEPI supported
451 22:52:42.265363 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:52:42.268850 in-header: 03 95 00 00 08 00 00 00
453 22:52:42.272607 in-data: 18 20 20 08 00 00 00 00
454 22:52:42.272683 Phase 1
455 22:52:42.276260 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:52:42.283400 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:52:42.287268 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:52:42.290654 Recovery requested (1009000e)
459 22:52:42.299599 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:52:42.305415 tlcl_extend: response is 0
461 22:52:42.314700 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:52:42.320479 tlcl_extend: response is 0
463 22:52:42.327262 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:52:42.347837 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 22:52:42.355726 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:52:42.355838
467 22:52:42.355934
468 22:52:42.362995 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:52:42.366363 ARM64: Exception handlers installed.
470 22:52:42.369917 ARM64: Testing exception
471 22:52:42.373789 ARM64: Done test exception
472 22:52:42.393229 pmic_efuse_setting: Set efuses in 11 msecs
473 22:52:42.396519 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:52:42.402698 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:52:42.406139 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:52:42.412829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:52:42.416628 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:52:42.422843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:52:42.426185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:52:42.429330 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:52:42.436210 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:52:42.439773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:52:42.446296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:52:42.449522 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:52:42.453058 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:52:42.459751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:52:42.466104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:52:42.469960 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:52:42.476939 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:52:42.481054 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:52:42.487817 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:52:42.495296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:52:42.499048 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:52:42.506476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:52:42.510107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:52:42.517403 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:52:42.520952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:52:42.525134 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:52:42.532301 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:52:42.536025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:52:42.543327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:52:42.546955 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:52:42.550421 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:52:42.557638 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:52:42.562031 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:52:42.568847 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:52:42.572337 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:52:42.576069 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:52:42.583129 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:52:42.587035 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:52:42.590828 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:52:42.597878 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:52:42.601570 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:52:42.605498 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:52:42.609095 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:52:42.612778 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:52:42.619842 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:52:42.623642 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:52:42.627343 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:52:42.630959 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:52:42.634566 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:52:42.641885 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:52:42.645460 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:52:42.649300 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:52:42.656448 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:52:42.663730 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:52:42.667247 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:52:42.678032 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:52:42.685978 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:52:42.689102 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:52:42.695823 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:52:42.699693 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:52:42.706787 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 22:52:42.709977 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:52:42.717771 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 22:52:42.721295 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:52:42.730438 [RTC]rtc_get_frequency_meter,154: input=15, output=765
538 22:52:42.740066 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 22:52:42.749321 [RTC]rtc_get_frequency_meter,154: input=19, output=856
540 22:52:42.759011 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 22:52:42.768435 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 22:52:42.777796 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 22:52:42.788083 [RTC]rtc_get_frequency_meter,154: input=17, output=810
544 22:52:42.790737 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 22:52:42.798428 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 22:52:42.801896 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:52:42.805501 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 22:52:42.809418 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:52:42.812496 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 22:52:42.815880 ADC[4]: Raw value=670432 ID=5
551 22:52:42.819745 ADC[3]: Raw value=212180 ID=1
552 22:52:42.819827 RAM Code: 0x51
553 22:52:42.823788 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:52:42.830731 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:52:42.837993 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 22:52:42.845445 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 22:52:42.849004 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:52:42.852560 in-header: 03 07 00 00 08 00 00 00
559 22:52:42.856125 in-data: aa e4 47 04 13 02 00 00
560 22:52:42.856208 Chrome EC: UHEPI supported
561 22:52:42.863501 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:52:42.867247 in-header: 03 95 00 00 08 00 00 00
563 22:52:42.870741 in-data: 18 20 20 08 00 00 00 00
564 22:52:42.874198 MRC: failed to locate region type 0.
565 22:52:42.881562 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:52:42.885170 DRAM-K: Running full calibration
567 22:52:42.889100 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 22:52:42.892465 header.status = 0x0
569 22:52:42.895907 header.version = 0x6 (expected: 0x6)
570 22:52:42.899625 header.size = 0xd00 (expected: 0xd00)
571 22:52:42.899708 header.flags = 0x0
572 22:52:42.906875 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:52:42.923668 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 22:52:42.931372 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:52:42.934979 dram_init: ddr_geometry: 0
576 22:52:42.935062 [EMI] MDL number = 0
577 22:52:42.938669 [EMI] Get MDL freq = 0
578 22:52:42.938752 dram_init: ddr_type: 0
579 22:52:42.942493 is_discrete_lpddr4: 1
580 22:52:42.945950 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:52:42.946090
582 22:52:42.946222
583 22:52:42.949577 [Bian_co] ETT version 0.0.0.1
584 22:52:42.953009 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 22:52:42.953092
586 22:52:42.956779 dramc_set_vcore_voltage set vcore to 650000
587 22:52:42.960244 Read voltage for 800, 4
588 22:52:42.960327 Vio18 = 0
589 22:52:42.960391 Vcore = 650000
590 22:52:42.960453 Vdram = 0
591 22:52:42.963853 Vddq = 0
592 22:52:42.963938 Vmddr = 0
593 22:52:42.967463 dram_init: config_dvfs: 1
594 22:52:42.971568 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:52:42.975133 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:52:42.978357 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 22:52:42.982533 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 22:52:42.985974 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 22:52:42.993419 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 22:52:42.993529 MEM_TYPE=3, freq_sel=18
601 22:52:42.997181 sv_algorithm_assistance_LP4_1600
602 22:52:43.000702 ============ PULL DRAM RESETB DOWN ============
603 22:52:43.004380 ========== PULL DRAM RESETB DOWN end =========
604 22:52:43.011464 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:52:43.011547 ===================================
606 22:52:43.015090 LPDDR4 DRAM CONFIGURATION
607 22:52:43.018643 ===================================
608 22:52:43.022312 EX_ROW_EN[0] = 0x0
609 22:52:43.022395 EX_ROW_EN[1] = 0x0
610 22:52:43.026007 LP4Y_EN = 0x0
611 22:52:43.026131 WORK_FSP = 0x0
612 22:52:43.030149 WL = 0x2
613 22:52:43.030231 RL = 0x2
614 22:52:43.030296 BL = 0x2
615 22:52:43.033334 RPST = 0x0
616 22:52:43.033416 RD_PRE = 0x0
617 22:52:43.037017 WR_PRE = 0x1
618 22:52:43.037099 WR_PST = 0x0
619 22:52:43.040691 DBI_WR = 0x0
620 22:52:43.040773 DBI_RD = 0x0
621 22:52:43.044187 OTF = 0x1
622 22:52:43.047634 ===================================
623 22:52:43.051581 ===================================
624 22:52:43.051663 ANA top config
625 22:52:43.054741 ===================================
626 22:52:43.058985 DLL_ASYNC_EN = 0
627 22:52:43.059084 ALL_SLAVE_EN = 1
628 22:52:43.062737 NEW_RANK_MODE = 1
629 22:52:43.066477 DLL_IDLE_MODE = 1
630 22:52:43.066560 LP45_APHY_COMB_EN = 1
631 22:52:43.070705 TX_ODT_DIS = 1
632 22:52:43.073953 NEW_8X_MODE = 1
633 22:52:43.077040 ===================================
634 22:52:43.080124 ===================================
635 22:52:43.083538 data_rate = 1600
636 22:52:43.083620 CKR = 1
637 22:52:43.087050 DQ_P2S_RATIO = 8
638 22:52:43.090311 ===================================
639 22:52:43.093679 CA_P2S_RATIO = 8
640 22:52:43.097689 DQ_CA_OPEN = 0
641 22:52:43.100508 DQ_SEMI_OPEN = 0
642 22:52:43.100591 CA_SEMI_OPEN = 0
643 22:52:43.104416 CA_FULL_RATE = 0
644 22:52:43.107866 DQ_CKDIV4_EN = 1
645 22:52:43.111510 CA_CKDIV4_EN = 1
646 22:52:43.111595 CA_PREDIV_EN = 0
647 22:52:43.115233 PH8_DLY = 0
648 22:52:43.118674 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:52:43.121915 DQ_AAMCK_DIV = 4
650 22:52:43.125037 CA_AAMCK_DIV = 4
651 22:52:43.125119 CA_ADMCK_DIV = 4
652 22:52:43.128361 DQ_TRACK_CA_EN = 0
653 22:52:43.132121 CA_PICK = 800
654 22:52:43.135890 CA_MCKIO = 800
655 22:52:43.139205 MCKIO_SEMI = 0
656 22:52:43.142467 PLL_FREQ = 3068
657 22:52:43.142549 DQ_UI_PI_RATIO = 32
658 22:52:43.145693 CA_UI_PI_RATIO = 0
659 22:52:43.149155 ===================================
660 22:52:43.152789 ===================================
661 22:52:43.156491 memory_type:LPDDR4
662 22:52:43.156591 GP_NUM : 10
663 22:52:43.160143 SRAM_EN : 1
664 22:52:43.163476 MD32_EN : 0
665 22:52:43.163575 ===================================
666 22:52:43.167545 [ANA_INIT] >>>>>>>>>>>>>>
667 22:52:43.170820 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:52:43.174522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:52:43.178141 ===================================
670 22:52:43.181682 data_rate = 1600,PCW = 0X7600
671 22:52:43.181765 ===================================
672 22:52:43.185407 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:52:43.192178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:52:43.199085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:52:43.201993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:52:43.205573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:52:43.208837 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:52:43.212567 [ANA_INIT] flow start
679 22:52:43.212650 [ANA_INIT] PLL >>>>>>>>
680 22:52:43.215626 [ANA_INIT] PLL <<<<<<<<
681 22:52:43.218783 [ANA_INIT] MIDPI >>>>>>>>
682 22:52:43.218866 [ANA_INIT] MIDPI <<<<<<<<
683 22:52:43.222054 [ANA_INIT] DLL >>>>>>>>
684 22:52:43.225532 [ANA_INIT] flow end
685 22:52:43.228982 ============ LP4 DIFF to SE enter ============
686 22:52:43.232247 ============ LP4 DIFF to SE exit ============
687 22:52:43.235488 [ANA_INIT] <<<<<<<<<<<<<
688 22:52:43.238786 [Flow] Enable top DCM control >>>>>
689 22:52:43.242036 [Flow] Enable top DCM control <<<<<
690 22:52:43.245454 Enable DLL master slave shuffle
691 22:52:43.248780 ==============================================================
692 22:52:43.252329 Gating Mode config
693 22:52:43.258831 ==============================================================
694 22:52:43.258917 Config description:
695 22:52:43.268747 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:52:43.275479 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:52:43.278789 SELPH_MODE 0: By rank 1: By Phase
698 22:52:43.285353 ==============================================================
699 22:52:43.288890 GAT_TRACK_EN = 1
700 22:52:43.292039 RX_GATING_MODE = 2
701 22:52:43.295184 RX_GATING_TRACK_MODE = 2
702 22:52:43.298582 SELPH_MODE = 1
703 22:52:43.301901 PICG_EARLY_EN = 1
704 22:52:43.305618 VALID_LAT_VALUE = 1
705 22:52:43.309072 ==============================================================
706 22:52:43.312343 Enter into Gating configuration >>>>
707 22:52:43.315681 Exit from Gating configuration <<<<
708 22:52:43.319100 Enter into DVFS_PRE_config >>>>>
709 22:52:43.328695 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:52:43.332162 Exit from DVFS_PRE_config <<<<<
711 22:52:43.335433 Enter into PICG configuration >>>>
712 22:52:43.338825 Exit from PICG configuration <<<<
713 22:52:43.342185 [RX_INPUT] configuration >>>>>
714 22:52:43.345717 [RX_INPUT] configuration <<<<<
715 22:52:43.352151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:52:43.355799 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:52:43.362299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:52:43.369688 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:52:43.375884 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:52:43.382500 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:52:43.386130 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:52:43.389422 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:52:43.393093 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:52:43.396004 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:52:43.402709 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:52:43.405986 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:52:43.409411 ===================================
728 22:52:43.412808 LPDDR4 DRAM CONFIGURATION
729 22:52:43.416091 ===================================
730 22:52:43.416517 EX_ROW_EN[0] = 0x0
731 22:52:43.419498 EX_ROW_EN[1] = 0x0
732 22:52:43.419922 LP4Y_EN = 0x0
733 22:52:43.422533 WORK_FSP = 0x0
734 22:52:43.422994 WL = 0x2
735 22:52:43.426130 RL = 0x2
736 22:52:43.426559 BL = 0x2
737 22:52:43.429449 RPST = 0x0
738 22:52:43.429871 RD_PRE = 0x0
739 22:52:43.432632 WR_PRE = 0x1
740 22:52:43.433055 WR_PST = 0x0
741 22:52:43.436135 DBI_WR = 0x0
742 22:52:43.436560 DBI_RD = 0x0
743 22:52:43.439591 OTF = 0x1
744 22:52:43.443104 ===================================
745 22:52:43.446389 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:52:43.449802 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:52:43.456465 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:52:43.459725 ===================================
749 22:52:43.460151 LPDDR4 DRAM CONFIGURATION
750 22:52:43.462708 ===================================
751 22:52:43.466482 EX_ROW_EN[0] = 0x10
752 22:52:43.469531 EX_ROW_EN[1] = 0x0
753 22:52:43.469964 LP4Y_EN = 0x0
754 22:52:43.472906 WORK_FSP = 0x0
755 22:52:43.473361 WL = 0x2
756 22:52:43.476723 RL = 0x2
757 22:52:43.477160 BL = 0x2
758 22:52:43.479502 RPST = 0x0
759 22:52:43.479936 RD_PRE = 0x0
760 22:52:43.482835 WR_PRE = 0x1
761 22:52:43.483270 WR_PST = 0x0
762 22:52:43.486111 DBI_WR = 0x0
763 22:52:43.486550 DBI_RD = 0x0
764 22:52:43.489397 OTF = 0x1
765 22:52:43.492691 ===================================
766 22:52:43.499426 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:52:43.502942 nWR fixed to 40
768 22:52:43.503404 [ModeRegInit_LP4] CH0 RK0
769 22:52:43.506112 [ModeRegInit_LP4] CH0 RK1
770 22:52:43.509484 [ModeRegInit_LP4] CH1 RK0
771 22:52:43.512815 [ModeRegInit_LP4] CH1 RK1
772 22:52:43.513252 match AC timing 12
773 22:52:43.516043 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 22:52:43.523039 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:52:43.526124 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:52:43.529595 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:52:43.536231 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:52:43.536666 [EMI DOE] emi_dcm 0
779 22:52:43.542953 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:52:43.543424 ==
781 22:52:43.546195 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:52:43.549534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 22:52:43.549969 ==
784 22:52:43.556430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:52:43.559612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:52:43.569365 [CA 0] Center 37 (7~68) winsize 62
787 22:52:43.572995 [CA 1] Center 37 (6~68) winsize 63
788 22:52:43.576213 [CA 2] Center 35 (5~66) winsize 62
789 22:52:43.579501 [CA 3] Center 35 (5~66) winsize 62
790 22:52:43.583061 [CA 4] Center 34 (3~65) winsize 63
791 22:52:43.586235 [CA 5] Center 33 (3~64) winsize 62
792 22:52:43.586672
793 22:52:43.589471 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 22:52:43.589906
795 22:52:43.593009 [CATrainingPosCal] consider 1 rank data
796 22:52:43.596384 u2DelayCellTimex100 = 270/100 ps
797 22:52:43.599526 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 22:52:43.602772 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 22:52:43.609483 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 22:52:43.612947 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
801 22:52:43.616418 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 22:52:43.619668 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 22:52:43.620089
804 22:52:43.622831 CA PerBit enable=1, Macro0, CA PI delay=33
805 22:52:43.623253
806 22:52:43.626093 [CBTSetCACLKResult] CA Dly = 33
807 22:52:43.626525 CS Dly: 5 (0~36)
808 22:52:43.629385 ==
809 22:52:43.629811 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:52:43.636103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 22:52:43.636530 ==
812 22:52:43.639489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:52:43.646223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:52:43.655535 [CA 0] Center 37 (7~68) winsize 62
815 22:52:43.659129 [CA 1] Center 37 (7~68) winsize 62
816 22:52:43.662153 [CA 2] Center 35 (4~66) winsize 63
817 22:52:43.665753 [CA 3] Center 35 (4~66) winsize 63
818 22:52:43.668921 [CA 4] Center 34 (4~64) winsize 61
819 22:52:43.672644 [CA 5] Center 34 (3~65) winsize 63
820 22:52:43.673070
821 22:52:43.675447 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 22:52:43.675872
823 22:52:43.678859 [CATrainingPosCal] consider 2 rank data
824 22:52:43.682235 u2DelayCellTimex100 = 270/100 ps
825 22:52:43.685731 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 22:52:43.688980 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 22:52:43.695758 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 22:52:43.698962 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
829 22:52:43.702511 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 22:52:43.705632 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 22:52:43.706092
832 22:52:43.709111 CA PerBit enable=1, Macro0, CA PI delay=33
833 22:52:43.709537
834 22:52:43.712514 [CBTSetCACLKResult] CA Dly = 33
835 22:52:43.712992 CS Dly: 5 (0~37)
836 22:52:43.713483
837 22:52:43.715598 ----->DramcWriteLeveling(PI) begin...
838 22:52:43.718938 ==
839 22:52:43.722358 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:52:43.725631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 22:52:43.726084 ==
842 22:52:43.729141 Write leveling (Byte 0): 28 => 28
843 22:52:43.732416 Write leveling (Byte 1): 29 => 29
844 22:52:43.736392 DramcWriteLeveling(PI) end<-----
845 22:52:43.736832
846 22:52:43.737172 ==
847 22:52:43.737492 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:52:43.743661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 22:52:43.744288 ==
850 22:52:43.744708 [Gating] SW mode calibration
851 22:52:43.751083 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:52:43.757312 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:52:43.761192 0 6 0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
854 22:52:43.764617 0 6 4 | B1->B0 | 2a2a 2525 | 0 0 | (0 0) (1 0)
855 22:52:43.771134 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 22:52:43.774546 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:52:43.777952 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:52:43.784498 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:52:43.787966 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:52:43.791269 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:52:43.797946 0 7 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
862 22:52:43.801317 0 7 4 | B1->B0 | 3a3a 3c3c | 0 0 | (0 0) (0 0)
863 22:52:43.804759 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 22:52:43.811375 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 22:52:43.814915 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 22:52:43.818158 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 22:52:43.824914 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 22:52:43.828214 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 22:52:43.831343 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 22:52:43.835034 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
871 22:52:43.841310 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 22:52:43.844791 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 22:52:43.848277 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 22:52:43.854965 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 22:52:43.858448 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 22:52:43.861441 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 22:52:43.868246 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 22:52:43.871496 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 22:52:43.874845 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 22:52:43.881599 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 22:52:43.884670 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 22:52:43.888067 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 22:52:43.894646 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 22:52:43.898267 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 22:52:43.901483 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
886 22:52:43.904814 Total UI for P1: 0, mck2ui 16
887 22:52:43.908010 best dqsien dly found for B0: ( 0, 9, 30)
888 22:52:43.911780 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 22:52:43.915155 Total UI for P1: 0, mck2ui 16
890 22:52:43.918160 best dqsien dly found for B1: ( 0, 10, 0)
891 22:52:43.921697 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
892 22:52:43.928952 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 22:52:43.929469
894 22:52:43.931606 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
895 22:52:43.934842 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 22:52:43.938368 [Gating] SW calibration Done
897 22:52:43.938800 ==
898 22:52:43.941610 Dram Type= 6, Freq= 0, CH_0, rank 0
899 22:52:43.944769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 22:52:43.945203 ==
901 22:52:43.945549 RX Vref Scan: 0
902 22:52:43.948356
903 22:52:43.948786 RX Vref 0 -> 0, step: 1
904 22:52:43.949127
905 22:52:43.951475 RX Delay -130 -> 252, step: 16
906 22:52:43.954849 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 22:52:43.958326 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 22:52:43.965195 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 22:52:43.968352 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 22:52:43.971842 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 22:52:43.975265 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 22:52:43.978720 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 22:52:43.985154 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
914 22:52:43.988340 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
915 22:52:43.991830 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 22:52:43.994935 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 22:52:43.998506 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 22:52:44.004964 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 22:52:44.008362 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 22:52:44.011867 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 22:52:44.015003 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 22:52:44.015399 ==
923 22:52:44.018604 Dram Type= 6, Freq= 0, CH_0, rank 0
924 22:52:44.025239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 22:52:44.025705 ==
926 22:52:44.026269 DQS Delay:
927 22:52:44.026711 DQS0 = 0, DQS1 = 0
928 22:52:44.028951 DQM Delay:
929 22:52:44.029455 DQM0 = 83, DQM1 = 75
930 22:52:44.031814 DQ Delay:
931 22:52:44.035138 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 22:52:44.038272 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
933 22:52:44.041987 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
934 22:52:44.044914 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 22:52:44.045441
936 22:52:44.045919
937 22:52:44.046336 ==
938 22:52:44.048293 Dram Type= 6, Freq= 0, CH_0, rank 0
939 22:52:44.051663 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 22:52:44.052175 ==
941 22:52:44.052667
942 22:52:44.053137
943 22:52:44.055081 TX Vref Scan disable
944 22:52:44.055534 == TX Byte 0 ==
945 22:52:44.061684 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
946 22:52:44.064928 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
947 22:52:44.065340 == TX Byte 1 ==
948 22:52:44.071660 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 22:52:44.075009 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 22:52:44.075393 ==
951 22:52:44.078257 Dram Type= 6, Freq= 0, CH_0, rank 0
952 22:52:44.081558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 22:52:44.081947 ==
954 22:52:44.095299 TX Vref=22, minBit 2, minWin=27, winSum=445
955 22:52:44.098576 TX Vref=24, minBit 0, minWin=27, winSum=445
956 22:52:44.101980 TX Vref=26, minBit 4, minWin=27, winSum=450
957 22:52:44.105370 TX Vref=28, minBit 4, minWin=27, winSum=453
958 22:52:44.108697 TX Vref=30, minBit 0, minWin=28, winSum=454
959 22:52:44.111977 TX Vref=32, minBit 0, minWin=27, winSum=452
960 22:52:44.118720 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
961 22:52:44.119203
962 22:52:44.121780 Final TX Range 1 Vref 30
963 22:52:44.122335
964 22:52:44.122879 ==
965 22:52:44.125154 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:52:44.129342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 22:52:44.129851 ==
968 22:52:44.130301
969 22:52:44.130794
970 22:52:44.132389 TX Vref Scan disable
971 22:52:44.136022 == TX Byte 0 ==
972 22:52:44.139105 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
973 22:52:44.142777 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
974 22:52:44.145902 == TX Byte 1 ==
975 22:52:44.149222 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
976 22:52:44.152569 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
977 22:52:44.153134
978 22:52:44.156475 [DATLAT]
979 22:52:44.157022 Freq=800, CH0 RK0
980 22:52:44.157373
981 22:52:44.159171 DATLAT Default: 0xa
982 22:52:44.159601 0, 0xFFFF, sum = 0
983 22:52:44.162481 1, 0xFFFF, sum = 0
984 22:52:44.162917 2, 0xFFFF, sum = 0
985 22:52:44.165664 3, 0xFFFF, sum = 0
986 22:52:44.166119 4, 0xFFFF, sum = 0
987 22:52:44.169214 5, 0xFFFF, sum = 0
988 22:52:44.169651 6, 0xFFFF, sum = 0
989 22:52:44.172575 7, 0xFFFF, sum = 0
990 22:52:44.173028 8, 0x0, sum = 1
991 22:52:44.175953 9, 0x0, sum = 2
992 22:52:44.176393 10, 0x0, sum = 3
993 22:52:44.179274 11, 0x0, sum = 4
994 22:52:44.179712 best_step = 9
995 22:52:44.180053
996 22:52:44.180368 ==
997 22:52:44.182662 Dram Type= 6, Freq= 0, CH_0, rank 0
998 22:52:44.185804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 22:52:44.186401 ==
1000 22:52:44.189150 RX Vref Scan: 1
1001 22:52:44.189674
1002 22:52:44.192396 Set Vref Range= 32 -> 127
1003 22:52:44.192789
1004 22:52:44.193118 RX Vref 32 -> 127, step: 1
1005 22:52:44.193448
1006 22:52:44.195723 RX Delay -111 -> 252, step: 8
1007 22:52:44.196171
1008 22:52:44.199258 Set Vref, RX VrefLevel [Byte0]: 32
1009 22:52:44.202492 [Byte1]: 32
1010 22:52:44.206518
1011 22:52:44.206967 Set Vref, RX VrefLevel [Byte0]: 33
1012 22:52:44.209437 [Byte1]: 33
1013 22:52:44.213544
1014 22:52:44.214089 Set Vref, RX VrefLevel [Byte0]: 34
1015 22:52:44.217063 [Byte1]: 34
1016 22:52:44.221849
1017 22:52:44.222401 Set Vref, RX VrefLevel [Byte0]: 35
1018 22:52:44.224805 [Byte1]: 35
1019 22:52:44.229022
1020 22:52:44.229465 Set Vref, RX VrefLevel [Byte0]: 36
1021 22:52:44.232480 [Byte1]: 36
1022 22:52:44.236824
1023 22:52:44.237310 Set Vref, RX VrefLevel [Byte0]: 37
1024 22:52:44.239981 [Byte1]: 37
1025 22:52:44.244154
1026 22:52:44.244574 Set Vref, RX VrefLevel [Byte0]: 38
1027 22:52:44.247550 [Byte1]: 38
1028 22:52:44.251994
1029 22:52:44.252366 Set Vref, RX VrefLevel [Byte0]: 39
1030 22:52:44.255236 [Byte1]: 39
1031 22:52:44.259573
1032 22:52:44.260089 Set Vref, RX VrefLevel [Byte0]: 40
1033 22:52:44.262974 [Byte1]: 40
1034 22:52:44.267413
1035 22:52:44.267833 Set Vref, RX VrefLevel [Byte0]: 41
1036 22:52:44.270703 [Byte1]: 41
1037 22:52:44.275093
1038 22:52:44.275510 Set Vref, RX VrefLevel [Byte0]: 42
1039 22:52:44.278146 [Byte1]: 42
1040 22:52:44.282501
1041 22:52:44.282920 Set Vref, RX VrefLevel [Byte0]: 43
1042 22:52:44.285797 [Byte1]: 43
1043 22:52:44.290256
1044 22:52:44.290673 Set Vref, RX VrefLevel [Byte0]: 44
1045 22:52:44.293606 [Byte1]: 44
1046 22:52:44.297754
1047 22:52:44.298209 Set Vref, RX VrefLevel [Byte0]: 45
1048 22:52:44.301106 [Byte1]: 45
1049 22:52:44.305322
1050 22:52:44.305743 Set Vref, RX VrefLevel [Byte0]: 46
1051 22:52:44.308523 [Byte1]: 46
1052 22:52:44.312930
1053 22:52:44.313349 Set Vref, RX VrefLevel [Byte0]: 47
1054 22:52:44.316333 [Byte1]: 47
1055 22:52:44.320862
1056 22:52:44.321279 Set Vref, RX VrefLevel [Byte0]: 48
1057 22:52:44.323903 [Byte1]: 48
1058 22:52:44.328631
1059 22:52:44.329051 Set Vref, RX VrefLevel [Byte0]: 49
1060 22:52:44.331756 [Byte1]: 49
1061 22:52:44.335946
1062 22:52:44.336363 Set Vref, RX VrefLevel [Byte0]: 50
1063 22:52:44.339602 [Byte1]: 50
1064 22:52:44.343609
1065 22:52:44.344029 Set Vref, RX VrefLevel [Byte0]: 51
1066 22:52:44.346703 [Byte1]: 51
1067 22:52:44.351355
1068 22:52:44.351772 Set Vref, RX VrefLevel [Byte0]: 52
1069 22:52:44.354689 [Byte1]: 52
1070 22:52:44.359040
1071 22:52:44.359460 Set Vref, RX VrefLevel [Byte0]: 53
1072 22:52:44.362368 [Byte1]: 53
1073 22:52:44.366532
1074 22:52:44.366954 Set Vref, RX VrefLevel [Byte0]: 54
1075 22:52:44.369967 [Byte1]: 54
1076 22:52:44.374148
1077 22:52:44.374530 Set Vref, RX VrefLevel [Byte0]: 55
1078 22:52:44.377530 [Byte1]: 55
1079 22:52:44.381650
1080 22:52:44.382184 Set Vref, RX VrefLevel [Byte0]: 56
1081 22:52:44.385174 [Byte1]: 56
1082 22:52:44.389339
1083 22:52:44.389868 Set Vref, RX VrefLevel [Byte0]: 57
1084 22:52:44.392951 [Byte1]: 57
1085 22:52:44.397369
1086 22:52:44.397750 Set Vref, RX VrefLevel [Byte0]: 58
1087 22:52:44.400635 [Byte1]: 58
1088 22:52:44.405220
1089 22:52:44.405753 Set Vref, RX VrefLevel [Byte0]: 59
1090 22:52:44.408059 [Byte1]: 59
1091 22:52:44.412715
1092 22:52:44.413227 Set Vref, RX VrefLevel [Byte0]: 60
1093 22:52:44.415958 [Byte1]: 60
1094 22:52:44.420336
1095 22:52:44.420846 Set Vref, RX VrefLevel [Byte0]: 61
1096 22:52:44.423484 [Byte1]: 61
1097 22:52:44.428107
1098 22:52:44.428637 Set Vref, RX VrefLevel [Byte0]: 62
1099 22:52:44.431243 [Byte1]: 62
1100 22:52:44.435848
1101 22:52:44.436356 Set Vref, RX VrefLevel [Byte0]: 63
1102 22:52:44.439078 [Byte1]: 63
1103 22:52:44.442897
1104 22:52:44.443292 Set Vref, RX VrefLevel [Byte0]: 64
1105 22:52:44.446371 [Byte1]: 64
1106 22:52:44.450949
1107 22:52:44.451328 Set Vref, RX VrefLevel [Byte0]: 65
1108 22:52:44.454152 [Byte1]: 65
1109 22:52:44.458281
1110 22:52:44.458661 Set Vref, RX VrefLevel [Byte0]: 66
1111 22:52:44.461709 [Byte1]: 66
1112 22:52:44.466373
1113 22:52:44.466753 Set Vref, RX VrefLevel [Byte0]: 67
1114 22:52:44.469203 [Byte1]: 67
1115 22:52:44.473389
1116 22:52:44.473907 Set Vref, RX VrefLevel [Byte0]: 68
1117 22:52:44.476969 [Byte1]: 68
1118 22:52:44.481232
1119 22:52:44.481597 Set Vref, RX VrefLevel [Byte0]: 69
1120 22:52:44.484583 [Byte1]: 69
1121 22:52:44.489244
1122 22:52:44.489752 Set Vref, RX VrefLevel [Byte0]: 70
1123 22:52:44.492053 [Byte1]: 70
1124 22:52:44.496712
1125 22:52:44.497087 Set Vref, RX VrefLevel [Byte0]: 71
1126 22:52:44.499919 [Byte1]: 71
1127 22:52:44.504483
1128 22:52:44.504986 Set Vref, RX VrefLevel [Byte0]: 72
1129 22:52:44.507674 [Byte1]: 72
1130 22:52:44.511775
1131 22:52:44.512307 Final RX Vref Byte 0 = 55 to rank0
1132 22:52:44.515206 Final RX Vref Byte 1 = 57 to rank0
1133 22:52:44.518782 Final RX Vref Byte 0 = 55 to rank1
1134 22:52:44.521965 Final RX Vref Byte 1 = 57 to rank1==
1135 22:52:44.525099 Dram Type= 6, Freq= 0, CH_0, rank 0
1136 22:52:44.531693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1137 22:52:44.532373 ==
1138 22:52:44.532990 DQS Delay:
1139 22:52:44.533594 DQS0 = 0, DQS1 = 0
1140 22:52:44.534908 DQM Delay:
1141 22:52:44.535366 DQM0 = 83, DQM1 = 72
1142 22:52:44.538165 DQ Delay:
1143 22:52:44.541475 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1144 22:52:44.544774 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1145 22:52:44.545017 DQ8 =60, DQ9 =56, DQ10 =76, DQ11 =64
1146 22:52:44.551501 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1147 22:52:44.551746
1148 22:52:44.551958
1149 22:52:44.558001 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1150 22:52:44.561296 CH0 RK0: MR19=606, MR18=3333
1151 22:52:44.568059 CH0_RK0: MR19=0x606, MR18=0x3333, DQSOSC=396, MR23=63, INC=94, DEC=62
1152 22:52:44.568190
1153 22:52:44.571644 ----->DramcWriteLeveling(PI) begin...
1154 22:52:44.571771 ==
1155 22:52:44.574664 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 22:52:44.578188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1157 22:52:44.578349 ==
1158 22:52:44.581357 Write leveling (Byte 0): 31 => 31
1159 22:52:44.584991 Write leveling (Byte 1): 28 => 28
1160 22:52:44.588124 DramcWriteLeveling(PI) end<-----
1161 22:52:44.588250
1162 22:52:44.588364 ==
1163 22:52:44.591622 Dram Type= 6, Freq= 0, CH_0, rank 1
1164 22:52:44.594825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1165 22:52:44.594981 ==
1166 22:52:44.597873 [Gating] SW mode calibration
1167 22:52:44.604698 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1168 22:52:44.611382 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1169 22:52:44.614720 0 6 0 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 1)
1170 22:52:44.618047 0 6 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1171 22:52:44.624488 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:52:44.628416 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:52:44.631239 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:52:44.637978 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:52:44.641273 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:52:44.644577 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:52:44.651302 0 7 0 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
1178 22:52:44.654305 0 7 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1179 22:52:44.657811 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1180 22:52:44.664425 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1181 22:52:44.667610 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 22:52:44.671115 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 22:52:44.677751 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 22:52:44.681208 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 22:52:44.684347 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 22:52:44.691219 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1187 22:52:44.694455 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1188 22:52:44.698224 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 22:52:44.701292 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 22:52:44.707553 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 22:52:44.710934 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 22:52:44.714267 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 22:52:44.721087 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 22:52:44.724535 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 22:52:44.728047 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 22:52:44.734427 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 22:52:44.737889 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 22:52:44.741241 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 22:52:44.747910 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 22:52:44.751148 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 22:52:44.754511 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1202 22:52:44.761181 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1203 22:52:44.761251 Total UI for P1: 0, mck2ui 16
1204 22:52:44.767604 best dqsien dly found for B0: ( 0, 10, 0)
1205 22:52:44.771386 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 22:52:44.774783 Total UI for P1: 0, mck2ui 16
1207 22:52:44.777559 best dqsien dly found for B1: ( 0, 10, 4)
1208 22:52:44.780970 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1209 22:52:44.784588 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
1210 22:52:44.784682
1211 22:52:44.787731 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1212 22:52:44.791443 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
1213 22:52:44.794201 [Gating] SW calibration Done
1214 22:52:44.794271 ==
1215 22:52:44.798100 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 22:52:44.801293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1217 22:52:44.801373 ==
1218 22:52:44.804493 RX Vref Scan: 0
1219 22:52:44.804570
1220 22:52:44.807788 RX Vref 0 -> 0, step: 1
1221 22:52:44.807888
1222 22:52:44.807980 RX Delay -130 -> 252, step: 16
1223 22:52:44.855128 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1224 22:52:44.855242 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1225 22:52:44.855694 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1226 22:52:44.855974 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1227 22:52:44.856070 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1228 22:52:44.856171 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1229 22:52:44.856665 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1230 22:52:44.856943 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1231 22:52:44.857037 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1232 22:52:44.857141 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1233 22:52:44.857414 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1234 22:52:44.866212 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1235 22:52:44.866311 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1236 22:52:44.869612 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1237 22:52:44.872630 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1238 22:52:44.872724 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1239 22:52:44.875983 ==
1240 22:52:44.876049 Dram Type= 6, Freq= 0, CH_0, rank 1
1241 22:52:44.882417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1242 22:52:44.882494 ==
1243 22:52:44.882561 DQS Delay:
1244 22:52:44.882623 DQS0 = 0, DQS1 = 0
1245 22:52:44.886053 DQM Delay:
1246 22:52:44.886177 DQM0 = 82, DQM1 = 74
1247 22:52:44.889555 DQ Delay:
1248 22:52:44.892507 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1249 22:52:44.892621 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1250 22:52:44.895789 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1251 22:52:44.902737 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1252 22:52:44.902814
1253 22:52:44.902876
1254 22:52:44.902935 ==
1255 22:52:44.905755 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 22:52:44.909033 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1257 22:52:44.909121 ==
1258 22:52:44.909185
1259 22:52:44.909244
1260 22:52:44.912438 TX Vref Scan disable
1261 22:52:44.912518 == TX Byte 0 ==
1262 22:52:44.919116 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1263 22:52:44.922440 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1264 22:52:44.922524 == TX Byte 1 ==
1265 22:52:44.929067 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1266 22:52:44.932354 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1267 22:52:44.932454 ==
1268 22:52:44.935984 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 22:52:44.939554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1270 22:52:44.939656 ==
1271 22:52:44.953129 TX Vref=22, minBit 14, minWin=27, winSum=448
1272 22:52:44.956401 TX Vref=24, minBit 0, minWin=28, winSum=454
1273 22:52:44.959678 TX Vref=26, minBit 0, minWin=28, winSum=453
1274 22:52:44.963292 TX Vref=28, minBit 2, minWin=28, winSum=458
1275 22:52:44.966473 TX Vref=30, minBit 2, minWin=28, winSum=458
1276 22:52:44.969962 TX Vref=32, minBit 0, minWin=28, winSum=455
1277 22:52:44.976448 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 28
1278 22:52:44.976550
1279 22:52:44.980220 Final TX Range 1 Vref 28
1280 22:52:44.980321
1281 22:52:44.980413 ==
1282 22:52:44.983850 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 22:52:44.987645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1284 22:52:44.987742 ==
1285 22:52:44.987832
1286 22:52:44.987917
1287 22:52:44.991189 TX Vref Scan disable
1288 22:52:44.994639 == TX Byte 0 ==
1289 22:52:44.997881 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1290 22:52:45.001328 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1291 22:52:45.001424 == TX Byte 1 ==
1292 22:52:45.008025 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1293 22:52:45.011953 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1294 22:52:45.012059
1295 22:52:45.012151 [DATLAT]
1296 22:52:45.015232 Freq=800, CH0 RK1
1297 22:52:45.015331
1298 22:52:45.015420 DATLAT Default: 0x9
1299 22:52:45.018698 0, 0xFFFF, sum = 0
1300 22:52:45.018808 1, 0xFFFF, sum = 0
1301 22:52:45.021864 2, 0xFFFF, sum = 0
1302 22:52:45.021958 3, 0xFFFF, sum = 0
1303 22:52:45.025065 4, 0xFFFF, sum = 0
1304 22:52:45.025145 5, 0xFFFF, sum = 0
1305 22:52:45.028437 6, 0xFFFF, sum = 0
1306 22:52:45.028534 7, 0xFFFF, sum = 0
1307 22:52:45.031820 8, 0x0, sum = 1
1308 22:52:45.031921 9, 0x0, sum = 2
1309 22:52:45.035007 10, 0x0, sum = 3
1310 22:52:45.035110 11, 0x0, sum = 4
1311 22:52:45.038553 best_step = 9
1312 22:52:45.038648
1313 22:52:45.038735 ==
1314 22:52:45.041733 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 22:52:45.045055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1316 22:52:45.045154 ==
1317 22:52:45.048320 RX Vref Scan: 0
1318 22:52:45.048388
1319 22:52:45.048465 RX Vref 0 -> 0, step: 1
1320 22:52:45.048524
1321 22:52:45.051728 RX Delay -111 -> 252, step: 8
1322 22:52:45.058597 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1323 22:52:45.061967 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1324 22:52:45.065203 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1325 22:52:45.068410 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1326 22:52:45.071689 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1327 22:52:45.075258 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1328 22:52:45.081657 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1329 22:52:45.085003 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1330 22:52:45.088284 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1331 22:52:45.091857 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1332 22:52:45.095135 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1333 22:52:45.101961 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1334 22:52:45.104950 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1335 22:52:45.108366 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1336 22:52:45.111990 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1337 22:52:45.118747 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1338 22:52:45.118821 ==
1339 22:52:45.121923 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 22:52:45.125865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1341 22:52:45.125959 ==
1342 22:52:45.126078 DQS Delay:
1343 22:52:45.128512 DQS0 = 0, DQS1 = 0
1344 22:52:45.128606 DQM Delay:
1345 22:52:45.131769 DQM0 = 85, DQM1 = 74
1346 22:52:45.131869 DQ Delay:
1347 22:52:45.135080 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =80
1348 22:52:45.138733 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1349 22:52:45.141924 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1350 22:52:45.145523 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1351 22:52:45.145602
1352 22:52:45.145664
1353 22:52:45.151875 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1354 22:52:45.155041 CH0 RK1: MR19=606, MR18=4B4B
1355 22:52:45.161911 CH0_RK1: MR19=0x606, MR18=0x4B4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1356 22:52:45.165316 [RxdqsGatingPostProcess] freq 800
1357 22:52:45.168889 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1358 22:52:45.171917 Pre-setting of DQS Precalculation
1359 22:52:45.178376 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1360 22:52:45.178473 ==
1361 22:52:45.181936 Dram Type= 6, Freq= 0, CH_1, rank 0
1362 22:52:45.185290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1363 22:52:45.185361 ==
1364 22:52:45.192089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1365 22:52:45.198241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1366 22:52:45.205810 [CA 0] Center 37 (6~68) winsize 63
1367 22:52:45.209660 [CA 1] Center 37 (6~68) winsize 63
1368 22:52:45.212427 [CA 2] Center 34 (4~65) winsize 62
1369 22:52:45.215856 [CA 3] Center 34 (4~65) winsize 62
1370 22:52:45.219203 [CA 4] Center 33 (3~64) winsize 62
1371 22:52:45.222659 [CA 5] Center 33 (3~64) winsize 62
1372 22:52:45.222727
1373 22:52:45.225905 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1374 22:52:45.225998
1375 22:52:45.229275 [CATrainingPosCal] consider 1 rank data
1376 22:52:45.232585 u2DelayCellTimex100 = 270/100 ps
1377 22:52:45.235915 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1378 22:52:45.239170 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1379 22:52:45.245877 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1380 22:52:45.249265 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1381 22:52:45.252623 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1382 22:52:45.256036 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1383 22:52:45.256132
1384 22:52:45.259217 CA PerBit enable=1, Macro0, CA PI delay=33
1385 22:52:45.259294
1386 22:52:45.262671 [CBTSetCACLKResult] CA Dly = 33
1387 22:52:45.262739 CS Dly: 5 (0~36)
1388 22:52:45.262799 ==
1389 22:52:45.265970 Dram Type= 6, Freq= 0, CH_1, rank 1
1390 22:52:45.272420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1391 22:52:45.272492 ==
1392 22:52:45.275789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1393 22:52:45.282415 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1394 22:52:45.291792 [CA 0] Center 36 (6~67) winsize 62
1395 22:52:45.295093 [CA 1] Center 37 (6~68) winsize 63
1396 22:52:45.298426 [CA 2] Center 34 (4~65) winsize 62
1397 22:52:45.301936 [CA 3] Center 34 (4~65) winsize 62
1398 22:52:45.304868 [CA 4] Center 33 (3~64) winsize 62
1399 22:52:45.308271 [CA 5] Center 33 (3~64) winsize 62
1400 22:52:45.308368
1401 22:52:45.311734 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1402 22:52:45.311833
1403 22:52:45.315057 [CATrainingPosCal] consider 2 rank data
1404 22:52:45.318316 u2DelayCellTimex100 = 270/100 ps
1405 22:52:45.321597 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1406 22:52:45.325085 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1407 22:52:45.331493 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1408 22:52:45.334756 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1409 22:52:45.338533 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1410 22:52:45.341518 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1411 22:52:45.341589
1412 22:52:45.345037 CA PerBit enable=1, Macro0, CA PI delay=33
1413 22:52:45.345130
1414 22:52:45.348245 [CBTSetCACLKResult] CA Dly = 33
1415 22:52:45.348342 CS Dly: 5 (0~36)
1416 22:52:45.348437
1417 22:52:45.351545 ----->DramcWriteLeveling(PI) begin...
1418 22:52:45.354754 ==
1419 22:52:45.358347 Dram Type= 6, Freq= 0, CH_1, rank 0
1420 22:52:45.361503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1421 22:52:45.361600 ==
1422 22:52:45.364655 Write leveling (Byte 0): 26 => 26
1423 22:52:45.368104 Write leveling (Byte 1): 26 => 26
1424 22:52:45.371511 DramcWriteLeveling(PI) end<-----
1425 22:52:45.371578
1426 22:52:45.371637 ==
1427 22:52:45.374975 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 22:52:45.378600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1429 22:52:45.378670 ==
1430 22:52:45.381478 [Gating] SW mode calibration
1431 22:52:45.387973 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1432 22:52:45.391508 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1433 22:52:45.398032 0 6 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (1 0)
1434 22:52:45.401394 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1435 22:52:45.405028 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1436 22:52:45.411582 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1437 22:52:45.414873 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 22:52:45.417916 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 22:52:45.424720 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 22:52:45.427855 0 6 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1441 22:52:45.431360 0 7 0 | B1->B0 | 3030 4040 | 0 0 | (1 1) (0 0)
1442 22:52:45.438148 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1443 22:52:45.441328 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1444 22:52:45.444825 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1445 22:52:45.451737 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 22:52:45.454563 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 22:52:45.457921 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 22:52:45.464817 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 22:52:45.467967 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1450 22:52:45.471402 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1451 22:52:45.477935 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 22:52:45.481359 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 22:52:45.484600 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 22:52:45.491287 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 22:52:45.494631 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 22:52:45.498286 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 22:52:45.501453 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 22:52:45.508367 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 22:52:45.511329 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 22:52:45.515163 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 22:52:45.521373 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 22:52:45.524845 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 22:52:45.527948 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 22:52:45.534781 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1465 22:52:45.538027 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1466 22:52:45.541478 Total UI for P1: 0, mck2ui 16
1467 22:52:45.544728 best dqsien dly found for B0: ( 0, 9, 28)
1468 22:52:45.547972 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1469 22:52:45.551268 Total UI for P1: 0, mck2ui 16
1470 22:52:45.555080 best dqsien dly found for B1: ( 0, 10, 0)
1471 22:52:45.557927 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1472 22:52:45.561290 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1473 22:52:45.561361
1474 22:52:45.568239 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1475 22:52:45.571674 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1476 22:52:45.571746 [Gating] SW calibration Done
1477 22:52:45.574775 ==
1478 22:52:45.578200 Dram Type= 6, Freq= 0, CH_1, rank 0
1479 22:52:45.581305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1480 22:52:45.581376 ==
1481 22:52:45.581437 RX Vref Scan: 0
1482 22:52:45.581495
1483 22:52:45.584635 RX Vref 0 -> 0, step: 1
1484 22:52:45.584702
1485 22:52:45.587980 RX Delay -130 -> 252, step: 16
1486 22:52:45.591436 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1487 22:52:45.594741 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1488 22:52:45.597958 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1489 22:52:45.605011 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1490 22:52:45.607939 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1491 22:52:45.611476 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1492 22:52:45.614710 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1493 22:52:45.618127 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1494 22:52:45.624755 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1495 22:52:45.628239 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1496 22:52:45.631352 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1497 22:52:45.634493 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1498 22:52:45.637776 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1499 22:52:45.645246 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1500 22:52:45.648843 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1501 22:52:45.652406 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1502 22:52:45.652479 ==
1503 22:52:45.656119 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 22:52:45.659825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1505 22:52:45.659923 ==
1506 22:52:45.660013 DQS Delay:
1507 22:52:45.663446 DQS0 = 0, DQS1 = 0
1508 22:52:45.663539 DQM Delay:
1509 22:52:45.667247 DQM0 = 80, DQM1 = 74
1510 22:52:45.667317 DQ Delay:
1511 22:52:45.670831 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1512 22:52:45.670899 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1513 22:52:45.674366 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1514 22:52:45.678377 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1515 22:52:45.678446
1516 22:52:45.678507
1517 22:52:45.678565 ==
1518 22:52:45.681851 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 22:52:45.688223 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1520 22:52:45.688303 ==
1521 22:52:45.688394
1522 22:52:45.688488
1523 22:52:45.688577 TX Vref Scan disable
1524 22:52:45.692026 == TX Byte 0 ==
1525 22:52:45.695293 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1526 22:52:45.702224 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1527 22:52:45.702296 == TX Byte 1 ==
1528 22:52:45.705499 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1529 22:52:45.712007 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1530 22:52:45.712111 ==
1531 22:52:45.715363 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 22:52:45.718627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1533 22:52:45.718702 ==
1534 22:52:45.731024 TX Vref=22, minBit 0, minWin=27, winSum=444
1535 22:52:45.734116 TX Vref=24, minBit 3, minWin=27, winSum=449
1536 22:52:45.737801 TX Vref=26, minBit 9, minWin=27, winSum=453
1537 22:52:45.741127 TX Vref=28, minBit 0, minWin=28, winSum=459
1538 22:52:45.744242 TX Vref=30, minBit 0, minWin=28, winSum=459
1539 22:52:45.747450 TX Vref=32, minBit 9, minWin=27, winSum=455
1540 22:52:45.754439 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1541 22:52:45.754512
1542 22:52:45.757672 Final TX Range 1 Vref 28
1543 22:52:45.757744
1544 22:52:45.757805 ==
1545 22:52:45.761099 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 22:52:45.764533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1547 22:52:45.764629 ==
1548 22:52:45.764716
1549 22:52:45.767646
1550 22:52:45.767738 TX Vref Scan disable
1551 22:52:45.771016 == TX Byte 0 ==
1552 22:52:45.774381 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1553 22:52:45.778211 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1554 22:52:45.781243 == TX Byte 1 ==
1555 22:52:45.784309 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1556 22:52:45.787575 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1557 22:52:45.790848
1558 22:52:45.790918 [DATLAT]
1559 22:52:45.790978 Freq=800, CH1 RK0
1560 22:52:45.791061
1561 22:52:45.794140 DATLAT Default: 0xa
1562 22:52:45.794218 0, 0xFFFF, sum = 0
1563 22:52:45.797492 1, 0xFFFF, sum = 0
1564 22:52:45.797587 2, 0xFFFF, sum = 0
1565 22:52:45.800835 3, 0xFFFF, sum = 0
1566 22:52:45.800934 4, 0xFFFF, sum = 0
1567 22:52:45.804241 5, 0xFFFF, sum = 0
1568 22:52:45.804338 6, 0xFFFF, sum = 0
1569 22:52:45.807383 7, 0xFFFF, sum = 0
1570 22:52:45.807478 8, 0x0, sum = 1
1571 22:52:45.810993 9, 0x0, sum = 2
1572 22:52:45.811073 10, 0x0, sum = 3
1573 22:52:45.814321 11, 0x0, sum = 4
1574 22:52:45.814420 best_step = 9
1575 22:52:45.814507
1576 22:52:45.814593 ==
1577 22:52:45.817694 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 22:52:45.824122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1579 22:52:45.824224 ==
1580 22:52:45.824316 RX Vref Scan: 1
1581 22:52:45.824402
1582 22:52:45.827726 Set Vref Range= 32 -> 127
1583 22:52:45.827820
1584 22:52:45.831041 RX Vref 32 -> 127, step: 1
1585 22:52:45.831110
1586 22:52:45.831171 RX Delay -111 -> 252, step: 8
1587 22:52:45.831229
1588 22:52:45.834404 Set Vref, RX VrefLevel [Byte0]: 32
1589 22:52:45.837677 [Byte1]: 32
1590 22:52:45.841693
1591 22:52:45.841788 Set Vref, RX VrefLevel [Byte0]: 33
1592 22:52:45.845111 [Byte1]: 33
1593 22:52:45.849514
1594 22:52:45.849611 Set Vref, RX VrefLevel [Byte0]: 34
1595 22:52:45.852572 [Byte1]: 34
1596 22:52:45.857201
1597 22:52:45.857295 Set Vref, RX VrefLevel [Byte0]: 35
1598 22:52:45.860304 [Byte1]: 35
1599 22:52:45.864710
1600 22:52:45.864778 Set Vref, RX VrefLevel [Byte0]: 36
1601 22:52:45.868128 [Byte1]: 36
1602 22:52:45.872261
1603 22:52:45.872332 Set Vref, RX VrefLevel [Byte0]: 37
1604 22:52:45.875928 [Byte1]: 37
1605 22:52:45.879928
1606 22:52:45.879995 Set Vref, RX VrefLevel [Byte0]: 38
1607 22:52:45.883210 [Byte1]: 38
1608 22:52:45.887675
1609 22:52:45.887769 Set Vref, RX VrefLevel [Byte0]: 39
1610 22:52:45.891234 [Byte1]: 39
1611 22:52:45.895319
1612 22:52:45.895390 Set Vref, RX VrefLevel [Byte0]: 40
1613 22:52:45.898501 [Byte1]: 40
1614 22:52:45.903002
1615 22:52:45.903072 Set Vref, RX VrefLevel [Byte0]: 41
1616 22:52:45.906579 [Byte1]: 41
1617 22:52:45.910549
1618 22:52:45.910639 Set Vref, RX VrefLevel [Byte0]: 42
1619 22:52:45.913725 [Byte1]: 42
1620 22:52:45.918392
1621 22:52:45.918461 Set Vref, RX VrefLevel [Byte0]: 43
1622 22:52:45.921669 [Byte1]: 43
1623 22:52:45.925901
1624 22:52:45.925996 Set Vref, RX VrefLevel [Byte0]: 44
1625 22:52:45.929434 [Byte1]: 44
1626 22:52:45.933497
1627 22:52:45.933570 Set Vref, RX VrefLevel [Byte0]: 45
1628 22:52:45.936969 [Byte1]: 45
1629 22:52:45.941323
1630 22:52:45.941391 Set Vref, RX VrefLevel [Byte0]: 46
1631 22:52:45.944529 [Byte1]: 46
1632 22:52:45.949553
1633 22:52:45.949621 Set Vref, RX VrefLevel [Byte0]: 47
1634 22:52:45.952738 [Byte1]: 47
1635 22:52:45.956590
1636 22:52:45.956675 Set Vref, RX VrefLevel [Byte0]: 48
1637 22:52:45.960063 [Byte1]: 48
1638 22:52:45.964045
1639 22:52:45.964111 Set Vref, RX VrefLevel [Byte0]: 49
1640 22:52:45.967434 [Byte1]: 49
1641 22:52:45.971834
1642 22:52:45.971921 Set Vref, RX VrefLevel [Byte0]: 50
1643 22:52:45.975147 [Byte1]: 50
1644 22:52:45.979803
1645 22:52:45.979904 Set Vref, RX VrefLevel [Byte0]: 51
1646 22:52:45.982839 [Byte1]: 51
1647 22:52:45.987206
1648 22:52:45.987305 Set Vref, RX VrefLevel [Byte0]: 52
1649 22:52:45.990398 [Byte1]: 52
1650 22:52:45.994876
1651 22:52:45.994996 Set Vref, RX VrefLevel [Byte0]: 53
1652 22:52:45.998670 [Byte1]: 53
1653 22:52:46.002441
1654 22:52:46.002598 Set Vref, RX VrefLevel [Byte0]: 54
1655 22:52:46.005880 [Byte1]: 54
1656 22:52:46.010138
1657 22:52:46.010323 Set Vref, RX VrefLevel [Byte0]: 55
1658 22:52:46.013629 [Byte1]: 55
1659 22:52:46.017894
1660 22:52:46.018204 Set Vref, RX VrefLevel [Byte0]: 56
1661 22:52:46.021223 [Byte1]: 56
1662 22:52:46.025646
1663 22:52:46.026140 Set Vref, RX VrefLevel [Byte0]: 57
1664 22:52:46.028761 [Byte1]: 57
1665 22:52:46.033276
1666 22:52:46.033647 Set Vref, RX VrefLevel [Byte0]: 58
1667 22:52:46.036352 [Byte1]: 58
1668 22:52:46.040856
1669 22:52:46.041245 Set Vref, RX VrefLevel [Byte0]: 59
1670 22:52:46.044189 [Byte1]: 59
1671 22:52:46.048473
1672 22:52:46.048889 Set Vref, RX VrefLevel [Byte0]: 60
1673 22:52:46.052286 [Byte1]: 60
1674 22:52:46.056314
1675 22:52:46.056685 Set Vref, RX VrefLevel [Byte0]: 61
1676 22:52:46.059625 [Byte1]: 61
1677 22:52:46.063769
1678 22:52:46.064146 Set Vref, RX VrefLevel [Byte0]: 62
1679 22:52:46.067309 [Byte1]: 62
1680 22:52:46.071672
1681 22:52:46.072037 Set Vref, RX VrefLevel [Byte0]: 63
1682 22:52:46.074658 [Byte1]: 63
1683 22:52:46.079069
1684 22:52:46.079600 Set Vref, RX VrefLevel [Byte0]: 64
1685 22:52:46.082517 [Byte1]: 64
1686 22:52:46.086731
1687 22:52:46.087172 Set Vref, RX VrefLevel [Byte0]: 65
1688 22:52:46.090253 [Byte1]: 65
1689 22:52:46.094501
1690 22:52:46.095048 Set Vref, RX VrefLevel [Byte0]: 66
1691 22:52:46.097791 [Byte1]: 66
1692 22:52:46.102052
1693 22:52:46.102516 Set Vref, RX VrefLevel [Byte0]: 67
1694 22:52:46.105773 [Byte1]: 67
1695 22:52:46.109792
1696 22:52:46.110314 Set Vref, RX VrefLevel [Byte0]: 68
1697 22:52:46.113088 [Byte1]: 68
1698 22:52:46.117570
1699 22:52:46.118015 Set Vref, RX VrefLevel [Byte0]: 69
1700 22:52:46.120774 [Byte1]: 69
1701 22:52:46.125150
1702 22:52:46.125590 Set Vref, RX VrefLevel [Byte0]: 70
1703 22:52:46.128365 [Byte1]: 70
1704 22:52:46.132954
1705 22:52:46.133394 Set Vref, RX VrefLevel [Byte0]: 71
1706 22:52:46.135972 [Byte1]: 71
1707 22:52:46.140351
1708 22:52:46.140779 Set Vref, RX VrefLevel [Byte0]: 72
1709 22:52:46.143625 [Byte1]: 72
1710 22:52:46.148039
1711 22:52:46.148471 Set Vref, RX VrefLevel [Byte0]: 73
1712 22:52:46.151431 [Byte1]: 73
1713 22:52:46.155550
1714 22:52:46.155978 Set Vref, RX VrefLevel [Byte0]: 74
1715 22:52:46.158956 [Byte1]: 74
1716 22:52:46.163326
1717 22:52:46.163764 Set Vref, RX VrefLevel [Byte0]: 75
1718 22:52:46.166602 [Byte1]: 75
1719 22:52:46.171165
1720 22:52:46.171599 Set Vref, RX VrefLevel [Byte0]: 76
1721 22:52:46.174312 [Byte1]: 76
1722 22:52:46.178653
1723 22:52:46.179080 Set Vref, RX VrefLevel [Byte0]: 77
1724 22:52:46.181783 [Byte1]: 77
1725 22:52:46.186258
1726 22:52:46.186688 Set Vref, RX VrefLevel [Byte0]: 78
1727 22:52:46.189611 [Byte1]: 78
1728 22:52:46.193939
1729 22:52:46.194558 Set Vref, RX VrefLevel [Byte0]: 79
1730 22:52:46.197106 [Byte1]: 79
1731 22:52:46.201447
1732 22:52:46.202008 Final RX Vref Byte 0 = 55 to rank0
1733 22:52:46.205081 Final RX Vref Byte 1 = 57 to rank0
1734 22:52:46.208138 Final RX Vref Byte 0 = 55 to rank1
1735 22:52:46.211469 Final RX Vref Byte 1 = 57 to rank1==
1736 22:52:46.214888 Dram Type= 6, Freq= 0, CH_1, rank 0
1737 22:52:46.221624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1738 22:52:46.222225 ==
1739 22:52:46.222577 DQS Delay:
1740 22:52:46.223045 DQS0 = 0, DQS1 = 0
1741 22:52:46.225188 DQM Delay:
1742 22:52:46.225637 DQM0 = 81, DQM1 = 75
1743 22:52:46.226148 DQ Delay:
1744 22:52:46.229338 DQ0 =88, DQ1 =72, DQ2 =72, DQ3 =76
1745 22:52:46.232030 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1746 22:52:46.235530 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1747 22:52:46.239066 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1748 22:52:46.239513
1749 22:52:46.239856
1750 22:52:46.249124 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1751 22:52:46.252302 CH1 RK0: MR19=606, MR18=5454
1752 22:52:46.255597 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65
1753 22:52:46.258907
1754 22:52:46.262313 ----->DramcWriteLeveling(PI) begin...
1755 22:52:46.262819 ==
1756 22:52:46.265324 Dram Type= 6, Freq= 0, CH_1, rank 1
1757 22:52:46.268864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1758 22:52:46.269405 ==
1759 22:52:46.272306 Write leveling (Byte 0): 27 => 27
1760 22:52:46.275750 Write leveling (Byte 1): 25 => 25
1761 22:52:46.278849 DramcWriteLeveling(PI) end<-----
1762 22:52:46.279283
1763 22:52:46.279615 ==
1764 22:52:46.282499 Dram Type= 6, Freq= 0, CH_1, rank 1
1765 22:52:46.285245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1766 22:52:46.285684 ==
1767 22:52:46.288599 [Gating] SW mode calibration
1768 22:52:46.295163 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1769 22:52:46.302077 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1770 22:52:46.305251 0 6 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
1771 22:52:46.308627 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1772 22:52:46.315110 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1773 22:52:46.318381 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1774 22:52:46.321657 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1775 22:52:46.328668 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 22:52:46.331522 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1777 22:52:46.335025 0 6 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1778 22:52:46.341525 0 7 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
1779 22:52:46.345037 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1780 22:52:46.348333 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1781 22:52:46.354995 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1782 22:52:46.357845 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1783 22:52:46.361405 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1784 22:52:46.368251 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1785 22:52:46.371461 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1786 22:52:46.374940 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1787 22:52:46.377822 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 22:52:46.384429 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 22:52:46.387864 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 22:52:46.391258 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 22:52:46.397793 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 22:52:46.401364 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 22:52:46.404417 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 22:52:46.411281 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 22:52:46.414785 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 22:52:46.418134 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 22:52:46.424589 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 22:52:46.427679 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 22:52:46.430971 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 22:52:46.437938 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 22:52:46.441423 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1802 22:52:46.444355 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1803 22:52:46.447788 Total UI for P1: 0, mck2ui 16
1804 22:52:46.451126 best dqsien dly found for B0: ( 0, 9, 28)
1805 22:52:46.457782 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1806 22:52:46.458226 Total UI for P1: 0, mck2ui 16
1807 22:52:46.464675 best dqsien dly found for B1: ( 0, 9, 30)
1808 22:52:46.467967 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1809 22:52:46.471117 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1810 22:52:46.471530
1811 22:52:46.474516 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1812 22:52:46.477695 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1813 22:52:46.480844 [Gating] SW calibration Done
1814 22:52:46.481316 ==
1815 22:52:46.484196 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 22:52:46.487535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1817 22:52:46.487982 ==
1818 22:52:46.490805 RX Vref Scan: 0
1819 22:52:46.491421
1820 22:52:46.491797 RX Vref 0 -> 0, step: 1
1821 22:52:46.492110
1822 22:52:46.494326 RX Delay -130 -> 252, step: 16
1823 22:52:46.497999 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1824 22:52:46.504342 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1825 22:52:46.507596 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1826 22:52:46.510952 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1827 22:52:46.514544 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1828 22:52:46.517479 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1829 22:52:46.524420 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1830 22:52:46.527412 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1831 22:52:46.530875 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1832 22:52:46.533995 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1833 22:52:46.537784 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1834 22:52:46.544225 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1835 22:52:46.547474 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1836 22:52:46.551092 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1837 22:52:46.554089 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1838 22:52:46.561200 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1839 22:52:46.561661 ==
1840 22:52:46.564315 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 22:52:46.567701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1842 22:52:46.568167 ==
1843 22:52:46.568497 DQS Delay:
1844 22:52:46.570757 DQS0 = 0, DQS1 = 0
1845 22:52:46.571169 DQM Delay:
1846 22:52:46.574313 DQM0 = 86, DQM1 = 74
1847 22:52:46.574729 DQ Delay:
1848 22:52:46.577520 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1849 22:52:46.580875 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1850 22:52:46.584091 DQ8 =53, DQ9 =69, DQ10 =69, DQ11 =69
1851 22:52:46.587460 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1852 22:52:46.587872
1853 22:52:46.588190
1854 22:52:46.588490 ==
1855 22:52:46.590915 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 22:52:46.594407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1857 22:52:46.594857 ==
1858 22:52:46.595182
1859 22:52:46.595482
1860 22:52:46.597538 TX Vref Scan disable
1861 22:52:46.600837 == TX Byte 0 ==
1862 22:52:46.604304 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1863 22:52:46.607602 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1864 22:52:46.610997 == TX Byte 1 ==
1865 22:52:46.613919 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1866 22:52:46.617538 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1867 22:52:46.617953 ==
1868 22:52:46.620557 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 22:52:46.627341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1870 22:52:46.627755 ==
1871 22:52:46.638809 TX Vref=22, minBit 0, minWin=27, winSum=448
1872 22:52:46.642551 TX Vref=24, minBit 0, minWin=27, winSum=450
1873 22:52:46.645910 TX Vref=26, minBit 2, minWin=28, winSum=455
1874 22:52:46.649099 TX Vref=28, minBit 0, minWin=28, winSum=457
1875 22:52:46.652388 TX Vref=30, minBit 0, minWin=28, winSum=456
1876 22:52:46.655914 TX Vref=32, minBit 9, minWin=27, winSum=454
1877 22:52:46.662336 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1878 22:52:46.662750
1879 22:52:46.665651 Final TX Range 1 Vref 28
1880 22:52:46.666098
1881 22:52:46.666426 ==
1882 22:52:46.669088 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 22:52:46.672178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1884 22:52:46.672639 ==
1885 22:52:46.672964
1886 22:52:46.675317
1887 22:52:46.675730 TX Vref Scan disable
1888 22:52:46.678881 == TX Byte 0 ==
1889 22:52:46.682403 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1890 22:52:46.685528 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1891 22:52:46.688836 == TX Byte 1 ==
1892 22:52:46.692018 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1893 22:52:46.695535 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1894 22:52:46.699117
1895 22:52:46.699530 [DATLAT]
1896 22:52:46.699851 Freq=800, CH1 RK1
1897 22:52:46.700153
1898 22:52:46.702112 DATLAT Default: 0x9
1899 22:52:46.702526 0, 0xFFFF, sum = 0
1900 22:52:46.705582 1, 0xFFFF, sum = 0
1901 22:52:46.706000 2, 0xFFFF, sum = 0
1902 22:52:46.708720 3, 0xFFFF, sum = 0
1903 22:52:46.709140 4, 0xFFFF, sum = 0
1904 22:52:46.712045 5, 0xFFFF, sum = 0
1905 22:52:46.715531 6, 0xFFFF, sum = 0
1906 22:52:46.715961 7, 0xFFFF, sum = 0
1907 22:52:46.716293 8, 0x0, sum = 1
1908 22:52:46.718929 9, 0x0, sum = 2
1909 22:52:46.719348 10, 0x0, sum = 3
1910 22:52:46.722218 11, 0x0, sum = 4
1911 22:52:46.722637 best_step = 9
1912 22:52:46.722961
1913 22:52:46.723262 ==
1914 22:52:46.725582 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 22:52:46.732245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1916 22:52:46.732660 ==
1917 22:52:46.732986 RX Vref Scan: 0
1918 22:52:46.733288
1919 22:52:46.735480 RX Vref 0 -> 0, step: 1
1920 22:52:46.735890
1921 22:52:46.739015 RX Delay -111 -> 252, step: 8
1922 22:52:46.742124 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1923 22:52:46.745355 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
1924 22:52:46.752279 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1925 22:52:46.755662 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1926 22:52:46.759063 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1927 22:52:46.762458 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1928 22:52:46.765392 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1929 22:52:46.771997 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1930 22:52:46.775552 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1931 22:52:46.778675 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1932 22:52:46.781988 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1933 22:52:46.785281 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1934 22:52:46.791901 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1935 22:52:46.795294 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1936 22:52:46.798659 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1937 22:52:46.802126 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1938 22:52:46.802630 ==
1939 22:52:46.805198 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 22:52:46.812126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1941 22:52:46.812771 ==
1942 22:52:46.813270 DQS Delay:
1943 22:52:46.813745 DQS0 = 0, DQS1 = 0
1944 22:52:46.815440 DQM Delay:
1945 22:52:46.815889 DQM0 = 85, DQM1 = 74
1946 22:52:46.819155 DQ Delay:
1947 22:52:46.822307 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =80
1948 22:52:46.822762 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1949 22:52:46.825518 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1950 22:52:46.828847 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1951 22:52:46.832137
1952 22:52:46.832623
1953 22:52:46.838680 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1954 22:52:46.842141 CH1 RK1: MR19=606, MR18=3636
1955 22:52:46.848964 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1956 22:52:46.851989 [RxdqsGatingPostProcess] freq 800
1957 22:52:46.855448 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1958 22:52:46.859106 Pre-setting of DQS Precalculation
1959 22:52:46.862305 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1960 22:52:46.872336 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1961 22:52:46.878853 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1962 22:52:46.879304
1963 22:52:46.879661
1964 22:52:46.882072 [Calibration Summary] 1600 Mbps
1965 22:52:46.882541 CH 0, Rank 0
1966 22:52:46.885613 SW Impedance : PASS
1967 22:52:46.886084 DUTY Scan : NO K
1968 22:52:46.888634 ZQ Calibration : PASS
1969 22:52:46.892364 Jitter Meter : NO K
1970 22:52:46.892816 CBT Training : PASS
1971 22:52:46.895594 Write leveling : PASS
1972 22:52:46.898957 RX DQS gating : PASS
1973 22:52:46.899369 RX DQ/DQS(RDDQC) : PASS
1974 22:52:46.902154 TX DQ/DQS : PASS
1975 22:52:46.905642 RX DATLAT : PASS
1976 22:52:46.906118 RX DQ/DQS(Engine): PASS
1977 22:52:46.908810 TX OE : NO K
1978 22:52:46.909255 All Pass.
1979 22:52:46.909613
1980 22:52:46.912119 CH 0, Rank 1
1981 22:52:46.912742 SW Impedance : PASS
1982 22:52:46.915530 DUTY Scan : NO K
1983 22:52:46.918624 ZQ Calibration : PASS
1984 22:52:46.919013 Jitter Meter : NO K
1985 22:52:46.922255 CBT Training : PASS
1986 22:52:46.922638 Write leveling : PASS
1987 22:52:46.925443 RX DQS gating : PASS
1988 22:52:46.928579 RX DQ/DQS(RDDQC) : PASS
1989 22:52:46.929120 TX DQ/DQS : PASS
1990 22:52:46.932155 RX DATLAT : PASS
1991 22:52:46.935321 RX DQ/DQS(Engine): PASS
1992 22:52:46.935757 TX OE : NO K
1993 22:52:46.938895 All Pass.
1994 22:52:46.939335
1995 22:52:46.939680 CH 1, Rank 0
1996 22:52:46.942005 SW Impedance : PASS
1997 22:52:46.942549 DUTY Scan : NO K
1998 22:52:46.945519 ZQ Calibration : PASS
1999 22:52:46.948599 Jitter Meter : NO K
2000 22:52:46.949063 CBT Training : PASS
2001 22:52:46.952016 Write leveling : PASS
2002 22:52:46.955592 RX DQS gating : PASS
2003 22:52:46.956054 RX DQ/DQS(RDDQC) : PASS
2004 22:52:46.958650 TX DQ/DQS : PASS
2005 22:52:46.959112 RX DATLAT : PASS
2006 22:52:46.961969 RX DQ/DQS(Engine): PASS
2007 22:52:46.965427 TX OE : NO K
2008 22:52:46.966000 All Pass.
2009 22:52:46.966502
2010 22:52:46.966927 CH 1, Rank 1
2011 22:52:46.968979 SW Impedance : PASS
2012 22:52:46.972152 DUTY Scan : NO K
2013 22:52:46.972646 ZQ Calibration : PASS
2014 22:52:46.975184 Jitter Meter : NO K
2015 22:52:46.978913 CBT Training : PASS
2016 22:52:46.979360 Write leveling : PASS
2017 22:52:46.981970 RX DQS gating : PASS
2018 22:52:46.985360 RX DQ/DQS(RDDQC) : PASS
2019 22:52:46.985736 TX DQ/DQS : PASS
2020 22:52:46.988992 RX DATLAT : PASS
2021 22:52:46.991917 RX DQ/DQS(Engine): PASS
2022 22:52:46.992336 TX OE : NO K
2023 22:52:46.992684 All Pass.
2024 22:52:46.995255
2025 22:52:46.995763 DramC Write-DBI off
2026 22:52:46.998792 PER_BANK_REFRESH: Hybrid Mode
2027 22:52:46.999378 TX_TRACKING: ON
2028 22:52:47.002157 [GetDramInforAfterCalByMRR] Vendor 6.
2029 22:52:47.005665 [GetDramInforAfterCalByMRR] Revision 606.
2030 22:52:47.012053 [GetDramInforAfterCalByMRR] Revision 2 0.
2031 22:52:47.012618 MR0 0x3939
2032 22:52:47.013175 MR8 0x1111
2033 22:52:47.015275 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2034 22:52:47.015721
2035 22:52:47.019026 MR0 0x3939
2036 22:52:47.019453 MR8 0x1111
2037 22:52:47.021832 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2038 22:52:47.022355
2039 22:52:47.031813 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2040 22:52:47.035218 [FAST_K] Save calibration result to emmc
2041 22:52:47.038465 [FAST_K] Save calibration result to emmc
2042 22:52:47.042013 dram_init: config_dvfs: 1
2043 22:52:47.045541 dramc_set_vcore_voltage set vcore to 662500
2044 22:52:47.045990 Read voltage for 1200, 2
2045 22:52:47.048941 Vio18 = 0
2046 22:52:47.049405 Vcore = 662500
2047 22:52:47.049751 Vdram = 0
2048 22:52:47.052083 Vddq = 0
2049 22:52:47.052558 Vmddr = 0
2050 22:52:47.058856 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2051 22:52:47.062076 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2052 22:52:47.065268 MEM_TYPE=3, freq_sel=15
2053 22:52:47.068769 sv_algorithm_assistance_LP4_1600
2054 22:52:47.072219 ============ PULL DRAM RESETB DOWN ============
2055 22:52:47.075530 ========== PULL DRAM RESETB DOWN end =========
2056 22:52:47.081970 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2057 22:52:47.085426 ===================================
2058 22:52:47.085871 LPDDR4 DRAM CONFIGURATION
2059 22:52:47.089053 ===================================
2060 22:52:47.092002 EX_ROW_EN[0] = 0x0
2061 22:52:47.092523 EX_ROW_EN[1] = 0x0
2062 22:52:47.095342 LP4Y_EN = 0x0
2063 22:52:47.098730 WORK_FSP = 0x0
2064 22:52:47.099174 WL = 0x4
2065 22:52:47.102005 RL = 0x4
2066 22:52:47.102612 BL = 0x2
2067 22:52:47.105922 RPST = 0x0
2068 22:52:47.106405 RD_PRE = 0x0
2069 22:52:47.108739 WR_PRE = 0x1
2070 22:52:47.109171 WR_PST = 0x0
2071 22:52:47.112076 DBI_WR = 0x0
2072 22:52:47.112501 DBI_RD = 0x0
2073 22:52:47.115403 OTF = 0x1
2074 22:52:47.118621 ===================================
2075 22:52:47.122277 ===================================
2076 22:52:47.122793 ANA top config
2077 22:52:47.125349 ===================================
2078 22:52:47.128595 DLL_ASYNC_EN = 0
2079 22:52:47.132067 ALL_SLAVE_EN = 0
2080 22:52:47.132582 NEW_RANK_MODE = 1
2081 22:52:47.135321 DLL_IDLE_MODE = 1
2082 22:52:47.138630 LP45_APHY_COMB_EN = 1
2083 22:52:47.141966 TX_ODT_DIS = 1
2084 22:52:47.142680 NEW_8X_MODE = 1
2085 22:52:47.145176 ===================================
2086 22:52:47.148551 ===================================
2087 22:52:47.152084 data_rate = 2400
2088 22:52:47.155153 CKR = 1
2089 22:52:47.158787 DQ_P2S_RATIO = 8
2090 22:52:47.161905 ===================================
2091 22:52:47.165334 CA_P2S_RATIO = 8
2092 22:52:47.168559 DQ_CA_OPEN = 0
2093 22:52:47.169055 DQ_SEMI_OPEN = 0
2094 22:52:47.172059 CA_SEMI_OPEN = 0
2095 22:52:47.175294 CA_FULL_RATE = 0
2096 22:52:47.178456 DQ_CKDIV4_EN = 0
2097 22:52:47.182191 CA_CKDIV4_EN = 0
2098 22:52:47.185337 CA_PREDIV_EN = 0
2099 22:52:47.185931 PH8_DLY = 17
2100 22:52:47.189326 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2101 22:52:47.192071 DQ_AAMCK_DIV = 4
2102 22:52:47.195125 CA_AAMCK_DIV = 4
2103 22:52:47.198530 CA_ADMCK_DIV = 4
2104 22:52:47.201932 DQ_TRACK_CA_EN = 0
2105 22:52:47.205211 CA_PICK = 1200
2106 22:52:47.205897 CA_MCKIO = 1200
2107 22:52:47.208678 MCKIO_SEMI = 0
2108 22:52:47.211686 PLL_FREQ = 2366
2109 22:52:47.215124 DQ_UI_PI_RATIO = 32
2110 22:52:47.218598 CA_UI_PI_RATIO = 0
2111 22:52:47.221963 ===================================
2112 22:52:47.225367 ===================================
2113 22:52:47.228319 memory_type:LPDDR4
2114 22:52:47.228760 GP_NUM : 10
2115 22:52:47.231696 SRAM_EN : 1
2116 22:52:47.232146 MD32_EN : 0
2117 22:52:47.235124 ===================================
2118 22:52:47.238456 [ANA_INIT] >>>>>>>>>>>>>>
2119 22:52:47.241581 <<<<<< [CONFIGURE PHASE]: ANA_TX
2120 22:52:47.245258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2121 22:52:47.248402 ===================================
2122 22:52:47.251802 data_rate = 2400,PCW = 0X5b00
2123 22:52:47.255092 ===================================
2124 22:52:47.258326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2125 22:52:47.261984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2126 22:52:47.268883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2127 22:52:47.271677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2128 22:52:47.278483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2129 22:52:47.281624 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2130 22:52:47.282167 [ANA_INIT] flow start
2131 22:52:47.285123 [ANA_INIT] PLL >>>>>>>>
2132 22:52:47.288271 [ANA_INIT] PLL <<<<<<<<
2133 22:52:47.288786 [ANA_INIT] MIDPI >>>>>>>>
2134 22:52:47.291937 [ANA_INIT] MIDPI <<<<<<<<
2135 22:52:47.295010 [ANA_INIT] DLL >>>>>>>>
2136 22:52:47.295546 [ANA_INIT] DLL <<<<<<<<
2137 22:52:47.298578 [ANA_INIT] flow end
2138 22:52:47.301767 ============ LP4 DIFF to SE enter ============
2139 22:52:47.305227 ============ LP4 DIFF to SE exit ============
2140 22:52:47.308584 [ANA_INIT] <<<<<<<<<<<<<
2141 22:52:47.311671 [Flow] Enable top DCM control >>>>>
2142 22:52:47.314837 [Flow] Enable top DCM control <<<<<
2143 22:52:47.318500 Enable DLL master slave shuffle
2144 22:52:47.324827 ==============================================================
2145 22:52:47.325391 Gating Mode config
2146 22:52:47.331578 ==============================================================
2147 22:52:47.332143 Config description:
2148 22:52:47.341498 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2149 22:52:47.348398 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2150 22:52:47.354862 SELPH_MODE 0: By rank 1: By Phase
2151 22:52:47.358123 ==============================================================
2152 22:52:47.361709 GAT_TRACK_EN = 1
2153 22:52:47.365263 RX_GATING_MODE = 2
2154 22:52:47.368165 RX_GATING_TRACK_MODE = 2
2155 22:52:47.371538 SELPH_MODE = 1
2156 22:52:47.374825 PICG_EARLY_EN = 1
2157 22:52:47.378403 VALID_LAT_VALUE = 1
2158 22:52:47.381491 ==============================================================
2159 22:52:47.384826 Enter into Gating configuration >>>>
2160 22:52:47.388201 Exit from Gating configuration <<<<
2161 22:52:47.391777 Enter into DVFS_PRE_config >>>>>
2162 22:52:47.404782 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2163 22:52:47.408202 Exit from DVFS_PRE_config <<<<<
2164 22:52:47.411588 Enter into PICG configuration >>>>
2165 22:52:47.412132 Exit from PICG configuration <<<<
2166 22:52:47.414918 [RX_INPUT] configuration >>>>>
2167 22:52:47.418293 [RX_INPUT] configuration <<<<<
2168 22:52:47.424870 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2169 22:52:47.428190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2170 22:52:47.434881 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2171 22:52:47.441498 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2172 22:52:47.448441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2173 22:52:47.454551 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2174 22:52:47.458064 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2175 22:52:47.461454 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2176 22:52:47.464910 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2177 22:52:47.471332 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2178 22:52:47.474810 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2179 22:52:47.478168 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2180 22:52:47.481313 ===================================
2181 22:52:47.484802 LPDDR4 DRAM CONFIGURATION
2182 22:52:47.488060 ===================================
2183 22:52:47.491356 EX_ROW_EN[0] = 0x0
2184 22:52:47.491761 EX_ROW_EN[1] = 0x0
2185 22:52:47.494684 LP4Y_EN = 0x0
2186 22:52:47.495242 WORK_FSP = 0x0
2187 22:52:47.497943 WL = 0x4
2188 22:52:47.498361 RL = 0x4
2189 22:52:47.501333 BL = 0x2
2190 22:52:47.501893 RPST = 0x0
2191 22:52:47.504485 RD_PRE = 0x0
2192 22:52:47.504924 WR_PRE = 0x1
2193 22:52:47.507923 WR_PST = 0x0
2194 22:52:47.508366 DBI_WR = 0x0
2195 22:52:47.511392 DBI_RD = 0x0
2196 22:52:47.511827 OTF = 0x1
2197 22:52:47.514804 ===================================
2198 22:52:47.521496 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2199 22:52:47.524625 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2200 22:52:47.528409 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2201 22:52:47.531381 ===================================
2202 22:52:47.534648 LPDDR4 DRAM CONFIGURATION
2203 22:52:47.538112 ===================================
2204 22:52:47.538558 EX_ROW_EN[0] = 0x10
2205 22:52:47.541386 EX_ROW_EN[1] = 0x0
2206 22:52:47.544913 LP4Y_EN = 0x0
2207 22:52:47.545345 WORK_FSP = 0x0
2208 22:52:47.548574 WL = 0x4
2209 22:52:47.549017 RL = 0x4
2210 22:52:47.551829 BL = 0x2
2211 22:52:47.552279 RPST = 0x0
2212 22:52:47.555416 RD_PRE = 0x0
2213 22:52:47.555858 WR_PRE = 0x1
2214 22:52:47.558533 WR_PST = 0x0
2215 22:52:47.558981 DBI_WR = 0x0
2216 22:52:47.561530 DBI_RD = 0x0
2217 22:52:47.561975 OTF = 0x1
2218 22:52:47.564717 ===================================
2219 22:52:47.571228 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2220 22:52:47.571662 ==
2221 22:52:47.574486 Dram Type= 6, Freq= 0, CH_0, rank 0
2222 22:52:47.577813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2223 22:52:47.581451 ==
2224 22:52:47.581928 [Duty_Offset_Calibration]
2225 22:52:47.584879 B0:0 B1:2 CA:1
2226 22:52:47.585418
2227 22:52:47.587744 [DutyScan_Calibration_Flow] k_type=0
2228 22:52:47.596178
2229 22:52:47.596750 ==CLK 0==
2230 22:52:47.599645 Final CLK duty delay cell = 0
2231 22:52:47.602686 [0] MAX Duty = 5093%(X100), DQS PI = 12
2232 22:52:47.606192 [0] MIN Duty = 4938%(X100), DQS PI = 52
2233 22:52:47.606628 [0] AVG Duty = 5015%(X100)
2234 22:52:47.609469
2235 22:52:47.612804 CH0 CLK Duty spec in!! Max-Min= 155%
2236 22:52:47.616232 [DutyScan_Calibration_Flow] ====Done====
2237 22:52:47.616860
2238 22:52:47.619420 [DutyScan_Calibration_Flow] k_type=1
2239 22:52:47.635681
2240 22:52:47.636287 ==DQS 0 ==
2241 22:52:47.638720 Final DQS duty delay cell = 0
2242 22:52:47.642448 [0] MAX Duty = 5125%(X100), DQS PI = 32
2243 22:52:47.645542 [0] MIN Duty = 5031%(X100), DQS PI = 4
2244 22:52:47.646155 [0] AVG Duty = 5078%(X100)
2245 22:52:47.648872
2246 22:52:47.649382 ==DQS 1 ==
2247 22:52:47.652116 Final DQS duty delay cell = 0
2248 22:52:47.655668 [0] MAX Duty = 5062%(X100), DQS PI = 58
2249 22:52:47.658870 [0] MIN Duty = 4906%(X100), DQS PI = 16
2250 22:52:47.659404 [0] AVG Duty = 4984%(X100)
2251 22:52:47.662047
2252 22:52:47.665406 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2253 22:52:47.666012
2254 22:52:47.669360 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2255 22:52:47.672294 [DutyScan_Calibration_Flow] ====Done====
2256 22:52:47.672808
2257 22:52:47.675244 [DutyScan_Calibration_Flow] k_type=3
2258 22:52:47.692628
2259 22:52:47.693116 ==DQM 0 ==
2260 22:52:47.696204 Final DQM duty delay cell = 0
2261 22:52:47.699326 [0] MAX Duty = 5187%(X100), DQS PI = 22
2262 22:52:47.702596 [0] MIN Duty = 4969%(X100), DQS PI = 40
2263 22:52:47.703222 [0] AVG Duty = 5078%(X100)
2264 22:52:47.706357
2265 22:52:47.706851 ==DQM 1 ==
2266 22:52:47.709461 Final DQM duty delay cell = 4
2267 22:52:47.712531 [4] MAX Duty = 5187%(X100), DQS PI = 52
2268 22:52:47.715819 [4] MIN Duty = 5000%(X100), DQS PI = 16
2269 22:52:47.716225 [4] AVG Duty = 5093%(X100)
2270 22:52:47.719428
2271 22:52:47.722966 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2272 22:52:47.723370
2273 22:52:47.725991 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2274 22:52:47.729560 [DutyScan_Calibration_Flow] ====Done====
2275 22:52:47.730184
2276 22:52:47.732600 [DutyScan_Calibration_Flow] k_type=2
2277 22:52:47.748040
2278 22:52:47.748465 ==DQ 0 ==
2279 22:52:47.750907 Final DQ duty delay cell = -4
2280 22:52:47.754158 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2281 22:52:47.757539 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2282 22:52:47.761072 [-4] AVG Duty = 4937%(X100)
2283 22:52:47.761580
2284 22:52:47.761992 ==DQ 1 ==
2285 22:52:47.764408 Final DQ duty delay cell = -4
2286 22:52:47.767632 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2287 22:52:47.771129 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2288 22:52:47.774399 [-4] AVG Duty = 4984%(X100)
2289 22:52:47.774827
2290 22:52:47.777637 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2291 22:52:47.778206
2292 22:52:47.780888 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2293 22:52:47.784157 [DutyScan_Calibration_Flow] ====Done====
2294 22:52:47.784593 ==
2295 22:52:47.787621 Dram Type= 6, Freq= 0, CH_1, rank 0
2296 22:52:47.790881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2297 22:52:47.791320 ==
2298 22:52:47.794183 [Duty_Offset_Calibration]
2299 22:52:47.794733 B0:0 B1:5 CA:-5
2300 22:52:47.795090
2301 22:52:47.797492 [DutyScan_Calibration_Flow] k_type=0
2302 22:52:47.808217
2303 22:52:47.808741 ==CLK 0==
2304 22:52:47.811472 Final CLK duty delay cell = 0
2305 22:52:47.814636 [0] MAX Duty = 5094%(X100), DQS PI = 24
2306 22:52:47.818448 [0] MIN Duty = 4907%(X100), DQS PI = 42
2307 22:52:47.819094 [0] AVG Duty = 5000%(X100)
2308 22:52:47.821338
2309 22:52:47.824933 CH1 CLK Duty spec in!! Max-Min= 187%
2310 22:52:47.828205 [DutyScan_Calibration_Flow] ====Done====
2311 22:52:47.828667
2312 22:52:47.831198 [DutyScan_Calibration_Flow] k_type=1
2313 22:52:47.846679
2314 22:52:47.847106 ==DQS 0 ==
2315 22:52:47.850058 Final DQS duty delay cell = 0
2316 22:52:47.853160 [0] MAX Duty = 5125%(X100), DQS PI = 16
2317 22:52:47.856850 [0] MIN Duty = 4875%(X100), DQS PI = 40
2318 22:52:47.860067 [0] AVG Duty = 5000%(X100)
2319 22:52:47.860619
2320 22:52:47.861107 ==DQS 1 ==
2321 22:52:47.863271 Final DQS duty delay cell = -4
2322 22:52:47.866466 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2323 22:52:47.869782 [-4] MIN Duty = 4907%(X100), DQS PI = 58
2324 22:52:47.873290 [-4] AVG Duty = 4969%(X100)
2325 22:52:47.873726
2326 22:52:47.876649 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2327 22:52:47.877199
2328 22:52:47.879897 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2329 22:52:47.883163 [DutyScan_Calibration_Flow] ====Done====
2330 22:52:47.883613
2331 22:52:47.886611 [DutyScan_Calibration_Flow] k_type=3
2332 22:52:47.901902
2333 22:52:47.902504 ==DQM 0 ==
2334 22:52:47.905257 Final DQM duty delay cell = -4
2335 22:52:47.908559 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2336 22:52:47.911820 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2337 22:52:47.915365 [-4] AVG Duty = 4968%(X100)
2338 22:52:47.915923
2339 22:52:47.916412 ==DQM 1 ==
2340 22:52:47.918721 Final DQM duty delay cell = -4
2341 22:52:47.921996 [-4] MAX Duty = 5094%(X100), DQS PI = 22
2342 22:52:47.925267 [-4] MIN Duty = 4906%(X100), DQS PI = 42
2343 22:52:47.928675 [-4] AVG Duty = 5000%(X100)
2344 22:52:47.929256
2345 22:52:47.932094 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2346 22:52:47.932624
2347 22:52:47.935517 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2348 22:52:47.938574 [DutyScan_Calibration_Flow] ====Done====
2349 22:52:47.939005
2350 22:52:47.941731 [DutyScan_Calibration_Flow] k_type=2
2351 22:52:47.959164
2352 22:52:47.959595 ==DQ 0 ==
2353 22:52:47.962912 Final DQ duty delay cell = 0
2354 22:52:47.965797 [0] MAX Duty = 5093%(X100), DQS PI = 0
2355 22:52:47.969509 [0] MIN Duty = 4938%(X100), DQS PI = 44
2356 22:52:47.969955 [0] AVG Duty = 5015%(X100)
2357 22:52:47.970364
2358 22:52:47.972914 ==DQ 1 ==
2359 22:52:47.975841 Final DQ duty delay cell = 0
2360 22:52:47.978951 [0] MAX Duty = 5000%(X100), DQS PI = 6
2361 22:52:47.982527 [0] MIN Duty = 4907%(X100), DQS PI = 0
2362 22:52:47.982958 [0] AVG Duty = 4953%(X100)
2363 22:52:47.983302
2364 22:52:47.985615 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2365 22:52:47.986082
2366 22:52:47.989102 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2367 22:52:47.996040 [DutyScan_Calibration_Flow] ====Done====
2368 22:52:47.998967 nWR fixed to 30
2369 22:52:47.999525 [ModeRegInit_LP4] CH0 RK0
2370 22:52:48.002485 [ModeRegInit_LP4] CH0 RK1
2371 22:52:48.005521 [ModeRegInit_LP4] CH1 RK0
2372 22:52:48.005946 [ModeRegInit_LP4] CH1 RK1
2373 22:52:48.009102 match AC timing 6
2374 22:52:48.012427 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2375 22:52:48.016090 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2376 22:52:48.022476 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2377 22:52:48.025488 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2378 22:52:48.032251 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2379 22:52:48.032805 ==
2380 22:52:48.035815 Dram Type= 6, Freq= 0, CH_0, rank 0
2381 22:52:48.038979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2382 22:52:48.039406 ==
2383 22:52:48.045855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2384 22:52:48.049016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2385 22:52:48.058633 [CA 0] Center 39 (9~70) winsize 62
2386 22:52:48.061997 [CA 1] Center 39 (8~70) winsize 63
2387 22:52:48.065416 [CA 2] Center 36 (5~67) winsize 63
2388 22:52:48.068807 [CA 3] Center 35 (4~66) winsize 63
2389 22:52:48.072361 [CA 4] Center 34 (3~65) winsize 63
2390 22:52:48.075705 [CA 5] Center 33 (3~64) winsize 62
2391 22:52:48.076138
2392 22:52:48.078584 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2393 22:52:48.079012
2394 22:52:48.082131 [CATrainingPosCal] consider 1 rank data
2395 22:52:48.085228 u2DelayCellTimex100 = 270/100 ps
2396 22:52:48.088887 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2397 22:52:48.092272 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2398 22:52:48.098729 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2399 22:52:48.101931 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2400 22:52:48.105428 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2401 22:52:48.108566 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2402 22:52:48.108999
2403 22:52:48.111953 CA PerBit enable=1, Macro0, CA PI delay=33
2404 22:52:48.112510
2405 22:52:48.115459 [CBTSetCACLKResult] CA Dly = 33
2406 22:52:48.116021 CS Dly: 7 (0~38)
2407 22:52:48.118876 ==
2408 22:52:48.119310 Dram Type= 6, Freq= 0, CH_0, rank 1
2409 22:52:48.125316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2410 22:52:48.125743 ==
2411 22:52:48.128579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2412 22:52:48.135291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2413 22:52:48.144202 [CA 0] Center 39 (8~70) winsize 63
2414 22:52:48.147722 [CA 1] Center 39 (8~70) winsize 63
2415 22:52:48.150897 [CA 2] Center 36 (5~67) winsize 63
2416 22:52:48.154153 [CA 3] Center 35 (4~66) winsize 63
2417 22:52:48.158145 [CA 4] Center 33 (3~64) winsize 62
2418 22:52:48.160817 [CA 5] Center 34 (3~65) winsize 63
2419 22:52:48.161256
2420 22:52:48.164386 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2421 22:52:48.164824
2422 22:52:48.167542 [CATrainingPosCal] consider 2 rank data
2423 22:52:48.170549 u2DelayCellTimex100 = 270/100 ps
2424 22:52:48.174475 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2425 22:52:48.180608 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2426 22:52:48.184334 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2427 22:52:48.187188 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2428 22:52:48.190847 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2429 22:52:48.194496 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2430 22:52:48.194945
2431 22:52:48.197249 CA PerBit enable=1, Macro0, CA PI delay=33
2432 22:52:48.197705
2433 22:52:48.200737 [CBTSetCACLKResult] CA Dly = 33
2434 22:52:48.201298 CS Dly: 7 (0~39)
2435 22:52:48.203741
2436 22:52:48.207316 ----->DramcWriteLeveling(PI) begin...
2437 22:52:48.207749 ==
2438 22:52:48.210880 Dram Type= 6, Freq= 0, CH_0, rank 0
2439 22:52:48.214008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2440 22:52:48.214477 ==
2441 22:52:48.217131 Write leveling (Byte 0): 26 => 26
2442 22:52:48.220608 Write leveling (Byte 1): 26 => 26
2443 22:52:48.223974 DramcWriteLeveling(PI) end<-----
2444 22:52:48.224401
2445 22:52:48.224751 ==
2446 22:52:48.227909 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 22:52:48.230481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2448 22:52:48.230917 ==
2449 22:52:48.233920 [Gating] SW mode calibration
2450 22:52:48.241007 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2451 22:52:48.247189 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2452 22:52:48.250443 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2453 22:52:48.253836 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2454 22:52:48.260394 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2455 22:52:48.263782 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2456 22:52:48.267320 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2457 22:52:48.270770 0 11 20 | B1->B0 | 2c2c 2b2b | 1 0 | (1 0) (0 0)
2458 22:52:48.277249 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2459 22:52:48.280920 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2460 22:52:48.283890 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2461 22:52:48.290405 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2462 22:52:48.294077 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2463 22:52:48.297223 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2464 22:52:48.303757 0 12 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
2465 22:52:48.307208 0 12 20 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (0 0)
2466 22:52:48.310827 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2467 22:52:48.317132 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2468 22:52:48.320347 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2469 22:52:48.323778 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2470 22:52:48.330633 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2471 22:52:48.333649 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2472 22:52:48.337050 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2473 22:52:48.343936 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2474 22:52:48.347049 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 22:52:48.350609 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 22:52:48.357052 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 22:52:48.360453 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 22:52:48.363850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 22:52:48.366936 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 22:52:48.373562 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 22:52:48.377515 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 22:52:48.380415 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 22:52:48.387295 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 22:52:48.390494 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 22:52:48.393915 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 22:52:48.400532 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 22:52:48.403963 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 22:52:48.407445 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2489 22:52:48.413782 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2490 22:52:48.417243 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2491 22:52:48.421201 Total UI for P1: 0, mck2ui 16
2492 22:52:48.423920 best dqsien dly found for B0: ( 0, 15, 20)
2493 22:52:48.427137 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2494 22:52:48.430439 Total UI for P1: 0, mck2ui 16
2495 22:52:48.434063 best dqsien dly found for B1: ( 0, 15, 22)
2496 22:52:48.437066 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2497 22:52:48.440585 best DQS1 dly(MCK, UI, PI) = (0, 15, 22)
2498 22:52:48.441141
2499 22:52:48.444005 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2500 22:52:48.450564 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22)
2501 22:52:48.451022 [Gating] SW calibration Done
2502 22:52:48.454055 ==
2503 22:52:48.454450 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 22:52:48.460943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2505 22:52:48.461433 ==
2506 22:52:48.461824 RX Vref Scan: 0
2507 22:52:48.462269
2508 22:52:48.464227 RX Vref 0 -> 0, step: 1
2509 22:52:48.464777
2510 22:52:48.467244 RX Delay -40 -> 252, step: 8
2511 22:52:48.470650 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2512 22:52:48.474018 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2513 22:52:48.477573 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2514 22:52:48.484211 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2515 22:52:48.487209 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2516 22:52:48.490916 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2517 22:52:48.494098 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2518 22:52:48.497452 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2519 22:52:48.500700 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2520 22:52:48.507372 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2521 22:52:48.510807 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2522 22:52:48.513942 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2523 22:52:48.517610 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2524 22:52:48.524122 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2525 22:52:48.527679 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2526 22:52:48.530853 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2527 22:52:48.531285 ==
2528 22:52:48.533948 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 22:52:48.537315 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2530 22:52:48.537783 ==
2531 22:52:48.540604 DQS Delay:
2532 22:52:48.541158 DQS0 = 0, DQS1 = 0
2533 22:52:48.541498 DQM Delay:
2534 22:52:48.544011 DQM0 = 115, DQM1 = 106
2535 22:52:48.544459 DQ Delay:
2536 22:52:48.547403 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2537 22:52:48.550867 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2538 22:52:48.557255 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2539 22:52:48.561012 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2540 22:52:48.561515
2541 22:52:48.562106
2542 22:52:48.562643 ==
2543 22:52:48.564020 Dram Type= 6, Freq= 0, CH_0, rank 0
2544 22:52:48.567744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2545 22:52:48.568267 ==
2546 22:52:48.568749
2547 22:52:48.569196
2548 22:52:48.570628 TX Vref Scan disable
2549 22:52:48.571055 == TX Byte 0 ==
2550 22:52:48.577304 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2551 22:52:48.580413 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2552 22:52:48.580982 == TX Byte 1 ==
2553 22:52:48.587022 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2554 22:52:48.590762 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2555 22:52:48.591291 ==
2556 22:52:48.594006 Dram Type= 6, Freq= 0, CH_0, rank 0
2557 22:52:48.597134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2558 22:52:48.597643 ==
2559 22:52:48.609835 TX Vref=22, minBit 8, minWin=25, winSum=410
2560 22:52:48.613116 TX Vref=24, minBit 4, minWin=25, winSum=416
2561 22:52:48.616701 TX Vref=26, minBit 1, minWin=26, winSum=423
2562 22:52:48.619954 TX Vref=28, minBit 10, minWin=25, winSum=425
2563 22:52:48.623248 TX Vref=30, minBit 4, minWin=26, winSum=429
2564 22:52:48.629882 TX Vref=32, minBit 5, minWin=26, winSum=427
2565 22:52:48.633455 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 30
2566 22:52:48.633968
2567 22:52:48.636612 Final TX Range 1 Vref 30
2568 22:52:48.637127
2569 22:52:48.637469 ==
2570 22:52:48.639792 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 22:52:48.643272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2572 22:52:48.643652 ==
2573 22:52:48.643988
2574 22:52:48.646517
2575 22:52:48.646880 TX Vref Scan disable
2576 22:52:48.649887 == TX Byte 0 ==
2577 22:52:48.653336 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2578 22:52:48.656538 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2579 22:52:48.659896 == TX Byte 1 ==
2580 22:52:48.663267 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2581 22:52:48.666287 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2582 22:52:48.666647
2583 22:52:48.669845 [DATLAT]
2584 22:52:48.670310 Freq=1200, CH0 RK0
2585 22:52:48.670643
2586 22:52:48.673169 DATLAT Default: 0xd
2587 22:52:48.673545 0, 0xFFFF, sum = 0
2588 22:52:48.676331 1, 0xFFFF, sum = 0
2589 22:52:48.676705 2, 0xFFFF, sum = 0
2590 22:52:48.679729 3, 0xFFFF, sum = 0
2591 22:52:48.680112 4, 0xFFFF, sum = 0
2592 22:52:48.683145 5, 0xFFFF, sum = 0
2593 22:52:48.683514 6, 0xFFFF, sum = 0
2594 22:52:48.686331 7, 0xFFFF, sum = 0
2595 22:52:48.686712 8, 0xFFFF, sum = 0
2596 22:52:48.689838 9, 0xFFFF, sum = 0
2597 22:52:48.693150 10, 0xFFFF, sum = 0
2598 22:52:48.693656 11, 0x0, sum = 1
2599 22:52:48.694143 12, 0x0, sum = 2
2600 22:52:48.696598 13, 0x0, sum = 3
2601 22:52:48.697106 14, 0x0, sum = 4
2602 22:52:48.700071 best_step = 12
2603 22:52:48.700570
2604 22:52:48.700997 ==
2605 22:52:48.703379 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 22:52:48.706477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2607 22:52:48.706965 ==
2608 22:52:48.709951 RX Vref Scan: 1
2609 22:52:48.710416
2610 22:52:48.710848 Set Vref Range= 32 -> 127
2611 22:52:48.713415
2612 22:52:48.713911 RX Vref 32 -> 127, step: 1
2613 22:52:48.714300
2614 22:52:48.716469 RX Delay -21 -> 252, step: 4
2615 22:52:48.716971
2616 22:52:48.720122 Set Vref, RX VrefLevel [Byte0]: 32
2617 22:52:48.723338 [Byte1]: 32
2618 22:52:48.723870
2619 22:52:48.726820 Set Vref, RX VrefLevel [Byte0]: 33
2620 22:52:48.729785 [Byte1]: 33
2621 22:52:48.734334
2622 22:52:48.734803 Set Vref, RX VrefLevel [Byte0]: 34
2623 22:52:48.737546 [Byte1]: 34
2624 22:52:48.742332
2625 22:52:48.742712 Set Vref, RX VrefLevel [Byte0]: 35
2626 22:52:48.745262 [Byte1]: 35
2627 22:52:48.750293
2628 22:52:48.750685 Set Vref, RX VrefLevel [Byte0]: 36
2629 22:52:48.753361 [Byte1]: 36
2630 22:52:48.757893
2631 22:52:48.758352 Set Vref, RX VrefLevel [Byte0]: 37
2632 22:52:48.761214 [Byte1]: 37
2633 22:52:48.765779
2634 22:52:48.766251 Set Vref, RX VrefLevel [Byte0]: 38
2635 22:52:48.769327 [Byte1]: 38
2636 22:52:48.773913
2637 22:52:48.774316 Set Vref, RX VrefLevel [Byte0]: 39
2638 22:52:48.777106 [Byte1]: 39
2639 22:52:48.781848
2640 22:52:48.782256 Set Vref, RX VrefLevel [Byte0]: 40
2641 22:52:48.785006 [Byte1]: 40
2642 22:52:48.789855
2643 22:52:48.790263 Set Vref, RX VrefLevel [Byte0]: 41
2644 22:52:48.792908 [Byte1]: 41
2645 22:52:48.797861
2646 22:52:48.798417 Set Vref, RX VrefLevel [Byte0]: 42
2647 22:52:48.800789 [Byte1]: 42
2648 22:52:48.805536
2649 22:52:48.806058 Set Vref, RX VrefLevel [Byte0]: 43
2650 22:52:48.808648 [Byte1]: 43
2651 22:52:48.813533
2652 22:52:48.813981 Set Vref, RX VrefLevel [Byte0]: 44
2653 22:52:48.817059 [Byte1]: 44
2654 22:52:48.821854
2655 22:52:48.822324 Set Vref, RX VrefLevel [Byte0]: 45
2656 22:52:48.824678 [Byte1]: 45
2657 22:52:48.829354
2658 22:52:48.829726 Set Vref, RX VrefLevel [Byte0]: 46
2659 22:52:48.832627 [Byte1]: 46
2660 22:52:48.837032
2661 22:52:48.837573 Set Vref, RX VrefLevel [Byte0]: 47
2662 22:52:48.840493 [Byte1]: 47
2663 22:52:48.845026
2664 22:52:48.845535 Set Vref, RX VrefLevel [Byte0]: 48
2665 22:52:48.848721 [Byte1]: 48
2666 22:52:48.853218
2667 22:52:48.853821 Set Vref, RX VrefLevel [Byte0]: 49
2668 22:52:48.856287 [Byte1]: 49
2669 22:52:48.861308
2670 22:52:48.861747 Set Vref, RX VrefLevel [Byte0]: 50
2671 22:52:48.864319 [Byte1]: 50
2672 22:52:48.868980
2673 22:52:48.869434 Set Vref, RX VrefLevel [Byte0]: 51
2674 22:52:48.872271 [Byte1]: 51
2675 22:52:48.877198
2676 22:52:48.877574 Set Vref, RX VrefLevel [Byte0]: 52
2677 22:52:48.880253 [Byte1]: 52
2678 22:52:48.885020
2679 22:52:48.885481 Set Vref, RX VrefLevel [Byte0]: 53
2680 22:52:48.888093 [Byte1]: 53
2681 22:52:48.892853
2682 22:52:48.893347 Set Vref, RX VrefLevel [Byte0]: 54
2683 22:52:48.895878 [Byte1]: 54
2684 22:52:48.900852
2685 22:52:48.901332 Set Vref, RX VrefLevel [Byte0]: 55
2686 22:52:48.904025 [Byte1]: 55
2687 22:52:48.908813
2688 22:52:48.909178 Set Vref, RX VrefLevel [Byte0]: 56
2689 22:52:48.911868 [Byte1]: 56
2690 22:52:48.916583
2691 22:52:48.917080 Set Vref, RX VrefLevel [Byte0]: 57
2692 22:52:48.920034 [Byte1]: 57
2693 22:52:48.924526
2694 22:52:48.925051 Set Vref, RX VrefLevel [Byte0]: 58
2695 22:52:48.927666 [Byte1]: 58
2696 22:52:48.932414
2697 22:52:48.932921 Set Vref, RX VrefLevel [Byte0]: 59
2698 22:52:48.935543 [Byte1]: 59
2699 22:52:48.940312
2700 22:52:48.940841 Set Vref, RX VrefLevel [Byte0]: 60
2701 22:52:48.943549 [Byte1]: 60
2702 22:52:48.948040
2703 22:52:48.948562 Set Vref, RX VrefLevel [Byte0]: 61
2704 22:52:48.951570 [Byte1]: 61
2705 22:52:48.957026
2706 22:52:48.957438 Set Vref, RX VrefLevel [Byte0]: 62
2707 22:52:48.959463 [Byte1]: 62
2708 22:52:48.964030
2709 22:52:48.964548 Set Vref, RX VrefLevel [Byte0]: 63
2710 22:52:48.967238 [Byte1]: 63
2711 22:52:48.971877
2712 22:52:48.972268 Set Vref, RX VrefLevel [Byte0]: 64
2713 22:52:48.975314 [Byte1]: 64
2714 22:52:48.979797
2715 22:52:48.980186 Set Vref, RX VrefLevel [Byte0]: 65
2716 22:52:48.983109 [Byte1]: 65
2717 22:52:48.987669
2718 22:52:48.988176 Set Vref, RX VrefLevel [Byte0]: 66
2719 22:52:48.991058 [Byte1]: 66
2720 22:52:48.995916
2721 22:52:48.996423 Final RX Vref Byte 0 = 47 to rank0
2722 22:52:48.998918 Final RX Vref Byte 1 = 49 to rank0
2723 22:52:49.002284 Final RX Vref Byte 0 = 47 to rank1
2724 22:52:49.005470 Final RX Vref Byte 1 = 49 to rank1==
2725 22:52:49.008914 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 22:52:49.015628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2727 22:52:49.016025 ==
2728 22:52:49.016365 DQS Delay:
2729 22:52:49.016693 DQS0 = 0, DQS1 = 0
2730 22:52:49.019070 DQM Delay:
2731 22:52:49.019440 DQM0 = 114, DQM1 = 105
2732 22:52:49.022309 DQ Delay:
2733 22:52:49.025523 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2734 22:52:49.028777 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2735 22:52:49.032224 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2736 22:52:49.035590 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2737 22:52:49.036095
2738 22:52:49.036563
2739 22:52:49.042467 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2740 22:52:49.045590 CH0 RK0: MR19=404, MR18=B0B
2741 22:52:49.052095 CH0_RK0: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2742 22:52:49.052637
2743 22:52:49.055491 ----->DramcWriteLeveling(PI) begin...
2744 22:52:49.055951 ==
2745 22:52:49.058984 Dram Type= 6, Freq= 0, CH_0, rank 1
2746 22:52:49.062130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2747 22:52:49.062533 ==
2748 22:52:49.065754 Write leveling (Byte 0): 28 => 28
2749 22:52:49.068775 Write leveling (Byte 1): 24 => 24
2750 22:52:49.072407 DramcWriteLeveling(PI) end<-----
2751 22:52:49.072914
2752 22:52:49.073375 ==
2753 22:52:49.075397 Dram Type= 6, Freq= 0, CH_0, rank 1
2754 22:52:49.078770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2755 22:52:49.081970 ==
2756 22:52:49.082388 [Gating] SW mode calibration
2757 22:52:49.091933 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2758 22:52:49.095550 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2759 22:52:49.098683 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2760 22:52:49.105351 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2761 22:52:49.108746 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2762 22:52:49.112075 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2763 22:52:49.118800 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2764 22:52:49.122207 0 11 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2765 22:52:49.125412 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2766 22:52:49.132314 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2767 22:52:49.135626 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2768 22:52:49.138707 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2769 22:52:49.145339 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2770 22:52:49.148921 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2771 22:52:49.151983 0 12 16 | B1->B0 | 2828 3636 | 0 1 | (0 0) (0 0)
2772 22:52:49.159107 0 12 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2773 22:52:49.162019 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2774 22:52:49.165809 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2775 22:52:49.171996 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2776 22:52:49.175372 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2777 22:52:49.178793 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2778 22:52:49.182093 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2779 22:52:49.188596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2780 22:52:49.192008 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2781 22:52:49.195433 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 22:52:49.201995 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 22:52:49.205682 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 22:52:49.208810 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 22:52:49.215527 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 22:52:49.218923 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 22:52:49.222179 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 22:52:49.228841 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 22:52:49.232065 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2790 22:52:49.235433 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2791 22:52:49.242137 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 22:52:49.245495 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 22:52:49.248682 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2794 22:52:49.255586 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2795 22:52:49.258619 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2796 22:52:49.262081 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2797 22:52:49.265587 Total UI for P1: 0, mck2ui 16
2798 22:52:49.268651 best dqsien dly found for B0: ( 0, 15, 18)
2799 22:52:49.271932 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2800 22:52:49.275426 Total UI for P1: 0, mck2ui 16
2801 22:52:49.278769 best dqsien dly found for B1: ( 0, 15, 20)
2802 22:52:49.282266 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2803 22:52:49.288700 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2804 22:52:49.289091
2805 22:52:49.292149 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2806 22:52:49.295493 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2807 22:52:49.298708 [Gating] SW calibration Done
2808 22:52:49.299213 ==
2809 22:52:49.302058 Dram Type= 6, Freq= 0, CH_0, rank 1
2810 22:52:49.305396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2811 22:52:49.305904 ==
2812 22:52:49.308871 RX Vref Scan: 0
2813 22:52:49.309236
2814 22:52:49.309566 RX Vref 0 -> 0, step: 1
2815 22:52:49.309968
2816 22:52:49.311938 RX Delay -40 -> 252, step: 8
2817 22:52:49.315357 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2818 22:52:49.318510 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2819 22:52:49.325550 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2820 22:52:49.329146 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2821 22:52:49.331942 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2822 22:52:49.335339 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2823 22:52:49.338982 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2824 22:52:49.345473 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2825 22:52:49.348749 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2826 22:52:49.352168 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2827 22:52:49.355199 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2828 22:52:49.358746 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2829 22:52:49.365566 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2830 22:52:49.368551 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2831 22:52:49.371936 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2832 22:52:49.375640 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2833 22:52:49.376148 ==
2834 22:52:49.378464 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 22:52:49.385180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2836 22:52:49.385600 ==
2837 22:52:49.386101 DQS Delay:
2838 22:52:49.386438 DQS0 = 0, DQS1 = 0
2839 22:52:49.388856 DQM Delay:
2840 22:52:49.389276 DQM0 = 113, DQM1 = 107
2841 22:52:49.391886 DQ Delay:
2842 22:52:49.395126 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =107
2843 22:52:49.398900 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2844 22:52:49.401955 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2845 22:52:49.405260 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2846 22:52:49.405639
2847 22:52:49.405974
2848 22:52:49.406328 ==
2849 22:52:49.408556 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 22:52:49.411870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2851 22:52:49.412323 ==
2852 22:52:49.412691
2853 22:52:49.415320
2854 22:52:49.415764 TX Vref Scan disable
2855 22:52:49.418521 == TX Byte 0 ==
2856 22:52:49.422131 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2857 22:52:49.425207 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2858 22:52:49.428510 == TX Byte 1 ==
2859 22:52:49.431919 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2860 22:52:49.435315 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2861 22:52:49.435832 ==
2862 22:52:49.438525 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 22:52:49.445066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2864 22:52:49.445544 ==
2865 22:52:49.455798 TX Vref=22, minBit 10, minWin=24, winSum=421
2866 22:52:49.459321 TX Vref=24, minBit 10, minWin=24, winSum=422
2867 22:52:49.462348 TX Vref=26, minBit 8, minWin=25, winSum=428
2868 22:52:49.466016 TX Vref=28, minBit 8, minWin=25, winSum=430
2869 22:52:49.469181 TX Vref=30, minBit 8, minWin=26, winSum=434
2870 22:52:49.475437 TX Vref=32, minBit 8, minWin=25, winSum=433
2871 22:52:49.479111 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
2872 22:52:49.479639
2873 22:52:49.482595 Final TX Range 1 Vref 30
2874 22:52:49.482992
2875 22:52:49.483324 ==
2876 22:52:49.485654 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 22:52:49.489305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2878 22:52:49.489688 ==
2879 22:52:49.492317
2880 22:52:49.492701
2881 22:52:49.493168 TX Vref Scan disable
2882 22:52:49.495618 == TX Byte 0 ==
2883 22:52:49.499362 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2884 22:52:49.502427 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2885 22:52:49.506082 == TX Byte 1 ==
2886 22:52:49.509276 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2887 22:52:49.512456 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2888 22:52:49.515597
2889 22:52:49.515990 [DATLAT]
2890 22:52:49.516324 Freq=1200, CH0 RK1
2891 22:52:49.516663
2892 22:52:49.518947 DATLAT Default: 0xc
2893 22:52:49.519321 0, 0xFFFF, sum = 0
2894 22:52:49.522279 1, 0xFFFF, sum = 0
2895 22:52:49.522805 2, 0xFFFF, sum = 0
2896 22:52:49.525496 3, 0xFFFF, sum = 0
2897 22:52:49.528996 4, 0xFFFF, sum = 0
2898 22:52:49.529566 5, 0xFFFF, sum = 0
2899 22:52:49.532248 6, 0xFFFF, sum = 0
2900 22:52:49.532821 7, 0xFFFF, sum = 0
2901 22:52:49.535924 8, 0xFFFF, sum = 0
2902 22:52:49.536500 9, 0xFFFF, sum = 0
2903 22:52:49.538805 10, 0xFFFF, sum = 0
2904 22:52:49.539280 11, 0x0, sum = 1
2905 22:52:49.542337 12, 0x0, sum = 2
2906 22:52:49.542791 13, 0x0, sum = 3
2907 22:52:49.545578 14, 0x0, sum = 4
2908 22:52:49.546207 best_step = 12
2909 22:52:49.546698
2910 22:52:49.547214 ==
2911 22:52:49.548953 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 22:52:49.552240 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2913 22:52:49.552812 ==
2914 22:52:49.555526 RX Vref Scan: 0
2915 22:52:49.555965
2916 22:52:49.558845 RX Vref 0 -> 0, step: 1
2917 22:52:49.559277
2918 22:52:49.559625 RX Delay -21 -> 252, step: 4
2919 22:52:49.566436 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2920 22:52:49.569719 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2921 22:52:49.572648 iDelay=195, Bit 2, Center 114 (43 ~ 186) 144
2922 22:52:49.576196 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2923 22:52:49.579546 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2924 22:52:49.586125 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2925 22:52:49.589469 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2926 22:52:49.593221 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2927 22:52:49.596059 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2928 22:52:49.599705 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2929 22:52:49.606301 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
2930 22:52:49.609938 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2931 22:52:49.612803 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
2932 22:52:49.616088 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2933 22:52:49.619426 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2934 22:52:49.625891 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2935 22:52:49.626624 ==
2936 22:52:49.629465 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 22:52:49.632628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2938 22:52:49.633193 ==
2939 22:52:49.633559 DQS Delay:
2940 22:52:49.636072 DQS0 = 0, DQS1 = 0
2941 22:52:49.636683 DQM Delay:
2942 22:52:49.639243 DQM0 = 115, DQM1 = 105
2943 22:52:49.639800 DQ Delay:
2944 22:52:49.642779 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2945 22:52:49.645980 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2946 22:52:49.649412 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2947 22:52:49.652619 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2948 22:52:49.653179
2949 22:52:49.653537
2950 22:52:49.662673 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2951 22:52:49.665713 CH0 RK1: MR19=404, MR18=E0E
2952 22:52:49.668960 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2953 22:52:49.672329 [RxdqsGatingPostProcess] freq 1200
2954 22:52:49.678828 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2955 22:52:49.682151 Pre-setting of DQS Precalculation
2956 22:52:49.685619 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2957 22:52:49.685727 ==
2958 22:52:49.688893 Dram Type= 6, Freq= 0, CH_1, rank 0
2959 22:52:49.695526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2960 22:52:49.695636 ==
2961 22:52:49.699391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2962 22:52:49.705509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2963 22:52:49.714212 [CA 0] Center 37 (7~68) winsize 62
2964 22:52:49.717344 [CA 1] Center 37 (7~68) winsize 62
2965 22:52:49.721117 [CA 2] Center 34 (4~65) winsize 62
2966 22:52:49.724089 [CA 3] Center 34 (4~64) winsize 61
2967 22:52:49.727417 [CA 4] Center 32 (1~63) winsize 63
2968 22:52:49.730727 [CA 5] Center 32 (2~63) winsize 62
2969 22:52:49.730826
2970 22:52:49.734101 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2971 22:52:49.734201
2972 22:52:49.737637 [CATrainingPosCal] consider 1 rank data
2973 22:52:49.740790 u2DelayCellTimex100 = 270/100 ps
2974 22:52:49.743955 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2975 22:52:49.747458 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2976 22:52:49.754524 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2977 22:52:49.757816 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
2978 22:52:49.760937 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2979 22:52:49.764426 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2980 22:52:49.764499
2981 22:52:49.768172 CA PerBit enable=1, Macro0, CA PI delay=32
2982 22:52:49.768276
2983 22:52:49.770996 [CBTSetCACLKResult] CA Dly = 32
2984 22:52:49.771067 CS Dly: 5 (0~36)
2985 22:52:49.771126 ==
2986 22:52:49.774257 Dram Type= 6, Freq= 0, CH_1, rank 1
2987 22:52:49.780909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2988 22:52:49.781008 ==
2989 22:52:49.784238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2990 22:52:49.790719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2991 22:52:49.799849 [CA 0] Center 37 (7~68) winsize 62
2992 22:52:49.802857 [CA 1] Center 37 (7~68) winsize 62
2993 22:52:49.805959 [CA 2] Center 34 (3~65) winsize 63
2994 22:52:49.809549 [CA 3] Center 33 (3~64) winsize 62
2995 22:52:49.812585 [CA 4] Center 32 (2~63) winsize 62
2996 22:52:49.816670 [CA 5] Center 32 (1~63) winsize 63
2997 22:52:49.816738
2998 22:52:49.819487 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2999 22:52:49.819559
3000 22:52:49.822662 [CATrainingPosCal] consider 2 rank data
3001 22:52:49.825884 u2DelayCellTimex100 = 270/100 ps
3002 22:52:49.829532 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
3003 22:52:49.835918 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3004 22:52:49.839325 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
3005 22:52:49.842685 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
3006 22:52:49.845967 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3007 22:52:49.849173 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3008 22:52:49.849253
3009 22:52:49.852612 CA PerBit enable=1, Macro0, CA PI delay=32
3010 22:52:49.852692
3011 22:52:49.855815 [CBTSetCACLKResult] CA Dly = 32
3012 22:52:49.855895 CS Dly: 6 (0~38)
3013 22:52:49.855960
3014 22:52:49.859190 ----->DramcWriteLeveling(PI) begin...
3015 22:52:49.862645 ==
3016 22:52:49.866130 Dram Type= 6, Freq= 0, CH_1, rank 0
3017 22:52:49.869380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3018 22:52:49.869460 ==
3019 22:52:49.872517 Write leveling (Byte 0): 21 => 21
3020 22:52:49.875923 Write leveling (Byte 1): 21 => 21
3021 22:52:49.879591 DramcWriteLeveling(PI) end<-----
3022 22:52:49.879671
3023 22:52:49.879733 ==
3024 22:52:49.882914 Dram Type= 6, Freq= 0, CH_1, rank 0
3025 22:52:49.885911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3026 22:52:49.885991 ==
3027 22:52:49.889049 [Gating] SW mode calibration
3028 22:52:49.895730 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3029 22:52:49.902331 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3030 22:52:49.905674 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3031 22:52:49.908944 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3032 22:52:49.915525 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3033 22:52:49.919065 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3034 22:52:49.922227 0 11 16 | B1->B0 | 3030 2525 | 1 0 | (1 0) (0 0)
3035 22:52:49.925618 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3036 22:52:49.932410 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3037 22:52:49.935553 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3038 22:52:49.939060 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3039 22:52:49.945695 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3040 22:52:49.948977 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3041 22:52:49.952303 0 12 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3042 22:52:49.959024 0 12 16 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
3043 22:52:49.962487 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3044 22:52:49.965883 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3045 22:52:49.972492 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3046 22:52:49.975665 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3047 22:52:49.979529 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3048 22:52:49.986212 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3049 22:52:49.989206 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3050 22:52:49.992857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3051 22:52:49.999294 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3052 22:52:50.002544 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 22:52:50.005850 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 22:52:50.012430 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 22:52:50.015471 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 22:52:50.019015 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 22:52:50.022161 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 22:52:50.028888 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 22:52:50.032333 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 22:52:50.035673 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3061 22:52:50.042225 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3062 22:52:50.045829 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 22:52:50.049187 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3064 22:52:50.055881 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3065 22:52:50.058903 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3066 22:52:50.062445 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3067 22:52:50.069074 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3068 22:52:50.069173 Total UI for P1: 0, mck2ui 16
3069 22:52:50.075742 best dqsien dly found for B0: ( 0, 15, 16)
3070 22:52:50.079192 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3071 22:52:50.082190 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3072 22:52:50.085532 Total UI for P1: 0, mck2ui 16
3073 22:52:50.088944 best dqsien dly found for B1: ( 0, 15, 22)
3074 22:52:50.092405 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3075 22:52:50.095908 best DQS1 dly(MCK, UI, PI) = (0, 15, 22)
3076 22:52:50.096003
3077 22:52:50.102419 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3078 22:52:50.105723 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22)
3079 22:52:50.105795 [Gating] SW calibration Done
3080 22:52:50.109384 ==
3081 22:52:50.112377 Dram Type= 6, Freq= 0, CH_1, rank 0
3082 22:52:50.115841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3083 22:52:50.115917 ==
3084 22:52:50.116037 RX Vref Scan: 0
3085 22:52:50.116108
3086 22:52:50.118916 RX Vref 0 -> 0, step: 1
3087 22:52:50.118987
3088 22:52:50.122739 RX Delay -40 -> 252, step: 8
3089 22:52:50.125641 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3090 22:52:50.129027 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3091 22:52:50.132524 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3092 22:52:50.138994 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3093 22:52:50.142463 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3094 22:52:50.145824 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3095 22:52:50.148808 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3096 22:52:50.152522 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3097 22:52:50.158992 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3098 22:52:50.162347 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3099 22:52:50.165648 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3100 22:52:50.168899 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3101 22:52:50.172255 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3102 22:52:50.179531 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3103 22:52:50.182220 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3104 22:52:50.185647 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3105 22:52:50.185715 ==
3106 22:52:50.189169 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 22:52:50.192196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3108 22:52:50.192291 ==
3109 22:52:50.195809 DQS Delay:
3110 22:52:50.195883 DQS0 = 0, DQS1 = 0
3111 22:52:50.198934 DQM Delay:
3112 22:52:50.199002 DQM0 = 116, DQM1 = 108
3113 22:52:50.199060 DQ Delay:
3114 22:52:50.202302 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3115 22:52:50.209210 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3116 22:52:50.212369 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =103
3117 22:52:50.215749 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3118 22:52:50.215818
3119 22:52:50.215875
3120 22:52:50.215931 ==
3121 22:52:50.219266 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 22:52:50.222230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3123 22:52:50.222297 ==
3124 22:52:50.222355
3125 22:52:50.222411
3126 22:52:50.225575 TX Vref Scan disable
3127 22:52:50.225667 == TX Byte 0 ==
3128 22:52:50.232365 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3129 22:52:50.235576 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3130 22:52:50.235677 == TX Byte 1 ==
3131 22:52:50.242251 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3132 22:52:50.245523 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3133 22:52:50.245593 ==
3134 22:52:50.248950 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 22:52:50.252311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3136 22:52:50.252413 ==
3137 22:52:50.265073 TX Vref=22, minBit 5, minWin=25, winSum=417
3138 22:52:50.268500 TX Vref=24, minBit 0, minWin=26, winSum=421
3139 22:52:50.271827 TX Vref=26, minBit 3, minWin=25, winSum=423
3140 22:52:50.274979 TX Vref=28, minBit 9, minWin=25, winSum=431
3141 22:52:50.278233 TX Vref=30, minBit 9, minWin=26, winSum=432
3142 22:52:50.281774 TX Vref=32, minBit 1, minWin=26, winSum=430
3143 22:52:50.288591 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3144 22:52:50.288688
3145 22:52:50.291791 Final TX Range 1 Vref 30
3146 22:52:50.291860
3147 22:52:50.291918 ==
3148 22:52:50.295088 Dram Type= 6, Freq= 0, CH_1, rank 0
3149 22:52:50.298434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3150 22:52:50.298534 ==
3151 22:52:50.298622
3152 22:52:50.302003
3153 22:52:50.302096 TX Vref Scan disable
3154 22:52:50.305250 == TX Byte 0 ==
3155 22:52:50.308691 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3156 22:52:50.311677 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3157 22:52:50.315049 == TX Byte 1 ==
3158 22:52:50.318221 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3159 22:52:50.321654 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3160 22:52:50.321724
3161 22:52:50.324794 [DATLAT]
3162 22:52:50.324861 Freq=1200, CH1 RK0
3163 22:52:50.324918
3164 22:52:50.328143 DATLAT Default: 0xd
3165 22:52:50.328243 0, 0xFFFF, sum = 0
3166 22:52:50.331712 1, 0xFFFF, sum = 0
3167 22:52:50.331822 2, 0xFFFF, sum = 0
3168 22:52:50.334900 3, 0xFFFF, sum = 0
3169 22:52:50.334973 4, 0xFFFF, sum = 0
3170 22:52:50.338200 5, 0xFFFF, sum = 0
3171 22:52:50.338272 6, 0xFFFF, sum = 0
3172 22:52:50.341989 7, 0xFFFF, sum = 0
3173 22:52:50.342105 8, 0xFFFF, sum = 0
3174 22:52:50.345018 9, 0xFFFF, sum = 0
3175 22:52:50.348128 10, 0xFFFF, sum = 0
3176 22:52:50.348228 11, 0x0, sum = 1
3177 22:52:50.348320 12, 0x0, sum = 2
3178 22:52:50.351651 13, 0x0, sum = 3
3179 22:52:50.351719 14, 0x0, sum = 4
3180 22:52:50.355015 best_step = 12
3181 22:52:50.355086
3182 22:52:50.355145 ==
3183 22:52:50.358454 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 22:52:50.361746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3185 22:52:50.361845 ==
3186 22:52:50.364764 RX Vref Scan: 1
3187 22:52:50.364834
3188 22:52:50.364893 Set Vref Range= 32 -> 127
3189 22:52:50.368272
3190 22:52:50.368365 RX Vref 32 -> 127, step: 1
3191 22:52:50.368452
3192 22:52:50.371597 RX Delay -29 -> 252, step: 4
3193 22:52:50.371668
3194 22:52:50.374748 Set Vref, RX VrefLevel [Byte0]: 32
3195 22:52:50.378625 [Byte1]: 32
3196 22:52:50.381466
3197 22:52:50.381532 Set Vref, RX VrefLevel [Byte0]: 33
3198 22:52:50.384581 [Byte1]: 33
3199 22:52:50.389321
3200 22:52:50.389392 Set Vref, RX VrefLevel [Byte0]: 34
3201 22:52:50.392593 [Byte1]: 34
3202 22:52:50.397201
3203 22:52:50.397270 Set Vref, RX VrefLevel [Byte0]: 35
3204 22:52:50.400508 [Byte1]: 35
3205 22:52:50.405169
3206 22:52:50.405242 Set Vref, RX VrefLevel [Byte0]: 36
3207 22:52:50.408510 [Byte1]: 36
3208 22:52:50.413335
3209 22:52:50.413403 Set Vref, RX VrefLevel [Byte0]: 37
3210 22:52:50.416345 [Byte1]: 37
3211 22:52:50.421282
3212 22:52:50.421375 Set Vref, RX VrefLevel [Byte0]: 38
3213 22:52:50.424751 [Byte1]: 38
3214 22:52:50.429273
3215 22:52:50.429349 Set Vref, RX VrefLevel [Byte0]: 39
3216 22:52:50.432441 [Byte1]: 39
3217 22:52:50.437175
3218 22:52:50.437246 Set Vref, RX VrefLevel [Byte0]: 40
3219 22:52:50.440754 [Byte1]: 40
3220 22:52:50.445025
3221 22:52:50.445103 Set Vref, RX VrefLevel [Byte0]: 41
3222 22:52:50.448264 [Byte1]: 41
3223 22:52:50.453576
3224 22:52:50.453656 Set Vref, RX VrefLevel [Byte0]: 42
3225 22:52:50.456707 [Byte1]: 42
3226 22:52:50.460853
3227 22:52:50.460932 Set Vref, RX VrefLevel [Byte0]: 43
3228 22:52:50.464481 [Byte1]: 43
3229 22:52:50.469160
3230 22:52:50.469263 Set Vref, RX VrefLevel [Byte0]: 44
3231 22:52:50.472181 [Byte1]: 44
3232 22:52:50.476820
3233 22:52:50.476890 Set Vref, RX VrefLevel [Byte0]: 45
3234 22:52:50.480202 [Byte1]: 45
3235 22:52:50.484715
3236 22:52:50.484811 Set Vref, RX VrefLevel [Byte0]: 46
3237 22:52:50.488170 [Byte1]: 46
3238 22:52:50.492572
3239 22:52:50.492645 Set Vref, RX VrefLevel [Byte0]: 47
3240 22:52:50.496072 [Byte1]: 47
3241 22:52:50.500694
3242 22:52:50.500790 Set Vref, RX VrefLevel [Byte0]: 48
3243 22:52:50.504471 [Byte1]: 48
3244 22:52:50.508859
3245 22:52:50.508938 Set Vref, RX VrefLevel [Byte0]: 49
3246 22:52:50.512094 [Byte1]: 49
3247 22:52:50.516693
3248 22:52:50.516773 Set Vref, RX VrefLevel [Byte0]: 50
3249 22:52:50.519946 [Byte1]: 50
3250 22:52:50.524580
3251 22:52:50.524659 Set Vref, RX VrefLevel [Byte0]: 51
3252 22:52:50.527839 [Byte1]: 51
3253 22:52:50.532706
3254 22:52:50.532786 Set Vref, RX VrefLevel [Byte0]: 52
3255 22:52:50.536044 [Byte1]: 52
3256 22:52:50.540395
3257 22:52:50.540474 Set Vref, RX VrefLevel [Byte0]: 53
3258 22:52:50.543897 [Byte1]: 53
3259 22:52:50.548506
3260 22:52:50.548586 Set Vref, RX VrefLevel [Byte0]: 54
3261 22:52:50.551933 [Byte1]: 54
3262 22:52:50.556428
3263 22:52:50.556508 Set Vref, RX VrefLevel [Byte0]: 55
3264 22:52:50.559997 [Byte1]: 55
3265 22:52:50.564373
3266 22:52:50.564453 Set Vref, RX VrefLevel [Byte0]: 56
3267 22:52:50.568172 [Byte1]: 56
3268 22:52:50.572316
3269 22:52:50.572396 Set Vref, RX VrefLevel [Byte0]: 57
3270 22:52:50.575712 [Byte1]: 57
3271 22:52:50.580683
3272 22:52:50.580762 Set Vref, RX VrefLevel [Byte0]: 58
3273 22:52:50.583501 [Byte1]: 58
3274 22:52:50.588494
3275 22:52:50.588573 Set Vref, RX VrefLevel [Byte0]: 59
3276 22:52:50.591827 [Byte1]: 59
3277 22:52:50.596312
3278 22:52:50.596386 Set Vref, RX VrefLevel [Byte0]: 60
3279 22:52:50.599670 [Byte1]: 60
3280 22:52:50.604083
3281 22:52:50.604152 Set Vref, RX VrefLevel [Byte0]: 61
3282 22:52:50.607659 [Byte1]: 61
3283 22:52:50.611949
3284 22:52:50.615232 Set Vref, RX VrefLevel [Byte0]: 62
3285 22:52:50.615310 [Byte1]: 62
3286 22:52:50.620193
3287 22:52:50.620265 Set Vref, RX VrefLevel [Byte0]: 63
3288 22:52:50.623435 [Byte1]: 63
3289 22:52:50.627933
3290 22:52:50.628014 Set Vref, RX VrefLevel [Byte0]: 64
3291 22:52:50.631413 [Byte1]: 64
3292 22:52:50.635858
3293 22:52:50.635938 Set Vref, RX VrefLevel [Byte0]: 65
3294 22:52:50.639133 [Byte1]: 65
3295 22:52:50.644052
3296 22:52:50.644131 Final RX Vref Byte 0 = 52 to rank0
3297 22:52:50.647495 Final RX Vref Byte 1 = 48 to rank0
3298 22:52:50.650539 Final RX Vref Byte 0 = 52 to rank1
3299 22:52:50.653836 Final RX Vref Byte 1 = 48 to rank1==
3300 22:52:50.657195 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 22:52:50.664063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3302 22:52:50.664144 ==
3303 22:52:50.664207 DQS Delay:
3304 22:52:50.664265 DQS0 = 0, DQS1 = 0
3305 22:52:50.667250 DQM Delay:
3306 22:52:50.667329 DQM0 = 115, DQM1 = 105
3307 22:52:50.670602 DQ Delay:
3308 22:52:50.673816 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3309 22:52:50.677193 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3310 22:52:50.680494 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3311 22:52:50.683693 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =112
3312 22:52:50.683769
3313 22:52:50.683831
3314 22:52:50.690524 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3315 22:52:50.693679 CH1 RK0: MR19=404, MR18=1B1B
3316 22:52:50.700315 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3317 22:52:50.700390
3318 22:52:50.703618 ----->DramcWriteLeveling(PI) begin...
3319 22:52:50.703715 ==
3320 22:52:50.706960 Dram Type= 6, Freq= 0, CH_1, rank 1
3321 22:52:50.710315 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3322 22:52:50.714232 ==
3323 22:52:50.714305 Write leveling (Byte 0): 23 => 23
3324 22:52:50.717012 Write leveling (Byte 1): 21 => 21
3325 22:52:50.720316 DramcWriteLeveling(PI) end<-----
3326 22:52:50.720412
3327 22:52:50.720502 ==
3328 22:52:50.723902 Dram Type= 6, Freq= 0, CH_1, rank 1
3329 22:52:50.730485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3330 22:52:50.730565 ==
3331 22:52:50.730631 [Gating] SW mode calibration
3332 22:52:50.740609 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3333 22:52:50.743584 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3334 22:52:50.747019 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3335 22:52:50.754163 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3336 22:52:50.756980 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3337 22:52:50.760288 0 11 12 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
3338 22:52:50.767050 0 11 16 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
3339 22:52:50.770593 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3340 22:52:50.773705 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3341 22:52:50.780572 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3342 22:52:50.783812 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3343 22:52:50.786941 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3344 22:52:50.793872 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3345 22:52:50.796987 0 12 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
3346 22:52:50.800315 0 12 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3347 22:52:50.807241 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 22:52:50.810413 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3349 22:52:50.813771 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3350 22:52:50.820660 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3351 22:52:50.823736 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3352 22:52:50.827116 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3353 22:52:50.833711 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3354 22:52:50.836991 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3355 22:52:50.840319 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 22:52:50.846589 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 22:52:50.849946 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 22:52:50.853336 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 22:52:50.859925 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 22:52:50.863377 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 22:52:50.866641 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 22:52:50.870343 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 22:52:50.876769 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 22:52:50.880018 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 22:52:50.883443 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 22:52:50.890282 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3367 22:52:50.893340 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 22:52:50.896907 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3369 22:52:50.903329 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3370 22:52:50.906802 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3371 22:52:50.909929 Total UI for P1: 0, mck2ui 16
3372 22:52:50.913149 best dqsien dly found for B0: ( 0, 15, 12)
3373 22:52:50.916556 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3374 22:52:50.923294 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3375 22:52:50.923369 Total UI for P1: 0, mck2ui 16
3376 22:52:50.929819 best dqsien dly found for B1: ( 0, 15, 16)
3377 22:52:50.933255 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3378 22:52:50.936434 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3379 22:52:50.936533
3380 22:52:50.939885 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3381 22:52:50.943228 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3382 22:52:50.946773 [Gating] SW calibration Done
3383 22:52:50.946844 ==
3384 22:52:50.949983 Dram Type= 6, Freq= 0, CH_1, rank 1
3385 22:52:50.953227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3386 22:52:50.953322 ==
3387 22:52:50.956570 RX Vref Scan: 0
3388 22:52:50.956644
3389 22:52:50.956705 RX Vref 0 -> 0, step: 1
3390 22:52:50.956761
3391 22:52:50.959852 RX Delay -40 -> 252, step: 8
3392 22:52:50.966699 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3393 22:52:50.969663 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3394 22:52:50.973162 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3395 22:52:50.976741 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3396 22:52:50.979716 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3397 22:52:50.983291 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3398 22:52:50.989695 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3399 22:52:50.992882 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3400 22:52:50.996302 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3401 22:52:50.999930 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3402 22:52:51.003194 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3403 22:52:51.010030 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3404 22:52:51.013202 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3405 22:52:51.016525 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3406 22:52:51.019767 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3407 22:52:51.023042 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3408 22:52:51.026370 ==
3409 22:52:51.029741 Dram Type= 6, Freq= 0, CH_1, rank 1
3410 22:52:51.033027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3411 22:52:51.033130 ==
3412 22:52:51.033198 DQS Delay:
3413 22:52:51.036623 DQS0 = 0, DQS1 = 0
3414 22:52:51.036718 DQM Delay:
3415 22:52:51.039741 DQM0 = 116, DQM1 = 105
3416 22:52:51.039840 DQ Delay:
3417 22:52:51.042941 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3418 22:52:51.046688 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3419 22:52:51.049686 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3420 22:52:51.053366 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3421 22:52:51.053437
3422 22:52:51.053497
3423 22:52:51.053553 ==
3424 22:52:51.056715 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 22:52:51.059891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3426 22:52:51.062989 ==
3427 22:52:51.063086
3428 22:52:51.063172
3429 22:52:51.063246 TX Vref Scan disable
3430 22:52:51.066607 == TX Byte 0 ==
3431 22:52:51.070404 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3432 22:52:51.073329 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3433 22:52:51.076473 == TX Byte 1 ==
3434 22:52:51.079824 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3435 22:52:51.083233 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3436 22:52:51.086757 ==
3437 22:52:51.086825 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 22:52:51.092979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3439 22:52:51.093047 ==
3440 22:52:51.104083 TX Vref=22, minBit 7, minWin=25, winSum=418
3441 22:52:51.107415 TX Vref=24, minBit 9, minWin=25, winSum=427
3442 22:52:51.111019 TX Vref=26, minBit 2, minWin=26, winSum=427
3443 22:52:51.114072 TX Vref=28, minBit 3, minWin=26, winSum=433
3444 22:52:51.117272 TX Vref=30, minBit 9, minWin=26, winSum=437
3445 22:52:51.120678 TX Vref=32, minBit 0, minWin=26, winSum=430
3446 22:52:51.127218 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3447 22:52:51.127313
3448 22:52:51.130791 Final TX Range 1 Vref 30
3449 22:52:51.130868
3450 22:52:51.130929 ==
3451 22:52:51.133937 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 22:52:51.137350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3453 22:52:51.137420 ==
3454 22:52:51.137479
3455 22:52:51.141102
3456 22:52:51.141169 TX Vref Scan disable
3457 22:52:51.144239 == TX Byte 0 ==
3458 22:52:51.147273 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3459 22:52:51.150733 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3460 22:52:51.154280 == TX Byte 1 ==
3461 22:52:51.157519 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3462 22:52:51.160985 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3463 22:52:51.161053
3464 22:52:51.164059 [DATLAT]
3465 22:52:51.164153 Freq=1200, CH1 RK1
3466 22:52:51.164236
3467 22:52:51.167342 DATLAT Default: 0xc
3468 22:52:51.167410 0, 0xFFFF, sum = 0
3469 22:52:51.170812 1, 0xFFFF, sum = 0
3470 22:52:51.170893 2, 0xFFFF, sum = 0
3471 22:52:51.174048 3, 0xFFFF, sum = 0
3472 22:52:51.174132 4, 0xFFFF, sum = 0
3473 22:52:51.177252 5, 0xFFFF, sum = 0
3474 22:52:51.177349 6, 0xFFFF, sum = 0
3475 22:52:51.180548 7, 0xFFFF, sum = 0
3476 22:52:51.180642 8, 0xFFFF, sum = 0
3477 22:52:51.183978 9, 0xFFFF, sum = 0
3478 22:52:51.187337 10, 0xFFFF, sum = 0
3479 22:52:51.187410 11, 0x0, sum = 1
3480 22:52:51.187470 12, 0x0, sum = 2
3481 22:52:51.190837 13, 0x0, sum = 3
3482 22:52:51.190903 14, 0x0, sum = 4
3483 22:52:51.194210 best_step = 12
3484 22:52:51.194279
3485 22:52:51.194335 ==
3486 22:52:51.197286 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 22:52:51.201014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3488 22:52:51.201094 ==
3489 22:52:51.203998 RX Vref Scan: 0
3490 22:52:51.204077
3491 22:52:51.204139 RX Vref 0 -> 0, step: 1
3492 22:52:51.204197
3493 22:52:51.207150 RX Delay -29 -> 252, step: 4
3494 22:52:51.214329 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3495 22:52:51.217623 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3496 22:52:51.220856 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3497 22:52:51.224236 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3498 22:52:51.227414 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3499 22:52:51.234221 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3500 22:52:51.237593 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3501 22:52:51.240991 iDelay=199, Bit 7, Center 110 (39 ~ 182) 144
3502 22:52:51.244162 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3503 22:52:51.247710 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3504 22:52:51.254218 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3505 22:52:51.257451 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3506 22:52:51.260690 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3507 22:52:51.264167 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3508 22:52:51.267623 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3509 22:52:51.274354 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3510 22:52:51.274426 ==
3511 22:52:51.277349 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 22:52:51.280796 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3513 22:52:51.280866 ==
3514 22:52:51.280931 DQS Delay:
3515 22:52:51.284142 DQS0 = 0, DQS1 = 0
3516 22:52:51.284212 DQM Delay:
3517 22:52:51.287598 DQM0 = 114, DQM1 = 103
3518 22:52:51.287665 DQ Delay:
3519 22:52:51.290822 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3520 22:52:51.293987 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3521 22:52:51.297443 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3522 22:52:51.300795 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3523 22:52:51.300889
3524 22:52:51.300978
3525 22:52:51.310848 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
3526 22:52:51.314345 CH1 RK1: MR19=404, MR18=E0E
3527 22:52:51.317473 CH1_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3528 22:52:51.320837 [RxdqsGatingPostProcess] freq 1200
3529 22:52:51.327482 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3530 22:52:51.330896 Pre-setting of DQS Precalculation
3531 22:52:51.334738 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3532 22:52:51.344441 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3533 22:52:51.351088 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3534 22:52:51.351161
3535 22:52:51.351221
3536 22:52:51.354223 [Calibration Summary] 2400 Mbps
3537 22:52:51.354290 CH 0, Rank 0
3538 22:52:51.357479 SW Impedance : PASS
3539 22:52:51.357547 DUTY Scan : NO K
3540 22:52:51.360990 ZQ Calibration : PASS
3541 22:52:51.364500 Jitter Meter : NO K
3542 22:52:51.364575 CBT Training : PASS
3543 22:52:51.367628 Write leveling : PASS
3544 22:52:51.367696 RX DQS gating : PASS
3545 22:52:51.371269 RX DQ/DQS(RDDQC) : PASS
3546 22:52:51.374373 TX DQ/DQS : PASS
3547 22:52:51.374446 RX DATLAT : PASS
3548 22:52:51.377976 RX DQ/DQS(Engine): PASS
3549 22:52:51.381082 TX OE : NO K
3550 22:52:51.381151 All Pass.
3551 22:52:51.381210
3552 22:52:51.381269 CH 0, Rank 1
3553 22:52:51.384228 SW Impedance : PASS
3554 22:52:51.387443 DUTY Scan : NO K
3555 22:52:51.387542 ZQ Calibration : PASS
3556 22:52:51.390937 Jitter Meter : NO K
3557 22:52:51.394254 CBT Training : PASS
3558 22:52:51.394326 Write leveling : PASS
3559 22:52:51.397593 RX DQS gating : PASS
3560 22:52:51.400793 RX DQ/DQS(RDDQC) : PASS
3561 22:52:51.400874 TX DQ/DQS : PASS
3562 22:52:51.404365 RX DATLAT : PASS
3563 22:52:51.407907 RX DQ/DQS(Engine): PASS
3564 22:52:51.407986 TX OE : NO K
3565 22:52:51.408049 All Pass.
3566 22:52:51.410889
3567 22:52:51.410967 CH 1, Rank 0
3568 22:52:51.414166 SW Impedance : PASS
3569 22:52:51.414244 DUTY Scan : NO K
3570 22:52:51.417556 ZQ Calibration : PASS
3571 22:52:51.417635 Jitter Meter : NO K
3572 22:52:51.421095 CBT Training : PASS
3573 22:52:51.424475 Write leveling : PASS
3574 22:52:51.424554 RX DQS gating : PASS
3575 22:52:51.427625 RX DQ/DQS(RDDQC) : PASS
3576 22:52:51.430981 TX DQ/DQS : PASS
3577 22:52:51.431062 RX DATLAT : PASS
3578 22:52:51.434176 RX DQ/DQS(Engine): PASS
3579 22:52:51.437705 TX OE : NO K
3580 22:52:51.437776 All Pass.
3581 22:52:51.437852
3582 22:52:51.437938 CH 1, Rank 1
3583 22:52:51.441241 SW Impedance : PASS
3584 22:52:51.444319 DUTY Scan : NO K
3585 22:52:51.444414 ZQ Calibration : PASS
3586 22:52:51.447700 Jitter Meter : NO K
3587 22:52:51.450949 CBT Training : PASS
3588 22:52:51.451018 Write leveling : PASS
3589 22:52:51.454343 RX DQS gating : PASS
3590 22:52:51.454410 RX DQ/DQS(RDDQC) : PASS
3591 22:52:51.457921 TX DQ/DQS : PASS
3592 22:52:51.460996 RX DATLAT : PASS
3593 22:52:51.461062 RX DQ/DQS(Engine): PASS
3594 22:52:51.464502 TX OE : NO K
3595 22:52:51.464590 All Pass.
3596 22:52:51.464649
3597 22:52:51.467782 DramC Write-DBI off
3598 22:52:51.470958 PER_BANK_REFRESH: Hybrid Mode
3599 22:52:51.471051 TX_TRACKING: ON
3600 22:52:51.481032 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3601 22:52:51.484524 [FAST_K] Save calibration result to emmc
3602 22:52:51.487691 dramc_set_vcore_voltage set vcore to 650000
3603 22:52:51.490941 Read voltage for 600, 5
3604 22:52:51.491011 Vio18 = 0
3605 22:52:51.491071 Vcore = 650000
3606 22:52:51.494554 Vdram = 0
3607 22:52:51.494620 Vddq = 0
3608 22:52:51.494681 Vmddr = 0
3609 22:52:51.501189 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3610 22:52:51.504093 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3611 22:52:51.507695 MEM_TYPE=3, freq_sel=19
3612 22:52:51.510695 sv_algorithm_assistance_LP4_1600
3613 22:52:51.514141 ============ PULL DRAM RESETB DOWN ============
3614 22:52:51.517512 ========== PULL DRAM RESETB DOWN end =========
3615 22:52:51.524827 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3616 22:52:51.527596 ===================================
3617 22:52:51.530952 LPDDR4 DRAM CONFIGURATION
3618 22:52:51.534159 ===================================
3619 22:52:51.534234 EX_ROW_EN[0] = 0x0
3620 22:52:51.537511 EX_ROW_EN[1] = 0x0
3621 22:52:51.537619 LP4Y_EN = 0x0
3622 22:52:51.540870 WORK_FSP = 0x0
3623 22:52:51.540966 WL = 0x2
3624 22:52:51.544121 RL = 0x2
3625 22:52:51.544216 BL = 0x2
3626 22:52:51.547359 RPST = 0x0
3627 22:52:51.547426 RD_PRE = 0x0
3628 22:52:51.550492 WR_PRE = 0x1
3629 22:52:51.550559 WR_PST = 0x0
3630 22:52:51.554257 DBI_WR = 0x0
3631 22:52:51.557565 DBI_RD = 0x0
3632 22:52:51.557660 OTF = 0x1
3633 22:52:51.560576 ===================================
3634 22:52:51.563733 ===================================
3635 22:52:51.563827 ANA top config
3636 22:52:51.567124 ===================================
3637 22:52:51.570692 DLL_ASYNC_EN = 0
3638 22:52:51.573740 ALL_SLAVE_EN = 1
3639 22:52:51.577173 NEW_RANK_MODE = 1
3640 22:52:51.580662 DLL_IDLE_MODE = 1
3641 22:52:51.580738 LP45_APHY_COMB_EN = 1
3642 22:52:51.583734 TX_ODT_DIS = 1
3643 22:52:51.587081 NEW_8X_MODE = 1
3644 22:52:51.590487 ===================================
3645 22:52:51.593883 ===================================
3646 22:52:51.597130 data_rate = 1200
3647 22:52:51.600553 CKR = 1
3648 22:52:51.600621 DQ_P2S_RATIO = 8
3649 22:52:51.603442 ===================================
3650 22:52:51.606785 CA_P2S_RATIO = 8
3651 22:52:51.610087 DQ_CA_OPEN = 0
3652 22:52:51.613482 DQ_SEMI_OPEN = 0
3653 22:52:51.616792 CA_SEMI_OPEN = 0
3654 22:52:51.620421 CA_FULL_RATE = 0
3655 22:52:51.620489 DQ_CKDIV4_EN = 1
3656 22:52:51.623532 CA_CKDIV4_EN = 1
3657 22:52:51.626890 CA_PREDIV_EN = 0
3658 22:52:51.630014 PH8_DLY = 0
3659 22:52:51.633199 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3660 22:52:51.636992 DQ_AAMCK_DIV = 4
3661 22:52:51.637063 CA_AAMCK_DIV = 4
3662 22:52:51.640311 CA_ADMCK_DIV = 4
3663 22:52:51.643306 DQ_TRACK_CA_EN = 0
3664 22:52:51.646710 CA_PICK = 600
3665 22:52:51.649963 CA_MCKIO = 600
3666 22:52:51.653360 MCKIO_SEMI = 0
3667 22:52:51.656758 PLL_FREQ = 2288
3668 22:52:51.656852 DQ_UI_PI_RATIO = 32
3669 22:52:51.660168 CA_UI_PI_RATIO = 0
3670 22:52:51.663470 ===================================
3671 22:52:51.666789 ===================================
3672 22:52:51.670041 memory_type:LPDDR4
3673 22:52:51.673283 GP_NUM : 10
3674 22:52:51.673355 SRAM_EN : 1
3675 22:52:51.676872 MD32_EN : 0
3676 22:52:51.679918 ===================================
3677 22:52:51.683074 [ANA_INIT] >>>>>>>>>>>>>>
3678 22:52:51.683143 <<<<<< [CONFIGURE PHASE]: ANA_TX
3679 22:52:51.686621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3680 22:52:51.689893 ===================================
3681 22:52:51.693199 data_rate = 1200,PCW = 0X5800
3682 22:52:51.696420 ===================================
3683 22:52:51.699814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3684 22:52:51.706549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3685 22:52:51.713243 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3686 22:52:51.716234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3687 22:52:51.719635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3688 22:52:51.723204 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3689 22:52:51.726143 [ANA_INIT] flow start
3690 22:52:51.726213 [ANA_INIT] PLL >>>>>>>>
3691 22:52:51.729544 [ANA_INIT] PLL <<<<<<<<
3692 22:52:51.733072 [ANA_INIT] MIDPI >>>>>>>>
3693 22:52:51.733172 [ANA_INIT] MIDPI <<<<<<<<
3694 22:52:51.736100 [ANA_INIT] DLL >>>>>>>>
3695 22:52:51.739453 [ANA_INIT] flow end
3696 22:52:51.742846 ============ LP4 DIFF to SE enter ============
3697 22:52:51.745955 ============ LP4 DIFF to SE exit ============
3698 22:52:51.749588 [ANA_INIT] <<<<<<<<<<<<<
3699 22:52:51.752693 [Flow] Enable top DCM control >>>>>
3700 22:52:51.755988 [Flow] Enable top DCM control <<<<<
3701 22:52:51.759278 Enable DLL master slave shuffle
3702 22:52:51.762709 ==============================================================
3703 22:52:51.765953 Gating Mode config
3704 22:52:51.772567 ==============================================================
3705 22:52:51.772638 Config description:
3706 22:52:51.782717 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3707 22:52:51.789364 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3708 22:52:51.795851 SELPH_MODE 0: By rank 1: By Phase
3709 22:52:51.799227 ==============================================================
3710 22:52:51.802216 GAT_TRACK_EN = 1
3711 22:52:51.805481 RX_GATING_MODE = 2
3712 22:52:51.808955 RX_GATING_TRACK_MODE = 2
3713 22:52:51.812572 SELPH_MODE = 1
3714 22:52:51.815401 PICG_EARLY_EN = 1
3715 22:52:51.818966 VALID_LAT_VALUE = 1
3716 22:52:51.822339 ==============================================================
3717 22:52:51.825617 Enter into Gating configuration >>>>
3718 22:52:51.829087 Exit from Gating configuration <<<<
3719 22:52:51.832236 Enter into DVFS_PRE_config >>>>>
3720 22:52:51.845371 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3721 22:52:51.848452 Exit from DVFS_PRE_config <<<<<
3722 22:52:51.851886 Enter into PICG configuration >>>>
3723 22:52:51.855199 Exit from PICG configuration <<<<
3724 22:52:51.855279 [RX_INPUT] configuration >>>>>
3725 22:52:51.858341 [RX_INPUT] configuration <<<<<
3726 22:52:51.865103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3727 22:52:51.868467 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3728 22:52:51.874926 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3729 22:52:51.881760 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3730 22:52:51.888062 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3731 22:52:51.895063 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3732 22:52:51.898403 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3733 22:52:51.901571 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3734 22:52:51.908001 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3735 22:52:51.911577 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3736 22:52:51.914940 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3737 22:52:51.918032 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3738 22:52:51.921596 ===================================
3739 22:52:51.924859 LPDDR4 DRAM CONFIGURATION
3740 22:52:51.928119 ===================================
3741 22:52:51.931353 EX_ROW_EN[0] = 0x0
3742 22:52:51.931450 EX_ROW_EN[1] = 0x0
3743 22:52:51.934683 LP4Y_EN = 0x0
3744 22:52:51.934762 WORK_FSP = 0x0
3745 22:52:51.937998 WL = 0x2
3746 22:52:51.938134 RL = 0x2
3747 22:52:51.941204 BL = 0x2
3748 22:52:51.941309 RPST = 0x0
3749 22:52:51.944478 RD_PRE = 0x0
3750 22:52:51.947867 WR_PRE = 0x1
3751 22:52:51.947946 WR_PST = 0x0
3752 22:52:51.950990 DBI_WR = 0x0
3753 22:52:51.951095 DBI_RD = 0x0
3754 22:52:51.954453 OTF = 0x1
3755 22:52:51.957904 ===================================
3756 22:52:51.961284 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3757 22:52:51.964447 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3758 22:52:51.967569 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3759 22:52:51.970959 ===================================
3760 22:52:51.974229 LPDDR4 DRAM CONFIGURATION
3761 22:52:51.977858 ===================================
3762 22:52:51.981039 EX_ROW_EN[0] = 0x10
3763 22:52:51.981118 EX_ROW_EN[1] = 0x0
3764 22:52:51.984147 LP4Y_EN = 0x0
3765 22:52:51.984227 WORK_FSP = 0x0
3766 22:52:51.987567 WL = 0x2
3767 22:52:51.987646 RL = 0x2
3768 22:52:51.990799 BL = 0x2
3769 22:52:51.990877 RPST = 0x0
3770 22:52:51.994161 RD_PRE = 0x0
3771 22:52:51.994239 WR_PRE = 0x1
3772 22:52:51.998220 WR_PST = 0x0
3773 22:52:52.000868 DBI_WR = 0x0
3774 22:52:52.000957 DBI_RD = 0x0
3775 22:52:52.004209 OTF = 0x1
3776 22:52:52.007473 ===================================
3777 22:52:52.010508 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3778 22:52:52.016014 nWR fixed to 30
3779 22:52:52.019298 [ModeRegInit_LP4] CH0 RK0
3780 22:52:52.019403 [ModeRegInit_LP4] CH0 RK1
3781 22:52:52.022713 [ModeRegInit_LP4] CH1 RK0
3782 22:52:52.026146 [ModeRegInit_LP4] CH1 RK1
3783 22:52:52.026237 match AC timing 16
3784 22:52:52.032522 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3785 22:52:52.035923 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3786 22:52:52.039227 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3787 22:52:52.045699 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3788 22:52:52.049177 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3789 22:52:52.049278 ==
3790 22:52:52.052577 Dram Type= 6, Freq= 0, CH_0, rank 0
3791 22:52:52.055535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3792 22:52:52.055628 ==
3793 22:52:52.062165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3794 22:52:52.068592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3795 22:52:52.072077 [CA 0] Center 35 (5~66) winsize 62
3796 22:52:52.075257 [CA 1] Center 35 (5~66) winsize 62
3797 22:52:52.078605 [CA 2] Center 34 (4~65) winsize 62
3798 22:52:52.082016 [CA 3] Center 34 (3~65) winsize 63
3799 22:52:52.085405 [CA 4] Center 33 (3~64) winsize 62
3800 22:52:52.088497 [CA 5] Center 33 (3~64) winsize 62
3801 22:52:52.088568
3802 22:52:52.092025 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3803 22:52:52.092116
3804 22:52:52.095143 [CATrainingPosCal] consider 1 rank data
3805 22:52:52.098558 u2DelayCellTimex100 = 270/100 ps
3806 22:52:52.101954 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3807 22:52:52.105018 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3808 22:52:52.109020 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3809 22:52:52.111828 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3810 22:52:52.118640 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3811 22:52:52.121741 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3812 22:52:52.121821
3813 22:52:52.125082 CA PerBit enable=1, Macro0, CA PI delay=33
3814 22:52:52.125163
3815 22:52:52.128589 [CBTSetCACLKResult] CA Dly = 33
3816 22:52:52.128668 CS Dly: 4 (0~35)
3817 22:52:52.128731 ==
3818 22:52:52.131441 Dram Type= 6, Freq= 0, CH_0, rank 1
3819 22:52:52.138237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3820 22:52:52.138342 ==
3821 22:52:52.141235 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3822 22:52:52.148008 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3823 22:52:52.151441 [CA 0] Center 35 (5~66) winsize 62
3824 22:52:52.154900 [CA 1] Center 35 (5~66) winsize 62
3825 22:52:52.157972 [CA 2] Center 34 (4~65) winsize 62
3826 22:52:52.161216 [CA 3] Center 34 (3~65) winsize 63
3827 22:52:52.164511 [CA 4] Center 33 (3~64) winsize 62
3828 22:52:52.167834 [CA 5] Center 33 (3~64) winsize 62
3829 22:52:52.167936
3830 22:52:52.170976 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3831 22:52:52.171076
3832 22:52:52.174450 [CATrainingPosCal] consider 2 rank data
3833 22:52:52.178048 u2DelayCellTimex100 = 270/100 ps
3834 22:52:52.181362 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3835 22:52:52.187590 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3836 22:52:52.191045 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3837 22:52:52.194236 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3838 22:52:52.197925 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3839 22:52:52.201130 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3840 22:52:52.201224
3841 22:52:52.204352 CA PerBit enable=1, Macro0, CA PI delay=33
3842 22:52:52.204448
3843 22:52:52.207452 [CBTSetCACLKResult] CA Dly = 33
3844 22:52:52.207548 CS Dly: 4 (0~36)
3845 22:52:52.211283
3846 22:52:52.214393 ----->DramcWriteLeveling(PI) begin...
3847 22:52:52.214464 ==
3848 22:52:52.217631 Dram Type= 6, Freq= 0, CH_0, rank 0
3849 22:52:52.220713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3850 22:52:52.220805 ==
3851 22:52:52.224141 Write leveling (Byte 0): 31 => 31
3852 22:52:52.227231 Write leveling (Byte 1): 28 => 28
3853 22:52:52.230740 DramcWriteLeveling(PI) end<-----
3854 22:52:52.230849
3855 22:52:52.230951 ==
3856 22:52:52.233954 Dram Type= 6, Freq= 0, CH_0, rank 0
3857 22:52:52.237169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3858 22:52:52.237267 ==
3859 22:52:52.240752 [Gating] SW mode calibration
3860 22:52:52.247403 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3861 22:52:52.253591 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3862 22:52:52.257048 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3863 22:52:52.260293 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3864 22:52:52.267198 0 5 8 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 0)
3865 22:52:52.270407 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3866 22:52:52.273532 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3867 22:52:52.280222 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3868 22:52:52.283717 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3869 22:52:52.286702 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3870 22:52:52.293352 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3871 22:52:52.296782 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3872 22:52:52.300210 0 6 8 | B1->B0 | 2c2c 3131 | 1 0 | (0 0) (0 0)
3873 22:52:52.306939 0 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3874 22:52:52.310211 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3875 22:52:52.313449 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3876 22:52:52.319977 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3877 22:52:52.323420 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3878 22:52:52.326559 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3879 22:52:52.333456 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3880 22:52:52.336629 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3881 22:52:52.339662 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 22:52:52.346341 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 22:52:52.349875 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 22:52:52.352711 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 22:52:52.359723 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 22:52:52.362896 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 22:52:52.366167 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 22:52:52.372918 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 22:52:52.376354 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 22:52:52.379586 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 22:52:52.386259 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 22:52:52.389651 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 22:52:52.392542 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 22:52:52.399120 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 22:52:52.402564 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3896 22:52:52.405912 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3897 22:52:52.412413 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3898 22:52:52.412490 Total UI for P1: 0, mck2ui 16
3899 22:52:52.416015 best dqsien dly found for B0: ( 0, 9, 8)
3900 22:52:52.419186 Total UI for P1: 0, mck2ui 16
3901 22:52:52.422306 best dqsien dly found for B1: ( 0, 9, 8)
3902 22:52:52.425940 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3903 22:52:52.432169 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3904 22:52:52.432271
3905 22:52:52.435760 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3906 22:52:52.438829 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3907 22:52:52.442310 [Gating] SW calibration Done
3908 22:52:52.442405 ==
3909 22:52:52.445283 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 22:52:52.448762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3911 22:52:52.448855 ==
3912 22:52:52.452052 RX Vref Scan: 0
3913 22:52:52.452122
3914 22:52:52.452212 RX Vref 0 -> 0, step: 1
3915 22:52:52.452297
3916 22:52:52.455498 RX Delay -230 -> 252, step: 16
3917 22:52:52.458665 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3918 22:52:52.465283 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3919 22:52:52.468632 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3920 22:52:52.471839 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3921 22:52:52.475301 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3922 22:52:52.481886 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3923 22:52:52.485049 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3924 22:52:52.488763 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3925 22:52:52.491718 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3926 22:52:52.494849 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3927 22:52:52.501480 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3928 22:52:52.504904 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3929 22:52:52.508037 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3930 22:52:52.511631 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3931 22:52:52.518234 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3932 22:52:52.521316 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3933 22:52:52.521382 ==
3934 22:52:52.524626 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 22:52:52.527856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3936 22:52:52.527921 ==
3937 22:52:52.531066 DQS Delay:
3938 22:52:52.531177 DQS0 = 0, DQS1 = 0
3939 22:52:52.534541 DQM Delay:
3940 22:52:52.534612 DQM0 = 39, DQM1 = 33
3941 22:52:52.534671 DQ Delay:
3942 22:52:52.537959 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
3943 22:52:52.541417 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3944 22:52:52.545305 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3945 22:52:52.548356 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3946 22:52:52.548447
3947 22:52:52.548535
3948 22:52:52.551044 ==
3949 22:52:52.551113 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 22:52:52.557794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3951 22:52:52.557888 ==
3952 22:52:52.557974
3953 22:52:52.558106
3954 22:52:52.561115 TX Vref Scan disable
3955 22:52:52.561207 == TX Byte 0 ==
3956 22:52:52.564138 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3957 22:52:52.572413 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3958 22:52:52.572485 == TX Byte 1 ==
3959 22:52:52.577395 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
3960 22:52:52.581041 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
3961 22:52:52.581117 ==
3962 22:52:52.584357 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 22:52:52.587371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3964 22:52:52.587469 ==
3965 22:52:52.587560
3966 22:52:52.587644
3967 22:52:52.590612 TX Vref Scan disable
3968 22:52:52.594152 == TX Byte 0 ==
3969 22:52:52.597314 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3970 22:52:52.600470 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3971 22:52:52.603721 == TX Byte 1 ==
3972 22:52:52.607279 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
3973 22:52:52.610435 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
3974 22:52:52.610505
3975 22:52:52.613674 [DATLAT]
3976 22:52:52.613740 Freq=600, CH0 RK0
3977 22:52:52.613798
3978 22:52:52.616967 DATLAT Default: 0x9
3979 22:52:52.617031 0, 0xFFFF, sum = 0
3980 22:52:52.620326 1, 0xFFFF, sum = 0
3981 22:52:52.620398 2, 0xFFFF, sum = 0
3982 22:52:52.623556 3, 0xFFFF, sum = 0
3983 22:52:52.623621 4, 0xFFFF, sum = 0
3984 22:52:52.627361 5, 0xFFFF, sum = 0
3985 22:52:52.627426 6, 0xFFFF, sum = 0
3986 22:52:52.630147 7, 0x0, sum = 1
3987 22:52:52.630248 8, 0x0, sum = 2
3988 22:52:52.633430 9, 0x0, sum = 3
3989 22:52:57.458427 10, 0x0, sum = 4
3990 22:52:57.459338 best_step = 8
3991 22:52:57.459719
3992 22:52:57.460061 ==
3993 22:52:57.460363 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 22:52:57.460436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3995 22:52:57.460506 ==
3996 22:52:57.460559 RX Vref Scan: 1
3997 22:52:57.460614
3998 22:52:57.460667 RX Vref 0 -> 0, step: 1
3999 22:52:57.460720
4000 22:52:57.460772 RX Delay -195 -> 252, step: 8
4001 22:52:57.460824
4002 22:52:57.460876 Set Vref, RX VrefLevel [Byte0]: 47
4003 22:52:57.460929 [Byte1]: 49
4004 22:52:57.460982
4005 22:52:57.461033 Final RX Vref Byte 0 = 47 to rank0
4006 22:52:57.461085 Final RX Vref Byte 1 = 49 to rank0
4007 22:52:57.461137 Final RX Vref Byte 0 = 47 to rank1
4008 22:52:57.461189 Final RX Vref Byte 1 = 49 to rank1==
4009 22:52:57.461241 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 22:52:57.461293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4011 22:52:57.461344 ==
4012 22:52:57.461396 DQS Delay:
4013 22:52:57.461447 DQS0 = 0, DQS1 = 0
4014 22:52:57.461498 DQM Delay:
4015 22:52:57.461550 DQM0 = 40, DQM1 = 30
4016 22:52:57.461602 DQ Delay:
4017 22:52:57.461654 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
4018 22:52:57.461705 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4019 22:52:57.461757 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4020 22:52:57.461808 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4021 22:52:57.461859
4022 22:52:57.461909
4023 22:52:57.461960 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4024 22:52:57.462013 CH0 RK0: MR19=808, MR18=5454
4025 22:52:57.462107 CH0_RK0: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
4026 22:52:57.462160
4027 22:52:57.462211 ----->DramcWriteLeveling(PI) begin...
4028 22:52:57.462264 ==
4029 22:52:57.462316 Dram Type= 6, Freq= 0, CH_0, rank 1
4030 22:52:57.462367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4031 22:52:57.462419 ==
4032 22:52:57.462470 Write leveling (Byte 0): 29 => 29
4033 22:52:57.462522 Write leveling (Byte 1): 29 => 29
4034 22:52:57.462573 DramcWriteLeveling(PI) end<-----
4035 22:52:57.462624
4036 22:52:57.462675 ==
4037 22:52:57.462726 Dram Type= 6, Freq= 0, CH_0, rank 1
4038 22:52:57.462778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4039 22:52:57.462829 ==
4040 22:52:57.462880 [Gating] SW mode calibration
4041 22:52:57.462932 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4042 22:52:57.462983 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4043 22:52:57.463034 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 22:52:57.463086 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4045 22:52:57.463138 0 5 8 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
4046 22:52:57.463189 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4047 22:52:57.463253 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 22:52:57.463303 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 22:52:57.463353 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 22:52:57.463403 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 22:52:57.463453 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 22:52:57.463503 0 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4053 22:52:57.463553 0 6 8 | B1->B0 | 2e2e 3131 | 0 0 | (1 1) (0 0)
4054 22:52:57.463603 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4055 22:52:57.463653 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 22:52:57.463703 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 22:52:57.463754 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 22:52:57.463804 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 22:52:57.463855 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 22:52:57.463904 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4061 22:52:57.463955 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4062 22:52:57.464005 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 22:52:57.464056 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 22:52:57.464106 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 22:52:57.464156 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 22:52:57.464207 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 22:52:57.464258 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 22:52:57.464308 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 22:52:57.464359 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 22:52:57.464409 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 22:52:57.464459 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 22:52:57.464510 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 22:52:57.464560 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 22:52:57.464610 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 22:52:57.464661 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 22:52:57.464711 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4077 22:52:57.464761 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4078 22:52:57.464812 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 22:52:57.464863 Total UI for P1: 0, mck2ui 16
4080 22:52:57.464914 best dqsien dly found for B0: ( 0, 9, 8)
4081 22:52:57.464964 Total UI for P1: 0, mck2ui 16
4082 22:52:57.465015 best dqsien dly found for B1: ( 0, 9, 6)
4083 22:52:57.465066 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4084 22:52:57.465116 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4085 22:52:57.465166
4086 22:52:57.465216 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4087 22:52:57.465267 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4088 22:52:57.465317 [Gating] SW calibration Done
4089 22:52:57.465367 ==
4090 22:52:57.465417 Dram Type= 6, Freq= 0, CH_0, rank 1
4091 22:52:57.465468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4092 22:52:57.465519 ==
4093 22:52:57.465570 RX Vref Scan: 0
4094 22:52:57.465620
4095 22:52:57.465671 RX Vref 0 -> 0, step: 1
4096 22:52:57.465722
4097 22:52:57.465772 RX Delay -230 -> 252, step: 16
4098 22:52:57.465822 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4099 22:52:57.465873 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4100 22:52:57.465924 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4101 22:52:57.465974 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4102 22:52:57.466030 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4103 22:52:57.466115 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4104 22:52:57.466390 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4105 22:52:57.466498 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4106 22:52:57.466551 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4107 22:52:57.466604 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4108 22:52:57.466656 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4109 22:52:57.466708 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4110 22:52:57.466759 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4111 22:52:57.466811 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4112 22:52:57.466863 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4113 22:52:57.466915 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4114 22:52:57.466967 ==
4115 22:52:57.467019 Dram Type= 6, Freq= 0, CH_0, rank 1
4116 22:52:57.467070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4117 22:52:57.467122 ==
4118 22:52:57.467173 DQS Delay:
4119 22:52:57.467224 DQS0 = 0, DQS1 = 0
4120 22:52:57.467275 DQM Delay:
4121 22:52:57.467326 DQM0 = 45, DQM1 = 34
4122 22:52:57.467378 DQ Delay:
4123 22:52:57.467429 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =41
4124 22:52:57.467481 DQ4 =57, DQ5 =33, DQ6 =57, DQ7 =57
4125 22:52:57.467533 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4126 22:52:57.467584 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4127 22:52:57.467635
4128 22:52:57.467686
4129 22:52:57.467737 ==
4130 22:52:57.467789 Dram Type= 6, Freq= 0, CH_0, rank 1
4131 22:52:57.467841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4132 22:52:57.467893 ==
4133 22:52:57.467944
4134 22:52:57.467996
4135 22:52:57.468047 TX Vref Scan disable
4136 22:52:57.468098 == TX Byte 0 ==
4137 22:52:57.468150 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4138 22:52:57.468203 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4139 22:52:57.468255 == TX Byte 1 ==
4140 22:52:57.468306 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4141 22:52:57.468357 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4142 22:52:57.468422 ==
4143 22:52:57.468472 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 22:52:57.468522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4145 22:52:57.468573 ==
4146 22:52:57.468623
4147 22:52:57.468691
4148 22:52:57.468756 TX Vref Scan disable
4149 22:52:57.468807 == TX Byte 0 ==
4150 22:52:57.468858 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4151 22:52:57.468909 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4152 22:52:57.468960 == TX Byte 1 ==
4153 22:52:57.469010 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4154 22:52:57.469061 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4155 22:52:57.469112
4156 22:52:57.469163 [DATLAT]
4157 22:52:57.469213 Freq=600, CH0 RK1
4158 22:52:57.469264
4159 22:52:57.469315 DATLAT Default: 0x8
4160 22:52:57.469366 0, 0xFFFF, sum = 0
4161 22:52:57.469418 1, 0xFFFF, sum = 0
4162 22:52:57.469469 2, 0xFFFF, sum = 0
4163 22:52:57.469521 3, 0xFFFF, sum = 0
4164 22:52:57.469588 4, 0xFFFF, sum = 0
4165 22:52:57.469641 5, 0xFFFF, sum = 0
4166 22:52:57.469706 6, 0xFFFF, sum = 0
4167 22:52:57.469758 7, 0x0, sum = 1
4168 22:52:57.469809 8, 0x0, sum = 2
4169 22:52:57.469861 9, 0x0, sum = 3
4170 22:52:57.469913 10, 0x0, sum = 4
4171 22:52:57.469964 best_step = 8
4172 22:52:57.470015
4173 22:52:57.470122 ==
4174 22:52:57.470174 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 22:52:57.470226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4176 22:52:57.470293 ==
4177 22:52:57.470345 RX Vref Scan: 0
4178 22:52:57.470408
4179 22:52:57.470458 RX Vref 0 -> 0, step: 1
4180 22:52:57.470509
4181 22:52:57.470560 RX Delay -195 -> 252, step: 8
4182 22:52:57.470610 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4183 22:52:57.470661 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4184 22:52:57.470711 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4185 22:52:57.470762 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4186 22:52:57.470813 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4187 22:52:57.470864 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4188 22:52:57.470915 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4189 22:52:57.470965 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4190 22:52:57.471016 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4191 22:52:57.471067 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4192 22:52:57.471118 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4193 22:52:57.471168 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4194 22:52:57.471219 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4195 22:52:57.471270 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4196 22:52:57.471321 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4197 22:52:57.471372 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4198 22:52:57.471423 ==
4199 22:52:57.471473 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 22:52:57.471524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4201 22:52:57.471575 ==
4202 22:52:57.471626 DQS Delay:
4203 22:52:57.471676 DQS0 = 0, DQS1 = 0
4204 22:52:57.471727 DQM Delay:
4205 22:52:57.471778 DQM0 = 41, DQM1 = 32
4206 22:52:57.471828 DQ Delay:
4207 22:52:57.471879 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4208 22:52:57.471930 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4209 22:52:57.471981 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =20
4210 22:52:57.472031 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4211 22:52:57.472082
4212 22:52:57.472132
4213 22:52:57.472182 [DQSOSCAuto] RK1, (LSB)MR18= 0x6262, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4214 22:52:57.472234 CH0 RK1: MR19=808, MR18=6262
4215 22:52:57.472301 CH0_RK1: MR19=0x808, MR18=0x6262, DQSOSC=391, MR23=63, INC=171, DEC=114
4216 22:52:57.472353 [RxdqsGatingPostProcess] freq 600
4217 22:52:57.472406 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4218 22:52:57.472471 Pre-setting of DQS Precalculation
4219 22:52:57.472523 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4220 22:52:57.472573 ==
4221 22:52:57.472624 Dram Type= 6, Freq= 0, CH_1, rank 0
4222 22:52:57.472675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4223 22:52:57.472726 ==
4224 22:52:57.472777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4225 22:52:57.472828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4226 22:52:57.472880 [CA 0] Center 35 (5~66) winsize 62
4227 22:52:57.472959 [CA 1] Center 35 (5~66) winsize 62
4228 22:52:57.473011 [CA 2] Center 33 (3~64) winsize 62
4229 22:52:57.473062 [CA 3] Center 33 (3~64) winsize 62
4230 22:52:57.473112 [CA 4] Center 33 (2~64) winsize 63
4231 22:52:57.473163 [CA 5] Center 33 (2~64) winsize 63
4232 22:52:57.473214
4233 22:52:57.473264 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4234 22:52:57.473315
4235 22:52:57.473366 [CATrainingPosCal] consider 1 rank data
4236 22:52:57.473417 u2DelayCellTimex100 = 270/100 ps
4237 22:52:57.473468 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4238 22:52:57.473520 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4239 22:52:57.473571 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4240 22:52:57.473809 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4241 22:52:57.473885 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4242 22:52:57.473938 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4243 22:52:57.473990
4244 22:52:57.474069 CA PerBit enable=1, Macro0, CA PI delay=33
4245 22:52:57.474136
4246 22:52:57.474187 [CBTSetCACLKResult] CA Dly = 33
4247 22:52:57.474240 CS Dly: 3 (0~34)
4248 22:52:57.474292 ==
4249 22:52:57.474343 Dram Type= 6, Freq= 0, CH_1, rank 1
4250 22:52:57.474407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4251 22:52:57.474459 ==
4252 22:52:57.474510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4253 22:52:57.474561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4254 22:52:57.474626 [CA 0] Center 35 (4~66) winsize 63
4255 22:52:57.474678 [CA 1] Center 34 (4~65) winsize 62
4256 22:52:57.474742 [CA 2] Center 33 (3~64) winsize 62
4257 22:52:57.474793 [CA 3] Center 33 (3~64) winsize 62
4258 22:52:57.474844 [CA 4] Center 32 (2~63) winsize 62
4259 22:52:57.474895 [CA 5] Center 32 (2~63) winsize 62
4260 22:52:57.474945
4261 22:52:57.474996 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4262 22:52:57.475047
4263 22:52:57.475097 [CATrainingPosCal] consider 2 rank data
4264 22:52:57.475148 u2DelayCellTimex100 = 270/100 ps
4265 22:52:57.475199 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4266 22:52:57.475250 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4267 22:52:57.475301 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4268 22:52:57.475352 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4269 22:52:57.475418 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4270 22:52:57.475483 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4271 22:52:57.475533
4272 22:52:57.475583 CA PerBit enable=1, Macro0, CA PI delay=32
4273 22:52:57.475634
4274 22:52:57.475685 [CBTSetCACLKResult] CA Dly = 32
4275 22:52:57.475736 CS Dly: 4 (0~36)
4276 22:52:57.475787
4277 22:52:57.475838 ----->DramcWriteLeveling(PI) begin...
4278 22:52:57.475889 ==
4279 22:52:57.475940 Dram Type= 6, Freq= 0, CH_1, rank 0
4280 22:52:57.475991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4281 22:52:57.476043 ==
4282 22:52:57.476094 Write leveling (Byte 0): 28 => 28
4283 22:52:57.476145 Write leveling (Byte 1): 28 => 28
4284 22:52:57.476195 DramcWriteLeveling(PI) end<-----
4285 22:52:57.476246
4286 22:52:57.476297 ==
4287 22:52:57.476348 Dram Type= 6, Freq= 0, CH_1, rank 0
4288 22:52:57.476398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4289 22:52:57.476449 ==
4290 22:52:57.476500 [Gating] SW mode calibration
4291 22:52:57.476551 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4292 22:52:57.476603 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4293 22:52:57.476654 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4294 22:52:57.476706 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4295 22:52:57.476801 0 5 8 | B1->B0 | 2f2f 2828 | 1 0 | (1 1) (1 0)
4296 22:52:57.476882 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4297 22:52:57.476955 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4298 22:52:57.477023 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4299 22:52:57.477087 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4300 22:52:57.477138 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4301 22:52:57.477189 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4302 22:52:57.477240 0 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4303 22:52:57.477291 0 6 8 | B1->B0 | 3636 4141 | 0 0 | (0 0) (0 0)
4304 22:52:57.477342 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 22:52:57.477393 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 22:52:57.477444 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4307 22:52:57.477495 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4308 22:52:57.477546 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4309 22:52:57.477596 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 22:52:57.477647 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4311 22:52:57.477697 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4312 22:52:57.477748 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 22:52:57.477798 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 22:52:57.477849 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 22:52:57.477900 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 22:52:57.477950 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 22:52:57.478001 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 22:52:57.478095 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 22:52:57.478174 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 22:52:57.478224 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 22:52:57.478275 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 22:52:57.478326 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 22:52:57.478377 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 22:52:57.478428 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 22:52:57.478479 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4326 22:52:57.478530 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4327 22:52:57.478581 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4328 22:52:57.478632 Total UI for P1: 0, mck2ui 16
4329 22:52:57.478684 best dqsien dly found for B0: ( 0, 9, 4)
4330 22:52:57.478735 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4331 22:52:57.478786 Total UI for P1: 0, mck2ui 16
4332 22:52:57.478837 best dqsien dly found for B1: ( 0, 9, 8)
4333 22:52:57.478888 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4334 22:52:57.478939 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4335 22:52:57.478990
4336 22:52:57.479040 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4337 22:52:57.479091 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4338 22:52:57.479142 [Gating] SW calibration Done
4339 22:52:57.479193 ==
4340 22:52:57.479244 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 22:52:57.479295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4342 22:52:57.479346 ==
4343 22:52:57.479397 RX Vref Scan: 0
4344 22:52:57.479447
4345 22:52:57.479497 RX Vref 0 -> 0, step: 1
4346 22:52:57.479548
4347 22:52:57.479627 RX Delay -230 -> 252, step: 16
4348 22:52:57.479677 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4349 22:52:57.479729 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4350 22:52:57.479967 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4351 22:52:57.480075 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4352 22:52:57.480128 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4353 22:52:57.480179 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4354 22:52:57.480231 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4355 22:52:57.480283 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4356 22:52:57.480334 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4357 22:52:57.480385 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4358 22:52:57.480437 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4359 22:52:57.480501 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4360 22:52:57.480552 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4361 22:52:57.480602 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4362 22:52:57.480652 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4363 22:52:57.480702 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4364 22:52:57.480753 ==
4365 22:52:57.480803 Dram Type= 6, Freq= 0, CH_1, rank 0
4366 22:52:57.480854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4367 22:52:57.480904 ==
4368 22:52:57.480955 DQS Delay:
4369 22:52:57.481005 DQS0 = 0, DQS1 = 0
4370 22:52:57.481055 DQM Delay:
4371 22:52:57.481106 DQM0 = 38, DQM1 = 34
4372 22:52:57.481155 DQ Delay:
4373 22:52:57.481205 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4374 22:52:57.481256 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4375 22:52:57.481306 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4376 22:52:57.481356 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4377 22:52:57.481406
4378 22:52:57.481456
4379 22:52:57.481506 ==
4380 22:52:57.481555 Dram Type= 6, Freq= 0, CH_1, rank 0
4381 22:52:57.481605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4382 22:52:57.481656 ==
4383 22:52:57.481705
4384 22:52:57.481755
4385 22:52:57.481804 TX Vref Scan disable
4386 22:52:57.481855 == TX Byte 0 ==
4387 22:52:57.481905 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4388 22:52:57.481957 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4389 22:52:57.482007 == TX Byte 1 ==
4390 22:52:57.482088 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4391 22:52:57.482152 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4392 22:52:57.482203 ==
4393 22:52:57.482253 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 22:52:57.482303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4395 22:52:57.482354 ==
4396 22:52:57.482404
4397 22:52:57.482454
4398 22:52:57.482504 TX Vref Scan disable
4399 22:52:57.482554 == TX Byte 0 ==
4400 22:52:57.482605 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4401 22:52:57.482655 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4402 22:52:57.482706 == TX Byte 1 ==
4403 22:52:57.482758 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4404 22:52:57.482809 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4405 22:52:57.482860
4406 22:52:57.482910 [DATLAT]
4407 22:52:57.482960 Freq=600, CH1 RK0
4408 22:52:57.483040
4409 22:52:57.483090 DATLAT Default: 0x9
4410 22:52:57.483140 0, 0xFFFF, sum = 0
4411 22:52:57.483191 1, 0xFFFF, sum = 0
4412 22:52:57.483243 2, 0xFFFF, sum = 0
4413 22:52:57.483294 3, 0xFFFF, sum = 0
4414 22:52:57.483345 4, 0xFFFF, sum = 0
4415 22:52:57.483396 5, 0xFFFF, sum = 0
4416 22:52:57.483447 6, 0xFFFF, sum = 0
4417 22:52:57.483498 7, 0x0, sum = 1
4418 22:52:57.483549 8, 0x0, sum = 2
4419 22:52:57.483599 9, 0x0, sum = 3
4420 22:52:57.483650 10, 0x0, sum = 4
4421 22:52:57.483701 best_step = 8
4422 22:52:57.483751
4423 22:52:57.483801 ==
4424 22:52:57.483851 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 22:52:57.483902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4426 22:52:57.483952 ==
4427 22:52:57.484002 RX Vref Scan: 1
4428 22:52:57.484052
4429 22:52:57.484103 RX Vref 0 -> 0, step: 1
4430 22:52:57.484153
4431 22:52:57.484203 RX Delay -195 -> 252, step: 8
4432 22:52:57.484253
4433 22:52:57.484303 Set Vref, RX VrefLevel [Byte0]: 52
4434 22:52:57.484354 [Byte1]: 48
4435 22:52:57.484404
4436 22:52:57.484454 Final RX Vref Byte 0 = 52 to rank0
4437 22:52:57.484505 Final RX Vref Byte 1 = 48 to rank0
4438 22:52:57.484556 Final RX Vref Byte 0 = 52 to rank1
4439 22:52:57.484606 Final RX Vref Byte 1 = 48 to rank1==
4440 22:52:57.484657 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 22:52:57.484707 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4442 22:52:57.484764 ==
4443 22:52:57.484826 DQS Delay:
4444 22:52:57.484886 DQS0 = 0, DQS1 = 0
4445 22:52:57.484944 DQM Delay:
4446 22:52:57.484995 DQM0 = 37, DQM1 = 30
4447 22:52:57.485046 DQ Delay:
4448 22:52:57.485101 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4449 22:52:57.485152 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4450 22:52:57.485203 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4451 22:52:57.485253 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4452 22:52:57.485308
4453 22:52:57.485359
4454 22:52:57.485409 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7e, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4455 22:52:57.485463 CH1 RK0: MR19=808, MR18=7E7E
4456 22:52:57.485515 CH1_RK0: MR19=0x808, MR18=0x7E7E, DQSOSC=386, MR23=63, INC=176, DEC=117
4457 22:52:57.485566
4458 22:52:57.485616 ----->DramcWriteLeveling(PI) begin...
4459 22:52:57.485668 ==
4460 22:52:57.485719 Dram Type= 6, Freq= 0, CH_1, rank 1
4461 22:52:57.485769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4462 22:52:57.485820 ==
4463 22:52:57.485870 Write leveling (Byte 0): 28 => 28
4464 22:52:57.485921 Write leveling (Byte 1): 28 => 28
4465 22:52:57.485972 DramcWriteLeveling(PI) end<-----
4466 22:52:57.486026
4467 22:52:57.486115 ==
4468 22:52:57.486196 Dram Type= 6, Freq= 0, CH_1, rank 1
4469 22:52:57.486247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4470 22:52:57.486297 ==
4471 22:52:57.486347 [Gating] SW mode calibration
4472 22:52:57.486397 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4473 22:52:57.486448 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4474 22:52:57.486499 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 22:52:57.486550 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4476 22:52:57.486601 0 5 8 | B1->B0 | 3232 2727 | 1 0 | (1 0) (1 1)
4477 22:52:57.486651 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 22:52:57.486717 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 22:52:57.486768 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 22:52:57.486831 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 22:52:57.486882 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 22:52:57.486931 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 22:52:57.486982 0 6 4 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
4484 22:52:57.487032 0 6 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4485 22:52:57.487083 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 22:52:57.487134 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 22:52:57.487373 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 22:52:57.487447 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 22:52:57.487500 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 22:52:57.487551 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 22:52:57.487603 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4492 22:52:57.487655 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4493 22:52:57.487706 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 22:52:57.487758 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 22:52:57.487809 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 22:52:57.487872 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 22:52:57.487922 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 22:52:57.487972 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 22:52:57.488022 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 22:52:57.488072 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 22:52:57.488122 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 22:52:57.488172 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 22:52:57.488222 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 22:52:57.488273 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 22:52:57.488323 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 22:52:57.488374 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 22:52:57.488424 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4508 22:52:57.488474 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 22:52:57.488524 Total UI for P1: 0, mck2ui 16
4510 22:52:57.488575 best dqsien dly found for B0: ( 0, 9, 4)
4511 22:52:57.488626 Total UI for P1: 0, mck2ui 16
4512 22:52:57.488705 best dqsien dly found for B1: ( 0, 9, 6)
4513 22:52:57.488756 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4514 22:52:57.488806 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4515 22:52:57.488856
4516 22:52:57.488907 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4517 22:52:57.488957 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4518 22:52:57.489008 [Gating] SW calibration Done
4519 22:52:57.489058 ==
4520 22:52:57.489108 Dram Type= 6, Freq= 0, CH_1, rank 1
4521 22:52:57.489159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4522 22:52:57.489210 ==
4523 22:52:57.489260 RX Vref Scan: 0
4524 22:52:57.489324
4525 22:52:57.489388 RX Vref 0 -> 0, step: 1
4526 22:52:57.489438
4527 22:52:57.489488 RX Delay -230 -> 252, step: 16
4528 22:52:57.489538 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4529 22:52:57.489604 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4530 22:52:57.489676 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4531 22:52:57.489726 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4532 22:52:57.489776 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4533 22:52:57.489826 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4534 22:52:57.489876 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4535 22:52:57.489926 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4536 22:52:57.489976 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4537 22:52:57.490032 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4538 22:52:57.490112 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4539 22:52:57.490163 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4540 22:52:57.490212 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4541 22:52:57.490263 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4542 22:52:57.490313 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4543 22:52:57.490363 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4544 22:52:57.490414 ==
4545 22:52:57.490464 Dram Type= 6, Freq= 0, CH_1, rank 1
4546 22:52:57.490515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4547 22:52:57.490565 ==
4548 22:52:57.490616 DQS Delay:
4549 22:52:57.490666 DQS0 = 0, DQS1 = 0
4550 22:52:57.490732 DQM Delay:
4551 22:52:57.490783 DQM0 = 42, DQM1 = 35
4552 22:52:57.490882 DQ Delay:
4553 22:52:57.490932 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4554 22:52:57.490982 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4555 22:52:57.491032 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4556 22:52:57.491082 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4557 22:52:57.491132
4558 22:52:57.491182
4559 22:52:57.491232 ==
4560 22:52:57.491282 Dram Type= 6, Freq= 0, CH_1, rank 1
4561 22:52:57.491333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4562 22:52:57.491383 ==
4563 22:52:57.491434
4564 22:52:57.491483
4565 22:52:57.491533 TX Vref Scan disable
4566 22:52:57.491582 == TX Byte 0 ==
4567 22:52:57.491633 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4568 22:52:57.491684 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4569 22:52:57.491734 == TX Byte 1 ==
4570 22:52:57.491784 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 22:52:57.491834 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 22:52:57.491884 ==
4573 22:52:57.491934 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 22:52:57.491985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4575 22:52:57.492035 ==
4576 22:52:57.492086
4577 22:52:57.492135
4578 22:52:57.492184 TX Vref Scan disable
4579 22:52:57.492234 == TX Byte 0 ==
4580 22:52:57.492285 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4581 22:52:57.492335 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4582 22:52:57.492386 == TX Byte 1 ==
4583 22:52:57.492436 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4584 22:52:57.492486 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4585 22:52:57.492536
4586 22:52:57.492585 [DATLAT]
4587 22:52:57.492635 Freq=600, CH1 RK1
4588 22:52:57.492685
4589 22:52:57.492735 DATLAT Default: 0x8
4590 22:52:57.492785 0, 0xFFFF, sum = 0
4591 22:52:57.492852 1, 0xFFFF, sum = 0
4592 22:52:57.492917 2, 0xFFFF, sum = 0
4593 22:52:57.492967 3, 0xFFFF, sum = 0
4594 22:52:57.493019 4, 0xFFFF, sum = 0
4595 22:52:57.493070 5, 0xFFFF, sum = 0
4596 22:52:57.493120 6, 0xFFFF, sum = 0
4597 22:52:57.493171 7, 0x0, sum = 1
4598 22:52:57.493222 8, 0x0, sum = 2
4599 22:52:57.493272 9, 0x0, sum = 3
4600 22:52:57.493323 10, 0x0, sum = 4
4601 22:52:57.493373 best_step = 8
4602 22:52:57.493423
4603 22:52:57.493473 ==
4604 22:52:57.493522 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 22:52:57.493574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4606 22:52:57.493624 ==
4607 22:52:57.493674 RX Vref Scan: 0
4608 22:52:57.493724
4609 22:52:57.493775 RX Vref 0 -> 0, step: 1
4610 22:52:57.493825
4611 22:52:57.493874 RX Delay -195 -> 252, step: 8
4612 22:52:57.493925 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4613 22:52:57.493975 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4614 22:52:57.494029 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4615 22:52:57.494116 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4616 22:52:57.494166 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4617 22:52:57.494405 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4618 22:52:57.494462 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4619 22:52:57.494513 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4620 22:52:57.494564 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4621 22:52:57.494615 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4622 22:52:57.494665 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4623 22:52:57.494716 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4624 22:52:57.494767 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4625 22:52:57.494858 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4626 22:52:57.494935 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4627 22:52:57.494986 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4628 22:52:57.495037 ==
4629 22:52:57.495088 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 22:52:57.495139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4631 22:52:57.495189 ==
4632 22:52:57.495240 DQS Delay:
4633 22:52:57.495289 DQS0 = 0, DQS1 = 0
4634 22:52:57.495340 DQM Delay:
4635 22:52:57.495390 DQM0 = 37, DQM1 = 30
4636 22:52:57.495440 DQ Delay:
4637 22:52:57.495490 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4638 22:52:57.495541 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4639 22:52:57.495591 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4640 22:52:57.495642 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4641 22:52:57.495692
4642 22:52:57.495742
4643 22:52:57.495793 [DQSOSCAuto] RK1, (LSB)MR18= 0x5959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4644 22:52:57.495844 CH1 RK1: MR19=808, MR18=5959
4645 22:52:57.495895 CH1_RK1: MR19=0x808, MR18=0x5959, DQSOSC=393, MR23=63, INC=169, DEC=113
4646 22:52:57.495946 [RxdqsGatingPostProcess] freq 600
4647 22:52:57.495997 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4648 22:52:57.496048 Pre-setting of DQS Precalculation
4649 22:52:57.496098 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4650 22:52:57.496178 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4651 22:52:57.496229 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4652 22:52:57.496279
4653 22:52:57.496329
4654 22:52:57.496379 [Calibration Summary] 1200 Mbps
4655 22:52:57.496429 CH 0, Rank 0
4656 22:52:57.496480 SW Impedance : PASS
4657 22:52:57.496530 DUTY Scan : NO K
4658 22:52:57.496580 ZQ Calibration : PASS
4659 22:52:57.496630 Jitter Meter : NO K
4660 22:52:57.496684 CBT Training : PASS
4661 22:52:57.496734 Write leveling : PASS
4662 22:52:57.496785 RX DQS gating : PASS
4663 22:52:57.496865 RX DQ/DQS(RDDQC) : PASS
4664 22:52:57.496953 TX DQ/DQS : PASS
4665 22:52:57.497004 RX DATLAT : PASS
4666 22:52:57.497058 RX DQ/DQS(Engine): PASS
4667 22:52:57.497139 TX OE : NO K
4668 22:52:57.497218 All Pass.
4669 22:52:57.497291
4670 22:52:57.497344 CH 0, Rank 1
4671 22:52:57.497395 SW Impedance : PASS
4672 22:52:57.497464 DUTY Scan : NO K
4673 22:52:57.497544 ZQ Calibration : PASS
4674 22:52:57.497625 Jitter Meter : NO K
4675 22:52:57.497704 CBT Training : PASS
4676 22:52:57.497783 Write leveling : PASS
4677 22:52:57.497839 RX DQS gating : PASS
4678 22:52:57.497890 RX DQ/DQS(RDDQC) : PASS
4679 22:52:57.497941 TX DQ/DQS : PASS
4680 22:52:57.497991 RX DATLAT : PASS
4681 22:52:57.498093 RX DQ/DQS(Engine): PASS
4682 22:52:57.498158 TX OE : NO K
4683 22:52:57.498209 All Pass.
4684 22:52:57.498261
4685 22:52:57.498313 CH 1, Rank 0
4686 22:52:57.498363 SW Impedance : PASS
4687 22:52:57.498415 DUTY Scan : NO K
4688 22:52:57.498465 ZQ Calibration : PASS
4689 22:52:57.498516 Jitter Meter : NO K
4690 22:52:57.498567 CBT Training : PASS
4691 22:52:57.498617 Write leveling : PASS
4692 22:52:57.498668 RX DQS gating : PASS
4693 22:52:57.498718 RX DQ/DQS(RDDQC) : PASS
4694 22:52:57.498769 TX DQ/DQS : PASS
4695 22:52:57.498833 RX DATLAT : PASS
4696 22:52:57.498904 RX DQ/DQS(Engine): PASS
4697 22:52:57.498954 TX OE : NO K
4698 22:52:57.499005 All Pass.
4699 22:52:57.499056
4700 22:52:57.499106 CH 1, Rank 1
4701 22:52:57.499156 SW Impedance : PASS
4702 22:52:57.499207 DUTY Scan : NO K
4703 22:52:57.499257 ZQ Calibration : PASS
4704 22:52:57.499308 Jitter Meter : NO K
4705 22:52:57.499358 CBT Training : PASS
4706 22:52:57.499408 Write leveling : PASS
4707 22:52:57.499459 RX DQS gating : PASS
4708 22:52:57.499510 RX DQ/DQS(RDDQC) : PASS
4709 22:52:57.499561 TX DQ/DQS : PASS
4710 22:52:57.499611 RX DATLAT : PASS
4711 22:52:57.499661 RX DQ/DQS(Engine): PASS
4712 22:52:57.499712 TX OE : NO K
4713 22:52:57.499763 All Pass.
4714 22:52:57.499813
4715 22:52:57.499863 DramC Write-DBI off
4716 22:52:57.499914 PER_BANK_REFRESH: Hybrid Mode
4717 22:52:57.499964 TX_TRACKING: ON
4718 22:52:57.500015 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4719 22:52:57.500066 [FAST_K] Save calibration result to emmc
4720 22:52:57.500117 dramc_set_vcore_voltage set vcore to 662500
4721 22:52:57.500168 Read voltage for 933, 3
4722 22:52:57.500219 Vio18 = 0
4723 22:52:57.500269 Vcore = 662500
4724 22:52:57.500319 Vdram = 0
4725 22:52:57.500369 Vddq = 0
4726 22:52:57.500420 Vmddr = 0
4727 22:52:57.500470 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4728 22:52:57.500522 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4729 22:52:57.500573 MEM_TYPE=3, freq_sel=17
4730 22:52:57.500624 sv_algorithm_assistance_LP4_1600
4731 22:52:57.500675 ============ PULL DRAM RESETB DOWN ============
4732 22:52:57.500726 ========== PULL DRAM RESETB DOWN end =========
4733 22:52:57.500777 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4734 22:52:57.500828 ===================================
4735 22:52:57.500879 LPDDR4 DRAM CONFIGURATION
4736 22:52:57.500929 ===================================
4737 22:52:57.500980 EX_ROW_EN[0] = 0x0
4738 22:52:57.501031 EX_ROW_EN[1] = 0x0
4739 22:52:57.501082 LP4Y_EN = 0x0
4740 22:52:57.501132 WORK_FSP = 0x0
4741 22:52:57.501182 WL = 0x3
4742 22:52:57.501232 RL = 0x3
4743 22:52:57.501282 BL = 0x2
4744 22:52:57.501332 RPST = 0x0
4745 22:52:57.501382 RD_PRE = 0x0
4746 22:52:57.501432 WR_PRE = 0x1
4747 22:52:57.501483 WR_PST = 0x0
4748 22:52:57.501533 DBI_WR = 0x0
4749 22:52:57.501582 DBI_RD = 0x0
4750 22:52:57.501632 OTF = 0x1
4751 22:52:57.501683 ===================================
4752 22:52:57.501734 ===================================
4753 22:52:57.501785 ANA top config
4754 22:52:57.501835 ===================================
4755 22:52:57.501887 DLL_ASYNC_EN = 0
4756 22:52:57.501937 ALL_SLAVE_EN = 1
4757 22:52:57.501987 NEW_RANK_MODE = 1
4758 22:52:57.502071 DLL_IDLE_MODE = 1
4759 22:52:57.502150 LP45_APHY_COMB_EN = 1
4760 22:52:57.502388 TX_ODT_DIS = 1
4761 22:52:57.502445 NEW_8X_MODE = 1
4762 22:52:57.502497 ===================================
4763 22:52:57.502549 ===================================
4764 22:52:57.502600 data_rate = 1866
4765 22:52:57.502651 CKR = 1
4766 22:52:57.502717 DQ_P2S_RATIO = 8
4767 22:52:57.502769 ===================================
4768 22:52:57.502821 CA_P2S_RATIO = 8
4769 22:52:57.502873 DQ_CA_OPEN = 0
4770 22:52:57.502924 DQ_SEMI_OPEN = 0
4771 22:52:57.502975 CA_SEMI_OPEN = 0
4772 22:52:57.503026 CA_FULL_RATE = 0
4773 22:52:57.503089 DQ_CKDIV4_EN = 1
4774 22:52:57.503140 CA_CKDIV4_EN = 1
4775 22:52:57.503190 CA_PREDIV_EN = 0
4776 22:52:57.503240 PH8_DLY = 0
4777 22:52:57.503290 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4778 22:52:57.503340 DQ_AAMCK_DIV = 4
4779 22:52:57.503390 CA_AAMCK_DIV = 4
4780 22:52:57.503440 CA_ADMCK_DIV = 4
4781 22:52:57.503490 DQ_TRACK_CA_EN = 0
4782 22:52:57.503540 CA_PICK = 933
4783 22:52:57.503590 CA_MCKIO = 933
4784 22:52:57.503640 MCKIO_SEMI = 0
4785 22:52:57.503690 PLL_FREQ = 3732
4786 22:52:57.503741 DQ_UI_PI_RATIO = 32
4787 22:52:57.503791 CA_UI_PI_RATIO = 0
4788 22:52:57.503841 ===================================
4789 22:52:57.503892 ===================================
4790 22:52:57.503943 memory_type:LPDDR4
4791 22:52:57.503993 GP_NUM : 10
4792 22:52:57.504043 SRAM_EN : 1
4793 22:52:57.504094 MD32_EN : 0
4794 22:52:57.504144 ===================================
4795 22:52:57.504195 [ANA_INIT] >>>>>>>>>>>>>>
4796 22:52:57.504245 <<<<<< [CONFIGURE PHASE]: ANA_TX
4797 22:52:57.504296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4798 22:52:57.504347 ===================================
4799 22:52:57.504397 data_rate = 1866,PCW = 0X8f00
4800 22:52:57.504447 ===================================
4801 22:52:57.504498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4802 22:52:57.504549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4803 22:52:57.504600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4804 22:52:57.504651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4805 22:52:57.504702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4806 22:52:57.504754 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4807 22:52:57.504805 [ANA_INIT] flow start
4808 22:52:57.504856 [ANA_INIT] PLL >>>>>>>>
4809 22:52:57.504935 [ANA_INIT] PLL <<<<<<<<
4810 22:52:57.504985 [ANA_INIT] MIDPI >>>>>>>>
4811 22:52:57.505065 [ANA_INIT] MIDPI <<<<<<<<
4812 22:52:57.505142 [ANA_INIT] DLL >>>>>>>>
4813 22:52:57.505191 [ANA_INIT] flow end
4814 22:52:57.505242 ============ LP4 DIFF to SE enter ============
4815 22:52:57.505294 ============ LP4 DIFF to SE exit ============
4816 22:52:57.505344 [ANA_INIT] <<<<<<<<<<<<<
4817 22:52:57.505395 [Flow] Enable top DCM control >>>>>
4818 22:52:57.505445 [Flow] Enable top DCM control <<<<<
4819 22:52:57.505496 Enable DLL master slave shuffle
4820 22:52:57.505547 ==============================================================
4821 22:52:57.505597 Gating Mode config
4822 22:52:57.505648 ==============================================================
4823 22:52:57.505698 Config description:
4824 22:52:57.505749 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4825 22:52:57.505801 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4826 22:52:57.505851 SELPH_MODE 0: By rank 1: By Phase
4827 22:52:57.505902 ==============================================================
4828 22:52:57.505953 GAT_TRACK_EN = 1
4829 22:52:57.506019 RX_GATING_MODE = 2
4830 22:52:57.506122 RX_GATING_TRACK_MODE = 2
4831 22:52:57.506173 SELPH_MODE = 1
4832 22:52:57.506224 PICG_EARLY_EN = 1
4833 22:52:57.506274 VALID_LAT_VALUE = 1
4834 22:52:57.506325 ==============================================================
4835 22:52:57.506376 Enter into Gating configuration >>>>
4836 22:52:57.506427 Exit from Gating configuration <<<<
4837 22:52:57.506478 Enter into DVFS_PRE_config >>>>>
4838 22:52:57.506529 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4839 22:52:57.506581 Exit from DVFS_PRE_config <<<<<
4840 22:52:57.506631 Enter into PICG configuration >>>>
4841 22:52:57.506682 Exit from PICG configuration <<<<
4842 22:52:57.506732 [RX_INPUT] configuration >>>>>
4843 22:52:57.506783 [RX_INPUT] configuration <<<<<
4844 22:52:57.506834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4845 22:52:57.506885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4846 22:52:57.506935 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4847 22:52:57.506986 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4848 22:52:57.507037 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4849 22:52:57.507088 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4850 22:52:57.507138 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4851 22:52:57.507189 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4852 22:52:57.507239 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4853 22:52:57.507290 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4854 22:52:57.507340 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4855 22:52:57.507406 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4856 22:52:57.507481 ===================================
4857 22:52:57.507532 LPDDR4 DRAM CONFIGURATION
4858 22:52:57.507582 ===================================
4859 22:52:57.507632 EX_ROW_EN[0] = 0x0
4860 22:52:57.507683 EX_ROW_EN[1] = 0x0
4861 22:52:57.507736 LP4Y_EN = 0x0
4862 22:52:57.507787 WORK_FSP = 0x0
4863 22:52:57.508041 WL = 0x3
4864 22:52:57.508147 RL = 0x3
4865 22:52:57.508199 BL = 0x2
4866 22:52:57.508250 RPST = 0x0
4867 22:52:57.508310 RD_PRE = 0x0
4868 22:52:57.508362 WR_PRE = 0x1
4869 22:52:57.508413 WR_PST = 0x0
4870 22:52:57.508468 DBI_WR = 0x0
4871 22:52:57.508519 DBI_RD = 0x0
4872 22:52:57.508570 OTF = 0x1
4873 22:52:57.508620 ===================================
4874 22:52:57.508680 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4875 22:52:57.508731 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4876 22:52:57.508783 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4877 22:52:57.508837 ===================================
4878 22:52:57.508889 LPDDR4 DRAM CONFIGURATION
4879 22:52:57.508940 ===================================
4880 22:52:57.508991 EX_ROW_EN[0] = 0x10
4881 22:52:57.509045 EX_ROW_EN[1] = 0x0
4882 22:52:57.509095 LP4Y_EN = 0x0
4883 22:52:57.509145 WORK_FSP = 0x0
4884 22:52:57.509196 WL = 0x3
4885 22:52:57.509246 RL = 0x3
4886 22:52:57.509296 BL = 0x2
4887 22:52:57.509347 RPST = 0x0
4888 22:52:57.509397 RD_PRE = 0x0
4889 22:52:57.509447 WR_PRE = 0x1
4890 22:52:57.509497 WR_PST = 0x0
4891 22:52:57.509547 DBI_WR = 0x0
4892 22:52:57.509597 DBI_RD = 0x0
4893 22:52:57.509647 OTF = 0x1
4894 22:52:57.509697 ===================================
4895 22:52:57.509766 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4896 22:52:57.509877 nWR fixed to 30
4897 22:52:57.509957 [ModeRegInit_LP4] CH0 RK0
4898 22:52:57.510067 [ModeRegInit_LP4] CH0 RK1
4899 22:52:57.510174 [ModeRegInit_LP4] CH1 RK0
4900 22:52:57.510253 [ModeRegInit_LP4] CH1 RK1
4901 22:52:57.510332 match AC timing 8
4902 22:52:57.510411 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4903 22:52:57.510491 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4904 22:52:57.510571 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4905 22:52:57.510651 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4906 22:52:57.510730 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4907 22:52:57.510809 ==
4908 22:52:57.510889 Dram Type= 6, Freq= 0, CH_0, rank 0
4909 22:52:57.510968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4910 22:52:57.511047 ==
4911 22:52:57.511127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4912 22:52:57.511208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4913 22:52:57.511288 [CA 0] Center 38 (8~69) winsize 62
4914 22:52:57.511367 [CA 1] Center 38 (8~69) winsize 62
4915 22:52:57.511446 [CA 2] Center 36 (6~67) winsize 62
4916 22:52:57.511525 [CA 3] Center 35 (5~66) winsize 62
4917 22:52:57.511605 [CA 4] Center 34 (4~65) winsize 62
4918 22:52:57.511684 [CA 5] Center 34 (4~65) winsize 62
4919 22:52:57.511762
4920 22:52:57.511842 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4921 22:52:57.511920
4922 22:52:57.511999 [CATrainingPosCal] consider 1 rank data
4923 22:52:57.512077 u2DelayCellTimex100 = 270/100 ps
4924 22:52:57.512157 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4925 22:52:57.512236 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4926 22:52:57.512315 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4927 22:52:57.512394 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4928 22:52:57.512473 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4929 22:52:57.512552 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4930 22:52:57.512630
4931 22:52:57.512709 CA PerBit enable=1, Macro0, CA PI delay=34
4932 22:52:57.512787
4933 22:52:57.512866 [CBTSetCACLKResult] CA Dly = 34
4934 22:52:57.512945 CS Dly: 7 (0~38)
4935 22:52:57.513023 ==
4936 22:52:57.513102 Dram Type= 6, Freq= 0, CH_0, rank 1
4937 22:52:57.513182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4938 22:52:57.513261 ==
4939 22:52:57.513341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4940 22:52:57.513421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4941 22:52:57.513500 [CA 0] Center 38 (8~69) winsize 62
4942 22:52:57.513579 [CA 1] Center 38 (8~69) winsize 62
4943 22:52:57.513658 [CA 2] Center 36 (6~67) winsize 62
4944 22:52:57.513738 [CA 3] Center 35 (5~66) winsize 62
4945 22:52:57.513816 [CA 4] Center 34 (3~65) winsize 63
4946 22:52:57.513895 [CA 5] Center 34 (4~65) winsize 62
4947 22:52:57.513973
4948 22:52:57.514095 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4949 22:52:57.514174
4950 22:52:57.514225 [CATrainingPosCal] consider 2 rank data
4951 22:52:57.514276 u2DelayCellTimex100 = 270/100 ps
4952 22:52:57.514327 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4953 22:52:57.514378 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4954 22:52:57.514428 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4955 22:52:57.514479 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4956 22:52:57.514529 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4957 22:52:57.514580 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4958 22:52:57.514631
4959 22:52:57.514682 CA PerBit enable=1, Macro0, CA PI delay=34
4960 22:52:57.514733
4961 22:52:57.514783 [CBTSetCACLKResult] CA Dly = 34
4962 22:52:57.514834 CS Dly: 7 (0~39)
4963 22:52:57.514884
4964 22:52:57.514935 ----->DramcWriteLeveling(PI) begin...
4965 22:52:57.514987 ==
4966 22:52:57.515038 Dram Type= 6, Freq= 0, CH_0, rank 0
4967 22:52:57.515089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4968 22:52:57.515140 ==
4969 22:52:57.515191 Write leveling (Byte 0): 28 => 28
4970 22:52:57.515241 Write leveling (Byte 1): 28 => 28
4971 22:52:57.515291 DramcWriteLeveling(PI) end<-----
4972 22:52:57.515341
4973 22:52:57.515391 ==
4974 22:52:57.515441 Dram Type= 6, Freq= 0, CH_0, rank 0
4975 22:52:57.515491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4976 22:52:57.515542 ==
4977 22:52:57.515592 [Gating] SW mode calibration
4978 22:52:57.515643 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4979 22:52:57.515694 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4980 22:52:57.515745 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4981 22:52:57.515796 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4982 22:52:57.515847 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4983 22:52:57.515897 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4984 22:52:57.515948 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4985 22:52:57.515999 0 10 20 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
4986 22:52:57.516049 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
4987 22:52:57.516100 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4988 22:52:57.516150 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4989 22:52:57.516390 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4990 22:52:57.516447 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4991 22:52:57.516528 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4992 22:52:57.516578 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4993 22:52:57.516629 0 11 20 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
4994 22:52:57.516679 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
4995 22:52:57.516730 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 22:52:57.977034 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4997 22:52:57.977552 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4998 22:52:57.977918 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4999 22:52:57.978292 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5000 22:52:57.978618 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5001 22:52:57.978933 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5002 22:52:57.979244 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 22:52:57.979615 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 22:52:57.979923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 22:52:57.980224 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 22:52:57.980524 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 22:52:57.980819 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 22:52:57.981113 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 22:52:57.981441 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 22:52:57.981745 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 22:52:57.982079 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 22:52:57.982387 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 22:52:57.982682 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 22:52:57.983025 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 22:52:57.983468 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 22:52:57.983922 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5017 22:52:57.984237 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5018 22:52:57.984538 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5019 22:52:57.984836 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5020 22:52:57.985130 Total UI for P1: 0, mck2ui 16
5021 22:52:57.985434 best dqsien dly found for B0: ( 0, 14, 22)
5022 22:52:57.985733 Total UI for P1: 0, mck2ui 16
5023 22:52:57.986057 best dqsien dly found for B1: ( 0, 14, 22)
5024 22:52:57.986364 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5025 22:52:57.986658 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5026 22:52:57.986948
5027 22:52:57.987244 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5028 22:52:57.987541 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5029 22:52:57.987835 [Gating] SW calibration Done
5030 22:52:57.988125 ==
5031 22:52:57.988420 Dram Type= 6, Freq= 0, CH_0, rank 0
5032 22:52:57.988717 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5033 22:52:57.989013 ==
5034 22:52:57.989305 RX Vref Scan: 0
5035 22:52:57.989597
5036 22:52:57.989889 RX Vref 0 -> 0, step: 1
5037 22:52:57.990237
5038 22:52:57.990533 RX Delay -80 -> 252, step: 8
5039 22:52:57.990828 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5040 22:52:57.991123 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5041 22:52:57.991417 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5042 22:52:57.991710 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5043 22:52:57.992002 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5044 22:52:57.992295 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5045 22:52:57.992589 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5046 22:52:57.992882 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5047 22:52:57.993176 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5048 22:52:57.993469 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5049 22:52:57.993762 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5050 22:52:57.994152 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5051 22:52:57.994808 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5052 22:52:57.995399 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5053 22:52:57.995931 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5054 22:52:57.996411 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5055 22:52:57.996877 ==
5056 22:52:57.997345 Dram Type= 6, Freq= 0, CH_0, rank 0
5057 22:52:57.997812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5058 22:52:57.998333 ==
5059 22:52:57.998819 DQS Delay:
5060 22:52:57.999303 DQS0 = 0, DQS1 = 0
5061 22:52:57.999911 DQM Delay:
5062 22:52:58.000340 DQM0 = 96, DQM1 = 87
5063 22:52:58.000655 DQ Delay:
5064 22:52:58.000957 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5065 22:52:58.001282 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5066 22:52:58.001501 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5067 22:52:58.001714 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5068 22:52:58.001923
5069 22:52:58.002246
5070 22:52:58.002460 ==
5071 22:52:58.002669 Dram Type= 6, Freq= 0, CH_0, rank 0
5072 22:52:58.002876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5073 22:52:58.003089 ==
5074 22:52:58.003296
5075 22:52:58.003502
5076 22:52:58.003706 TX Vref Scan disable
5077 22:52:58.003916 == TX Byte 0 ==
5078 22:52:58.004125 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5079 22:52:58.004335 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5080 22:52:58.004543 == TX Byte 1 ==
5081 22:52:58.004751 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5082 22:52:58.004959 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5083 22:52:58.005166 ==
5084 22:52:58.005373 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 22:52:58.005582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5086 22:52:58.005793 ==
5087 22:52:58.006003
5088 22:52:58.006243
5089 22:52:58.006436 TX Vref Scan disable
5090 22:52:58.006761 == TX Byte 0 ==
5091 22:52:58.007082 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5092 22:52:58.007376 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5093 22:52:58.007551 == TX Byte 1 ==
5094 22:52:58.007813 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5095 22:52:58.008114 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5096 22:52:58.008290
5097 22:52:58.008452 [DATLAT]
5098 22:52:58.008610 Freq=933, CH0 RK0
5099 22:52:58.008805
5100 22:52:58.008964 DATLAT Default: 0xd
5101 22:52:58.009122 0, 0xFFFF, sum = 0
5102 22:52:58.009281 1, 0xFFFF, sum = 0
5103 22:52:58.009439 2, 0xFFFF, sum = 0
5104 22:52:58.009594 3, 0xFFFF, sum = 0
5105 22:52:58.009751 4, 0xFFFF, sum = 0
5106 22:52:58.009906 5, 0xFFFF, sum = 0
5107 22:52:58.010080 6, 0xFFFF, sum = 0
5108 22:52:58.010241 7, 0xFFFF, sum = 0
5109 22:52:58.010398 8, 0xFFFF, sum = 0
5110 22:52:58.010842 9, 0xFFFF, sum = 0
5111 22:52:58.011042 10, 0x0, sum = 1
5112 22:52:58.011365 11, 0x0, sum = 2
5113 22:52:58.011628 12, 0x0, sum = 3
5114 22:52:58.011891 13, 0x0, sum = 4
5115 22:52:58.012110 best_step = 11
5116 22:52:58.012241
5117 22:52:58.012366 ==
5118 22:52:58.012491 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 22:52:58.012616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5120 22:52:58.012740 ==
5121 22:52:58.012862 RX Vref Scan: 1
5122 22:52:58.012984
5123 22:52:58.013105 RX Vref 0 -> 0, step: 1
5124 22:52:58.013228
5125 22:52:58.013353 RX Delay -61 -> 252, step: 4
5126 22:52:58.013479
5127 22:52:58.013601 Set Vref, RX VrefLevel [Byte0]: 47
5128 22:52:58.013726 [Byte1]: 49
5129 22:52:58.013848
5130 22:52:58.013969 Final RX Vref Byte 0 = 47 to rank0
5131 22:52:58.014116 Final RX Vref Byte 1 = 49 to rank0
5132 22:52:58.014253 Final RX Vref Byte 0 = 47 to rank1
5133 22:52:58.014377 Final RX Vref Byte 1 = 49 to rank1==
5134 22:52:58.014507 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 22:52:58.014631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5136 22:52:58.014766 ==
5137 22:52:58.014944 DQS Delay:
5138 22:52:58.015227 DQS0 = 0, DQS1 = 0
5139 22:52:58.015459 DQM Delay:
5140 22:52:58.015606 DQM0 = 97, DQM1 = 87
5141 22:52:58.015800 DQ Delay:
5142 22:52:58.015991 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5143 22:52:58.016197 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =104
5144 22:52:58.016355 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =78
5145 22:52:58.016513 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =98
5146 22:52:58.016673
5147 22:52:58.016797
5148 22:52:58.017003 [DQSOSCAuto] RK0, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5149 22:52:58.017247 CH0 RK0: MR19=505, MR18=2121
5150 22:52:58.017416 CH0_RK0: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5151 22:52:58.017561
5152 22:52:58.017670 ----->DramcWriteLeveling(PI) begin...
5153 22:52:58.017776 ==
5154 22:52:58.017879 Dram Type= 6, Freq= 0, CH_0, rank 1
5155 22:52:58.017982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5156 22:52:58.018103 ==
5157 22:52:58.018206 Write leveling (Byte 0): 26 => 26
5158 22:52:58.018308 Write leveling (Byte 1): 25 => 25
5159 22:52:58.018409 DramcWriteLeveling(PI) end<-----
5160 22:52:58.018509
5161 22:52:58.018610 ==
5162 22:52:58.018711 Dram Type= 6, Freq= 0, CH_0, rank 1
5163 22:52:58.018813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5164 22:52:58.018916 ==
5165 22:52:58.019017 [Gating] SW mode calibration
5166 22:52:58.019120 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5167 22:52:58.019223 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5168 22:52:58.019325 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 22:52:58.019428 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 22:52:58.019530 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 22:52:58.019784 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 22:52:58.019985 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5173 22:52:58.020110 0 10 20 | B1->B0 | 3232 2e2e | 0 0 | (1 0) (0 1)
5174 22:52:58.020272 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5175 22:52:58.020452 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 22:52:58.020563 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 22:52:58.020667 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 22:52:58.020770 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 22:52:58.020871 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 22:52:58.020972 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 22:52:58.021073 0 11 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5182 22:52:58.021175 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5183 22:52:58.021299 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 22:52:58.021394 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 22:52:58.021481 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 22:52:58.021568 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 22:52:58.021655 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 22:52:58.021740 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 22:52:58.021827 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 22:52:58.021913 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 22:52:58.021999 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 22:52:58.022100 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 22:52:58.022187 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 22:52:58.022274 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 22:52:58.022360 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 22:52:58.022445 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 22:52:58.022532 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 22:52:58.022618 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 22:52:58.022705 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 22:52:58.022791 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 22:52:58.022877 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 22:52:58.022963 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 22:52:58.023049 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 22:52:58.023136 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 22:52:58.023222 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5206 22:52:58.023308 Total UI for P1: 0, mck2ui 16
5207 22:52:58.023396 best dqsien dly found for B0: ( 0, 14, 18)
5208 22:52:58.023483 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5209 22:52:58.023569 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 22:52:58.023655 Total UI for P1: 0, mck2ui 16
5211 22:52:58.023742 best dqsien dly found for B1: ( 0, 14, 22)
5212 22:52:58.023829 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5213 22:52:58.023916 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5214 22:52:58.024002
5215 22:52:58.024087 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5216 22:52:58.024173 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5217 22:52:58.024258 [Gating] SW calibration Done
5218 22:52:58.024344 ==
5219 22:52:58.024431 Dram Type= 6, Freq= 0, CH_0, rank 1
5220 22:52:58.024518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5221 22:52:58.024604 ==
5222 22:52:58.024690 RX Vref Scan: 0
5223 22:52:58.024776
5224 22:52:58.024862 RX Vref 0 -> 0, step: 1
5225 22:52:58.024948
5226 22:52:58.025033 RX Delay -80 -> 252, step: 8
5227 22:52:58.025353 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5228 22:52:58.025452 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5229 22:52:58.025540 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5230 22:52:58.025627 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5231 22:52:58.025714 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5232 22:52:58.025800 iDelay=200, Bit 5, Center 87 (-16 ~ 191) 208
5233 22:52:58.025887 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5234 22:52:58.026038 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5235 22:52:58.026132 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5236 22:52:58.026219 iDelay=200, Bit 9, Center 67 (-32 ~ 167) 200
5237 22:52:58.026312 iDelay=200, Bit 10, Center 83 (-16 ~ 183) 200
5238 22:52:58.026388 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5239 22:52:58.026463 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5240 22:52:58.026538 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5241 22:52:58.026613 iDelay=200, Bit 14, Center 91 (-8 ~ 191) 200
5242 22:52:58.026688 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5243 22:52:58.026763 ==
5244 22:52:58.026837 Dram Type= 6, Freq= 0, CH_0, rank 1
5245 22:52:58.026913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5246 22:52:58.026988 ==
5247 22:52:58.027063 DQS Delay:
5248 22:52:58.027138 DQS0 = 0, DQS1 = 0
5249 22:52:58.027213 DQM Delay:
5250 22:52:58.027287 DQM0 = 96, DQM1 = 84
5251 22:52:58.027361 DQ Delay:
5252 22:52:58.027436 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5253 22:52:58.027510 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5254 22:52:58.027584 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5255 22:52:58.027659 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95
5256 22:52:58.027734
5257 22:52:58.027808
5258 22:52:58.027881 ==
5259 22:52:58.027971 Dram Type= 6, Freq= 0, CH_0, rank 1
5260 22:52:58.028054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5261 22:52:58.028130 ==
5262 22:52:58.028204
5263 22:52:58.028278
5264 22:52:58.028352 TX Vref Scan disable
5265 22:52:58.028428 == TX Byte 0 ==
5266 22:52:58.028502 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5267 22:52:58.028578 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5268 22:52:58.028653 == TX Byte 1 ==
5269 22:52:58.028729 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5270 22:52:58.028804 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5271 22:52:58.028879 ==
5272 22:52:58.028954 Dram Type= 6, Freq= 0, CH_0, rank 1
5273 22:52:58.029029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5274 22:52:58.029106 ==
5275 22:52:58.029181
5276 22:52:58.029255
5277 22:52:58.029329 TX Vref Scan disable
5278 22:52:58.029404 == TX Byte 0 ==
5279 22:52:58.029479 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5280 22:52:58.029554 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5281 22:52:58.029628 == TX Byte 1 ==
5282 22:52:58.029702 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5283 22:52:58.029777 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5284 22:52:58.029852
5285 22:52:58.029925 [DATLAT]
5286 22:52:58.029999 Freq=933, CH0 RK1
5287 22:52:58.030093
5288 22:52:58.030169 DATLAT Default: 0xb
5289 22:52:58.030244 0, 0xFFFF, sum = 0
5290 22:52:58.030321 1, 0xFFFF, sum = 0
5291 22:52:58.030398 2, 0xFFFF, sum = 0
5292 22:52:58.030475 3, 0xFFFF, sum = 0
5293 22:52:58.030551 4, 0xFFFF, sum = 0
5294 22:52:58.030627 5, 0xFFFF, sum = 0
5295 22:52:58.030703 6, 0xFFFF, sum = 0
5296 22:52:58.030778 7, 0xFFFF, sum = 0
5297 22:52:58.030853 8, 0xFFFF, sum = 0
5298 22:52:58.030929 9, 0xFFFF, sum = 0
5299 22:52:58.031005 10, 0x0, sum = 1
5300 22:52:58.031081 11, 0x0, sum = 2
5301 22:52:58.031155 12, 0x0, sum = 3
5302 22:52:58.031230 13, 0x0, sum = 4
5303 22:52:58.031313 best_step = 11
5304 22:52:58.031379
5305 22:52:58.031444 ==
5306 22:52:58.031510 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 22:52:58.031577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5308 22:52:58.031644 ==
5309 22:52:58.031710 RX Vref Scan: 0
5310 22:52:58.031775
5311 22:52:58.031842 RX Vref 0 -> 0, step: 1
5312 22:52:58.031908
5313 22:52:58.031997 RX Delay -77 -> 252, step: 4
5314 22:52:58.032111 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5315 22:52:58.032184 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5316 22:52:58.032252 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5317 22:52:58.032320 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5318 22:52:58.032387 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5319 22:52:58.032454 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5320 22:52:58.032521 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5321 22:52:58.032587 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5322 22:52:58.032653 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5323 22:52:58.032719 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5324 22:52:58.032786 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5325 22:52:58.032852 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5326 22:52:58.032919 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5327 22:52:58.032985 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5328 22:52:58.033051 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5329 22:52:58.033117 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5330 22:52:58.033184 ==
5331 22:52:58.033250 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 22:52:58.033317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5333 22:52:58.033384 ==
5334 22:52:58.033451 DQS Delay:
5335 22:52:58.033518 DQS0 = 0, DQS1 = 0
5336 22:52:58.033585 DQM Delay:
5337 22:52:58.033651 DQM0 = 97, DQM1 = 86
5338 22:52:58.033717 DQ Delay:
5339 22:52:58.033784 DQ0 =96, DQ1 =100, DQ2 =94, DQ3 =92
5340 22:52:58.033850 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =108
5341 22:52:58.033917 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5342 22:52:58.033984 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5343 22:52:58.034064
5344 22:52:58.034132
5345 22:52:58.034199 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5346 22:52:58.034267 CH0 RK1: MR19=505, MR18=2A2A
5347 22:52:58.034334 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5348 22:52:58.034402 [RxdqsGatingPostProcess] freq 933
5349 22:52:58.034469 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5350 22:52:58.034536 Pre-setting of DQS Precalculation
5351 22:52:58.034603 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5352 22:52:58.034670 ==
5353 22:52:58.034738 Dram Type= 6, Freq= 0, CH_1, rank 0
5354 22:52:58.034815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5355 22:52:58.034882 ==
5356 22:52:58.034949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5357 22:52:58.035017 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5358 22:52:58.035085 [CA 0] Center 37 (7~68) winsize 62
5359 22:52:58.035152 [CA 1] Center 37 (6~68) winsize 63
5360 22:52:58.035219 [CA 2] Center 34 (4~65) winsize 62
5361 22:52:58.035285 [CA 3] Center 34 (4~65) winsize 62
5362 22:52:58.035608 [CA 4] Center 33 (3~64) winsize 62
5363 22:52:58.035749 [CA 5] Center 33 (3~64) winsize 62
5364 22:52:58.035827
5365 22:52:58.035897 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5366 22:52:58.035969
5367 22:52:58.036054 [CATrainingPosCal] consider 1 rank data
5368 22:52:58.036127 u2DelayCellTimex100 = 270/100 ps
5369 22:52:58.036196 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5370 22:52:58.036263 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5371 22:52:58.036338 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5372 22:52:58.036398 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5373 22:52:58.036457 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5374 22:52:58.036517 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5375 22:52:58.036577
5376 22:52:58.036636 CA PerBit enable=1, Macro0, CA PI delay=33
5377 22:52:58.036696
5378 22:52:58.036755 [CBTSetCACLKResult] CA Dly = 33
5379 22:52:58.036815 CS Dly: 5 (0~36)
5380 22:52:58.036874 ==
5381 22:52:58.036933 Dram Type= 6, Freq= 0, CH_1, rank 1
5382 22:52:58.036993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5383 22:52:58.037053 ==
5384 22:52:58.037113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5385 22:52:58.037173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5386 22:52:58.037233 [CA 0] Center 37 (6~68) winsize 63
5387 22:52:58.037294 [CA 1] Center 37 (6~68) winsize 63
5388 22:52:58.037353 [CA 2] Center 35 (5~65) winsize 61
5389 22:52:58.037412 [CA 3] Center 34 (3~65) winsize 63
5390 22:52:58.037472 [CA 4] Center 33 (3~64) winsize 62
5391 22:52:58.037532 [CA 5] Center 33 (3~64) winsize 62
5392 22:52:58.037591
5393 22:52:58.037650 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5394 22:52:58.037709
5395 22:52:58.037768 [CATrainingPosCal] consider 2 rank data
5396 22:52:58.037827 u2DelayCellTimex100 = 270/100 ps
5397 22:52:58.037886 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5398 22:52:58.037946 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5399 22:52:58.038005 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5400 22:52:58.038078 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5401 22:52:58.038138 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5402 22:52:58.038198 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5403 22:52:58.038256
5404 22:52:58.038315 CA PerBit enable=1, Macro0, CA PI delay=33
5405 22:52:58.038375
5406 22:52:58.038434 [CBTSetCACLKResult] CA Dly = 33
5407 22:52:58.038493 CS Dly: 5 (0~37)
5408 22:52:58.038552
5409 22:52:58.038612 ----->DramcWriteLeveling(PI) begin...
5410 22:52:58.038672 ==
5411 22:52:58.038732 Dram Type= 6, Freq= 0, CH_1, rank 0
5412 22:52:58.038791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5413 22:52:58.038852 ==
5414 22:52:58.038911 Write leveling (Byte 0): 25 => 25
5415 22:52:58.038971 Write leveling (Byte 1): 25 => 25
5416 22:52:58.039030 DramcWriteLeveling(PI) end<-----
5417 22:52:58.039089
5418 22:52:58.039147 ==
5419 22:52:58.039207 Dram Type= 6, Freq= 0, CH_1, rank 0
5420 22:52:58.039265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5421 22:52:58.039325 ==
5422 22:52:58.039385 [Gating] SW mode calibration
5423 22:52:58.039445 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5424 22:52:58.039505 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5425 22:52:58.039565 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5426 22:52:58.039626 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5427 22:52:58.039686 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5428 22:52:58.039758 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5429 22:52:58.039819 0 10 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5430 22:52:58.039879 0 10 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5431 22:52:58.039938 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5432 22:52:58.039998 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 22:52:58.040057 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 22:52:58.040117 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 22:52:58.040176 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5436 22:52:58.040236 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5437 22:52:58.040296 0 11 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5438 22:52:58.040355 0 11 20 | B1->B0 | 2a2a 4343 | 0 0 | (0 0) (0 0)
5439 22:52:58.040416 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5440 22:52:58.040482 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 22:52:58.040552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 22:52:58.040617 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 22:52:58.040679 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5444 22:52:58.040739 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5445 22:52:58.040799 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 22:52:58.040864 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5447 22:52:58.040924 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 22:52:58.040984 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 22:52:58.041074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 22:52:58.041167 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 22:52:58.041273 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 22:52:58.041358 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 22:52:58.041443 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 22:52:58.041527 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 22:52:58.041612 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 22:52:58.041697 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 22:52:58.041781 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 22:52:58.041866 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 22:52:58.041951 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 22:52:58.042038 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 22:52:58.042095 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5462 22:52:58.042150 Total UI for P1: 0, mck2ui 16
5463 22:52:58.042206 best dqsien dly found for B0: ( 0, 14, 14)
5464 22:52:58.042261 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5465 22:52:58.042316 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5466 22:52:58.042370 Total UI for P1: 0, mck2ui 16
5467 22:52:58.042425 best dqsien dly found for B1: ( 0, 14, 18)
5468 22:52:58.042672 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5469 22:52:58.042733 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5470 22:52:58.042789
5471 22:52:58.042843 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5472 22:52:58.042898 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5473 22:52:58.042952 [Gating] SW calibration Done
5474 22:52:58.043007 ==
5475 22:52:58.043061 Dram Type= 6, Freq= 0, CH_1, rank 0
5476 22:52:58.043115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5477 22:52:58.043170 ==
5478 22:52:58.043224 RX Vref Scan: 0
5479 22:52:58.043278
5480 22:52:58.043332 RX Vref 0 -> 0, step: 1
5481 22:52:58.043386
5482 22:52:58.043439 RX Delay -80 -> 252, step: 8
5483 22:52:58.043493 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5484 22:52:58.043547 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5485 22:52:58.043602 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5486 22:52:58.043655 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5487 22:52:58.043710 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5488 22:52:58.043763 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5489 22:52:58.043817 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5490 22:52:58.043871 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5491 22:52:58.043925 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5492 22:52:58.043979 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5493 22:52:58.044033 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5494 22:52:58.044087 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5495 22:52:58.044141 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5496 22:52:58.044195 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5497 22:52:58.044249 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5498 22:52:58.044303 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5499 22:52:58.044356 ==
5500 22:52:58.044410 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 22:52:58.044464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5502 22:52:58.044518 ==
5503 22:52:58.044572 DQS Delay:
5504 22:52:58.044626 DQS0 = 0, DQS1 = 0
5505 22:52:58.044679 DQM Delay:
5506 22:52:58.044733 DQM0 = 95, DQM1 = 88
5507 22:52:58.044786 DQ Delay:
5508 22:52:58.044840 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5509 22:52:58.044893 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5510 22:52:58.044947 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5511 22:52:58.045001 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5512 22:52:58.045055
5513 22:52:58.045109
5514 22:52:58.045162 ==
5515 22:52:58.045216 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 22:52:58.045270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5517 22:52:58.045325 ==
5518 22:52:58.045378
5519 22:52:58.045431
5520 22:52:58.045484 TX Vref Scan disable
5521 22:52:58.045538 == TX Byte 0 ==
5522 22:52:58.045592 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5523 22:52:58.045646 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5524 22:52:58.045700 == TX Byte 1 ==
5525 22:52:58.045754 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5526 22:52:58.045808 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5527 22:52:58.045862 ==
5528 22:52:58.045916 Dram Type= 6, Freq= 0, CH_1, rank 0
5529 22:52:58.045970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5530 22:52:58.046037 ==
5531 22:52:58.046124
5532 22:52:58.046208
5533 22:52:58.046302 TX Vref Scan disable
5534 22:52:58.046382 == TX Byte 0 ==
5535 22:52:58.046463 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5536 22:52:58.046537 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5537 22:52:58.046591 == TX Byte 1 ==
5538 22:52:58.046643 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5539 22:52:58.046695 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5540 22:52:58.046746
5541 22:52:58.046797 [DATLAT]
5542 22:52:58.046849 Freq=933, CH1 RK0
5543 22:52:58.046900
5544 22:52:58.046951 DATLAT Default: 0xd
5545 22:52:58.047003 0, 0xFFFF, sum = 0
5546 22:52:58.047056 1, 0xFFFF, sum = 0
5547 22:52:58.047110 2, 0xFFFF, sum = 0
5548 22:52:58.047162 3, 0xFFFF, sum = 0
5549 22:52:58.047214 4, 0xFFFF, sum = 0
5550 22:52:58.047267 5, 0xFFFF, sum = 0
5551 22:52:58.047319 6, 0xFFFF, sum = 0
5552 22:52:58.047371 7, 0xFFFF, sum = 0
5553 22:52:58.047423 8, 0xFFFF, sum = 0
5554 22:52:58.047476 9, 0xFFFF, sum = 0
5555 22:52:58.047528 10, 0x0, sum = 1
5556 22:52:58.047582 11, 0x0, sum = 2
5557 22:52:58.047635 12, 0x0, sum = 3
5558 22:52:58.047687 13, 0x0, sum = 4
5559 22:52:58.047740 best_step = 11
5560 22:52:58.047791
5561 22:52:58.047842 ==
5562 22:52:58.047893 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 22:52:58.047945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5564 22:52:58.047997 ==
5565 22:52:58.048048 RX Vref Scan: 1
5566 22:52:58.048100
5567 22:52:58.048151 RX Vref 0 -> 0, step: 1
5568 22:52:58.048202
5569 22:52:58.048253 RX Delay -69 -> 252, step: 4
5570 22:52:58.048305
5571 22:52:58.048356 Set Vref, RX VrefLevel [Byte0]: 52
5572 22:52:58.048408 [Byte1]: 48
5573 22:52:58.048459
5574 22:52:58.048511 Final RX Vref Byte 0 = 52 to rank0
5575 22:52:58.048563 Final RX Vref Byte 1 = 48 to rank0
5576 22:52:58.048615 Final RX Vref Byte 0 = 52 to rank1
5577 22:52:58.048666 Final RX Vref Byte 1 = 48 to rank1==
5578 22:52:58.048718 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 22:52:58.048769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5580 22:52:58.048821 ==
5581 22:52:58.048872 DQS Delay:
5582 22:52:58.048923 DQS0 = 0, DQS1 = 0
5583 22:52:58.048982 DQM Delay:
5584 22:52:58.049079 DQM0 = 94, DQM1 = 88
5585 22:52:58.049165 DQ Delay:
5586 22:52:58.049246 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5587 22:52:58.049327 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5588 22:52:58.049408 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
5589 22:52:58.049492 DQ12 =94, DQ13 =100, DQ14 =98, DQ15 =98
5590 22:52:58.049546
5591 22:52:58.049598
5592 22:52:58.049650 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5593 22:52:58.049703 CH1 RK0: MR19=505, MR18=3636
5594 22:52:58.049755 CH1_RK0: MR19=0x505, MR18=0x3636, DQSOSC=404, MR23=63, INC=66, DEC=44
5595 22:52:58.049808
5596 22:52:58.049859 ----->DramcWriteLeveling(PI) begin...
5597 22:52:58.049913 ==
5598 22:52:58.049965 Dram Type= 6, Freq= 0, CH_1, rank 1
5599 22:52:58.050018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5600 22:52:58.050111 ==
5601 22:52:58.050163 Write leveling (Byte 0): 23 => 23
5602 22:52:58.050214 Write leveling (Byte 1): 22 => 22
5603 22:52:58.050266 DramcWriteLeveling(PI) end<-----
5604 22:52:58.050317
5605 22:52:58.050368 ==
5606 22:52:58.050420 Dram Type= 6, Freq= 0, CH_1, rank 1
5607 22:52:58.050472 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5608 22:52:58.050523 ==
5609 22:52:58.050575 [Gating] SW mode calibration
5610 22:52:58.050627 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5611 22:52:58.050678 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5612 22:52:58.050730 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 22:52:58.050782 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 22:52:58.050833 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 22:52:58.050885 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5616 22:52:58.051137 0 10 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
5617 22:52:58.051199 0 10 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5618 22:52:58.051252 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 22:52:58.051306 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 22:52:58.051358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 22:52:58.051410 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 22:52:58.051462 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 22:52:58.051523 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5624 22:52:58.051577 0 11 16 | B1->B0 | 2323 3636 | 0 1 | (0 0) (1 1)
5625 22:52:58.051629 0 11 20 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5626 22:52:58.051682 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 22:52:58.051740 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 22:52:58.051792 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 22:52:58.051843 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 22:52:58.051899 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 22:52:58.051950 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 22:52:58.052002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 22:52:58.052059 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5634 22:52:58.052113 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 22:52:58.052165 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 22:52:58.052216 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 22:52:58.052272 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 22:52:58.052323 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 22:52:58.052375 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 22:52:58.052432 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 22:52:58.052514 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 22:52:58.052595 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 22:52:58.052678 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 22:52:58.052760 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 22:52:58.052840 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 22:52:58.052922 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 22:52:58.053003 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 22:52:58.053084 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 22:52:58.053165 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5650 22:52:58.053245 Total UI for P1: 0, mck2ui 16
5651 22:52:58.053327 best dqsien dly found for B0: ( 0, 14, 18)
5652 22:52:58.053408 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 22:52:58.053489 Total UI for P1: 0, mck2ui 16
5654 22:52:58.053570 best dqsien dly found for B1: ( 0, 14, 20)
5655 22:52:58.053651 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5656 22:52:58.053733 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5657 22:52:58.053813
5658 22:52:58.053894 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5659 22:52:58.053975 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5660 22:52:58.054103 [Gating] SW calibration Done
5661 22:52:58.054192 ==
5662 22:52:58.054274 Dram Type= 6, Freq= 0, CH_1, rank 1
5663 22:52:58.054370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5664 22:52:58.054534 ==
5665 22:52:58.054635 RX Vref Scan: 0
5666 22:52:58.054694
5667 22:52:58.054755 RX Vref 0 -> 0, step: 1
5668 22:52:58.054820
5669 22:52:58.054874 RX Delay -80 -> 252, step: 8
5670 22:52:58.054926 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5671 22:52:58.054979 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5672 22:52:58.055032 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5673 22:52:58.055084 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5674 22:52:58.055135 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5675 22:52:58.055187 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5676 22:52:58.055238 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5677 22:52:58.055290 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5678 22:52:58.055342 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5679 22:52:58.055402 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5680 22:52:58.055485 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5681 22:52:58.055567 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5682 22:52:58.055649 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5683 22:52:58.055719 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5684 22:52:58.055772 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5685 22:52:58.055824 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5686 22:52:58.055876 ==
5687 22:52:58.055928 Dram Type= 6, Freq= 0, CH_1, rank 1
5688 22:52:58.055980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5689 22:52:58.056032 ==
5690 22:52:58.056083 DQS Delay:
5691 22:52:58.056135 DQS0 = 0, DQS1 = 0
5692 22:52:58.056186 DQM Delay:
5693 22:52:58.056238 DQM0 = 95, DQM1 = 86
5694 22:52:58.056289 DQ Delay:
5695 22:52:58.056340 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5696 22:52:58.056392 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5697 22:52:58.056443 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5698 22:52:58.056494 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =91
5699 22:52:58.056546
5700 22:52:58.056597
5701 22:52:58.056648 ==
5702 22:52:58.056699 Dram Type= 6, Freq= 0, CH_1, rank 1
5703 22:52:58.056752 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5704 22:52:58.056804 ==
5705 22:52:58.056855
5706 22:52:58.056906
5707 22:52:58.056957 TX Vref Scan disable
5708 22:52:58.057009 == TX Byte 0 ==
5709 22:52:58.057060 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5710 22:52:58.057113 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5711 22:52:58.057166 == TX Byte 1 ==
5712 22:52:58.057217 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5713 22:52:58.057269 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5714 22:52:58.057320 ==
5715 22:52:58.057372 Dram Type= 6, Freq= 0, CH_1, rank 1
5716 22:52:58.057424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5717 22:52:58.057476 ==
5718 22:52:58.057527
5719 22:52:58.057578
5720 22:52:58.057629 TX Vref Scan disable
5721 22:52:58.057680 == TX Byte 0 ==
5722 22:52:58.057732 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5723 22:52:58.057898 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5724 22:52:58.057999 == TX Byte 1 ==
5725 22:52:58.058102 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5726 22:52:58.058157 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5727 22:52:58.058209
5728 22:52:58.058261 [DATLAT]
5729 22:52:58.058313 Freq=933, CH1 RK1
5730 22:52:58.058365
5731 22:52:58.058607 DATLAT Default: 0xb
5732 22:52:58.058665 0, 0xFFFF, sum = 0
5733 22:52:58.058719 1, 0xFFFF, sum = 0
5734 22:52:58.058772 2, 0xFFFF, sum = 0
5735 22:52:58.058824 3, 0xFFFF, sum = 0
5736 22:52:58.058877 4, 0xFFFF, sum = 0
5737 22:52:58.058928 5, 0xFFFF, sum = 0
5738 22:52:58.058981 6, 0xFFFF, sum = 0
5739 22:52:58.059033 7, 0xFFFF, sum = 0
5740 22:52:58.059085 8, 0xFFFF, sum = 0
5741 22:52:58.059138 9, 0xFFFF, sum = 0
5742 22:52:58.059190 10, 0x0, sum = 1
5743 22:52:58.059242 11, 0x0, sum = 2
5744 22:52:58.059294 12, 0x0, sum = 3
5745 22:52:58.059346 13, 0x0, sum = 4
5746 22:52:58.059399 best_step = 11
5747 22:52:58.059450
5748 22:52:58.059501 ==
5749 22:52:58.059553 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 22:52:58.059605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5751 22:52:58.059656 ==
5752 22:52:58.059708 RX Vref Scan: 0
5753 22:52:58.059759
5754 22:52:58.059810 RX Vref 0 -> 0, step: 1
5755 22:52:58.059863
5756 22:52:58.059914 RX Delay -69 -> 252, step: 4
5757 22:52:58.059966 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5758 22:52:58.060018 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5759 22:52:58.060070 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5760 22:52:58.060121 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5761 22:52:58.060173 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5762 22:52:58.060224 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5763 22:52:58.060376 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5764 22:52:58.060492 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5765 22:52:58.060559 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5766 22:52:58.060613 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5767 22:52:58.060666 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5768 22:52:58.060718 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5769 22:52:58.060770 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5770 22:52:58.060822 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5771 22:52:58.060874 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5772 22:52:58.060925 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5773 22:52:58.060977 ==
5774 22:52:58.061029 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 22:52:58.061080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5776 22:52:58.061132 ==
5777 22:52:58.061183 DQS Delay:
5778 22:52:58.061234 DQS0 = 0, DQS1 = 0
5779 22:52:58.061286 DQM Delay:
5780 22:52:58.061337 DQM0 = 96, DQM1 = 87
5781 22:52:58.061388 DQ Delay:
5782 22:52:58.061439 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5783 22:52:58.061491 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5784 22:52:58.061542 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5785 22:52:58.061594 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5786 22:52:58.061645
5787 22:52:58.061696
5788 22:52:58.061747 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5789 22:52:58.061800 CH1 RK1: MR19=505, MR18=2626
5790 22:52:58.061851 CH1_RK1: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5791 22:52:58.061903 [RxdqsGatingPostProcess] freq 933
5792 22:52:58.061955 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5793 22:52:58.062007 Pre-setting of DQS Precalculation
5794 22:52:58.062100 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5795 22:52:58.062153 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5796 22:52:58.062205 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5797 22:52:58.062258
5798 22:52:58.062309
5799 22:52:58.062360 [Calibration Summary] 1866 Mbps
5800 22:52:58.062411 CH 0, Rank 0
5801 22:52:58.062462 SW Impedance : PASS
5802 22:52:58.062514 DUTY Scan : NO K
5803 22:52:58.062566 ZQ Calibration : PASS
5804 22:52:58.062617 Jitter Meter : NO K
5805 22:52:58.062670 CBT Training : PASS
5806 22:52:58.062721 Write leveling : PASS
5807 22:52:58.062773 RX DQS gating : PASS
5808 22:52:58.062824 RX DQ/DQS(RDDQC) : PASS
5809 22:52:58.062876 TX DQ/DQS : PASS
5810 22:52:58.062928 RX DATLAT : PASS
5811 22:52:58.062979 RX DQ/DQS(Engine): PASS
5812 22:52:58.063030 TX OE : NO K
5813 22:52:58.063082 All Pass.
5814 22:52:58.063133
5815 22:52:58.063184 CH 0, Rank 1
5816 22:52:58.063236 SW Impedance : PASS
5817 22:52:58.063287 DUTY Scan : NO K
5818 22:52:58.063338 ZQ Calibration : PASS
5819 22:52:58.063390 Jitter Meter : NO K
5820 22:52:58.063440 CBT Training : PASS
5821 22:52:58.063492 Write leveling : PASS
5822 22:52:58.063543 RX DQS gating : PASS
5823 22:52:58.063594 RX DQ/DQS(RDDQC) : PASS
5824 22:52:58.063645 TX DQ/DQS : PASS
5825 22:52:58.063696 RX DATLAT : PASS
5826 22:52:58.063747 RX DQ/DQS(Engine): PASS
5827 22:52:58.063798 TX OE : NO K
5828 22:52:58.063850 All Pass.
5829 22:52:58.063902
5830 22:52:58.063953 CH 1, Rank 0
5831 22:52:58.064004 SW Impedance : PASS
5832 22:52:58.064056 DUTY Scan : NO K
5833 22:52:58.064108 ZQ Calibration : PASS
5834 22:52:58.064159 Jitter Meter : NO K
5835 22:52:58.064211 CBT Training : PASS
5836 22:52:58.064263 Write leveling : PASS
5837 22:52:58.064314 RX DQS gating : PASS
5838 22:52:58.064365 RX DQ/DQS(RDDQC) : PASS
5839 22:52:58.064417 TX DQ/DQS : PASS
5840 22:52:58.064468 RX DATLAT : PASS
5841 22:52:58.064520 RX DQ/DQS(Engine): PASS
5842 22:52:58.064571 TX OE : NO K
5843 22:52:58.064622 All Pass.
5844 22:52:58.064674
5845 22:52:58.064725 CH 1, Rank 1
5846 22:52:58.064777 SW Impedance : PASS
5847 22:52:58.064828 DUTY Scan : NO K
5848 22:52:58.064879 ZQ Calibration : PASS
5849 22:52:58.064930 Jitter Meter : NO K
5850 22:52:58.064982 CBT Training : PASS
5851 22:52:58.065033 Write leveling : PASS
5852 22:52:58.065084 RX DQS gating : PASS
5853 22:52:58.065136 RX DQ/DQS(RDDQC) : PASS
5854 22:52:58.065187 TX DQ/DQS : PASS
5855 22:52:58.065239 RX DATLAT : PASS
5856 22:52:58.065290 RX DQ/DQS(Engine): PASS
5857 22:52:58.065342 TX OE : NO K
5858 22:52:58.065393 All Pass.
5859 22:52:58.065444
5860 22:52:58.065495 DramC Write-DBI off
5861 22:52:58.065546 PER_BANK_REFRESH: Hybrid Mode
5862 22:52:58.065598 TX_TRACKING: ON
5863 22:52:58.065649 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5864 22:52:58.065702 [FAST_K] Save calibration result to emmc
5865 22:52:58.065753 dramc_set_vcore_voltage set vcore to 650000
5866 22:52:58.065804 Read voltage for 400, 6
5867 22:52:58.065865 Vio18 = 0
5868 22:52:58.065947 Vcore = 650000
5869 22:52:58.066036 Vdram = 0
5870 22:52:58.066126 Vddq = 0
5871 22:52:58.066178 Vmddr = 0
5872 22:52:58.066230 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5873 22:52:58.066289 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5874 22:52:58.066344 MEM_TYPE=3, freq_sel=20
5875 22:52:58.066396 sv_algorithm_assistance_LP4_800
5876 22:52:58.066448 ============ PULL DRAM RESETB DOWN ============
5877 22:52:58.066505 ========== PULL DRAM RESETB DOWN end =========
5878 22:52:58.066745 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5879 22:52:58.066804 ===================================
5880 22:52:58.066860 LPDDR4 DRAM CONFIGURATION
5881 22:52:58.066913 ===================================
5882 22:52:58.066966 EX_ROW_EN[0] = 0x0
5883 22:52:58.067020 EX_ROW_EN[1] = 0x0
5884 22:52:58.067072 LP4Y_EN = 0x0
5885 22:52:58.067124 WORK_FSP = 0x0
5886 22:52:58.067175 WL = 0x2
5887 22:52:58.067226 RL = 0x2
5888 22:52:58.067278 BL = 0x2
5889 22:52:58.067329 RPST = 0x0
5890 22:52:58.067381 RD_PRE = 0x0
5891 22:52:58.067433 WR_PRE = 0x1
5892 22:52:58.067484 WR_PST = 0x0
5893 22:52:58.067535 DBI_WR = 0x0
5894 22:52:58.067586 DBI_RD = 0x0
5895 22:52:58.067637 OTF = 0x1
5896 22:52:58.067688 ===================================
5897 22:52:58.067740 ===================================
5898 22:52:58.067792 ANA top config
5899 22:52:58.067843 ===================================
5900 22:52:58.067895 DLL_ASYNC_EN = 0
5901 22:52:58.067946 ALL_SLAVE_EN = 1
5902 22:52:58.067996 NEW_RANK_MODE = 1
5903 22:52:58.068049 DLL_IDLE_MODE = 1
5904 22:52:58.068100 LP45_APHY_COMB_EN = 1
5905 22:52:58.068151 TX_ODT_DIS = 1
5906 22:52:58.068202 NEW_8X_MODE = 1
5907 22:52:58.068254 ===================================
5908 22:52:58.068306 ===================================
5909 22:52:58.068358 data_rate = 800
5910 22:52:58.068409 CKR = 1
5911 22:52:58.068460 DQ_P2S_RATIO = 4
5912 22:52:58.068512 ===================================
5913 22:52:58.068563 CA_P2S_RATIO = 4
5914 22:52:58.068614 DQ_CA_OPEN = 0
5915 22:52:58.068665 DQ_SEMI_OPEN = 1
5916 22:52:58.068717 CA_SEMI_OPEN = 1
5917 22:52:58.068768 CA_FULL_RATE = 0
5918 22:52:58.068820 DQ_CKDIV4_EN = 0
5919 22:52:58.068871 CA_CKDIV4_EN = 1
5920 22:52:58.068922 CA_PREDIV_EN = 0
5921 22:52:58.068973 PH8_DLY = 0
5922 22:52:58.069036 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5923 22:52:58.069090 DQ_AAMCK_DIV = 0
5924 22:52:58.072436 CA_AAMCK_DIV = 0
5925 22:52:58.075581 CA_ADMCK_DIV = 4
5926 22:52:58.079028 DQ_TRACK_CA_EN = 0
5927 22:52:58.082547 CA_PICK = 800
5928 22:52:58.085821 CA_MCKIO = 400
5929 22:52:58.089086 MCKIO_SEMI = 400
5930 22:52:58.089550 PLL_FREQ = 3016
5931 22:52:58.092610 DQ_UI_PI_RATIO = 32
5932 22:52:58.095863 CA_UI_PI_RATIO = 32
5933 22:52:58.099590 ===================================
5934 22:52:58.102392 ===================================
5935 22:52:58.105821 memory_type:LPDDR4
5936 22:52:58.109114 GP_NUM : 10
5937 22:52:58.109431 SRAM_EN : 1
5938 22:52:58.112241 MD32_EN : 0
5939 22:52:58.115617 ===================================
5940 22:52:58.116062 [ANA_INIT] >>>>>>>>>>>>>>
5941 22:52:58.119175 <<<<<< [CONFIGURE PHASE]: ANA_TX
5942 22:52:58.122480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5943 22:52:58.125786 ===================================
5944 22:52:58.129061 data_rate = 800,PCW = 0X7400
5945 22:52:58.132471 ===================================
5946 22:52:58.136096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5947 22:52:58.142259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5948 22:52:58.152639 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5949 22:52:58.158894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5950 22:52:58.162614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5951 22:52:58.165557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5952 22:52:58.165972 [ANA_INIT] flow start
5953 22:52:58.169069 [ANA_INIT] PLL >>>>>>>>
5954 22:52:58.172203 [ANA_INIT] PLL <<<<<<<<
5955 22:52:58.172614 [ANA_INIT] MIDPI >>>>>>>>
5956 22:52:58.175826 [ANA_INIT] MIDPI <<<<<<<<
5957 22:52:58.178804 [ANA_INIT] DLL >>>>>>>>
5958 22:52:58.179217 [ANA_INIT] flow end
5959 22:52:58.185734 ============ LP4 DIFF to SE enter ============
5960 22:52:58.189351 ============ LP4 DIFF to SE exit ============
5961 22:52:58.192421 [ANA_INIT] <<<<<<<<<<<<<
5962 22:52:58.195698 [Flow] Enable top DCM control >>>>>
5963 22:52:58.198822 [Flow] Enable top DCM control <<<<<
5964 22:52:58.199330 Enable DLL master slave shuffle
5965 22:52:58.205926 ==============================================================
5966 22:52:58.208840 Gating Mode config
5967 22:52:58.211905 ==============================================================
5968 22:52:58.215232 Config description:
5969 22:52:58.225355 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5970 22:52:58.231913 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5971 22:52:58.235537 SELPH_MODE 0: By rank 1: By Phase
5972 22:52:58.242171 ==============================================================
5973 22:52:58.245474 GAT_TRACK_EN = 0
5974 22:52:58.248433 RX_GATING_MODE = 2
5975 22:52:58.251755 RX_GATING_TRACK_MODE = 2
5976 22:52:58.254907 SELPH_MODE = 1
5977 22:52:58.258383 PICG_EARLY_EN = 1
5978 22:52:58.258918 VALID_LAT_VALUE = 1
5979 22:52:58.264812 ==============================================================
5980 22:52:58.268374 Enter into Gating configuration >>>>
5981 22:52:58.271644 Exit from Gating configuration <<<<
5982 22:52:58.274870 Enter into DVFS_PRE_config >>>>>
5983 22:52:58.284811 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5984 22:52:58.288166 Exit from DVFS_PRE_config <<<<<
5985 22:52:58.291502 Enter into PICG configuration >>>>
5986 22:52:58.294684 Exit from PICG configuration <<<<
5987 22:52:58.297978 [RX_INPUT] configuration >>>>>
5988 22:52:58.301356 [RX_INPUT] configuration <<<<<
5989 22:52:58.305087 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5990 22:52:58.311404 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5991 22:52:58.824970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5992 22:52:58.825553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5993 22:52:58.825921 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5994 22:52:58.826324 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5995 22:52:58.826654 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5996 22:52:58.826970 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5997 22:52:58.827297 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5998 22:52:58.827602 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5999 22:52:58.827953 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6000 22:52:58.828254 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6001 22:52:58.828593 ===================================
6002 22:52:58.828896 LPDDR4 DRAM CONFIGURATION
6003 22:52:58.829194 ===================================
6004 22:52:58.829490 EX_ROW_EN[0] = 0x0
6005 22:52:58.829785 EX_ROW_EN[1] = 0x0
6006 22:52:58.830125 LP4Y_EN = 0x0
6007 22:52:58.830427 WORK_FSP = 0x0
6008 22:52:58.830718 WL = 0x2
6009 22:52:58.831011 RL = 0x2
6010 22:52:58.831302 BL = 0x2
6011 22:52:58.831670 RPST = 0x0
6012 22:52:58.832009 RD_PRE = 0x0
6013 22:52:58.832303 WR_PRE = 0x1
6014 22:52:58.832594 WR_PST = 0x0
6015 22:52:58.832884 DBI_WR = 0x0
6016 22:52:58.833173 DBI_RD = 0x0
6017 22:52:58.833460 OTF = 0x1
6018 22:52:58.833798 ===================================
6019 22:52:58.834186 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6020 22:52:58.834491 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6021 22:52:58.834858 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6022 22:52:58.835159 ===================================
6023 22:52:58.835453 LPDDR4 DRAM CONFIGURATION
6024 22:52:58.835745 ===================================
6025 22:52:58.836036 EX_ROW_EN[0] = 0x10
6026 22:52:58.836326 EX_ROW_EN[1] = 0x0
6027 22:52:58.836622 LP4Y_EN = 0x0
6028 22:52:58.836909 WORK_FSP = 0x0
6029 22:52:58.837200 WL = 0x2
6030 22:52:58.837485 RL = 0x2
6031 22:52:58.837813 BL = 0x2
6032 22:52:58.838161 RPST = 0x0
6033 22:52:58.838460 RD_PRE = 0x0
6034 22:52:58.838749 WR_PRE = 0x1
6035 22:52:58.839036 WR_PST = 0x0
6036 22:52:58.839325 DBI_WR = 0x0
6037 22:52:58.839613 DBI_RD = 0x0
6038 22:52:58.839901 OTF = 0x1
6039 22:52:58.840188 ===================================
6040 22:52:58.840521 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6041 22:52:58.840822 nWR fixed to 30
6042 22:52:58.841160 [ModeRegInit_LP4] CH0 RK0
6043 22:52:58.841485 [ModeRegInit_LP4] CH0 RK1
6044 22:52:58.841781 [ModeRegInit_LP4] CH1 RK0
6045 22:52:58.842092 [ModeRegInit_LP4] CH1 RK1
6046 22:52:58.842385 match AC timing 18
6047 22:52:58.842719 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6048 22:52:58.843013 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6049 22:52:58.843315 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6050 22:52:58.843579 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6051 22:52:58.843843 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6052 22:52:58.844104 ==
6053 22:52:58.844401 Dram Type= 6, Freq= 0, CH_0, rank 0
6054 22:52:58.844669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6055 22:52:58.844972 ==
6056 22:52:58.845234 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6057 22:52:58.845544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6058 22:52:58.845839 [CA 0] Center 36 (8~64) winsize 57
6059 22:52:58.846161 [CA 1] Center 36 (8~64) winsize 57
6060 22:52:58.846449 [CA 2] Center 36 (8~64) winsize 57
6061 22:52:58.846711 [CA 3] Center 36 (8~64) winsize 57
6062 22:52:58.846972 [CA 4] Center 36 (8~64) winsize 57
6063 22:52:58.847235 [CA 5] Center 36 (8~64) winsize 57
6064 22:52:58.847496
6065 22:52:58.847798 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6066 22:52:58.848063
6067 22:52:58.848396 [CATrainingPosCal] consider 1 rank data
6068 22:52:58.848588 u2DelayCellTimex100 = 270/100 ps
6069 22:52:58.848778 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 22:52:58.848968 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 22:52:58.849156 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6072 22:52:58.849344 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6073 22:52:58.849530 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6074 22:52:58.849719 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6075 22:52:58.849906
6076 22:52:58.850127 CA PerBit enable=1, Macro0, CA PI delay=36
6077 22:52:58.850323
6078 22:52:58.850517 [CBTSetCACLKResult] CA Dly = 36
6079 22:52:58.850709 CS Dly: 1 (0~32)
6080 22:52:58.850898 ==
6081 22:52:58.851169 Dram Type= 6, Freq= 0, CH_0, rank 1
6082 22:52:58.851365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6083 22:52:58.851587 ==
6084 22:52:58.851779 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6085 22:52:58.851967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6086 22:52:58.852157 [CA 0] Center 36 (8~64) winsize 57
6087 22:52:58.852346 [CA 1] Center 36 (8~64) winsize 57
6088 22:52:58.852545 [CA 2] Center 36 (8~64) winsize 57
6089 22:52:58.852737 [CA 3] Center 36 (8~64) winsize 57
6090 22:52:58.852926 [CA 4] Center 36 (8~64) winsize 57
6091 22:52:58.853113 [CA 5] Center 36 (8~64) winsize 57
6092 22:52:58.853289
6093 22:52:58.853429 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6094 22:52:58.853571
6095 22:52:58.853711 [CATrainingPosCal] consider 2 rank data
6096 22:52:58.853852 u2DelayCellTimex100 = 270/100 ps
6097 22:52:58.854002 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6098 22:52:58.854168 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6099 22:52:58.854314 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6100 22:52:58.854487 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6101 22:52:58.854631 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6102 22:52:58.854793 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6103 22:52:58.855032
6104 22:52:58.855240 CA PerBit enable=1, Macro0, CA PI delay=36
6105 22:52:58.855391
6106 22:52:58.855537 [CBTSetCACLKResult] CA Dly = 36
6107 22:52:58.855682 CS Dly: 1 (0~32)
6108 22:52:58.855824
6109 22:52:58.855967 ----->DramcWriteLeveling(PI) begin...
6110 22:52:58.856112 ==
6111 22:52:58.856256 Dram Type= 6, Freq= 0, CH_0, rank 0
6112 22:52:58.856399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6113 22:52:58.856543 ==
6114 22:52:58.856685 Write leveling (Byte 0): 32 => 0
6115 22:52:58.856828 Write leveling (Byte 1): 32 => 0
6116 22:52:58.857228 DramcWriteLeveling(PI) end<-----
6117 22:52:58.857389
6118 22:52:58.857566 ==
6119 22:52:58.857710 Dram Type= 6, Freq= 0, CH_0, rank 0
6120 22:52:58.857853 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6121 22:52:58.858062 ==
6122 22:52:58.858229 [Gating] SW mode calibration
6123 22:52:58.858363 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6124 22:52:58.858479 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6125 22:52:58.858600 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6126 22:52:58.858717 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6127 22:52:58.858833 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6128 22:52:58.858948 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6129 22:52:58.859063 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6130 22:52:58.859176 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6131 22:52:58.859291 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6132 22:52:58.859405 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6133 22:52:58.859521 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6134 22:52:58.859636 Total UI for P1: 0, mck2ui 16
6135 22:52:58.859752 best dqsien dly found for B0: ( 0, 10, 16)
6136 22:52:58.859868 Total UI for P1: 0, mck2ui 16
6137 22:52:58.859983 best dqsien dly found for B1: ( 0, 10, 16)
6138 22:52:58.860096 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6139 22:52:58.860221 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6140 22:52:58.860336
6141 22:52:58.860448 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6142 22:52:58.860562 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6143 22:52:58.860676 [Gating] SW calibration Done
6144 22:52:58.860791 ==
6145 22:52:58.860906 Dram Type= 6, Freq= 0, CH_0, rank 0
6146 22:52:58.861037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6147 22:52:58.861155 ==
6148 22:52:58.861270 RX Vref Scan: 0
6149 22:52:58.861384
6150 22:52:58.861514 RX Vref 0 -> 0, step: 1
6151 22:52:58.861628
6152 22:52:58.861742 RX Delay -410 -> 252, step: 16
6153 22:52:58.861857 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6154 22:52:58.861972 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6155 22:52:58.862107 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6156 22:52:58.862235 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6157 22:52:58.862349 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6158 22:52:58.862463 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6159 22:52:58.862576 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6160 22:52:58.862690 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6161 22:52:58.862805 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6162 22:52:58.862919 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6163 22:52:58.863032 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6164 22:52:58.863147 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6165 22:52:58.863274 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6166 22:52:58.863370 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6167 22:52:58.863466 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6168 22:52:58.863560 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6169 22:52:58.863655 ==
6170 22:52:58.863750 Dram Type= 6, Freq= 0, CH_0, rank 0
6171 22:52:58.863847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6172 22:52:58.863942 ==
6173 22:52:58.864037 DQS Delay:
6174 22:52:58.864131 DQS0 = 51, DQS1 = 59
6175 22:52:58.864276 DQM Delay:
6176 22:52:58.864452 DQM0 = 12, DQM1 = 13
6177 22:52:58.864559 DQ Delay:
6178 22:52:58.864657 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6179 22:52:58.864755 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6180 22:52:58.867908 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6181 22:52:58.871357 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6182 22:52:58.871485
6183 22:52:58.871584
6184 22:52:58.871676 ==
6185 22:52:58.874392 Dram Type= 6, Freq= 0, CH_0, rank 0
6186 22:52:58.877804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6187 22:52:58.877932 ==
6188 22:52:58.878065
6189 22:52:58.878162
6190 22:52:58.881340 TX Vref Scan disable
6191 22:52:58.881549 == TX Byte 0 ==
6192 22:52:58.888047 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6193 22:52:58.891605 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6194 22:52:58.891814 == TX Byte 1 ==
6195 22:52:58.898201 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6196 22:52:58.901207 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6197 22:52:58.901415 ==
6198 22:52:58.904624 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 22:52:58.907755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6200 22:52:58.907938 ==
6201 22:52:58.908049
6202 22:52:58.908148
6203 22:52:58.911101 TX Vref Scan disable
6204 22:52:58.914176 == TX Byte 0 ==
6205 22:52:58.917879 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6206 22:52:58.920961 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6207 22:52:58.924878 == TX Byte 1 ==
6208 22:52:58.928342 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6209 22:52:58.931811 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6210 22:52:58.932382
6211 22:52:58.932741 [DATLAT]
6212 22:52:58.934813 Freq=400, CH0 RK0
6213 22:52:58.935293
6214 22:52:58.935653 DATLAT Default: 0xf
6215 22:52:58.938087 0, 0xFFFF, sum = 0
6216 22:52:58.938663 1, 0xFFFF, sum = 0
6217 22:52:58.941227 2, 0xFFFF, sum = 0
6218 22:52:58.945150 3, 0xFFFF, sum = 0
6219 22:52:58.945718 4, 0xFFFF, sum = 0
6220 22:52:58.948072 5, 0xFFFF, sum = 0
6221 22:52:58.948604 6, 0xFFFF, sum = 0
6222 22:52:58.951003 7, 0xFFFF, sum = 0
6223 22:52:58.951526 8, 0xFFFF, sum = 0
6224 22:52:58.954549 9, 0xFFFF, sum = 0
6225 22:52:58.955013 10, 0xFFFF, sum = 0
6226 22:52:58.957805 11, 0xFFFF, sum = 0
6227 22:52:58.958414 12, 0x0, sum = 1
6228 22:52:58.961114 13, 0x0, sum = 2
6229 22:52:58.961578 14, 0x0, sum = 3
6230 22:52:58.964711 15, 0x0, sum = 4
6231 22:52:58.965294 best_step = 13
6232 22:52:58.965657
6233 22:52:58.965991 ==
6234 22:52:58.968227 Dram Type= 6, Freq= 0, CH_0, rank 0
6235 22:52:58.970861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6236 22:52:58.974341 ==
6237 22:52:58.974868 RX Vref Scan: 1
6238 22:52:58.975229
6239 22:52:58.977763 RX Vref 0 -> 0, step: 1
6240 22:52:58.978263
6241 22:52:58.981192 RX Delay -359 -> 252, step: 8
6242 22:52:58.981741
6243 22:52:58.984108 Set Vref, RX VrefLevel [Byte0]: 47
6244 22:52:58.987463 [Byte1]: 49
6245 22:52:58.987925
6246 22:52:58.990991 Final RX Vref Byte 0 = 47 to rank0
6247 22:52:58.994278 Final RX Vref Byte 1 = 49 to rank0
6248 22:52:58.997525 Final RX Vref Byte 0 = 47 to rank1
6249 22:52:59.000878 Final RX Vref Byte 1 = 49 to rank1==
6250 22:52:59.004103 Dram Type= 6, Freq= 0, CH_0, rank 0
6251 22:52:59.007358 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6252 22:52:59.007822 ==
6253 22:52:59.010614 DQS Delay:
6254 22:52:59.011095 DQS0 = 52, DQS1 = 68
6255 22:52:59.014131 DQM Delay:
6256 22:52:59.014609 DQM0 = 9, DQM1 = 17
6257 22:52:59.017348 DQ Delay:
6258 22:52:59.017806 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6259 22:52:59.020657 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6260 22:52:59.023907 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6261 22:52:59.027102 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6262 22:52:59.027562
6263 22:52:59.027916
6264 22:52:59.037064 [DQSOSCAuto] RK0, (LSB)MR18= 0x9e9e, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6265 22:52:59.040414 CH0 RK0: MR19=C0C, MR18=9E9E
6266 22:52:59.044240 CH0_RK0: MR19=0xC0C, MR18=0x9E9E, DQSOSC=390, MR23=63, INC=388, DEC=258
6267 22:52:59.047063 ==
6268 22:52:59.050458 Dram Type= 6, Freq= 0, CH_0, rank 1
6269 22:52:59.053657 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6270 22:52:59.054323 ==
6271 22:52:59.056938 [Gating] SW mode calibration
6272 22:52:59.063524 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6273 22:52:59.067093 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6274 22:52:59.073434 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 22:52:59.076984 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 22:52:59.080464 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 22:52:59.086840 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6278 22:52:59.090084 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 22:52:59.093185 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 22:52:59.100263 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 22:52:59.103507 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6282 22:52:59.107243 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 22:52:59.110468 Total UI for P1: 0, mck2ui 16
6284 22:52:59.113319 best dqsien dly found for B0: ( 0, 10, 16)
6285 22:52:59.116648 Total UI for P1: 0, mck2ui 16
6286 22:52:59.119754 best dqsien dly found for B1: ( 0, 10, 24)
6287 22:52:59.123213 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6288 22:52:59.126691 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6289 22:52:59.127313
6290 22:52:59.133563 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6291 22:52:59.136317 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6292 22:52:59.139836 [Gating] SW calibration Done
6293 22:52:59.140352 ==
6294 22:52:59.143198 Dram Type= 6, Freq= 0, CH_0, rank 1
6295 22:52:59.146415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6296 22:52:59.146845 ==
6297 22:52:59.147171 RX Vref Scan: 0
6298 22:52:59.147473
6299 22:52:59.150010 RX Vref 0 -> 0, step: 1
6300 22:52:59.150466
6301 22:52:59.153089 RX Delay -410 -> 252, step: 16
6302 22:52:59.156446 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6303 22:52:59.163132 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6304 22:52:59.166806 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6305 22:52:59.169449 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6306 22:52:59.173079 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6307 22:52:59.179678 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6308 22:52:59.183015 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6309 22:52:59.186201 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6310 22:52:59.189713 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6311 22:52:59.196053 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6312 22:52:59.199488 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6313 22:52:59.202705 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6314 22:52:59.205973 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6315 22:52:59.212777 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6316 22:52:59.216238 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6317 22:52:59.219313 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6318 22:52:59.219727 ==
6319 22:52:59.222699 Dram Type= 6, Freq= 0, CH_0, rank 1
6320 22:52:59.226082 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6321 22:52:59.229724 ==
6322 22:52:59.230170 DQS Delay:
6323 22:52:59.230500 DQS0 = 43, DQS1 = 59
6324 22:52:59.232631 DQM Delay:
6325 22:52:59.233042 DQM0 = 7, DQM1 = 14
6326 22:52:59.236194 DQ Delay:
6327 22:52:59.236602 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6328 22:52:59.239262 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6329 22:52:59.242919 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6330 22:52:59.246079 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6331 22:52:59.246490
6332 22:52:59.246808
6333 22:52:59.247104 ==
6334 22:52:59.249517 Dram Type= 6, Freq= 0, CH_0, rank 1
6335 22:52:59.255951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6336 22:52:59.256366 ==
6337 22:52:59.256690
6338 22:52:59.257079
6339 22:52:59.257584 TX Vref Scan disable
6340 22:52:59.259403 == TX Byte 0 ==
6341 22:52:59.262772 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6342 22:52:59.266189 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6343 22:52:59.269393 == TX Byte 1 ==
6344 22:52:59.272752 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6345 22:52:59.276098 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6346 22:52:59.276683 ==
6347 22:52:59.279338 Dram Type= 6, Freq= 0, CH_0, rank 1
6348 22:52:59.286097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6349 22:52:59.286528 ==
6350 22:52:59.287048
6351 22:52:59.287373
6352 22:52:59.287798 TX Vref Scan disable
6353 22:52:59.289174 == TX Byte 0 ==
6354 22:52:59.292539 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6355 22:52:59.296225 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6356 22:52:59.299300 == TX Byte 1 ==
6357 22:52:59.302609 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6358 22:52:59.305964 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6359 22:52:59.306424
6360 22:52:59.309852 [DATLAT]
6361 22:52:59.310312 Freq=400, CH0 RK1
6362 22:52:59.310639
6363 22:52:59.312454 DATLAT Default: 0xd
6364 22:52:59.312870 0, 0xFFFF, sum = 0
6365 22:52:59.316011 1, 0xFFFF, sum = 0
6366 22:52:59.316427 2, 0xFFFF, sum = 0
6367 22:52:59.318916 3, 0xFFFF, sum = 0
6368 22:52:59.319497 4, 0xFFFF, sum = 0
6369 22:52:59.322572 5, 0xFFFF, sum = 0
6370 22:52:59.323017 6, 0xFFFF, sum = 0
6371 22:52:59.325891 7, 0xFFFF, sum = 0
6372 22:52:59.326345 8, 0xFFFF, sum = 0
6373 22:52:59.329466 9, 0xFFFF, sum = 0
6374 22:52:59.332247 10, 0xFFFF, sum = 0
6375 22:52:59.332834 11, 0xFFFF, sum = 0
6376 22:52:59.335657 12, 0x0, sum = 1
6377 22:52:59.336178 13, 0x0, sum = 2
6378 22:52:59.339082 14, 0x0, sum = 3
6379 22:52:59.339585 15, 0x0, sum = 4
6380 22:52:59.339913 best_step = 13
6381 22:52:59.340214
6382 22:52:59.341939 ==
6383 22:52:59.345471 Dram Type= 6, Freq= 0, CH_0, rank 1
6384 22:52:59.348769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6385 22:52:59.349443 ==
6386 22:52:59.349997 RX Vref Scan: 0
6387 22:52:59.350537
6388 22:52:59.351943 RX Vref 0 -> 0, step: 1
6389 22:52:59.352351
6390 22:52:59.355420 RX Delay -359 -> 252, step: 8
6391 22:52:59.362400 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6392 22:52:59.365798 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6393 22:52:59.369612 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6394 22:52:59.375679 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6395 22:52:59.378897 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6396 22:52:59.382218 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6397 22:52:59.385616 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6398 22:52:59.392464 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6399 22:52:59.395587 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6400 22:52:59.398661 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6401 22:52:59.402428 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6402 22:52:59.409243 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6403 22:52:59.412557 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6404 22:52:59.415246 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6405 22:52:59.418570 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6406 22:52:59.425489 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6407 22:52:59.426055 ==
6408 22:52:59.428506 Dram Type= 6, Freq= 0, CH_0, rank 1
6409 22:52:59.431892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6410 22:52:59.432470 ==
6411 22:52:59.432834 DQS Delay:
6412 22:52:59.435234 DQS0 = 52, DQS1 = 60
6413 22:52:59.435692 DQM Delay:
6414 22:52:59.438257 DQM0 = 10, DQM1 = 10
6415 22:52:59.438713 DQ Delay:
6416 22:52:59.441926 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6417 22:52:59.445515 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6418 22:52:59.448676 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6419 22:52:59.451761 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6420 22:52:59.452217
6421 22:52:59.452648
6422 22:52:59.458192 [DQSOSCAuto] RK1, (LSB)MR18= 0xcdcd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6423 22:52:59.461609 CH0 RK1: MR19=C0C, MR18=CDCD
6424 22:52:59.468221 CH0_RK1: MR19=0xC0C, MR18=0xCDCD, DQSOSC=384, MR23=63, INC=400, DEC=267
6425 22:52:59.471454 [RxdqsGatingPostProcess] freq 400
6426 22:52:59.477972 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6427 22:52:59.481467 Pre-setting of DQS Precalculation
6428 22:52:59.484956 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6429 22:52:59.485523 ==
6430 22:52:59.488267 Dram Type= 6, Freq= 0, CH_1, rank 0
6431 22:52:59.491190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6432 22:52:59.494555 ==
6433 22:52:59.498141 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6434 22:52:59.504531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6435 22:52:59.507563 [CA 0] Center 36 (8~64) winsize 57
6436 22:52:59.511200 [CA 1] Center 36 (8~64) winsize 57
6437 22:52:59.514219 [CA 2] Center 36 (8~64) winsize 57
6438 22:52:59.517699 [CA 3] Center 36 (8~64) winsize 57
6439 22:52:59.520996 [CA 4] Center 36 (8~64) winsize 57
6440 22:52:59.524107 [CA 5] Center 36 (8~64) winsize 57
6441 22:52:59.524533
6442 22:52:59.527952 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6443 22:52:59.528600
6444 22:52:59.530751 [CATrainingPosCal] consider 1 rank data
6445 22:52:59.534183 u2DelayCellTimex100 = 270/100 ps
6446 22:52:59.537749 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 22:52:59.540737 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 22:52:59.544097 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6449 22:52:59.547499 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6450 22:52:59.550342 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6451 22:52:59.553921 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6452 22:52:59.557169
6453 22:52:59.560498 CA PerBit enable=1, Macro0, CA PI delay=36
6454 22:52:59.560911
6455 22:52:59.563773 [CBTSetCACLKResult] CA Dly = 36
6456 22:52:59.564180 CS Dly: 1 (0~32)
6457 22:52:59.564504 ==
6458 22:52:59.566874 Dram Type= 6, Freq= 0, CH_1, rank 1
6459 22:52:59.570452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6460 22:52:59.570884 ==
6461 22:52:59.577157 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6462 22:52:59.583816 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6463 22:52:59.586900 [CA 0] Center 36 (8~64) winsize 57
6464 22:52:59.590364 [CA 1] Center 36 (8~64) winsize 57
6465 22:52:59.593645 [CA 2] Center 36 (8~64) winsize 57
6466 22:52:59.597134 [CA 3] Center 36 (8~64) winsize 57
6467 22:52:59.600427 [CA 4] Center 36 (8~64) winsize 57
6468 22:52:59.600951 [CA 5] Center 36 (8~64) winsize 57
6469 22:52:59.603553
6470 22:52:59.607056 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6471 22:52:59.607596
6472 22:52:59.610242 [CATrainingPosCal] consider 2 rank data
6473 22:52:59.613954 u2DelayCellTimex100 = 270/100 ps
6474 22:52:59.616906 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6475 22:52:59.620206 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6476 22:52:59.623889 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6477 22:52:59.627275 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6478 22:52:59.630747 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6479 22:52:59.633890 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6480 22:52:59.634484
6481 22:52:59.637226 CA PerBit enable=1, Macro0, CA PI delay=36
6482 22:52:59.637784
6483 22:52:59.640222 [CBTSetCACLKResult] CA Dly = 36
6484 22:52:59.643610 CS Dly: 1 (0~32)
6485 22:52:59.644072
6486 22:52:59.646788 ----->DramcWriteLeveling(PI) begin...
6487 22:52:59.647254 ==
6488 22:52:59.650218 Dram Type= 6, Freq= 0, CH_1, rank 0
6489 22:52:59.653718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6490 22:52:59.654215 ==
6491 22:52:59.656781 Write leveling (Byte 0): 32 => 0
6492 22:52:59.659975 Write leveling (Byte 1): 32 => 0
6493 22:52:59.663286 DramcWriteLeveling(PI) end<-----
6494 22:52:59.663747
6495 22:52:59.664108 ==
6496 22:52:59.666760 Dram Type= 6, Freq= 0, CH_1, rank 0
6497 22:52:59.670113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6498 22:52:59.670576 ==
6499 22:52:59.673797 [Gating] SW mode calibration
6500 22:52:59.680096 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6501 22:52:59.686564 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6502 22:52:59.689829 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6503 22:52:59.693815 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 22:52:59.700121 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 22:52:59.703211 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6506 22:52:59.706577 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 22:52:59.713351 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 22:52:59.716345 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 22:52:59.719951 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6510 22:52:59.726571 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 22:52:59.729472 Total UI for P1: 0, mck2ui 16
6512 22:52:59.733297 best dqsien dly found for B0: ( 0, 10, 16)
6513 22:52:59.733859 Total UI for P1: 0, mck2ui 16
6514 22:52:59.739961 best dqsien dly found for B1: ( 0, 10, 16)
6515 22:52:59.743104 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6516 22:52:59.746192 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6517 22:52:59.746652
6518 22:52:59.749315 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6519 22:52:59.752857 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6520 22:52:59.756110 [Gating] SW calibration Done
6521 22:52:59.756569 ==
6522 22:52:59.759698 Dram Type= 6, Freq= 0, CH_1, rank 0
6523 22:52:59.762670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6524 22:52:59.763186 ==
6525 22:52:59.766313 RX Vref Scan: 0
6526 22:52:59.766882
6527 22:52:59.769382 RX Vref 0 -> 0, step: 1
6528 22:52:59.769947
6529 22:52:59.770340 RX Delay -410 -> 252, step: 16
6530 22:52:59.776516 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6531 22:52:59.779505 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6532 22:52:59.782617 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6533 22:52:59.786388 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6534 22:52:59.792756 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6535 22:52:59.795913 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6536 22:52:59.799173 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6537 22:52:59.802960 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6538 22:52:59.809429 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6539 22:52:59.812476 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6540 22:52:59.815868 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6541 22:52:59.822823 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6542 22:52:59.825924 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6543 22:52:59.829314 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6544 22:52:59.832568 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6545 22:52:59.839220 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6546 22:52:59.839783 ==
6547 22:52:59.842563 Dram Type= 6, Freq= 0, CH_1, rank 0
6548 22:52:59.846136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6549 22:52:59.846705 ==
6550 22:52:59.847073 DQS Delay:
6551 22:52:59.849174 DQS0 = 43, DQS1 = 59
6552 22:52:59.849753 DQM Delay:
6553 22:52:59.852356 DQM0 = 6, DQM1 = 16
6554 22:52:59.852922 DQ Delay:
6555 22:52:59.855502 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6556 22:52:59.858641 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6557 22:52:59.862220 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6558 22:52:59.865470 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6559 22:52:59.866082
6560 22:52:59.866460
6561 22:52:59.866797 ==
6562 22:52:59.868895 Dram Type= 6, Freq= 0, CH_1, rank 0
6563 22:52:59.872515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6564 22:52:59.873084 ==
6565 22:52:59.873448
6566 22:52:59.873781
6567 22:52:59.875393 TX Vref Scan disable
6568 22:52:59.878760 == TX Byte 0 ==
6569 22:52:59.882230 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6570 22:52:59.885280 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6571 22:52:59.888768 == TX Byte 1 ==
6572 22:52:59.892197 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6573 22:52:59.895542 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6574 22:52:59.896106 ==
6575 22:52:59.898732 Dram Type= 6, Freq= 0, CH_1, rank 0
6576 22:52:59.902058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6577 22:52:59.905356 ==
6578 22:52:59.905913
6579 22:52:59.906334
6580 22:52:59.906675 TX Vref Scan disable
6581 22:52:59.908353 == TX Byte 0 ==
6582 22:52:59.911891 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6583 22:52:59.915404 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6584 22:52:59.918164 == TX Byte 1 ==
6585 22:52:59.921605 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6586 22:52:59.925149 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6587 22:52:59.925719
6588 22:52:59.928279 [DATLAT]
6589 22:52:59.928828 Freq=400, CH1 RK0
6590 22:52:59.929191
6591 22:52:59.932419 DATLAT Default: 0xf
6592 22:52:59.932980 0, 0xFFFF, sum = 0
6593 22:52:59.935023 1, 0xFFFF, sum = 0
6594 22:52:59.935794 2, 0xFFFF, sum = 0
6595 22:52:59.938237 3, 0xFFFF, sum = 0
6596 22:52:59.938703 4, 0xFFFF, sum = 0
6597 22:52:59.941548 5, 0xFFFF, sum = 0
6598 22:52:59.942164 6, 0xFFFF, sum = 0
6599 22:52:59.945096 7, 0xFFFF, sum = 0
6600 22:52:59.945662 8, 0xFFFF, sum = 0
6601 22:52:59.948527 9, 0xFFFF, sum = 0
6602 22:52:59.949094 10, 0xFFFF, sum = 0
6603 22:52:59.951337 11, 0xFFFF, sum = 0
6604 22:52:59.951804 12, 0x0, sum = 1
6605 22:52:59.954695 13, 0x0, sum = 2
6606 22:52:59.955158 14, 0x0, sum = 3
6607 22:52:59.958127 15, 0x0, sum = 4
6608 22:52:59.958666 best_step = 13
6609 22:52:59.959029
6610 22:52:59.959364 ==
6611 22:52:59.961557 Dram Type= 6, Freq= 0, CH_1, rank 0
6612 22:52:59.968396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6613 22:52:59.968957 ==
6614 22:52:59.969325 RX Vref Scan: 1
6615 22:52:59.969661
6616 22:52:59.971510 RX Vref 0 -> 0, step: 1
6617 22:52:59.972067
6618 22:52:59.974621 RX Delay -359 -> 252, step: 8
6619 22:52:59.975082
6620 22:52:59.978217 Set Vref, RX VrefLevel [Byte0]: 52
6621 22:52:59.981370 [Byte1]: 48
6622 22:52:59.984423
6623 22:52:59.984882 Final RX Vref Byte 0 = 52 to rank0
6624 22:52:59.988185 Final RX Vref Byte 1 = 48 to rank0
6625 22:52:59.991426 Final RX Vref Byte 0 = 52 to rank1
6626 22:52:59.994854 Final RX Vref Byte 1 = 48 to rank1==
6627 22:52:59.998082 Dram Type= 6, Freq= 0, CH_1, rank 0
6628 22:53:00.004722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6629 22:53:00.005285 ==
6630 22:53:00.005653 DQS Delay:
6631 22:53:00.005990 DQS0 = 48, DQS1 = 64
6632 22:53:00.007893 DQM Delay:
6633 22:53:00.008349 DQM0 = 9, DQM1 = 16
6634 22:53:00.011164 DQ Delay:
6635 22:53:00.011622 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =8
6636 22:53:00.014736 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6637 22:53:00.017787 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6638 22:53:00.021413 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6639 22:53:00.021874
6640 22:53:00.022287
6641 22:53:00.030936 [DQSOSCAuto] RK0, (LSB)MR18= 0xdddd, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6642 22:53:00.034572 CH1 RK0: MR19=C0C, MR18=DDDD
6643 22:53:00.040930 CH1_RK0: MR19=0xC0C, MR18=0xDDDD, DQSOSC=382, MR23=63, INC=404, DEC=269
6644 22:53:00.041490 ==
6645 22:53:00.044248 Dram Type= 6, Freq= 0, CH_1, rank 1
6646 22:53:00.047508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6647 22:53:00.048070 ==
6648 22:53:00.050810 [Gating] SW mode calibration
6649 22:53:00.057436 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6650 22:53:00.060710 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6651 22:53:00.067393 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6652 22:53:00.071002 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6653 22:53:00.074382 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 22:53:00.080830 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6655 22:53:00.084130 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 22:53:00.087554 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 22:53:00.094183 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 22:53:00.097417 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6659 22:53:00.100748 Total UI for P1: 0, mck2ui 16
6660 22:53:00.103997 best dqsien dly found for B0: ( 0, 10, 8)
6661 22:53:00.107417 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 22:53:00.110811 Total UI for P1: 0, mck2ui 16
6663 22:53:00.113922 best dqsien dly found for B1: ( 0, 10, 16)
6664 22:53:00.117247 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6665 22:53:00.120398 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6666 22:53:00.120860
6667 22:53:00.127117 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6668 22:53:00.130738 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6669 22:53:00.134414 [Gating] SW calibration Done
6670 22:53:00.134873 ==
6671 22:53:00.137119 Dram Type= 6, Freq= 0, CH_1, rank 1
6672 22:53:00.140836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6673 22:53:00.141406 ==
6674 22:53:00.141773 RX Vref Scan: 0
6675 22:53:00.142150
6676 22:53:00.143630 RX Vref 0 -> 0, step: 1
6677 22:53:00.144092
6678 22:53:00.147105 RX Delay -410 -> 252, step: 16
6679 22:53:00.150651 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6680 22:53:00.157553 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6681 22:53:00.160285 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6682 22:53:00.163875 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6683 22:53:00.166961 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6684 22:53:00.173786 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6685 22:53:00.177491 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6686 22:53:00.180358 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6687 22:53:00.183684 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6688 22:53:00.190425 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6689 22:53:00.193538 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6690 22:53:00.196975 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6691 22:53:00.200311 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6692 22:53:00.206939 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6693 22:53:00.210086 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6694 22:53:00.213172 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6695 22:53:00.213636 ==
6696 22:53:00.216672 Dram Type= 6, Freq= 0, CH_1, rank 1
6697 22:53:00.223566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6698 22:53:00.224133 ==
6699 22:53:00.224500 DQS Delay:
6700 22:53:00.226781 DQS0 = 35, DQS1 = 59
6701 22:53:00.227341 DQM Delay:
6702 22:53:00.227706 DQM0 = 4, DQM1 = 18
6703 22:53:00.230091 DQ Delay:
6704 22:53:00.233437 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6705 22:53:00.233895 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6706 22:53:00.236659 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6707 22:53:00.240362 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6708 22:53:00.240923
6709 22:53:00.241283
6710 22:53:00.243365 ==
6711 22:53:00.243824 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 22:53:00.249924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6713 22:53:00.250735 ==
6714 22:53:00.251289
6715 22:53:00.251792
6716 22:53:00.253191 TX Vref Scan disable
6717 22:53:00.253727 == TX Byte 0 ==
6718 22:53:00.256762 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6719 22:53:00.262973 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6720 22:53:00.263438 == TX Byte 1 ==
6721 22:53:00.266551 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6722 22:53:00.269767 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6723 22:53:00.272892 ==
6724 22:53:00.276540 Dram Type= 6, Freq= 0, CH_1, rank 1
6725 22:53:00.280060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6726 22:53:00.280627 ==
6727 22:53:00.280996
6728 22:53:00.281331
6729 22:53:00.283096 TX Vref Scan disable
6730 22:53:00.283555 == TX Byte 0 ==
6731 22:53:00.286245 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6732 22:53:00.293032 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6733 22:53:00.293618 == TX Byte 1 ==
6734 22:53:00.296686 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6735 22:53:00.302980 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6736 22:53:00.303548
6737 22:53:00.303912 [DATLAT]
6738 22:53:00.304246 Freq=400, CH1 RK1
6739 22:53:00.304569
6740 22:53:00.306135 DATLAT Default: 0xd
6741 22:53:00.306596 0, 0xFFFF, sum = 0
6742 22:53:00.309422 1, 0xFFFF, sum = 0
6743 22:53:00.309886 2, 0xFFFF, sum = 0
6744 22:53:00.312889 3, 0xFFFF, sum = 0
6745 22:53:00.313356 4, 0xFFFF, sum = 0
6746 22:53:00.316200 5, 0xFFFF, sum = 0
6747 22:53:00.319511 6, 0xFFFF, sum = 0
6748 22:53:00.319975 7, 0xFFFF, sum = 0
6749 22:53:00.323269 8, 0xFFFF, sum = 0
6750 22:53:00.323842 9, 0xFFFF, sum = 0
6751 22:53:00.326410 10, 0xFFFF, sum = 0
6752 22:53:00.326982 11, 0xFFFF, sum = 0
6753 22:53:00.329690 12, 0x0, sum = 1
6754 22:53:00.330304 13, 0x0, sum = 2
6755 22:53:00.333156 14, 0x0, sum = 3
6756 22:53:00.333735 15, 0x0, sum = 4
6757 22:53:00.334147 best_step = 13
6758 22:53:00.334492
6759 22:53:00.336437 ==
6760 22:53:00.340208 Dram Type= 6, Freq= 0, CH_1, rank 1
6761 22:53:00.342871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6762 22:53:00.343333 ==
6763 22:53:00.343698 RX Vref Scan: 0
6764 22:53:00.344035
6765 22:53:00.346650 RX Vref 0 -> 0, step: 1
6766 22:53:00.347233
6767 22:53:00.349699 RX Delay -359 -> 252, step: 8
6768 22:53:00.356476 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6769 22:53:00.359871 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6770 22:53:00.363683 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6771 22:53:00.369611 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6772 22:53:00.373343 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6773 22:53:00.376361 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6774 22:53:00.379679 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6775 22:53:00.385997 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6776 22:53:00.389272 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6777 22:53:00.392501 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6778 22:53:00.396406 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6779 22:53:00.402577 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6780 22:53:00.405806 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6781 22:53:00.409802 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6782 22:53:00.412492 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6783 22:53:00.419178 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6784 22:53:00.419594 ==
6785 22:53:00.422620 Dram Type= 6, Freq= 0, CH_1, rank 1
6786 22:53:00.425552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6787 22:53:00.425970 ==
6788 22:53:00.426331 DQS Delay:
6789 22:53:00.429264 DQS0 = 48, DQS1 = 64
6790 22:53:00.429781 DQM Delay:
6791 22:53:00.433106 DQM0 = 9, DQM1 = 16
6792 22:53:00.433627 DQ Delay:
6793 22:53:00.435432 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6794 22:53:00.438933 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6795 22:53:00.442431 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6796 22:53:00.445783 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6797 22:53:00.446282
6798 22:53:00.446642
6799 22:53:00.455435 [DQSOSCAuto] RK1, (LSB)MR18= 0xa0a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6800 22:53:00.455898 CH1 RK1: MR19=C0C, MR18=A0A0
6801 22:53:00.461868 CH1_RK1: MR19=0xC0C, MR18=0xA0A0, DQSOSC=389, MR23=63, INC=390, DEC=260
6802 22:53:00.465060 [RxdqsGatingPostProcess] freq 400
6803 22:53:00.471616 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6804 22:53:00.475238 Pre-setting of DQS Precalculation
6805 22:53:00.478508 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6806 22:53:00.485438 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6807 22:53:00.495002 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6808 22:53:00.495556
6809 22:53:00.495982
6810 22:53:00.498267 [Calibration Summary] 800 Mbps
6811 22:53:00.498730 CH 0, Rank 0
6812 22:53:00.501632 SW Impedance : PASS
6813 22:53:00.502346 DUTY Scan : NO K
6814 22:53:00.504951 ZQ Calibration : PASS
6815 22:53:00.505440 Jitter Meter : NO K
6816 22:53:00.508514 CBT Training : PASS
6817 22:53:00.511454 Write leveling : PASS
6818 22:53:00.511911 RX DQS gating : PASS
6819 22:53:00.514822 RX DQ/DQS(RDDQC) : PASS
6820 22:53:00.518136 TX DQ/DQS : PASS
6821 22:53:00.518602 RX DATLAT : PASS
6822 22:53:00.521179 RX DQ/DQS(Engine): PASS
6823 22:53:00.524660 TX OE : NO K
6824 22:53:00.525224 All Pass.
6825 22:53:00.525589
6826 22:53:00.525918 CH 0, Rank 1
6827 22:53:00.528203 SW Impedance : PASS
6828 22:53:00.531398 DUTY Scan : NO K
6829 22:53:00.531963 ZQ Calibration : PASS
6830 22:53:00.534706 Jitter Meter : NO K
6831 22:53:00.538043 CBT Training : PASS
6832 22:53:00.538611 Write leveling : NO K
6833 22:53:00.541443 RX DQS gating : PASS
6834 22:53:00.544970 RX DQ/DQS(RDDQC) : PASS
6835 22:53:00.545533 TX DQ/DQS : PASS
6836 22:53:00.548043 RX DATLAT : PASS
6837 22:53:00.551321 RX DQ/DQS(Engine): PASS
6838 22:53:00.551893 TX OE : NO K
6839 22:53:00.554633 All Pass.
6840 22:53:00.555107
6841 22:53:00.555557 CH 1, Rank 0
6842 22:53:00.557897 SW Impedance : PASS
6843 22:53:00.558522 DUTY Scan : NO K
6844 22:53:00.560931 ZQ Calibration : PASS
6845 22:53:00.564149 Jitter Meter : NO K
6846 22:53:00.564610 CBT Training : PASS
6847 22:53:00.567590 Write leveling : PASS
6848 22:53:00.570791 RX DQS gating : PASS
6849 22:53:00.571250 RX DQ/DQS(RDDQC) : PASS
6850 22:53:00.574162 TX DQ/DQS : PASS
6851 22:53:00.574573 RX DATLAT : PASS
6852 22:53:00.577533 RX DQ/DQS(Engine): PASS
6853 22:53:00.580997 TX OE : NO K
6854 22:53:00.581567 All Pass.
6855 22:53:00.581932
6856 22:53:00.582320 CH 1, Rank 1
6857 22:53:00.584179 SW Impedance : PASS
6858 22:53:00.587776 DUTY Scan : NO K
6859 22:53:00.588338 ZQ Calibration : PASS
6860 22:53:00.590956 Jitter Meter : NO K
6861 22:53:00.594207 CBT Training : PASS
6862 22:53:00.594777 Write leveling : NO K
6863 22:53:00.597415 RX DQS gating : PASS
6864 22:53:00.601062 RX DQ/DQS(RDDQC) : PASS
6865 22:53:00.601632 TX DQ/DQS : PASS
6866 22:53:00.604291 RX DATLAT : PASS
6867 22:53:00.607651 RX DQ/DQS(Engine): PASS
6868 22:53:00.608110 TX OE : NO K
6869 22:53:00.610742 All Pass.
6870 22:53:00.611345
6871 22:53:00.611714 DramC Write-DBI off
6872 22:53:00.614208 PER_BANK_REFRESH: Hybrid Mode
6873 22:53:00.614768 TX_TRACKING: ON
6874 22:53:00.624083 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6875 22:53:00.627289 [FAST_K] Save calibration result to emmc
6876 22:53:00.630785 dramc_set_vcore_voltage set vcore to 725000
6877 22:53:00.634118 Read voltage for 1600, 0
6878 22:53:00.634682 Vio18 = 0
6879 22:53:00.637084 Vcore = 725000
6880 22:53:00.637649 Vdram = 0
6881 22:53:00.638010 Vddq = 0
6882 22:53:00.640472 Vmddr = 0
6883 22:53:00.643781 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6884 22:53:00.650666 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6885 22:53:00.651235 MEM_TYPE=3, freq_sel=13
6886 22:53:00.653454 sv_algorithm_assistance_LP4_3733
6887 22:53:00.660057 ============ PULL DRAM RESETB DOWN ============
6888 22:53:00.663566 ========== PULL DRAM RESETB DOWN end =========
6889 22:53:00.666942 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6890 22:53:00.670059 ===================================
6891 22:53:00.673592 LPDDR4 DRAM CONFIGURATION
6892 22:53:00.676526 ===================================
6893 22:53:00.680103 EX_ROW_EN[0] = 0x0
6894 22:53:00.680665 EX_ROW_EN[1] = 0x0
6895 22:53:00.683557 LP4Y_EN = 0x0
6896 22:53:00.684113 WORK_FSP = 0x1
6897 22:53:00.686570 WL = 0x5
6898 22:53:00.687026 RL = 0x5
6899 22:53:00.690277 BL = 0x2
6900 22:53:00.690856 RPST = 0x0
6901 22:53:00.693666 RD_PRE = 0x0
6902 22:53:00.694276 WR_PRE = 0x1
6903 22:53:00.696750 WR_PST = 0x1
6904 22:53:00.697321 DBI_WR = 0x0
6905 22:53:00.700500 DBI_RD = 0x0
6906 22:53:00.701067 OTF = 0x1
6907 22:53:00.703603 ===================================
6908 22:53:00.706738 ===================================
6909 22:53:00.710060 ANA top config
6910 22:53:00.713018 ===================================
6911 22:53:00.716589 DLL_ASYNC_EN = 0
6912 22:53:00.717049 ALL_SLAVE_EN = 0
6913 22:53:00.719745 NEW_RANK_MODE = 1
6914 22:53:00.722895 DLL_IDLE_MODE = 1
6915 22:53:00.726301 LP45_APHY_COMB_EN = 1
6916 22:53:00.726861 TX_ODT_DIS = 0
6917 22:53:00.729667 NEW_8X_MODE = 1
6918 22:53:00.732999 ===================================
6919 22:53:00.736217 ===================================
6920 22:53:00.739292 data_rate = 3200
6921 22:53:00.742623 CKR = 1
6922 22:53:00.745915 DQ_P2S_RATIO = 8
6923 22:53:00.749468 ===================================
6924 22:53:00.752404 CA_P2S_RATIO = 8
6925 22:53:00.755716 DQ_CA_OPEN = 0
6926 22:53:00.756199 DQ_SEMI_OPEN = 0
6927 22:53:00.759411 CA_SEMI_OPEN = 0
6928 22:53:00.762628 CA_FULL_RATE = 0
6929 22:53:00.765519 DQ_CKDIV4_EN = 0
6930 22:53:00.768805 CA_CKDIV4_EN = 0
6931 22:53:00.772151 CA_PREDIV_EN = 0
6932 22:53:00.772697 PH8_DLY = 12
6933 22:53:00.775806 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6934 22:53:00.779676 DQ_AAMCK_DIV = 4
6935 22:53:00.782247 CA_AAMCK_DIV = 4
6936 22:53:00.785614 CA_ADMCK_DIV = 4
6937 22:53:00.789087 DQ_TRACK_CA_EN = 0
6938 22:53:00.792394 CA_PICK = 1600
6939 22:53:00.792956 CA_MCKIO = 1600
6940 22:53:00.795945 MCKIO_SEMI = 0
6941 22:53:00.798728 PLL_FREQ = 3068
6942 22:53:00.802309 DQ_UI_PI_RATIO = 32
6943 22:53:00.805382 CA_UI_PI_RATIO = 0
6944 22:53:00.808727 ===================================
6945 22:53:00.812075 ===================================
6946 22:53:00.815259 memory_type:LPDDR4
6947 22:53:00.815822 GP_NUM : 10
6948 22:53:00.818396 SRAM_EN : 1
6949 22:53:00.818853 MD32_EN : 0
6950 22:53:00.821572 ===================================
6951 22:53:00.825260 [ANA_INIT] >>>>>>>>>>>>>>
6952 22:53:00.828773 <<<<<< [CONFIGURE PHASE]: ANA_TX
6953 22:53:00.831962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6954 22:53:00.835220 ===================================
6955 22:53:00.838818 data_rate = 3200,PCW = 0X7600
6956 22:53:00.841922 ===================================
6957 22:53:00.844987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6958 22:53:00.851827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6959 22:53:00.855122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6960 22:53:00.861507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6961 22:53:00.864520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6962 22:53:00.868248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6963 22:53:00.868819 [ANA_INIT] flow start
6964 22:53:00.871614 [ANA_INIT] PLL >>>>>>>>
6965 22:53:00.874873 [ANA_INIT] PLL <<<<<<<<
6966 22:53:00.875334 [ANA_INIT] MIDPI >>>>>>>>
6967 22:53:00.877814 [ANA_INIT] MIDPI <<<<<<<<
6968 22:53:00.881418 [ANA_INIT] DLL >>>>>>>>
6969 22:53:00.884667 [ANA_INIT] DLL <<<<<<<<
6970 22:53:00.885235 [ANA_INIT] flow end
6971 22:53:00.888082 ============ LP4 DIFF to SE enter ============
6972 22:53:00.894795 ============ LP4 DIFF to SE exit ============
6973 22:53:00.895360 [ANA_INIT] <<<<<<<<<<<<<
6974 22:53:00.897772 [Flow] Enable top DCM control >>>>>
6975 22:53:00.901043 [Flow] Enable top DCM control <<<<<
6976 22:53:00.904377 Enable DLL master slave shuffle
6977 22:53:00.910962 ==============================================================
6978 22:53:00.911506 Gating Mode config
6979 22:53:00.917968 ==============================================================
6980 22:53:00.921152 Config description:
6981 22:53:00.930738 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6982 22:53:00.937724 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6983 22:53:00.941118 SELPH_MODE 0: By rank 1: By Phase
6984 22:53:00.947713 ==============================================================
6985 22:53:00.950617 GAT_TRACK_EN = 1
6986 22:53:00.951173 RX_GATING_MODE = 2
6987 22:53:00.953971 RX_GATING_TRACK_MODE = 2
6988 22:53:00.957231 SELPH_MODE = 1
6989 22:53:00.960449 PICG_EARLY_EN = 1
6990 22:53:00.963804 VALID_LAT_VALUE = 1
6991 22:53:00.970277 ==============================================================
6992 22:53:00.974279 Enter into Gating configuration >>>>
6993 22:53:00.977584 Exit from Gating configuration <<<<
6994 22:53:00.980548 Enter into DVFS_PRE_config >>>>>
6995 22:53:00.990654 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6996 22:53:00.993807 Exit from DVFS_PRE_config <<<<<
6997 22:53:00.996799 Enter into PICG configuration >>>>
6998 22:53:01.000473 Exit from PICG configuration <<<<
6999 22:53:01.003518 [RX_INPUT] configuration >>>>>
7000 22:53:01.006962 [RX_INPUT] configuration <<<<<
7001 22:53:01.010293 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7002 22:53:01.016888 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7003 22:53:01.023509 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7004 22:53:01.030048 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7005 22:53:01.033617 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7006 22:53:01.039830 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7007 22:53:01.043459 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7008 22:53:01.049789 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7009 22:53:01.053393 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7010 22:53:01.056263 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7011 22:53:01.059801 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7012 22:53:01.066096 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7013 22:53:01.069452 ===================================
7014 22:53:01.073095 LPDDR4 DRAM CONFIGURATION
7015 22:53:01.076428 ===================================
7016 22:53:01.076987 EX_ROW_EN[0] = 0x0
7017 22:53:01.079748 EX_ROW_EN[1] = 0x0
7018 22:53:01.080306 LP4Y_EN = 0x0
7019 22:53:01.082903 WORK_FSP = 0x1
7020 22:53:01.083367 WL = 0x5
7021 22:53:01.086141 RL = 0x5
7022 22:53:01.086605 BL = 0x2
7023 22:53:01.089629 RPST = 0x0
7024 22:53:01.090242 RD_PRE = 0x0
7025 22:53:01.092862 WR_PRE = 0x1
7026 22:53:01.093416 WR_PST = 0x1
7027 22:53:01.096137 DBI_WR = 0x0
7028 22:53:01.100033 DBI_RD = 0x0
7029 22:53:01.100596 OTF = 0x1
7030 22:53:01.102742 ===================================
7031 22:53:01.106068 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7032 22:53:01.109327 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7033 22:53:01.115927 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7034 22:53:01.119182 ===================================
7035 22:53:01.122566 LPDDR4 DRAM CONFIGURATION
7036 22:53:01.125917 ===================================
7037 22:53:01.126547 EX_ROW_EN[0] = 0x10
7038 22:53:01.129248 EX_ROW_EN[1] = 0x0
7039 22:53:01.129843 LP4Y_EN = 0x0
7040 22:53:01.132630 WORK_FSP = 0x1
7041 22:53:01.133199 WL = 0x5
7042 22:53:01.135946 RL = 0x5
7043 22:53:01.136509 BL = 0x2
7044 22:53:01.138861 RPST = 0x0
7045 22:53:01.139323 RD_PRE = 0x0
7046 22:53:01.142485 WR_PRE = 0x1
7047 22:53:01.142948 WR_PST = 0x1
7048 22:53:01.145811 DBI_WR = 0x0
7049 22:53:01.149088 DBI_RD = 0x0
7050 22:53:01.149655 OTF = 0x1
7051 22:53:01.152100 ===================================
7052 22:53:01.158753 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7053 22:53:01.159221 ==
7054 22:53:01.162219 Dram Type= 6, Freq= 0, CH_0, rank 0
7055 22:53:01.165654 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7056 22:53:01.166333 ==
7057 22:53:01.168748 [Duty_Offset_Calibration]
7058 22:53:01.169210 B0:0 B1:2 CA:1
7059 22:53:01.169584
7060 22:53:01.172425 [DutyScan_Calibration_Flow] k_type=0
7061 22:53:01.183579
7062 22:53:01.184142 ==CLK 0==
7063 22:53:01.186990 Final CLK duty delay cell = 0
7064 22:53:01.190186 [0] MAX Duty = 5187%(X100), DQS PI = 24
7065 22:53:01.193523 [0] MIN Duty = 4938%(X100), DQS PI = 54
7066 22:53:01.196669 [0] AVG Duty = 5062%(X100)
7067 22:53:01.197229
7068 22:53:01.200481 CH0 CLK Duty spec in!! Max-Min= 249%
7069 22:53:01.203463 [DutyScan_Calibration_Flow] ====Done====
7070 22:53:01.203927
7071 22:53:01.206407 [DutyScan_Calibration_Flow] k_type=1
7072 22:53:01.223509
7073 22:53:01.224057 ==DQS 0 ==
7074 22:53:01.227233 Final DQS duty delay cell = 0
7075 22:53:01.230126 [0] MAX Duty = 5125%(X100), DQS PI = 26
7076 22:53:01.233644 [0] MIN Duty = 5000%(X100), DQS PI = 8
7077 22:53:01.236731 [0] AVG Duty = 5062%(X100)
7078 22:53:01.237287
7079 22:53:01.237652 ==DQS 1 ==
7080 22:53:01.240119 Final DQS duty delay cell = 0
7081 22:53:01.243380 [0] MAX Duty = 5031%(X100), DQS PI = 2
7082 22:53:01.246979 [0] MIN Duty = 4876%(X100), DQS PI = 18
7083 22:53:01.250247 [0] AVG Duty = 4953%(X100)
7084 22:53:01.250827
7085 22:53:01.253434 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7086 22:53:01.254004
7087 22:53:01.256415 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7088 22:53:01.259838 [DutyScan_Calibration_Flow] ====Done====
7089 22:53:01.260303
7090 22:53:01.263008 [DutyScan_Calibration_Flow] k_type=3
7091 22:53:01.280833
7092 22:53:01.281390 ==DQM 0 ==
7093 22:53:01.283649 Final DQM duty delay cell = 0
7094 22:53:01.287176 [0] MAX Duty = 5187%(X100), DQS PI = 24
7095 22:53:01.290630 [0] MIN Duty = 4907%(X100), DQS PI = 42
7096 22:53:01.293724 [0] AVG Duty = 5047%(X100)
7097 22:53:01.294393
7098 22:53:01.294946 ==DQM 1 ==
7099 22:53:01.296988 Final DQM duty delay cell = 0
7100 22:53:01.300381 [0] MAX Duty = 5031%(X100), DQS PI = 50
7101 22:53:01.303746 [0] MIN Duty = 4782%(X100), DQS PI = 16
7102 22:53:01.307190 [0] AVG Duty = 4906%(X100)
7103 22:53:01.307653
7104 22:53:01.310422 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7105 22:53:01.310957
7106 22:53:01.314010 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7107 22:53:01.317067 [DutyScan_Calibration_Flow] ====Done====
7108 22:53:01.317539
7109 22:53:01.320486 [DutyScan_Calibration_Flow] k_type=2
7110 22:53:01.337069
7111 22:53:01.337633 ==DQ 0 ==
7112 22:53:01.340422 Final DQ duty delay cell = 0
7113 22:53:01.343590 [0] MAX Duty = 5218%(X100), DQS PI = 18
7114 22:53:01.346737 [0] MIN Duty = 4969%(X100), DQS PI = 56
7115 22:53:01.347201 [0] AVG Duty = 5093%(X100)
7116 22:53:01.349943
7117 22:53:01.350421 ==DQ 1 ==
7118 22:53:01.353406 Final DQ duty delay cell = -4
7119 22:53:01.356758 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7120 22:53:01.360025 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7121 22:53:01.363260 [-4] AVG Duty = 4969%(X100)
7122 22:53:01.363786
7123 22:53:01.366614 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7124 22:53:01.367090
7125 22:53:01.370163 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7126 22:53:01.373133 [DutyScan_Calibration_Flow] ====Done====
7127 22:53:01.373607 ==
7128 22:53:01.376565 Dram Type= 6, Freq= 0, CH_1, rank 0
7129 22:53:01.379952 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7130 22:53:01.380507 ==
7131 22:53:01.382935 [Duty_Offset_Calibration]
7132 22:53:01.383391 B0:0 B1:5 CA:-5
7133 22:53:01.383786
7134 22:53:01.386381 [DutyScan_Calibration_Flow] k_type=0
7135 22:53:01.397445
7136 22:53:01.397970 ==CLK 0==
7137 22:53:01.400907 Final CLK duty delay cell = 0
7138 22:53:01.404095 [0] MAX Duty = 5156%(X100), DQS PI = 22
7139 22:53:01.407609 [0] MIN Duty = 4906%(X100), DQS PI = 50
7140 22:53:01.408140 [0] AVG Duty = 5031%(X100)
7141 22:53:01.410746
7142 22:53:01.413871 CH1 CLK Duty spec in!! Max-Min= 250%
7143 22:53:01.417735 [DutyScan_Calibration_Flow] ====Done====
7144 22:53:01.418399
7145 22:53:01.420691 [DutyScan_Calibration_Flow] k_type=1
7146 22:53:01.436439
7147 22:53:01.436998 ==DQS 0 ==
7148 22:53:01.439520 Final DQS duty delay cell = 0
7149 22:53:01.443140 [0] MAX Duty = 5187%(X100), DQS PI = 18
7150 22:53:01.446642 [0] MIN Duty = 4876%(X100), DQS PI = 42
7151 22:53:01.449693 [0] AVG Duty = 5031%(X100)
7152 22:53:01.450215
7153 22:53:01.450610 ==DQS 1 ==
7154 22:53:01.452959 Final DQS duty delay cell = -4
7155 22:53:01.455950 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7156 22:53:01.459375 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7157 22:53:01.463388 [-4] AVG Duty = 4922%(X100)
7158 22:53:01.463954
7159 22:53:01.466392 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7160 22:53:01.466866
7161 22:53:01.469556 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7162 22:53:01.472789 [DutyScan_Calibration_Flow] ====Done====
7163 22:53:01.473264
7164 22:53:01.476146 [DutyScan_Calibration_Flow] k_type=3
7165 22:53:01.492041
7166 22:53:01.492555 ==DQM 0 ==
7167 22:53:01.495389 Final DQM duty delay cell = -4
7168 22:53:01.498783 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7169 22:53:01.501930 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7170 22:53:01.505240 [-4] AVG Duty = 4937%(X100)
7171 22:53:01.505826
7172 22:53:01.506311 ==DQM 1 ==
7173 22:53:01.508434 Final DQM duty delay cell = -4
7174 22:53:01.511982 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7175 22:53:01.514833 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7176 22:53:01.518284 [-4] AVG Duty = 4984%(X100)
7177 22:53:01.518837
7178 22:53:01.521478 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7179 22:53:01.521892
7180 22:53:01.524877 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7181 22:53:01.528756 [DutyScan_Calibration_Flow] ====Done====
7182 22:53:01.529271
7183 22:53:01.531471 [DutyScan_Calibration_Flow] k_type=2
7184 22:53:01.549472
7185 22:53:01.549953 ==DQ 0 ==
7186 22:53:01.553105 Final DQ duty delay cell = 0
7187 22:53:01.555971 [0] MAX Duty = 5093%(X100), DQS PI = 18
7188 22:53:01.559747 [0] MIN Duty = 4938%(X100), DQS PI = 46
7189 22:53:01.560278 [0] AVG Duty = 5015%(X100)
7190 22:53:01.562492
7191 22:53:01.562905 ==DQ 1 ==
7192 22:53:01.566014 Final DQ duty delay cell = 0
7193 22:53:01.569407 [0] MAX Duty = 5062%(X100), DQS PI = 6
7194 22:53:01.572583 [0] MIN Duty = 4876%(X100), DQS PI = 26
7195 22:53:01.573079 [0] AVG Duty = 4969%(X100)
7196 22:53:01.575974
7197 22:53:01.579194 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7198 22:53:01.579610
7199 22:53:01.582333 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7200 22:53:01.585897 [DutyScan_Calibration_Flow] ====Done====
7201 22:53:01.589305 nWR fixed to 30
7202 22:53:01.589788 [ModeRegInit_LP4] CH0 RK0
7203 22:53:01.592988 [ModeRegInit_LP4] CH0 RK1
7204 22:53:01.595701 [ModeRegInit_LP4] CH1 RK0
7205 22:53:01.599468 [ModeRegInit_LP4] CH1 RK1
7206 22:53:01.599887 match AC timing 4
7207 22:53:01.605693 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7208 22:53:01.608915 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7209 22:53:01.612378 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7210 22:53:01.618757 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7211 22:53:01.622016 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7212 22:53:01.622527 [MiockJmeterHQA]
7213 22:53:01.622891
7214 22:53:01.626014 [DramcMiockJmeter] u1RxGatingPI = 0
7215 22:53:01.629114 0 : 4255, 4026
7216 22:53:01.629681 4 : 4257, 4029
7217 22:53:01.632091 8 : 4252, 4027
7218 22:53:01.632672 12 : 4252, 4027
7219 22:53:01.635412 16 : 4360, 4138
7220 22:53:01.636022 20 : 4252, 4027
7221 22:53:01.636526 24 : 4255, 4029
7222 22:53:01.638589 28 : 4253, 4027
7223 22:53:01.639119 32 : 4363, 4138
7224 22:53:01.641739 36 : 4363, 4138
7225 22:53:01.642279 40 : 4250, 4027
7226 22:53:01.645706 44 : 4252, 4027
7227 22:53:01.646361 48 : 4253, 4027
7228 22:53:01.648491 52 : 4252, 4026
7229 22:53:01.648971 56 : 4255, 4029
7230 22:53:01.649465 60 : 4361, 4138
7231 22:53:01.652296 64 : 4250, 4027
7232 22:53:01.652935 68 : 4250, 4027
7233 22:53:01.655425 72 : 4252, 4026
7234 22:53:01.656075 76 : 4252, 4029
7235 22:53:01.658567 80 : 4250, 4027
7236 22:53:01.659205 84 : 4361, 4138
7237 22:53:01.659684 88 : 4360, 4138
7238 22:53:01.662400 92 : 4250, 4027
7239 22:53:01.662878 96 : 4250, 4027
7240 22:53:01.664936 100 : 4250, 2181
7241 22:53:01.665429 104 : 4250, 0
7242 22:53:01.668376 108 : 4250, 0
7243 22:53:01.668898 112 : 4252, 0
7244 22:53:01.669395 116 : 4250, 0
7245 22:53:01.671600 120 : 4250, 0
7246 22:53:01.672075 124 : 4252, 0
7247 22:53:01.674739 128 : 4250, 0
7248 22:53:01.675287 132 : 4250, 0
7249 22:53:01.675816 136 : 4252, 0
7250 22:53:01.677994 140 : 4361, 0
7251 22:53:01.678524 144 : 4361, 0
7252 22:53:01.681482 148 : 4363, 0
7253 22:53:01.681913 152 : 4250, 0
7254 22:53:01.682419 156 : 4250, 0
7255 22:53:01.684610 160 : 4250, 0
7256 22:53:01.685041 164 : 4250, 0
7257 22:53:01.688280 168 : 4250, 0
7258 22:53:01.688715 172 : 4250, 0
7259 22:53:01.689145 176 : 4252, 0
7260 22:53:01.691134 180 : 4250, 0
7261 22:53:01.691564 184 : 4250, 0
7262 22:53:01.691998 188 : 4252, 0
7263 22:53:01.694562 192 : 4361, 0
7264 22:53:01.694994 196 : 4361, 0
7265 22:53:01.698072 200 : 4363, 0
7266 22:53:01.698505 204 : 4250, 0
7267 22:53:01.699029 208 : 4250, 0
7268 22:53:01.701175 212 : 4250, 0
7269 22:53:01.701605 216 : 4250, 0
7270 22:53:01.704770 220 : 4250, 764
7271 22:53:01.705412 224 : 4252, 3998
7272 22:53:01.707994 228 : 4360, 4138
7273 22:53:01.708424 232 : 4361, 4137
7274 22:53:01.711262 236 : 4250, 4027
7275 22:53:01.711696 240 : 4253, 4030
7276 22:53:01.712127 244 : 4360, 4138
7277 22:53:01.714521 248 : 4250, 4027
7278 22:53:01.715032 252 : 4250, 4027
7279 22:53:01.717955 256 : 4250, 4027
7280 22:53:01.718572 260 : 4252, 4029
7281 22:53:01.721077 264 : 4250, 4027
7282 22:53:01.721508 268 : 4250, 4026
7283 22:53:01.724267 272 : 4363, 4140
7284 22:53:01.724685 276 : 4250, 4027
7285 22:53:01.727828 280 : 4250, 4027
7286 22:53:01.728350 284 : 4361, 4137
7287 22:53:01.730987 288 : 4250, 4027
7288 22:53:01.731403 292 : 4250, 4027
7289 22:53:01.734649 296 : 4363, 4140
7290 22:53:01.735231 300 : 4250, 4027
7291 22:53:01.735570 304 : 4250, 4027
7292 22:53:01.738519 308 : 4250, 4027
7293 22:53:01.738940 312 : 4252, 4030
7294 22:53:01.740970 316 : 4250, 4027
7295 22:53:01.741392 320 : 4250, 4027
7296 22:53:01.744688 324 : 4363, 4140
7297 22:53:01.745209 328 : 4250, 4027
7298 22:53:01.747759 332 : 4250, 4027
7299 22:53:01.748201 336 : 4361, 3731
7300 22:53:01.751160 340 : 4250, 2063
7301 22:53:01.751675
7302 22:53:01.752008 MIOCK jitter meter ch=0
7303 22:53:01.752314
7304 22:53:01.754689 1T = (340-104) = 236 dly cells
7305 22:53:01.761395 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7306 22:53:01.761942 ==
7307 22:53:01.764272 Dram Type= 6, Freq= 0, CH_0, rank 0
7308 22:53:01.767601 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7309 22:53:01.768053 ==
7310 22:53:01.774498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7311 22:53:01.777777 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7312 22:53:01.784293 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7313 22:53:01.787953 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7314 22:53:01.797203 [CA 0] Center 42 (12~73) winsize 62
7315 22:53:01.800222 [CA 1] Center 42 (12~73) winsize 62
7316 22:53:01.803694 [CA 2] Center 39 (9~69) winsize 61
7317 22:53:01.806769 [CA 3] Center 38 (9~68) winsize 60
7318 22:53:01.810114 [CA 4] Center 37 (7~67) winsize 61
7319 22:53:01.813691 [CA 5] Center 36 (6~66) winsize 61
7320 22:53:01.814353
7321 22:53:01.816819 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7322 22:53:01.817282
7323 22:53:01.819948 [CATrainingPosCal] consider 1 rank data
7324 22:53:01.823897 u2DelayCellTimex100 = 275/100 ps
7325 22:53:01.826946 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7326 22:53:01.833263 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7327 22:53:01.836736 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7328 22:53:01.839923 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7329 22:53:01.843544 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7330 22:53:01.847095 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7331 22:53:01.847643
7332 22:53:01.849954 CA PerBit enable=1, Macro0, CA PI delay=36
7333 22:53:01.850392
7334 22:53:01.853323 [CBTSetCACLKResult] CA Dly = 36
7335 22:53:01.856603 CS Dly: 10 (0~41)
7336 22:53:01.859786 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7337 22:53:01.863190 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7338 22:53:01.863651 ==
7339 22:53:01.867114 Dram Type= 6, Freq= 0, CH_0, rank 1
7340 22:53:01.870132 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7341 22:53:01.873151 ==
7342 22:53:01.876337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7343 22:53:01.879649 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7344 22:53:01.886395 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7345 22:53:01.893233 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7346 22:53:01.899564 [CA 0] Center 42 (12~73) winsize 62
7347 22:53:01.903187 [CA 1] Center 41 (11~72) winsize 62
7348 22:53:01.906675 [CA 2] Center 38 (9~68) winsize 60
7349 22:53:01.910013 [CA 3] Center 37 (7~67) winsize 61
7350 22:53:01.912563 [CA 4] Center 35 (5~65) winsize 61
7351 22:53:01.915894 [CA 5] Center 35 (5~66) winsize 62
7352 22:53:01.916403
7353 22:53:01.919595 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7354 22:53:01.920060
7355 22:53:01.926187 [CATrainingPosCal] consider 2 rank data
7356 22:53:01.926770 u2DelayCellTimex100 = 275/100 ps
7357 22:53:01.933054 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7358 22:53:01.936052 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7359 22:53:01.939094 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7360 22:53:01.942434 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7361 22:53:01.945655 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7362 22:53:01.949225 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7363 22:53:01.949684
7364 22:53:01.952399 CA PerBit enable=1, Macro0, CA PI delay=36
7365 22:53:01.952859
7366 22:53:01.955551 [CBTSetCACLKResult] CA Dly = 36
7367 22:53:01.959014 CS Dly: 11 (0~43)
7368 22:53:01.962190 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7369 22:53:01.965344 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7370 22:53:01.965584
7371 22:53:01.968791 ----->DramcWriteLeveling(PI) begin...
7372 22:53:01.969034 ==
7373 22:53:01.971951 Dram Type= 6, Freq= 0, CH_0, rank 0
7374 22:53:01.978847 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7375 22:53:01.979088 ==
7376 22:53:01.982053 Write leveling (Byte 0): 30 => 30
7377 22:53:01.985385 Write leveling (Byte 1): 27 => 27
7378 22:53:01.985799 DramcWriteLeveling(PI) end<-----
7379 22:53:01.986156
7380 22:53:01.988856 ==
7381 22:53:01.992431 Dram Type= 6, Freq= 0, CH_0, rank 0
7382 22:53:01.995371 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7383 22:53:01.995876 ==
7384 22:53:01.999101 [Gating] SW mode calibration
7385 22:53:02.005392 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7386 22:53:02.009298 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7387 22:53:02.015338 0 12 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7388 22:53:02.018768 0 12 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
7389 22:53:02.022112 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7390 22:53:02.028644 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7391 22:53:02.032187 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7392 22:53:02.035303 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7393 22:53:02.042109 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7394 22:53:02.045517 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7395 22:53:02.048507 0 13 0 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
7396 22:53:02.055088 0 13 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7397 22:53:02.058351 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7398 22:53:02.061900 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 22:53:02.068355 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7400 22:53:02.071691 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7401 22:53:02.075376 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7402 22:53:02.081932 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7403 22:53:02.085238 0 14 0 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
7404 22:53:02.088470 0 14 4 | B1->B0 | 3939 4646 | 1 0 | (1 1) (0 0)
7405 22:53:02.095054 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 22:53:02.098168 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7407 22:53:02.101695 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7408 22:53:02.105267 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7409 22:53:02.111616 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7410 22:53:02.114837 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7411 22:53:02.118343 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7412 22:53:02.125029 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7413 22:53:02.128551 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7414 22:53:02.131747 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 22:53:02.138301 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 22:53:02.141853 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 22:53:02.144836 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 22:53:02.151577 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 22:53:02.155119 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 22:53:02.157867 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 22:53:02.164839 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 22:53:02.168234 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 22:53:02.171440 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7424 22:53:02.177724 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7425 22:53:02.181207 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7426 22:53:02.184800 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7427 22:53:02.191306 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7428 22:53:02.194636 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7429 22:53:02.197975 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7430 22:53:02.201463 Total UI for P1: 0, mck2ui 16
7431 22:53:02.204766 best dqsien dly found for B0: ( 1, 1, 0)
7432 22:53:02.208189 Total UI for P1: 0, mck2ui 16
7433 22:53:02.211518 best dqsien dly found for B1: ( 1, 1, 2)
7434 22:53:02.214948 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7435 22:53:02.217931 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7436 22:53:02.218549
7437 22:53:02.221311 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7438 22:53:02.227575 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7439 22:53:02.228030 [Gating] SW calibration Done
7440 22:53:02.228388 ==
7441 22:53:02.230662 Dram Type= 6, Freq= 0, CH_0, rank 0
7442 22:53:02.237436 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7443 22:53:02.237991 ==
7444 22:53:02.238385 RX Vref Scan: 0
7445 22:53:02.238719
7446 22:53:02.240647 RX Vref 0 -> 0, step: 1
7447 22:53:02.241103
7448 22:53:02.244431 RX Delay 0 -> 252, step: 8
7449 22:53:02.247604 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7450 22:53:02.250782 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7451 22:53:02.254183 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7452 22:53:02.260484 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7453 22:53:02.263935 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7454 22:53:02.267220 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7455 22:53:02.270450 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7456 22:53:02.273661 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7457 22:53:02.280420 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7458 22:53:02.283540 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7459 22:53:02.286977 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7460 22:53:02.290243 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7461 22:53:02.293410 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7462 22:53:02.300316 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7463 22:53:02.303359 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7464 22:53:02.306857 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7465 22:53:02.307314 ==
7466 22:53:02.310132 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 22:53:02.313588 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7468 22:53:02.316702 ==
7469 22:53:02.317256 DQS Delay:
7470 22:53:02.317621 DQS0 = 0, DQS1 = 0
7471 22:53:02.320051 DQM Delay:
7472 22:53:02.320453 DQM0 = 129, DQM1 = 123
7473 22:53:02.323358 DQ Delay:
7474 22:53:02.326806 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7475 22:53:02.330278 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7476 22:53:02.333610 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7477 22:53:02.336804 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7478 22:53:02.337366
7479 22:53:02.337737
7480 22:53:02.338122 ==
7481 22:53:02.339779 Dram Type= 6, Freq= 0, CH_0, rank 0
7482 22:53:02.343097 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7483 22:53:02.343742 ==
7484 22:53:02.344317
7485 22:53:02.346677
7486 22:53:02.347402 TX Vref Scan disable
7487 22:53:02.350260 == TX Byte 0 ==
7488 22:53:02.353665 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7489 22:53:02.356461 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7490 22:53:02.359971 == TX Byte 1 ==
7491 22:53:02.362962 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7492 22:53:02.366246 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7493 22:53:02.366901 ==
7494 22:53:02.369661 Dram Type= 6, Freq= 0, CH_0, rank 0
7495 22:53:02.376424 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7496 22:53:02.376964 ==
7497 22:53:02.388350
7498 22:53:02.391369 TX Vref early break, caculate TX vref
7499 22:53:02.394703 TX Vref=16, minBit 11, minWin=21, winSum=371
7500 22:53:02.398208 TX Vref=18, minBit 8, minWin=22, winSum=381
7501 22:53:02.401463 TX Vref=20, minBit 8, minWin=22, winSum=389
7502 22:53:02.404909 TX Vref=22, minBit 8, minWin=23, winSum=399
7503 22:53:02.407979 TX Vref=24, minBit 8, minWin=24, winSum=405
7504 22:53:02.414550 TX Vref=26, minBit 7, minWin=25, winSum=414
7505 22:53:02.417998 TX Vref=28, minBit 2, minWin=25, winSum=416
7506 22:53:02.421257 TX Vref=30, minBit 0, minWin=25, winSum=412
7507 22:53:02.424647 TX Vref=32, minBit 8, minWin=23, winSum=400
7508 22:53:02.427773 TX Vref=34, minBit 0, minWin=24, winSum=391
7509 22:53:02.434866 [TxChooseVref] Worse bit 2, Min win 25, Win sum 416, Final Vref 28
7510 22:53:02.435430
7511 22:53:02.437729 Final TX Range 0 Vref 28
7512 22:53:02.438341
7513 22:53:02.438703 ==
7514 22:53:02.441126 Dram Type= 6, Freq= 0, CH_0, rank 0
7515 22:53:02.444552 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7516 22:53:02.445077 ==
7517 22:53:02.445449
7518 22:53:02.445786
7519 22:53:02.447559 TX Vref Scan disable
7520 22:53:02.454563 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7521 22:53:02.455128 == TX Byte 0 ==
7522 22:53:02.457571 u2DelayCellOfst[0]=14 cells (4 PI)
7523 22:53:02.461066 u2DelayCellOfst[1]=17 cells (5 PI)
7524 22:53:02.464711 u2DelayCellOfst[2]=14 cells (4 PI)
7525 22:53:02.467439 u2DelayCellOfst[3]=10 cells (3 PI)
7526 22:53:02.470692 u2DelayCellOfst[4]=7 cells (2 PI)
7527 22:53:02.474359 u2DelayCellOfst[5]=0 cells (0 PI)
7528 22:53:02.477420 u2DelayCellOfst[6]=17 cells (5 PI)
7529 22:53:02.480906 u2DelayCellOfst[7]=17 cells (5 PI)
7530 22:53:02.484174 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7531 22:53:02.487610 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7532 22:53:02.490878 == TX Byte 1 ==
7533 22:53:02.493899 u2DelayCellOfst[8]=3 cells (1 PI)
7534 22:53:02.494427 u2DelayCellOfst[9]=0 cells (0 PI)
7535 22:53:02.497336 u2DelayCellOfst[10]=10 cells (3 PI)
7536 22:53:02.501078 u2DelayCellOfst[11]=7 cells (2 PI)
7537 22:53:02.504107 u2DelayCellOfst[12]=14 cells (4 PI)
7538 22:53:02.507449 u2DelayCellOfst[13]=14 cells (4 PI)
7539 22:53:02.510625 u2DelayCellOfst[14]=21 cells (6 PI)
7540 22:53:02.514060 u2DelayCellOfst[15]=14 cells (4 PI)
7541 22:53:02.517531 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7542 22:53:02.523819 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7543 22:53:02.524281 DramC Write-DBI on
7544 22:53:02.524646 ==
7545 22:53:02.527090 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 22:53:02.533611 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7547 22:53:02.534180 ==
7548 22:53:02.534556
7549 22:53:02.534895
7550 22:53:02.535218 TX Vref Scan disable
7551 22:53:02.537811 == TX Byte 0 ==
7552 22:53:02.540920 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7553 22:53:02.544173 == TX Byte 1 ==
7554 22:53:02.547857 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7555 22:53:02.550857 DramC Write-DBI off
7556 22:53:02.551320
7557 22:53:02.551681 [DATLAT]
7558 22:53:02.552015 Freq=1600, CH0 RK0
7559 22:53:02.552341
7560 22:53:02.554016 DATLAT Default: 0xf
7561 22:53:02.554517 0, 0xFFFF, sum = 0
7562 22:53:02.557323 1, 0xFFFF, sum = 0
7563 22:53:02.560979 2, 0xFFFF, sum = 0
7564 22:53:02.561447 3, 0xFFFF, sum = 0
7565 22:53:02.564248 4, 0xFFFF, sum = 0
7566 22:53:02.564712 5, 0xFFFF, sum = 0
7567 22:53:02.567293 6, 0xFFFF, sum = 0
7568 22:53:02.567757 7, 0xFFFF, sum = 0
7569 22:53:02.570729 8, 0xFFFF, sum = 0
7570 22:53:02.571197 9, 0xFFFF, sum = 0
7571 22:53:02.574351 10, 0xFFFF, sum = 0
7572 22:53:02.574813 11, 0xFFFF, sum = 0
7573 22:53:02.577360 12, 0xFFF, sum = 0
7574 22:53:02.577828 13, 0x0, sum = 1
7575 22:53:02.580540 14, 0x0, sum = 2
7576 22:53:02.581003 15, 0x0, sum = 3
7577 22:53:02.584177 16, 0x0, sum = 4
7578 22:53:02.584733 best_step = 14
7579 22:53:02.585092
7580 22:53:02.585427 ==
7581 22:53:02.587625 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 22:53:02.590532 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7583 22:53:02.593697 ==
7584 22:53:02.594172 RX Vref Scan: 1
7585 22:53:02.594531
7586 22:53:02.597056 Set Vref Range= 24 -> 127
7587 22:53:02.597513
7588 22:53:02.601007 RX Vref 24 -> 127, step: 1
7589 22:53:02.601565
7590 22:53:02.601928 RX Delay 11 -> 252, step: 4
7591 22:53:02.602323
7592 22:53:02.603725 Set Vref, RX VrefLevel [Byte0]: 24
7593 22:53:02.607030 [Byte1]: 24
7594 22:53:02.611219
7595 22:53:02.611748 Set Vref, RX VrefLevel [Byte0]: 25
7596 22:53:02.614540 [Byte1]: 25
7597 22:53:02.618810
7598 22:53:02.619362 Set Vref, RX VrefLevel [Byte0]: 26
7599 22:53:02.622207 [Byte1]: 26
7600 22:53:02.626290
7601 22:53:02.626874 Set Vref, RX VrefLevel [Byte0]: 27
7602 22:53:02.629365 [Byte1]: 27
7603 22:53:02.633764
7604 22:53:02.634365 Set Vref, RX VrefLevel [Byte0]: 28
7605 22:53:02.637374 [Byte1]: 28
7606 22:53:02.641507
7607 22:53:02.641965 Set Vref, RX VrefLevel [Byte0]: 29
7608 22:53:02.644802 [Byte1]: 29
7609 22:53:02.649226
7610 22:53:02.649779 Set Vref, RX VrefLevel [Byte0]: 30
7611 22:53:02.652615 [Byte1]: 30
7612 22:53:02.656824
7613 22:53:02.657401 Set Vref, RX VrefLevel [Byte0]: 31
7614 22:53:02.660080 [Byte1]: 31
7615 22:53:02.664165
7616 22:53:02.664668 Set Vref, RX VrefLevel [Byte0]: 32
7617 22:53:02.670706 [Byte1]: 32
7618 22:53:02.671214
7619 22:53:02.674126 Set Vref, RX VrefLevel [Byte0]: 33
7620 22:53:02.677317 [Byte1]: 33
7621 22:53:02.677973
7622 22:53:02.680739 Set Vref, RX VrefLevel [Byte0]: 34
7623 22:53:02.683775 [Byte1]: 34
7624 22:53:02.687732
7625 22:53:02.688188 Set Vref, RX VrefLevel [Byte0]: 35
7626 22:53:02.690544 [Byte1]: 35
7627 22:53:02.695244
7628 22:53:02.695796 Set Vref, RX VrefLevel [Byte0]: 36
7629 22:53:02.697894 [Byte1]: 36
7630 22:53:02.702409
7631 22:53:02.702868 Set Vref, RX VrefLevel [Byte0]: 37
7632 22:53:02.705415 [Byte1]: 37
7633 22:53:02.709947
7634 22:53:02.710631 Set Vref, RX VrefLevel [Byte0]: 38
7635 22:53:02.713040 [Byte1]: 38
7636 22:53:02.718103
7637 22:53:02.718652 Set Vref, RX VrefLevel [Byte0]: 39
7638 22:53:02.720922 [Byte1]: 39
7639 22:53:02.725027
7640 22:53:02.725628 Set Vref, RX VrefLevel [Byte0]: 40
7641 22:53:02.728718 [Byte1]: 40
7642 22:53:02.732969
7643 22:53:02.733562 Set Vref, RX VrefLevel [Byte0]: 41
7644 22:53:02.736181 [Byte1]: 41
7645 22:53:02.740466
7646 22:53:02.741081 Set Vref, RX VrefLevel [Byte0]: 42
7647 22:53:02.743501 [Byte1]: 42
7648 22:53:02.748009
7649 22:53:02.748558 Set Vref, RX VrefLevel [Byte0]: 43
7650 22:53:02.751401 [Byte1]: 43
7651 22:53:02.755707
7652 22:53:02.756301 Set Vref, RX VrefLevel [Byte0]: 44
7653 22:53:02.758869 [Byte1]: 44
7654 22:53:02.763351
7655 22:53:02.763810 Set Vref, RX VrefLevel [Byte0]: 45
7656 22:53:02.766619 [Byte1]: 45
7657 22:53:02.770865
7658 22:53:02.771320 Set Vref, RX VrefLevel [Byte0]: 46
7659 22:53:02.774081 [Byte1]: 46
7660 22:53:02.778607
7661 22:53:02.779061 Set Vref, RX VrefLevel [Byte0]: 47
7662 22:53:02.781977 [Byte1]: 47
7663 22:53:02.786210
7664 22:53:02.786793 Set Vref, RX VrefLevel [Byte0]: 48
7665 22:53:02.789457 [Byte1]: 48
7666 22:53:02.794306
7667 22:53:02.794860 Set Vref, RX VrefLevel [Byte0]: 49
7668 22:53:02.797043 [Byte1]: 49
7669 22:53:02.801542
7670 22:53:02.802139 Set Vref, RX VrefLevel [Byte0]: 50
7671 22:53:02.804395 [Byte1]: 50
7672 22:53:02.808850
7673 22:53:02.809500 Set Vref, RX VrefLevel [Byte0]: 51
7674 22:53:02.812276 [Byte1]: 51
7675 22:53:02.816618
7676 22:53:02.817172 Set Vref, RX VrefLevel [Byte0]: 52
7677 22:53:02.819979 [Byte1]: 52
7678 22:53:02.824157
7679 22:53:02.824612 Set Vref, RX VrefLevel [Byte0]: 53
7680 22:53:02.827637 [Byte1]: 53
7681 22:53:02.832091
7682 22:53:02.832648 Set Vref, RX VrefLevel [Byte0]: 54
7683 22:53:02.835159 [Byte1]: 54
7684 22:53:02.839414
7685 22:53:02.839968 Set Vref, RX VrefLevel [Byte0]: 55
7686 22:53:02.842617 [Byte1]: 55
7687 22:53:02.847552
7688 22:53:02.848111 Set Vref, RX VrefLevel [Byte0]: 56
7689 22:53:02.850413 [Byte1]: 56
7690 22:53:02.854595
7691 22:53:02.855155 Set Vref, RX VrefLevel [Byte0]: 57
7692 22:53:02.857902 [Byte1]: 57
7693 22:53:02.862290
7694 22:53:02.862842 Set Vref, RX VrefLevel [Byte0]: 58
7695 22:53:02.865333 [Byte1]: 58
7696 22:53:02.869844
7697 22:53:02.870341 Set Vref, RX VrefLevel [Byte0]: 59
7698 22:53:02.873202 [Byte1]: 59
7699 22:53:02.877424
7700 22:53:02.877970 Set Vref, RX VrefLevel [Byte0]: 60
7701 22:53:02.880806 [Byte1]: 60
7702 22:53:02.885065
7703 22:53:02.885614 Set Vref, RX VrefLevel [Byte0]: 61
7704 22:53:02.888731 [Byte1]: 61
7705 22:53:02.892701
7706 22:53:02.893249 Set Vref, RX VrefLevel [Byte0]: 62
7707 22:53:02.895950 [Byte1]: 62
7708 22:53:02.900171
7709 22:53:02.900627 Set Vref, RX VrefLevel [Byte0]: 63
7710 22:53:02.903369 [Byte1]: 63
7711 22:53:02.907911
7712 22:53:02.908475 Set Vref, RX VrefLevel [Byte0]: 64
7713 22:53:02.911264 [Byte1]: 64
7714 22:53:02.915828
7715 22:53:02.916378 Set Vref, RX VrefLevel [Byte0]: 65
7716 22:53:02.918698 [Byte1]: 65
7717 22:53:02.923147
7718 22:53:02.923635 Set Vref, RX VrefLevel [Byte0]: 66
7719 22:53:02.926666 [Byte1]: 66
7720 22:53:02.930733
7721 22:53:02.931276 Set Vref, RX VrefLevel [Byte0]: 67
7722 22:53:02.934120 [Byte1]: 67
7723 22:53:02.938626
7724 22:53:02.939178 Set Vref, RX VrefLevel [Byte0]: 68
7725 22:53:02.941605 [Byte1]: 68
7726 22:53:02.946134
7727 22:53:02.946691 Set Vref, RX VrefLevel [Byte0]: 69
7728 22:53:02.949588 [Byte1]: 69
7729 22:53:02.953556
7730 22:53:02.954179 Set Vref, RX VrefLevel [Byte0]: 70
7731 22:53:02.957089 [Byte1]: 70
7732 22:53:02.961147
7733 22:53:02.961605 Set Vref, RX VrefLevel [Byte0]: 71
7734 22:53:02.964308 [Byte1]: 71
7735 22:53:02.969025
7736 22:53:02.969579 Final RX Vref Byte 0 = 53 to rank0
7737 22:53:02.971869 Final RX Vref Byte 1 = 55 to rank0
7738 22:53:02.975322 Final RX Vref Byte 0 = 53 to rank1
7739 22:53:02.978718 Final RX Vref Byte 1 = 55 to rank1==
7740 22:53:02.982226 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 22:53:02.988666 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7742 22:53:02.989224 ==
7743 22:53:02.989585 DQS Delay:
7744 22:53:02.991854 DQS0 = 0, DQS1 = 0
7745 22:53:02.992307 DQM Delay:
7746 22:53:02.992660 DQM0 = 126, DQM1 = 120
7747 22:53:02.995523 DQ Delay:
7748 22:53:02.998523 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7749 22:53:03.002261 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7750 22:53:03.005421 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7751 22:53:03.008653 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7752 22:53:03.009208
7753 22:53:03.009566
7754 22:53:03.009897
7755 22:53:03.011911 [DramC_TX_OE_Calibration] TA2
7756 22:53:03.015206 Original DQ_B0 (3 6) =30, OEN = 27
7757 22:53:03.019046 Original DQ_B1 (3 6) =30, OEN = 27
7758 22:53:03.021738 24, 0x0, End_B0=24 End_B1=24
7759 22:53:03.022292 25, 0x0, End_B0=25 End_B1=25
7760 22:53:03.024830 26, 0x0, End_B0=26 End_B1=26
7761 22:53:03.028897 27, 0x0, End_B0=27 End_B1=27
7762 22:53:03.031436 28, 0x0, End_B0=28 End_B1=28
7763 22:53:03.034635 29, 0x0, End_B0=29 End_B1=29
7764 22:53:03.035097 30, 0x0, End_B0=30 End_B1=30
7765 22:53:03.038220 31, 0x4545, End_B0=30 End_B1=30
7766 22:53:03.041694 Byte0 end_step=30 best_step=27
7767 22:53:03.044731 Byte1 end_step=30 best_step=27
7768 22:53:03.048206 Byte0 TX OE(2T, 0.5T) = (3, 3)
7769 22:53:03.051951 Byte1 TX OE(2T, 0.5T) = (3, 3)
7770 22:53:03.052541
7771 22:53:03.052900
7772 22:53:03.058381 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7773 22:53:03.061437 CH0 RK0: MR19=303, MR18=1B1B
7774 22:53:03.067882 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7775 22:53:03.068370
7776 22:53:03.071288 ----->DramcWriteLeveling(PI) begin...
7777 22:53:03.071749 ==
7778 22:53:03.074321 Dram Type= 6, Freq= 0, CH_0, rank 1
7779 22:53:03.077513 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7780 22:53:03.077971 ==
7781 22:53:03.081142 Write leveling (Byte 0): 30 => 30
7782 22:53:03.084302 Write leveling (Byte 1): 25 => 25
7783 22:53:03.087655 DramcWriteLeveling(PI) end<-----
7784 22:53:03.088206
7785 22:53:03.088565 ==
7786 22:53:03.090778 Dram Type= 6, Freq= 0, CH_0, rank 1
7787 22:53:03.094324 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7788 22:53:03.097527 ==
7789 22:53:03.098008 [Gating] SW mode calibration
7790 22:53:03.104626 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7791 22:53:03.111078 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7792 22:53:03.114252 0 12 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7793 22:53:03.120767 0 12 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7794 22:53:03.124279 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7795 22:53:03.127215 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7796 22:53:03.134245 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7797 22:53:03.137494 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7798 22:53:03.141098 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7799 22:53:03.147549 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7800 22:53:03.150940 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7801 22:53:03.154399 0 13 4 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7802 22:53:03.160649 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7803 22:53:03.163916 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7804 22:53:03.167155 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7805 22:53:03.173907 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7806 22:53:03.177037 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7807 22:53:03.180564 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7808 22:53:03.187419 0 14 0 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
7809 22:53:03.190255 0 14 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7810 22:53:03.193537 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7811 22:53:03.200513 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7812 22:53:03.203625 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7813 22:53:03.207379 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7814 22:53:03.213451 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 22:53:03.216930 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7816 22:53:03.220165 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7817 22:53:03.226730 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7818 22:53:03.230422 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 22:53:03.233627 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 22:53:03.236863 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 22:53:03.243729 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 22:53:03.247282 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 22:53:03.250280 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 22:53:03.256910 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 22:53:03.260099 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 22:53:03.263250 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 22:53:03.269768 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7828 22:53:03.273128 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7829 22:53:03.276577 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7830 22:53:03.282909 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7831 22:53:03.286384 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7832 22:53:03.289686 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7833 22:53:03.296519 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7834 22:53:03.299653 Total UI for P1: 0, mck2ui 16
7835 22:53:03.302745 best dqsien dly found for B0: ( 1, 0, 30)
7836 22:53:03.306116 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7837 22:53:03.309444 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7838 22:53:03.312896 Total UI for P1: 0, mck2ui 16
7839 22:53:03.316082 best dqsien dly found for B1: ( 1, 1, 4)
7840 22:53:03.319216 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7841 22:53:03.322500 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7842 22:53:03.325670
7843 22:53:03.329365 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7844 22:53:03.332442 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7845 22:53:03.335915 [Gating] SW calibration Done
7846 22:53:03.336484 ==
7847 22:53:03.338954 Dram Type= 6, Freq= 0, CH_0, rank 1
7848 22:53:03.342356 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7849 22:53:03.342873 ==
7850 22:53:03.343351 RX Vref Scan: 0
7851 22:53:03.345586
7852 22:53:03.346090 RX Vref 0 -> 0, step: 1
7853 22:53:03.346567
7854 22:53:03.349394 RX Delay 0 -> 252, step: 8
7855 22:53:03.352170 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7856 22:53:03.356001 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7857 22:53:03.362289 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7858 22:53:03.365458 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7859 22:53:03.369013 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7860 22:53:03.372494 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7861 22:53:03.375228 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7862 22:53:03.382222 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7863 22:53:03.385425 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7864 22:53:03.388779 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7865 22:53:03.392573 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7866 22:53:03.395291 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7867 22:53:03.401928 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7868 22:53:03.405244 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7869 22:53:03.408387 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7870 22:53:03.411896 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7871 22:53:03.412369 ==
7872 22:53:03.415232 Dram Type= 6, Freq= 0, CH_0, rank 1
7873 22:53:03.421695 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7874 22:53:03.422310 ==
7875 22:53:03.422792 DQS Delay:
7876 22:53:03.425139 DQS0 = 0, DQS1 = 0
7877 22:53:03.425742 DQM Delay:
7878 22:53:03.426298 DQM0 = 130, DQM1 = 124
7879 22:53:03.428334 DQ Delay:
7880 22:53:03.431768 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7881 22:53:03.434972 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7882 22:53:03.438220 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7883 22:53:03.441776 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7884 22:53:03.442364
7885 22:53:03.442836
7886 22:53:03.443283 ==
7887 22:53:03.444914 Dram Type= 6, Freq= 0, CH_0, rank 1
7888 22:53:03.452006 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7889 22:53:03.452580 ==
7890 22:53:03.453059
7891 22:53:03.453543
7892 22:53:03.453982 TX Vref Scan disable
7893 22:53:03.454827 == TX Byte 0 ==
7894 22:53:03.457902 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7895 22:53:03.461409 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7896 22:53:03.464865 == TX Byte 1 ==
7897 22:53:03.468069 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7898 22:53:03.474619 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7899 22:53:03.475190 ==
7900 22:53:03.477894 Dram Type= 6, Freq= 0, CH_0, rank 1
7901 22:53:03.481205 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7902 22:53:03.481668 ==
7903 22:53:03.495075
7904 22:53:03.498664 TX Vref early break, caculate TX vref
7905 22:53:03.501996 TX Vref=16, minBit 1, minWin=21, winSum=371
7906 22:53:03.505219 TX Vref=18, minBit 8, minWin=22, winSum=377
7907 22:53:03.508475 TX Vref=20, minBit 11, minWin=22, winSum=389
7908 22:53:03.511706 TX Vref=22, minBit 1, minWin=24, winSum=393
7909 22:53:03.514949 TX Vref=24, minBit 8, minWin=24, winSum=405
7910 22:53:03.521518 TX Vref=26, minBit 8, minWin=24, winSum=408
7911 22:53:03.525519 TX Vref=28, minBit 6, minWin=25, winSum=408
7912 22:53:03.528314 TX Vref=30, minBit 8, minWin=24, winSum=409
7913 22:53:03.531734 TX Vref=32, minBit 0, minWin=24, winSum=401
7914 22:53:03.535390 TX Vref=34, minBit 8, minWin=23, winSum=392
7915 22:53:03.538476 TX Vref=36, minBit 8, minWin=22, winSum=384
7916 22:53:03.544539 [TxChooseVref] Worse bit 6, Min win 25, Win sum 408, Final Vref 28
7917 22:53:03.545020
7918 22:53:03.548212 Final TX Range 0 Vref 28
7919 22:53:03.548781
7920 22:53:03.549148 ==
7921 22:53:03.551633 Dram Type= 6, Freq= 0, CH_0, rank 1
7922 22:53:03.554895 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7923 22:53:03.555457 ==
7924 22:53:03.555824
7925 22:53:03.557841
7926 22:53:03.558350 TX Vref Scan disable
7927 22:53:03.564606 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7928 22:53:03.565152 == TX Byte 0 ==
7929 22:53:03.567901 u2DelayCellOfst[0]=14 cells (4 PI)
7930 22:53:03.571538 u2DelayCellOfst[1]=21 cells (6 PI)
7931 22:53:03.574807 u2DelayCellOfst[2]=14 cells (4 PI)
7932 22:53:03.577826 u2DelayCellOfst[3]=14 cells (4 PI)
7933 22:53:03.581605 u2DelayCellOfst[4]=7 cells (2 PI)
7934 22:53:03.584379 u2DelayCellOfst[5]=0 cells (0 PI)
7935 22:53:03.588097 u2DelayCellOfst[6]=17 cells (5 PI)
7936 22:53:03.591255 u2DelayCellOfst[7]=17 cells (5 PI)
7937 22:53:03.594730 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7938 22:53:03.598403 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7939 22:53:03.601218 == TX Byte 1 ==
7940 22:53:03.604480 u2DelayCellOfst[8]=3 cells (1 PI)
7941 22:53:03.607740 u2DelayCellOfst[9]=0 cells (0 PI)
7942 22:53:03.611369 u2DelayCellOfst[10]=10 cells (3 PI)
7943 22:53:03.614480 u2DelayCellOfst[11]=7 cells (2 PI)
7944 22:53:03.615040 u2DelayCellOfst[12]=17 cells (5 PI)
7945 22:53:03.617868 u2DelayCellOfst[13]=17 cells (5 PI)
7946 22:53:03.621257 u2DelayCellOfst[14]=21 cells (6 PI)
7947 22:53:03.624401 u2DelayCellOfst[15]=14 cells (4 PI)
7948 22:53:03.630890 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7949 22:53:03.634185 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7950 22:53:03.634611 DramC Write-DBI on
7951 22:53:03.637688 ==
7952 22:53:03.638302 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 22:53:03.644528 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7954 22:53:03.645088 ==
7955 22:53:03.645456
7956 22:53:03.645799
7957 22:53:03.647991 TX Vref Scan disable
7958 22:53:03.648546 == TX Byte 0 ==
7959 22:53:03.654356 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7960 22:53:03.654912 == TX Byte 1 ==
7961 22:53:03.657929 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7962 22:53:03.660593 DramC Write-DBI off
7963 22:53:03.661054
7964 22:53:03.661416 [DATLAT]
7965 22:53:03.663825 Freq=1600, CH0 RK1
7966 22:53:03.664285
7967 22:53:03.664644 DATLAT Default: 0xe
7968 22:53:03.667197 0, 0xFFFF, sum = 0
7969 22:53:03.667668 1, 0xFFFF, sum = 0
7970 22:53:03.670784 2, 0xFFFF, sum = 0
7971 22:53:03.671255 3, 0xFFFF, sum = 0
7972 22:53:03.674291 4, 0xFFFF, sum = 0
7973 22:53:03.674861 5, 0xFFFF, sum = 0
7974 22:53:03.677165 6, 0xFFFF, sum = 0
7975 22:53:03.677683 7, 0xFFFF, sum = 0
7976 22:53:03.680647 8, 0xFFFF, sum = 0
7977 22:53:03.684445 9, 0xFFFF, sum = 0
7978 22:53:03.685009 10, 0xFFFF, sum = 0
7979 22:53:03.687215 11, 0xFFFF, sum = 0
7980 22:53:03.687721 12, 0xCFFF, sum = 0
7981 22:53:03.690322 13, 0x0, sum = 1
7982 22:53:03.690789 14, 0x0, sum = 2
7983 22:53:03.693789 15, 0x0, sum = 3
7984 22:53:03.694326 16, 0x0, sum = 4
7985 22:53:03.694703 best_step = 14
7986 22:53:03.695040
7987 22:53:03.697186 ==
7988 22:53:03.700351 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 22:53:03.703962 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7990 22:53:03.704428 ==
7991 22:53:03.704796 RX Vref Scan: 0
7992 22:53:03.705139
7993 22:53:03.706951 RX Vref 0 -> 0, step: 1
7994 22:53:03.707411
7995 22:53:03.710567 RX Delay 11 -> 252, step: 4
7996 22:53:03.713877 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7997 22:53:03.720027 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7998 22:53:03.723903 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7999 22:53:03.726686 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8000 22:53:03.730277 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8001 22:53:03.733575 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
8002 22:53:03.740170 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8003 22:53:03.743259 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8004 22:53:03.746485 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
8005 22:53:03.750183 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8006 22:53:03.753095 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8007 22:53:03.760180 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8008 22:53:03.763126 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8009 22:53:03.766704 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8010 22:53:03.769815 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8011 22:53:03.773125 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8012 22:53:03.776300 ==
8013 22:53:03.779454 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 22:53:03.782753 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8015 22:53:03.783219 ==
8016 22:53:03.783613 DQS Delay:
8017 22:53:03.786150 DQS0 = 0, DQS1 = 0
8018 22:53:03.786685 DQM Delay:
8019 22:53:03.789523 DQM0 = 128, DQM1 = 120
8020 22:53:03.789986 DQ Delay:
8021 22:53:03.792567 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
8022 22:53:03.796230 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
8023 22:53:03.799221 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8024 22:53:03.802502 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8025 22:53:03.802968
8026 22:53:03.803325
8027 22:53:03.803660
8028 22:53:03.806406 [DramC_TX_OE_Calibration] TA2
8029 22:53:03.809176 Original DQ_B0 (3 6) =30, OEN = 27
8030 22:53:03.812503 Original DQ_B1 (3 6) =30, OEN = 27
8031 22:53:03.816128 24, 0x0, End_B0=24 End_B1=24
8032 22:53:03.819251 25, 0x0, End_B0=25 End_B1=25
8033 22:53:03.819711 26, 0x0, End_B0=26 End_B1=26
8034 22:53:03.822493 27, 0x0, End_B0=27 End_B1=27
8035 22:53:03.825965 28, 0x0, End_B0=28 End_B1=28
8036 22:53:03.829209 29, 0x0, End_B0=29 End_B1=29
8037 22:53:03.832471 30, 0x0, End_B0=30 End_B1=30
8038 22:53:03.833072 31, 0x4141, End_B0=30 End_B1=30
8039 22:53:03.836225 Byte0 end_step=30 best_step=27
8040 22:53:03.839499 Byte1 end_step=30 best_step=27
8041 22:53:03.842400 Byte0 TX OE(2T, 0.5T) = (3, 3)
8042 22:53:03.845903 Byte1 TX OE(2T, 0.5T) = (3, 3)
8043 22:53:03.846394
8044 22:53:03.846729
8045 22:53:03.852363 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8046 22:53:03.855792 CH0 RK1: MR19=303, MR18=1F1F
8047 22:53:03.862565 CH0_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8048 22:53:03.865512 [RxdqsGatingPostProcess] freq 1600
8049 22:53:03.872203 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8050 22:53:03.875700 Pre-setting of DQS Precalculation
8051 22:53:03.878917 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8052 22:53:03.879470 ==
8053 22:53:03.882485 Dram Type= 6, Freq= 0, CH_1, rank 0
8054 22:53:03.885460 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8055 22:53:03.885884 ==
8056 22:53:03.892237 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8057 22:53:03.895419 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8058 22:53:03.902127 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8059 22:53:03.905949 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8060 22:53:03.914585 [CA 0] Center 41 (11~71) winsize 61
8061 22:53:03.917886 [CA 1] Center 40 (10~71) winsize 62
8062 22:53:03.921128 [CA 2] Center 36 (7~66) winsize 60
8063 22:53:03.924108 [CA 3] Center 35 (6~65) winsize 60
8064 22:53:03.927884 [CA 4] Center 33 (4~63) winsize 60
8065 22:53:03.930800 [CA 5] Center 33 (4~63) winsize 60
8066 22:53:03.931276
8067 22:53:03.934109 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8068 22:53:03.934535
8069 22:53:03.937693 [CATrainingPosCal] consider 1 rank data
8070 22:53:03.941718 u2DelayCellTimex100 = 275/100 ps
8071 22:53:03.947513 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8072 22:53:03.950774 CA1 delay=40 (10~71),Diff = 7 PI (24 cell)
8073 22:53:03.954001 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8074 22:53:03.958095 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8075 22:53:03.960958 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8076 22:53:03.964309 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8077 22:53:03.964871
8078 22:53:03.967368 CA PerBit enable=1, Macro0, CA PI delay=33
8079 22:53:03.967834
8080 22:53:03.970594 [CBTSetCACLKResult] CA Dly = 33
8081 22:53:03.974411 CS Dly: 9 (0~40)
8082 22:53:03.977532 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8083 22:53:03.980519 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8084 22:53:03.980983 ==
8085 22:53:03.984113 Dram Type= 6, Freq= 0, CH_1, rank 1
8086 22:53:03.990844 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8087 22:53:03.991392 ==
8088 22:53:03.993830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8089 22:53:04.000690 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8090 22:53:04.003860 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8091 22:53:04.010328 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8092 22:53:04.016976 [CA 0] Center 40 (10~70) winsize 61
8093 22:53:04.020475 [CA 1] Center 39 (9~70) winsize 62
8094 22:53:04.023340 [CA 2] Center 36 (7~65) winsize 59
8095 22:53:04.026764 [CA 3] Center 35 (6~65) winsize 60
8096 22:53:04.030243 [CA 4] Center 32 (3~62) winsize 60
8097 22:53:04.033607 [CA 5] Center 33 (3~63) winsize 61
8098 22:53:04.034102
8099 22:53:04.036924 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8100 22:53:04.037473
8101 22:53:04.040163 [CATrainingPosCal] consider 2 rank data
8102 22:53:04.043608 u2DelayCellTimex100 = 275/100 ps
8103 22:53:04.047069 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8104 22:53:04.053855 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8105 22:53:04.056980 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8106 22:53:04.060619 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8107 22:53:04.063356 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8108 22:53:04.066659 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8109 22:53:04.067212
8110 22:53:04.070178 CA PerBit enable=1, Macro0, CA PI delay=33
8111 22:53:04.070727
8112 22:53:04.073612 [CBTSetCACLKResult] CA Dly = 33
8113 22:53:04.076997 CS Dly: 9 (0~41)
8114 22:53:04.080022 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8115 22:53:04.083283 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8116 22:53:04.083748
8117 22:53:04.086526 ----->DramcWriteLeveling(PI) begin...
8118 22:53:04.086995 ==
8119 22:53:04.090087 Dram Type= 6, Freq= 0, CH_1, rank 0
8120 22:53:04.093379 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8121 22:53:04.096858 ==
8122 22:53:04.097411 Write leveling (Byte 0): 23 => 23
8123 22:53:04.099880 Write leveling (Byte 1): 23 => 23
8124 22:53:04.103530 DramcWriteLeveling(PI) end<-----
8125 22:53:04.104085
8126 22:53:04.104452 ==
8127 22:53:04.106419 Dram Type= 6, Freq= 0, CH_1, rank 0
8128 22:53:04.113488 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8129 22:53:04.114085 ==
8130 22:53:04.116500 [Gating] SW mode calibration
8131 22:53:04.122970 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8132 22:53:04.126539 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8133 22:53:04.132889 0 12 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8134 22:53:04.136277 0 12 4 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
8135 22:53:04.139859 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8136 22:53:04.146434 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8137 22:53:04.149741 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8138 22:53:04.152863 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8139 22:53:04.159393 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8140 22:53:04.163023 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8141 22:53:04.165970 0 13 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8142 22:53:04.173025 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8143 22:53:04.175920 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8144 22:53:04.179190 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8145 22:53:04.185949 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8146 22:53:04.189234 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8147 22:53:04.192796 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8148 22:53:04.199280 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8149 22:53:04.202607 0 14 0 | B1->B0 | 3333 4646 | 1 0 | (1 1) (0 0)
8150 22:53:04.205651 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8151 22:53:04.212006 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8152 22:53:04.215991 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8153 22:53:04.218929 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8154 22:53:04.225318 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8155 22:53:04.228942 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8156 22:53:04.232306 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8157 22:53:04.238755 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8158 22:53:04.242137 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8159 22:53:04.245263 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 22:53:04.251708 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 22:53:04.254946 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 22:53:04.258511 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 22:53:04.264941 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 22:53:04.268362 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 22:53:04.271838 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 22:53:04.275142 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8167 22:53:04.282136 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8168 22:53:04.285288 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8169 22:53:04.288582 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8170 22:53:04.295099 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8171 22:53:04.298551 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8172 22:53:04.302228 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8173 22:53:04.308358 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8174 22:53:04.311521 Total UI for P1: 0, mck2ui 16
8175 22:53:04.314810 best dqsien dly found for B0: ( 1, 0, 26)
8176 22:53:04.318413 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8177 22:53:04.321731 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8178 22:53:04.324805 Total UI for P1: 0, mck2ui 16
8179 22:53:04.328506 best dqsien dly found for B1: ( 1, 1, 2)
8180 22:53:04.331505 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8181 22:53:04.334810 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8182 22:53:04.335356
8183 22:53:04.341347 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8184 22:53:04.344724 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8185 22:53:04.345280 [Gating] SW calibration Done
8186 22:53:04.347914 ==
8187 22:53:04.351432 Dram Type= 6, Freq= 0, CH_1, rank 0
8188 22:53:04.355004 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8189 22:53:04.355569 ==
8190 22:53:04.355933 RX Vref Scan: 0
8191 22:53:04.356274
8192 22:53:04.358173 RX Vref 0 -> 0, step: 1
8193 22:53:04.358628
8194 22:53:04.361615 RX Delay 0 -> 252, step: 8
8195 22:53:04.364730 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8196 22:53:04.367852 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8197 22:53:04.371112 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8198 22:53:04.378435 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8199 22:53:04.381115 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8200 22:53:04.384628 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8201 22:53:04.388002 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8202 22:53:04.391224 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8203 22:53:04.397926 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8204 22:53:04.401327 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8205 22:53:04.404625 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8206 22:53:04.407650 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8207 22:53:04.411001 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8208 22:53:04.417881 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8209 22:53:04.420832 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8210 22:53:04.424414 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8211 22:53:04.424882 ==
8212 22:53:04.427485 Dram Type= 6, Freq= 0, CH_1, rank 0
8213 22:53:04.430842 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8214 22:53:04.433944 ==
8215 22:53:04.434461 DQS Delay:
8216 22:53:04.434824 DQS0 = 0, DQS1 = 0
8217 22:53:04.437595 DQM Delay:
8218 22:53:04.438190 DQM0 = 130, DQM1 = 125
8219 22:53:04.441016 DQ Delay:
8220 22:53:04.444034 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8221 22:53:04.447579 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8222 22:53:04.450922 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8223 22:53:04.454344 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8224 22:53:04.454990
8225 22:53:04.455361
8226 22:53:04.455696 ==
8227 22:53:04.457434 Dram Type= 6, Freq= 0, CH_1, rank 0
8228 22:53:04.460775 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8229 22:53:04.461231 ==
8230 22:53:04.461663
8231 22:53:04.464364
8232 22:53:04.464938 TX Vref Scan disable
8233 22:53:04.467350 == TX Byte 0 ==
8234 22:53:04.471199 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8235 22:53:04.473950 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8236 22:53:04.477402 == TX Byte 1 ==
8237 22:53:04.480935 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8238 22:53:04.483938 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8239 22:53:04.484400 ==
8240 22:53:04.487645 Dram Type= 6, Freq= 0, CH_1, rank 0
8241 22:53:04.493913 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8242 22:53:04.494529 ==
8243 22:53:04.505387
8244 22:53:04.508668 TX Vref early break, caculate TX vref
8245 22:53:04.511663 TX Vref=16, minBit 3, minWin=21, winSum=365
8246 22:53:04.515145 TX Vref=18, minBit 0, minWin=22, winSum=372
8247 22:53:04.518425 TX Vref=20, minBit 0, minWin=23, winSum=384
8248 22:53:04.521727 TX Vref=22, minBit 0, minWin=24, winSum=394
8249 22:53:04.524785 TX Vref=24, minBit 3, minWin=23, winSum=405
8250 22:53:04.531624 TX Vref=26, minBit 0, minWin=24, winSum=409
8251 22:53:04.535223 TX Vref=28, minBit 0, minWin=25, winSum=415
8252 22:53:04.538774 TX Vref=30, minBit 3, minWin=24, winSum=405
8253 22:53:04.541868 TX Vref=32, minBit 3, minWin=23, winSum=396
8254 22:53:04.544880 TX Vref=34, minBit 3, minWin=23, winSum=386
8255 22:53:04.551828 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8256 22:53:04.552413
8257 22:53:04.554658 Final TX Range 0 Vref 28
8258 22:53:04.555234
8259 22:53:04.555594 ==
8260 22:53:04.558182 Dram Type= 6, Freq= 0, CH_1, rank 0
8261 22:53:04.561168 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8262 22:53:04.561628 ==
8263 22:53:04.561986
8264 22:53:04.562368
8265 22:53:04.564747 TX Vref Scan disable
8266 22:53:04.570995 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8267 22:53:04.571484 == TX Byte 0 ==
8268 22:53:04.574434 u2DelayCellOfst[0]=14 cells (4 PI)
8269 22:53:04.577926 u2DelayCellOfst[1]=10 cells (3 PI)
8270 22:53:04.581268 u2DelayCellOfst[2]=0 cells (0 PI)
8271 22:53:04.584415 u2DelayCellOfst[3]=7 cells (2 PI)
8272 22:53:04.587858 u2DelayCellOfst[4]=7 cells (2 PI)
8273 22:53:04.591412 u2DelayCellOfst[5]=14 cells (4 PI)
8274 22:53:04.594472 u2DelayCellOfst[6]=14 cells (4 PI)
8275 22:53:04.598006 u2DelayCellOfst[7]=7 cells (2 PI)
8276 22:53:04.601433 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8277 22:53:04.604322 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8278 22:53:04.607577 == TX Byte 1 ==
8279 22:53:04.608033 u2DelayCellOfst[8]=0 cells (0 PI)
8280 22:53:04.611192 u2DelayCellOfst[9]=7 cells (2 PI)
8281 22:53:04.614366 u2DelayCellOfst[10]=10 cells (3 PI)
8282 22:53:04.617538 u2DelayCellOfst[11]=3 cells (1 PI)
8283 22:53:04.620934 u2DelayCellOfst[12]=17 cells (5 PI)
8284 22:53:04.624045 u2DelayCellOfst[13]=21 cells (6 PI)
8285 22:53:04.627451 u2DelayCellOfst[14]=21 cells (6 PI)
8286 22:53:04.630729 u2DelayCellOfst[15]=21 cells (6 PI)
8287 22:53:04.634194 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8288 22:53:04.641313 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8289 22:53:04.641912 DramC Write-DBI on
8290 22:53:04.642340 ==
8291 22:53:04.644011 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 22:53:04.647894 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8293 22:53:04.650660 ==
8294 22:53:04.651216
8295 22:53:04.651613
8296 22:53:04.651960 TX Vref Scan disable
8297 22:53:04.654589 == TX Byte 0 ==
8298 22:53:04.657584 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8299 22:53:04.660725 == TX Byte 1 ==
8300 22:53:04.664126 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8301 22:53:04.667433 DramC Write-DBI off
8302 22:53:04.667885
8303 22:53:04.668241 [DATLAT]
8304 22:53:04.668571 Freq=1600, CH1 RK0
8305 22:53:04.668894
8306 22:53:04.670434 DATLAT Default: 0xf
8307 22:53:04.670890 0, 0xFFFF, sum = 0
8308 22:53:04.673791 1, 0xFFFF, sum = 0
8309 22:53:04.677452 2, 0xFFFF, sum = 0
8310 22:53:04.677954 3, 0xFFFF, sum = 0
8311 22:53:04.680632 4, 0xFFFF, sum = 0
8312 22:53:04.681203 5, 0xFFFF, sum = 0
8313 22:53:04.684151 6, 0xFFFF, sum = 0
8314 22:53:04.684876 7, 0xFFFF, sum = 0
8315 22:53:04.687253 8, 0xFFFF, sum = 0
8316 22:53:04.687828 9, 0xFFFF, sum = 0
8317 22:53:04.690481 10, 0xFFFF, sum = 0
8318 22:53:04.690941 11, 0xFFFF, sum = 0
8319 22:53:04.693805 12, 0xF7F, sum = 0
8320 22:53:04.694378 13, 0x0, sum = 1
8321 22:53:04.697345 14, 0x0, sum = 2
8322 22:53:04.698179 15, 0x0, sum = 3
8323 22:53:04.700792 16, 0x0, sum = 4
8324 22:53:04.701351 best_step = 14
8325 22:53:04.701706
8326 22:53:04.702249 ==
8327 22:53:04.703644 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 22:53:04.706979 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8329 22:53:04.710636 ==
8330 22:53:04.711193 RX Vref Scan: 1
8331 22:53:04.711553
8332 22:53:04.714001 Set Vref Range= 24 -> 127
8333 22:53:04.714588
8334 22:53:04.717376 RX Vref 24 -> 127, step: 1
8335 22:53:04.717932
8336 22:53:04.718352 RX Delay 3 -> 252, step: 4
8337 22:53:04.718695
8338 22:53:04.720336 Set Vref, RX VrefLevel [Byte0]: 24
8339 22:53:04.723471 [Byte1]: 24
8340 22:53:04.727298
8341 22:53:04.727752 Set Vref, RX VrefLevel [Byte0]: 25
8342 22:53:04.730730 [Byte1]: 25
8343 22:53:04.735262
8344 22:53:04.735817 Set Vref, RX VrefLevel [Byte0]: 26
8345 22:53:04.738447 [Byte1]: 26
8346 22:53:04.742695
8347 22:53:04.743251 Set Vref, RX VrefLevel [Byte0]: 27
8348 22:53:04.746118 [Byte1]: 27
8349 22:53:04.750576
8350 22:53:04.751153 Set Vref, RX VrefLevel [Byte0]: 28
8351 22:53:04.753917 [Byte1]: 28
8352 22:53:04.758625
8353 22:53:04.759175 Set Vref, RX VrefLevel [Byte0]: 29
8354 22:53:04.761572 [Byte1]: 29
8355 22:53:04.765600
8356 22:53:04.766085 Set Vref, RX VrefLevel [Byte0]: 30
8357 22:53:04.769031 [Byte1]: 30
8358 22:53:04.773223
8359 22:53:04.773675 Set Vref, RX VrefLevel [Byte0]: 31
8360 22:53:04.776436 [Byte1]: 31
8361 22:53:04.781205
8362 22:53:04.781655 Set Vref, RX VrefLevel [Byte0]: 32
8363 22:53:04.784078 [Byte1]: 32
8364 22:53:04.788367
8365 22:53:04.788814 Set Vref, RX VrefLevel [Byte0]: 33
8366 22:53:04.791962 [Byte1]: 33
8367 22:53:04.796106
8368 22:53:04.796575 Set Vref, RX VrefLevel [Byte0]: 34
8369 22:53:04.799513 [Byte1]: 34
8370 22:53:04.804026
8371 22:53:04.804592 Set Vref, RX VrefLevel [Byte0]: 35
8372 22:53:04.806977 [Byte1]: 35
8373 22:53:04.811588
8374 22:53:04.812134 Set Vref, RX VrefLevel [Byte0]: 36
8375 22:53:04.814861 [Byte1]: 36
8376 22:53:04.819248
8377 22:53:04.819802 Set Vref, RX VrefLevel [Byte0]: 37
8378 22:53:04.822257 [Byte1]: 37
8379 22:53:04.826879
8380 22:53:04.827325 Set Vref, RX VrefLevel [Byte0]: 38
8381 22:53:04.829984 [Byte1]: 38
8382 22:53:04.834404
8383 22:53:04.834855 Set Vref, RX VrefLevel [Byte0]: 39
8384 22:53:04.837608 [Byte1]: 39
8385 22:53:04.842263
8386 22:53:04.842816 Set Vref, RX VrefLevel [Byte0]: 40
8387 22:53:04.845769 [Byte1]: 40
8388 22:53:04.849838
8389 22:53:04.850331 Set Vref, RX VrefLevel [Byte0]: 41
8390 22:53:04.853237 [Byte1]: 41
8391 22:53:04.857814
8392 22:53:04.858410 Set Vref, RX VrefLevel [Byte0]: 42
8393 22:53:04.861012 [Byte1]: 42
8394 22:53:04.865211
8395 22:53:04.865767 Set Vref, RX VrefLevel [Byte0]: 43
8396 22:53:04.868402 [Byte1]: 43
8397 22:53:04.872785
8398 22:53:04.873259 Set Vref, RX VrefLevel [Byte0]: 44
8399 22:53:04.876146 [Byte1]: 44
8400 22:53:04.880639
8401 22:53:04.881188 Set Vref, RX VrefLevel [Byte0]: 45
8402 22:53:04.883860 [Byte1]: 45
8403 22:53:04.888242
8404 22:53:04.888853 Set Vref, RX VrefLevel [Byte0]: 46
8405 22:53:04.891320 [Byte1]: 46
8406 22:53:04.895766
8407 22:53:04.896316 Set Vref, RX VrefLevel [Byte0]: 47
8408 22:53:04.898877 [Byte1]: 47
8409 22:53:04.903309
8410 22:53:04.903878 Set Vref, RX VrefLevel [Byte0]: 48
8411 22:53:04.906603 [Byte1]: 48
8412 22:53:04.910939
8413 22:53:04.911384 Set Vref, RX VrefLevel [Byte0]: 49
8414 22:53:04.914554 [Byte1]: 49
8415 22:53:04.918985
8416 22:53:04.919532 Set Vref, RX VrefLevel [Byte0]: 50
8417 22:53:04.922119 [Byte1]: 50
8418 22:53:04.926240
8419 22:53:04.926689 Set Vref, RX VrefLevel [Byte0]: 51
8420 22:53:04.929470 [Byte1]: 51
8421 22:53:04.934451
8422 22:53:04.934999 Set Vref, RX VrefLevel [Byte0]: 52
8423 22:53:04.937508 [Byte1]: 52
8424 22:53:04.941728
8425 22:53:04.942356 Set Vref, RX VrefLevel [Byte0]: 53
8426 22:53:04.945169 [Byte1]: 53
8427 22:53:04.949403
8428 22:53:04.949949 Set Vref, RX VrefLevel [Byte0]: 54
8429 22:53:04.952633 [Byte1]: 54
8430 22:53:04.956908
8431 22:53:04.957614 Set Vref, RX VrefLevel [Byte0]: 55
8432 22:53:04.960116 [Byte1]: 55
8433 22:53:04.964441
8434 22:53:04.964892 Set Vref, RX VrefLevel [Byte0]: 56
8435 22:53:04.967658 [Byte1]: 56
8436 22:53:04.971939
8437 22:53:04.972628 Set Vref, RX VrefLevel [Byte0]: 57
8438 22:53:04.975447 [Byte1]: 57
8439 22:53:04.980058
8440 22:53:04.980608 Set Vref, RX VrefLevel [Byte0]: 58
8441 22:53:04.983302 [Byte1]: 58
8442 22:53:04.987355
8443 22:53:04.987932 Set Vref, RX VrefLevel [Byte0]: 59
8444 22:53:04.991040 [Byte1]: 59
8445 22:53:04.995024
8446 22:53:04.995481 Set Vref, RX VrefLevel [Byte0]: 60
8447 22:53:04.998613 [Byte1]: 60
8448 22:53:05.002751
8449 22:53:05.003207 Set Vref, RX VrefLevel [Byte0]: 61
8450 22:53:05.006266 [Byte1]: 61
8451 22:53:05.010372
8452 22:53:05.010824 Set Vref, RX VrefLevel [Byte0]: 62
8453 22:53:05.013688 [Byte1]: 62
8454 22:53:05.017988
8455 22:53:05.018491 Set Vref, RX VrefLevel [Byte0]: 63
8456 22:53:05.021422 [Byte1]: 63
8457 22:53:05.025508
8458 22:53:05.025960 Set Vref, RX VrefLevel [Byte0]: 64
8459 22:53:05.028855 [Byte1]: 64
8460 22:53:05.033699
8461 22:53:05.034315 Set Vref, RX VrefLevel [Byte0]: 65
8462 22:53:05.037122 [Byte1]: 65
8463 22:53:05.040928
8464 22:53:05.041403 Set Vref, RX VrefLevel [Byte0]: 66
8465 22:53:05.044868 [Byte1]: 66
8466 22:53:05.048716
8467 22:53:05.049121 Set Vref, RX VrefLevel [Byte0]: 67
8468 22:53:05.051846 [Byte1]: 67
8469 22:53:05.056218
8470 22:53:05.056672 Set Vref, RX VrefLevel [Byte0]: 68
8471 22:53:05.059614 [Byte1]: 68
8472 22:53:05.064401
8473 22:53:05.064853 Set Vref, RX VrefLevel [Byte0]: 69
8474 22:53:05.067421 [Byte1]: 69
8475 22:53:05.071606
8476 22:53:05.072094 Set Vref, RX VrefLevel [Byte0]: 70
8477 22:53:05.075027 [Byte1]: 70
8478 22:53:05.079410
8479 22:53:05.079865 Set Vref, RX VrefLevel [Byte0]: 71
8480 22:53:05.082928 [Byte1]: 71
8481 22:53:05.086971
8482 22:53:05.087427 Set Vref, RX VrefLevel [Byte0]: 72
8483 22:53:05.090143 [Byte1]: 72
8484 22:53:05.094423
8485 22:53:05.094875 Set Vref, RX VrefLevel [Byte0]: 73
8486 22:53:05.097792 [Byte1]: 73
8487 22:53:05.101997
8488 22:53:05.102528 Set Vref, RX VrefLevel [Byte0]: 74
8489 22:53:05.105747 [Byte1]: 74
8490 22:53:05.109981
8491 22:53:05.110579 Set Vref, RX VrefLevel [Byte0]: 75
8492 22:53:05.113509 [Byte1]: 75
8493 22:53:05.117728
8494 22:53:05.118231 Set Vref, RX VrefLevel [Byte0]: 76
8495 22:53:05.120696 [Byte1]: 76
8496 22:53:05.125297
8497 22:53:05.125751 Final RX Vref Byte 0 = 57 to rank0
8498 22:53:05.128573 Final RX Vref Byte 1 = 53 to rank0
8499 22:53:05.132017 Final RX Vref Byte 0 = 57 to rank1
8500 22:53:05.134851 Final RX Vref Byte 1 = 53 to rank1==
8501 22:53:05.138175 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 22:53:05.144944 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8503 22:53:05.145500 ==
8504 22:53:05.145864 DQS Delay:
8505 22:53:05.148499 DQS0 = 0, DQS1 = 0
8506 22:53:05.149054 DQM Delay:
8507 22:53:05.149415 DQM0 = 128, DQM1 = 123
8508 22:53:05.151492 DQ Delay:
8509 22:53:05.155115 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8510 22:53:05.158246 DQ4 =128, DQ5 =140, DQ6 =134, DQ7 =126
8511 22:53:05.161436 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8512 22:53:05.164782 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8513 22:53:05.165235
8514 22:53:05.165591
8515 22:53:05.165920
8516 22:53:05.168162 [DramC_TX_OE_Calibration] TA2
8517 22:53:05.171374 Original DQ_B0 (3 6) =30, OEN = 27
8518 22:53:05.174762 Original DQ_B1 (3 6) =30, OEN = 27
8519 22:53:05.178076 24, 0x0, End_B0=24 End_B1=24
8520 22:53:05.178543 25, 0x0, End_B0=25 End_B1=25
8521 22:53:05.181567 26, 0x0, End_B0=26 End_B1=26
8522 22:53:05.185046 27, 0x0, End_B0=27 End_B1=27
8523 22:53:05.188213 28, 0x0, End_B0=28 End_B1=28
8524 22:53:05.191590 29, 0x0, End_B0=29 End_B1=29
8525 22:53:05.192161 30, 0x0, End_B0=30 End_B1=30
8526 22:53:05.194751 31, 0x4141, End_B0=30 End_B1=30
8527 22:53:05.197921 Byte0 end_step=30 best_step=27
8528 22:53:05.201438 Byte1 end_step=30 best_step=27
8529 22:53:05.204806 Byte0 TX OE(2T, 0.5T) = (3, 3)
8530 22:53:05.208242 Byte1 TX OE(2T, 0.5T) = (3, 3)
8531 22:53:05.208868
8532 22:53:05.209240
8533 22:53:05.214584 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8534 22:53:05.217938 CH1 RK0: MR19=303, MR18=2929
8535 22:53:05.224407 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8536 22:53:05.224998
8537 22:53:05.227544 ----->DramcWriteLeveling(PI) begin...
8538 22:53:05.228121 ==
8539 22:53:05.231055 Dram Type= 6, Freq= 0, CH_1, rank 1
8540 22:53:05.234315 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8541 22:53:05.234776 ==
8542 22:53:05.237576 Write leveling (Byte 0): 21 => 21
8543 22:53:05.240994 Write leveling (Byte 1): 20 => 20
8544 22:53:05.244467 DramcWriteLeveling(PI) end<-----
8545 22:53:05.245107
8546 22:53:05.245558 ==
8547 22:53:05.247633 Dram Type= 6, Freq= 0, CH_1, rank 1
8548 22:53:05.250884 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8549 22:53:05.251344 ==
8550 22:53:05.254261 [Gating] SW mode calibration
8551 22:53:05.260803 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8552 22:53:05.267358 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8553 22:53:05.270533 0 12 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8554 22:53:05.277037 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8555 22:53:05.280480 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8556 22:53:05.284142 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8557 22:53:05.290639 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8558 22:53:05.293921 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8559 22:53:05.297512 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8560 22:53:05.303638 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8561 22:53:05.307473 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8562 22:53:05.310184 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8563 22:53:05.316810 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8564 22:53:05.320405 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8565 22:53:05.323415 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8566 22:53:05.330621 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8567 22:53:05.333733 0 13 24 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8568 22:53:05.337089 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8569 22:53:05.343771 0 14 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8570 22:53:05.346769 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8571 22:53:05.350265 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8572 22:53:05.356845 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8573 22:53:05.359687 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8574 22:53:05.363249 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8575 22:53:05.369593 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8576 22:53:05.373763 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8577 22:53:05.376632 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 22:53:05.383199 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 22:53:05.386624 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 22:53:05.389986 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 22:53:05.393580 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 22:53:05.400200 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 22:53:05.403213 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 22:53:05.406240 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8585 22:53:05.413445 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8586 22:53:05.416811 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8587 22:53:05.420326 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8588 22:53:05.426242 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8589 22:53:05.429883 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8590 22:53:05.433053 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8591 22:53:05.439540 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8592 22:53:05.442973 Total UI for P1: 0, mck2ui 16
8593 22:53:05.446064 best dqsien dly found for B0: ( 1, 0, 20)
8594 22:53:05.449295 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8595 22:53:05.453152 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8596 22:53:05.459839 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8597 22:53:05.460397 Total UI for P1: 0, mck2ui 16
8598 22:53:05.466095 best dqsien dly found for B1: ( 1, 0, 30)
8599 22:53:05.469244 best DQS0 dly(MCK, UI, PI) = (1, 0, 20)
8600 22:53:05.472878 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8601 22:53:05.473332
8602 22:53:05.476049 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 20)
8603 22:53:05.479438 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8604 22:53:05.482992 [Gating] SW calibration Done
8605 22:53:05.483542 ==
8606 22:53:05.486191 Dram Type= 6, Freq= 0, CH_1, rank 1
8607 22:53:05.489404 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8608 22:53:05.489866 ==
8609 22:53:05.492540 RX Vref Scan: 0
8610 22:53:05.492999
8611 22:53:05.493376 RX Vref 0 -> 0, step: 1
8612 22:53:05.493709
8613 22:53:05.496251 RX Delay 0 -> 252, step: 8
8614 22:53:05.499501 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8615 22:53:05.505809 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8616 22:53:05.509141 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8617 22:53:05.512728 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8618 22:53:05.515965 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8619 22:53:05.519347 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8620 22:53:05.525947 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8621 22:53:05.529253 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8622 22:53:05.532411 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8623 22:53:05.535530 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8624 22:53:05.539191 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8625 22:53:05.545841 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8626 22:53:05.549052 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8627 22:53:05.552555 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8628 22:53:05.555838 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8629 22:53:05.562361 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8630 22:53:05.562889 ==
8631 22:53:05.565611 Dram Type= 6, Freq= 0, CH_1, rank 1
8632 22:53:05.568949 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8633 22:53:05.569556 ==
8634 22:53:05.569933 DQS Delay:
8635 22:53:05.572376 DQS0 = 0, DQS1 = 0
8636 22:53:05.572926 DQM Delay:
8637 22:53:05.575636 DQM0 = 131, DQM1 = 124
8638 22:53:05.576190 DQ Delay:
8639 22:53:05.578840 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8640 22:53:05.582471 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =131
8641 22:53:05.585837 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8642 22:53:05.588662 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8643 22:53:05.589136
8644 22:53:05.589545
8645 22:53:05.592141 ==
8646 22:53:05.592704 Dram Type= 6, Freq= 0, CH_1, rank 1
8647 22:53:05.598573 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8648 22:53:05.599121 ==
8649 22:53:05.599483
8650 22:53:05.599891
8651 22:53:05.602086 TX Vref Scan disable
8652 22:53:05.602545 == TX Byte 0 ==
8653 22:53:05.604987 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8654 22:53:05.611827 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8655 22:53:05.612377 == TX Byte 1 ==
8656 22:53:05.614813 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8657 22:53:05.621652 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8658 22:53:05.622391 ==
8659 22:53:05.624953 Dram Type= 6, Freq= 0, CH_1, rank 1
8660 22:53:05.628376 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8661 22:53:05.628935 ==
8662 22:53:05.641355
8663 22:53:05.644523 TX Vref early break, caculate TX vref
8664 22:53:05.647630 TX Vref=16, minBit 0, minWin=22, winSum=379
8665 22:53:05.651474 TX Vref=18, minBit 7, minWin=22, winSum=389
8666 22:53:05.654005 TX Vref=20, minBit 2, minWin=23, winSum=402
8667 22:53:05.657536 TX Vref=22, minBit 2, minWin=24, winSum=408
8668 22:53:05.661125 TX Vref=24, minBit 3, minWin=24, winSum=412
8669 22:53:05.667273 TX Vref=26, minBit 0, minWin=25, winSum=419
8670 22:53:05.670667 TX Vref=28, minBit 0, minWin=25, winSum=420
8671 22:53:05.674462 TX Vref=30, minBit 0, minWin=25, winSum=417
8672 22:53:05.677459 TX Vref=32, minBit 3, minWin=24, winSum=407
8673 22:53:05.680835 TX Vref=34, minBit 0, minWin=23, winSum=398
8674 22:53:05.687278 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8675 22:53:05.687837
8676 22:53:05.690788 Final TX Range 0 Vref 28
8677 22:53:05.691246
8678 22:53:05.691600 ==
8679 22:53:05.693749 Dram Type= 6, Freq= 0, CH_1, rank 1
8680 22:53:05.697050 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8681 22:53:05.697611 ==
8682 22:53:05.698021
8683 22:53:05.698450
8684 22:53:05.700615 TX Vref Scan disable
8685 22:53:05.707017 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8686 22:53:05.707575 == TX Byte 0 ==
8687 22:53:05.710018 u2DelayCellOfst[0]=17 cells (5 PI)
8688 22:53:05.713606 u2DelayCellOfst[1]=10 cells (3 PI)
8689 22:53:05.717250 u2DelayCellOfst[2]=0 cells (0 PI)
8690 22:53:05.720401 u2DelayCellOfst[3]=7 cells (2 PI)
8691 22:53:05.723633 u2DelayCellOfst[4]=7 cells (2 PI)
8692 22:53:05.726626 u2DelayCellOfst[5]=14 cells (4 PI)
8693 22:53:05.730686 u2DelayCellOfst[6]=14 cells (4 PI)
8694 22:53:05.733758 u2DelayCellOfst[7]=7 cells (2 PI)
8695 22:53:05.737074 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8696 22:53:05.740414 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8697 22:53:05.743710 == TX Byte 1 ==
8698 22:53:05.746600 u2DelayCellOfst[8]=0 cells (0 PI)
8699 22:53:05.747074 u2DelayCellOfst[9]=7 cells (2 PI)
8700 22:53:05.750411 u2DelayCellOfst[10]=10 cells (3 PI)
8701 22:53:05.753723 u2DelayCellOfst[11]=3 cells (1 PI)
8702 22:53:05.756611 u2DelayCellOfst[12]=14 cells (4 PI)
8703 22:53:05.760098 u2DelayCellOfst[13]=17 cells (5 PI)
8704 22:53:05.763169 u2DelayCellOfst[14]=17 cells (5 PI)
8705 22:53:05.766322 u2DelayCellOfst[15]=17 cells (5 PI)
8706 22:53:05.769827 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8707 22:53:05.777294 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8708 22:53:05.777848 DramC Write-DBI on
8709 22:53:05.778283 ==
8710 22:53:05.780013 Dram Type= 6, Freq= 0, CH_1, rank 1
8711 22:53:05.786654 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8712 22:53:05.787208 ==
8713 22:53:05.787568
8714 22:53:05.787903
8715 22:53:05.788221 TX Vref Scan disable
8716 22:53:05.790593 == TX Byte 0 ==
8717 22:53:05.793593 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8718 22:53:05.797164 == TX Byte 1 ==
8719 22:53:05.800590 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8720 22:53:05.803345 DramC Write-DBI off
8721 22:53:05.803797
8722 22:53:05.804150 [DATLAT]
8723 22:53:05.804479 Freq=1600, CH1 RK1
8724 22:53:05.804828
8725 22:53:05.806381 DATLAT Default: 0xe
8726 22:53:05.810135 0, 0xFFFF, sum = 0
8727 22:53:05.810600 1, 0xFFFF, sum = 0
8728 22:53:05.812962 2, 0xFFFF, sum = 0
8729 22:53:05.813423 3, 0xFFFF, sum = 0
8730 22:53:05.816624 4, 0xFFFF, sum = 0
8731 22:53:05.817206 5, 0xFFFF, sum = 0
8732 22:53:05.819848 6, 0xFFFF, sum = 0
8733 22:53:05.820407 7, 0xFFFF, sum = 0
8734 22:53:05.823373 8, 0xFFFF, sum = 0
8735 22:53:05.823948 9, 0xFFFF, sum = 0
8736 22:53:05.826430 10, 0xFFFF, sum = 0
8737 22:53:05.826946 11, 0xFFFF, sum = 0
8738 22:53:05.829599 12, 0xF7F, sum = 0
8739 22:53:05.830099 13, 0x0, sum = 1
8740 22:53:05.832958 14, 0x0, sum = 2
8741 22:53:05.833550 15, 0x0, sum = 3
8742 22:53:05.836144 16, 0x0, sum = 4
8743 22:53:05.836605 best_step = 14
8744 22:53:05.837001
8745 22:53:05.837337 ==
8746 22:53:05.839897 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 22:53:05.845848 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8748 22:53:05.846402 ==
8749 22:53:05.846819 RX Vref Scan: 0
8750 22:53:05.847158
8751 22:53:05.849396 RX Vref 0 -> 0, step: 1
8752 22:53:05.849850
8753 22:53:05.852640 RX Delay 3 -> 252, step: 4
8754 22:53:05.856069 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8755 22:53:05.859545 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8756 22:53:05.862536 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8757 22:53:05.869393 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8758 22:53:05.872467 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8759 22:53:05.875594 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8760 22:53:05.879518 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8761 22:53:05.882932 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8762 22:53:05.888918 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8763 22:53:05.892147 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8764 22:53:05.895782 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8765 22:53:05.898785 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8766 22:53:05.902715 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8767 22:53:05.909469 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8768 22:53:05.912013 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8769 22:53:05.915563 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8770 22:53:05.916022 ==
8771 22:53:05.918690 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 22:53:05.921949 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8773 22:53:05.925567 ==
8774 22:53:05.926190 DQS Delay:
8775 22:53:05.926671 DQS0 = 0, DQS1 = 0
8776 22:53:05.928907 DQM Delay:
8777 22:53:05.929465 DQM0 = 127, DQM1 = 122
8778 22:53:05.932386 DQ Delay:
8779 22:53:05.935512 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =122
8780 22:53:05.938993 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8781 22:53:05.942199 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =112
8782 22:53:05.945412 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8783 22:53:05.945982
8784 22:53:05.946386
8785 22:53:05.946729
8786 22:53:05.948461 [DramC_TX_OE_Calibration] TA2
8787 22:53:05.952236 Original DQ_B0 (3 6) =30, OEN = 27
8788 22:53:05.955154 Original DQ_B1 (3 6) =30, OEN = 27
8789 22:53:05.958662 24, 0x0, End_B0=24 End_B1=24
8790 22:53:05.959229 25, 0x0, End_B0=25 End_B1=25
8791 22:53:05.961836 26, 0x0, End_B0=26 End_B1=26
8792 22:53:05.965320 27, 0x0, End_B0=27 End_B1=27
8793 22:53:05.968444 28, 0x0, End_B0=28 End_B1=28
8794 22:53:05.971643 29, 0x0, End_B0=29 End_B1=29
8795 22:53:05.972152 30, 0x0, End_B0=30 End_B1=30
8796 22:53:05.975314 31, 0x4141, End_B0=30 End_B1=30
8797 22:53:05.978306 Byte0 end_step=30 best_step=27
8798 22:53:05.981607 Byte1 end_step=30 best_step=27
8799 22:53:05.984858 Byte0 TX OE(2T, 0.5T) = (3, 3)
8800 22:53:05.988573 Byte1 TX OE(2T, 0.5T) = (3, 3)
8801 22:53:05.989135
8802 22:53:05.989496
8803 22:53:05.995017 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8804 22:53:05.998300 CH1 RK1: MR19=303, MR18=1B1B
8805 22:53:06.004884 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8806 22:53:06.008294 [RxdqsGatingPostProcess] freq 1600
8807 22:53:06.011648 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8808 22:53:06.014594 Pre-setting of DQS Precalculation
8809 22:53:06.021961 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8810 22:53:06.028085 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8811 22:53:06.034453 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8812 22:53:06.035011
8813 22:53:06.035367
8814 22:53:06.037623 [Calibration Summary] 3200 Mbps
8815 22:53:06.041108 CH 0, Rank 0
8816 22:53:06.041659 SW Impedance : PASS
8817 22:53:06.044464 DUTY Scan : NO K
8818 22:53:06.045028 ZQ Calibration : PASS
8819 22:53:06.047660 Jitter Meter : NO K
8820 22:53:06.051022 CBT Training : PASS
8821 22:53:06.051478 Write leveling : PASS
8822 22:53:06.054610 RX DQS gating : PASS
8823 22:53:06.057516 RX DQ/DQS(RDDQC) : PASS
8824 22:53:06.058154 TX DQ/DQS : PASS
8825 22:53:06.060985 RX DATLAT : PASS
8826 22:53:06.064427 RX DQ/DQS(Engine): PASS
8827 22:53:06.064972 TX OE : PASS
8828 22:53:06.067314 All Pass.
8829 22:53:06.067769
8830 22:53:06.068160 CH 0, Rank 1
8831 22:53:06.070968 SW Impedance : PASS
8832 22:53:06.071422 DUTY Scan : NO K
8833 22:53:06.074594 ZQ Calibration : PASS
8834 22:53:06.077560 Jitter Meter : NO K
8835 22:53:06.078199 CBT Training : PASS
8836 22:53:06.080913 Write leveling : PASS
8837 22:53:06.084480 RX DQS gating : PASS
8838 22:53:06.085037 RX DQ/DQS(RDDQC) : PASS
8839 22:53:06.087670 TX DQ/DQS : PASS
8840 22:53:06.090440 RX DATLAT : PASS
8841 22:53:06.091159 RX DQ/DQS(Engine): PASS
8842 22:53:06.093856 TX OE : PASS
8843 22:53:06.094359 All Pass.
8844 22:53:06.094724
8845 22:53:06.097321 CH 1, Rank 0
8846 22:53:06.098095 SW Impedance : PASS
8847 22:53:06.100573 DUTY Scan : NO K
8848 22:53:06.101131 ZQ Calibration : PASS
8849 22:53:06.104201 Jitter Meter : NO K
8850 22:53:06.106944 CBT Training : PASS
8851 22:53:06.107425 Write leveling : PASS
8852 22:53:06.110425 RX DQS gating : PASS
8853 22:53:06.113803 RX DQ/DQS(RDDQC) : PASS
8854 22:53:06.114418 TX DQ/DQS : PASS
8855 22:53:06.117466 RX DATLAT : PASS
8856 22:53:06.120331 RX DQ/DQS(Engine): PASS
8857 22:53:06.120791 TX OE : PASS
8858 22:53:06.123736 All Pass.
8859 22:53:06.124198
8860 22:53:06.124555 CH 1, Rank 1
8861 22:53:06.127050 SW Impedance : PASS
8862 22:53:06.127559 DUTY Scan : NO K
8863 22:53:06.130159 ZQ Calibration : PASS
8864 22:53:06.133867 Jitter Meter : NO K
8865 22:53:06.134462 CBT Training : PASS
8866 22:53:06.136779 Write leveling : PASS
8867 22:53:06.140382 RX DQS gating : PASS
8868 22:53:06.140943 RX DQ/DQS(RDDQC) : PASS
8869 22:53:06.143988 TX DQ/DQS : PASS
8870 22:53:06.147216 RX DATLAT : PASS
8871 22:53:06.147772 RX DQ/DQS(Engine): PASS
8872 22:53:06.150129 TX OE : PASS
8873 22:53:06.150590 All Pass.
8874 22:53:06.150949
8875 22:53:06.153264 DramC Write-DBI on
8876 22:53:06.156891 PER_BANK_REFRESH: Hybrid Mode
8877 22:53:06.157452 TX_TRACKING: ON
8878 22:53:06.166740 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8879 22:53:06.173153 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8880 22:53:06.180060 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8881 22:53:06.183411 [FAST_K] Save calibration result to emmc
8882 22:53:06.186676 sync common calibartion params.
8883 22:53:06.190567 sync cbt_mode0:0, 1:0
8884 22:53:06.193107 dram_init: ddr_geometry: 0
8885 22:53:06.193549 dram_init: ddr_geometry: 0
8886 22:53:06.196484 dram_init: ddr_geometry: 0
8887 22:53:06.199892 0:dram_rank_size:80000000
8888 22:53:06.200464 1:dram_rank_size:80000000
8889 22:53:06.206098 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8890 22:53:06.209498 DFS_SHUFFLE_HW_MODE: ON
8891 22:53:06.212974 dramc_set_vcore_voltage set vcore to 725000
8892 22:53:06.216024 Read voltage for 1600, 0
8893 22:53:06.216482 Vio18 = 0
8894 22:53:06.216844 Vcore = 725000
8895 22:53:06.219469 Vdram = 0
8896 22:53:06.219928 Vddq = 0
8897 22:53:06.220286 Vmddr = 0
8898 22:53:06.222918 switch to 3200 Mbps bootup
8899 22:53:06.223474 [DramcRunTimeConfig]
8900 22:53:06.226136 PHYPLL
8901 22:53:06.226596 DPM_CONTROL_AFTERK: ON
8902 22:53:06.229481 PER_BANK_REFRESH: ON
8903 22:53:06.232727 REFRESH_OVERHEAD_REDUCTION: ON
8904 22:53:06.233184 CMD_PICG_NEW_MODE: OFF
8905 22:53:06.236144 XRTWTW_NEW_MODE: ON
8906 22:53:06.236705 XRTRTR_NEW_MODE: ON
8907 22:53:06.239324 TX_TRACKING: ON
8908 22:53:06.239889 RDSEL_TRACKING: OFF
8909 22:53:06.242747 DQS Precalculation for DVFS: ON
8910 22:53:06.246302 RX_TRACKING: OFF
8911 22:53:06.246870 HW_GATING DBG: ON
8912 22:53:06.249229 ZQCS_ENABLE_LP4: ON
8913 22:53:06.249687 RX_PICG_NEW_MODE: ON
8914 22:53:06.252744 TX_PICG_NEW_MODE: ON
8915 22:53:06.255825 ENABLE_RX_DCM_DPHY: ON
8916 22:53:06.256384 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8917 22:53:06.259568 DUMMY_READ_FOR_TRACKING: OFF
8918 22:53:06.262643 !!! SPM_CONTROL_AFTERK: OFF
8919 22:53:06.265677 !!! SPM could not control APHY
8920 22:53:06.266215 IMPEDANCE_TRACKING: ON
8921 22:53:06.268741 TEMP_SENSOR: ON
8922 22:53:06.269212 HW_SAVE_FOR_SR: OFF
8923 22:53:06.272148 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8924 22:53:06.278865 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8925 22:53:06.279321 Read ODT Tracking: ON
8926 22:53:06.282113 Refresh Rate DeBounce: ON
8927 22:53:06.282568 DFS_NO_QUEUE_FLUSH: ON
8928 22:53:06.286104 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8929 22:53:06.289250 ENABLE_DFS_RUNTIME_MRW: OFF
8930 22:53:06.292199 DDR_RESERVE_NEW_MODE: ON
8931 22:53:06.292670 MR_CBT_SWITCH_FREQ: ON
8932 22:53:06.295313 =========================
8933 22:53:06.314651 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8934 22:53:06.317660 dram_init: ddr_geometry: 0
8935 22:53:06.336294 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8936 22:53:06.339461 dram_init: dram init end (result: 0)
8937 22:53:06.345804 DRAM-K: Full calibration passed in 23450 msecs
8938 22:53:06.349355 MRC: failed to locate region type 0.
8939 22:53:06.349925 DRAM rank0 size:0x80000000,
8940 22:53:06.352990 DRAM rank1 size=0x80000000
8941 22:53:06.362631 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8942 22:53:06.369692 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8943 22:53:06.375604 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8944 22:53:06.382825 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8945 22:53:06.385990 DRAM rank0 size:0x80000000,
8946 22:53:06.388772 DRAM rank1 size=0x80000000
8947 22:53:06.389242 CBMEM:
8948 22:53:06.392206 IMD: root @ 0xfffff000 254 entries.
8949 22:53:06.395793 IMD: root @ 0xffffec00 62 entries.
8950 22:53:06.398673 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8951 22:53:06.401999 WARNING: RO_VPD is uninitialized or empty.
8952 22:53:06.409018 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8953 22:53:06.415412 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8954 22:53:06.428198 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8955 22:53:06.439878 BS: romstage times (exec / console): total (unknown) / 22987 ms
8956 22:53:06.440340
8957 22:53:06.440700
8958 22:53:06.449436 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8959 22:53:06.453151 ARM64: Exception handlers installed.
8960 22:53:06.456198 ARM64: Testing exception
8961 22:53:06.459412 ARM64: Done test exception
8962 22:53:06.459828 Enumerating buses...
8963 22:53:06.462793 Show all devs... Before device enumeration.
8964 22:53:06.466058 Root Device: enabled 1
8965 22:53:06.469792 CPU_CLUSTER: 0: enabled 1
8966 22:53:06.470292 CPU: 00: enabled 1
8967 22:53:06.473023 Compare with tree...
8968 22:53:06.473558 Root Device: enabled 1
8969 22:53:06.475970 CPU_CLUSTER: 0: enabled 1
8970 22:53:06.480332 CPU: 00: enabled 1
8971 22:53:06.480888 Root Device scanning...
8972 22:53:06.482705 scan_static_bus for Root Device
8973 22:53:06.486221 CPU_CLUSTER: 0 enabled
8974 22:53:06.489521 scan_static_bus for Root Device done
8975 22:53:06.492642 scan_bus: bus Root Device finished in 8 msecs
8976 22:53:06.493324 done
8977 22:53:06.499550 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8978 22:53:06.502714 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8979 22:53:06.509616 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8980 22:53:06.512619 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8981 22:53:06.516081 Allocating resources...
8982 22:53:06.519060 Reading resources...
8983 22:53:06.522466 Root Device read_resources bus 0 link: 0
8984 22:53:06.522921 DRAM rank0 size:0x80000000,
8985 22:53:06.525931 DRAM rank1 size=0x80000000
8986 22:53:06.529092 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8987 22:53:06.532530 CPU: 00 missing read_resources
8988 22:53:06.539447 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8989 22:53:06.542414 Root Device read_resources bus 0 link: 0 done
8990 22:53:06.542966 Done reading resources.
8991 22:53:06.549117 Show resources in subtree (Root Device)...After reading.
8992 22:53:06.552413 Root Device child on link 0 CPU_CLUSTER: 0
8993 22:53:06.555960 CPU_CLUSTER: 0 child on link 0 CPU: 00
8994 22:53:06.565612 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8995 22:53:06.566196 CPU: 00
8996 22:53:06.569340 Root Device assign_resources, bus 0 link: 0
8997 22:53:06.572354 CPU_CLUSTER: 0 missing set_resources
8998 22:53:06.575679 Root Device assign_resources, bus 0 link: 0 done
8999 22:53:06.578889 Done setting resources.
9000 22:53:06.586096 Show resources in subtree (Root Device)...After assigning values.
9001 22:53:06.589149 Root Device child on link 0 CPU_CLUSTER: 0
9002 22:53:06.592276 CPU_CLUSTER: 0 child on link 0 CPU: 00
9003 22:53:06.602243 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9004 22:53:06.602807 CPU: 00
9005 22:53:06.605591 Done allocating resources.
9006 22:53:06.609052 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9007 22:53:06.612026 Enabling resources...
9008 22:53:06.612584 done.
9009 22:53:06.618360 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9010 22:53:06.618905 Initializing devices...
9011 22:53:06.622414 Root Device init
9012 22:53:06.622968 init hardware done!
9013 22:53:06.625447 0x00000018: ctrlr->caps
9014 22:53:06.628379 52.000 MHz: ctrlr->f_max
9015 22:53:06.628851 0.400 MHz: ctrlr->f_min
9016 22:53:06.631788 0x40ff8080: ctrlr->voltages
9017 22:53:06.635510 sclk: 390625
9018 22:53:06.636075 Bus Width = 1
9019 22:53:06.636441 sclk: 390625
9020 22:53:06.638637 Bus Width = 1
9021 22:53:06.639202 Early init status = 3
9022 22:53:06.645095 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9023 22:53:06.648492 in-header: 03 fc 00 00 01 00 00 00
9024 22:53:06.651585 in-data: 00
9025 22:53:06.654723 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9026 22:53:06.659449 in-header: 03 fd 00 00 00 00 00 00
9027 22:53:06.662494 in-data:
9028 22:53:06.666280 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9029 22:53:06.670275 in-header: 03 fc 00 00 01 00 00 00
9030 22:53:06.673310 in-data: 00
9031 22:53:06.676559 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9032 22:53:06.682908 in-header: 03 fd 00 00 00 00 00 00
9033 22:53:06.686078 in-data:
9034 22:53:06.689074 [SSUSB] Setting up USB HOST controller...
9035 22:53:06.692606 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9036 22:53:06.695710 [SSUSB] phy power-on done.
9037 22:53:06.698824 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9038 22:53:06.705671 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9039 22:53:06.709413 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9040 22:53:06.715785 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9041 22:53:06.722567 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9042 22:53:06.728623 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9043 22:53:06.735311 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9044 22:53:06.742913 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9045 22:53:06.745412 SPM: binary array size = 0x9dc
9046 22:53:06.748751 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9047 22:53:06.755407 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9048 22:53:06.761850 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9049 22:53:06.768241 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9050 22:53:06.771472 configure_display: Starting display init
9051 22:53:06.806070 anx7625_power_on_init: Init interface.
9052 22:53:06.809271 anx7625_disable_pd_protocol: Disabled PD feature.
9053 22:53:06.812343 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9054 22:53:06.840099 anx7625_start_dp_work: Secure OCM version=00
9055 22:53:06.843291 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9056 22:53:06.858202 sp_tx_get_edid_block: EDID Block = 1
9057 22:53:06.960937 Extracted contents:
9058 22:53:06.964058 header: 00 ff ff ff ff ff ff 00
9059 22:53:06.967461 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9060 22:53:06.970920 version: 01 04
9061 22:53:06.974013 basic params: 95 1f 11 78 0a
9062 22:53:06.977150 chroma info: 76 90 94 55 54 90 27 21 50 54
9063 22:53:06.980660 established: 00 00 00
9064 22:53:06.987190 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9065 22:53:06.990991 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9066 22:53:06.997064 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9067 22:53:07.003643 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9068 22:53:07.010413 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9069 22:53:07.013543 extensions: 00
9070 22:53:07.014069 checksum: fb
9071 22:53:07.014450
9072 22:53:07.017311 Manufacturer: IVO Model 57d Serial Number 0
9073 22:53:07.020288 Made week 0 of 2020
9074 22:53:07.023658 EDID version: 1.4
9075 22:53:07.024212 Digital display
9076 22:53:07.027105 6 bits per primary color channel
9077 22:53:07.027571 DisplayPort interface
9078 22:53:07.030132 Maximum image size: 31 cm x 17 cm
9079 22:53:07.033599 Gamma: 220%
9080 22:53:07.034255 Check DPMS levels
9081 22:53:07.037156 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9082 22:53:07.043305 First detailed timing is preferred timing
9083 22:53:07.043863 Established timings supported:
9084 22:53:07.046684 Standard timings supported:
9085 22:53:07.049933 Detailed timings
9086 22:53:07.053429 Hex of detail: 383680a07038204018303c0035ae10000019
9087 22:53:07.060005 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9088 22:53:07.062881 0780 0798 07c8 0820 hborder 0
9089 22:53:07.066596 0438 043b 0447 0458 vborder 0
9090 22:53:07.069626 -hsync -vsync
9091 22:53:07.070126 Did detailed timing
9092 22:53:07.076516 Hex of detail: 000000000000000000000000000000000000
9093 22:53:07.079816 Manufacturer-specified data, tag 0
9094 22:53:07.083358 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9095 22:53:07.086189 ASCII string: InfoVision
9096 22:53:07.089659 Hex of detail: 000000fe00523134304e574635205248200a
9097 22:53:07.092804 ASCII string: R140NWF5 RH
9098 22:53:07.093365 Checksum
9099 22:53:07.096009 Checksum: 0xfb (valid)
9100 22:53:07.099665 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9101 22:53:07.102859 DSI data_rate: 832800000 bps
9102 22:53:07.109696 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9103 22:53:07.112721 anx7625_parse_edid: pixelclock(138800).
9104 22:53:07.116358 hactive(1920), hsync(48), hfp(24), hbp(88)
9105 22:53:07.119295 vactive(1080), vsync(12), vfp(3), vbp(17)
9106 22:53:07.122491 anx7625_dsi_config: config dsi.
9107 22:53:07.129480 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9108 22:53:07.143066 anx7625_dsi_config: success to config DSI
9109 22:53:07.146273 anx7625_dp_start: MIPI phy setup OK.
9110 22:53:07.149675 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9111 22:53:07.152546 mtk_ddp_mode_set invalid vrefresh 60
9112 22:53:07.156392 main_disp_path_setup
9113 22:53:07.156984 ovl_layer_smi_id_en
9114 22:53:07.159763 ovl_layer_smi_id_en
9115 22:53:07.160319 ccorr_config
9116 22:53:07.160685 aal_config
9117 22:53:07.162481 gamma_config
9118 22:53:07.162942 postmask_config
9119 22:53:07.165858 dither_config
9120 22:53:07.169025 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9121 22:53:07.175659 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9122 22:53:07.179144 Root Device init finished in 554 msecs
9123 22:53:07.182536 CPU_CLUSTER: 0 init
9124 22:53:07.189309 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9125 22:53:07.196167 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9126 22:53:07.197041 APU_MBOX 0x190000b0 = 0x10001
9127 22:53:07.198720 APU_MBOX 0x190001b0 = 0x10001
9128 22:53:07.202226 APU_MBOX 0x190005b0 = 0x10001
9129 22:53:07.205708 APU_MBOX 0x190006b0 = 0x10001
9130 22:53:07.212416 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9131 22:53:07.221684 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9132 22:53:07.234746 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9133 22:53:07.241108 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9134 22:53:07.252324 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9135 22:53:07.261714 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9136 22:53:07.265139 CPU_CLUSTER: 0 init finished in 81 msecs
9137 22:53:07.268028 Devices initialized
9138 22:53:07.271262 Show all devs... After init.
9139 22:53:07.271733 Root Device: enabled 1
9140 22:53:07.274859 CPU_CLUSTER: 0: enabled 1
9141 22:53:07.277898 CPU: 00: enabled 1
9142 22:53:07.281300 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9143 22:53:07.284475 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9144 22:53:07.288100 ELOG: NV offset 0x57f000 size 0x1000
9145 22:53:07.294941 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9146 22:53:07.301375 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9147 22:53:07.304963 ELOG: Event(17) added with size 13 at 2024-05-07 22:53:07 UTC
9148 22:53:07.311402 out: cmd=0x121: 03 db 21 01 00 00 00 00
9149 22:53:07.314640 in-header: 03 d7 00 00 2c 00 00 00
9150 22:53:07.327616 in-data: 8c 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9151 22:53:07.331019 ELOG: Event(A1) added with size 10 at 2024-05-07 22:53:07 UTC
9152 22:53:07.337823 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9153 22:53:07.344509 ELOG: Event(A0) added with size 9 at 2024-05-07 22:53:07 UTC
9154 22:53:07.347918 elog_add_boot_reason: Logged dev mode boot
9155 22:53:07.354298 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9156 22:53:07.354866 Finalize devices...
9157 22:53:07.357479 Devices finalized
9158 22:53:07.360737 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9159 22:53:07.364660 Writing coreboot table at 0xffe64000
9160 22:53:07.370602 0. 000000000010a000-0000000000113fff: RAMSTAGE
9161 22:53:07.374133 1. 0000000040000000-00000000400fffff: RAM
9162 22:53:07.377265 2. 0000000040100000-000000004032afff: RAMSTAGE
9163 22:53:07.380660 3. 000000004032b000-00000000545fffff: RAM
9164 22:53:07.384221 4. 0000000054600000-000000005465ffff: BL31
9165 22:53:07.390706 5. 0000000054660000-00000000ffe63fff: RAM
9166 22:53:07.394051 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9167 22:53:07.397198 7. 0000000100000000-000000013fffffff: RAM
9168 22:53:07.400882 Passing 5 GPIOs to payload:
9169 22:53:07.403820 NAME | PORT | POLARITY | VALUE
9170 22:53:07.410740 EC in RW | 0x000000aa | low | undefined
9171 22:53:07.413754 EC interrupt | 0x00000005 | low | undefined
9172 22:53:07.420472 TPM interrupt | 0x000000ab | high | undefined
9173 22:53:07.424115 SD card detect | 0x00000011 | high | undefined
9174 22:53:07.429947 speaker enable | 0x00000093 | high | undefined
9175 22:53:07.433220 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9176 22:53:07.437181 in-header: 03 f8 00 00 02 00 00 00
9177 22:53:07.437753 in-data: 03 00
9178 22:53:07.440134 ADC[4]: Raw value=668958 ID=5
9179 22:53:07.443402 ADC[3]: Raw value=212549 ID=1
9180 22:53:07.443960 RAM Code: 0x51
9181 22:53:07.446681 ADC[6]: Raw value=74778 ID=0
9182 22:53:07.450184 ADC[5]: Raw value=211444 ID=1
9183 22:53:07.450742 SKU Code: 0x1
9184 22:53:07.456561 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 212e
9185 22:53:07.459909 coreboot table: 964 bytes.
9186 22:53:07.463348 IMD ROOT 0. 0xfffff000 0x00001000
9187 22:53:07.466243 IMD SMALL 1. 0xffffe000 0x00001000
9188 22:53:07.469888 RO MCACHE 2. 0xffffc000 0x00001104
9189 22:53:07.472924 CONSOLE 3. 0xfff7c000 0x00080000
9190 22:53:07.476536 FMAP 4. 0xfff7b000 0x00000452
9191 22:53:07.479628 TIME STAMP 5. 0xfff7a000 0x00000910
9192 22:53:07.483148 VBOOT WORK 6. 0xfff66000 0x00014000
9193 22:53:07.486188 RAMOOPS 7. 0xffe66000 0x00100000
9194 22:53:07.489926 COREBOOT 8. 0xffe64000 0x00002000
9195 22:53:07.490539 IMD small region:
9196 22:53:07.492851 IMD ROOT 0. 0xffffec00 0x00000400
9197 22:53:07.496253 VPD 1. 0xffffeb80 0x0000006c
9198 22:53:07.499445 MMC STATUS 2. 0xffffeb60 0x00000004
9199 22:53:07.506093 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9200 22:53:07.506562 Probing TPM: done!
9201 22:53:07.512869 Connected to device vid:did:rid of 1ae0:0028:00
9202 22:53:07.519246 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9203 22:53:07.522819 Initialized TPM device CR50 revision 0
9204 22:53:07.526350 Checking cr50 for pending updates
9205 22:53:07.532568 Reading cr50 TPM mode
9206 22:53:07.540722 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9207 22:53:07.547680 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9208 22:53:07.587616 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9209 22:53:07.590832 Checking segment from ROM address 0x40100000
9210 22:53:07.593902 Checking segment from ROM address 0x4010001c
9211 22:53:07.600710 Loading segment from ROM address 0x40100000
9212 22:53:07.601325 code (compression=0)
9213 22:53:07.610771 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9214 22:53:07.617248 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9215 22:53:07.617725 it's not compressed!
9216 22:53:07.623890 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9217 22:53:07.627518 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9218 22:53:07.648020 Loading segment from ROM address 0x4010001c
9219 22:53:07.648576 Entry Point 0x80000000
9220 22:53:07.651039 Loaded segments
9221 22:53:07.654270 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9222 22:53:07.661153 Jumping to boot code at 0x80000000(0xffe64000)
9223 22:53:07.667858 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9224 22:53:07.674651 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9225 22:53:07.682138 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9226 22:53:07.685631 Checking segment from ROM address 0x40100000
9227 22:53:07.689194 Checking segment from ROM address 0x4010001c
9228 22:53:07.696057 Loading segment from ROM address 0x40100000
9229 22:53:07.696610 code (compression=1)
9230 22:53:07.703021 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9231 22:53:07.712717 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9232 22:53:07.713274 using LZMA
9233 22:53:07.720749 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9234 22:53:07.727823 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9235 22:53:07.730481 Loading segment from ROM address 0x4010001c
9236 22:53:07.730940 Entry Point 0x54601000
9237 22:53:07.733851 Loaded segments
9238 22:53:07.737408 NOTICE: MT8192 bl31_setup
9239 22:53:07.744497 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9240 22:53:07.747662 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9241 22:53:07.751311 WARNING: region 0:
9242 22:53:07.754570 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9243 22:53:07.755126 WARNING: region 1:
9244 22:53:07.761110 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9245 22:53:07.764380 WARNING: region 2:
9246 22:53:07.767716 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9247 22:53:07.771224 WARNING: region 3:
9248 22:53:07.774306 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9249 22:53:07.777639 WARNING: region 4:
9250 22:53:07.784377 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9251 22:53:07.784947 WARNING: region 5:
9252 22:53:07.787504 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9253 22:53:07.791019 WARNING: region 6:
9254 22:53:07.794480 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9255 22:53:07.797197 WARNING: region 7:
9256 22:53:07.800892 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9257 22:53:07.807611 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9258 22:53:07.810635 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9259 22:53:07.814178 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9260 22:53:07.821044 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9261 22:53:07.823951 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9262 22:53:07.827579 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9263 22:53:07.833972 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9264 22:53:07.837569 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9265 22:53:07.843961 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9266 22:53:07.847444 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9267 22:53:07.850517 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9268 22:53:07.857303 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9269 22:53:07.861113 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9270 22:53:07.863893 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9271 22:53:07.870516 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9272 22:53:07.874271 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9273 22:53:07.880884 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9274 22:53:07.884053 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9275 22:53:07.887216 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9276 22:53:07.893932 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9277 22:53:07.897312 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9278 22:53:07.900454 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9279 22:53:07.907462 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9280 22:53:07.911000 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9281 22:53:07.917415 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9282 22:53:07.920650 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9283 22:53:07.924133 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9284 22:53:07.930355 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9285 22:53:07.933807 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9286 22:53:07.940773 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9287 22:53:07.944127 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9288 22:53:07.947362 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9289 22:53:07.953913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9290 22:53:07.957581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9291 22:53:07.960735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9292 22:53:07.964159 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9293 22:53:07.970606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9294 22:53:07.974204 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9295 22:53:07.977264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9296 22:53:07.980809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9297 22:53:07.987272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9298 22:53:07.990875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9299 22:53:07.993673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9300 22:53:07.997807 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9301 22:53:08.003678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9302 22:53:08.006886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9303 22:53:08.010296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9304 22:53:08.013609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9305 22:53:08.020586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9306 22:53:08.023848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9307 22:53:08.030277 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9308 22:53:08.033737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9309 22:53:08.040057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9310 22:53:08.043443 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9311 22:53:08.046959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9312 22:53:08.053740 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9313 22:53:08.057012 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9314 22:53:08.064124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9315 22:53:08.066913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9316 22:53:08.073470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9317 22:53:08.077222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9318 22:53:08.083379 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9319 22:53:08.086799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9320 22:53:08.090009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9321 22:53:08.097275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9322 22:53:08.100492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9323 22:53:08.106680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9324 22:53:08.110252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9325 22:53:08.116605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9326 22:53:08.119832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9327 22:53:08.123281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9328 22:53:08.129697 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9329 22:53:08.133886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9330 22:53:08.140102 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9331 22:53:08.143248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9332 22:53:08.150122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9333 22:53:08.153518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9334 22:53:08.159816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9335 22:53:08.163286 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9336 22:53:08.166747 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9337 22:53:08.173109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9338 22:53:08.176262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9339 22:53:08.183114 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9340 22:53:08.186389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9341 22:53:08.193000 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9342 22:53:08.196253 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9343 22:53:08.199938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9344 22:53:08.206133 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9345 22:53:08.209343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9346 22:53:08.216173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9347 22:53:08.219274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9348 22:53:08.225902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9349 22:53:08.229418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9350 22:53:08.236305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9351 22:53:08.239130 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9352 22:53:08.242771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9353 22:53:08.249344 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9354 22:53:08.252807 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9355 22:53:08.256309 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9356 22:53:08.259742 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9357 22:53:08.266202 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9358 22:53:08.269305 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9359 22:53:08.275973 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9360 22:53:08.279335 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9361 22:53:08.282690 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9362 22:53:08.289500 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9363 22:53:08.292648 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9364 22:53:08.299242 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9365 22:53:08.302612 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9366 22:53:08.305814 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9367 22:53:08.312836 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9368 22:53:08.315879 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9369 22:53:08.322906 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9370 22:53:08.325643 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9371 22:53:08.328980 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9372 22:53:08.336201 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9373 22:53:08.339116 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9374 22:53:08.342259 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9375 22:53:08.349154 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9376 22:53:08.352660 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9377 22:53:08.356227 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9378 22:53:08.359301 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9379 22:53:08.362688 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9380 22:53:08.369280 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9381 22:53:08.372484 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9382 22:53:08.378750 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9383 22:53:08.382673 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9384 22:53:08.386058 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9385 22:53:08.392519 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9386 22:53:08.395480 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9387 22:53:08.402205 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9388 22:53:08.405503 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9389 22:53:08.409269 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9390 22:53:08.415701 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9391 22:53:08.419030 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9392 22:53:08.425488 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9393 22:53:08.428774 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9394 22:53:08.432133 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9395 22:53:08.438774 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9396 22:53:08.442091 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9397 22:53:08.445593 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9398 22:53:08.452080 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9399 22:53:08.455448 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9400 22:53:08.462186 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9401 22:53:08.465536 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9402 22:53:08.468900 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9403 22:53:08.475450 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9404 22:53:08.478929 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9405 22:53:08.485556 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9406 22:53:08.488829 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9407 22:53:08.492435 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9408 22:53:08.498891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9409 22:53:08.502166 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9410 22:53:08.505321 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9411 22:53:08.512078 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9412 22:53:08.515306 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9413 22:53:08.522129 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9414 22:53:08.525294 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9415 22:53:08.528645 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9416 22:53:08.535218 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9417 22:53:08.538832 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9418 22:53:08.545248 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9419 22:53:08.548508 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9420 22:53:08.552087 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9421 22:53:08.558276 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9422 22:53:08.561805 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9423 22:53:08.568246 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9424 22:53:08.571786 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9425 22:53:08.575231 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9426 22:53:08.581571 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9427 22:53:08.584822 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9428 22:53:08.591668 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9429 22:53:08.594984 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9430 22:53:08.598135 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9431 22:53:08.604720 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9432 22:53:08.608098 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9433 22:53:08.614718 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9434 22:53:08.617766 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9435 22:53:08.621301 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9436 22:53:08.628311 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9437 22:53:08.631153 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9438 22:53:08.637683 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9439 22:53:08.640945 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9440 22:53:08.644126 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9441 22:53:08.651186 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9442 22:53:08.654323 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9443 22:53:08.660737 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9444 22:53:08.664034 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9445 22:53:08.667191 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9446 22:53:08.673968 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9447 22:53:08.677153 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9448 22:53:08.683889 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9449 22:53:08.687054 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9450 22:53:08.690724 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9451 22:53:08.697226 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9452 22:53:08.700845 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9453 22:53:08.707131 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9454 22:53:08.710399 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9455 22:53:08.717127 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9456 22:53:08.720215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9457 22:53:08.723636 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9458 22:53:08.730400 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9459 22:53:08.733346 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9460 22:53:08.740539 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9461 22:53:08.743148 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9462 22:53:08.749973 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9463 22:53:08.753405 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9464 22:53:08.756650 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9465 22:53:08.763162 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9466 22:53:08.766299 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9467 22:53:08.773084 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9468 22:53:08.776119 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9469 22:53:08.782911 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9470 22:53:08.786176 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9471 22:53:08.789382 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9472 22:53:08.796558 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9473 22:53:08.799884 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9474 22:53:08.806085 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9475 22:53:08.809339 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9476 22:53:08.816068 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9477 22:53:08.819079 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9478 22:53:08.822538 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9479 22:53:08.829140 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9480 22:53:08.832497 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9481 22:53:08.838850 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9482 22:53:08.842142 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9483 22:53:08.849344 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9484 22:53:08.852355 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9485 22:53:08.855682 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9486 22:53:08.862169 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9487 22:53:08.866100 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9488 22:53:08.869267 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9489 22:53:08.871811 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9490 22:53:08.875138 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9491 22:53:08.881771 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9492 22:53:08.885532 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9493 22:53:08.892247 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9494 22:53:08.895000 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9495 22:53:08.898351 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9496 22:53:08.905419 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9497 22:53:08.908379 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9498 22:53:08.914834 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9499 22:53:08.918468 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9500 22:53:08.921555 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9501 22:53:08.928599 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9502 22:53:08.931258 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9503 22:53:08.934717 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9504 22:53:08.941383 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9505 22:53:08.945381 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9506 22:53:08.948023 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9507 22:53:08.954582 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9508 22:53:08.957796 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9509 22:53:08.964942 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9510 22:53:08.968046 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9511 22:53:08.971209 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9512 22:53:08.977814 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9513 22:53:08.981387 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9514 22:53:08.987485 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9515 22:53:08.991000 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9516 22:53:08.994242 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9517 22:53:09.001094 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9518 22:53:09.004135 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9519 22:53:09.007484 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9520 22:53:09.014101 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9521 22:53:09.017557 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9522 22:53:09.021079 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9523 22:53:09.027231 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9524 22:53:09.030550 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9525 22:53:09.037162 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9526 22:53:09.040238 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9527 22:53:09.043770 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9528 22:53:09.047138 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9529 22:53:09.050554 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9530 22:53:09.054132 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9531 22:53:09.061038 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9532 22:53:09.063638 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9533 22:53:09.067214 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9534 22:53:09.073676 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9535 22:53:09.077006 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9536 22:53:09.080461 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9537 22:53:09.087434 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9538 22:53:09.090422 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9539 22:53:09.093623 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9540 22:53:09.100277 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9541 22:53:09.103962 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9542 22:53:09.106868 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9543 22:53:09.113400 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9544 22:53:09.116849 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9545 22:53:09.123408 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9546 22:53:09.126525 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9547 22:53:09.130136 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9548 22:53:09.136645 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9549 22:53:09.139698 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9550 22:53:09.146390 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9551 22:53:09.150182 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9552 22:53:09.156650 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9553 22:53:09.159463 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9554 22:53:09.162942 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9555 22:53:09.169705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9556 22:53:09.173025 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9557 22:53:09.179300 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9558 22:53:09.182720 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9559 22:53:09.189355 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9560 22:53:09.193101 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9561 22:53:09.196494 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9562 22:53:09.202461 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9563 22:53:09.205764 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9564 22:53:09.212696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9565 22:53:09.216289 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9566 22:53:09.219534 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9567 22:53:09.225947 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9568 22:53:09.229220 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9569 22:53:09.235628 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9570 22:53:09.239032 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9571 22:53:09.242274 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9572 22:53:09.249087 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9573 22:53:09.252634 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9574 22:53:09.258970 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9575 22:53:09.262176 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9576 22:53:09.268931 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9577 22:53:09.272008 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9578 22:53:09.275481 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9579 22:53:09.282157 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9580 22:53:09.285378 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9581 22:53:09.291948 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9582 22:53:09.295035 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9583 22:53:09.298630 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9584 22:53:09.305214 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9585 22:53:09.308527 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9586 22:53:09.314910 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9587 22:53:09.318356 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9588 22:53:09.321535 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9589 22:53:09.328232 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9590 22:53:09.331498 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9591 22:53:09.338005 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9592 22:53:09.341430 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9593 22:53:09.348450 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9594 22:53:09.351584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9595 22:53:09.354943 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9596 22:53:09.361459 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9597 22:53:09.365272 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9598 22:53:09.371885 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9599 22:53:09.374461 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9600 22:53:09.378365 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9601 22:53:09.384789 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9602 22:53:09.388063 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9603 22:53:09.394632 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9604 22:53:09.397815 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9605 22:53:09.404474 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9606 22:53:09.407594 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9607 22:53:09.410849 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9608 22:53:09.417699 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9609 22:53:09.420663 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9610 22:53:09.427311 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9611 22:53:09.430509 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9612 22:53:09.437245 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9613 22:53:09.440301 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9614 22:53:09.443957 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9615 22:53:09.450354 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9616 22:53:09.453699 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9617 22:53:09.460769 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9618 22:53:09.463650 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9619 22:53:09.470296 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9620 22:53:09.473802 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9621 22:53:09.480080 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9622 22:53:09.483380 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9623 22:53:09.486781 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9624 22:53:09.493417 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9625 22:53:09.496512 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9626 22:53:09.503538 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9627 22:53:09.506736 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9628 22:53:09.512808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9629 22:53:09.516653 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9630 22:53:09.523109 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9631 22:53:09.526762 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9632 22:53:09.529767 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9633 22:53:09.536482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9634 22:53:09.539541 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9635 22:53:09.545930 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9636 22:53:09.549403 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9637 22:53:09.555909 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9638 22:53:09.559385 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9639 22:53:09.562512 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9640 22:53:09.569262 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9641 22:53:09.572604 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9642 22:53:09.578817 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9643 22:53:09.582249 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9644 22:53:09.588945 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9645 22:53:09.592184 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9646 22:53:09.598927 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9647 22:53:09.602523 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9648 22:53:09.609109 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9649 22:53:09.611878 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9650 22:53:09.615454 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9651 22:53:09.622081 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9652 22:53:09.625447 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9653 22:53:09.632059 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9654 22:53:09.635508 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9655 22:53:09.642143 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9656 22:53:09.645630 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9657 22:53:09.649006 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9658 22:53:09.655100 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9659 22:53:09.658498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9660 22:53:09.665000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9661 22:53:09.668766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9662 22:53:09.672028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9663 22:53:09.678865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9664 22:53:09.681771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9665 22:53:09.688668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9666 22:53:09.692049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9667 22:53:09.698361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9668 22:53:09.701710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9669 22:53:09.708304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9670 22:53:09.711479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9671 22:53:09.718131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9672 22:53:09.721464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9673 22:53:09.727738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9674 22:53:09.731329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9675 22:53:09.738054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9676 22:53:09.741418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9677 22:53:09.748122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9678 22:53:09.751332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9679 22:53:09.757853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9680 22:53:09.761174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9681 22:53:09.767916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9682 22:53:09.771263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9683 22:53:09.777558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9684 22:53:09.780984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9685 22:53:09.787693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9686 22:53:09.790861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9687 22:53:09.797638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9688 22:53:09.800571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9689 22:53:09.807292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9690 22:53:09.810645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9691 22:53:09.817116 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9692 22:53:09.817579 INFO: [APUAPC] vio 0
9693 22:53:09.824063 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9694 22:53:09.827490 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9695 22:53:09.830734 INFO: [APUAPC] D0_APC_0: 0x400510
9696 22:53:09.834204 INFO: [APUAPC] D0_APC_1: 0x0
9697 22:53:09.837156 INFO: [APUAPC] D0_APC_2: 0x1540
9698 22:53:09.840602 INFO: [APUAPC] D0_APC_3: 0x0
9699 22:53:09.843852 INFO: [APUAPC] D1_APC_0: 0xffffffff
9700 22:53:09.847032 INFO: [APUAPC] D1_APC_1: 0xffffffff
9701 22:53:09.850417 INFO: [APUAPC] D1_APC_2: 0x3fffff
9702 22:53:09.853905 INFO: [APUAPC] D1_APC_3: 0x0
9703 22:53:09.857333 INFO: [APUAPC] D2_APC_0: 0xffffffff
9704 22:53:09.860561 INFO: [APUAPC] D2_APC_1: 0xffffffff
9705 22:53:09.864257 INFO: [APUAPC] D2_APC_2: 0x3fffff
9706 22:53:09.867009 INFO: [APUAPC] D2_APC_3: 0x0
9707 22:53:09.870688 INFO: [APUAPC] D3_APC_0: 0xffffffff
9708 22:53:09.873597 INFO: [APUAPC] D3_APC_1: 0xffffffff
9709 22:53:09.877082 INFO: [APUAPC] D3_APC_2: 0x3fffff
9710 22:53:09.880220 INFO: [APUAPC] D3_APC_3: 0x0
9711 22:53:09.883609 INFO: [APUAPC] D4_APC_0: 0xffffffff
9712 22:53:09.886867 INFO: [APUAPC] D4_APC_1: 0xffffffff
9713 22:53:09.890703 INFO: [APUAPC] D4_APC_2: 0x3fffff
9714 22:53:09.891275 INFO: [APUAPC] D4_APC_3: 0x0
9715 22:53:09.893685 INFO: [APUAPC] D5_APC_0: 0xffffffff
9716 22:53:09.900291 INFO: [APUAPC] D5_APC_1: 0xffffffff
9717 22:53:09.903773 INFO: [APUAPC] D5_APC_2: 0x3fffff
9718 22:53:09.904337 INFO: [APUAPC] D5_APC_3: 0x0
9719 22:53:09.906845 INFO: [APUAPC] D6_APC_0: 0xffffffff
9720 22:53:09.913241 INFO: [APUAPC] D6_APC_1: 0xffffffff
9721 22:53:09.917019 INFO: [APUAPC] D6_APC_2: 0x3fffff
9722 22:53:09.917562 INFO: [APUAPC] D6_APC_3: 0x0
9723 22:53:09.920289 INFO: [APUAPC] D7_APC_0: 0xffffffff
9724 22:53:09.923350 INFO: [APUAPC] D7_APC_1: 0xffffffff
9725 22:53:09.926612 INFO: [APUAPC] D7_APC_2: 0x3fffff
9726 22:53:09.929947 INFO: [APUAPC] D7_APC_3: 0x0
9727 22:53:09.933278 INFO: [APUAPC] D8_APC_0: 0xffffffff
9728 22:53:09.936492 INFO: [APUAPC] D8_APC_1: 0xffffffff
9729 22:53:09.939966 INFO: [APUAPC] D8_APC_2: 0x3fffff
9730 22:53:09.943240 INFO: [APUAPC] D8_APC_3: 0x0
9731 22:53:09.946624 INFO: [APUAPC] D9_APC_0: 0xffffffff
9732 22:53:09.950192 INFO: [APUAPC] D9_APC_1: 0xffffffff
9733 22:53:09.953041 INFO: [APUAPC] D9_APC_2: 0x3fffff
9734 22:53:09.956353 INFO: [APUAPC] D9_APC_3: 0x0
9735 22:53:09.959455 INFO: [APUAPC] D10_APC_0: 0xffffffff
9736 22:53:09.963049 INFO: [APUAPC] D10_APC_1: 0xffffffff
9737 22:53:09.966289 INFO: [APUAPC] D10_APC_2: 0x3fffff
9738 22:53:09.969811 INFO: [APUAPC] D10_APC_3: 0x0
9739 22:53:09.972924 INFO: [APUAPC] D11_APC_0: 0xffffffff
9740 22:53:09.976045 INFO: [APUAPC] D11_APC_1: 0xffffffff
9741 22:53:09.979291 INFO: [APUAPC] D11_APC_2: 0x3fffff
9742 22:53:09.982578 INFO: [APUAPC] D11_APC_3: 0x0
9743 22:53:09.986277 INFO: [APUAPC] D12_APC_0: 0xffffffff
9744 22:53:09.989523 INFO: [APUAPC] D12_APC_1: 0xffffffff
9745 22:53:09.992881 INFO: [APUAPC] D12_APC_2: 0x3fffff
9746 22:53:09.996253 INFO: [APUAPC] D12_APC_3: 0x0
9747 22:53:09.999498 INFO: [APUAPC] D13_APC_0: 0xffffffff
9748 22:53:10.002553 INFO: [APUAPC] D13_APC_1: 0xffffffff
9749 22:53:10.005696 INFO: [APUAPC] D13_APC_2: 0x3fffff
9750 22:53:10.009088 INFO: [APUAPC] D13_APC_3: 0x0
9751 22:53:10.012591 INFO: [APUAPC] D14_APC_0: 0xffffffff
9752 22:53:10.016140 INFO: [APUAPC] D14_APC_1: 0xffffffff
9753 22:53:10.022517 INFO: [APUAPC] D14_APC_2: 0x3fffff
9754 22:53:10.023085 INFO: [APUAPC] D14_APC_3: 0x0
9755 22:53:10.025802 INFO: [APUAPC] D15_APC_0: 0xffffffff
9756 22:53:10.032262 INFO: [APUAPC] D15_APC_1: 0xffffffff
9757 22:53:10.035575 INFO: [APUAPC] D15_APC_2: 0x3fffff
9758 22:53:10.036054 INFO: [APUAPC] D15_APC_3: 0x0
9759 22:53:10.038727 INFO: [APUAPC] APC_CON: 0x4
9760 22:53:10.042230 INFO: [NOCDAPC] D0_APC_0: 0x0
9761 22:53:10.045514 INFO: [NOCDAPC] D0_APC_1: 0x0
9762 22:53:10.048709 INFO: [NOCDAPC] D1_APC_0: 0x0
9763 22:53:10.051772 INFO: [NOCDAPC] D1_APC_1: 0xfff
9764 22:53:10.055141 INFO: [NOCDAPC] D2_APC_0: 0x0
9765 22:53:10.058804 INFO: [NOCDAPC] D2_APC_1: 0xfff
9766 22:53:10.062153 INFO: [NOCDAPC] D3_APC_0: 0x0
9767 22:53:10.065483 INFO: [NOCDAPC] D3_APC_1: 0xfff
9768 22:53:10.066083 INFO: [NOCDAPC] D4_APC_0: 0x0
9769 22:53:10.068448 INFO: [NOCDAPC] D4_APC_1: 0xfff
9770 22:53:10.072183 INFO: [NOCDAPC] D5_APC_0: 0x0
9771 22:53:10.075270 INFO: [NOCDAPC] D5_APC_1: 0xfff
9772 22:53:10.079137 INFO: [NOCDAPC] D6_APC_0: 0x0
9773 22:53:10.081665 INFO: [NOCDAPC] D6_APC_1: 0xfff
9774 22:53:10.085392 INFO: [NOCDAPC] D7_APC_0: 0x0
9775 22:53:10.088333 INFO: [NOCDAPC] D7_APC_1: 0xfff
9776 22:53:10.091774 INFO: [NOCDAPC] D8_APC_0: 0x0
9777 22:53:10.095538 INFO: [NOCDAPC] D8_APC_1: 0xfff
9778 22:53:10.098812 INFO: [NOCDAPC] D9_APC_0: 0x0
9779 22:53:10.101707 INFO: [NOCDAPC] D9_APC_1: 0xfff
9780 22:53:10.102321 INFO: [NOCDAPC] D10_APC_0: 0x0
9781 22:53:10.104760 INFO: [NOCDAPC] D10_APC_1: 0xfff
9782 22:53:10.108514 INFO: [NOCDAPC] D11_APC_0: 0x0
9783 22:53:10.111260 INFO: [NOCDAPC] D11_APC_1: 0xfff
9784 22:53:10.114579 INFO: [NOCDAPC] D12_APC_0: 0x0
9785 22:53:10.117786 INFO: [NOCDAPC] D12_APC_1: 0xfff
9786 22:53:10.121165 INFO: [NOCDAPC] D13_APC_0: 0x0
9787 22:53:10.124602 INFO: [NOCDAPC] D13_APC_1: 0xfff
9788 22:53:10.127890 INFO: [NOCDAPC] D14_APC_0: 0x0
9789 22:53:10.131118 INFO: [NOCDAPC] D14_APC_1: 0xfff
9790 22:53:10.134393 INFO: [NOCDAPC] D15_APC_0: 0x0
9791 22:53:10.137852 INFO: [NOCDAPC] D15_APC_1: 0xfff
9792 22:53:10.140874 INFO: [NOCDAPC] APC_CON: 0x4
9793 22:53:10.144294 INFO: [APUAPC] set_apusys_apc done
9794 22:53:10.147554 INFO: [DEVAPC] devapc_init done
9795 22:53:10.150919 INFO: GICv3 without legacy support detected.
9796 22:53:10.154352 INFO: ARM GICv3 driver initialized in EL3
9797 22:53:10.157422 INFO: Maximum SPI INTID supported: 639
9798 22:53:10.160700 INFO: BL31: Initializing runtime services
9799 22:53:10.167738 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9800 22:53:10.170734 INFO: SPM: enable CPC mode
9801 22:53:10.177346 INFO: mcdi ready for mcusys-off-idle and system suspend
9802 22:53:10.180601 INFO: BL31: Preparing for EL3 exit to normal world
9803 22:53:10.183835 INFO: Entry point address = 0x80000000
9804 22:53:10.187582 INFO: SPSR = 0x8
9805 22:53:10.192431
9806 22:53:10.192991
9807 22:53:10.193360
9808 22:53:10.195479 Starting depthcharge on Spherion...
9809 22:53:10.196042
9810 22:53:10.196411 Wipe memory regions:
9811 22:53:10.196753
9812 22:53:10.199323 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9813 22:53:10.199884 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9814 22:53:10.200344 Setting prompt string to ['asurada:']
9815 22:53:10.200865 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9816 22:53:10.201599 [0x00000040000000, 0x00000054600000)
9817 22:53:10.321156
9818 22:53:10.321690 [0x00000054660000, 0x00000080000000)
9819 22:53:10.581413
9820 22:53:10.581949 [0x000000821a7280, 0x000000ffe64000)
9821 22:53:11.326314
9822 22:53:11.326879 [0x00000100000000, 0x00000140000000)
9823 22:53:11.706834
9824 22:53:11.710115 Initializing XHCI USB controller at 0x11200000.
9825 22:53:12.747861
9826 22:53:12.751219 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9827 22:53:12.751793
9828 22:53:12.752278
9829 22:53:12.752726
9830 22:53:12.753667 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9832 22:53:12.855270 asurada: tftpboot 192.168.201.1 13683711/tftp-deploy-rojg5qzj/kernel/image.itb 13683711/tftp-deploy-rojg5qzj/kernel/cmdline
9833 22:53:12.855949 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9834 22:53:12.856508 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9835 22:53:12.861102 tftpboot 192.168.201.1 13683711/tftp-deploy-rojg5qzj/kernel/image.ittp-deploy-rojg5qzj/kernel/cmdline
9836 22:53:12.861674
9837 22:53:12.862084 Waiting for link
9838 22:53:13.021508
9839 22:53:13.022124 R8152: Initializing
9840 22:53:13.022505
9841 22:53:13.025736 Version 9 (ocp_data = 6010)
9842 22:53:13.026454
9843 22:53:13.027814 R8152: Done initializing
9844 22:53:13.028276
9845 22:53:13.028769 Adding net device
9846 22:53:14.930847
9847 22:53:14.931425 done.
9848 22:53:14.931818
9849 22:53:14.932191 MAC: 00:e0:4c:68:03:bd
9850 22:53:14.932523
9851 22:53:14.933574 Sending DHCP discover... done.
9852 22:53:14.934240
9853 22:53:14.936919 Waiting for reply... done.
9854 22:53:14.937499
9855 22:53:14.940479 Sending DHCP request... done.
9856 22:53:14.941071
9857 22:53:14.943976 Waiting for reply... done.
9858 22:53:14.944566
9859 22:53:14.945070 My ip is 192.168.201.16
9860 22:53:14.945556
9861 22:53:14.947302 The DHCP server ip is 192.168.201.1
9862 22:53:14.947862
9863 22:53:14.954180 TFTP server IP predefined by user: 192.168.201.1
9864 22:53:14.954768
9865 22:53:14.960826 Bootfile predefined by user: 13683711/tftp-deploy-rojg5qzj/kernel/image.itb
9866 22:53:14.961382
9867 22:53:14.964063 Sending tftp read request... done.
9868 22:53:14.964608
9869 22:53:14.970795 Waiting for the transfer...
9870 22:53:14.971394
9871 22:53:15.361117 00000000 ################################################################
9872 22:53:15.361621
9873 22:53:15.734476 00080000 ################################################################
9874 22:53:15.734612
9875 22:53:16.009329 00100000 ################################################################
9876 22:53:16.009464
9877 22:53:16.270958 00180000 ################################################################
9878 22:53:16.271096
9879 22:53:16.532792 00200000 ################################################################
9880 22:53:16.532926
9881 22:53:16.790355 00280000 ################################################################
9882 22:53:16.790487
9883 22:53:17.066909 00300000 ################################################################
9884 22:53:17.067049
9885 22:53:17.338980 00380000 ################################################################
9886 22:53:17.339124
9887 22:53:17.621527 00400000 ################################################################
9888 22:53:17.621674
9889 22:53:17.913198 00480000 ################################################################
9890 22:53:17.913338
9891 22:53:18.172531 00500000 ################################################################
9892 22:53:18.172665
9893 22:53:18.435262 00580000 ################################################################
9894 22:53:18.435403
9895 22:53:18.729622 00600000 ################################################################
9896 22:53:18.729762
9897 22:53:19.019605 00680000 ################################################################
9898 22:53:19.019739
9899 22:53:19.315138 00700000 ################################################################
9900 22:53:19.315274
9901 22:53:19.599198 00780000 ################################################################
9902 22:53:19.599340
9903 22:53:19.886995 00800000 ################################################################
9904 22:53:19.887150
9905 22:53:20.171331 00880000 ################################################################
9906 22:53:20.171475
9907 22:53:20.467164 00900000 ################################################################
9908 22:53:20.467304
9909 22:53:20.761988 00980000 ################################################################
9910 22:53:20.762163
9911 22:53:21.058267 00a00000 ################################################################
9912 22:53:21.058401
9913 22:53:21.352555 00a80000 ################################################################
9914 22:53:21.352696
9915 22:53:21.641869 00b00000 ################################################################
9916 22:53:21.642003
9917 22:53:21.930705 00b80000 ################################################################
9918 22:53:21.930853
9919 22:53:22.209813 00c00000 ################################################################
9920 22:53:22.209954
9921 22:53:22.488734 00c80000 ################################################################
9922 22:53:22.488872
9923 22:53:22.785290 00d00000 ################################################################
9924 22:53:22.785423
9925 22:53:23.056216 00d80000 ################################################################
9926 22:53:23.056368
9927 22:53:23.307326 00e00000 ################################################################
9928 22:53:23.307455
9929 22:53:23.575329 00e80000 ################################################################
9930 22:53:23.575464
9931 22:53:23.833454 00f00000 ################################################################
9932 22:53:23.833587
9933 22:53:24.107369 00f80000 ################################################################
9934 22:53:24.107516
9935 22:53:24.357035 01000000 ################################################################
9936 22:53:24.357182
9937 22:53:24.631711 01080000 ################################################################
9938 22:53:24.631844
9939 22:53:24.927984 01100000 ################################################################
9940 22:53:24.928123
9941 22:53:25.197355 01180000 ################################################################
9942 22:53:25.197493
9943 22:53:25.475817 01200000 ################################################################
9944 22:53:25.475970
9945 22:53:25.741005 01280000 ################################################################
9946 22:53:25.741141
9947 22:53:26.037428 01300000 ################################################################
9948 22:53:26.037566
9949 22:53:26.303954 01380000 ################################################################
9950 22:53:26.304089
9951 22:53:26.577082 01400000 ################################################################
9952 22:53:26.577225
9953 22:53:26.842883 01480000 ################################################################
9954 22:53:26.843017
9955 22:53:27.140117 01500000 ################################################################
9956 22:53:27.140256
9957 22:53:27.436817 01580000 ################################################################
9958 22:53:27.436954
9959 22:53:27.715480 01600000 ################################################################
9960 22:53:27.715633
9961 22:53:27.997312 01680000 ################################################################
9962 22:53:27.997454
9963 22:53:28.288731 01700000 ################################################################
9964 22:53:28.288866
9965 22:53:28.579509 01780000 ################################################################
9966 22:53:28.579656
9967 22:53:28.853454 01800000 ################################################################
9968 22:53:28.853599
9969 22:53:29.141163 01880000 ################################################################
9970 22:53:29.141306
9971 22:53:29.415587 01900000 ################################################################
9972 22:53:29.415722
9973 22:53:29.684841 01980000 ################################################################
9974 22:53:29.684976
9975 22:53:29.941712 01a00000 ################################################################
9976 22:53:29.941847
9977 22:53:30.190143 01a80000 ################################################################
9978 22:53:30.190294
9979 22:53:30.440557 01b00000 ################################################################
9980 22:53:30.440695
9981 22:53:30.705909 01b80000 ################################################################
9982 22:53:30.706057
9983 22:53:30.956758 01c00000 ################################################################
9984 22:53:30.956887
9985 22:53:31.207735 01c80000 ################################################################
9986 22:53:31.207868
9987 22:53:31.463098 01d00000 ################################################################
9988 22:53:31.463242
9989 22:53:31.722879 01d80000 ################################################################
9990 22:53:31.723025
9991 22:53:31.926388 01e00000 ############################################## done.
9992 22:53:31.926534
9993 22:53:31.929532 The bootfile was 31833546 bytes long.
9994 22:53:31.929622
9995 22:53:31.933090 Sending tftp read request... done.
9996 22:53:31.933272
9997 22:53:31.933371 Waiting for the transfer...
9998 22:53:31.933458
9999 22:53:31.936399 00000000 # done.
10000 22:53:31.936584
10001 22:53:31.942957 Command line loaded dynamically from TFTP file: 13683711/tftp-deploy-rojg5qzj/kernel/cmdline
10002 22:53:31.943150
10003 22:53:31.965969 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683711/extract-nfsrootfs-_8ka395z,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10004 22:53:31.966262
10005 22:53:31.966448 Loading FIT.
10006 22:53:31.966601
10007 22:53:31.969227 Image ramdisk-1 has 18724700 bytes.
10008 22:53:31.969430
10009 22:53:31.972813 Image fdt-1 has 47258 bytes.
10010 22:53:31.973151
10011 22:53:31.976125 Image kernel-1 has 13059555 bytes.
10012 22:53:31.976500
10013 22:53:31.986084 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10014 22:53:31.986629
10015 22:53:32.003288 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10016 22:53:32.003881
10017 22:53:32.009386 Choosing best match conf-1 for compat google,spherion-rev3.
10018 22:53:32.009854
10019 22:53:32.016659 Connected to device vid:did:rid of 1ae0:0028:00
10020 22:53:32.023661
10021 22:53:32.026892 tpm_get_response: command 0x17b, return code 0x0
10022 22:53:32.027456
10023 22:53:32.030582 ec_init: CrosEC protocol v3 supported (256, 248)
10024 22:53:32.035322
10025 22:53:32.038450 tpm_cleanup: add release locality here.
10026 22:53:32.039013
10027 22:53:32.039378 Shutting down all USB controllers.
10028 22:53:32.041981
10029 22:53:32.042589 Removing current net device
10030 22:53:32.042956
10031 22:53:32.048567 Exiting depthcharge with code 4 at timestamp: 50113351
10032 22:53:32.049123
10033 22:53:32.051652 LZMA decompressing kernel-1 to 0x821a6718
10034 22:53:32.052107
10035 22:53:32.054831 LZMA decompressing kernel-1 to 0x40000000
10036 22:53:33.665109
10037 22:53:33.665657 jumping to kernel
10038 22:53:33.667493 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10039 22:53:33.668040 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10040 22:53:33.668443 Setting prompt string to ['Linux version [0-9]']
10041 22:53:33.668813 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 22:53:33.669179 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10043 22:53:33.716087
10044 22:53:33.719154 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10045 22:53:33.723262 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10046 22:53:33.723761 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10047 22:53:33.724179 Setting prompt string to []
10048 22:53:33.724600 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10049 22:53:33.724982 Using line separator: #'\n'#
10050 22:53:33.725363 No login prompt set.
10051 22:53:33.725727 Parsing kernel messages
10052 22:53:33.726150 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10053 22:53:33.726725 [login-action] Waiting for messages, (timeout 00:04:03)
10054 22:53:33.727079 Waiting using forced prompt support (timeout 00:02:01)
10055 22:53:33.742733 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10056 22:53:33.745850 [ 0.000000] random: crng init done
10057 22:53:33.752566 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10058 22:53:33.755682 [ 0.000000] efi: UEFI not found.
10059 22:53:33.762725 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10060 22:53:33.768976 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10061 22:53:33.778822 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10062 22:53:33.789180 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10063 22:53:33.795292 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10064 22:53:33.802289 [ 0.000000] printk: bootconsole [mtk8250] enabled
10065 22:53:33.808472 [ 0.000000] NUMA: No NUMA configuration found
10066 22:53:33.815200 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10067 22:53:33.818285 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10068 22:53:33.821972 [ 0.000000] Zone ranges:
10069 22:53:33.828380 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10070 22:53:33.831750 [ 0.000000] DMA32 empty
10071 22:53:33.838288 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10072 22:53:33.841547 [ 0.000000] Movable zone start for each node
10073 22:53:33.845105 [ 0.000000] Early memory node ranges
10074 22:53:33.851197 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10075 22:53:33.858163 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10076 22:53:33.864614 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10077 22:53:33.871161 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10078 22:53:33.877781 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10079 22:53:33.884461 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10080 22:53:33.914890 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10081 22:53:33.921676 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10082 22:53:33.928118 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10083 22:53:33.931437 [ 0.000000] psci: probing for conduit method from DT.
10084 22:53:33.937681 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10085 22:53:33.940911 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10086 22:53:33.947700 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10087 22:53:33.951175 [ 0.000000] psci: SMC Calling Convention v1.2
10088 22:53:33.957877 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10089 22:53:33.960908 [ 0.000000] Detected VIPT I-cache on CPU0
10090 22:53:33.967900 [ 0.000000] CPU features: detected: GIC system register CPU interface
10091 22:53:33.974386 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10092 22:53:33.980755 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10093 22:53:33.987756 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10094 22:53:33.997529 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10095 22:53:34.004139 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10096 22:53:34.007185 [ 0.000000] alternatives: applying boot alternatives
10097 22:53:34.013951 [ 0.000000] Fallback order for Node 0: 0
10098 22:53:34.020603 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10099 22:53:34.023533 [ 0.000000] Policy zone: Normal
10100 22:53:34.046987 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683711/extract-nfsrootfs-_8ka395z,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10101 22:53:34.056680 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10102 22:53:34.066472 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10103 22:53:34.073158 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10104 22:53:34.079926 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10105 22:53:34.086312 <6>[ 0.000000] software IO TLB: area num 8.
10106 22:53:34.141659 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10107 22:53:34.221899 <6>[ 0.000000] Memory: 3831492K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 326972K reserved, 32768K cma-reserved)
10108 22:53:34.228413 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10109 22:53:34.234939 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10110 22:53:34.238427 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10111 22:53:34.244721 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10112 22:53:34.251512 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10113 22:53:34.254685 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10114 22:53:34.264674 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10115 22:53:34.270991 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10116 22:53:34.277498 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10117 22:53:34.284490 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10118 22:53:34.287735 <6>[ 0.000000] GICv3: 608 SPIs implemented
10119 22:53:34.290828 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10120 22:53:34.297671 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10121 22:53:34.300981 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10122 22:53:34.307826 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10123 22:53:34.320811 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10124 22:53:34.334126 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10125 22:53:34.340695 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10126 22:53:34.348550 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10127 22:53:34.362064 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10128 22:53:34.368183 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10129 22:53:34.374955 <6>[ 0.009177] Console: colour dummy device 80x25
10130 22:53:34.384820 <6>[ 0.013932] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10131 22:53:34.391315 <6>[ 0.024374] pid_max: default: 32768 minimum: 301
10132 22:53:34.394904 <6>[ 0.029245] LSM: Security Framework initializing
10133 22:53:34.401346 <6>[ 0.034158] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10134 22:53:34.411421 <6>[ 0.041765] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10135 22:53:34.418070 <6>[ 0.051066] cblist_init_generic: Setting adjustable number of callback queues.
10136 22:53:34.424530 <6>[ 0.058511] cblist_init_generic: Setting shift to 3 and lim to 1.
10137 22:53:34.434567 <6>[ 0.064889] cblist_init_generic: Setting adjustable number of callback queues.
10138 22:53:34.437807 <6>[ 0.072316] cblist_init_generic: Setting shift to 3 and lim to 1.
10139 22:53:34.444679 <6>[ 0.078716] rcu: Hierarchical SRCU implementation.
10140 22:53:34.451091 <6>[ 0.083761] rcu: Max phase no-delay instances is 1000.
10141 22:53:34.457612 <6>[ 0.090776] EFI services will not be available.
10142 22:53:34.461177 <6>[ 0.095763] smp: Bringing up secondary CPUs ...
10143 22:53:34.468736 <6>[ 0.100840] Detected VIPT I-cache on CPU1
10144 22:53:34.475540 <6>[ 0.100913] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10145 22:53:34.481890 <6>[ 0.100944] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10146 22:53:34.485503 <6>[ 0.101275] Detected VIPT I-cache on CPU2
10147 22:53:34.495124 <6>[ 0.101322] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10148 22:53:34.501909 <6>[ 0.101338] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10149 22:53:34.505104 <6>[ 0.101594] Detected VIPT I-cache on CPU3
10150 22:53:34.511680 <6>[ 0.101640] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10151 22:53:34.518205 <6>[ 0.101654] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10152 22:53:34.524597 <6>[ 0.101956] CPU features: detected: Spectre-v4
10153 22:53:34.527892 <6>[ 0.101962] CPU features: detected: Spectre-BHB
10154 22:53:34.531598 <6>[ 0.101967] Detected PIPT I-cache on CPU4
10155 22:53:34.538361 <6>[ 0.102025] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10156 22:53:34.544799 <6>[ 0.102041] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10157 22:53:34.551385 <6>[ 0.102331] Detected PIPT I-cache on CPU5
10158 22:53:34.557970 <6>[ 0.102394] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10159 22:53:34.564472 <6>[ 0.102410] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10160 22:53:34.567864 <6>[ 0.102693] Detected PIPT I-cache on CPU6
10161 22:53:34.574547 <6>[ 0.102754] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10162 22:53:34.584386 <6>[ 0.102770] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10163 22:53:34.587691 <6>[ 0.103074] Detected PIPT I-cache on CPU7
10164 22:53:34.594154 <6>[ 0.103139] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10165 22:53:34.600960 <6>[ 0.103155] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10166 22:53:34.604008 <6>[ 0.103203] smp: Brought up 1 node, 8 CPUs
10167 22:53:34.610492 <6>[ 0.244508] SMP: Total of 8 processors activated.
10168 22:53:34.614336 <6>[ 0.249429] CPU features: detected: 32-bit EL0 Support
10169 22:53:34.623938 <6>[ 0.254791] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10170 22:53:34.630598 <6>[ 0.263647] CPU features: detected: Common not Private translations
10171 22:53:34.637373 <6>[ 0.270122] CPU features: detected: CRC32 instructions
10172 22:53:34.643706 <6>[ 0.275474] CPU features: detected: RCpc load-acquire (LDAPR)
10173 22:53:34.646996 <6>[ 0.281434] CPU features: detected: LSE atomic instructions
10174 22:53:34.653481 <6>[ 0.287216] CPU features: detected: Privileged Access Never
10175 22:53:34.660020 <6>[ 0.292995] CPU features: detected: RAS Extension Support
10176 22:53:34.666708 <6>[ 0.298604] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10177 22:53:34.669875 <6>[ 0.305825] CPU: All CPU(s) started at EL2
10178 22:53:34.676795 <6>[ 0.310168] alternatives: applying system-wide alternatives
10179 22:53:34.685579 <6>[ 0.320192] devtmpfs: initialized
10180 22:53:34.700879 <6>[ 0.328516] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10181 22:53:34.707242 <6>[ 0.338475] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10182 22:53:34.713827 <6>[ 0.346693] pinctrl core: initialized pinctrl subsystem
10183 22:53:34.717370 <6>[ 0.353345] DMI not present or invalid.
10184 22:53:34.723482 <6>[ 0.357755] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10185 22:53:34.734159 <6>[ 0.364627] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10186 22:53:34.740378 <6>[ 0.372078] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10187 22:53:34.749935 <6>[ 0.380175] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10188 22:53:34.753298 <6>[ 0.388331] audit: initializing netlink subsys (disabled)
10189 22:53:34.763118 <5>[ 0.394027] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10190 22:53:34.769606 <6>[ 0.394730] thermal_sys: Registered thermal governor 'step_wise'
10191 22:53:34.776624 <6>[ 0.401993] thermal_sys: Registered thermal governor 'power_allocator'
10192 22:53:34.779647 <6>[ 0.408245] cpuidle: using governor menu
10193 22:53:34.786592 <6>[ 0.419205] NET: Registered PF_QIPCRTR protocol family
10194 22:53:34.792847 <6>[ 0.424693] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10195 22:53:34.799401 <6>[ 0.431794] ASID allocator initialised with 32768 entries
10196 22:53:34.802744 <6>[ 0.438352] Serial: AMBA PL011 UART driver
10197 22:53:34.812729 <4>[ 0.447098] Trying to register duplicate clock ID: 134
10198 22:53:34.872633 <6>[ 0.510162] KASLR enabled
10199 22:53:34.886867 <6>[ 0.517897] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10200 22:53:34.893625 <6>[ 0.524907] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10201 22:53:34.900030 <6>[ 0.531393] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10202 22:53:34.906562 <6>[ 0.538398] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10203 22:53:34.913407 <6>[ 0.544886] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10204 22:53:34.919703 <6>[ 0.551888] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10205 22:53:34.926505 <6>[ 0.558374] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10206 22:53:34.933094 <6>[ 0.565379] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10207 22:53:34.936454 <6>[ 0.572828] ACPI: Interpreter disabled.
10208 22:53:34.944836 <6>[ 0.579252] iommu: Default domain type: Translated
10209 22:53:34.951699 <6>[ 0.584366] iommu: DMA domain TLB invalidation policy: strict mode
10210 22:53:34.955025 <5>[ 0.591028] SCSI subsystem initialized
10211 22:53:34.961301 <6>[ 0.595278] usbcore: registered new interface driver usbfs
10212 22:53:34.967961 <6>[ 0.601011] usbcore: registered new interface driver hub
10213 22:53:34.971177 <6>[ 0.606562] usbcore: registered new device driver usb
10214 22:53:34.978298 <6>[ 0.612677] pps_core: LinuxPPS API ver. 1 registered
10215 22:53:34.988157 <6>[ 0.617870] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10216 22:53:34.991618 <6>[ 0.627214] PTP clock support registered
10217 22:53:34.994838 <6>[ 0.631454] EDAC MC: Ver: 3.0.0
10218 22:53:35.002442 <6>[ 0.636637] FPGA manager framework
10219 22:53:35.008920 <6>[ 0.640315] Advanced Linux Sound Architecture Driver Initialized.
10220 22:53:35.012688 <6>[ 0.647092] vgaarb: loaded
10221 22:53:35.018544 <6>[ 0.650244] clocksource: Switched to clocksource arch_sys_counter
10222 22:53:35.022195 <5>[ 0.656687] VFS: Disk quotas dquot_6.6.0
10223 22:53:35.028918 <6>[ 0.660870] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10224 22:53:35.031947 <6>[ 0.668063] pnp: PnP ACPI: disabled
10225 22:53:35.040520 <6>[ 0.674762] NET: Registered PF_INET protocol family
10226 22:53:35.046995 <6>[ 0.680148] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10227 22:53:35.059137 <6>[ 0.690176] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10228 22:53:35.069243 <6>[ 0.698960] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10229 22:53:35.075664 <6>[ 0.706927] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10230 22:53:35.082189 <6>[ 0.715329] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10231 22:53:35.092751 <6>[ 0.723985] TCP: Hash tables configured (established 32768 bind 32768)
10232 22:53:35.099509 <6>[ 0.730844] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10233 22:53:35.106211 <6>[ 0.737863] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10234 22:53:35.113619 <6>[ 0.745385] NET: Registered PF_UNIX/PF_LOCAL protocol family
10235 22:53:35.119335 <6>[ 0.751527] RPC: Registered named UNIX socket transport module.
10236 22:53:35.122457 <6>[ 0.757683] RPC: Registered udp transport module.
10237 22:53:35.129334 <6>[ 0.762617] RPC: Registered tcp transport module.
10238 22:53:35.136089 <6>[ 0.767549] RPC: Registered tcp NFSv4.1 backchannel transport module.
10239 22:53:35.139132 <6>[ 0.774216] PCI: CLS 0 bytes, default 64
10240 22:53:35.142084 <6>[ 0.778548] Unpacking initramfs...
10241 22:53:35.167361 <6>[ 0.798345] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10242 22:53:35.177251 <6>[ 0.807014] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10243 22:53:35.180340 <6>[ 0.815835] kvm [1]: IPA Size Limit: 40 bits
10244 22:53:35.186930 <6>[ 0.820362] kvm [1]: GICv3: no GICV resource entry
10245 22:53:35.190218 <6>[ 0.825383] kvm [1]: disabling GICv2 emulation
10246 22:53:35.197265 <6>[ 0.830069] kvm [1]: GIC system register CPU interface enabled
10247 22:53:35.200634 <6>[ 0.836227] kvm [1]: vgic interrupt IRQ18
10248 22:53:35.206916 <6>[ 0.840590] kvm [1]: VHE mode initialized successfully
10249 22:53:35.213665 <5>[ 0.847012] Initialise system trusted keyrings
10250 22:53:35.220192 <6>[ 0.851794] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10251 22:53:35.227649 <6>[ 0.861778] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10252 22:53:35.233947 <5>[ 0.868171] NFS: Registering the id_resolver key type
10253 22:53:35.237328 <5>[ 0.873478] Key type id_resolver registered
10254 22:53:35.244093 <5>[ 0.877894] Key type id_legacy registered
10255 22:53:35.250685 <6>[ 0.882174] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10256 22:53:35.256902 <6>[ 0.889098] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10257 22:53:35.263542 <6>[ 0.896821] 9p: Installing v9fs 9p2000 file system support
10258 22:53:35.300959 <5>[ 0.935076] Key type asymmetric registered
10259 22:53:35.304182 <5>[ 0.939413] Asymmetric key parser 'x509' registered
10260 22:53:35.314192 <6>[ 0.944551] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10261 22:53:35.317605 <6>[ 0.952174] io scheduler mq-deadline registered
10262 22:53:35.320578 <6>[ 0.956935] io scheduler kyber registered
10263 22:53:35.339498 <6>[ 0.973759] EINJ: ACPI disabled.
10264 22:53:35.372540 <4>[ 1.000155] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10265 22:53:35.382218 <4>[ 1.010791] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10266 22:53:35.397542 <6>[ 1.031965] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10267 22:53:35.405701 <6>[ 1.039939] printk: console [ttyS0] disabled
10268 22:53:35.433344 <6>[ 1.064586] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10269 22:53:35.440106 <6>[ 1.074082] printk: console [ttyS0] enabled
10270 22:53:35.443396 <6>[ 1.074082] printk: console [ttyS0] enabled
10271 22:53:35.450225 <6>[ 1.082974] printk: bootconsole [mtk8250] disabled
10272 22:53:35.453238 <6>[ 1.082974] printk: bootconsole [mtk8250] disabled
10273 22:53:35.459790 <6>[ 1.094182] SuperH (H)SCI(F) driver initialized
10274 22:53:35.463287 <6>[ 1.099470] msm_serial: driver initialized
10275 22:53:35.477786 <6>[ 1.108444] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10276 22:53:35.487296 <6>[ 1.116991] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10277 22:53:35.494020 <6>[ 1.125533] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10278 22:53:35.504399 <6>[ 1.134162] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10279 22:53:35.513810 <6>[ 1.142870] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10280 22:53:35.520585 <6>[ 1.151586] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10281 22:53:35.530692 <6>[ 1.160135] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10282 22:53:35.537346 <6>[ 1.168938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10283 22:53:35.546905 <6>[ 1.177482] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10284 22:53:35.558679 <6>[ 1.193158] loop: module loaded
10285 22:53:35.565608 <6>[ 1.199121] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10286 22:53:35.588142 <4>[ 1.222467] mtk-pmic-keys: Failed to locate of_node [id: -1]
10287 22:53:35.594937 <6>[ 1.229404] megasas: 07.719.03.00-rc1
10288 22:53:35.604844 <6>[ 1.239406] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10289 22:53:35.618757 <6>[ 1.249634] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10290 22:53:35.631736 <6>[ 1.266227] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10291 22:53:35.687801 <6>[ 1.315608] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10292 22:53:35.928146 <6>[ 1.562858] Freeing initrd memory: 18280K
10293 22:53:35.940009 <6>[ 1.574387] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10294 22:53:35.950741 <6>[ 1.585327] tun: Universal TUN/TAP device driver, 1.6
10295 22:53:35.954357 <6>[ 1.591399] thunder_xcv, ver 1.0
10296 22:53:35.957714 <6>[ 1.594904] thunder_bgx, ver 1.0
10297 22:53:35.960668 <6>[ 1.598399] nicpf, ver 1.0
10298 22:53:35.971144 <6>[ 1.602424] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10299 22:53:35.974547 <6>[ 1.609899] hns3: Copyright (c) 2017 Huawei Corporation.
10300 22:53:35.981098 <6>[ 1.615488] hclge is initializing
10301 22:53:35.984380 <6>[ 1.619066] e1000: Intel(R) PRO/1000 Network Driver
10302 22:53:35.991481 <6>[ 1.624195] e1000: Copyright (c) 1999-2006 Intel Corporation.
10303 22:53:35.994369 <6>[ 1.630207] e1000e: Intel(R) PRO/1000 Network Driver
10304 22:53:36.001301 <6>[ 1.635423] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10305 22:53:36.007876 <6>[ 1.641612] igb: Intel(R) Gigabit Ethernet Network Driver
10306 22:53:36.014742 <6>[ 1.647262] igb: Copyright (c) 2007-2014 Intel Corporation.
10307 22:53:36.021045 <6>[ 1.653098] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10308 22:53:36.027659 <6>[ 1.659616] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10309 22:53:36.030778 <6>[ 1.666075] sky2: driver version 1.30
10310 22:53:36.037441 <6>[ 1.671013] usbcore: registered new device driver r8152-cfgselector
10311 22:53:36.044210 <6>[ 1.677547] usbcore: registered new interface driver r8152
10312 22:53:36.050598 <6>[ 1.683369] VFIO - User Level meta-driver version: 0.3
10313 22:53:36.057574 <6>[ 1.691599] usbcore: registered new interface driver usb-storage
10314 22:53:36.064028 <6>[ 1.698043] usbcore: registered new device driver onboard-usb-hub
10315 22:53:36.072822 <6>[ 1.707220] mt6397-rtc mt6359-rtc: registered as rtc0
10316 22:53:36.083247 <6>[ 1.712692] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:53:36 UTC (1715122416)
10317 22:53:36.085674 <6>[ 1.722279] i2c_dev: i2c /dev entries driver
10318 22:53:36.102960 <6>[ 1.734137] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10319 22:53:36.109681 <4>[ 1.742872] cpu cpu0: supply cpu not found, using dummy regulator
10320 22:53:36.116525 <4>[ 1.749295] cpu cpu1: supply cpu not found, using dummy regulator
10321 22:53:36.122758 <4>[ 1.755712] cpu cpu2: supply cpu not found, using dummy regulator
10322 22:53:36.129910 <4>[ 1.762114] cpu cpu3: supply cpu not found, using dummy regulator
10323 22:53:36.136316 <4>[ 1.768511] cpu cpu4: supply cpu not found, using dummy regulator
10324 22:53:36.142931 <4>[ 1.774911] cpu cpu5: supply cpu not found, using dummy regulator
10325 22:53:36.149417 <4>[ 1.781326] cpu cpu6: supply cpu not found, using dummy regulator
10326 22:53:36.156221 <4>[ 1.787724] cpu cpu7: supply cpu not found, using dummy regulator
10327 22:53:36.173982 <6>[ 1.808349] cpu cpu0: EM: created perf domain
10328 22:53:36.177162 <6>[ 1.813249] cpu cpu4: EM: created perf domain
10329 22:53:36.184502 <6>[ 1.818799] sdhci: Secure Digital Host Controller Interface driver
10330 22:53:36.191052 <6>[ 1.825228] sdhci: Copyright(c) Pierre Ossman
10331 22:53:36.197657 <6>[ 1.830141] Synopsys Designware Multimedia Card Interface Driver
10332 22:53:36.204553 <6>[ 1.836740] sdhci-pltfm: SDHCI platform and OF driver helper
10333 22:53:36.207864 <6>[ 1.836906] mmc0: CQHCI version 5.10
10334 22:53:36.214448 <6>[ 1.846836] ledtrig-cpu: registered to indicate activity on CPUs
10335 22:53:36.220899 <6>[ 1.853850] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10336 22:53:36.227226 <6>[ 1.860881] usbcore: registered new interface driver usbhid
10337 22:53:36.230749 <6>[ 1.866703] usbhid: USB HID core driver
10338 22:53:36.237426 <6>[ 1.870921] spi_master spi0: will run message pump with realtime priority
10339 22:53:36.282612 <6>[ 1.910486] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10340 22:53:36.302146 <6>[ 1.926625] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10341 22:53:36.305845 <6>[ 1.940186] mmc0: Command Queue Engine enabled
10342 22:53:36.312387 <6>[ 1.944951] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10343 22:53:36.318954 <6>[ 1.952071] cros-ec-spi spi0.0: Chrome EC device registered
10344 22:53:36.322337 <6>[ 1.952342] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10345 22:53:36.332413 <6>[ 1.967092] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10346 22:53:36.339992 <6>[ 1.974537] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10347 22:53:36.346669 <6>[ 1.980543] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10348 22:53:36.353187 <6>[ 1.986519] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10349 22:53:36.367495 <6>[ 1.998433] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10350 22:53:36.374224 <6>[ 2.008702] NET: Registered PF_PACKET protocol family
10351 22:53:36.377402 <6>[ 2.014153] 9pnet: Installing 9P2000 support
10352 22:53:36.384564 <5>[ 2.018740] Key type dns_resolver registered
10353 22:53:36.387571 <6>[ 2.023859] registered taskstats version 1
10354 22:53:36.394237 <5>[ 2.028270] Loading compiled-in X.509 certificates
10355 22:53:36.422172 <4>[ 2.050222] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10356 22:53:36.432332 <4>[ 2.061108] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10357 22:53:36.438776 <3>[ 2.071660] debugfs: File 'uA_load' in directory '/' already present!
10358 22:53:36.445543 <3>[ 2.078388] debugfs: File 'min_uV' in directory '/' already present!
10359 22:53:36.452321 <3>[ 2.085005] debugfs: File 'max_uV' in directory '/' already present!
10360 22:53:36.458952 <3>[ 2.091616] debugfs: File 'constraint_flags' in directory '/' already present!
10361 22:53:36.473886 <6>[ 2.108180] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10362 22:53:36.480641 <6>[ 2.115075] xhci-mtk 11200000.usb: xHCI Host Controller
10363 22:53:36.487245 <6>[ 2.120590] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10364 22:53:36.497455 <6>[ 2.128483] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10365 22:53:36.504421 <6>[ 2.137920] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10366 22:53:36.510831 <6>[ 2.144028] xhci-mtk 11200000.usb: xHCI Host Controller
10367 22:53:36.517252 <6>[ 2.149516] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10368 22:53:36.523819 <6>[ 2.157172] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10369 22:53:36.530321 <6>[ 2.165009] hub 1-0:1.0: USB hub found
10370 22:53:36.533996 <6>[ 2.169031] hub 1-0:1.0: 1 port detected
10371 22:53:36.540585 <6>[ 2.173341] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10372 22:53:36.547768 <6>[ 2.182159] hub 2-0:1.0: USB hub found
10373 22:53:36.550933 <6>[ 2.186181] hub 2-0:1.0: 1 port detected
10374 22:53:36.559649 <6>[ 2.194146] mtk-msdc 11f70000.mmc: Got CD GPIO
10375 22:53:36.576903 <6>[ 2.207974] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10376 22:53:36.583481 <6>[ 2.216029] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10377 22:53:36.593550 <4>[ 2.223961] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10378 22:53:36.603195 <6>[ 2.233537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10379 22:53:36.610439 <6>[ 2.241619] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10380 22:53:36.616771 <6>[ 2.249644] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10381 22:53:36.626730 <6>[ 2.257563] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10382 22:53:36.633425 <6>[ 2.265379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10383 22:53:36.643438 <6>[ 2.273196] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10384 22:53:36.653428 <6>[ 2.283521] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10385 22:53:36.659696 <6>[ 2.291879] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10386 22:53:36.669512 <6>[ 2.300234] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10387 22:53:36.676136 <6>[ 2.308572] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10388 22:53:36.686301 <6>[ 2.316910] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10389 22:53:36.692792 <6>[ 2.325247] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10390 22:53:36.702663 <6>[ 2.333584] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10391 22:53:36.709277 <6>[ 2.341921] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10392 22:53:36.718911 <6>[ 2.350258] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10393 22:53:36.728763 <6>[ 2.358596] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10394 22:53:36.735693 <6>[ 2.366933] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10395 22:53:36.745577 <6>[ 2.375270] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10396 22:53:36.752249 <6>[ 2.383606] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10397 22:53:36.762312 <6>[ 2.391943] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10398 22:53:36.768592 <6>[ 2.400281] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10399 22:53:36.775708 <6>[ 2.408995] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10400 22:53:36.782130 <6>[ 2.416108] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10401 22:53:36.788549 <6>[ 2.422840] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10402 22:53:36.795365 <6>[ 2.429570] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10403 22:53:36.805452 <6>[ 2.436470] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10404 22:53:36.811888 <6>[ 2.443332] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10405 22:53:36.821991 <6>[ 2.452461] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10406 22:53:36.831995 <6>[ 2.461580] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10407 22:53:36.842084 <6>[ 2.470873] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10408 22:53:36.851695 <6>[ 2.480340] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10409 22:53:36.858164 <6>[ 2.489810] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10410 22:53:36.868222 <6>[ 2.498930] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10411 22:53:36.877998 <6>[ 2.508399] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10412 22:53:36.887979 <6>[ 2.517517] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10413 22:53:36.897932 <6>[ 2.526811] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10414 22:53:36.907684 <6>[ 2.536971] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10415 22:53:36.917572 <6>[ 2.548881] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10416 22:53:36.924213 <6>[ 2.558498] Trying to probe devices needed for running init ...
10417 22:53:36.963043 <6>[ 2.594516] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10418 22:53:37.117870 <6>[ 2.752396] hub 1-1:1.0: USB hub found
10419 22:53:37.121160 <6>[ 2.756922] hub 1-1:1.0: 4 ports detected
10420 22:53:37.130594 <6>[ 2.765373] hub 1-1:1.0: USB hub found
10421 22:53:37.133933 <6>[ 2.769806] hub 1-1:1.0: 4 ports detected
10422 22:53:37.243668 <6>[ 2.874808] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10423 22:53:37.269319 <6>[ 2.903604] hub 2-1:1.0: USB hub found
10424 22:53:37.272336 <6>[ 2.908096] hub 2-1:1.0: 3 ports detected
10425 22:53:37.280386 <6>[ 2.915188] hub 2-1:1.0: USB hub found
10426 22:53:37.283702 <6>[ 2.919639] hub 2-1:1.0: 3 ports detected
10427 22:53:37.459062 <6>[ 3.090386] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10428 22:53:37.591090 <6>[ 3.225667] hub 1-1.4:1.0: USB hub found
10429 22:53:37.593998 <6>[ 3.230208] hub 1-1.4:1.0: 2 ports detected
10430 22:53:37.602672 <6>[ 3.237103] hub 1-1.4:1.0: USB hub found
10431 22:53:37.605603 <6>[ 3.241660] hub 1-1.4:1.0: 2 ports detected
10432 22:53:37.671410 <6>[ 3.302554] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10433 22:53:37.779402 <6>[ 3.410869] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10434 22:53:37.811361 <4>[ 3.442705] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10435 22:53:37.821365 <4>[ 3.451801] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10436 22:53:37.861291 <6>[ 3.495586] r8152 2-1.3:1.0 eth0: v1.12.13
10437 22:53:37.907371 <6>[ 3.538562] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10438 22:53:38.099371 <6>[ 3.730521] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10439 22:53:39.478226 <6>[ 5.113295] r8152 2-1.3:1.0 eth0: carrier on
10440 22:53:41.643192 <5>[ 5.134385] Sending DHCP requests .., OK
10441 22:53:41.649548 <6>[ 7.282703] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10442 22:53:41.652949 <6>[ 7.290990] IP-Config: Complete:
10443 22:53:41.666251 <6>[ 7.294488] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10444 22:53:41.672935 <6>[ 7.305209] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10445 22:53:41.679529 <6>[ 7.313828] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10446 22:53:41.685977 <6>[ 7.313837] nameserver0=192.168.201.1
10447 22:53:41.689236 <6>[ 7.326018] clk: Disabling unused clocks
10448 22:53:41.692780 <6>[ 7.331434] ALSA device list:
10449 22:53:41.699529 <6>[ 7.334719] No soundcards found.
10450 22:53:41.706684 <6>[ 7.342014] Freeing unused kernel memory: 8512K
10451 22:53:41.710163 <6>[ 7.346974] Run /init as init process
10452 22:53:41.718903 Loading, please wait...
10453 22:53:41.747943 Starting systemd-udevd version 252.22-1~deb12u1
10454 22:53:41.748482
10455 22:53:41.999013 <6>[ 7.630944] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10456 22:53:42.009291 <6>[ 7.640972] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10457 22:53:42.012244 <6>[ 7.644740] remoteproc remoteproc0: scp is available
10458 22:53:42.022312 <6>[ 7.649541] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10459 22:53:42.029172 <6>[ 7.653875] remoteproc remoteproc0: powering up scp
10460 22:53:42.035729 <6>[ 7.662630] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10461 22:53:42.045780 <6>[ 7.667750] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10462 22:53:42.048772 <6>[ 7.684999] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10463 22:53:42.055600 <6>[ 7.686142] mc: Linux media interface: v0.10
10464 22:53:42.062457 <4>[ 7.696377] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10465 22:53:42.072447 <4>[ 7.704017] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10466 22:53:42.084877 <3>[ 7.716354] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10467 22:53:42.091341 <3>[ 7.724675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10468 22:53:42.101605 <6>[ 7.728490] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10469 22:53:42.108099 <3>[ 7.732786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10470 22:53:42.114634 <6>[ 7.741072] videodev: Linux video capture interface: v2.00
10471 22:53:42.121147 <3>[ 7.750162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10472 22:53:42.131880 <4>[ 7.751563] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10473 22:53:42.135086 <4>[ 7.751563] Fallback method does not support PEC.
10474 22:53:42.145204 <3>[ 7.767894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10475 22:53:42.151821 <3>[ 7.776036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10476 22:53:42.162180 <3>[ 7.776041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10477 22:53:42.168970 <3>[ 7.776045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10478 22:53:42.175527 <3>[ 7.776049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10479 22:53:42.185279 <3>[ 7.776087] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10480 22:53:42.192341 <3>[ 7.776213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10481 22:53:42.201821 <3>[ 7.776223] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10482 22:53:42.208675 <3>[ 7.776231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10483 22:53:42.218325 <3>[ 7.776485] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10484 22:53:42.225091 <6>[ 7.799624] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10485 22:53:42.231717 <3>[ 7.801198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10486 22:53:42.241590 <3>[ 7.807280] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10487 22:53:42.248730 <6>[ 7.809277] pci_bus 0000:00: root bus resource [bus 00-ff]
10488 22:53:42.254918 <6>[ 7.816141] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10489 22:53:42.262229 <3>[ 7.817348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10490 22:53:42.271672 <6>[ 7.825435] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10491 22:53:42.281668 <6>[ 7.825599] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10492 22:53:42.287978 <6>[ 7.826250] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10493 22:53:42.298480 <6>[ 7.826257] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10494 22:53:42.304781 <6>[ 7.826292] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10495 22:53:42.311004 <6>[ 7.826307] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10496 22:53:42.314507 <6>[ 7.826369] pci 0000:00:00.0: supports D1 D2
10497 22:53:42.321313 <6>[ 7.826370] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10498 22:53:42.331250 <6>[ 7.827158] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10499 22:53:42.337810 <6>[ 7.827220] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10500 22:53:42.344555 <6>[ 7.827244] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10501 22:53:42.351250 <6>[ 7.827259] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10502 22:53:42.357453 <6>[ 7.827273] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10503 22:53:42.364227 <6>[ 7.827373] pci 0000:01:00.0: supports D1 D2
10504 22:53:42.371001 <6>[ 7.827374] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10505 22:53:42.377501 <3>[ 7.833502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10506 22:53:42.387454 <6>[ 7.834833] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10507 22:53:42.394358 <6>[ 7.837147] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10508 22:53:42.401129 <6>[ 7.841578] remoteproc remoteproc0: remote processor scp is now up
10509 22:53:42.407339 <6>[ 7.842626] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10510 22:53:42.417266 <6>[ 7.843421] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10511 22:53:42.426942 <6>[ 7.843846] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10512 22:53:42.437102 <3>[ 7.849717] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10513 22:53:42.443362 <6>[ 7.858565] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10514 22:53:42.450211 <3>[ 7.864792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10515 22:53:42.460026 <6>[ 7.872881] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10516 22:53:42.463296 <6>[ 7.882351] Bluetooth: Core ver 2.22
10517 22:53:42.470195 <6>[ 7.887379] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10518 22:53:42.476545 <6>[ 7.894652] NET: Registered PF_BLUETOOTH protocol family
10519 22:53:42.486353 <6>[ 7.902405] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10520 22:53:42.492735 <6>[ 7.911057] Bluetooth: HCI device and connection manager initialized
10521 22:53:42.499995 <6>[ 7.911465] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10522 22:53:42.509513 <6>[ 7.912665] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10523 22:53:42.516333 <6>[ 7.912754] usbcore: registered new interface driver uvcvideo
10524 22:53:42.526077 <6>[ 7.920211] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10525 22:53:42.529238 <6>[ 7.927367] Bluetooth: HCI socket layer initialized
10526 22:53:42.535690 <6>[ 7.927962] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10527 22:53:42.542307 <6>[ 7.937231] pci 0000:00:00.0: PCI bridge to [bus 01]
10528 22:53:42.545747 <6>[ 7.943490] Bluetooth: L2CAP socket layer initialized
10529 22:53:42.555833 <6>[ 7.950944] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10530 22:53:42.559097 <6>[ 7.955474] Bluetooth: SCO socket layer initialized
10531 22:53:42.565547 <6>[ 7.962490] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10532 22:53:42.571958 <6>[ 8.042039] usbcore: registered new interface driver btusb
10533 22:53:42.582161 <4>[ 8.043031] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10534 22:53:42.588537 <3>[ 8.043043] Bluetooth: hci0: Failed to load firmware file (-2)
10535 22:53:42.595016 <3>[ 8.043048] Bluetooth: hci0: Failed to set up firmware (-2)
10536 22:53:42.605350 <4>[ 8.043054] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10537 22:53:42.611736 <6>[ 8.048895] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10538 22:53:42.618192 <6>[ 8.252110] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10539 22:53:42.640810 <5>[ 8.273039] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10540 22:53:42.662551 <5>[ 8.294597] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10541 22:53:42.668967 <5>[ 8.302591] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10542 22:53:42.679092 <4>[ 8.311049] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10543 22:53:42.685418 <6>[ 8.319947] cfg80211: failed to load regulatory.db
10544 22:53:42.737189 <6>[ 8.369052] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10545 22:53:42.743385 <6>[ 8.376682] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10546 22:53:42.768628 <6>[ 8.403650] mt7921e 0000:01:00.0: ASIC revision: 79610010
10547 22:53:42.872722 <6>[ 8.504528] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10548 22:53:42.875784 <6>[ 8.504528]
10549 22:53:42.883926 Begin: Loading essential drivers ... done.
10550 22:53:42.887187 Begin: Running /scripts/init-premount ... done.
10551 22:53:42.893853 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10552 22:53:42.904064 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10553 22:53:42.906969 Device /sys/class/net/eth0 found
10554 22:53:42.907430 done.
10555 22:53:42.919820 Begin: Waiting up to 180 secs for any network device to become available ... done.
10556 22:53:42.955063 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10557 22:53:42.961957 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10558 22:53:42.968274 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10559 22:53:42.974821 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10560 22:53:42.981537 host : mt8192-asurada-spherion-r0-cbg-4
10561 22:53:42.988134 domain : lava-rack
10562 22:53:42.991406 rootserver: 192.168.201.1 rootpath:
10563 22:53:42.991862 filename :
10564 22:53:43.083968 done.
10565 22:53:43.090754 Begin: Running /scripts/nfs-bottom ... done.
10566 22:53:43.101824 Begin: Running /scripts/init-bottom ... done.
10567 22:53:43.142828 <6>[ 8.775020] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10568 22:53:44.438159 <6>[ 10.073525] NET: Registered PF_INET6 protocol family
10569 22:53:44.445429 <6>[ 10.081039] Segment Routing with IPv6
10570 22:53:44.448501 <6>[ 10.084997] In-situ OAM (IOAM) with IPv6
10571 22:53:44.609151 <30>[ 10.217939] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10572 22:53:44.615322 <30>[ 10.251061] systemd[1]: Detected architecture arm64.
10573 22:53:44.625586
10574 22:53:44.628159 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10575 22:53:44.628621
10576 22:53:44.628976
10577 22:53:44.652687 <30>[ 10.288368] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10578 22:53:45.735019 <30>[ 11.367376] systemd[1]: Queued start job for default target graphical.target.
10579 22:53:45.783170 <30>[ 11.415305] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10580 22:53:45.789895 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10581 22:53:45.790496
10582 22:53:45.811769 <30>[ 11.444170] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10583 22:53:45.821721 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10584 22:53:45.822341
10585 22:53:45.840293 <30>[ 11.472123] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10586 22:53:45.849654 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10587 22:53:45.850259
10588 22:53:45.867582 <30>[ 11.499763] systemd[1]: Created slice user.slice - User and Session Slice.
10589 22:53:45.874001 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10590 22:53:45.874605
10591 22:53:45.893976 <30>[ 11.522758] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10592 22:53:45.900223 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10593 22:53:45.900779
10594 22:53:45.921690 <30>[ 11.550705] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10595 22:53:45.928234 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10596 22:53:45.928806
10597 22:53:45.956619 <30>[ 11.579155] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10598 22:53:45.966978 <30>[ 11.599139] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10599 22:53:45.973495 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10600 22:53:45.974144
10601 22:53:45.990918 <30>[ 11.622510] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10602 22:53:45.996855 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10603 22:53:45.997429
10604 22:53:46.014551 <30>[ 11.646561] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10605 22:53:46.024400 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10606 22:53:46.024977
10607 22:53:46.039269 <30>[ 11.674597] systemd[1]: Reached target paths.target - Path Units.
10608 22:53:46.045600 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10609 22:53:46.048531
10610 22:53:46.066288 <30>[ 11.698520] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10611 22:53:46.073052 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10612 22:53:46.073618
10613 22:53:46.086933 <30>[ 11.722493] systemd[1]: Reached target slices.target - Slice Units.
10614 22:53:46.096931 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10615 22:53:46.097497
10616 22:53:46.111368 <30>[ 11.746940] systemd[1]: Reached target swap.target - Swaps.
10617 22:53:46.118140 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10618 22:53:46.118705
10619 22:53:46.138442 <30>[ 11.770590] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10620 22:53:46.148345 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10621 22:53:46.149101
10622 22:53:46.167096 <30>[ 11.799355] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10623 22:53:46.176946 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10624 22:53:46.177578
10625 22:53:46.197633 <30>[ 11.829880] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10626 22:53:46.207389 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10627 22:53:46.207958
10628 22:53:46.223517 <30>[ 11.855963] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10629 22:53:46.234326 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10630 22:53:46.234899
10631 22:53:46.250797 <30>[ 11.883087] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10632 22:53:46.257092 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10633 22:53:46.257553
10634 22:53:46.275734 <30>[ 11.908042] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10635 22:53:46.285653 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10636 22:53:46.286249
10637 22:53:46.305030 <30>[ 11.937238] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10638 22:53:46.314805 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10639 22:53:46.315382
10640 22:53:46.330662 <30>[ 11.962939] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10641 22:53:46.340644 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10642 22:53:46.341255
10643 22:53:46.390573 <30>[ 12.023028] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10644 22:53:46.397050 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10645 22:53:46.397572
10646 22:53:46.419246 <30>[ 12.051773] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10647 22:53:46.425831 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10648 22:53:46.426387
10649 22:53:46.474541 <30>[ 12.106964] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10650 22:53:46.481349 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10651 22:53:46.481823
10652 22:53:46.509386 <30>[ 12.135194] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10653 22:53:46.524748 <30>[ 12.157039] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10654 22:53:46.534374 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10655 22:53:46.534974
10656 22:53:46.555452 <30>[ 12.187984] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10657 22:53:46.562171 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10658 22:53:46.562658
10659 22:53:46.587864 <30>[ 12.220009] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10660 22:53:46.594290 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10661 22:53:46.594763
10662 22:53:46.636394 <6>[ 12.268887] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10663 22:53:46.655145 <30>[ 12.287574] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10664 22:53:46.661729 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10665 22:53:46.662277
10666 22:53:46.687873 <30>[ 12.320351] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10667 22:53:46.697922 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10668 22:53:46.698497
10669 22:53:46.719867 <30>[ 12.352133] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10670 22:53:46.726254 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10671 22:53:46.726769
10672 22:53:46.754310 <30>[ 12.386900] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10673 22:53:46.764321 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 12.399122] fuse: init (API version 7.37)
10674 22:53:46.767643 [0m - Load Kernel Module loop...
10675 22:53:46.768120
10676 22:53:46.822785 <30>[ 12.455354] systemd[1]: Starting systemd-journald.service - Journal Service...
10677 22:53:46.829571 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10678 22:53:46.830174
10679 22:53:46.891293 <30>[ 12.523437] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10680 22:53:46.897504 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10681 22:53:46.898091
10682 22:53:46.926840 <30>[ 12.555949] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10683 22:53:46.933587 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10684 22:53:46.934195
10685 22:53:46.957810 <30>[ 12.590021] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10686 22:53:46.971745 Starting [0;1;39msystemd-remount-f…n<3>[ 12.603773] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10687 22:53:46.974390 t Root and Kernel File Systems...
10688 22:53:46.974906
10689 22:53:46.998565 <30>[ 12.630595] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10690 22:53:47.008413 <3>[ 12.633837] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10691 22:53:47.014790 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10692 22:53:47.015277
10693 22:53:47.041589 <30>[ 12.674296] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10694 22:53:47.048872 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10695 22:53:47.049398
10696 22:53:47.058813 <3>[ 12.691574] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10697 22:53:47.070358 <30>[ 12.703036] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10698 22:53:47.077522 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10699 22:53:47.077984
10700 22:53:47.088622 <3>[ 12.721094] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10701 22:53:47.098742 <30>[ 12.730520] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10702 22:53:47.104920 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10703 22:53:47.105348
10704 22:53:47.121418 <3>[ 12.753654] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 22:53:47.131150 <30>[ 12.763444] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10706 22:53:47.141183 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10707 22:53:47.141656
10708 22:53:47.151655 <3>[ 12.784362] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10709 22:53:47.162549 <30>[ 12.795047] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10710 22:53:47.169676 <30>[ 12.803224] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10711 22:53:47.183240 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 12.814920] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10712 22:53:47.189609 onfigfs…[0m - Load Kernel Module configfs.
10713 22:53:47.190249
10714 22:53:47.204802 <30>[ 12.839509] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10715 22:53:47.215023 <30>[ 12.847472] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10716 22:53:47.224982 <3>[ 12.848199] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10717 22:53:47.231672 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10718 22:53:47.232237
10719 22:53:47.250109 <30>[ 12.885257] systemd[1]: modprobe@drm.service: Deactivated successfully.
10720 22:53:47.260102 <3>[ 12.890921] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10721 22:53:47.266585 <30>[ 12.893149] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10722 22:53:47.276402 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10723 22:53:47.276961
10724 22:53:47.294740 <3>[ 12.927252] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10725 22:53:47.301325 <30>[ 12.928780] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10726 22:53:47.312084 <30>[ 12.944585] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10727 22:53:47.319628 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10728 22:53:47.323066
10729 22:53:47.329913 <3>[ 12.961324] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10730 22:53:47.340947 <30>[ 12.973157] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10731 22:53:47.350704 <30>[ 12.981883] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10732 22:53:47.364788 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Mo<3>[ 12.995500] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10733 22:53:47.365366 dule fuse.
10734 22:53:47.365725
10735 22:53:47.384928 <30>[ 13.016831] systemd[1]: modprobe@loop.service: Deactivated successfully.
10736 22:53:47.391777 <30>[ 13.025257] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10737 22:53:47.401760 [[0;32m OK [<3>[ 13.033697] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10738 22:53:47.408343 0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10739 22:53:47.408917
10740 22:53:47.428037 <30>[ 13.060221] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10741 22:53:47.438386 <3>[ 13.063817] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10742 22:53:47.452277 <4>[ 13.077204] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10743 22:53:47.458543 <3>[ 13.077207] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10744 22:53:47.468670 <3>[ 13.084701] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10745 22:53:47.475405 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10746 22:53:47.475957
10747 22:53:47.500239 <30>[ 13.128745] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10748 22:53:47.506741 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10749 22:53:47.507407
10750 22:53:47.527876 <30>[ 13.159909] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10751 22:53:47.537812 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10752 22:53:47.538410
10753 22:53:47.555381 <30>[ 13.187848] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10754 22:53:47.565395 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10755 22:53:47.565959
10756 22:53:47.584016 <30>[ 13.216282] systemd[1]: Reached target network-pre.target - Preparation for Network.
10757 22:53:47.590240 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10758 22:53:47.593899
10759 22:53:47.646272 <30>[ 13.278821] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10760 22:53:47.652862 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10761 22:53:47.653354
10762 22:53:47.678714 <30>[ 13.311376] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10763 22:53:47.685256 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10764 22:53:47.688713
10765 22:53:47.709637 <30>[ 13.338734] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10766 22:53:47.726504 <30>[ 13.352312] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10767 22:53:47.740790 <30>[ 13.373389] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10768 22:53:47.747303 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10769 22:53:47.747961
10770 22:53:47.771781 <30>[ 13.400960] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10771 22:53:47.784599 <30>[ 13.417292] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10772 22:53:47.791231 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10773 22:53:47.791693
10774 22:53:47.816641 <30>[ 13.449405] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10775 22:53:47.823278 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10776 22:53:47.823745
10777 22:53:47.854823 <30>[ 13.487550] systemd[1]: Started systemd-journald.service - Journal Service.
10778 22:53:47.861826 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10779 22:53:47.862385
10780 22:53:47.883321 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10781 22:53:47.883747
10782 22:53:47.903492 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10783 22:53:47.904060
10784 22:53:47.923548 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10785 22:53:47.924115
10786 22:53:47.943443 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10787 22:53:47.944001
10788 22:53:47.963265 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10789 22:53:47.963866
10790 22:53:48.015160 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10791 22:53:48.015713
10792 22:53:48.043516 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10793 22:53:48.044066
10794 22:53:48.089287 <46>[ 13.722215] systemd-journald[298]: Received client request to flush runtime journal.
10795 22:53:48.132696 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10796 22:53:48.133172
10797 22:53:48.154525 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10798 22:53:48.154965
10799 22:53:48.170274 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10800 22:53:48.170695
10801 22:53:48.882954 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10802 22:53:48.883463
10803 22:53:49.509284 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10804 22:53:49.509469
10805 22:53:49.562508 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10806 22:53:49.562634
10807 22:53:49.601936 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10808 22:53:49.602382
10809 22:53:49.654738 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10810 22:53:49.655174
10811 22:53:49.739298 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10812 22:53:49.739726
10813 22:53:50.011154 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10814 22:53:50.011646
10815 22:53:50.046764 <6>[ 15.683033] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10816 22:53:50.075666 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10817 22:53:50.076115
10818 22:53:50.110102 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10819 22:53:50.110576
10820 22:53:50.184115 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10821 22:53:50.184566
10822 22:53:50.229727 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10823 22:53:50.229869
10824 22:53:50.247908 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10825 22:53:50.248021
10826 22:53:50.287814 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10827 22:53:50.288279
10828 22:53:50.308576 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10829 22:53:50.308994
10830 22:53:50.365225 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10831 22:53:50.365663
10832 22:53:50.426276 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10833 22:53:50.426835
10834 22:53:50.492013 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10835 22:53:50.492561
10836 22:53:50.516104 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10837 22:53:50.516652
10838 22:53:50.562112 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10839 22:53:50.562886
10840 22:53:50.655664 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10841 22:53:50.656240
10842 22:53:50.678497 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10843 22:53:50.679046
10844 22:53:50.685234 <46>[ 16.320619] systemd-journald[298]: Time jumped backwards, rotating.
10845 22:53:50.702099 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10846 22:53:50.702581
10847 22:53:50.722069 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10848 22:53:50.722659
10849 22:53:51.015332 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10850 22:53:51.015593
10851 22:53:51.461317 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10852 22:53:51.461554
10853 22:53:51.477941 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10854 22:53:51.478155
10855 22:53:51.800150 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10856 22:53:51.800298
10857 22:53:52.161006 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10858 22:53:52.161158
10859 22:53:52.177203 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10860 22:53:52.177331
10861 22:53:52.195518 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10862 22:53:52.195786
10863 22:53:52.213635 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10864 22:53:52.214174
10865 22:53:52.230270 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10866 22:53:52.230844
10867 22:53:52.275069 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10868 22:53:52.275605
10869 22:53:52.310355 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10870 22:53:52.310821
10871 22:53:52.410400 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10872 22:53:52.410918
10873 22:53:52.439182 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10874 22:53:52.439336
10875 22:53:52.645846 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10876 22:53:52.646380
10877 22:53:52.698268 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10878 22:53:52.698364
10879 22:53:52.718127 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10880 22:53:52.718224
10881 22:53:52.737669 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10882 22:53:52.737875
10883 22:53:52.754682 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10884 22:53:52.755248
10885 22:53:52.784816 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10886 22:53:52.785374
10887 22:53:52.808637 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10888 22:53:52.809101
10889 22:53:52.828535 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10890 22:53:52.829101
10891 22:53:52.847877 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10892 22:53:52.848429
10893 22:53:52.888374 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10894 22:53:52.888922
10895 22:53:52.948643 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10896 22:53:52.949202
10897 22:53:53.015615
10898 22:53:53.016167
10899 22:53:53.018909 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10900 22:53:53.019365
10901 22:53:53.022391 debian-bookworm-arm64 login: root (automatic login)
10902 22:53:53.022850
10903 22:53:53.023206
10904 22:53:53.355238 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
10905 22:53:53.355788
10906 22:53:53.361687 The programs included with the Debian GNU/Linux system are free software;
10907 22:53:53.367979 the exact distribution terms for each program are described in the
10908 22:53:53.371370 individual files in /usr/share/doc/*/copyright.
10909 22:53:53.371787
10910 22:53:53.378097 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10911 22:53:53.381511 permitted by applicable law.
10912 22:53:54.368986 Matched prompt #10: / #
10914 22:53:54.370273 Setting prompt string to ['/ #']
10915 22:53:54.370778 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10917 22:53:54.371819 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10918 22:53:54.372443 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
10919 22:53:54.372939 Setting prompt string to ['/ #']
10920 22:53:54.373296 Forcing a shell prompt, looking for ['/ #']
10922 22:53:54.423777 / #
10923 22:53:54.424174 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10924 22:53:54.424417 Waiting using forced prompt support (timeout 00:02:30)
10925 22:53:54.429690
10926 22:53:54.430438 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10927 22:53:54.430789 start: 2.2.7 export-device-env (timeout 00:03:42) [common]
10929 22:53:54.531900 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683711/extract-nfsrootfs-_8ka395z'
10930 22:53:54.538208 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683711/extract-nfsrootfs-_8ka395z'
10932 22:53:54.640212 / # export NFS_SERVER_IP='192.168.201.1'
10933 22:53:54.646283 export NFS_SERVER_IP='192.168.201.1'
10934 22:53:54.647211 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10935 22:53:54.647748 end: 2.2 depthcharge-retry (duration 00:01:18) [common]
10936 22:53:54.648238 end: 2 depthcharge-action (duration 00:01:18) [common]
10937 22:53:54.648725 start: 3 lava-test-retry (timeout 00:08:04) [common]
10938 22:53:54.649204 start: 3.1 lava-test-shell (timeout 00:08:04) [common]
10939 22:53:54.649627 Using namespace: common
10941 22:53:54.750903 / # #
10942 22:53:54.751574 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10943 22:53:54.757287 #
10944 22:53:54.758072 Using /lava-13683711
10946 22:53:54.859212 / # export SHELL=/bin/bash
10947 22:53:54.865280 export SHELL=/bin/bash
10949 22:53:54.967127 / # . /lava-13683711/environment
10950 22:53:54.973406 . /lava-13683711/environment
10952 22:53:55.081707 / # /lava-13683711/bin/lava-test-runner /lava-13683711/0
10953 22:53:55.082375 Test shell timeout: 10s (minimum of the action and connection timeout)
10954 22:53:55.087990 /lava-13683711/bin/lava-test-runner /lava-13683711/0
10955 22:53:55.344743 + export TESTRUN_ID=0_timesync-off
10956 22:53:55.348294 + TESTRUN_ID=0_timesync-off
10957 22:53:55.351656 + cd /lava-13683711/0/tests/0_timesync-off
10958 22:53:55.354502 ++ cat uuid
10959 22:53:55.360253 + UUID=13683711_1.6.2.3.1
10960 22:53:55.360730 + set +x
10961 22:53:55.366930 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13683711_1.6.2.3.1>
10962 22:53:55.367624 Received signal: <STARTRUN> 0_timesync-off 13683711_1.6.2.3.1
10963 22:53:55.367986 Starting test lava.0_timesync-off (13683711_1.6.2.3.1)
10964 22:53:55.368430 Skipping test definition patterns.
10965 22:53:55.369984 + systemctl stop systemd-timesyncd
10966 22:53:55.431496 + set +x
10967 22:53:55.434464 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13683711_1.6.2.3.1>
10968 22:53:55.435188 Received signal: <ENDRUN> 0_timesync-off 13683711_1.6.2.3.1
10969 22:53:55.435583 Ending use of test pattern.
10970 22:53:55.435900 Ending test lava.0_timesync-off (13683711_1.6.2.3.1), duration 0.07
10972 22:53:55.500512 + export TESTRUN_ID=1_kselftest-arm64
10973 22:53:55.500977 + TESTRUN_ID=1_kselftest-arm64
10974 22:53:55.506847 + cd /lava-13683711/0/tests/1_kselftest-arm64
10975 22:53:55.507287 ++ cat uuid
10976 22:53:55.510014 + UUID=13683711_1.6.2.3.5
10977 22:53:55.510619 + set +x
10978 22:53:55.516936 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 13683711_1.6.2.3.5>
10979 22:53:55.517609 Received signal: <STARTRUN> 1_kselftest-arm64 13683711_1.6.2.3.5
10980 22:53:55.517958 Starting test lava.1_kselftest-arm64 (13683711_1.6.2.3.5)
10981 22:53:55.518375 Skipping test definition patterns.
10982 22:53:55.520292 + cd ./automated/linux/kselftest/
10983 22:53:55.543295 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10984 22:53:55.583796 INFO: install_deps skipped
10985 22:53:56.084674 --2024-05-07 22:53:56-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10986 22:53:56.100574 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10987 22:53:56.229511 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10988 22:53:56.358204 HTTP request sent, awaiting response... 200 OK
10989 22:53:56.361441 Length: 1651624 (1.6M) [application/octet-stream]
10990 22:53:56.365156 Saving to: 'kselftest_armhf.tar.gz'
10991 22:53:56.365616
10992 22:53:56.365977
10993 22:53:56.616797 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10994 22:53:56.875108 kselftest_armhf.tar 3%[ ] 49.22K 191KB/s
10995 22:53:57.179354 kselftest_armhf.tar 13%[=> ] 218.91K 424KB/s
10996 22:53:57.311945 kselftest_armhf.tar 50%[=========> ] 808.57K 985KB/s
10997 22:53:57.318277 kselftest_armhf.tar 100%[===================>] 1.57M 1.65MB/s in 1.0s
10998 22:53:57.318447
10999 22:53:57.463709 2024-05-07 22:53:57 (1.65 MB/s) - 'kselftest_armhf.tar.gz' saved [1651624/1651624]
11000 22:53:57.463859
11001 22:54:01.131637 skiplist:
11002 22:54:01.134769 ========================================
11003 22:54:01.138311 ========================================
11004 22:54:01.176444 arm64:tags_test
11005 22:54:01.179631 arm64:run_tags_test.sh
11006 22:54:01.179752 arm64:fake_sigreturn_bad_magic
11007 22:54:01.183213 arm64:fake_sigreturn_bad_size
11008 22:54:01.186774 arm64:fake_sigreturn_bad_size_for_magic0
11009 22:54:01.189793 arm64:fake_sigreturn_duplicated_fpsimd
11010 22:54:01.192962 arm64:fake_sigreturn_misaligned_sp
11011 22:54:01.196107 arm64:fake_sigreturn_missing_fpsimd
11012 22:54:01.199239 arm64:fake_sigreturn_sme_change_vl
11013 22:54:01.202718 arm64:fake_sigreturn_sve_change_vl
11014 22:54:01.205931 arm64:mangle_pstate_invalid_compat_toggle
11015 22:54:01.209254 arm64:mangle_pstate_invalid_daif_bits
11016 22:54:01.212825 arm64:mangle_pstate_invalid_mode_el1h
11017 22:54:01.216111 arm64:mangle_pstate_invalid_mode_el1t
11018 22:54:01.219085 arm64:mangle_pstate_invalid_mode_el2h
11019 22:54:01.225931 arm64:mangle_pstate_invalid_mode_el2t
11020 22:54:01.229042 arm64:mangle_pstate_invalid_mode_el3h
11021 22:54:01.232384 arm64:mangle_pstate_invalid_mode_el3t
11022 22:54:01.232493 arm64:sme_trap_no_sm
11023 22:54:01.235758 arm64:sme_trap_non_streaming
11024 22:54:01.235867 arm64:sme_trap_za
11025 22:54:01.238886 arm64:sme_vl
11026 22:54:01.238993 arm64:ssve_regs
11027 22:54:01.242463 arm64:sve_regs
11028 22:54:01.242572 arm64:sve_vl
11029 22:54:01.245587 arm64:za_no_regs
11030 22:54:01.245694 arm64:za_regs
11031 22:54:01.245793 arm64:pac
11032 22:54:01.248931 arm64:fp-stress
11033 22:54:01.249038 arm64:sve-ptrace
11034 22:54:01.252027 arm64:sve-probe-vls
11035 22:54:01.252130 arm64:vec-syscfg
11036 22:54:01.255725 arm64:za-fork
11037 22:54:01.255830 arm64:za-ptrace
11038 22:54:01.258639 arm64:check_buffer_fill
11039 22:54:01.258753 arm64:check_child_memory
11040 22:54:01.261918 arm64:check_gcr_el1_cswitch
11041 22:54:01.265447 arm64:check_ksm_options
11042 22:54:01.265553 arm64:check_mmap_options
11043 22:54:01.268533 arm64:check_prctl
11044 22:54:01.271897 arm64:check_tags_inclusion
11045 22:54:01.272003 arm64:check_user_mem
11046 22:54:01.275263 arm64:btitest
11047 22:54:01.275370 arm64:nobtitest
11048 22:54:01.275466 arm64:hwcap
11049 22:54:01.278563 arm64:ptrace
11050 22:54:01.278670 arm64:syscall-abi
11051 22:54:01.281972 arm64:tpidr2
11052 22:54:01.285284 ============== Tests to run ===============
11053 22:54:01.285394 arm64:tags_test
11054 22:54:01.288430 arm64:run_tags_test.sh
11055 22:54:01.291696 arm64:fake_sigreturn_bad_magic
11056 22:54:01.295024 arm64:fake_sigreturn_bad_size
11057 22:54:01.298395 arm64:fake_sigreturn_bad_size_for_magic0
11058 22:54:01.301513 arm64:fake_sigreturn_duplicated_fpsimd
11059 22:54:01.304836 arm64:fake_sigreturn_misaligned_sp
11060 22:54:01.308202 arm64:fake_sigreturn_missing_fpsimd
11061 22:54:01.311441 arm64:fake_sigreturn_sme_change_vl
11062 22:54:01.314925 arm64:fake_sigreturn_sve_change_vl
11063 22:54:01.318353 arm64:mangle_pstate_invalid_compat_toggle
11064 22:54:01.321539 arm64:mangle_pstate_invalid_daif_bits
11065 22:54:01.324933 arm64:mangle_pstate_invalid_mode_el1h
11066 22:54:01.328298 arm64:mangle_pstate_invalid_mode_el1t
11067 22:54:01.331563 arm64:mangle_pstate_invalid_mode_el2h
11068 22:54:01.334952 arm64:mangle_pstate_invalid_mode_el2t
11069 22:54:01.337961 arm64:mangle_pstate_invalid_mode_el3h
11070 22:54:01.341346 arm64:mangle_pstate_invalid_mode_el3t
11071 22:54:01.341442 arm64:sme_trap_no_sm
11072 22:54:01.344652 arm64:sme_trap_non_streaming
11073 22:54:01.348025 arm64:sme_trap_za
11074 22:54:01.348106 arm64:sme_vl
11075 22:54:01.351308 arm64:ssve_regs
11076 22:54:01.351389 arm64:sve_regs
11077 22:54:01.351452 arm64:sve_vl
11078 22:54:01.354713 arm64:za_no_regs
11079 22:54:01.354795 arm64:za_regs
11080 22:54:01.354858 arm64:pac
11081 22:54:01.357769 arm64:fp-stress
11082 22:54:01.357849 arm64:sve-ptrace
11083 22:54:01.361168 arm64:sve-probe-vls
11084 22:54:01.361248 arm64:vec-syscfg
11085 22:54:01.364622 arm64:za-fork
11086 22:54:01.364702 arm64:za-ptrace
11087 22:54:01.367873 arm64:check_buffer_fill
11088 22:54:01.371058 arm64:check_child_memory
11089 22:54:01.371165 arm64:check_gcr_el1_cswitch
11090 22:54:01.374541 arm64:check_ksm_options
11091 22:54:01.377719 arm64:check_mmap_options
11092 22:54:01.377821 arm64:check_prctl
11093 22:54:01.381021 arm64:check_tags_inclusion
11094 22:54:01.381128 arm64:check_user_mem
11095 22:54:01.384237 arm64:btitest
11096 22:54:01.384339 arm64:nobtitest
11097 22:54:01.387671 arm64:hwcap
11098 22:54:01.387773 arm64:ptrace
11099 22:54:01.391113 arm64:syscall-abi
11100 22:54:01.391217 arm64:tpidr2
11101 22:54:01.394182 ===========End Tests to run ===============
11102 22:54:01.397531 shardfile-arm64 pass
11103 22:54:01.542753 <12>[ 27.180943] kselftest: Running tests in arm64
11104 22:54:01.552330 TAP version 13
11105 22:54:01.564786 1..48
11106 22:54:01.581398 # selftests: arm64: tags_test
11107 22:54:02.013102 ok 1 selftests: arm64: tags_test
11108 22:54:02.025772 # selftests: arm64: run_tags_test.sh
11109 22:54:02.073157 # --------------------
11110 22:54:02.076514 # running tags test
11111 22:54:02.076638 # --------------------
11112 22:54:02.079528 # [PASS]
11113 22:54:02.082738 ok 2 selftests: arm64: run_tags_test.sh
11114 22:54:02.094812 # selftests: arm64: fake_sigreturn_bad_magic
11115 22:54:02.154384 # Registered handlers for all signals.
11116 22:54:02.154573 # Detected MINSTKSIGSZ:4720
11117 22:54:02.157929 # Testcase initialized.
11118 22:54:02.161152 # uc context validated.
11119 22:54:02.164403 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11120 22:54:02.167778 # Handled SIG_COPYCTX
11121 22:54:02.167887 # Available space:3568
11122 22:54:02.174225 # Using badly built context - ERR: BAD MAGIC !
11123 22:54:02.182847 # SIG_OK -- SP:0xFFFFE439F250 si_addr@:0xffffe439f250 si_code:2 token@:0xffffe439dff0 offset:-4704
11124 22:54:02.184162 # ==>> completed. PASS(1)
11125 22:54:02.190819 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11126 22:54:02.197815 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE439DFF0
11127 22:54:02.204012 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11128 22:54:02.207169 # selftests: arm64: fake_sigreturn_bad_size
11129 22:54:02.225239 # Registered handlers for all signals.
11130 22:54:02.225378 # Detected MINSTKSIGSZ:4720
11131 22:54:02.228626 # Testcase initialized.
11132 22:54:02.231763 # uc context validated.
11133 22:54:02.235057 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11134 22:54:02.238460 # Handled SIG_COPYCTX
11135 22:54:02.238541 # Available space:3568
11136 22:54:02.241477 # uc context validated.
11137 22:54:02.248212 # Using badly built context - ERR: Bad size for esr_context
11138 22:54:02.254823 # SIG_OK -- SP:0xFFFFC8066AD0 si_addr@:0xffffc8066ad0 si_code:2 token@:0xffffc8065870 offset:-4704
11139 22:54:02.258221 # ==>> completed. PASS(1)
11140 22:54:02.264720 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11141 22:54:02.271325 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC8065870
11142 22:54:02.274581 ok 4 selftests: arm64: fake_sigreturn_bad_size
11143 22:54:02.281222 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11144 22:54:02.294167 # Registered handlers for all signals.
11145 22:54:02.294254 # Detected MINSTKSIGSZ:4720
11146 22:54:02.297668 # Testcase initialized.
11147 22:54:02.300691 # uc context validated.
11148 22:54:02.304036 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11149 22:54:02.307403 # Handled SIG_COPYCTX
11150 22:54:02.307484 # Available space:3568
11151 22:54:02.314232 # Using badly built context - ERR: Bad size for terminator
11152 22:54:02.323877 # SIG_OK -- SP:0xFFFFD32F28E0 si_addr@:0xffffd32f28e0 si_code:2 token@:0xffffd32f1680 offset:-4704
11153 22:54:02.323962 # ==>> completed. PASS(1)
11154 22:54:02.333666 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11155 22:54:02.340578 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD32F1680
11156 22:54:02.343751 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11157 22:54:02.350018 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11158 22:54:02.371275 # Registered handlers for all signals.
11159 22:54:02.371376 # Detected MINSTKSIGSZ:4720
11160 22:54:02.374620 # Testcase initialized.
11161 22:54:02.377910 # uc context validated.
11162 22:54:02.381102 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11163 22:54:02.384398 # Handled SIG_COPYCTX
11164 22:54:02.384507 # Available space:3568
11165 22:54:02.391248 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11166 22:54:02.401000 # SIG_OK -- SP:0xFFFFD2683350 si_addr@:0xffffd2683350 si_code:2 token@:0xffffd26820f0 offset:-4704
11167 22:54:02.401094 # ==>> completed. PASS(1)
11168 22:54:02.410900 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11169 22:54:02.417575 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD26820F0
11170 22:54:02.420870 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11171 22:54:02.424000 # selftests: arm64: fake_sigreturn_misaligned_sp
11172 22:54:02.427489 # Registered handlers for all signals.
11173 22:54:02.430741 # Detected MINSTKSIGSZ:4720
11174 22:54:02.433999 # Testcase initialized.
11175 22:54:02.437200 # uc context validated.
11176 22:54:02.440567 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11177 22:54:02.443867 # Handled SIG_COPYCTX
11178 22:54:02.450414 # SIG_OK -- SP:0xFFFFF049CF03 si_addr@:0xfffff049cf03 si_code:2 token@:0xfffff049cf03 offset:0
11179 22:54:02.453864 # ==>> completed. PASS(1)
11180 22:54:02.460488 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11181 22:54:02.467030 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF049CF03
11182 22:54:02.473597 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11183 22:54:02.476903 # selftests: arm64: fake_sigreturn_missing_fpsimd
11184 22:54:02.506508 # Registered handlers for all signals.
11185 22:54:02.506625 # Detected MINSTKSIGSZ:4720
11186 22:54:02.509649 # Testcase initialized.
11187 22:54:02.513025 # uc context validated.
11188 22:54:02.516246 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11189 22:54:02.519484 # Handled SIG_COPYCTX
11190 22:54:02.522803 # Mangling template header. Spare space:4096
11191 22:54:02.525991 # Using badly built context - ERR: Missing FPSIMD
11192 22:54:02.536028 # SIG_OK -- SP:0xFFFFC67E8530 si_addr@:0xffffc67e8530 si_code:2 token@:0xffffc67e72d0 offset:-4704
11193 22:54:02.539341 # ==>> completed. PASS(1)
11194 22:54:02.545810 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11195 22:54:02.552690 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC67E72D0
11196 22:54:02.555743 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11197 22:54:02.562321 # selftests: arm64: fake_sigreturn_sme_change_vl
11198 22:54:02.586759 # Registered handlers for all signals.
11199 22:54:02.586882 # Detected MINSTKSIGSZ:4720
11200 22:54:02.589703 # ==>> completed. SKIP.
11201 22:54:02.596157 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11202 22:54:02.599608 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11203 22:54:02.606113 # selftests: arm64: fake_sigreturn_sve_change_vl
11204 22:54:02.658311 # Registered handlers for all signals.
11205 22:54:02.658466 # Detected MINSTKSIGSZ:4720
11206 22:54:02.661694 # ==>> completed. SKIP.
11207 22:54:02.668104 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11208 22:54:02.671532 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11209 22:54:02.677967 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11210 22:54:02.730450 # Registered handlers for all signals.
11211 22:54:02.730610 # Detected MINSTKSIGSZ:4720
11212 22:54:02.733918 # Testcase initialized.
11213 22:54:02.737135 # uc context validated.
11214 22:54:02.737240 # Handled SIG_TRIG
11215 22:54:02.747013 # SIG_OK -- SP:0xFFFFDA5F1BD0 si_addr@:0xffffda5f1bd0 si_code:2 token@:(nil) offset:-281474345409488
11216 22:54:02.750444 # ==>> completed. PASS(1)
11217 22:54:02.757095 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11218 22:54:02.763584 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11219 22:54:02.766963 # selftests: arm64: mangle_pstate_invalid_daif_bits
11220 22:54:02.794471 # Registered handlers for all signals.
11221 22:54:02.794578 # Detected MINSTKSIGSZ:4720
11222 22:54:02.798304 # Testcase initialized.
11223 22:54:02.801454 # uc context validated.
11224 22:54:02.801560 # Handled SIG_TRIG
11225 22:54:02.810952 # SIG_OK -- SP:0xFFFFCA883F30 si_addr@:0xffffca883f30 si_code:2 token@:(nil) offset:-281474079670064
11226 22:54:02.814804 # ==>> completed. PASS(1)
11227 22:54:02.820894 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11228 22:54:02.824359 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11229 22:54:02.830718 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11230 22:54:02.862257 # Registered handlers for all signals.
11231 22:54:02.862365 # Detected MINSTKSIGSZ:4720
11232 22:54:02.865745 # Testcase initialized.
11233 22:54:02.868866 # uc context validated.
11234 22:54:02.868949 # Handled SIG_TRIG
11235 22:54:02.878938 # SIG_OK -- SP:0xFFFFC4074010 si_addr@:0xffffc4074010 si_code:2 token@:(nil) offset:-281473970552848
11236 22:54:02.882227 # ==>> completed. PASS(1)
11237 22:54:02.888602 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11238 22:54:02.891980 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11239 22:54:02.898638 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11240 22:54:02.946474 # Registered handlers for all signals.
11241 22:54:02.946641 # Detected MINSTKSIGSZ:4720
11242 22:54:02.949558 # Testcase initialized.
11243 22:54:02.952918 # uc context validated.
11244 22:54:02.953026 # Handled SIG_TRIG
11245 22:54:02.963021 # SIG_OK -- SP:0xFFFFF2BB8140 si_addr@:0xfffff2bb8140 si_code:2 token@:(nil) offset:-281474754117952
11246 22:54:02.966124 # ==>> completed. PASS(1)
11247 22:54:02.972579 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11248 22:54:02.976058 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11249 22:54:02.982646 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11250 22:54:03.008636 # Registered handlers for all signals.
11251 22:54:03.008783 # Detected MINSTKSIGSZ:4720
11252 22:54:03.012000 # Testcase initialized.
11253 22:54:03.015290 # uc context validated.
11254 22:54:03.015399 # Handled SIG_TRIG
11255 22:54:03.025099 # SIG_OK -- SP:0xFFFFED3182B0 si_addr@:0xffffed3182b0 si_code:2 token@:(nil) offset:-281474661188272
11256 22:54:03.028471 # ==>> completed. PASS(1)
11257 22:54:03.035262 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11258 22:54:03.038268 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11259 22:54:03.045138 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11260 22:54:03.083532 # Registered handlers for all signals.
11261 22:54:03.083654 # Detected MINSTKSIGSZ:4720
11262 22:54:03.086828 # Testcase initialized.
11263 22:54:03.090430 # uc context validated.
11264 22:54:03.090536 # Handled SIG_TRIG
11265 22:54:03.100254 # SIG_OK -- SP:0xFFFFE1249D80 si_addr@:0xffffe1249d80 si_code:2 token@:(nil) offset:-281474459016576
11266 22:54:03.103142 # ==>> completed. PASS(1)
11267 22:54:03.109847 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11268 22:54:03.112951 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11269 22:54:03.119720 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11270 22:54:03.146396 # Registered handlers for all signals.
11271 22:54:03.146521 # Detected MINSTKSIGSZ:4720
11272 22:54:03.149572 # Testcase initialized.
11273 22:54:03.153010 # uc context validated.
11274 22:54:03.153116 # Handled SIG_TRIG
11275 22:54:03.162943 # SIG_OK -- SP:0xFFFFF3773E70 si_addr@:0xfffff3773e70 si_code:2 token@:(nil) offset:-281474766421616
11276 22:54:03.166258 # ==>> completed. PASS(1)
11277 22:54:03.172724 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11278 22:54:03.175964 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11279 22:54:03.182717 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11280 22:54:03.194699 # Registered handlers for all signals.
11281 22:54:03.194811 # Detected MINSTKSIGSZ:4720
11282 22:54:03.197995 # Testcase initialized.
11283 22:54:03.201129 # uc context validated.
11284 22:54:03.201241 # Handled SIG_TRIG
11285 22:54:03.211066 # SIG_OK -- SP:0xFFFFEE503940 si_addr@:0xffffee503940 si_code:2 token@:(nil) offset:-281474679978304
11286 22:54:03.214583 # ==>> completed. PASS(1)
11287 22:54:03.221057 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11288 22:54:03.224188 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11289 22:54:03.227415 # selftests: arm64: sme_trap_no_sm
11290 22:54:03.265488 # Registered handlers for all signals.
11291 22:54:03.265636 # Detected MINSTKSIGSZ:4720
11292 22:54:03.268811 # ==>> completed. SKIP.
11293 22:54:03.278712 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11294 22:54:03.281777 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11295 22:54:03.289943 # selftests: arm64: sme_trap_non_streaming
11296 22:54:03.345465 # Registered handlers for all signals.
11297 22:54:03.345606 # Detected MINSTKSIGSZ:4720
11298 22:54:03.348708 # ==>> completed. SKIP.
11299 22:54:03.358490 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11300 22:54:03.365219 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11301 22:54:03.368251 # selftests: arm64: sme_trap_za
11302 22:54:03.413818 # Registered handlers for all signals.
11303 22:54:03.413973 # Detected MINSTKSIGSZ:4720
11304 22:54:03.416810 # Testcase initialized.
11305 22:54:03.426726 # SIG_OK -- SP:0xFFFFE798A770 si_addr@:0xaaaac7e22510 si_code:1 token@:(nil) offset:-187650474648848
11306 22:54:03.426840 # ==>> completed. PASS(1)
11307 22:54:03.436586 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11308 22:54:03.439980 ok 21 selftests: arm64: sme_trap_za
11309 22:54:03.440093 # selftests: arm64: sme_vl
11310 22:54:03.478064 # Registered handlers for all signals.
11311 22:54:03.478198 # Detected MINSTKSIGSZ:4720
11312 22:54:03.481404 # ==>> completed. SKIP.
11313 22:54:03.488230 # # SME VL :: Check that we get the right SME VL reported
11314 22:54:03.491231 ok 22 selftests: arm64: sme_vl # SKIP
11315 22:54:03.494601 # selftests: arm64: ssve_regs
11316 22:54:03.549831 # Registered handlers for all signals.
11317 22:54:03.550003 # Detected MINSTKSIGSZ:4720
11318 22:54:03.553408 # ==>> completed. SKIP.
11319 22:54:03.559688 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11320 22:54:03.566410 ok 23 selftests: arm64: ssve_regs # SKIP
11321 22:54:03.566521 # selftests: arm64: sve_regs
11322 22:54:03.623385 # Registered handlers for all signals.
11323 22:54:03.623555 # Detected MINSTKSIGSZ:4720
11324 22:54:03.626685 # ==>> completed. SKIP.
11325 22:54:03.633319 # # SVE registers :: Check that we get the right SVE registers reported
11326 22:54:03.636774 ok 24 selftests: arm64: sve_regs # SKIP
11327 22:54:03.640159 # selftests: arm64: sve_vl
11328 22:54:03.693020 # Registered handlers for all signals.
11329 22:54:03.693193 # Detected MINSTKSIGSZ:4720
11330 22:54:03.696320 # ==>> completed. SKIP.
11331 22:54:03.702892 # # SVE VL :: Check that we get the right SVE VL reported
11332 22:54:03.706276 ok 25 selftests: arm64: sve_vl # SKIP
11333 22:54:03.709504 # selftests: arm64: za_no_regs
11334 22:54:03.764933 # Registered handlers for all signals.
11335 22:54:03.765094 # Detected MINSTKSIGSZ:4720
11336 22:54:03.768338 # ==>> completed. SKIP.
11337 22:54:03.775117 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11338 22:54:03.778144 ok 26 selftests: arm64: za_no_regs # SKIP
11339 22:54:03.781375 # selftests: arm64: za_regs
11340 22:54:03.842906 # Registered handlers for all signals.
11341 22:54:03.843094 # Detected MINSTKSIGSZ:4720
11342 22:54:03.846211 # ==>> completed. SKIP.
11343 22:54:03.852649 # # ZA register :: Check that we get the right ZA registers reported
11344 22:54:03.856133 ok 27 selftests: arm64: za_regs # SKIP
11345 22:54:03.859524 # selftests: arm64: pac
11346 22:54:03.890815 # TAP version 13
11347 22:54:03.890975 # 1..7
11348 22:54:03.894463 # # Starting 7 tests from 1 test cases.
11349 22:54:03.897462 # # RUN global.corrupt_pac ...
11350 22:54:03.900991 # # SKIP PAUTH not enabled
11351 22:54:03.904026 # # OK global.corrupt_pac
11352 22:54:03.907242 # ok 1 # SKIP PAUTH not enabled
11353 22:54:03.914001 # # RUN global.pac_instructions_not_nop ...
11354 22:54:03.917395 # # SKIP PAUTH not enabled
11355 22:54:03.920637 # # OK global.pac_instructions_not_nop
11356 22:54:03.923833 # ok 2 # SKIP PAUTH not enabled
11357 22:54:03.930547 # # RUN global.pac_instructions_not_nop_generic ...
11358 22:54:03.933645 # # SKIP Generic PAUTH not enabled
11359 22:54:03.936986 # # OK global.pac_instructions_not_nop_generic
11360 22:54:03.943488 # ok 3 # SKIP Generic PAUTH not enabled
11361 22:54:03.947220 # # RUN global.single_thread_different_keys ...
11362 22:54:03.950062 # # SKIP PAUTH not enabled
11363 22:54:03.956733 # # OK global.single_thread_different_keys
11364 22:54:03.956860 # ok 4 # SKIP PAUTH not enabled
11365 22:54:03.963369 # # RUN global.exec_changed_keys ...
11366 22:54:03.966934 # # SKIP PAUTH not enabled
11367 22:54:03.970260 # # OK global.exec_changed_keys
11368 22:54:03.973327 # ok 5 # SKIP PAUTH not enabled
11369 22:54:03.976683 # # RUN global.context_switch_keep_keys ...
11370 22:54:03.979893 # # SKIP PAUTH not enabled
11371 22:54:03.986604 # # OK global.context_switch_keep_keys
11372 22:54:03.989916 # ok 6 # SKIP PAUTH not enabled
11373 22:54:03.993257 # # RUN global.context_switch_keep_keys_generic ...
11374 22:54:03.996371 # # SKIP Generic PAUTH not enabled
11375 22:54:04.003158 # # OK global.context_switch_keep_keys_generic
11376 22:54:04.006430 # ok 7 # SKIP Generic PAUTH not enabled
11377 22:54:04.009499 # # PASSED: 7 / 7 tests passed.
11378 22:54:04.012879 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11379 22:54:04.016334 ok 28 selftests: arm64: pac
11380 22:54:04.019415 # selftests: arm64: fp-stress
11381 22:54:12.324180 <6>[ 37.966402] vpu: disabling
11382 22:54:12.327179 <6>[ 37.969532] vproc2: disabling
11383 22:54:12.330660 <6>[ 37.972815] vproc1: disabling
11384 22:54:12.333952 <6>[ 37.976089] vaud18: disabling
11385 22:54:12.340359 <6>[ 37.979524] vsram_others: disabling
11386 22:54:12.343693 <6>[ 37.983419] va09: disabling
11387 22:54:12.346947 <6>[ 37.986537] vsram_md: disabling
11388 22:54:12.350502 <6>[ 37.990036] Vgpu: disabling
11389 22:54:13.956120 # TAP version 13
11390 22:54:13.956278 # 1..16
11391 22:54:13.959272 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11392 22:54:13.962613 # # Will run for 10s
11393 22:54:13.962695 # # Started FPSIMD-0-0
11394 22:54:13.965879 # # Started FPSIMD-0-1
11395 22:54:13.969169 # # Started FPSIMD-1-0
11396 22:54:13.969251 # # Started FPSIMD-1-1
11397 22:54:13.972698 # # Started FPSIMD-2-0
11398 22:54:13.975858 # # Started FPSIMD-2-1
11399 22:54:13.975939 # # Started FPSIMD-3-0
11400 22:54:13.979102 # # Started FPSIMD-3-1
11401 22:54:13.982266 # # Started FPSIMD-4-0
11402 22:54:13.982347 # # Started FPSIMD-4-1
11403 22:54:13.985777 # # Started FPSIMD-5-0
11404 22:54:13.985858 # # Started FPSIMD-5-1
11405 22:54:13.988829 # # Started FPSIMD-6-0
11406 22:54:13.992308 # # Started FPSIMD-6-1
11407 22:54:13.992389 # # Started FPSIMD-7-0
11408 22:54:13.995633 # # Started FPSIMD-7-1
11409 22:54:13.998900 # # FPSIMD-0-0: Vector length: 128 bits
11410 22:54:14.002077 # # FPSIMD-0-0: PID: 1158
11411 22:54:14.005438 # # FPSIMD-0-1: Vector length: 128 bits
11412 22:54:14.008623 # # FPSIMD-0-1: PID: 1159
11413 22:54:14.012202 # # FPSIMD-1-0: Vector length: 128 bits
11414 22:54:14.012282 # # FPSIMD-1-0: PID: 1160
11415 22:54:14.015390 # # FPSIMD-1-1: Vector length: 128 bits
11416 22:54:14.018626 # # FPSIMD-1-1: PID: 1161
11417 22:54:14.021888 # # FPSIMD-2-0: Vector length: 128 bits
11418 22:54:14.025209 # # FPSIMD-2-0: PID: 1162
11419 22:54:14.028782 # # FPSIMD-4-1: Vector length: 128 bits
11420 22:54:14.031765 # # FPSIMD-4-1: PID: 1167
11421 22:54:14.035218 # # FPSIMD-4-0: Vector length: 128 bits
11422 22:54:14.035298 # # FPSIMD-4-0: PID: 1166
11423 22:54:14.041632 # # FPSIMD-5-0: Vector length: 128 bits
11424 22:54:14.041713 # # FPSIMD-5-0: PID: 1168
11425 22:54:14.044932 # # FPSIMD-2-1: Vector length: 128 bits
11426 22:54:14.048415 # # FPSIMD-2-1: PID: 1163
11427 22:54:14.051518 # # FPSIMD-3-1: Vector length: 128 bits
11428 22:54:14.054967 # # FPSIMD-3-1: PID: 1165
11429 22:54:14.058567 # # FPSIMD-7-1: Vector length: 128 bits
11430 22:54:14.061437 # # FPSIMD-7-1: PID: 1173
11431 22:54:14.064783 # # FPSIMD-7-0: Vector length: 128 bits
11432 22:54:14.064864 # # FPSIMD-7-0: PID: 1172
11433 22:54:14.068294 # # FPSIMD-6-0: Vector length: 128 bits
11434 22:54:14.071522 # # FPSIMD-6-0: PID: 1170
11435 22:54:14.074769 # # FPSIMD-6-1: Vector length: 128 bits
11436 22:54:14.078001 # # FPSIMD-6-1: PID: 1171
11437 22:54:14.081415 # # FPSIMD-3-0: Vector length: 128 bits
11438 22:54:14.084702 # # FPSIMD-3-0: PID: 1164
11439 22:54:14.087734 # # FPSIMD-5-1: Vector length: 128 bits
11440 22:54:14.091143 # # FPSIMD-5-1: PID: 1169
11441 22:54:14.091222 # # Finishing up...
11442 22:54:14.097761 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=2102659, signals=10
11443 22:54:14.104264 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1018455, signals=10
11444 22:54:14.114125 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1008514, signals=10
11445 22:54:14.120843 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1003148, signals=10
11446 22:54:14.127536 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=2140136, signals=10
11447 22:54:14.134012 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=2193974, signals=10
11448 22:54:14.140718 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=2158471, signals=10
11449 22:54:14.143879 # ok 1 FPSIMD-0-0
11450 22:54:14.143960 # ok 2 FPSIMD-0-1
11451 22:54:14.147434 # ok 3 FPSIMD-1-0
11452 22:54:14.147515 # ok 4 FPSIMD-1-1
11453 22:54:14.150558 # ok 5 FPSIMD-2-0
11454 22:54:14.150639 # ok 6 FPSIMD-2-1
11455 22:54:14.153721 # ok 7 FPSIMD-3-0
11456 22:54:14.153801 # ok 8 FPSIMD-3-1
11457 22:54:14.156937 # ok 9 FPSIMD-4-0
11458 22:54:14.157018 # ok 10 FPSIMD-4-1
11459 22:54:14.160321 # ok 11 FPSIMD-5-0
11460 22:54:14.160403 # ok 12 FPSIMD-5-1
11461 22:54:14.163674 # ok 13 FPSIMD-6-0
11462 22:54:14.166991 # ok 14 FPSIMD-6-1
11463 22:54:14.167072 # ok 15 FPSIMD-7-0
11464 22:54:14.170330 # ok 16 FPSIMD-7-1
11465 22:54:14.177002 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=990824, signals=9
11466 22:54:14.183608 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1005218, signals=10
11467 22:54:14.190640 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1003728, signals=10
11468 22:54:14.196714 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=992724, signals=9
11469 22:54:14.203439 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1051020, signals=10
11470 22:54:14.213087 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1166803, signals=10
11471 22:54:14.219799 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=996058, signals=10
11472 22:54:14.226411 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1043733, signals=9
11473 22:54:14.232981 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1008706, signals=9
11474 22:54:14.239627 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11475 22:54:14.243034 ok 29 selftests: arm64: fp-stress
11476 22:54:14.243115 # selftests: arm64: sve-ptrace
11477 22:54:14.246298 # TAP version 13
11478 22:54:14.246377 # 1..4104
11479 22:54:14.249397 # ok 2 # SKIP SVE not available
11480 22:54:14.253140 # # Planned tests != run tests (4104 != 1)
11481 22:54:14.259460 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11482 22:54:14.262716 ok 30 selftests: arm64: sve-ptrace # SKIP
11483 22:54:14.266283 # selftests: arm64: sve-probe-vls
11484 22:54:14.266362 # TAP version 13
11485 22:54:14.266424 # 1..2
11486 22:54:14.269550 # ok 2 # SKIP SVE not available
11487 22:54:14.272600 # # Planned tests != run tests (2 != 1)
11488 22:54:14.279242 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11489 22:54:14.282604 ok 31 selftests: arm64: sve-probe-vls # SKIP
11490 22:54:14.285761 # selftests: arm64: vec-syscfg
11491 22:54:14.285841 # TAP version 13
11492 22:54:14.289185 # 1..20
11493 22:54:14.289264 # ok 1 # SKIP SVE not supported
11494 22:54:14.292474 # ok 2 # SKIP SVE not supported
11495 22:54:14.295989 # ok 3 # SKIP SVE not supported
11496 22:54:14.299111 # ok 4 # SKIP SVE not supported
11497 22:54:14.302440 # ok 5 # SKIP SVE not supported
11498 22:54:14.305706 # ok 6 # SKIP SVE not supported
11499 22:54:14.308903 # ok 7 # SKIP SVE not supported
11500 22:54:14.312153 # ok 8 # SKIP SVE not supported
11501 22:54:14.312232 # ok 9 # SKIP SVE not supported
11502 22:54:14.315713 # ok 10 # SKIP SVE not supported
11503 22:54:14.319000 # ok 11 # SKIP SME not supported
11504 22:54:14.322175 # ok 12 # SKIP SME not supported
11505 22:54:14.325646 # ok 13 # SKIP SME not supported
11506 22:54:14.328785 # ok 14 # SKIP SME not supported
11507 22:54:14.332171 # ok 15 # SKIP SME not supported
11508 22:54:14.335377 # ok 16 # SKIP SME not supported
11509 22:54:14.338806 # ok 17 # SKIP SME not supported
11510 22:54:14.338886 # ok 18 # SKIP SME not supported
11511 22:54:14.342136 # ok 19 # SKIP SME not supported
11512 22:54:14.345321 # ok 20 # SKIP SME not supported
11513 22:54:14.352210 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11514 22:54:14.355425 ok 32 selftests: arm64: vec-syscfg
11515 22:54:14.358571 # selftests: arm64: za-fork
11516 22:54:14.358651 # TAP version 13
11517 22:54:14.358713 # 1..1
11518 22:54:14.361742 # # PID: 1250
11519 22:54:14.361821 # # SME support not present
11520 22:54:14.365129 # ok 0 skipped
11521 22:54:14.368385 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11522 22:54:14.371779 ok 33 selftests: arm64: za-fork
11523 22:54:14.375105 # selftests: arm64: za-ptrace
11524 22:54:14.375185 # TAP version 13
11525 22:54:14.378310 # 1..1
11526 22:54:14.381657 # ok 2 # SKIP SME not available
11527 22:54:14.384886 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11528 22:54:14.388251 ok 34 selftests: arm64: za-ptrace # SKIP
11529 22:54:14.391458 # selftests: arm64: check_buffer_fill
11530 22:54:14.399956 # # SKIP: MTE features unavailable
11531 22:54:14.406640 ok 35 selftests: arm64: check_buffer_fill # SKIP
11532 22:54:14.422419 # selftests: arm64: check_child_memory
11533 22:54:14.469275 # # SKIP: MTE features unavailable
11534 22:54:14.476229 ok 36 selftests: arm64: check_child_memory # SKIP
11535 22:54:14.490482 # selftests: arm64: check_gcr_el1_cswitch
11536 22:54:14.528952 # # SKIP: MTE features unavailable
11537 22:54:14.535487 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11538 22:54:14.546846 # selftests: arm64: check_ksm_options
11539 22:54:14.605919 # # SKIP: MTE features unavailable
11540 22:54:14.613294 ok 38 selftests: arm64: check_ksm_options # SKIP
11541 22:54:14.626277 # selftests: arm64: check_mmap_options
11542 22:54:14.660989 # # SKIP: MTE features unavailable
11543 22:54:14.669085 ok 39 selftests: arm64: check_mmap_options # SKIP
11544 22:54:14.680250 # selftests: arm64: check_prctl
11545 22:54:14.730586 # TAP version 13
11546 22:54:14.730692 # 1..5
11547 22:54:14.733914 # ok 1 check_basic_read
11548 22:54:14.734019 # ok 2 NONE
11549 22:54:14.737334 # ok 3 # SKIP SYNC
11550 22:54:14.737413 # ok 4 # SKIP ASYNC
11551 22:54:14.740549 # ok 5 # SKIP SYNC+ASYNC
11552 22:54:14.743812 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11553 22:54:14.747010 ok 40 selftests: arm64: check_prctl
11554 22:54:14.753715 # selftests: arm64: check_tags_inclusion
11555 22:54:14.806147 # # SKIP: MTE features unavailable
11556 22:54:14.813520 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11557 22:54:14.823546 # selftests: arm64: check_user_mem
11558 22:54:14.872497 # # SKIP: MTE features unavailable
11559 22:54:14.879489 ok 42 selftests: arm64: check_user_mem # SKIP
11560 22:54:14.889858 # selftests: arm64: btitest
11561 22:54:14.941705 # TAP version 13
11562 22:54:14.941794 # 1..18
11563 22:54:14.944698 # # HWCAP_PACA not present
11564 22:54:14.948163 # # HWCAP2_BTI not present
11565 22:54:14.948243 # # Test binary built for BTI
11566 22:54:14.954734 # ok 1 nohint_func/call_using_br_x0 # SKIP
11567 22:54:14.957857 # ok 1 nohint_func/call_using_br_x16 # SKIP
11568 22:54:14.961216 # ok 1 nohint_func/call_using_blr # SKIP
11569 22:54:14.964561 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11570 22:54:14.967823 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11571 22:54:14.974745 # ok 1 bti_none_func/call_using_blr # SKIP
11572 22:54:14.978006 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11573 22:54:14.981110 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11574 22:54:14.984376 # ok 1 bti_c_func/call_using_blr # SKIP
11575 22:54:14.987769 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11576 22:54:14.991040 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11577 22:54:14.994407 # ok 1 bti_j_func/call_using_blr # SKIP
11578 22:54:14.997699 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11579 22:54:15.004207 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11580 22:54:15.007966 # ok 1 bti_jc_func/call_using_blr # SKIP
11581 22:54:15.011155 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11582 22:54:15.014344 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11583 22:54:15.017317 # ok 1 paciasp_func/call_using_blr # SKIP
11584 22:54:15.024012 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11585 22:54:15.027434 # # WARNING - EXPECTED TEST COUNT WRONG
11586 22:54:15.030805 ok 43 selftests: arm64: btitest
11587 22:54:15.033822 # selftests: arm64: nobtitest
11588 22:54:15.033902 # TAP version 13
11589 22:54:15.033966 # 1..18
11590 22:54:15.037146 # # HWCAP_PACA not present
11591 22:54:15.040549 # # HWCAP2_BTI not present
11592 22:54:15.043728 # # Test binary not built for BTI
11593 22:54:15.047218 # ok 1 nohint_func/call_using_br_x0 # SKIP
11594 22:54:15.050331 # ok 1 nohint_func/call_using_br_x16 # SKIP
11595 22:54:15.053718 # ok 1 nohint_func/call_using_blr # SKIP
11596 22:54:15.057193 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11597 22:54:15.063615 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11598 22:54:15.067014 # ok 1 bti_none_func/call_using_blr # SKIP
11599 22:54:15.070147 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11600 22:54:15.073714 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11601 22:54:15.076875 # ok 1 bti_c_func/call_using_blr # SKIP
11602 22:54:15.080143 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11603 22:54:15.083358 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11604 22:54:15.086739 # ok 1 bti_j_func/call_using_blr # SKIP
11605 22:54:15.093201 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11606 22:54:15.096496 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11607 22:54:15.099746 # ok 1 bti_jc_func/call_using_blr # SKIP
11608 22:54:15.103203 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11609 22:54:15.106360 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11610 22:54:15.109742 # ok 1 paciasp_func/call_using_blr # SKIP
11611 22:54:15.116556 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11612 22:54:15.119644 # # WARNING - EXPECTED TEST COUNT WRONG
11613 22:54:15.122822 ok 44 selftests: arm64: nobtitest
11614 22:54:15.126218 # selftests: arm64: hwcap
11615 22:54:15.126297 # TAP version 13
11616 22:54:15.126360 # 1..28
11617 22:54:15.129450 # ok 1 cpuinfo_match_RNG
11618 22:54:15.132913 # # SIGILL reported for RNG
11619 22:54:15.136036 # ok 2 # SKIP sigill_RNG
11620 22:54:15.136116 # ok 3 cpuinfo_match_SME
11621 22:54:15.139587 # ok 4 sigill_SME
11622 22:54:15.139667 # ok 5 cpuinfo_match_SVE
11623 22:54:15.142656 # ok 6 sigill_SVE
11624 22:54:15.146352 # ok 7 cpuinfo_match_SVE 2
11625 22:54:15.146431 # # SIGILL reported for SVE 2
11626 22:54:15.149227 # ok 8 # SKIP sigill_SVE 2
11627 22:54:15.152666 # ok 9 cpuinfo_match_SVE AES
11628 22:54:15.155897 # # SIGILL reported for SVE AES
11629 22:54:15.159505 # ok 10 # SKIP sigill_SVE AES
11630 22:54:15.162697 # ok 11 cpuinfo_match_SVE2 PMULL
11631 22:54:15.162777 # # SIGILL reported for SVE2 PMULL
11632 22:54:15.165935 # ok 12 # SKIP sigill_SVE2 PMULL
11633 22:54:15.169283 # ok 13 cpuinfo_match_SVE2 BITPERM
11634 22:54:15.172394 # # SIGILL reported for SVE2 BITPERM
11635 22:54:15.175948 # ok 14 # SKIP sigill_SVE2 BITPERM
11636 22:54:15.179070 # ok 15 cpuinfo_match_SVE2 SHA3
11637 22:54:15.182503 # # SIGILL reported for SVE2 SHA3
11638 22:54:15.185623 # ok 16 # SKIP sigill_SVE2 SHA3
11639 22:54:15.188984 # ok 17 cpuinfo_match_SVE2 SM4
11640 22:54:15.192290 # # SIGILL reported for SVE2 SM4
11641 22:54:15.192396 # ok 18 # SKIP sigill_SVE2 SM4
11642 22:54:15.195793 # ok 19 cpuinfo_match_SVE2 I8MM
11643 22:54:15.198837 # # SIGILL reported for SVE2 I8MM
11644 22:54:15.202309 # ok 20 # SKIP sigill_SVE2 I8MM
11645 22:54:15.205554 # ok 21 cpuinfo_match_SVE2 F32MM
11646 22:54:15.208820 # # SIGILL reported for SVE2 F32MM
11647 22:54:15.212123 # ok 22 # SKIP sigill_SVE2 F32MM
11648 22:54:15.215414 # ok 23 cpuinfo_match_SVE2 F64MM
11649 22:54:15.218931 # # SIGILL reported for SVE2 F64MM
11650 22:54:15.222154 # ok 24 # SKIP sigill_SVE2 F64MM
11651 22:54:15.222234 # ok 25 cpuinfo_match_SVE2 BF16
11652 22:54:15.225453 # # SIGILL reported for SVE2 BF16
11653 22:54:15.228609 # ok 26 # SKIP sigill_SVE2 BF16
11654 22:54:15.232126 # ok 27 cpuinfo_match_SVE2 EBF16
11655 22:54:15.235232 # ok 28 # SKIP sigill_SVE2 EBF16
11656 22:54:15.241824 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11657 22:54:15.241935 ok 45 selftests: arm64: hwcap
11658 22:54:15.245156 # selftests: arm64: ptrace
11659 22:54:15.248490 # TAP version 13
11660 22:54:15.248570 # 1..7
11661 22:54:15.251812 # # Parent is 1492, child is 1493
11662 22:54:15.251903 # ok 1 read_tpidr_one
11663 22:54:15.255054 # ok 2 write_tpidr_one
11664 22:54:15.258529 # ok 3 verify_tpidr_one
11665 22:54:15.258609 # ok 4 count_tpidrs
11666 22:54:15.261536 # ok 5 tpidr2_write
11667 22:54:15.261616 # ok 6 tpidr2_read
11668 22:54:15.264968 # ok 7 write_tpidr_only
11669 22:54:15.268123 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11670 22:54:15.271508 ok 46 selftests: arm64: ptrace
11671 22:54:15.274785 # selftests: arm64: syscall-abi
11672 22:54:15.278233 # TAP version 13
11673 22:54:15.278313 # 1..2
11674 22:54:15.281581 # ok 1 getpid() FPSIMD
11675 22:54:15.281660 # ok 2 sched_yield() FPSIMD
11676 22:54:15.287911 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11677 22:54:15.291398 ok 47 selftests: arm64: syscall-abi
11678 22:54:15.294750 # selftests: arm64: tpidr2
11679 22:54:15.294829 # TAP version 13
11680 22:54:15.297845 # 1..5
11681 22:54:15.297964 # # PID: 1529
11682 22:54:15.301272 # # SME support not present
11683 22:54:15.304555 # ok 0 skipped, TPIDR2 not supported
11684 22:54:15.308018 # ok 1 skipped, TPIDR2 not supported
11685 22:54:15.310955 # ok 2 skipped, TPIDR2 not supported
11686 22:54:15.314291 # ok 3 skipped, TPIDR2 not supported
11687 22:54:15.317715 # ok 4 skipped, TPIDR2 not supported
11688 22:54:15.321066 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11689 22:54:15.324274 ok 48 selftests: arm64: tpidr2
11690 22:54:16.746881 arm64_tags_test pass
11691 22:54:16.750258 arm64_run_tags_test_sh pass
11692 22:54:16.753704 arm64_fake_sigreturn_bad_magic pass
11693 22:54:16.757036 arm64_fake_sigreturn_bad_size pass
11694 22:54:16.760016 arm64_fake_sigreturn_bad_size_for_magic0 pass
11695 22:54:16.763703 arm64_fake_sigreturn_duplicated_fpsimd pass
11696 22:54:16.766998 arm64_fake_sigreturn_misaligned_sp pass
11697 22:54:16.769887 arm64_fake_sigreturn_missing_fpsimd pass
11698 22:54:16.773251 arm64_fake_sigreturn_sme_change_vl skip
11699 22:54:16.779957 arm64_fake_sigreturn_sve_change_vl skip
11700 22:54:16.783222 arm64_mangle_pstate_invalid_compat_toggle pass
11701 22:54:16.786569 arm64_mangle_pstate_invalid_daif_bits pass
11702 22:54:16.789677 arm64_mangle_pstate_invalid_mode_el1h pass
11703 22:54:16.793159 arm64_mangle_pstate_invalid_mode_el1t pass
11704 22:54:16.796382 arm64_mangle_pstate_invalid_mode_el2h pass
11705 22:54:16.802890 arm64_mangle_pstate_invalid_mode_el2t pass
11706 22:54:16.806193 arm64_mangle_pstate_invalid_mode_el3h pass
11707 22:54:16.809400 arm64_mangle_pstate_invalid_mode_el3t pass
11708 22:54:16.812900 arm64_sme_trap_no_sm skip
11709 22:54:16.816563 arm64_sme_trap_non_streaming skip
11710 22:54:16.816643 arm64_sme_trap_za pass
11711 22:54:16.819532 arm64_sme_vl skip
11712 22:54:16.819611 arm64_ssve_regs skip
11713 22:54:16.822759 arm64_sve_regs skip
11714 22:54:16.822843 arm64_sve_vl skip
11715 22:54:16.826286 arm64_za_no_regs skip
11716 22:54:16.826365 arm64_za_regs skip
11717 22:54:16.829557 arm64_pac_PAUTH_not_enabled skip
11718 22:54:16.832677 arm64_pac_PAUTH_not_enabled_dup2 skip
11719 22:54:16.835790 arm64_pac_Generic_PAUTH_not_enabled skip
11720 22:54:16.839184 arm64_pac_PAUTH_not_enabled_dup3 skip
11721 22:54:16.842473 arm64_pac_PAUTH_not_enabled_dup4 skip
11722 22:54:16.845732 arm64_pac_PAUTH_not_enabled_dup5 skip
11723 22:54:16.852391 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11724 22:54:16.852470 arm64_pac pass
11725 22:54:16.855938 arm64_fp-stress_FPSIMD-0-0 pass
11726 22:54:16.859153 arm64_fp-stress_FPSIMD-0-1 pass
11727 22:54:16.862425 arm64_fp-stress_FPSIMD-1-0 pass
11728 22:54:16.865650 arm64_fp-stress_FPSIMD-1-1 pass
11729 22:54:16.865755 arm64_fp-stress_FPSIMD-2-0 pass
11730 22:54:16.868957 arm64_fp-stress_FPSIMD-2-1 pass
11731 22:54:16.872409 arm64_fp-stress_FPSIMD-3-0 pass
11732 22:54:16.875556 arm64_fp-stress_FPSIMD-3-1 pass
11733 22:54:16.878836 arm64_fp-stress_FPSIMD-4-0 pass
11734 22:54:16.882194 arm64_fp-stress_FPSIMD-4-1 pass
11735 22:54:16.885568 arm64_fp-stress_FPSIMD-5-0 pass
11736 22:54:16.888853 arm64_fp-stress_FPSIMD-5-1 pass
11737 22:54:16.888932 arm64_fp-stress_FPSIMD-6-0 pass
11738 22:54:16.892014 arm64_fp-stress_FPSIMD-6-1 pass
11739 22:54:16.895329 arm64_fp-stress_FPSIMD-7-0 pass
11740 22:54:16.899243 arm64_fp-stress_FPSIMD-7-1 pass
11741 22:54:16.902201 arm64_fp-stress pass
11742 22:54:16.905442 arm64_sve-ptrace_SVE_not_available skip
11743 22:54:16.905521 arm64_sve-ptrace skip
11744 22:54:16.908770 arm64_sve-probe-vls_SVE_not_available skip
11745 22:54:16.911989 arm64_sve-probe-vls skip
11746 22:54:16.915114 arm64_vec-syscfg_SVE_not_supported skip
11747 22:54:16.918419 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11748 22:54:16.924973 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11749 22:54:16.928447 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11750 22:54:16.931743 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11751 22:54:16.935046 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11752 22:54:16.938232 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11753 22:54:16.945010 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11754 22:54:16.948142 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11755 22:54:16.951474 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11756 22:54:16.955186 arm64_vec-syscfg_SME_not_supported skip
11757 22:54:16.958137 arm64_vec-syscfg_SME_not_supported_dup2 skip
11758 22:54:16.964608 arm64_vec-syscfg_SME_not_supported_dup3 skip
11759 22:54:16.967871 arm64_vec-syscfg_SME_not_supported_dup4 skip
11760 22:54:16.971226 arm64_vec-syscfg_SME_not_supported_dup5 skip
11761 22:54:16.974622 arm64_vec-syscfg_SME_not_supported_dup6 skip
11762 22:54:16.977772 arm64_vec-syscfg_SME_not_supported_dup7 skip
11763 22:54:16.984747 arm64_vec-syscfg_SME_not_supported_dup8 skip
11764 22:54:16.988029 arm64_vec-syscfg_SME_not_supported_dup9 skip
11765 22:54:16.991123 arm64_vec-syscfg_SME_not_supported_dup10 skip
11766 22:54:16.994376 arm64_vec-syscfg pass
11767 22:54:16.994455 arm64_za-fork_skipped pass
11768 22:54:16.997731 arm64_za-fork pass
11769 22:54:17.001337 arm64_za-ptrace_SME_not_available skip
11770 22:54:17.004425 arm64_za-ptrace skip
11771 22:54:17.004505 arm64_check_buffer_fill skip
11772 22:54:17.007490 arm64_check_child_memory skip
11773 22:54:17.010737 arm64_check_gcr_el1_cswitch skip
11774 22:54:17.014341 arm64_check_ksm_options skip
11775 22:54:17.017700 arm64_check_mmap_options skip
11776 22:54:17.020681 arm64_check_prctl_check_basic_read pass
11777 22:54:17.023959 arm64_check_prctl_NONE pass
11778 22:54:17.024039 arm64_check_prctl_SYNC skip
11779 22:54:17.027271 arm64_check_prctl_ASYNC skip
11780 22:54:17.030506 arm64_check_prctl_SYNC_ASYNC skip
11781 22:54:17.033841 arm64_check_prctl pass
11782 22:54:17.037114 arm64_check_tags_inclusion skip
11783 22:54:17.037193 arm64_check_user_mem skip
11784 22:54:17.043830 arm64_btitest_nohint_func_call_using_br_x0 skip
11785 22:54:17.047046 arm64_btitest_nohint_func_call_using_br_x16 skip
11786 22:54:17.050436 arm64_btitest_nohint_func_call_using_blr skip
11787 22:54:17.053814 arm64_btitest_bti_none_func_call_using_br_x0 skip
11788 22:54:17.060390 arm64_btitest_bti_none_func_call_using_br_x16 skip
11789 22:54:17.063682 arm64_btitest_bti_none_func_call_using_blr skip
11790 22:54:17.067456 arm64_btitest_bti_c_func_call_using_br_x0 skip
11791 22:54:17.073700 arm64_btitest_bti_c_func_call_using_br_x16 skip
11792 22:54:17.076814 arm64_btitest_bti_c_func_call_using_blr skip
11793 22:54:17.080203 arm64_btitest_bti_j_func_call_using_br_x0 skip
11794 22:54:17.083556 arm64_btitest_bti_j_func_call_using_br_x16 skip
11795 22:54:17.090043 arm64_btitest_bti_j_func_call_using_blr skip
11796 22:54:17.093398 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11797 22:54:17.096602 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11798 22:54:17.100042 arm64_btitest_bti_jc_func_call_using_blr skip
11799 22:54:17.106631 arm64_btitest_paciasp_func_call_using_br_x0 skip
11800 22:54:17.109945 arm64_btitest_paciasp_func_call_using_br_x16 skip
11801 22:54:17.113308 arm64_btitest_paciasp_func_call_using_blr skip
11802 22:54:17.116572 arm64_btitest pass
11803 22:54:17.120070 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11804 22:54:17.126313 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11805 22:54:17.129703 arm64_nobtitest_nohint_func_call_using_blr skip
11806 22:54:17.132989 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11807 22:54:17.139779 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11808 22:54:17.142876 arm64_nobtitest_bti_none_func_call_using_blr skip
11809 22:54:17.146319 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11810 22:54:17.152726 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11811 22:54:17.156116 arm64_nobtitest_bti_c_func_call_using_blr skip
11812 22:54:17.159390 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11813 22:54:17.165912 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11814 22:54:17.169566 arm64_nobtitest_bti_j_func_call_using_blr skip
11815 22:54:17.172827 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11816 22:54:17.179169 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11817 22:54:17.182651 arm64_nobtitest_bti_jc_func_call_using_blr skip
11818 22:54:17.185847 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11819 22:54:17.192358 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11820 22:54:17.195842 arm64_nobtitest_paciasp_func_call_using_blr skip
11821 22:54:17.195922 arm64_nobtitest pass
11822 22:54:17.199174 arm64_hwcap_cpuinfo_match_RNG pass
11823 22:54:17.202414 arm64_hwcap_sigill_RNG skip
11824 22:54:17.205656 arm64_hwcap_cpuinfo_match_SME pass
11825 22:54:17.209315 arm64_hwcap_sigill_SME pass
11826 22:54:17.212443 arm64_hwcap_cpuinfo_match_SVE pass
11827 22:54:17.215603 arm64_hwcap_sigill_SVE pass
11828 22:54:17.218837 arm64_hwcap_cpuinfo_match_SVE_2 pass
11829 22:54:17.218917 arm64_hwcap_sigill_SVE_2 skip
11830 22:54:17.222450 arm64_hwcap_cpuinfo_match_SVE_AES pass
11831 22:54:17.225517 arm64_hwcap_sigill_SVE_AES skip
11832 22:54:17.228824 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11833 22:54:17.232304 arm64_hwcap_sigill_SVE2_PMULL skip
11834 22:54:17.238778 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11835 22:54:17.242203 arm64_hwcap_sigill_SVE2_BITPERM skip
11836 22:54:17.245430 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11837 22:54:17.248768 arm64_hwcap_sigill_SVE2_SHA3 skip
11838 22:54:17.251905 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11839 22:54:17.255382 arm64_hwcap_sigill_SVE2_SM4 skip
11840 22:54:17.258775 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11841 22:54:17.261957 arm64_hwcap_sigill_SVE2_I8MM skip
11842 22:54:17.265390 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11843 22:54:17.268829 arm64_hwcap_sigill_SVE2_F32MM skip
11844 22:54:17.271805 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11845 22:54:17.275165 arm64_hwcap_sigill_SVE2_F64MM skip
11846 22:54:17.278785 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11847 22:54:17.281888 arm64_hwcap_sigill_SVE2_BF16 skip
11848 22:54:17.285017 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11849 22:54:17.288280 arm64_hwcap_sigill_SVE2_EBF16 skip
11850 22:54:17.288360 arm64_hwcap pass
11851 22:54:17.291885 arm64_ptrace_read_tpidr_one pass
11852 22:54:17.295138 arm64_ptrace_write_tpidr_one pass
11853 22:54:17.298462 arm64_ptrace_verify_tpidr_one pass
11854 22:54:17.301521 arm64_ptrace_count_tpidrs pass
11855 22:54:17.304878 arm64_ptrace_tpidr2_write pass
11856 22:54:17.308040 arm64_ptrace_tpidr2_read pass
11857 22:54:17.311499 arm64_ptrace_write_tpidr_only pass
11858 22:54:17.311579 arm64_ptrace pass
11859 22:54:17.315096 arm64_syscall-abi_getpid_FPSIMD pass
11860 22:54:17.318227 arm64_syscall-abi_sched_yield_FPSIMD pass
11861 22:54:17.321220 arm64_syscall-abi pass
11862 22:54:17.324518 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11863 22:54:17.328055 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
11864 22:54:17.334400 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
11865 22:54:17.337676 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
11866 22:54:17.344444 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
11867 22:54:17.344553 arm64_tpidr2 pass
11868 22:54:17.347568 + ../../utils/send-to-lava.sh ./output/result.txt
11869 22:54:17.354189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11870 22:54:17.354462 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11872 22:54:17.360895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11873 22:54:17.361145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11875 22:54:17.367437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11876 22:54:17.367686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11878 22:54:17.374191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11879 22:54:17.374443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11881 22:54:17.380869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11882 22:54:17.381117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11884 22:54:17.387248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11885 22:54:17.387497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11887 22:54:17.397366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11888 22:54:17.397615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11890 22:54:17.404204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11891 22:54:17.404455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11893 22:54:17.410383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11894 22:54:17.410633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11896 22:54:17.434640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11897 22:54:17.434897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11899 22:54:17.468250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11900 22:54:17.468507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11902 22:54:17.498902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11903 22:54:17.499154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11905 22:54:17.528509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11906 22:54:17.528767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11908 22:54:17.564944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11909 22:54:17.565198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11911 22:54:17.602606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11912 22:54:17.602858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11914 22:54:17.634054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11915 22:54:17.634325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11917 22:54:17.667117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11918 22:54:17.667371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11920 22:54:17.701178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11921 22:54:17.701431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11923 22:54:17.741233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11924 22:54:17.741491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11926 22:54:17.776958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11927 22:54:17.777212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11929 22:54:17.817643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11931 22:54:17.820881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11932 22:54:17.854838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11933 22:54:17.855096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11935 22:54:17.887210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11936 22:54:17.887463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
11938 22:54:17.921945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
11939 22:54:17.922260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
11941 22:54:17.957779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
11942 22:54:17.958074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
11944 22:54:17.993287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
11945 22:54:17.993539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
11947 22:54:18.031495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
11948 22:54:18.031757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
11950 22:54:18.071309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
11951 22:54:18.071565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
11953 22:54:18.113741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
11955 22:54:18.116897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
11956 22:54:18.156701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
11957 22:54:18.156964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
11959 22:54:18.192422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
11960 22:54:18.192674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
11962 22:54:18.231864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
11963 22:54:18.232128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
11965 22:54:18.265237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
11966 22:54:18.265537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
11968 22:54:18.294456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
11969 22:54:18.294713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
11971 22:54:18.327339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
11972 22:54:18.327602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
11974 22:54:18.356619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
11975 22:54:18.356904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
11977 22:54:18.389812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
11978 22:54:18.390062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
11980 22:54:18.422834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
11981 22:54:18.423094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
11983 22:54:18.457554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
11984 22:54:18.457814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
11986 22:54:18.493813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
11987 22:54:18.494076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
11989 22:54:18.534867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
11990 22:54:18.535130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
11992 22:54:18.570715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
11993 22:54:18.570969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
11995 22:54:18.605921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
11996 22:54:18.606213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
11998 22:54:18.641436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
11999 22:54:18.641707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12001 22:54:18.673947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12002 22:54:18.674221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12004 22:54:18.708075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12005 22:54:18.708347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12007 22:54:18.741609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12008 22:54:18.741869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12010 22:54:18.769472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12011 22:54:18.769726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12013 22:54:18.799548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12014 22:54:18.799799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12016 22:54:18.831618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12017 22:54:18.831904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12019 22:54:18.861708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12020 22:54:18.861991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12022 22:54:18.893610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12023 22:54:18.893892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12025 22:54:18.924177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12026 22:54:18.924440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12028 22:54:18.963195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12029 22:54:18.963470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12031 22:54:18.997118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12032 22:54:18.997423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12034 22:54:19.037186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12035 22:54:19.037480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12037 22:54:19.072176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12038 22:54:19.072488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12040 22:54:19.109527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12041 22:54:19.109843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12043 22:54:19.147608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12044 22:54:19.147903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12046 22:54:19.183544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12047 22:54:19.183805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12049 22:54:19.222084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12050 22:54:19.222343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12052 22:54:19.257295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12053 22:54:19.257593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12055 22:54:19.290694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12056 22:54:19.291012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12058 22:54:19.331255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12059 22:54:19.331580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12061 22:54:19.367081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12062 22:54:19.367390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12064 22:54:19.401317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12065 22:54:19.401588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12067 22:54:19.436871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12068 22:54:19.437176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12070 22:54:19.467495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12071 22:54:19.467778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12073 22:54:19.501548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12074 22:54:19.501828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12076 22:54:19.534086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12077 22:54:19.534403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12079 22:54:19.573472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12080 22:54:19.573799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12082 22:54:19.607827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12083 22:54:19.608149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12085 22:54:19.640688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12086 22:54:19.640968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12088 22:54:19.677172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12089 22:54:19.677433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12091 22:54:19.716991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12092 22:54:19.717252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12094 22:54:19.757358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12095 22:54:19.757627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12097 22:54:19.793168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12098 22:54:19.793422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12100 22:54:19.825225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12101 22:54:19.825479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12103 22:54:19.861580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12104 22:54:19.861850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12106 22:54:19.894272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12107 22:54:19.894529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12109 22:54:19.929924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12110 22:54:19.930229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12112 22:54:19.960031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12113 22:54:19.960287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12115 22:54:19.992566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12116 22:54:19.992818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12118 22:54:20.029786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12119 22:54:20.030075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12121 22:54:20.061751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12123 22:54:20.064580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12124 22:54:20.092676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12125 22:54:20.092980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12127 22:54:20.124639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12128 22:54:20.124952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12130 22:54:20.160416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12131 22:54:20.160739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12133 22:54:20.191005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12134 22:54:20.191310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12136 22:54:20.225966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12137 22:54:20.226305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12139 22:54:20.265486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12140 22:54:20.265784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12142 22:54:20.303746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12144 22:54:20.306748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12145 22:54:20.337081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12146 22:54:20.337377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12148 22:54:20.374794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12149 22:54:20.375085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12151 22:54:20.413176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12152 22:54:20.413473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12154 22:54:20.457391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12155 22:54:20.457726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12157 22:54:20.494185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12158 22:54:20.494473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12160 22:54:20.531478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12161 22:54:20.531787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12163 22:54:20.561863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12164 22:54:20.562184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12166 22:54:20.600724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12167 22:54:20.601038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12169 22:54:20.638015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12170 22:54:20.638352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12172 22:54:20.673335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12173 22:54:20.673656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12175 22:54:20.715157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12176 22:54:20.715472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12178 22:54:20.757445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12179 22:54:20.757760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12181 22:54:20.803861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12182 22:54:20.804171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12184 22:54:20.847392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12185 22:54:20.847709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12187 22:54:20.889832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12188 22:54:20.890258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12190 22:54:20.931687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12191 22:54:20.931988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12193 22:54:20.970280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12194 22:54:20.970540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12196 22:54:21.008163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12197 22:54:21.008415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12199 22:54:21.048149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12200 22:54:21.048410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12202 22:54:21.087247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12203 22:54:21.087506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12205 22:54:21.126921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12206 22:54:21.127183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12208 22:54:21.160697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12209 22:54:21.160956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12211 22:54:21.205172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12212 22:54:21.205428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12214 22:54:21.241700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12215 22:54:21.241960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12217 22:54:21.277823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12218 22:54:21.278045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12220 22:54:21.317387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12221 22:54:21.317643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12223 22:54:21.363733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12224 22:54:21.363997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12226 22:54:21.404561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12227 22:54:21.404816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12229 22:54:21.446710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12230 22:54:21.446972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12232 22:54:21.492269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12233 22:54:21.492525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12235 22:54:21.531980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12236 22:54:21.532241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12238 22:54:21.573661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12239 22:54:21.573945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12241 22:54:21.617321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12242 22:54:21.617581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12244 22:54:21.656043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12245 22:54:21.656303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12247 22:54:21.697645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12248 22:54:21.697906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12250 22:54:21.735095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12251 22:54:21.735393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12253 22:54:21.770495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12254 22:54:21.770768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12256 22:54:21.807780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12257 22:54:21.808063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12259 22:54:21.841309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12260 22:54:21.841581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12262 22:54:21.880646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12263 22:54:21.880903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12265 22:54:21.915430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12266 22:54:21.915682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12268 22:54:21.955569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12269 22:54:21.955831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12271 22:54:21.986228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12272 22:54:21.986483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12274 22:54:22.031210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12275 22:54:22.031467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12277 22:54:22.069420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12278 22:54:22.069680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12280 22:54:22.108989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12281 22:54:22.109246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12283 22:54:22.142822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12284 22:54:22.143081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12286 22:54:22.180282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12287 22:54:22.180536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12289 22:54:22.215461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12290 22:54:22.215763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12292 22:54:22.252500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12293 22:54:22.252758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12295 22:54:22.291519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12296 22:54:22.291772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12298 22:54:22.338728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12299 22:54:22.338992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12301 22:54:22.379851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12302 22:54:22.380108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12304 22:54:22.422139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12305 22:54:22.422394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12307 22:54:22.464383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12308 22:54:22.464648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12310 22:54:22.505980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12311 22:54:22.506255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12313 22:54:22.543937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12315 22:54:22.547332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12316 22:54:22.583900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12317 22:54:22.584157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12319 22:54:22.616797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12321 22:54:22.619659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12322 22:54:22.654216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12323 22:54:22.654477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12325 22:54:22.686855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12327 22:54:22.689843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12328 22:54:22.724365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12329 22:54:22.724619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12331 22:54:22.765377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12332 22:54:22.765676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12334 22:54:22.800102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12335 22:54:22.800358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12337 22:54:22.837305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12338 22:54:22.837594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12340 22:54:22.869543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12341 22:54:22.869802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12343 22:54:22.901633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12345 22:54:22.904578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12346 22:54:22.939914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12347 22:54:22.940205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12349 22:54:22.978135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12350 22:54:22.978454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12352 22:54:23.010089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12353 22:54:23.010406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12355 22:54:23.052411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12357 22:54:23.055339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12358 22:54:23.090171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12360 22:54:23.093477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12361 22:54:23.132515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12363 22:54:23.135458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12364 22:54:23.175895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12365 22:54:23.176210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12367 22:54:23.217571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12368 22:54:23.217896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12370 22:54:23.258284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12371 22:54:23.258612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12373 22:54:23.295961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12374 22:54:23.296283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12376 22:54:23.325612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12377 22:54:23.325935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12379 22:54:23.363945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12380 22:54:23.364271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12382 22:54:23.402557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12383 22:54:23.402881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12385 22:54:23.438834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12386 22:54:23.439159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12388 22:54:23.479390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12389 22:54:23.479715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12391 22:54:23.521378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12392 22:54:23.521728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12394 22:54:23.556408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12395 22:54:23.556739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12397 22:54:23.595747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12398 22:54:23.596075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12400 22:54:23.636656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12401 22:54:23.636985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12403 22:54:23.675249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12404 22:54:23.675400 + set +x
12405 22:54:23.675648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12407 22:54:23.681937 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 13683711_1.6.2.3.5>
12408 22:54:23.682219 Received signal: <ENDRUN> 1_kselftest-arm64 13683711_1.6.2.3.5
12409 22:54:23.682294 Ending use of test pattern.
12410 22:54:23.682355 Ending test lava.1_kselftest-arm64 (13683711_1.6.2.3.5), duration 28.16
12412 22:54:23.685281 <LAVA_TEST_RUNNER EXIT>
12413 22:54:23.685535 ok: lava_test_shell seems to have completed
12414 22:54:23.686660 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12415 22:54:23.686817 end: 3.1 lava-test-shell (duration 00:00:29) [common]
12416 22:54:23.686904 end: 3 lava-test-retry (duration 00:00:29) [common]
12417 22:54:23.686992 start: 4 finalize (timeout 00:07:35) [common]
12418 22:54:23.687080 start: 4.1 power-off (timeout 00:00:30) [common]
12419 22:54:23.687236 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
12420 22:54:23.762422 >> Command sent successfully.
12421 22:54:23.764834 Returned 0 in 0 seconds
12422 22:54:23.865234 end: 4.1 power-off (duration 00:00:00) [common]
12424 22:54:23.865584 start: 4.2 read-feedback (timeout 00:07:35) [common]
12425 22:54:23.865850 Listened to connection for namespace 'common' for up to 1s
12426 22:54:24.866151 Finalising connection for namespace 'common'
12427 22:54:24.866341 Disconnecting from shell: Finalise
12428 22:54:24.866428 / #
12429 22:54:24.966809 end: 4.2 read-feedback (duration 00:00:01) [common]
12430 22:54:24.966996 end: 4 finalize (duration 00:00:01) [common]
12431 22:54:24.967118 Cleaning after the job
12432 22:54:24.967220 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/ramdisk
12433 22:54:24.969449 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/kernel
12434 22:54:24.980201 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/dtb
12435 22:54:24.980431 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/nfsrootfs
12436 22:54:25.044701 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683711/tftp-deploy-rojg5qzj/modules
12437 22:54:25.050371 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683711
12438 22:54:25.610704 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683711
12439 22:54:25.610893 Job finished correctly