Boot log: mt8192-asurada-spherion-r0
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Kernel Errors: 0
- Boot result: UNKNOWN
1 22:52:43.084451 lava-dispatcher, installed at version: 2024.01
2 22:52:43.084657 start: 0 validate
3 22:52:43.084782 Start time: 2024-05-07 22:52:43.084775+00:00 (UTC)
4 22:52:43.084900 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:52:43.085023 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:52:43.347409 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:52:43.348057 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:52:43.602860 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:52:43.603503 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:52:43.867124 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:52:43.868182 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:52:44.130533 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:52:44.131217 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:52:44.397859 validate duration: 1.31
16 22:52:44.398106 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:52:44.398198 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:52:44.398280 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:52:44.398397 Not decompressing ramdisk as can be used compressed.
20 22:52:44.398480 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:52:44.398541 saving as /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/ramdisk/initrd.cpio.gz
22 22:52:44.398604 total size: 5628169 (5 MB)
23 22:52:44.399695 progress 0 % (0 MB)
24 22:52:44.401399 progress 5 % (0 MB)
25 22:52:44.403017 progress 10 % (0 MB)
26 22:52:44.404527 progress 15 % (0 MB)
27 22:52:44.406288 progress 20 % (1 MB)
28 22:52:44.407858 progress 25 % (1 MB)
29 22:52:44.409630 progress 30 % (1 MB)
30 22:52:44.411332 progress 35 % (1 MB)
31 22:52:44.412844 progress 40 % (2 MB)
32 22:52:44.414577 progress 45 % (2 MB)
33 22:52:44.416148 progress 50 % (2 MB)
34 22:52:44.417851 progress 55 % (2 MB)
35 22:52:44.419541 progress 60 % (3 MB)
36 22:52:44.421057 progress 65 % (3 MB)
37 22:52:44.422765 progress 70 % (3 MB)
38 22:52:44.424273 progress 75 % (4 MB)
39 22:52:44.425967 progress 80 % (4 MB)
40 22:52:44.427481 progress 85 % (4 MB)
41 22:52:44.429159 progress 90 % (4 MB)
42 22:52:44.430710 progress 95 % (5 MB)
43 22:52:44.432105 progress 100 % (5 MB)
44 22:52:44.432312 5 MB downloaded in 0.03 s (159.25 MB/s)
45 22:52:44.432467 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:52:44.432714 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:52:44.432802 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:52:44.432888 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:52:44.433017 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:52:44.433087 saving as /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/kernel/Image
52 22:52:44.433151 total size: 54682112 (52 MB)
53 22:52:44.433221 No compression specified
54 22:52:44.434373 progress 0 % (0 MB)
55 22:52:44.448138 progress 5 % (2 MB)
56 22:52:44.461604 progress 10 % (5 MB)
57 22:52:44.475158 progress 15 % (7 MB)
58 22:52:44.488687 progress 20 % (10 MB)
59 22:52:44.502376 progress 25 % (13 MB)
60 22:52:44.515982 progress 30 % (15 MB)
61 22:52:44.530006 progress 35 % (18 MB)
62 22:52:44.543670 progress 40 % (20 MB)
63 22:52:44.557432 progress 45 % (23 MB)
64 22:52:44.571247 progress 50 % (26 MB)
65 22:52:44.584853 progress 55 % (28 MB)
66 22:52:44.598549 progress 60 % (31 MB)
67 22:52:44.612034 progress 65 % (33 MB)
68 22:52:44.625898 progress 70 % (36 MB)
69 22:52:44.639631 progress 75 % (39 MB)
70 22:52:44.653407 progress 80 % (41 MB)
71 22:52:44.667089 progress 85 % (44 MB)
72 22:52:44.680563 progress 90 % (46 MB)
73 22:52:44.693957 progress 95 % (49 MB)
74 22:52:44.707165 progress 100 % (52 MB)
75 22:52:44.707381 52 MB downloaded in 0.27 s (190.17 MB/s)
76 22:52:44.707529 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:52:44.707761 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:52:44.707846 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:52:44.707933 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:52:44.708067 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:52:44.708134 saving as /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/dtb/mt8192-asurada-spherion-r0.dtb
83 22:52:44.708194 total size: 47258 (0 MB)
84 22:52:44.708254 No compression specified
85 22:52:44.709375 progress 69 % (0 MB)
86 22:52:44.709656 progress 100 % (0 MB)
87 22:52:44.709807 0 MB downloaded in 0.00 s (27.98 MB/s)
88 22:52:44.709925 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:52:44.710140 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:52:44.710222 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:52:44.710302 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:52:44.710411 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:52:44.710477 saving as /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/nfsrootfs/full.rootfs.tar
95 22:52:44.710536 total size: 120894716 (115 MB)
96 22:52:44.710600 Using unxz to decompress xz
97 22:52:44.714522 progress 0 % (0 MB)
98 22:52:45.055943 progress 5 % (5 MB)
99 22:52:45.404402 progress 10 % (11 MB)
100 22:52:45.748713 progress 15 % (17 MB)
101 22:52:46.070098 progress 20 % (23 MB)
102 22:52:46.359143 progress 25 % (28 MB)
103 22:52:46.709289 progress 30 % (34 MB)
104 22:52:47.038377 progress 35 % (40 MB)
105 22:52:47.200573 progress 40 % (46 MB)
106 22:52:47.377881 progress 45 % (51 MB)
107 22:52:47.681410 progress 50 % (57 MB)
108 22:52:48.058317 progress 55 % (63 MB)
109 22:52:48.394397 progress 60 % (69 MB)
110 22:52:48.730754 progress 65 % (74 MB)
111 22:52:49.066323 progress 70 % (80 MB)
112 22:52:49.413489 progress 75 % (86 MB)
113 22:52:49.747176 progress 80 % (92 MB)
114 22:52:50.077986 progress 85 % (98 MB)
115 22:52:50.424664 progress 90 % (103 MB)
116 22:52:50.743971 progress 95 % (109 MB)
117 22:52:51.095070 progress 100 % (115 MB)
118 22:52:51.100281 115 MB downloaded in 6.39 s (18.04 MB/s)
119 22:52:51.100558 end: 1.4.1 http-download (duration 00:00:06) [common]
121 22:52:51.100858 end: 1.4 download-retry (duration 00:00:06) [common]
122 22:52:51.100965 start: 1.5 download-retry (timeout 00:09:53) [common]
123 22:52:51.101072 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 22:52:51.101268 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:52:51.101344 saving as /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/modules/modules.tar
126 22:52:51.101427 total size: 8594396 (8 MB)
127 22:52:51.101531 Using unxz to decompress xz
128 22:52:51.106069 progress 0 % (0 MB)
129 22:52:51.124771 progress 5 % (0 MB)
130 22:52:51.148883 progress 10 % (0 MB)
131 22:52:51.172495 progress 15 % (1 MB)
132 22:52:51.195117 progress 20 % (1 MB)
133 22:52:51.219139 progress 25 % (2 MB)
134 22:52:51.242419 progress 30 % (2 MB)
135 22:52:51.265793 progress 35 % (2 MB)
136 22:52:51.290322 progress 40 % (3 MB)
137 22:52:51.314842 progress 45 % (3 MB)
138 22:52:51.339073 progress 50 % (4 MB)
139 22:52:51.363065 progress 55 % (4 MB)
140 22:52:51.388141 progress 60 % (4 MB)
141 22:52:51.412627 progress 65 % (5 MB)
142 22:52:51.436765 progress 70 % (5 MB)
143 22:52:51.460411 progress 75 % (6 MB)
144 22:52:51.485205 progress 80 % (6 MB)
145 22:52:51.510499 progress 85 % (6 MB)
146 22:52:51.538742 progress 90 % (7 MB)
147 22:52:51.567261 progress 95 % (7 MB)
148 22:52:51.592956 progress 100 % (8 MB)
149 22:52:51.598062 8 MB downloaded in 0.50 s (16.50 MB/s)
150 22:52:51.598317 end: 1.5.1 http-download (duration 00:00:00) [common]
152 22:52:51.598587 end: 1.5 download-retry (duration 00:00:00) [common]
153 22:52:51.598681 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 22:52:51.598774 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 22:52:54.952950 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13683717/extract-nfsrootfs-rw2fg62o
156 22:52:54.953173 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:52:54.953434 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 22:52:54.953599 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs
159 22:52:54.953726 makedir: /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin
160 22:52:54.953824 makedir: /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/tests
161 22:52:54.953919 makedir: /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/results
162 22:52:54.954018 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-add-keys
163 22:52:54.954156 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-add-sources
164 22:52:54.954281 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-background-process-start
165 22:52:54.954403 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-background-process-stop
166 22:52:54.954524 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-common-functions
167 22:52:54.954644 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-echo-ipv4
168 22:52:54.954766 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-install-packages
169 22:52:54.954885 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-installed-packages
170 22:52:54.955003 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-os-build
171 22:52:54.955120 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-probe-channel
172 22:52:54.955237 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-probe-ip
173 22:52:54.955354 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-target-ip
174 22:52:54.955472 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-target-mac
175 22:52:54.955589 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-target-storage
176 22:52:54.955710 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-test-case
177 22:52:54.955830 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-test-event
178 22:52:54.955948 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-test-feedback
179 22:52:54.956065 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-test-raise
180 22:52:54.956183 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-test-reference
181 22:52:54.956301 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-test-runner
182 22:52:54.956420 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-test-set
183 22:52:54.956538 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-test-shell
184 22:52:54.956658 Updating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-add-keys (debian)
185 22:52:54.956801 Updating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-add-sources (debian)
186 22:52:54.956935 Updating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-install-packages (debian)
187 22:52:54.957066 Updating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-installed-packages (debian)
188 22:52:54.957196 Updating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/bin/lava-os-build (debian)
189 22:52:54.957373 Creating /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/environment
190 22:52:54.957464 LAVA metadata
191 22:52:54.957531 - LAVA_JOB_ID=13683717
192 22:52:54.957592 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:52:54.957690 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 22:52:54.957754 skipped lava-vland-overlay
195 22:52:54.957825 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:52:54.957901 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 22:52:54.957959 skipped lava-multinode-overlay
198 22:52:54.958040 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:52:54.958116 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 22:52:54.958197 Loading test definitions
201 22:52:54.958286 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 22:52:54.958354 Using /lava-13683717 at stage 0
203 22:52:54.958621 uuid=13683717_1.6.2.3.1 testdef=None
204 22:52:54.958705 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:52:54.958786 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 22:52:54.959221 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:52:54.959438 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 22:52:54.959977 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:52:54.960221 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 22:52:54.960746 runner path: /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/0/tests/0_timesync-off test_uuid 13683717_1.6.2.3.1
213 22:52:54.960899 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:52:54.961119 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 22:52:54.961189 Using /lava-13683717 at stage 0
217 22:52:54.961343 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:52:54.961428 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/0/tests/1_kselftest-rtc'
219 22:52:56.756639 Running '/usr/bin/git checkout kernelci.org
220 22:52:56.903582 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 22:52:56.904329 uuid=13683717_1.6.2.3.5 testdef=None
222 22:52:56.904491 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 22:52:56.904737 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 22:52:56.905486 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:52:56.905716 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 22:52:56.906679 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:52:56.906914 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 22:52:56.907833 runner path: /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/0/tests/1_kselftest-rtc test_uuid 13683717_1.6.2.3.5
232 22:52:56.907921 BOARD='mt8192-asurada-spherion-r0'
233 22:52:56.907984 BRANCH='cip'
234 22:52:56.908042 SKIPFILE='/dev/null'
235 22:52:56.908099 SKIP_INSTALL='True'
236 22:52:56.908154 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:52:56.908212 TST_CASENAME=''
238 22:52:56.908266 TST_CMDFILES='rtc'
239 22:52:56.908402 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:52:56.908606 Creating lava-test-runner.conf files
242 22:52:56.908669 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683717/lava-overlay-2eddc2vs/lava-13683717/0 for stage 0
243 22:52:56.908761 - 0_timesync-off
244 22:52:56.908827 - 1_kselftest-rtc
245 22:52:56.908919 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 22:52:56.909006 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 22:53:04.345676 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 22:53:04.345823 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 22:53:04.345915 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:53:04.346013 end: 1.6.2 lava-overlay (duration 00:00:09) [common]
251 22:53:04.346103 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 22:53:04.510777 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:53:04.511171 start: 1.6.4 extract-modules (timeout 00:09:40) [common]
254 22:53:04.511297 extracting modules file /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683717/extract-nfsrootfs-rw2fg62o
255 22:53:04.725443 extracting modules file /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683717/extract-overlay-ramdisk-xayxtq6p/ramdisk
256 22:53:04.944211 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:53:04.944385 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 22:53:04.944476 [common] Applying overlay to NFS
259 22:53:04.944550 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683717/compress-overlay-645pqt1k/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683717/extract-nfsrootfs-rw2fg62o
260 22:53:05.864393 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:53:05.864564 start: 1.6.6 configure-preseed-file (timeout 00:09:39) [common]
262 22:53:05.864659 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:53:05.864749 start: 1.6.7 compress-ramdisk (timeout 00:09:39) [common]
264 22:53:05.864830 Building ramdisk /var/lib/lava/dispatcher/tmp/13683717/extract-overlay-ramdisk-xayxtq6p/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683717/extract-overlay-ramdisk-xayxtq6p/ramdisk
265 22:53:06.213286 >> 130327 blocks
266 22:53:08.207273 rename /var/lib/lava/dispatcher/tmp/13683717/extract-overlay-ramdisk-xayxtq6p/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/ramdisk/ramdisk.cpio.gz
267 22:53:08.207730 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:53:08.207862 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 22:53:08.207967 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 22:53:08.208077 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/kernel/Image'
271 22:53:21.638191 Returned 0 in 13 seconds
272 22:53:21.738847 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/kernel/image.itb
273 22:53:22.107753 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:53:22.108129 output: Created: Tue May 7 23:53:22 2024
275 22:53:22.108208 output: Image 0 (kernel-1)
276 22:53:22.108271 output: Description:
277 22:53:22.108333 output: Created: Tue May 7 23:53:22 2024
278 22:53:22.108393 output: Type: Kernel Image
279 22:53:22.108455 output: Compression: lzma compressed
280 22:53:22.108511 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
281 22:53:22.108568 output: Architecture: AArch64
282 22:53:22.108627 output: OS: Linux
283 22:53:22.108684 output: Load Address: 0x00000000
284 22:53:22.108741 output: Entry Point: 0x00000000
285 22:53:22.108798 output: Hash algo: crc32
286 22:53:22.108854 output: Hash value: 727ee7c6
287 22:53:22.108910 output: Image 1 (fdt-1)
288 22:53:22.108966 output: Description: mt8192-asurada-spherion-r0
289 22:53:22.109020 output: Created: Tue May 7 23:53:22 2024
290 22:53:22.109074 output: Type: Flat Device Tree
291 22:53:22.109127 output: Compression: uncompressed
292 22:53:22.109181 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 22:53:22.109291 output: Architecture: AArch64
294 22:53:22.109347 output: Hash algo: crc32
295 22:53:22.109401 output: Hash value: 0f8e4d2e
296 22:53:22.109455 output: Image 2 (ramdisk-1)
297 22:53:22.109508 output: Description: unavailable
298 22:53:22.109561 output: Created: Tue May 7 23:53:22 2024
299 22:53:22.109615 output: Type: RAMDisk Image
300 22:53:22.109668 output: Compression: Unknown Compression
301 22:53:22.109721 output: Data Size: 18725805 Bytes = 18286.92 KiB = 17.86 MiB
302 22:53:22.109775 output: Architecture: AArch64
303 22:53:22.109828 output: OS: Linux
304 22:53:22.109881 output: Load Address: unavailable
305 22:53:22.109933 output: Entry Point: unavailable
306 22:53:22.109986 output: Hash algo: crc32
307 22:53:22.110039 output: Hash value: af7644b7
308 22:53:22.110092 output: Default Configuration: 'conf-1'
309 22:53:22.110144 output: Configuration 0 (conf-1)
310 22:53:22.110197 output: Description: mt8192-asurada-spherion-r0
311 22:53:22.110250 output: Kernel: kernel-1
312 22:53:22.110314 output: Init Ramdisk: ramdisk-1
313 22:53:22.110377 output: FDT: fdt-1
314 22:53:22.110431 output: Loadables: kernel-1
315 22:53:22.110484 output:
316 22:53:22.110691 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 22:53:22.110795 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 22:53:22.110902 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 22:53:22.110997 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 22:53:22.111078 No LXC device requested
321 22:53:22.111154 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:53:22.111242 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 22:53:22.111324 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:53:22.111395 Checking files for TFTP limit of 4294967296 bytes.
325 22:53:22.111897 end: 1 tftp-deploy (duration 00:00:38) [common]
326 22:53:22.112007 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:53:22.112098 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:53:22.112227 substitutions:
329 22:53:22.112300 - {DTB}: 13683717/tftp-deploy-2iu6kz9l/dtb/mt8192-asurada-spherion-r0.dtb
330 22:53:22.112365 - {INITRD}: 13683717/tftp-deploy-2iu6kz9l/ramdisk/ramdisk.cpio.gz
331 22:53:22.112425 - {KERNEL}: 13683717/tftp-deploy-2iu6kz9l/kernel/Image
332 22:53:22.112483 - {LAVA_MAC}: None
333 22:53:22.112540 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13683717/extract-nfsrootfs-rw2fg62o
334 22:53:22.112597 - {NFS_SERVER_IP}: 192.168.201.1
335 22:53:22.112652 - {PRESEED_CONFIG}: None
336 22:53:22.112707 - {PRESEED_LOCAL}: None
337 22:53:22.112761 - {RAMDISK}: 13683717/tftp-deploy-2iu6kz9l/ramdisk/ramdisk.cpio.gz
338 22:53:22.112816 - {ROOT_PART}: None
339 22:53:22.112870 - {ROOT}: None
340 22:53:22.112925 - {SERVER_IP}: 192.168.201.1
341 22:53:22.112978 - {TEE}: None
342 22:53:22.113033 Parsed boot commands:
343 22:53:22.113087 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:53:22.113306 Parsed boot commands: tftpboot 192.168.201.1 13683717/tftp-deploy-2iu6kz9l/kernel/image.itb 13683717/tftp-deploy-2iu6kz9l/kernel/cmdline
345 22:53:22.113394 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:53:22.113481 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:53:22.113575 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:53:22.113659 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:53:22.113734 Not connected, no need to disconnect.
350 22:53:22.113808 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:53:22.113889 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:53:22.113960 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 22:53:22.117951 Setting prompt string to ['lava-test: # ']
354 22:53:22.118318 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:53:22.118436 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:53:22.118535 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:53:22.118657 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:53:22.118924 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 22:53:27.265993 >> Command sent successfully.
360 22:53:27.276378 Returned 0 in 5 seconds
361 22:53:27.377627 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:53:27.379052 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:53:27.379540 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:53:27.379980 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:53:27.380324 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:53:27.380670 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:53:27.381907 [Enter `^Ec?' for help]
369 22:53:27.543487
370 22:53:27.544051
371 22:53:27.544529 F0: 102B 0000
372 22:53:27.544885
373 22:53:27.545246 F3: 1001 0000 [0200]
374 22:53:27.545565
375 22:53:27.546643 F3: 1001 0000
376 22:53:27.547070
377 22:53:27.547409 F7: 102D 0000
378 22:53:27.547725
379 22:53:27.549878 F1: 0000 0000
380 22:53:27.550320
381 22:53:27.550667 V0: 0000 0000 [0001]
382 22:53:27.550996
383 22:53:27.553601 00: 0007 8000
384 22:53:27.554047
385 22:53:27.554385 01: 0000 0000
386 22:53:27.554711
387 22:53:27.555017 BP: 0C00 0209 [0000]
388 22:53:27.556571
389 22:53:27.556995 G0: 1182 0000
390 22:53:27.557365
391 22:53:27.557685 EC: 0000 0021 [4000]
392 22:53:27.560214
393 22:53:27.560655 S7: 0000 0000 [0000]
394 22:53:27.560966
395 22:53:27.561285 CC: 0000 0000 [0001]
396 22:53:27.563374
397 22:53:27.563762 T0: 0000 0040 [010F]
398 22:53:27.564076
399 22:53:27.564366 Jump to BL
400 22:53:27.564645
401 22:53:27.589996
402 22:53:27.590486
403 22:53:27.590803
404 22:53:27.597585 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:53:27.601272 ARM64: Exception handlers installed.
406 22:53:27.605820 ARM64: Testing exception
407 22:53:27.608351 ARM64: Done test exception
408 22:53:27.615740 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:53:27.625638 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:53:27.632309 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:53:27.642171 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:53:27.648674 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:53:27.655758 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:53:27.666831 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:53:27.673849 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:53:27.692729 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:53:27.696011 WDT: Last reset was cold boot
418 22:53:27.699465 SPI1(PAD0) initialized at 2873684 Hz
419 22:53:27.703230 SPI5(PAD0) initialized at 992727 Hz
420 22:53:27.706286 VBOOT: Loading verstage.
421 22:53:27.712846 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:53:27.716107 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:53:27.719443 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:53:27.723625 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:53:27.730536 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:53:27.736980 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:53:27.747948 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 22:53:27.748469
429 22:53:27.748813
430 22:53:27.758343 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:53:27.761161 ARM64: Exception handlers installed.
432 22:53:27.764890 ARM64: Testing exception
433 22:53:27.765477 ARM64: Done test exception
434 22:53:27.771135 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:53:27.774760 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:53:27.789766 Probing TPM: . done!
437 22:53:27.790303 TPM ready after 0 ms
438 22:53:27.796216 Connected to device vid:did:rid of 1ae0:0028:00
439 22:53:27.802735 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 22:53:27.861590 Initialized TPM device CR50 revision 0
441 22:53:27.873611 tlcl_send_startup: Startup return code is 0
442 22:53:27.874151 TPM: setup succeeded
443 22:53:27.884982 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:53:27.893890 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:53:27.906096 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:53:27.915888 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:53:27.919182 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:53:27.924288 in-header: 03 07 00 00 08 00 00 00
449 22:53:27.928211 in-data: aa e4 47 04 13 02 00 00
450 22:53:27.932013 Chrome EC: UHEPI supported
451 22:53:27.940092 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:53:27.942162 in-header: 03 ad 00 00 08 00 00 00
453 22:53:27.945953 in-data: 00 20 20 08 00 00 00 00
454 22:53:27.946043 Phase 1
455 22:53:27.949725 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:53:27.957446 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:53:27.960997 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:53:27.964328 Recovery requested (1009000e)
459 22:53:27.972952 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:53:27.978677 tlcl_extend: response is 0
461 22:53:27.988047 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:53:27.993751 tlcl_extend: response is 0
463 22:53:28.000410 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:53:28.020381 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 22:53:28.027111 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:53:28.027648
467 22:53:28.027993
468 22:53:28.037998 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:53:28.041752 ARM64: Exception handlers installed.
470 22:53:28.042215 ARM64: Testing exception
471 22:53:28.044730 ARM64: Done test exception
472 22:53:28.065905 pmic_efuse_setting: Set efuses in 11 msecs
473 22:53:28.070461 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:53:28.076931 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:53:28.079911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:53:28.083418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:53:28.090406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:53:28.094209 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:53:28.097950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:53:28.104826 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:53:28.108567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:53:28.113184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:53:28.120089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:53:28.123385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:53:28.127364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:53:28.130619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:53:28.138251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:53:28.145736 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:53:28.149378 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:53:28.157036 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:53:28.161818 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:53:28.168484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:53:28.172634 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:53:28.179392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:53:28.183165 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:53:28.190747 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:53:28.194617 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:53:28.198569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:53:28.205427 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:53:28.209018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:53:28.216304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:53:28.219663 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:53:28.223507 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:53:28.231082 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:53:28.234652 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:53:28.238266 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:53:28.245995 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:53:28.249579 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:53:28.253037 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:53:28.261016 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:53:28.264629 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:53:28.268708 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:53:28.271920 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:53:28.279199 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:53:28.282684 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:53:28.287297 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:53:28.290532 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:53:28.294741 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:53:28.302434 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:53:28.305616 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:53:28.309141 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:53:28.312963 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:53:28.316617 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:53:28.320332 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:53:28.328045 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:53:28.339498 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:53:28.343175 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:53:28.350671 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:53:28.357476 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:53:28.361395 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:53:28.368904 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:53:28.372854 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:53:28.379201 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 22:53:28.382515 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:53:28.391078 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 22:53:28.394218 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:53:28.403883 [RTC]rtc_get_frequency_meter,154: input=15, output=790
538 22:53:28.413291 [RTC]rtc_get_frequency_meter,154: input=23, output=980
539 22:53:28.422748 [RTC]rtc_get_frequency_meter,154: input=19, output=884
540 22:53:28.431985 [RTC]rtc_get_frequency_meter,154: input=17, output=838
541 22:53:28.441726 [RTC]rtc_get_frequency_meter,154: input=16, output=813
542 22:53:28.451086 [RTC]rtc_get_frequency_meter,154: input=15, output=791
543 22:53:28.461025 [RTC]rtc_get_frequency_meter,154: input=16, output=813
544 22:53:28.465090 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 22:53:28.469071 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 22:53:28.472750 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:53:28.479857 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 22:53:28.484103 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:53:28.487253 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 22:53:28.487695 ADC[4]: Raw value=901697 ID=7
551 22:53:28.490805 ADC[3]: Raw value=213336 ID=1
552 22:53:28.494682 RAM Code: 0x71
553 22:53:28.498048 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:53:28.501816 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:53:28.509667 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 22:53:28.517352 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 22:53:28.520211 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:53:28.524744 in-header: 03 07 00 00 08 00 00 00
559 22:53:28.528396 in-data: aa e4 47 04 13 02 00 00
560 22:53:28.532115 Chrome EC: UHEPI supported
561 22:53:28.539949 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:53:28.540499 in-header: 03 ed 00 00 08 00 00 00
563 22:53:28.543064 in-data: 80 20 60 08 00 00 00 00
564 22:53:28.546872 MRC: failed to locate region type 0.
565 22:53:28.554644 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:53:28.558093 DRAM-K: Running full calibration
567 22:53:28.562144 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 22:53:28.565660 header.status = 0x0
569 22:53:28.569261 header.version = 0x6 (expected: 0x6)
570 22:53:28.573317 header.size = 0xd00 (expected: 0xd00)
571 22:53:28.573859 header.flags = 0x0
572 22:53:28.580774 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:53:28.598279 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 22:53:28.605648 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:53:28.606193 dram_init: ddr_geometry: 2
576 22:53:28.609234 [EMI] MDL number = 2
577 22:53:28.612638 [EMI] Get MDL freq = 0
578 22:53:28.613072 dram_init: ddr_type: 0
579 22:53:28.616110 is_discrete_lpddr4: 1
580 22:53:28.619564 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:53:28.620005
582 22:53:28.620364
583 22:53:28.620688 [Bian_co] ETT version 0.0.0.1
584 22:53:28.627564 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 22:53:28.628108
586 22:53:28.630807 dramc_set_vcore_voltage set vcore to 650000
587 22:53:28.631359 Read voltage for 800, 4
588 22:53:28.634201 Vio18 = 0
589 22:53:28.634635 Vcore = 650000
590 22:53:28.634979 Vdram = 0
591 22:53:28.638383 Vddq = 0
592 22:53:28.638907 Vmddr = 0
593 22:53:28.639259 dram_init: config_dvfs: 1
594 22:53:28.645087 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:53:28.651961 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:53:28.654683 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 22:53:28.658124 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 22:53:28.661875 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 22:53:28.664501 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 22:53:28.667886 MEM_TYPE=3, freq_sel=18
601 22:53:28.671369 sv_algorithm_assistance_LP4_1600
602 22:53:28.674914 ============ PULL DRAM RESETB DOWN ============
603 22:53:28.678157 ========== PULL DRAM RESETB DOWN end =========
604 22:53:28.685101 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:53:28.687964 ===================================
606 22:53:28.688406 LPDDR4 DRAM CONFIGURATION
607 22:53:28.692378 ===================================
608 22:53:28.695151 EX_ROW_EN[0] = 0x0
609 22:53:28.695588 EX_ROW_EN[1] = 0x0
610 22:53:28.698642 LP4Y_EN = 0x0
611 22:53:28.699177 WORK_FSP = 0x0
612 22:53:28.701741 WL = 0x2
613 22:53:28.702176 RL = 0x2
614 22:53:28.705476 BL = 0x2
615 22:53:28.706055 RPST = 0x0
616 22:53:28.708359 RD_PRE = 0x0
617 22:53:28.708796 WR_PRE = 0x1
618 22:53:28.712457 WR_PST = 0x0
619 22:53:28.713007 DBI_WR = 0x0
620 22:53:28.715239 DBI_RD = 0x0
621 22:53:28.715672 OTF = 0x1
622 22:53:28.718473 ===================================
623 22:53:28.727151 ===================================
624 22:53:28.727918 ANA top config
625 22:53:28.728943 ===================================
626 22:53:28.732049 DLL_ASYNC_EN = 0
627 22:53:28.732483 ALL_SLAVE_EN = 1
628 22:53:28.735324 NEW_RANK_MODE = 1
629 22:53:28.738700 DLL_IDLE_MODE = 1
630 22:53:28.742143 LP45_APHY_COMB_EN = 1
631 22:53:28.742596 TX_ODT_DIS = 1
632 22:53:28.745348 NEW_8X_MODE = 1
633 22:53:28.748521 ===================================
634 22:53:28.752865 ===================================
635 22:53:28.755326 data_rate = 1600
636 22:53:28.758945 CKR = 1
637 22:53:28.762048 DQ_P2S_RATIO = 8
638 22:53:28.765161 ===================================
639 22:53:28.769250 CA_P2S_RATIO = 8
640 22:53:28.769691 DQ_CA_OPEN = 0
641 22:53:28.772247 DQ_SEMI_OPEN = 0
642 22:53:28.776110 CA_SEMI_OPEN = 0
643 22:53:28.779073 CA_FULL_RATE = 0
644 22:53:28.782515 DQ_CKDIV4_EN = 1
645 22:53:28.783159 CA_CKDIV4_EN = 1
646 22:53:28.786067 CA_PREDIV_EN = 0
647 22:53:28.788759 PH8_DLY = 0
648 22:53:28.792061 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:53:28.796023 DQ_AAMCK_DIV = 4
650 22:53:28.799675 CA_AAMCK_DIV = 4
651 22:53:28.800204 CA_ADMCK_DIV = 4
652 22:53:28.802466 DQ_TRACK_CA_EN = 0
653 22:53:28.805858 CA_PICK = 800
654 22:53:28.809540 CA_MCKIO = 800
655 22:53:28.812337 MCKIO_SEMI = 0
656 22:53:28.816769 PLL_FREQ = 3068
657 22:53:28.817498 DQ_UI_PI_RATIO = 32
658 22:53:28.819812 CA_UI_PI_RATIO = 0
659 22:53:28.823998 ===================================
660 22:53:28.827059 ===================================
661 22:53:28.831013 memory_type:LPDDR4
662 22:53:28.831540 GP_NUM : 10
663 22:53:28.835741 SRAM_EN : 1
664 22:53:28.836325 MD32_EN : 0
665 22:53:28.839294 ===================================
666 22:53:28.842722 [ANA_INIT] >>>>>>>>>>>>>>
667 22:53:28.843206 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:53:28.846599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:53:28.850387 ===================================
670 22:53:28.853898 data_rate = 1600,PCW = 0X7600
671 22:53:28.857201 ===================================
672 22:53:28.860381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:53:28.867523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:53:28.870405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:53:28.876835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:53:28.880567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:53:28.884054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:53:28.884486 [ANA_INIT] flow start
679 22:53:28.887273 [ANA_INIT] PLL >>>>>>>>
680 22:53:28.890699 [ANA_INIT] PLL <<<<<<<<
681 22:53:28.891139 [ANA_INIT] MIDPI >>>>>>>>
682 22:53:28.893897 [ANA_INIT] MIDPI <<<<<<<<
683 22:53:28.897262 [ANA_INIT] DLL >>>>>>>>
684 22:53:28.897877 [ANA_INIT] flow end
685 22:53:28.900813 ============ LP4 DIFF to SE enter ============
686 22:53:28.907184 ============ LP4 DIFF to SE exit ============
687 22:53:28.907702 [ANA_INIT] <<<<<<<<<<<<<
688 22:53:28.910793 [Flow] Enable top DCM control >>>>>
689 22:53:28.914378 [Flow] Enable top DCM control <<<<<
690 22:53:28.917811 Enable DLL master slave shuffle
691 22:53:28.924029 ==============================================================
692 22:53:28.924571 Gating Mode config
693 22:53:28.931406 ==============================================================
694 22:53:28.934310 Config description:
695 22:53:28.941149 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:53:28.947738 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:53:28.954508 SELPH_MODE 0: By rank 1: By Phase
698 22:53:28.961675 ==============================================================
699 22:53:28.962212 GAT_TRACK_EN = 1
700 22:53:28.964773 RX_GATING_MODE = 2
701 22:53:28.968022 RX_GATING_TRACK_MODE = 2
702 22:53:28.971128 SELPH_MODE = 1
703 22:53:28.974630 PICG_EARLY_EN = 1
704 22:53:28.978539 VALID_LAT_VALUE = 1
705 22:53:28.984794 ==============================================================
706 22:53:28.987649 Enter into Gating configuration >>>>
707 22:53:28.991272 Exit from Gating configuration <<<<
708 22:53:28.994241 Enter into DVFS_PRE_config >>>>>
709 22:53:29.004614 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:53:29.007921 Exit from DVFS_PRE_config <<<<<
711 22:53:29.011464 Enter into PICG configuration >>>>
712 22:53:29.014709 Exit from PICG configuration <<<<
713 22:53:29.015148 [RX_INPUT] configuration >>>>>
714 22:53:29.018038 [RX_INPUT] configuration <<<<<
715 22:53:29.024689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:53:29.028136 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:53:29.035147 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:53:29.042091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:53:29.048722 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:53:29.056075 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:53:29.059154 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:53:29.062411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:53:29.065683 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:53:29.072742 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:53:29.076446 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:53:29.079430 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:53:29.082463 ===================================
728 22:53:29.086113 LPDDR4 DRAM CONFIGURATION
729 22:53:29.089008 ===================================
730 22:53:29.089474 EX_ROW_EN[0] = 0x0
731 22:53:29.092548 EX_ROW_EN[1] = 0x0
732 22:53:29.093176 LP4Y_EN = 0x0
733 22:53:29.096005 WORK_FSP = 0x0
734 22:53:29.096438 WL = 0x2
735 22:53:29.099035 RL = 0x2
736 22:53:29.099472 BL = 0x2
737 22:53:29.102618 RPST = 0x0
738 22:53:29.103108 RD_PRE = 0x0
739 22:53:29.105910 WR_PRE = 0x1
740 22:53:29.109445 WR_PST = 0x0
741 22:53:29.109990 DBI_WR = 0x0
742 22:53:29.112586 DBI_RD = 0x0
743 22:53:29.113021 OTF = 0x1
744 22:53:29.116052 ===================================
745 22:53:29.119354 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:53:29.122462 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:53:29.129350 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:53:29.133197 ===================================
749 22:53:29.133781 LPDDR4 DRAM CONFIGURATION
750 22:53:29.136837 ===================================
751 22:53:29.139369 EX_ROW_EN[0] = 0x10
752 22:53:29.142774 EX_ROW_EN[1] = 0x0
753 22:53:29.143210 LP4Y_EN = 0x0
754 22:53:29.145790 WORK_FSP = 0x0
755 22:53:29.146229 WL = 0x2
756 22:53:29.149143 RL = 0x2
757 22:53:29.149611 BL = 0x2
758 22:53:29.153141 RPST = 0x0
759 22:53:29.153720 RD_PRE = 0x0
760 22:53:29.156424 WR_PRE = 0x1
761 22:53:29.157187 WR_PST = 0x0
762 22:53:29.159560 DBI_WR = 0x0
763 22:53:29.160094 DBI_RD = 0x0
764 22:53:29.162750 OTF = 0x1
765 22:53:29.166313 ===================================
766 22:53:29.173707 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:53:29.176624 nWR fixed to 40
768 22:53:29.177163 [ModeRegInit_LP4] CH0 RK0
769 22:53:29.179705 [ModeRegInit_LP4] CH0 RK1
770 22:53:29.182805 [ModeRegInit_LP4] CH1 RK0
771 22:53:29.186688 [ModeRegInit_LP4] CH1 RK1
772 22:53:29.187223 match AC timing 13
773 22:53:29.189792 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 22:53:29.193842 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:53:29.200365 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:53:29.203098 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:53:29.210117 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:53:29.210657 [EMI DOE] emi_dcm 0
779 22:53:29.213089 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:53:29.216888 ==
781 22:53:29.217473 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:53:29.223874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 22:53:29.224415 ==
784 22:53:29.226959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:53:29.233765 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:53:29.242911 [CA 0] Center 37 (7~68) winsize 62
787 22:53:29.246379 [CA 1] Center 37 (6~68) winsize 63
788 22:53:29.249941 [CA 2] Center 35 (5~66) winsize 62
789 22:53:29.253375 [CA 3] Center 34 (4~65) winsize 62
790 22:53:29.256737 [CA 4] Center 34 (3~65) winsize 63
791 22:53:29.259769 [CA 5] Center 33 (3~64) winsize 62
792 22:53:29.260206
793 22:53:29.263236 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 22:53:29.263674
795 22:53:29.266679 [CATrainingPosCal] consider 1 rank data
796 22:53:29.269895 u2DelayCellTimex100 = 270/100 ps
797 22:53:29.273471 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 22:53:29.276957 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 22:53:29.283199 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 22:53:29.286428 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 22:53:29.290168 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 22:53:29.293124 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 22:53:29.293689
804 22:53:29.296711 CA PerBit enable=1, Macro0, CA PI delay=33
805 22:53:29.297147
806 22:53:29.300386 [CBTSetCACLKResult] CA Dly = 33
807 22:53:29.300921 CS Dly: 5 (0~36)
808 22:53:29.301347 ==
809 22:53:29.303938 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:53:29.310138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:53:29.310679 ==
812 22:53:29.314048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:53:29.320627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:53:29.329369 [CA 0] Center 37 (7~68) winsize 62
815 22:53:29.332532 [CA 1] Center 37 (7~68) winsize 62
816 22:53:29.336260 [CA 2] Center 35 (5~66) winsize 62
817 22:53:29.339393 [CA 3] Center 35 (4~66) winsize 63
818 22:53:29.342583 [CA 4] Center 34 (3~65) winsize 63
819 22:53:29.346494 [CA 5] Center 33 (3~64) winsize 62
820 22:53:29.347025
821 22:53:29.349494 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 22:53:29.349927
823 22:53:29.352666 [CATrainingPosCal] consider 2 rank data
824 22:53:29.356115 u2DelayCellTimex100 = 270/100 ps
825 22:53:29.359526 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 22:53:29.363356 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 22:53:29.366168 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 22:53:29.373085 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 22:53:29.376537 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
830 22:53:29.379602 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 22:53:29.380065
832 22:53:29.383535 CA PerBit enable=1, Macro0, CA PI delay=33
833 22:53:29.384069
834 22:53:29.386110 [CBTSetCACLKResult] CA Dly = 33
835 22:53:29.386641 CS Dly: 5 (0~37)
836 22:53:29.386994
837 22:53:29.389864 ----->DramcWriteLeveling(PI) begin...
838 22:53:29.390302 ==
839 22:53:29.393231 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:53:29.400094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 22:53:29.400564 ==
842 22:53:29.403521 Write leveling (Byte 0): 30 => 30
843 22:53:29.403961 Write leveling (Byte 1): 28 => 28
844 22:53:29.407229 DramcWriteLeveling(PI) end<-----
845 22:53:29.407664
846 22:53:29.408123 ==
847 22:53:29.410939 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:53:29.415656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 22:53:29.416114 ==
850 22:53:29.419654 [Gating] SW mode calibration
851 22:53:29.425532 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:53:29.429695 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:53:29.437289 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:53:29.439712 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 22:53:29.443258 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 22:53:29.450134 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
857 22:53:29.453264 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:53:29.456903 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:53:29.460442 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:53:29.467811 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:53:29.470019 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:53:29.474166 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:53:29.480437 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:53:29.484239 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:53:29.487059 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:53:29.493416 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:53:29.496536 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:53:29.500208 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:53:29.506788 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:53:29.510406 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 22:53:29.513596 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
872 22:53:29.517348 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
873 22:53:29.523919 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:53:29.526899 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:53:29.530088 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:53:29.537310 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:53:29.540707 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:53:29.544212 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:53:29.550150 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 22:53:29.553848 0 9 12 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (1 1)
881 22:53:29.557283 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:53:29.564402 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:53:29.567011 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:53:29.570666 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:53:29.573648 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 22:53:29.580547 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 22:53:29.583832 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
888 22:53:29.587640 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
889 22:53:29.594056 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:53:29.597446 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:53:29.600475 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:53:29.607123 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:53:29.610998 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 22:53:29.614007 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 22:53:29.620985 0 11 8 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
896 22:53:29.624409 0 11 12 | B1->B0 | 3535 4242 | 0 0 | (0 0) (0 0)
897 22:53:29.627699 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:53:29.634172 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:53:29.637189 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:53:29.640523 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:53:29.643899 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 22:53:29.651227 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 22:53:29.654206 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 22:53:29.658107 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
905 22:53:29.664117 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:53:29.667760 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:53:29.670824 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:53:29.677576 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:53:29.680901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:53:29.684399 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:53:29.691182 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:53:29.694186 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:53:29.698011 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:53:29.704961 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:53:29.707919 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:53:29.711120 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:53:29.714330 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:53:29.721328 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 22:53:29.724640 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 22:53:29.727976 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
921 22:53:29.734441 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 22:53:29.734576 Total UI for P1: 0, mck2ui 16
923 22:53:29.741155 best dqsien dly found for B0: ( 0, 14, 10)
924 22:53:29.741335 Total UI for P1: 0, mck2ui 16
925 22:53:29.748068 best dqsien dly found for B1: ( 0, 14, 10)
926 22:53:29.751414 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
927 22:53:29.754541 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 22:53:29.754660
929 22:53:29.758593 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 22:53:29.761346 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 22:53:29.764582 [Gating] SW calibration Done
932 22:53:29.764702 ==
933 22:53:29.767906 Dram Type= 6, Freq= 0, CH_0, rank 0
934 22:53:29.771470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 22:53:29.771594 ==
936 22:53:29.774791 RX Vref Scan: 0
937 22:53:29.774912
938 22:53:29.775008 RX Vref 0 -> 0, step: 1
939 22:53:29.775100
940 22:53:29.778177 RX Delay -130 -> 252, step: 16
941 22:53:29.781794 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 22:53:29.788472 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 22:53:29.791416 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
944 22:53:29.794786 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
945 22:53:29.798610 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 22:53:29.801373 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
947 22:53:29.808055 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
948 22:53:29.811991 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 22:53:29.814729 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 22:53:29.818436 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
951 22:53:29.821628 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 22:53:29.825245 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 22:53:29.831600 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
954 22:53:29.835068 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 22:53:29.838454 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 22:53:29.841740 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 22:53:29.841862 ==
958 22:53:29.845339 Dram Type= 6, Freq= 0, CH_0, rank 0
959 22:53:29.851697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 22:53:29.851853 ==
961 22:53:29.851954 DQS Delay:
962 22:53:29.855605 DQS0 = 0, DQS1 = 0
963 22:53:29.855727 DQM Delay:
964 22:53:29.855823 DQM0 = 83, DQM1 = 76
965 22:53:29.858379 DQ Delay:
966 22:53:29.861902 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
967 22:53:29.865304 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
968 22:53:29.868802 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
969 22:53:29.872329 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
970 22:53:29.872564
971 22:53:29.872696
972 22:53:29.872814 ==
973 22:53:29.875851 Dram Type= 6, Freq= 0, CH_0, rank 0
974 22:53:29.878994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 22:53:29.879254 ==
976 22:53:29.879394
977 22:53:29.879520
978 22:53:29.882490 TX Vref Scan disable
979 22:53:29.882688 == TX Byte 0 ==
980 22:53:29.888659 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
981 22:53:29.892122 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
982 22:53:29.892499 == TX Byte 1 ==
983 22:53:29.899135 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
984 22:53:29.902598 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
985 22:53:29.903151 ==
986 22:53:29.905892 Dram Type= 6, Freq= 0, CH_0, rank 0
987 22:53:29.908836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 22:53:29.909317 ==
989 22:53:29.923467 TX Vref=22, minBit 0, minWin=27, winSum=439
990 22:53:29.926880 TX Vref=24, minBit 5, minWin=27, winSum=442
991 22:53:29.929748 TX Vref=26, minBit 5, minWin=27, winSum=448
992 22:53:29.933734 TX Vref=28, minBit 5, minWin=27, winSum=450
993 22:53:29.936458 TX Vref=30, minBit 5, minWin=27, winSum=454
994 22:53:29.940495 TX Vref=32, minBit 1, minWin=28, winSum=453
995 22:53:29.946957 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 32
996 22:53:29.947397
997 22:53:29.949990 Final TX Range 1 Vref 32
998 22:53:29.950624
999 22:53:29.951280 ==
1000 22:53:29.953165 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 22:53:29.957001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 22:53:29.957592 ==
1003 22:53:29.957948
1004 22:53:29.958316
1005 22:53:29.960046 TX Vref Scan disable
1006 22:53:29.963437 == TX Byte 0 ==
1007 22:53:29.966491 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1008 22:53:29.970441 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1009 22:53:29.973950 == TX Byte 1 ==
1010 22:53:29.976713 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1011 22:53:29.980399 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1012 22:53:29.980983
1013 22:53:29.983138 [DATLAT]
1014 22:53:29.983623 Freq=800, CH0 RK0
1015 22:53:29.983973
1016 22:53:29.987063 DATLAT Default: 0xa
1017 22:53:29.987497 0, 0xFFFF, sum = 0
1018 22:53:29.989999 1, 0xFFFF, sum = 0
1019 22:53:29.990454 2, 0xFFFF, sum = 0
1020 22:53:29.993549 3, 0xFFFF, sum = 0
1021 22:53:29.993987 4, 0xFFFF, sum = 0
1022 22:53:29.996914 5, 0xFFFF, sum = 0
1023 22:53:29.997528 6, 0xFFFF, sum = 0
1024 22:53:30.000485 7, 0xFFFF, sum = 0
1025 22:53:30.000937 8, 0xFFFF, sum = 0
1026 22:53:30.003788 9, 0x0, sum = 1
1027 22:53:30.004224 10, 0x0, sum = 2
1028 22:53:30.007018 11, 0x0, sum = 3
1029 22:53:30.007481 12, 0x0, sum = 4
1030 22:53:30.010878 best_step = 10
1031 22:53:30.011590
1032 22:53:30.012186 ==
1033 22:53:30.013808 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 22:53:30.017000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 22:53:30.017606 ==
1036 22:53:30.018099 RX Vref Scan: 1
1037 22:53:30.018570
1038 22:53:30.020328 Set Vref Range= 32 -> 127
1039 22:53:30.020753
1040 22:53:30.023655 RX Vref 32 -> 127, step: 1
1041 22:53:30.024148
1042 22:53:30.027094 RX Delay -95 -> 252, step: 8
1043 22:53:30.027522
1044 22:53:30.030690 Set Vref, RX VrefLevel [Byte0]: 32
1045 22:53:30.033878 [Byte1]: 32
1046 22:53:30.034308
1047 22:53:30.037431 Set Vref, RX VrefLevel [Byte0]: 33
1048 22:53:30.041049 [Byte1]: 33
1049 22:53:30.041658
1050 22:53:30.044292 Set Vref, RX VrefLevel [Byte0]: 34
1051 22:53:30.047564 [Byte1]: 34
1052 22:53:30.051079
1053 22:53:30.051507 Set Vref, RX VrefLevel [Byte0]: 35
1054 22:53:30.054210 [Byte1]: 35
1055 22:53:30.059002
1056 22:53:30.059516 Set Vref, RX VrefLevel [Byte0]: 36
1057 22:53:30.061863 [Byte1]: 36
1058 22:53:30.066621
1059 22:53:30.067062 Set Vref, RX VrefLevel [Byte0]: 37
1060 22:53:30.069361 [Byte1]: 37
1061 22:53:30.073948
1062 22:53:30.074372 Set Vref, RX VrefLevel [Byte0]: 38
1063 22:53:30.077472 [Byte1]: 38
1064 22:53:30.081905
1065 22:53:30.082421 Set Vref, RX VrefLevel [Byte0]: 39
1066 22:53:30.084918 [Byte1]: 39
1067 22:53:30.088975
1068 22:53:30.089471 Set Vref, RX VrefLevel [Byte0]: 40
1069 22:53:30.092229 [Byte1]: 40
1070 22:53:30.096373
1071 22:53:30.096805 Set Vref, RX VrefLevel [Byte0]: 41
1072 22:53:30.100278 [Byte1]: 41
1073 22:53:30.104021
1074 22:53:30.104445 Set Vref, RX VrefLevel [Byte0]: 42
1075 22:53:30.107124 [Byte1]: 42
1076 22:53:30.111824
1077 22:53:30.112344 Set Vref, RX VrefLevel [Byte0]: 43
1078 22:53:30.114778 [Byte1]: 43
1079 22:53:30.119131
1080 22:53:30.119658 Set Vref, RX VrefLevel [Byte0]: 44
1081 22:53:30.122488 [Byte1]: 44
1082 22:53:30.126823
1083 22:53:30.127272 Set Vref, RX VrefLevel [Byte0]: 45
1084 22:53:30.130132 [Byte1]: 45
1085 22:53:30.134447
1086 22:53:30.134867 Set Vref, RX VrefLevel [Byte0]: 46
1087 22:53:30.137746 [Byte1]: 46
1088 22:53:30.142200
1089 22:53:30.142619 Set Vref, RX VrefLevel [Byte0]: 47
1090 22:53:30.145464 [Byte1]: 47
1091 22:53:30.149309
1092 22:53:30.149768 Set Vref, RX VrefLevel [Byte0]: 48
1093 22:53:30.153385 [Byte1]: 48
1094 22:53:30.157394
1095 22:53:30.157912 Set Vref, RX VrefLevel [Byte0]: 49
1096 22:53:30.161044 [Byte1]: 49
1097 22:53:30.164963
1098 22:53:30.165646 Set Vref, RX VrefLevel [Byte0]: 50
1099 22:53:30.167907 [Byte1]: 50
1100 22:53:30.172285
1101 22:53:30.172787 Set Vref, RX VrefLevel [Byte0]: 51
1102 22:53:30.175950 [Byte1]: 51
1103 22:53:30.180380
1104 22:53:30.180899 Set Vref, RX VrefLevel [Byte0]: 52
1105 22:53:30.183245 [Byte1]: 52
1106 22:53:30.187774
1107 22:53:30.188335 Set Vref, RX VrefLevel [Byte0]: 53
1108 22:53:30.190769 [Byte1]: 53
1109 22:53:30.195199
1110 22:53:30.195718 Set Vref, RX VrefLevel [Byte0]: 54
1111 22:53:30.198754 [Byte1]: 54
1112 22:53:30.203065
1113 22:53:30.203486 Set Vref, RX VrefLevel [Byte0]: 55
1114 22:53:30.205994 [Byte1]: 55
1115 22:53:30.210502
1116 22:53:30.211025 Set Vref, RX VrefLevel [Byte0]: 56
1117 22:53:30.213739 [Byte1]: 56
1118 22:53:30.218064
1119 22:53:30.221531 Set Vref, RX VrefLevel [Byte0]: 57
1120 22:53:30.222051 [Byte1]: 57
1121 22:53:30.225466
1122 22:53:30.226082 Set Vref, RX VrefLevel [Byte0]: 58
1123 22:53:30.228686 [Byte1]: 58
1124 22:53:30.232975
1125 22:53:30.233545 Set Vref, RX VrefLevel [Byte0]: 59
1126 22:53:30.236496 [Byte1]: 59
1127 22:53:30.241403
1128 22:53:30.241921 Set Vref, RX VrefLevel [Byte0]: 60
1129 22:53:30.244394 [Byte1]: 60
1130 22:53:30.248706
1131 22:53:30.249467 Set Vref, RX VrefLevel [Byte0]: 61
1132 22:53:30.251717 [Byte1]: 61
1133 22:53:30.256012
1134 22:53:30.256533 Set Vref, RX VrefLevel [Byte0]: 62
1135 22:53:30.259214 [Byte1]: 62
1136 22:53:30.263843
1137 22:53:30.264375 Set Vref, RX VrefLevel [Byte0]: 63
1138 22:53:30.267345 [Byte1]: 63
1139 22:53:30.271332
1140 22:53:30.271848 Set Vref, RX VrefLevel [Byte0]: 64
1141 22:53:30.274605 [Byte1]: 64
1142 22:53:30.279119
1143 22:53:30.279640 Set Vref, RX VrefLevel [Byte0]: 65
1144 22:53:30.281898 [Byte1]: 65
1145 22:53:30.286159
1146 22:53:30.286694 Set Vref, RX VrefLevel [Byte0]: 66
1147 22:53:30.290011 [Byte1]: 66
1148 22:53:30.293711
1149 22:53:30.294102 Set Vref, RX VrefLevel [Byte0]: 67
1150 22:53:30.297769 [Byte1]: 67
1151 22:53:30.301800
1152 22:53:30.302383 Set Vref, RX VrefLevel [Byte0]: 68
1153 22:53:30.304820 [Byte1]: 68
1154 22:53:30.309242
1155 22:53:30.309770 Set Vref, RX VrefLevel [Byte0]: 69
1156 22:53:30.312566 [Byte1]: 69
1157 22:53:30.316728
1158 22:53:30.317300 Set Vref, RX VrefLevel [Byte0]: 70
1159 22:53:30.319980 [Byte1]: 70
1160 22:53:30.324435
1161 22:53:30.324957 Set Vref, RX VrefLevel [Byte0]: 71
1162 22:53:30.327513 [Byte1]: 71
1163 22:53:30.332007
1164 22:53:30.332528 Set Vref, RX VrefLevel [Byte0]: 72
1165 22:53:30.335600 [Byte1]: 72
1166 22:53:30.339897
1167 22:53:30.340416 Set Vref, RX VrefLevel [Byte0]: 73
1168 22:53:30.342935 [Byte1]: 73
1169 22:53:30.346882
1170 22:53:30.347306 Set Vref, RX VrefLevel [Byte0]: 74
1171 22:53:30.350500 [Byte1]: 74
1172 22:53:30.354631
1173 22:53:30.355154 Set Vref, RX VrefLevel [Byte0]: 75
1174 22:53:30.358504 [Byte1]: 75
1175 22:53:30.362237
1176 22:53:30.362767 Set Vref, RX VrefLevel [Byte0]: 76
1177 22:53:30.365435 [Byte1]: 76
1178 22:53:30.370147
1179 22:53:30.370676 Set Vref, RX VrefLevel [Byte0]: 77
1180 22:53:30.373751 [Byte1]: 77
1181 22:53:30.377557
1182 22:53:30.378080 Final RX Vref Byte 0 = 61 to rank0
1183 22:53:30.380957 Final RX Vref Byte 1 = 57 to rank0
1184 22:53:30.384635 Final RX Vref Byte 0 = 61 to rank1
1185 22:53:30.387305 Final RX Vref Byte 1 = 57 to rank1==
1186 22:53:30.391244 Dram Type= 6, Freq= 0, CH_0, rank 0
1187 22:53:30.394377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 22:53:30.397243 ==
1189 22:53:30.397666 DQS Delay:
1190 22:53:30.398044 DQS0 = 0, DQS1 = 0
1191 22:53:30.400546 DQM Delay:
1192 22:53:30.400967 DQM0 = 88, DQM1 = 79
1193 22:53:30.404084 DQ Delay:
1194 22:53:30.407605 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1195 22:53:30.408035 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1196 22:53:30.410960 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1197 22:53:30.414039 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1198 22:53:30.414465
1199 22:53:30.417513
1200 22:53:30.424189 [DQSOSCAuto] RK0, (LSB)MR18= 0x230b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
1201 22:53:30.427335 CH0 RK0: MR19=606, MR18=230B
1202 22:53:30.434938 CH0_RK0: MR19=0x606, MR18=0x230B, DQSOSC=401, MR23=63, INC=91, DEC=61
1203 22:53:30.435468
1204 22:53:30.437777 ----->DramcWriteLeveling(PI) begin...
1205 22:53:30.438208 ==
1206 22:53:30.441048 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 22:53:30.444217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 22:53:30.444755 ==
1209 22:53:30.447831 Write leveling (Byte 0): 29 => 29
1210 22:53:30.451039 Write leveling (Byte 1): 28 => 28
1211 22:53:30.454451 DramcWriteLeveling(PI) end<-----
1212 22:53:30.454872
1213 22:53:30.455205 ==
1214 22:53:30.458134 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 22:53:30.461475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 22:53:30.462036 ==
1217 22:53:30.464984 [Gating] SW mode calibration
1218 22:53:30.471130 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1219 22:53:30.519044 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1220 22:53:30.519582 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 22:53:30.519929 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1222 22:53:30.520593 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1223 22:53:30.520932 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:53:30.521337 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:53:30.521660 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:53:30.522011 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:53:30.522316 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:53:30.522676 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:53:30.541843 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:53:30.542558 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:53:30.543256 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:53:30.543605 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:53:30.543915 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 22:53:30.544217 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:53:30.545811 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:53:30.552568 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 22:53:30.555998 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1238 22:53:30.559328 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1239 22:53:30.565844 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1240 22:53:30.569177 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:53:30.572697 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:53:30.576094 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 22:53:30.582277 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 22:53:30.586538 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 22:53:30.589581 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 22:53:30.596092 0 9 8 | B1->B0 | 2323 3030 | 1 1 | (0 0) (0 0)
1247 22:53:30.599606 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1248 22:53:30.602839 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 22:53:30.609979 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 22:53:30.613146 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 22:53:30.616823 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 22:53:30.623569 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1253 22:53:30.626486 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1254 22:53:30.629327 0 10 8 | B1->B0 | 3030 2828 | 1 0 | (1 0) (0 0)
1255 22:53:30.633380 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1256 22:53:30.640463 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 22:53:30.642733 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 22:53:30.647433 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 22:53:30.653943 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 22:53:30.657358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 22:53:30.661356 0 11 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
1262 22:53:30.665340 0 11 8 | B1->B0 | 2e2e 4242 | 0 0 | (1 1) (0 0)
1263 22:53:30.668648 0 11 12 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1264 22:53:30.675833 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 22:53:30.679292 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 22:53:30.683403 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 22:53:30.686604 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 22:53:30.693040 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 22:53:30.696470 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1270 22:53:30.699791 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1271 22:53:30.703518 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 22:53:30.709730 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 22:53:30.713302 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 22:53:30.716253 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 22:53:30.723326 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 22:53:30.726731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 22:53:30.729727 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 22:53:30.736628 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 22:53:30.740394 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 22:53:30.743831 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 22:53:30.750094 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 22:53:30.753617 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 22:53:30.756494 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 22:53:30.763498 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 22:53:30.766417 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1286 22:53:30.770515 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1287 22:53:30.773891 Total UI for P1: 0, mck2ui 16
1288 22:53:30.777260 best dqsien dly found for B0: ( 0, 14, 4)
1289 22:53:30.780848 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 22:53:30.783342 Total UI for P1: 0, mck2ui 16
1291 22:53:30.787046 best dqsien dly found for B1: ( 0, 14, 8)
1292 22:53:30.790421 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1293 22:53:30.793815 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1294 22:53:30.797255
1295 22:53:30.800313 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1296 22:53:30.803915 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1297 22:53:30.807163 [Gating] SW calibration Done
1298 22:53:30.807610 ==
1299 22:53:30.810547 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 22:53:30.813539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 22:53:30.814064 ==
1302 22:53:30.814404 RX Vref Scan: 0
1303 22:53:30.814718
1304 22:53:30.816849 RX Vref 0 -> 0, step: 1
1305 22:53:30.817313
1306 22:53:30.820218 RX Delay -130 -> 252, step: 16
1307 22:53:30.823651 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1308 22:53:30.827084 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1309 22:53:30.830150 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1310 22:53:30.837314 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1311 22:53:30.840635 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1312 22:53:30.844188 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1313 22:53:30.846966 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1314 22:53:30.850291 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1315 22:53:30.857626 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1316 22:53:30.860251 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1317 22:53:30.863709 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1318 22:53:30.867426 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1319 22:53:30.870600 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1320 22:53:30.877605 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1321 22:53:30.880512 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1322 22:53:30.884468 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1323 22:53:30.885000 ==
1324 22:53:30.887349 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 22:53:30.891119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 22:53:30.891657 ==
1327 22:53:30.893794 DQS Delay:
1328 22:53:30.894221 DQS0 = 0, DQS1 = 0
1329 22:53:30.897614 DQM Delay:
1330 22:53:30.898132 DQM0 = 87, DQM1 = 77
1331 22:53:30.898468 DQ Delay:
1332 22:53:30.901385 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1333 22:53:30.904194 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1334 22:53:30.907880 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1335 22:53:30.910587 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1336 22:53:30.911018
1337 22:53:30.911355
1338 22:53:30.914540 ==
1339 22:53:30.917542 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 22:53:30.921224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 22:53:30.921760 ==
1342 22:53:30.922107
1343 22:53:30.922428
1344 22:53:30.924549 TX Vref Scan disable
1345 22:53:30.925069 == TX Byte 0 ==
1346 22:53:30.927388 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1347 22:53:30.934019 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1348 22:53:30.934543 == TX Byte 1 ==
1349 22:53:30.937321 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1350 22:53:30.944246 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1351 22:53:30.944771 ==
1352 22:53:30.947321 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 22:53:30.951172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 22:53:30.951604 ==
1355 22:53:30.963959 TX Vref=22, minBit 3, minWin=27, winSum=440
1356 22:53:30.967891 TX Vref=24, minBit 2, minWin=27, winSum=441
1357 22:53:30.971256 TX Vref=26, minBit 0, minWin=28, winSum=453
1358 22:53:30.974075 TX Vref=28, minBit 3, minWin=27, winSum=451
1359 22:53:30.977132 TX Vref=30, minBit 0, minWin=28, winSum=457
1360 22:53:30.980853 TX Vref=32, minBit 12, minWin=27, winSum=455
1361 22:53:30.987300 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1362 22:53:30.987726
1363 22:53:30.990576 Final TX Range 1 Vref 30
1364 22:53:30.991104
1365 22:53:30.991444 ==
1366 22:53:30.994643 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 22:53:30.997514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 22:53:30.997962 ==
1369 22:53:30.998322
1370 22:53:30.998637
1371 22:53:31.000503 TX Vref Scan disable
1372 22:53:31.004327 == TX Byte 0 ==
1373 22:53:31.007455 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1374 22:53:31.010768 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1375 22:53:31.014337 == TX Byte 1 ==
1376 22:53:31.017460 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1377 22:53:31.021077 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1378 22:53:31.021644
1379 22:53:31.024036 [DATLAT]
1380 22:53:31.024547 Freq=800, CH0 RK1
1381 22:53:31.024884
1382 22:53:31.027487 DATLAT Default: 0xa
1383 22:53:31.027913 0, 0xFFFF, sum = 0
1384 22:53:31.031091 1, 0xFFFF, sum = 0
1385 22:53:31.031519 2, 0xFFFF, sum = 0
1386 22:53:31.034290 3, 0xFFFF, sum = 0
1387 22:53:31.035000 4, 0xFFFF, sum = 0
1388 22:53:31.038222 5, 0xFFFF, sum = 0
1389 22:53:31.038744 6, 0xFFFF, sum = 0
1390 22:53:31.040639 7, 0xFFFF, sum = 0
1391 22:53:31.041151 8, 0xFFFF, sum = 0
1392 22:53:31.044809 9, 0x0, sum = 1
1393 22:53:31.045274 10, 0x0, sum = 2
1394 22:53:31.048008 11, 0x0, sum = 3
1395 22:53:31.048413 12, 0x0, sum = 4
1396 22:53:31.051429 best_step = 10
1397 22:53:31.051946
1398 22:53:31.052282 ==
1399 22:53:31.054248 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 22:53:31.058238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 22:53:31.058661 ==
1402 22:53:31.061590 RX Vref Scan: 0
1403 22:53:31.062117
1404 22:53:31.062468 RX Vref 0 -> 0, step: 1
1405 22:53:31.062785
1406 22:53:31.064536 RX Delay -95 -> 252, step: 8
1407 22:53:31.071165 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1408 22:53:31.074921 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1409 22:53:31.078066 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1410 22:53:31.081903 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1411 22:53:31.084769 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1412 22:53:31.088450 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1413 22:53:31.094583 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1414 22:53:31.098255 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1415 22:53:31.101863 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1416 22:53:31.104943 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1417 22:53:31.108171 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1418 22:53:31.114930 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1419 22:53:31.118575 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1420 22:53:31.121635 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1421 22:53:31.124761 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1422 22:53:31.128318 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1423 22:53:31.131524 ==
1424 22:53:31.132045 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 22:53:31.138359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 22:53:31.138794 ==
1427 22:53:31.139134 DQS Delay:
1428 22:53:31.141865 DQS0 = 0, DQS1 = 0
1429 22:53:31.142385 DQM Delay:
1430 22:53:31.142728 DQM0 = 87, DQM1 = 78
1431 22:53:31.145026 DQ Delay:
1432 22:53:31.148995 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1433 22:53:31.152096 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1434 22:53:31.155333 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1435 22:53:31.158648 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1436 22:53:31.159181
1437 22:53:31.159513
1438 22:53:31.165593 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1439 22:53:31.168504 CH0 RK1: MR19=606, MR18=2B15
1440 22:53:31.175055 CH0_RK1: MR19=0x606, MR18=0x2B15, DQSOSC=398, MR23=63, INC=93, DEC=62
1441 22:53:31.178347 [RxdqsGatingPostProcess] freq 800
1442 22:53:31.182291 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 22:53:31.185323 Pre-setting of DQS Precalculation
1444 22:53:31.192582 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 22:53:31.193104 ==
1446 22:53:31.194984 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 22:53:31.198955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 22:53:31.199524 ==
1449 22:53:31.205594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 22:53:31.209002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 22:53:31.218964 [CA 0] Center 36 (6~67) winsize 62
1452 22:53:31.222508 [CA 1] Center 36 (5~67) winsize 63
1453 22:53:31.225618 [CA 2] Center 34 (4~64) winsize 61
1454 22:53:31.228933 [CA 3] Center 33 (3~64) winsize 62
1455 22:53:31.232179 [CA 4] Center 33 (3~64) winsize 62
1456 22:53:31.235829 [CA 5] Center 33 (3~64) winsize 62
1457 22:53:31.236247
1458 22:53:31.239082 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1459 22:53:31.239625
1460 22:53:31.242068 [CATrainingPosCal] consider 1 rank data
1461 22:53:31.246007 u2DelayCellTimex100 = 270/100 ps
1462 22:53:31.248896 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1463 22:53:31.252292 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1464 22:53:31.256035 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1465 22:53:31.262416 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1466 22:53:31.265765 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1467 22:53:31.269422 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1468 22:53:31.269927
1469 22:53:31.272351 CA PerBit enable=1, Macro0, CA PI delay=33
1470 22:53:31.272769
1471 22:53:31.275534 [CBTSetCACLKResult] CA Dly = 33
1472 22:53:31.276013 CS Dly: 4 (0~35)
1473 22:53:31.276351 ==
1474 22:53:31.279474 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 22:53:31.285915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 22:53:31.286443 ==
1477 22:53:31.289183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 22:53:31.295739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 22:53:31.305273 [CA 0] Center 36 (6~67) winsize 62
1480 22:53:31.308576 [CA 1] Center 36 (6~67) winsize 62
1481 22:53:31.311873 [CA 2] Center 34 (3~65) winsize 63
1482 22:53:31.315523 [CA 3] Center 33 (3~64) winsize 62
1483 22:53:31.319038 [CA 4] Center 34 (3~65) winsize 63
1484 22:53:31.322423 [CA 5] Center 33 (2~64) winsize 63
1485 22:53:31.322869
1486 22:53:31.326398 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1487 22:53:31.326819
1488 22:53:31.330287 [CATrainingPosCal] consider 2 rank data
1489 22:53:31.333420 u2DelayCellTimex100 = 270/100 ps
1490 22:53:31.337021 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1491 22:53:31.341603 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1492 22:53:31.344559 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1493 22:53:31.348199 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1494 22:53:31.351819 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1495 22:53:31.355107 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1496 22:53:31.355546
1497 22:53:31.359628 CA PerBit enable=1, Macro0, CA PI delay=33
1498 22:53:31.360155
1499 22:53:31.361814 [CBTSetCACLKResult] CA Dly = 33
1500 22:53:31.362235 CS Dly: 5 (0~37)
1501 22:53:31.362569
1502 22:53:31.365777 ----->DramcWriteLeveling(PI) begin...
1503 22:53:31.366216 ==
1504 22:53:31.369096 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 22:53:31.376391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 22:53:31.376916 ==
1507 22:53:31.379160 Write leveling (Byte 0): 27 => 27
1508 22:53:31.379687 Write leveling (Byte 1): 29 => 29
1509 22:53:31.383019 DramcWriteLeveling(PI) end<-----
1510 22:53:31.383541
1511 22:53:31.383871 ==
1512 22:53:31.385888 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 22:53:31.392565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 22:53:31.393092 ==
1515 22:53:31.395703 [Gating] SW mode calibration
1516 22:53:31.402625 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 22:53:31.405371 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 22:53:31.412678 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 22:53:31.415918 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1520 22:53:31.419481 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1521 22:53:31.422663 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:53:31.429399 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:53:31.432681 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:53:31.436100 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:53:31.442747 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:53:31.446116 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:53:31.449902 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:53:31.455881 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:53:31.459835 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:53:31.463276 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:53:31.469983 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:53:31.472896 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:53:31.476590 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:53:31.479648 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 22:53:31.486292 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:53:31.490104 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1537 22:53:31.493313 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:53:31.499759 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:53:31.503150 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:53:31.506624 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 22:53:31.513142 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 22:53:31.516530 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 22:53:31.520111 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 22:53:31.526683 0 9 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1545 22:53:31.529815 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1546 22:53:31.533380 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 22:53:31.539967 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 22:53:31.543073 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 22:53:31.546868 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 22:53:31.549678 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1551 22:53:31.556644 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1552 22:53:31.560345 0 10 8 | B1->B0 | 2929 2f2f | 0 1 | (1 0) (1 0)
1553 22:53:31.563421 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 22:53:31.569882 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 22:53:31.574074 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 22:53:31.576477 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 22:53:31.584013 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 22:53:31.586937 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 22:53:31.590685 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1560 22:53:31.597007 0 11 8 | B1->B0 | 3636 3333 | 0 0 | (0 0) (0 0)
1561 22:53:31.600520 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 22:53:31.603482 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 22:53:31.607305 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 22:53:31.614160 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 22:53:31.617599 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 22:53:31.620353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 22:53:31.627171 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 22:53:31.630352 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 22:53:31.633979 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 22:53:31.640686 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 22:53:31.644376 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 22:53:31.647579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 22:53:31.653796 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 22:53:31.657699 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 22:53:31.660828 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 22:53:31.664599 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 22:53:31.670807 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 22:53:31.674411 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 22:53:31.677650 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 22:53:31.684431 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 22:53:31.688075 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 22:53:31.690997 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 22:53:31.697584 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 22:53:31.700812 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 22:53:31.704907 Total UI for P1: 0, mck2ui 16
1586 22:53:31.707769 best dqsien dly found for B0: ( 0, 14, 6)
1587 22:53:31.711255 Total UI for P1: 0, mck2ui 16
1588 22:53:31.714207 best dqsien dly found for B1: ( 0, 14, 6)
1589 22:53:31.717712 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1590 22:53:31.721425 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1591 22:53:31.721958
1592 22:53:31.724030 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1593 22:53:31.727839 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1594 22:53:31.731601 [Gating] SW calibration Done
1595 22:53:31.732126 ==
1596 22:53:31.733999 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 22:53:31.737661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 22:53:31.738082 ==
1599 22:53:31.740643 RX Vref Scan: 0
1600 22:53:31.741056
1601 22:53:31.744711 RX Vref 0 -> 0, step: 1
1602 22:53:31.745273
1603 22:53:31.745614 RX Delay -130 -> 252, step: 16
1604 22:53:31.751115 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1605 22:53:31.754549 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1606 22:53:31.757668 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1607 22:53:31.761482 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1608 22:53:31.764646 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1609 22:53:31.770809 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1610 22:53:31.774712 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1611 22:53:31.778041 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1612 22:53:31.781137 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1613 22:53:31.784738 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1614 22:53:31.787902 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1615 22:53:31.794396 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1616 22:53:31.798402 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1617 22:53:31.801697 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1618 22:53:31.804340 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1619 22:53:31.808027 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1620 22:53:31.811582 ==
1621 22:53:31.814848 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 22:53:31.817971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 22:53:31.818415 ==
1624 22:53:31.818860 DQS Delay:
1625 22:53:31.821590 DQS0 = 0, DQS1 = 0
1626 22:53:31.822027 DQM Delay:
1627 22:53:31.824783 DQM0 = 81, DQM1 = 74
1628 22:53:31.825399 DQ Delay:
1629 22:53:31.828154 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1630 22:53:31.831462 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1631 22:53:31.834426 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1632 22:53:31.837983 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1633 22:53:31.838417
1634 22:53:31.838746
1635 22:53:31.839052 ==
1636 22:53:31.841181 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 22:53:31.845092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 22:53:31.845549 ==
1639 22:53:31.845881
1640 22:53:31.846226
1641 22:53:31.848113 TX Vref Scan disable
1642 22:53:31.851192 == TX Byte 0 ==
1643 22:53:31.854937 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1644 22:53:31.858163 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1645 22:53:31.861406 == TX Byte 1 ==
1646 22:53:31.864720 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1647 22:53:31.868233 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1648 22:53:31.868864 ==
1649 22:53:31.871241 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 22:53:31.874545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 22:53:31.874992 ==
1652 22:53:31.889282 TX Vref=22, minBit 0, minWin=27, winSum=438
1653 22:53:31.892866 TX Vref=24, minBit 0, minWin=27, winSum=440
1654 22:53:31.896670 TX Vref=26, minBit 15, minWin=26, winSum=445
1655 22:53:31.900203 TX Vref=28, minBit 10, minWin=27, winSum=450
1656 22:53:31.904200 TX Vref=30, minBit 10, minWin=27, winSum=451
1657 22:53:31.906966 TX Vref=32, minBit 0, minWin=28, winSum=454
1658 22:53:31.913912 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1659 22:53:31.914331
1660 22:53:31.917516 Final TX Range 1 Vref 32
1661 22:53:31.917935
1662 22:53:31.918264 ==
1663 22:53:31.920790 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 22:53:31.923710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 22:53:31.924132 ==
1666 22:53:31.924462
1667 22:53:31.924768
1668 22:53:31.927415 TX Vref Scan disable
1669 22:53:31.930618 == TX Byte 0 ==
1670 22:53:31.933656 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1671 22:53:31.937415 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1672 22:53:31.941058 == TX Byte 1 ==
1673 22:53:31.944244 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1674 22:53:31.947199 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1675 22:53:31.947731
1676 22:53:31.948065 [DATLAT]
1677 22:53:31.950957 Freq=800, CH1 RK0
1678 22:53:31.951536
1679 22:53:31.955095 DATLAT Default: 0xa
1680 22:53:31.955648 0, 0xFFFF, sum = 0
1681 22:53:31.957614 1, 0xFFFF, sum = 0
1682 22:53:31.958041 2, 0xFFFF, sum = 0
1683 22:53:31.961203 3, 0xFFFF, sum = 0
1684 22:53:31.961777 4, 0xFFFF, sum = 0
1685 22:53:31.964023 5, 0xFFFF, sum = 0
1686 22:53:31.964552 6, 0xFFFF, sum = 0
1687 22:53:31.967095 7, 0xFFFF, sum = 0
1688 22:53:31.967561 8, 0xFFFF, sum = 0
1689 22:53:31.970422 9, 0x0, sum = 1
1690 22:53:31.970854 10, 0x0, sum = 2
1691 22:53:31.974545 11, 0x0, sum = 3
1692 22:53:31.975086 12, 0x0, sum = 4
1693 22:53:31.975435 best_step = 10
1694 22:53:31.975751
1695 22:53:31.977366 ==
1696 22:53:31.980523 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 22:53:31.984424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 22:53:31.984856 ==
1699 22:53:31.985272 RX Vref Scan: 1
1700 22:53:31.985604
1701 22:53:31.987722 Set Vref Range= 32 -> 127
1702 22:53:31.988253
1703 22:53:31.990801 RX Vref 32 -> 127, step: 1
1704 22:53:31.991335
1705 22:53:31.994754 RX Delay -111 -> 252, step: 8
1706 22:53:31.995286
1707 22:53:31.997342 Set Vref, RX VrefLevel [Byte0]: 32
1708 22:53:32.000304 [Byte1]: 32
1709 22:53:32.000723
1710 22:53:32.004202 Set Vref, RX VrefLevel [Byte0]: 33
1711 22:53:32.007380 [Byte1]: 33
1712 22:53:32.007805
1713 22:53:32.010642 Set Vref, RX VrefLevel [Byte0]: 34
1714 22:53:32.013787 [Byte1]: 34
1715 22:53:32.017889
1716 22:53:32.018425 Set Vref, RX VrefLevel [Byte0]: 35
1717 22:53:32.021199 [Byte1]: 35
1718 22:53:32.025693
1719 22:53:32.026144 Set Vref, RX VrefLevel [Byte0]: 36
1720 22:53:32.028806 [Byte1]: 36
1721 22:53:32.032968
1722 22:53:32.033561 Set Vref, RX VrefLevel [Byte0]: 37
1723 22:53:32.036496 [Byte1]: 37
1724 22:53:32.041121
1725 22:53:32.041690 Set Vref, RX VrefLevel [Byte0]: 38
1726 22:53:32.044443 [Byte1]: 38
1727 22:53:32.048576
1728 22:53:32.049011 Set Vref, RX VrefLevel [Byte0]: 39
1729 22:53:32.052201 [Byte1]: 39
1730 22:53:32.056089
1731 22:53:32.056511 Set Vref, RX VrefLevel [Byte0]: 40
1732 22:53:32.058816 [Byte1]: 40
1733 22:53:32.063810
1734 22:53:32.064418 Set Vref, RX VrefLevel [Byte0]: 41
1735 22:53:32.066791 [Byte1]: 41
1736 22:53:32.071141
1737 22:53:32.071605 Set Vref, RX VrefLevel [Byte0]: 42
1738 22:53:32.074202 [Byte1]: 42
1739 22:53:32.078739
1740 22:53:32.079162 Set Vref, RX VrefLevel [Byte0]: 43
1741 22:53:32.082110 [Byte1]: 43
1742 22:53:32.086337
1743 22:53:32.087013 Set Vref, RX VrefLevel [Byte0]: 44
1744 22:53:32.089924 [Byte1]: 44
1745 22:53:32.093905
1746 22:53:32.094365 Set Vref, RX VrefLevel [Byte0]: 45
1747 22:53:32.097294 [Byte1]: 45
1748 22:53:32.101483
1749 22:53:32.101955 Set Vref, RX VrefLevel [Byte0]: 46
1750 22:53:32.104875 [Byte1]: 46
1751 22:53:32.109847
1752 22:53:32.110270 Set Vref, RX VrefLevel [Byte0]: 47
1753 22:53:32.112504 [Byte1]: 47
1754 22:53:32.116869
1755 22:53:32.117329 Set Vref, RX VrefLevel [Byte0]: 48
1756 22:53:32.120105 [Byte1]: 48
1757 22:53:32.125099
1758 22:53:32.125675 Set Vref, RX VrefLevel [Byte0]: 49
1759 22:53:32.128216 [Byte1]: 49
1760 22:53:32.132590
1761 22:53:32.133102 Set Vref, RX VrefLevel [Byte0]: 50
1762 22:53:32.135965 [Byte1]: 50
1763 22:53:32.140298
1764 22:53:32.140722 Set Vref, RX VrefLevel [Byte0]: 51
1765 22:53:32.143150 [Byte1]: 51
1766 22:53:32.147913
1767 22:53:32.148434 Set Vref, RX VrefLevel [Byte0]: 52
1768 22:53:32.150813 [Byte1]: 52
1769 22:53:32.155637
1770 22:53:32.156177 Set Vref, RX VrefLevel [Byte0]: 53
1771 22:53:32.159114 [Byte1]: 53
1772 22:53:32.163293
1773 22:53:32.163814 Set Vref, RX VrefLevel [Byte0]: 54
1774 22:53:32.166540 [Byte1]: 54
1775 22:53:32.170639
1776 22:53:32.171179 Set Vref, RX VrefLevel [Byte0]: 55
1777 22:53:32.174579 [Byte1]: 55
1778 22:53:32.178187
1779 22:53:32.178709 Set Vref, RX VrefLevel [Byte0]: 56
1780 22:53:32.182113 [Byte1]: 56
1781 22:53:32.186112
1782 22:53:32.186633 Set Vref, RX VrefLevel [Byte0]: 57
1783 22:53:32.189402 [Byte1]: 57
1784 22:53:32.193871
1785 22:53:32.194397 Set Vref, RX VrefLevel [Byte0]: 58
1786 22:53:32.197539 [Byte1]: 58
1787 22:53:32.201467
1788 22:53:32.202071 Set Vref, RX VrefLevel [Byte0]: 59
1789 22:53:32.204530 [Byte1]: 59
1790 22:53:32.209044
1791 22:53:32.209525 Set Vref, RX VrefLevel [Byte0]: 60
1792 22:53:32.211798 [Byte1]: 60
1793 22:53:32.216087
1794 22:53:32.216508 Set Vref, RX VrefLevel [Byte0]: 61
1795 22:53:32.220319 [Byte1]: 61
1796 22:53:32.224081
1797 22:53:32.224527 Set Vref, RX VrefLevel [Byte0]: 62
1798 22:53:32.227804 [Byte1]: 62
1799 22:53:32.231515
1800 22:53:32.231946 Set Vref, RX VrefLevel [Byte0]: 63
1801 22:53:32.235674 [Byte1]: 63
1802 22:53:32.239466
1803 22:53:32.240009 Set Vref, RX VrefLevel [Byte0]: 64
1804 22:53:32.242983 [Byte1]: 64
1805 22:53:32.247618
1806 22:53:32.248142 Set Vref, RX VrefLevel [Byte0]: 65
1807 22:53:32.250340 [Byte1]: 65
1808 22:53:32.254943
1809 22:53:32.255498 Set Vref, RX VrefLevel [Byte0]: 66
1810 22:53:32.257876 [Byte1]: 66
1811 22:53:32.262400
1812 22:53:32.262978 Set Vref, RX VrefLevel [Byte0]: 67
1813 22:53:32.265347 [Byte1]: 67
1814 22:53:32.270249
1815 22:53:32.270737 Set Vref, RX VrefLevel [Byte0]: 68
1816 22:53:32.273304 [Byte1]: 68
1817 22:53:32.277739
1818 22:53:32.278259 Set Vref, RX VrefLevel [Byte0]: 69
1819 22:53:32.280680 [Byte1]: 69
1820 22:53:32.285702
1821 22:53:32.286226 Set Vref, RX VrefLevel [Byte0]: 70
1822 22:53:32.288307 [Byte1]: 70
1823 22:53:32.293298
1824 22:53:32.293837 Set Vref, RX VrefLevel [Byte0]: 71
1825 22:53:32.296086 [Byte1]: 71
1826 22:53:32.300902
1827 22:53:32.301512 Set Vref, RX VrefLevel [Byte0]: 72
1828 22:53:32.303934 [Byte1]: 72
1829 22:53:32.308485
1830 22:53:32.308915 Set Vref, RX VrefLevel [Byte0]: 73
1831 22:53:32.311841 [Byte1]: 73
1832 22:53:32.315913
1833 22:53:32.316351 Set Vref, RX VrefLevel [Byte0]: 74
1834 22:53:32.319439 [Byte1]: 74
1835 22:53:32.324001
1836 22:53:32.324562 Set Vref, RX VrefLevel [Byte0]: 75
1837 22:53:32.326598 [Byte1]: 75
1838 22:53:32.330970
1839 22:53:32.331409 Set Vref, RX VrefLevel [Byte0]: 76
1840 22:53:32.334496 [Byte1]: 76
1841 22:53:32.338770
1842 22:53:32.339350 Final RX Vref Byte 0 = 63 to rank0
1843 22:53:32.341959 Final RX Vref Byte 1 = 58 to rank0
1844 22:53:32.345764 Final RX Vref Byte 0 = 63 to rank1
1845 22:53:32.348677 Final RX Vref Byte 1 = 58 to rank1==
1846 22:53:32.352297 Dram Type= 6, Freq= 0, CH_1, rank 0
1847 22:53:32.355216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 22:53:32.359349 ==
1849 22:53:32.359791 DQS Delay:
1850 22:53:32.360271 DQS0 = 0, DQS1 = 0
1851 22:53:32.362750 DQM Delay:
1852 22:53:32.363189 DQM0 = 82, DQM1 = 73
1853 22:53:32.365841 DQ Delay:
1854 22:53:32.366333 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1855 22:53:32.369048 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1856 22:53:32.372078 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1857 22:53:32.376029 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1858 22:53:32.376563
1859 22:53:32.379087
1860 22:53:32.385733 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c01, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1861 22:53:32.388926 CH1 RK0: MR19=606, MR18=2C01
1862 22:53:32.395748 CH1_RK0: MR19=0x606, MR18=0x2C01, DQSOSC=398, MR23=63, INC=93, DEC=62
1863 22:53:32.396218
1864 22:53:32.399136 ----->DramcWriteLeveling(PI) begin...
1865 22:53:32.399597 ==
1866 22:53:32.402745 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 22:53:32.405622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 22:53:32.406050 ==
1869 22:53:32.409586 Write leveling (Byte 0): 28 => 28
1870 22:53:32.412611 Write leveling (Byte 1): 30 => 30
1871 22:53:32.415840 DramcWriteLeveling(PI) end<-----
1872 22:53:32.416294
1873 22:53:32.416949 ==
1874 22:53:32.419057 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 22:53:32.422736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 22:53:32.423182 ==
1877 22:53:32.425525 [Gating] SW mode calibration
1878 22:53:32.432630 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1879 22:53:32.436112 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1880 22:53:32.443269 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1881 22:53:32.446183 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1882 22:53:32.449526 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:53:32.456309 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:53:32.459347 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 22:53:32.463039 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 22:53:32.469638 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:53:32.473173 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:53:32.476555 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:53:32.483211 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:53:32.486476 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:53:32.490005 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:53:32.496889 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:53:32.499839 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1894 22:53:32.503027 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:53:32.509762 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:53:32.513036 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1897 22:53:32.516137 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1898 22:53:32.519990 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1899 22:53:32.526044 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 22:53:32.529522 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 22:53:32.533294 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 22:53:32.540112 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 22:53:32.542962 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:53:32.546847 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:53:32.553287 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
1906 22:53:32.556391 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1907 22:53:32.559887 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 22:53:32.566861 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 22:53:32.569583 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1910 22:53:32.573439 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 22:53:32.580248 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 22:53:32.583550 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1913 22:53:32.586491 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 0)
1914 22:53:32.590115 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1915 22:53:32.597407 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 22:53:32.600592 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 22:53:32.603114 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 22:53:32.610327 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 22:53:32.614070 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 22:53:32.616938 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 22:53:32.624141 0 11 4 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 0)
1922 22:53:32.627291 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1923 22:53:32.629989 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 22:53:32.636877 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 22:53:32.640493 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 22:53:32.643389 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 22:53:32.650144 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 22:53:32.653660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 22:53:32.656818 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1930 22:53:32.660070 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 22:53:32.667132 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 22:53:32.670606 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 22:53:32.673697 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 22:53:32.680969 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 22:53:32.684267 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 22:53:32.687343 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 22:53:32.693985 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 22:53:32.697196 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 22:53:32.701251 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 22:53:32.707254 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 22:53:32.711404 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 22:53:32.714113 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 22:53:32.717390 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 22:53:32.724149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 22:53:32.727627 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1946 22:53:32.730491 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 22:53:32.734116 Total UI for P1: 0, mck2ui 16
1948 22:53:32.737473 best dqsien dly found for B0: ( 0, 14, 4)
1949 22:53:32.741322 Total UI for P1: 0, mck2ui 16
1950 22:53:32.743832 best dqsien dly found for B1: ( 0, 14, 4)
1951 22:53:32.747732 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1952 22:53:32.750944 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1953 22:53:32.751370
1954 22:53:32.758025 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1955 22:53:32.761403 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1956 22:53:32.761831 [Gating] SW calibration Done
1957 22:53:32.762171 ==
1958 22:53:32.764595 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 22:53:32.771307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 22:53:32.771740 ==
1961 22:53:32.772078 RX Vref Scan: 0
1962 22:53:32.772391
1963 22:53:32.775165 RX Vref 0 -> 0, step: 1
1964 22:53:32.775687
1965 22:53:32.778186 RX Delay -130 -> 252, step: 16
1966 22:53:32.781631 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1967 22:53:32.784518 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1968 22:53:32.788285 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1969 22:53:32.791574 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1970 22:53:32.797787 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1971 22:53:32.801537 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1972 22:53:32.804513 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1973 22:53:32.808851 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1974 22:53:32.811626 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1975 22:53:32.818056 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1976 22:53:32.821532 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1977 22:53:32.825157 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1978 22:53:32.828056 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1979 22:53:32.831386 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1980 22:53:32.838155 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1981 22:53:32.841172 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1982 22:53:32.841765 ==
1983 22:53:32.844733 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 22:53:32.848180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 22:53:32.848760 ==
1986 22:53:32.851582 DQS Delay:
1987 22:53:32.852003 DQS0 = 0, DQS1 = 0
1988 22:53:32.852337 DQM Delay:
1989 22:53:32.854997 DQM0 = 82, DQM1 = 77
1990 22:53:32.855419 DQ Delay:
1991 22:53:32.857985 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1992 22:53:32.862049 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1993 22:53:32.864753 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1994 22:53:32.868376 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1995 22:53:32.868835
1996 22:53:32.869166
1997 22:53:32.869514 ==
1998 22:53:32.871585 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 22:53:32.874996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 22:53:32.878424 ==
2001 22:53:32.878841
2002 22:53:32.879167
2003 22:53:32.879472 TX Vref Scan disable
2004 22:53:32.882348 == TX Byte 0 ==
2005 22:53:32.885321 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2006 22:53:32.888123 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2007 22:53:32.892607 == TX Byte 1 ==
2008 22:53:32.895524 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2009 22:53:32.898757 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2010 22:53:32.899269 ==
2011 22:53:32.901567 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 22:53:32.908912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 22:53:32.909487 ==
2014 22:53:32.920735 TX Vref=22, minBit 7, minWin=27, winSum=445
2015 22:53:32.923715 TX Vref=24, minBit 6, minWin=27, winSum=446
2016 22:53:32.927176 TX Vref=26, minBit 0, minWin=27, winSum=451
2017 22:53:32.931196 TX Vref=28, minBit 15, minWin=27, winSum=450
2018 22:53:32.934569 TX Vref=30, minBit 15, minWin=27, winSum=452
2019 22:53:32.939307 TX Vref=32, minBit 1, minWin=28, winSum=456
2020 22:53:32.944353 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 32
2021 22:53:32.944872
2022 22:53:32.947616 Final TX Range 1 Vref 32
2023 22:53:32.948038
2024 22:53:32.948367 ==
2025 22:53:32.950711 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 22:53:32.954173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 22:53:32.954598 ==
2028 22:53:32.954932
2029 22:53:32.955245
2030 22:53:32.957666 TX Vref Scan disable
2031 22:53:32.960966 == TX Byte 0 ==
2032 22:53:32.964111 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2033 22:53:32.967699 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2034 22:53:32.971659 == TX Byte 1 ==
2035 22:53:32.974098 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2036 22:53:32.978154 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2037 22:53:32.978675
2038 22:53:32.981327 [DATLAT]
2039 22:53:32.981862 Freq=800, CH1 RK1
2040 22:53:32.982206
2041 22:53:32.984588 DATLAT Default: 0xa
2042 22:53:32.985109 0, 0xFFFF, sum = 0
2043 22:53:32.987556 1, 0xFFFF, sum = 0
2044 22:53:32.988051 2, 0xFFFF, sum = 0
2045 22:53:32.991435 3, 0xFFFF, sum = 0
2046 22:53:32.991958 4, 0xFFFF, sum = 0
2047 22:53:32.994612 5, 0xFFFF, sum = 0
2048 22:53:32.995042 6, 0xFFFF, sum = 0
2049 22:53:32.998039 7, 0xFFFF, sum = 0
2050 22:53:32.998574 8, 0xFFFF, sum = 0
2051 22:53:33.002006 9, 0x0, sum = 1
2052 22:53:33.002530 10, 0x0, sum = 2
2053 22:53:33.004648 11, 0x0, sum = 3
2054 22:53:33.005075 12, 0x0, sum = 4
2055 22:53:33.008437 best_step = 10
2056 22:53:33.008961
2057 22:53:33.009337 ==
2058 22:53:33.011501 Dram Type= 6, Freq= 0, CH_1, rank 1
2059 22:53:33.014358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2060 22:53:33.014801 ==
2061 22:53:33.015138 RX Vref Scan: 0
2062 22:53:33.017954
2063 22:53:33.018373 RX Vref 0 -> 0, step: 1
2064 22:53:33.018708
2065 22:53:33.021145 RX Delay -111 -> 252, step: 8
2066 22:53:33.024564 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2067 22:53:33.031819 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2068 22:53:33.034831 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2069 22:53:33.038075 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2070 22:53:33.041765 iDelay=201, Bit 4, Center 76 (-39 ~ 192) 232
2071 22:53:33.044759 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2072 22:53:33.051753 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2073 22:53:33.055549 iDelay=201, Bit 7, Center 76 (-39 ~ 192) 232
2074 22:53:33.058688 iDelay=201, Bit 8, Center 68 (-47 ~ 184) 232
2075 22:53:33.062598 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2076 22:53:33.065044 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2077 22:53:33.072096 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2078 22:53:33.075244 iDelay=201, Bit 12, Center 84 (-31 ~ 200) 232
2079 22:53:33.078432 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2080 22:53:33.081873 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2081 22:53:33.085375 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2082 22:53:33.085899 ==
2083 22:53:33.088679 Dram Type= 6, Freq= 0, CH_1, rank 1
2084 22:53:33.095708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2085 22:53:33.096197 ==
2086 22:53:33.096536 DQS Delay:
2087 22:53:33.098791 DQS0 = 0, DQS1 = 0
2088 22:53:33.099214 DQM Delay:
2089 22:53:33.099548 DQM0 = 79, DQM1 = 76
2090 22:53:33.102506 DQ Delay:
2091 22:53:33.105342 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2092 22:53:33.108857 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2093 22:53:33.112666 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2094 22:53:33.115246 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2095 22:53:33.115672
2096 22:53:33.116004
2097 22:53:33.121691 [DQSOSCAuto] RK1, (LSB)MR18= 0x232f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
2098 22:53:33.125382 CH1 RK1: MR19=606, MR18=232F
2099 22:53:33.132212 CH1_RK1: MR19=0x606, MR18=0x232F, DQSOSC=397, MR23=63, INC=93, DEC=62
2100 22:53:33.135910 [RxdqsGatingPostProcess] freq 800
2101 22:53:33.139259 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2102 22:53:33.142147 Pre-setting of DQS Precalculation
2103 22:53:33.148397 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2104 22:53:33.155259 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2105 22:53:33.162410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2106 22:53:33.162832
2107 22:53:33.163167
2108 22:53:33.165278 [Calibration Summary] 1600 Mbps
2109 22:53:33.165703 CH 0, Rank 0
2110 22:53:33.168960 SW Impedance : PASS
2111 22:53:33.171998 DUTY Scan : NO K
2112 22:53:33.172425 ZQ Calibration : PASS
2113 22:53:33.175439 Jitter Meter : NO K
2114 22:53:33.178764 CBT Training : PASS
2115 22:53:33.179294 Write leveling : PASS
2116 22:53:33.182041 RX DQS gating : PASS
2117 22:53:33.182465 RX DQ/DQS(RDDQC) : PASS
2118 22:53:33.185431 TX DQ/DQS : PASS
2119 22:53:33.188471 RX DATLAT : PASS
2120 22:53:33.188888 RX DQ/DQS(Engine): PASS
2121 22:53:33.192396 TX OE : NO K
2122 22:53:33.192854 All Pass.
2123 22:53:33.193187
2124 22:53:33.195548 CH 0, Rank 1
2125 22:53:33.195968 SW Impedance : PASS
2126 22:53:33.198877 DUTY Scan : NO K
2127 22:53:33.202457 ZQ Calibration : PASS
2128 22:53:33.202974 Jitter Meter : NO K
2129 22:53:33.205126 CBT Training : PASS
2130 22:53:33.208936 Write leveling : PASS
2131 22:53:33.209394 RX DQS gating : PASS
2132 22:53:33.212476 RX DQ/DQS(RDDQC) : PASS
2133 22:53:33.215369 TX DQ/DQS : PASS
2134 22:53:33.215795 RX DATLAT : PASS
2135 22:53:33.219084 RX DQ/DQS(Engine): PASS
2136 22:53:33.219505 TX OE : NO K
2137 22:53:33.222028 All Pass.
2138 22:53:33.222451
2139 22:53:33.222786 CH 1, Rank 0
2140 22:53:33.225577 SW Impedance : PASS
2141 22:53:33.225997 DUTY Scan : NO K
2142 22:53:33.228949 ZQ Calibration : PASS
2143 22:53:33.232506 Jitter Meter : NO K
2144 22:53:33.232928 CBT Training : PASS
2145 22:53:33.236020 Write leveling : PASS
2146 22:53:33.239386 RX DQS gating : PASS
2147 22:53:33.239916 RX DQ/DQS(RDDQC) : PASS
2148 22:53:33.242307 TX DQ/DQS : PASS
2149 22:53:33.245430 RX DATLAT : PASS
2150 22:53:33.245855 RX DQ/DQS(Engine): PASS
2151 22:53:33.249204 TX OE : NO K
2152 22:53:33.249679 All Pass.
2153 22:53:33.250015
2154 22:53:33.252598 CH 1, Rank 1
2155 22:53:33.253017 SW Impedance : PASS
2156 22:53:33.255859 DUTY Scan : NO K
2157 22:53:33.256279 ZQ Calibration : PASS
2158 22:53:33.259480 Jitter Meter : NO K
2159 22:53:33.262344 CBT Training : PASS
2160 22:53:33.262764 Write leveling : PASS
2161 22:53:33.266199 RX DQS gating : PASS
2162 22:53:33.269023 RX DQ/DQS(RDDQC) : PASS
2163 22:53:33.269491 TX DQ/DQS : PASS
2164 22:53:33.272605 RX DATLAT : PASS
2165 22:53:33.276272 RX DQ/DQS(Engine): PASS
2166 22:53:33.276795 TX OE : NO K
2167 22:53:33.279491 All Pass.
2168 22:53:33.280024
2169 22:53:33.280357 DramC Write-DBI off
2170 22:53:33.282346 PER_BANK_REFRESH: Hybrid Mode
2171 22:53:33.282769 TX_TRACKING: ON
2172 22:53:33.285711 [GetDramInforAfterCalByMRR] Vendor 6.
2173 22:53:33.292907 [GetDramInforAfterCalByMRR] Revision 606.
2174 22:53:33.296099 [GetDramInforAfterCalByMRR] Revision 2 0.
2175 22:53:33.296646 MR0 0x3b3b
2176 22:53:33.296996 MR8 0x5151
2177 22:53:33.299232 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 22:53:33.299652
2179 22:53:33.302489 MR0 0x3b3b
2180 22:53:33.302920 MR8 0x5151
2181 22:53:33.306058 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 22:53:33.306487
2183 22:53:33.315987 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2184 22:53:33.319257 [FAST_K] Save calibration result to emmc
2185 22:53:33.322712 [FAST_K] Save calibration result to emmc
2186 22:53:33.326050 dram_init: config_dvfs: 1
2187 22:53:33.329353 dramc_set_vcore_voltage set vcore to 662500
2188 22:53:33.329775 Read voltage for 1200, 2
2189 22:53:33.333062 Vio18 = 0
2190 22:53:33.333513 Vcore = 662500
2191 22:53:33.333847 Vdram = 0
2192 22:53:33.336464 Vddq = 0
2193 22:53:33.336936 Vmddr = 0
2194 22:53:33.339295 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2195 22:53:33.346278 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2196 22:53:33.349776 MEM_TYPE=3, freq_sel=15
2197 22:53:33.352805 sv_algorithm_assistance_LP4_1600
2198 22:53:33.356311 ============ PULL DRAM RESETB DOWN ============
2199 22:53:33.359434 ========== PULL DRAM RESETB DOWN end =========
2200 22:53:33.366357 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2201 22:53:33.369632 ===================================
2202 22:53:33.370051 LPDDR4 DRAM CONFIGURATION
2203 22:53:33.373807 ===================================
2204 22:53:33.376558 EX_ROW_EN[0] = 0x0
2205 22:53:33.377083 EX_ROW_EN[1] = 0x0
2206 22:53:33.380032 LP4Y_EN = 0x0
2207 22:53:33.380566 WORK_FSP = 0x0
2208 22:53:33.383434 WL = 0x4
2209 22:53:33.383957 RL = 0x4
2210 22:53:33.386854 BL = 0x2
2211 22:53:33.387380 RPST = 0x0
2212 22:53:33.390034 RD_PRE = 0x0
2213 22:53:33.390464 WR_PRE = 0x1
2214 22:53:33.393570 WR_PST = 0x0
2215 22:53:33.396410 DBI_WR = 0x0
2216 22:53:33.396939 DBI_RD = 0x0
2217 22:53:33.399416 OTF = 0x1
2218 22:53:33.402915 ===================================
2219 22:53:33.403337 ===================================
2220 22:53:33.406669 ANA top config
2221 22:53:33.409761 ===================================
2222 22:53:33.413096 DLL_ASYNC_EN = 0
2223 22:53:33.413618 ALL_SLAVE_EN = 0
2224 22:53:33.416822 NEW_RANK_MODE = 1
2225 22:53:33.419772 DLL_IDLE_MODE = 1
2226 22:53:33.423473 LP45_APHY_COMB_EN = 1
2227 22:53:33.424059 TX_ODT_DIS = 1
2228 22:53:33.426677 NEW_8X_MODE = 1
2229 22:53:33.431461 ===================================
2230 22:53:33.433580 ===================================
2231 22:53:33.436746 data_rate = 2400
2232 22:53:33.440736 CKR = 1
2233 22:53:33.443578 DQ_P2S_RATIO = 8
2234 22:53:33.446423 ===================================
2235 22:53:33.450445 CA_P2S_RATIO = 8
2236 22:53:33.450860 DQ_CA_OPEN = 0
2237 22:53:33.453162 DQ_SEMI_OPEN = 0
2238 22:53:33.456796 CA_SEMI_OPEN = 0
2239 22:53:33.460611 CA_FULL_RATE = 0
2240 22:53:33.463554 DQ_CKDIV4_EN = 0
2241 22:53:33.463975 CA_CKDIV4_EN = 0
2242 22:53:33.467330 CA_PREDIV_EN = 0
2243 22:53:33.469932 PH8_DLY = 17
2244 22:53:33.473643 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2245 22:53:33.477438 DQ_AAMCK_DIV = 4
2246 22:53:33.480382 CA_AAMCK_DIV = 4
2247 22:53:33.480899 CA_ADMCK_DIV = 4
2248 22:53:33.484502 DQ_TRACK_CA_EN = 0
2249 22:53:33.487243 CA_PICK = 1200
2250 22:53:33.490758 CA_MCKIO = 1200
2251 22:53:33.494191 MCKIO_SEMI = 0
2252 22:53:33.497994 PLL_FREQ = 2366
2253 22:53:33.500915 DQ_UI_PI_RATIO = 32
2254 22:53:33.501484 CA_UI_PI_RATIO = 0
2255 22:53:33.503871 ===================================
2256 22:53:33.507474 ===================================
2257 22:53:33.510576 memory_type:LPDDR4
2258 22:53:33.513875 GP_NUM : 10
2259 22:53:33.514296 SRAM_EN : 1
2260 22:53:33.516978 MD32_EN : 0
2261 22:53:33.520323 ===================================
2262 22:53:33.524254 [ANA_INIT] >>>>>>>>>>>>>>
2263 22:53:33.524676 <<<<<< [CONFIGURE PHASE]: ANA_TX
2264 22:53:33.527329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2265 22:53:33.530581 ===================================
2266 22:53:33.534152 data_rate = 2400,PCW = 0X5b00
2267 22:53:33.537279 ===================================
2268 22:53:33.540468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2269 22:53:33.547425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 22:53:33.554244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 22:53:33.557770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2272 22:53:33.560598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2273 22:53:33.564485 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2274 22:53:33.567536 [ANA_INIT] flow start
2275 22:53:33.567954 [ANA_INIT] PLL >>>>>>>>
2276 22:53:33.571078 [ANA_INIT] PLL <<<<<<<<
2277 22:53:33.573976 [ANA_INIT] MIDPI >>>>>>>>
2278 22:53:33.574415 [ANA_INIT] MIDPI <<<<<<<<
2279 22:53:33.578202 [ANA_INIT] DLL >>>>>>>>
2280 22:53:33.580976 [ANA_INIT] DLL <<<<<<<<
2281 22:53:33.581425 [ANA_INIT] flow end
2282 22:53:33.587355 ============ LP4 DIFF to SE enter ============
2283 22:53:33.591882 ============ LP4 DIFF to SE exit ============
2284 22:53:33.592414 [ANA_INIT] <<<<<<<<<<<<<
2285 22:53:33.594471 [Flow] Enable top DCM control >>>>>
2286 22:53:33.597688 [Flow] Enable top DCM control <<<<<
2287 22:53:33.601402 Enable DLL master slave shuffle
2288 22:53:33.608019 ==============================================================
2289 22:53:33.608446 Gating Mode config
2290 22:53:33.614276 ==============================================================
2291 22:53:33.617592 Config description:
2292 22:53:33.628087 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2293 22:53:33.634863 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2294 22:53:33.638588 SELPH_MODE 0: By rank 1: By Phase
2295 22:53:33.645164 ==============================================================
2296 22:53:33.647978 GAT_TRACK_EN = 1
2297 22:53:33.648398 RX_GATING_MODE = 2
2298 22:53:33.651633 RX_GATING_TRACK_MODE = 2
2299 22:53:33.655103 SELPH_MODE = 1
2300 22:53:33.658233 PICG_EARLY_EN = 1
2301 22:53:33.661771 VALID_LAT_VALUE = 1
2302 22:53:33.668733 ==============================================================
2303 22:53:33.671757 Enter into Gating configuration >>>>
2304 22:53:33.675470 Exit from Gating configuration <<<<
2305 22:53:33.678044 Enter into DVFS_PRE_config >>>>>
2306 22:53:33.688028 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2307 22:53:33.691978 Exit from DVFS_PRE_config <<<<<
2308 22:53:33.695023 Enter into PICG configuration >>>>
2309 22:53:33.698503 Exit from PICG configuration <<<<
2310 22:53:33.699017 [RX_INPUT] configuration >>>>>
2311 22:53:33.701913 [RX_INPUT] configuration <<<<<
2312 22:53:33.708916 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2313 22:53:33.711928 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2314 22:53:33.718538 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 22:53:33.725018 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 22:53:33.731585 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 22:53:33.738420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 22:53:33.742164 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2319 22:53:33.745367 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2320 22:53:33.748999 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2321 22:53:33.755283 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2322 22:53:33.758935 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2323 22:53:33.762099 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 22:53:33.765563 ===================================
2325 22:53:33.768911 LPDDR4 DRAM CONFIGURATION
2326 22:53:33.772395 ===================================
2327 22:53:33.775418 EX_ROW_EN[0] = 0x0
2328 22:53:33.775835 EX_ROW_EN[1] = 0x0
2329 22:53:33.779163 LP4Y_EN = 0x0
2330 22:53:33.779655 WORK_FSP = 0x0
2331 22:53:33.782317 WL = 0x4
2332 22:53:33.782734 RL = 0x4
2333 22:53:33.785549 BL = 0x2
2334 22:53:33.786039 RPST = 0x0
2335 22:53:33.789145 RD_PRE = 0x0
2336 22:53:33.789603 WR_PRE = 0x1
2337 22:53:33.792284 WR_PST = 0x0
2338 22:53:33.792701 DBI_WR = 0x0
2339 22:53:33.796459 DBI_RD = 0x0
2340 22:53:33.796982 OTF = 0x1
2341 22:53:33.799524 ===================================
2342 22:53:33.802786 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2343 22:53:33.809393 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2344 22:53:33.812374 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2345 22:53:33.815937 ===================================
2346 22:53:33.819205 LPDDR4 DRAM CONFIGURATION
2347 22:53:33.822468 ===================================
2348 22:53:33.822893 EX_ROW_EN[0] = 0x10
2349 22:53:33.826034 EX_ROW_EN[1] = 0x0
2350 22:53:33.826453 LP4Y_EN = 0x0
2351 22:53:33.829010 WORK_FSP = 0x0
2352 22:53:33.829457 WL = 0x4
2353 22:53:33.832764 RL = 0x4
2354 22:53:33.833458 BL = 0x2
2355 22:53:33.836306 RPST = 0x0
2356 22:53:33.836841 RD_PRE = 0x0
2357 22:53:33.839979 WR_PRE = 0x1
2358 22:53:33.840499 WR_PST = 0x0
2359 22:53:33.842477 DBI_WR = 0x0
2360 22:53:33.846038 DBI_RD = 0x0
2361 22:53:33.846455 OTF = 0x1
2362 22:53:33.849241 ===================================
2363 22:53:33.855793 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2364 22:53:33.856274 ==
2365 22:53:33.859485 Dram Type= 6, Freq= 0, CH_0, rank 0
2366 22:53:33.863124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 22:53:33.863543 ==
2368 22:53:33.865664 [Duty_Offset_Calibration]
2369 22:53:33.866077 B0:2 B1:-1 CA:1
2370 22:53:33.866403
2371 22:53:33.869404 [DutyScan_Calibration_Flow] k_type=0
2372 22:53:33.879207
2373 22:53:33.879675 ==CLK 0==
2374 22:53:33.883127 Final CLK duty delay cell = -4
2375 22:53:33.885873 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2376 22:53:33.889265 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2377 22:53:33.893345 [-4] AVG Duty = 4953%(X100)
2378 22:53:33.893865
2379 22:53:33.896197 CH0 CLK Duty spec in!! Max-Min= 156%
2380 22:53:33.899946 [DutyScan_Calibration_Flow] ====Done====
2381 22:53:33.900466
2382 22:53:33.902659 [DutyScan_Calibration_Flow] k_type=1
2383 22:53:33.918331
2384 22:53:33.918815 ==DQS 0 ==
2385 22:53:33.921523 Final DQS duty delay cell = 0
2386 22:53:33.925278 [0] MAX Duty = 5125%(X100), DQS PI = 48
2387 22:53:33.928148 [0] MIN Duty = 5000%(X100), DQS PI = 12
2388 22:53:33.928713 [0] AVG Duty = 5062%(X100)
2389 22:53:33.931626
2390 22:53:33.932038 ==DQS 1 ==
2391 22:53:33.934729 Final DQS duty delay cell = -4
2392 22:53:33.938339 [-4] MAX Duty = 5093%(X100), DQS PI = 6
2393 22:53:33.941399 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2394 22:53:33.945307 [-4] AVG Duty = 5046%(X100)
2395 22:53:33.945721
2396 22:53:33.948719 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2397 22:53:33.949300
2398 22:53:33.951312 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2399 22:53:33.955210 [DutyScan_Calibration_Flow] ====Done====
2400 22:53:33.955907
2401 22:53:33.958561 [DutyScan_Calibration_Flow] k_type=3
2402 22:53:33.975583
2403 22:53:33.976244 ==DQM 0 ==
2404 22:53:33.978742 Final DQM duty delay cell = 0
2405 22:53:33.981534 [0] MAX Duty = 5000%(X100), DQS PI = 56
2406 22:53:33.984948 [0] MIN Duty = 4907%(X100), DQS PI = 2
2407 22:53:33.985416 [0] AVG Duty = 4953%(X100)
2408 22:53:33.988359
2409 22:53:33.988879 ==DQM 1 ==
2410 22:53:33.991602 Final DQM duty delay cell = 0
2411 22:53:33.995087 [0] MAX Duty = 5124%(X100), DQS PI = 32
2412 22:53:33.998479 [0] MIN Duty = 5000%(X100), DQS PI = 10
2413 22:53:33.998967 [0] AVG Duty = 5062%(X100)
2414 22:53:33.999297
2415 22:53:34.002096 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2416 22:53:34.005271
2417 22:53:34.008386 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2418 22:53:34.011955 [DutyScan_Calibration_Flow] ====Done====
2419 22:53:34.012516
2420 22:53:34.015012 [DutyScan_Calibration_Flow] k_type=2
2421 22:53:34.030972
2422 22:53:34.031659 ==DQ 0 ==
2423 22:53:34.033920 Final DQ duty delay cell = -4
2424 22:53:34.037391 [-4] MAX Duty = 5031%(X100), DQS PI = 44
2425 22:53:34.040661 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2426 22:53:34.044064 [-4] AVG Duty = 4937%(X100)
2427 22:53:34.044519
2428 22:53:34.044847 ==DQ 1 ==
2429 22:53:34.047719 Final DQ duty delay cell = 0
2430 22:53:34.050298 [0] MAX Duty = 5031%(X100), DQS PI = 18
2431 22:53:34.053922 [0] MIN Duty = 4907%(X100), DQS PI = 46
2432 22:53:34.054347 [0] AVG Duty = 4969%(X100)
2433 22:53:34.056929
2434 22:53:34.060798 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2435 22:53:34.061269
2436 22:53:34.064009 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2437 22:53:34.067299 [DutyScan_Calibration_Flow] ====Done====
2438 22:53:34.067719 ==
2439 22:53:34.071219 Dram Type= 6, Freq= 0, CH_1, rank 0
2440 22:53:34.074187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 22:53:34.074610 ==
2442 22:53:34.077474 [Duty_Offset_Calibration]
2443 22:53:34.077952 B0:1 B1:1 CA:2
2444 22:53:34.078290
2445 22:53:34.080471 [DutyScan_Calibration_Flow] k_type=0
2446 22:53:34.090586
2447 22:53:34.091071 ==CLK 0==
2448 22:53:34.094322 Final CLK duty delay cell = 0
2449 22:53:34.097499 [0] MAX Duty = 5156%(X100), DQS PI = 24
2450 22:53:34.101025 [0] MIN Duty = 4969%(X100), DQS PI = 42
2451 22:53:34.101554 [0] AVG Duty = 5062%(X100)
2452 22:53:34.104181
2453 22:53:34.104596 CH1 CLK Duty spec in!! Max-Min= 187%
2454 22:53:34.111313 [DutyScan_Calibration_Flow] ====Done====
2455 22:53:34.111738
2456 22:53:34.114000 [DutyScan_Calibration_Flow] k_type=1
2457 22:53:34.130648
2458 22:53:34.131177 ==DQS 0 ==
2459 22:53:34.133933 Final DQS duty delay cell = 0
2460 22:53:34.136862 [0] MAX Duty = 5031%(X100), DQS PI = 18
2461 22:53:34.140704 [0] MIN Duty = 4813%(X100), DQS PI = 50
2462 22:53:34.141123 [0] AVG Duty = 4922%(X100)
2463 22:53:34.143555
2464 22:53:34.143971 ==DQS 1 ==
2465 22:53:34.147414 Final DQS duty delay cell = 0
2466 22:53:34.150377 [0] MAX Duty = 5062%(X100), DQS PI = 36
2467 22:53:34.154116 [0] MIN Duty = 4907%(X100), DQS PI = 32
2468 22:53:34.154536 [0] AVG Duty = 4984%(X100)
2469 22:53:34.154867
2470 22:53:34.160575 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2471 22:53:34.161093
2472 22:53:34.164083 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2473 22:53:34.167225 [DutyScan_Calibration_Flow] ====Done====
2474 22:53:34.167657
2475 22:53:34.170601 [DutyScan_Calibration_Flow] k_type=3
2476 22:53:34.186810
2477 22:53:34.187302 ==DQM 0 ==
2478 22:53:34.190051 Final DQM duty delay cell = 0
2479 22:53:34.193805 [0] MAX Duty = 5093%(X100), DQS PI = 18
2480 22:53:34.196936 [0] MIN Duty = 4875%(X100), DQS PI = 48
2481 22:53:34.197382 [0] AVG Duty = 4984%(X100)
2482 22:53:34.200400
2483 22:53:34.200840 ==DQM 1 ==
2484 22:53:34.204141 Final DQM duty delay cell = 0
2485 22:53:34.207950 [0] MAX Duty = 5125%(X100), DQS PI = 0
2486 22:53:34.210488 [0] MIN Duty = 4938%(X100), DQS PI = 22
2487 22:53:34.210930 [0] AVG Duty = 5031%(X100)
2488 22:53:34.211264
2489 22:53:34.216979 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2490 22:53:34.217442
2491 22:53:34.220362 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2492 22:53:34.223676 [DutyScan_Calibration_Flow] ====Done====
2493 22:53:34.224112
2494 22:53:34.226919 [DutyScan_Calibration_Flow] k_type=2
2495 22:53:34.243115
2496 22:53:34.243607 ==DQ 0 ==
2497 22:53:34.246676 Final DQ duty delay cell = 0
2498 22:53:34.250143 [0] MAX Duty = 5093%(X100), DQS PI = 18
2499 22:53:34.253753 [0] MIN Duty = 4907%(X100), DQS PI = 50
2500 22:53:34.254178 [0] AVG Duty = 5000%(X100)
2501 22:53:34.254512
2502 22:53:34.256951 ==DQ 1 ==
2503 22:53:34.260114 Final DQ duty delay cell = 0
2504 22:53:34.263959 [0] MAX Duty = 5093%(X100), DQS PI = 10
2505 22:53:34.266851 [0] MIN Duty = 5000%(X100), DQS PI = 2
2506 22:53:34.267274 [0] AVG Duty = 5046%(X100)
2507 22:53:34.267608
2508 22:53:34.270384 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2509 22:53:34.270805
2510 22:53:34.273506 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2511 22:53:34.277423 [DutyScan_Calibration_Flow] ====Done====
2512 22:53:34.282218 nWR fixed to 30
2513 22:53:34.285771 [ModeRegInit_LP4] CH0 RK0
2514 22:53:34.286299 [ModeRegInit_LP4] CH0 RK1
2515 22:53:34.289052 [ModeRegInit_LP4] CH1 RK0
2516 22:53:34.292243 [ModeRegInit_LP4] CH1 RK1
2517 22:53:34.292664 match AC timing 7
2518 22:53:34.299103 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2519 22:53:34.302245 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2520 22:53:34.305907 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2521 22:53:34.312240 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2522 22:53:34.316391 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2523 22:53:34.316918 ==
2524 22:53:34.318911 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 22:53:34.322614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 22:53:34.323038 ==
2527 22:53:34.328921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2528 22:53:34.335592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2529 22:53:34.343567 [CA 0] Center 40 (10~71) winsize 62
2530 22:53:34.346322 [CA 1] Center 39 (9~70) winsize 62
2531 22:53:34.350145 [CA 2] Center 36 (6~67) winsize 62
2532 22:53:34.353903 [CA 3] Center 36 (6~66) winsize 61
2533 22:53:34.357064 [CA 4] Center 34 (4~65) winsize 62
2534 22:53:34.360023 [CA 5] Center 34 (4~64) winsize 61
2535 22:53:34.360553
2536 22:53:34.363633 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2537 22:53:34.364055
2538 22:53:34.366484 [CATrainingPosCal] consider 1 rank data
2539 22:53:34.370253 u2DelayCellTimex100 = 270/100 ps
2540 22:53:34.373566 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2541 22:53:34.377595 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2542 22:53:34.383415 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2543 22:53:34.386945 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2544 22:53:34.390320 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2545 22:53:34.393676 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2546 22:53:34.394112
2547 22:53:34.396956 CA PerBit enable=1, Macro0, CA PI delay=34
2548 22:53:34.397404
2549 22:53:34.400003 [CBTSetCACLKResult] CA Dly = 34
2550 22:53:34.400422 CS Dly: 7 (0~38)
2551 22:53:34.400792 ==
2552 22:53:34.403591 Dram Type= 6, Freq= 0, CH_0, rank 1
2553 22:53:34.410621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2554 22:53:34.411045 ==
2555 22:53:34.413488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2556 22:53:34.419898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2557 22:53:34.429567 [CA 0] Center 39 (9~70) winsize 62
2558 22:53:34.432192 [CA 1] Center 39 (9~70) winsize 62
2559 22:53:34.436004 [CA 2] Center 36 (6~67) winsize 62
2560 22:53:34.439264 [CA 3] Center 36 (5~67) winsize 63
2561 22:53:34.442513 [CA 4] Center 34 (4~65) winsize 62
2562 22:53:34.446386 [CA 5] Center 34 (4~64) winsize 61
2563 22:53:34.446808
2564 22:53:34.449067 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2565 22:53:34.449598
2566 22:53:34.452781 [CATrainingPosCal] consider 2 rank data
2567 22:53:34.455970 u2DelayCellTimex100 = 270/100 ps
2568 22:53:34.459180 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2569 22:53:34.462480 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2570 22:53:34.466088 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2571 22:53:34.472584 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2572 22:53:34.476283 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2573 22:53:34.479635 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2574 22:53:34.480122
2575 22:53:34.483349 CA PerBit enable=1, Macro0, CA PI delay=34
2576 22:53:34.483919
2577 22:53:34.486461 [CBTSetCACLKResult] CA Dly = 34
2578 22:53:34.487064 CS Dly: 8 (0~41)
2579 22:53:34.487405
2580 22:53:34.489519 ----->DramcWriteLeveling(PI) begin...
2581 22:53:34.489945 ==
2582 22:53:34.492927 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 22:53:34.500090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 22:53:34.500629 ==
2585 22:53:34.502850 Write leveling (Byte 0): 31 => 31
2586 22:53:34.506995 Write leveling (Byte 1): 29 => 29
2587 22:53:34.507418 DramcWriteLeveling(PI) end<-----
2588 22:53:34.507753
2589 22:53:34.509707 ==
2590 22:53:34.513071 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 22:53:34.517036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 22:53:34.517565 ==
2593 22:53:34.520057 [Gating] SW mode calibration
2594 22:53:34.526207 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2595 22:53:34.530143 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2596 22:53:34.536545 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 22:53:34.540170 0 15 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2598 22:53:34.543756 0 15 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2599 22:53:34.549878 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 22:53:34.553164 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 22:53:34.556258 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 22:53:34.560083 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 22:53:34.566771 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 22:53:34.569745 1 0 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
2605 22:53:34.573789 1 0 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2606 22:53:34.579740 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 22:53:34.583578 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 22:53:34.587248 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 22:53:34.593385 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 22:53:34.596609 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 22:53:34.600469 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 22:53:34.606935 1 1 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2613 22:53:34.610445 1 1 4 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (1 1)
2614 22:53:34.613663 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 22:53:34.617257 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 22:53:34.624120 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 22:53:34.627458 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 22:53:34.630601 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 22:53:34.637421 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 22:53:34.640941 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2621 22:53:34.644555 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2622 22:53:34.650543 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 22:53:34.653970 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 22:53:34.657196 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 22:53:34.663963 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 22:53:34.667265 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 22:53:34.671061 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 22:53:34.677373 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 22:53:34.680741 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 22:53:34.684456 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 22:53:34.688068 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 22:53:34.694425 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 22:53:34.697587 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 22:53:34.701028 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 22:53:34.708053 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 22:53:34.711517 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2637 22:53:34.714312 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2638 22:53:34.721368 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2639 22:53:34.721810 Total UI for P1: 0, mck2ui 16
2640 22:53:34.724649 best dqsien dly found for B0: ( 1, 4, 2)
2641 22:53:34.727756 Total UI for P1: 0, mck2ui 16
2642 22:53:34.731183 best dqsien dly found for B1: ( 1, 4, 2)
2643 22:53:34.734824 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2644 22:53:34.737967 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2645 22:53:34.741576
2646 22:53:34.745046 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2647 22:53:34.748161 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2648 22:53:34.751223 [Gating] SW calibration Done
2649 22:53:34.751883 ==
2650 22:53:34.754556 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 22:53:34.758221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 22:53:34.758648 ==
2653 22:53:34.758985 RX Vref Scan: 0
2654 22:53:34.759300
2655 22:53:34.761306 RX Vref 0 -> 0, step: 1
2656 22:53:34.761734
2657 22:53:34.765012 RX Delay -40 -> 252, step: 8
2658 22:53:34.767871 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2659 22:53:34.771633 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2660 22:53:34.774860 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2661 22:53:34.781908 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2662 22:53:34.784850 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2663 22:53:34.788418 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2664 22:53:34.792017 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2665 22:53:34.794827 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2666 22:53:34.801601 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2667 22:53:34.804638 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2668 22:53:34.808645 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2669 22:53:34.812066 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2670 22:53:34.814777 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2671 22:53:34.818252 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2672 22:53:34.824917 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2673 22:53:34.829101 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2674 22:53:34.829680 ==
2675 22:53:34.832358 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 22:53:34.834854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 22:53:34.835309 ==
2678 22:53:34.838882 DQS Delay:
2679 22:53:34.839417 DQS0 = 0, DQS1 = 0
2680 22:53:34.839756 DQM Delay:
2681 22:53:34.841768 DQM0 = 115, DQM1 = 107
2682 22:53:34.842191 DQ Delay:
2683 22:53:34.845161 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2684 22:53:34.848632 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2685 22:53:34.852305 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2686 22:53:34.858151 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2687 22:53:34.858647
2688 22:53:34.858984
2689 22:53:34.859293 ==
2690 22:53:34.861705 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 22:53:34.864997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 22:53:34.865456 ==
2693 22:53:34.865793
2694 22:53:34.866103
2695 22:53:34.868560 TX Vref Scan disable
2696 22:53:34.868981 == TX Byte 0 ==
2697 22:53:34.875216 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2698 22:53:34.878278 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2699 22:53:34.878710 == TX Byte 1 ==
2700 22:53:34.885637 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2701 22:53:34.888897 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2702 22:53:34.889473 ==
2703 22:53:34.891907 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 22:53:34.895206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 22:53:34.895745 ==
2706 22:53:34.907605 TX Vref=22, minBit 1, minWin=24, winSum=418
2707 22:53:34.911348 TX Vref=24, minBit 7, minWin=25, winSum=424
2708 22:53:34.914279 TX Vref=26, minBit 5, minWin=25, winSum=429
2709 22:53:34.918050 TX Vref=28, minBit 1, minWin=25, winSum=431
2710 22:53:34.921495 TX Vref=30, minBit 4, minWin=26, winSum=435
2711 22:53:34.924971 TX Vref=32, minBit 1, minWin=26, winSum=434
2712 22:53:34.931338 [TxChooseVref] Worse bit 4, Min win 26, Win sum 435, Final Vref 30
2713 22:53:34.931892
2714 22:53:34.934793 Final TX Range 1 Vref 30
2715 22:53:34.935376
2716 22:53:34.935721 ==
2717 22:53:34.938424 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 22:53:34.941521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 22:53:34.942083 ==
2720 22:53:34.942429
2721 22:53:34.942745
2722 22:53:34.944985 TX Vref Scan disable
2723 22:53:34.947731 == TX Byte 0 ==
2724 22:53:34.951278 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2725 22:53:34.954717 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2726 22:53:34.957787 == TX Byte 1 ==
2727 22:53:34.961328 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2728 22:53:34.964879 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2729 22:53:34.965379
2730 22:53:34.967980 [DATLAT]
2731 22:53:34.968283 Freq=1200, CH0 RK0
2732 22:53:34.968527
2733 22:53:34.970980 DATLAT Default: 0xd
2734 22:53:34.971284 0, 0xFFFF, sum = 0
2735 22:53:34.974715 1, 0xFFFF, sum = 0
2736 22:53:34.974948 2, 0xFFFF, sum = 0
2737 22:53:34.977809 3, 0xFFFF, sum = 0
2738 22:53:34.977995 4, 0xFFFF, sum = 0
2739 22:53:34.980886 5, 0xFFFF, sum = 0
2740 22:53:34.981068 6, 0xFFFF, sum = 0
2741 22:53:34.984372 7, 0xFFFF, sum = 0
2742 22:53:34.984653 8, 0xFFFF, sum = 0
2743 22:53:34.987813 9, 0xFFFF, sum = 0
2744 22:53:34.987994 10, 0xFFFF, sum = 0
2745 22:53:34.991252 11, 0xFFFF, sum = 0
2746 22:53:34.991434 12, 0x0, sum = 1
2747 22:53:34.994757 13, 0x0, sum = 2
2748 22:53:34.994941 14, 0x0, sum = 3
2749 22:53:34.997799 15, 0x0, sum = 4
2750 22:53:34.997982 best_step = 13
2751 22:53:34.998126
2752 22:53:34.998259 ==
2753 22:53:35.001370 Dram Type= 6, Freq= 0, CH_0, rank 0
2754 22:53:35.004540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2755 22:53:35.008445 ==
2756 22:53:35.008628 RX Vref Scan: 1
2757 22:53:35.008774
2758 22:53:35.011199 Set Vref Range= 32 -> 127
2759 22:53:35.011381
2760 22:53:35.014816 RX Vref 32 -> 127, step: 1
2761 22:53:35.014999
2762 22:53:35.015144 RX Delay -21 -> 252, step: 4
2763 22:53:35.015279
2764 22:53:35.018227 Set Vref, RX VrefLevel [Byte0]: 32
2765 22:53:35.021256 [Byte1]: 32
2766 22:53:35.025663
2767 22:53:35.025847 Set Vref, RX VrefLevel [Byte0]: 33
2768 22:53:35.028787 [Byte1]: 33
2769 22:53:35.033566
2770 22:53:35.033750 Set Vref, RX VrefLevel [Byte0]: 34
2771 22:53:35.037245 [Byte1]: 34
2772 22:53:35.041844
2773 22:53:35.042026 Set Vref, RX VrefLevel [Byte0]: 35
2774 22:53:35.044909 [Byte1]: 35
2775 22:53:35.049514
2776 22:53:35.049667 Set Vref, RX VrefLevel [Byte0]: 36
2777 22:53:35.052615 [Byte1]: 36
2778 22:53:35.057174
2779 22:53:35.057320 Set Vref, RX VrefLevel [Byte0]: 37
2780 22:53:35.060627 [Byte1]: 37
2781 22:53:35.065683
2782 22:53:35.065826 Set Vref, RX VrefLevel [Byte0]: 38
2783 22:53:35.068259 [Byte1]: 38
2784 22:53:35.073314
2785 22:53:35.073419 Set Vref, RX VrefLevel [Byte0]: 39
2786 22:53:35.076909 [Byte1]: 39
2787 22:53:35.080954
2788 22:53:35.081058 Set Vref, RX VrefLevel [Byte0]: 40
2789 22:53:35.085166 [Byte1]: 40
2790 22:53:35.089865
2791 22:53:35.090381 Set Vref, RX VrefLevel [Byte0]: 41
2792 22:53:35.092973 [Byte1]: 41
2793 22:53:35.097775
2794 22:53:35.098295 Set Vref, RX VrefLevel [Byte0]: 42
2795 22:53:35.100611 [Byte1]: 42
2796 22:53:35.105532
2797 22:53:35.106049 Set Vref, RX VrefLevel [Byte0]: 43
2798 22:53:35.112063 [Byte1]: 43
2799 22:53:35.112584
2800 22:53:35.115083 Set Vref, RX VrefLevel [Byte0]: 44
2801 22:53:35.118412 [Byte1]: 44
2802 22:53:35.118955
2803 22:53:35.121790 Set Vref, RX VrefLevel [Byte0]: 45
2804 22:53:35.125050 [Byte1]: 45
2805 22:53:35.129098
2806 22:53:35.129661 Set Vref, RX VrefLevel [Byte0]: 46
2807 22:53:35.132592 [Byte1]: 46
2808 22:53:35.137531
2809 22:53:35.138050 Set Vref, RX VrefLevel [Byte0]: 47
2810 22:53:35.140233 [Byte1]: 47
2811 22:53:35.145452
2812 22:53:35.145995 Set Vref, RX VrefLevel [Byte0]: 48
2813 22:53:35.148409 [Byte1]: 48
2814 22:53:35.153101
2815 22:53:35.153706 Set Vref, RX VrefLevel [Byte0]: 49
2816 22:53:35.156453 [Byte1]: 49
2817 22:53:35.161042
2818 22:53:35.161503 Set Vref, RX VrefLevel [Byte0]: 50
2819 22:53:35.164035 [Byte1]: 50
2820 22:53:35.168943
2821 22:53:35.169545 Set Vref, RX VrefLevel [Byte0]: 51
2822 22:53:35.171970 [Byte1]: 51
2823 22:53:35.176991
2824 22:53:35.177565 Set Vref, RX VrefLevel [Byte0]: 52
2825 22:53:35.179988 [Byte1]: 52
2826 22:53:35.184634
2827 22:53:35.185148 Set Vref, RX VrefLevel [Byte0]: 53
2828 22:53:35.187897 [Byte1]: 53
2829 22:53:35.192760
2830 22:53:35.193349 Set Vref, RX VrefLevel [Byte0]: 54
2831 22:53:35.196435 [Byte1]: 54
2832 22:53:35.200826
2833 22:53:35.201389 Set Vref, RX VrefLevel [Byte0]: 55
2834 22:53:35.203833 [Byte1]: 55
2835 22:53:35.208519
2836 22:53:35.208940 Set Vref, RX VrefLevel [Byte0]: 56
2837 22:53:35.211619 [Byte1]: 56
2838 22:53:35.215996
2839 22:53:35.216416 Set Vref, RX VrefLevel [Byte0]: 57
2840 22:53:35.220126 [Byte1]: 57
2841 22:53:35.224337
2842 22:53:35.225008 Set Vref, RX VrefLevel [Byte0]: 58
2843 22:53:35.227169 [Byte1]: 58
2844 22:53:35.232245
2845 22:53:35.232762 Set Vref, RX VrefLevel [Byte0]: 59
2846 22:53:35.235779 [Byte1]: 59
2847 22:53:35.240583
2848 22:53:35.241100 Set Vref, RX VrefLevel [Byte0]: 60
2849 22:53:35.243362 [Byte1]: 60
2850 22:53:35.248171
2851 22:53:35.248694 Set Vref, RX VrefLevel [Byte0]: 61
2852 22:53:35.251497 [Byte1]: 61
2853 22:53:35.256554
2854 22:53:35.257092 Set Vref, RX VrefLevel [Byte0]: 62
2855 22:53:35.259276 [Byte1]: 62
2856 22:53:35.264182
2857 22:53:35.264702 Set Vref, RX VrefLevel [Byte0]: 63
2858 22:53:35.267428 [Byte1]: 63
2859 22:53:35.271771
2860 22:53:35.272310 Set Vref, RX VrefLevel [Byte0]: 64
2861 22:53:35.276031 [Byte1]: 64
2862 22:53:35.279881
2863 22:53:35.280400 Set Vref, RX VrefLevel [Byte0]: 65
2864 22:53:35.282900 [Byte1]: 65
2865 22:53:35.288459
2866 22:53:35.288977 Set Vref, RX VrefLevel [Byte0]: 66
2867 22:53:35.291472 [Byte1]: 66
2868 22:53:35.295523
2869 22:53:35.296039 Set Vref, RX VrefLevel [Byte0]: 67
2870 22:53:35.299001 [Byte1]: 67
2871 22:53:35.303603
2872 22:53:35.304166 Set Vref, RX VrefLevel [Byte0]: 68
2873 22:53:35.306680 [Byte1]: 68
2874 22:53:35.311575
2875 22:53:35.312090 Final RX Vref Byte 0 = 53 to rank0
2876 22:53:35.314680 Final RX Vref Byte 1 = 51 to rank0
2877 22:53:35.318563 Final RX Vref Byte 0 = 53 to rank1
2878 22:53:35.321579 Final RX Vref Byte 1 = 51 to rank1==
2879 22:53:35.324970 Dram Type= 6, Freq= 0, CH_0, rank 0
2880 22:53:35.331679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 22:53:35.332205 ==
2882 22:53:35.332542 DQS Delay:
2883 22:53:35.332855 DQS0 = 0, DQS1 = 0
2884 22:53:35.334885 DQM Delay:
2885 22:53:35.335309 DQM0 = 115, DQM1 = 104
2886 22:53:35.337931 DQ Delay:
2887 22:53:35.341267 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2888 22:53:35.344862 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2889 22:53:35.348022 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2890 22:53:35.351151 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2891 22:53:35.351578
2892 22:53:35.351913
2893 22:53:35.358639 [DQSOSCAuto] RK0, (LSB)MR18= 0xffef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2894 22:53:35.361316 CH0 RK0: MR19=303, MR18=FFEF
2895 22:53:35.368397 CH0_RK0: MR19=0x303, MR18=0xFFEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2896 22:53:35.368827
2897 22:53:35.371782 ----->DramcWriteLeveling(PI) begin...
2898 22:53:35.372218 ==
2899 22:53:35.374811 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 22:53:35.378488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 22:53:35.378921 ==
2902 22:53:35.381759 Write leveling (Byte 0): 34 => 34
2903 22:53:35.385363 Write leveling (Byte 1): 28 => 28
2904 22:53:35.388536 DramcWriteLeveling(PI) end<-----
2905 22:53:35.389058
2906 22:53:35.389447 ==
2907 22:53:35.391353 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 22:53:35.394890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 22:53:35.398720 ==
2910 22:53:35.399237 [Gating] SW mode calibration
2911 22:53:35.405476 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2912 22:53:35.412616 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2913 22:53:35.415907 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2914 22:53:35.422067 0 15 4 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
2915 22:53:35.425585 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 22:53:35.429044 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 22:53:35.432331 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 22:53:35.439103 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 22:53:35.442126 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 22:53:35.445950 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2921 22:53:35.452527 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2922 22:53:35.455451 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2923 22:53:35.458984 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 22:53:35.465348 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 22:53:35.469389 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 22:53:35.472560 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 22:53:35.478685 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2928 22:53:35.482430 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2929 22:53:35.486308 1 1 0 | B1->B0 | 3030 4242 | 0 0 | (0 0) (0 0)
2930 22:53:35.492164 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 22:53:35.496532 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 22:53:35.499252 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 22:53:35.502574 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 22:53:35.508897 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 22:53:35.512693 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 22:53:35.516023 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2937 22:53:35.522462 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2938 22:53:35.526193 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 22:53:35.529186 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 22:53:35.536045 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 22:53:35.539514 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 22:53:35.542791 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 22:53:35.549658 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 22:53:35.553007 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 22:53:35.556147 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 22:53:35.562676 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 22:53:35.566132 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 22:53:35.569685 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 22:53:35.573118 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 22:53:35.580078 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 22:53:35.582800 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 22:53:35.586040 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2953 22:53:35.593409 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2954 22:53:35.593934 Total UI for P1: 0, mck2ui 16
2955 22:53:35.599743 best dqsien dly found for B0: ( 1, 3, 28)
2956 22:53:35.603028 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 22:53:35.606538 Total UI for P1: 0, mck2ui 16
2958 22:53:35.610102 best dqsien dly found for B1: ( 1, 4, 0)
2959 22:53:35.613437 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2960 22:53:35.616375 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2961 22:53:35.616914
2962 22:53:35.620912 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2963 22:53:35.623285 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2964 22:53:35.626349 [Gating] SW calibration Done
2965 22:53:35.626772 ==
2966 22:53:35.629665 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 22:53:35.633593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 22:53:35.634122 ==
2969 22:53:35.636980 RX Vref Scan: 0
2970 22:53:35.637537
2971 22:53:35.640093 RX Vref 0 -> 0, step: 1
2972 22:53:35.640612
2973 22:53:35.640942 RX Delay -40 -> 252, step: 8
2974 22:53:35.646475 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2975 22:53:35.650774 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2976 22:53:35.653453 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2977 22:53:35.656898 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2978 22:53:35.659870 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2979 22:53:35.663510 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2980 22:53:35.670070 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2981 22:53:35.673525 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2982 22:53:35.676980 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2983 22:53:35.679954 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2984 22:53:35.683849 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2985 22:53:35.690206 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2986 22:53:35.693660 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2987 22:53:35.696999 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2988 22:53:35.700171 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2989 22:53:35.703208 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2990 22:53:35.703638 ==
2991 22:53:35.707173 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 22:53:35.713879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 22:53:35.714415 ==
2994 22:53:35.714761 DQS Delay:
2995 22:53:35.716704 DQS0 = 0, DQS1 = 0
2996 22:53:35.717130 DQM Delay:
2997 22:53:35.720643 DQM0 = 115, DQM1 = 105
2998 22:53:35.721179 DQ Delay:
2999 22:53:35.723902 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3000 22:53:35.726749 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3001 22:53:35.730200 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3002 22:53:35.733353 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
3003 22:53:35.733772
3004 22:53:35.734102
3005 22:53:35.734410 ==
3006 22:53:35.736771 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 22:53:35.740730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 22:53:35.741284 ==
3009 22:53:35.744157
3010 22:53:35.744691
3011 22:53:35.745029 TX Vref Scan disable
3012 22:53:35.746953 == TX Byte 0 ==
3013 22:53:35.750660 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3014 22:53:35.753667 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3015 22:53:35.757552 == TX Byte 1 ==
3016 22:53:35.761091 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3017 22:53:35.764137 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3018 22:53:35.764668 ==
3019 22:53:35.767629 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 22:53:35.773644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 22:53:35.774173 ==
3022 22:53:35.784781 TX Vref=22, minBit 1, minWin=25, winSum=418
3023 22:53:35.788470 TX Vref=24, minBit 1, minWin=25, winSum=424
3024 22:53:35.791744 TX Vref=26, minBit 0, minWin=26, winSum=427
3025 22:53:35.794968 TX Vref=28, minBit 2, minWin=26, winSum=430
3026 22:53:35.799048 TX Vref=30, minBit 1, minWin=26, winSum=429
3027 22:53:35.802164 TX Vref=32, minBit 2, minWin=26, winSum=430
3028 22:53:35.808631 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 28
3029 22:53:35.809245
3030 22:53:35.812506 Final TX Range 1 Vref 28
3031 22:53:35.813027
3032 22:53:35.813423 ==
3033 22:53:35.815304 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 22:53:35.818386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 22:53:35.818950 ==
3036 22:53:35.819352
3037 22:53:35.819666
3038 22:53:35.821992 TX Vref Scan disable
3039 22:53:35.825100 == TX Byte 0 ==
3040 22:53:35.828849 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3041 22:53:35.832095 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3042 22:53:35.835553 == TX Byte 1 ==
3043 22:53:35.838314 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3044 22:53:35.842110 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3045 22:53:35.842529
3046 22:53:35.845560 [DATLAT]
3047 22:53:35.845974 Freq=1200, CH0 RK1
3048 22:53:35.846327
3049 22:53:35.848738 DATLAT Default: 0xd
3050 22:53:35.849157 0, 0xFFFF, sum = 0
3051 22:53:35.852009 1, 0xFFFF, sum = 0
3052 22:53:35.852430 2, 0xFFFF, sum = 0
3053 22:53:35.855615 3, 0xFFFF, sum = 0
3054 22:53:35.856039 4, 0xFFFF, sum = 0
3055 22:53:35.859100 5, 0xFFFF, sum = 0
3056 22:53:35.859521 6, 0xFFFF, sum = 0
3057 22:53:35.862177 7, 0xFFFF, sum = 0
3058 22:53:35.862600 8, 0xFFFF, sum = 0
3059 22:53:35.865613 9, 0xFFFF, sum = 0
3060 22:53:35.866059 10, 0xFFFF, sum = 0
3061 22:53:35.869126 11, 0xFFFF, sum = 0
3062 22:53:35.869587 12, 0x0, sum = 1
3063 22:53:35.872720 13, 0x0, sum = 2
3064 22:53:35.873162 14, 0x0, sum = 3
3065 22:53:35.876173 15, 0x0, sum = 4
3066 22:53:35.876700 best_step = 13
3067 22:53:35.877037
3068 22:53:35.877420 ==
3069 22:53:35.878620 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 22:53:35.886161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 22:53:35.886687 ==
3072 22:53:35.887027 RX Vref Scan: 0
3073 22:53:35.887340
3074 22:53:35.888586 RX Vref 0 -> 0, step: 1
3075 22:53:35.889011
3076 22:53:35.892454 RX Delay -21 -> 252, step: 4
3077 22:53:35.895407 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3078 22:53:35.899041 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3079 22:53:35.902385 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3080 22:53:35.909002 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3081 22:53:35.912287 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3082 22:53:35.915685 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3083 22:53:35.919045 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3084 22:53:35.922825 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3085 22:53:35.929399 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3086 22:53:35.932555 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3087 22:53:35.935920 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3088 22:53:35.939369 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3089 22:53:35.942215 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3090 22:53:35.948921 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3091 22:53:35.952152 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3092 22:53:35.955943 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3093 22:53:35.956363 ==
3094 22:53:35.959375 Dram Type= 6, Freq= 0, CH_0, rank 1
3095 22:53:35.962576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 22:53:35.962996 ==
3097 22:53:35.966169 DQS Delay:
3098 22:53:35.966782 DQS0 = 0, DQS1 = 0
3099 22:53:35.967278 DQM Delay:
3100 22:53:35.969114 DQM0 = 114, DQM1 = 104
3101 22:53:35.969520 DQ Delay:
3102 22:53:35.972549 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3103 22:53:35.976231 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3104 22:53:35.979801 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3105 22:53:35.982908 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3106 22:53:35.985941
3107 22:53:35.986360
3108 22:53:35.993726 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3109 22:53:35.996080 CH0 RK1: MR19=403, MR18=4F6
3110 22:53:36.003297 CH0_RK1: MR19=0x403, MR18=0x4F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3111 22:53:36.003821 [RxdqsGatingPostProcess] freq 1200
3112 22:53:36.009770 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3113 22:53:36.013010 best DQS0 dly(2T, 0.5T) = (0, 12)
3114 22:53:36.016964 best DQS1 dly(2T, 0.5T) = (0, 12)
3115 22:53:36.019477 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3116 22:53:36.023016 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3117 22:53:36.026637 best DQS0 dly(2T, 0.5T) = (0, 11)
3118 22:53:36.029711 best DQS1 dly(2T, 0.5T) = (0, 12)
3119 22:53:36.032989 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3120 22:53:36.036969 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3121 22:53:36.037564 Pre-setting of DQS Precalculation
3122 22:53:36.043591 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3123 22:53:36.044112 ==
3124 22:53:36.046305 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 22:53:36.049736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 22:53:36.050159 ==
3127 22:53:36.057034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3128 22:53:36.063509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3129 22:53:36.070346 [CA 0] Center 38 (9~68) winsize 60
3130 22:53:36.073870 [CA 1] Center 38 (8~68) winsize 61
3131 22:53:36.077989 [CA 2] Center 35 (6~65) winsize 60
3132 22:53:36.081082 [CA 3] Center 34 (4~65) winsize 62
3133 22:53:36.084284 [CA 4] Center 34 (4~65) winsize 62
3134 22:53:36.087530 [CA 5] Center 34 (4~64) winsize 61
3135 22:53:36.088053
3136 22:53:36.090671 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3137 22:53:36.091194
3138 22:53:36.094010 [CATrainingPosCal] consider 1 rank data
3139 22:53:36.097160 u2DelayCellTimex100 = 270/100 ps
3140 22:53:36.101087 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3141 22:53:36.103970 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3142 22:53:36.108351 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3143 22:53:36.114590 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3144 22:53:36.117635 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3145 22:53:36.121041 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3146 22:53:36.121624
3147 22:53:36.124221 CA PerBit enable=1, Macro0, CA PI delay=34
3148 22:53:36.124743
3149 22:53:36.127424 [CBTSetCACLKResult] CA Dly = 34
3150 22:53:36.128069 CS Dly: 6 (0~37)
3151 22:53:36.128426 ==
3152 22:53:36.131278 Dram Type= 6, Freq= 0, CH_1, rank 1
3153 22:53:36.137977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 22:53:36.138533 ==
3155 22:53:36.141203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3156 22:53:36.147675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3157 22:53:36.156245 [CA 0] Center 38 (8~68) winsize 61
3158 22:53:36.159452 [CA 1] Center 38 (8~68) winsize 61
3159 22:53:36.163180 [CA 2] Center 34 (4~65) winsize 62
3160 22:53:36.165806 [CA 3] Center 34 (3~65) winsize 63
3161 22:53:36.169476 [CA 4] Center 34 (4~65) winsize 62
3162 22:53:36.172920 [CA 5] Center 33 (3~63) winsize 61
3163 22:53:36.173382
3164 22:53:36.176310 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3165 22:53:36.176831
3166 22:53:36.179498 [CATrainingPosCal] consider 2 rank data
3167 22:53:36.183392 u2DelayCellTimex100 = 270/100 ps
3168 22:53:36.186093 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3169 22:53:36.189454 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3170 22:53:36.193873 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3171 22:53:36.200550 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3172 22:53:36.203339 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3173 22:53:36.207406 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3174 22:53:36.207930
3175 22:53:36.209729 CA PerBit enable=1, Macro0, CA PI delay=33
3176 22:53:36.210144
3177 22:53:36.213296 [CBTSetCACLKResult] CA Dly = 33
3178 22:53:36.213819 CS Dly: 7 (0~40)
3179 22:53:36.214151
3180 22:53:36.217085 ----->DramcWriteLeveling(PI) begin...
3181 22:53:36.217560 ==
3182 22:53:36.219878 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 22:53:36.226736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 22:53:36.227190 ==
3185 22:53:36.230148 Write leveling (Byte 0): 25 => 25
3186 22:53:36.230566 Write leveling (Byte 1): 30 => 30
3187 22:53:36.233629 DramcWriteLeveling(PI) end<-----
3188 22:53:36.234273
3189 22:53:36.234616 ==
3190 22:53:36.236511 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 22:53:36.243585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 22:53:36.244109 ==
3193 22:53:36.246929 [Gating] SW mode calibration
3194 22:53:36.253716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3195 22:53:36.256756 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3196 22:53:36.263308 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3197 22:53:36.266977 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 22:53:36.270631 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 22:53:36.273284 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3200 22:53:36.280703 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 22:53:36.283585 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 22:53:36.287409 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 22:53:36.293673 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3204 22:53:36.297140 1 0 0 | B1->B0 | 2323 2929 | 0 0 | (1 0) (0 1)
3205 22:53:36.300502 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 22:53:36.307104 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 22:53:36.310100 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 22:53:36.313844 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 22:53:36.320745 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 22:53:36.324251 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 22:53:36.327314 1 0 28 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
3212 22:53:36.333866 1 1 0 | B1->B0 | 4040 3131 | 0 0 | (0 0) (0 0)
3213 22:53:36.337748 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 22:53:36.340626 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 22:53:36.344269 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 22:53:36.350451 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 22:53:36.354165 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 22:53:36.357507 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 22:53:36.364363 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 22:53:36.367005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3221 22:53:36.370412 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 22:53:36.377373 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 22:53:36.380663 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 22:53:36.384116 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 22:53:36.390443 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 22:53:36.393928 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 22:53:36.397538 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 22:53:36.401506 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 22:53:36.407981 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 22:53:36.411040 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 22:53:36.414766 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 22:53:36.421298 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 22:53:36.424057 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 22:53:36.427826 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 22:53:36.434606 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3236 22:53:36.437995 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3237 22:53:36.441093 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 22:53:36.445101 Total UI for P1: 0, mck2ui 16
3239 22:53:36.448176 best dqsien dly found for B0: ( 1, 3, 30)
3240 22:53:36.451228 Total UI for P1: 0, mck2ui 16
3241 22:53:36.454751 best dqsien dly found for B1: ( 1, 3, 30)
3242 22:53:36.458010 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3243 22:53:36.461513 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3244 22:53:36.462057
3245 22:53:36.464940 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3246 22:53:36.468616 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3247 22:53:36.471348 [Gating] SW calibration Done
3248 22:53:36.471790 ==
3249 22:53:36.474822 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 22:53:36.481742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 22:53:36.482322 ==
3252 22:53:36.482770 RX Vref Scan: 0
3253 22:53:36.483186
3254 22:53:36.485037 RX Vref 0 -> 0, step: 1
3255 22:53:36.485507
3256 22:53:36.488275 RX Delay -40 -> 252, step: 8
3257 22:53:36.491758 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3258 22:53:36.494806 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3259 22:53:36.498826 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3260 22:53:36.501440 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3261 22:53:36.508711 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3262 22:53:36.512070 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3263 22:53:36.515715 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3264 22:53:36.518189 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3265 22:53:36.521935 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3266 22:53:36.525321 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3267 22:53:36.531942 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3268 22:53:36.534962 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3269 22:53:36.539001 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3270 22:53:36.542058 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3271 22:53:36.545645 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3272 22:53:36.552240 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3273 22:53:36.552773 ==
3274 22:53:36.555357 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 22:53:36.558838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 22:53:36.559263 ==
3277 22:53:36.559597 DQS Delay:
3278 22:53:36.561999 DQS0 = 0, DQS1 = 0
3279 22:53:36.562419 DQM Delay:
3280 22:53:36.565100 DQM0 = 116, DQM1 = 109
3281 22:53:36.565554 DQ Delay:
3282 22:53:36.568574 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3283 22:53:36.572151 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3284 22:53:36.575798 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3285 22:53:36.578911 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3286 22:53:36.579334
3287 22:53:36.579670
3288 22:53:36.582000 ==
3289 22:53:36.582424 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 22:53:36.589399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 22:53:36.589929 ==
3292 22:53:36.590266
3293 22:53:36.590600
3294 22:53:36.591800 TX Vref Scan disable
3295 22:53:36.592232 == TX Byte 0 ==
3296 22:53:36.595613 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3297 22:53:36.602097 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3298 22:53:36.602638 == TX Byte 1 ==
3299 22:53:36.605625 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3300 22:53:36.612586 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3301 22:53:36.613140 ==
3302 22:53:36.615256 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 22:53:36.618499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 22:53:36.619126 ==
3305 22:53:36.630807 TX Vref=22, minBit 15, minWin=24, winSum=411
3306 22:53:36.633913 TX Vref=24, minBit 9, minWin=25, winSum=415
3307 22:53:36.637242 TX Vref=26, minBit 0, minWin=26, winSum=422
3308 22:53:36.640706 TX Vref=28, minBit 15, minWin=25, winSum=425
3309 22:53:36.644197 TX Vref=30, minBit 15, minWin=25, winSum=426
3310 22:53:36.650541 TX Vref=32, minBit 13, minWin=25, winSum=426
3311 22:53:36.653761 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 26
3312 22:53:36.654189
3313 22:53:36.657854 Final TX Range 1 Vref 26
3314 22:53:36.658284
3315 22:53:36.658621 ==
3316 22:53:36.661094 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 22:53:36.663947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 22:53:36.664372 ==
3319 22:53:36.667304
3320 22:53:36.667738
3321 22:53:36.668076 TX Vref Scan disable
3322 22:53:36.670750 == TX Byte 0 ==
3323 22:53:36.674164 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3324 22:53:36.680737 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3325 22:53:36.681166 == TX Byte 1 ==
3326 22:53:36.684457 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3327 22:53:36.687252 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3328 22:53:36.690426
3329 22:53:36.690872 [DATLAT]
3330 22:53:36.691306 Freq=1200, CH1 RK0
3331 22:53:36.691716
3332 22:53:36.694248 DATLAT Default: 0xd
3333 22:53:36.694681 0, 0xFFFF, sum = 0
3334 22:53:36.697920 1, 0xFFFF, sum = 0
3335 22:53:36.698362 2, 0xFFFF, sum = 0
3336 22:53:36.700988 3, 0xFFFF, sum = 0
3337 22:53:36.701460 4, 0xFFFF, sum = 0
3338 22:53:36.704033 5, 0xFFFF, sum = 0
3339 22:53:36.704472 6, 0xFFFF, sum = 0
3340 22:53:36.707572 7, 0xFFFF, sum = 0
3341 22:53:36.711550 8, 0xFFFF, sum = 0
3342 22:53:36.711990 9, 0xFFFF, sum = 0
3343 22:53:36.714035 10, 0xFFFF, sum = 0
3344 22:53:36.714475 11, 0xFFFF, sum = 0
3345 22:53:36.717640 12, 0x0, sum = 1
3346 22:53:36.718080 13, 0x0, sum = 2
3347 22:53:36.721044 14, 0x0, sum = 3
3348 22:53:36.721614 15, 0x0, sum = 4
3349 22:53:36.722130 best_step = 13
3350 22:53:36.722487
3351 22:53:36.724436 ==
3352 22:53:36.724860 Dram Type= 6, Freq= 0, CH_1, rank 0
3353 22:53:36.730715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3354 22:53:36.731138 ==
3355 22:53:36.731468 RX Vref Scan: 1
3356 22:53:36.731777
3357 22:53:36.734172 Set Vref Range= 32 -> 127
3358 22:53:36.734591
3359 22:53:36.737506 RX Vref 32 -> 127, step: 1
3360 22:53:36.737922
3361 22:53:36.740871 RX Delay -21 -> 252, step: 4
3362 22:53:36.741327
3363 22:53:36.744229 Set Vref, RX VrefLevel [Byte0]: 32
3364 22:53:36.747484 [Byte1]: 32
3365 22:53:36.747902
3366 22:53:36.750999 Set Vref, RX VrefLevel [Byte0]: 33
3367 22:53:36.754990 [Byte1]: 33
3368 22:53:36.755407
3369 22:53:36.757865 Set Vref, RX VrefLevel [Byte0]: 34
3370 22:53:36.760732 [Byte1]: 34
3371 22:53:36.764673
3372 22:53:36.764904 Set Vref, RX VrefLevel [Byte0]: 35
3373 22:53:36.768489 [Byte1]: 35
3374 22:53:36.773138
3375 22:53:36.773387 Set Vref, RX VrefLevel [Byte0]: 36
3376 22:53:36.775994 [Byte1]: 36
3377 22:53:36.780528
3378 22:53:36.780748 Set Vref, RX VrefLevel [Byte0]: 37
3379 22:53:36.784556 [Byte1]: 37
3380 22:53:36.788649
3381 22:53:36.788871 Set Vref, RX VrefLevel [Byte0]: 38
3382 22:53:36.791925 [Byte1]: 38
3383 22:53:36.796694
3384 22:53:36.796917 Set Vref, RX VrefLevel [Byte0]: 39
3385 22:53:36.799994 [Byte1]: 39
3386 22:53:36.804716
3387 22:53:36.804937 Set Vref, RX VrefLevel [Byte0]: 40
3388 22:53:36.807753 [Byte1]: 40
3389 22:53:36.812715
3390 22:53:36.812796 Set Vref, RX VrefLevel [Byte0]: 41
3391 22:53:36.815585 [Byte1]: 41
3392 22:53:36.820421
3393 22:53:36.820502 Set Vref, RX VrefLevel [Byte0]: 42
3394 22:53:36.823446 [Byte1]: 42
3395 22:53:36.828265
3396 22:53:36.828345 Set Vref, RX VrefLevel [Byte0]: 43
3397 22:53:36.831384 [Byte1]: 43
3398 22:53:36.835933
3399 22:53:36.836013 Set Vref, RX VrefLevel [Byte0]: 44
3400 22:53:36.839400 [Byte1]: 44
3401 22:53:36.843717
3402 22:53:36.843814 Set Vref, RX VrefLevel [Byte0]: 45
3403 22:53:36.847263 [Byte1]: 45
3404 22:53:36.851799
3405 22:53:36.851884 Set Vref, RX VrefLevel [Byte0]: 46
3406 22:53:36.854982 [Byte1]: 46
3407 22:53:36.860137
3408 22:53:36.860246 Set Vref, RX VrefLevel [Byte0]: 47
3409 22:53:36.863102 [Byte1]: 47
3410 22:53:36.868263
3411 22:53:36.868344 Set Vref, RX VrefLevel [Byte0]: 48
3412 22:53:36.871198 [Byte1]: 48
3413 22:53:36.875629
3414 22:53:36.875711 Set Vref, RX VrefLevel [Byte0]: 49
3415 22:53:36.878942 [Byte1]: 49
3416 22:53:36.883802
3417 22:53:36.883884 Set Vref, RX VrefLevel [Byte0]: 50
3418 22:53:36.886771 [Byte1]: 50
3419 22:53:36.891780
3420 22:53:36.891861 Set Vref, RX VrefLevel [Byte0]: 51
3421 22:53:36.894565 [Byte1]: 51
3422 22:53:36.899243
3423 22:53:36.899325 Set Vref, RX VrefLevel [Byte0]: 52
3424 22:53:36.902635 [Byte1]: 52
3425 22:53:36.907464
3426 22:53:36.907546 Set Vref, RX VrefLevel [Byte0]: 53
3427 22:53:36.910912 [Byte1]: 53
3428 22:53:36.915001
3429 22:53:36.915082 Set Vref, RX VrefLevel [Byte0]: 54
3430 22:53:36.918298 [Byte1]: 54
3431 22:53:36.923064
3432 22:53:36.923149 Set Vref, RX VrefLevel [Byte0]: 55
3433 22:53:36.926991 [Byte1]: 55
3434 22:53:36.930975
3435 22:53:36.931057 Set Vref, RX VrefLevel [Byte0]: 56
3436 22:53:36.934483 [Byte1]: 56
3437 22:53:36.938631
3438 22:53:36.938714 Set Vref, RX VrefLevel [Byte0]: 57
3439 22:53:36.942159 [Byte1]: 57
3440 22:53:36.947210
3441 22:53:36.947292 Set Vref, RX VrefLevel [Byte0]: 58
3442 22:53:36.950354 [Byte1]: 58
3443 22:53:36.954998
3444 22:53:36.955080 Set Vref, RX VrefLevel [Byte0]: 59
3445 22:53:36.957827 [Byte1]: 59
3446 22:53:36.962811
3447 22:53:36.962893 Set Vref, RX VrefLevel [Byte0]: 60
3448 22:53:36.966255 [Byte1]: 60
3449 22:53:36.970491
3450 22:53:36.970573 Set Vref, RX VrefLevel [Byte0]: 61
3451 22:53:36.974189 [Byte1]: 61
3452 22:53:36.978598
3453 22:53:36.978681 Set Vref, RX VrefLevel [Byte0]: 62
3454 22:53:36.981888 [Byte1]: 62
3455 22:53:36.986502
3456 22:53:36.986584 Set Vref, RX VrefLevel [Byte0]: 63
3457 22:53:36.989593 [Byte1]: 63
3458 22:53:36.994247
3459 22:53:36.994330 Set Vref, RX VrefLevel [Byte0]: 64
3460 22:53:36.997953 [Byte1]: 64
3461 22:53:37.002740
3462 22:53:37.002822 Set Vref, RX VrefLevel [Byte0]: 65
3463 22:53:37.005376 [Byte1]: 65
3464 22:53:37.010592
3465 22:53:37.010694 Set Vref, RX VrefLevel [Byte0]: 66
3466 22:53:37.013748 [Byte1]: 66
3467 22:53:37.018580
3468 22:53:37.018662 Set Vref, RX VrefLevel [Byte0]: 67
3469 22:53:37.021856 [Byte1]: 67
3470 22:53:37.026196
3471 22:53:37.026278 Set Vref, RX VrefLevel [Byte0]: 68
3472 22:53:37.029591 [Byte1]: 68
3473 22:53:37.034009
3474 22:53:37.034091 Set Vref, RX VrefLevel [Byte0]: 69
3475 22:53:37.037460 [Byte1]: 69
3476 22:53:37.042062
3477 22:53:37.042144 Set Vref, RX VrefLevel [Byte0]: 70
3478 22:53:37.045135 [Byte1]: 70
3479 22:53:37.049855
3480 22:53:37.049937 Set Vref, RX VrefLevel [Byte0]: 71
3481 22:53:37.053347 [Byte1]: 71
3482 22:53:37.057640
3483 22:53:37.057736 Set Vref, RX VrefLevel [Byte0]: 72
3484 22:53:37.061169 [Byte1]: 72
3485 22:53:37.065514
3486 22:53:37.065596 Final RX Vref Byte 0 = 57 to rank0
3487 22:53:37.068937 Final RX Vref Byte 1 = 52 to rank0
3488 22:53:37.072444 Final RX Vref Byte 0 = 57 to rank1
3489 22:53:37.075912 Final RX Vref Byte 1 = 52 to rank1==
3490 22:53:37.078986 Dram Type= 6, Freq= 0, CH_1, rank 0
3491 22:53:37.082550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 22:53:37.086060 ==
3493 22:53:37.086172 DQS Delay:
3494 22:53:37.086237 DQS0 = 0, DQS1 = 0
3495 22:53:37.088911 DQM Delay:
3496 22:53:37.088993 DQM0 = 115, DQM1 = 109
3497 22:53:37.092426 DQ Delay:
3498 22:53:37.095781 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3499 22:53:37.098933 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3500 22:53:37.102610 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3501 22:53:37.105796 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3502 22:53:37.105882
3503 22:53:37.105947
3504 22:53:37.113010 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
3505 22:53:37.115976 CH1 RK0: MR19=303, MR18=FCE0
3506 22:53:37.122526 CH1_RK0: MR19=0x303, MR18=0xFCE0, DQSOSC=411, MR23=63, INC=38, DEC=25
3507 22:53:37.122609
3508 22:53:37.126702 ----->DramcWriteLeveling(PI) begin...
3509 22:53:37.126786 ==
3510 22:53:37.129398 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 22:53:37.132949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 22:53:37.133032 ==
3513 22:53:37.135862 Write leveling (Byte 0): 25 => 25
3514 22:53:37.139757 Write leveling (Byte 1): 29 => 29
3515 22:53:37.142871 DramcWriteLeveling(PI) end<-----
3516 22:53:37.142954
3517 22:53:37.143019 ==
3518 22:53:37.146168 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 22:53:37.149355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 22:53:37.152828 ==
3521 22:53:37.152910 [Gating] SW mode calibration
3522 22:53:37.159731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3523 22:53:37.166342 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3524 22:53:37.170020 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3525 22:53:37.176617 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 22:53:37.179839 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 22:53:37.182897 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 22:53:37.186444 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 22:53:37.193278 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 22:53:37.196300 0 15 24 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (1 0)
3531 22:53:37.199827 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3532 22:53:37.206439 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 22:53:37.210535 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 22:53:37.213049 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 22:53:37.219885 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 22:53:37.222958 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 22:53:37.226834 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 22:53:37.233149 1 0 24 | B1->B0 | 2727 4343 | 0 0 | (0 0) (0 0)
3539 22:53:37.236721 1 0 28 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
3540 22:53:37.239693 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 22:53:37.246472 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 22:53:37.249559 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 22:53:37.252869 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 22:53:37.260228 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 22:53:37.263225 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3546 22:53:37.266572 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3547 22:53:37.272846 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3548 22:53:37.276471 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 22:53:37.279607 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 22:53:37.282758 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 22:53:37.289723 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 22:53:37.292813 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 22:53:37.296525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 22:53:37.303343 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 22:53:37.306685 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 22:53:37.309566 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 22:53:37.316195 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 22:53:37.319648 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 22:53:37.323151 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 22:53:37.330103 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 22:53:37.333363 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3562 22:53:37.337052 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3563 22:53:37.343835 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3564 22:53:37.343918 Total UI for P1: 0, mck2ui 16
3565 22:53:37.349774 best dqsien dly found for B0: ( 1, 3, 22)
3566 22:53:37.353103 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 22:53:37.356284 Total UI for P1: 0, mck2ui 16
3568 22:53:37.359592 best dqsien dly found for B1: ( 1, 3, 28)
3569 22:53:37.363532 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3570 22:53:37.366811 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3571 22:53:37.366893
3572 22:53:37.369640 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3573 22:53:37.373128 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3574 22:53:37.376302 [Gating] SW calibration Done
3575 22:53:37.376385 ==
3576 22:53:37.379611 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 22:53:37.383089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 22:53:37.383172 ==
3579 22:53:37.386636 RX Vref Scan: 0
3580 22:53:37.386720
3581 22:53:37.389862 RX Vref 0 -> 0, step: 1
3582 22:53:37.389944
3583 22:53:37.390009 RX Delay -40 -> 252, step: 8
3584 22:53:37.396677 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3585 22:53:37.400200 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3586 22:53:37.402954 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3587 22:53:37.406324 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3588 22:53:37.409789 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3589 22:53:37.416553 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3590 22:53:37.419536 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3591 22:53:37.423244 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3592 22:53:37.426469 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3593 22:53:37.429807 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3594 22:53:37.436330 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3595 22:53:37.439714 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3596 22:53:37.443338 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3597 22:53:37.446278 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3598 22:53:37.450371 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3599 22:53:37.456670 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3600 22:53:37.456753 ==
3601 22:53:37.460006 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 22:53:37.463616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 22:53:37.463725 ==
3604 22:53:37.463818 DQS Delay:
3605 22:53:37.466392 DQS0 = 0, DQS1 = 0
3606 22:53:37.466474 DQM Delay:
3607 22:53:37.470159 DQM0 = 114, DQM1 = 110
3608 22:53:37.470241 DQ Delay:
3609 22:53:37.473182 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3610 22:53:37.476378 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =107
3611 22:53:37.479925 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3612 22:53:37.482867 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3613 22:53:37.482950
3614 22:53:37.483014
3615 22:53:37.483074 ==
3616 22:53:37.486436 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 22:53:37.492789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 22:53:37.492871 ==
3619 22:53:37.492937
3620 22:53:37.492997
3621 22:53:37.493055 TX Vref Scan disable
3622 22:53:37.496547 == TX Byte 0 ==
3623 22:53:37.500055 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3624 22:53:37.506959 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3625 22:53:37.507046 == TX Byte 1 ==
3626 22:53:37.510196 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3627 22:53:37.513200 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3628 22:53:37.516674 ==
3629 22:53:37.520347 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 22:53:37.523193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 22:53:37.523276 ==
3632 22:53:37.534898 TX Vref=22, minBit 1, minWin=25, winSum=418
3633 22:53:37.538208 TX Vref=24, minBit 0, minWin=26, winSum=424
3634 22:53:37.541646 TX Vref=26, minBit 0, minWin=26, winSum=427
3635 22:53:37.544991 TX Vref=28, minBit 1, minWin=26, winSum=432
3636 22:53:37.548055 TX Vref=30, minBit 3, minWin=26, winSum=431
3637 22:53:37.551410 TX Vref=32, minBit 0, minWin=26, winSum=430
3638 22:53:37.557958 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 28
3639 22:53:37.558041
3640 22:53:37.561702 Final TX Range 1 Vref 28
3641 22:53:37.561784
3642 22:53:37.561849 ==
3643 22:53:37.565281 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 22:53:37.568386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 22:53:37.568469 ==
3646 22:53:37.568534
3647 22:53:37.568593
3648 22:53:37.571575 TX Vref Scan disable
3649 22:53:37.574854 == TX Byte 0 ==
3650 22:53:37.578058 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3651 22:53:37.581529 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3652 22:53:37.584951 == TX Byte 1 ==
3653 22:53:37.588167 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3654 22:53:37.591961 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3655 22:53:37.592043
3656 22:53:37.595370 [DATLAT]
3657 22:53:37.595451 Freq=1200, CH1 RK1
3658 22:53:37.595516
3659 22:53:37.598643 DATLAT Default: 0xd
3660 22:53:37.598759 0, 0xFFFF, sum = 0
3661 22:53:37.601796 1, 0xFFFF, sum = 0
3662 22:53:37.601879 2, 0xFFFF, sum = 0
3663 22:53:37.605108 3, 0xFFFF, sum = 0
3664 22:53:37.605191 4, 0xFFFF, sum = 0
3665 22:53:37.608234 5, 0xFFFF, sum = 0
3666 22:53:37.608317 6, 0xFFFF, sum = 0
3667 22:53:37.611686 7, 0xFFFF, sum = 0
3668 22:53:37.611770 8, 0xFFFF, sum = 0
3669 22:53:37.615736 9, 0xFFFF, sum = 0
3670 22:53:37.615820 10, 0xFFFF, sum = 0
3671 22:53:37.618576 11, 0xFFFF, sum = 0
3672 22:53:37.618659 12, 0x0, sum = 1
3673 22:53:37.621995 13, 0x0, sum = 2
3674 22:53:37.622078 14, 0x0, sum = 3
3675 22:53:37.624936 15, 0x0, sum = 4
3676 22:53:37.625019 best_step = 13
3677 22:53:37.625084
3678 22:53:37.625144 ==
3679 22:53:37.628793 Dram Type= 6, Freq= 0, CH_1, rank 1
3680 22:53:37.634982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3681 22:53:37.635065 ==
3682 22:53:37.635129 RX Vref Scan: 0
3683 22:53:37.635190
3684 22:53:37.638633 RX Vref 0 -> 0, step: 1
3685 22:53:37.638716
3686 22:53:37.641622 RX Delay -21 -> 252, step: 4
3687 22:53:37.644977 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3688 22:53:37.648726 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3689 22:53:37.655208 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3690 22:53:37.658155 iDelay=191, Bit 3, Center 110 (43 ~ 178) 136
3691 22:53:37.661842 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3692 22:53:37.665125 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3693 22:53:37.668421 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3694 22:53:37.674940 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3695 22:53:37.678338 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3696 22:53:37.682080 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3697 22:53:37.684843 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3698 22:53:37.689341 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3699 22:53:37.691488 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3700 22:53:37.698453 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3701 22:53:37.702245 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3702 22:53:37.705291 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3703 22:53:37.705374 ==
3704 22:53:37.708254 Dram Type= 6, Freq= 0, CH_1, rank 1
3705 22:53:37.711658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3706 22:53:37.714987 ==
3707 22:53:37.715070 DQS Delay:
3708 22:53:37.715135 DQS0 = 0, DQS1 = 0
3709 22:53:37.718212 DQM Delay:
3710 22:53:37.718295 DQM0 = 113, DQM1 = 109
3711 22:53:37.721917 DQ Delay:
3712 22:53:37.725046 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =110
3713 22:53:37.728452 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3714 22:53:37.731906 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =102
3715 22:53:37.734990 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3716 22:53:37.735073
3717 22:53:37.735137
3718 22:53:37.741474 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3719 22:53:37.745425 CH1 RK1: MR19=304, MR18=FA02
3720 22:53:37.751743 CH1_RK1: MR19=0x304, MR18=0xFA02, DQSOSC=409, MR23=63, INC=39, DEC=26
3721 22:53:37.754767 [RxdqsGatingPostProcess] freq 1200
3722 22:53:37.761752 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3723 22:53:37.761835 best DQS0 dly(2T, 0.5T) = (0, 11)
3724 22:53:37.765070 best DQS1 dly(2T, 0.5T) = (0, 11)
3725 22:53:37.768357 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3726 22:53:37.772025 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3727 22:53:37.774978 best DQS0 dly(2T, 0.5T) = (0, 11)
3728 22:53:37.778306 best DQS1 dly(2T, 0.5T) = (0, 11)
3729 22:53:37.781943 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3730 22:53:37.785253 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3731 22:53:37.788614 Pre-setting of DQS Precalculation
3732 22:53:37.791602 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3733 22:53:37.802187 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3734 22:53:37.808343 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3735 22:53:37.808426
3736 22:53:37.808491
3737 22:53:37.811851 [Calibration Summary] 2400 Mbps
3738 22:53:37.811933 CH 0, Rank 0
3739 22:53:37.815564 SW Impedance : PASS
3740 22:53:37.815647 DUTY Scan : NO K
3741 22:53:37.818857 ZQ Calibration : PASS
3742 22:53:37.821965 Jitter Meter : NO K
3743 22:53:37.822047 CBT Training : PASS
3744 22:53:37.824895 Write leveling : PASS
3745 22:53:37.829080 RX DQS gating : PASS
3746 22:53:37.829180 RX DQ/DQS(RDDQC) : PASS
3747 22:53:37.831929 TX DQ/DQS : PASS
3748 22:53:37.835271 RX DATLAT : PASS
3749 22:53:37.835354 RX DQ/DQS(Engine): PASS
3750 22:53:37.838385 TX OE : NO K
3751 22:53:37.838467 All Pass.
3752 22:53:37.838532
3753 22:53:37.841705 CH 0, Rank 1
3754 22:53:37.841787 SW Impedance : PASS
3755 22:53:37.845036 DUTY Scan : NO K
3756 22:53:37.848707 ZQ Calibration : PASS
3757 22:53:37.848789 Jitter Meter : NO K
3758 22:53:37.851769 CBT Training : PASS
3759 22:53:37.851851 Write leveling : PASS
3760 22:53:37.855809 RX DQS gating : PASS
3761 22:53:37.858615 RX DQ/DQS(RDDQC) : PASS
3762 22:53:37.858697 TX DQ/DQS : PASS
3763 22:53:37.862069 RX DATLAT : PASS
3764 22:53:37.865278 RX DQ/DQS(Engine): PASS
3765 22:53:37.865360 TX OE : NO K
3766 22:53:37.868482 All Pass.
3767 22:53:37.868564
3768 22:53:37.868629 CH 1, Rank 0
3769 22:53:37.871689 SW Impedance : PASS
3770 22:53:37.871771 DUTY Scan : NO K
3771 22:53:37.875291 ZQ Calibration : PASS
3772 22:53:37.878719 Jitter Meter : NO K
3773 22:53:37.878801 CBT Training : PASS
3774 22:53:37.882207 Write leveling : PASS
3775 22:53:37.885170 RX DQS gating : PASS
3776 22:53:37.885261 RX DQ/DQS(RDDQC) : PASS
3777 22:53:37.888675 TX DQ/DQS : PASS
3778 22:53:37.891673 RX DATLAT : PASS
3779 22:53:37.891755 RX DQ/DQS(Engine): PASS
3780 22:53:37.895426 TX OE : NO K
3781 22:53:37.895509 All Pass.
3782 22:53:37.895573
3783 22:53:37.898185 CH 1, Rank 1
3784 22:53:37.898267 SW Impedance : PASS
3785 22:53:37.901876 DUTY Scan : NO K
3786 22:53:37.901957 ZQ Calibration : PASS
3787 22:53:37.905539 Jitter Meter : NO K
3788 22:53:37.909076 CBT Training : PASS
3789 22:53:37.909158 Write leveling : PASS
3790 22:53:37.911915 RX DQS gating : PASS
3791 22:53:37.914917 RX DQ/DQS(RDDQC) : PASS
3792 22:53:37.915004 TX DQ/DQS : PASS
3793 22:53:37.918467 RX DATLAT : PASS
3794 22:53:37.921906 RX DQ/DQS(Engine): PASS
3795 22:53:37.921988 TX OE : NO K
3796 22:53:37.925258 All Pass.
3797 22:53:37.925340
3798 22:53:37.925405 DramC Write-DBI off
3799 22:53:37.928571 PER_BANK_REFRESH: Hybrid Mode
3800 22:53:37.928653 TX_TRACKING: ON
3801 22:53:37.938557 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3802 22:53:37.941860 [FAST_K] Save calibration result to emmc
3803 22:53:37.945609 dramc_set_vcore_voltage set vcore to 650000
3804 22:53:37.948910 Read voltage for 600, 5
3805 22:53:37.948992 Vio18 = 0
3806 22:53:37.952038 Vcore = 650000
3807 22:53:37.952121 Vdram = 0
3808 22:53:37.952185 Vddq = 0
3809 22:53:37.952246 Vmddr = 0
3810 22:53:37.958495 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3811 22:53:37.965405 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3812 22:53:37.965488 MEM_TYPE=3, freq_sel=19
3813 22:53:37.968903 sv_algorithm_assistance_LP4_1600
3814 22:53:37.971687 ============ PULL DRAM RESETB DOWN ============
3815 22:53:37.978730 ========== PULL DRAM RESETB DOWN end =========
3816 22:53:37.981912 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3817 22:53:37.985131 ===================================
3818 22:53:37.988546 LPDDR4 DRAM CONFIGURATION
3819 22:53:37.992423 ===================================
3820 22:53:37.992506 EX_ROW_EN[0] = 0x0
3821 22:53:37.995756 EX_ROW_EN[1] = 0x0
3822 22:53:37.995837 LP4Y_EN = 0x0
3823 22:53:37.998643 WORK_FSP = 0x0
3824 22:53:37.998726 WL = 0x2
3825 22:53:38.002114 RL = 0x2
3826 22:53:38.002196 BL = 0x2
3827 22:53:38.005529 RPST = 0x0
3828 22:53:38.005611 RD_PRE = 0x0
3829 22:53:38.009113 WR_PRE = 0x1
3830 22:53:38.009219 WR_PST = 0x0
3831 22:53:38.011918 DBI_WR = 0x0
3832 22:53:38.012018 DBI_RD = 0x0
3833 22:53:38.015474 OTF = 0x1
3834 22:53:38.018911 ===================================
3835 22:53:38.021984 ===================================
3836 22:53:38.022068 ANA top config
3837 22:53:38.025399 ===================================
3838 22:53:38.028600 DLL_ASYNC_EN = 0
3839 22:53:38.032229 ALL_SLAVE_EN = 1
3840 22:53:38.035367 NEW_RANK_MODE = 1
3841 22:53:38.035450 DLL_IDLE_MODE = 1
3842 22:53:38.038753 LP45_APHY_COMB_EN = 1
3843 22:53:38.042257 TX_ODT_DIS = 1
3844 22:53:38.045257 NEW_8X_MODE = 1
3845 22:53:38.049108 ===================================
3846 22:53:38.051992 ===================================
3847 22:53:38.055528 data_rate = 1200
3848 22:53:38.058488 CKR = 1
3849 22:53:38.058571 DQ_P2S_RATIO = 8
3850 22:53:38.062120 ===================================
3851 22:53:38.065595 CA_P2S_RATIO = 8
3852 22:53:38.068832 DQ_CA_OPEN = 0
3853 22:53:38.072177 DQ_SEMI_OPEN = 0
3854 22:53:38.075527 CA_SEMI_OPEN = 0
3855 22:53:38.075609 CA_FULL_RATE = 0
3856 22:53:38.079020 DQ_CKDIV4_EN = 1
3857 22:53:38.081897 CA_CKDIV4_EN = 1
3858 22:53:38.085605 CA_PREDIV_EN = 0
3859 22:53:38.088863 PH8_DLY = 0
3860 22:53:38.091792 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3861 22:53:38.091875 DQ_AAMCK_DIV = 4
3862 22:53:38.095402 CA_AAMCK_DIV = 4
3863 22:53:38.098889 CA_ADMCK_DIV = 4
3864 22:53:38.101981 DQ_TRACK_CA_EN = 0
3865 22:53:38.105765 CA_PICK = 600
3866 22:53:38.108849 CA_MCKIO = 600
3867 22:53:38.108931 MCKIO_SEMI = 0
3868 22:53:38.111993 PLL_FREQ = 2288
3869 22:53:38.115811 DQ_UI_PI_RATIO = 32
3870 22:53:38.118668 CA_UI_PI_RATIO = 0
3871 22:53:38.122084 ===================================
3872 22:53:38.125674 ===================================
3873 22:53:38.129165 memory_type:LPDDR4
3874 22:53:38.129284 GP_NUM : 10
3875 22:53:38.132085 SRAM_EN : 1
3876 22:53:38.135242 MD32_EN : 0
3877 22:53:38.138717 ===================================
3878 22:53:38.138799 [ANA_INIT] >>>>>>>>>>>>>>
3879 22:53:38.142224 <<<<<< [CONFIGURE PHASE]: ANA_TX
3880 22:53:38.145993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3881 22:53:38.148740 ===================================
3882 22:53:38.152286 data_rate = 1200,PCW = 0X5800
3883 22:53:38.155399 ===================================
3884 22:53:38.158904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3885 22:53:38.165180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3886 22:53:38.169125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3887 22:53:38.175598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3888 22:53:38.178890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3889 22:53:38.182023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3890 22:53:38.182106 [ANA_INIT] flow start
3891 22:53:38.185564 [ANA_INIT] PLL >>>>>>>>
3892 22:53:38.188561 [ANA_INIT] PLL <<<<<<<<
3893 22:53:38.188643 [ANA_INIT] MIDPI >>>>>>>>
3894 22:53:38.192475 [ANA_INIT] MIDPI <<<<<<<<
3895 22:53:38.195292 [ANA_INIT] DLL >>>>>>>>
3896 22:53:38.195374 [ANA_INIT] flow end
3897 22:53:38.201867 ============ LP4 DIFF to SE enter ============
3898 22:53:38.205160 ============ LP4 DIFF to SE exit ============
3899 22:53:38.208517 [ANA_INIT] <<<<<<<<<<<<<
3900 22:53:38.212176 [Flow] Enable top DCM control >>>>>
3901 22:53:38.215599 [Flow] Enable top DCM control <<<<<
3902 22:53:38.215686 Enable DLL master slave shuffle
3903 22:53:38.221804 ==============================================================
3904 22:53:38.225358 Gating Mode config
3905 22:53:38.228821 ==============================================================
3906 22:53:38.231896 Config description:
3907 22:53:38.242250 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3908 22:53:38.248640 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3909 22:53:38.251953 SELPH_MODE 0: By rank 1: By Phase
3910 22:53:38.258773 ==============================================================
3911 22:53:38.262092 GAT_TRACK_EN = 1
3912 22:53:38.265184 RX_GATING_MODE = 2
3913 22:53:38.268713 RX_GATING_TRACK_MODE = 2
3914 22:53:38.271660 SELPH_MODE = 1
3915 22:53:38.271745 PICG_EARLY_EN = 1
3916 22:53:38.275073 VALID_LAT_VALUE = 1
3917 22:53:38.282177 ==============================================================
3918 22:53:38.284896 Enter into Gating configuration >>>>
3919 22:53:38.288664 Exit from Gating configuration <<<<
3920 22:53:38.291759 Enter into DVFS_PRE_config >>>>>
3921 22:53:38.301610 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3922 22:53:38.305278 Exit from DVFS_PRE_config <<<<<
3923 22:53:38.308405 Enter into PICG configuration >>>>
3924 22:53:38.311954 Exit from PICG configuration <<<<
3925 22:53:38.315658 [RX_INPUT] configuration >>>>>
3926 22:53:38.318503 [RX_INPUT] configuration <<<<<
3927 22:53:38.322292 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3928 22:53:38.328751 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3929 22:53:38.335136 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3930 22:53:38.341714 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3931 22:53:38.344867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3932 22:53:38.351806 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3933 22:53:38.355443 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3934 22:53:38.361758 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3935 22:53:38.365268 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3936 22:53:38.368570 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3937 22:53:38.372332 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3938 22:53:38.378524 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3939 22:53:38.381894 ===================================
3940 22:53:38.381998 LPDDR4 DRAM CONFIGURATION
3941 22:53:38.385093 ===================================
3942 22:53:38.388779 EX_ROW_EN[0] = 0x0
3943 22:53:38.391664 EX_ROW_EN[1] = 0x0
3944 22:53:38.391747 LP4Y_EN = 0x0
3945 22:53:38.395096 WORK_FSP = 0x0
3946 22:53:38.395179 WL = 0x2
3947 22:53:38.398701 RL = 0x2
3948 22:53:38.398784 BL = 0x2
3949 22:53:38.402149 RPST = 0x0
3950 22:53:38.402231 RD_PRE = 0x0
3951 22:53:38.405437 WR_PRE = 0x1
3952 22:53:38.405519 WR_PST = 0x0
3953 22:53:38.408678 DBI_WR = 0x0
3954 22:53:38.408759 DBI_RD = 0x0
3955 22:53:38.411721 OTF = 0x1
3956 22:53:38.415446 ===================================
3957 22:53:38.418510 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3958 22:53:38.421482 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3959 22:53:38.428779 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3960 22:53:38.431513 ===================================
3961 22:53:38.431596 LPDDR4 DRAM CONFIGURATION
3962 22:53:38.435067 ===================================
3963 22:53:38.438288 EX_ROW_EN[0] = 0x10
3964 22:53:38.441793 EX_ROW_EN[1] = 0x0
3965 22:53:38.441875 LP4Y_EN = 0x0
3966 22:53:38.445114 WORK_FSP = 0x0
3967 22:53:38.445196 WL = 0x2
3968 22:53:38.448638 RL = 0x2
3969 22:53:38.448737 BL = 0x2
3970 22:53:38.451300 RPST = 0x0
3971 22:53:38.451382 RD_PRE = 0x0
3972 22:53:38.454910 WR_PRE = 0x1
3973 22:53:38.454992 WR_PST = 0x0
3974 22:53:38.458024 DBI_WR = 0x0
3975 22:53:38.458106 DBI_RD = 0x0
3976 22:53:38.461262 OTF = 0x1
3977 22:53:38.464921 ===================================
3978 22:53:38.471272 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3979 22:53:38.474873 nWR fixed to 30
3980 22:53:38.474956 [ModeRegInit_LP4] CH0 RK0
3981 22:53:38.478210 [ModeRegInit_LP4] CH0 RK1
3982 22:53:38.481281 [ModeRegInit_LP4] CH1 RK0
3983 22:53:38.484546 [ModeRegInit_LP4] CH1 RK1
3984 22:53:38.484629 match AC timing 17
3985 22:53:38.488078 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3986 22:53:38.494662 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3987 22:53:38.497966 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3988 22:53:38.504529 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3989 22:53:38.507699 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3990 22:53:38.507781 ==
3991 22:53:38.511709 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 22:53:38.514885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 22:53:38.514969 ==
3994 22:53:38.521233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3995 22:53:38.527632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3996 22:53:38.531882 [CA 0] Center 36 (6~66) winsize 61
3997 22:53:38.534932 [CA 1] Center 36 (6~66) winsize 61
3998 22:53:38.537687 [CA 2] Center 34 (4~64) winsize 61
3999 22:53:38.541151 [CA 3] Center 34 (4~64) winsize 61
4000 22:53:38.544555 [CA 4] Center 33 (3~64) winsize 62
4001 22:53:38.548271 [CA 5] Center 33 (3~64) winsize 62
4002 22:53:38.548353
4003 22:53:38.551161 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4004 22:53:38.551243
4005 22:53:38.554878 [CATrainingPosCal] consider 1 rank data
4006 22:53:38.558109 u2DelayCellTimex100 = 270/100 ps
4007 22:53:38.561185 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4008 22:53:38.564707 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4009 22:53:38.567788 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4010 22:53:38.571153 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4011 22:53:38.574776 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4012 22:53:38.577711 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 22:53:38.577794
4014 22:53:38.580959 CA PerBit enable=1, Macro0, CA PI delay=33
4015 22:53:38.584674
4016 22:53:38.584756 [CBTSetCACLKResult] CA Dly = 33
4017 22:53:38.587621 CS Dly: 5 (0~36)
4018 22:53:38.587703 ==
4019 22:53:38.591757 Dram Type= 6, Freq= 0, CH_0, rank 1
4020 22:53:38.594123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 22:53:38.594205 ==
4022 22:53:38.600716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4023 22:53:38.607668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4024 22:53:38.611469 [CA 0] Center 36 (6~66) winsize 61
4025 22:53:38.614533 [CA 1] Center 36 (6~66) winsize 61
4026 22:53:38.617688 [CA 2] Center 34 (4~65) winsize 62
4027 22:53:38.621503 [CA 3] Center 34 (4~65) winsize 62
4028 22:53:38.624146 [CA 4] Center 33 (3~64) winsize 62
4029 22:53:38.627988 [CA 5] Center 33 (3~64) winsize 62
4030 22:53:38.628085
4031 22:53:38.631343 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4032 22:53:38.631425
4033 22:53:38.634201 [CATrainingPosCal] consider 2 rank data
4034 22:53:38.637675 u2DelayCellTimex100 = 270/100 ps
4035 22:53:38.641146 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4036 22:53:38.644372 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4037 22:53:38.647747 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4038 22:53:38.651076 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4039 22:53:38.654548 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4040 22:53:38.657743 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4041 22:53:38.657826
4042 22:53:38.661087 CA PerBit enable=1, Macro0, CA PI delay=33
4043 22:53:38.664861
4044 22:53:38.664942 [CBTSetCACLKResult] CA Dly = 33
4045 22:53:38.668465 CS Dly: 5 (0~37)
4046 22:53:38.668547
4047 22:53:38.671404 ----->DramcWriteLeveling(PI) begin...
4048 22:53:38.671488 ==
4049 22:53:38.674987 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 22:53:38.678050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 22:53:38.678133 ==
4052 22:53:38.681586 Write leveling (Byte 0): 32 => 32
4053 22:53:38.684848 Write leveling (Byte 1): 29 => 29
4054 22:53:38.687834 DramcWriteLeveling(PI) end<-----
4055 22:53:38.687917
4056 22:53:38.688008 ==
4057 22:53:38.691687 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 22:53:38.695100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 22:53:38.695183 ==
4060 22:53:38.698072 [Gating] SW mode calibration
4061 22:53:38.704830 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4062 22:53:38.711701 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4063 22:53:38.714894 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4064 22:53:38.718316 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4065 22:53:38.724688 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4066 22:53:38.728107 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 22:53:38.731448 0 9 16 | B1->B0 | 3232 2c2c | 0 1 | (0 0) (1 0)
4068 22:53:38.737974 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4069 22:53:38.742005 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 22:53:38.744916 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 22:53:38.751967 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 22:53:38.755604 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 22:53:38.758071 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 22:53:38.765017 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 22:53:38.767956 0 10 16 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
4076 22:53:38.771269 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4077 22:53:38.778112 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 22:53:38.781551 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 22:53:38.785136 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 22:53:38.791532 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 22:53:38.795243 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 22:53:38.797974 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 22:53:38.804562 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4084 22:53:38.808082 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4085 22:53:38.811410 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 22:53:38.814681 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 22:53:38.821413 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 22:53:38.824994 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 22:53:38.828235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 22:53:38.834881 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 22:53:38.838277 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 22:53:38.841617 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 22:53:38.847891 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 22:53:38.851306 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 22:53:38.854751 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 22:53:38.861648 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 22:53:38.865020 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 22:53:38.868230 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 22:53:38.874904 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4100 22:53:38.874987 Total UI for P1: 0, mck2ui 16
4101 22:53:38.881615 best dqsien dly found for B1: ( 0, 13, 14)
4102 22:53:38.884946 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 22:53:38.888793 Total UI for P1: 0, mck2ui 16
4104 22:53:38.891838 best dqsien dly found for B0: ( 0, 13, 16)
4105 22:53:38.895381 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4106 22:53:38.898880 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4107 22:53:38.898963
4108 22:53:38.901822 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4109 22:53:38.904936 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4110 22:53:38.908161 [Gating] SW calibration Done
4111 22:53:38.908243 ==
4112 22:53:38.911381 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 22:53:38.915213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 22:53:38.915295 ==
4115 22:53:38.918182 RX Vref Scan: 0
4116 22:53:38.918264
4117 22:53:38.921603 RX Vref 0 -> 0, step: 1
4118 22:53:38.921685
4119 22:53:38.921750 RX Delay -230 -> 252, step: 16
4120 22:53:38.928922 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4121 22:53:38.931399 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4122 22:53:38.934798 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4123 22:53:38.938085 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4124 22:53:38.945021 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4125 22:53:38.948703 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4126 22:53:38.951466 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4127 22:53:38.954829 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4128 22:53:38.958222 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4129 22:53:38.965357 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4130 22:53:38.968386 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4131 22:53:38.971569 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4132 22:53:38.975183 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4133 22:53:38.981121 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4134 22:53:38.984623 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4135 22:53:38.988269 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4136 22:53:38.988353 ==
4137 22:53:38.991249 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 22:53:38.994568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 22:53:38.997904 ==
4140 22:53:38.997986 DQS Delay:
4141 22:53:38.998052 DQS0 = 0, DQS1 = 0
4142 22:53:39.001823 DQM Delay:
4143 22:53:39.001905 DQM0 = 41, DQM1 = 32
4144 22:53:39.004848 DQ Delay:
4145 22:53:39.008103 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4146 22:53:39.008185 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4147 22:53:39.011454 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4148 22:53:39.015078 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4149 22:53:39.015160
4150 22:53:39.017930
4151 22:53:39.018012 ==
4152 22:53:39.021548 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 22:53:39.024592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 22:53:39.024675 ==
4155 22:53:39.024740
4156 22:53:39.024800
4157 22:53:39.028186 TX Vref Scan disable
4158 22:53:39.028269 == TX Byte 0 ==
4159 22:53:39.034539 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4160 22:53:39.038477 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4161 22:53:39.038559 == TX Byte 1 ==
4162 22:53:39.044723 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4163 22:53:39.048040 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4164 22:53:39.048123 ==
4165 22:53:39.051083 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 22:53:39.055370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 22:53:39.055452 ==
4168 22:53:39.055517
4169 22:53:39.055577
4170 22:53:39.058326 TX Vref Scan disable
4171 22:53:39.061875 == TX Byte 0 ==
4172 22:53:39.064789 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4173 22:53:39.067923 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4174 22:53:39.071466 == TX Byte 1 ==
4175 22:53:39.075103 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4176 22:53:39.077934 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4177 22:53:39.078016
4178 22:53:39.081511 [DATLAT]
4179 22:53:39.081594 Freq=600, CH0 RK0
4180 22:53:39.081659
4181 22:53:39.084825 DATLAT Default: 0x9
4182 22:53:39.084933 0, 0xFFFF, sum = 0
4183 22:53:39.087828 1, 0xFFFF, sum = 0
4184 22:53:39.087912 2, 0xFFFF, sum = 0
4185 22:53:39.091289 3, 0xFFFF, sum = 0
4186 22:53:39.091438 4, 0xFFFF, sum = 0
4187 22:53:39.094715 5, 0xFFFF, sum = 0
4188 22:53:39.094799 6, 0xFFFF, sum = 0
4189 22:53:39.098030 7, 0xFFFF, sum = 0
4190 22:53:39.098114 8, 0x0, sum = 1
4191 22:53:39.101154 9, 0x0, sum = 2
4192 22:53:39.101282 10, 0x0, sum = 3
4193 22:53:39.104711 11, 0x0, sum = 4
4194 22:53:39.104794 best_step = 9
4195 22:53:39.104859
4196 22:53:39.104920 ==
4197 22:53:39.108508 Dram Type= 6, Freq= 0, CH_0, rank 0
4198 22:53:39.111449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 22:53:39.114944 ==
4200 22:53:39.115027 RX Vref Scan: 1
4201 22:53:39.115091
4202 22:53:39.118461 RX Vref 0 -> 0, step: 1
4203 22:53:39.118543
4204 22:53:39.121327 RX Delay -195 -> 252, step: 8
4205 22:53:39.121410
4206 22:53:39.124976 Set Vref, RX VrefLevel [Byte0]: 53
4207 22:53:39.127892 [Byte1]: 51
4208 22:53:39.127975
4209 22:53:39.131164 Final RX Vref Byte 0 = 53 to rank0
4210 22:53:39.134287 Final RX Vref Byte 1 = 51 to rank0
4211 22:53:39.137999 Final RX Vref Byte 0 = 53 to rank1
4212 22:53:39.141778 Final RX Vref Byte 1 = 51 to rank1==
4213 22:53:39.144888 Dram Type= 6, Freq= 0, CH_0, rank 0
4214 22:53:39.147559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 22:53:39.147642 ==
4216 22:53:39.151140 DQS Delay:
4217 22:53:39.151222 DQS0 = 0, DQS1 = 0
4218 22:53:39.151287 DQM Delay:
4219 22:53:39.155052 DQM0 = 41, DQM1 = 33
4220 22:53:39.155135 DQ Delay:
4221 22:53:39.157592 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4222 22:53:39.161139 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4223 22:53:39.164387 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4224 22:53:39.167955 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4225 22:53:39.168038
4226 22:53:39.168102
4227 22:53:39.177690 [DQSOSCAuto] RK0, (LSB)MR18= 0x4121, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4228 22:53:39.177774 CH0 RK0: MR19=808, MR18=4121
4229 22:53:39.184402 CH0_RK0: MR19=0x808, MR18=0x4121, DQSOSC=397, MR23=63, INC=166, DEC=110
4230 22:53:39.184485
4231 22:53:39.187610 ----->DramcWriteLeveling(PI) begin...
4232 22:53:39.187695 ==
4233 22:53:39.191127 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 22:53:39.197953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 22:53:39.198036 ==
4236 22:53:39.202190 Write leveling (Byte 0): 32 => 32
4237 22:53:39.202273 Write leveling (Byte 1): 31 => 31
4238 22:53:39.204522 DramcWriteLeveling(PI) end<-----
4239 22:53:39.204604
4240 22:53:39.208192 ==
4241 22:53:39.208275 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 22:53:39.214796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 22:53:39.214878 ==
4244 22:53:39.217696 [Gating] SW mode calibration
4245 22:53:39.224432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4246 22:53:39.228003 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4247 22:53:39.234457 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4248 22:53:39.237874 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4249 22:53:39.241687 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 22:53:39.247767 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
4251 22:53:39.251261 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4252 22:53:39.254802 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 22:53:39.261056 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 22:53:39.264539 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 22:53:39.268304 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 22:53:39.271037 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 22:53:39.278041 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 22:53:39.281856 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4259 22:53:39.284715 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4260 22:53:39.291527 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4261 22:53:39.294329 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 22:53:39.297891 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 22:53:39.304578 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 22:53:39.307795 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 22:53:39.311323 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 22:53:39.317717 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4267 22:53:39.321194 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4268 22:53:39.324664 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 22:53:39.331527 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 22:53:39.334424 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 22:53:39.338150 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 22:53:39.344632 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 22:53:39.348304 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 22:53:39.351271 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 22:53:39.354788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 22:53:39.361075 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 22:53:39.364608 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 22:53:39.368069 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 22:53:39.374854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 22:53:39.378015 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 22:53:39.381386 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 22:53:39.388201 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4283 22:53:39.391232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4284 22:53:39.394596 Total UI for P1: 0, mck2ui 16
4285 22:53:39.398366 best dqsien dly found for B0: ( 0, 13, 12)
4286 22:53:39.401885 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 22:53:39.404535 Total UI for P1: 0, mck2ui 16
4288 22:53:39.408705 best dqsien dly found for B1: ( 0, 13, 14)
4289 22:53:39.411700 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4290 22:53:39.414975 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4291 22:53:39.415058
4292 22:53:39.421250 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4293 22:53:39.424989 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4294 22:53:39.425139 [Gating] SW calibration Done
4295 22:53:39.428020 ==
4296 22:53:39.431660 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 22:53:39.434794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 22:53:39.434878 ==
4299 22:53:39.434943 RX Vref Scan: 0
4300 22:53:39.435003
4301 22:53:39.438093 RX Vref 0 -> 0, step: 1
4302 22:53:39.438175
4303 22:53:39.442020 RX Delay -230 -> 252, step: 16
4304 22:53:39.444712 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4305 22:53:39.448526 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4306 22:53:39.454509 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4307 22:53:39.458444 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4308 22:53:39.461503 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4309 22:53:39.465066 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4310 22:53:39.468213 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4311 22:53:39.475129 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4312 22:53:39.477994 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4313 22:53:39.481412 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4314 22:53:39.485082 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4315 22:53:39.491715 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4316 22:53:39.494758 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4317 22:53:39.498475 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4318 22:53:39.501251 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4319 22:53:39.508032 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4320 22:53:39.508115 ==
4321 22:53:39.511854 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 22:53:39.514936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 22:53:39.515019 ==
4324 22:53:39.515085 DQS Delay:
4325 22:53:39.517978 DQS0 = 0, DQS1 = 0
4326 22:53:39.518061 DQM Delay:
4327 22:53:39.521740 DQM0 = 39, DQM1 = 31
4328 22:53:39.521823 DQ Delay:
4329 22:53:39.525117 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4330 22:53:39.528518 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4331 22:53:39.531827 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4332 22:53:39.535140 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4333 22:53:39.535222
4334 22:53:39.535287
4335 22:53:39.535346 ==
4336 22:53:39.538110 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 22:53:39.541740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 22:53:39.541824 ==
4339 22:53:39.541888
4340 22:53:39.541985
4341 22:53:39.545683 TX Vref Scan disable
4342 22:53:39.548350 == TX Byte 0 ==
4343 22:53:39.551519 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4344 22:53:39.554698 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4345 22:53:39.557984 == TX Byte 1 ==
4346 22:53:39.561768 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4347 22:53:39.564690 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4348 22:53:39.564798 ==
4349 22:53:39.568664 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 22:53:39.571772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 22:53:39.574830 ==
4352 22:53:39.574913
4353 22:53:39.574977
4354 22:53:39.575039 TX Vref Scan disable
4355 22:53:39.578725 == TX Byte 0 ==
4356 22:53:39.581981 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4357 22:53:39.585362 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4358 22:53:39.588985 == TX Byte 1 ==
4359 22:53:39.592034 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4360 22:53:39.595744 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4361 22:53:39.599169
4362 22:53:39.599251 [DATLAT]
4363 22:53:39.599316 Freq=600, CH0 RK1
4364 22:53:39.599377
4365 22:53:39.602245 DATLAT Default: 0x9
4366 22:53:39.602326 0, 0xFFFF, sum = 0
4367 22:53:39.605567 1, 0xFFFF, sum = 0
4368 22:53:39.605649 2, 0xFFFF, sum = 0
4369 22:53:39.608950 3, 0xFFFF, sum = 0
4370 22:53:39.609033 4, 0xFFFF, sum = 0
4371 22:53:39.612266 5, 0xFFFF, sum = 0
4372 22:53:39.615892 6, 0xFFFF, sum = 0
4373 22:53:39.615985 7, 0xFFFF, sum = 0
4374 22:53:39.616057 8, 0x0, sum = 1
4375 22:53:39.618843 9, 0x0, sum = 2
4376 22:53:39.618926 10, 0x0, sum = 3
4377 22:53:39.622237 11, 0x0, sum = 4
4378 22:53:39.622320 best_step = 9
4379 22:53:39.622384
4380 22:53:39.622443 ==
4381 22:53:39.625369 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 22:53:39.632142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 22:53:39.632250 ==
4384 22:53:39.632344 RX Vref Scan: 0
4385 22:53:39.632433
4386 22:53:39.635723 RX Vref 0 -> 0, step: 1
4387 22:53:39.635804
4388 22:53:39.639243 RX Delay -195 -> 252, step: 8
4389 22:53:39.642290 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4390 22:53:39.649118 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4391 22:53:39.652194 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4392 22:53:39.656404 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4393 22:53:39.659083 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4394 22:53:39.662489 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4395 22:53:39.668813 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4396 22:53:39.672715 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4397 22:53:39.675476 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4398 22:53:39.678898 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4399 22:53:39.682230 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4400 22:53:39.688994 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4401 22:53:39.692088 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4402 22:53:39.695859 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4403 22:53:39.699158 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4404 22:53:39.705092 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4405 22:53:39.705200 ==
4406 22:53:39.709031 Dram Type= 6, Freq= 0, CH_0, rank 1
4407 22:53:39.712143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 22:53:39.712225 ==
4409 22:53:39.712290 DQS Delay:
4410 22:53:39.715381 DQS0 = 0, DQS1 = 0
4411 22:53:39.715462 DQM Delay:
4412 22:53:39.718810 DQM0 = 39, DQM1 = 33
4413 22:53:39.718892 DQ Delay:
4414 22:53:39.722080 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4415 22:53:39.725718 DQ4 =36, DQ5 =28, DQ6 =52, DQ7 =44
4416 22:53:39.728933 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =20
4417 22:53:39.732029 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4418 22:53:39.732112
4419 22:53:39.732176
4420 22:53:39.738672 [DQSOSCAuto] RK1, (LSB)MR18= 0x4628, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4421 22:53:39.742382 CH0 RK1: MR19=808, MR18=4628
4422 22:53:39.748913 CH0_RK1: MR19=0x808, MR18=0x4628, DQSOSC=396, MR23=63, INC=167, DEC=111
4423 22:53:39.751864 [RxdqsGatingPostProcess] freq 600
4424 22:53:39.758638 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4425 22:53:39.762154 Pre-setting of DQS Precalculation
4426 22:53:39.765747 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4427 22:53:39.765830 ==
4428 22:53:39.769052 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 22:53:39.772000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 22:53:39.772083 ==
4431 22:53:39.778827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 22:53:39.785855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4433 22:53:39.788595 [CA 0] Center 35 (5~66) winsize 62
4434 22:53:39.791975 [CA 1] Center 35 (5~66) winsize 62
4435 22:53:39.795270 [CA 2] Center 34 (3~65) winsize 63
4436 22:53:39.798657 [CA 3] Center 33 (3~64) winsize 62
4437 22:53:39.802389 [CA 4] Center 34 (3~65) winsize 63
4438 22:53:39.805581 [CA 5] Center 33 (3~64) winsize 62
4439 22:53:39.805663
4440 22:53:39.808885 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4441 22:53:39.808967
4442 22:53:39.812156 [CATrainingPosCal] consider 1 rank data
4443 22:53:39.815913 u2DelayCellTimex100 = 270/100 ps
4444 22:53:39.818663 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4445 22:53:39.822310 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4446 22:53:39.825688 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4447 22:53:39.828695 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4448 22:53:39.832247 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4449 22:53:39.835593 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 22:53:39.838751
4451 22:53:39.841984 CA PerBit enable=1, Macro0, CA PI delay=33
4452 22:53:39.842067
4453 22:53:39.845452 [CBTSetCACLKResult] CA Dly = 33
4454 22:53:39.845534 CS Dly: 4 (0~35)
4455 22:53:39.845600 ==
4456 22:53:39.848734 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 22:53:39.852209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 22:53:39.852292 ==
4459 22:53:39.858858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4460 22:53:39.865516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4461 22:53:39.868705 [CA 0] Center 35 (5~66) winsize 62
4462 22:53:39.871843 [CA 1] Center 35 (5~66) winsize 62
4463 22:53:39.875351 [CA 2] Center 34 (4~65) winsize 62
4464 22:53:39.878667 [CA 3] Center 33 (3~64) winsize 62
4465 22:53:39.882466 [CA 4] Center 34 (3~65) winsize 63
4466 22:53:39.885521 [CA 5] Center 33 (3~64) winsize 62
4467 22:53:39.885604
4468 22:53:39.888698 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4469 22:53:39.888780
4470 22:53:39.892192 [CATrainingPosCal] consider 2 rank data
4471 22:53:39.895836 u2DelayCellTimex100 = 270/100 ps
4472 22:53:39.898757 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4473 22:53:39.902548 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4474 22:53:39.905688 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4475 22:53:39.908734 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4476 22:53:39.911885 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4477 22:53:39.918899 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4478 22:53:39.918982
4479 22:53:39.922095 CA PerBit enable=1, Macro0, CA PI delay=33
4480 22:53:39.922178
4481 22:53:39.925591 [CBTSetCACLKResult] CA Dly = 33
4482 22:53:39.925674 CS Dly: 4 (0~36)
4483 22:53:39.925739
4484 22:53:39.929033 ----->DramcWriteLeveling(PI) begin...
4485 22:53:39.929117 ==
4486 22:53:39.932133 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 22:53:39.935300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 22:53:39.939015 ==
4489 22:53:39.939097 Write leveling (Byte 0): 30 => 30
4490 22:53:39.941946 Write leveling (Byte 1): 31 => 31
4491 22:53:39.945757 DramcWriteLeveling(PI) end<-----
4492 22:53:39.945839
4493 22:53:39.945903 ==
4494 22:53:39.948705 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 22:53:39.955585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 22:53:39.955668 ==
4497 22:53:39.955733 [Gating] SW mode calibration
4498 22:53:39.965349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4499 22:53:39.968726 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4500 22:53:39.972160 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4501 22:53:39.978784 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4502 22:53:39.982290 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4503 22:53:39.985212 0 9 12 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
4504 22:53:39.992036 0 9 16 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (0 0)
4505 22:53:39.995822 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 22:53:39.998642 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 22:53:40.005761 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 22:53:40.009021 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4509 22:53:40.012689 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 22:53:40.018919 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 22:53:40.022022 0 10 12 | B1->B0 | 2727 2d2d | 0 0 | (0 0) (0 0)
4512 22:53:40.025416 0 10 16 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
4513 22:53:40.032208 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 22:53:40.035382 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 22:53:40.038777 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 22:53:40.045220 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 22:53:40.048873 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 22:53:40.052293 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 22:53:40.058708 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 22:53:40.061919 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 22:53:40.065726 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 22:53:40.069001 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 22:53:40.075288 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 22:53:40.078656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 22:53:40.081955 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 22:53:40.088688 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 22:53:40.091825 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 22:53:40.095071 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 22:53:40.102017 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 22:53:40.105043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 22:53:40.108745 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 22:53:40.115303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 22:53:40.118377 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 22:53:40.122174 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 22:53:40.128712 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 22:53:40.132023 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 22:53:40.135132 Total UI for P1: 0, mck2ui 16
4538 22:53:40.138984 best dqsien dly found for B0: ( 0, 13, 14)
4539 22:53:40.141891 Total UI for P1: 0, mck2ui 16
4540 22:53:40.145535 best dqsien dly found for B1: ( 0, 13, 14)
4541 22:53:40.148491 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4542 22:53:40.152187 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4543 22:53:40.152270
4544 22:53:40.155301 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4545 22:53:40.158770 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4546 22:53:40.162305 [Gating] SW calibration Done
4547 22:53:40.162387 ==
4548 22:53:40.165494 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 22:53:40.168765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 22:53:40.168847 ==
4551 22:53:40.172572 RX Vref Scan: 0
4552 22:53:40.172654
4553 22:53:40.175134 RX Vref 0 -> 0, step: 1
4554 22:53:40.175217
4555 22:53:40.175282 RX Delay -230 -> 252, step: 16
4556 22:53:40.182501 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4557 22:53:40.185373 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4558 22:53:40.189148 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4559 22:53:40.192423 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4560 22:53:40.198984 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4561 22:53:40.202285 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4562 22:53:40.205555 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4563 22:53:40.208822 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4564 22:53:40.212165 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4565 22:53:40.219027 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4566 22:53:40.222350 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4567 22:53:40.225650 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4568 22:53:40.228820 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4569 22:53:40.235279 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4570 22:53:40.238859 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4571 22:53:40.242155 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4572 22:53:40.242238 ==
4573 22:53:40.245758 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 22:53:40.248778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 22:53:40.252172 ==
4576 22:53:40.252255 DQS Delay:
4577 22:53:40.252320 DQS0 = 0, DQS1 = 0
4578 22:53:40.255528 DQM Delay:
4579 22:53:40.255610 DQM0 = 45, DQM1 = 36
4580 22:53:40.258760 DQ Delay:
4581 22:53:40.258842 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4582 22:53:40.262302 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4583 22:53:40.265531 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4584 22:53:40.268944 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4585 22:53:40.269027
4586 22:53:40.269091
4587 22:53:40.272300 ==
4588 22:53:40.272382 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 22:53:40.279455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 22:53:40.279538 ==
4591 22:53:40.279603
4592 22:53:40.279664
4593 22:53:40.282188 TX Vref Scan disable
4594 22:53:40.282270 == TX Byte 0 ==
4595 22:53:40.285464 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4596 22:53:40.291909 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4597 22:53:40.291991 == TX Byte 1 ==
4598 22:53:40.295834 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4599 22:53:40.302093 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4600 22:53:40.302176 ==
4601 22:53:40.305860 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 22:53:40.309059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 22:53:40.309168 ==
4604 22:53:40.309255
4605 22:53:40.309318
4606 22:53:40.312789 TX Vref Scan disable
4607 22:53:40.315640 == TX Byte 0 ==
4608 22:53:40.319384 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4609 22:53:40.322091 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4610 22:53:40.325406 == TX Byte 1 ==
4611 22:53:40.328677 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4612 22:53:40.332512 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4613 22:53:40.332595
4614 22:53:40.336061 [DATLAT]
4615 22:53:40.336144 Freq=600, CH1 RK0
4616 22:53:40.336211
4617 22:53:40.339092 DATLAT Default: 0x9
4618 22:53:40.339175 0, 0xFFFF, sum = 0
4619 22:53:40.342548 1, 0xFFFF, sum = 0
4620 22:53:40.342633 2, 0xFFFF, sum = 0
4621 22:53:40.345716 3, 0xFFFF, sum = 0
4622 22:53:40.345806 4, 0xFFFF, sum = 0
4623 22:53:40.349359 5, 0xFFFF, sum = 0
4624 22:53:40.349444 6, 0xFFFF, sum = 0
4625 22:53:40.352548 7, 0xFFFF, sum = 0
4626 22:53:40.352632 8, 0x0, sum = 1
4627 22:53:40.355857 9, 0x0, sum = 2
4628 22:53:40.355941 10, 0x0, sum = 3
4629 22:53:40.359112 11, 0x0, sum = 4
4630 22:53:40.359197 best_step = 9
4631 22:53:40.359262
4632 22:53:40.359322 ==
4633 22:53:40.362653 Dram Type= 6, Freq= 0, CH_1, rank 0
4634 22:53:40.365848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 22:53:40.365948 ==
4636 22:53:40.369250 RX Vref Scan: 1
4637 22:53:40.369333
4638 22:53:40.372755 RX Vref 0 -> 0, step: 1
4639 22:53:40.372868
4640 22:53:40.372932 RX Delay -195 -> 252, step: 8
4641 22:53:40.372993
4642 22:53:40.376353 Set Vref, RX VrefLevel [Byte0]: 57
4643 22:53:40.379097 [Byte1]: 52
4644 22:53:40.383206
4645 22:53:40.383305 Final RX Vref Byte 0 = 57 to rank0
4646 22:53:40.386860 Final RX Vref Byte 1 = 52 to rank0
4647 22:53:40.390150 Final RX Vref Byte 0 = 57 to rank1
4648 22:53:40.393842 Final RX Vref Byte 1 = 52 to rank1==
4649 22:53:40.397011 Dram Type= 6, Freq= 0, CH_1, rank 0
4650 22:53:40.400112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 22:53:40.404521 ==
4652 22:53:40.404629 DQS Delay:
4653 22:53:40.404756 DQS0 = 0, DQS1 = 0
4654 22:53:40.407387 DQM Delay:
4655 22:53:40.407487 DQM0 = 41, DQM1 = 32
4656 22:53:40.410256 DQ Delay:
4657 22:53:40.413875 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4658 22:53:40.413959 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4659 22:53:40.416946 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4660 22:53:40.419973 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4661 22:53:40.423769
4662 22:53:40.423894
4663 22:53:40.430522 [DQSOSCAuto] RK0, (LSB)MR18= 0x4107, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4664 22:53:40.434286 CH1 RK0: MR19=808, MR18=4107
4665 22:53:40.440183 CH1_RK0: MR19=0x808, MR18=0x4107, DQSOSC=397, MR23=63, INC=166, DEC=110
4666 22:53:40.440273
4667 22:53:40.443695 ----->DramcWriteLeveling(PI) begin...
4668 22:53:40.443779 ==
4669 22:53:40.446947 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 22:53:40.450415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 22:53:40.450498 ==
4672 22:53:40.453421 Write leveling (Byte 0): 31 => 31
4673 22:53:40.457238 Write leveling (Byte 1): 32 => 32
4674 22:53:40.460293 DramcWriteLeveling(PI) end<-----
4675 22:53:40.460376
4676 22:53:40.460440 ==
4677 22:53:40.463409 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 22:53:40.466868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 22:53:40.466952 ==
4680 22:53:40.470233 [Gating] SW mode calibration
4681 22:53:40.476667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4682 22:53:40.483652 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4683 22:53:40.487029 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4684 22:53:40.490519 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4685 22:53:40.497460 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4686 22:53:40.500037 0 9 12 | B1->B0 | 3030 2d2d | 1 1 | (0 0) (1 0)
4687 22:53:40.503596 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4688 22:53:40.510220 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 22:53:40.513919 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 22:53:40.516776 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 22:53:40.524122 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 22:53:40.527163 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 22:53:40.530291 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 22:53:40.536975 0 10 12 | B1->B0 | 2d2d 3a3a | 0 1 | (0 0) (0 0)
4695 22:53:40.540525 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4696 22:53:40.543683 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 22:53:40.547409 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 22:53:40.553856 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 22:53:40.557125 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 22:53:40.560357 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 22:53:40.567467 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4702 22:53:40.570323 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4703 22:53:40.573754 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 22:53:40.580246 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 22:53:40.583731 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 22:53:40.587397 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 22:53:40.593846 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 22:53:40.597497 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 22:53:40.600649 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 22:53:40.604284 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 22:53:40.610913 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 22:53:40.614547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 22:53:40.617595 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 22:53:40.624443 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 22:53:40.627736 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 22:53:40.630970 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 22:53:40.637944 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4718 22:53:40.641405 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4719 22:53:40.644545 Total UI for P1: 0, mck2ui 16
4720 22:53:40.647792 best dqsien dly found for B0: ( 0, 13, 8)
4721 22:53:40.651380 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 22:53:40.654086 Total UI for P1: 0, mck2ui 16
4723 22:53:40.657587 best dqsien dly found for B1: ( 0, 13, 14)
4724 22:53:40.660643 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4725 22:53:40.664823 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4726 22:53:40.664905
4727 22:53:40.670892 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4728 22:53:40.674337 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4729 22:53:40.674447 [Gating] SW calibration Done
4730 22:53:40.678078 ==
4731 22:53:40.678161 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 22:53:40.684150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 22:53:40.684233 ==
4734 22:53:40.684298 RX Vref Scan: 0
4735 22:53:40.684359
4736 22:53:40.687735 RX Vref 0 -> 0, step: 1
4737 22:53:40.687818
4738 22:53:40.690975 RX Delay -230 -> 252, step: 16
4739 22:53:40.694436 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4740 22:53:40.698038 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4741 22:53:40.704063 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4742 22:53:40.707428 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4743 22:53:40.710579 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4744 22:53:40.714708 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4745 22:53:40.717608 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4746 22:53:40.724107 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4747 22:53:40.727143 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4748 22:53:40.730532 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4749 22:53:40.734248 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4750 22:53:40.740780 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4751 22:53:40.744159 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4752 22:53:40.747372 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4753 22:53:40.750690 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4754 22:53:40.757171 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4755 22:53:40.757277 ==
4756 22:53:40.760530 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 22:53:40.763856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 22:53:40.763940 ==
4759 22:53:40.764004 DQS Delay:
4760 22:53:40.767311 DQS0 = 0, DQS1 = 0
4761 22:53:40.767393 DQM Delay:
4762 22:53:40.770429 DQM0 = 41, DQM1 = 37
4763 22:53:40.770511 DQ Delay:
4764 22:53:40.773823 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4765 22:53:40.777109 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4766 22:53:40.780870 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4767 22:53:40.783651 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4768 22:53:40.783736
4769 22:53:40.783801
4770 22:53:40.783861 ==
4771 22:53:40.787561 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 22:53:40.790774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 22:53:40.790857 ==
4774 22:53:40.790922
4775 22:53:40.790982
4776 22:53:40.793704 TX Vref Scan disable
4777 22:53:40.797234 == TX Byte 0 ==
4778 22:53:40.800399 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4779 22:53:40.803851 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4780 22:53:40.807469 == TX Byte 1 ==
4781 22:53:40.810692 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4782 22:53:40.813667 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4783 22:53:40.813749 ==
4784 22:53:40.817697 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 22:53:40.821024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 22:53:40.824050 ==
4787 22:53:40.824132
4788 22:53:40.824196
4789 22:53:40.824256 TX Vref Scan disable
4790 22:53:40.827943 == TX Byte 0 ==
4791 22:53:40.831027 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4792 22:53:40.834368 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4793 22:53:40.837871 == TX Byte 1 ==
4794 22:53:40.841377 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4795 22:53:40.844641 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4796 22:53:40.847961
4797 22:53:40.848042 [DATLAT]
4798 22:53:40.848106 Freq=600, CH1 RK1
4799 22:53:40.848167
4800 22:53:40.851872 DATLAT Default: 0x9
4801 22:53:40.851955 0, 0xFFFF, sum = 0
4802 22:53:40.854456 1, 0xFFFF, sum = 0
4803 22:53:40.854539 2, 0xFFFF, sum = 0
4804 22:53:40.858043 3, 0xFFFF, sum = 0
4805 22:53:40.858126 4, 0xFFFF, sum = 0
4806 22:53:40.861244 5, 0xFFFF, sum = 0
4807 22:53:40.861342 6, 0xFFFF, sum = 0
4808 22:53:40.864858 7, 0xFFFF, sum = 0
4809 22:53:40.864980 8, 0x0, sum = 1
4810 22:53:40.868102 9, 0x0, sum = 2
4811 22:53:40.868186 10, 0x0, sum = 3
4812 22:53:40.871821 11, 0x0, sum = 4
4813 22:53:40.871916 best_step = 9
4814 22:53:40.871981
4815 22:53:40.872041 ==
4816 22:53:40.875024 Dram Type= 6, Freq= 0, CH_1, rank 1
4817 22:53:40.881466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4818 22:53:40.881550 ==
4819 22:53:40.881615 RX Vref Scan: 0
4820 22:53:40.881674
4821 22:53:40.884961 RX Vref 0 -> 0, step: 1
4822 22:53:40.885070
4823 22:53:40.888094 RX Delay -179 -> 252, step: 8
4824 22:53:40.891454 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4825 22:53:40.894861 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4826 22:53:40.902244 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4827 22:53:40.904668 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4828 22:53:40.908313 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4829 22:53:40.911504 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4830 22:53:40.915307 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4831 22:53:40.922402 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4832 22:53:40.924807 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4833 22:53:40.928384 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4834 22:53:40.931746 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4835 22:53:40.938254 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4836 22:53:40.941707 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4837 22:53:40.945123 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4838 22:53:40.947888 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4839 22:53:40.954814 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4840 22:53:40.954942 ==
4841 22:53:40.958186 Dram Type= 6, Freq= 0, CH_1, rank 1
4842 22:53:40.961471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4843 22:53:40.961554 ==
4844 22:53:40.961619 DQS Delay:
4845 22:53:40.964754 DQS0 = 0, DQS1 = 0
4846 22:53:40.964852 DQM Delay:
4847 22:53:40.968384 DQM0 = 39, DQM1 = 34
4848 22:53:40.968466 DQ Delay:
4849 22:53:40.971235 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4850 22:53:40.975227 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4851 22:53:40.977929 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4852 22:53:40.981675 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4853 22:53:40.981757
4854 22:53:40.981822
4855 22:53:40.988178 [DQSOSCAuto] RK1, (LSB)MR18= 0x3241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4856 22:53:40.991556 CH1 RK1: MR19=808, MR18=3241
4857 22:53:40.997921 CH1_RK1: MR19=0x808, MR18=0x3241, DQSOSC=397, MR23=63, INC=166, DEC=110
4858 22:53:41.001446 [RxdqsGatingPostProcess] freq 600
4859 22:53:41.007834 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4860 22:53:41.010989 Pre-setting of DQS Precalculation
4861 22:53:41.014329 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4862 22:53:41.020998 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4863 22:53:41.028286 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4864 22:53:41.028369
4865 22:53:41.028433
4866 22:53:41.031140 [Calibration Summary] 1200 Mbps
4867 22:53:41.034771 CH 0, Rank 0
4868 22:53:41.034853 SW Impedance : PASS
4869 22:53:41.038199 DUTY Scan : NO K
4870 22:53:41.041335 ZQ Calibration : PASS
4871 22:53:41.041418 Jitter Meter : NO K
4872 22:53:41.044971 CBT Training : PASS
4873 22:53:41.048321 Write leveling : PASS
4874 22:53:41.048404 RX DQS gating : PASS
4875 22:53:41.051159 RX DQ/DQS(RDDQC) : PASS
4876 22:53:41.051242 TX DQ/DQS : PASS
4877 22:53:41.054704 RX DATLAT : PASS
4878 22:53:41.057713 RX DQ/DQS(Engine): PASS
4879 22:53:41.057795 TX OE : NO K
4880 22:53:41.061108 All Pass.
4881 22:53:41.061239
4882 22:53:41.061321 CH 0, Rank 1
4883 22:53:41.064821 SW Impedance : PASS
4884 22:53:41.064903 DUTY Scan : NO K
4885 22:53:41.067709 ZQ Calibration : PASS
4886 22:53:41.071422 Jitter Meter : NO K
4887 22:53:41.071512 CBT Training : PASS
4888 22:53:41.074667 Write leveling : PASS
4889 22:53:41.077932 RX DQS gating : PASS
4890 22:53:41.078015 RX DQ/DQS(RDDQC) : PASS
4891 22:53:41.081107 TX DQ/DQS : PASS
4892 22:53:41.084706 RX DATLAT : PASS
4893 22:53:41.084789 RX DQ/DQS(Engine): PASS
4894 22:53:41.087955 TX OE : NO K
4895 22:53:41.088038 All Pass.
4896 22:53:41.088103
4897 22:53:41.091458 CH 1, Rank 0
4898 22:53:41.091540 SW Impedance : PASS
4899 22:53:41.095048 DUTY Scan : NO K
4900 22:53:41.098262 ZQ Calibration : PASS
4901 22:53:41.098344 Jitter Meter : NO K
4902 22:53:41.101218 CBT Training : PASS
4903 22:53:41.101315 Write leveling : PASS
4904 22:53:41.104834 RX DQS gating : PASS
4905 22:53:41.108056 RX DQ/DQS(RDDQC) : PASS
4906 22:53:41.108138 TX DQ/DQS : PASS
4907 22:53:41.111550 RX DATLAT : PASS
4908 22:53:41.114826 RX DQ/DQS(Engine): PASS
4909 22:53:41.114908 TX OE : NO K
4910 22:53:41.118213 All Pass.
4911 22:53:41.118294
4912 22:53:41.118359 CH 1, Rank 1
4913 22:53:41.121142 SW Impedance : PASS
4914 22:53:41.121280 DUTY Scan : NO K
4915 22:53:41.124712 ZQ Calibration : PASS
4916 22:53:41.127978 Jitter Meter : NO K
4917 22:53:41.128088 CBT Training : PASS
4918 22:53:41.131448 Write leveling : PASS
4919 22:53:41.134529 RX DQS gating : PASS
4920 22:53:41.134611 RX DQ/DQS(RDDQC) : PASS
4921 22:53:41.138515 TX DQ/DQS : PASS
4922 22:53:41.138598 RX DATLAT : PASS
4923 22:53:41.141587 RX DQ/DQS(Engine): PASS
4924 22:53:41.144600 TX OE : NO K
4925 22:53:41.144682 All Pass.
4926 22:53:41.144747
4927 22:53:41.148322 DramC Write-DBI off
4928 22:53:41.148409 PER_BANK_REFRESH: Hybrid Mode
4929 22:53:41.151897 TX_TRACKING: ON
4930 22:53:41.157881 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4931 22:53:41.164805 [FAST_K] Save calibration result to emmc
4932 22:53:41.168309 dramc_set_vcore_voltage set vcore to 662500
4933 22:53:41.168392 Read voltage for 933, 3
4934 22:53:41.171705 Vio18 = 0
4935 22:53:41.171786 Vcore = 662500
4936 22:53:41.171851 Vdram = 0
4937 22:53:41.174599 Vddq = 0
4938 22:53:41.174681 Vmddr = 0
4939 22:53:41.178273 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4940 22:53:41.184603 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4941 22:53:41.188035 MEM_TYPE=3, freq_sel=17
4942 22:53:41.191299 sv_algorithm_assistance_LP4_1600
4943 22:53:41.194699 ============ PULL DRAM RESETB DOWN ============
4944 22:53:41.198084 ========== PULL DRAM RESETB DOWN end =========
4945 22:53:41.205240 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4946 22:53:41.205336 ===================================
4947 22:53:41.208105 LPDDR4 DRAM CONFIGURATION
4948 22:53:41.211266 ===================================
4949 22:53:41.214632 EX_ROW_EN[0] = 0x0
4950 22:53:41.214714 EX_ROW_EN[1] = 0x0
4951 22:53:41.218248 LP4Y_EN = 0x0
4952 22:53:41.218330 WORK_FSP = 0x0
4953 22:53:41.221854 WL = 0x3
4954 22:53:41.221936 RL = 0x3
4955 22:53:41.224937 BL = 0x2
4956 22:53:41.225020 RPST = 0x0
4957 22:53:41.228257 RD_PRE = 0x0
4958 22:53:41.228339 WR_PRE = 0x1
4959 22:53:41.231742 WR_PST = 0x0
4960 22:53:41.231825 DBI_WR = 0x0
4961 22:53:41.235307 DBI_RD = 0x0
4962 22:53:41.235390 OTF = 0x1
4963 22:53:41.238836 ===================================
4964 22:53:41.241789 ===================================
4965 22:53:41.244975 ANA top config
4966 22:53:41.248764 ===================================
4967 22:53:41.251536 DLL_ASYNC_EN = 0
4968 22:53:41.251618 ALL_SLAVE_EN = 1
4969 22:53:41.255036 NEW_RANK_MODE = 1
4970 22:53:41.258638 DLL_IDLE_MODE = 1
4971 22:53:41.261761 LP45_APHY_COMB_EN = 1
4972 22:53:41.261843 TX_ODT_DIS = 1
4973 22:53:41.264986 NEW_8X_MODE = 1
4974 22:53:41.268234 ===================================
4975 22:53:41.271643 ===================================
4976 22:53:41.274808 data_rate = 1866
4977 22:53:41.278592 CKR = 1
4978 22:53:41.281443 DQ_P2S_RATIO = 8
4979 22:53:41.284904 ===================================
4980 22:53:41.288369 CA_P2S_RATIO = 8
4981 22:53:41.288451 DQ_CA_OPEN = 0
4982 22:53:41.291685 DQ_SEMI_OPEN = 0
4983 22:53:41.295324 CA_SEMI_OPEN = 0
4984 22:53:41.298445 CA_FULL_RATE = 0
4985 22:53:41.301978 DQ_CKDIV4_EN = 1
4986 22:53:41.302060 CA_CKDIV4_EN = 1
4987 22:53:41.305395 CA_PREDIV_EN = 0
4988 22:53:41.309300 PH8_DLY = 0
4989 22:53:41.312307 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4990 22:53:41.315362 DQ_AAMCK_DIV = 4
4991 22:53:41.318656 CA_AAMCK_DIV = 4
4992 22:53:41.318738 CA_ADMCK_DIV = 4
4993 22:53:41.321869 DQ_TRACK_CA_EN = 0
4994 22:53:41.325497 CA_PICK = 933
4995 22:53:41.328997 CA_MCKIO = 933
4996 22:53:41.331724 MCKIO_SEMI = 0
4997 22:53:41.335148 PLL_FREQ = 3732
4998 22:53:41.338232 DQ_UI_PI_RATIO = 32
4999 22:53:41.338315 CA_UI_PI_RATIO = 0
5000 22:53:41.341778 ===================================
5001 22:53:41.344911 ===================================
5002 22:53:41.348652 memory_type:LPDDR4
5003 22:53:41.351901 GP_NUM : 10
5004 22:53:41.351984 SRAM_EN : 1
5005 22:53:41.355074 MD32_EN : 0
5006 22:53:41.358252 ===================================
5007 22:53:41.361423 [ANA_INIT] >>>>>>>>>>>>>>
5008 22:53:41.364759 <<<<<< [CONFIGURE PHASE]: ANA_TX
5009 22:53:41.368393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5010 22:53:41.372081 ===================================
5011 22:53:41.372164 data_rate = 1866,PCW = 0X8f00
5012 22:53:41.374888 ===================================
5013 22:53:41.378293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5014 22:53:41.384696 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5015 22:53:41.391789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5016 22:53:41.395154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5017 22:53:41.398097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5018 22:53:41.401227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5019 22:53:41.404713 [ANA_INIT] flow start
5020 22:53:41.407885 [ANA_INIT] PLL >>>>>>>>
5021 22:53:41.407967 [ANA_INIT] PLL <<<<<<<<
5022 22:53:41.411258 [ANA_INIT] MIDPI >>>>>>>>
5023 22:53:41.414654 [ANA_INIT] MIDPI <<<<<<<<
5024 22:53:41.414737 [ANA_INIT] DLL >>>>>>>>
5025 22:53:41.417880 [ANA_INIT] flow end
5026 22:53:41.421692 ============ LP4 DIFF to SE enter ============
5027 22:53:41.424550 ============ LP4 DIFF to SE exit ============
5028 22:53:41.428135 [ANA_INIT] <<<<<<<<<<<<<
5029 22:53:41.431404 [Flow] Enable top DCM control >>>>>
5030 22:53:41.435279 [Flow] Enable top DCM control <<<<<
5031 22:53:41.438023 Enable DLL master slave shuffle
5032 22:53:41.445294 ==============================================================
5033 22:53:41.445378 Gating Mode config
5034 22:53:41.451406 ==============================================================
5035 22:53:41.451489 Config description:
5036 22:53:41.461525 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5037 22:53:41.468036 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5038 22:53:41.474899 SELPH_MODE 0: By rank 1: By Phase
5039 22:53:41.478108 ==============================================================
5040 22:53:41.481465 GAT_TRACK_EN = 1
5041 22:53:41.484818 RX_GATING_MODE = 2
5042 22:53:41.488230 RX_GATING_TRACK_MODE = 2
5043 22:53:41.491618 SELPH_MODE = 1
5044 22:53:41.494896 PICG_EARLY_EN = 1
5045 22:53:41.498402 VALID_LAT_VALUE = 1
5046 22:53:41.501796 ==============================================================
5047 22:53:41.505249 Enter into Gating configuration >>>>
5048 22:53:41.508267 Exit from Gating configuration <<<<
5049 22:53:41.511614 Enter into DVFS_PRE_config >>>>>
5050 22:53:41.524847 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5051 22:53:41.528529 Exit from DVFS_PRE_config <<<<<
5052 22:53:41.528640 Enter into PICG configuration >>>>
5053 22:53:41.531567 Exit from PICG configuration <<<<
5054 22:53:41.535010 [RX_INPUT] configuration >>>>>
5055 22:53:41.538087 [RX_INPUT] configuration <<<<<
5056 22:53:41.545017 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5057 22:53:41.548509 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5058 22:53:41.555558 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5059 22:53:41.562061 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5060 22:53:41.568441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5061 22:53:41.575107 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5062 22:53:41.578126 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5063 22:53:41.582362 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5064 22:53:41.585112 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5065 22:53:41.591657 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5066 22:53:41.594894 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5067 22:53:41.598343 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5068 22:53:41.601486 ===================================
5069 22:53:41.605152 LPDDR4 DRAM CONFIGURATION
5070 22:53:41.608376 ===================================
5071 22:53:41.608458 EX_ROW_EN[0] = 0x0
5072 22:53:41.611443 EX_ROW_EN[1] = 0x0
5073 22:53:41.614692 LP4Y_EN = 0x0
5074 22:53:41.614774 WORK_FSP = 0x0
5075 22:53:41.618406 WL = 0x3
5076 22:53:41.618537 RL = 0x3
5077 22:53:41.622357 BL = 0x2
5078 22:53:41.622460 RPST = 0x0
5079 22:53:41.624768 RD_PRE = 0x0
5080 22:53:41.624864 WR_PRE = 0x1
5081 22:53:41.628892 WR_PST = 0x0
5082 22:53:41.628975 DBI_WR = 0x0
5083 22:53:41.631997 DBI_RD = 0x0
5084 22:53:41.632080 OTF = 0x1
5085 22:53:41.634919 ===================================
5086 22:53:41.638458 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5087 22:53:41.645172 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5088 22:53:41.648331 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5089 22:53:41.651310 ===================================
5090 22:53:41.654974 LPDDR4 DRAM CONFIGURATION
5091 22:53:41.658234 ===================================
5092 22:53:41.658315 EX_ROW_EN[0] = 0x10
5093 22:53:41.661601 EX_ROW_EN[1] = 0x0
5094 22:53:41.661682 LP4Y_EN = 0x0
5095 22:53:41.664750 WORK_FSP = 0x0
5096 22:53:41.664831 WL = 0x3
5097 22:53:41.668455 RL = 0x3
5098 22:53:41.671668 BL = 0x2
5099 22:53:41.671750 RPST = 0x0
5100 22:53:41.674773 RD_PRE = 0x0
5101 22:53:41.674855 WR_PRE = 0x1
5102 22:53:41.678336 WR_PST = 0x0
5103 22:53:41.678418 DBI_WR = 0x0
5104 22:53:41.681651 DBI_RD = 0x0
5105 22:53:41.681733 OTF = 0x1
5106 22:53:41.684814 ===================================
5107 22:53:41.692020 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5108 22:53:41.695641 nWR fixed to 30
5109 22:53:41.698501 [ModeRegInit_LP4] CH0 RK0
5110 22:53:41.698582 [ModeRegInit_LP4] CH0 RK1
5111 22:53:41.702419 [ModeRegInit_LP4] CH1 RK0
5112 22:53:41.705256 [ModeRegInit_LP4] CH1 RK1
5113 22:53:41.705339 match AC timing 9
5114 22:53:41.711939 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5115 22:53:41.715164 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5116 22:53:41.718840 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5117 22:53:41.725460 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5118 22:53:41.728809 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5119 22:53:41.728891 ==
5120 22:53:41.732337 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 22:53:41.735972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 22:53:41.736055 ==
5123 22:53:41.742341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 22:53:41.748844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5125 22:53:41.752632 [CA 0] Center 38 (8~69) winsize 62
5126 22:53:41.755505 [CA 1] Center 38 (7~69) winsize 63
5127 22:53:41.758582 [CA 2] Center 35 (5~66) winsize 62
5128 22:53:41.762393 [CA 3] Center 35 (5~66) winsize 62
5129 22:53:41.765194 [CA 4] Center 34 (3~65) winsize 63
5130 22:53:41.768566 [CA 5] Center 33 (3~64) winsize 62
5131 22:53:41.768683
5132 22:53:41.771963 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5133 22:53:41.772065
5134 22:53:41.775613 [CATrainingPosCal] consider 1 rank data
5135 22:53:41.778700 u2DelayCellTimex100 = 270/100 ps
5136 22:53:41.782011 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5137 22:53:41.785384 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5138 22:53:41.788889 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5139 22:53:41.792046 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5140 22:53:41.795482 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5141 22:53:41.798549 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5142 22:53:41.798631
5143 22:53:41.805362 CA PerBit enable=1, Macro0, CA PI delay=33
5144 22:53:41.805444
5145 22:53:41.805509 [CBTSetCACLKResult] CA Dly = 33
5146 22:53:41.809136 CS Dly: 6 (0~37)
5147 22:53:41.809228 ==
5148 22:53:41.811921 Dram Type= 6, Freq= 0, CH_0, rank 1
5149 22:53:41.815271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 22:53:41.815354 ==
5151 22:53:41.821800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5152 22:53:41.828233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5153 22:53:41.831681 [CA 0] Center 38 (7~69) winsize 63
5154 22:53:41.834823 [CA 1] Center 38 (7~69) winsize 63
5155 22:53:41.838411 [CA 2] Center 35 (5~66) winsize 62
5156 22:53:41.841706 [CA 3] Center 35 (5~66) winsize 62
5157 22:53:41.844825 [CA 4] Center 34 (3~65) winsize 63
5158 22:53:41.848081 [CA 5] Center 33 (3~64) winsize 62
5159 22:53:41.848163
5160 22:53:41.851403 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5161 22:53:41.851486
5162 22:53:41.854761 [CATrainingPosCal] consider 2 rank data
5163 22:53:41.858522 u2DelayCellTimex100 = 270/100 ps
5164 22:53:41.861805 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5165 22:53:41.865082 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5166 22:53:41.868305 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5167 22:53:41.871458 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5168 22:53:41.874901 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5169 22:53:41.881482 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5170 22:53:41.881564
5171 22:53:41.884638 CA PerBit enable=1, Macro0, CA PI delay=33
5172 22:53:41.884744
5173 22:53:41.887952 [CBTSetCACLKResult] CA Dly = 33
5174 22:53:41.888033 CS Dly: 7 (0~39)
5175 22:53:41.888097
5176 22:53:41.891802 ----->DramcWriteLeveling(PI) begin...
5177 22:53:41.891885 ==
5178 22:53:41.894706 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 22:53:41.898402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 22:53:41.901614 ==
5181 22:53:41.901695 Write leveling (Byte 0): 28 => 28
5182 22:53:41.904757 Write leveling (Byte 1): 27 => 27
5183 22:53:41.908505 DramcWriteLeveling(PI) end<-----
5184 22:53:41.908586
5185 22:53:41.908649 ==
5186 22:53:41.911568 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 22:53:41.918839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 22:53:41.918925 ==
5189 22:53:41.918990 [Gating] SW mode calibration
5190 22:53:41.928199 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5191 22:53:41.931352 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5192 22:53:41.934671 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
5193 22:53:41.941416 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5194 22:53:41.945346 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 22:53:41.948784 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 22:53:41.955034 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 22:53:41.958373 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 22:53:41.961899 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 22:53:41.968425 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
5200 22:53:41.972088 0 15 0 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (0 1)
5201 22:53:41.975329 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5202 22:53:41.982267 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 22:53:41.985036 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 22:53:41.988122 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 22:53:41.994994 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 22:53:41.998456 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 22:53:42.001563 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5208 22:53:42.008382 1 0 0 | B1->B0 | 3232 4242 | 1 0 | (0 0) (0 0)
5209 22:53:42.011480 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 22:53:42.014883 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 22:53:42.021476 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 22:53:42.025083 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 22:53:42.028415 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 22:53:42.031809 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 22:53:42.037981 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5216 22:53:42.041772 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5217 22:53:42.044901 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 22:53:42.051631 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 22:53:42.055098 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 22:53:42.058257 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 22:53:42.065055 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 22:53:42.068440 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 22:53:42.071546 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 22:53:42.078474 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 22:53:42.082070 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 22:53:42.084793 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 22:53:42.091531 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 22:53:42.095107 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 22:53:42.098752 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 22:53:42.105251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 22:53:42.108186 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 22:53:42.111765 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5233 22:53:42.118280 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5234 22:53:42.118363 Total UI for P1: 0, mck2ui 16
5235 22:53:42.121820 best dqsien dly found for B0: ( 1, 3, 0)
5236 22:53:42.128229 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 22:53:42.131580 Total UI for P1: 0, mck2ui 16
5238 22:53:42.134735 best dqsien dly found for B1: ( 1, 3, 2)
5239 22:53:42.138006 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5240 22:53:42.141561 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5241 22:53:42.141643
5242 22:53:42.145134 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5243 22:53:42.148655 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5244 22:53:42.151441 [Gating] SW calibration Done
5245 22:53:42.151523 ==
5246 22:53:42.155025 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 22:53:42.158732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 22:53:42.158815 ==
5249 22:53:42.161869 RX Vref Scan: 0
5250 22:53:42.161951
5251 22:53:42.162017 RX Vref 0 -> 0, step: 1
5252 22:53:42.162077
5253 22:53:42.165202 RX Delay -80 -> 252, step: 8
5254 22:53:42.168583 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5255 22:53:42.174936 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5256 22:53:42.178173 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5257 22:53:42.181969 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5258 22:53:42.184820 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5259 22:53:42.188936 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5260 22:53:42.192187 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5261 22:53:42.198538 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5262 22:53:42.201671 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5263 22:53:42.205424 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5264 22:53:42.208338 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5265 22:53:42.211889 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5266 22:53:42.214810 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5267 22:53:42.222143 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5268 22:53:42.225149 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5269 22:53:42.228340 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5270 22:53:42.228422 ==
5271 22:53:42.231906 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 22:53:42.235395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 22:53:42.235477 ==
5274 22:53:42.238738 DQS Delay:
5275 22:53:42.238820 DQS0 = 0, DQS1 = 0
5276 22:53:42.241870 DQM Delay:
5277 22:53:42.241950 DQM0 = 97, DQM1 = 87
5278 22:53:42.242014 DQ Delay:
5279 22:53:42.244749 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5280 22:53:42.248500 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5281 22:53:42.251460 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5282 22:53:42.254965 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5283 22:53:42.255048
5284 22:53:42.255115
5285 22:53:42.258121 ==
5286 22:53:42.261490 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 22:53:42.264738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 22:53:42.264812 ==
5289 22:53:42.264875
5290 22:53:42.264932
5291 22:53:42.268358 TX Vref Scan disable
5292 22:53:42.268426 == TX Byte 0 ==
5293 22:53:42.271590 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5294 22:53:42.278425 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5295 22:53:42.278507 == TX Byte 1 ==
5296 22:53:42.281506 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5297 22:53:42.288215 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5298 22:53:42.288297 ==
5299 22:53:42.291384 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 22:53:42.294714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 22:53:42.294796 ==
5302 22:53:42.294859
5303 22:53:42.294918
5304 22:53:42.297953 TX Vref Scan disable
5305 22:53:42.301169 == TX Byte 0 ==
5306 22:53:42.304611 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5307 22:53:42.307989 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5308 22:53:42.311718 == TX Byte 1 ==
5309 22:53:42.314547 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5310 22:53:42.318062 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5311 22:53:42.318144
5312 22:53:42.321000 [DATLAT]
5313 22:53:42.321107 Freq=933, CH0 RK0
5314 22:53:42.321199
5315 22:53:42.324979 DATLAT Default: 0xd
5316 22:53:42.325060 0, 0xFFFF, sum = 0
5317 22:53:42.327658 1, 0xFFFF, sum = 0
5318 22:53:42.327740 2, 0xFFFF, sum = 0
5319 22:53:42.331332 3, 0xFFFF, sum = 0
5320 22:53:42.331415 4, 0xFFFF, sum = 0
5321 22:53:42.334490 5, 0xFFFF, sum = 0
5322 22:53:42.334601 6, 0xFFFF, sum = 0
5323 22:53:42.337842 7, 0xFFFF, sum = 0
5324 22:53:42.337924 8, 0xFFFF, sum = 0
5325 22:53:42.341124 9, 0xFFFF, sum = 0
5326 22:53:42.341265 10, 0x0, sum = 1
5327 22:53:42.344254 11, 0x0, sum = 2
5328 22:53:42.344339 12, 0x0, sum = 3
5329 22:53:42.348036 13, 0x0, sum = 4
5330 22:53:42.348124 best_step = 11
5331 22:53:42.348218
5332 22:53:42.348290 ==
5333 22:53:42.351332 Dram Type= 6, Freq= 0, CH_0, rank 0
5334 22:53:42.354438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 22:53:42.358005 ==
5336 22:53:42.358086 RX Vref Scan: 1
5337 22:53:42.358149
5338 22:53:42.361082 RX Vref 0 -> 0, step: 1
5339 22:53:42.361195
5340 22:53:42.364451 RX Delay -61 -> 252, step: 4
5341 22:53:42.364532
5342 22:53:42.364596 Set Vref, RX VrefLevel [Byte0]: 53
5343 22:53:42.367883 [Byte1]: 51
5344 22:53:42.372901
5345 22:53:42.373009 Final RX Vref Byte 0 = 53 to rank0
5346 22:53:42.376209 Final RX Vref Byte 1 = 51 to rank0
5347 22:53:42.379657 Final RX Vref Byte 0 = 53 to rank1
5348 22:53:42.383074 Final RX Vref Byte 1 = 51 to rank1==
5349 22:53:42.386124 Dram Type= 6, Freq= 0, CH_0, rank 0
5350 22:53:42.393370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 22:53:42.393453 ==
5352 22:53:42.393518 DQS Delay:
5353 22:53:42.393577 DQS0 = 0, DQS1 = 0
5354 22:53:42.396336 DQM Delay:
5355 22:53:42.396418 DQM0 = 97, DQM1 = 86
5356 22:53:42.399709 DQ Delay:
5357 22:53:42.403181 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5358 22:53:42.406298 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104
5359 22:53:42.410365 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =80
5360 22:53:42.412775 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =96
5361 22:53:42.412856
5362 22:53:42.412920
5363 22:53:42.419316 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5364 22:53:42.422717 CH0 RK0: MR19=504, MR18=13FE
5365 22:53:42.429727 CH0_RK0: MR19=0x504, MR18=0x13FE, DQSOSC=415, MR23=63, INC=62, DEC=41
5366 22:53:42.429809
5367 22:53:42.433579 ----->DramcWriteLeveling(PI) begin...
5368 22:53:42.433662 ==
5369 22:53:42.436338 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 22:53:42.439830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 22:53:42.439912 ==
5372 22:53:42.442822 Write leveling (Byte 0): 32 => 32
5373 22:53:42.446384 Write leveling (Byte 1): 27 => 27
5374 22:53:42.450129 DramcWriteLeveling(PI) end<-----
5375 22:53:42.450211
5376 22:53:42.450274 ==
5377 22:53:42.452929 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 22:53:42.456509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 22:53:42.456591 ==
5380 22:53:42.459897 [Gating] SW mode calibration
5381 22:53:42.466405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5382 22:53:42.472857 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5383 22:53:42.476422 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5384 22:53:42.479821 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5385 22:53:42.486486 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 22:53:42.489333 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 22:53:42.492927 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 22:53:42.499585 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 22:53:42.502839 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5390 22:53:42.506569 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
5391 22:53:42.513069 0 15 0 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
5392 22:53:42.516056 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 22:53:42.519544 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 22:53:42.526447 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 22:53:42.529598 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 22:53:42.532792 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 22:53:42.540001 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 22:53:42.542712 0 15 28 | B1->B0 | 2424 3535 | 1 0 | (0 0) (0 0)
5399 22:53:42.546064 1 0 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
5400 22:53:42.552999 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 22:53:42.556462 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 22:53:42.559424 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 22:53:42.566728 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 22:53:42.569971 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 22:53:42.572939 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 22:53:42.576396 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5407 22:53:42.582596 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5408 22:53:42.586086 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5409 22:53:42.589436 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 22:53:42.596433 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 22:53:42.599587 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 22:53:42.602857 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 22:53:42.609345 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 22:53:42.612982 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 22:53:42.616006 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 22:53:42.623186 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 22:53:42.626313 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 22:53:42.629560 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 22:53:42.636486 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 22:53:42.639389 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 22:53:42.642611 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 22:53:42.649272 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5423 22:53:42.653016 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5424 22:53:42.656150 Total UI for P1: 0, mck2ui 16
5425 22:53:42.659286 best dqsien dly found for B0: ( 1, 2, 28)
5426 22:53:42.662757 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5427 22:53:42.666124 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 22:53:42.669287 Total UI for P1: 0, mck2ui 16
5429 22:53:42.672734 best dqsien dly found for B1: ( 1, 3, 2)
5430 22:53:42.675927 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5431 22:53:42.682961 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5432 22:53:42.683039
5433 22:53:42.686121 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5434 22:53:42.689477 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5435 22:53:42.692766 [Gating] SW calibration Done
5436 22:53:42.692834 ==
5437 22:53:42.696061 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 22:53:42.699448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 22:53:42.699519 ==
5440 22:53:42.699579 RX Vref Scan: 0
5441 22:53:42.699638
5442 22:53:42.703126 RX Vref 0 -> 0, step: 1
5443 22:53:42.703196
5444 22:53:42.706697 RX Delay -80 -> 252, step: 8
5445 22:53:42.709452 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5446 22:53:42.712853 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5447 22:53:42.716170 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5448 22:53:42.722860 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5449 22:53:42.726214 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5450 22:53:42.729654 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5451 22:53:42.732796 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5452 22:53:42.736000 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5453 22:53:42.739364 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5454 22:53:42.746558 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5455 22:53:42.749520 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5456 22:53:42.752648 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5457 22:53:42.756029 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5458 22:53:42.759570 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5459 22:53:42.763090 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5460 22:53:42.769270 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5461 22:53:42.769347 ==
5462 22:53:42.772808 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 22:53:42.776039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 22:53:42.776112 ==
5465 22:53:42.776173 DQS Delay:
5466 22:53:42.779444 DQS0 = 0, DQS1 = 0
5467 22:53:42.779514 DQM Delay:
5468 22:53:42.782844 DQM0 = 97, DQM1 = 87
5469 22:53:42.782919 DQ Delay:
5470 22:53:42.786203 DQ0 =99, DQ1 =95, DQ2 =95, DQ3 =95
5471 22:53:42.789641 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5472 22:53:42.792547 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5473 22:53:42.796399 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5474 22:53:42.796466
5475 22:53:42.796525
5476 22:53:42.796585 ==
5477 22:53:42.799353 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 22:53:42.802711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 22:53:42.802782 ==
5480 22:53:42.806368
5481 22:53:42.806433
5482 22:53:42.806489 TX Vref Scan disable
5483 22:53:42.809536 == TX Byte 0 ==
5484 22:53:42.812927 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5485 22:53:42.815942 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5486 22:53:42.819675 == TX Byte 1 ==
5487 22:53:42.822937 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5488 22:53:42.826049 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5489 22:53:42.826120 ==
5490 22:53:42.829136 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 22:53:42.836081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 22:53:42.836159 ==
5493 22:53:42.836221
5494 22:53:42.836278
5495 22:53:42.836337 TX Vref Scan disable
5496 22:53:42.841088 == TX Byte 0 ==
5497 22:53:42.843680 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5498 22:53:42.850176 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5499 22:53:42.850262 == TX Byte 1 ==
5500 22:53:42.853572 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5501 22:53:42.860495 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5502 22:53:42.860580
5503 22:53:42.860664 [DATLAT]
5504 22:53:42.860744 Freq=933, CH0 RK1
5505 22:53:42.860842
5506 22:53:42.863675 DATLAT Default: 0xb
5507 22:53:42.863759 0, 0xFFFF, sum = 0
5508 22:53:42.867193 1, 0xFFFF, sum = 0
5509 22:53:42.867279 2, 0xFFFF, sum = 0
5510 22:53:42.870240 3, 0xFFFF, sum = 0
5511 22:53:42.874172 4, 0xFFFF, sum = 0
5512 22:53:42.874258 5, 0xFFFF, sum = 0
5513 22:53:42.877116 6, 0xFFFF, sum = 0
5514 22:53:42.877202 7, 0xFFFF, sum = 0
5515 22:53:42.880054 8, 0xFFFF, sum = 0
5516 22:53:42.880139 9, 0xFFFF, sum = 0
5517 22:53:42.883470 10, 0x0, sum = 1
5518 22:53:42.883555 11, 0x0, sum = 2
5519 22:53:42.886989 12, 0x0, sum = 3
5520 22:53:42.887074 13, 0x0, sum = 4
5521 22:53:42.887159 best_step = 11
5522 22:53:42.887239
5523 22:53:42.890105 ==
5524 22:53:42.893613 Dram Type= 6, Freq= 0, CH_0, rank 1
5525 22:53:42.896704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 22:53:42.896789 ==
5527 22:53:42.896875 RX Vref Scan: 0
5528 22:53:42.896955
5529 22:53:42.900261 RX Vref 0 -> 0, step: 1
5530 22:53:42.900345
5531 22:53:42.903676 RX Delay -61 -> 252, step: 4
5532 22:53:42.907069 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5533 22:53:42.913245 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5534 22:53:42.916961 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5535 22:53:42.920400 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5536 22:53:42.924199 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5537 22:53:42.927110 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5538 22:53:42.930539 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5539 22:53:42.933897 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5540 22:53:42.940356 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5541 22:53:42.943747 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5542 22:53:42.947649 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5543 22:53:42.950833 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5544 22:53:42.954320 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5545 22:53:42.957519 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5546 22:53:42.963426 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5547 22:53:42.968041 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5548 22:53:42.968159 ==
5549 22:53:42.971097 Dram Type= 6, Freq= 0, CH_0, rank 1
5550 22:53:42.974094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 22:53:42.974177 ==
5552 22:53:42.977157 DQS Delay:
5553 22:53:42.977252 DQS0 = 0, DQS1 = 0
5554 22:53:42.977345 DQM Delay:
5555 22:53:42.980653 DQM0 = 96, DQM1 = 88
5556 22:53:42.980734 DQ Delay:
5557 22:53:42.983641 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5558 22:53:42.987239 DQ4 =96, DQ5 =84, DQ6 =106, DQ7 =104
5559 22:53:42.990918 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =78
5560 22:53:42.993946 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =94
5561 22:53:42.994028
5562 22:53:42.994092
5563 22:53:43.004176 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5564 22:53:43.004259 CH0 RK1: MR19=505, MR18=1C0A
5565 22:53:43.010414 CH0_RK1: MR19=0x505, MR18=0x1C0A, DQSOSC=412, MR23=63, INC=63, DEC=42
5566 22:53:43.013647 [RxdqsGatingPostProcess] freq 933
5567 22:53:43.020982 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5568 22:53:43.024069 best DQS0 dly(2T, 0.5T) = (0, 11)
5569 22:53:43.027502 best DQS1 dly(2T, 0.5T) = (0, 11)
5570 22:53:43.030822 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5571 22:53:43.034267 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5572 22:53:43.037084 best DQS0 dly(2T, 0.5T) = (0, 10)
5573 22:53:43.037165 best DQS1 dly(2T, 0.5T) = (0, 11)
5574 22:53:43.040933 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5575 22:53:43.044445 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5576 22:53:43.047694 Pre-setting of DQS Precalculation
5577 22:53:43.054016 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5578 22:53:43.054098 ==
5579 22:53:43.057408 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 22:53:43.060563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 22:53:43.060645 ==
5582 22:53:43.067845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5583 22:53:43.073776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5584 22:53:43.077573 [CA 0] Center 36 (6~67) winsize 62
5585 22:53:43.080275 [CA 1] Center 36 (6~67) winsize 62
5586 22:53:43.083623 [CA 2] Center 34 (4~64) winsize 61
5587 22:53:43.087276 [CA 3] Center 33 (3~64) winsize 62
5588 22:53:43.090669 [CA 4] Center 33 (3~64) winsize 62
5589 22:53:43.093547 [CA 5] Center 33 (3~64) winsize 62
5590 22:53:43.093629
5591 22:53:43.096863 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5592 22:53:43.096945
5593 22:53:43.100924 [CATrainingPosCal] consider 1 rank data
5594 22:53:43.103762 u2DelayCellTimex100 = 270/100 ps
5595 22:53:43.107415 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5596 22:53:43.110386 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5597 22:53:43.113583 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5598 22:53:43.117367 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5599 22:53:43.120715 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5600 22:53:43.124073 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5601 22:53:43.124155
5602 22:53:43.127315 CA PerBit enable=1, Macro0, CA PI delay=33
5603 22:53:43.127399
5604 22:53:43.130727 [CBTSetCACLKResult] CA Dly = 33
5605 22:53:43.133883 CS Dly: 4 (0~35)
5606 22:53:43.133967 ==
5607 22:53:43.136971 Dram Type= 6, Freq= 0, CH_1, rank 1
5608 22:53:43.140465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 22:53:43.140550 ==
5610 22:53:43.146796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5611 22:53:43.153447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5612 22:53:43.157192 [CA 0] Center 36 (6~67) winsize 62
5613 22:53:43.160647 [CA 1] Center 36 (6~67) winsize 62
5614 22:53:43.163620 [CA 2] Center 33 (3~64) winsize 62
5615 22:53:43.166809 [CA 3] Center 33 (3~64) winsize 62
5616 22:53:43.170345 [CA 4] Center 34 (3~65) winsize 63
5617 22:53:43.173568 [CA 5] Center 32 (2~63) winsize 62
5618 22:53:43.173654
5619 22:53:43.176717 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5620 22:53:43.176805
5621 22:53:43.180355 [CATrainingPosCal] consider 2 rank data
5622 22:53:43.184141 u2DelayCellTimex100 = 270/100 ps
5623 22:53:43.187126 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5624 22:53:43.190471 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5625 22:53:43.193944 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5626 22:53:43.197247 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5627 22:53:43.200682 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5628 22:53:43.203700 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5629 22:53:43.203784
5630 22:53:43.206894 CA PerBit enable=1, Macro0, CA PI delay=33
5631 22:53:43.206979
5632 22:53:43.210540 [CBTSetCACLKResult] CA Dly = 33
5633 22:53:43.213788 CS Dly: 5 (0~37)
5634 22:53:43.213873
5635 22:53:43.217272 ----->DramcWriteLeveling(PI) begin...
5636 22:53:43.217357 ==
5637 22:53:43.220431 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 22:53:43.224018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 22:53:43.224104 ==
5640 22:53:43.227411 Write leveling (Byte 0): 27 => 27
5641 22:53:43.230405 Write leveling (Byte 1): 31 => 31
5642 22:53:43.234132 DramcWriteLeveling(PI) end<-----
5643 22:53:43.234217
5644 22:53:43.234300 ==
5645 22:53:43.237128 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 22:53:43.240600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 22:53:43.240685 ==
5648 22:53:43.243678 [Gating] SW mode calibration
5649 22:53:43.250341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5650 22:53:43.257139 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5651 22:53:43.260336 0 14 0 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
5652 22:53:43.267366 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 22:53:43.270374 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5654 22:53:43.273871 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5655 22:53:43.277322 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 22:53:43.283584 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5657 22:53:43.287063 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5658 22:53:43.290290 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
5659 22:53:43.297004 0 15 0 | B1->B0 | 2727 2525 | 0 0 | (1 0) (1 0)
5660 22:53:43.300455 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 22:53:43.303753 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5662 22:53:43.310573 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 22:53:43.313534 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5664 22:53:43.317139 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 22:53:43.324092 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 22:53:43.326949 0 15 28 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (0 0)
5667 22:53:43.330559 1 0 0 | B1->B0 | 4040 4343 | 0 0 | (0 0) (0 0)
5668 22:53:43.336774 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 22:53:43.340751 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 22:53:43.343576 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 22:53:43.350155 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 22:53:43.353716 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 22:53:43.357257 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 22:53:43.363550 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5675 22:53:43.367161 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5676 22:53:43.369877 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 22:53:43.377450 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 22:53:43.380004 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 22:53:43.383433 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 22:53:43.389968 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 22:53:43.393285 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 22:53:43.397187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 22:53:43.400558 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 22:53:43.406810 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 22:53:43.410430 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 22:53:43.413190 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 22:53:43.420459 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 22:53:43.423299 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 22:53:43.427009 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 22:53:43.433504 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5691 22:53:43.436764 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 22:53:43.440316 Total UI for P1: 0, mck2ui 16
5693 22:53:43.444060 best dqsien dly found for B0: ( 1, 2, 28)
5694 22:53:43.447151 Total UI for P1: 0, mck2ui 16
5695 22:53:43.450305 best dqsien dly found for B1: ( 1, 2, 28)
5696 22:53:43.453620 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5697 22:53:43.456960 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5698 22:53:43.457044
5699 22:53:43.460301 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5700 22:53:43.463710 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5701 22:53:43.466907 [Gating] SW calibration Done
5702 22:53:43.466990 ==
5703 22:53:43.470313 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 22:53:43.473608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 22:53:43.473683 ==
5706 22:53:43.477035 RX Vref Scan: 0
5707 22:53:43.477109
5708 22:53:43.480337 RX Vref 0 -> 0, step: 1
5709 22:53:43.480408
5710 22:53:43.480466 RX Delay -80 -> 252, step: 8
5711 22:53:43.487265 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5712 22:53:43.490491 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5713 22:53:43.494018 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5714 22:53:43.497043 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5715 22:53:43.500609 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5716 22:53:43.504210 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5717 22:53:43.510317 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5718 22:53:43.513929 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5719 22:53:43.517179 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5720 22:53:43.520513 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5721 22:53:43.523708 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5722 22:53:43.527718 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5723 22:53:43.533967 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5724 22:53:43.537197 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5725 22:53:43.540772 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5726 22:53:43.543973 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5727 22:53:43.544058 ==
5728 22:53:43.547261 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 22:53:43.550743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 22:53:43.554019 ==
5731 22:53:43.554104 DQS Delay:
5732 22:53:43.554189 DQS0 = 0, DQS1 = 0
5733 22:53:43.557031 DQM Delay:
5734 22:53:43.557115 DQM0 = 96, DQM1 = 89
5735 22:53:43.557223 DQ Delay:
5736 22:53:43.561123 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5737 22:53:43.564083 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5738 22:53:43.567632 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5739 22:53:43.570578 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5740 22:53:43.570662
5741 22:53:43.573773
5742 22:53:43.573857 ==
5743 22:53:43.577143 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 22:53:43.580810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 22:53:43.580895 ==
5746 22:53:43.580996
5747 22:53:43.581096
5748 22:53:43.583794 TX Vref Scan disable
5749 22:53:43.583878 == TX Byte 0 ==
5750 22:53:43.590404 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5751 22:53:43.593666 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5752 22:53:43.593751 == TX Byte 1 ==
5753 22:53:43.600339 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5754 22:53:43.604077 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5755 22:53:43.604161 ==
5756 22:53:43.607002 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 22:53:43.610392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 22:53:43.610477 ==
5759 22:53:43.610561
5760 22:53:43.610659
5761 22:53:43.614017 TX Vref Scan disable
5762 22:53:43.617605 == TX Byte 0 ==
5763 22:53:43.620613 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5764 22:53:43.623823 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5765 22:53:43.627249 == TX Byte 1 ==
5766 22:53:43.630735 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5767 22:53:43.633988 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5768 22:53:43.634073
5769 22:53:43.637401 [DATLAT]
5770 22:53:43.637485 Freq=933, CH1 RK0
5771 22:53:43.637570
5772 22:53:43.640412 DATLAT Default: 0xd
5773 22:53:43.640496 0, 0xFFFF, sum = 0
5774 22:53:43.644260 1, 0xFFFF, sum = 0
5775 22:53:43.644346 2, 0xFFFF, sum = 0
5776 22:53:43.647167 3, 0xFFFF, sum = 0
5777 22:53:43.647252 4, 0xFFFF, sum = 0
5778 22:53:43.650622 5, 0xFFFF, sum = 0
5779 22:53:43.650708 6, 0xFFFF, sum = 0
5780 22:53:43.654524 7, 0xFFFF, sum = 0
5781 22:53:43.654609 8, 0xFFFF, sum = 0
5782 22:53:43.657512 9, 0xFFFF, sum = 0
5783 22:53:43.657597 10, 0x0, sum = 1
5784 22:53:43.660400 11, 0x0, sum = 2
5785 22:53:43.660485 12, 0x0, sum = 3
5786 22:53:43.664032 13, 0x0, sum = 4
5787 22:53:43.664118 best_step = 11
5788 22:53:43.664202
5789 22:53:43.664282 ==
5790 22:53:43.667129 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 22:53:43.670549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 22:53:43.670634 ==
5793 22:53:43.674175 RX Vref Scan: 1
5794 22:53:43.674259
5795 22:53:43.677734 RX Vref 0 -> 0, step: 1
5796 22:53:43.677819
5797 22:53:43.677903 RX Delay -61 -> 252, step: 4
5798 22:53:43.680840
5799 22:53:43.680946 Set Vref, RX VrefLevel [Byte0]: 57
5800 22:53:43.683751 [Byte1]: 52
5801 22:53:43.688962
5802 22:53:43.689071 Final RX Vref Byte 0 = 57 to rank0
5803 22:53:43.692362 Final RX Vref Byte 1 = 52 to rank0
5804 22:53:43.695326 Final RX Vref Byte 0 = 57 to rank1
5805 22:53:43.699205 Final RX Vref Byte 1 = 52 to rank1==
5806 22:53:43.702277 Dram Type= 6, Freq= 0, CH_1, rank 0
5807 22:53:43.708978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 22:53:43.709076 ==
5809 22:53:43.709169 DQS Delay:
5810 22:53:43.709281 DQS0 = 0, DQS1 = 0
5811 22:53:43.712200 DQM Delay:
5812 22:53:43.712266 DQM0 = 97, DQM1 = 90
5813 22:53:43.715423 DQ Delay:
5814 22:53:43.719737 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =98
5815 22:53:43.722195 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5816 22:53:43.725548 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =88
5817 22:53:43.728751 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =94
5818 22:53:43.728819
5819 22:53:43.728878
5820 22:53:43.735940 [DQSOSCAuto] RK0, (LSB)MR18= 0x14f1, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5821 22:53:43.739384 CH1 RK0: MR19=504, MR18=14F1
5822 22:53:43.745530 CH1_RK0: MR19=0x504, MR18=0x14F1, DQSOSC=415, MR23=63, INC=62, DEC=41
5823 22:53:43.745601
5824 22:53:43.748899 ----->DramcWriteLeveling(PI) begin...
5825 22:53:43.748997 ==
5826 22:53:43.752190 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 22:53:43.755901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 22:53:43.755969 ==
5829 22:53:43.758785 Write leveling (Byte 0): 28 => 28
5830 22:53:43.762262 Write leveling (Byte 1): 29 => 29
5831 22:53:43.765337 DramcWriteLeveling(PI) end<-----
5832 22:53:43.765408
5833 22:53:43.765468 ==
5834 22:53:43.768694 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 22:53:43.772170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 22:53:43.772248 ==
5837 22:53:43.775327 [Gating] SW mode calibration
5838 22:53:43.781964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5839 22:53:43.789124 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5840 22:53:43.792235 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5841 22:53:43.795567 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5842 22:53:43.801850 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5843 22:53:43.805663 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5844 22:53:43.808625 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5845 22:53:43.816020 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 22:53:43.819520 0 14 24 | B1->B0 | 3332 2d2d | 1 1 | (0 0) (1 0)
5847 22:53:43.822269 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5848 22:53:43.828806 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 22:53:43.832250 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 22:53:43.836258 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 22:53:43.842438 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 22:53:43.845318 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5853 22:53:43.848653 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 22:53:43.855760 0 15 24 | B1->B0 | 2828 3535 | 0 0 | (0 0) (1 1)
5855 22:53:43.858920 0 15 28 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
5856 22:53:43.862058 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 22:53:43.868954 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 22:53:43.872074 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 22:53:43.875451 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 22:53:43.878813 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 22:53:43.885721 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5862 22:53:43.888954 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5863 22:53:43.892439 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5864 22:53:43.898922 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 22:53:43.902460 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 22:53:43.905445 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 22:53:43.912118 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 22:53:43.915413 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 22:53:43.918716 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 22:53:43.925938 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 22:53:43.928814 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 22:53:43.932267 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 22:53:43.939054 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 22:53:43.942023 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 22:53:43.945648 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 22:53:43.952660 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 22:53:43.955572 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 22:53:43.958861 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5879 22:53:43.965465 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 22:53:43.965550 Total UI for P1: 0, mck2ui 16
5881 22:53:43.968960 best dqsien dly found for B0: ( 1, 2, 24)
5882 22:53:43.971827 Total UI for P1: 0, mck2ui 16
5883 22:53:43.975611 best dqsien dly found for B1: ( 1, 2, 26)
5884 22:53:43.982075 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5885 22:53:43.985509 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5886 22:53:43.985594
5887 22:53:43.988770 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5888 22:53:43.991987 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5889 22:53:43.995032 [Gating] SW calibration Done
5890 22:53:43.995117 ==
5891 22:53:43.998693 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 22:53:44.002281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 22:53:44.002366 ==
5894 22:53:44.005274 RX Vref Scan: 0
5895 22:53:44.005358
5896 22:53:44.005443 RX Vref 0 -> 0, step: 1
5897 22:53:44.005523
5898 22:53:44.008803 RX Delay -80 -> 252, step: 8
5899 22:53:44.011915 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5900 22:53:44.015055 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5901 22:53:44.021729 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5902 22:53:44.025267 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5903 22:53:44.028688 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5904 22:53:44.031984 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5905 22:53:44.035032 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5906 22:53:44.038895 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5907 22:53:44.045223 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5908 22:53:44.048489 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5909 22:53:44.052726 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5910 22:53:44.055664 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5911 22:53:44.058913 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5912 22:53:44.062001 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5913 22:53:44.068399 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5914 22:53:44.071716 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5915 22:53:44.071800 ==
5916 22:53:44.075168 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 22:53:44.078773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 22:53:44.078859 ==
5919 22:53:44.078961 DQS Delay:
5920 22:53:44.081976 DQS0 = 0, DQS1 = 0
5921 22:53:44.082059 DQM Delay:
5922 22:53:44.085136 DQM0 = 94, DQM1 = 89
5923 22:53:44.085242 DQ Delay:
5924 22:53:44.089013 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5925 22:53:44.092079 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5926 22:53:44.095290 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5927 22:53:44.098692 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5928 22:53:44.098776
5929 22:53:44.098861
5930 22:53:44.098941 ==
5931 22:53:44.102168 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 22:53:44.105746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 22:53:44.109483 ==
5934 22:53:44.109567
5935 22:53:44.109652
5936 22:53:44.109731 TX Vref Scan disable
5937 22:53:44.112102 == TX Byte 0 ==
5938 22:53:44.115341 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5939 22:53:44.118679 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5940 22:53:44.121941 == TX Byte 1 ==
5941 22:53:44.125777 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5942 22:53:44.128938 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5943 22:53:44.129022 ==
5944 22:53:44.131996 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 22:53:44.138808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 22:53:44.138888 ==
5947 22:53:44.138953
5948 22:53:44.139016
5949 22:53:44.139074 TX Vref Scan disable
5950 22:53:44.143242 == TX Byte 0 ==
5951 22:53:44.146931 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5952 22:53:44.153078 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5953 22:53:44.153183 == TX Byte 1 ==
5954 22:53:44.156160 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5955 22:53:44.162667 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5956 22:53:44.162741
5957 22:53:44.162802 [DATLAT]
5958 22:53:44.162860 Freq=933, CH1 RK1
5959 22:53:44.162923
5960 22:53:44.166469 DATLAT Default: 0xb
5961 22:53:44.166534 0, 0xFFFF, sum = 0
5962 22:53:44.169904 1, 0xFFFF, sum = 0
5963 22:53:44.170005 2, 0xFFFF, sum = 0
5964 22:53:44.173381 3, 0xFFFF, sum = 0
5965 22:53:44.173463 4, 0xFFFF, sum = 0
5966 22:53:44.176753 5, 0xFFFF, sum = 0
5967 22:53:44.179400 6, 0xFFFF, sum = 0
5968 22:53:44.179472 7, 0xFFFF, sum = 0
5969 22:53:44.182966 8, 0xFFFF, sum = 0
5970 22:53:44.183063 9, 0xFFFF, sum = 0
5971 22:53:44.186813 10, 0x0, sum = 1
5972 22:53:44.186922 11, 0x0, sum = 2
5973 22:53:44.187015 12, 0x0, sum = 3
5974 22:53:44.189557 13, 0x0, sum = 4
5975 22:53:44.189629 best_step = 11
5976 22:53:44.189688
5977 22:53:44.189744 ==
5978 22:53:44.193198 Dram Type= 6, Freq= 0, CH_1, rank 1
5979 22:53:44.200031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5980 22:53:44.200105 ==
5981 22:53:44.200166 RX Vref Scan: 0
5982 22:53:44.200227
5983 22:53:44.203551 RX Vref 0 -> 0, step: 1
5984 22:53:44.203645
5985 22:53:44.206663 RX Delay -61 -> 252, step: 4
5986 22:53:44.209744 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5987 22:53:44.213457 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5988 22:53:44.220024 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5989 22:53:44.223099 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5990 22:53:44.226568 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5991 22:53:44.230020 iDelay=199, Bit 5, Center 104 (15 ~ 194) 180
5992 22:53:44.233683 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5993 22:53:44.236198 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5994 22:53:44.242884 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5995 22:53:44.246303 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5996 22:53:44.249416 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5997 22:53:44.253043 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5998 22:53:44.256168 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5999 22:53:44.262921 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
6000 22:53:44.266001 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
6001 22:53:44.270181 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
6002 22:53:44.270255 ==
6003 22:53:44.272908 Dram Type= 6, Freq= 0, CH_1, rank 1
6004 22:53:44.276306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6005 22:53:44.276379 ==
6006 22:53:44.279381 DQS Delay:
6007 22:53:44.279452 DQS0 = 0, DQS1 = 0
6008 22:53:44.279511 DQM Delay:
6009 22:53:44.283274 DQM0 = 95, DQM1 = 91
6010 22:53:44.283342 DQ Delay:
6011 22:53:44.286078 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =94
6012 22:53:44.289236 DQ4 =96, DQ5 =104, DQ6 =106, DQ7 =92
6013 22:53:44.293095 DQ8 =78, DQ9 =78, DQ10 =94, DQ11 =84
6014 22:53:44.296504 DQ12 =96, DQ13 =98, DQ14 =102, DQ15 =98
6015 22:53:44.296577
6016 22:53:44.296637
6017 22:53:44.306434 [DQSOSCAuto] RK1, (LSB)MR18= 0x111a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
6018 22:53:44.309458 CH1 RK1: MR19=505, MR18=111A
6019 22:53:44.312829 CH1_RK1: MR19=0x505, MR18=0x111A, DQSOSC=413, MR23=63, INC=63, DEC=42
6020 22:53:44.316175 [RxdqsGatingPostProcess] freq 933
6021 22:53:44.323054 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6022 22:53:44.326403 best DQS0 dly(2T, 0.5T) = (0, 10)
6023 22:53:44.329440 best DQS1 dly(2T, 0.5T) = (0, 10)
6024 22:53:44.332559 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6025 22:53:44.336441 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6026 22:53:44.338929 best DQS0 dly(2T, 0.5T) = (0, 10)
6027 22:53:44.342603 best DQS1 dly(2T, 0.5T) = (0, 10)
6028 22:53:44.346338 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6029 22:53:44.349362 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6030 22:53:44.352938 Pre-setting of DQS Precalculation
6031 22:53:44.355775 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6032 22:53:44.362363 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6033 22:53:44.369424 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6034 22:53:44.369502
6035 22:53:44.369596
6036 22:53:44.372800 [Calibration Summary] 1866 Mbps
6037 22:53:44.375754 CH 0, Rank 0
6038 22:53:44.375857 SW Impedance : PASS
6039 22:53:44.379460 DUTY Scan : NO K
6040 22:53:44.382722 ZQ Calibration : PASS
6041 22:53:44.382817 Jitter Meter : NO K
6042 22:53:44.386172 CBT Training : PASS
6043 22:53:44.389419 Write leveling : PASS
6044 22:53:44.389521 RX DQS gating : PASS
6045 22:53:44.392568 RX DQ/DQS(RDDQC) : PASS
6046 22:53:44.392639 TX DQ/DQS : PASS
6047 22:53:44.396080 RX DATLAT : PASS
6048 22:53:44.399299 RX DQ/DQS(Engine): PASS
6049 22:53:44.399398 TX OE : NO K
6050 22:53:44.402469 All Pass.
6051 22:53:44.402562
6052 22:53:44.402649 CH 0, Rank 1
6053 22:53:44.405897 SW Impedance : PASS
6054 22:53:44.405993 DUTY Scan : NO K
6055 22:53:44.409630 ZQ Calibration : PASS
6056 22:53:44.412571 Jitter Meter : NO K
6057 22:53:44.412666 CBT Training : PASS
6058 22:53:44.416255 Write leveling : PASS
6059 22:53:44.419569 RX DQS gating : PASS
6060 22:53:44.419644 RX DQ/DQS(RDDQC) : PASS
6061 22:53:44.422453 TX DQ/DQS : PASS
6062 22:53:44.426040 RX DATLAT : PASS
6063 22:53:44.426106 RX DQ/DQS(Engine): PASS
6064 22:53:44.429104 TX OE : NO K
6065 22:53:44.429200 All Pass.
6066 22:53:44.429270
6067 22:53:44.432795 CH 1, Rank 0
6068 22:53:44.432882 SW Impedance : PASS
6069 22:53:44.436284 DUTY Scan : NO K
6070 22:53:44.439125 ZQ Calibration : PASS
6071 22:53:44.439207 Jitter Meter : NO K
6072 22:53:44.442805 CBT Training : PASS
6073 22:53:44.442887 Write leveling : PASS
6074 22:53:44.445908 RX DQS gating : PASS
6075 22:53:44.449535 RX DQ/DQS(RDDQC) : PASS
6076 22:53:44.449617 TX DQ/DQS : PASS
6077 22:53:44.452945 RX DATLAT : PASS
6078 22:53:44.455813 RX DQ/DQS(Engine): PASS
6079 22:53:44.455894 TX OE : NO K
6080 22:53:44.459717 All Pass.
6081 22:53:44.459798
6082 22:53:44.459861 CH 1, Rank 1
6083 22:53:44.462794 SW Impedance : PASS
6084 22:53:44.462875 DUTY Scan : NO K
6085 22:53:44.466419 ZQ Calibration : PASS
6086 22:53:44.469146 Jitter Meter : NO K
6087 22:53:44.469252 CBT Training : PASS
6088 22:53:44.472897 Write leveling : PASS
6089 22:53:44.476229 RX DQS gating : PASS
6090 22:53:44.476310 RX DQ/DQS(RDDQC) : PASS
6091 22:53:44.479317 TX DQ/DQS : PASS
6092 22:53:44.479399 RX DATLAT : PASS
6093 22:53:44.482984 RX DQ/DQS(Engine): PASS
6094 22:53:44.486174 TX OE : NO K
6095 22:53:44.486256 All Pass.
6096 22:53:44.486321
6097 22:53:44.489145 DramC Write-DBI off
6098 22:53:44.489234 PER_BANK_REFRESH: Hybrid Mode
6099 22:53:44.492739 TX_TRACKING: ON
6100 22:53:44.502663 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6101 22:53:44.506077 [FAST_K] Save calibration result to emmc
6102 22:53:44.509500 dramc_set_vcore_voltage set vcore to 650000
6103 22:53:44.509582 Read voltage for 400, 6
6104 22:53:44.513092 Vio18 = 0
6105 22:53:44.513198 Vcore = 650000
6106 22:53:44.513306 Vdram = 0
6107 22:53:44.516241 Vddq = 0
6108 22:53:44.516322 Vmddr = 0
6109 22:53:44.519604 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6110 22:53:44.525859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6111 22:53:44.529676 MEM_TYPE=3, freq_sel=20
6112 22:53:44.533029 sv_algorithm_assistance_LP4_800
6113 22:53:44.535840 ============ PULL DRAM RESETB DOWN ============
6114 22:53:44.539547 ========== PULL DRAM RESETB DOWN end =========
6115 22:53:44.546297 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6116 22:53:44.546379 ===================================
6117 22:53:44.549275 LPDDR4 DRAM CONFIGURATION
6118 22:53:44.552927 ===================================
6119 22:53:44.555863 EX_ROW_EN[0] = 0x0
6120 22:53:44.555944 EX_ROW_EN[1] = 0x0
6121 22:53:44.559321 LP4Y_EN = 0x0
6122 22:53:44.559402 WORK_FSP = 0x0
6123 22:53:44.562820 WL = 0x2
6124 22:53:44.562901 RL = 0x2
6125 22:53:44.566155 BL = 0x2
6126 22:53:44.566237 RPST = 0x0
6127 22:53:44.569440 RD_PRE = 0x0
6128 22:53:44.572905 WR_PRE = 0x1
6129 22:53:44.572987 WR_PST = 0x0
6130 22:53:44.575931 DBI_WR = 0x0
6131 22:53:44.576012 DBI_RD = 0x0
6132 22:53:44.579546 OTF = 0x1
6133 22:53:44.583249 ===================================
6134 22:53:44.585873 ===================================
6135 22:53:44.585955 ANA top config
6136 22:53:44.589191 ===================================
6137 22:53:44.592984 DLL_ASYNC_EN = 0
6138 22:53:44.596274 ALL_SLAVE_EN = 1
6139 22:53:44.596355 NEW_RANK_MODE = 1
6140 22:53:44.599819 DLL_IDLE_MODE = 1
6141 22:53:44.602631 LP45_APHY_COMB_EN = 1
6142 22:53:44.606326 TX_ODT_DIS = 1
6143 22:53:44.606407 NEW_8X_MODE = 1
6144 22:53:44.609406 ===================================
6145 22:53:44.612691 ===================================
6146 22:53:44.616180 data_rate = 800
6147 22:53:44.620533 CKR = 1
6148 22:53:44.622910 DQ_P2S_RATIO = 4
6149 22:53:44.626284 ===================================
6150 22:53:44.629308 CA_P2S_RATIO = 4
6151 22:53:44.632276 DQ_CA_OPEN = 0
6152 22:53:44.632358 DQ_SEMI_OPEN = 1
6153 22:53:44.636337 CA_SEMI_OPEN = 1
6154 22:53:44.639556 CA_FULL_RATE = 0
6155 22:53:44.642445 DQ_CKDIV4_EN = 0
6156 22:53:44.645693 CA_CKDIV4_EN = 1
6157 22:53:44.649609 CA_PREDIV_EN = 0
6158 22:53:44.649691 PH8_DLY = 0
6159 22:53:44.652321 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6160 22:53:44.655957 DQ_AAMCK_DIV = 0
6161 22:53:44.659799 CA_AAMCK_DIV = 0
6162 22:53:44.662720 CA_ADMCK_DIV = 4
6163 22:53:44.662804 DQ_TRACK_CA_EN = 0
6164 22:53:44.665880 CA_PICK = 800
6165 22:53:44.669792 CA_MCKIO = 400
6166 22:53:44.672433 MCKIO_SEMI = 400
6167 22:53:44.676126 PLL_FREQ = 3016
6168 22:53:44.679341 DQ_UI_PI_RATIO = 32
6169 22:53:44.683278 CA_UI_PI_RATIO = 32
6170 22:53:44.685972 ===================================
6171 22:53:44.689330 ===================================
6172 22:53:44.689413 memory_type:LPDDR4
6173 22:53:44.692734 GP_NUM : 10
6174 22:53:44.695537 SRAM_EN : 1
6175 22:53:44.695619 MD32_EN : 0
6176 22:53:44.699313 ===================================
6177 22:53:44.702861 [ANA_INIT] >>>>>>>>>>>>>>
6178 22:53:44.705607 <<<<<< [CONFIGURE PHASE]: ANA_TX
6179 22:53:44.709246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6180 22:53:44.712320 ===================================
6181 22:53:44.715621 data_rate = 800,PCW = 0X7400
6182 22:53:44.719092 ===================================
6183 22:53:44.722145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6184 22:53:44.725739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6185 22:53:44.739445 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6186 22:53:44.742379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6187 22:53:44.746117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6188 22:53:44.749562 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6189 22:53:44.752669 [ANA_INIT] flow start
6190 22:53:44.752750 [ANA_INIT] PLL >>>>>>>>
6191 22:53:44.755976 [ANA_INIT] PLL <<<<<<<<
6192 22:53:44.759301 [ANA_INIT] MIDPI >>>>>>>>
6193 22:53:44.762801 [ANA_INIT] MIDPI <<<<<<<<
6194 22:53:44.762883 [ANA_INIT] DLL >>>>>>>>
6195 22:53:44.765571 [ANA_INIT] flow end
6196 22:53:44.769089 ============ LP4 DIFF to SE enter ============
6197 22:53:44.772879 ============ LP4 DIFF to SE exit ============
6198 22:53:44.775993 [ANA_INIT] <<<<<<<<<<<<<
6199 22:53:44.779094 [Flow] Enable top DCM control >>>>>
6200 22:53:44.782417 [Flow] Enable top DCM control <<<<<
6201 22:53:44.785570 Enable DLL master slave shuffle
6202 22:53:44.792437 ==============================================================
6203 22:53:44.792519 Gating Mode config
6204 22:53:44.799594 ==============================================================
6205 22:53:44.799676 Config description:
6206 22:53:44.809101 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6207 22:53:44.816194 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6208 22:53:44.822039 SELPH_MODE 0: By rank 1: By Phase
6209 22:53:44.825304 ==============================================================
6210 22:53:44.829516 GAT_TRACK_EN = 0
6211 22:53:44.832545 RX_GATING_MODE = 2
6212 22:53:44.835550 RX_GATING_TRACK_MODE = 2
6213 22:53:44.839208 SELPH_MODE = 1
6214 22:53:44.842111 PICG_EARLY_EN = 1
6215 22:53:44.846519 VALID_LAT_VALUE = 1
6216 22:53:44.849403 ==============================================================
6217 22:53:44.852704 Enter into Gating configuration >>>>
6218 22:53:44.855713 Exit from Gating configuration <<<<
6219 22:53:44.859035 Enter into DVFS_PRE_config >>>>>
6220 22:53:44.872391 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6221 22:53:44.875662 Exit from DVFS_PRE_config <<<<<
6222 22:53:44.879915 Enter into PICG configuration >>>>
6223 22:53:44.880018 Exit from PICG configuration <<<<
6224 22:53:44.882961 [RX_INPUT] configuration >>>>>
6225 22:53:44.885861 [RX_INPUT] configuration <<<<<
6226 22:53:44.892463 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6227 22:53:44.895962 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6228 22:53:44.902585 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6229 22:53:44.909362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6230 22:53:44.915572 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6231 22:53:44.922566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6232 22:53:44.925583 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6233 22:53:44.929021 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6234 22:53:44.932476 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6235 22:53:44.938941 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6236 22:53:44.942192 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6237 22:53:44.945847 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6238 22:53:44.948880 ===================================
6239 22:53:44.952385 LPDDR4 DRAM CONFIGURATION
6240 22:53:44.956198 ===================================
6241 22:53:44.956267 EX_ROW_EN[0] = 0x0
6242 22:53:44.958950 EX_ROW_EN[1] = 0x0
6243 22:53:44.962440 LP4Y_EN = 0x0
6244 22:53:44.962510 WORK_FSP = 0x0
6245 22:53:44.966337 WL = 0x2
6246 22:53:44.966405 RL = 0x2
6247 22:53:44.969078 BL = 0x2
6248 22:53:44.969173 RPST = 0x0
6249 22:53:44.972398 RD_PRE = 0x0
6250 22:53:44.972493 WR_PRE = 0x1
6251 22:53:44.976003 WR_PST = 0x0
6252 22:53:44.976103 DBI_WR = 0x0
6253 22:53:44.979000 DBI_RD = 0x0
6254 22:53:44.979097 OTF = 0x1
6255 22:53:44.982692 ===================================
6256 22:53:44.985779 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6257 22:53:44.992430 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6258 22:53:44.995676 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6259 22:53:44.999051 ===================================
6260 22:53:45.002272 LPDDR4 DRAM CONFIGURATION
6261 22:53:45.005936 ===================================
6262 22:53:45.006009 EX_ROW_EN[0] = 0x10
6263 22:53:45.008976 EX_ROW_EN[1] = 0x0
6264 22:53:45.009073 LP4Y_EN = 0x0
6265 22:53:45.013119 WORK_FSP = 0x0
6266 22:53:45.013220 WL = 0x2
6267 22:53:45.016195 RL = 0x2
6268 22:53:45.016287 BL = 0x2
6269 22:53:45.019224 RPST = 0x0
6270 22:53:45.022436 RD_PRE = 0x0
6271 22:53:45.022505 WR_PRE = 0x1
6272 22:53:45.025546 WR_PST = 0x0
6273 22:53:45.025614 DBI_WR = 0x0
6274 22:53:45.029797 DBI_RD = 0x0
6275 22:53:45.029894 OTF = 0x1
6276 22:53:45.032555 ===================================
6277 22:53:45.039039 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6278 22:53:45.042478 nWR fixed to 30
6279 22:53:45.046644 [ModeRegInit_LP4] CH0 RK0
6280 22:53:45.046714 [ModeRegInit_LP4] CH0 RK1
6281 22:53:45.049380 [ModeRegInit_LP4] CH1 RK0
6282 22:53:45.052831 [ModeRegInit_LP4] CH1 RK1
6283 22:53:45.052900 match AC timing 19
6284 22:53:45.059741 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6285 22:53:45.062926 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6286 22:53:45.066331 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6287 22:53:45.072713 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6288 22:53:45.076453 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6289 22:53:45.076553 ==
6290 22:53:45.079481 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 22:53:45.082603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 22:53:45.082702 ==
6293 22:53:45.089601 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6294 22:53:45.096117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6295 22:53:45.100562 [CA 0] Center 36 (8~64) winsize 57
6296 22:53:45.100635 [CA 1] Center 36 (8~64) winsize 57
6297 22:53:45.103082 [CA 2] Center 36 (8~64) winsize 57
6298 22:53:45.106732 [CA 3] Center 36 (8~64) winsize 57
6299 22:53:45.109530 [CA 4] Center 36 (8~64) winsize 57
6300 22:53:45.112875 [CA 5] Center 36 (8~64) winsize 57
6301 22:53:45.112973
6302 22:53:45.116472 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6303 22:53:45.116561
6304 22:53:45.119452 [CATrainingPosCal] consider 1 rank data
6305 22:53:45.123227 u2DelayCellTimex100 = 270/100 ps
6306 22:53:45.126444 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 22:53:45.132893 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 22:53:45.136136 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 22:53:45.139758 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 22:53:45.143166 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 22:53:45.146114 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 22:53:45.146185
6313 22:53:45.149426 CA PerBit enable=1, Macro0, CA PI delay=36
6314 22:53:45.149499
6315 22:53:45.152668 [CBTSetCACLKResult] CA Dly = 36
6316 22:53:45.152765 CS Dly: 1 (0~32)
6317 22:53:45.156109 ==
6318 22:53:45.159767 Dram Type= 6, Freq= 0, CH_0, rank 1
6319 22:53:45.163362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 22:53:45.163433 ==
6321 22:53:45.166016 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6322 22:53:45.172790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6323 22:53:45.176300 [CA 0] Center 36 (8~64) winsize 57
6324 22:53:45.179140 [CA 1] Center 36 (8~64) winsize 57
6325 22:53:45.183238 [CA 2] Center 36 (8~64) winsize 57
6326 22:53:45.186251 [CA 3] Center 36 (8~64) winsize 57
6327 22:53:45.189634 [CA 4] Center 36 (8~64) winsize 57
6328 22:53:45.192724 [CA 5] Center 36 (8~64) winsize 57
6329 22:53:45.192807
6330 22:53:45.196073 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6331 22:53:45.196156
6332 22:53:45.199340 [CATrainingPosCal] consider 2 rank data
6333 22:53:45.202801 u2DelayCellTimex100 = 270/100 ps
6334 22:53:45.206136 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 22:53:45.209443 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 22:53:45.213099 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 22:53:45.215878 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 22:53:45.222650 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 22:53:45.226164 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 22:53:45.226247
6341 22:53:45.229633 CA PerBit enable=1, Macro0, CA PI delay=36
6342 22:53:45.229715
6343 22:53:45.232708 [CBTSetCACLKResult] CA Dly = 36
6344 22:53:45.232790 CS Dly: 1 (0~32)
6345 22:53:45.232854
6346 22:53:45.236059 ----->DramcWriteLeveling(PI) begin...
6347 22:53:45.236143 ==
6348 22:53:45.239358 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 22:53:45.246492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 22:53:45.246579 ==
6351 22:53:45.246668 Write leveling (Byte 0): 40 => 8
6352 22:53:45.249358 Write leveling (Byte 1): 32 => 0
6353 22:53:45.252948 DramcWriteLeveling(PI) end<-----
6354 22:53:45.253031
6355 22:53:45.253095 ==
6356 22:53:45.256293 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 22:53:45.263315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 22:53:45.263398 ==
6359 22:53:45.263464 [Gating] SW mode calibration
6360 22:53:45.272725 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6361 22:53:45.276183 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6362 22:53:45.279611 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6363 22:53:45.286172 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6364 22:53:45.289826 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6365 22:53:45.293312 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6366 22:53:45.299267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6367 22:53:45.303252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6368 22:53:45.305977 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6369 22:53:45.312484 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6370 22:53:45.315975 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6371 22:53:45.319298 Total UI for P1: 0, mck2ui 16
6372 22:53:45.323119 best dqsien dly found for B0: ( 0, 14, 24)
6373 22:53:45.325907 Total UI for P1: 0, mck2ui 16
6374 22:53:45.329746 best dqsien dly found for B1: ( 0, 14, 24)
6375 22:53:45.332671 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6376 22:53:45.336044 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6377 22:53:45.336129
6378 22:53:45.339386 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6379 22:53:45.342678 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6380 22:53:45.345861 [Gating] SW calibration Done
6381 22:53:45.345930 ==
6382 22:53:45.349331 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 22:53:45.352639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 22:53:45.356263 ==
6385 22:53:45.356335 RX Vref Scan: 0
6386 22:53:45.356398
6387 22:53:45.359558 RX Vref 0 -> 0, step: 1
6388 22:53:45.359653
6389 22:53:45.362768 RX Delay -410 -> 252, step: 16
6390 22:53:45.365890 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6391 22:53:45.369277 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6392 22:53:45.372784 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6393 22:53:45.379511 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6394 22:53:45.383125 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6395 22:53:45.385781 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6396 22:53:45.389215 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6397 22:53:45.396348 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6398 22:53:45.400136 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6399 22:53:45.402714 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6400 22:53:45.405907 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6401 22:53:45.412987 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6402 22:53:45.416025 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6403 22:53:45.419741 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6404 22:53:45.422875 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6405 22:53:45.429457 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6406 22:53:45.429540 ==
6407 22:53:45.432301 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 22:53:45.436066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 22:53:45.436148 ==
6410 22:53:45.436212 DQS Delay:
6411 22:53:45.439184 DQS0 = 35, DQS1 = 51
6412 22:53:45.439266 DQM Delay:
6413 22:53:45.442783 DQM0 = 6, DQM1 = 10
6414 22:53:45.442865 DQ Delay:
6415 22:53:45.446336 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6416 22:53:45.449541 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6417 22:53:45.452611 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6418 22:53:45.455610 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6419 22:53:45.455692
6420 22:53:45.455755
6421 22:53:45.455815 ==
6422 22:53:45.459196 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 22:53:45.462861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 22:53:45.462944 ==
6425 22:53:45.463008
6426 22:53:45.463068
6427 22:53:45.465890 TX Vref Scan disable
6428 22:53:45.469599 == TX Byte 0 ==
6429 22:53:45.472614 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6430 22:53:45.476314 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6431 22:53:45.476396 == TX Byte 1 ==
6432 22:53:45.482367 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6433 22:53:45.485930 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6434 22:53:45.486013 ==
6435 22:53:45.489048 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 22:53:45.492678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 22:53:45.492762 ==
6438 22:53:45.492827
6439 22:53:45.492887
6440 22:53:45.495705 TX Vref Scan disable
6441 22:53:45.499384 == TX Byte 0 ==
6442 22:53:45.503200 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6443 22:53:45.506462 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6444 22:53:45.506544 == TX Byte 1 ==
6445 22:53:45.512479 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6446 22:53:45.516389 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6447 22:53:45.516471
6448 22:53:45.516534 [DATLAT]
6449 22:53:45.519965 Freq=400, CH0 RK0
6450 22:53:45.520046
6451 22:53:45.520111 DATLAT Default: 0xf
6452 22:53:45.522701 0, 0xFFFF, sum = 0
6453 22:53:45.522785 1, 0xFFFF, sum = 0
6454 22:53:45.526168 2, 0xFFFF, sum = 0
6455 22:53:45.526251 3, 0xFFFF, sum = 0
6456 22:53:45.529457 4, 0xFFFF, sum = 0
6457 22:53:45.532800 5, 0xFFFF, sum = 0
6458 22:53:45.532884 6, 0xFFFF, sum = 0
6459 22:53:45.536225 7, 0xFFFF, sum = 0
6460 22:53:45.536309 8, 0xFFFF, sum = 0
6461 22:53:45.539538 9, 0xFFFF, sum = 0
6462 22:53:45.539622 10, 0xFFFF, sum = 0
6463 22:53:45.542497 11, 0xFFFF, sum = 0
6464 22:53:45.542581 12, 0xFFFF, sum = 0
6465 22:53:45.545928 13, 0x0, sum = 1
6466 22:53:45.546012 14, 0x0, sum = 2
6467 22:53:45.549087 15, 0x0, sum = 3
6468 22:53:45.549170 16, 0x0, sum = 4
6469 22:53:45.552521 best_step = 14
6470 22:53:45.552603
6471 22:53:45.552668 ==
6472 22:53:45.555868 Dram Type= 6, Freq= 0, CH_0, rank 0
6473 22:53:45.559618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 22:53:45.559701 ==
6475 22:53:45.559766 RX Vref Scan: 1
6476 22:53:45.559826
6477 22:53:45.562484 RX Vref 0 -> 0, step: 1
6478 22:53:45.562567
6479 22:53:45.565670 RX Delay -343 -> 252, step: 8
6480 22:53:45.565753
6481 22:53:45.569151 Set Vref, RX VrefLevel [Byte0]: 53
6482 22:53:45.572489 [Byte1]: 51
6483 22:53:45.576284
6484 22:53:45.576366 Final RX Vref Byte 0 = 53 to rank0
6485 22:53:45.579753 Final RX Vref Byte 1 = 51 to rank0
6486 22:53:45.584039 Final RX Vref Byte 0 = 53 to rank1
6487 22:53:45.586596 Final RX Vref Byte 1 = 51 to rank1==
6488 22:53:45.590177 Dram Type= 6, Freq= 0, CH_0, rank 0
6489 22:53:45.596340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 22:53:45.596423 ==
6491 22:53:45.596488 DQS Delay:
6492 22:53:45.599995 DQS0 = 44, DQS1 = 60
6493 22:53:45.600081 DQM Delay:
6494 22:53:45.600147 DQM0 = 11, DQM1 = 13
6495 22:53:45.603133 DQ Delay:
6496 22:53:45.606384 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6497 22:53:45.606466 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6498 22:53:45.609910 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6499 22:53:45.613264 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6500 22:53:45.613346
6501 22:53:45.616819
6502 22:53:45.623037 [DQSOSCAuto] RK0, (LSB)MR18= 0x8756, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6503 22:53:45.626532 CH0 RK0: MR19=C0C, MR18=8756
6504 22:53:45.632907 CH0_RK0: MR19=0xC0C, MR18=0x8756, DQSOSC=392, MR23=63, INC=384, DEC=256
6505 22:53:45.632990 ==
6506 22:53:45.636399 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 22:53:45.639770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 22:53:45.639853 ==
6509 22:53:45.643024 [Gating] SW mode calibration
6510 22:53:45.650221 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6511 22:53:45.656208 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6512 22:53:45.659801 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6513 22:53:45.663157 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6514 22:53:45.666459 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6515 22:53:45.673002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6516 22:53:45.676598 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6517 22:53:45.679889 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6518 22:53:45.686236 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6519 22:53:45.689504 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 22:53:45.693132 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6521 22:53:45.696427 Total UI for P1: 0, mck2ui 16
6522 22:53:45.699438 best dqsien dly found for B0: ( 0, 14, 24)
6523 22:53:45.703053 Total UI for P1: 0, mck2ui 16
6524 22:53:45.706122 best dqsien dly found for B1: ( 0, 14, 24)
6525 22:53:45.709975 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6526 22:53:45.713440 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6527 22:53:45.713522
6528 22:53:45.719683 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6529 22:53:45.722894 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6530 22:53:45.726232 [Gating] SW calibration Done
6531 22:53:45.726315 ==
6532 22:53:45.729688 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 22:53:45.733243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 22:53:45.733327 ==
6535 22:53:45.733392 RX Vref Scan: 0
6536 22:53:45.733452
6537 22:53:45.736622 RX Vref 0 -> 0, step: 1
6538 22:53:45.736704
6539 22:53:45.739845 RX Delay -410 -> 252, step: 16
6540 22:53:45.743424 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6541 22:53:45.746521 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6542 22:53:45.753221 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6543 22:53:45.756484 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6544 22:53:45.760017 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6545 22:53:45.763105 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6546 22:53:45.769757 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6547 22:53:45.773546 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6548 22:53:45.776508 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6549 22:53:45.779613 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6550 22:53:45.786617 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6551 22:53:45.789633 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6552 22:53:45.792878 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6553 22:53:45.796424 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6554 22:53:45.802910 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6555 22:53:45.806556 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6556 22:53:45.806640 ==
6557 22:53:45.809648 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 22:53:45.813315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 22:53:45.813399 ==
6560 22:53:45.816309 DQS Delay:
6561 22:53:45.816391 DQS0 = 43, DQS1 = 51
6562 22:53:45.819936 DQM Delay:
6563 22:53:45.820019 DQM0 = 11, DQM1 = 10
6564 22:53:45.820084 DQ Delay:
6565 22:53:45.823299 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6566 22:53:45.826666 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6567 22:53:45.829743 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6568 22:53:45.833179 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6569 22:53:45.833278
6570 22:53:45.833344
6571 22:53:45.833404 ==
6572 22:53:45.836513 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 22:53:45.840265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 22:53:45.842917 ==
6575 22:53:45.842999
6576 22:53:45.843064
6577 22:53:45.843124 TX Vref Scan disable
6578 22:53:45.846511 == TX Byte 0 ==
6579 22:53:45.849941 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6580 22:53:45.853321 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6581 22:53:45.856263 == TX Byte 1 ==
6582 22:53:45.859443 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6583 22:53:45.862922 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6584 22:53:45.863005 ==
6585 22:53:45.867212 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 22:53:45.872920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 22:53:45.873007 ==
6588 22:53:45.873072
6589 22:53:45.873132
6590 22:53:45.873190 TX Vref Scan disable
6591 22:53:45.876646 == TX Byte 0 ==
6592 22:53:45.879814 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6593 22:53:45.882807 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6594 22:53:45.886811 == TX Byte 1 ==
6595 22:53:45.889977 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6596 22:53:45.893454 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6597 22:53:45.893537
6598 22:53:45.896397 [DATLAT]
6599 22:53:45.896504 Freq=400, CH0 RK1
6600 22:53:45.896598
6601 22:53:45.900036 DATLAT Default: 0xe
6602 22:53:45.900122 0, 0xFFFF, sum = 0
6603 22:53:45.903035 1, 0xFFFF, sum = 0
6604 22:53:45.903118 2, 0xFFFF, sum = 0
6605 22:53:45.906382 3, 0xFFFF, sum = 0
6606 22:53:45.906466 4, 0xFFFF, sum = 0
6607 22:53:45.909808 5, 0xFFFF, sum = 0
6608 22:53:45.909893 6, 0xFFFF, sum = 0
6609 22:53:45.913017 7, 0xFFFF, sum = 0
6610 22:53:45.913101 8, 0xFFFF, sum = 0
6611 22:53:45.916257 9, 0xFFFF, sum = 0
6612 22:53:45.916341 10, 0xFFFF, sum = 0
6613 22:53:45.919419 11, 0xFFFF, sum = 0
6614 22:53:45.919503 12, 0xFFFF, sum = 0
6615 22:53:45.922832 13, 0x0, sum = 1
6616 22:53:45.922916 14, 0x0, sum = 2
6617 22:53:45.926401 15, 0x0, sum = 3
6618 22:53:45.926484 16, 0x0, sum = 4
6619 22:53:45.929869 best_step = 14
6620 22:53:45.929951
6621 22:53:45.930016 ==
6622 22:53:45.933067 Dram Type= 6, Freq= 0, CH_0, rank 1
6623 22:53:45.937065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 22:53:45.937147 ==
6625 22:53:45.939576 RX Vref Scan: 0
6626 22:53:45.939658
6627 22:53:45.939723 RX Vref 0 -> 0, step: 1
6628 22:53:45.939784
6629 22:53:45.943126 RX Delay -343 -> 252, step: 8
6630 22:53:45.950596 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6631 22:53:45.954234 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6632 22:53:45.957507 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6633 22:53:45.961161 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6634 22:53:45.967589 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6635 22:53:45.970684 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6636 22:53:45.974336 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6637 22:53:45.977450 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6638 22:53:45.984020 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6639 22:53:45.987725 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6640 22:53:45.990699 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6641 22:53:45.993950 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6642 22:53:46.001146 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6643 22:53:46.003957 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6644 22:53:46.007601 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6645 22:53:46.013918 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6646 22:53:46.014001 ==
6647 22:53:46.018024 Dram Type= 6, Freq= 0, CH_0, rank 1
6648 22:53:46.021162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 22:53:46.021272 ==
6650 22:53:46.021338 DQS Delay:
6651 22:53:46.024026 DQS0 = 48, DQS1 = 56
6652 22:53:46.024111 DQM Delay:
6653 22:53:46.027864 DQM0 = 12, DQM1 = 10
6654 22:53:46.027947 DQ Delay:
6655 22:53:46.030813 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6656 22:53:46.033920 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6657 22:53:46.037304 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =0
6658 22:53:46.040778 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6659 22:53:46.040860
6660 22:53:46.040924
6661 22:53:46.047242 [DQSOSCAuto] RK1, (LSB)MR18= 0x9366, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6662 22:53:46.050914 CH0 RK1: MR19=C0C, MR18=9366
6663 22:53:46.057681 CH0_RK1: MR19=0xC0C, MR18=0x9366, DQSOSC=391, MR23=63, INC=386, DEC=257
6664 22:53:46.061064 [RxdqsGatingPostProcess] freq 400
6665 22:53:46.064177 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6666 22:53:46.067599 best DQS0 dly(2T, 0.5T) = (0, 10)
6667 22:53:46.071203 best DQS1 dly(2T, 0.5T) = (0, 10)
6668 22:53:46.074760 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6669 22:53:46.077580 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6670 22:53:46.081113 best DQS0 dly(2T, 0.5T) = (0, 10)
6671 22:53:46.084853 best DQS1 dly(2T, 0.5T) = (0, 10)
6672 22:53:46.088003 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6673 22:53:46.090707 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6674 22:53:46.094139 Pre-setting of DQS Precalculation
6675 22:53:46.097577 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6676 22:53:46.097660 ==
6677 22:53:46.100599 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 22:53:46.107714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 22:53:46.107797 ==
6680 22:53:46.110769 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6681 22:53:46.117416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6682 22:53:46.121078 [CA 0] Center 36 (8~64) winsize 57
6683 22:53:46.124352 [CA 1] Center 36 (8~64) winsize 57
6684 22:53:46.127517 [CA 2] Center 36 (8~64) winsize 57
6685 22:53:46.131084 [CA 3] Center 36 (8~64) winsize 57
6686 22:53:46.134581 [CA 4] Center 36 (8~64) winsize 57
6687 22:53:46.137756 [CA 5] Center 36 (8~64) winsize 57
6688 22:53:46.137839
6689 22:53:46.141262 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6690 22:53:46.141345
6691 22:53:46.144272 [CATrainingPosCal] consider 1 rank data
6692 22:53:46.147232 u2DelayCellTimex100 = 270/100 ps
6693 22:53:46.150727 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 22:53:46.154015 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 22:53:46.158456 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 22:53:46.160735 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 22:53:46.164224 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 22:53:46.167513 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 22:53:46.167596
6700 22:53:46.174231 CA PerBit enable=1, Macro0, CA PI delay=36
6701 22:53:46.174314
6702 22:53:46.174379 [CBTSetCACLKResult] CA Dly = 36
6703 22:53:46.177754 CS Dly: 1 (0~32)
6704 22:53:46.177836 ==
6705 22:53:46.180637 Dram Type= 6, Freq= 0, CH_1, rank 1
6706 22:53:46.184557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 22:53:46.184640 ==
6708 22:53:46.190554 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6709 22:53:46.197465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6710 22:53:46.200769 [CA 0] Center 36 (8~64) winsize 57
6711 22:53:46.204011 [CA 1] Center 36 (8~64) winsize 57
6712 22:53:46.207694 [CA 2] Center 36 (8~64) winsize 57
6713 22:53:46.207777 [CA 3] Center 36 (8~64) winsize 57
6714 22:53:46.210918 [CA 4] Center 36 (8~64) winsize 57
6715 22:53:46.214511 [CA 5] Center 36 (8~64) winsize 57
6716 22:53:46.214593
6717 22:53:46.221334 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6718 22:53:46.221416
6719 22:53:46.224827 [CATrainingPosCal] consider 2 rank data
6720 22:53:46.224910 u2DelayCellTimex100 = 270/100 ps
6721 22:53:46.230587 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 22:53:46.234390 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 22:53:46.237551 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 22:53:46.240922 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 22:53:46.244060 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 22:53:46.247355 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 22:53:46.247437
6728 22:53:46.250522 CA PerBit enable=1, Macro0, CA PI delay=36
6729 22:53:46.250605
6730 22:53:46.254436 [CBTSetCACLKResult] CA Dly = 36
6731 22:53:46.257905 CS Dly: 1 (0~32)
6732 22:53:46.257988
6733 22:53:46.260649 ----->DramcWriteLeveling(PI) begin...
6734 22:53:46.260733 ==
6735 22:53:46.263969 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 22:53:46.267337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 22:53:46.267420 ==
6738 22:53:46.271145 Write leveling (Byte 0): 40 => 8
6739 22:53:46.274205 Write leveling (Byte 1): 40 => 8
6740 22:53:46.277616 DramcWriteLeveling(PI) end<-----
6741 22:53:46.277712
6742 22:53:46.277778 ==
6743 22:53:46.280644 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 22:53:46.284022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 22:53:46.284106 ==
6746 22:53:46.287183 [Gating] SW mode calibration
6747 22:53:46.294240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6748 22:53:46.300924 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6749 22:53:46.304272 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6750 22:53:46.307412 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6751 22:53:46.314190 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6752 22:53:46.317995 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6753 22:53:46.321047 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6754 22:53:46.324260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6755 22:53:46.331349 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6756 22:53:46.334910 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6757 22:53:46.338077 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6758 22:53:46.340767 Total UI for P1: 0, mck2ui 16
6759 22:53:46.344012 best dqsien dly found for B0: ( 0, 14, 24)
6760 22:53:46.347827 Total UI for P1: 0, mck2ui 16
6761 22:53:46.351293 best dqsien dly found for B1: ( 0, 14, 24)
6762 22:53:46.354334 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6763 22:53:46.357772 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6764 22:53:46.360783
6765 22:53:46.364159 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6766 22:53:46.367553 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6767 22:53:46.370894 [Gating] SW calibration Done
6768 22:53:46.370978 ==
6769 22:53:46.374142 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 22:53:46.377886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 22:53:46.377966 ==
6772 22:53:46.378030 RX Vref Scan: 0
6773 22:53:46.381382
6774 22:53:46.381457 RX Vref 0 -> 0, step: 1
6775 22:53:46.381520
6776 22:53:46.383960 RX Delay -410 -> 252, step: 16
6777 22:53:46.387559 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6778 22:53:46.393954 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6779 22:53:46.397427 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6780 22:53:46.400976 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6781 22:53:46.403755 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6782 22:53:46.411021 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6783 22:53:46.413854 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6784 22:53:46.417310 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6785 22:53:46.420793 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6786 22:53:46.427132 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6787 22:53:46.430914 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6788 22:53:46.433888 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6789 22:53:46.437465 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6790 22:53:46.444152 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6791 22:53:46.447498 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6792 22:53:46.450540 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6793 22:53:46.450626 ==
6794 22:53:46.454206 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 22:53:46.457312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 22:53:46.461299 ==
6797 22:53:46.461374 DQS Delay:
6798 22:53:46.461444 DQS0 = 51, DQS1 = 59
6799 22:53:46.463864 DQM Delay:
6800 22:53:46.463933 DQM0 = 19, DQM1 = 17
6801 22:53:46.468032 DQ Delay:
6802 22:53:46.468147 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6803 22:53:46.471095 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6804 22:53:46.474589 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6805 22:53:46.477514 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6806 22:53:46.477599
6807 22:53:46.477663
6808 22:53:46.480529 ==
6809 22:53:46.484425 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 22:53:46.488062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 22:53:46.488138 ==
6812 22:53:46.488229
6813 22:53:46.488319
6814 22:53:46.490726 TX Vref Scan disable
6815 22:53:46.490804 == TX Byte 0 ==
6816 22:53:46.494520 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6817 22:53:46.500681 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6818 22:53:46.500760 == TX Byte 1 ==
6819 22:53:46.504471 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 22:53:46.507509 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 22:53:46.510827 ==
6822 22:53:46.514014 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 22:53:46.518002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 22:53:46.518077 ==
6825 22:53:46.518139
6826 22:53:46.518204
6827 22:53:46.520962 TX Vref Scan disable
6828 22:53:46.521035 == TX Byte 0 ==
6829 22:53:46.524244 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6830 22:53:46.530953 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6831 22:53:46.531066 == TX Byte 1 ==
6832 22:53:46.534338 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6833 22:53:46.537589 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6834 22:53:46.541088
6835 22:53:46.541223 [DATLAT]
6836 22:53:46.541304 Freq=400, CH1 RK0
6837 22:53:46.541365
6838 22:53:46.544438 DATLAT Default: 0xf
6839 22:53:46.544511 0, 0xFFFF, sum = 0
6840 22:53:46.547660 1, 0xFFFF, sum = 0
6841 22:53:46.547736 2, 0xFFFF, sum = 0
6842 22:53:46.550847 3, 0xFFFF, sum = 0
6843 22:53:46.550935 4, 0xFFFF, sum = 0
6844 22:53:46.554428 5, 0xFFFF, sum = 0
6845 22:53:46.554512 6, 0xFFFF, sum = 0
6846 22:53:46.558186 7, 0xFFFF, sum = 0
6847 22:53:46.560722 8, 0xFFFF, sum = 0
6848 22:53:46.560795 9, 0xFFFF, sum = 0
6849 22:53:46.564311 10, 0xFFFF, sum = 0
6850 22:53:46.564395 11, 0xFFFF, sum = 0
6851 22:53:46.567531 12, 0xFFFF, sum = 0
6852 22:53:46.567615 13, 0x0, sum = 1
6853 22:53:46.571236 14, 0x0, sum = 2
6854 22:53:46.571320 15, 0x0, sum = 3
6855 22:53:46.571387 16, 0x0, sum = 4
6856 22:53:46.574818 best_step = 14
6857 22:53:46.574901
6858 22:53:46.574971 ==
6859 22:53:46.578088 Dram Type= 6, Freq= 0, CH_1, rank 0
6860 22:53:46.581146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 22:53:46.581268 ==
6862 22:53:46.584996 RX Vref Scan: 1
6863 22:53:46.585081
6864 22:53:46.585178 RX Vref 0 -> 0, step: 1
6865 22:53:46.588385
6866 22:53:46.588467 RX Delay -359 -> 252, step: 8
6867 22:53:46.588532
6868 22:53:46.590981 Set Vref, RX VrefLevel [Byte0]: 57
6869 22:53:46.594502 [Byte1]: 52
6870 22:53:46.599656
6871 22:53:46.599738 Final RX Vref Byte 0 = 57 to rank0
6872 22:53:46.603731 Final RX Vref Byte 1 = 52 to rank0
6873 22:53:46.606273 Final RX Vref Byte 0 = 57 to rank1
6874 22:53:46.609714 Final RX Vref Byte 1 = 52 to rank1==
6875 22:53:46.612667 Dram Type= 6, Freq= 0, CH_1, rank 0
6876 22:53:46.619739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 22:53:46.619823 ==
6878 22:53:46.619888 DQS Delay:
6879 22:53:46.622823 DQS0 = 48, DQS1 = 60
6880 22:53:46.622906 DQM Delay:
6881 22:53:46.622971 DQM0 = 11, DQM1 = 12
6882 22:53:46.626520 DQ Delay:
6883 22:53:46.629847 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6884 22:53:46.629929 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6885 22:53:46.633476 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6886 22:53:46.636470 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6887 22:53:46.636553
6888 22:53:46.636617
6889 22:53:46.646579 [DQSOSCAuto] RK0, (LSB)MR18= 0x8329, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6890 22:53:46.649822 CH1 RK0: MR19=C0C, MR18=8329
6891 22:53:46.656696 CH1_RK0: MR19=0xC0C, MR18=0x8329, DQSOSC=393, MR23=63, INC=382, DEC=254
6892 22:53:46.656779 ==
6893 22:53:46.659574 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 22:53:46.663260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 22:53:46.663343 ==
6896 22:53:46.666544 [Gating] SW mode calibration
6897 22:53:46.673386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6898 22:53:46.676348 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6899 22:53:46.683272 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6900 22:53:46.686527 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6901 22:53:46.689555 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6902 22:53:46.695973 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6903 22:53:46.699615 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6904 22:53:46.703131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6905 22:53:46.709321 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6906 22:53:46.712790 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6907 22:53:46.716354 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6908 22:53:46.719624 Total UI for P1: 0, mck2ui 16
6909 22:53:46.722950 best dqsien dly found for B0: ( 0, 14, 24)
6910 22:53:46.726414 Total UI for P1: 0, mck2ui 16
6911 22:53:46.729664 best dqsien dly found for B1: ( 0, 14, 24)
6912 22:53:46.733387 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6913 22:53:46.736217 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6914 22:53:46.736351
6915 22:53:46.742945 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6916 22:53:46.746011 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6917 22:53:46.746094 [Gating] SW calibration Done
6918 22:53:46.749596 ==
6919 22:53:46.752769 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 22:53:46.756021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 22:53:46.756104 ==
6922 22:53:46.756169 RX Vref Scan: 0
6923 22:53:46.756230
6924 22:53:46.759271 RX Vref 0 -> 0, step: 1
6925 22:53:46.759353
6926 22:53:46.762849 RX Delay -410 -> 252, step: 16
6927 22:53:46.766301 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6928 22:53:46.769404 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6929 22:53:46.775998 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6930 22:53:46.779907 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6931 22:53:46.782929 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6932 22:53:46.785944 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6933 22:53:46.793195 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6934 22:53:46.795911 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6935 22:53:46.799160 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6936 22:53:46.802568 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6937 22:53:46.809365 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6938 22:53:46.812528 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6939 22:53:46.815767 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6940 22:53:46.822582 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6941 22:53:46.826522 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6942 22:53:46.829391 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6943 22:53:46.829473 ==
6944 22:53:46.833123 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 22:53:46.836026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 22:53:46.836112 ==
6947 22:53:46.839597 DQS Delay:
6948 22:53:46.839698 DQS0 = 43, DQS1 = 59
6949 22:53:46.843139 DQM Delay:
6950 22:53:46.843250 DQM0 = 9, DQM1 = 19
6951 22:53:46.843341 DQ Delay:
6952 22:53:46.846189 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6953 22:53:46.849379 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6954 22:53:46.852591 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6955 22:53:46.856074 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6956 22:53:46.856153
6957 22:53:46.856215
6958 22:53:46.856273 ==
6959 22:53:46.859308 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 22:53:46.866222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 22:53:46.866297 ==
6962 22:53:46.866359
6963 22:53:46.866424
6964 22:53:46.866480 TX Vref Scan disable
6965 22:53:46.869384 == TX Byte 0 ==
6966 22:53:46.872741 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6967 22:53:46.876272 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6968 22:53:46.879236 == TX Byte 1 ==
6969 22:53:46.883079 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6970 22:53:46.885868 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6971 22:53:46.885945 ==
6972 22:53:46.889371 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 22:53:46.895949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 22:53:46.896025 ==
6975 22:53:46.896087
6976 22:53:46.896153
6977 22:53:46.896253 TX Vref Scan disable
6978 22:53:46.899819 == TX Byte 0 ==
6979 22:53:46.903132 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6980 22:53:46.906064 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6981 22:53:46.909432 == TX Byte 1 ==
6982 22:53:46.912681 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6983 22:53:46.915983 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6984 22:53:46.916055
6985 22:53:46.916116 [DATLAT]
6986 22:53:46.920042 Freq=400, CH1 RK1
6987 22:53:46.920114
6988 22:53:46.922870 DATLAT Default: 0xe
6989 22:53:46.922943 0, 0xFFFF, sum = 0
6990 22:53:46.926988 1, 0xFFFF, sum = 0
6991 22:53:46.927085 2, 0xFFFF, sum = 0
6992 22:53:46.929609 3, 0xFFFF, sum = 0
6993 22:53:46.929683 4, 0xFFFF, sum = 0
6994 22:53:46.933564 5, 0xFFFF, sum = 0
6995 22:53:46.933643 6, 0xFFFF, sum = 0
6996 22:53:46.936106 7, 0xFFFF, sum = 0
6997 22:53:46.936178 8, 0xFFFF, sum = 0
6998 22:53:46.939514 9, 0xFFFF, sum = 0
6999 22:53:46.939590 10, 0xFFFF, sum = 0
7000 22:53:46.942725 11, 0xFFFF, sum = 0
7001 22:53:46.942833 12, 0xFFFF, sum = 0
7002 22:53:46.946081 13, 0x0, sum = 1
7003 22:53:46.946167 14, 0x0, sum = 2
7004 22:53:46.949600 15, 0x0, sum = 3
7005 22:53:46.949676 16, 0x0, sum = 4
7006 22:53:46.952891 best_step = 14
7007 22:53:46.952971
7008 22:53:46.953033 ==
7009 22:53:46.956506 Dram Type= 6, Freq= 0, CH_1, rank 1
7010 22:53:46.959471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7011 22:53:46.959546 ==
7012 22:53:46.962824 RX Vref Scan: 0
7013 22:53:46.962916
7014 22:53:46.963009 RX Vref 0 -> 0, step: 1
7015 22:53:46.963106
7016 22:53:46.966017 RX Delay -359 -> 252, step: 8
7017 22:53:46.973580 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7018 22:53:46.977619 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7019 22:53:46.980928 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7020 22:53:46.984056 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7021 22:53:46.990485 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7022 22:53:46.993929 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7023 22:53:46.996777 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7024 22:53:47.000648 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7025 22:53:47.007214 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7026 22:53:47.010393 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7027 22:53:47.013933 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7028 22:53:47.017622 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7029 22:53:47.023756 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7030 22:53:47.026913 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7031 22:53:47.030767 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7032 22:53:47.037091 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7033 22:53:47.037193 ==
7034 22:53:47.040450 Dram Type= 6, Freq= 0, CH_1, rank 1
7035 22:53:47.043634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7036 22:53:47.043710 ==
7037 22:53:47.043780 DQS Delay:
7038 22:53:47.047350 DQS0 = 52, DQS1 = 56
7039 22:53:47.047425 DQM Delay:
7040 22:53:47.050274 DQM0 = 13, DQM1 = 9
7041 22:53:47.050350 DQ Delay:
7042 22:53:47.053561 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7043 22:53:47.056754 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7044 22:53:47.060713 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7045 22:53:47.063534 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7046 22:53:47.063610
7047 22:53:47.063671
7048 22:53:47.070210 [DQSOSCAuto] RK1, (LSB)MR18= 0x768c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
7049 22:53:47.073733 CH1 RK1: MR19=C0C, MR18=768C
7050 22:53:47.080494 CH1_RK1: MR19=0xC0C, MR18=0x768C, DQSOSC=392, MR23=63, INC=384, DEC=256
7051 22:53:47.083756 [RxdqsGatingPostProcess] freq 400
7052 22:53:47.087003 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7053 22:53:47.090536 best DQS0 dly(2T, 0.5T) = (0, 10)
7054 22:53:47.093737 best DQS1 dly(2T, 0.5T) = (0, 10)
7055 22:53:47.097556 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7056 22:53:47.100789 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7057 22:53:47.103666 best DQS0 dly(2T, 0.5T) = (0, 10)
7058 22:53:47.107629 best DQS1 dly(2T, 0.5T) = (0, 10)
7059 22:53:47.110503 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7060 22:53:47.113929 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7061 22:53:47.117215 Pre-setting of DQS Precalculation
7062 22:53:47.120272 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7063 22:53:47.130523 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7064 22:53:47.137210 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7065 22:53:47.137288
7066 22:53:47.137351
7067 22:53:47.140315 [Calibration Summary] 800 Mbps
7068 22:53:47.140391 CH 0, Rank 0
7069 22:53:47.143858 SW Impedance : PASS
7070 22:53:47.143936 DUTY Scan : NO K
7071 22:53:47.147426 ZQ Calibration : PASS
7072 22:53:47.150508 Jitter Meter : NO K
7073 22:53:47.150589 CBT Training : PASS
7074 22:53:47.153726 Write leveling : PASS
7075 22:53:47.157259 RX DQS gating : PASS
7076 22:53:47.157332 RX DQ/DQS(RDDQC) : PASS
7077 22:53:47.161188 TX DQ/DQS : PASS
7078 22:53:47.161276 RX DATLAT : PASS
7079 22:53:47.163655 RX DQ/DQS(Engine): PASS
7080 22:53:47.167138 TX OE : NO K
7081 22:53:47.167223 All Pass.
7082 22:53:47.167287
7083 22:53:47.167348 CH 0, Rank 1
7084 22:53:47.170668 SW Impedance : PASS
7085 22:53:47.173845 DUTY Scan : NO K
7086 22:53:47.173920 ZQ Calibration : PASS
7087 22:53:47.177219 Jitter Meter : NO K
7088 22:53:47.180428 CBT Training : PASS
7089 22:53:47.180503 Write leveling : NO K
7090 22:53:47.183761 RX DQS gating : PASS
7091 22:53:47.187257 RX DQ/DQS(RDDQC) : PASS
7092 22:53:47.187336 TX DQ/DQS : PASS
7093 22:53:47.190327 RX DATLAT : PASS
7094 22:53:47.193978 RX DQ/DQS(Engine): PASS
7095 22:53:47.194054 TX OE : NO K
7096 22:53:47.194125 All Pass.
7097 22:53:47.194185
7098 22:53:47.197501 CH 1, Rank 0
7099 22:53:47.200853 SW Impedance : PASS
7100 22:53:47.200929 DUTY Scan : NO K
7101 22:53:47.203988 ZQ Calibration : PASS
7102 22:53:47.204061 Jitter Meter : NO K
7103 22:53:47.207093 CBT Training : PASS
7104 22:53:47.210764 Write leveling : PASS
7105 22:53:47.210836 RX DQS gating : PASS
7106 22:53:47.213619 RX DQ/DQS(RDDQC) : PASS
7107 22:53:47.217286 TX DQ/DQS : PASS
7108 22:53:47.217361 RX DATLAT : PASS
7109 22:53:47.220357 RX DQ/DQS(Engine): PASS
7110 22:53:47.223851 TX OE : NO K
7111 22:53:47.223926 All Pass.
7112 22:53:47.223987
7113 22:53:47.224046 CH 1, Rank 1
7114 22:53:47.226877 SW Impedance : PASS
7115 22:53:47.230377 DUTY Scan : NO K
7116 22:53:47.230454 ZQ Calibration : PASS
7117 22:53:47.233934 Jitter Meter : NO K
7118 22:53:47.237138 CBT Training : PASS
7119 22:53:47.237277 Write leveling : NO K
7120 22:53:47.240358 RX DQS gating : PASS
7121 22:53:47.243808 RX DQ/DQS(RDDQC) : PASS
7122 22:53:47.243887 TX DQ/DQS : PASS
7123 22:53:47.246866 RX DATLAT : PASS
7124 22:53:47.246940 RX DQ/DQS(Engine): PASS
7125 22:53:47.250519 TX OE : NO K
7126 22:53:47.250599 All Pass.
7127 22:53:47.250661
7128 22:53:47.254249 DramC Write-DBI off
7129 22:53:47.257321 PER_BANK_REFRESH: Hybrid Mode
7130 22:53:47.257422 TX_TRACKING: ON
7131 22:53:47.267207 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7132 22:53:47.270799 [FAST_K] Save calibration result to emmc
7133 22:53:47.273857 dramc_set_vcore_voltage set vcore to 725000
7134 22:53:47.277126 Read voltage for 1600, 0
7135 22:53:47.277268 Vio18 = 0
7136 22:53:47.277334 Vcore = 725000
7137 22:53:47.280755 Vdram = 0
7138 22:53:47.280849 Vddq = 0
7139 22:53:47.280981 Vmddr = 0
7140 22:53:47.287389 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7141 22:53:47.290319 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7142 22:53:47.293766 MEM_TYPE=3, freq_sel=13
7143 22:53:47.296931 sv_algorithm_assistance_LP4_3733
7144 22:53:47.300689 ============ PULL DRAM RESETB DOWN ============
7145 22:53:47.303877 ========== PULL DRAM RESETB DOWN end =========
7146 22:53:47.310435 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7147 22:53:47.313873 ===================================
7148 22:53:47.317105 LPDDR4 DRAM CONFIGURATION
7149 22:53:47.320062 ===================================
7150 22:53:47.320138 EX_ROW_EN[0] = 0x0
7151 22:53:47.323609 EX_ROW_EN[1] = 0x0
7152 22:53:47.323696 LP4Y_EN = 0x0
7153 22:53:47.326729 WORK_FSP = 0x1
7154 22:53:47.326802 WL = 0x5
7155 22:53:47.330258 RL = 0x5
7156 22:53:47.330329 BL = 0x2
7157 22:53:47.333630 RPST = 0x0
7158 22:53:47.333701 RD_PRE = 0x0
7159 22:53:47.337595 WR_PRE = 0x1
7160 22:53:47.337676 WR_PST = 0x1
7161 22:53:47.340073 DBI_WR = 0x0
7162 22:53:47.340141 DBI_RD = 0x0
7163 22:53:47.343719 OTF = 0x1
7164 22:53:47.347110 ===================================
7165 22:53:47.350875 ===================================
7166 22:53:47.350948 ANA top config
7167 22:53:47.353791 ===================================
7168 22:53:47.356912 DLL_ASYNC_EN = 0
7169 22:53:47.360094 ALL_SLAVE_EN = 0
7170 22:53:47.363387 NEW_RANK_MODE = 1
7171 22:53:47.363466 DLL_IDLE_MODE = 1
7172 22:53:47.367223 LP45_APHY_COMB_EN = 1
7173 22:53:47.370364 TX_ODT_DIS = 0
7174 22:53:47.373587 NEW_8X_MODE = 1
7175 22:53:47.376789 ===================================
7176 22:53:47.380424 ===================================
7177 22:53:47.383828 data_rate = 3200
7178 22:53:47.386832 CKR = 1
7179 22:53:47.386903 DQ_P2S_RATIO = 8
7180 22:53:47.390461 ===================================
7181 22:53:47.393613 CA_P2S_RATIO = 8
7182 22:53:47.396874 DQ_CA_OPEN = 0
7183 22:53:47.400180 DQ_SEMI_OPEN = 0
7184 22:53:47.403560 CA_SEMI_OPEN = 0
7185 22:53:47.403632 CA_FULL_RATE = 0
7186 22:53:47.406581 DQ_CKDIV4_EN = 0
7187 22:53:47.410043 CA_CKDIV4_EN = 0
7188 22:53:47.413561 CA_PREDIV_EN = 0
7189 22:53:47.416888 PH8_DLY = 12
7190 22:53:47.420077 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7191 22:53:47.420145 DQ_AAMCK_DIV = 4
7192 22:53:47.424001 CA_AAMCK_DIV = 4
7193 22:53:47.426790 CA_ADMCK_DIV = 4
7194 22:53:47.430178 DQ_TRACK_CA_EN = 0
7195 22:53:47.433887 CA_PICK = 1600
7196 22:53:47.437406 CA_MCKIO = 1600
7197 22:53:47.440206 MCKIO_SEMI = 0
7198 22:53:47.440273 PLL_FREQ = 3068
7199 22:53:47.443369 DQ_UI_PI_RATIO = 32
7200 22:53:47.447153 CA_UI_PI_RATIO = 0
7201 22:53:47.450282 ===================================
7202 22:53:47.453785 ===================================
7203 22:53:47.457190 memory_type:LPDDR4
7204 22:53:47.457320 GP_NUM : 10
7205 22:53:47.460611 SRAM_EN : 1
7206 22:53:47.463650 MD32_EN : 0
7207 22:53:47.467173 ===================================
7208 22:53:47.467241 [ANA_INIT] >>>>>>>>>>>>>>
7209 22:53:47.470470 <<<<<< [CONFIGURE PHASE]: ANA_TX
7210 22:53:47.473647 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7211 22:53:47.477077 ===================================
7212 22:53:47.480572 data_rate = 3200,PCW = 0X7600
7213 22:53:47.483886 ===================================
7214 22:53:47.487203 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7215 22:53:47.493524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7216 22:53:47.496912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7217 22:53:47.503445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7218 22:53:47.506697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7219 22:53:47.510181 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7220 22:53:47.510255 [ANA_INIT] flow start
7221 22:53:47.513456 [ANA_INIT] PLL >>>>>>>>
7222 22:53:47.516551 [ANA_INIT] PLL <<<<<<<<
7223 22:53:47.520094 [ANA_INIT] MIDPI >>>>>>>>
7224 22:53:47.520165 [ANA_INIT] MIDPI <<<<<<<<
7225 22:53:47.523333 [ANA_INIT] DLL >>>>>>>>
7226 22:53:47.526772 [ANA_INIT] DLL <<<<<<<<
7227 22:53:47.526848 [ANA_INIT] flow end
7228 22:53:47.530319 ============ LP4 DIFF to SE enter ============
7229 22:53:47.537043 ============ LP4 DIFF to SE exit ============
7230 22:53:47.537119 [ANA_INIT] <<<<<<<<<<<<<
7231 22:53:47.540289 [Flow] Enable top DCM control >>>>>
7232 22:53:47.543387 [Flow] Enable top DCM control <<<<<
7233 22:53:47.546622 Enable DLL master slave shuffle
7234 22:53:47.553634 ==============================================================
7235 22:53:47.553708 Gating Mode config
7236 22:53:47.560329 ==============================================================
7237 22:53:47.563692 Config description:
7238 22:53:47.570362 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7239 22:53:47.576857 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7240 22:53:47.583443 SELPH_MODE 0: By rank 1: By Phase
7241 22:53:47.590076 ==============================================================
7242 22:53:47.593150 GAT_TRACK_EN = 1
7243 22:53:47.593251 RX_GATING_MODE = 2
7244 22:53:47.596752 RX_GATING_TRACK_MODE = 2
7245 22:53:47.600030 SELPH_MODE = 1
7246 22:53:47.603764 PICG_EARLY_EN = 1
7247 22:53:47.606533 VALID_LAT_VALUE = 1
7248 22:53:47.613572 ==============================================================
7249 22:53:47.616484 Enter into Gating configuration >>>>
7250 22:53:47.620230 Exit from Gating configuration <<<<
7251 22:53:47.623327 Enter into DVFS_PRE_config >>>>>
7252 22:53:47.633706 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7253 22:53:47.636787 Exit from DVFS_PRE_config <<<<<
7254 22:53:47.640307 Enter into PICG configuration >>>>
7255 22:53:47.643662 Exit from PICG configuration <<<<
7256 22:53:47.647017 [RX_INPUT] configuration >>>>>
7257 22:53:47.647103 [RX_INPUT] configuration <<<<<
7258 22:53:47.653578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7259 22:53:47.660527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7260 22:53:47.663486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7261 22:53:47.670579 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7262 22:53:47.677475 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7263 22:53:47.683385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7264 22:53:47.686988 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7265 22:53:47.690367 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7266 22:53:47.696966 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7267 22:53:47.700246 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7268 22:53:47.703487 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7269 22:53:47.707073 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7270 22:53:47.710849 ===================================
7271 22:53:47.714139 LPDDR4 DRAM CONFIGURATION
7272 22:53:47.716909 ===================================
7273 22:53:47.720346 EX_ROW_EN[0] = 0x0
7274 22:53:47.720415 EX_ROW_EN[1] = 0x0
7275 22:53:47.723699 LP4Y_EN = 0x0
7276 22:53:47.723773 WORK_FSP = 0x1
7277 22:53:47.727013 WL = 0x5
7278 22:53:47.727086 RL = 0x5
7279 22:53:47.730554 BL = 0x2
7280 22:53:47.730630 RPST = 0x0
7281 22:53:47.733929 RD_PRE = 0x0
7282 22:53:47.734003 WR_PRE = 0x1
7283 22:53:47.737211 WR_PST = 0x1
7284 22:53:47.737302 DBI_WR = 0x0
7285 22:53:47.740644 DBI_RD = 0x0
7286 22:53:47.740717 OTF = 0x1
7287 22:53:47.743697 ===================================
7288 22:53:47.750305 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7289 22:53:47.753781 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7290 22:53:47.757139 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7291 22:53:47.760404 ===================================
7292 22:53:47.763443 LPDDR4 DRAM CONFIGURATION
7293 22:53:47.766783 ===================================
7294 22:53:47.770304 EX_ROW_EN[0] = 0x10
7295 22:53:47.770378 EX_ROW_EN[1] = 0x0
7296 22:53:47.773967 LP4Y_EN = 0x0
7297 22:53:47.774039 WORK_FSP = 0x1
7298 22:53:47.777324 WL = 0x5
7299 22:53:47.777392 RL = 0x5
7300 22:53:47.780346 BL = 0x2
7301 22:53:47.780416 RPST = 0x0
7302 22:53:47.783555 RD_PRE = 0x0
7303 22:53:47.783627 WR_PRE = 0x1
7304 22:53:47.787316 WR_PST = 0x1
7305 22:53:47.787395 DBI_WR = 0x0
7306 22:53:47.790112 DBI_RD = 0x0
7307 22:53:47.790184 OTF = 0x1
7308 22:53:47.793685 ===================================
7309 22:53:47.800367 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7310 22:53:47.800446 ==
7311 22:53:47.804145 Dram Type= 6, Freq= 0, CH_0, rank 0
7312 22:53:47.807205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7313 22:53:47.810465 ==
7314 22:53:47.810543 [Duty_Offset_Calibration]
7315 22:53:47.814017 B0:2 B1:-1 CA:1
7316 22:53:47.814088
7317 22:53:47.817733 [DutyScan_Calibration_Flow] k_type=0
7318 22:53:47.825343
7319 22:53:47.825417 ==CLK 0==
7320 22:53:47.828619 Final CLK duty delay cell = -4
7321 22:53:47.831730 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7322 22:53:47.834971 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7323 22:53:47.838567 [-4] AVG Duty = 4937%(X100)
7324 22:53:47.838646
7325 22:53:47.842027 CH0 CLK Duty spec in!! Max-Min= 187%
7326 22:53:47.845357 [DutyScan_Calibration_Flow] ====Done====
7327 22:53:47.845434
7328 22:53:47.848558 [DutyScan_Calibration_Flow] k_type=1
7329 22:53:47.864909
7330 22:53:47.865013 ==DQS 0 ==
7331 22:53:47.868078 Final DQS duty delay cell = 0
7332 22:53:47.871213 [0] MAX Duty = 5125%(X100), DQS PI = 56
7333 22:53:47.874520 [0] MIN Duty = 5000%(X100), DQS PI = 14
7334 22:53:47.877948 [0] AVG Duty = 5062%(X100)
7335 22:53:47.878031
7336 22:53:47.878115 ==DQS 1 ==
7337 22:53:47.881739 Final DQS duty delay cell = -4
7338 22:53:47.884751 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7339 22:53:47.888283 [-4] MIN Duty = 5031%(X100), DQS PI = 6
7340 22:53:47.891342 [-4] AVG Duty = 5062%(X100)
7341 22:53:47.891426
7342 22:53:47.894798 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7343 22:53:47.894882
7344 22:53:47.898241 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7345 22:53:47.901131 [DutyScan_Calibration_Flow] ====Done====
7346 22:53:47.901272
7347 22:53:47.904472 [DutyScan_Calibration_Flow] k_type=3
7348 22:53:47.922128
7349 22:53:47.922214 ==DQM 0 ==
7350 22:53:47.925547 Final DQM duty delay cell = 0
7351 22:53:47.928692 [0] MAX Duty = 5000%(X100), DQS PI = 18
7352 22:53:47.932003 [0] MIN Duty = 4875%(X100), DQS PI = 6
7353 22:53:47.932087 [0] AVG Duty = 4937%(X100)
7354 22:53:47.935630
7355 22:53:47.935738 ==DQM 1 ==
7356 22:53:47.939079 Final DQM duty delay cell = 0
7357 22:53:47.942531 [0] MAX Duty = 5218%(X100), DQS PI = 58
7358 22:53:47.945317 [0] MIN Duty = 4969%(X100), DQS PI = 18
7359 22:53:47.945425 [0] AVG Duty = 5093%(X100)
7360 22:53:47.948943
7361 22:53:47.952232 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7362 22:53:47.952313
7363 22:53:47.955670 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7364 22:53:47.959295 [DutyScan_Calibration_Flow] ====Done====
7365 22:53:47.959375
7366 22:53:47.962009 [DutyScan_Calibration_Flow] k_type=2
7367 22:53:47.978325
7368 22:53:47.978405 ==DQ 0 ==
7369 22:53:47.982307 Final DQ duty delay cell = -4
7370 22:53:47.985044 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7371 22:53:47.988648 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7372 22:53:47.988729 [-4] AVG Duty = 4922%(X100)
7373 22:53:47.991615
7374 22:53:47.991695 ==DQ 1 ==
7375 22:53:47.995523 Final DQ duty delay cell = 0
7376 22:53:47.998275 [0] MAX Duty = 5031%(X100), DQS PI = 30
7377 22:53:48.001791 [0] MIN Duty = 4907%(X100), DQS PI = 18
7378 22:53:48.001872 [0] AVG Duty = 4969%(X100)
7379 22:53:48.005352
7380 22:53:48.008334 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7381 22:53:48.008414
7382 22:53:48.012168 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7383 22:53:48.015305 [DutyScan_Calibration_Flow] ====Done====
7384 22:53:48.015385 ==
7385 22:53:48.018670 Dram Type= 6, Freq= 0, CH_1, rank 0
7386 22:53:48.021518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7387 22:53:48.021594 ==
7388 22:53:48.025441 [Duty_Offset_Calibration]
7389 22:53:48.025522 B0:1 B1:1 CA:2
7390 22:53:48.025587
7391 22:53:48.028533 [DutyScan_Calibration_Flow] k_type=0
7392 22:53:48.038944
7393 22:53:48.039019 ==CLK 0==
7394 22:53:48.042026 Final CLK duty delay cell = 0
7395 22:53:48.045874 [0] MAX Duty = 5187%(X100), DQS PI = 24
7396 22:53:48.048826 [0] MIN Duty = 4938%(X100), DQS PI = 50
7397 22:53:48.048924 [0] AVG Duty = 5062%(X100)
7398 22:53:48.052789
7399 22:53:48.055547 CH1 CLK Duty spec in!! Max-Min= 249%
7400 22:53:48.058598 [DutyScan_Calibration_Flow] ====Done====
7401 22:53:48.058672
7402 22:53:48.062045 [DutyScan_Calibration_Flow] k_type=1
7403 22:53:48.078592
7404 22:53:48.078679 ==DQS 0 ==
7405 22:53:48.082408 Final DQS duty delay cell = 0
7406 22:53:48.085219 [0] MAX Duty = 5062%(X100), DQS PI = 22
7407 22:53:48.088955 [0] MIN Duty = 4813%(X100), DQS PI = 52
7408 22:53:48.091985 [0] AVG Duty = 4937%(X100)
7409 22:53:48.092061
7410 22:53:48.092130 ==DQS 1 ==
7411 22:53:48.095235 Final DQS duty delay cell = 0
7412 22:53:48.098737 [0] MAX Duty = 5031%(X100), DQS PI = 34
7413 22:53:48.101887 [0] MIN Duty = 4938%(X100), DQS PI = 14
7414 22:53:48.105350 [0] AVG Duty = 4984%(X100)
7415 22:53:48.105424
7416 22:53:48.109344 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7417 22:53:48.109421
7418 22:53:48.112069 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7419 22:53:48.115888 [DutyScan_Calibration_Flow] ====Done====
7420 22:53:48.115965
7421 22:53:48.118822 [DutyScan_Calibration_Flow] k_type=3
7422 22:53:48.135515
7423 22:53:48.135598 ==DQM 0 ==
7424 22:53:48.139393 Final DQM duty delay cell = 0
7425 22:53:48.142187 [0] MAX Duty = 5156%(X100), DQS PI = 20
7426 22:53:48.145434 [0] MIN Duty = 4844%(X100), DQS PI = 50
7427 22:53:48.145507 [0] AVG Duty = 5000%(X100)
7428 22:53:48.148766
7429 22:53:48.148849 ==DQM 1 ==
7430 22:53:48.152188 Final DQM duty delay cell = 0
7431 22:53:48.155930 [0] MAX Duty = 5125%(X100), DQS PI = 8
7432 22:53:48.159172 [0] MIN Duty = 4907%(X100), DQS PI = 20
7433 22:53:48.159246 [0] AVG Duty = 5016%(X100)
7434 22:53:48.162370
7435 22:53:48.165606 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7436 22:53:48.165684
7437 22:53:48.169019 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7438 22:53:48.172229 [DutyScan_Calibration_Flow] ====Done====
7439 22:53:48.172302
7440 22:53:48.175758 [DutyScan_Calibration_Flow] k_type=2
7441 22:53:48.192653
7442 22:53:48.192733 ==DQ 0 ==
7443 22:53:48.195555 Final DQ duty delay cell = 0
7444 22:53:48.199039 [0] MAX Duty = 5156%(X100), DQS PI = 20
7445 22:53:48.202105 [0] MIN Duty = 4907%(X100), DQS PI = 52
7446 22:53:48.202185 [0] AVG Duty = 5031%(X100)
7447 22:53:48.205439
7448 22:53:48.205511 ==DQ 1 ==
7449 22:53:48.208966 Final DQ duty delay cell = 0
7450 22:53:48.212410 [0] MAX Duty = 5093%(X100), DQS PI = 6
7451 22:53:48.215656 [0] MIN Duty = 5031%(X100), DQS PI = 0
7452 22:53:48.215729 [0] AVG Duty = 5062%(X100)
7453 22:53:48.215797
7454 22:53:48.219035 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7455 22:53:48.219106
7456 22:53:48.222456 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7457 22:53:48.229106 [DutyScan_Calibration_Flow] ====Done====
7458 22:53:48.232595 nWR fixed to 30
7459 22:53:48.232669 [ModeRegInit_LP4] CH0 RK0
7460 22:53:48.235981 [ModeRegInit_LP4] CH0 RK1
7461 22:53:48.238810 [ModeRegInit_LP4] CH1 RK0
7462 22:53:48.238894 [ModeRegInit_LP4] CH1 RK1
7463 22:53:48.242411 match AC timing 5
7464 22:53:48.245736 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7465 22:53:48.248728 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7466 22:53:48.255767 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7467 22:53:48.259177 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7468 22:53:48.265990 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7469 22:53:48.266072 [MiockJmeterHQA]
7470 22:53:48.266137
7471 22:53:48.269682 [DramcMiockJmeter] u1RxGatingPI = 0
7472 22:53:48.272174 0 : 4253, 4027
7473 22:53:48.272258 4 : 4363, 4137
7474 22:53:48.272324 8 : 4252, 4027
7475 22:53:48.275709 12 : 4252, 4027
7476 22:53:48.275793 16 : 4252, 4027
7477 22:53:48.278876 20 : 4252, 4027
7478 22:53:48.278960 24 : 4255, 4029
7479 22:53:48.282205 28 : 4253, 4026
7480 22:53:48.282288 32 : 4252, 4027
7481 22:53:48.282355 36 : 4365, 4140
7482 22:53:48.285389 40 : 4252, 4027
7483 22:53:48.285472 44 : 4255, 4029
7484 22:53:48.288906 48 : 4255, 4029
7485 22:53:48.288989 52 : 4363, 4138
7486 22:53:48.291870 56 : 4253, 4026
7487 22:53:48.291953 60 : 4363, 4137
7488 22:53:48.295555 64 : 4252, 4029
7489 22:53:48.295639 68 : 4250, 4027
7490 22:53:48.295705 72 : 4250, 4027
7491 22:53:48.299167 76 : 4252, 4029
7492 22:53:48.299250 80 : 4360, 4138
7493 22:53:48.302141 84 : 4252, 4027
7494 22:53:48.302225 88 : 4361, 4137
7495 22:53:48.305270 92 : 4250, 4027
7496 22:53:48.305396 96 : 4250, 3335
7497 22:53:48.305463 100 : 4250, 0
7498 22:53:48.308988 104 : 4252, 0
7499 22:53:48.309071 108 : 4253, 0
7500 22:53:48.312085 112 : 4252, 0
7501 22:53:48.312169 116 : 4253, 0
7502 22:53:48.312235 120 : 4250, 0
7503 22:53:48.315792 124 : 4360, 0
7504 22:53:48.315876 128 : 4361, 0
7505 22:53:48.315942 132 : 4250, 0
7506 22:53:48.319084 136 : 4250, 0
7507 22:53:48.319168 140 : 4250, 0
7508 22:53:48.322119 144 : 4252, 0
7509 22:53:48.322202 148 : 4250, 0
7510 22:53:48.322269 152 : 4250, 0
7511 22:53:48.326011 156 : 4252, 0
7512 22:53:48.326097 160 : 4361, 0
7513 22:53:48.329159 164 : 4250, 0
7514 22:53:48.329287 168 : 4250, 0
7515 22:53:48.329355 172 : 4250, 0
7516 22:53:48.332269 176 : 4361, 0
7517 22:53:48.332352 180 : 4360, 0
7518 22:53:48.335704 184 : 4250, 0
7519 22:53:48.335787 188 : 4250, 0
7520 22:53:48.335854 192 : 4250, 0
7521 22:53:48.339311 196 : 4252, 0
7522 22:53:48.339399 200 : 4250, 0
7523 22:53:48.339466 204 : 4250, 0
7524 22:53:48.342410 208 : 4253, 0
7525 22:53:48.342479 212 : 4361, 59
7526 22:53:48.345764 216 : 4250, 3435
7527 22:53:48.345838 220 : 4361, 4137
7528 22:53:48.348804 224 : 4360, 4138
7529 22:53:48.348875 228 : 4247, 4024
7530 22:53:48.352224 232 : 4363, 4140
7531 22:53:48.352291 236 : 4250, 4027
7532 22:53:48.355866 240 : 4250, 4027
7533 22:53:48.355937 244 : 4249, 4027
7534 22:53:48.355997 248 : 4252, 4029
7535 22:53:48.359112 252 : 4250, 4027
7536 22:53:48.359192 256 : 4250, 4027
7537 22:53:48.362165 260 : 4249, 4027
7538 22:53:48.362242 264 : 4250, 4027
7539 22:53:48.365293 268 : 4250, 4027
7540 22:53:48.365378 272 : 4361, 4137
7541 22:53:48.369294 276 : 4361, 4138
7542 22:53:48.369368 280 : 4250, 4027
7543 22:53:48.372465 284 : 4363, 4140
7544 22:53:48.372546 288 : 4250, 4027
7545 22:53:48.375432 292 : 4250, 4027
7546 22:53:48.375507 296 : 4250, 4027
7547 22:53:48.378665 300 : 4252, 4029
7548 22:53:48.378736 304 : 4250, 4026
7549 22:53:48.382061 308 : 4252, 4029
7550 22:53:48.382134 312 : 4250, 4027
7551 22:53:48.382206 316 : 4252, 4029
7552 22:53:48.385462 320 : 4250, 4027
7553 22:53:48.385539 324 : 4360, 4138
7554 22:53:48.388764 328 : 4361, 4138
7555 22:53:48.388841 332 : 4250, 3194
7556 22:53:48.392382 336 : 4363, 170
7557 22:53:48.392457
7558 22:53:48.392524 MIOCK jitter meter ch=0
7559 22:53:48.392583
7560 22:53:48.395753 1T = (336-100) = 236 dly cells
7561 22:53:48.402300 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7562 22:53:48.402377 ==
7563 22:53:48.405481 Dram Type= 6, Freq= 0, CH_0, rank 0
7564 22:53:48.408568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 22:53:48.408641 ==
7566 22:53:48.415495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 22:53:48.418852 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 22:53:48.425446 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 22:53:48.428630 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 22:53:48.438878 [CA 0] Center 44 (14~75) winsize 62
7571 22:53:48.442213 [CA 1] Center 44 (14~74) winsize 61
7572 22:53:48.445726 [CA 2] Center 39 (10~68) winsize 59
7573 22:53:48.448961 [CA 3] Center 39 (10~68) winsize 59
7574 22:53:48.452781 [CA 4] Center 37 (7~67) winsize 61
7575 22:53:48.455723 [CA 5] Center 37 (7~67) winsize 61
7576 22:53:48.455796
7577 22:53:48.459098 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7578 22:53:48.459177
7579 22:53:48.462099 [CATrainingPosCal] consider 1 rank data
7580 22:53:48.465808 u2DelayCellTimex100 = 275/100 ps
7581 22:53:48.468731 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7582 22:53:48.475273 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7583 22:53:48.478925 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7584 22:53:48.482001 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7585 22:53:48.485242 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7586 22:53:48.488923 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7587 22:53:48.488997
7588 22:53:48.492282 CA PerBit enable=1, Macro0, CA PI delay=37
7589 22:53:48.492362
7590 22:53:48.495792 [CBTSetCACLKResult] CA Dly = 37
7591 22:53:48.499402 CS Dly: 10 (0~41)
7592 22:53:48.501999 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 22:53:48.505395 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 22:53:48.505466 ==
7595 22:53:48.508991 Dram Type= 6, Freq= 0, CH_0, rank 1
7596 22:53:48.512060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 22:53:48.515459 ==
7598 22:53:48.518953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7599 22:53:48.522395 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7600 22:53:48.529249 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7601 22:53:48.532348 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7602 22:53:48.543065 [CA 0] Center 44 (14~75) winsize 62
7603 22:53:48.545780 [CA 1] Center 44 (14~75) winsize 62
7604 22:53:48.550321 [CA 2] Center 40 (11~69) winsize 59
7605 22:53:48.552365 [CA 3] Center 39 (10~69) winsize 60
7606 22:53:48.555900 [CA 4] Center 38 (8~68) winsize 61
7607 22:53:48.559318 [CA 5] Center 37 (7~67) winsize 61
7608 22:53:48.559402
7609 22:53:48.562521 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7610 22:53:48.562604
7611 22:53:48.566187 [CATrainingPosCal] consider 2 rank data
7612 22:53:48.569379 u2DelayCellTimex100 = 275/100 ps
7613 22:53:48.572849 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7614 22:53:48.579843 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7615 22:53:48.583023 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7616 22:53:48.586099 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7617 22:53:48.589558 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7618 22:53:48.592623 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7619 22:53:48.592706
7620 22:53:48.596037 CA PerBit enable=1, Macro0, CA PI delay=37
7621 22:53:48.596120
7622 22:53:48.599748 [CBTSetCACLKResult] CA Dly = 37
7623 22:53:48.602879 CS Dly: 11 (0~44)
7624 22:53:48.605819 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7625 22:53:48.609221 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7626 22:53:48.609304
7627 22:53:48.612756 ----->DramcWriteLeveling(PI) begin...
7628 22:53:48.612840 ==
7629 22:53:48.615803 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 22:53:48.619237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 22:53:48.623113 ==
7632 22:53:48.623196 Write leveling (Byte 0): 33 => 33
7633 22:53:48.625834 Write leveling (Byte 1): 28 => 28
7634 22:53:48.629075 DramcWriteLeveling(PI) end<-----
7635 22:53:48.629177
7636 22:53:48.629259 ==
7637 22:53:48.632802 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 22:53:48.639134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 22:53:48.639219 ==
7640 22:53:48.639283 [Gating] SW mode calibration
7641 22:53:48.649240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7642 22:53:48.652937 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7643 22:53:48.656259 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 22:53:48.662760 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 22:53:48.667265 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 22:53:48.669671 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 22:53:48.675904 1 4 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7648 22:53:48.679231 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7649 22:53:48.682686 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7650 22:53:48.689243 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7651 22:53:48.692843 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7652 22:53:48.696273 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7653 22:53:48.702784 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 22:53:48.706132 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7655 22:53:48.709442 1 5 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7656 22:53:48.716268 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7657 22:53:48.719693 1 5 24 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
7658 22:53:48.722940 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 22:53:48.730020 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 22:53:48.732853 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 22:53:48.736409 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 22:53:48.742612 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 22:53:48.746808 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7664 22:53:48.749417 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7665 22:53:48.753738 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7666 22:53:48.759513 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 22:53:48.762945 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 22:53:48.766352 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 22:53:48.772779 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 22:53:48.776461 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 22:53:48.779511 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7672 22:53:48.786292 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7673 22:53:48.789318 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7674 22:53:48.792836 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 22:53:48.799097 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 22:53:48.802673 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 22:53:48.806612 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 22:53:48.812472 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 22:53:48.816222 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 22:53:48.819157 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 22:53:48.826476 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 22:53:48.829373 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 22:53:48.832835 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 22:53:48.839478 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 22:53:48.842845 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 22:53:48.845793 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 22:53:48.849402 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7688 22:53:48.856389 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7689 22:53:48.859443 Total UI for P1: 0, mck2ui 16
7690 22:53:48.862794 best dqsien dly found for B0: ( 1, 9, 16)
7691 22:53:48.866176 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7692 22:53:48.869318 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7693 22:53:48.872777 Total UI for P1: 0, mck2ui 16
7694 22:53:48.876625 best dqsien dly found for B1: ( 1, 9, 20)
7695 22:53:48.879420 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7696 22:53:48.882693 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7697 22:53:48.882805
7698 22:53:48.889453 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7699 22:53:48.893469 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7700 22:53:48.896956 [Gating] SW calibration Done
7701 22:53:48.897063 ==
7702 22:53:48.899295 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 22:53:48.903153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 22:53:48.903247 ==
7705 22:53:48.903315 RX Vref Scan: 0
7706 22:53:48.903374
7707 22:53:48.906052 RX Vref 0 -> 0, step: 1
7708 22:53:48.906123
7709 22:53:48.909523 RX Delay 0 -> 252, step: 8
7710 22:53:48.913172 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7711 22:53:48.915986 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7712 22:53:48.919563 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7713 22:53:48.926020 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7714 22:53:48.929563 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7715 22:53:48.933123 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7716 22:53:48.935965 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7717 22:53:48.939644 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7718 22:53:48.946488 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7719 22:53:48.949419 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7720 22:53:48.952975 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7721 22:53:48.956364 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7722 22:53:48.959654 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7723 22:53:48.966485 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7724 22:53:48.969609 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7725 22:53:48.972778 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7726 22:53:48.972860 ==
7727 22:53:48.976059 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 22:53:48.979480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 22:53:48.979563 ==
7730 22:53:48.982923 DQS Delay:
7731 22:53:48.983005 DQS0 = 0, DQS1 = 0
7732 22:53:48.986124 DQM Delay:
7733 22:53:48.986206 DQM0 = 132, DQM1 = 124
7734 22:53:48.989544 DQ Delay:
7735 22:53:48.993398 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7736 22:53:48.996094 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7737 22:53:48.999592 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =115
7738 22:53:49.002687 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7739 22:53:49.002768
7740 22:53:49.002832
7741 22:53:49.002892 ==
7742 22:53:49.006073 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 22:53:49.009412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 22:53:49.009484 ==
7745 22:53:49.009562
7746 22:53:49.009623
7747 22:53:49.012561 TX Vref Scan disable
7748 22:53:49.016581 == TX Byte 0 ==
7749 22:53:49.019624 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7750 22:53:49.023372 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7751 22:53:49.026330 == TX Byte 1 ==
7752 22:53:49.029628 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7753 22:53:49.033114 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7754 22:53:49.033185 ==
7755 22:53:49.036109 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 22:53:49.043063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 22:53:49.043138 ==
7758 22:53:49.054478
7759 22:53:49.058084 TX Vref early break, caculate TX vref
7760 22:53:49.061524 TX Vref=16, minBit 1, minWin=21, winSum=357
7761 22:53:49.064511 TX Vref=18, minBit 0, minWin=22, winSum=373
7762 22:53:49.068245 TX Vref=20, minBit 4, minWin=22, winSum=378
7763 22:53:49.071513 TX Vref=22, minBit 1, minWin=23, winSum=389
7764 22:53:49.074572 TX Vref=24, minBit 4, minWin=23, winSum=403
7765 22:53:49.081054 TX Vref=26, minBit 0, minWin=25, winSum=416
7766 22:53:49.084764 TX Vref=28, minBit 4, minWin=24, winSum=420
7767 22:53:49.088152 TX Vref=30, minBit 4, minWin=24, winSum=415
7768 22:53:49.091437 TX Vref=32, minBit 4, minWin=24, winSum=410
7769 22:53:49.094517 TX Vref=34, minBit 4, minWin=23, winSum=398
7770 22:53:49.101062 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
7771 22:53:49.101169
7772 22:53:49.105073 Final TX Range 0 Vref 26
7773 22:53:49.105171
7774 22:53:49.105258 ==
7775 22:53:49.108018 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 22:53:49.111298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 22:53:49.111370 ==
7778 22:53:49.111436
7779 22:53:49.111494
7780 22:53:49.114586 TX Vref Scan disable
7781 22:53:49.121080 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7782 22:53:49.121158 == TX Byte 0 ==
7783 22:53:49.125153 u2DelayCellOfst[0]=17 cells (5 PI)
7784 22:53:49.128337 u2DelayCellOfst[1]=21 cells (6 PI)
7785 22:53:49.131450 u2DelayCellOfst[2]=14 cells (4 PI)
7786 22:53:49.134736 u2DelayCellOfst[3]=17 cells (5 PI)
7787 22:53:49.138450 u2DelayCellOfst[4]=10 cells (3 PI)
7788 22:53:49.141142 u2DelayCellOfst[5]=0 cells (0 PI)
7789 22:53:49.141276 u2DelayCellOfst[6]=21 cells (6 PI)
7790 22:53:49.144413 u2DelayCellOfst[7]=21 cells (6 PI)
7791 22:53:49.151380 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7792 22:53:49.154888 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7793 22:53:49.154961 == TX Byte 1 ==
7794 22:53:49.157939 u2DelayCellOfst[8]=0 cells (0 PI)
7795 22:53:49.161144 u2DelayCellOfst[9]=0 cells (0 PI)
7796 22:53:49.164685 u2DelayCellOfst[10]=10 cells (3 PI)
7797 22:53:49.168274 u2DelayCellOfst[11]=0 cells (0 PI)
7798 22:53:49.170980 u2DelayCellOfst[12]=14 cells (4 PI)
7799 22:53:49.174504 u2DelayCellOfst[13]=10 cells (3 PI)
7800 22:53:49.177561 u2DelayCellOfst[14]=17 cells (5 PI)
7801 22:53:49.181044 u2DelayCellOfst[15]=10 cells (3 PI)
7802 22:53:49.184175 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7803 22:53:49.187723 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7804 22:53:49.191727 DramC Write-DBI on
7805 22:53:49.191802 ==
7806 22:53:49.194140 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 22:53:49.197925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 22:53:49.197999 ==
7809 22:53:49.198061
7810 22:53:49.201389
7811 22:53:49.201460 TX Vref Scan disable
7812 22:53:49.204682 == TX Byte 0 ==
7813 22:53:49.207527 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7814 22:53:49.211202 == TX Byte 1 ==
7815 22:53:49.214562 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7816 22:53:49.214635 DramC Write-DBI off
7817 22:53:49.214696
7818 22:53:49.217418 [DATLAT]
7819 22:53:49.217487 Freq=1600, CH0 RK0
7820 22:53:49.217553
7821 22:53:49.220889 DATLAT Default: 0xf
7822 22:53:49.220959 0, 0xFFFF, sum = 0
7823 22:53:49.224885 1, 0xFFFF, sum = 0
7824 22:53:49.224958 2, 0xFFFF, sum = 0
7825 22:53:49.227750 3, 0xFFFF, sum = 0
7826 22:53:49.227822 4, 0xFFFF, sum = 0
7827 22:53:49.231341 5, 0xFFFF, sum = 0
7828 22:53:49.231412 6, 0xFFFF, sum = 0
7829 22:53:49.234079 7, 0xFFFF, sum = 0
7830 22:53:49.237519 8, 0xFFFF, sum = 0
7831 22:53:49.237629 9, 0xFFFF, sum = 0
7832 22:53:49.240852 10, 0xFFFF, sum = 0
7833 22:53:49.240925 11, 0xFFFF, sum = 0
7834 22:53:49.243983 12, 0xFFFF, sum = 0
7835 22:53:49.244056 13, 0xFFFF, sum = 0
7836 22:53:49.247436 14, 0x0, sum = 1
7837 22:53:49.247515 15, 0x0, sum = 2
7838 22:53:49.250651 16, 0x0, sum = 3
7839 22:53:49.250730 17, 0x0, sum = 4
7840 22:53:49.254235 best_step = 15
7841 22:53:49.254311
7842 22:53:49.254372 ==
7843 22:53:49.257623 Dram Type= 6, Freq= 0, CH_0, rank 0
7844 22:53:49.260885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7845 22:53:49.260958 ==
7846 22:53:49.261018 RX Vref Scan: 1
7847 22:53:49.261083
7848 22:53:49.264248 Set Vref Range= 24 -> 127
7849 22:53:49.264324
7850 22:53:49.267515 RX Vref 24 -> 127, step: 1
7851 22:53:49.267590
7852 22:53:49.270860 RX Delay 11 -> 252, step: 4
7853 22:53:49.270932
7854 22:53:49.274235 Set Vref, RX VrefLevel [Byte0]: 24
7855 22:53:49.277852 [Byte1]: 24
7856 22:53:49.277931
7857 22:53:49.280864 Set Vref, RX VrefLevel [Byte0]: 25
7858 22:53:49.284301 [Byte1]: 25
7859 22:53:49.284374
7860 22:53:49.287303 Set Vref, RX VrefLevel [Byte0]: 26
7861 22:53:49.290907 [Byte1]: 26
7862 22:53:49.294363
7863 22:53:49.294438 Set Vref, RX VrefLevel [Byte0]: 27
7864 22:53:49.297625 [Byte1]: 27
7865 22:53:49.302506
7866 22:53:49.302579 Set Vref, RX VrefLevel [Byte0]: 28
7867 22:53:49.305166 [Byte1]: 28
7868 22:53:49.310195
7869 22:53:49.310274 Set Vref, RX VrefLevel [Byte0]: 29
7870 22:53:49.313121 [Byte1]: 29
7871 22:53:49.317632
7872 22:53:49.317704 Set Vref, RX VrefLevel [Byte0]: 30
7873 22:53:49.321370 [Byte1]: 30
7874 22:53:49.324726
7875 22:53:49.324798 Set Vref, RX VrefLevel [Byte0]: 31
7876 22:53:49.328302 [Byte1]: 31
7877 22:53:49.333322
7878 22:53:49.333395 Set Vref, RX VrefLevel [Byte0]: 32
7879 22:53:49.336119 [Byte1]: 32
7880 22:53:49.340304
7881 22:53:49.340378 Set Vref, RX VrefLevel [Byte0]: 33
7882 22:53:49.343550 [Byte1]: 33
7883 22:53:49.347743
7884 22:53:49.347819 Set Vref, RX VrefLevel [Byte0]: 34
7885 22:53:49.351504 [Byte1]: 34
7886 22:53:49.355576
7887 22:53:49.355650 Set Vref, RX VrefLevel [Byte0]: 35
7888 22:53:49.359185 [Byte1]: 35
7889 22:53:49.362806
7890 22:53:49.362877 Set Vref, RX VrefLevel [Byte0]: 36
7891 22:53:49.366237 [Byte1]: 36
7892 22:53:49.370713
7893 22:53:49.370789 Set Vref, RX VrefLevel [Byte0]: 37
7894 22:53:49.373858 [Byte1]: 37
7895 22:53:49.378376
7896 22:53:49.378452 Set Vref, RX VrefLevel [Byte0]: 38
7897 22:53:49.381568 [Byte1]: 38
7898 22:53:49.385910
7899 22:53:49.385982 Set Vref, RX VrefLevel [Byte0]: 39
7900 22:53:49.389548 [Byte1]: 39
7901 22:53:49.393303
7902 22:53:49.393379 Set Vref, RX VrefLevel [Byte0]: 40
7903 22:53:49.396939 [Byte1]: 40
7904 22:53:49.401896
7905 22:53:49.401969 Set Vref, RX VrefLevel [Byte0]: 41
7906 22:53:49.404264 [Byte1]: 41
7907 22:53:49.408713
7908 22:53:49.408785 Set Vref, RX VrefLevel [Byte0]: 42
7909 22:53:49.411794 [Byte1]: 42
7910 22:53:49.416162
7911 22:53:49.416235 Set Vref, RX VrefLevel [Byte0]: 43
7912 22:53:49.420006 [Byte1]: 43
7913 22:53:49.423730
7914 22:53:49.423802 Set Vref, RX VrefLevel [Byte0]: 44
7915 22:53:49.427201 [Byte1]: 44
7916 22:53:49.431711
7917 22:53:49.431793 Set Vref, RX VrefLevel [Byte0]: 45
7918 22:53:49.438107 [Byte1]: 45
7919 22:53:49.438211
7920 22:53:49.441164 Set Vref, RX VrefLevel [Byte0]: 46
7921 22:53:49.444800 [Byte1]: 46
7922 22:53:49.444872
7923 22:53:49.448538 Set Vref, RX VrefLevel [Byte0]: 47
7924 22:53:49.451393 [Byte1]: 47
7925 22:53:49.451470
7926 22:53:49.454754 Set Vref, RX VrefLevel [Byte0]: 48
7927 22:53:49.457975 [Byte1]: 48
7928 22:53:49.461903
7929 22:53:49.461977 Set Vref, RX VrefLevel [Byte0]: 49
7930 22:53:49.465223 [Byte1]: 49
7931 22:53:49.469695
7932 22:53:49.469768 Set Vref, RX VrefLevel [Byte0]: 50
7933 22:53:49.473084 [Byte1]: 50
7934 22:53:49.477116
7935 22:53:49.477247 Set Vref, RX VrefLevel [Byte0]: 51
7936 22:53:49.480545 [Byte1]: 51
7937 22:53:49.484610
7938 22:53:49.484690 Set Vref, RX VrefLevel [Byte0]: 52
7939 22:53:49.487911 [Byte1]: 52
7940 22:53:49.492167
7941 22:53:49.492243 Set Vref, RX VrefLevel [Byte0]: 53
7942 22:53:49.495759 [Byte1]: 53
7943 22:53:49.500161
7944 22:53:49.500234 Set Vref, RX VrefLevel [Byte0]: 54
7945 22:53:49.503042 [Byte1]: 54
7946 22:53:49.507602
7947 22:53:49.507673 Set Vref, RX VrefLevel [Byte0]: 55
7948 22:53:49.510678 [Byte1]: 55
7949 22:53:49.514968
7950 22:53:49.515044 Set Vref, RX VrefLevel [Byte0]: 56
7951 22:53:49.518472 [Byte1]: 56
7952 22:53:49.522660
7953 22:53:49.522732 Set Vref, RX VrefLevel [Byte0]: 57
7954 22:53:49.525952 [Byte1]: 57
7955 22:53:49.530515
7956 22:53:49.530586 Set Vref, RX VrefLevel [Byte0]: 58
7957 22:53:49.533801 [Byte1]: 58
7958 22:53:49.538526
7959 22:53:49.538598 Set Vref, RX VrefLevel [Byte0]: 59
7960 22:53:49.541374 [Byte1]: 59
7961 22:53:49.545586
7962 22:53:49.545663 Set Vref, RX VrefLevel [Byte0]: 60
7963 22:53:49.549138 [Byte1]: 60
7964 22:53:49.553466
7965 22:53:49.553538 Set Vref, RX VrefLevel [Byte0]: 61
7966 22:53:49.556665 [Byte1]: 61
7967 22:53:49.561363
7968 22:53:49.561436 Set Vref, RX VrefLevel [Byte0]: 62
7969 22:53:49.564469 [Byte1]: 62
7970 22:53:49.568337
7971 22:53:49.568416 Set Vref, RX VrefLevel [Byte0]: 63
7972 22:53:49.571918 [Byte1]: 63
7973 22:53:49.576395
7974 22:53:49.576470 Set Vref, RX VrefLevel [Byte0]: 64
7975 22:53:49.579479 [Byte1]: 64
7976 22:53:49.583911
7977 22:53:49.583984 Set Vref, RX VrefLevel [Byte0]: 65
7978 22:53:49.587405 [Byte1]: 65
7979 22:53:49.591568
7980 22:53:49.591666 Set Vref, RX VrefLevel [Byte0]: 66
7981 22:53:49.594787 [Byte1]: 66
7982 22:53:49.599803
7983 22:53:49.599887 Set Vref, RX VrefLevel [Byte0]: 67
7984 22:53:49.602318 [Byte1]: 67
7985 22:53:49.606326
7986 22:53:49.606401 Set Vref, RX VrefLevel [Byte0]: 68
7987 22:53:49.610229 [Byte1]: 68
7988 22:53:49.614321
7989 22:53:49.614397 Set Vref, RX VrefLevel [Byte0]: 69
7990 22:53:49.617628 [Byte1]: 69
7991 22:53:49.622611
7992 22:53:49.622684 Set Vref, RX VrefLevel [Byte0]: 70
7993 22:53:49.625301 [Byte1]: 70
7994 22:53:49.629553
7995 22:53:49.629621 Set Vref, RX VrefLevel [Byte0]: 71
7996 22:53:49.632919 [Byte1]: 71
7997 22:53:49.636783
7998 22:53:49.636851 Set Vref, RX VrefLevel [Byte0]: 72
7999 22:53:49.640491 [Byte1]: 72
8000 22:53:49.645002
8001 22:53:49.645070 Set Vref, RX VrefLevel [Byte0]: 73
8002 22:53:49.647672 [Byte1]: 73
8003 22:53:49.652319
8004 22:53:49.652392 Set Vref, RX VrefLevel [Byte0]: 74
8005 22:53:49.655504 [Byte1]: 74
8006 22:53:49.659785
8007 22:53:49.659854 Set Vref, RX VrefLevel [Byte0]: 75
8008 22:53:49.663434 [Byte1]: 75
8009 22:53:49.667369
8010 22:53:49.667445 Final RX Vref Byte 0 = 61 to rank0
8011 22:53:49.670890 Final RX Vref Byte 1 = 60 to rank0
8012 22:53:49.674150 Final RX Vref Byte 0 = 61 to rank1
8013 22:53:49.677436 Final RX Vref Byte 1 = 60 to rank1==
8014 22:53:49.680618 Dram Type= 6, Freq= 0, CH_0, rank 0
8015 22:53:49.687439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 22:53:49.687513 ==
8017 22:53:49.687574 DQS Delay:
8018 22:53:49.687639 DQS0 = 0, DQS1 = 0
8019 22:53:49.690992 DQM Delay:
8020 22:53:49.691060 DQM0 = 129, DQM1 = 122
8021 22:53:49.694285 DQ Delay:
8022 22:53:49.697400 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =124
8023 22:53:49.700569 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8024 22:53:49.703940 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
8025 22:53:49.707350 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
8026 22:53:49.707419
8027 22:53:49.707478
8028 22:53:49.707534
8029 22:53:49.710791 [DramC_TX_OE_Calibration] TA2
8030 22:53:49.714141 Original DQ_B0 (3 6) =30, OEN = 27
8031 22:53:49.717409 Original DQ_B1 (3 6) =30, OEN = 27
8032 22:53:49.720848 24, 0x0, End_B0=24 End_B1=24
8033 22:53:49.720928 25, 0x0, End_B0=25 End_B1=25
8034 22:53:49.724238 26, 0x0, End_B0=26 End_B1=26
8035 22:53:49.727755 27, 0x0, End_B0=27 End_B1=27
8036 22:53:49.730935 28, 0x0, End_B0=28 End_B1=28
8037 22:53:49.731006 29, 0x0, End_B0=29 End_B1=29
8038 22:53:49.734378 30, 0x0, End_B0=30 End_B1=30
8039 22:53:49.737991 31, 0x4141, End_B0=30 End_B1=30
8040 22:53:49.740594 Byte0 end_step=30 best_step=27
8041 22:53:49.744627 Byte1 end_step=30 best_step=27
8042 22:53:49.747665 Byte0 TX OE(2T, 0.5T) = (3, 3)
8043 22:53:49.747733 Byte1 TX OE(2T, 0.5T) = (3, 3)
8044 22:53:49.747798
8045 22:53:49.747856
8046 22:53:49.757326 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8047 22:53:49.760892 CH0 RK0: MR19=303, MR18=1408
8048 22:53:49.767479 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
8049 22:53:49.767561
8050 22:53:49.770961 ----->DramcWriteLeveling(PI) begin...
8051 22:53:49.771043 ==
8052 22:53:49.773859 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 22:53:49.777324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 22:53:49.777406 ==
8055 22:53:49.781096 Write leveling (Byte 0): 35 => 35
8056 22:53:49.784614 Write leveling (Byte 1): 26 => 26
8057 22:53:49.787624 DramcWriteLeveling(PI) end<-----
8058 22:53:49.787698
8059 22:53:49.787759 ==
8060 22:53:49.791291 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 22:53:49.794299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 22:53:49.794373 ==
8063 22:53:49.797523 [Gating] SW mode calibration
8064 22:53:49.804379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8065 22:53:49.811143 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8066 22:53:49.814018 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 22:53:49.817221 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 22:53:49.824137 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8069 22:53:49.827554 1 4 12 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
8070 22:53:49.831089 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8071 22:53:49.837682 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8072 22:53:49.840934 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 22:53:49.844458 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 22:53:49.847281 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 22:53:49.854261 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 22:53:49.857427 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
8077 22:53:49.860518 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 1)
8078 22:53:49.867389 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8079 22:53:49.870814 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8080 22:53:49.874056 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8081 22:53:49.880654 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 22:53:49.884178 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 22:53:49.887983 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 22:53:49.893965 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8085 22:53:49.897853 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8086 22:53:49.901608 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8087 22:53:49.907785 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8088 22:53:49.911596 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 22:53:49.914500 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 22:53:49.920894 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 22:53:49.924413 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8092 22:53:49.927532 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8093 22:53:49.934542 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8094 22:53:49.937564 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8095 22:53:49.940863 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8096 22:53:49.947411 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 22:53:49.950828 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 22:53:49.953856 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 22:53:49.958380 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 22:53:49.964141 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 22:53:49.967342 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 22:53:49.970732 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 22:53:49.977505 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 22:53:49.980431 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 22:53:49.983962 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 22:53:49.990998 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 22:53:49.993984 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 22:53:49.997315 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8109 22:53:50.003956 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8110 22:53:50.007557 Total UI for P1: 0, mck2ui 16
8111 22:53:50.010682 best dqsien dly found for B0: ( 1, 9, 8)
8112 22:53:50.013929 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8113 22:53:50.017244 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8114 22:53:50.023619 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 22:53:50.023694 Total UI for P1: 0, mck2ui 16
8116 22:53:50.030325 best dqsien dly found for B1: ( 1, 9, 18)
8117 22:53:50.033760 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8118 22:53:50.037304 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8119 22:53:50.037374
8120 22:53:50.040190 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8121 22:53:50.043910 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8122 22:53:50.047288 [Gating] SW calibration Done
8123 22:53:50.047357 ==
8124 22:53:50.050496 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 22:53:50.053609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 22:53:50.053681 ==
8127 22:53:50.057202 RX Vref Scan: 0
8128 22:53:50.057312
8129 22:53:50.057371 RX Vref 0 -> 0, step: 1
8130 22:53:50.057428
8131 22:53:50.060329 RX Delay 0 -> 252, step: 8
8132 22:53:50.063555 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8133 22:53:50.069996 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8134 22:53:50.073766 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8135 22:53:50.077389 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8136 22:53:50.080517 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8137 22:53:50.083710 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8138 22:53:50.090370 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8139 22:53:50.093716 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8140 22:53:50.097286 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8141 22:53:50.100558 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8142 22:53:50.103853 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8143 22:53:50.110653 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8144 22:53:50.114126 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8145 22:53:50.117718 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8146 22:53:50.120252 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8147 22:53:50.123910 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8148 22:53:50.123982 ==
8149 22:53:50.127110 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 22:53:50.133707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 22:53:50.133801 ==
8152 22:53:50.133864 DQS Delay:
8153 22:53:50.137403 DQS0 = 0, DQS1 = 0
8154 22:53:50.137476 DQM Delay:
8155 22:53:50.140478 DQM0 = 132, DQM1 = 125
8156 22:53:50.140558 DQ Delay:
8157 22:53:50.143548 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8158 22:53:50.146798 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8159 22:53:50.150440 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8160 22:53:50.153507 DQ12 =127, DQ13 =135, DQ14 =135, DQ15 =131
8161 22:53:50.153586
8162 22:53:50.153648
8163 22:53:50.153707 ==
8164 22:53:50.156694 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 22:53:50.163698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 22:53:50.163781 ==
8167 22:53:50.163844
8168 22:53:50.163910
8169 22:53:50.163967 TX Vref Scan disable
8170 22:53:50.167072 == TX Byte 0 ==
8171 22:53:50.170412 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8172 22:53:50.173603 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8173 22:53:50.176978 == TX Byte 1 ==
8174 22:53:50.180373 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8175 22:53:50.183706 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8176 22:53:50.186887 ==
8177 22:53:50.190354 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 22:53:50.193372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 22:53:50.193459 ==
8180 22:53:50.209472
8181 22:53:50.212693 TX Vref early break, caculate TX vref
8182 22:53:50.215839 TX Vref=16, minBit 5, minWin=22, winSum=371
8183 22:53:50.219083 TX Vref=18, minBit 9, minWin=22, winSum=384
8184 22:53:50.222679 TX Vref=20, minBit 1, minWin=23, winSum=386
8185 22:53:50.225819 TX Vref=22, minBit 9, minWin=23, winSum=397
8186 22:53:50.229314 TX Vref=24, minBit 4, minWin=24, winSum=405
8187 22:53:50.235736 TX Vref=26, minBit 1, minWin=25, winSum=414
8188 22:53:50.239272 TX Vref=28, minBit 0, minWin=25, winSum=415
8189 22:53:50.242899 TX Vref=30, minBit 4, minWin=25, winSum=419
8190 22:53:50.245988 TX Vref=32, minBit 1, minWin=25, winSum=411
8191 22:53:50.249667 TX Vref=34, minBit 7, minWin=24, winSum=402
8192 22:53:50.252369 TX Vref=36, minBit 4, minWin=23, winSum=398
8193 22:53:50.259800 TX Vref=38, minBit 13, minWin=22, winSum=381
8194 22:53:50.262886 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 30
8195 22:53:50.262967
8196 22:53:50.265950 Final TX Range 0 Vref 30
8197 22:53:50.266023
8198 22:53:50.266083 ==
8199 22:53:50.269197 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 22:53:50.272660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 22:53:50.272732 ==
8202 22:53:50.275744
8203 22:53:50.275822
8204 22:53:50.275885 TX Vref Scan disable
8205 22:53:50.282568 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8206 22:53:50.282643 == TX Byte 0 ==
8207 22:53:50.286086 u2DelayCellOfst[0]=14 cells (4 PI)
8208 22:53:50.289731 u2DelayCellOfst[1]=17 cells (5 PI)
8209 22:53:50.292731 u2DelayCellOfst[2]=10 cells (3 PI)
8210 22:53:50.296037 u2DelayCellOfst[3]=10 cells (3 PI)
8211 22:53:50.299592 u2DelayCellOfst[4]=10 cells (3 PI)
8212 22:53:50.302714 u2DelayCellOfst[5]=0 cells (0 PI)
8213 22:53:50.306560 u2DelayCellOfst[6]=17 cells (5 PI)
8214 22:53:50.309163 u2DelayCellOfst[7]=17 cells (5 PI)
8215 22:53:50.312884 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8216 22:53:50.315804 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8217 22:53:50.319421 == TX Byte 1 ==
8218 22:53:50.322650 u2DelayCellOfst[8]=0 cells (0 PI)
8219 22:53:50.326040 u2DelayCellOfst[9]=0 cells (0 PI)
8220 22:53:50.329415 u2DelayCellOfst[10]=3 cells (1 PI)
8221 22:53:50.329498 u2DelayCellOfst[11]=0 cells (0 PI)
8222 22:53:50.332505 u2DelayCellOfst[12]=10 cells (3 PI)
8223 22:53:50.336110 u2DelayCellOfst[13]=10 cells (3 PI)
8224 22:53:50.339485 u2DelayCellOfst[14]=14 cells (4 PI)
8225 22:53:50.343416 u2DelayCellOfst[15]=10 cells (3 PI)
8226 22:53:50.347251 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8227 22:53:50.352611 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8228 22:53:50.352693 DramC Write-DBI on
8229 22:53:50.352758 ==
8230 22:53:50.355887 Dram Type= 6, Freq= 0, CH_0, rank 1
8231 22:53:50.362661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 22:53:50.362744 ==
8233 22:53:50.362810
8234 22:53:50.362870
8235 22:53:50.362928 TX Vref Scan disable
8236 22:53:50.366619 == TX Byte 0 ==
8237 22:53:50.370213 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8238 22:53:50.373455 == TX Byte 1 ==
8239 22:53:50.376360 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8240 22:53:50.380548 DramC Write-DBI off
8241 22:53:50.380631
8242 22:53:50.380695 [DATLAT]
8243 22:53:50.380755 Freq=1600, CH0 RK1
8244 22:53:50.380814
8245 22:53:50.383078 DATLAT Default: 0xf
8246 22:53:50.383175 0, 0xFFFF, sum = 0
8247 22:53:50.386859 1, 0xFFFF, sum = 0
8248 22:53:50.386943 2, 0xFFFF, sum = 0
8249 22:53:50.390289 3, 0xFFFF, sum = 0
8250 22:53:50.393179 4, 0xFFFF, sum = 0
8251 22:53:50.393303 5, 0xFFFF, sum = 0
8252 22:53:50.396606 6, 0xFFFF, sum = 0
8253 22:53:50.396690 7, 0xFFFF, sum = 0
8254 22:53:50.399839 8, 0xFFFF, sum = 0
8255 22:53:50.399922 9, 0xFFFF, sum = 0
8256 22:53:50.403198 10, 0xFFFF, sum = 0
8257 22:53:50.403281 11, 0xFFFF, sum = 0
8258 22:53:50.407316 12, 0xFFFF, sum = 0
8259 22:53:50.407399 13, 0xFFFF, sum = 0
8260 22:53:50.410404 14, 0x0, sum = 1
8261 22:53:50.410491 15, 0x0, sum = 2
8262 22:53:50.413456 16, 0x0, sum = 3
8263 22:53:50.413538 17, 0x0, sum = 4
8264 22:53:50.416796 best_step = 15
8265 22:53:50.416898
8266 22:53:50.416963 ==
8267 22:53:50.420372 Dram Type= 6, Freq= 0, CH_0, rank 1
8268 22:53:50.423679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 22:53:50.423762 ==
8270 22:53:50.423827 RX Vref Scan: 0
8271 22:53:50.423887
8272 22:53:50.427230 RX Vref 0 -> 0, step: 1
8273 22:53:50.427312
8274 22:53:50.430142 RX Delay 11 -> 252, step: 4
8275 22:53:50.433587 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8276 22:53:50.440230 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8277 22:53:50.443910 iDelay=195, Bit 2, Center 124 (67 ~ 182) 116
8278 22:53:50.446662 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8279 22:53:50.450222 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8280 22:53:50.453659 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8281 22:53:50.457044 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
8282 22:53:50.463604 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8283 22:53:50.467134 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8284 22:53:50.470619 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8285 22:53:50.473997 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8286 22:53:50.477246 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8287 22:53:50.483978 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8288 22:53:50.487680 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8289 22:53:50.490453 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8290 22:53:50.493829 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8291 22:53:50.493912 ==
8292 22:53:50.496514 Dram Type= 6, Freq= 0, CH_0, rank 1
8293 22:53:50.503580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 22:53:50.503662 ==
8295 22:53:50.503727 DQS Delay:
8296 22:53:50.506682 DQS0 = 0, DQS1 = 0
8297 22:53:50.506765 DQM Delay:
8298 22:53:50.506830 DQM0 = 127, DQM1 = 122
8299 22:53:50.510062 DQ Delay:
8300 22:53:50.513178 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8301 22:53:50.516732 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =134
8302 22:53:50.520148 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8303 22:53:50.523480 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8304 22:53:50.523562
8305 22:53:50.523626
8306 22:53:50.523686
8307 22:53:50.526770 [DramC_TX_OE_Calibration] TA2
8308 22:53:50.529596 Original DQ_B0 (3 6) =30, OEN = 27
8309 22:53:50.533371 Original DQ_B1 (3 6) =30, OEN = 27
8310 22:53:50.536489 24, 0x0, End_B0=24 End_B1=24
8311 22:53:50.536573 25, 0x0, End_B0=25 End_B1=25
8312 22:53:50.539858 26, 0x0, End_B0=26 End_B1=26
8313 22:53:50.543249 27, 0x0, End_B0=27 End_B1=27
8314 22:53:50.546430 28, 0x0, End_B0=28 End_B1=28
8315 22:53:50.550188 29, 0x0, End_B0=29 End_B1=29
8316 22:53:50.550271 30, 0x0, End_B0=30 End_B1=30
8317 22:53:50.553426 31, 0x4141, End_B0=30 End_B1=30
8318 22:53:50.556536 Byte0 end_step=30 best_step=27
8319 22:53:50.560240 Byte1 end_step=30 best_step=27
8320 22:53:50.563026 Byte0 TX OE(2T, 0.5T) = (3, 3)
8321 22:53:50.566391 Byte1 TX OE(2T, 0.5T) = (3, 3)
8322 22:53:50.566473
8323 22:53:50.566538
8324 22:53:50.573038 [DQSOSCAuto] RK1, (LSB)MR18= 0x1409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8325 22:53:50.576509 CH0 RK1: MR19=303, MR18=1409
8326 22:53:50.583351 CH0_RK1: MR19=0x303, MR18=0x1409, DQSOSC=399, MR23=63, INC=23, DEC=15
8327 22:53:50.586944 [RxdqsGatingPostProcess] freq 1600
8328 22:53:50.589777 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8329 22:53:50.593354 best DQS0 dly(2T, 0.5T) = (1, 1)
8330 22:53:50.596448 best DQS1 dly(2T, 0.5T) = (1, 1)
8331 22:53:50.599759 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8332 22:53:50.603159 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8333 22:53:50.606249 best DQS0 dly(2T, 0.5T) = (1, 1)
8334 22:53:50.610102 best DQS1 dly(2T, 0.5T) = (1, 1)
8335 22:53:50.612957 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8336 22:53:50.616576 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8337 22:53:50.619810 Pre-setting of DQS Precalculation
8338 22:53:50.623205 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8339 22:53:50.623288 ==
8340 22:53:50.626011 Dram Type= 6, Freq= 0, CH_1, rank 0
8341 22:53:50.629515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 22:53:50.632684 ==
8343 22:53:50.635884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8344 22:53:50.639321 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8345 22:53:50.646018 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8346 22:53:50.652442 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8347 22:53:50.659562 [CA 0] Center 43 (15~72) winsize 58
8348 22:53:50.663027 [CA 1] Center 43 (14~72) winsize 59
8349 22:53:50.666586 [CA 2] Center 38 (9~67) winsize 59
8350 22:53:50.670169 [CA 3] Center 37 (8~66) winsize 59
8351 22:53:50.673835 [CA 4] Center 38 (9~68) winsize 60
8352 22:53:50.676438 [CA 5] Center 36 (7~66) winsize 60
8353 22:53:50.676511
8354 22:53:50.680099 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8355 22:53:50.680166
8356 22:53:50.683451 [CATrainingPosCal] consider 1 rank data
8357 22:53:50.686761 u2DelayCellTimex100 = 275/100 ps
8358 22:53:50.689934 CA0 delay=43 (15~72),Diff = 7 PI (24 cell)
8359 22:53:50.696564 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8360 22:53:50.700134 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8361 22:53:50.703145 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8362 22:53:50.706908 CA4 delay=38 (9~68),Diff = 2 PI (7 cell)
8363 22:53:50.710624 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8364 22:53:50.710695
8365 22:53:50.713555 CA PerBit enable=1, Macro0, CA PI delay=36
8366 22:53:50.713650
8367 22:53:50.716643 [CBTSetCACLKResult] CA Dly = 36
8368 22:53:50.716714 CS Dly: 8 (0~39)
8369 22:53:50.723335 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8370 22:53:50.726509 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8371 22:53:50.726582 ==
8372 22:53:50.729838 Dram Type= 6, Freq= 0, CH_1, rank 1
8373 22:53:50.733250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 22:53:50.733323 ==
8375 22:53:50.740083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8376 22:53:50.743648 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8377 22:53:50.746596 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8378 22:53:50.753521 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8379 22:53:50.762960 [CA 0] Center 43 (14~72) winsize 59
8380 22:53:50.766530 [CA 1] Center 43 (14~72) winsize 59
8381 22:53:50.769358 [CA 2] Center 38 (9~67) winsize 59
8382 22:53:50.773141 [CA 3] Center 37 (8~66) winsize 59
8383 22:53:50.776371 [CA 4] Center 38 (9~68) winsize 60
8384 22:53:50.779747 [CA 5] Center 36 (7~66) winsize 60
8385 22:53:50.779828
8386 22:53:50.782805 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8387 22:53:50.782877
8388 22:53:50.786342 [CATrainingPosCal] consider 2 rank data
8389 22:53:50.789692 u2DelayCellTimex100 = 275/100 ps
8390 22:53:50.793191 CA0 delay=43 (15~72),Diff = 7 PI (24 cell)
8391 22:53:50.799402 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8392 22:53:50.802588 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8393 22:53:50.806314 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8394 22:53:50.809612 CA4 delay=38 (9~68),Diff = 2 PI (7 cell)
8395 22:53:50.812425 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8396 22:53:50.812502
8397 22:53:50.816398 CA PerBit enable=1, Macro0, CA PI delay=36
8398 22:53:50.816477
8399 22:53:50.819682 [CBTSetCACLKResult] CA Dly = 36
8400 22:53:50.822725 CS Dly: 11 (0~45)
8401 22:53:50.826220 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8402 22:53:50.829342 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8403 22:53:50.829414
8404 22:53:50.832653 ----->DramcWriteLeveling(PI) begin...
8405 22:53:50.832725 ==
8406 22:53:50.835959 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 22:53:50.839236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 22:53:50.842582 ==
8409 22:53:50.842654 Write leveling (Byte 0): 26 => 26
8410 22:53:50.845931 Write leveling (Byte 1): 30 => 30
8411 22:53:50.849086 DramcWriteLeveling(PI) end<-----
8412 22:53:50.849187
8413 22:53:50.849304 ==
8414 22:53:50.852763 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 22:53:50.859651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 22:53:50.859734 ==
8417 22:53:50.862358 [Gating] SW mode calibration
8418 22:53:50.869188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8419 22:53:50.872521 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8420 22:53:50.879307 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 22:53:50.882580 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 22:53:50.886182 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 22:53:50.889510 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 22:53:50.895976 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 22:53:50.899482 1 4 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8426 22:53:50.902647 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 22:53:50.909130 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 22:53:50.912437 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 22:53:50.915797 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 22:53:50.922799 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 22:53:50.926102 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 22:53:50.929361 1 5 16 | B1->B0 | 3030 3434 | 1 0 | (1 0) (0 1)
8433 22:53:50.936423 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8434 22:53:50.939200 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 22:53:50.942861 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 22:53:50.949575 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 22:53:50.952961 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 22:53:50.956124 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 22:53:50.959676 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 22:53:50.966699 1 6 16 | B1->B0 | 3232 3232 | 0 0 | (0 0) (0 0)
8441 22:53:50.969712 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8442 22:53:50.972658 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 22:53:50.979728 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 22:53:50.982743 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 22:53:50.986190 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 22:53:50.992909 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 22:53:50.996383 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 22:53:50.999806 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8449 22:53:51.006312 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8450 22:53:51.009631 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 22:53:51.012984 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 22:53:51.020042 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 22:53:51.022964 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 22:53:51.026484 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 22:53:51.033173 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 22:53:51.036586 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 22:53:51.039660 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 22:53:51.042815 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 22:53:51.049853 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 22:53:51.053241 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 22:53:51.056725 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 22:53:51.063116 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 22:53:51.066263 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 22:53:51.069840 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8465 22:53:51.076597 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8466 22:53:51.079782 Total UI for P1: 0, mck2ui 16
8467 22:53:51.083022 best dqsien dly found for B1: ( 1, 9, 16)
8468 22:53:51.086192 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 22:53:51.089958 Total UI for P1: 0, mck2ui 16
8470 22:53:51.093426 best dqsien dly found for B0: ( 1, 9, 18)
8471 22:53:51.096347 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
8472 22:53:51.099568 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8473 22:53:51.099641
8474 22:53:51.102767 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
8475 22:53:51.106312 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8476 22:53:51.109754 [Gating] SW calibration Done
8477 22:53:51.109825 ==
8478 22:53:51.112757 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 22:53:51.116246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 22:53:51.120008 ==
8481 22:53:51.120087 RX Vref Scan: 0
8482 22:53:51.120167
8483 22:53:51.123165 RX Vref 0 -> 0, step: 1
8484 22:53:51.123235
8485 22:53:51.126817 RX Delay 0 -> 252, step: 8
8486 22:53:51.129608 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8487 22:53:51.133177 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8488 22:53:51.136171 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8489 22:53:51.139625 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8490 22:53:51.146206 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8491 22:53:51.149577 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8492 22:53:51.152895 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8493 22:53:51.156243 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8494 22:53:51.159564 iDelay=208, Bit 8, Center 115 (64 ~ 167) 104
8495 22:53:51.162850 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8496 22:53:51.169379 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8497 22:53:51.172614 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8498 22:53:51.176226 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8499 22:53:51.179330 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8500 22:53:51.186260 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8501 22:53:51.189833 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8502 22:53:51.189907 ==
8503 22:53:51.193371 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 22:53:51.196433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 22:53:51.196505 ==
8506 22:53:51.196567 DQS Delay:
8507 22:53:51.199490 DQS0 = 0, DQS1 = 0
8508 22:53:51.199561 DQM Delay:
8509 22:53:51.202754 DQM0 = 135, DQM1 = 127
8510 22:53:51.202825 DQ Delay:
8511 22:53:51.206324 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8512 22:53:51.209622 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8513 22:53:51.212944 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8514 22:53:51.216119 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8515 22:53:51.219782
8516 22:53:51.219860
8517 22:53:51.219920 ==
8518 22:53:51.222862 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 22:53:51.226183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 22:53:51.226255 ==
8521 22:53:51.226323
8522 22:53:51.226380
8523 22:53:51.229380 TX Vref Scan disable
8524 22:53:51.229450 == TX Byte 0 ==
8525 22:53:51.236589 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8526 22:53:51.240034 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8527 22:53:51.240133 == TX Byte 1 ==
8528 22:53:51.246270 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8529 22:53:51.249357 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8530 22:53:51.249431 ==
8531 22:53:51.252782 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 22:53:51.255997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 22:53:51.256070 ==
8534 22:53:51.271179
8535 22:53:51.274057 TX Vref early break, caculate TX vref
8536 22:53:51.277652 TX Vref=16, minBit 0, minWin=21, winSum=359
8537 22:53:51.280543 TX Vref=18, minBit 5, minWin=22, winSum=371
8538 22:53:51.284110 TX Vref=20, minBit 8, minWin=22, winSum=375
8539 22:53:51.287655 TX Vref=22, minBit 8, minWin=22, winSum=391
8540 22:53:51.291121 TX Vref=24, minBit 8, minWin=24, winSum=402
8541 22:53:51.298008 TX Vref=26, minBit 11, minWin=24, winSum=410
8542 22:53:51.300829 TX Vref=28, minBit 0, minWin=25, winSum=413
8543 22:53:51.304178 TX Vref=30, minBit 0, minWin=24, winSum=413
8544 22:53:51.307522 TX Vref=32, minBit 0, minWin=24, winSum=405
8545 22:53:51.310905 TX Vref=34, minBit 11, minWin=23, winSum=393
8546 22:53:51.314150 TX Vref=36, minBit 0, minWin=23, winSum=385
8547 22:53:51.321100 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8548 22:53:51.321214
8549 22:53:51.324489 Final TX Range 0 Vref 28
8550 22:53:51.324571
8551 22:53:51.324635 ==
8552 22:53:51.327452 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 22:53:51.331085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 22:53:51.331172 ==
8555 22:53:51.331239
8556 22:53:51.331299
8557 22:53:51.334146 TX Vref Scan disable
8558 22:53:51.340722 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8559 22:53:51.340826 == TX Byte 0 ==
8560 22:53:51.344445 u2DelayCellOfst[0]=17 cells (5 PI)
8561 22:53:51.347899 u2DelayCellOfst[1]=10 cells (3 PI)
8562 22:53:51.351001 u2DelayCellOfst[2]=0 cells (0 PI)
8563 22:53:51.353882 u2DelayCellOfst[3]=7 cells (2 PI)
8564 22:53:51.357483 u2DelayCellOfst[4]=10 cells (3 PI)
8565 22:53:51.360752 u2DelayCellOfst[5]=21 cells (6 PI)
8566 22:53:51.363905 u2DelayCellOfst[6]=17 cells (5 PI)
8567 22:53:51.367572 u2DelayCellOfst[7]=7 cells (2 PI)
8568 22:53:51.370699 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8569 22:53:51.373981 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8570 22:53:51.377669 == TX Byte 1 ==
8571 22:53:51.377750 u2DelayCellOfst[8]=0 cells (0 PI)
8572 22:53:51.380560 u2DelayCellOfst[9]=7 cells (2 PI)
8573 22:53:51.383966 u2DelayCellOfst[10]=10 cells (3 PI)
8574 22:53:51.387126 u2DelayCellOfst[11]=7 cells (2 PI)
8575 22:53:51.391137 u2DelayCellOfst[12]=14 cells (4 PI)
8576 22:53:51.393992 u2DelayCellOfst[13]=17 cells (5 PI)
8577 22:53:51.397598 u2DelayCellOfst[14]=21 cells (6 PI)
8578 22:53:51.401327 u2DelayCellOfst[15]=17 cells (5 PI)
8579 22:53:51.404208 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8580 22:53:51.410513 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8581 22:53:51.410594 DramC Write-DBI on
8582 22:53:51.410657 ==
8583 22:53:51.414152 Dram Type= 6, Freq= 0, CH_1, rank 0
8584 22:53:51.417430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8585 22:53:51.420726 ==
8586 22:53:51.420802
8587 22:53:51.420870
8588 22:53:51.420929 TX Vref Scan disable
8589 22:53:51.423999 == TX Byte 0 ==
8590 22:53:51.427199 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8591 22:53:51.430914 == TX Byte 1 ==
8592 22:53:51.434017 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8593 22:53:51.437742 DramC Write-DBI off
8594 22:53:51.437819
8595 22:53:51.437879 [DATLAT]
8596 22:53:51.437945 Freq=1600, CH1 RK0
8597 22:53:51.438003
8598 22:53:51.440616 DATLAT Default: 0xf
8599 22:53:51.440683 0, 0xFFFF, sum = 0
8600 22:53:51.444238 1, 0xFFFF, sum = 0
8601 22:53:51.444315 2, 0xFFFF, sum = 0
8602 22:53:51.447804 3, 0xFFFF, sum = 0
8603 22:53:51.451090 4, 0xFFFF, sum = 0
8604 22:53:51.451166 5, 0xFFFF, sum = 0
8605 22:53:51.454309 6, 0xFFFF, sum = 0
8606 22:53:51.454381 7, 0xFFFF, sum = 0
8607 22:53:51.457661 8, 0xFFFF, sum = 0
8608 22:53:51.457735 9, 0xFFFF, sum = 0
8609 22:53:51.461111 10, 0xFFFF, sum = 0
8610 22:53:51.461191 11, 0xFFFF, sum = 0
8611 22:53:51.464177 12, 0xFFFF, sum = 0
8612 22:53:51.464249 13, 0xFFFF, sum = 0
8613 22:53:51.467537 14, 0x0, sum = 1
8614 22:53:51.467615 15, 0x0, sum = 2
8615 22:53:51.471105 16, 0x0, sum = 3
8616 22:53:51.471175 17, 0x0, sum = 4
8617 22:53:51.471236 best_step = 15
8618 22:53:51.474305
8619 22:53:51.474384 ==
8620 22:53:51.477419 Dram Type= 6, Freq= 0, CH_1, rank 0
8621 22:53:51.481295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8622 22:53:51.481372 ==
8623 22:53:51.481441 RX Vref Scan: 1
8624 22:53:51.481500
8625 22:53:51.484609 Set Vref Range= 24 -> 127
8626 22:53:51.484699
8627 22:53:51.487365 RX Vref 24 -> 127, step: 1
8628 22:53:51.487435
8629 22:53:51.490951 RX Delay 19 -> 252, step: 4
8630 22:53:51.491022
8631 22:53:51.494041 Set Vref, RX VrefLevel [Byte0]: 24
8632 22:53:51.497899 [Byte1]: 24
8633 22:53:51.497974
8634 22:53:51.501059 Set Vref, RX VrefLevel [Byte0]: 25
8635 22:53:51.504464 [Byte1]: 25
8636 22:53:51.504535
8637 22:53:51.507644 Set Vref, RX VrefLevel [Byte0]: 26
8638 22:53:51.511260 [Byte1]: 26
8639 22:53:51.514369
8640 22:53:51.514440 Set Vref, RX VrefLevel [Byte0]: 27
8641 22:53:51.517495 [Byte1]: 27
8642 22:53:51.521956
8643 22:53:51.522029 Set Vref, RX VrefLevel [Byte0]: 28
8644 22:53:51.525290 [Byte1]: 28
8645 22:53:51.529833
8646 22:53:51.529909 Set Vref, RX VrefLevel [Byte0]: 29
8647 22:53:51.533217 [Byte1]: 29
8648 22:53:51.537162
8649 22:53:51.537294 Set Vref, RX VrefLevel [Byte0]: 30
8650 22:53:51.540502 [Byte1]: 30
8651 22:53:51.544513
8652 22:53:51.544584 Set Vref, RX VrefLevel [Byte0]: 31
8653 22:53:51.548169 [Byte1]: 31
8654 22:53:51.552477
8655 22:53:51.552549 Set Vref, RX VrefLevel [Byte0]: 32
8656 22:53:51.555525 [Byte1]: 32
8657 22:53:51.559856
8658 22:53:51.559930 Set Vref, RX VrefLevel [Byte0]: 33
8659 22:53:51.563843 [Byte1]: 33
8660 22:53:51.568017
8661 22:53:51.568087 Set Vref, RX VrefLevel [Byte0]: 34
8662 22:53:51.570536 [Byte1]: 34
8663 22:53:51.574985
8664 22:53:51.575054 Set Vref, RX VrefLevel [Byte0]: 35
8665 22:53:51.578111 [Byte1]: 35
8666 22:53:51.582897
8667 22:53:51.582969 Set Vref, RX VrefLevel [Byte0]: 36
8668 22:53:51.585837 [Byte1]: 36
8669 22:53:51.590309
8670 22:53:51.590386 Set Vref, RX VrefLevel [Byte0]: 37
8671 22:53:51.593756 [Byte1]: 37
8672 22:53:51.598088
8673 22:53:51.598167 Set Vref, RX VrefLevel [Byte0]: 38
8674 22:53:51.600965 [Byte1]: 38
8675 22:53:51.605500
8676 22:53:51.605581 Set Vref, RX VrefLevel [Byte0]: 39
8677 22:53:51.608560 [Byte1]: 39
8678 22:53:51.612856
8679 22:53:51.612933 Set Vref, RX VrefLevel [Byte0]: 40
8680 22:53:51.616187 [Byte1]: 40
8681 22:53:51.620633
8682 22:53:51.620708 Set Vref, RX VrefLevel [Byte0]: 41
8683 22:53:51.623644 [Byte1]: 41
8684 22:53:51.627683
8685 22:53:51.627763 Set Vref, RX VrefLevel [Byte0]: 42
8686 22:53:51.631151 [Byte1]: 42
8687 22:53:51.635374
8688 22:53:51.635455 Set Vref, RX VrefLevel [Byte0]: 43
8689 22:53:51.638801 [Byte1]: 43
8690 22:53:51.642955
8691 22:53:51.643027 Set Vref, RX VrefLevel [Byte0]: 44
8692 22:53:51.646376 [Byte1]: 44
8693 22:53:51.650603
8694 22:53:51.650674 Set Vref, RX VrefLevel [Byte0]: 45
8695 22:53:51.654392 [Byte1]: 45
8696 22:53:51.658349
8697 22:53:51.658422 Set Vref, RX VrefLevel [Byte0]: 46
8698 22:53:51.661369 [Byte1]: 46
8699 22:53:51.665559
8700 22:53:51.665639 Set Vref, RX VrefLevel [Byte0]: 47
8701 22:53:51.669504 [Byte1]: 47
8702 22:53:51.673338
8703 22:53:51.673410 Set Vref, RX VrefLevel [Byte0]: 48
8704 22:53:51.676784 [Byte1]: 48
8705 22:53:51.681030
8706 22:53:51.681104 Set Vref, RX VrefLevel [Byte0]: 49
8707 22:53:51.684395 [Byte1]: 49
8708 22:53:51.688503
8709 22:53:51.688603 Set Vref, RX VrefLevel [Byte0]: 50
8710 22:53:51.691739 [Byte1]: 50
8711 22:53:51.696132
8712 22:53:51.696236 Set Vref, RX VrefLevel [Byte0]: 51
8713 22:53:51.699225 [Byte1]: 51
8714 22:53:51.703813
8715 22:53:51.703912 Set Vref, RX VrefLevel [Byte0]: 52
8716 22:53:51.706934 [Byte1]: 52
8717 22:53:51.711250
8718 22:53:51.711346 Set Vref, RX VrefLevel [Byte0]: 53
8719 22:53:51.714814 [Byte1]: 53
8720 22:53:51.718714
8721 22:53:51.718794 Set Vref, RX VrefLevel [Byte0]: 54
8722 22:53:51.722285 [Byte1]: 54
8723 22:53:51.726471
8724 22:53:51.726542 Set Vref, RX VrefLevel [Byte0]: 55
8725 22:53:51.729847 [Byte1]: 55
8726 22:53:51.734008
8727 22:53:51.734079 Set Vref, RX VrefLevel [Byte0]: 56
8728 22:53:51.737513 [Byte1]: 56
8729 22:53:51.741779
8730 22:53:51.741851 Set Vref, RX VrefLevel [Byte0]: 57
8731 22:53:51.745332 [Byte1]: 57
8732 22:53:51.749028
8733 22:53:51.749108 Set Vref, RX VrefLevel [Byte0]: 58
8734 22:53:51.752869 [Byte1]: 58
8735 22:53:51.756837
8736 22:53:51.756918 Set Vref, RX VrefLevel [Byte0]: 59
8737 22:53:51.760056 [Byte1]: 59
8738 22:53:51.764282
8739 22:53:51.764364 Set Vref, RX VrefLevel [Byte0]: 60
8740 22:53:51.767598 [Byte1]: 60
8741 22:53:51.771519
8742 22:53:51.771595 Set Vref, RX VrefLevel [Byte0]: 61
8743 22:53:51.775185 [Byte1]: 61
8744 22:53:51.779086
8745 22:53:51.779161 Set Vref, RX VrefLevel [Byte0]: 62
8746 22:53:51.784766 [Byte1]: 62
8747 22:53:51.787443
8748 22:53:51.787516 Set Vref, RX VrefLevel [Byte0]: 63
8749 22:53:51.790599 [Byte1]: 63
8750 22:53:51.794361
8751 22:53:51.794434 Set Vref, RX VrefLevel [Byte0]: 64
8752 22:53:51.798480 [Byte1]: 64
8753 22:53:51.802060
8754 22:53:51.802132 Set Vref, RX VrefLevel [Byte0]: 65
8755 22:53:51.805310 [Byte1]: 65
8756 22:53:51.809367
8757 22:53:51.809439 Set Vref, RX VrefLevel [Byte0]: 66
8758 22:53:51.812881 [Byte1]: 66
8759 22:53:51.818013
8760 22:53:51.818095 Set Vref, RX VrefLevel [Byte0]: 67
8761 22:53:51.820433 [Byte1]: 67
8762 22:53:51.824902
8763 22:53:51.824973 Set Vref, RX VrefLevel [Byte0]: 68
8764 22:53:51.827937 [Byte1]: 68
8765 22:53:51.832469
8766 22:53:51.832540 Set Vref, RX VrefLevel [Byte0]: 69
8767 22:53:51.835894 [Byte1]: 69
8768 22:53:51.839929
8769 22:53:51.840001 Set Vref, RX VrefLevel [Byte0]: 70
8770 22:53:51.843219 [Byte1]: 70
8771 22:53:51.847436
8772 22:53:51.847508 Set Vref, RX VrefLevel [Byte0]: 71
8773 22:53:51.851096 [Byte1]: 71
8774 22:53:51.855268
8775 22:53:51.855343 Set Vref, RX VrefLevel [Byte0]: 72
8776 22:53:51.858766 [Byte1]: 72
8777 22:53:51.862376
8778 22:53:51.862452 Set Vref, RX VrefLevel [Byte0]: 73
8779 22:53:51.866071 [Byte1]: 73
8780 22:53:51.869946
8781 22:53:51.870016 Set Vref, RX VrefLevel [Byte0]: 74
8782 22:53:51.873411 [Byte1]: 74
8783 22:53:51.878379
8784 22:53:51.878455 Final RX Vref Byte 0 = 62 to rank0
8785 22:53:51.881625 Final RX Vref Byte 1 = 58 to rank0
8786 22:53:51.884874 Final RX Vref Byte 0 = 62 to rank1
8787 22:53:51.888400 Final RX Vref Byte 1 = 58 to rank1==
8788 22:53:51.891107 Dram Type= 6, Freq= 0, CH_1, rank 0
8789 22:53:51.898062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 22:53:51.898138 ==
8791 22:53:51.898201 DQS Delay:
8792 22:53:51.898267 DQS0 = 0, DQS1 = 0
8793 22:53:51.901186 DQM Delay:
8794 22:53:51.901274 DQM0 = 131, DQM1 = 124
8795 22:53:51.904446 DQ Delay:
8796 22:53:51.908574 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8797 22:53:51.911262 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8798 22:53:51.915033 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =118
8799 22:53:51.917709 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8800 22:53:51.917788
8801 22:53:51.917851
8802 22:53:51.917909
8803 22:53:51.921534 [DramC_TX_OE_Calibration] TA2
8804 22:53:51.924626 Original DQ_B0 (3 6) =30, OEN = 27
8805 22:53:51.927870 Original DQ_B1 (3 6) =30, OEN = 27
8806 22:53:51.927949 24, 0x0, End_B0=24 End_B1=24
8807 22:53:51.931430 25, 0x0, End_B0=25 End_B1=25
8808 22:53:51.934947 26, 0x0, End_B0=26 End_B1=26
8809 22:53:51.938340 27, 0x0, End_B0=27 End_B1=27
8810 22:53:51.941626 28, 0x0, End_B0=28 End_B1=28
8811 22:53:51.941709 29, 0x0, End_B0=29 End_B1=29
8812 22:53:51.944769 30, 0x0, End_B0=30 End_B1=30
8813 22:53:51.948032 31, 0x4141, End_B0=30 End_B1=30
8814 22:53:51.951024 Byte0 end_step=30 best_step=27
8815 22:53:51.955075 Byte1 end_step=30 best_step=27
8816 22:53:51.957803 Byte0 TX OE(2T, 0.5T) = (3, 3)
8817 22:53:51.957888 Byte1 TX OE(2T, 0.5T) = (3, 3)
8818 22:53:51.957953
8819 22:53:51.961403
8820 22:53:51.967759 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fd, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8821 22:53:51.971277 CH1 RK0: MR19=302, MR18=13FD
8822 22:53:51.978133 CH1_RK0: MR19=0x302, MR18=0x13FD, DQSOSC=400, MR23=63, INC=23, DEC=15
8823 22:53:51.978216
8824 22:53:51.981274 ----->DramcWriteLeveling(PI) begin...
8825 22:53:51.981357 ==
8826 22:53:51.984550 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 22:53:51.987991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 22:53:51.988073 ==
8829 22:53:51.991317 Write leveling (Byte 0): 23 => 23
8830 22:53:51.994240 Write leveling (Byte 1): 26 => 26
8831 22:53:51.998112 DramcWriteLeveling(PI) end<-----
8832 22:53:51.998193
8833 22:53:51.998257 ==
8834 22:53:52.001981 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 22:53:52.004602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 22:53:52.004684 ==
8837 22:53:52.007810 [Gating] SW mode calibration
8838 22:53:52.014485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8839 22:53:52.021236 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8840 22:53:52.024166 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 22:53:52.027575 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 22:53:52.034573 1 4 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 0)
8843 22:53:52.037769 1 4 12 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8844 22:53:52.041185 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 22:53:52.047833 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8846 22:53:52.051221 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8847 22:53:52.054369 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 22:53:52.061006 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 22:53:52.064419 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8850 22:53:52.067868 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8851 22:53:52.070898 1 5 12 | B1->B0 | 2e2e 2424 | 1 0 | (1 1) (1 0)
8852 22:53:52.077399 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8853 22:53:52.081269 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 22:53:52.084573 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8855 22:53:52.091211 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 22:53:52.094511 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 22:53:52.097741 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 22:53:52.104875 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8859 22:53:52.107951 1 6 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8860 22:53:52.111356 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 22:53:52.117856 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 22:53:52.121628 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 22:53:52.124668 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 22:53:52.131211 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 22:53:52.134407 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 22:53:52.137763 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8867 22:53:52.144518 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8868 22:53:52.147679 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8869 22:53:52.151152 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 22:53:52.157924 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 22:53:52.161231 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 22:53:52.164843 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 22:53:52.167982 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 22:53:52.174459 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 22:53:52.177580 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 22:53:52.181029 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 22:53:52.187821 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 22:53:52.190931 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 22:53:52.194195 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 22:53:52.200955 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 22:53:52.204360 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8882 22:53:52.207845 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8883 22:53:52.214402 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8884 22:53:52.214485 Total UI for P1: 0, mck2ui 16
8885 22:53:52.221123 best dqsien dly found for B0: ( 1, 9, 6)
8886 22:53:52.224166 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 22:53:52.227626 Total UI for P1: 0, mck2ui 16
8888 22:53:52.231208 best dqsien dly found for B1: ( 1, 9, 12)
8889 22:53:52.234746 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8890 22:53:52.237538 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8891 22:53:52.237613
8892 22:53:52.240979 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8893 22:53:52.244831 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8894 22:53:52.247716 [Gating] SW calibration Done
8895 22:53:52.247792 ==
8896 22:53:52.250959 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 22:53:52.254306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 22:53:52.254386 ==
8899 22:53:52.257753 RX Vref Scan: 0
8900 22:53:52.257822
8901 22:53:52.260918 RX Vref 0 -> 0, step: 1
8902 22:53:52.260996
8903 22:53:52.261057 RX Delay 0 -> 252, step: 8
8904 22:53:52.267674 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8905 22:53:52.271012 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8906 22:53:52.274768 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8907 22:53:52.278146 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8908 22:53:52.281435 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8909 22:53:52.287815 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8910 22:53:52.291251 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8911 22:53:52.294284 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8912 22:53:52.298005 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8913 22:53:52.301314 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8914 22:53:52.307754 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8915 22:53:52.310835 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8916 22:53:52.314735 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8917 22:53:52.317521 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8918 22:53:52.321086 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8919 22:53:52.327895 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8920 22:53:52.327985 ==
8921 22:53:52.330876 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 22:53:52.334326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 22:53:52.334405 ==
8924 22:53:52.334467 DQS Delay:
8925 22:53:52.337762 DQS0 = 0, DQS1 = 0
8926 22:53:52.337831 DQM Delay:
8927 22:53:52.340829 DQM0 = 133, DQM1 = 127
8928 22:53:52.340905 DQ Delay:
8929 22:53:52.344042 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8930 22:53:52.347682 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8931 22:53:52.350741 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8932 22:53:52.354430 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8933 22:53:52.354510
8934 22:53:52.354572
8935 22:53:52.357936 ==
8936 22:53:52.360960 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 22:53:52.364755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 22:53:52.364838 ==
8939 22:53:52.364901
8940 22:53:52.364960
8941 22:53:52.367714 TX Vref Scan disable
8942 22:53:52.367788 == TX Byte 0 ==
8943 22:53:52.370939 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8944 22:53:52.377678 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8945 22:53:52.377759 == TX Byte 1 ==
8946 22:53:52.381232 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8947 22:53:52.388151 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8948 22:53:52.388233 ==
8949 22:53:52.391435 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 22:53:52.394460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 22:53:52.394546 ==
8952 22:53:52.408499
8953 22:53:52.411977 TX Vref early break, caculate TX vref
8954 22:53:52.415389 TX Vref=16, minBit 0, minWin=23, winSum=381
8955 22:53:52.418421 TX Vref=18, minBit 15, minWin=23, winSum=392
8956 22:53:52.422263 TX Vref=20, minBit 5, minWin=24, winSum=402
8957 22:53:52.424840 TX Vref=22, minBit 8, minWin=24, winSum=411
8958 22:53:52.428395 TX Vref=24, minBit 8, minWin=25, winSum=416
8959 22:53:52.434791 TX Vref=26, minBit 0, minWin=26, winSum=428
8960 22:53:52.438365 TX Vref=28, minBit 0, minWin=26, winSum=425
8961 22:53:52.441642 TX Vref=30, minBit 0, minWin=26, winSum=425
8962 22:53:52.445166 TX Vref=32, minBit 0, minWin=25, winSum=419
8963 22:53:52.448663 TX Vref=34, minBit 0, minWin=24, winSum=412
8964 22:53:52.451507 TX Vref=36, minBit 0, minWin=24, winSum=402
8965 22:53:52.458819 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8966 22:53:52.458894
8967 22:53:52.461901 Final TX Range 0 Vref 26
8968 22:53:52.461972
8969 22:53:52.462039 ==
8970 22:53:52.464884 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 22:53:52.468092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 22:53:52.468160 ==
8973 22:53:52.468225
8974 22:53:52.468282
8975 22:53:52.471384 TX Vref Scan disable
8976 22:53:52.478262 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8977 22:53:52.478341 == TX Byte 0 ==
8978 22:53:52.482171 u2DelayCellOfst[0]=17 cells (5 PI)
8979 22:53:52.485038 u2DelayCellOfst[1]=14 cells (4 PI)
8980 22:53:52.488428 u2DelayCellOfst[2]=0 cells (0 PI)
8981 22:53:52.491883 u2DelayCellOfst[3]=7 cells (2 PI)
8982 22:53:52.495039 u2DelayCellOfst[4]=7 cells (2 PI)
8983 22:53:52.498342 u2DelayCellOfst[5]=17 cells (5 PI)
8984 22:53:52.501914 u2DelayCellOfst[6]=17 cells (5 PI)
8985 22:53:52.505044 u2DelayCellOfst[7]=7 cells (2 PI)
8986 22:53:52.508666 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8987 22:53:52.511383 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8988 22:53:52.514776 == TX Byte 1 ==
8989 22:53:52.514857 u2DelayCellOfst[8]=0 cells (0 PI)
8990 22:53:52.518594 u2DelayCellOfst[9]=7 cells (2 PI)
8991 22:53:52.521273 u2DelayCellOfst[10]=14 cells (4 PI)
8992 22:53:52.524853 u2DelayCellOfst[11]=7 cells (2 PI)
8993 22:53:52.528224 u2DelayCellOfst[12]=17 cells (5 PI)
8994 22:53:52.531673 u2DelayCellOfst[13]=17 cells (5 PI)
8995 22:53:52.534935 u2DelayCellOfst[14]=17 cells (5 PI)
8996 22:53:52.538462 u2DelayCellOfst[15]=17 cells (5 PI)
8997 22:53:52.541559 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8998 22:53:52.548068 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8999 22:53:52.548150 DramC Write-DBI on
9000 22:53:52.548214 ==
9001 22:53:52.551539 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 22:53:52.554971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 22:53:52.558245 ==
9004 22:53:52.558326
9005 22:53:52.558390
9006 22:53:52.558450 TX Vref Scan disable
9007 22:53:52.561651 == TX Byte 0 ==
9008 22:53:52.565257 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9009 22:53:52.568286 == TX Byte 1 ==
9010 22:53:52.571768 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9011 22:53:52.571850 DramC Write-DBI off
9012 22:53:52.574684
9013 22:53:52.574765 [DATLAT]
9014 22:53:52.574829 Freq=1600, CH1 RK1
9015 22:53:52.574890
9016 22:53:52.578594 DATLAT Default: 0xf
9017 22:53:52.578675 0, 0xFFFF, sum = 0
9018 22:53:52.581940 1, 0xFFFF, sum = 0
9019 22:53:52.582023 2, 0xFFFF, sum = 0
9020 22:53:52.584993 3, 0xFFFF, sum = 0
9021 22:53:52.588423 4, 0xFFFF, sum = 0
9022 22:53:52.588506 5, 0xFFFF, sum = 0
9023 22:53:52.591488 6, 0xFFFF, sum = 0
9024 22:53:52.591570 7, 0xFFFF, sum = 0
9025 22:53:52.595122 8, 0xFFFF, sum = 0
9026 22:53:52.595204 9, 0xFFFF, sum = 0
9027 22:53:52.598171 10, 0xFFFF, sum = 0
9028 22:53:52.598254 11, 0xFFFF, sum = 0
9029 22:53:52.601597 12, 0xFFFF, sum = 0
9030 22:53:52.601680 13, 0xFFFF, sum = 0
9031 22:53:52.605077 14, 0x0, sum = 1
9032 22:53:52.605159 15, 0x0, sum = 2
9033 22:53:52.608180 16, 0x0, sum = 3
9034 22:53:52.608263 17, 0x0, sum = 4
9035 22:53:52.611675 best_step = 15
9036 22:53:52.611756
9037 22:53:52.611819 ==
9038 22:53:52.614953 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 22:53:52.618717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 22:53:52.618799 ==
9041 22:53:52.618863 RX Vref Scan: 0
9042 22:53:52.618923
9043 22:53:52.621696 RX Vref 0 -> 0, step: 1
9044 22:53:52.621777
9045 22:53:52.624799 RX Delay 11 -> 252, step: 4
9046 22:53:52.628031 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
9047 22:53:52.635197 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
9048 22:53:52.638792 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9049 22:53:52.641703 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
9050 22:53:52.644894 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9051 22:53:52.648294 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9052 22:53:52.651708 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9053 22:53:52.658311 iDelay=191, Bit 7, Center 124 (75 ~ 174) 100
9054 22:53:52.661785 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9055 22:53:52.664656 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9056 22:53:52.668423 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9057 22:53:52.671928 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
9058 22:53:52.678218 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9059 22:53:52.682030 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9060 22:53:52.684810 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
9061 22:53:52.688642 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
9062 22:53:52.688723 ==
9063 22:53:52.691676 Dram Type= 6, Freq= 0, CH_1, rank 1
9064 22:53:52.698405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9065 22:53:52.698487 ==
9066 22:53:52.698552 DQS Delay:
9067 22:53:52.701443 DQS0 = 0, DQS1 = 0
9068 22:53:52.701525 DQM Delay:
9069 22:53:52.701590 DQM0 = 129, DQM1 = 126
9070 22:53:52.704852 DQ Delay:
9071 22:53:52.708385 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =126
9072 22:53:52.711733 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
9073 22:53:52.715051 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9074 22:53:52.718419 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9075 22:53:52.718501
9076 22:53:52.718565
9077 22:53:52.718625
9078 22:53:52.721600 [DramC_TX_OE_Calibration] TA2
9079 22:53:52.724621 Original DQ_B0 (3 6) =30, OEN = 27
9080 22:53:52.727963 Original DQ_B1 (3 6) =30, OEN = 27
9081 22:53:52.731454 24, 0x0, End_B0=24 End_B1=24
9082 22:53:52.731565 25, 0x0, End_B0=25 End_B1=25
9083 22:53:52.734616 26, 0x0, End_B0=26 End_B1=26
9084 22:53:52.738403 27, 0x0, End_B0=27 End_B1=27
9085 22:53:52.741632 28, 0x0, End_B0=28 End_B1=28
9086 22:53:52.744967 29, 0x0, End_B0=29 End_B1=29
9087 22:53:52.745049 30, 0x0, End_B0=30 End_B1=30
9088 22:53:52.748127 31, 0x4141, End_B0=30 End_B1=30
9089 22:53:52.751523 Byte0 end_step=30 best_step=27
9090 22:53:52.754864 Byte1 end_step=30 best_step=27
9091 22:53:52.758290 Byte0 TX OE(2T, 0.5T) = (3, 3)
9092 22:53:52.761908 Byte1 TX OE(2T, 0.5T) = (3, 3)
9093 22:53:52.761990
9094 22:53:52.762054
9095 22:53:52.768257 [DQSOSCAuto] RK1, (LSB)MR18= 0x1015, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
9096 22:53:52.771197 CH1 RK1: MR19=303, MR18=1015
9097 22:53:52.778556 CH1_RK1: MR19=0x303, MR18=0x1015, DQSOSC=399, MR23=63, INC=23, DEC=15
9098 22:53:52.781667 [RxdqsGatingPostProcess] freq 1600
9099 22:53:52.784741 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9100 22:53:52.787945 best DQS0 dly(2T, 0.5T) = (1, 1)
9101 22:53:52.791947 best DQS1 dly(2T, 0.5T) = (1, 1)
9102 22:53:52.794603 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9103 22:53:52.798238 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9104 22:53:52.802327 best DQS0 dly(2T, 0.5T) = (1, 1)
9105 22:53:52.804977 best DQS1 dly(2T, 0.5T) = (1, 1)
9106 22:53:52.808008 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9107 22:53:52.811750 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9108 22:53:52.814946 Pre-setting of DQS Precalculation
9109 22:53:52.817761 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9110 22:53:52.825327 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9111 22:53:52.831398 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 22:53:52.831480
9113 22:53:52.834858
9114 22:53:52.834938 [Calibration Summary] 3200 Mbps
9115 22:53:52.837798 CH 0, Rank 0
9116 22:53:52.837880 SW Impedance : PASS
9117 22:53:52.841541 DUTY Scan : NO K
9118 22:53:52.844756 ZQ Calibration : PASS
9119 22:53:52.844837 Jitter Meter : NO K
9120 22:53:52.847912 CBT Training : PASS
9121 22:53:52.851072 Write leveling : PASS
9122 22:53:52.851154 RX DQS gating : PASS
9123 22:53:52.854710 RX DQ/DQS(RDDQC) : PASS
9124 22:53:52.858251 TX DQ/DQS : PASS
9125 22:53:52.858333 RX DATLAT : PASS
9126 22:53:52.861151 RX DQ/DQS(Engine): PASS
9127 22:53:52.864549 TX OE : PASS
9128 22:53:52.864631 All Pass.
9129 22:53:52.864695
9130 22:53:52.864754 CH 0, Rank 1
9131 22:53:52.867708 SW Impedance : PASS
9132 22:53:52.871317 DUTY Scan : NO K
9133 22:53:52.871398 ZQ Calibration : PASS
9134 22:53:52.874444 Jitter Meter : NO K
9135 22:53:52.874525 CBT Training : PASS
9136 22:53:52.877994 Write leveling : PASS
9137 22:53:52.881685 RX DQS gating : PASS
9138 22:53:52.881766 RX DQ/DQS(RDDQC) : PASS
9139 22:53:52.884769 TX DQ/DQS : PASS
9140 22:53:52.887811 RX DATLAT : PASS
9141 22:53:52.887892 RX DQ/DQS(Engine): PASS
9142 22:53:52.891196 TX OE : PASS
9143 22:53:52.891280 All Pass.
9144 22:53:52.891370
9145 22:53:52.894696 CH 1, Rank 0
9146 22:53:52.894777 SW Impedance : PASS
9147 22:53:52.898232 DUTY Scan : NO K
9148 22:53:52.902005 ZQ Calibration : PASS
9149 22:53:52.902087 Jitter Meter : NO K
9150 22:53:52.904623 CBT Training : PASS
9151 22:53:52.907762 Write leveling : PASS
9152 22:53:52.907843 RX DQS gating : PASS
9153 22:53:52.911999 RX DQ/DQS(RDDQC) : PASS
9154 22:53:52.912081 TX DQ/DQS : PASS
9155 22:53:52.915099 RX DATLAT : PASS
9156 22:53:52.918178 RX DQ/DQS(Engine): PASS
9157 22:53:52.918260 TX OE : PASS
9158 22:53:52.921248 All Pass.
9159 22:53:52.921329
9160 22:53:52.921393 CH 1, Rank 1
9161 22:53:52.924424 SW Impedance : PASS
9162 22:53:52.924505 DUTY Scan : NO K
9163 22:53:52.927822 ZQ Calibration : PASS
9164 22:53:52.931846 Jitter Meter : NO K
9165 22:53:52.931932 CBT Training : PASS
9166 22:53:52.934651 Write leveling : PASS
9167 22:53:52.937888 RX DQS gating : PASS
9168 22:53:52.937970 RX DQ/DQS(RDDQC) : PASS
9169 22:53:52.941487 TX DQ/DQS : PASS
9170 22:53:52.944755 RX DATLAT : PASS
9171 22:53:52.944837 RX DQ/DQS(Engine): PASS
9172 22:53:52.947920 TX OE : PASS
9173 22:53:52.948007 All Pass.
9174 22:53:52.948073
9175 22:53:52.951082 DramC Write-DBI on
9176 22:53:52.954791 PER_BANK_REFRESH: Hybrid Mode
9177 22:53:52.954864 TX_TRACKING: ON
9178 22:53:52.964729 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9179 22:53:52.971337 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9180 22:53:52.977983 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9181 22:53:52.981637 [FAST_K] Save calibration result to emmc
9182 22:53:52.985033 sync common calibartion params.
9183 22:53:52.988296 sync cbt_mode0:1, 1:1
9184 22:53:52.988371 dram_init: ddr_geometry: 2
9185 22:53:52.991688 dram_init: ddr_geometry: 2
9186 22:53:52.994888 dram_init: ddr_geometry: 2
9187 22:53:52.998325 0:dram_rank_size:100000000
9188 22:53:52.998402 1:dram_rank_size:100000000
9189 22:53:53.005088 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9190 22:53:53.008219 DFS_SHUFFLE_HW_MODE: ON
9191 22:53:53.011571 dramc_set_vcore_voltage set vcore to 725000
9192 22:53:53.016032 Read voltage for 1600, 0
9193 22:53:53.016103 Vio18 = 0
9194 22:53:53.016163 Vcore = 725000
9195 22:53:53.016228 Vdram = 0
9196 22:53:53.018008 Vddq = 0
9197 22:53:53.018080 Vmddr = 0
9198 22:53:53.021348 switch to 3200 Mbps bootup
9199 22:53:53.021416 [DramcRunTimeConfig]
9200 22:53:53.024827 PHYPLL
9201 22:53:53.024893 DPM_CONTROL_AFTERK: ON
9202 22:53:53.028254 PER_BANK_REFRESH: ON
9203 22:53:53.031390 REFRESH_OVERHEAD_REDUCTION: ON
9204 22:53:53.031460 CMD_PICG_NEW_MODE: OFF
9205 22:53:53.035235 XRTWTW_NEW_MODE: ON
9206 22:53:53.035307 XRTRTR_NEW_MODE: ON
9207 22:53:53.038216 TX_TRACKING: ON
9208 22:53:53.038283 RDSEL_TRACKING: OFF
9209 22:53:53.041457 DQS Precalculation for DVFS: ON
9210 22:53:53.044775 RX_TRACKING: OFF
9211 22:53:53.044842 HW_GATING DBG: ON
9212 22:53:53.048849 ZQCS_ENABLE_LP4: ON
9213 22:53:53.048919 RX_PICG_NEW_MODE: ON
9214 22:53:53.051259 TX_PICG_NEW_MODE: ON
9215 22:53:53.051329 ENABLE_RX_DCM_DPHY: ON
9216 22:53:53.054826 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9217 22:53:53.058039 DUMMY_READ_FOR_TRACKING: OFF
9218 22:53:53.061543 !!! SPM_CONTROL_AFTERK: OFF
9219 22:53:53.065302 !!! SPM could not control APHY
9220 22:53:53.065370 IMPEDANCE_TRACKING: ON
9221 22:53:53.068312 TEMP_SENSOR: ON
9222 22:53:53.068382 HW_SAVE_FOR_SR: OFF
9223 22:53:53.071317 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9224 22:53:53.074700 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9225 22:53:53.078511 Read ODT Tracking: ON
9226 22:53:53.078580 Refresh Rate DeBounce: ON
9227 22:53:53.081304 DFS_NO_QUEUE_FLUSH: ON
9228 22:53:53.085203 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9229 22:53:53.088296 ENABLE_DFS_RUNTIME_MRW: OFF
9230 22:53:53.088368 DDR_RESERVE_NEW_MODE: ON
9231 22:53:53.091525 MR_CBT_SWITCH_FREQ: ON
9232 22:53:53.094944 =========================
9233 22:53:53.113133 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9234 22:53:53.116229 dram_init: ddr_geometry: 2
9235 22:53:53.135075 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9236 22:53:53.138055 dram_init: dram init end (result: 0)
9237 22:53:53.144606 DRAM-K: Full calibration passed in 24576 msecs
9238 22:53:53.147868 MRC: failed to locate region type 0.
9239 22:53:53.147950 DRAM rank0 size:0x100000000,
9240 22:53:53.151434 DRAM rank1 size=0x100000000
9241 22:53:53.161130 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9242 22:53:53.168062 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9243 22:53:53.174383 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9244 22:53:53.181161 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9245 22:53:53.184721 DRAM rank0 size:0x100000000,
9246 22:53:53.187757 DRAM rank1 size=0x100000000
9247 22:53:53.187830 CBMEM:
9248 22:53:53.191097 IMD: root @ 0xfffff000 254 entries.
9249 22:53:53.194398 IMD: root @ 0xffffec00 62 entries.
9250 22:53:53.198228 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9251 22:53:53.201242 WARNING: RO_VPD is uninitialized or empty.
9252 22:53:53.207810 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9253 22:53:53.214670 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9254 22:53:53.227130 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9255 22:53:53.238774 BS: romstage times (exec / console): total (unknown) / 24079 ms
9256 22:53:53.238852
9257 22:53:53.238916
9258 22:53:53.249135 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9259 22:53:53.252553 ARM64: Exception handlers installed.
9260 22:53:53.255410 ARM64: Testing exception
9261 22:53:53.258563 ARM64: Done test exception
9262 22:53:53.258641 Enumerating buses...
9263 22:53:53.262401 Show all devs... Before device enumeration.
9264 22:53:53.265291 Root Device: enabled 1
9265 22:53:53.268395 CPU_CLUSTER: 0: enabled 1
9266 22:53:53.268462 CPU: 00: enabled 1
9267 22:53:53.272251 Compare with tree...
9268 22:53:53.272323 Root Device: enabled 1
9269 22:53:53.275138 CPU_CLUSTER: 0: enabled 1
9270 22:53:53.278842 CPU: 00: enabled 1
9271 22:53:53.278912 Root Device scanning...
9272 22:53:53.281876 scan_static_bus for Root Device
9273 22:53:53.285330 CPU_CLUSTER: 0 enabled
9274 22:53:53.288692 scan_static_bus for Root Device done
9275 22:53:53.292239 scan_bus: bus Root Device finished in 8 msecs
9276 22:53:53.292320 done
9277 22:53:53.299104 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9278 22:53:53.302127 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9279 22:53:53.308540 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9280 22:53:53.311862 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9281 22:53:53.315184 Allocating resources...
9282 22:53:53.315264 Reading resources...
9283 22:53:53.322075 Root Device read_resources bus 0 link: 0
9284 22:53:53.322156 DRAM rank0 size:0x100000000,
9285 22:53:53.325145 DRAM rank1 size=0x100000000
9286 22:53:53.329762 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9287 22:53:53.331932 CPU: 00 missing read_resources
9288 22:53:53.335245 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9289 22:53:53.341842 Root Device read_resources bus 0 link: 0 done
9290 22:53:53.341973 Done reading resources.
9291 22:53:53.348606 Show resources in subtree (Root Device)...After reading.
9292 22:53:53.351821 Root Device child on link 0 CPU_CLUSTER: 0
9293 22:53:53.354935 CPU_CLUSTER: 0 child on link 0 CPU: 00
9294 22:53:53.365568 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9295 22:53:53.365651 CPU: 00
9296 22:53:53.368435 Root Device assign_resources, bus 0 link: 0
9297 22:53:53.371860 CPU_CLUSTER: 0 missing set_resources
9298 22:53:53.375421 Root Device assign_resources, bus 0 link: 0 done
9299 22:53:53.378908 Done setting resources.
9300 22:53:53.385159 Show resources in subtree (Root Device)...After assigning values.
9301 22:53:53.388767 Root Device child on link 0 CPU_CLUSTER: 0
9302 22:53:53.392128 CPU_CLUSTER: 0 child on link 0 CPU: 00
9303 22:53:53.401887 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9304 22:53:53.401968 CPU: 00
9305 22:53:53.405060 Done allocating resources.
9306 22:53:53.408427 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9307 22:53:53.411837 Enabling resources...
9308 22:53:53.411918 done.
9309 22:53:53.418734 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9310 22:53:53.418815 Initializing devices...
9311 22:53:53.422273 Root Device init
9312 22:53:53.422353 init hardware done!
9313 22:53:53.425182 0x00000018: ctrlr->caps
9314 22:53:53.428315 52.000 MHz: ctrlr->f_max
9315 22:53:53.428403 0.400 MHz: ctrlr->f_min
9316 22:53:53.431571 0x40ff8080: ctrlr->voltages
9317 22:53:53.431658 sclk: 390625
9318 22:53:53.435394 Bus Width = 1
9319 22:53:53.435475 sclk: 390625
9320 22:53:53.435539 Bus Width = 1
9321 22:53:53.438531 Early init status = 3
9322 22:53:53.445055 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9323 22:53:53.448096 in-header: 03 fc 00 00 01 00 00 00
9324 22:53:53.448178 in-data: 00
9325 22:53:53.454994 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9326 22:53:53.458407 in-header: 03 fd 00 00 00 00 00 00
9327 22:53:53.461646 in-data:
9328 22:53:53.464880 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9329 22:53:53.469197 in-header: 03 fc 00 00 01 00 00 00
9330 22:53:53.472527 in-data: 00
9331 22:53:53.475674 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9332 22:53:53.481234 in-header: 03 fd 00 00 00 00 00 00
9333 22:53:53.485231 in-data:
9334 22:53:53.487735 [SSUSB] Setting up USB HOST controller...
9335 22:53:53.491334 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9336 22:53:53.495263 [SSUSB] phy power-on done.
9337 22:53:53.498512 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9338 22:53:53.504468 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9339 22:53:53.508291 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9340 22:53:53.514500 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9341 22:53:53.521793 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9342 22:53:53.527817 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9343 22:53:53.534474 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9344 22:53:53.541315 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9345 22:53:53.541387 SPM: binary array size = 0x9dc
9346 22:53:53.547915 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9347 22:53:53.554291 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9348 22:53:53.561512 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9349 22:53:53.564657 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9350 22:53:53.567828 configure_display: Starting display init
9351 22:53:53.604621 anx7625_power_on_init: Init interface.
9352 22:53:53.607867 anx7625_disable_pd_protocol: Disabled PD feature.
9353 22:53:53.611089 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9354 22:53:53.639215 anx7625_start_dp_work: Secure OCM version=00
9355 22:53:53.642732 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9356 22:53:53.657215 sp_tx_get_edid_block: EDID Block = 1
9357 22:53:53.759969 Extracted contents:
9358 22:53:53.763019 header: 00 ff ff ff ff ff ff 00
9359 22:53:53.766636 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9360 22:53:53.769665 version: 01 04
9361 22:53:53.772802 basic params: 95 1f 11 78 0a
9362 22:53:53.775984 chroma info: 76 90 94 55 54 90 27 21 50 54
9363 22:53:53.779497 established: 00 00 00
9364 22:53:53.786659 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9365 22:53:53.789334 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9366 22:53:53.796562 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9367 22:53:53.802937 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9368 22:53:53.809495 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9369 22:53:53.812913 extensions: 00
9370 22:53:53.812987 checksum: fb
9371 22:53:53.813049
9372 22:53:53.816258 Manufacturer: IVO Model 57d Serial Number 0
9373 22:53:53.819347 Made week 0 of 2020
9374 22:53:53.819416 EDID version: 1.4
9375 22:53:53.822613 Digital display
9376 22:53:53.826065 6 bits per primary color channel
9377 22:53:53.826134 DisplayPort interface
9378 22:53:53.829371 Maximum image size: 31 cm x 17 cm
9379 22:53:53.832817 Gamma: 220%
9380 22:53:53.832883 Check DPMS levels
9381 22:53:53.836170 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9382 22:53:53.839586 First detailed timing is preferred timing
9383 22:53:53.843046 Established timings supported:
9384 22:53:53.846274 Standard timings supported:
9385 22:53:53.846341 Detailed timings
9386 22:53:53.852979 Hex of detail: 383680a07038204018303c0035ae10000019
9387 22:53:53.856348 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9388 22:53:53.863066 0780 0798 07c8 0820 hborder 0
9389 22:53:53.866200 0438 043b 0447 0458 vborder 0
9390 22:53:53.866275 -hsync -vsync
9391 22:53:53.869380 Did detailed timing
9392 22:53:53.872482 Hex of detail: 000000000000000000000000000000000000
9393 22:53:53.875966 Manufacturer-specified data, tag 0
9394 22:53:53.882812 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9395 22:53:53.882893 ASCII string: InfoVision
9396 22:53:53.889465 Hex of detail: 000000fe00523134304e574635205248200a
9397 22:53:53.889547 ASCII string: R140NWF5 RH
9398 22:53:53.892672 Checksum
9399 22:53:53.892745 Checksum: 0xfb (valid)
9400 22:53:53.899145 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9401 22:53:53.899223 DSI data_rate: 832800000 bps
9402 22:53:53.907198 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9403 22:53:53.910457 anx7625_parse_edid: pixelclock(138800).
9404 22:53:53.913955 hactive(1920), hsync(48), hfp(24), hbp(88)
9405 22:53:53.917459 vactive(1080), vsync(12), vfp(3), vbp(17)
9406 22:53:53.920384 anx7625_dsi_config: config dsi.
9407 22:53:53.927347 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9408 22:53:53.942087 anx7625_dsi_config: success to config DSI
9409 22:53:53.944670 anx7625_dp_start: MIPI phy setup OK.
9410 22:53:53.948438 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9411 22:53:53.951470 mtk_ddp_mode_set invalid vrefresh 60
9412 22:53:53.954777 main_disp_path_setup
9413 22:53:53.954847 ovl_layer_smi_id_en
9414 22:53:53.958139 ovl_layer_smi_id_en
9415 22:53:53.958216 ccorr_config
9416 22:53:53.958277 aal_config
9417 22:53:53.961450 gamma_config
9418 22:53:53.961520 postmask_config
9419 22:53:53.965031 dither_config
9420 22:53:53.968336 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9421 22:53:53.974659 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9422 22:53:53.978081 Root Device init finished in 553 msecs
9423 22:53:53.978158 CPU_CLUSTER: 0 init
9424 22:53:53.988566 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9425 22:53:53.991563 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9426 22:53:53.994900 APU_MBOX 0x190000b0 = 0x10001
9427 22:53:53.998124 APU_MBOX 0x190001b0 = 0x10001
9428 22:53:54.001468 APU_MBOX 0x190005b0 = 0x10001
9429 22:53:54.004670 APU_MBOX 0x190006b0 = 0x10001
9430 22:53:54.008097 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9431 22:53:54.020435 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9432 22:53:54.032857 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9433 22:53:54.039926 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9434 22:53:54.051136 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9435 22:53:54.060838 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9436 22:53:54.063447 CPU_CLUSTER: 0 init finished in 81 msecs
9437 22:53:54.067256 Devices initialized
9438 22:53:54.070181 Show all devs... After init.
9439 22:53:54.070262 Root Device: enabled 1
9440 22:53:54.073537 CPU_CLUSTER: 0: enabled 1
9441 22:53:54.076812 CPU: 00: enabled 1
9442 22:53:54.080426 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9443 22:53:54.083526 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9444 22:53:54.087013 ELOG: NV offset 0x57f000 size 0x1000
9445 22:53:54.093266 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9446 22:53:54.100142 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9447 22:53:54.103428 ELOG: Event(17) added with size 13 at 2024-05-07 22:53:55 UTC
9448 22:53:54.110465 out: cmd=0x121: 03 db 21 01 00 00 00 00
9449 22:53:54.113285 in-header: 03 d8 00 00 2c 00 00 00
9450 22:53:54.126947 in-data: 87 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9451 22:53:54.130065 ELOG: Event(A1) added with size 10 at 2024-05-07 22:53:55 UTC
9452 22:53:54.136504 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9453 22:53:54.143196 ELOG: Event(A0) added with size 9 at 2024-05-07 22:53:55 UTC
9454 22:53:54.146659 elog_add_boot_reason: Logged dev mode boot
9455 22:53:54.153116 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9456 22:53:54.153199 Finalize devices...
9457 22:53:54.156451 Devices finalized
9458 22:53:54.160248 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9459 22:53:54.163107 Writing coreboot table at 0xffe64000
9460 22:53:54.170333 0. 000000000010a000-0000000000113fff: RAMSTAGE
9461 22:53:54.173468 1. 0000000040000000-00000000400fffff: RAM
9462 22:53:54.176566 2. 0000000040100000-000000004032afff: RAMSTAGE
9463 22:53:54.180037 3. 000000004032b000-00000000545fffff: RAM
9464 22:53:54.183467 4. 0000000054600000-000000005465ffff: BL31
9465 22:53:54.186622 5. 0000000054660000-00000000ffe63fff: RAM
9466 22:53:54.193425 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9467 22:53:54.196457 7. 0000000100000000-000000023fffffff: RAM
9468 22:53:54.199810 Passing 5 GPIOs to payload:
9469 22:53:54.203109 NAME | PORT | POLARITY | VALUE
9470 22:53:54.210395 EC in RW | 0x000000aa | low | undefined
9471 22:53:54.214318 EC interrupt | 0x00000005 | low | undefined
9472 22:53:54.216860 TPM interrupt | 0x000000ab | high | undefined
9473 22:53:54.223682 SD card detect | 0x00000011 | high | undefined
9474 22:53:54.226740 speaker enable | 0x00000093 | high | undefined
9475 22:53:54.230337 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9476 22:53:54.233371 in-header: 03 f9 00 00 02 00 00 00
9477 22:53:54.236414 in-data: 02 00
9478 22:53:54.239899 ADC[4]: Raw value=900221 ID=7
9479 22:53:54.239981 ADC[3]: Raw value=213336 ID=1
9480 22:53:54.243360 RAM Code: 0x71
9481 22:53:54.246620 ADC[6]: Raw value=74557 ID=0
9482 22:53:54.246701 ADC[5]: Raw value=212229 ID=1
9483 22:53:54.249755 SKU Code: 0x1
9484 22:53:54.256729 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ab9e
9485 22:53:54.256811 coreboot table: 964 bytes.
9486 22:53:54.260157 IMD ROOT 0. 0xfffff000 0x00001000
9487 22:53:54.263214 IMD SMALL 1. 0xffffe000 0x00001000
9488 22:53:54.266797 RO MCACHE 2. 0xffffc000 0x00001104
9489 22:53:54.270042 CONSOLE 3. 0xfff7c000 0x00080000
9490 22:53:54.273953 FMAP 4. 0xfff7b000 0x00000452
9491 22:53:54.276891 TIME STAMP 5. 0xfff7a000 0x00000910
9492 22:53:54.279848 VBOOT WORK 6. 0xfff66000 0x00014000
9493 22:53:54.283233 RAMOOPS 7. 0xffe66000 0x00100000
9494 22:53:54.286573 COREBOOT 8. 0xffe64000 0x00002000
9495 22:53:54.289953 IMD small region:
9496 22:53:54.293128 IMD ROOT 0. 0xffffec00 0x00000400
9497 22:53:54.296985 VPD 1. 0xffffeb80 0x0000006c
9498 22:53:54.300018 MMC STATUS 2. 0xffffeb60 0x00000004
9499 22:53:54.303419 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9500 22:53:54.306517 Probing TPM: done!
9501 22:53:54.310395 Connected to device vid:did:rid of 1ae0:0028:00
9502 22:53:54.320398 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9503 22:53:54.324426 Initialized TPM device CR50 revision 0
9504 22:53:54.328166 Checking cr50 for pending updates
9505 22:53:54.331920 Reading cr50 TPM mode
9506 22:53:54.340763 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9507 22:53:54.346441 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9508 22:53:54.386750 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9509 22:53:54.390245 Checking segment from ROM address 0x40100000
9510 22:53:54.393264 Checking segment from ROM address 0x4010001c
9511 22:53:54.400056 Loading segment from ROM address 0x40100000
9512 22:53:54.400130 code (compression=0)
9513 22:53:54.407100 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9514 22:53:54.416814 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9515 22:53:54.416895 it's not compressed!
9516 22:53:54.423409 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9517 22:53:54.426571 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9518 22:53:54.447378 Loading segment from ROM address 0x4010001c
9519 22:53:54.447452 Entry Point 0x80000000
9520 22:53:54.450214 Loaded segments
9521 22:53:54.453691 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9522 22:53:54.460888 Jumping to boot code at 0x80000000(0xffe64000)
9523 22:53:54.467472 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9524 22:53:54.473485 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9525 22:53:54.481545 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9526 22:53:54.484896 Checking segment from ROM address 0x40100000
9527 22:53:54.488235 Checking segment from ROM address 0x4010001c
9528 22:53:54.495160 Loading segment from ROM address 0x40100000
9529 22:53:54.495243 code (compression=1)
9530 22:53:54.501610 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9531 22:53:54.512032 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9532 22:53:54.512114 using LZMA
9533 22:53:54.519813 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9534 22:53:54.526334 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9535 22:53:54.529776 Loading segment from ROM address 0x4010001c
9536 22:53:54.529857 Entry Point 0x54601000
9537 22:53:54.533399 Loaded segments
9538 22:53:54.536354 NOTICE: MT8192 bl31_setup
9539 22:53:54.543270 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9540 22:53:54.546885 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9541 22:53:54.549984 WARNING: region 0:
9542 22:53:54.553943 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 22:53:54.554024 WARNING: region 1:
9544 22:53:54.560339 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9545 22:53:54.563484 WARNING: region 2:
9546 22:53:54.567175 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9547 22:53:54.570418 WARNING: region 3:
9548 22:53:54.574123 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9549 22:53:54.576977 WARNING: region 4:
9550 22:53:54.580142 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9551 22:53:54.584263 WARNING: region 5:
9552 22:53:54.587281 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 22:53:54.590536 WARNING: region 6:
9554 22:53:54.593938 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9555 22:53:54.594020 WARNING: region 7:
9556 22:53:54.600853 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9557 22:53:54.607067 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9558 22:53:54.610495 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9559 22:53:54.613803 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9560 22:53:54.617338 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9561 22:53:54.623906 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9562 22:53:54.627365 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9563 22:53:54.634341 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9564 22:53:54.637851 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9565 22:53:54.640890 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9566 22:53:54.647933 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9567 22:53:54.650914 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9568 22:53:54.654087 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9569 22:53:54.660875 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9570 22:53:54.664486 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9571 22:53:54.668105 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9572 22:53:54.674134 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9573 22:53:54.678010 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9574 22:53:54.684568 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9575 22:53:54.687690 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9576 22:53:54.691122 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9577 22:53:54.698146 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9578 22:53:54.701191 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9579 22:53:54.704659 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9580 22:53:54.711170 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9581 22:53:54.714821 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9582 22:53:54.721982 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9583 22:53:54.724521 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9584 22:53:54.727927 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9585 22:53:54.734854 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9586 22:53:54.738254 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9587 22:53:54.744811 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9588 22:53:54.748538 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9589 22:53:54.751853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9590 22:53:54.755307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9591 22:53:54.761655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9592 22:53:54.764854 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9593 22:53:54.768534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9594 22:53:54.771577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9595 22:53:54.778086 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9596 22:53:54.782097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9597 22:53:54.785202 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9598 22:53:54.788199 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9599 22:53:54.794834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9600 22:53:54.798250 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9601 22:53:54.801305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9602 22:53:54.804966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9603 22:53:54.811536 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9604 22:53:54.815807 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9605 22:53:54.818532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9606 22:53:54.824957 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9607 22:53:54.828539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9608 22:53:54.835291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9609 22:53:54.838334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9610 22:53:54.841899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9611 22:53:54.848550 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9612 22:53:54.851813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9613 22:53:54.858355 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9614 22:53:54.861971 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9615 22:53:54.864841 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9616 22:53:54.871889 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9617 22:53:54.875222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9618 22:53:54.882250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9619 22:53:54.885097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9620 22:53:54.891884 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9621 22:53:54.895328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9622 22:53:54.902114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9623 22:53:54.905638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9624 22:53:54.908782 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9625 22:53:54.915572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9626 22:53:54.918575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9627 22:53:54.925516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9628 22:53:54.928696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9629 22:53:54.931834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9630 22:53:54.939092 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9631 22:53:54.942049 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9632 22:53:54.949005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9633 22:53:54.952721 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9634 22:53:54.958965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9635 22:53:54.962480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9636 22:53:54.965831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9637 22:53:54.972083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9638 22:53:54.975419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9639 22:53:54.982436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9640 22:53:54.986358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9641 22:53:54.992212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9642 22:53:54.995863 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9643 22:53:54.999043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9644 22:53:55.006041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9645 22:53:55.009471 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9646 22:53:55.016178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9647 22:53:55.019263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9648 22:53:55.023055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9649 22:53:55.029683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9650 22:53:55.033067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9651 22:53:55.039496 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9652 22:53:55.043361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9653 22:53:55.046242 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9654 22:53:55.052814 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9655 22:53:55.056303 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9656 22:53:55.059722 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9657 22:53:55.062764 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9658 22:53:55.069439 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9659 22:53:55.072730 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9660 22:53:55.080093 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9661 22:53:55.083039 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9662 22:53:55.086509 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9663 22:53:55.092808 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9664 22:53:55.096073 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9665 22:53:55.102866 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9666 22:53:55.106407 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9667 22:53:55.109497 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9668 22:53:55.116454 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9669 22:53:55.119714 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9670 22:53:55.126622 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9671 22:53:55.130166 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9672 22:53:55.133452 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9673 22:53:55.136386 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9674 22:53:55.142991 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9675 22:53:55.147104 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9676 22:53:55.149934 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9677 22:53:55.156744 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9678 22:53:55.159761 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9679 22:53:55.163180 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9680 22:53:55.166567 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9681 22:53:55.173745 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9682 22:53:55.177812 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9683 22:53:55.180077 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9684 22:53:55.186716 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9685 22:53:55.190548 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9686 22:53:55.196800 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9687 22:53:55.200213 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9688 22:53:55.203484 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9689 22:53:55.210370 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9690 22:53:55.213980 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9691 22:53:55.216820 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9692 22:53:55.223789 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9693 22:53:55.227724 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9694 22:53:55.234236 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9695 22:53:55.237388 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9696 22:53:55.240495 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9697 22:53:55.247252 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9698 22:53:55.250634 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9699 22:53:55.254209 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9700 22:53:55.261054 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9701 22:53:55.264041 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9702 22:53:55.270554 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9703 22:53:55.274191 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9704 22:53:55.277604 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9705 22:53:55.284428 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9706 22:53:55.287511 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9707 22:53:55.290780 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9708 22:53:55.297461 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9709 22:53:55.301292 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9710 22:53:55.307677 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9711 22:53:55.310963 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9712 22:53:55.314246 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9713 22:53:55.321099 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9714 22:53:55.324261 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9715 22:53:55.327613 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9716 22:53:55.334406 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9717 22:53:55.337627 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9718 22:53:55.344078 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9719 22:53:55.347725 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9720 22:53:55.351344 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9721 22:53:55.358083 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9722 22:53:55.361058 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9723 22:53:55.367728 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9724 22:53:55.371000 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9725 22:53:55.374548 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9726 22:53:55.380718 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9727 22:53:55.384297 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9728 22:53:55.390830 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9729 22:53:55.394188 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9730 22:53:55.397181 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9731 22:53:55.403811 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9732 22:53:55.407597 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9733 22:53:55.413795 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9734 22:53:55.417179 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9735 22:53:55.420834 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9736 22:53:55.427498 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9737 22:53:55.430627 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9738 22:53:55.433864 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9739 22:53:55.440248 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9740 22:53:55.444022 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9741 22:53:55.450582 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9742 22:53:55.453653 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9743 22:53:55.456877 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9744 22:53:55.463772 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9745 22:53:55.467247 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9746 22:53:55.473898 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9747 22:53:55.477415 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9748 22:53:55.480358 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9749 22:53:55.487215 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9750 22:53:55.490413 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9751 22:53:55.497009 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9752 22:53:55.500542 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9753 22:53:55.507172 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9754 22:53:55.510222 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9755 22:53:55.513629 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9756 22:53:55.520782 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9757 22:53:55.524382 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9758 22:53:55.530884 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9759 22:53:55.533853 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9760 22:53:55.537204 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9761 22:53:55.543797 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9762 22:53:55.547338 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9763 22:53:55.553943 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9764 22:53:55.557123 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9765 22:53:55.560488 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9766 22:53:55.567125 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9767 22:53:55.570475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9768 22:53:55.577301 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9769 22:53:55.580494 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9770 22:53:55.583909 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9771 22:53:55.590411 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9772 22:53:55.594194 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9773 22:53:55.600473 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9774 22:53:55.604027 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9775 22:53:55.610615 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9776 22:53:55.613802 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9777 22:53:55.617265 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9778 22:53:55.623731 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9779 22:53:55.627744 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9780 22:53:55.634037 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9781 22:53:55.637048 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9782 22:53:55.640466 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9783 22:53:55.647331 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9784 22:53:55.650887 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9785 22:53:55.657181 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9786 22:53:55.661033 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9787 22:53:55.664654 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9788 22:53:55.667387 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9789 22:53:55.670679 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9790 22:53:55.677397 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9791 22:53:55.680798 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9792 22:53:55.684145 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9793 22:53:55.690955 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9794 22:53:55.693785 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9795 22:53:55.697355 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9796 22:53:55.703988 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9797 22:53:55.707659 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9798 22:53:55.714137 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9799 22:53:55.717593 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9800 22:53:55.720945 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9801 22:53:55.727174 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9802 22:53:55.730761 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9803 22:53:55.734354 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9804 22:53:55.741512 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9805 22:53:55.744068 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9806 22:53:55.747182 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9807 22:53:55.754799 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9808 22:53:55.757420 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9809 22:53:55.764184 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9810 22:53:55.767190 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9811 22:53:55.770860 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9812 22:53:55.777768 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9813 22:53:55.780707 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9814 22:53:55.784003 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9815 22:53:55.790709 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9816 22:53:55.794365 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9817 22:53:55.797326 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9818 22:53:55.804135 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9819 22:53:55.807225 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9820 22:53:55.810773 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9821 22:53:55.817280 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9822 22:53:55.820945 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9823 22:53:55.827767 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9824 22:53:55.830543 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9825 22:53:55.834312 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9826 22:53:55.837092 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9827 22:53:55.844011 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9828 22:53:55.847433 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9829 22:53:55.851152 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9830 22:53:55.854652 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9831 22:53:55.857360 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9832 22:53:55.864467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9833 22:53:55.867547 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9834 22:53:55.870917 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9835 22:53:55.874269 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9836 22:53:55.880722 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9837 22:53:55.884972 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9838 22:53:55.887581 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9839 22:53:55.895092 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9840 22:53:55.898033 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9841 22:53:55.904516 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9842 22:53:55.907949 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9843 22:53:55.911040 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9844 22:53:55.918228 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9845 22:53:55.921130 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9846 22:53:55.924618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9847 22:53:55.931097 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9848 22:53:55.934487 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9849 22:53:55.941347 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9850 22:53:55.944615 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9851 22:53:55.951439 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9852 22:53:55.954140 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9853 22:53:55.957613 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9854 22:53:55.964638 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9855 22:53:55.967633 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9856 22:53:55.974635 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9857 22:53:55.977699 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9858 22:53:55.981778 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9859 22:53:55.987503 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9860 22:53:55.991115 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9861 22:53:55.997823 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9862 22:53:56.001409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9863 22:53:56.004865 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9864 22:53:56.011507 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9865 22:53:56.014535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9866 22:53:56.021011 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9867 22:53:56.024353 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9868 22:53:56.027728 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9869 22:53:56.034533 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9870 22:53:56.038104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9871 22:53:56.044388 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9872 22:53:56.047815 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9873 22:53:56.051274 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9874 22:53:56.058141 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9875 22:53:56.061494 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9876 22:53:56.067858 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9877 22:53:56.071108 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9878 22:53:56.074689 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9879 22:53:56.081147 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9880 22:53:56.084790 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9881 22:53:56.091662 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9882 22:53:56.095144 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9883 22:53:56.097946 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9884 22:53:56.104717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9885 22:53:56.107969 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9886 22:53:56.111752 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9887 22:53:56.118495 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9888 22:53:56.121705 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9889 22:53:56.128315 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9890 22:53:56.132349 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9891 22:53:56.138142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9892 22:53:56.142076 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9893 22:53:56.145023 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9894 22:53:56.152086 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9895 22:53:56.155177 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9896 22:53:56.158183 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9897 22:53:56.165385 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9898 22:53:56.168295 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9899 22:53:56.175377 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9900 22:53:56.178836 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9901 22:53:56.185233 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9902 22:53:56.188494 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9903 22:53:56.191638 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9904 22:53:56.198474 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9905 22:53:56.202081 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9906 22:53:56.205489 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9907 22:53:56.212065 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9908 22:53:56.215197 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9909 22:53:56.221665 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9910 22:53:56.225038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9911 22:53:56.228479 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9912 22:53:56.235052 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9913 22:53:56.238583 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9914 22:53:56.245514 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9915 22:53:56.248416 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9916 22:53:56.255455 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9917 22:53:56.258698 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9918 22:53:56.261645 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9919 22:53:56.268626 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9920 22:53:56.271790 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9921 22:53:56.278622 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9922 22:53:56.282317 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9923 22:53:56.288602 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9924 22:53:56.291834 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9925 22:53:56.299000 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9926 22:53:56.302181 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9927 22:53:56.305318 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9928 22:53:56.312132 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9929 22:53:56.314857 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9930 22:53:56.321406 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9931 22:53:56.324801 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9932 22:53:56.332343 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9933 22:53:56.335020 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9934 22:53:56.338208 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9935 22:53:56.345121 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9936 22:53:56.348085 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9937 22:53:56.355256 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9938 22:53:56.358843 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9939 22:53:56.365043 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9940 22:53:56.369047 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9941 22:53:56.372057 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9942 22:53:56.378408 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9943 22:53:56.381941 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9944 22:53:56.388427 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9945 22:53:56.391850 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9946 22:53:56.398347 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9947 22:53:56.401501 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9948 22:53:56.404856 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9949 22:53:56.411861 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9950 22:53:56.414909 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9951 22:53:56.421691 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9952 22:53:56.425223 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9953 22:53:56.429132 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9954 22:53:56.435154 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9955 22:53:56.438266 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9956 22:53:56.445196 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9957 22:53:56.448450 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9958 22:53:56.454996 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9959 22:53:56.458630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9960 22:53:56.461889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9961 22:53:56.468216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9962 22:53:56.471990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9963 22:53:56.478536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9964 22:53:56.481969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9965 22:53:56.488745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9966 22:53:56.492051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9967 22:53:56.498307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9968 22:53:56.501917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9969 22:53:56.508471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9970 22:53:56.511999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9971 22:53:56.518719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9972 22:53:56.521956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9973 22:53:56.525242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9974 22:53:56.532068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9975 22:53:56.535658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9976 22:53:56.542257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9977 22:53:56.545176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9978 22:53:56.551833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9979 22:53:56.555020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9980 22:53:56.562072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9981 22:53:56.565598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9982 22:53:56.572237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9983 22:53:56.575106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9984 22:53:56.582121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9985 22:53:56.585422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9986 22:53:56.592130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9987 22:53:56.595444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9988 22:53:56.602149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9989 22:53:56.605364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9990 22:53:56.612085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9991 22:53:56.615447 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9992 22:53:56.619049 INFO: [APUAPC] vio 0
9993 22:53:56.622463 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9994 22:53:56.625599 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9995 22:53:56.628670 INFO: [APUAPC] D0_APC_0: 0x400510
9996 22:53:56.632056 INFO: [APUAPC] D0_APC_1: 0x0
9997 22:53:56.635677 INFO: [APUAPC] D0_APC_2: 0x1540
9998 22:53:56.638804 INFO: [APUAPC] D0_APC_3: 0x0
9999 22:53:56.642134 INFO: [APUAPC] D1_APC_0: 0xffffffff
10000 22:53:56.645329 INFO: [APUAPC] D1_APC_1: 0xffffffff
10001 22:53:56.648785 INFO: [APUAPC] D1_APC_2: 0x3fffff
10002 22:53:56.651769 INFO: [APUAPC] D1_APC_3: 0x0
10003 22:53:56.655322 INFO: [APUAPC] D2_APC_0: 0xffffffff
10004 22:53:56.658517 INFO: [APUAPC] D2_APC_1: 0xffffffff
10005 22:53:56.662060 INFO: [APUAPC] D2_APC_2: 0x3fffff
10006 22:53:56.665707 INFO: [APUAPC] D2_APC_3: 0x0
10007 22:53:56.668848 INFO: [APUAPC] D3_APC_0: 0xffffffff
10008 22:53:56.672474 INFO: [APUAPC] D3_APC_1: 0xffffffff
10009 22:53:56.675674 INFO: [APUAPC] D3_APC_2: 0x3fffff
10010 22:53:56.678818 INFO: [APUAPC] D3_APC_3: 0x0
10011 22:53:56.682023 INFO: [APUAPC] D4_APC_0: 0xffffffff
10012 22:53:56.685196 INFO: [APUAPC] D4_APC_1: 0xffffffff
10013 22:53:56.688891 INFO: [APUAPC] D4_APC_2: 0x3fffff
10014 22:53:56.691791 INFO: [APUAPC] D4_APC_3: 0x0
10015 22:53:56.694860 INFO: [APUAPC] D5_APC_0: 0xffffffff
10016 22:53:56.698591 INFO: [APUAPC] D5_APC_1: 0xffffffff
10017 22:53:56.701793 INFO: [APUAPC] D5_APC_2: 0x3fffff
10018 22:53:56.705327 INFO: [APUAPC] D5_APC_3: 0x0
10019 22:53:56.708675 INFO: [APUAPC] D6_APC_0: 0xffffffff
10020 22:53:56.711737 INFO: [APUAPC] D6_APC_1: 0xffffffff
10021 22:53:56.714925 INFO: [APUAPC] D6_APC_2: 0x3fffff
10022 22:53:56.718371 INFO: [APUAPC] D6_APC_3: 0x0
10023 22:53:56.721645 INFO: [APUAPC] D7_APC_0: 0xffffffff
10024 22:53:56.725307 INFO: [APUAPC] D7_APC_1: 0xffffffff
10025 22:53:56.728655 INFO: [APUAPC] D7_APC_2: 0x3fffff
10026 22:53:56.731417 INFO: [APUAPC] D7_APC_3: 0x0
10027 22:53:56.735115 INFO: [APUAPC] D8_APC_0: 0xffffffff
10028 22:53:56.738676 INFO: [APUAPC] D8_APC_1: 0xffffffff
10029 22:53:56.741417 INFO: [APUAPC] D8_APC_2: 0x3fffff
10030 22:53:56.741496 INFO: [APUAPC] D8_APC_3: 0x0
10031 22:53:56.745226 INFO: [APUAPC] D9_APC_0: 0xffffffff
10032 22:53:56.751444 INFO: [APUAPC] D9_APC_1: 0xffffffff
10033 22:53:56.755224 INFO: [APUAPC] D9_APC_2: 0x3fffff
10034 22:53:56.755307 INFO: [APUAPC] D9_APC_3: 0x0
10035 22:53:56.758541 INFO: [APUAPC] D10_APC_0: 0xffffffff
10036 22:53:56.761659 INFO: [APUAPC] D10_APC_1: 0xffffffff
10037 22:53:56.764877 INFO: [APUAPC] D10_APC_2: 0x3fffff
10038 22:53:56.768743 INFO: [APUAPC] D10_APC_3: 0x0
10039 22:53:56.771911 INFO: [APUAPC] D11_APC_0: 0xffffffff
10040 22:53:56.778408 INFO: [APUAPC] D11_APC_1: 0xffffffff
10041 22:53:56.781409 INFO: [APUAPC] D11_APC_2: 0x3fffff
10042 22:53:56.781489 INFO: [APUAPC] D11_APC_3: 0x0
10043 22:53:56.784738 INFO: [APUAPC] D12_APC_0: 0xffffffff
10044 22:53:56.791509 INFO: [APUAPC] D12_APC_1: 0xffffffff
10045 22:53:56.794661 INFO: [APUAPC] D12_APC_2: 0x3fffff
10046 22:53:56.794743 INFO: [APUAPC] D12_APC_3: 0x0
10047 22:53:56.798383 INFO: [APUAPC] D13_APC_0: 0xffffffff
10048 22:53:56.804954 INFO: [APUAPC] D13_APC_1: 0xffffffff
10049 22:53:56.808354 INFO: [APUAPC] D13_APC_2: 0x3fffff
10050 22:53:56.808437 INFO: [APUAPC] D13_APC_3: 0x0
10051 22:53:56.811895 INFO: [APUAPC] D14_APC_0: 0xffffffff
10052 22:53:56.818151 INFO: [APUAPC] D14_APC_1: 0xffffffff
10053 22:53:56.821583 INFO: [APUAPC] D14_APC_2: 0x3fffff
10054 22:53:56.821666 INFO: [APUAPC] D14_APC_3: 0x0
10055 22:53:56.824978 INFO: [APUAPC] D15_APC_0: 0xffffffff
10056 22:53:56.831509 INFO: [APUAPC] D15_APC_1: 0xffffffff
10057 22:53:56.834752 INFO: [APUAPC] D15_APC_2: 0x3fffff
10058 22:53:56.834835 INFO: [APUAPC] D15_APC_3: 0x0
10059 22:53:56.838559 INFO: [APUAPC] APC_CON: 0x4
10060 22:53:56.841800 INFO: [NOCDAPC] D0_APC_0: 0x0
10061 22:53:56.845244 INFO: [NOCDAPC] D0_APC_1: 0x0
10062 22:53:56.848096 INFO: [NOCDAPC] D1_APC_0: 0x0
10063 22:53:56.851558 INFO: [NOCDAPC] D1_APC_1: 0xfff
10064 22:53:56.854841 INFO: [NOCDAPC] D2_APC_0: 0x0
10065 22:53:56.858340 INFO: [NOCDAPC] D2_APC_1: 0xfff
10066 22:53:56.858422 INFO: [NOCDAPC] D3_APC_0: 0x0
10067 22:53:56.861418 INFO: [NOCDAPC] D3_APC_1: 0xfff
10068 22:53:56.864865 INFO: [NOCDAPC] D4_APC_0: 0x0
10069 22:53:56.868643 INFO: [NOCDAPC] D4_APC_1: 0xfff
10070 22:53:56.872209 INFO: [NOCDAPC] D5_APC_0: 0x0
10071 22:53:56.875261 INFO: [NOCDAPC] D5_APC_1: 0xfff
10072 22:53:56.878299 INFO: [NOCDAPC] D6_APC_0: 0x0
10073 22:53:56.882261 INFO: [NOCDAPC] D6_APC_1: 0xfff
10074 22:53:56.885439 INFO: [NOCDAPC] D7_APC_0: 0x0
10075 22:53:56.888168 INFO: [NOCDAPC] D7_APC_1: 0xfff
10076 22:53:56.891580 INFO: [NOCDAPC] D8_APC_0: 0x0
10077 22:53:56.891663 INFO: [NOCDAPC] D8_APC_1: 0xfff
10078 22:53:56.895093 INFO: [NOCDAPC] D9_APC_0: 0x0
10079 22:53:56.898545 INFO: [NOCDAPC] D9_APC_1: 0xfff
10080 22:53:56.902233 INFO: [NOCDAPC] D10_APC_0: 0x0
10081 22:53:56.904934 INFO: [NOCDAPC] D10_APC_1: 0xfff
10082 22:53:56.908532 INFO: [NOCDAPC] D11_APC_0: 0x0
10083 22:53:56.912004 INFO: [NOCDAPC] D11_APC_1: 0xfff
10084 22:53:56.914957 INFO: [NOCDAPC] D12_APC_0: 0x0
10085 22:53:56.919147 INFO: [NOCDAPC] D12_APC_1: 0xfff
10086 22:53:56.922133 INFO: [NOCDAPC] D13_APC_0: 0x0
10087 22:53:56.925216 INFO: [NOCDAPC] D13_APC_1: 0xfff
10088 22:53:56.928776 INFO: [NOCDAPC] D14_APC_0: 0x0
10089 22:53:56.932114 INFO: [NOCDAPC] D14_APC_1: 0xfff
10090 22:53:56.932197 INFO: [NOCDAPC] D15_APC_0: 0x0
10091 22:53:56.935357 INFO: [NOCDAPC] D15_APC_1: 0xfff
10092 22:53:56.939013 INFO: [NOCDAPC] APC_CON: 0x4
10093 22:53:56.941681 INFO: [APUAPC] set_apusys_apc done
10094 22:53:56.945272 INFO: [DEVAPC] devapc_init done
10095 22:53:56.949115 INFO: GICv3 without legacy support detected.
10096 22:53:56.955721 INFO: ARM GICv3 driver initialized in EL3
10097 22:53:56.958621 INFO: Maximum SPI INTID supported: 639
10098 22:53:56.961931 INFO: BL31: Initializing runtime services
10099 22:53:56.968488 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10100 22:53:56.968570 INFO: SPM: enable CPC mode
10101 22:53:56.975569 INFO: mcdi ready for mcusys-off-idle and system suspend
10102 22:53:56.979009 INFO: BL31: Preparing for EL3 exit to normal world
10103 22:53:56.985182 INFO: Entry point address = 0x80000000
10104 22:53:56.985273 INFO: SPSR = 0x8
10105 22:53:56.991657
10106 22:53:56.991739
10107 22:53:56.991803
10108 22:53:56.994799 Starting depthcharge on Spherion...
10109 22:53:56.994882
10110 22:53:56.994947 Wipe memory regions:
10111 22:53:56.995007
10112 22:53:56.995653 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10113 22:53:56.995755 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10114 22:53:56.995835 Setting prompt string to ['asurada:']
10115 22:53:56.995919 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10116 22:53:56.998181 [0x00000040000000, 0x00000054600000)
10117 22:53:57.120137
10118 22:53:57.120247 [0x00000054660000, 0x00000080000000)
10119 22:53:57.380790
10120 22:53:57.380923 [0x000000821a7280, 0x000000ffe64000)
10121 22:53:58.125638
10122 22:53:58.125788 [0x00000100000000, 0x00000240000000)
10123 22:54:00.016151
10124 22:54:00.019574 Initializing XHCI USB controller at 0x11200000.
10125 22:54:01.058825
10126 22:54:01.061887 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10127 22:54:01.061978
10128 22:54:01.062044
10129 22:54:01.062106
10130 22:54:01.062391 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10132 22:54:01.162755 asurada: tftpboot 192.168.201.1 13683717/tftp-deploy-2iu6kz9l/kernel/image.itb 13683717/tftp-deploy-2iu6kz9l/kernel/cmdline
10133 22:54:01.162914 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10134 22:54:01.163018 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10135 22:54:01.166811 tftpboot 192.168.201.1 13683717/tftp-deploy-2iu6kz9l/kernel/image.ittp-deploy-2iu6kz9l/kernel/cmdline
10136 22:54:01.166896
10137 22:54:01.166962 Waiting for link
10138 22:54:01.327363
10139 22:54:01.327496 R8152: Initializing
10140 22:54:01.327562
10141 22:54:01.330898 Version 6 (ocp_data = 5c30)
10142 22:54:01.330982
10143 22:54:01.334457 R8152: Done initializing
10144 22:54:01.334601
10145 22:54:01.334701 Adding net device
10146 22:54:03.310219
10147 22:54:03.310399 done.
10148 22:54:03.310493
10149 22:54:03.310584 MAC: 00:24:32:30:78:52
10150 22:54:03.310649
10151 22:54:03.314137 Sending DHCP discover... done.
10152 22:54:03.314221
10153 22:54:13.029759 Waiting for reply... R8152: Bulk read error 0xffffffbf
10154 22:54:13.030589
10155 22:54:13.032798 Receive failed.
10156 22:54:13.033503
10157 22:54:13.034196 done.
10158 22:54:13.034644
10159 22:54:13.036485 Sending DHCP request... done.
10160 22:54:13.036951
10161 22:54:13.039580 Waiting for reply... done.
10162 22:54:13.040049
10163 22:54:13.042833 My ip is 192.168.201.14
10164 22:54:13.043302
10165 22:54:13.045951 The DHCP server ip is 192.168.201.1
10166 22:54:13.046421
10167 22:54:13.050108 TFTP server IP predefined by user: 192.168.201.1
10168 22:54:13.050632
10169 22:54:13.056678 Bootfile predefined by user: 13683717/tftp-deploy-2iu6kz9l/kernel/image.itb
10170 22:54:13.057287
10171 22:54:13.059353 Sending tftp read request... done.
10172 22:54:13.059821
10173 22:54:13.066779 Waiting for the transfer...
10174 22:54:13.067356
10175 22:54:13.768382 00000000 ################################################################
10176 22:54:13.768922
10177 22:54:14.481010 00080000 ################################################################
10178 22:54:14.481546
10179 22:54:15.193994 00100000 ################################################################
10180 22:54:15.194519
10181 22:54:15.907827 00180000 ################################################################
10182 22:54:15.908379
10183 22:54:16.630588 00200000 ################################################################
10184 22:54:16.631085
10185 22:54:17.330123 00280000 ################################################################
10186 22:54:17.330652
10187 22:54:18.031364 00300000 ################################################################
10188 22:54:18.031888
10189 22:54:18.744896 00380000 ################################################################
10190 22:54:18.745465
10191 22:54:19.450122 00400000 ################################################################
10192 22:54:19.450621
10193 22:54:20.166845 00480000 ################################################################
10194 22:54:20.167368
10195 22:54:20.880991 00500000 ################################################################
10196 22:54:20.881675
10197 22:54:21.615839 00580000 ################################################################
10198 22:54:21.616373
10199 22:54:22.328747 00600000 ################################################################
10200 22:54:22.329315
10201 22:54:23.046624 00680000 ################################################################
10202 22:54:23.047341
10203 22:54:23.769171 00700000 ################################################################
10204 22:54:23.769727
10205 22:54:24.477301 00780000 ################################################################
10206 22:54:24.477836
10207 22:54:25.199633 00800000 ################################################################
10208 22:54:25.200199
10209 22:54:25.930576 00880000 ################################################################
10210 22:54:25.931203
10211 22:54:26.658163 00900000 ################################################################
10212 22:54:26.658704
10213 22:54:27.395109 00980000 ################################################################
10214 22:54:27.395633
10215 22:54:28.119574 00a00000 ################################################################
10216 22:54:28.120096
10217 22:54:28.851743 00a80000 ################################################################
10218 22:54:28.852257
10219 22:54:29.596666 00b00000 ################################################################
10220 22:54:29.597254
10221 22:54:30.288881 00b80000 ################################################################
10222 22:54:30.289443
10223 22:54:31.012565 00c00000 ################################################################
10224 22:54:31.013087
10225 22:54:31.728322 00c80000 ################################################################
10226 22:54:31.728852
10227 22:54:32.449159 00d00000 ################################################################
10228 22:54:32.449709
10229 22:54:33.185048 00d80000 ################################################################
10230 22:54:33.185651
10231 22:54:33.917665 00e00000 ################################################################
10232 22:54:33.918194
10233 22:54:34.645160 00e80000 ################################################################
10234 22:54:34.645723
10235 22:54:35.355179 00f00000 ################################################################
10236 22:54:35.355730
10237 22:54:36.062244 00f80000 ################################################################
10238 22:54:36.062761
10239 22:54:36.783731 01000000 ################################################################
10240 22:54:36.784250
10241 22:54:37.493552 01080000 ################################################################
10242 22:54:37.494080
10243 22:54:38.219747 01100000 ################################################################
10244 22:54:38.220266
10245 22:54:38.934236 01180000 ################################################################
10246 22:54:38.934875
10247 22:54:39.664183 01200000 ################################################################
10248 22:54:39.664724
10249 22:54:40.388540 01280000 ################################################################
10250 22:54:40.389060
10251 22:54:41.102095 01300000 ################################################################
10252 22:54:41.102627
10253 22:54:41.816215 01380000 ################################################################
10254 22:54:41.816731
10255 22:54:42.549142 01400000 ################################################################
10256 22:54:42.549694
10257 22:54:43.262158 01480000 ################################################################
10258 22:54:43.262834
10259 22:54:43.993114 01500000 ################################################################
10260 22:54:43.993666
10261 22:54:44.719715 01580000 ################################################################
10262 22:54:44.720387
10263 22:54:45.440798 01600000 ################################################################
10264 22:54:45.441474
10265 22:54:46.162223 01680000 ################################################################
10266 22:54:46.162770
10267 22:54:46.888973 01700000 ################################################################
10268 22:54:46.889534
10269 22:54:47.627872 01780000 ################################################################
10270 22:54:47.628416
10271 22:54:48.349191 01800000 ################################################################
10272 22:54:48.349747
10273 22:54:49.069560 01880000 ################################################################
10274 22:54:49.070100
10275 22:54:49.788386 01900000 ################################################################
10276 22:54:49.788927
10277 22:54:50.495004 01980000 ################################################################
10278 22:54:50.495540
10279 22:54:51.223948 01a00000 ################################################################
10280 22:54:51.224460
10282 22:58:21.996888 end: 2.2.4 bootloader-commands (duration 00:04:25) [common]
10284 22:58:21.997909 depthcharge-retry failed: 1 of 1 attempts. 'bootloader-commands timed out after 265 seconds'
10286 22:58:21.998702 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
10289 22:58:22.000062 end: 2 depthcharge-action (duration 00:05:00) [common]
10291 22:58:22.001192 Cleaning after the job
10292 22:58:22.001676 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/ramdisk
10293 22:58:22.010585 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/kernel
10294 22:58:22.040798 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/dtb
10295 22:58:22.041128 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/nfsrootfs
10296 22:58:22.108252 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683717/tftp-deploy-2iu6kz9l/modules
10297 22:58:22.113824 start: 4.1 power-off (timeout 00:00:30) [common]
10298 22:58:22.114006 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
10299 22:58:22.191388 >> Command sent successfully.
10300 22:58:22.195079 Returned 0 in 0 seconds
10301 22:58:22.295937 end: 4.1 power-off (duration 00:00:00) [common]
10303 22:58:22.297377 start: 4.2 read-feedback (timeout 00:10:00) [common]
10304 22:58:22.298559 Listened to connection for namespace 'common' for up to 1s
10305 22:58:23.299339 Finalising connection for namespace 'common'
10306 22:58:23.300194 Disconnecting from shell: Finalise
10307 22:58:23.300669 01a80000 ################
10308 22:58:23.401654 end: 4.2 read-feedback (duration 00:00:01) [common]
10309 22:58:23.402229 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683717
10310 22:58:23.970300 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683717
10311 22:58:23.970496 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.