Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
1 22:48:42.920484 lava-dispatcher, installed at version: 2024.01
2 22:48:42.920692 start: 0 validate
3 22:48:42.920821 Start time: 2024-05-07 22:48:42.920813+00:00 (UTC)
4 22:48:42.920948 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:48:42.921081 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:48:43.181458 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:48:43.181632 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:48:43.440453 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:48:43.441149 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:49:04.689979 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:49:04.690826 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:49:05.202395 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:49:05.203185 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:49:05.473580 validate duration: 22.55
16 22:49:05.474797 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:49:05.475327 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:49:05.475805 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:49:05.476414 Not decompressing ramdisk as can be used compressed.
20 22:49:05.476878 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:49:05.477250 saving as /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/ramdisk/initrd.cpio.gz
22 22:49:05.477747 total size: 5628169 (5 MB)
23 22:49:08.223231 progress 0 % (0 MB)
24 22:49:08.232369 progress 5 % (0 MB)
25 22:49:08.240390 progress 10 % (0 MB)
26 22:49:08.247791 progress 15 % (0 MB)
27 22:49:08.253851 progress 20 % (1 MB)
28 22:49:08.257860 progress 25 % (1 MB)
29 22:49:08.261608 progress 30 % (1 MB)
30 22:49:08.264870 progress 35 % (1 MB)
31 22:49:08.267406 progress 40 % (2 MB)
32 22:49:08.270133 progress 45 % (2 MB)
33 22:49:08.272272 progress 50 % (2 MB)
34 22:49:08.274672 progress 55 % (2 MB)
35 22:49:08.276797 progress 60 % (3 MB)
36 22:49:08.278746 progress 65 % (3 MB)
37 22:49:08.280710 progress 70 % (3 MB)
38 22:49:08.282401 progress 75 % (4 MB)
39 22:49:08.284273 progress 80 % (4 MB)
40 22:49:08.285812 progress 85 % (4 MB)
41 22:49:08.287511 progress 90 % (4 MB)
42 22:49:08.289199 progress 95 % (5 MB)
43 22:49:08.290638 progress 100 % (5 MB)
44 22:49:08.290854 5 MB downloaded in 2.81 s (1.91 MB/s)
45 22:49:08.291012 end: 1.1.1 http-download (duration 00:00:03) [common]
47 22:49:08.291258 end: 1.1 download-retry (duration 00:00:03) [common]
48 22:49:08.291346 start: 1.2 download-retry (timeout 00:09:57) [common]
49 22:49:08.291430 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 22:49:08.291565 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:49:08.291635 saving as /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/kernel/Image
52 22:49:08.291700 total size: 54682112 (52 MB)
53 22:49:08.291765 No compression specified
54 22:49:08.292868 progress 0 % (0 MB)
55 22:49:08.306849 progress 5 % (2 MB)
56 22:49:08.320500 progress 10 % (5 MB)
57 22:49:08.334321 progress 15 % (7 MB)
58 22:49:08.347949 progress 20 % (10 MB)
59 22:49:08.361721 progress 25 % (13 MB)
60 22:49:08.375341 progress 30 % (15 MB)
61 22:49:08.389363 progress 35 % (18 MB)
62 22:49:08.403216 progress 40 % (20 MB)
63 22:49:08.416819 progress 45 % (23 MB)
64 22:49:08.430641 progress 50 % (26 MB)
65 22:49:08.444117 progress 55 % (28 MB)
66 22:49:08.457818 progress 60 % (31 MB)
67 22:49:08.471396 progress 65 % (33 MB)
68 22:49:08.485107 progress 70 % (36 MB)
69 22:49:08.498796 progress 75 % (39 MB)
70 22:49:08.512626 progress 80 % (41 MB)
71 22:49:08.526222 progress 85 % (44 MB)
72 22:49:08.539607 progress 90 % (46 MB)
73 22:49:08.553320 progress 95 % (49 MB)
74 22:49:08.566572 progress 100 % (52 MB)
75 22:49:08.566791 52 MB downloaded in 0.28 s (189.57 MB/s)
76 22:49:08.566941 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:49:08.567171 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:49:08.567256 start: 1.3 download-retry (timeout 00:09:57) [common]
80 22:49:08.567341 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 22:49:08.567475 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:49:08.567543 saving as /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/dtb/mt8192-asurada-spherion-r0.dtb
83 22:49:08.567604 total size: 47258 (0 MB)
84 22:49:08.567663 No compression specified
85 22:49:08.568750 progress 69 % (0 MB)
86 22:49:08.569030 progress 100 % (0 MB)
87 22:49:08.569181 0 MB downloaded in 0.00 s (28.62 MB/s)
88 22:49:08.569343 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:49:08.569557 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:49:08.569639 start: 1.4 download-retry (timeout 00:09:57) [common]
92 22:49:08.569719 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 22:49:08.569829 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:49:08.569895 saving as /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/nfsrootfs/full.rootfs.tar
95 22:49:08.569955 total size: 120894716 (115 MB)
96 22:49:08.570015 Using unxz to decompress xz
97 22:49:08.577408 progress 0 % (0 MB)
98 22:49:08.925074 progress 5 % (5 MB)
99 22:49:09.278270 progress 10 % (11 MB)
100 22:49:09.624758 progress 15 % (17 MB)
101 22:49:09.952518 progress 20 % (23 MB)
102 22:49:10.242237 progress 25 % (28 MB)
103 22:49:10.594688 progress 30 % (34 MB)
104 22:49:10.928907 progress 35 % (40 MB)
105 22:49:11.094405 progress 40 % (46 MB)
106 22:49:11.271871 progress 45 % (51 MB)
107 22:49:11.576802 progress 50 % (57 MB)
108 22:49:11.946628 progress 55 % (63 MB)
109 22:49:12.286283 progress 60 % (69 MB)
110 22:49:12.622655 progress 65 % (74 MB)
111 22:49:12.963257 progress 70 % (80 MB)
112 22:49:13.323391 progress 75 % (86 MB)
113 22:49:13.665360 progress 80 % (92 MB)
114 22:49:14.004646 progress 85 % (98 MB)
115 22:49:14.361435 progress 90 % (103 MB)
116 22:49:14.691617 progress 95 % (109 MB)
117 22:49:15.048576 progress 100 % (115 MB)
118 22:49:15.053993 115 MB downloaded in 6.48 s (17.78 MB/s)
119 22:49:15.054280 end: 1.4.1 http-download (duration 00:00:06) [common]
121 22:49:15.054558 end: 1.4 download-retry (duration 00:00:06) [common]
122 22:49:15.054649 start: 1.5 download-retry (timeout 00:09:50) [common]
123 22:49:15.054737 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 22:49:15.054887 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:49:15.054956 saving as /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/modules/modules.tar
126 22:49:15.055017 total size: 8594396 (8 MB)
127 22:49:15.055081 Using unxz to decompress xz
128 22:49:15.059115 progress 0 % (0 MB)
129 22:49:15.077925 progress 5 % (0 MB)
130 22:49:15.102692 progress 10 % (0 MB)
131 22:49:15.127158 progress 15 % (1 MB)
132 22:49:15.151186 progress 20 % (1 MB)
133 22:49:15.175944 progress 25 % (2 MB)
134 22:49:15.199944 progress 30 % (2 MB)
135 22:49:15.224089 progress 35 % (2 MB)
136 22:49:15.249825 progress 40 % (3 MB)
137 22:49:15.276005 progress 45 % (3 MB)
138 22:49:15.301316 progress 50 % (4 MB)
139 22:49:15.326445 progress 55 % (4 MB)
140 22:49:15.352869 progress 60 % (4 MB)
141 22:49:15.378438 progress 65 % (5 MB)
142 22:49:15.404295 progress 70 % (5 MB)
143 22:49:15.428829 progress 75 % (6 MB)
144 22:49:15.454478 progress 80 % (6 MB)
145 22:49:15.480499 progress 85 % (6 MB)
146 22:49:15.510061 progress 90 % (7 MB)
147 22:49:15.539804 progress 95 % (7 MB)
148 22:49:15.566009 progress 100 % (8 MB)
149 22:49:15.571112 8 MB downloaded in 0.52 s (15.88 MB/s)
150 22:49:15.571400 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:49:15.571675 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:49:15.571769 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 22:49:15.571867 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 22:49:19.015629 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13683654/extract-nfsrootfs-a6eey1um
156 22:49:19.015854 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:49:19.015959 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 22:49:19.016138 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem
159 22:49:19.016267 makedir: /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin
160 22:49:19.016366 makedir: /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/tests
161 22:49:19.016463 makedir: /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/results
162 22:49:19.016566 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-add-keys
163 22:49:19.016728 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-add-sources
164 22:49:19.016895 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-background-process-start
165 22:49:19.017028 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-background-process-stop
166 22:49:19.017155 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-common-functions
167 22:49:19.017497 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-echo-ipv4
168 22:49:19.017629 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-install-packages
169 22:49:19.017755 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-installed-packages
170 22:49:19.017880 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-os-build
171 22:49:19.018005 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-probe-channel
172 22:49:19.018130 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-probe-ip
173 22:49:19.018252 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-target-ip
174 22:49:19.018375 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-target-mac
175 22:49:19.018497 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-target-storage
176 22:49:19.018623 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-test-case
177 22:49:19.018767 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-test-event
178 22:49:19.018988 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-test-feedback
179 22:49:19.019119 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-test-raise
180 22:49:19.019246 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-test-reference
181 22:49:19.019372 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-test-runner
182 22:49:19.019498 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-test-set
183 22:49:19.019621 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-test-shell
184 22:49:19.019751 Updating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-add-keys (debian)
185 22:49:19.019911 Updating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-add-sources (debian)
186 22:49:19.020056 Updating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-install-packages (debian)
187 22:49:19.020204 Updating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-installed-packages (debian)
188 22:49:19.020344 Updating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/bin/lava-os-build (debian)
189 22:49:19.020468 Creating /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/environment
190 22:49:19.020568 LAVA metadata
191 22:49:19.020640 - LAVA_JOB_ID=13683654
192 22:49:19.020703 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:49:19.020810 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 22:49:19.020876 skipped lava-vland-overlay
195 22:49:19.020950 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:49:19.021028 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 22:49:19.021087 skipped lava-multinode-overlay
198 22:49:19.021157 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:49:19.021244 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 22:49:19.021321 Loading test definitions
201 22:49:19.021409 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 22:49:19.021480 Using /lava-13683654 at stage 0
203 22:49:19.021758 uuid=13683654_1.6.2.3.1 testdef=None
204 22:49:19.021847 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:49:19.021931 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 22:49:19.022378 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:49:19.022600 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 22:49:19.023178 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:49:19.023406 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 22:49:19.023936 runner path: /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/0/tests/0_timesync-off test_uuid 13683654_1.6.2.3.1
213 22:49:19.024092 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:49:19.024315 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 22:49:19.024386 Using /lava-13683654 at stage 0
217 22:49:19.024481 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:49:19.024567 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/0/tests/1_kselftest-tpm2'
219 22:49:23.108669 Running '/usr/bin/git checkout kernelci.org
220 22:49:23.194504 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 22:49:23.195248 uuid=13683654_1.6.2.3.5 testdef=None
222 22:49:23.195406 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 22:49:23.195651 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 22:49:23.196466 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:49:23.196696 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 22:49:23.197678 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:49:23.197912 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 22:49:23.198830 runner path: /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/0/tests/1_kselftest-tpm2 test_uuid 13683654_1.6.2.3.5
232 22:49:23.198923 BOARD='mt8192-asurada-spherion-r0'
233 22:49:23.198987 BRANCH='cip'
234 22:49:23.199048 SKIPFILE='/dev/null'
235 22:49:23.199105 SKIP_INSTALL='True'
236 22:49:23.199161 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:49:23.199220 TST_CASENAME=''
238 22:49:23.199275 TST_CMDFILES='tpm2'
239 22:49:23.199413 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:49:23.199622 Creating lava-test-runner.conf files
242 22:49:23.199684 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683654/lava-overlay-bb0qxwem/lava-13683654/0 for stage 0
243 22:49:23.199776 - 0_timesync-off
244 22:49:23.199844 - 1_kselftest-tpm2
245 22:49:23.199938 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 22:49:23.200024 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 22:49:30.723916 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:49:30.724122 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 22:49:30.724229 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:49:30.724422 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 22:49:30.724548 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 22:49:30.892383 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:49:30.892782 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 22:49:30.892894 extracting modules file /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683654/extract-nfsrootfs-a6eey1um
255 22:49:31.105275 extracting modules file /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683654/extract-overlay-ramdisk-zhe7xzd8/ramdisk
256 22:49:31.322462 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:49:31.322635 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 22:49:31.322726 [common] Applying overlay to NFS
259 22:49:31.322795 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683654/compress-overlay-eaq2lqr8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683654/extract-nfsrootfs-a6eey1um
260 22:49:32.229720 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:49:32.229878 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 22:49:32.229980 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:49:32.230110 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 22:49:32.230193 Building ramdisk /var/lib/lava/dispatcher/tmp/13683654/extract-overlay-ramdisk-zhe7xzd8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683654/extract-overlay-ramdisk-zhe7xzd8/ramdisk
265 22:49:32.570103 >> 130327 blocks
266 22:49:34.569063 rename /var/lib/lava/dispatcher/tmp/13683654/extract-overlay-ramdisk-zhe7xzd8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/ramdisk/ramdisk.cpio.gz
267 22:49:34.569503 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:49:34.569627 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 22:49:34.569730 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 22:49:34.569855 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/kernel/Image'
271 22:49:48.016272 Returned 0 in 13 seconds
272 22:49:48.116902 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/kernel/image.itb
273 22:49:48.485596 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:49:48.485978 output: Created: Tue May 7 23:49:48 2024
275 22:49:48.486055 output: Image 0 (kernel-1)
276 22:49:48.486122 output: Description:
277 22:49:48.486184 output: Created: Tue May 7 23:49:48 2024
278 22:49:48.486249 output: Type: Kernel Image
279 22:49:48.486322 output: Compression: lzma compressed
280 22:49:48.486381 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
281 22:49:48.486437 output: Architecture: AArch64
282 22:49:48.486492 output: OS: Linux
283 22:49:48.486549 output: Load Address: 0x00000000
284 22:49:48.486608 output: Entry Point: 0x00000000
285 22:49:48.486666 output: Hash algo: crc32
286 22:49:48.486724 output: Hash value: 727ee7c6
287 22:49:48.486782 output: Image 1 (fdt-1)
288 22:49:48.486838 output: Description: mt8192-asurada-spherion-r0
289 22:49:48.486892 output: Created: Tue May 7 23:49:48 2024
290 22:49:48.486945 output: Type: Flat Device Tree
291 22:49:48.486998 output: Compression: uncompressed
292 22:49:48.487051 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 22:49:48.487104 output: Architecture: AArch64
294 22:49:48.487158 output: Hash algo: crc32
295 22:49:48.487210 output: Hash value: 0f8e4d2e
296 22:49:48.487263 output: Image 2 (ramdisk-1)
297 22:49:48.487315 output: Description: unavailable
298 22:49:48.487367 output: Created: Tue May 7 23:49:48 2024
299 22:49:48.487420 output: Type: RAMDisk Image
300 22:49:48.487472 output: Compression: Unknown Compression
301 22:49:48.487525 output: Data Size: 18725504 Bytes = 18286.62 KiB = 17.86 MiB
302 22:49:48.487584 output: Architecture: AArch64
303 22:49:48.487643 output: OS: Linux
304 22:49:48.487697 output: Load Address: unavailable
305 22:49:48.487749 output: Entry Point: unavailable
306 22:49:48.487802 output: Hash algo: crc32
307 22:49:48.487855 output: Hash value: faeac428
308 22:49:48.487908 output: Default Configuration: 'conf-1'
309 22:49:48.487960 output: Configuration 0 (conf-1)
310 22:49:48.488013 output: Description: mt8192-asurada-spherion-r0
311 22:49:48.488066 output: Kernel: kernel-1
312 22:49:48.488118 output: Init Ramdisk: ramdisk-1
313 22:49:48.488171 output: FDT: fdt-1
314 22:49:48.488224 output: Loadables: kernel-1
315 22:49:48.488344 output:
316 22:49:48.488582 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 22:49:48.488687 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 22:49:48.488789 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 22:49:48.488889 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 22:49:48.488975 No LXC device requested
321 22:49:48.489056 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:49:48.489145 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 22:49:48.489268 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:49:48.489341 Checking files for TFTP limit of 4294967296 bytes.
325 22:49:48.489963 end: 1 tftp-deploy (duration 00:00:43) [common]
326 22:49:48.490075 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:49:48.490166 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:49:48.490292 substitutions:
329 22:49:48.490361 - {DTB}: 13683654/tftp-deploy-_j5d1c4q/dtb/mt8192-asurada-spherion-r0.dtb
330 22:49:48.490427 - {INITRD}: 13683654/tftp-deploy-_j5d1c4q/ramdisk/ramdisk.cpio.gz
331 22:49:48.490486 - {KERNEL}: 13683654/tftp-deploy-_j5d1c4q/kernel/Image
332 22:49:48.490543 - {LAVA_MAC}: None
333 22:49:48.490599 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13683654/extract-nfsrootfs-a6eey1um
334 22:49:48.490655 - {NFS_SERVER_IP}: 192.168.201.1
335 22:49:48.490710 - {PRESEED_CONFIG}: None
336 22:49:48.490763 - {PRESEED_LOCAL}: None
337 22:49:48.490817 - {RAMDISK}: 13683654/tftp-deploy-_j5d1c4q/ramdisk/ramdisk.cpio.gz
338 22:49:48.490872 - {ROOT_PART}: None
339 22:49:48.490926 - {ROOT}: None
340 22:49:48.490979 - {SERVER_IP}: 192.168.201.1
341 22:49:48.491032 - {TEE}: None
342 22:49:48.491085 Parsed boot commands:
343 22:49:48.491141 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:49:48.491340 Parsed boot commands: tftpboot 192.168.201.1 13683654/tftp-deploy-_j5d1c4q/kernel/image.itb 13683654/tftp-deploy-_j5d1c4q/kernel/cmdline
345 22:49:48.491429 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:49:48.491513 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:49:48.491603 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:49:48.491688 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:49:48.491763 Not connected, no need to disconnect.
350 22:49:48.491836 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:49:48.491917 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:49:48.491985 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 22:49:48.495868 Setting prompt string to ['lava-test: # ']
354 22:49:48.496232 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:49:48.496344 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:49:48.496437 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:49:48.496530 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:49:48.496746 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 22:49:53.632310 >> Command sent successfully.
360 22:49:53.634730 Returned 0 in 5 seconds
361 22:49:53.735133 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:49:53.735468 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:49:53.735570 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:49:53.735671 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:49:53.735741 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:49:53.735809 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:49:53.736221 [Enter `^Ec?' for help]
369 22:49:53.909602
370 22:49:53.909757
371 22:49:53.909849 F0: 102B 0000
372 22:49:53.909917
373 22:49:53.909979 F3: 1001 0000 [0200]
374 22:49:53.913361
375 22:49:53.913477 F3: 1001 0000
376 22:49:53.913574
377 22:49:53.913666 F7: 102D 0000
378 22:49:53.913765
379 22:49:53.916638 F1: 0000 0000
380 22:49:53.916722
381 22:49:53.916804 V0: 0000 0000 [0001]
382 22:49:53.916872
383 22:49:53.920536 00: 0007 8000
384 22:49:53.920650
385 22:49:53.920745 01: 0000 0000
386 22:49:53.920848
387 22:49:53.923341 BP: 0C00 0209 [0000]
388 22:49:53.923424
389 22:49:53.923503 G0: 1182 0000
390 22:49:53.923567
391 22:49:53.926754 EC: 0000 0021 [4000]
392 22:49:53.926851
393 22:49:53.926941 S7: 0000 0000 [0000]
394 22:49:53.927036
395 22:49:53.930231 CC: 0000 0000 [0001]
396 22:49:53.930314
397 22:49:53.930391 T0: 0000 0040 [010F]
398 22:49:53.930522
399 22:49:53.930626 Jump to BL
400 22:49:53.930683
401 22:49:53.956786
402 22:49:53.956886
403 22:49:53.956977
404 22:49:53.964233 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:49:53.967929 ARM64: Exception handlers installed.
406 22:49:53.971513 ARM64: Testing exception
407 22:49:53.974712 ARM64: Done test exception
408 22:49:53.981833 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:49:53.991932 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:49:53.998919 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:49:54.008606 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:49:54.015169 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:49:54.021906 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:49:54.034318 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:49:54.040613 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:49:54.059965 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:49:54.063053 WDT: Last reset was cold boot
418 22:49:54.066362 SPI1(PAD0) initialized at 2873684 Hz
419 22:49:54.069988 SPI5(PAD0) initialized at 992727 Hz
420 22:49:54.073186 VBOOT: Loading verstage.
421 22:49:54.080487 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:49:54.083502 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:49:54.086521 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:49:54.089511 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:49:54.096829 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:49:54.103902 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:49:54.114513 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
428 22:49:54.114654
429 22:49:54.114729
430 22:49:54.124795 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:49:54.127836 ARM64: Exception handlers installed.
432 22:49:54.131173 ARM64: Testing exception
433 22:49:54.131268 ARM64: Done test exception
434 22:49:54.138614 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:49:54.141354 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:49:54.156741 Probing TPM: . done!
437 22:49:54.156895 TPM ready after 0 ms
438 22:49:54.163255 Connected to device vid:did:rid of 1ae0:0028:00
439 22:49:54.169756 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 22:49:54.227877 Initialized TPM device CR50 revision 0
441 22:49:54.240190 tlcl_send_startup: Startup return code is 0
442 22:49:54.240303 TPM: setup succeeded
443 22:49:54.251823 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:49:54.260132 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:49:54.272608 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:49:54.282908 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:49:54.286675 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:49:54.289887 in-header: 03 07 00 00 08 00 00 00
449 22:49:54.293887 in-data: aa e4 47 04 13 02 00 00
450 22:49:54.297292 Chrome EC: UHEPI supported
451 22:49:54.304485 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:49:54.308395 in-header: 03 ad 00 00 08 00 00 00
453 22:49:54.308522 in-data: 00 20 20 08 00 00 00 00
454 22:49:54.311957 Phase 1
455 22:49:54.315836 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:49:54.319232 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:49:54.327156 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:49:54.330337 Recovery requested (1009000e)
459 22:49:54.338261 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:49:54.344480 tlcl_extend: response is 0
461 22:49:54.353438 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:49:54.359151 tlcl_extend: response is 0
463 22:49:54.365649 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:49:54.385818 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
465 22:49:54.392497 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:49:54.392587
467 22:49:54.392654
468 22:49:54.403303 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:49:54.407153 ARM64: Exception handlers installed.
470 22:49:54.407243 ARM64: Testing exception
471 22:49:54.410270 ARM64: Done test exception
472 22:49:54.431048 pmic_efuse_setting: Set efuses in 11 msecs
473 22:49:54.435091 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:49:54.441478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:49:54.445202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:49:54.451866 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:49:54.455016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:49:54.458962 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:49:54.465953 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:49:54.469719 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:49:54.473537 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:49:54.481109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:49:54.484267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:49:54.487791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:49:54.491428 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:49:54.498442 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:49:54.502212 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:49:54.509702 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:49:54.513612 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:49:54.520919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:49:54.525203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:49:54.532411 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:49:54.535983 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:49:54.542779 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:49:54.546973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:49:54.554407 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:49:54.557635 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:49:54.565295 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:49:54.569175 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:49:54.577035 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:49:54.580267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:49:54.584526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:49:54.591646 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:49:54.595422 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:49:54.599519 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:49:54.606396 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:49:54.609649 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:49:54.613475 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:49:54.620515 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:49:54.624439 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:49:54.632019 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:49:54.635525 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:49:54.639419 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:49:54.642954 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:49:54.646894 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:49:54.653321 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:49:54.657478 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:49:54.660997 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:49:54.665021 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:49:54.668963 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:49:54.672259 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:49:54.680315 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:49:54.683430 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:49:54.687113 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:49:54.694771 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:49:54.702281 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:49:54.705533 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:49:54.716961 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:49:54.724286 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:49:54.728593 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:49:54.731849 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:49:54.739049 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:49:54.742818 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 22:49:54.750088 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:49:54.753856 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 22:49:54.757687 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:49:54.768660 [RTC]rtc_get_frequency_meter,154: input=15, output=790
538 22:49:54.778289 [RTC]rtc_get_frequency_meter,154: input=23, output=979
539 22:49:54.788005 [RTC]rtc_get_frequency_meter,154: input=19, output=885
540 22:49:54.798000 [RTC]rtc_get_frequency_meter,154: input=17, output=837
541 22:49:54.806717 [RTC]rtc_get_frequency_meter,154: input=16, output=813
542 22:49:54.816371 [RTC]rtc_get_frequency_meter,154: input=15, output=791
543 22:49:54.826271 [RTC]rtc_get_frequency_meter,154: input=16, output=813
544 22:49:54.829905 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 22:49:54.833834 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 22:49:54.837524 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:49:54.845704 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 22:49:54.849094 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:49:54.852915 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 22:49:54.856569 ADC[4]: Raw value=902066 ID=7
551 22:49:54.856655 ADC[3]: Raw value=213336 ID=1
552 22:49:54.859895 RAM Code: 0x71
553 22:49:54.864093 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:49:54.867706 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:49:54.875138 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 22:49:54.882543 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 22:49:54.885500 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:49:54.889539 in-header: 03 07 00 00 08 00 00 00
559 22:49:54.893531 in-data: aa e4 47 04 13 02 00 00
560 22:49:54.897244 Chrome EC: UHEPI supported
561 22:49:54.905212 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:49:54.908392 in-header: 03 ed 00 00 08 00 00 00
563 22:49:54.908481 in-data: 80 20 60 08 00 00 00 00
564 22:49:54.911723 MRC: failed to locate region type 0.
565 22:49:54.919173 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:49:54.923160 DRAM-K: Running full calibration
567 22:49:54.929864 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 22:49:54.929949 header.status = 0x0
569 22:49:54.934317 header.version = 0x6 (expected: 0x6)
570 22:49:54.937255 header.size = 0xd00 (expected: 0xd00)
571 22:49:54.941192 header.flags = 0x0
572 22:49:54.944183 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:49:54.963835 read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps
574 22:49:54.971724 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:49:54.971830 dram_init: ddr_geometry: 2
576 22:49:54.975102 [EMI] MDL number = 2
577 22:49:54.979343 [EMI] Get MDL freq = 0
578 22:49:54.979427 dram_init: ddr_type: 0
579 22:49:54.983015 is_discrete_lpddr4: 1
580 22:49:54.983099 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:49:54.986364
582 22:49:54.986448
583 22:49:54.986515 [Bian_co] ETT version 0.0.0.1
584 22:49:54.993481 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 22:49:54.993619
586 22:49:54.998076 dramc_set_vcore_voltage set vcore to 650000
587 22:49:54.998170 Read voltage for 800, 4
588 22:49:54.998257 Vio18 = 0
589 22:49:55.001814 Vcore = 650000
590 22:49:55.001897 Vdram = 0
591 22:49:55.001964 Vddq = 0
592 22:49:55.004297 Vmddr = 0
593 22:49:55.004379 dram_init: config_dvfs: 1
594 22:49:55.011440 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:49:55.014800 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:49:55.017808 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 22:49:55.025048 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 22:49:55.027673 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 22:49:55.031170 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 22:49:55.034531 MEM_TYPE=3, freq_sel=18
601 22:49:55.034614 sv_algorithm_assistance_LP4_1600
602 22:49:55.041320 ============ PULL DRAM RESETB DOWN ============
603 22:49:55.045094 ========== PULL DRAM RESETB DOWN end =========
604 22:49:55.048135 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:49:55.051657 ===================================
606 22:49:55.055181 LPDDR4 DRAM CONFIGURATION
607 22:49:55.057744 ===================================
608 22:49:55.061651 EX_ROW_EN[0] = 0x0
609 22:49:55.061734 EX_ROW_EN[1] = 0x0
610 22:49:55.065005 LP4Y_EN = 0x0
611 22:49:55.065088 WORK_FSP = 0x0
612 22:49:55.068122 WL = 0x2
613 22:49:55.068232 RL = 0x2
614 22:49:55.071198 BL = 0x2
615 22:49:55.071280 RPST = 0x0
616 22:49:55.075082 RD_PRE = 0x0
617 22:49:55.075169 WR_PRE = 0x1
618 22:49:55.077857 WR_PST = 0x0
619 22:49:55.077940 DBI_WR = 0x0
620 22:49:55.081459 DBI_RD = 0x0
621 22:49:55.081542 OTF = 0x1
622 22:49:55.084927 ===================================
623 22:49:55.088236 ===================================
624 22:49:55.091597 ANA top config
625 22:49:55.095072 ===================================
626 22:49:55.095155 DLL_ASYNC_EN = 0
627 22:49:55.098035 ALL_SLAVE_EN = 1
628 22:49:55.101955 NEW_RANK_MODE = 1
629 22:49:55.104899 DLL_IDLE_MODE = 1
630 22:49:55.108222 LP45_APHY_COMB_EN = 1
631 22:49:55.108306 TX_ODT_DIS = 1
632 22:49:55.111927 NEW_8X_MODE = 1
633 22:49:55.115089 ===================================
634 22:49:55.118255 ===================================
635 22:49:55.121798 data_rate = 1600
636 22:49:55.124906 CKR = 1
637 22:49:55.128675 DQ_P2S_RATIO = 8
638 22:49:55.131872 ===================================
639 22:49:55.131957 CA_P2S_RATIO = 8
640 22:49:55.135357 DQ_CA_OPEN = 0
641 22:49:55.138302 DQ_SEMI_OPEN = 0
642 22:49:55.141572 CA_SEMI_OPEN = 0
643 22:49:55.145125 CA_FULL_RATE = 0
644 22:49:55.148279 DQ_CKDIV4_EN = 1
645 22:49:55.148363 CA_CKDIV4_EN = 1
646 22:49:55.151665 CA_PREDIV_EN = 0
647 22:49:55.155272 PH8_DLY = 0
648 22:49:55.159116 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:49:55.162514 DQ_AAMCK_DIV = 4
650 22:49:55.162598 CA_AAMCK_DIV = 4
651 22:49:55.165529 CA_ADMCK_DIV = 4
652 22:49:55.168609 DQ_TRACK_CA_EN = 0
653 22:49:55.172578 CA_PICK = 800
654 22:49:55.175719 CA_MCKIO = 800
655 22:49:55.178613 MCKIO_SEMI = 0
656 22:49:55.182263 PLL_FREQ = 3068
657 22:49:55.182346 DQ_UI_PI_RATIO = 32
658 22:49:55.187260 CA_UI_PI_RATIO = 0
659 22:49:55.190299 ===================================
660 22:49:55.193543 ===================================
661 22:49:55.193627 memory_type:LPDDR4
662 22:49:55.197835 GP_NUM : 10
663 22:49:55.197918 SRAM_EN : 1
664 22:49:55.201342 MD32_EN : 0
665 22:49:55.205175 ===================================
666 22:49:55.209031 [ANA_INIT] >>>>>>>>>>>>>>
667 22:49:55.209140 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:49:55.212569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:49:55.216348 ===================================
670 22:49:55.219387 data_rate = 1600,PCW = 0X7600
671 22:49:55.222869 ===================================
672 22:49:55.226076 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:49:55.232846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:49:55.236334 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:49:55.243580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:49:55.246355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:49:55.249762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:49:55.249845 [ANA_INIT] flow start
679 22:49:55.253176 [ANA_INIT] PLL >>>>>>>>
680 22:49:55.256727 [ANA_INIT] PLL <<<<<<<<
681 22:49:55.256816 [ANA_INIT] MIDPI >>>>>>>>
682 22:49:55.259784 [ANA_INIT] MIDPI <<<<<<<<
683 22:49:55.263517 [ANA_INIT] DLL >>>>>>>>
684 22:49:55.263606 [ANA_INIT] flow end
685 22:49:55.266841 ============ LP4 DIFF to SE enter ============
686 22:49:55.273162 ============ LP4 DIFF to SE exit ============
687 22:49:55.273306 [ANA_INIT] <<<<<<<<<<<<<
688 22:49:55.276939 [Flow] Enable top DCM control >>>>>
689 22:49:55.280046 [Flow] Enable top DCM control <<<<<
690 22:49:55.283406 Enable DLL master slave shuffle
691 22:49:55.290524 ==============================================================
692 22:49:55.290619 Gating Mode config
693 22:49:55.296427 ==============================================================
694 22:49:55.300023 Config description:
695 22:49:55.309729 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:49:55.317005 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:49:55.320417 SELPH_MODE 0: By rank 1: By Phase
698 22:49:55.327123 ==============================================================
699 22:49:55.327233 GAT_TRACK_EN = 1
700 22:49:55.330052 RX_GATING_MODE = 2
701 22:49:55.333893 RX_GATING_TRACK_MODE = 2
702 22:49:55.336700 SELPH_MODE = 1
703 22:49:55.340003 PICG_EARLY_EN = 1
704 22:49:55.343317 VALID_LAT_VALUE = 1
705 22:49:55.350304 ==============================================================
706 22:49:55.353844 Enter into Gating configuration >>>>
707 22:49:55.356734 Exit from Gating configuration <<<<
708 22:49:55.360101 Enter into DVFS_PRE_config >>>>>
709 22:49:55.370119 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:49:55.373777 Exit from DVFS_PRE_config <<<<<
711 22:49:55.377544 Enter into PICG configuration >>>>
712 22:49:55.380533 Exit from PICG configuration <<<<
713 22:49:55.380617 [RX_INPUT] configuration >>>>>
714 22:49:55.384114 [RX_INPUT] configuration <<<<<
715 22:49:55.390371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:49:55.393573 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:49:55.400481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:49:55.407486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:49:55.413994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:49:55.421103 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:49:55.424054 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:49:55.427524 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:49:55.430929 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:49:55.438019 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:49:55.441556 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:49:55.444692 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:49:55.447877 ===================================
728 22:49:55.451036 LPDDR4 DRAM CONFIGURATION
729 22:49:55.454357 ===================================
730 22:49:55.454440 EX_ROW_EN[0] = 0x0
731 22:49:55.457760 EX_ROW_EN[1] = 0x0
732 22:49:55.461327 LP4Y_EN = 0x0
733 22:49:55.461411 WORK_FSP = 0x0
734 22:49:55.464944 WL = 0x2
735 22:49:55.465027 RL = 0x2
736 22:49:55.468001 BL = 0x2
737 22:49:55.468084 RPST = 0x0
738 22:49:55.471260 RD_PRE = 0x0
739 22:49:55.471348 WR_PRE = 0x1
740 22:49:55.474533 WR_PST = 0x0
741 22:49:55.474618 DBI_WR = 0x0
742 22:49:55.477741 DBI_RD = 0x0
743 22:49:55.477827 OTF = 0x1
744 22:49:55.481366 ===================================
745 22:49:55.484741 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:49:55.491712 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:49:55.495182 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:49:55.498292 ===================================
749 22:49:55.501733 LPDDR4 DRAM CONFIGURATION
750 22:49:55.504919 ===================================
751 22:49:55.505007 EX_ROW_EN[0] = 0x10
752 22:49:55.508313 EX_ROW_EN[1] = 0x0
753 22:49:55.508397 LP4Y_EN = 0x0
754 22:49:55.511985 WORK_FSP = 0x0
755 22:49:55.512068 WL = 0x2
756 22:49:55.514794 RL = 0x2
757 22:49:55.514876 BL = 0x2
758 22:49:55.518353 RPST = 0x0
759 22:49:55.518436 RD_PRE = 0x0
760 22:49:55.522138 WR_PRE = 0x1
761 22:49:55.522221 WR_PST = 0x0
762 22:49:55.525664 DBI_WR = 0x0
763 22:49:55.525747 DBI_RD = 0x0
764 22:49:55.528094 OTF = 0x1
765 22:49:55.531830 ===================================
766 22:49:55.538868 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:49:55.541595 nWR fixed to 40
768 22:49:55.545153 [ModeRegInit_LP4] CH0 RK0
769 22:49:55.545309 [ModeRegInit_LP4] CH0 RK1
770 22:49:55.548474 [ModeRegInit_LP4] CH1 RK0
771 22:49:55.551624 [ModeRegInit_LP4] CH1 RK1
772 22:49:55.551708 match AC timing 13
773 22:49:55.558332 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 22:49:55.561540 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:49:55.564732 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:49:55.571749 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:49:55.574989 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:49:55.575080 [EMI DOE] emi_dcm 0
779 22:49:55.581880 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:49:55.581971 ==
781 22:49:55.585165 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:49:55.588610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 22:49:55.588696 ==
784 22:49:55.595173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:49:55.598672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:49:55.608882 [CA 0] Center 37 (7~68) winsize 62
787 22:49:55.612501 [CA 1] Center 37 (6~68) winsize 63
788 22:49:55.615602 [CA 2] Center 35 (5~66) winsize 62
789 22:49:55.618862 [CA 3] Center 34 (4~65) winsize 62
790 22:49:55.622236 [CA 4] Center 33 (3~64) winsize 62
791 22:49:55.625864 [CA 5] Center 33 (3~64) winsize 62
792 22:49:55.625948
793 22:49:55.628920 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 22:49:55.629003
795 22:49:55.632791 [CATrainingPosCal] consider 1 rank data
796 22:49:55.635650 u2DelayCellTimex100 = 270/100 ps
797 22:49:55.639269 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 22:49:55.642698 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 22:49:55.645813 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 22:49:55.652982 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 22:49:55.656239 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 22:49:55.659508 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 22:49:55.659593
804 22:49:55.663548 CA PerBit enable=1, Macro0, CA PI delay=33
805 22:49:55.663632
806 22:49:55.666050 [CBTSetCACLKResult] CA Dly = 33
807 22:49:55.666135 CS Dly: 5 (0~36)
808 22:49:55.666202 ==
809 22:49:55.669191 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:49:55.676418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:49:55.676504 ==
812 22:49:55.679330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:49:55.686788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:49:55.695285 [CA 0] Center 37 (7~68) winsize 62
815 22:49:55.698364 [CA 1] Center 37 (6~68) winsize 63
816 22:49:55.701860 [CA 2] Center 35 (4~66) winsize 63
817 22:49:55.705614 [CA 3] Center 35 (4~66) winsize 63
818 22:49:55.708601 [CA 4] Center 33 (3~64) winsize 62
819 22:49:55.711953 [CA 5] Center 33 (3~64) winsize 62
820 22:49:55.712036
821 22:49:55.715394 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 22:49:55.715478
823 22:49:55.718717 [CATrainingPosCal] consider 2 rank data
824 22:49:55.722315 u2DelayCellTimex100 = 270/100 ps
825 22:49:55.726335 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 22:49:55.729258 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
827 22:49:55.732079 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 22:49:55.739447 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 22:49:55.742803 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 22:49:55.746332 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 22:49:55.746416
832 22:49:55.748958 CA PerBit enable=1, Macro0, CA PI delay=33
833 22:49:55.749041
834 22:49:55.752446 [CBTSetCACLKResult] CA Dly = 33
835 22:49:55.752530 CS Dly: 6 (0~38)
836 22:49:55.752596
837 22:49:55.755885 ----->DramcWriteLeveling(PI) begin...
838 22:49:55.755973 ==
839 22:49:55.758841 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:49:55.766329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 22:49:55.766416 ==
842 22:49:55.766484 Write leveling (Byte 0): 31 => 31
843 22:49:55.770308 Write leveling (Byte 1): 32 => 32
844 22:49:55.773145 DramcWriteLeveling(PI) end<-----
845 22:49:55.773254
846 22:49:55.773321 ==
847 22:49:55.777088 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:49:55.781488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 22:49:55.781595 ==
850 22:49:55.784152 [Gating] SW mode calibration
851 22:49:55.790680 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:49:55.798282 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:49:55.801584 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:49:55.804943 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 22:49:55.808196 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 22:49:55.814657 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:49:55.818235 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:49:55.821935 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:49:55.828339 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:49:55.831586 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:49:55.834800 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:49:55.841710 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:49:55.845379 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:49:55.848597 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:49:55.855338 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:49:55.858524 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:49:55.862202 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:49:55.869472 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:49:55.872176 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:49:55.875941 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 22:49:55.879235 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
872 22:49:55.885571 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
873 22:49:55.888805 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:49:55.892055 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:49:55.898572 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:49:55.902551 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:49:55.905451 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:49:55.912397 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:49:55.915838 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
880 22:49:55.919335 0 9 12 | B1->B0 | 2b2b 3232 | 1 1 | (0 0) (1 1)
881 22:49:55.926032 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
882 22:49:55.928932 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:49:55.932761 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:49:55.936043 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:49:55.942584 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 22:49:55.945851 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 22:49:55.949549 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
888 22:49:55.955894 0 10 12 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (0 0)
889 22:49:55.959291 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:49:55.962513 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:49:55.969500 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:49:55.973047 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:49:55.976957 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 22:49:55.982903 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 22:49:55.986344 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
896 22:49:55.989636 0 11 12 | B1->B0 | 3535 3d3d | 1 1 | (0 0) (0 0)
897 22:49:55.992945 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:49:55.999564 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:49:56.002693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:49:56.006311 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:49:56.012925 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 22:49:56.016432 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 22:49:56.019553 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 22:49:56.026493 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 22:49:56.029904 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:49:56.033111 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:49:56.039777 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:49:56.043068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:49:56.046552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:49:56.053152 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:49:56.056540 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:49:56.059658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:49:56.063010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:49:56.070262 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:49:56.073159 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:49:56.076414 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:49:56.083289 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:49:56.086448 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 22:49:56.090166 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 22:49:56.093402 Total UI for P1: 0, mck2ui 16
921 22:49:56.096472 best dqsien dly found for B0: ( 0, 14, 6)
922 22:49:56.103316 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 22:49:56.106510 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 22:49:56.110033 Total UI for P1: 0, mck2ui 16
925 22:49:56.113133 best dqsien dly found for B1: ( 0, 14, 10)
926 22:49:56.116684 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 22:49:56.119944 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 22:49:56.120030
929 22:49:56.123830 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 22:49:56.126898 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 22:49:56.130063 [Gating] SW calibration Done
932 22:49:56.130148 ==
933 22:49:56.133908 Dram Type= 6, Freq= 0, CH_0, rank 0
934 22:49:56.137002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 22:49:56.137088 ==
936 22:49:56.140255 RX Vref Scan: 0
937 22:49:56.140339
938 22:49:56.143562 RX Vref 0 -> 0, step: 1
939 22:49:56.143648
940 22:49:56.143736 RX Delay -130 -> 252, step: 16
941 22:49:56.150234 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 22:49:56.153422 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 22:49:56.157590 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 22:49:56.160554 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 22:49:56.163368 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 22:49:56.170208 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 22:49:56.173724 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 22:49:56.176915 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 22:49:56.180800 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
950 22:49:56.184350 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
951 22:49:56.187259 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 22:49:56.194028 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
953 22:49:56.197675 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 22:49:56.200365 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
955 22:49:56.204537 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
956 22:49:56.210699 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
957 22:49:56.210785 ==
958 22:49:56.214466 Dram Type= 6, Freq= 0, CH_0, rank 0
959 22:49:56.217526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 22:49:56.217612 ==
961 22:49:56.217698 DQS Delay:
962 22:49:56.220791 DQS0 = 0, DQS1 = 0
963 22:49:56.220876 DQM Delay:
964 22:49:56.224082 DQM0 = 87, DQM1 = 81
965 22:49:56.224167 DQ Delay:
966 22:49:56.227925 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 22:49:56.231316 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
968 22:49:56.234435 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
969 22:49:56.237377 DQ12 =85, DQ13 =77, DQ14 =93, DQ15 =93
970 22:49:56.237462
971 22:49:56.237550
972 22:49:56.237632 ==
973 22:49:56.240762 Dram Type= 6, Freq= 0, CH_0, rank 0
974 22:49:56.244600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 22:49:56.244686 ==
976 22:49:56.244775
977 22:49:56.244856
978 22:49:56.247587 TX Vref Scan disable
979 22:49:56.251130 == TX Byte 0 ==
980 22:49:56.254799 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
981 22:49:56.257671 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
982 22:49:56.261126 == TX Byte 1 ==
983 22:49:56.264632 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
984 22:49:56.268054 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
985 22:49:56.268139 ==
986 22:49:56.271232 Dram Type= 6, Freq= 0, CH_0, rank 0
987 22:49:56.274156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 22:49:56.274241 ==
989 22:49:56.288659 TX Vref=22, minBit 5, minWin=27, winSum=441
990 22:49:56.292044 TX Vref=24, minBit 5, minWin=27, winSum=444
991 22:49:56.295381 TX Vref=26, minBit 0, minWin=28, winSum=453
992 22:49:56.298530 TX Vref=28, minBit 3, minWin=28, winSum=458
993 22:49:56.301901 TX Vref=30, minBit 3, minWin=28, winSum=458
994 22:49:56.305572 TX Vref=32, minBit 2, minWin=28, winSum=454
995 22:49:56.312249 [TxChooseVref] Worse bit 3, Min win 28, Win sum 458, Final Vref 28
996 22:49:56.312333
997 22:49:56.316111 Final TX Range 1 Vref 28
998 22:49:56.316196
999 22:49:56.316280 ==
1000 22:49:56.319069 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 22:49:56.321872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 22:49:56.321957 ==
1003 22:49:56.322041
1004 22:49:56.322121
1005 22:49:56.325797 TX Vref Scan disable
1006 22:49:56.328857 == TX Byte 0 ==
1007 22:49:56.332438 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1008 22:49:56.336015 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1009 22:49:56.338940 == TX Byte 1 ==
1010 22:49:56.342175 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1011 22:49:56.345597 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1012 22:49:56.345680
1013 22:49:56.348591 [DATLAT]
1014 22:49:56.348674 Freq=800, CH0 RK0
1015 22:49:56.348759
1016 22:49:56.353035 DATLAT Default: 0xa
1017 22:49:56.353118 0, 0xFFFF, sum = 0
1018 22:49:56.355261 1, 0xFFFF, sum = 0
1019 22:49:56.355346 2, 0xFFFF, sum = 0
1020 22:49:56.359166 3, 0xFFFF, sum = 0
1021 22:49:56.359251 4, 0xFFFF, sum = 0
1022 22:49:56.362088 5, 0xFFFF, sum = 0
1023 22:49:56.362174 6, 0xFFFF, sum = 0
1024 22:49:56.365225 7, 0xFFFF, sum = 0
1025 22:49:56.365335 8, 0xFFFF, sum = 0
1026 22:49:56.368777 9, 0x0, sum = 1
1027 22:49:56.368861 10, 0x0, sum = 2
1028 22:49:56.372506 11, 0x0, sum = 3
1029 22:49:56.372590 12, 0x0, sum = 4
1030 22:49:56.375695 best_step = 10
1031 22:49:56.375777
1032 22:49:56.375860 ==
1033 22:49:56.379153 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 22:49:56.382806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 22:49:56.382891 ==
1036 22:49:56.386260 RX Vref Scan: 1
1037 22:49:56.386344
1038 22:49:56.386430 Set Vref Range= 32 -> 127
1039 22:49:56.386510
1040 22:49:56.389157 RX Vref 32 -> 127, step: 1
1041 22:49:56.389295
1042 22:49:56.392762 RX Delay -95 -> 252, step: 8
1043 22:49:56.392846
1044 22:49:56.396053 Set Vref, RX VrefLevel [Byte0]: 32
1045 22:49:56.399145 [Byte1]: 32
1046 22:49:56.399229
1047 22:49:56.403074 Set Vref, RX VrefLevel [Byte0]: 33
1048 22:49:56.406326 [Byte1]: 33
1049 22:49:56.406410
1050 22:49:56.410347 Set Vref, RX VrefLevel [Byte0]: 34
1051 22:49:56.413127 [Byte1]: 34
1052 22:49:56.413271
1053 22:49:56.416573 Set Vref, RX VrefLevel [Byte0]: 35
1054 22:49:56.419729 [Byte1]: 35
1055 22:49:56.425001
1056 22:49:56.425085 Set Vref, RX VrefLevel [Byte0]: 36
1057 22:49:56.427728 [Byte1]: 36
1058 22:49:56.432034
1059 22:49:56.432117 Set Vref, RX VrefLevel [Byte0]: 37
1060 22:49:56.435873 [Byte1]: 37
1061 22:49:56.440550
1062 22:49:56.440633 Set Vref, RX VrefLevel [Byte0]: 38
1063 22:49:56.442920 [Byte1]: 38
1064 22:49:56.447175
1065 22:49:56.447259 Set Vref, RX VrefLevel [Byte0]: 39
1066 22:49:56.450294 [Byte1]: 39
1067 22:49:56.454848
1068 22:49:56.454932 Set Vref, RX VrefLevel [Byte0]: 40
1069 22:49:56.457832 [Byte1]: 40
1070 22:49:56.462595
1071 22:49:56.462676 Set Vref, RX VrefLevel [Byte0]: 41
1072 22:49:56.465500 [Byte1]: 41
1073 22:49:56.469907
1074 22:49:56.469988 Set Vref, RX VrefLevel [Byte0]: 42
1075 22:49:56.473266 [Byte1]: 42
1076 22:49:56.477089
1077 22:49:56.477170 Set Vref, RX VrefLevel [Byte0]: 43
1078 22:49:56.481142 [Byte1]: 43
1079 22:49:56.485662
1080 22:49:56.485796 Set Vref, RX VrefLevel [Byte0]: 44
1081 22:49:56.487974 [Byte1]: 44
1082 22:49:56.492312
1083 22:49:56.492409 Set Vref, RX VrefLevel [Byte0]: 45
1084 22:49:56.495774 [Byte1]: 45
1085 22:49:56.499660
1086 22:49:56.499741 Set Vref, RX VrefLevel [Byte0]: 46
1087 22:49:56.503094 [Byte1]: 46
1088 22:49:56.507511
1089 22:49:56.507592 Set Vref, RX VrefLevel [Byte0]: 47
1090 22:49:56.511139 [Byte1]: 47
1091 22:49:56.515131
1092 22:49:56.515211 Set Vref, RX VrefLevel [Byte0]: 48
1093 22:49:56.518224 [Byte1]: 48
1094 22:49:56.523045
1095 22:49:56.523126 Set Vref, RX VrefLevel [Byte0]: 49
1096 22:49:56.526320 [Byte1]: 49
1097 22:49:56.530520
1098 22:49:56.530601 Set Vref, RX VrefLevel [Byte0]: 50
1099 22:49:56.533670 [Byte1]: 50
1100 22:49:56.537873
1101 22:49:56.537954 Set Vref, RX VrefLevel [Byte0]: 51
1102 22:49:56.541497 [Byte1]: 51
1103 22:49:56.545238
1104 22:49:56.545318 Set Vref, RX VrefLevel [Byte0]: 52
1105 22:49:56.548520 [Byte1]: 52
1106 22:49:56.553104
1107 22:49:56.553184 Set Vref, RX VrefLevel [Byte0]: 53
1108 22:49:56.556645 [Byte1]: 53
1109 22:49:56.560689
1110 22:49:56.560770 Set Vref, RX VrefLevel [Byte0]: 54
1111 22:49:56.563815 [Byte1]: 54
1112 22:49:56.568398
1113 22:49:56.568480 Set Vref, RX VrefLevel [Byte0]: 55
1114 22:49:56.571907 [Byte1]: 55
1115 22:49:56.576249
1116 22:49:56.576329 Set Vref, RX VrefLevel [Byte0]: 56
1117 22:49:56.578997 [Byte1]: 56
1118 22:49:56.583754
1119 22:49:56.583835 Set Vref, RX VrefLevel [Byte0]: 57
1120 22:49:56.587032 [Byte1]: 57
1121 22:49:56.590969
1122 22:49:56.591049 Set Vref, RX VrefLevel [Byte0]: 58
1123 22:49:56.594360 [Byte1]: 58
1124 22:49:56.598428
1125 22:49:56.598509 Set Vref, RX VrefLevel [Byte0]: 59
1126 22:49:56.602162 [Byte1]: 59
1127 22:49:56.606652
1128 22:49:56.606732 Set Vref, RX VrefLevel [Byte0]: 60
1129 22:49:56.609242 [Byte1]: 60
1130 22:49:56.614236
1131 22:49:56.614317 Set Vref, RX VrefLevel [Byte0]: 61
1132 22:49:56.617014 [Byte1]: 61
1133 22:49:56.621159
1134 22:49:56.621249 Set Vref, RX VrefLevel [Byte0]: 62
1135 22:49:56.624789 [Byte1]: 62
1136 22:49:56.629456
1137 22:49:56.629537 Set Vref, RX VrefLevel [Byte0]: 63
1138 22:49:56.632506 [Byte1]: 63
1139 22:49:56.637399
1140 22:49:56.637479 Set Vref, RX VrefLevel [Byte0]: 64
1141 22:49:56.639853 [Byte1]: 64
1142 22:49:56.644568
1143 22:49:56.644649 Set Vref, RX VrefLevel [Byte0]: 65
1144 22:49:56.647595 [Byte1]: 65
1145 22:49:56.651644
1146 22:49:56.651725 Set Vref, RX VrefLevel [Byte0]: 66
1147 22:49:56.655525 [Byte1]: 66
1148 22:49:56.659230
1149 22:49:56.659314 Set Vref, RX VrefLevel [Byte0]: 67
1150 22:49:56.662666 [Byte1]: 67
1151 22:49:56.667529
1152 22:49:56.667610 Set Vref, RX VrefLevel [Byte0]: 68
1153 22:49:56.670840 [Byte1]: 68
1154 22:49:56.674433
1155 22:49:56.674514 Set Vref, RX VrefLevel [Byte0]: 69
1156 22:49:56.677816 [Byte1]: 69
1157 22:49:56.682198
1158 22:49:56.682279 Set Vref, RX VrefLevel [Byte0]: 70
1159 22:49:56.685265 [Byte1]: 70
1160 22:49:56.689953
1161 22:49:56.690034 Set Vref, RX VrefLevel [Byte0]: 71
1162 22:49:56.693394 [Byte1]: 71
1163 22:49:56.697762
1164 22:49:56.697843 Set Vref, RX VrefLevel [Byte0]: 72
1165 22:49:56.701029 [Byte1]: 72
1166 22:49:56.705083
1167 22:49:56.705164 Set Vref, RX VrefLevel [Byte0]: 73
1168 22:49:56.708207 [Byte1]: 73
1169 22:49:56.712841
1170 22:49:56.712922 Set Vref, RX VrefLevel [Byte0]: 74
1171 22:49:56.716099 [Byte1]: 74
1172 22:49:56.720319
1173 22:49:56.720400 Set Vref, RX VrefLevel [Byte0]: 75
1174 22:49:56.723725 [Byte1]: 75
1175 22:49:56.728112
1176 22:49:56.728192 Set Vref, RX VrefLevel [Byte0]: 76
1177 22:49:56.731154 [Byte1]: 76
1178 22:49:56.735385
1179 22:49:56.735466 Final RX Vref Byte 0 = 59 to rank0
1180 22:49:56.738921 Final RX Vref Byte 1 = 58 to rank0
1181 22:49:56.741906 Final RX Vref Byte 0 = 59 to rank1
1182 22:49:56.745167 Final RX Vref Byte 1 = 58 to rank1==
1183 22:49:56.748752 Dram Type= 6, Freq= 0, CH_0, rank 0
1184 22:49:56.752809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 22:49:56.755592 ==
1186 22:49:56.755673 DQS Delay:
1187 22:49:56.755737 DQS0 = 0, DQS1 = 0
1188 22:49:56.758829 DQM Delay:
1189 22:49:56.758910 DQM0 = 87, DQM1 = 78
1190 22:49:56.762245 DQ Delay:
1191 22:49:56.762327 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1192 22:49:56.765641 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =92
1193 22:49:56.769111 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1194 22:49:56.772423 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1195 22:49:56.772504
1196 22:49:56.775744
1197 22:49:56.782490 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1198 22:49:56.785866 CH0 RK0: MR19=606, MR18=260D
1199 22:49:56.792489 CH0_RK0: MR19=0x606, MR18=0x260D, DQSOSC=400, MR23=63, INC=92, DEC=61
1200 22:49:56.792587
1201 22:49:56.796128 ----->DramcWriteLeveling(PI) begin...
1202 22:49:56.796210 ==
1203 22:49:56.799027 Dram Type= 6, Freq= 0, CH_0, rank 1
1204 22:49:56.802125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 22:49:56.802207 ==
1206 22:49:56.805435 Write leveling (Byte 0): 32 => 32
1207 22:49:56.809557 Write leveling (Byte 1): 30 => 30
1208 22:49:56.812662 DramcWriteLeveling(PI) end<-----
1209 22:49:56.812742
1210 22:49:56.812806 ==
1211 22:49:56.816071 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 22:49:56.818932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1213 22:49:56.819013 ==
1214 22:49:56.822470 [Gating] SW mode calibration
1215 22:49:56.828894 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1216 22:49:56.835914 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1217 22:49:56.838739 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1218 22:49:56.842553 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1219 22:49:56.886271 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 22:49:56.886551 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 22:49:56.887392 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 22:49:56.887657 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:49:56.887726 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:49:56.888263 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:49:56.888556 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:49:56.888627 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:49:56.888883 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:49:56.888979 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:49:56.908552 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:49:56.909263 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:49:56.909651 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:49:56.909733 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:49:56.909992 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 22:49:56.912687 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1235 22:49:56.916309 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1236 22:49:56.922690 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1237 22:49:56.926266 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:49:56.929760 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:49:56.936016 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:49:56.939373 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:49:56.942856 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:49:56.949395 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 22:49:56.952917 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1244 22:49:56.956420 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1245 22:49:56.962664 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 22:49:56.966263 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 22:49:56.969588 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 22:49:56.976466 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 22:49:56.979957 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1250 22:49:56.983025 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1251 22:49:56.987205 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1252 22:49:56.993101 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1253 22:49:56.996658 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 22:49:56.999775 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 22:49:57.007208 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 22:49:57.010640 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 22:49:57.013586 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 22:49:57.017408 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1259 22:49:57.024192 0 11 8 | B1->B0 | 2b2b 3b3b | 1 0 | (0 0) (0 0)
1260 22:49:57.027705 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
1261 22:49:57.031494 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 22:49:57.037992 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 22:49:57.041870 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 22:49:57.044936 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 22:49:57.048629 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 22:49:57.055417 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 22:49:57.058579 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1268 22:49:57.062333 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 22:49:57.068464 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 22:49:57.071694 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 22:49:57.075339 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 22:49:57.081999 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 22:49:57.085594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 22:49:57.088686 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 22:49:57.092169 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 22:49:57.098912 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 22:49:57.102358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 22:49:57.105285 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 22:49:57.111967 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 22:49:57.115952 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 22:49:57.119858 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 22:49:57.125417 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 22:49:57.129039 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 22:49:57.132264 Total UI for P1: 0, mck2ui 16
1285 22:49:57.135691 best dqsien dly found for B0: ( 0, 14, 6)
1286 22:49:57.138858 Total UI for P1: 0, mck2ui 16
1287 22:49:57.142546 best dqsien dly found for B1: ( 0, 14, 6)
1288 22:49:57.145986 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1289 22:49:57.149478 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1290 22:49:57.149562
1291 22:49:57.152662 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1292 22:49:57.156048 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1293 22:49:57.159613 [Gating] SW calibration Done
1294 22:49:57.159697 ==
1295 22:49:57.162781 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 22:49:57.166830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 22:49:57.166919 ==
1298 22:49:57.169185 RX Vref Scan: 0
1299 22:49:57.169305
1300 22:49:57.169369 RX Vref 0 -> 0, step: 1
1301 22:49:57.169428
1302 22:49:57.172923 RX Delay -130 -> 252, step: 16
1303 22:49:57.176763 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1304 22:49:57.182873 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1305 22:49:57.186373 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1306 22:49:57.189434 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1307 22:49:57.193758 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1308 22:49:57.196175 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1309 22:49:57.203063 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1310 22:49:57.206639 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1311 22:49:57.209848 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1312 22:49:57.212802 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1313 22:49:57.216452 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1314 22:49:57.223368 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1315 22:49:57.226465 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1316 22:49:57.229965 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1317 22:49:57.233035 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1318 22:49:57.236343 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1319 22:49:57.236425 ==
1320 22:49:57.240311 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 22:49:57.247015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 22:49:57.247098 ==
1323 22:49:57.247163 DQS Delay:
1324 22:49:57.250335 DQS0 = 0, DQS1 = 0
1325 22:49:57.250441 DQM Delay:
1326 22:49:57.250534 DQM0 = 85, DQM1 = 76
1327 22:49:57.253514 DQ Delay:
1328 22:49:57.256712 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1329 22:49:57.259889 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1330 22:49:57.259971 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1331 22:49:57.266960 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1332 22:49:57.267042
1333 22:49:57.267106
1334 22:49:57.267165 ==
1335 22:49:57.269800 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 22:49:57.273613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 22:49:57.273693 ==
1338 22:49:57.273757
1339 22:49:57.273816
1340 22:49:57.276786 TX Vref Scan disable
1341 22:49:57.276869 == TX Byte 0 ==
1342 22:49:57.283271 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1343 22:49:57.286869 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1344 22:49:57.286951 == TX Byte 1 ==
1345 22:49:57.293652 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1346 22:49:57.297448 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1347 22:49:57.297530 ==
1348 22:49:57.300365 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 22:49:57.303632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 22:49:57.303713 ==
1351 22:49:57.317622 TX Vref=22, minBit 8, minWin=27, winSum=445
1352 22:49:57.320681 TX Vref=24, minBit 8, minWin=27, winSum=449
1353 22:49:57.324559 TX Vref=26, minBit 9, minWin=27, winSum=451
1354 22:49:57.327529 TX Vref=28, minBit 9, minWin=27, winSum=451
1355 22:49:57.330641 TX Vref=30, minBit 4, minWin=28, winSum=457
1356 22:49:57.334807 TX Vref=32, minBit 4, minWin=28, winSum=456
1357 22:49:57.340886 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 30
1358 22:49:57.340969
1359 22:49:57.344480 Final TX Range 1 Vref 30
1360 22:49:57.344564
1361 22:49:57.344628 ==
1362 22:49:57.347350 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 22:49:57.351005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 22:49:57.351114 ==
1365 22:49:57.351191
1366 22:49:57.351251
1367 22:49:57.354426 TX Vref Scan disable
1368 22:49:57.357678 == TX Byte 0 ==
1369 22:49:57.361324 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1370 22:49:57.364202 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1371 22:49:57.367795 == TX Byte 1 ==
1372 22:49:57.371053 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1373 22:49:57.374214 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1374 22:49:57.374296
1375 22:49:57.377607 [DATLAT]
1376 22:49:57.377689 Freq=800, CH0 RK1
1377 22:49:57.377754
1378 22:49:57.380876 DATLAT Default: 0xa
1379 22:49:57.380959 0, 0xFFFF, sum = 0
1380 22:49:57.384435 1, 0xFFFF, sum = 0
1381 22:49:57.384518 2, 0xFFFF, sum = 0
1382 22:49:57.387284 3, 0xFFFF, sum = 0
1383 22:49:57.387367 4, 0xFFFF, sum = 0
1384 22:49:57.390644 5, 0xFFFF, sum = 0
1385 22:49:57.390733 6, 0xFFFF, sum = 0
1386 22:49:57.394264 7, 0xFFFF, sum = 0
1387 22:49:57.394347 8, 0xFFFF, sum = 0
1388 22:49:57.397508 9, 0x0, sum = 1
1389 22:49:57.397592 10, 0x0, sum = 2
1390 22:49:57.401078 11, 0x0, sum = 3
1391 22:49:57.401162 12, 0x0, sum = 4
1392 22:49:57.404571 best_step = 10
1393 22:49:57.404651
1394 22:49:57.404715 ==
1395 22:49:57.407485 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 22:49:57.411164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 22:49:57.411246 ==
1398 22:49:57.414744 RX Vref Scan: 0
1399 22:49:57.414825
1400 22:49:57.414889 RX Vref 0 -> 0, step: 1
1401 22:49:57.414949
1402 22:49:57.417931 RX Delay -95 -> 252, step: 8
1403 22:49:57.424756 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1404 22:49:57.427966 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1405 22:49:57.431574 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1406 22:49:57.434938 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1407 22:49:57.437859 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1408 22:49:57.441184 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1409 22:49:57.447729 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1410 22:49:57.451392 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1411 22:49:57.455287 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1412 22:49:57.458584 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1413 22:49:57.461101 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1414 22:49:57.468037 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1415 22:49:57.471656 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1416 22:49:57.474676 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1417 22:49:57.478476 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1418 22:49:57.481142 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1419 22:49:57.484974 ==
1420 22:49:57.485055 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 22:49:57.491400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 22:49:57.491481 ==
1423 22:49:57.491544 DQS Delay:
1424 22:49:57.494737 DQS0 = 0, DQS1 = 0
1425 22:49:57.494821 DQM Delay:
1426 22:49:57.498212 DQM0 = 87, DQM1 = 78
1427 22:49:57.498293 DQ Delay:
1428 22:49:57.501761 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1429 22:49:57.504638 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1430 22:49:57.508007 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1431 22:49:57.511419 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1432 22:49:57.511499
1433 22:49:57.511562
1434 22:49:57.519085 [DQSOSCAuto] RK1, (LSB)MR18= 0x331d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1435 22:49:57.521618 CH0 RK1: MR19=606, MR18=331D
1436 22:49:57.528691 CH0_RK1: MR19=0x606, MR18=0x331D, DQSOSC=396, MR23=63, INC=94, DEC=62
1437 22:49:57.531499 [RxdqsGatingPostProcess] freq 800
1438 22:49:57.534856 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 22:49:57.538214 Pre-setting of DQS Precalculation
1440 22:49:57.545566 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 22:49:57.545646 ==
1442 22:49:57.548434 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 22:49:57.551689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 22:49:57.551771 ==
1445 22:49:57.558802 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 22:49:57.562422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 22:49:57.573065 [CA 0] Center 36 (6~67) winsize 62
1448 22:49:57.575757 [CA 1] Center 36 (6~67) winsize 62
1449 22:49:57.579398 [CA 2] Center 34 (4~65) winsize 62
1450 22:49:57.582162 [CA 3] Center 34 (3~65) winsize 63
1451 22:49:57.585658 [CA 4] Center 34 (3~65) winsize 63
1452 22:49:57.589142 [CA 5] Center 33 (3~64) winsize 62
1453 22:49:57.589279
1454 22:49:57.592313 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 22:49:57.592394
1456 22:49:57.596151 [CATrainingPosCal] consider 1 rank data
1457 22:49:57.598902 u2DelayCellTimex100 = 270/100 ps
1458 22:49:57.602528 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1459 22:49:57.605836 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1460 22:49:57.609348 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 22:49:57.616034 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1462 22:49:57.619163 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1463 22:49:57.622992 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 22:49:57.623073
1465 22:49:57.625755 CA PerBit enable=1, Macro0, CA PI delay=33
1466 22:49:57.625837
1467 22:49:57.629397 [CBTSetCACLKResult] CA Dly = 33
1468 22:49:57.629478 CS Dly: 5 (0~36)
1469 22:49:57.629542 ==
1470 22:49:57.632523 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 22:49:57.639285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 22:49:57.639366 ==
1473 22:49:57.642656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 22:49:57.649364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 22:49:57.658841 [CA 0] Center 36 (6~67) winsize 62
1476 22:49:57.661355 [CA 1] Center 36 (6~67) winsize 62
1477 22:49:57.664868 [CA 2] Center 33 (3~64) winsize 62
1478 22:49:57.668964 [CA 3] Center 33 (3~64) winsize 62
1479 22:49:57.671453 [CA 4] Center 34 (3~65) winsize 63
1480 22:49:57.675285 [CA 5] Center 33 (3~64) winsize 62
1481 22:49:57.675366
1482 22:49:57.678627 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1483 22:49:57.678709
1484 22:49:57.682164 [CATrainingPosCal] consider 2 rank data
1485 22:49:57.685713 u2DelayCellTimex100 = 270/100 ps
1486 22:49:57.689844 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1487 22:49:57.693108 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1488 22:49:57.696107 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1489 22:49:57.700113 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1490 22:49:57.703330 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1491 22:49:57.706697 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 22:49:57.706779
1493 22:49:57.710416 CA PerBit enable=1, Macro0, CA PI delay=33
1494 22:49:57.710497
1495 22:49:57.714606 [CBTSetCACLKResult] CA Dly = 33
1496 22:49:57.718810 CS Dly: 5 (0~37)
1497 22:49:57.718891
1498 22:49:57.721192 ----->DramcWriteLeveling(PI) begin...
1499 22:49:57.721296 ==
1500 22:49:57.724956 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 22:49:57.728587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 22:49:57.728672 ==
1503 22:49:57.731369 Write leveling (Byte 0): 26 => 26
1504 22:49:57.734961 Write leveling (Byte 1): 30 => 30
1505 22:49:57.738391 DramcWriteLeveling(PI) end<-----
1506 22:49:57.738471
1507 22:49:57.738534 ==
1508 22:49:57.741421 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 22:49:57.745338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 22:49:57.745420 ==
1511 22:49:57.748653 [Gating] SW mode calibration
1512 22:49:57.755467 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 22:49:57.758453 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 22:49:57.765245 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 22:49:57.768296 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1516 22:49:57.771825 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1517 22:49:57.778637 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 22:49:57.782667 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 22:49:57.785517 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 22:49:57.792269 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:49:57.795526 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:49:57.798522 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:49:57.802439 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:49:57.809110 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:49:57.812305 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:49:57.815391 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:49:57.822109 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:49:57.825874 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:49:57.828908 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:49:57.835525 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:49:57.839575 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:49:57.842356 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:49:57.849203 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:49:57.852453 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 22:49:57.855765 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:49:57.862390 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:49:57.865765 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:49:57.869077 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:49:57.872535 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:49:57.879696 0 9 8 | B1->B0 | 2a2a 2929 | 0 0 | (0 0) (0 0)
1541 22:49:57.883029 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 22:49:57.885914 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 22:49:57.893097 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 22:49:57.895770 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 22:49:57.899379 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1546 22:49:57.906247 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 22:49:57.909400 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
1548 22:49:57.913055 0 10 8 | B1->B0 | 2c2c 2e2e | 1 1 | (1 0) (1 0)
1549 22:49:57.919354 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 22:49:57.922662 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 22:49:57.926050 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 22:49:57.930137 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 22:49:57.936748 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 22:49:57.939697 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 22:49:57.943040 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1556 22:49:57.949551 0 11 8 | B1->B0 | 3636 3232 | 1 0 | (0 0) (1 1)
1557 22:49:57.953051 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 22:49:57.956597 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 22:49:57.964055 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 22:49:57.966166 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 22:49:57.969770 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 22:49:57.977051 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 22:49:57.980139 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 22:49:57.982999 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 22:49:57.986421 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 22:49:57.993601 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 22:49:57.996487 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 22:49:57.999976 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 22:49:58.006693 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 22:49:58.009889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 22:49:58.013630 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 22:49:58.019862 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 22:49:58.023348 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 22:49:58.026367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 22:49:58.033826 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 22:49:58.037126 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 22:49:58.040155 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 22:49:58.046663 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 22:49:58.050371 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 22:49:58.053633 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1581 22:49:58.056785 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 22:49:58.060468 Total UI for P1: 0, mck2ui 16
1583 22:49:58.063589 best dqsien dly found for B0: ( 0, 14, 8)
1584 22:49:58.067277 Total UI for P1: 0, mck2ui 16
1585 22:49:58.071228 best dqsien dly found for B1: ( 0, 14, 8)
1586 22:49:58.074396 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1587 22:49:58.077436 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1588 22:49:58.077520
1589 22:49:58.083860 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1590 22:49:58.087631 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1591 22:49:58.087715 [Gating] SW calibration Done
1592 22:49:58.087800 ==
1593 22:49:58.090454 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 22:49:58.097529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 22:49:58.097615 ==
1596 22:49:58.097709 RX Vref Scan: 0
1597 22:49:58.097789
1598 22:49:58.100677 RX Vref 0 -> 0, step: 1
1599 22:49:58.100761
1600 22:49:58.104595 RX Delay -130 -> 252, step: 16
1601 22:49:58.107392 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1602 22:49:58.110701 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1603 22:49:58.114191 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1604 22:49:58.121141 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1605 22:49:58.124384 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1606 22:49:58.127563 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1607 22:49:58.130869 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1608 22:49:58.133989 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1609 22:49:58.137505 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1610 22:49:58.144107 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1611 22:49:58.147401 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1612 22:49:58.151192 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1613 22:49:58.154385 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1614 22:49:58.157545 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1615 22:49:58.164556 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1616 22:49:58.167748 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1617 22:49:58.167837 ==
1618 22:49:58.171571 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 22:49:58.174426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 22:49:58.174512 ==
1621 22:49:58.177883 DQS Delay:
1622 22:49:58.177967 DQS0 = 0, DQS1 = 0
1623 22:49:58.178032 DQM Delay:
1624 22:49:58.181329 DQM0 = 80, DQM1 = 75
1625 22:49:58.181412 DQ Delay:
1626 22:49:58.184332 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1627 22:49:58.187811 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =69
1628 22:49:58.191412 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1629 22:49:58.194808 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1630 22:49:58.194893
1631 22:49:58.194957
1632 22:49:58.195017 ==
1633 22:49:58.198247 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 22:49:58.204948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 22:49:58.205050 ==
1636 22:49:58.205117
1637 22:49:58.205177
1638 22:49:58.205294 TX Vref Scan disable
1639 22:49:58.207998 == TX Byte 0 ==
1640 22:49:58.211157 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1641 22:49:58.214993 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1642 22:49:58.218411 == TX Byte 1 ==
1643 22:49:58.221128 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1644 22:49:58.225053 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1645 22:49:58.228242 ==
1646 22:49:58.228332 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 22:49:58.235191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 22:49:58.235282 ==
1649 22:49:58.247033 TX Vref=22, minBit 0, minWin=27, winSum=435
1650 22:49:58.250827 TX Vref=24, minBit 0, minWin=27, winSum=442
1651 22:49:58.253772 TX Vref=26, minBit 0, minWin=27, winSum=444
1652 22:49:58.257783 TX Vref=28, minBit 10, minWin=27, winSum=448
1653 22:49:58.260833 TX Vref=30, minBit 5, minWin=27, winSum=453
1654 22:49:58.264942 TX Vref=32, minBit 0, minWin=28, winSum=456
1655 22:49:58.271860 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 32
1656 22:49:58.271962
1657 22:49:58.275153 Final TX Range 1 Vref 32
1658 22:49:58.275239
1659 22:49:58.275304 ==
1660 22:49:58.278494 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 22:49:58.281511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 22:49:58.281596 ==
1663 22:49:58.281666
1664 22:49:58.281759
1665 22:49:58.285309 TX Vref Scan disable
1666 22:49:58.288389 == TX Byte 0 ==
1667 22:49:58.291906 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1668 22:49:58.295125 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1669 22:49:58.298392 == TX Byte 1 ==
1670 22:49:58.302050 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1671 22:49:58.305299 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1672 22:49:58.305411
1673 22:49:58.305504 [DATLAT]
1674 22:49:58.308550 Freq=800, CH1 RK0
1675 22:49:58.308640
1676 22:49:58.312002 DATLAT Default: 0xa
1677 22:49:58.312086 0, 0xFFFF, sum = 0
1678 22:49:58.315504 1, 0xFFFF, sum = 0
1679 22:49:58.315590 2, 0xFFFF, sum = 0
1680 22:49:58.318603 3, 0xFFFF, sum = 0
1681 22:49:58.318687 4, 0xFFFF, sum = 0
1682 22:49:58.321699 5, 0xFFFF, sum = 0
1683 22:49:58.321782 6, 0xFFFF, sum = 0
1684 22:49:58.325487 7, 0xFFFF, sum = 0
1685 22:49:58.325571 8, 0xFFFF, sum = 0
1686 22:49:58.329149 9, 0x0, sum = 1
1687 22:49:58.329256 10, 0x0, sum = 2
1688 22:49:58.329324 11, 0x0, sum = 3
1689 22:49:58.332014 12, 0x0, sum = 4
1690 22:49:58.332097 best_step = 10
1691 22:49:58.332163
1692 22:49:58.335259 ==
1693 22:49:58.335342 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 22:49:58.341835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 22:49:58.341928 ==
1696 22:49:58.341994 RX Vref Scan: 1
1697 22:49:58.342054
1698 22:49:58.345522 Set Vref Range= 32 -> 127
1699 22:49:58.345606
1700 22:49:58.348728 RX Vref 32 -> 127, step: 1
1701 22:49:58.348812
1702 22:49:58.352264 RX Delay -111 -> 252, step: 8
1703 22:49:58.352355
1704 22:49:58.355578 Set Vref, RX VrefLevel [Byte0]: 32
1705 22:49:58.358793 [Byte1]: 32
1706 22:49:58.358899
1707 22:49:58.361915 Set Vref, RX VrefLevel [Byte0]: 33
1708 22:49:58.365598 [Byte1]: 33
1709 22:49:58.365683
1710 22:49:58.368548 Set Vref, RX VrefLevel [Byte0]: 34
1711 22:49:58.372487 [Byte1]: 34
1712 22:49:58.375682
1713 22:49:58.375767 Set Vref, RX VrefLevel [Byte0]: 35
1714 22:49:58.378628 [Byte1]: 35
1715 22:49:58.383178
1716 22:49:58.383266 Set Vref, RX VrefLevel [Byte0]: 36
1717 22:49:58.386764 [Byte1]: 36
1718 22:49:58.390656
1719 22:49:58.390745 Set Vref, RX VrefLevel [Byte0]: 37
1720 22:49:58.394624 [Byte1]: 37
1721 22:49:58.398313
1722 22:49:58.398400 Set Vref, RX VrefLevel [Byte0]: 38
1723 22:49:58.402109 [Byte1]: 38
1724 22:49:58.405800
1725 22:49:58.405885 Set Vref, RX VrefLevel [Byte0]: 39
1726 22:49:58.409651 [Byte1]: 39
1727 22:49:58.413826
1728 22:49:58.413914 Set Vref, RX VrefLevel [Byte0]: 40
1729 22:49:58.417075 [Byte1]: 40
1730 22:49:58.421383
1731 22:49:58.421480 Set Vref, RX VrefLevel [Byte0]: 41
1732 22:49:58.424532 [Byte1]: 41
1733 22:49:58.428864
1734 22:49:58.428976 Set Vref, RX VrefLevel [Byte0]: 42
1735 22:49:58.432892 [Byte1]: 42
1736 22:49:58.436590
1737 22:49:58.436701 Set Vref, RX VrefLevel [Byte0]: 43
1738 22:49:58.439917 [Byte1]: 43
1739 22:49:58.444391
1740 22:49:58.444476 Set Vref, RX VrefLevel [Byte0]: 44
1741 22:49:58.447564 [Byte1]: 44
1742 22:49:58.452333
1743 22:49:58.452423 Set Vref, RX VrefLevel [Byte0]: 45
1744 22:49:58.455092 [Byte1]: 45
1745 22:49:58.459372
1746 22:49:58.459456 Set Vref, RX VrefLevel [Byte0]: 46
1747 22:49:58.462820 [Byte1]: 46
1748 22:49:58.467901
1749 22:49:58.467992 Set Vref, RX VrefLevel [Byte0]: 47
1750 22:49:58.470358 [Byte1]: 47
1751 22:49:58.474754
1752 22:49:58.474843 Set Vref, RX VrefLevel [Byte0]: 48
1753 22:49:58.478454 [Byte1]: 48
1754 22:49:58.482283
1755 22:49:58.482372 Set Vref, RX VrefLevel [Byte0]: 49
1756 22:49:58.485805 [Byte1]: 49
1757 22:49:58.490353
1758 22:49:58.490440 Set Vref, RX VrefLevel [Byte0]: 50
1759 22:49:58.493510 [Byte1]: 50
1760 22:49:58.498048
1761 22:49:58.498143 Set Vref, RX VrefLevel [Byte0]: 51
1762 22:49:58.501358 [Byte1]: 51
1763 22:49:58.505254
1764 22:49:58.505341 Set Vref, RX VrefLevel [Byte0]: 52
1765 22:49:58.508571 [Byte1]: 52
1766 22:49:58.513335
1767 22:49:58.513427 Set Vref, RX VrefLevel [Byte0]: 53
1768 22:49:58.516890 [Byte1]: 53
1769 22:49:58.520557
1770 22:49:58.520642 Set Vref, RX VrefLevel [Byte0]: 54
1771 22:49:58.523933 [Byte1]: 54
1772 22:49:58.528928
1773 22:49:58.529019 Set Vref, RX VrefLevel [Byte0]: 55
1774 22:49:58.531708 [Byte1]: 55
1775 22:49:58.536307
1776 22:49:58.536394 Set Vref, RX VrefLevel [Byte0]: 56
1777 22:49:58.539549 [Byte1]: 56
1778 22:49:58.543703
1779 22:49:58.543789 Set Vref, RX VrefLevel [Byte0]: 57
1780 22:49:58.546974 [Byte1]: 57
1781 22:49:58.551225
1782 22:49:58.551313 Set Vref, RX VrefLevel [Byte0]: 58
1783 22:49:58.554678 [Byte1]: 58
1784 22:49:58.558958
1785 22:49:58.559049 Set Vref, RX VrefLevel [Byte0]: 59
1786 22:49:58.562126 [Byte1]: 59
1787 22:49:58.567043
1788 22:49:58.567152 Set Vref, RX VrefLevel [Byte0]: 60
1789 22:49:58.570021 [Byte1]: 60
1790 22:49:58.574275
1791 22:49:58.574365 Set Vref, RX VrefLevel [Byte0]: 61
1792 22:49:58.577611 [Byte1]: 61
1793 22:49:58.581906
1794 22:49:58.581999 Set Vref, RX VrefLevel [Byte0]: 62
1795 22:49:58.585288 [Byte1]: 62
1796 22:49:58.590034
1797 22:49:58.590125 Set Vref, RX VrefLevel [Byte0]: 63
1798 22:49:58.592929 [Byte1]: 63
1799 22:49:58.597707
1800 22:49:58.597799 Set Vref, RX VrefLevel [Byte0]: 64
1801 22:49:58.600306 [Byte1]: 64
1802 22:49:58.604734
1803 22:49:58.604823 Set Vref, RX VrefLevel [Byte0]: 65
1804 22:49:58.608180 [Byte1]: 65
1805 22:49:58.612534
1806 22:49:58.612627 Set Vref, RX VrefLevel [Byte0]: 66
1807 22:49:58.615644 [Byte1]: 66
1808 22:49:58.620334
1809 22:49:58.620454 Set Vref, RX VrefLevel [Byte0]: 67
1810 22:49:58.623505 [Byte1]: 67
1811 22:49:58.627694
1812 22:49:58.627783 Set Vref, RX VrefLevel [Byte0]: 68
1813 22:49:58.631151 [Byte1]: 68
1814 22:49:58.635298
1815 22:49:58.635389 Set Vref, RX VrefLevel [Byte0]: 69
1816 22:49:58.638530 [Byte1]: 69
1817 22:49:58.643306
1818 22:49:58.643407 Set Vref, RX VrefLevel [Byte0]: 70
1819 22:49:58.646410 [Byte1]: 70
1820 22:49:58.650861
1821 22:49:58.650951 Set Vref, RX VrefLevel [Byte0]: 71
1822 22:49:58.654451 [Byte1]: 71
1823 22:49:58.658421
1824 22:49:58.658507 Set Vref, RX VrefLevel [Byte0]: 72
1825 22:49:58.662230 [Byte1]: 72
1826 22:49:58.666407
1827 22:49:58.666498 Set Vref, RX VrefLevel [Byte0]: 73
1828 22:49:58.669153 [Byte1]: 73
1829 22:49:58.673782
1830 22:49:58.673873 Set Vref, RX VrefLevel [Byte0]: 74
1831 22:49:58.677289 [Byte1]: 74
1832 22:49:58.681171
1833 22:49:58.681302 Set Vref, RX VrefLevel [Byte0]: 75
1834 22:49:58.684311 [Byte1]: 75
1835 22:49:58.688662
1836 22:49:58.688756 Set Vref, RX VrefLevel [Byte0]: 76
1837 22:49:58.692446 [Byte1]: 76
1838 22:49:58.696486
1839 22:49:58.696575 Set Vref, RX VrefLevel [Byte0]: 77
1840 22:49:58.700247 [Byte1]: 77
1841 22:49:58.704471
1842 22:49:58.704560 Set Vref, RX VrefLevel [Byte0]: 78
1843 22:49:58.708041 [Byte1]: 78
1844 22:49:58.711861
1845 22:49:58.711952 Final RX Vref Byte 0 = 66 to rank0
1846 22:49:58.715218 Final RX Vref Byte 1 = 59 to rank0
1847 22:49:58.718885 Final RX Vref Byte 0 = 66 to rank1
1848 22:49:58.722228 Final RX Vref Byte 1 = 59 to rank1==
1849 22:49:58.725032 Dram Type= 6, Freq= 0, CH_1, rank 0
1850 22:49:58.728840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 22:49:58.731834 ==
1852 22:49:58.731922 DQS Delay:
1853 22:49:58.731987 DQS0 = 0, DQS1 = 0
1854 22:49:58.736031 DQM Delay:
1855 22:49:58.736117 DQM0 = 82, DQM1 = 74
1856 22:49:58.739249 DQ Delay:
1857 22:49:58.739334 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1858 22:49:58.742305 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1859 22:49:58.745377 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1860 22:49:58.749379 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1861 22:49:58.749465
1862 22:49:58.752309
1863 22:49:58.758827 [DQSOSCAuto] RK0, (LSB)MR18= 0x29fe, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1864 22:49:58.762627 CH1 RK0: MR19=605, MR18=29FE
1865 22:49:58.769168 CH1_RK0: MR19=0x605, MR18=0x29FE, DQSOSC=399, MR23=63, INC=92, DEC=61
1866 22:49:58.769276
1867 22:49:58.772093 ----->DramcWriteLeveling(PI) begin...
1868 22:49:58.772179 ==
1869 22:49:58.775969 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 22:49:58.779322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 22:49:58.779416 ==
1872 22:49:58.782538 Write leveling (Byte 0): 28 => 28
1873 22:49:58.786514 Write leveling (Byte 1): 28 => 28
1874 22:49:58.788959 DramcWriteLeveling(PI) end<-----
1875 22:49:58.789044
1876 22:49:58.789107 ==
1877 22:49:58.792367 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 22:49:58.795479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 22:49:58.795565 ==
1880 22:49:58.799125 [Gating] SW mode calibration
1881 22:49:58.805917 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1882 22:49:58.812448 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1883 22:49:58.815701 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1884 22:49:58.819639 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1885 22:49:58.825735 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1886 22:49:58.828891 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:49:58.832271 0 6 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1888 22:49:58.835938 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:49:58.842747 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:49:58.845886 0 6 28 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1891 22:49:58.849202 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:49:58.856132 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:49:58.859136 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:49:58.862597 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1895 22:49:58.869122 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:49:58.873613 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1897 22:49:58.876063 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 22:49:58.882613 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 22:49:58.886135 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 22:49:58.889531 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1901 22:49:58.892503 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1902 22:49:58.899635 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 22:49:58.902917 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:49:58.906306 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:49:58.912878 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 22:49:58.916258 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 22:49:58.919497 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 22:49:58.926465 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1909 22:49:58.929796 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1910 22:49:58.932907 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 22:49:58.939537 0 9 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1912 22:49:58.943040 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 22:49:58.946232 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 22:49:58.952909 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1915 22:49:58.956304 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1916 22:49:58.960440 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 0)
1917 22:49:58.963417 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 22:49:58.969676 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 22:49:58.973794 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 22:49:58.976715 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 22:49:58.983512 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 22:49:58.986795 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 22:49:58.990261 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 22:49:58.997191 0 11 4 | B1->B0 | 2f2f 3535 | 0 1 | (0 0) (0 0)
1925 22:49:59.000562 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1926 22:49:59.003127 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 22:49:59.010777 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 22:49:59.013580 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 22:49:59.016811 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 22:49:59.019975 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 22:49:59.026818 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 22:49:59.030361 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1933 22:49:59.033530 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 22:49:59.041163 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 22:49:59.043281 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 22:49:59.046730 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 22:49:59.053668 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 22:49:59.056942 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 22:49:59.060274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 22:49:59.066946 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 22:49:59.070702 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 22:49:59.073972 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 22:49:59.080552 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 22:49:59.083551 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 22:49:59.086935 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 22:49:59.090341 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 22:49:59.097366 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 22:49:59.100216 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1949 22:49:59.103925 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1950 22:49:59.106899 Total UI for P1: 0, mck2ui 16
1951 22:49:59.111029 best dqsien dly found for B0: ( 0, 14, 4)
1952 22:49:59.117591 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 22:49:59.117699 Total UI for P1: 0, mck2ui 16
1954 22:49:59.124249 best dqsien dly found for B1: ( 0, 14, 6)
1955 22:49:59.126888 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1956 22:49:59.130532 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1957 22:49:59.130625
1958 22:49:59.133904 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1959 22:49:59.137303 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1960 22:49:59.140642 [Gating] SW calibration Done
1961 22:49:59.140731 ==
1962 22:49:59.143706 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 22:49:59.147401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 22:49:59.147491 ==
1965 22:49:59.151064 RX Vref Scan: 0
1966 22:49:59.151159
1967 22:49:59.151266 RX Vref 0 -> 0, step: 1
1968 22:49:59.151327
1969 22:49:59.154033 RX Delay -130 -> 252, step: 16
1970 22:49:59.157523 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1971 22:49:59.163924 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1972 22:49:59.167674 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1973 22:49:59.171091 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1974 22:49:59.174448 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1975 22:49:59.177479 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1976 22:49:59.180598 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1977 22:49:59.188035 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1978 22:49:59.190917 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1979 22:49:59.194446 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1980 22:49:59.197906 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1981 22:49:59.200846 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1982 22:49:59.207752 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1983 22:49:59.210670 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1984 22:49:59.214301 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1985 22:49:59.217628 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1986 22:49:59.217723 ==
1987 22:49:59.221316 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 22:49:59.227704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 22:49:59.227809 ==
1990 22:49:59.227878 DQS Delay:
1991 22:49:59.227939 DQS0 = 0, DQS1 = 0
1992 22:49:59.231194 DQM Delay:
1993 22:49:59.231280 DQM0 = 79, DQM1 = 76
1994 22:49:59.234534 DQ Delay:
1995 22:49:59.238111 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1996 22:49:59.238206 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1997 22:49:59.241474 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1998 22:49:59.247904 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1999 22:49:59.248015
2000 22:49:59.248085
2001 22:49:59.248146 ==
2002 22:49:59.251546 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 22:49:59.254367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 22:49:59.254454 ==
2005 22:49:59.254519
2006 22:49:59.254579
2007 22:49:59.257840 TX Vref Scan disable
2008 22:49:59.257926 == TX Byte 0 ==
2009 22:49:59.264635 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2010 22:49:59.268334 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2011 22:49:59.268436 == TX Byte 1 ==
2012 22:49:59.274909 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2013 22:49:59.277893 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2014 22:49:59.277992 ==
2015 22:49:59.281584 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 22:49:59.284691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 22:49:59.284788 ==
2018 22:49:59.297779 TX Vref=22, minBit 10, minWin=26, winSum=436
2019 22:49:59.301185 TX Vref=24, minBit 9, minWin=27, winSum=445
2020 22:49:59.305159 TX Vref=26, minBit 15, minWin=26, winSum=446
2021 22:49:59.308129 TX Vref=28, minBit 13, minWin=27, winSum=449
2022 22:49:59.312146 TX Vref=30, minBit 3, minWin=28, winSum=456
2023 22:49:59.318303 TX Vref=32, minBit 2, minWin=28, winSum=453
2024 22:49:59.321336 [TxChooseVref] Worse bit 3, Min win 28, Win sum 456, Final Vref 30
2025 22:49:59.321437
2026 22:49:59.324811 Final TX Range 1 Vref 30
2027 22:49:59.324898
2028 22:49:59.324964 ==
2029 22:49:59.328713 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 22:49:59.331652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 22:49:59.331742 ==
2032 22:49:59.331809
2033 22:49:59.335040
2034 22:49:59.335126 TX Vref Scan disable
2035 22:49:59.338093 == TX Byte 0 ==
2036 22:49:59.341712 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2037 22:49:59.345452 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2038 22:49:59.348577 == TX Byte 1 ==
2039 22:49:59.351656 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2040 22:49:59.354655 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2041 22:49:59.354746
2042 22:49:59.358432 [DATLAT]
2043 22:49:59.358524 Freq=800, CH1 RK1
2044 22:49:59.358591
2045 22:49:59.361994 DATLAT Default: 0xa
2046 22:49:59.362082 0, 0xFFFF, sum = 0
2047 22:49:59.365145 1, 0xFFFF, sum = 0
2048 22:49:59.365254 2, 0xFFFF, sum = 0
2049 22:49:59.368388 3, 0xFFFF, sum = 0
2050 22:49:59.368476 4, 0xFFFF, sum = 0
2051 22:49:59.371965 5, 0xFFFF, sum = 0
2052 22:49:59.372056 6, 0xFFFF, sum = 0
2053 22:49:59.374852 7, 0xFFFF, sum = 0
2054 22:49:59.374940 8, 0xFFFF, sum = 0
2055 22:49:59.378505 9, 0x0, sum = 1
2056 22:49:59.378593 10, 0x0, sum = 2
2057 22:49:59.381627 11, 0x0, sum = 3
2058 22:49:59.381716 12, 0x0, sum = 4
2059 22:49:59.385097 best_step = 10
2060 22:49:59.385215
2061 22:49:59.385284 ==
2062 22:49:59.388432 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 22:49:59.392035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 22:49:59.392125 ==
2065 22:49:59.394963 RX Vref Scan: 0
2066 22:49:59.395048
2067 22:49:59.395113 RX Vref 0 -> 0, step: 1
2068 22:49:59.395174
2069 22:49:59.398380 RX Delay -111 -> 252, step: 8
2070 22:49:59.404867 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2071 22:49:59.408248 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2072 22:49:59.411635 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2073 22:49:59.415157 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2074 22:49:59.418304 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2075 22:49:59.425093 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2076 22:49:59.428423 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2077 22:49:59.431988 iDelay=201, Bit 7, Center 72 (-39 ~ 184) 224
2078 22:49:59.434893 iDelay=201, Bit 8, Center 68 (-47 ~ 184) 232
2079 22:49:59.438540 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2080 22:49:59.441927 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2081 22:49:59.448518 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2082 22:49:59.452617 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2083 22:49:59.455548 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2084 22:49:59.458648 iDelay=201, Bit 14, Center 80 (-39 ~ 200) 240
2085 22:49:59.465310 iDelay=201, Bit 15, Center 80 (-39 ~ 200) 240
2086 22:49:59.465420 ==
2087 22:49:59.468569 Dram Type= 6, Freq= 0, CH_1, rank 1
2088 22:49:59.471902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2089 22:49:59.471991 ==
2090 22:49:59.472057 DQS Delay:
2091 22:49:59.475482 DQS0 = 0, DQS1 = 0
2092 22:49:59.475568 DQM Delay:
2093 22:49:59.478799 DQM0 = 78, DQM1 = 75
2094 22:49:59.478892 DQ Delay:
2095 22:49:59.481844 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =76
2096 22:49:59.485544 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =72
2097 22:49:59.488590 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2098 22:49:59.492120 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =80
2099 22:49:59.492220
2100 22:49:59.492286
2101 22:49:59.499221 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
2102 22:49:59.502077 CH1 RK1: MR19=606, MR18=1F2B
2103 22:49:59.508800 CH1_RK1: MR19=0x606, MR18=0x1F2B, DQSOSC=398, MR23=63, INC=93, DEC=62
2104 22:49:59.512082 [RxdqsGatingPostProcess] freq 800
2105 22:49:59.515589 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2106 22:49:59.519330 Pre-setting of DQS Precalculation
2107 22:49:59.525839 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2108 22:49:59.532525 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2109 22:49:59.539082 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2110 22:49:59.539197
2111 22:49:59.539264
2112 22:49:59.542998 [Calibration Summary] 1600 Mbps
2113 22:49:59.543088 CH 0, Rank 0
2114 22:49:59.545983 SW Impedance : PASS
2115 22:49:59.549627 DUTY Scan : NO K
2116 22:49:59.549719 ZQ Calibration : PASS
2117 22:49:59.552280 Jitter Meter : NO K
2118 22:49:59.555863 CBT Training : PASS
2119 22:49:59.555953 Write leveling : PASS
2120 22:49:59.559628 RX DQS gating : PASS
2121 22:49:59.562677 RX DQ/DQS(RDDQC) : PASS
2122 22:49:59.562767 TX DQ/DQS : PASS
2123 22:49:59.565937 RX DATLAT : PASS
2124 22:49:59.566026 RX DQ/DQS(Engine): PASS
2125 22:49:59.569937 TX OE : NO K
2126 22:49:59.570028 All Pass.
2127 22:49:59.570093
2128 22:49:59.572513 CH 0, Rank 1
2129 22:49:59.572598 SW Impedance : PASS
2130 22:49:59.575920 DUTY Scan : NO K
2131 22:49:59.579290 ZQ Calibration : PASS
2132 22:49:59.579387 Jitter Meter : NO K
2133 22:49:59.582709 CBT Training : PASS
2134 22:49:59.586050 Write leveling : PASS
2135 22:49:59.586148 RX DQS gating : PASS
2136 22:49:59.589416 RX DQ/DQS(RDDQC) : PASS
2137 22:49:59.592589 TX DQ/DQS : PASS
2138 22:49:59.592680 RX DATLAT : PASS
2139 22:49:59.596115 RX DQ/DQS(Engine): PASS
2140 22:49:59.596203 TX OE : NO K
2141 22:49:59.599460 All Pass.
2142 22:49:59.599548
2143 22:49:59.599614 CH 1, Rank 0
2144 22:49:59.602751 SW Impedance : PASS
2145 22:49:59.602841 DUTY Scan : NO K
2146 22:49:59.606579 ZQ Calibration : PASS
2147 22:49:59.609923 Jitter Meter : NO K
2148 22:49:59.610056 CBT Training : PASS
2149 22:49:59.613252 Write leveling : PASS
2150 22:49:59.616367 RX DQS gating : PASS
2151 22:49:59.616458 RX DQ/DQS(RDDQC) : PASS
2152 22:49:59.619594 TX DQ/DQS : PASS
2153 22:49:59.623467 RX DATLAT : PASS
2154 22:49:59.623568 RX DQ/DQS(Engine): PASS
2155 22:49:59.626556 TX OE : NO K
2156 22:49:59.626644 All Pass.
2157 22:49:59.626710
2158 22:49:59.629639 CH 1, Rank 1
2159 22:49:59.629726 SW Impedance : PASS
2160 22:49:59.633109 DUTY Scan : NO K
2161 22:49:59.636622 ZQ Calibration : PASS
2162 22:49:59.636712 Jitter Meter : NO K
2163 22:49:59.639817 CBT Training : PASS
2164 22:49:59.639906 Write leveling : PASS
2165 22:49:59.643272 RX DQS gating : PASS
2166 22:49:59.646383 RX DQ/DQS(RDDQC) : PASS
2167 22:49:59.646472 TX DQ/DQS : PASS
2168 22:49:59.649581 RX DATLAT : PASS
2169 22:49:59.653506 RX DQ/DQS(Engine): PASS
2170 22:49:59.653595 TX OE : NO K
2171 22:49:59.656777 All Pass.
2172 22:49:59.656862
2173 22:49:59.656927 DramC Write-DBI off
2174 22:49:59.659792 PER_BANK_REFRESH: Hybrid Mode
2175 22:49:59.659877 TX_TRACKING: ON
2176 22:49:59.663342 [GetDramInforAfterCalByMRR] Vendor 6.
2177 22:49:59.669773 [GetDramInforAfterCalByMRR] Revision 606.
2178 22:49:59.673177 [GetDramInforAfterCalByMRR] Revision 2 0.
2179 22:49:59.673310 MR0 0x3b3b
2180 22:49:59.673376 MR8 0x5151
2181 22:49:59.676529 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 22:49:59.676615
2183 22:49:59.679859 MR0 0x3b3b
2184 22:49:59.679947 MR8 0x5151
2185 22:49:59.683150 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 22:49:59.683235
2187 22:49:59.693408 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2188 22:49:59.697156 [FAST_K] Save calibration result to emmc
2189 22:49:59.700676 [FAST_K] Save calibration result to emmc
2190 22:49:59.703558 dram_init: config_dvfs: 1
2191 22:49:59.706729 dramc_set_vcore_voltage set vcore to 662500
2192 22:49:59.706817 Read voltage for 1200, 2
2193 22:49:59.710062 Vio18 = 0
2194 22:49:59.710181 Vcore = 662500
2195 22:49:59.710250 Vdram = 0
2196 22:49:59.713406 Vddq = 0
2197 22:49:59.713493 Vmddr = 0
2198 22:49:59.717055 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2199 22:49:59.724143 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2200 22:49:59.727108 MEM_TYPE=3, freq_sel=15
2201 22:49:59.730354 sv_algorithm_assistance_LP4_1600
2202 22:49:59.733557 ============ PULL DRAM RESETB DOWN ============
2203 22:49:59.737259 ========== PULL DRAM RESETB DOWN end =========
2204 22:49:59.743683 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 22:49:59.747579 ===================================
2206 22:49:59.747682 LPDDR4 DRAM CONFIGURATION
2207 22:49:59.750509 ===================================
2208 22:49:59.753585 EX_ROW_EN[0] = 0x0
2209 22:49:59.753674 EX_ROW_EN[1] = 0x0
2210 22:49:59.757159 LP4Y_EN = 0x0
2211 22:49:59.757281 WORK_FSP = 0x0
2212 22:49:59.760588 WL = 0x4
2213 22:49:59.760701 RL = 0x4
2214 22:49:59.763900 BL = 0x2
2215 22:49:59.763987 RPST = 0x0
2216 22:49:59.767000 RD_PRE = 0x0
2217 22:49:59.767084 WR_PRE = 0x1
2218 22:49:59.770389 WR_PST = 0x0
2219 22:49:59.770475 DBI_WR = 0x0
2220 22:49:59.774198 DBI_RD = 0x0
2221 22:49:59.777234 OTF = 0x1
2222 22:49:59.777324 ===================================
2223 22:49:59.780340 ===================================
2224 22:49:59.783902 ANA top config
2225 22:49:59.787304 ===================================
2226 22:49:59.790894 DLL_ASYNC_EN = 0
2227 22:49:59.790985 ALL_SLAVE_EN = 0
2228 22:49:59.793985 NEW_RANK_MODE = 1
2229 22:49:59.797182 DLL_IDLE_MODE = 1
2230 22:49:59.800922 LP45_APHY_COMB_EN = 1
2231 22:49:59.801012 TX_ODT_DIS = 1
2232 22:49:59.804022 NEW_8X_MODE = 1
2233 22:49:59.807712 ===================================
2234 22:49:59.810678 ===================================
2235 22:49:59.814219 data_rate = 2400
2236 22:49:59.817544 CKR = 1
2237 22:49:59.820971 DQ_P2S_RATIO = 8
2238 22:49:59.824075 ===================================
2239 22:49:59.824166 CA_P2S_RATIO = 8
2240 22:49:59.828007 DQ_CA_OPEN = 0
2241 22:49:59.831044 DQ_SEMI_OPEN = 0
2242 22:49:59.834490 CA_SEMI_OPEN = 0
2243 22:49:59.837684 CA_FULL_RATE = 0
2244 22:49:59.841156 DQ_CKDIV4_EN = 0
2245 22:49:59.841294 CA_CKDIV4_EN = 0
2246 22:49:59.844454 CA_PREDIV_EN = 0
2247 22:49:59.847876 PH8_DLY = 17
2248 22:49:59.850984 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2249 22:49:59.854795 DQ_AAMCK_DIV = 4
2250 22:49:59.857859 CA_AAMCK_DIV = 4
2251 22:49:59.857947 CA_ADMCK_DIV = 4
2252 22:49:59.861592 DQ_TRACK_CA_EN = 0
2253 22:49:59.864453 CA_PICK = 1200
2254 22:49:59.868400 CA_MCKIO = 1200
2255 22:49:59.871543 MCKIO_SEMI = 0
2256 22:49:59.874882 PLL_FREQ = 2366
2257 22:49:59.877857 DQ_UI_PI_RATIO = 32
2258 22:49:59.877945 CA_UI_PI_RATIO = 0
2259 22:49:59.881456 ===================================
2260 22:49:59.885104 ===================================
2261 22:49:59.888420 memory_type:LPDDR4
2262 22:49:59.891910 GP_NUM : 10
2263 22:49:59.892004 SRAM_EN : 1
2264 22:49:59.895176 MD32_EN : 0
2265 22:49:59.898959 ===================================
2266 22:49:59.902019 [ANA_INIT] >>>>>>>>>>>>>>
2267 22:49:59.902111 <<<<<< [CONFIGURE PHASE]: ANA_TX
2268 22:49:59.905177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2269 22:49:59.908881 ===================================
2270 22:49:59.912088 data_rate = 2400,PCW = 0X5b00
2271 22:49:59.915138 ===================================
2272 22:49:59.918628 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2273 22:49:59.925428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 22:49:59.931665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 22:49:59.935112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2276 22:49:59.938590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2277 22:49:59.941787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2278 22:49:59.945153 [ANA_INIT] flow start
2279 22:49:59.945272 [ANA_INIT] PLL >>>>>>>>
2280 22:49:59.948603 [ANA_INIT] PLL <<<<<<<<
2281 22:49:59.951991 [ANA_INIT] MIDPI >>>>>>>>
2282 22:49:59.952082 [ANA_INIT] MIDPI <<<<<<<<
2283 22:49:59.955299 [ANA_INIT] DLL >>>>>>>>
2284 22:49:59.958848 [ANA_INIT] DLL <<<<<<<<
2285 22:49:59.958940 [ANA_INIT] flow end
2286 22:49:59.961847 ============ LP4 DIFF to SE enter ============
2287 22:49:59.968433 ============ LP4 DIFF to SE exit ============
2288 22:49:59.968540 [ANA_INIT] <<<<<<<<<<<<<
2289 22:49:59.971748 [Flow] Enable top DCM control >>>>>
2290 22:49:59.975454 [Flow] Enable top DCM control <<<<<
2291 22:49:59.978617 Enable DLL master slave shuffle
2292 22:49:59.986191 ==============================================================
2293 22:49:59.986303 Gating Mode config
2294 22:49:59.991754 ==============================================================
2295 22:49:59.994987 Config description:
2296 22:50:00.006055 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2297 22:50:00.011914 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2298 22:50:00.015343 SELPH_MODE 0: By rank 1: By Phase
2299 22:50:00.022465 ==============================================================
2300 22:50:00.022581 GAT_TRACK_EN = 1
2301 22:50:00.026011 RX_GATING_MODE = 2
2302 22:50:00.029107 RX_GATING_TRACK_MODE = 2
2303 22:50:00.032319 SELPH_MODE = 1
2304 22:50:00.035603 PICG_EARLY_EN = 1
2305 22:50:00.039216 VALID_LAT_VALUE = 1
2306 22:50:00.045527 ==============================================================
2307 22:50:00.048772 Enter into Gating configuration >>>>
2308 22:50:00.052287 Exit from Gating configuration <<<<
2309 22:50:00.055579 Enter into DVFS_PRE_config >>>>>
2310 22:50:00.065523 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2311 22:50:00.069050 Exit from DVFS_PRE_config <<<<<
2312 22:50:00.072229 Enter into PICG configuration >>>>
2313 22:50:00.075536 Exit from PICG configuration <<<<
2314 22:50:00.075630 [RX_INPUT] configuration >>>>>
2315 22:50:00.079005 [RX_INPUT] configuration <<<<<
2316 22:50:00.086158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2317 22:50:00.089016 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2318 22:50:00.095990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 22:50:00.102776 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 22:50:00.109051 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 22:50:00.116107 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 22:50:00.119173 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2323 22:50:00.122693 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2324 22:50:00.125765 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2325 22:50:00.132916 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2326 22:50:00.135880 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2327 22:50:00.139316 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 22:50:00.143492 ===================================
2329 22:50:00.146140 LPDDR4 DRAM CONFIGURATION
2330 22:50:00.149294 ===================================
2331 22:50:00.152564 EX_ROW_EN[0] = 0x0
2332 22:50:00.152655 EX_ROW_EN[1] = 0x0
2333 22:50:00.156494 LP4Y_EN = 0x0
2334 22:50:00.156586 WORK_FSP = 0x0
2335 22:50:00.159374 WL = 0x4
2336 22:50:00.159460 RL = 0x4
2337 22:50:00.162957 BL = 0x2
2338 22:50:00.163045 RPST = 0x0
2339 22:50:00.166582 RD_PRE = 0x0
2340 22:50:00.166669 WR_PRE = 0x1
2341 22:50:00.169856 WR_PST = 0x0
2342 22:50:00.169942 DBI_WR = 0x0
2343 22:50:00.172756 DBI_RD = 0x0
2344 22:50:00.172840 OTF = 0x1
2345 22:50:00.176235 ===================================
2346 22:50:00.179727 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2347 22:50:00.186269 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2348 22:50:00.189772 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2349 22:50:00.192889 ===================================
2350 22:50:00.196158 LPDDR4 DRAM CONFIGURATION
2351 22:50:00.200161 ===================================
2352 22:50:00.200260 EX_ROW_EN[0] = 0x10
2353 22:50:00.203708 EX_ROW_EN[1] = 0x0
2354 22:50:00.203794 LP4Y_EN = 0x0
2355 22:50:00.206364 WORK_FSP = 0x0
2356 22:50:00.206452 WL = 0x4
2357 22:50:00.210529 RL = 0x4
2358 22:50:00.210620 BL = 0x2
2359 22:50:00.213528 RPST = 0x0
2360 22:50:00.213613 RD_PRE = 0x0
2361 22:50:00.216357 WR_PRE = 0x1
2362 22:50:00.219734 WR_PST = 0x0
2363 22:50:00.219820 DBI_WR = 0x0
2364 22:50:00.223125 DBI_RD = 0x0
2365 22:50:00.223210 OTF = 0x1
2366 22:50:00.226686 ===================================
2367 22:50:00.233181 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2368 22:50:00.233331 ==
2369 22:50:00.236631 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 22:50:00.239834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 22:50:00.239922 ==
2372 22:50:00.243204 [Duty_Offset_Calibration]
2373 22:50:00.243289 B0:3 B1:-1 CA:1
2374 22:50:00.246650
2375 22:50:00.249491 [DutyScan_Calibration_Flow] k_type=0
2376 22:50:00.257034
2377 22:50:00.257170 ==CLK 0==
2378 22:50:00.260351 Final CLK duty delay cell = -4
2379 22:50:00.263691 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2380 22:50:00.266850 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2381 22:50:00.270480 [-4] AVG Duty = 4953%(X100)
2382 22:50:00.270575
2383 22:50:00.273285 CH0 CLK Duty spec in!! Max-Min= 156%
2384 22:50:00.276671 [DutyScan_Calibration_Flow] ====Done====
2385 22:50:00.276763
2386 22:50:00.280448 [DutyScan_Calibration_Flow] k_type=1
2387 22:50:00.295837
2388 22:50:00.295967 ==DQS 0 ==
2389 22:50:00.299114 Final DQS duty delay cell = 0
2390 22:50:00.302498 [0] MAX Duty = 5125%(X100), DQS PI = 44
2391 22:50:00.305668 [0] MIN Duty = 5000%(X100), DQS PI = 12
2392 22:50:00.305758 [0] AVG Duty = 5062%(X100)
2393 22:50:00.305823
2394 22:50:00.308947 ==DQS 1 ==
2395 22:50:00.312497 Final DQS duty delay cell = -4
2396 22:50:00.316071 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2397 22:50:00.319336 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2398 22:50:00.319450 [-4] AVG Duty = 5062%(X100)
2399 22:50:00.322768
2400 22:50:00.325738 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2401 22:50:00.325824
2402 22:50:00.329673 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2403 22:50:00.332781 [DutyScan_Calibration_Flow] ====Done====
2404 22:50:00.332865
2405 22:50:00.335706 [DutyScan_Calibration_Flow] k_type=3
2406 22:50:00.352786
2407 22:50:00.352938 ==DQM 0 ==
2408 22:50:00.355777 Final DQM duty delay cell = 0
2409 22:50:00.359115 [0] MAX Duty = 5000%(X100), DQS PI = 54
2410 22:50:00.362713 [0] MIN Duty = 4906%(X100), DQS PI = 2
2411 22:50:00.362802 [0] AVG Duty = 4953%(X100)
2412 22:50:00.362866
2413 22:50:00.366238 ==DQM 1 ==
2414 22:50:00.369468 Final DQM duty delay cell = 0
2415 22:50:00.373031 [0] MAX Duty = 5124%(X100), DQS PI = 32
2416 22:50:00.376126 [0] MIN Duty = 4969%(X100), DQS PI = 58
2417 22:50:00.376216 [0] AVG Duty = 5046%(X100)
2418 22:50:00.376281
2419 22:50:00.379891 CH0 DQM 0 Duty spec in!! Max-Min= 94%
2420 22:50:00.383010
2421 22:50:00.385946 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2422 22:50:00.389710 [DutyScan_Calibration_Flow] ====Done====
2423 22:50:00.389803
2424 22:50:00.392690 [DutyScan_Calibration_Flow] k_type=2
2425 22:50:00.408513
2426 22:50:00.408661 ==DQ 0 ==
2427 22:50:00.411657 Final DQ duty delay cell = -4
2428 22:50:00.414804 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2429 22:50:00.417937 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2430 22:50:00.421329 [-4] AVG Duty = 4968%(X100)
2431 22:50:00.421416
2432 22:50:00.421482 ==DQ 1 ==
2433 22:50:00.425109 Final DQ duty delay cell = 0
2434 22:50:00.428335 [0] MAX Duty = 5031%(X100), DQS PI = 18
2435 22:50:00.432100 [0] MIN Duty = 4907%(X100), DQS PI = 60
2436 22:50:00.434898 [0] AVG Duty = 4969%(X100)
2437 22:50:00.434986
2438 22:50:00.438203 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2439 22:50:00.438289
2440 22:50:00.441736 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2441 22:50:00.445113 [DutyScan_Calibration_Flow] ====Done====
2442 22:50:00.445265 ==
2443 22:50:00.448306 Dram Type= 6, Freq= 0, CH_1, rank 0
2444 22:50:00.451710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 22:50:00.451800 ==
2446 22:50:00.455484 [Duty_Offset_Calibration]
2447 22:50:00.455573 B0:1 B1:1 CA:2
2448 22:50:00.455638
2449 22:50:00.458087 [DutyScan_Calibration_Flow] k_type=0
2450 22:50:00.468254
2451 22:50:00.468378 ==CLK 0==
2452 22:50:00.471884 Final CLK duty delay cell = 0
2453 22:50:00.475320 [0] MAX Duty = 5156%(X100), DQS PI = 24
2454 22:50:00.478681 [0] MIN Duty = 4969%(X100), DQS PI = 42
2455 22:50:00.478773 [0] AVG Duty = 5062%(X100)
2456 22:50:00.482120
2457 22:50:00.482208 CH1 CLK Duty spec in!! Max-Min= 187%
2458 22:50:00.488397 [DutyScan_Calibration_Flow] ====Done====
2459 22:50:00.488500
2460 22:50:00.491763 [DutyScan_Calibration_Flow] k_type=1
2461 22:50:00.507904
2462 22:50:00.508062 ==DQS 0 ==
2463 22:50:00.510851 Final DQS duty delay cell = 0
2464 22:50:00.515131 [0] MAX Duty = 5062%(X100), DQS PI = 20
2465 22:50:00.517676 [0] MIN Duty = 4875%(X100), DQS PI = 48
2466 22:50:00.521923 [0] AVG Duty = 4968%(X100)
2467 22:50:00.522014
2468 22:50:00.522080 ==DQS 1 ==
2469 22:50:00.524310 Final DQS duty delay cell = 0
2470 22:50:00.527871 [0] MAX Duty = 5062%(X100), DQS PI = 36
2471 22:50:00.531100 [0] MIN Duty = 4907%(X100), DQS PI = 14
2472 22:50:00.531192 [0] AVG Duty = 4984%(X100)
2473 22:50:00.534794
2474 22:50:00.537837 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2475 22:50:00.537927
2476 22:50:00.541330 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2477 22:50:00.544750 [DutyScan_Calibration_Flow] ====Done====
2478 22:50:00.544840
2479 22:50:00.547859 [DutyScan_Calibration_Flow] k_type=3
2480 22:50:00.564391
2481 22:50:00.564544 ==DQM 0 ==
2482 22:50:00.567492 Final DQM duty delay cell = 0
2483 22:50:00.571290 [0] MAX Duty = 5093%(X100), DQS PI = 18
2484 22:50:00.574602 [0] MIN Duty = 4875%(X100), DQS PI = 50
2485 22:50:00.574692 [0] AVG Duty = 4984%(X100)
2486 22:50:00.577511
2487 22:50:00.577597 ==DQM 1 ==
2488 22:50:00.580801 Final DQM duty delay cell = 0
2489 22:50:00.584551 [0] MAX Duty = 5156%(X100), DQS PI = 62
2490 22:50:00.588169 [0] MIN Duty = 4938%(X100), DQS PI = 22
2491 22:50:00.588260 [0] AVG Duty = 5047%(X100)
2492 22:50:00.591164
2493 22:50:00.594800 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2494 22:50:00.594902
2495 22:50:00.598108 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2496 22:50:00.601156 [DutyScan_Calibration_Flow] ====Done====
2497 22:50:00.601264
2498 22:50:00.604698 [DutyScan_Calibration_Flow] k_type=2
2499 22:50:00.620938
2500 22:50:00.621094 ==DQ 0 ==
2501 22:50:00.624280 Final DQ duty delay cell = 0
2502 22:50:00.627492 [0] MAX Duty = 5124%(X100), DQS PI = 18
2503 22:50:00.630695 [0] MIN Duty = 4907%(X100), DQS PI = 50
2504 22:50:00.630787 [0] AVG Duty = 5015%(X100)
2505 22:50:00.630853
2506 22:50:00.634536 ==DQ 1 ==
2507 22:50:00.637607 Final DQ duty delay cell = 0
2508 22:50:00.640984 [0] MAX Duty = 5093%(X100), DQS PI = 8
2509 22:50:00.644241 [0] MIN Duty = 5000%(X100), DQS PI = 52
2510 22:50:00.644330 [0] AVG Duty = 5046%(X100)
2511 22:50:00.644396
2512 22:50:00.647895 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2513 22:50:00.647983
2514 22:50:00.650991 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2515 22:50:00.654952 [DutyScan_Calibration_Flow] ====Done====
2516 22:50:00.659984 nWR fixed to 30
2517 22:50:00.663685 [ModeRegInit_LP4] CH0 RK0
2518 22:50:00.663785 [ModeRegInit_LP4] CH0 RK1
2519 22:50:00.666891 [ModeRegInit_LP4] CH1 RK0
2520 22:50:00.669639 [ModeRegInit_LP4] CH1 RK1
2521 22:50:00.669730 match AC timing 7
2522 22:50:00.676395 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2523 22:50:00.680329 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2524 22:50:00.682926 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2525 22:50:00.690409 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2526 22:50:00.693139 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2527 22:50:00.693288 ==
2528 22:50:00.696526 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 22:50:00.699503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 22:50:00.699599 ==
2531 22:50:00.707081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 22:50:00.713740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2533 22:50:00.720713 [CA 0] Center 40 (10~71) winsize 62
2534 22:50:00.724141 [CA 1] Center 39 (9~70) winsize 62
2535 22:50:00.727677 [CA 2] Center 36 (6~67) winsize 62
2536 22:50:00.731039 [CA 3] Center 35 (5~66) winsize 62
2537 22:50:00.734337 [CA 4] Center 35 (5~65) winsize 61
2538 22:50:00.737746 [CA 5] Center 34 (4~65) winsize 62
2539 22:50:00.737843
2540 22:50:00.741118 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2541 22:50:00.741266
2542 22:50:00.744569 [CATrainingPosCal] consider 1 rank data
2543 22:50:00.747502 u2DelayCellTimex100 = 270/100 ps
2544 22:50:00.750739 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2545 22:50:00.754763 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2546 22:50:00.760834 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2547 22:50:00.764856 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2548 22:50:00.767752 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2549 22:50:00.770829 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2550 22:50:00.770923
2551 22:50:00.774505 CA PerBit enable=1, Macro0, CA PI delay=34
2552 22:50:00.774594
2553 22:50:00.777978 [CBTSetCACLKResult] CA Dly = 34
2554 22:50:00.778068 CS Dly: 7 (0~38)
2555 22:50:00.778134 ==
2556 22:50:00.781066 Dram Type= 6, Freq= 0, CH_0, rank 1
2557 22:50:00.788023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 22:50:00.788132 ==
2559 22:50:00.791256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2560 22:50:00.797693 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2561 22:50:00.807349 [CA 0] Center 39 (9~70) winsize 62
2562 22:50:00.810396 [CA 1] Center 39 (9~70) winsize 62
2563 22:50:00.813490 [CA 2] Center 36 (6~67) winsize 62
2564 22:50:00.816909 [CA 3] Center 35 (5~66) winsize 62
2565 22:50:00.820187 [CA 4] Center 34 (4~65) winsize 62
2566 22:50:00.823521 [CA 5] Center 34 (4~64) winsize 61
2567 22:50:00.823614
2568 22:50:00.826709 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2569 22:50:00.826796
2570 22:50:00.830272 [CATrainingPosCal] consider 2 rank data
2571 22:50:00.833538 u2DelayCellTimex100 = 270/100 ps
2572 22:50:00.836981 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2573 22:50:00.840160 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2574 22:50:00.846929 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2575 22:50:00.850273 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2576 22:50:00.853411 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2577 22:50:00.856879 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2578 22:50:00.856970
2579 22:50:00.860380 CA PerBit enable=1, Macro0, CA PI delay=34
2580 22:50:00.860482
2581 22:50:00.863545 [CBTSetCACLKResult] CA Dly = 34
2582 22:50:00.863632 CS Dly: 8 (0~41)
2583 22:50:00.863697
2584 22:50:00.867227 ----->DramcWriteLeveling(PI) begin...
2585 22:50:00.867315 ==
2586 22:50:00.870732 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 22:50:00.876942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 22:50:00.877046 ==
2589 22:50:00.880961 Write leveling (Byte 0): 31 => 31
2590 22:50:00.884461 Write leveling (Byte 1): 30 => 30
2591 22:50:00.884555 DramcWriteLeveling(PI) end<-----
2592 22:50:00.884622
2593 22:50:00.887218 ==
2594 22:50:00.890464 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 22:50:00.894231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 22:50:00.894325 ==
2597 22:50:00.897219 [Gating] SW mode calibration
2598 22:50:00.903686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2599 22:50:00.907505 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2600 22:50:00.914344 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 22:50:00.917709 0 15 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
2602 22:50:00.920952 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2603 22:50:00.927728 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 22:50:00.930904 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 22:50:00.934265 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 22:50:00.937528 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 22:50:00.943991 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 22:50:00.947804 1 0 0 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
2609 22:50:00.950654 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2610 22:50:00.957565 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 22:50:00.960826 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 22:50:00.964268 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 22:50:00.971336 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 22:50:00.974244 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 22:50:00.977661 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 22:50:00.984217 1 1 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2617 22:50:00.988010 1 1 4 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
2618 22:50:00.990997 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 22:50:00.997968 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 22:50:01.001848 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 22:50:01.004600 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 22:50:01.008026 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 22:50:01.014829 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 22:50:01.018095 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2625 22:50:01.021800 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2626 22:50:01.027968 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 22:50:01.031261 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 22:50:01.035076 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 22:50:01.041334 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 22:50:01.044773 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 22:50:01.048417 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 22:50:01.055017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 22:50:01.058570 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 22:50:01.061534 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 22:50:01.068607 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 22:50:01.071433 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 22:50:01.075075 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 22:50:01.078487 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 22:50:01.085235 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 22:50:01.088501 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2641 22:50:01.092125 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2642 22:50:01.095417 Total UI for P1: 0, mck2ui 16
2643 22:50:01.098677 best dqsien dly found for B0: ( 1, 4, 0)
2644 22:50:01.104954 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2645 22:50:01.105067 Total UI for P1: 0, mck2ui 16
2646 22:50:01.109101 best dqsien dly found for B1: ( 1, 4, 4)
2647 22:50:01.111820 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2648 22:50:01.118862 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2649 22:50:01.118979
2650 22:50:01.122386 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2651 22:50:01.125104 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2652 22:50:01.129031 [Gating] SW calibration Done
2653 22:50:01.129148 ==
2654 22:50:01.131931 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 22:50:01.135786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 22:50:01.135881 ==
2657 22:50:01.135948 RX Vref Scan: 0
2658 22:50:01.136009
2659 22:50:01.138487 RX Vref 0 -> 0, step: 1
2660 22:50:01.138572
2661 22:50:01.142164 RX Delay -40 -> 252, step: 8
2662 22:50:01.145494 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2663 22:50:01.148681 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2664 22:50:01.152392 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2665 22:50:01.159123 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2666 22:50:01.162107 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2667 22:50:01.165711 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2668 22:50:01.169035 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2669 22:50:01.173646 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2670 22:50:01.178900 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2671 22:50:01.182792 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2672 22:50:01.185811 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2673 22:50:01.189111 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2674 22:50:01.192474 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2675 22:50:01.199475 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2676 22:50:01.202754 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2677 22:50:01.205726 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2678 22:50:01.205822 ==
2679 22:50:01.210015 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 22:50:01.212276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 22:50:01.212366 ==
2682 22:50:01.216280 DQS Delay:
2683 22:50:01.216374 DQS0 = 0, DQS1 = 0
2684 22:50:01.218767 DQM Delay:
2685 22:50:01.218853 DQM0 = 115, DQM1 = 107
2686 22:50:01.218919 DQ Delay:
2687 22:50:01.222274 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2688 22:50:01.225566 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2689 22:50:01.229552 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2690 22:50:01.235718 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2691 22:50:01.235824
2692 22:50:01.235893
2693 22:50:01.235954 ==
2694 22:50:01.238875 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 22:50:01.242671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 22:50:01.242765 ==
2697 22:50:01.242831
2698 22:50:01.242891
2699 22:50:01.245585 TX Vref Scan disable
2700 22:50:01.245671 == TX Byte 0 ==
2701 22:50:01.252746 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2702 22:50:01.255759 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2703 22:50:01.255852 == TX Byte 1 ==
2704 22:50:01.262572 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2705 22:50:01.266212 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2706 22:50:01.266306 ==
2707 22:50:01.269303 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 22:50:01.272599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 22:50:01.272690 ==
2710 22:50:01.284948 TX Vref=22, minBit 1, minWin=24, winSum=414
2711 22:50:01.289047 TX Vref=24, minBit 0, minWin=26, winSum=422
2712 22:50:01.291928 TX Vref=26, minBit 4, minWin=26, winSum=430
2713 22:50:01.295322 TX Vref=28, minBit 0, minWin=26, winSum=428
2714 22:50:01.299085 TX Vref=30, minBit 12, minWin=26, winSum=436
2715 22:50:01.302380 TX Vref=32, minBit 0, minWin=27, winSum=436
2716 22:50:01.308965 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 32
2717 22:50:01.309074
2718 22:50:01.312591 Final TX Range 1 Vref 32
2719 22:50:01.312687
2720 22:50:01.312755 ==
2721 22:50:01.315302 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 22:50:01.319145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 22:50:01.319236 ==
2724 22:50:01.319301
2725 22:50:01.322104
2726 22:50:01.322188 TX Vref Scan disable
2727 22:50:01.325064 == TX Byte 0 ==
2728 22:50:01.328850 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2729 22:50:01.332261 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2730 22:50:01.335441 == TX Byte 1 ==
2731 22:50:01.338647 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2732 22:50:01.342001 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2733 22:50:01.342090
2734 22:50:01.345549 [DATLAT]
2735 22:50:01.345639 Freq=1200, CH0 RK0
2736 22:50:01.345706
2737 22:50:01.348659 DATLAT Default: 0xd
2738 22:50:01.348744 0, 0xFFFF, sum = 0
2739 22:50:01.352096 1, 0xFFFF, sum = 0
2740 22:50:01.352184 2, 0xFFFF, sum = 0
2741 22:50:01.355614 3, 0xFFFF, sum = 0
2742 22:50:01.355703 4, 0xFFFF, sum = 0
2743 22:50:01.358885 5, 0xFFFF, sum = 0
2744 22:50:01.358973 6, 0xFFFF, sum = 0
2745 22:50:01.361874 7, 0xFFFF, sum = 0
2746 22:50:01.361959 8, 0xFFFF, sum = 0
2747 22:50:01.365787 9, 0xFFFF, sum = 0
2748 22:50:01.365883 10, 0xFFFF, sum = 0
2749 22:50:01.369104 11, 0xFFFF, sum = 0
2750 22:50:01.369259 12, 0x0, sum = 1
2751 22:50:01.372316 13, 0x0, sum = 2
2752 22:50:01.372404 14, 0x0, sum = 3
2753 22:50:01.375500 15, 0x0, sum = 4
2754 22:50:01.375588 best_step = 13
2755 22:50:01.375653
2756 22:50:01.375713 ==
2757 22:50:01.379120 Dram Type= 6, Freq= 0, CH_0, rank 0
2758 22:50:01.386184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2759 22:50:01.386299 ==
2760 22:50:01.386371 RX Vref Scan: 1
2761 22:50:01.386433
2762 22:50:01.389053 Set Vref Range= 32 -> 127
2763 22:50:01.389139
2764 22:50:01.392504 RX Vref 32 -> 127, step: 1
2765 22:50:01.392591
2766 22:50:01.392657 RX Delay -21 -> 252, step: 4
2767 22:50:01.395693
2768 22:50:01.395779 Set Vref, RX VrefLevel [Byte0]: 32
2769 22:50:01.398881 [Byte1]: 32
2770 22:50:01.403530
2771 22:50:01.403631 Set Vref, RX VrefLevel [Byte0]: 33
2772 22:50:01.406713 [Byte1]: 33
2773 22:50:01.411319
2774 22:50:01.411420 Set Vref, RX VrefLevel [Byte0]: 34
2775 22:50:01.414892 [Byte1]: 34
2776 22:50:01.419567
2777 22:50:01.419668 Set Vref, RX VrefLevel [Byte0]: 35
2778 22:50:01.422854 [Byte1]: 35
2779 22:50:01.427596
2780 22:50:01.427693 Set Vref, RX VrefLevel [Byte0]: 36
2781 22:50:01.430547 [Byte1]: 36
2782 22:50:01.435382
2783 22:50:01.435482 Set Vref, RX VrefLevel [Byte0]: 37
2784 22:50:01.438339 [Byte1]: 37
2785 22:50:01.443747
2786 22:50:01.443846 Set Vref, RX VrefLevel [Byte0]: 38
2787 22:50:01.446576 [Byte1]: 38
2788 22:50:01.450796
2789 22:50:01.450891 Set Vref, RX VrefLevel [Byte0]: 39
2790 22:50:01.454376 [Byte1]: 39
2791 22:50:01.459735
2792 22:50:01.459836 Set Vref, RX VrefLevel [Byte0]: 40
2793 22:50:01.462006 [Byte1]: 40
2794 22:50:01.467036
2795 22:50:01.467133 Set Vref, RX VrefLevel [Byte0]: 41
2796 22:50:01.470493 [Byte1]: 41
2797 22:50:01.474812
2798 22:50:01.474908 Set Vref, RX VrefLevel [Byte0]: 42
2799 22:50:01.477839 [Byte1]: 42
2800 22:50:01.483037
2801 22:50:01.483189 Set Vref, RX VrefLevel [Byte0]: 43
2802 22:50:01.487189 [Byte1]: 43
2803 22:50:01.490883
2804 22:50:01.490986 Set Vref, RX VrefLevel [Byte0]: 44
2805 22:50:01.494701 [Byte1]: 44
2806 22:50:01.498337
2807 22:50:01.498429 Set Vref, RX VrefLevel [Byte0]: 45
2808 22:50:01.502132 [Byte1]: 45
2809 22:50:01.506480
2810 22:50:01.506578 Set Vref, RX VrefLevel [Byte0]: 46
2811 22:50:01.510042 [Byte1]: 46
2812 22:50:01.514818
2813 22:50:01.514927 Set Vref, RX VrefLevel [Byte0]: 47
2814 22:50:01.517931 [Byte1]: 47
2815 22:50:01.522308
2816 22:50:01.522414 Set Vref, RX VrefLevel [Byte0]: 48
2817 22:50:01.525880 [Byte1]: 48
2818 22:50:01.530488
2819 22:50:01.530591 Set Vref, RX VrefLevel [Byte0]: 49
2820 22:50:01.533702 [Byte1]: 49
2821 22:50:01.538295
2822 22:50:01.538399 Set Vref, RX VrefLevel [Byte0]: 50
2823 22:50:01.541749 [Byte1]: 50
2824 22:50:01.546146
2825 22:50:01.546250 Set Vref, RX VrefLevel [Byte0]: 51
2826 22:50:01.549619 [Byte1]: 51
2827 22:50:01.553932
2828 22:50:01.554035 Set Vref, RX VrefLevel [Byte0]: 52
2829 22:50:01.557310 [Byte1]: 52
2830 22:50:01.562169
2831 22:50:01.562277 Set Vref, RX VrefLevel [Byte0]: 53
2832 22:50:01.565677 [Byte1]: 53
2833 22:50:01.570145
2834 22:50:01.570245 Set Vref, RX VrefLevel [Byte0]: 54
2835 22:50:01.573332 [Byte1]: 54
2836 22:50:01.578251
2837 22:50:01.578353 Set Vref, RX VrefLevel [Byte0]: 55
2838 22:50:01.581182 [Byte1]: 55
2839 22:50:01.586283
2840 22:50:01.586390 Set Vref, RX VrefLevel [Byte0]: 56
2841 22:50:01.589030 [Byte1]: 56
2842 22:50:01.594105
2843 22:50:01.594214 Set Vref, RX VrefLevel [Byte0]: 57
2844 22:50:01.597182 [Byte1]: 57
2845 22:50:01.601840
2846 22:50:01.601942 Set Vref, RX VrefLevel [Byte0]: 58
2847 22:50:01.604924 [Byte1]: 58
2848 22:50:01.609607
2849 22:50:01.612821 Set Vref, RX VrefLevel [Byte0]: 59
2850 22:50:01.612927 [Byte1]: 59
2851 22:50:01.617572
2852 22:50:01.617674 Set Vref, RX VrefLevel [Byte0]: 60
2853 22:50:01.620824 [Byte1]: 60
2854 22:50:01.625497
2855 22:50:01.625599 Set Vref, RX VrefLevel [Byte0]: 61
2856 22:50:01.629191 [Byte1]: 61
2857 22:50:01.633263
2858 22:50:01.633360 Set Vref, RX VrefLevel [Byte0]: 62
2859 22:50:01.636572 [Byte1]: 62
2860 22:50:01.640992
2861 22:50:01.641090 Set Vref, RX VrefLevel [Byte0]: 63
2862 22:50:01.644505 [Byte1]: 63
2863 22:50:01.649785
2864 22:50:01.649891 Set Vref, RX VrefLevel [Byte0]: 64
2865 22:50:01.653083 [Byte1]: 64
2866 22:50:01.657178
2867 22:50:01.657327 Set Vref, RX VrefLevel [Byte0]: 65
2868 22:50:01.660845 [Byte1]: 65
2869 22:50:01.664913
2870 22:50:01.665011 Set Vref, RX VrefLevel [Byte0]: 66
2871 22:50:01.668345 [Byte1]: 66
2872 22:50:01.672796
2873 22:50:01.672901 Set Vref, RX VrefLevel [Byte0]: 67
2874 22:50:01.676108 [Byte1]: 67
2875 22:50:01.681038
2876 22:50:01.681143 Set Vref, RX VrefLevel [Byte0]: 68
2877 22:50:01.684376 [Byte1]: 68
2878 22:50:01.688972
2879 22:50:01.689073 Final RX Vref Byte 0 = 53 to rank0
2880 22:50:01.692047 Final RX Vref Byte 1 = 51 to rank0
2881 22:50:01.695473 Final RX Vref Byte 0 = 53 to rank1
2882 22:50:01.698949 Final RX Vref Byte 1 = 51 to rank1==
2883 22:50:01.702200 Dram Type= 6, Freq= 0, CH_0, rank 0
2884 22:50:01.706113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 22:50:01.708878 ==
2886 22:50:01.708971 DQS Delay:
2887 22:50:01.709036 DQS0 = 0, DQS1 = 0
2888 22:50:01.712404 DQM Delay:
2889 22:50:01.712494 DQM0 = 114, DQM1 = 105
2890 22:50:01.716010 DQ Delay:
2891 22:50:01.718780 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =112
2892 22:50:01.722327 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2893 22:50:01.725836 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2894 22:50:01.729035 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2895 22:50:01.729154
2896 22:50:01.729285
2897 22:50:01.735638 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2898 22:50:01.739304 CH0 RK0: MR19=303, MR18=FDEC
2899 22:50:01.746088 CH0_RK0: MR19=0x303, MR18=0xFDEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2900 22:50:01.746202
2901 22:50:01.749222 ----->DramcWriteLeveling(PI) begin...
2902 22:50:01.749343 ==
2903 22:50:01.752581 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 22:50:01.756007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 22:50:01.756098 ==
2906 22:50:01.759119 Write leveling (Byte 0): 31 => 31
2907 22:50:01.762892 Write leveling (Byte 1): 30 => 30
2908 22:50:01.766327 DramcWriteLeveling(PI) end<-----
2909 22:50:01.766428
2910 22:50:01.766494 ==
2911 22:50:01.769467 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 22:50:01.772341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 22:50:01.772429 ==
2914 22:50:01.776346 [Gating] SW mode calibration
2915 22:50:01.782647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2916 22:50:01.789543 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2917 22:50:01.792872 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2918 22:50:01.799855 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2919 22:50:01.802638 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 22:50:01.806319 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 22:50:01.810028 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 22:50:01.816121 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 22:50:01.819624 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 22:50:01.823207 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
2925 22:50:01.829799 1 0 0 | B1->B0 | 2d2d 2424 | 0 0 | (0 1) (0 0)
2926 22:50:01.832866 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 22:50:01.836505 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 22:50:01.843066 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 22:50:01.847238 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 22:50:01.849943 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 22:50:01.856842 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2932 22:50:01.859996 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2933 22:50:01.863219 1 1 0 | B1->B0 | 3434 4242 | 0 0 | (0 0) (0 0)
2934 22:50:01.866586 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 22:50:01.873261 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 22:50:01.876741 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 22:50:01.880112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 22:50:01.886918 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 22:50:01.889925 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 22:50:01.893393 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2941 22:50:01.900206 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2942 22:50:01.903390 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2943 22:50:01.907073 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 22:50:01.913908 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 22:50:01.917420 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 22:50:01.920525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 22:50:01.923883 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 22:50:01.930503 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 22:50:01.934509 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 22:50:01.936968 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 22:50:01.944126 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 22:50:01.947629 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 22:50:01.951116 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 22:50:01.957246 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 22:50:01.960617 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2956 22:50:01.964106 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2957 22:50:01.970592 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2958 22:50:01.970704 Total UI for P1: 0, mck2ui 16
2959 22:50:01.974581 best dqsien dly found for B0: ( 1, 3, 26)
2960 22:50:01.980983 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 22:50:01.984253 Total UI for P1: 0, mck2ui 16
2962 22:50:01.987699 best dqsien dly found for B1: ( 1, 4, 0)
2963 22:50:01.991059 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2964 22:50:01.994736 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2965 22:50:01.994830
2966 22:50:01.998159 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2967 22:50:02.000828 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2968 22:50:02.004328 [Gating] SW calibration Done
2969 22:50:02.004423 ==
2970 22:50:02.007776 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 22:50:02.011049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 22:50:02.011140 ==
2973 22:50:02.014686 RX Vref Scan: 0
2974 22:50:02.014776
2975 22:50:02.014841 RX Vref 0 -> 0, step: 1
2976 22:50:02.014903
2977 22:50:02.017490 RX Delay -40 -> 252, step: 8
2978 22:50:02.020955 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2979 22:50:02.027648 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2980 22:50:02.031673 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2981 22:50:02.034474 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2982 22:50:02.037933 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2983 22:50:02.041658 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2984 22:50:02.047970 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2985 22:50:02.051479 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2986 22:50:02.055321 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2987 22:50:02.058029 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2988 22:50:02.061262 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2989 22:50:02.064605 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2990 22:50:02.072063 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2991 22:50:02.075091 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2992 22:50:02.078381 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2993 22:50:02.081347 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2994 22:50:02.081441 ==
2995 22:50:02.084680 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 22:50:02.088259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 22:50:02.091512 ==
2998 22:50:02.091604 DQS Delay:
2999 22:50:02.091669 DQS0 = 0, DQS1 = 0
3000 22:50:02.095528 DQM Delay:
3001 22:50:02.095618 DQM0 = 116, DQM1 = 105
3002 22:50:02.098446 DQ Delay:
3003 22:50:02.101587 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3004 22:50:02.105073 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3005 22:50:02.108314 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3006 22:50:02.112155 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
3007 22:50:02.112249
3008 22:50:02.112316
3009 22:50:02.112376 ==
3010 22:50:02.115037 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 22:50:02.118396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 22:50:02.118487 ==
3013 22:50:02.118553
3014 22:50:02.118613
3015 22:50:02.122630 TX Vref Scan disable
3016 22:50:02.125014 == TX Byte 0 ==
3017 22:50:02.128385 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3018 22:50:02.131857 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3019 22:50:02.135508 == TX Byte 1 ==
3020 22:50:02.138762 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3021 22:50:02.142074 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3022 22:50:02.142167 ==
3023 22:50:02.145401 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 22:50:02.148884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 22:50:02.148974 ==
3026 22:50:02.162178 TX Vref=22, minBit 0, minWin=26, winSum=423
3027 22:50:02.165349 TX Vref=24, minBit 1, minWin=26, winSum=430
3028 22:50:02.168335 TX Vref=26, minBit 12, minWin=26, winSum=432
3029 22:50:02.172355 TX Vref=28, minBit 1, minWin=27, winSum=436
3030 22:50:02.175220 TX Vref=30, minBit 3, minWin=26, winSum=438
3031 22:50:02.181657 TX Vref=32, minBit 12, minWin=26, winSum=436
3032 22:50:02.185093 [TxChooseVref] Worse bit 1, Min win 27, Win sum 436, Final Vref 28
3033 22:50:02.185190
3034 22:50:02.188861 Final TX Range 1 Vref 28
3035 22:50:02.188952
3036 22:50:02.189017 ==
3037 22:50:02.191861 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 22:50:02.195322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 22:50:02.195414 ==
3040 22:50:02.195480
3041 22:50:02.198723
3042 22:50:02.198809 TX Vref Scan disable
3043 22:50:02.202583 == TX Byte 0 ==
3044 22:50:02.205228 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3045 22:50:02.208562 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3046 22:50:02.211904 == TX Byte 1 ==
3047 22:50:02.216002 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3048 22:50:02.218844 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3049 22:50:02.218935
3050 22:50:02.222264 [DATLAT]
3051 22:50:02.222351 Freq=1200, CH0 RK1
3052 22:50:02.222416
3053 22:50:02.226400 DATLAT Default: 0xd
3054 22:50:02.226488 0, 0xFFFF, sum = 0
3055 22:50:02.229607 1, 0xFFFF, sum = 0
3056 22:50:02.229698 2, 0xFFFF, sum = 0
3057 22:50:02.232469 3, 0xFFFF, sum = 0
3058 22:50:02.232556 4, 0xFFFF, sum = 0
3059 22:50:02.235789 5, 0xFFFF, sum = 0
3060 22:50:02.235878 6, 0xFFFF, sum = 0
3061 22:50:02.239256 7, 0xFFFF, sum = 0
3062 22:50:02.239343 8, 0xFFFF, sum = 0
3063 22:50:02.242632 9, 0xFFFF, sum = 0
3064 22:50:02.242718 10, 0xFFFF, sum = 0
3065 22:50:02.246323 11, 0xFFFF, sum = 0
3066 22:50:02.246410 12, 0x0, sum = 1
3067 22:50:02.248975 13, 0x0, sum = 2
3068 22:50:02.249060 14, 0x0, sum = 3
3069 22:50:02.252359 15, 0x0, sum = 4
3070 22:50:02.252446 best_step = 13
3071 22:50:02.252509
3072 22:50:02.252569 ==
3073 22:50:02.255846 Dram Type= 6, Freq= 0, CH_0, rank 1
3074 22:50:02.262443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 22:50:02.262556 ==
3076 22:50:02.262625 RX Vref Scan: 0
3077 22:50:02.262686
3078 22:50:02.265968 RX Vref 0 -> 0, step: 1
3079 22:50:02.266057
3080 22:50:02.269403 RX Delay -21 -> 252, step: 4
3081 22:50:02.272598 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3082 22:50:02.276262 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3083 22:50:02.279634 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3084 22:50:02.286678 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3085 22:50:02.290203 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3086 22:50:02.292785 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3087 22:50:02.296253 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3088 22:50:02.299924 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3089 22:50:02.306188 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3090 22:50:02.309504 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3091 22:50:02.312913 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3092 22:50:02.316209 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3093 22:50:02.319433 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3094 22:50:02.325938 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3095 22:50:02.329644 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3096 22:50:02.332879 iDelay=195, Bit 15, Center 112 (43 ~ 182) 140
3097 22:50:02.332969 ==
3098 22:50:02.336496 Dram Type= 6, Freq= 0, CH_0, rank 1
3099 22:50:02.339646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 22:50:02.339736 ==
3101 22:50:02.342656 DQS Delay:
3102 22:50:02.342740 DQS0 = 0, DQS1 = 0
3103 22:50:02.342805 DQM Delay:
3104 22:50:02.346097 DQM0 = 114, DQM1 = 104
3105 22:50:02.346181 DQ Delay:
3106 22:50:02.349645 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3107 22:50:02.353086 DQ4 =112, DQ5 =106, DQ6 =122, DQ7 =122
3108 22:50:02.356448 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3109 22:50:02.362860 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3110 22:50:02.362962
3111 22:50:02.363030
3112 22:50:02.369766 [DQSOSCAuto] RK1, (LSB)MR18= 0xfff1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3113 22:50:02.373736 CH0 RK1: MR19=303, MR18=FFF1
3114 22:50:02.379670 CH0_RK1: MR19=0x303, MR18=0xFFF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3115 22:50:02.383659 [RxdqsGatingPostProcess] freq 1200
3116 22:50:02.386824 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3117 22:50:02.390177 best DQS0 dly(2T, 0.5T) = (0, 12)
3118 22:50:02.393971 best DQS1 dly(2T, 0.5T) = (0, 12)
3119 22:50:02.396713 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3120 22:50:02.399925 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3121 22:50:02.403437 best DQS0 dly(2T, 0.5T) = (0, 11)
3122 22:50:02.407167 best DQS1 dly(2T, 0.5T) = (0, 12)
3123 22:50:02.410524 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3124 22:50:02.413779 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3125 22:50:02.413871 Pre-setting of DQS Precalculation
3126 22:50:02.420216 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3127 22:50:02.420324 ==
3128 22:50:02.424288 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 22:50:02.427862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 22:50:02.427954 ==
3131 22:50:02.434285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3132 22:50:02.440569 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3133 22:50:02.448111 [CA 0] Center 38 (9~68) winsize 60
3134 22:50:02.451021 [CA 1] Center 38 (8~68) winsize 61
3135 22:50:02.454763 [CA 2] Center 35 (5~65) winsize 61
3136 22:50:02.458102 [CA 3] Center 34 (4~65) winsize 62
3137 22:50:02.461497 [CA 4] Center 34 (4~65) winsize 62
3138 22:50:02.464643 [CA 5] Center 33 (4~63) winsize 60
3139 22:50:02.464735
3140 22:50:02.467484 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3141 22:50:02.467572
3142 22:50:02.471252 [CATrainingPosCal] consider 1 rank data
3143 22:50:02.474620 u2DelayCellTimex100 = 270/100 ps
3144 22:50:02.477609 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3145 22:50:02.480972 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3146 22:50:02.484452 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3147 22:50:02.491609 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3148 22:50:02.494717 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3149 22:50:02.497731 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3150 22:50:02.497839
3151 22:50:02.501082 CA PerBit enable=1, Macro0, CA PI delay=33
3152 22:50:02.501218
3153 22:50:02.504770 [CBTSetCACLKResult] CA Dly = 33
3154 22:50:02.504858 CS Dly: 6 (0~37)
3155 22:50:02.504928 ==
3156 22:50:02.508512 Dram Type= 6, Freq= 0, CH_1, rank 1
3157 22:50:02.514519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3158 22:50:02.514640 ==
3159 22:50:02.518487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3160 22:50:02.524782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3161 22:50:02.533178 [CA 0] Center 38 (8~68) winsize 61
3162 22:50:02.536309 [CA 1] Center 38 (8~68) winsize 61
3163 22:50:02.540284 [CA 2] Center 34 (4~65) winsize 62
3164 22:50:02.543426 [CA 3] Center 34 (4~65) winsize 62
3165 22:50:02.546831 [CA 4] Center 34 (4~65) winsize 62
3166 22:50:02.550078 [CA 5] Center 33 (3~64) winsize 62
3167 22:50:02.550180
3168 22:50:02.553554 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3169 22:50:02.553646
3170 22:50:02.556589 [CATrainingPosCal] consider 2 rank data
3171 22:50:02.559758 u2DelayCellTimex100 = 270/100 ps
3172 22:50:02.563592 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3173 22:50:02.566599 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3174 22:50:02.573454 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3175 22:50:02.576943 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3176 22:50:02.580056 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3177 22:50:02.583672 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3178 22:50:02.583772
3179 22:50:02.586695 CA PerBit enable=1, Macro0, CA PI delay=33
3180 22:50:02.586787
3181 22:50:02.589831 [CBTSetCACLKResult] CA Dly = 33
3182 22:50:02.589922 CS Dly: 7 (0~40)
3183 22:50:02.589988
3184 22:50:02.593140 ----->DramcWriteLeveling(PI) begin...
3185 22:50:02.596817 ==
3186 22:50:02.596917 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 22:50:02.603518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 22:50:02.603624 ==
3189 22:50:02.607670 Write leveling (Byte 0): 25 => 25
3190 22:50:02.610138 Write leveling (Byte 1): 28 => 28
3191 22:50:02.610251 DramcWriteLeveling(PI) end<-----
3192 22:50:02.613529
3193 22:50:02.613622 ==
3194 22:50:02.617367 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 22:50:02.619917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 22:50:02.620007 ==
3197 22:50:02.623619 [Gating] SW mode calibration
3198 22:50:02.630079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3199 22:50:02.633415 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3200 22:50:02.640382 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3201 22:50:02.644855 0 15 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3202 22:50:02.647008 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 22:50:02.653506 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 22:50:02.657087 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 22:50:02.660157 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 22:50:02.667219 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 22:50:02.670264 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3208 22:50:02.673983 1 0 0 | B1->B0 | 2323 2d2d | 0 1 | (1 0) (1 0)
3209 22:50:02.677201 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 22:50:02.684509 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 22:50:02.687436 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3212 22:50:02.690806 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 22:50:02.697149 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 22:50:02.700445 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 22:50:02.704010 1 0 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3216 22:50:02.710837 1 1 0 | B1->B0 | 4343 3535 | 0 0 | (0 0) (1 1)
3217 22:50:02.714172 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 22:50:02.717358 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 22:50:02.724089 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 22:50:02.727270 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 22:50:02.731020 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 22:50:02.734319 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 22:50:02.740906 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3224 22:50:02.744296 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3225 22:50:02.747725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 22:50:02.754053 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 22:50:02.758029 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 22:50:02.761168 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 22:50:02.767682 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 22:50:02.771849 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 22:50:02.774619 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 22:50:02.781107 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 22:50:02.784516 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 22:50:02.787815 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 22:50:02.794750 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 22:50:02.797595 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 22:50:02.801526 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 22:50:02.805167 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 22:50:02.811060 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 22:50:02.814501 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 22:50:02.818074 Total UI for P1: 0, mck2ui 16
3242 22:50:02.821167 best dqsien dly found for B0: ( 1, 3, 30)
3243 22:50:02.824669 Total UI for P1: 0, mck2ui 16
3244 22:50:02.828091 best dqsien dly found for B1: ( 1, 3, 30)
3245 22:50:02.831680 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3246 22:50:02.834640 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3247 22:50:02.834734
3248 22:50:02.838158 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3249 22:50:02.840969 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3250 22:50:02.844451 [Gating] SW calibration Done
3251 22:50:02.844544 ==
3252 22:50:02.847668 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 22:50:02.851108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 22:50:02.854617 ==
3255 22:50:02.854711 RX Vref Scan: 0
3256 22:50:02.854777
3257 22:50:02.858506 RX Vref 0 -> 0, step: 1
3258 22:50:02.858594
3259 22:50:02.861374 RX Delay -40 -> 252, step: 8
3260 22:50:02.864495 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3261 22:50:02.868045 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3262 22:50:02.871736 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3263 22:50:02.875090 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3264 22:50:02.878187 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3265 22:50:02.884737 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3266 22:50:02.888644 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3267 22:50:02.891603 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3268 22:50:02.894962 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3269 22:50:02.898420 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3270 22:50:02.904854 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3271 22:50:02.908592 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3272 22:50:02.912192 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3273 22:50:02.915833 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3274 22:50:02.918341 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3275 22:50:02.925177 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3276 22:50:02.925322 ==
3277 22:50:02.928321 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 22:50:02.931661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 22:50:02.931752 ==
3280 22:50:02.931818 DQS Delay:
3281 22:50:02.935773 DQS0 = 0, DQS1 = 0
3282 22:50:02.935863 DQM Delay:
3283 22:50:02.938867 DQM0 = 115, DQM1 = 109
3284 22:50:02.938953 DQ Delay:
3285 22:50:02.942346 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3286 22:50:02.945749 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111
3287 22:50:02.948866 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3288 22:50:02.951935 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =115
3289 22:50:02.952024
3290 22:50:02.952090
3291 22:50:02.952149 ==
3292 22:50:02.955380 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 22:50:02.962452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 22:50:02.962563 ==
3295 22:50:02.962634
3296 22:50:02.962694
3297 22:50:02.962754 TX Vref Scan disable
3298 22:50:02.965781 == TX Byte 0 ==
3299 22:50:02.968889 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3300 22:50:02.972669 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3301 22:50:02.976053 == TX Byte 1 ==
3302 22:50:02.979371 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3303 22:50:02.982730 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3304 22:50:02.985781 ==
3305 22:50:02.989200 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 22:50:02.992655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 22:50:02.992751 ==
3308 22:50:03.003404 TX Vref=22, minBit 11, minWin=24, winSum=410
3309 22:50:03.006677 TX Vref=24, minBit 2, minWin=25, winSum=417
3310 22:50:03.010049 TX Vref=26, minBit 1, minWin=25, winSum=421
3311 22:50:03.013136 TX Vref=28, minBit 0, minWin=26, winSum=428
3312 22:50:03.017142 TX Vref=30, minBit 1, minWin=26, winSum=430
3313 22:50:03.020205 TX Vref=32, minBit 1, minWin=26, winSum=432
3314 22:50:03.026785 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 32
3315 22:50:03.026895
3316 22:50:03.030453 Final TX Range 1 Vref 32
3317 22:50:03.030544
3318 22:50:03.030611 ==
3319 22:50:03.033424 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 22:50:03.036637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 22:50:03.036734 ==
3322 22:50:03.036801
3323 22:50:03.036861
3324 22:50:03.040079 TX Vref Scan disable
3325 22:50:03.043726 == TX Byte 0 ==
3326 22:50:03.047357 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3327 22:50:03.050402 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3328 22:50:03.053495 == TX Byte 1 ==
3329 22:50:03.057160 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3330 22:50:03.060612 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3331 22:50:03.060704
3332 22:50:03.064449 [DATLAT]
3333 22:50:03.064540 Freq=1200, CH1 RK0
3334 22:50:03.064605
3335 22:50:03.067193 DATLAT Default: 0xd
3336 22:50:03.067279 0, 0xFFFF, sum = 0
3337 22:50:03.070903 1, 0xFFFF, sum = 0
3338 22:50:03.070990 2, 0xFFFF, sum = 0
3339 22:50:03.073865 3, 0xFFFF, sum = 0
3340 22:50:03.073952 4, 0xFFFF, sum = 0
3341 22:50:03.077864 5, 0xFFFF, sum = 0
3342 22:50:03.077952 6, 0xFFFF, sum = 0
3343 22:50:03.080544 7, 0xFFFF, sum = 0
3344 22:50:03.080629 8, 0xFFFF, sum = 0
3345 22:50:03.084563 9, 0xFFFF, sum = 0
3346 22:50:03.084653 10, 0xFFFF, sum = 0
3347 22:50:03.088047 11, 0xFFFF, sum = 0
3348 22:50:03.088134 12, 0x0, sum = 1
3349 22:50:03.090454 13, 0x0, sum = 2
3350 22:50:03.090539 14, 0x0, sum = 3
3351 22:50:03.094216 15, 0x0, sum = 4
3352 22:50:03.094303 best_step = 13
3353 22:50:03.094368
3354 22:50:03.094428 ==
3355 22:50:03.097358 Dram Type= 6, Freq= 0, CH_1, rank 0
3356 22:50:03.103907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3357 22:50:03.104013 ==
3358 22:50:03.104081 RX Vref Scan: 1
3359 22:50:03.104142
3360 22:50:03.107663 Set Vref Range= 32 -> 127
3361 22:50:03.107760
3362 22:50:03.110938 RX Vref 32 -> 127, step: 1
3363 22:50:03.111027
3364 22:50:03.111093 RX Delay -21 -> 252, step: 4
3365 22:50:03.111153
3366 22:50:03.114093 Set Vref, RX VrefLevel [Byte0]: 32
3367 22:50:03.117471 [Byte1]: 32
3368 22:50:03.121491
3369 22:50:03.121587 Set Vref, RX VrefLevel [Byte0]: 33
3370 22:50:03.125107 [Byte1]: 33
3371 22:50:03.129475
3372 22:50:03.129575 Set Vref, RX VrefLevel [Byte0]: 34
3373 22:50:03.133435 [Byte1]: 34
3374 22:50:03.137795
3375 22:50:03.137889 Set Vref, RX VrefLevel [Byte0]: 35
3376 22:50:03.141465 [Byte1]: 35
3377 22:50:03.145407
3378 22:50:03.145500 Set Vref, RX VrefLevel [Byte0]: 36
3379 22:50:03.148596 [Byte1]: 36
3380 22:50:03.153179
3381 22:50:03.153351 Set Vref, RX VrefLevel [Byte0]: 37
3382 22:50:03.156607 [Byte1]: 37
3383 22:50:03.161599
3384 22:50:03.161701 Set Vref, RX VrefLevel [Byte0]: 38
3385 22:50:03.164826 [Byte1]: 38
3386 22:50:03.170146
3387 22:50:03.170247 Set Vref, RX VrefLevel [Byte0]: 39
3388 22:50:03.172816 [Byte1]: 39
3389 22:50:03.177829
3390 22:50:03.177929 Set Vref, RX VrefLevel [Byte0]: 40
3391 22:50:03.180494 [Byte1]: 40
3392 22:50:03.184842
3393 22:50:03.184934 Set Vref, RX VrefLevel [Byte0]: 41
3394 22:50:03.188505 [Byte1]: 41
3395 22:50:03.193139
3396 22:50:03.193275 Set Vref, RX VrefLevel [Byte0]: 42
3397 22:50:03.196312 [Byte1]: 42
3398 22:50:03.201197
3399 22:50:03.201304 Set Vref, RX VrefLevel [Byte0]: 43
3400 22:50:03.204391 [Byte1]: 43
3401 22:50:03.209094
3402 22:50:03.209188 Set Vref, RX VrefLevel [Byte0]: 44
3403 22:50:03.212089 [Byte1]: 44
3404 22:50:03.217233
3405 22:50:03.217346 Set Vref, RX VrefLevel [Byte0]: 45
3406 22:50:03.219920 [Byte1]: 45
3407 22:50:03.225179
3408 22:50:03.225324 Set Vref, RX VrefLevel [Byte0]: 46
3409 22:50:03.228111 [Byte1]: 46
3410 22:50:03.232753
3411 22:50:03.232851 Set Vref, RX VrefLevel [Byte0]: 47
3412 22:50:03.235715 [Byte1]: 47
3413 22:50:03.240439
3414 22:50:03.240536 Set Vref, RX VrefLevel [Byte0]: 48
3415 22:50:03.243716 [Byte1]: 48
3416 22:50:03.248453
3417 22:50:03.248554 Set Vref, RX VrefLevel [Byte0]: 49
3418 22:50:03.252620 [Byte1]: 49
3419 22:50:03.256400
3420 22:50:03.256494 Set Vref, RX VrefLevel [Byte0]: 50
3421 22:50:03.259870 [Byte1]: 50
3422 22:50:03.264486
3423 22:50:03.264585 Set Vref, RX VrefLevel [Byte0]: 51
3424 22:50:03.267846 [Byte1]: 51
3425 22:50:03.272325
3426 22:50:03.272422 Set Vref, RX VrefLevel [Byte0]: 52
3427 22:50:03.276308 [Byte1]: 52
3428 22:50:03.280055
3429 22:50:03.280150 Set Vref, RX VrefLevel [Byte0]: 53
3430 22:50:03.283459 [Byte1]: 53
3431 22:50:03.288273
3432 22:50:03.288374 Set Vref, RX VrefLevel [Byte0]: 54
3433 22:50:03.291238 [Byte1]: 54
3434 22:50:03.296146
3435 22:50:03.296248 Set Vref, RX VrefLevel [Byte0]: 55
3436 22:50:03.299442 [Byte1]: 55
3437 22:50:03.303661
3438 22:50:03.303755 Set Vref, RX VrefLevel [Byte0]: 56
3439 22:50:03.307228 [Byte1]: 56
3440 22:50:03.311728
3441 22:50:03.311823 Set Vref, RX VrefLevel [Byte0]: 57
3442 22:50:03.315220 [Byte1]: 57
3443 22:50:03.319773
3444 22:50:03.319877 Set Vref, RX VrefLevel [Byte0]: 58
3445 22:50:03.322848 [Byte1]: 58
3446 22:50:03.327712
3447 22:50:03.327812 Set Vref, RX VrefLevel [Byte0]: 59
3448 22:50:03.330883 [Byte1]: 59
3449 22:50:03.335469
3450 22:50:03.335565 Set Vref, RX VrefLevel [Byte0]: 60
3451 22:50:03.338939 [Byte1]: 60
3452 22:50:03.344043
3453 22:50:03.344146 Set Vref, RX VrefLevel [Byte0]: 61
3454 22:50:03.346828 [Byte1]: 61
3455 22:50:03.351490
3456 22:50:03.351584 Set Vref, RX VrefLevel [Byte0]: 62
3457 22:50:03.355308 [Byte1]: 62
3458 22:50:03.359248
3459 22:50:03.359342 Set Vref, RX VrefLevel [Byte0]: 63
3460 22:50:03.362565 [Byte1]: 63
3461 22:50:03.367734
3462 22:50:03.367854 Set Vref, RX VrefLevel [Byte0]: 64
3463 22:50:03.370411 [Byte1]: 64
3464 22:50:03.375130
3465 22:50:03.375231 Set Vref, RX VrefLevel [Byte0]: 65
3466 22:50:03.378898 [Byte1]: 65
3467 22:50:03.383077
3468 22:50:03.383175 Set Vref, RX VrefLevel [Byte0]: 66
3469 22:50:03.386477 [Byte1]: 66
3470 22:50:03.391157
3471 22:50:03.391259 Set Vref, RX VrefLevel [Byte0]: 67
3472 22:50:03.394595 [Byte1]: 67
3473 22:50:03.399246
3474 22:50:03.399346 Set Vref, RX VrefLevel [Byte0]: 68
3475 22:50:03.402427 [Byte1]: 68
3476 22:50:03.407867
3477 22:50:03.407970 Set Vref, RX VrefLevel [Byte0]: 69
3478 22:50:03.409921 [Byte1]: 69
3479 22:50:03.415608
3480 22:50:03.415708 Set Vref, RX VrefLevel [Byte0]: 70
3481 22:50:03.418320 [Byte1]: 70
3482 22:50:03.422688
3483 22:50:03.422785 Set Vref, RX VrefLevel [Byte0]: 71
3484 22:50:03.426596 [Byte1]: 71
3485 22:50:03.430857
3486 22:50:03.430956 Final RX Vref Byte 0 = 54 to rank0
3487 22:50:03.433963 Final RX Vref Byte 1 = 54 to rank0
3488 22:50:03.437386 Final RX Vref Byte 0 = 54 to rank1
3489 22:50:03.440649 Final RX Vref Byte 1 = 54 to rank1==
3490 22:50:03.444141 Dram Type= 6, Freq= 0, CH_1, rank 0
3491 22:50:03.451350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 22:50:03.451464 ==
3493 22:50:03.451531 DQS Delay:
3494 22:50:03.451591 DQS0 = 0, DQS1 = 0
3495 22:50:03.454672 DQM Delay:
3496 22:50:03.454756 DQM0 = 115, DQM1 = 109
3497 22:50:03.457225 DQ Delay:
3498 22:50:03.460854 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =114
3499 22:50:03.464085 DQ4 =116, DQ5 =122, DQ6 =128, DQ7 =112
3500 22:50:03.467513 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3501 22:50:03.471062 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3502 22:50:03.471155
3503 22:50:03.471219
3504 22:50:03.477844 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3505 22:50:03.480868 CH1 RK0: MR19=303, MR18=FEE3
3506 22:50:03.488432 CH1_RK0: MR19=0x303, MR18=0xFEE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3507 22:50:03.488555
3508 22:50:03.491225 ----->DramcWriteLeveling(PI) begin...
3509 22:50:03.491317 ==
3510 22:50:03.494418 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 22:50:03.497569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 22:50:03.497660 ==
3513 22:50:03.501007 Write leveling (Byte 0): 26 => 26
3514 22:50:03.504435 Write leveling (Byte 1): 28 => 28
3515 22:50:03.507846 DramcWriteLeveling(PI) end<-----
3516 22:50:03.507946
3517 22:50:03.508013 ==
3518 22:50:03.511350 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 22:50:03.514760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 22:50:03.514851 ==
3521 22:50:03.518512 [Gating] SW mode calibration
3522 22:50:03.525112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3523 22:50:03.532311 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3524 22:50:03.535179 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 22:50:03.538178 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 22:50:03.544762 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 22:50:03.548283 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 22:50:03.551485 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 22:50:03.558255 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 22:50:03.562085 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
3531 22:50:03.565096 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3532 22:50:03.571940 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 22:50:03.575199 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 22:50:03.578160 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 22:50:03.585366 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 22:50:03.588216 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 22:50:03.591628 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3538 22:50:03.598155 1 0 24 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
3539 22:50:03.601443 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3540 22:50:03.604724 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 22:50:03.611554 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 22:50:03.614777 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 22:50:03.618043 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 22:50:03.624665 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 22:50:03.628363 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3546 22:50:03.631879 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3547 22:50:03.635362 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3548 22:50:03.641809 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 22:50:03.645081 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 22:50:03.648261 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 22:50:03.654938 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 22:50:03.658314 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 22:50:03.661769 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 22:50:03.668078 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 22:50:03.671649 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 22:50:03.675372 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 22:50:03.681934 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 22:50:03.684823 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 22:50:03.688165 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 22:50:03.694631 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 22:50:03.698296 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3562 22:50:03.701394 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3563 22:50:03.708061 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3564 22:50:03.708181 Total UI for P1: 0, mck2ui 16
3565 22:50:03.714715 best dqsien dly found for B0: ( 1, 3, 22)
3566 22:50:03.718618 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 22:50:03.721670 Total UI for P1: 0, mck2ui 16
3568 22:50:03.724637 best dqsien dly found for B1: ( 1, 3, 28)
3569 22:50:03.728117 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3570 22:50:03.731488 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3571 22:50:03.731583
3572 22:50:03.734858 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3573 22:50:03.738265 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3574 22:50:03.741249 [Gating] SW calibration Done
3575 22:50:03.741354 ==
3576 22:50:03.744671 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 22:50:03.748401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 22:50:03.748492 ==
3579 22:50:03.751560 RX Vref Scan: 0
3580 22:50:03.751648
3581 22:50:03.754834 RX Vref 0 -> 0, step: 1
3582 22:50:03.754925
3583 22:50:03.754991 RX Delay -40 -> 252, step: 8
3584 22:50:03.762213 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3585 22:50:03.764922 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3586 22:50:03.768133 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3587 22:50:03.771527 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3588 22:50:03.775260 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3589 22:50:03.781758 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3590 22:50:03.785129 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3591 22:50:03.788337 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3592 22:50:03.792132 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3593 22:50:03.795362 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3594 22:50:03.798499 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3595 22:50:03.804913 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3596 22:50:03.808481 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3597 22:50:03.811835 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3598 22:50:03.815381 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3599 22:50:03.821721 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3600 22:50:03.821836 ==
3601 22:50:03.825406 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 22:50:03.828280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 22:50:03.828368 ==
3604 22:50:03.828492 DQS Delay:
3605 22:50:03.831826 DQS0 = 0, DQS1 = 0
3606 22:50:03.831912 DQM Delay:
3607 22:50:03.835393 DQM0 = 113, DQM1 = 111
3608 22:50:03.835510 DQ Delay:
3609 22:50:03.838475 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3610 22:50:03.841618 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3611 22:50:03.845488 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3612 22:50:03.848578 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3613 22:50:03.848670
3614 22:50:03.848736
3615 22:50:03.848795 ==
3616 22:50:03.851917 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 22:50:03.858238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 22:50:03.858348 ==
3619 22:50:03.858417
3620 22:50:03.858478
3621 22:50:03.858536 TX Vref Scan disable
3622 22:50:03.861751 == TX Byte 0 ==
3623 22:50:03.865257 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3624 22:50:03.868880 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3625 22:50:03.871837 == TX Byte 1 ==
3626 22:50:03.875480 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3627 22:50:03.878968 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3628 22:50:03.881990 ==
3629 22:50:03.885369 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 22:50:03.888779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 22:50:03.888875 ==
3632 22:50:03.900061 TX Vref=22, minBit 1, minWin=25, winSum=417
3633 22:50:03.903366 TX Vref=24, minBit 2, minWin=25, winSum=419
3634 22:50:03.906448 TX Vref=26, minBit 0, minWin=26, winSum=430
3635 22:50:03.910067 TX Vref=28, minBit 1, minWin=25, winSum=431
3636 22:50:03.913204 TX Vref=30, minBit 4, minWin=26, winSum=434
3637 22:50:03.916469 TX Vref=32, minBit 1, minWin=26, winSum=436
3638 22:50:03.923161 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 32
3639 22:50:03.923278
3640 22:50:03.926521 Final TX Range 1 Vref 32
3641 22:50:03.926606
3642 22:50:03.926671 ==
3643 22:50:03.929704 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 22:50:03.932829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 22:50:03.932941 ==
3646 22:50:03.936102
3647 22:50:03.936213
3648 22:50:03.936306 TX Vref Scan disable
3649 22:50:03.939727 == TX Byte 0 ==
3650 22:50:03.942928 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3651 22:50:03.946636 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3652 22:50:03.949737 == TX Byte 1 ==
3653 22:50:03.952976 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3654 22:50:03.956767 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3655 22:50:03.956870
3656 22:50:03.959436 [DATLAT]
3657 22:50:03.959522 Freq=1200, CH1 RK1
3658 22:50:03.959609
3659 22:50:03.962881 DATLAT Default: 0xd
3660 22:50:03.962968 0, 0xFFFF, sum = 0
3661 22:50:03.966184 1, 0xFFFF, sum = 0
3662 22:50:03.966274 2, 0xFFFF, sum = 0
3663 22:50:03.969488 3, 0xFFFF, sum = 0
3664 22:50:03.969579 4, 0xFFFF, sum = 0
3665 22:50:03.973550 5, 0xFFFF, sum = 0
3666 22:50:03.973641 6, 0xFFFF, sum = 0
3667 22:50:03.976113 7, 0xFFFF, sum = 0
3668 22:50:03.979739 8, 0xFFFF, sum = 0
3669 22:50:03.979831 9, 0xFFFF, sum = 0
3670 22:50:03.983075 10, 0xFFFF, sum = 0
3671 22:50:03.983164 11, 0xFFFF, sum = 0
3672 22:50:03.986450 12, 0x0, sum = 1
3673 22:50:03.986539 13, 0x0, sum = 2
3674 22:50:03.989612 14, 0x0, sum = 3
3675 22:50:03.989700 15, 0x0, sum = 4
3676 22:50:03.989788 best_step = 13
3677 22:50:03.989868
3678 22:50:03.992820 ==
3679 22:50:03.996527 Dram Type= 6, Freq= 0, CH_1, rank 1
3680 22:50:03.999622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3681 22:50:03.999716 ==
3682 22:50:03.999802 RX Vref Scan: 0
3683 22:50:03.999882
3684 22:50:04.003313 RX Vref 0 -> 0, step: 1
3685 22:50:04.003400
3686 22:50:04.007000 RX Delay -21 -> 252, step: 4
3687 22:50:04.010059 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3688 22:50:04.016185 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3689 22:50:04.019500 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3690 22:50:04.022914 iDelay=191, Bit 3, Center 110 (43 ~ 178) 136
3691 22:50:04.026138 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3692 22:50:04.029736 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3693 22:50:04.032900 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3694 22:50:04.039804 iDelay=191, Bit 7, Center 110 (43 ~ 178) 136
3695 22:50:04.043334 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3696 22:50:04.046418 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3697 22:50:04.050049 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3698 22:50:04.052938 iDelay=191, Bit 11, Center 104 (39 ~ 170) 132
3699 22:50:04.059496 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3700 22:50:04.062878 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3701 22:50:04.066038 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3702 22:50:04.069528 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3703 22:50:04.069621 ==
3704 22:50:04.073096 Dram Type= 6, Freq= 0, CH_1, rank 1
3705 22:50:04.079745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3706 22:50:04.079858 ==
3707 22:50:04.079947 DQS Delay:
3708 22:50:04.083361 DQS0 = 0, DQS1 = 0
3709 22:50:04.083448 DQM Delay:
3710 22:50:04.083534 DQM0 = 113, DQM1 = 110
3711 22:50:04.086510 DQ Delay:
3712 22:50:04.089562 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =110
3713 22:50:04.092897 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3714 22:50:04.096127 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =104
3715 22:50:04.099421 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =120
3716 22:50:04.099524
3717 22:50:04.099611
3718 22:50:04.110077 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 414 ps
3719 22:50:04.110202 CH1 RK1: MR19=303, MR18=F6FE
3720 22:50:04.116475 CH1_RK1: MR19=0x303, MR18=0xF6FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3721 22:50:04.120218 [RxdqsGatingPostProcess] freq 1200
3722 22:50:04.126394 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3723 22:50:04.129594 best DQS0 dly(2T, 0.5T) = (0, 11)
3724 22:50:04.132934 best DQS1 dly(2T, 0.5T) = (0, 11)
3725 22:50:04.136436 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3726 22:50:04.136530 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3727 22:50:04.140518 best DQS0 dly(2T, 0.5T) = (0, 11)
3728 22:50:04.143329 best DQS1 dly(2T, 0.5T) = (0, 11)
3729 22:50:04.146767 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3730 22:50:04.149988 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3731 22:50:04.153263 Pre-setting of DQS Precalculation
3732 22:50:04.159773 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3733 22:50:04.166323 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3734 22:50:04.173184 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3735 22:50:04.173326
3736 22:50:04.173419
3737 22:50:04.176317 [Calibration Summary] 2400 Mbps
3738 22:50:04.176404 CH 0, Rank 0
3739 22:50:04.180330 SW Impedance : PASS
3740 22:50:04.183194 DUTY Scan : NO K
3741 22:50:04.183283 ZQ Calibration : PASS
3742 22:50:04.186302 Jitter Meter : NO K
3743 22:50:04.189695 CBT Training : PASS
3744 22:50:04.189787 Write leveling : PASS
3745 22:50:04.193410 RX DQS gating : PASS
3746 22:50:04.193504 RX DQ/DQS(RDDQC) : PASS
3747 22:50:04.197070 TX DQ/DQS : PASS
3748 22:50:04.199698 RX DATLAT : PASS
3749 22:50:04.199789 RX DQ/DQS(Engine): PASS
3750 22:50:04.202780 TX OE : NO K
3751 22:50:04.202868 All Pass.
3752 22:50:04.202954
3753 22:50:04.206759 CH 0, Rank 1
3754 22:50:04.206849 SW Impedance : PASS
3755 22:50:04.209902 DUTY Scan : NO K
3756 22:50:04.212714 ZQ Calibration : PASS
3757 22:50:04.212803 Jitter Meter : NO K
3758 22:50:04.216390 CBT Training : PASS
3759 22:50:04.219635 Write leveling : PASS
3760 22:50:04.219728 RX DQS gating : PASS
3761 22:50:04.223078 RX DQ/DQS(RDDQC) : PASS
3762 22:50:04.226167 TX DQ/DQS : PASS
3763 22:50:04.226257 RX DATLAT : PASS
3764 22:50:04.229652 RX DQ/DQS(Engine): PASS
3765 22:50:04.232992 TX OE : NO K
3766 22:50:04.233081 All Pass.
3767 22:50:04.233183
3768 22:50:04.233304 CH 1, Rank 0
3769 22:50:04.236043 SW Impedance : PASS
3770 22:50:04.239576 DUTY Scan : NO K
3771 22:50:04.239663 ZQ Calibration : PASS
3772 22:50:04.243610 Jitter Meter : NO K
3773 22:50:04.246035 CBT Training : PASS
3774 22:50:04.246123 Write leveling : PASS
3775 22:50:04.249850 RX DQS gating : PASS
3776 22:50:04.249938 RX DQ/DQS(RDDQC) : PASS
3777 22:50:04.253191 TX DQ/DQS : PASS
3778 22:50:04.256508 RX DATLAT : PASS
3779 22:50:04.256600 RX DQ/DQS(Engine): PASS
3780 22:50:04.259810 TX OE : NO K
3781 22:50:04.259897 All Pass.
3782 22:50:04.259983
3783 22:50:04.262840 CH 1, Rank 1
3784 22:50:04.262926 SW Impedance : PASS
3785 22:50:04.266945 DUTY Scan : NO K
3786 22:50:04.269986 ZQ Calibration : PASS
3787 22:50:04.270074 Jitter Meter : NO K
3788 22:50:04.273037 CBT Training : PASS
3789 22:50:04.276424 Write leveling : PASS
3790 22:50:04.276514 RX DQS gating : PASS
3791 22:50:04.279902 RX DQ/DQS(RDDQC) : PASS
3792 22:50:04.283085 TX DQ/DQS : PASS
3793 22:50:04.283176 RX DATLAT : PASS
3794 22:50:04.286714 RX DQ/DQS(Engine): PASS
3795 22:50:04.286800 TX OE : NO K
3796 22:50:04.289737 All Pass.
3797 22:50:04.289824
3798 22:50:04.289909 DramC Write-DBI off
3799 22:50:04.292777 PER_BANK_REFRESH: Hybrid Mode
3800 22:50:04.296291 TX_TRACKING: ON
3801 22:50:04.303059 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3802 22:50:04.306471 [FAST_K] Save calibration result to emmc
3803 22:50:04.309553 dramc_set_vcore_voltage set vcore to 650000
3804 22:50:04.313191 Read voltage for 600, 5
3805 22:50:04.313329 Vio18 = 0
3806 22:50:04.316230 Vcore = 650000
3807 22:50:04.316318 Vdram = 0
3808 22:50:04.316403 Vddq = 0
3809 22:50:04.319681 Vmddr = 0
3810 22:50:04.323169 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3811 22:50:04.329753 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3812 22:50:04.329864 MEM_TYPE=3, freq_sel=19
3813 22:50:04.332737 sv_algorithm_assistance_LP4_1600
3814 22:50:04.339716 ============ PULL DRAM RESETB DOWN ============
3815 22:50:04.343374 ========== PULL DRAM RESETB DOWN end =========
3816 22:50:04.346457 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3817 22:50:04.349476 ===================================
3818 22:50:04.352941 LPDDR4 DRAM CONFIGURATION
3819 22:50:04.356504 ===================================
3820 22:50:04.356598 EX_ROW_EN[0] = 0x0
3821 22:50:04.360241 EX_ROW_EN[1] = 0x0
3822 22:50:04.363739 LP4Y_EN = 0x0
3823 22:50:04.363829 WORK_FSP = 0x0
3824 22:50:04.366689 WL = 0x2
3825 22:50:04.366776 RL = 0x2
3826 22:50:04.370141 BL = 0x2
3827 22:50:04.370228 RPST = 0x0
3828 22:50:04.373514 RD_PRE = 0x0
3829 22:50:04.373604 WR_PRE = 0x1
3830 22:50:04.376388 WR_PST = 0x0
3831 22:50:04.376475 DBI_WR = 0x0
3832 22:50:04.380123 DBI_RD = 0x0
3833 22:50:04.380214 OTF = 0x1
3834 22:50:04.383335 ===================================
3835 22:50:04.386719 ===================================
3836 22:50:04.389681 ANA top config
3837 22:50:04.392967 ===================================
3838 22:50:04.393057 DLL_ASYNC_EN = 0
3839 22:50:04.396751 ALL_SLAVE_EN = 1
3840 22:50:04.399942 NEW_RANK_MODE = 1
3841 22:50:04.403767 DLL_IDLE_MODE = 1
3842 22:50:04.406426 LP45_APHY_COMB_EN = 1
3843 22:50:04.406516 TX_ODT_DIS = 1
3844 22:50:04.409648 NEW_8X_MODE = 1
3845 22:50:04.413511 ===================================
3846 22:50:04.416710 ===================================
3847 22:50:04.419996 data_rate = 1200
3848 22:50:04.423293 CKR = 1
3849 22:50:04.426304 DQ_P2S_RATIO = 8
3850 22:50:04.429674 ===================================
3851 22:50:04.429772 CA_P2S_RATIO = 8
3852 22:50:04.433049 DQ_CA_OPEN = 0
3853 22:50:04.436672 DQ_SEMI_OPEN = 0
3854 22:50:04.440056 CA_SEMI_OPEN = 0
3855 22:50:04.443444 CA_FULL_RATE = 0
3856 22:50:04.446380 DQ_CKDIV4_EN = 1
3857 22:50:04.446470 CA_CKDIV4_EN = 1
3858 22:50:04.449810 CA_PREDIV_EN = 0
3859 22:50:04.453032 PH8_DLY = 0
3860 22:50:04.456259 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3861 22:50:04.459740 DQ_AAMCK_DIV = 4
3862 22:50:04.462916 CA_AAMCK_DIV = 4
3863 22:50:04.463005 CA_ADMCK_DIV = 4
3864 22:50:04.466187 DQ_TRACK_CA_EN = 0
3865 22:50:04.470092 CA_PICK = 600
3866 22:50:04.473429 CA_MCKIO = 600
3867 22:50:04.476100 MCKIO_SEMI = 0
3868 22:50:04.479863 PLL_FREQ = 2288
3869 22:50:04.482832 DQ_UI_PI_RATIO = 32
3870 22:50:04.482923 CA_UI_PI_RATIO = 0
3871 22:50:04.486481 ===================================
3872 22:50:04.490210 ===================================
3873 22:50:04.492976 memory_type:LPDDR4
3874 22:50:04.496743 GP_NUM : 10
3875 22:50:04.496836 SRAM_EN : 1
3876 22:50:04.499353 MD32_EN : 0
3877 22:50:04.502859 ===================================
3878 22:50:04.506390 [ANA_INIT] >>>>>>>>>>>>>>
3879 22:50:04.506483 <<<<<< [CONFIGURE PHASE]: ANA_TX
3880 22:50:04.512916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3881 22:50:04.513016 ===================================
3882 22:50:04.516079 data_rate = 1200,PCW = 0X5800
3883 22:50:04.519471 ===================================
3884 22:50:04.522813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3885 22:50:04.529704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3886 22:50:04.536115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3887 22:50:04.539346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3888 22:50:04.542649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3889 22:50:04.546751 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3890 22:50:04.549689 [ANA_INIT] flow start
3891 22:50:04.549781 [ANA_INIT] PLL >>>>>>>>
3892 22:50:04.552835 [ANA_INIT] PLL <<<<<<<<
3893 22:50:04.556536 [ANA_INIT] MIDPI >>>>>>>>
3894 22:50:04.556631 [ANA_INIT] MIDPI <<<<<<<<
3895 22:50:04.559778 [ANA_INIT] DLL >>>>>>>>
3896 22:50:04.562797 [ANA_INIT] flow end
3897 22:50:04.566582 ============ LP4 DIFF to SE enter ============
3898 22:50:04.570076 ============ LP4 DIFF to SE exit ============
3899 22:50:04.573637 [ANA_INIT] <<<<<<<<<<<<<
3900 22:50:04.576592 [Flow] Enable top DCM control >>>>>
3901 22:50:04.579449 [Flow] Enable top DCM control <<<<<
3902 22:50:04.583139 Enable DLL master slave shuffle
3903 22:50:04.586108 ==============================================================
3904 22:50:04.589729 Gating Mode config
3905 22:50:04.596546 ==============================================================
3906 22:50:04.596662 Config description:
3907 22:50:04.606518 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3908 22:50:04.612846 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3909 22:50:04.617197 SELPH_MODE 0: By rank 1: By Phase
3910 22:50:04.623234 ==============================================================
3911 22:50:04.626292 GAT_TRACK_EN = 1
3912 22:50:04.629649 RX_GATING_MODE = 2
3913 22:50:04.633113 RX_GATING_TRACK_MODE = 2
3914 22:50:04.636499 SELPH_MODE = 1
3915 22:50:04.640077 PICG_EARLY_EN = 1
3916 22:50:04.643339 VALID_LAT_VALUE = 1
3917 22:50:04.646187 ==============================================================
3918 22:50:04.650243 Enter into Gating configuration >>>>
3919 22:50:04.653022 Exit from Gating configuration <<<<
3920 22:50:04.656362 Enter into DVFS_PRE_config >>>>>
3921 22:50:04.666198 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3922 22:50:04.669622 Exit from DVFS_PRE_config <<<<<
3923 22:50:04.672938 Enter into PICG configuration >>>>
3924 22:50:04.676759 Exit from PICG configuration <<<<
3925 22:50:04.679789 [RX_INPUT] configuration >>>>>
3926 22:50:04.683321 [RX_INPUT] configuration <<<<<
3927 22:50:04.686985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3928 22:50:04.693075 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3929 22:50:04.699795 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3930 22:50:04.706990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3931 22:50:04.713587 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3932 22:50:04.716526 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3933 22:50:04.723412 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3934 22:50:04.726495 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3935 22:50:04.729886 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3936 22:50:04.734116 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3937 22:50:04.739771 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3938 22:50:04.743179 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3939 22:50:04.747611 ===================================
3940 22:50:04.749894 LPDDR4 DRAM CONFIGURATION
3941 22:50:04.753974 ===================================
3942 22:50:04.754073 EX_ROW_EN[0] = 0x0
3943 22:50:04.756835 EX_ROW_EN[1] = 0x0
3944 22:50:04.756922 LP4Y_EN = 0x0
3945 22:50:04.760010 WORK_FSP = 0x0
3946 22:50:04.760095 WL = 0x2
3947 22:50:04.763344 RL = 0x2
3948 22:50:04.763433 BL = 0x2
3949 22:50:04.766854 RPST = 0x0
3950 22:50:04.766943 RD_PRE = 0x0
3951 22:50:04.770522 WR_PRE = 0x1
3952 22:50:04.770611 WR_PST = 0x0
3953 22:50:04.773788 DBI_WR = 0x0
3954 22:50:04.773874 DBI_RD = 0x0
3955 22:50:04.776572 OTF = 0x1
3956 22:50:04.779836 ===================================
3957 22:50:04.783153 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3958 22:50:04.786721 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3959 22:50:04.793523 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3960 22:50:04.797178 ===================================
3961 22:50:04.797320 LPDDR4 DRAM CONFIGURATION
3962 22:50:04.800048 ===================================
3963 22:50:04.803247 EX_ROW_EN[0] = 0x10
3964 22:50:04.806742 EX_ROW_EN[1] = 0x0
3965 22:50:04.806834 LP4Y_EN = 0x0
3966 22:50:04.810452 WORK_FSP = 0x0
3967 22:50:04.810541 WL = 0x2
3968 22:50:04.813777 RL = 0x2
3969 22:50:04.813864 BL = 0x2
3970 22:50:04.817435 RPST = 0x0
3971 22:50:04.817526 RD_PRE = 0x0
3972 22:50:04.820297 WR_PRE = 0x1
3973 22:50:04.820384 WR_PST = 0x0
3974 22:50:04.823535 DBI_WR = 0x0
3975 22:50:04.823621 DBI_RD = 0x0
3976 22:50:04.826924 OTF = 0x1
3977 22:50:04.830832 ===================================
3978 22:50:04.836977 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3979 22:50:04.840768 nWR fixed to 30
3980 22:50:04.840867 [ModeRegInit_LP4] CH0 RK0
3981 22:50:04.843506 [ModeRegInit_LP4] CH0 RK1
3982 22:50:04.846848 [ModeRegInit_LP4] CH1 RK0
3983 22:50:04.846939 [ModeRegInit_LP4] CH1 RK1
3984 22:50:04.850290 match AC timing 17
3985 22:50:04.853347 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3986 22:50:04.856649 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3987 22:50:04.863336 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3988 22:50:04.866715 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3989 22:50:04.873648 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3990 22:50:04.873765 ==
3991 22:50:04.876815 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 22:50:04.880409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 22:50:04.880499 ==
3994 22:50:04.886730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3995 22:50:04.893121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3996 22:50:04.896757 [CA 0] Center 36 (6~66) winsize 61
3997 22:50:04.900006 [CA 1] Center 36 (6~66) winsize 61
3998 22:50:04.903331 [CA 2] Center 34 (4~65) winsize 62
3999 22:50:04.906915 [CA 3] Center 34 (4~64) winsize 61
4000 22:50:04.910086 [CA 4] Center 34 (4~64) winsize 61
4001 22:50:04.910177 [CA 5] Center 33 (3~64) winsize 62
4002 22:50:04.913083
4003 22:50:04.917688 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4004 22:50:04.917788
4005 22:50:04.919937 [CATrainingPosCal] consider 1 rank data
4006 22:50:04.923440 u2DelayCellTimex100 = 270/100 ps
4007 22:50:04.926788 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4008 22:50:04.929982 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4009 22:50:04.933324 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4010 22:50:04.936904 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4011 22:50:04.940146 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4012 22:50:04.943434 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 22:50:04.943515
4014 22:50:04.946700 CA PerBit enable=1, Macro0, CA PI delay=33
4015 22:50:04.946782
4016 22:50:04.950381 [CBTSetCACLKResult] CA Dly = 33
4017 22:50:04.953586 CS Dly: 4 (0~35)
4018 22:50:04.953669 ==
4019 22:50:04.957499 Dram Type= 6, Freq= 0, CH_0, rank 1
4020 22:50:04.960418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 22:50:04.960503 ==
4022 22:50:04.967418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4023 22:50:04.970455 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4024 22:50:04.974577 [CA 0] Center 36 (6~67) winsize 62
4025 22:50:04.977890 [CA 1] Center 36 (6~66) winsize 61
4026 22:50:04.981324 [CA 2] Center 34 (4~65) winsize 62
4027 22:50:04.984542 [CA 3] Center 34 (4~64) winsize 61
4028 22:50:04.987786 [CA 4] Center 33 (3~64) winsize 62
4029 22:50:04.991650 [CA 5] Center 33 (3~64) winsize 62
4030 22:50:04.991738
4031 22:50:04.994576 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4032 22:50:04.994658
4033 22:50:04.998512 [CATrainingPosCal] consider 2 rank data
4034 22:50:05.001177 u2DelayCellTimex100 = 270/100 ps
4035 22:50:05.005015 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4036 22:50:05.008108 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4037 22:50:05.014815 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4038 22:50:05.017918 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4039 22:50:05.021541 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4040 22:50:05.024723 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4041 22:50:05.024805
4042 22:50:05.028803 CA PerBit enable=1, Macro0, CA PI delay=33
4043 22:50:05.028884
4044 22:50:05.031454 [CBTSetCACLKResult] CA Dly = 33
4045 22:50:05.031536 CS Dly: 4 (0~36)
4046 22:50:05.031600
4047 22:50:05.034652 ----->DramcWriteLeveling(PI) begin...
4048 22:50:05.037953 ==
4049 22:50:05.038035 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 22:50:05.044825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 22:50:05.044907 ==
4052 22:50:05.048607 Write leveling (Byte 0): 33 => 33
4053 22:50:05.052057 Write leveling (Byte 1): 29 => 29
4054 22:50:05.052138 DramcWriteLeveling(PI) end<-----
4055 22:50:05.054853
4056 22:50:05.054934 ==
4057 22:50:05.058045 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 22:50:05.061752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 22:50:05.061833 ==
4060 22:50:05.064860 [Gating] SW mode calibration
4061 22:50:05.072395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4062 22:50:05.075198 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4063 22:50:05.081572 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4064 22:50:05.084864 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4065 22:50:05.088353 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4066 22:50:05.094725 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 22:50:05.098610 0 9 16 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (0 0)
4068 22:50:05.101422 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 22:50:05.108267 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 22:50:05.111954 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 22:50:05.115365 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 22:50:05.118477 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 22:50:05.125161 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 22:50:05.128278 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4075 22:50:05.131772 0 10 16 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (0 0)
4076 22:50:05.138251 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 22:50:05.141972 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 22:50:05.145567 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 22:50:05.152066 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 22:50:05.155082 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 22:50:05.158445 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 22:50:05.165364 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 22:50:05.168451 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4084 22:50:05.171685 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 22:50:05.178668 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 22:50:05.182058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 22:50:05.185279 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 22:50:05.191681 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 22:50:05.195099 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 22:50:05.198665 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 22:50:05.204977 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 22:50:05.208836 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 22:50:05.211961 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 22:50:05.215329 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 22:50:05.221575 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 22:50:05.225079 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 22:50:05.228535 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 22:50:05.235672 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4099 22:50:05.238784 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4100 22:50:05.242081 Total UI for P1: 0, mck2ui 16
4101 22:50:05.245415 best dqsien dly found for B0: ( 0, 13, 12)
4102 22:50:05.248469 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 22:50:05.252782 Total UI for P1: 0, mck2ui 16
4104 22:50:05.255345 best dqsien dly found for B1: ( 0, 13, 16)
4105 22:50:05.258312 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4106 22:50:05.262178 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4107 22:50:05.262263
4108 22:50:05.268508 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4109 22:50:05.271921 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4110 22:50:05.275145 [Gating] SW calibration Done
4111 22:50:05.275230 ==
4112 22:50:05.278259 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 22:50:05.282261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 22:50:05.282346 ==
4115 22:50:05.282432 RX Vref Scan: 0
4116 22:50:05.282513
4117 22:50:05.284903 RX Vref 0 -> 0, step: 1
4118 22:50:05.284988
4119 22:50:05.288942 RX Delay -230 -> 252, step: 16
4120 22:50:05.292257 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4121 22:50:05.294963 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4122 22:50:05.301901 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4123 22:50:05.304890 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4124 22:50:05.308797 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4125 22:50:05.311814 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4126 22:50:05.318396 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4127 22:50:05.321991 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4128 22:50:05.325380 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4129 22:50:05.328726 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4130 22:50:05.331943 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4131 22:50:05.338516 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4132 22:50:05.341633 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4133 22:50:05.345129 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4134 22:50:05.348309 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4135 22:50:05.355023 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4136 22:50:05.355105 ==
4137 22:50:05.358703 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 22:50:05.361907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 22:50:05.361991 ==
4140 22:50:05.362057 DQS Delay:
4141 22:50:05.365004 DQS0 = 0, DQS1 = 0
4142 22:50:05.365086 DQM Delay:
4143 22:50:05.368475 DQM0 = 40, DQM1 = 34
4144 22:50:05.368558 DQ Delay:
4145 22:50:05.371880 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4146 22:50:05.374862 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4147 22:50:05.378509 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4148 22:50:05.381702 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =49
4149 22:50:05.381784
4150 22:50:05.381849
4151 22:50:05.381909 ==
4152 22:50:05.384906 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 22:50:05.388379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 22:50:05.388461 ==
4155 22:50:05.388526
4156 22:50:05.391866
4157 22:50:05.391948 TX Vref Scan disable
4158 22:50:05.395022 == TX Byte 0 ==
4159 22:50:05.398327 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4160 22:50:05.401704 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4161 22:50:05.405261 == TX Byte 1 ==
4162 22:50:05.408511 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4163 22:50:05.411814 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4164 22:50:05.411896 ==
4165 22:50:05.414948 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 22:50:05.421421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 22:50:05.421508 ==
4168 22:50:05.421573
4169 22:50:05.421634
4170 22:50:05.421692 TX Vref Scan disable
4171 22:50:05.426222 == TX Byte 0 ==
4172 22:50:05.429413 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4173 22:50:05.435917 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4174 22:50:05.435999 == TX Byte 1 ==
4175 22:50:05.439506 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4176 22:50:05.446184 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4177 22:50:05.446266
4178 22:50:05.446330 [DATLAT]
4179 22:50:05.446390 Freq=600, CH0 RK0
4180 22:50:05.446449
4181 22:50:05.449166 DATLAT Default: 0x9
4182 22:50:05.449313 0, 0xFFFF, sum = 0
4183 22:50:05.452465 1, 0xFFFF, sum = 0
4184 22:50:05.455764 2, 0xFFFF, sum = 0
4185 22:50:05.455847 3, 0xFFFF, sum = 0
4186 22:50:05.459701 4, 0xFFFF, sum = 0
4187 22:50:05.459784 5, 0xFFFF, sum = 0
4188 22:50:05.462637 6, 0xFFFF, sum = 0
4189 22:50:05.462719 7, 0xFFFF, sum = 0
4190 22:50:05.465834 8, 0x0, sum = 1
4191 22:50:05.465918 9, 0x0, sum = 2
4192 22:50:05.465984 10, 0x0, sum = 3
4193 22:50:05.469889 11, 0x0, sum = 4
4194 22:50:05.469972 best_step = 9
4195 22:50:05.470038
4196 22:50:05.470097 ==
4197 22:50:05.472539 Dram Type= 6, Freq= 0, CH_0, rank 0
4198 22:50:05.479488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 22:50:05.479573 ==
4200 22:50:05.479638 RX Vref Scan: 1
4201 22:50:05.479698
4202 22:50:05.482899 RX Vref 0 -> 0, step: 1
4203 22:50:05.482982
4204 22:50:05.486078 RX Delay -195 -> 252, step: 8
4205 22:50:05.486160
4206 22:50:05.489647 Set Vref, RX VrefLevel [Byte0]: 53
4207 22:50:05.492616 [Byte1]: 51
4208 22:50:05.492698
4209 22:50:05.496048 Final RX Vref Byte 0 = 53 to rank0
4210 22:50:05.499822 Final RX Vref Byte 1 = 51 to rank0
4211 22:50:05.502538 Final RX Vref Byte 0 = 53 to rank1
4212 22:50:05.506059 Final RX Vref Byte 1 = 51 to rank1==
4213 22:50:05.509382 Dram Type= 6, Freq= 0, CH_0, rank 0
4214 22:50:05.512810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 22:50:05.512894 ==
4216 22:50:05.515854 DQS Delay:
4217 22:50:05.515937 DQS0 = 0, DQS1 = 0
4218 22:50:05.516002 DQM Delay:
4219 22:50:05.518994 DQM0 = 42, DQM1 = 33
4220 22:50:05.519076 DQ Delay:
4221 22:50:05.522761 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4222 22:50:05.525945 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4223 22:50:05.530282 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4224 22:50:05.532995 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4225 22:50:05.533078
4226 22:50:05.533143
4227 22:50:05.542535 [DQSOSCAuto] RK0, (LSB)MR18= 0x4524, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4228 22:50:05.542620 CH0 RK0: MR19=808, MR18=4524
4229 22:50:05.549971 CH0_RK0: MR19=0x808, MR18=0x4524, DQSOSC=396, MR23=63, INC=167, DEC=111
4230 22:50:05.550055
4231 22:50:05.552645 ----->DramcWriteLeveling(PI) begin...
4232 22:50:05.556305 ==
4233 22:50:05.556389 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 22:50:05.563003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 22:50:05.563093 ==
4236 22:50:05.566339 Write leveling (Byte 0): 31 => 31
4237 22:50:05.569454 Write leveling (Byte 1): 30 => 30
4238 22:50:05.572669 DramcWriteLeveling(PI) end<-----
4239 22:50:05.572753
4240 22:50:05.572819 ==
4241 22:50:05.575822 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 22:50:05.579719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 22:50:05.579803 ==
4244 22:50:05.582874 [Gating] SW mode calibration
4245 22:50:05.589567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4246 22:50:05.592961 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4247 22:50:05.599251 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4248 22:50:05.602709 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4249 22:50:05.606087 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 22:50:05.612919 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4251 22:50:05.616139 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4252 22:50:05.619347 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 22:50:05.625890 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 22:50:05.629538 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 22:50:05.632894 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 22:50:05.639331 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 22:50:05.642789 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 22:50:05.645773 0 10 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
4259 22:50:05.652475 0 10 16 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
4260 22:50:05.656551 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 22:50:05.659103 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 22:50:05.665890 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 22:50:05.669288 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 22:50:05.673314 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 22:50:05.676007 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 22:50:05.682549 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4267 22:50:05.685981 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4268 22:50:05.689442 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 22:50:05.695638 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 22:50:05.699090 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 22:50:05.702391 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 22:50:05.709093 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 22:50:05.712652 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 22:50:05.716467 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 22:50:05.722399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 22:50:05.725601 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 22:50:05.728972 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 22:50:05.735772 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 22:50:05.739168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 22:50:05.742770 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 22:50:05.749067 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 22:50:05.752470 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4283 22:50:05.755928 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 22:50:05.759035 Total UI for P1: 0, mck2ui 16
4285 22:50:05.762777 best dqsien dly found for B0: ( 0, 13, 12)
4286 22:50:05.766218 Total UI for P1: 0, mck2ui 16
4287 22:50:05.769250 best dqsien dly found for B1: ( 0, 13, 12)
4288 22:50:05.772831 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4289 22:50:05.775663 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4290 22:50:05.775746
4291 22:50:05.779299 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4292 22:50:05.785965 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4293 22:50:05.786090 [Gating] SW calibration Done
4294 22:50:05.789505 ==
4295 22:50:05.789601 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 22:50:05.796065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 22:50:05.796179 ==
4298 22:50:05.796246 RX Vref Scan: 0
4299 22:50:05.796306
4300 22:50:05.799133 RX Vref 0 -> 0, step: 1
4301 22:50:05.799225
4302 22:50:05.802628 RX Delay -230 -> 252, step: 16
4303 22:50:05.806045 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4304 22:50:05.809646 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4305 22:50:05.813086 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4306 22:50:05.819882 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4307 22:50:05.822835 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4308 22:50:05.825821 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4309 22:50:05.829701 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4310 22:50:05.836307 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4311 22:50:05.839303 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4312 22:50:05.842923 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4313 22:50:05.845690 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4314 22:50:05.849139 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4315 22:50:05.856048 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4316 22:50:05.859166 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4317 22:50:05.862395 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4318 22:50:05.866145 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4319 22:50:05.869114 ==
4320 22:50:05.869229 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 22:50:05.876050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 22:50:05.876152 ==
4323 22:50:05.876240 DQS Delay:
4324 22:50:05.879243 DQS0 = 0, DQS1 = 0
4325 22:50:05.879327 DQM Delay:
4326 22:50:05.882628 DQM0 = 41, DQM1 = 34
4327 22:50:05.882712 DQ Delay:
4328 22:50:05.886308 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4329 22:50:05.889141 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4330 22:50:05.892474 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4331 22:50:05.897168 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4332 22:50:05.897271
4333 22:50:05.897355
4334 22:50:05.897434 ==
4335 22:50:05.898895 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 22:50:05.902481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 22:50:05.902566 ==
4338 22:50:05.902650
4339 22:50:05.902730
4340 22:50:05.906330 TX Vref Scan disable
4341 22:50:05.909620 == TX Byte 0 ==
4342 22:50:05.912325 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4343 22:50:05.915999 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4344 22:50:05.919383 == TX Byte 1 ==
4345 22:50:05.922251 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4346 22:50:05.926157 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4347 22:50:05.926245 ==
4348 22:50:05.929711 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 22:50:05.932434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 22:50:05.935729 ==
4351 22:50:05.935811
4352 22:50:05.935876
4353 22:50:05.935935 TX Vref Scan disable
4354 22:50:05.939800 == TX Byte 0 ==
4355 22:50:05.943163 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4356 22:50:05.946909 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4357 22:50:05.949781 == TX Byte 1 ==
4358 22:50:05.952806 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4359 22:50:05.956226 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4360 22:50:05.959678
4361 22:50:05.959779 [DATLAT]
4362 22:50:05.959843 Freq=600, CH0 RK1
4363 22:50:05.959910
4364 22:50:05.963123 DATLAT Default: 0x9
4365 22:50:05.963204 0, 0xFFFF, sum = 0
4366 22:50:05.966393 1, 0xFFFF, sum = 0
4367 22:50:05.966474 2, 0xFFFF, sum = 0
4368 22:50:05.969753 3, 0xFFFF, sum = 0
4369 22:50:05.969835 4, 0xFFFF, sum = 0
4370 22:50:05.973316 5, 0xFFFF, sum = 0
4371 22:50:05.973404 6, 0xFFFF, sum = 0
4372 22:50:05.976227 7, 0xFFFF, sum = 0
4373 22:50:05.976309 8, 0x0, sum = 1
4374 22:50:05.980039 9, 0x0, sum = 2
4375 22:50:05.980124 10, 0x0, sum = 3
4376 22:50:05.983144 11, 0x0, sum = 4
4377 22:50:05.983231 best_step = 9
4378 22:50:05.983295
4379 22:50:05.983353 ==
4380 22:50:05.986566 Dram Type= 6, Freq= 0, CH_0, rank 1
4381 22:50:05.993427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 22:50:05.993520 ==
4383 22:50:05.993584 RX Vref Scan: 0
4384 22:50:05.993642
4385 22:50:05.996317 RX Vref 0 -> 0, step: 1
4386 22:50:05.996403
4387 22:50:05.999813 RX Delay -195 -> 252, step: 8
4388 22:50:06.003033 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4389 22:50:06.009716 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4390 22:50:06.013083 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4391 22:50:06.016821 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4392 22:50:06.020219 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4393 22:50:06.023057 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4394 22:50:06.029897 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4395 22:50:06.033320 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4396 22:50:06.036496 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4397 22:50:06.040233 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4398 22:50:06.043586 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4399 22:50:06.050259 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4400 22:50:06.053324 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4401 22:50:06.057191 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4402 22:50:06.059830 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4403 22:50:06.066857 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4404 22:50:06.066971 ==
4405 22:50:06.069823 Dram Type= 6, Freq= 0, CH_0, rank 1
4406 22:50:06.073074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 22:50:06.073157 ==
4408 22:50:06.073246 DQS Delay:
4409 22:50:06.076497 DQS0 = 0, DQS1 = 0
4410 22:50:06.076579 DQM Delay:
4411 22:50:06.079754 DQM0 = 40, DQM1 = 33
4412 22:50:06.079835 DQ Delay:
4413 22:50:06.083423 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4414 22:50:06.086383 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4415 22:50:06.090634 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4416 22:50:06.093691 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4417 22:50:06.093774
4418 22:50:06.093837
4419 22:50:06.100343 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c2e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4420 22:50:06.103254 CH0 RK1: MR19=808, MR18=4C2E
4421 22:50:06.109973 CH0_RK1: MR19=0x808, MR18=0x4C2E, DQSOSC=395, MR23=63, INC=168, DEC=112
4422 22:50:06.114099 [RxdqsGatingPostProcess] freq 600
4423 22:50:06.120125 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4424 22:50:06.123358 Pre-setting of DQS Precalculation
4425 22:50:06.126670 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4426 22:50:06.126756 ==
4427 22:50:06.129882 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 22:50:06.133180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 22:50:06.133300 ==
4430 22:50:06.140021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4431 22:50:06.146872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4432 22:50:06.149796 [CA 0] Center 35 (5~66) winsize 62
4433 22:50:06.153413 [CA 1] Center 35 (5~66) winsize 62
4434 22:50:06.156425 [CA 2] Center 34 (4~64) winsize 61
4435 22:50:06.159648 [CA 3] Center 33 (3~64) winsize 62
4436 22:50:06.163230 [CA 4] Center 34 (3~65) winsize 63
4437 22:50:06.166487 [CA 5] Center 33 (2~64) winsize 63
4438 22:50:06.166571
4439 22:50:06.169685 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4440 22:50:06.169766
4441 22:50:06.173237 [CATrainingPosCal] consider 1 rank data
4442 22:50:06.176600 u2DelayCellTimex100 = 270/100 ps
4443 22:50:06.180222 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4444 22:50:06.183099 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4445 22:50:06.187511 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4446 22:50:06.189729 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4447 22:50:06.193335 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4448 22:50:06.197606 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4449 22:50:06.197693
4450 22:50:06.203377 CA PerBit enable=1, Macro0, CA PI delay=33
4451 22:50:06.203464
4452 22:50:06.203528 [CBTSetCACLKResult] CA Dly = 33
4453 22:50:06.206651 CS Dly: 4 (0~35)
4454 22:50:06.206731 ==
4455 22:50:06.210409 Dram Type= 6, Freq= 0, CH_1, rank 1
4456 22:50:06.213532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 22:50:06.213615 ==
4458 22:50:06.220351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4459 22:50:06.226517 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4460 22:50:06.230154 [CA 0] Center 35 (5~66) winsize 62
4461 22:50:06.233060 [CA 1] Center 35 (5~66) winsize 62
4462 22:50:06.236413 [CA 2] Center 34 (3~65) winsize 63
4463 22:50:06.239875 [CA 3] Center 33 (3~64) winsize 62
4464 22:50:06.243069 [CA 4] Center 34 (3~65) winsize 63
4465 22:50:06.247192 [CA 5] Center 33 (3~64) winsize 62
4466 22:50:06.247274
4467 22:50:06.249736 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4468 22:50:06.249822
4469 22:50:06.253098 [CATrainingPosCal] consider 2 rank data
4470 22:50:06.256631 u2DelayCellTimex100 = 270/100 ps
4471 22:50:06.260220 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4472 22:50:06.263002 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4473 22:50:06.266677 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4474 22:50:06.270184 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4475 22:50:06.273536 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4476 22:50:06.276556 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4477 22:50:06.276667
4478 22:50:06.283253 CA PerBit enable=1, Macro0, CA PI delay=33
4479 22:50:06.283365
4480 22:50:06.286671 [CBTSetCACLKResult] CA Dly = 33
4481 22:50:06.286758 CS Dly: 5 (0~37)
4482 22:50:06.286843
4483 22:50:06.289771 ----->DramcWriteLeveling(PI) begin...
4484 22:50:06.289876 ==
4485 22:50:06.293966 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 22:50:06.297040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 22:50:06.297151 ==
4488 22:50:06.299994 Write leveling (Byte 0): 29 => 29
4489 22:50:06.303346 Write leveling (Byte 1): 31 => 31
4490 22:50:06.306967 DramcWriteLeveling(PI) end<-----
4491 22:50:06.307055
4492 22:50:06.307139 ==
4493 22:50:06.310272 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 22:50:06.313838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 22:50:06.316979 ==
4496 22:50:06.317088 [Gating] SW mode calibration
4497 22:50:06.326894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4498 22:50:06.329894 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4499 22:50:06.333586 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4500 22:50:06.339896 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4501 22:50:06.343139 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4502 22:50:06.346779 0 9 12 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
4503 22:50:06.353993 0 9 16 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
4504 22:50:06.356902 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 22:50:06.360137 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4506 22:50:06.366912 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 22:50:06.370508 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 22:50:06.373518 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 22:50:06.376904 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 22:50:06.383271 0 10 12 | B1->B0 | 2626 2929 | 0 0 | (0 0) (1 1)
4511 22:50:06.386736 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4512 22:50:06.390240 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 22:50:06.396993 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 22:50:06.400468 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 22:50:06.403504 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 22:50:06.410298 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 22:50:06.413474 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 22:50:06.416815 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 22:50:06.423738 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4520 22:50:06.427811 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 22:50:06.430351 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 22:50:06.436547 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 22:50:06.440167 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 22:50:06.443672 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 22:50:06.450246 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 22:50:06.454199 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 22:50:06.456700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 22:50:06.463519 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 22:50:06.467202 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 22:50:06.470183 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 22:50:06.473603 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 22:50:06.480155 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 22:50:06.484171 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 22:50:06.486939 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4535 22:50:06.493676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4536 22:50:06.497073 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 22:50:06.500373 Total UI for P1: 0, mck2ui 16
4538 22:50:06.503525 best dqsien dly found for B0: ( 0, 13, 14)
4539 22:50:06.507613 Total UI for P1: 0, mck2ui 16
4540 22:50:06.510344 best dqsien dly found for B1: ( 0, 13, 14)
4541 22:50:06.513430 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4542 22:50:06.516698 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4543 22:50:06.516785
4544 22:50:06.520077 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4545 22:50:06.523556 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4546 22:50:06.527063 [Gating] SW calibration Done
4547 22:50:06.527150 ==
4548 22:50:06.530112 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 22:50:06.536838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 22:50:06.536932 ==
4551 22:50:06.536998 RX Vref Scan: 0
4552 22:50:06.537058
4553 22:50:06.540300 RX Vref 0 -> 0, step: 1
4554 22:50:06.540382
4555 22:50:06.543942 RX Delay -230 -> 252, step: 16
4556 22:50:06.547261 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4557 22:50:06.550071 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4558 22:50:06.553649 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4559 22:50:06.560345 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4560 22:50:06.563473 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4561 22:50:06.567524 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4562 22:50:06.570615 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4563 22:50:06.573602 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4564 22:50:06.580780 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4565 22:50:06.584354 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4566 22:50:06.587299 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4567 22:50:06.590273 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4568 22:50:06.596842 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4569 22:50:06.600392 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4570 22:50:06.603593 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4571 22:50:06.607077 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4572 22:50:06.607161 ==
4573 22:50:06.610829 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 22:50:06.617127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 22:50:06.617238 ==
4576 22:50:06.617319 DQS Delay:
4577 22:50:06.620001 DQS0 = 0, DQS1 = 0
4578 22:50:06.620082 DQM Delay:
4579 22:50:06.620145 DQM0 = 44, DQM1 = 35
4580 22:50:06.623787 DQ Delay:
4581 22:50:06.627163 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4582 22:50:06.630206 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4583 22:50:06.630290 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4584 22:50:06.636659 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4585 22:50:06.636747
4586 22:50:06.636811
4587 22:50:06.636870 ==
4588 22:50:06.640069 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 22:50:06.643722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 22:50:06.643804 ==
4591 22:50:06.643868
4592 22:50:06.643926
4593 22:50:06.646766 TX Vref Scan disable
4594 22:50:06.646847 == TX Byte 0 ==
4595 22:50:06.653556 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4596 22:50:06.657566 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4597 22:50:06.657652 == TX Byte 1 ==
4598 22:50:06.663260 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4599 22:50:06.667126 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4600 22:50:06.667212 ==
4601 22:50:06.670259 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 22:50:06.674134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 22:50:06.674218 ==
4604 22:50:06.674282
4605 22:50:06.674344
4606 22:50:06.676771 TX Vref Scan disable
4607 22:50:06.680721 == TX Byte 0 ==
4608 22:50:06.683675 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4609 22:50:06.686701 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4610 22:50:06.690433 == TX Byte 1 ==
4611 22:50:06.693604 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4612 22:50:06.696707 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4613 22:50:06.700113
4614 22:50:06.700197 [DATLAT]
4615 22:50:06.700262 Freq=600, CH1 RK0
4616 22:50:06.700322
4617 22:50:06.703708 DATLAT Default: 0x9
4618 22:50:06.703790 0, 0xFFFF, sum = 0
4619 22:50:06.707049 1, 0xFFFF, sum = 0
4620 22:50:06.707131 2, 0xFFFF, sum = 0
4621 22:50:06.710371 3, 0xFFFF, sum = 0
4622 22:50:06.710453 4, 0xFFFF, sum = 0
4623 22:50:06.713447 5, 0xFFFF, sum = 0
4624 22:50:06.713533 6, 0xFFFF, sum = 0
4625 22:50:06.717079 7, 0xFFFF, sum = 0
4626 22:50:06.717187 8, 0x0, sum = 1
4627 22:50:06.720170 9, 0x0, sum = 2
4628 22:50:06.720251 10, 0x0, sum = 3
4629 22:50:06.723555 11, 0x0, sum = 4
4630 22:50:06.723637 best_step = 9
4631 22:50:06.723700
4632 22:50:06.723759 ==
4633 22:50:06.727162 Dram Type= 6, Freq= 0, CH_1, rank 0
4634 22:50:06.730790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 22:50:06.733794 ==
4636 22:50:06.733882 RX Vref Scan: 1
4637 22:50:06.733967
4638 22:50:06.737326 RX Vref 0 -> 0, step: 1
4639 22:50:06.737409
4640 22:50:06.740893 RX Delay -195 -> 252, step: 8
4641 22:50:06.740978
4642 22:50:06.743648 Set Vref, RX VrefLevel [Byte0]: 54
4643 22:50:06.746996 [Byte1]: 54
4644 22:50:06.747080
4645 22:50:06.750494 Final RX Vref Byte 0 = 54 to rank0
4646 22:50:06.753643 Final RX Vref Byte 1 = 54 to rank0
4647 22:50:06.756943 Final RX Vref Byte 0 = 54 to rank1
4648 22:50:06.760488 Final RX Vref Byte 1 = 54 to rank1==
4649 22:50:06.764824 Dram Type= 6, Freq= 0, CH_1, rank 0
4650 22:50:06.767101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 22:50:06.767196 ==
4652 22:50:06.767280 DQS Delay:
4653 22:50:06.770379 DQS0 = 0, DQS1 = 0
4654 22:50:06.770462 DQM Delay:
4655 22:50:06.774144 DQM0 = 41, DQM1 = 33
4656 22:50:06.774227 DQ Delay:
4657 22:50:06.777158 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4658 22:50:06.780441 DQ4 =44, DQ5 =52, DQ6 =52, DQ7 =36
4659 22:50:06.783783 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4660 22:50:06.787467 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4661 22:50:06.787550
4662 22:50:06.787633
4663 22:50:06.797227 [DQSOSCAuto] RK0, (LSB)MR18= 0x4106, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4664 22:50:06.797314 CH1 RK0: MR19=808, MR18=4106
4665 22:50:06.803909 CH1_RK0: MR19=0x808, MR18=0x4106, DQSOSC=397, MR23=63, INC=166, DEC=110
4666 22:50:06.803995
4667 22:50:06.807119 ----->DramcWriteLeveling(PI) begin...
4668 22:50:06.807204 ==
4669 22:50:06.810462 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 22:50:06.817107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 22:50:06.817192 ==
4672 22:50:06.821176 Write leveling (Byte 0): 30 => 30
4673 22:50:06.821322 Write leveling (Byte 1): 30 => 30
4674 22:50:06.824019 DramcWriteLeveling(PI) end<-----
4675 22:50:06.824102
4676 22:50:06.824186 ==
4677 22:50:06.827231 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 22:50:06.833775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 22:50:06.833859 ==
4680 22:50:06.837344 [Gating] SW mode calibration
4681 22:50:06.844219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4682 22:50:06.847173 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4683 22:50:06.853654 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4684 22:50:06.857038 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4685 22:50:06.860724 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4686 22:50:06.867115 0 9 12 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (1 1)
4687 22:50:06.870613 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 22:50:06.873569 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4689 22:50:06.877022 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 22:50:06.884028 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4691 22:50:06.887647 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 22:50:06.890594 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 22:50:06.897151 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4694 22:50:06.900786 0 10 12 | B1->B0 | 2f2f 3c3c | 1 0 | (0 0) (0 0)
4695 22:50:06.904048 0 10 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4696 22:50:06.910658 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 22:50:06.913573 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 22:50:06.917401 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 22:50:06.924095 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 22:50:06.927549 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 22:50:06.930482 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 22:50:06.937553 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4703 22:50:06.941127 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 22:50:06.944400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 22:50:06.950377 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 22:50:06.954216 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 22:50:06.957169 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 22:50:06.960776 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 22:50:06.967556 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 22:50:06.971188 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 22:50:06.974593 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 22:50:06.980721 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 22:50:06.984301 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 22:50:06.987674 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 22:50:06.994902 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 22:50:06.997638 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 22:50:07.000853 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4718 22:50:07.007309 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4719 22:50:07.007392 Total UI for P1: 0, mck2ui 16
4720 22:50:07.014169 best dqsien dly found for B1: ( 0, 13, 10)
4721 22:50:07.017486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 22:50:07.020773 Total UI for P1: 0, mck2ui 16
4723 22:50:07.024527 best dqsien dly found for B0: ( 0, 13, 10)
4724 22:50:07.027509 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4725 22:50:07.030631 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4726 22:50:07.030716
4727 22:50:07.034730 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4728 22:50:07.037728 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4729 22:50:07.040919 [Gating] SW calibration Done
4730 22:50:07.041004 ==
4731 22:50:07.043584 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 22:50:07.047257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 22:50:07.050430 ==
4734 22:50:07.050515 RX Vref Scan: 0
4735 22:50:07.050600
4736 22:50:07.053963 RX Vref 0 -> 0, step: 1
4737 22:50:07.054047
4738 22:50:07.057049 RX Delay -230 -> 252, step: 16
4739 22:50:07.060927 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4740 22:50:07.063850 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4741 22:50:07.067090 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4742 22:50:07.073515 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4743 22:50:07.077237 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4744 22:50:07.080103 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4745 22:50:07.083851 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4746 22:50:07.087045 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4747 22:50:07.093605 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4748 22:50:07.097071 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4749 22:50:07.100126 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4750 22:50:07.104135 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4751 22:50:07.110862 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4752 22:50:07.113779 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4753 22:50:07.116890 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4754 22:50:07.120082 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4755 22:50:07.120167 ==
4756 22:50:07.123641 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 22:50:07.130714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 22:50:07.130805 ==
4759 22:50:07.130871 DQS Delay:
4760 22:50:07.133917 DQS0 = 0, DQS1 = 0
4761 22:50:07.133999 DQM Delay:
4762 22:50:07.134063 DQM0 = 40, DQM1 = 35
4763 22:50:07.136698 DQ Delay:
4764 22:50:07.139994 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4765 22:50:07.143471 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4766 22:50:07.146724 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4767 22:50:07.150471 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4768 22:50:07.150553
4769 22:50:07.150617
4770 22:50:07.150675 ==
4771 22:50:07.153628 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 22:50:07.156774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 22:50:07.156856 ==
4774 22:50:07.156921
4775 22:50:07.156979
4776 22:50:07.160140 TX Vref Scan disable
4777 22:50:07.160222 == TX Byte 0 ==
4778 22:50:07.166777 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4779 22:50:07.170374 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4780 22:50:07.170458 == TX Byte 1 ==
4781 22:50:07.176966 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4782 22:50:07.179933 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4783 22:50:07.180018 ==
4784 22:50:07.183462 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 22:50:07.186548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 22:50:07.186638 ==
4787 22:50:07.186704
4788 22:50:07.190268
4789 22:50:07.190349 TX Vref Scan disable
4790 22:50:07.193589 == TX Byte 0 ==
4791 22:50:07.196773 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4792 22:50:07.199877 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4793 22:50:07.204015 == TX Byte 1 ==
4794 22:50:07.206755 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4795 22:50:07.213553 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4796 22:50:07.213644
4797 22:50:07.213709 [DATLAT]
4798 22:50:07.213772 Freq=600, CH1 RK1
4799 22:50:07.213852
4800 22:50:07.216723 DATLAT Default: 0x9
4801 22:50:07.216807 0, 0xFFFF, sum = 0
4802 22:50:07.220161 1, 0xFFFF, sum = 0
4803 22:50:07.220247 2, 0xFFFF, sum = 0
4804 22:50:07.223664 3, 0xFFFF, sum = 0
4805 22:50:07.223776 4, 0xFFFF, sum = 0
4806 22:50:07.226599 5, 0xFFFF, sum = 0
4807 22:50:07.226686 6, 0xFFFF, sum = 0
4808 22:50:07.230372 7, 0xFFFF, sum = 0
4809 22:50:07.230459 8, 0x0, sum = 1
4810 22:50:07.233523 9, 0x0, sum = 2
4811 22:50:07.233609 10, 0x0, sum = 3
4812 22:50:07.237112 11, 0x0, sum = 4
4813 22:50:07.237196 best_step = 9
4814 22:50:07.237309
4815 22:50:07.237371 ==
4816 22:50:07.240650 Dram Type= 6, Freq= 0, CH_1, rank 1
4817 22:50:07.247010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4818 22:50:07.247097 ==
4819 22:50:07.247162 RX Vref Scan: 0
4820 22:50:07.247221
4821 22:50:07.250318 RX Vref 0 -> 0, step: 1
4822 22:50:07.250401
4823 22:50:07.253529 RX Delay -195 -> 252, step: 8
4824 22:50:07.256813 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4825 22:50:07.263386 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4826 22:50:07.266862 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4827 22:50:07.270129 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4828 22:50:07.273536 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4829 22:50:07.276725 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4830 22:50:07.283501 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4831 22:50:07.286539 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4832 22:50:07.290187 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4833 22:50:07.293474 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4834 22:50:07.300404 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4835 22:50:07.303366 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4836 22:50:07.306672 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4837 22:50:07.310300 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4838 22:50:07.316896 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4839 22:50:07.320297 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4840 22:50:07.320389 ==
4841 22:50:07.323484 Dram Type= 6, Freq= 0, CH_1, rank 1
4842 22:50:07.326755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4843 22:50:07.326844 ==
4844 22:50:07.326911 DQS Delay:
4845 22:50:07.329729 DQS0 = 0, DQS1 = 0
4846 22:50:07.329881 DQM Delay:
4847 22:50:07.333106 DQM0 = 38, DQM1 = 33
4848 22:50:07.333268 DQ Delay:
4849 22:50:07.336841 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4850 22:50:07.340011 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4851 22:50:07.343336 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4852 22:50:07.347626 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4853 22:50:07.347734
4854 22:50:07.347803
4855 22:50:07.357431 [DQSOSCAuto] RK1, (LSB)MR18= 0x3645, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4856 22:50:07.357566 CH1 RK1: MR19=808, MR18=3645
4857 22:50:07.363647 CH1_RK1: MR19=0x808, MR18=0x3645, DQSOSC=396, MR23=63, INC=167, DEC=111
4858 22:50:07.367167 [RxdqsGatingPostProcess] freq 600
4859 22:50:07.373838 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4860 22:50:07.377445 Pre-setting of DQS Precalculation
4861 22:50:07.380232 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4862 22:50:07.386801 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4863 22:50:07.393757 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4864 22:50:07.393855
4865 22:50:07.397040
4866 22:50:07.397179 [Calibration Summary] 1200 Mbps
4867 22:50:07.400217 CH 0, Rank 0
4868 22:50:07.400300 SW Impedance : PASS
4869 22:50:07.403455 DUTY Scan : NO K
4870 22:50:07.406666 ZQ Calibration : PASS
4871 22:50:07.406779 Jitter Meter : NO K
4872 22:50:07.410097 CBT Training : PASS
4873 22:50:07.413516 Write leveling : PASS
4874 22:50:07.413602 RX DQS gating : PASS
4875 22:50:07.416990 RX DQ/DQS(RDDQC) : PASS
4876 22:50:07.420344 TX DQ/DQS : PASS
4877 22:50:07.420430 RX DATLAT : PASS
4878 22:50:07.423601 RX DQ/DQS(Engine): PASS
4879 22:50:07.423685 TX OE : NO K
4880 22:50:07.426722 All Pass.
4881 22:50:07.426805
4882 22:50:07.426870 CH 0, Rank 1
4883 22:50:07.429783 SW Impedance : PASS
4884 22:50:07.429870 DUTY Scan : NO K
4885 22:50:07.433319 ZQ Calibration : PASS
4886 22:50:07.436587 Jitter Meter : NO K
4887 22:50:07.436673 CBT Training : PASS
4888 22:50:07.440318 Write leveling : PASS
4889 22:50:07.443508 RX DQS gating : PASS
4890 22:50:07.443593 RX DQ/DQS(RDDQC) : PASS
4891 22:50:07.446660 TX DQ/DQS : PASS
4892 22:50:07.450028 RX DATLAT : PASS
4893 22:50:07.450117 RX DQ/DQS(Engine): PASS
4894 22:50:07.453918 TX OE : NO K
4895 22:50:07.454004 All Pass.
4896 22:50:07.454089
4897 22:50:07.456503 CH 1, Rank 0
4898 22:50:07.456587 SW Impedance : PASS
4899 22:50:07.460259 DUTY Scan : NO K
4900 22:50:07.463709 ZQ Calibration : PASS
4901 22:50:07.463794 Jitter Meter : NO K
4902 22:50:07.467170 CBT Training : PASS
4903 22:50:07.467256 Write leveling : PASS
4904 22:50:07.470376 RX DQS gating : PASS
4905 22:50:07.473676 RX DQ/DQS(RDDQC) : PASS
4906 22:50:07.473760 TX DQ/DQS : PASS
4907 22:50:07.476942 RX DATLAT : PASS
4908 22:50:07.480288 RX DQ/DQS(Engine): PASS
4909 22:50:07.480377 TX OE : NO K
4910 22:50:07.483548 All Pass.
4911 22:50:07.483632
4912 22:50:07.483717 CH 1, Rank 1
4913 22:50:07.487504 SW Impedance : PASS
4914 22:50:07.487591 DUTY Scan : NO K
4915 22:50:07.490399 ZQ Calibration : PASS
4916 22:50:07.493824 Jitter Meter : NO K
4917 22:50:07.493908 CBT Training : PASS
4918 22:50:07.497425 Write leveling : PASS
4919 22:50:07.500717 RX DQS gating : PASS
4920 22:50:07.500804 RX DQ/DQS(RDDQC) : PASS
4921 22:50:07.504024 TX DQ/DQS : PASS
4922 22:50:07.504109 RX DATLAT : PASS
4923 22:50:07.507391 RX DQ/DQS(Engine): PASS
4924 22:50:07.510835 TX OE : NO K
4925 22:50:07.510922 All Pass.
4926 22:50:07.511008
4927 22:50:07.513908 DramC Write-DBI off
4928 22:50:07.513993 PER_BANK_REFRESH: Hybrid Mode
4929 22:50:07.517158 TX_TRACKING: ON
4930 22:50:07.526972 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4931 22:50:07.530374 [FAST_K] Save calibration result to emmc
4932 22:50:07.533579 dramc_set_vcore_voltage set vcore to 662500
4933 22:50:07.533664 Read voltage for 933, 3
4934 22:50:07.537713 Vio18 = 0
4935 22:50:07.537798 Vcore = 662500
4936 22:50:07.537882 Vdram = 0
4937 22:50:07.540359 Vddq = 0
4938 22:50:07.540442 Vmddr = 0
4939 22:50:07.544193 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4940 22:50:07.551154 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4941 22:50:07.553803 MEM_TYPE=3, freq_sel=17
4942 22:50:07.557177 sv_algorithm_assistance_LP4_1600
4943 22:50:07.560421 ============ PULL DRAM RESETB DOWN ============
4944 22:50:07.563854 ========== PULL DRAM RESETB DOWN end =========
4945 22:50:07.567612 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4946 22:50:07.570441 ===================================
4947 22:50:07.573996 LPDDR4 DRAM CONFIGURATION
4948 22:50:07.577356 ===================================
4949 22:50:07.580239 EX_ROW_EN[0] = 0x0
4950 22:50:07.580326 EX_ROW_EN[1] = 0x0
4951 22:50:07.583641 LP4Y_EN = 0x0
4952 22:50:07.583728 WORK_FSP = 0x0
4953 22:50:07.587112 WL = 0x3
4954 22:50:07.587197 RL = 0x3
4955 22:50:07.590223 BL = 0x2
4956 22:50:07.590332 RPST = 0x0
4957 22:50:07.593815 RD_PRE = 0x0
4958 22:50:07.593899 WR_PRE = 0x1
4959 22:50:07.596845 WR_PST = 0x0
4960 22:50:07.600166 DBI_WR = 0x0
4961 22:50:07.600250 DBI_RD = 0x0
4962 22:50:07.603892 OTF = 0x1
4963 22:50:07.607273 ===================================
4964 22:50:07.610664 ===================================
4965 22:50:07.610749 ANA top config
4966 22:50:07.614172 ===================================
4967 22:50:07.617383 DLL_ASYNC_EN = 0
4968 22:50:07.617468 ALL_SLAVE_EN = 1
4969 22:50:07.620470 NEW_RANK_MODE = 1
4970 22:50:07.623626 DLL_IDLE_MODE = 1
4971 22:50:07.627119 LP45_APHY_COMB_EN = 1
4972 22:50:07.630574 TX_ODT_DIS = 1
4973 22:50:07.630660 NEW_8X_MODE = 1
4974 22:50:07.634013 ===================================
4975 22:50:07.637078 ===================================
4976 22:50:07.641380 data_rate = 1866
4977 22:50:07.644018 CKR = 1
4978 22:50:07.647195 DQ_P2S_RATIO = 8
4979 22:50:07.651096 ===================================
4980 22:50:07.653850 CA_P2S_RATIO = 8
4981 22:50:07.653933 DQ_CA_OPEN = 0
4982 22:50:07.657706 DQ_SEMI_OPEN = 0
4983 22:50:07.661047 CA_SEMI_OPEN = 0
4984 22:50:07.664621 CA_FULL_RATE = 0
4985 22:50:07.667553 DQ_CKDIV4_EN = 1
4986 22:50:07.670785 CA_CKDIV4_EN = 1
4987 22:50:07.670869 CA_PREDIV_EN = 0
4988 22:50:07.674210 PH8_DLY = 0
4989 22:50:07.677455 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4990 22:50:07.681199 DQ_AAMCK_DIV = 4
4991 22:50:07.684742 CA_AAMCK_DIV = 4
4992 22:50:07.684826 CA_ADMCK_DIV = 4
4993 22:50:07.687718 DQ_TRACK_CA_EN = 0
4994 22:50:07.690821 CA_PICK = 933
4995 22:50:07.693954 CA_MCKIO = 933
4996 22:50:07.697377 MCKIO_SEMI = 0
4997 22:50:07.700991 PLL_FREQ = 3732
4998 22:50:07.704055 DQ_UI_PI_RATIO = 32
4999 22:50:07.704139 CA_UI_PI_RATIO = 0
5000 22:50:07.708004 ===================================
5001 22:50:07.710936 ===================================
5002 22:50:07.714201 memory_type:LPDDR4
5003 22:50:07.717805 GP_NUM : 10
5004 22:50:07.717892 SRAM_EN : 1
5005 22:50:07.721169 MD32_EN : 0
5006 22:50:07.724357 ===================================
5007 22:50:07.727368 [ANA_INIT] >>>>>>>>>>>>>>
5008 22:50:07.731181 <<<<<< [CONFIGURE PHASE]: ANA_TX
5009 22:50:07.734587 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5010 22:50:07.737919 ===================================
5011 22:50:07.738009 data_rate = 1866,PCW = 0X8f00
5012 22:50:07.740739 ===================================
5013 22:50:07.744057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5014 22:50:07.751053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5015 22:50:07.757734 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5016 22:50:07.760944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5017 22:50:07.763860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5018 22:50:07.767268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5019 22:50:07.770450 [ANA_INIT] flow start
5020 22:50:07.770534 [ANA_INIT] PLL >>>>>>>>
5021 22:50:07.773893 [ANA_INIT] PLL <<<<<<<<
5022 22:50:07.777468 [ANA_INIT] MIDPI >>>>>>>>
5023 22:50:07.780912 [ANA_INIT] MIDPI <<<<<<<<
5024 22:50:07.780996 [ANA_INIT] DLL >>>>>>>>
5025 22:50:07.784306 [ANA_INIT] flow end
5026 22:50:07.787524 ============ LP4 DIFF to SE enter ============
5027 22:50:07.790968 ============ LP4 DIFF to SE exit ============
5028 22:50:07.794733 [ANA_INIT] <<<<<<<<<<<<<
5029 22:50:07.797501 [Flow] Enable top DCM control >>>>>
5030 22:50:07.800986 [Flow] Enable top DCM control <<<<<
5031 22:50:07.804525 Enable DLL master slave shuffle
5032 22:50:07.807801 ==============================================================
5033 22:50:07.810968 Gating Mode config
5034 22:50:07.817514 ==============================================================
5035 22:50:07.817609 Config description:
5036 22:50:07.828072 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5037 22:50:07.834454 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5038 22:50:07.840717 SELPH_MODE 0: By rank 1: By Phase
5039 22:50:07.843968 ==============================================================
5040 22:50:07.847351 GAT_TRACK_EN = 1
5041 22:50:07.850764 RX_GATING_MODE = 2
5042 22:50:07.854771 RX_GATING_TRACK_MODE = 2
5043 22:50:07.857700 SELPH_MODE = 1
5044 22:50:07.860940 PICG_EARLY_EN = 1
5045 22:50:07.864100 VALID_LAT_VALUE = 1
5046 22:50:07.867525 ==============================================================
5047 22:50:07.871059 Enter into Gating configuration >>>>
5048 22:50:07.874026 Exit from Gating configuration <<<<
5049 22:50:07.878175 Enter into DVFS_PRE_config >>>>>
5050 22:50:07.891256 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5051 22:50:07.891364 Exit from DVFS_PRE_config <<<<<
5052 22:50:07.894260 Enter into PICG configuration >>>>
5053 22:50:07.897956 Exit from PICG configuration <<<<
5054 22:50:07.901243 [RX_INPUT] configuration >>>>>
5055 22:50:07.904365 [RX_INPUT] configuration <<<<<
5056 22:50:07.910829 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5057 22:50:07.914114 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5058 22:50:07.921541 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5059 22:50:07.927934 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5060 22:50:07.934407 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5061 22:50:07.941512 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5062 22:50:07.944099 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5063 22:50:07.947432 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5064 22:50:07.951438 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5065 22:50:07.957645 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5066 22:50:07.961130 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5067 22:50:07.964170 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5068 22:50:07.967445 ===================================
5069 22:50:07.971183 LPDDR4 DRAM CONFIGURATION
5070 22:50:07.974143 ===================================
5071 22:50:07.974230 EX_ROW_EN[0] = 0x0
5072 22:50:07.977899 EX_ROW_EN[1] = 0x0
5073 22:50:07.977982 LP4Y_EN = 0x0
5074 22:50:07.981483 WORK_FSP = 0x0
5075 22:50:07.984381 WL = 0x3
5076 22:50:07.984464 RL = 0x3
5077 22:50:07.987677 BL = 0x2
5078 22:50:07.987759 RPST = 0x0
5079 22:50:07.991136 RD_PRE = 0x0
5080 22:50:07.991257 WR_PRE = 0x1
5081 22:50:07.994550 WR_PST = 0x0
5082 22:50:07.994634 DBI_WR = 0x0
5083 22:50:07.997501 DBI_RD = 0x0
5084 22:50:07.997586 OTF = 0x1
5085 22:50:08.000776 ===================================
5086 22:50:08.004307 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5087 22:50:08.007561 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5088 22:50:08.014474 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5089 22:50:08.017911 ===================================
5090 22:50:08.021245 LPDDR4 DRAM CONFIGURATION
5091 22:50:08.024408 ===================================
5092 22:50:08.024500 EX_ROW_EN[0] = 0x10
5093 22:50:08.027822 EX_ROW_EN[1] = 0x0
5094 22:50:08.027909 LP4Y_EN = 0x0
5095 22:50:08.031306 WORK_FSP = 0x0
5096 22:50:08.031390 WL = 0x3
5097 22:50:08.034699 RL = 0x3
5098 22:50:08.034783 BL = 0x2
5099 22:50:08.037820 RPST = 0x0
5100 22:50:08.037902 RD_PRE = 0x0
5101 22:50:08.041527 WR_PRE = 0x1
5102 22:50:08.041611 WR_PST = 0x0
5103 22:50:08.044812 DBI_WR = 0x0
5104 22:50:08.044896 DBI_RD = 0x0
5105 22:50:08.047761 OTF = 0x1
5106 22:50:08.051676 ===================================
5107 22:50:08.058044 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5108 22:50:08.061388 nWR fixed to 30
5109 22:50:08.064590 [ModeRegInit_LP4] CH0 RK0
5110 22:50:08.064678 [ModeRegInit_LP4] CH0 RK1
5111 22:50:08.068279 [ModeRegInit_LP4] CH1 RK0
5112 22:50:08.071530 [ModeRegInit_LP4] CH1 RK1
5113 22:50:08.071616 match AC timing 9
5114 22:50:08.078046 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5115 22:50:08.081366 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5116 22:50:08.084813 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5117 22:50:08.091646 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5118 22:50:08.094709 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5119 22:50:08.094801 ==
5120 22:50:08.097860 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 22:50:08.101118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 22:50:08.101269 ==
5123 22:50:08.108348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 22:50:08.115164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5125 22:50:08.118240 [CA 0] Center 38 (8~69) winsize 62
5126 22:50:08.121404 [CA 1] Center 38 (7~69) winsize 63
5127 22:50:08.124417 [CA 2] Center 35 (5~66) winsize 62
5128 22:50:08.127770 [CA 3] Center 35 (4~66) winsize 63
5129 22:50:08.131088 [CA 4] Center 34 (4~64) winsize 61
5130 22:50:08.134393 [CA 5] Center 34 (4~64) winsize 61
5131 22:50:08.134487
5132 22:50:08.138260 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5133 22:50:08.138348
5134 22:50:08.142332 [CATrainingPosCal] consider 1 rank data
5135 22:50:08.144709 u2DelayCellTimex100 = 270/100 ps
5136 22:50:08.148366 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5137 22:50:08.151737 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5138 22:50:08.154679 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5139 22:50:08.157901 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5140 22:50:08.161185 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5141 22:50:08.164781 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5142 22:50:08.164864
5143 22:50:08.167681 CA PerBit enable=1, Macro0, CA PI delay=34
5144 22:50:08.171053
5145 22:50:08.171134 [CBTSetCACLKResult] CA Dly = 34
5146 22:50:08.174812 CS Dly: 6 (0~37)
5147 22:50:08.174897 ==
5148 22:50:08.178129 Dram Type= 6, Freq= 0, CH_0, rank 1
5149 22:50:08.180953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 22:50:08.181038 ==
5151 22:50:08.187696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5152 22:50:08.194624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5153 22:50:08.197845 [CA 0] Center 38 (7~69) winsize 63
5154 22:50:08.201176 [CA 1] Center 38 (8~69) winsize 62
5155 22:50:08.204652 [CA 2] Center 35 (5~66) winsize 62
5156 22:50:08.207972 [CA 3] Center 35 (4~66) winsize 63
5157 22:50:08.211419 [CA 4] Center 34 (3~65) winsize 63
5158 22:50:08.214815 [CA 5] Center 33 (3~64) winsize 62
5159 22:50:08.214898
5160 22:50:08.218049 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5161 22:50:08.218131
5162 22:50:08.221170 [CATrainingPosCal] consider 2 rank data
5163 22:50:08.224741 u2DelayCellTimex100 = 270/100 ps
5164 22:50:08.228041 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5165 22:50:08.231129 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5166 22:50:08.234808 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5167 22:50:08.237651 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5168 22:50:08.241580 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5169 22:50:08.244342 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5170 22:50:08.244450
5171 22:50:08.248037 CA PerBit enable=1, Macro0, CA PI delay=34
5172 22:50:08.248119
5173 22:50:08.251916 [CBTSetCACLKResult] CA Dly = 34
5174 22:50:08.254713 CS Dly: 7 (0~39)
5175 22:50:08.254794
5176 22:50:08.258258 ----->DramcWriteLeveling(PI) begin...
5177 22:50:08.258341 ==
5178 22:50:08.261429 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 22:50:08.264995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 22:50:08.265078 ==
5181 22:50:08.267953 Write leveling (Byte 0): 28 => 28
5182 22:50:08.271950 Write leveling (Byte 1): 27 => 27
5183 22:50:08.275437 DramcWriteLeveling(PI) end<-----
5184 22:50:08.275521
5185 22:50:08.275588 ==
5186 22:50:08.278155 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 22:50:08.281793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 22:50:08.281879 ==
5189 22:50:08.285004 [Gating] SW mode calibration
5190 22:50:08.291932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5191 22:50:08.298135 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5192 22:50:08.301743 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5193 22:50:08.304834 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5194 22:50:08.311595 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 22:50:08.314961 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 22:50:08.318377 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 22:50:08.325130 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 22:50:08.328608 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 22:50:08.331477 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 22:50:08.338065 0 15 0 | B1->B0 | 3131 2727 | 1 0 | (1 0) (1 0)
5201 22:50:08.341360 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5202 22:50:08.345236 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 22:50:08.351570 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 22:50:08.354751 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 22:50:08.358860 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 22:50:08.365113 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 22:50:08.368690 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5208 22:50:08.371628 1 0 0 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
5209 22:50:08.374979 1 0 4 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
5210 22:50:08.381656 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 22:50:08.385370 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 22:50:08.388246 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 22:50:08.394989 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 22:50:08.398289 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 22:50:08.401532 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 22:50:08.408646 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5217 22:50:08.411960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 22:50:08.415731 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 22:50:08.422229 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 22:50:08.424941 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 22:50:08.428155 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 22:50:08.434838 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 22:50:08.439086 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 22:50:08.441655 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 22:50:08.448325 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 22:50:08.452277 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 22:50:08.455352 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 22:50:08.458867 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 22:50:08.465200 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 22:50:08.468731 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 22:50:08.471715 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5232 22:50:08.479240 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5233 22:50:08.481914 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5234 22:50:08.485524 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 22:50:08.489087 Total UI for P1: 0, mck2ui 16
5236 22:50:08.492169 best dqsien dly found for B0: ( 1, 3, 0)
5237 22:50:08.495161 Total UI for P1: 0, mck2ui 16
5238 22:50:08.498864 best dqsien dly found for B1: ( 1, 3, 4)
5239 22:50:08.501942 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5240 22:50:08.505085 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5241 22:50:08.505168
5242 22:50:08.523971 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5243 22:50:08.524103 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5244 22:50:08.524170 [Gating] SW calibration Done
5245 22:50:08.524230 ==
5246 22:50:08.524290 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 22:50:08.525154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 22:50:08.525263 ==
5249 22:50:08.525356 RX Vref Scan: 0
5250 22:50:08.525438
5251 22:50:08.528549 RX Vref 0 -> 0, step: 1
5252 22:50:08.528630
5253 22:50:08.531957 RX Delay -80 -> 252, step: 8
5254 22:50:08.536079 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5255 22:50:08.538404 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5256 22:50:08.541961 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5257 22:50:08.545050 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5258 22:50:08.548528 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5259 22:50:08.555058 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5260 22:50:08.558336 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5261 22:50:08.561891 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5262 22:50:08.565403 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5263 22:50:08.568283 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5264 22:50:08.575308 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5265 22:50:08.578505 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5266 22:50:08.582109 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5267 22:50:08.585152 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5268 22:50:08.588363 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5269 22:50:08.592063 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5270 22:50:08.595741 ==
5271 22:50:08.598559 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 22:50:08.601952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 22:50:08.602037 ==
5274 22:50:08.602101 DQS Delay:
5275 22:50:08.605167 DQS0 = 0, DQS1 = 0
5276 22:50:08.605292 DQM Delay:
5277 22:50:08.608327 DQM0 = 97, DQM1 = 87
5278 22:50:08.608408 DQ Delay:
5279 22:50:08.612105 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5280 22:50:08.615484 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5281 22:50:08.618426 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5282 22:50:08.621723 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5283 22:50:08.621807
5284 22:50:08.621889
5285 22:50:08.622005 ==
5286 22:50:08.625007 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 22:50:08.629688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 22:50:08.629777 ==
5289 22:50:08.629842
5290 22:50:08.629902
5291 22:50:08.632037 TX Vref Scan disable
5292 22:50:08.635212 == TX Byte 0 ==
5293 22:50:08.638785 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5294 22:50:08.641876 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5295 22:50:08.645175 == TX Byte 1 ==
5296 22:50:08.648736 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5297 22:50:08.651762 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5298 22:50:08.651892 ==
5299 22:50:08.655910 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 22:50:08.658609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 22:50:08.658747 ==
5302 22:50:08.662095
5303 22:50:08.662227
5304 22:50:08.662350 TX Vref Scan disable
5305 22:50:08.665802 == TX Byte 0 ==
5306 22:50:08.668528 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5307 22:50:08.675277 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5308 22:50:08.675367 == TX Byte 1 ==
5309 22:50:08.678845 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5310 22:50:08.682094 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5311 22:50:08.685708
5312 22:50:08.685790 [DATLAT]
5313 22:50:08.685855 Freq=933, CH0 RK0
5314 22:50:08.685915
5315 22:50:08.688696 DATLAT Default: 0xd
5316 22:50:08.688778 0, 0xFFFF, sum = 0
5317 22:50:08.692315 1, 0xFFFF, sum = 0
5318 22:50:08.692400 2, 0xFFFF, sum = 0
5319 22:50:08.695382 3, 0xFFFF, sum = 0
5320 22:50:08.698493 4, 0xFFFF, sum = 0
5321 22:50:08.698577 5, 0xFFFF, sum = 0
5322 22:50:08.702103 6, 0xFFFF, sum = 0
5323 22:50:08.702187 7, 0xFFFF, sum = 0
5324 22:50:08.705622 8, 0xFFFF, sum = 0
5325 22:50:08.705705 9, 0xFFFF, sum = 0
5326 22:50:08.709028 10, 0x0, sum = 1
5327 22:50:08.709110 11, 0x0, sum = 2
5328 22:50:08.712155 12, 0x0, sum = 3
5329 22:50:08.712237 13, 0x0, sum = 4
5330 22:50:08.712302 best_step = 11
5331 22:50:08.712361
5332 22:50:08.715195 ==
5333 22:50:08.715281 Dram Type= 6, Freq= 0, CH_0, rank 0
5334 22:50:08.721918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 22:50:08.722002 ==
5336 22:50:08.722076 RX Vref Scan: 1
5337 22:50:08.722141
5338 22:50:08.725327 RX Vref 0 -> 0, step: 1
5339 22:50:08.725409
5340 22:50:08.728301 RX Delay -61 -> 252, step: 4
5341 22:50:08.728382
5342 22:50:08.732011 Set Vref, RX VrefLevel [Byte0]: 53
5343 22:50:08.735117 [Byte1]: 51
5344 22:50:08.735199
5345 22:50:08.738678 Final RX Vref Byte 0 = 53 to rank0
5346 22:50:08.741869 Final RX Vref Byte 1 = 51 to rank0
5347 22:50:08.745489 Final RX Vref Byte 0 = 53 to rank1
5348 22:50:08.748937 Final RX Vref Byte 1 = 51 to rank1==
5349 22:50:08.751832 Dram Type= 6, Freq= 0, CH_0, rank 0
5350 22:50:08.754970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 22:50:08.755114 ==
5352 22:50:08.759284 DQS Delay:
5353 22:50:08.759425 DQS0 = 0, DQS1 = 0
5354 22:50:08.761758 DQM Delay:
5355 22:50:08.761856 DQM0 = 97, DQM1 = 87
5356 22:50:08.761922 DQ Delay:
5357 22:50:08.765013 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5358 22:50:08.768330 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5359 22:50:08.771826 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =80
5360 22:50:08.775505 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5361 22:50:08.775606
5362 22:50:08.775671
5363 22:50:08.784993 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5364 22:50:08.788702 CH0 RK0: MR19=505, MR18=1601
5365 22:50:08.794919 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5366 22:50:08.795003
5367 22:50:08.798256 ----->DramcWriteLeveling(PI) begin...
5368 22:50:08.798339 ==
5369 22:50:08.801902 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 22:50:08.804806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 22:50:08.804889 ==
5372 22:50:08.808429 Write leveling (Byte 0): 31 => 31
5373 22:50:08.811677 Write leveling (Byte 1): 31 => 31
5374 22:50:08.815364 DramcWriteLeveling(PI) end<-----
5375 22:50:08.815445
5376 22:50:08.815509 ==
5377 22:50:08.818404 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 22:50:08.821860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 22:50:08.821941 ==
5380 22:50:08.824842 [Gating] SW mode calibration
5381 22:50:08.831699 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5382 22:50:08.838489 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5383 22:50:08.841647 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
5384 22:50:08.845137 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 22:50:08.852091 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 22:50:08.855253 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 22:50:08.858206 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 22:50:08.865018 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 22:50:08.868409 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 22:50:08.871479 0 14 28 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 1)
5391 22:50:08.879159 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
5392 22:50:08.881877 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 22:50:08.885326 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 22:50:08.888813 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 22:50:08.895607 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 22:50:08.899062 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 22:50:08.902785 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 22:50:08.908550 0 15 28 | B1->B0 | 2a2a 3030 | 0 0 | (0 0) (1 1)
5399 22:50:08.911586 1 0 0 | B1->B0 | 3938 4646 | 1 0 | (0 0) (0 0)
5400 22:50:08.914892 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 22:50:08.922060 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 22:50:08.925143 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 22:50:08.928354 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 22:50:08.934898 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 22:50:08.938396 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 22:50:08.941888 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5407 22:50:08.948463 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 22:50:08.951798 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 22:50:08.955399 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 22:50:08.961750 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 22:50:08.964977 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 22:50:08.968310 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 22:50:08.971776 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 22:50:08.978575 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 22:50:08.981608 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 22:50:08.985217 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 22:50:08.991995 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 22:50:08.995297 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 22:50:08.999406 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 22:50:09.005234 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 22:50:09.008728 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 22:50:09.012018 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5423 22:50:09.018609 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5424 22:50:09.018693 Total UI for P1: 0, mck2ui 16
5425 22:50:09.025990 best dqsien dly found for B0: ( 1, 2, 28)
5426 22:50:09.028680 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 22:50:09.031908 Total UI for P1: 0, mck2ui 16
5428 22:50:09.035404 best dqsien dly found for B1: ( 1, 3, 0)
5429 22:50:09.038535 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5430 22:50:09.042273 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5431 22:50:09.042356
5432 22:50:09.045648 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5433 22:50:09.048524 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5434 22:50:09.051922 [Gating] SW calibration Done
5435 22:50:09.052004 ==
5436 22:50:09.055209 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 22:50:09.058931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 22:50:09.059013 ==
5439 22:50:09.061814 RX Vref Scan: 0
5440 22:50:09.061895
5441 22:50:09.065451 RX Vref 0 -> 0, step: 1
5442 22:50:09.065533
5443 22:50:09.065596 RX Delay -80 -> 252, step: 8
5444 22:50:09.071824 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5445 22:50:09.075230 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5446 22:50:09.078695 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5447 22:50:09.081769 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5448 22:50:09.085212 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5449 22:50:09.088972 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5450 22:50:09.095034 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5451 22:50:09.098422 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5452 22:50:09.102935 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5453 22:50:09.105456 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5454 22:50:09.108567 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5455 22:50:09.111674 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5456 22:50:09.118211 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5457 22:50:09.122003 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5458 22:50:09.125294 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5459 22:50:09.128708 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5460 22:50:09.128823 ==
5461 22:50:09.131939 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 22:50:09.135964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 22:50:09.136046 ==
5464 22:50:09.138710 DQS Delay:
5465 22:50:09.138792 DQS0 = 0, DQS1 = 0
5466 22:50:09.141694 DQM Delay:
5467 22:50:09.141779 DQM0 = 97, DQM1 = 87
5468 22:50:09.141844 DQ Delay:
5469 22:50:09.145511 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5470 22:50:09.148746 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5471 22:50:09.151784 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5472 22:50:09.155020 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5473 22:50:09.155102
5474 22:50:09.159376
5475 22:50:09.159456 ==
5476 22:50:09.162164 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 22:50:09.165162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 22:50:09.165250 ==
5479 22:50:09.165316
5480 22:50:09.165375
5481 22:50:09.168212 TX Vref Scan disable
5482 22:50:09.168293 == TX Byte 0 ==
5483 22:50:09.175274 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5484 22:50:09.178383 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5485 22:50:09.178465 == TX Byte 1 ==
5486 22:50:09.184988 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5487 22:50:09.188052 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5488 22:50:09.188134 ==
5489 22:50:09.191535 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 22:50:09.194988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 22:50:09.195071 ==
5492 22:50:09.195135
5493 22:50:09.195193
5494 22:50:09.198150 TX Vref Scan disable
5495 22:50:09.201781 == TX Byte 0 ==
5496 22:50:09.205045 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5497 22:50:09.208060 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5498 22:50:09.212453 == TX Byte 1 ==
5499 22:50:09.215154 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5500 22:50:09.218298 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5501 22:50:09.218379
5502 22:50:09.221514 [DATLAT]
5503 22:50:09.221595 Freq=933, CH0 RK1
5504 22:50:09.221659
5505 22:50:09.224978 DATLAT Default: 0xb
5506 22:50:09.225059 0, 0xFFFF, sum = 0
5507 22:50:09.228406 1, 0xFFFF, sum = 0
5508 22:50:09.228490 2, 0xFFFF, sum = 0
5509 22:50:09.231633 3, 0xFFFF, sum = 0
5510 22:50:09.231715 4, 0xFFFF, sum = 0
5511 22:50:09.234750 5, 0xFFFF, sum = 0
5512 22:50:09.234833 6, 0xFFFF, sum = 0
5513 22:50:09.238358 7, 0xFFFF, sum = 0
5514 22:50:09.238440 8, 0xFFFF, sum = 0
5515 22:50:09.242746 9, 0xFFFF, sum = 0
5516 22:50:09.242828 10, 0x0, sum = 1
5517 22:50:09.245612 11, 0x0, sum = 2
5518 22:50:09.245694 12, 0x0, sum = 3
5519 22:50:09.248254 13, 0x0, sum = 4
5520 22:50:09.248336 best_step = 11
5521 22:50:09.248400
5522 22:50:09.248458 ==
5523 22:50:09.251596 Dram Type= 6, Freq= 0, CH_0, rank 1
5524 22:50:09.255084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 22:50:09.257983 ==
5526 22:50:09.258065 RX Vref Scan: 0
5527 22:50:09.258129
5528 22:50:09.261960 RX Vref 0 -> 0, step: 1
5529 22:50:09.262041
5530 22:50:09.264786 RX Delay -61 -> 252, step: 4
5531 22:50:09.268345 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5532 22:50:09.271202 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5533 22:50:09.275021 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5534 22:50:09.281400 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5535 22:50:09.284749 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5536 22:50:09.287976 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5537 22:50:09.291406 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5538 22:50:09.294622 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5539 22:50:09.301420 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5540 22:50:09.304696 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5541 22:50:09.307994 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5542 22:50:09.311984 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5543 22:50:09.314685 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5544 22:50:09.318024 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5545 22:50:09.324843 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5546 22:50:09.328168 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5547 22:50:09.328252 ==
5548 22:50:09.331141 Dram Type= 6, Freq= 0, CH_0, rank 1
5549 22:50:09.335232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 22:50:09.335315 ==
5551 22:50:09.337766 DQS Delay:
5552 22:50:09.337847 DQS0 = 0, DQS1 = 0
5553 22:50:09.337912 DQM Delay:
5554 22:50:09.341751 DQM0 = 95, DQM1 = 87
5555 22:50:09.341832 DQ Delay:
5556 22:50:09.344731 DQ0 =96, DQ1 =94, DQ2 =92, DQ3 =94
5557 22:50:09.347988 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5558 22:50:09.351324 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =78
5559 22:50:09.354652 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5560 22:50:09.354733
5561 22:50:09.354798
5562 22:50:09.365184 [DQSOSCAuto] RK1, (LSB)MR18= 0x1906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5563 22:50:09.365275 CH0 RK1: MR19=505, MR18=1906
5564 22:50:09.371501 CH0_RK1: MR19=0x505, MR18=0x1906, DQSOSC=413, MR23=63, INC=63, DEC=42
5565 22:50:09.374846 [RxdqsGatingPostProcess] freq 933
5566 22:50:09.381332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5567 22:50:09.384660 best DQS0 dly(2T, 0.5T) = (0, 11)
5568 22:50:09.388577 best DQS1 dly(2T, 0.5T) = (0, 11)
5569 22:50:09.391274 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5570 22:50:09.394521 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5571 22:50:09.397793 best DQS0 dly(2T, 0.5T) = (0, 10)
5572 22:50:09.397875 best DQS1 dly(2T, 0.5T) = (0, 11)
5573 22:50:09.401331 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5574 22:50:09.405089 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5575 22:50:09.407807 Pre-setting of DQS Precalculation
5576 22:50:09.415784 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5577 22:50:09.415869 ==
5578 22:50:09.418207 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 22:50:09.421529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 22:50:09.421611 ==
5581 22:50:09.428424 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5582 22:50:09.431627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5583 22:50:09.435840 [CA 0] Center 36 (6~67) winsize 62
5584 22:50:09.439971 [CA 1] Center 36 (6~67) winsize 62
5585 22:50:09.442764 [CA 2] Center 34 (4~64) winsize 61
5586 22:50:09.445846 [CA 3] Center 33 (3~64) winsize 62
5587 22:50:09.449612 [CA 4] Center 33 (3~64) winsize 62
5588 22:50:09.452679 [CA 5] Center 33 (3~63) winsize 61
5589 22:50:09.452786
5590 22:50:09.456135 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5591 22:50:09.456218
5592 22:50:09.459422 [CATrainingPosCal] consider 1 rank data
5593 22:50:09.462351 u2DelayCellTimex100 = 270/100 ps
5594 22:50:09.466206 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5595 22:50:09.469497 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5596 22:50:09.475756 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5597 22:50:09.479484 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5598 22:50:09.482633 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5599 22:50:09.485849 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5600 22:50:09.485933
5601 22:50:09.489685 CA PerBit enable=1, Macro0, CA PI delay=33
5602 22:50:09.489768
5603 22:50:09.493012 [CBTSetCACLKResult] CA Dly = 33
5604 22:50:09.493120 CS Dly: 4 (0~35)
5605 22:50:09.493219 ==
5606 22:50:09.495876 Dram Type= 6, Freq= 0, CH_1, rank 1
5607 22:50:09.502727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 22:50:09.502821 ==
5609 22:50:09.506439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5610 22:50:09.512729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5611 22:50:09.515930 [CA 0] Center 36 (6~67) winsize 62
5612 22:50:09.519349 [CA 1] Center 36 (6~67) winsize 62
5613 22:50:09.522974 [CA 2] Center 34 (4~64) winsize 61
5614 22:50:09.525902 [CA 3] Center 33 (3~64) winsize 62
5615 22:50:09.529475 [CA 4] Center 34 (4~64) winsize 61
5616 22:50:09.532771 [CA 5] Center 33 (3~63) winsize 61
5617 22:50:09.532856
5618 22:50:09.535883 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5619 22:50:09.535966
5620 22:50:09.539814 [CATrainingPosCal] consider 2 rank data
5621 22:50:09.542498 u2DelayCellTimex100 = 270/100 ps
5622 22:50:09.546405 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5623 22:50:09.549368 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5624 22:50:09.553197 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5625 22:50:09.559742 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5626 22:50:09.562595 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5627 22:50:09.566668 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5628 22:50:09.566755
5629 22:50:09.569802 CA PerBit enable=1, Macro0, CA PI delay=33
5630 22:50:09.569885
5631 22:50:09.572800 [CBTSetCACLKResult] CA Dly = 33
5632 22:50:09.572882 CS Dly: 5 (0~38)
5633 22:50:09.572946
5634 22:50:09.576422 ----->DramcWriteLeveling(PI) begin...
5635 22:50:09.576505 ==
5636 22:50:09.579296 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 22:50:09.586568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 22:50:09.586653 ==
5639 22:50:09.589401 Write leveling (Byte 0): 25 => 25
5640 22:50:09.592798 Write leveling (Byte 1): 28 => 28
5641 22:50:09.592881 DramcWriteLeveling(PI) end<-----
5642 22:50:09.596114
5643 22:50:09.596195 ==
5644 22:50:09.599727 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 22:50:09.602574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 22:50:09.602657 ==
5647 22:50:09.606394 [Gating] SW mode calibration
5648 22:50:09.612581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5649 22:50:09.615917 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5650 22:50:09.623138 0 14 0 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
5651 22:50:09.625983 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 22:50:09.629368 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5653 22:50:09.635925 0 14 12 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5654 22:50:09.639474 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5655 22:50:09.642811 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 22:50:09.649882 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5657 22:50:09.653860 0 14 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (1 0)
5658 22:50:09.656237 0 15 0 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
5659 22:50:09.662483 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 22:50:09.665984 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 22:50:09.669922 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 22:50:09.673162 0 15 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5663 22:50:09.679488 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5664 22:50:09.682720 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 22:50:09.687265 0 15 28 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
5666 22:50:09.693229 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 22:50:09.696258 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 22:50:09.699885 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 22:50:09.705948 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 22:50:09.710000 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 22:50:09.712537 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 22:50:09.719504 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 22:50:09.723487 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5674 22:50:09.726452 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5675 22:50:09.732897 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 22:50:09.736216 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 22:50:09.739430 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 22:50:09.745980 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 22:50:09.750000 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 22:50:09.752750 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 22:50:09.759654 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 22:50:09.762627 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 22:50:09.766493 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 22:50:09.769450 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 22:50:09.776022 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 22:50:09.779925 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 22:50:09.782929 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 22:50:09.789854 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 22:50:09.792636 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5690 22:50:09.796284 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5691 22:50:09.803078 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 22:50:09.806446 Total UI for P1: 0, mck2ui 16
5693 22:50:09.809163 best dqsien dly found for B0: ( 1, 2, 30)
5694 22:50:09.809260 Total UI for P1: 0, mck2ui 16
5695 22:50:09.816042 best dqsien dly found for B1: ( 1, 2, 30)
5696 22:50:09.819405 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5697 22:50:09.823057 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5698 22:50:09.823141
5699 22:50:09.826494 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5700 22:50:09.830010 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5701 22:50:09.833265 [Gating] SW calibration Done
5702 22:50:09.833348 ==
5703 22:50:09.836740 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 22:50:09.839330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 22:50:09.839414 ==
5706 22:50:09.842668 RX Vref Scan: 0
5707 22:50:09.842750
5708 22:50:09.842815 RX Vref 0 -> 0, step: 1
5709 22:50:09.842875
5710 22:50:09.846314 RX Delay -80 -> 252, step: 8
5711 22:50:09.849539 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5712 22:50:09.856635 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5713 22:50:09.859352 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5714 22:50:09.862886 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5715 22:50:09.866196 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5716 22:50:09.869841 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5717 22:50:09.872618 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5718 22:50:09.876233 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5719 22:50:09.882628 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5720 22:50:09.886280 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5721 22:50:09.889583 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5722 22:50:09.892737 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5723 22:50:09.896348 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5724 22:50:09.899516 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5725 22:50:09.906682 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5726 22:50:09.910593 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5727 22:50:09.910675 ==
5728 22:50:09.913433 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 22:50:09.916366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 22:50:09.916447 ==
5731 22:50:09.919956 DQS Delay:
5732 22:50:09.920037 DQS0 = 0, DQS1 = 0
5733 22:50:09.920101 DQM Delay:
5734 22:50:09.923671 DQM0 = 96, DQM1 = 88
5735 22:50:09.923752 DQ Delay:
5736 22:50:09.926215 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =95
5737 22:50:09.929586 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5738 22:50:09.933115 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5739 22:50:09.936290 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5740 22:50:09.936371
5741 22:50:09.936435
5742 22:50:09.936493 ==
5743 22:50:09.940191 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 22:50:09.946269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 22:50:09.946351 ==
5746 22:50:09.946415
5747 22:50:09.946474
5748 22:50:09.946530 TX Vref Scan disable
5749 22:50:09.950792 == TX Byte 0 ==
5750 22:50:09.952971 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5751 22:50:09.956290 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5752 22:50:09.960027 == TX Byte 1 ==
5753 22:50:09.963475 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5754 22:50:09.966441 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5755 22:50:09.969945 ==
5756 22:50:09.973186 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 22:50:09.976279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 22:50:09.976360 ==
5759 22:50:09.976424
5760 22:50:09.976497
5761 22:50:09.980153 TX Vref Scan disable
5762 22:50:09.980235 == TX Byte 0 ==
5763 22:50:09.986859 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5764 22:50:09.990145 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5765 22:50:09.990233 == TX Byte 1 ==
5766 22:50:09.997185 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5767 22:50:10.000537 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5768 22:50:10.000622
5769 22:50:10.000688 [DATLAT]
5770 22:50:10.003903 Freq=933, CH1 RK0
5771 22:50:10.003987
5772 22:50:10.004052 DATLAT Default: 0xd
5773 22:50:10.006702 0, 0xFFFF, sum = 0
5774 22:50:10.006786 1, 0xFFFF, sum = 0
5775 22:50:10.009982 2, 0xFFFF, sum = 0
5776 22:50:10.010066 3, 0xFFFF, sum = 0
5777 22:50:10.013144 4, 0xFFFF, sum = 0
5778 22:50:10.013265 5, 0xFFFF, sum = 0
5779 22:50:10.016476 6, 0xFFFF, sum = 0
5780 22:50:10.016560 7, 0xFFFF, sum = 0
5781 22:50:10.020203 8, 0xFFFF, sum = 0
5782 22:50:10.020287 9, 0xFFFF, sum = 0
5783 22:50:10.023361 10, 0x0, sum = 1
5784 22:50:10.023447 11, 0x0, sum = 2
5785 22:50:10.026637 12, 0x0, sum = 3
5786 22:50:10.026724 13, 0x0, sum = 4
5787 22:50:10.029805 best_step = 11
5788 22:50:10.029889
5789 22:50:10.029954 ==
5790 22:50:10.033174 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 22:50:10.036366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 22:50:10.036449 ==
5793 22:50:10.039829 RX Vref Scan: 1
5794 22:50:10.039911
5795 22:50:10.039976 RX Vref 0 -> 0, step: 1
5796 22:50:10.040037
5797 22:50:10.043707 RX Delay -61 -> 252, step: 4
5798 22:50:10.043789
5799 22:50:10.046733 Set Vref, RX VrefLevel [Byte0]: 54
5800 22:50:10.049635 [Byte1]: 54
5801 22:50:10.054218
5802 22:50:10.054301 Final RX Vref Byte 0 = 54 to rank0
5803 22:50:10.056915 Final RX Vref Byte 1 = 54 to rank0
5804 22:50:10.060594 Final RX Vref Byte 0 = 54 to rank1
5805 22:50:10.063455 Final RX Vref Byte 1 = 54 to rank1==
5806 22:50:10.066799 Dram Type= 6, Freq= 0, CH_1, rank 0
5807 22:50:10.073609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 22:50:10.073694 ==
5809 22:50:10.073760 DQS Delay:
5810 22:50:10.073820 DQS0 = 0, DQS1 = 0
5811 22:50:10.077157 DQM Delay:
5812 22:50:10.077282 DQM0 = 98, DQM1 = 90
5813 22:50:10.080267 DQ Delay:
5814 22:50:10.083477 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =98
5815 22:50:10.087118 DQ4 =98, DQ5 =108, DQ6 =108, DQ7 =96
5816 22:50:10.090149 DQ8 =80, DQ9 =80, DQ10 =94, DQ11 =86
5817 22:50:10.093666 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5818 22:50:10.093750
5819 22:50:10.093814
5820 22:50:10.100883 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5821 22:50:10.103746 CH1 RK0: MR19=504, MR18=17F4
5822 22:50:10.110366 CH1_RK0: MR19=0x504, MR18=0x17F4, DQSOSC=414, MR23=63, INC=63, DEC=42
5823 22:50:10.110453
5824 22:50:10.113555 ----->DramcWriteLeveling(PI) begin...
5825 22:50:10.113638 ==
5826 22:50:10.117080 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 22:50:10.120199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 22:50:10.120282 ==
5829 22:50:10.123620 Write leveling (Byte 0): 24 => 24
5830 22:50:10.127107 Write leveling (Byte 1): 26 => 26
5831 22:50:10.130047 DramcWriteLeveling(PI) end<-----
5832 22:50:10.130130
5833 22:50:10.130195 ==
5834 22:50:10.133567 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 22:50:10.136692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 22:50:10.136779 ==
5837 22:50:10.139950 [Gating] SW mode calibration
5838 22:50:10.146680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5839 22:50:10.153656 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5840 22:50:10.156861 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5841 22:50:10.160439 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5842 22:50:10.166956 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5843 22:50:10.170220 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5844 22:50:10.173500 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5845 22:50:10.180143 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 22:50:10.183659 0 14 24 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
5847 22:50:10.186889 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5848 22:50:10.193423 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 22:50:10.196973 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 22:50:10.200199 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 22:50:10.207297 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 22:50:10.210577 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5853 22:50:10.213694 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 22:50:10.220530 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
5855 22:50:10.223910 0 15 28 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
5856 22:50:10.227412 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 22:50:10.231016 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 22:50:10.237132 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 22:50:10.240891 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 22:50:10.243965 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 22:50:10.250549 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 22:50:10.253871 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5863 22:50:10.257211 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5864 22:50:10.264148 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5865 22:50:10.267739 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 22:50:10.270848 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 22:50:10.278428 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 22:50:10.280710 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 22:50:10.283770 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 22:50:10.290996 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 22:50:10.294071 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 22:50:10.297474 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 22:50:10.303648 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 22:50:10.307064 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 22:50:10.310842 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 22:50:10.314213 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 22:50:10.320444 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 22:50:10.323917 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5879 22:50:10.327144 Total UI for P1: 0, mck2ui 16
5880 22:50:10.330730 best dqsien dly found for B0: ( 1, 2, 22)
5881 22:50:10.333687 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 22:50:10.337168 Total UI for P1: 0, mck2ui 16
5883 22:50:10.340339 best dqsien dly found for B1: ( 1, 2, 24)
5884 22:50:10.343758 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5885 22:50:10.347897 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5886 22:50:10.347980
5887 22:50:10.353607 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5888 22:50:10.357083 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5889 22:50:10.360776 [Gating] SW calibration Done
5890 22:50:10.360860 ==
5891 22:50:10.363808 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 22:50:10.367206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 22:50:10.367289 ==
5894 22:50:10.367354 RX Vref Scan: 0
5895 22:50:10.367414
5896 22:50:10.370629 RX Vref 0 -> 0, step: 1
5897 22:50:10.370713
5898 22:50:10.373808 RX Delay -80 -> 252, step: 8
5899 22:50:10.377093 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5900 22:50:10.380568 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5901 22:50:10.384065 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5902 22:50:10.390531 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5903 22:50:10.394367 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5904 22:50:10.397075 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5905 22:50:10.400840 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5906 22:50:10.403886 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5907 22:50:10.407718 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5908 22:50:10.413881 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5909 22:50:10.417456 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5910 22:50:10.420644 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5911 22:50:10.423856 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5912 22:50:10.427387 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5913 22:50:10.430799 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5914 22:50:10.436937 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5915 22:50:10.437020 ==
5916 22:50:10.440283 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 22:50:10.443834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 22:50:10.443916 ==
5919 22:50:10.443980 DQS Delay:
5920 22:50:10.447082 DQS0 = 0, DQS1 = 0
5921 22:50:10.447163 DQM Delay:
5922 22:50:10.450687 DQM0 = 94, DQM1 = 89
5923 22:50:10.450768 DQ Delay:
5924 22:50:10.453598 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5925 22:50:10.457148 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5926 22:50:10.461015 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5927 22:50:10.463700 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5928 22:50:10.463782
5929 22:50:10.463847
5930 22:50:10.463906 ==
5931 22:50:10.467322 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 22:50:10.470342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 22:50:10.470423 ==
5934 22:50:10.470488
5935 22:50:10.473675
5936 22:50:10.473756 TX Vref Scan disable
5937 22:50:10.477475 == TX Byte 0 ==
5938 22:50:10.480528 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5939 22:50:10.484292 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5940 22:50:10.486990 == TX Byte 1 ==
5941 22:50:10.490757 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5942 22:50:10.493680 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5943 22:50:10.493761 ==
5944 22:50:10.497478 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 22:50:10.504183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 22:50:10.504267 ==
5947 22:50:10.504330
5948 22:50:10.504388
5949 22:50:10.504445 TX Vref Scan disable
5950 22:50:10.507942 == TX Byte 0 ==
5951 22:50:10.511371 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5952 22:50:10.514441 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5953 22:50:10.517755 == TX Byte 1 ==
5954 22:50:10.521076 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5955 22:50:10.524636 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5956 22:50:10.527703
5957 22:50:10.527790 [DATLAT]
5958 22:50:10.527855 Freq=933, CH1 RK1
5959 22:50:10.527916
5960 22:50:10.531040 DATLAT Default: 0xb
5961 22:50:10.531126 0, 0xFFFF, sum = 0
5962 22:50:10.534980 1, 0xFFFF, sum = 0
5963 22:50:10.535065 2, 0xFFFF, sum = 0
5964 22:50:10.538187 3, 0xFFFF, sum = 0
5965 22:50:10.538272 4, 0xFFFF, sum = 0
5966 22:50:10.541084 5, 0xFFFF, sum = 0
5967 22:50:10.544806 6, 0xFFFF, sum = 0
5968 22:50:10.544890 7, 0xFFFF, sum = 0
5969 22:50:10.547605 8, 0xFFFF, sum = 0
5970 22:50:10.547689 9, 0xFFFF, sum = 0
5971 22:50:10.551341 10, 0x0, sum = 1
5972 22:50:10.551425 11, 0x0, sum = 2
5973 22:50:10.551491 12, 0x0, sum = 3
5974 22:50:10.554401 13, 0x0, sum = 4
5975 22:50:10.554484 best_step = 11
5976 22:50:10.554550
5977 22:50:10.554610 ==
5978 22:50:10.558383 Dram Type= 6, Freq= 0, CH_1, rank 1
5979 22:50:10.564743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5980 22:50:10.564827 ==
5981 22:50:10.564892 RX Vref Scan: 0
5982 22:50:10.564953
5983 22:50:10.567821 RX Vref 0 -> 0, step: 1
5984 22:50:10.567903
5985 22:50:10.571310 RX Delay -61 -> 252, step: 4
5986 22:50:10.574895 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5987 22:50:10.577730 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5988 22:50:10.584586 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5989 22:50:10.588288 iDelay=199, Bit 3, Center 90 (-1 ~ 182) 184
5990 22:50:10.591481 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5991 22:50:10.594661 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5992 22:50:10.598609 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5993 22:50:10.601328 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5994 22:50:10.607708 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5995 22:50:10.611592 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5996 22:50:10.615105 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5997 22:50:10.618263 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5998 22:50:10.622072 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5999 22:50:10.628284 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
6000 22:50:10.631274 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
6001 22:50:10.634813 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
6002 22:50:10.634899 ==
6003 22:50:10.637865 Dram Type= 6, Freq= 0, CH_1, rank 1
6004 22:50:10.640998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6005 22:50:10.641115 ==
6006 22:50:10.644599 DQS Delay:
6007 22:50:10.644697 DQS0 = 0, DQS1 = 0
6008 22:50:10.647731 DQM Delay:
6009 22:50:10.647814 DQM0 = 94, DQM1 = 91
6010 22:50:10.647879 DQ Delay:
6011 22:50:10.651265 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =90
6012 22:50:10.654639 DQ4 =94, DQ5 =104, DQ6 =104, DQ7 =90
6013 22:50:10.658540 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
6014 22:50:10.661720 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
6015 22:50:10.661806
6016 22:50:10.664688
6017 22:50:10.671120 [DQSOSCAuto] RK1, (LSB)MR18= 0xa14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
6018 22:50:10.675306 CH1 RK1: MR19=505, MR18=A14
6019 22:50:10.681244 CH1_RK1: MR19=0x505, MR18=0xA14, DQSOSC=415, MR23=63, INC=62, DEC=41
6020 22:50:10.681344 [RxdqsGatingPostProcess] freq 933
6021 22:50:10.687738 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6022 22:50:10.691150 best DQS0 dly(2T, 0.5T) = (0, 10)
6023 22:50:10.694795 best DQS1 dly(2T, 0.5T) = (0, 10)
6024 22:50:10.697816 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6025 22:50:10.701162 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6026 22:50:10.704452 best DQS0 dly(2T, 0.5T) = (0, 10)
6027 22:50:10.708094 best DQS1 dly(2T, 0.5T) = (0, 10)
6028 22:50:10.710860 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6029 22:50:10.714715 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6030 22:50:10.717856 Pre-setting of DQS Precalculation
6031 22:50:10.721598 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6032 22:50:10.727709 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6033 22:50:10.735025 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6034 22:50:10.735119
6035 22:50:10.737732
6036 22:50:10.737815 [Calibration Summary] 1866 Mbps
6037 22:50:10.741634 CH 0, Rank 0
6038 22:50:10.741717 SW Impedance : PASS
6039 22:50:10.744364 DUTY Scan : NO K
6040 22:50:10.748261 ZQ Calibration : PASS
6041 22:50:10.748344 Jitter Meter : NO K
6042 22:50:10.751060 CBT Training : PASS
6043 22:50:10.754384 Write leveling : PASS
6044 22:50:10.754466 RX DQS gating : PASS
6045 22:50:10.757535 RX DQ/DQS(RDDQC) : PASS
6046 22:50:10.761073 TX DQ/DQS : PASS
6047 22:50:10.761156 RX DATLAT : PASS
6048 22:50:10.764359 RX DQ/DQS(Engine): PASS
6049 22:50:10.764441 TX OE : NO K
6050 22:50:10.767768 All Pass.
6051 22:50:10.767852
6052 22:50:10.767917 CH 0, Rank 1
6053 22:50:10.771755 SW Impedance : PASS
6054 22:50:10.771839 DUTY Scan : NO K
6055 22:50:10.774388 ZQ Calibration : PASS
6056 22:50:10.777818 Jitter Meter : NO K
6057 22:50:10.777902 CBT Training : PASS
6058 22:50:10.781132 Write leveling : PASS
6059 22:50:10.784755 RX DQS gating : PASS
6060 22:50:10.784838 RX DQ/DQS(RDDQC) : PASS
6061 22:50:10.787668 TX DQ/DQS : PASS
6062 22:50:10.791388 RX DATLAT : PASS
6063 22:50:10.791471 RX DQ/DQS(Engine): PASS
6064 22:50:10.794430 TX OE : NO K
6065 22:50:10.794513 All Pass.
6066 22:50:10.794578
6067 22:50:10.798047 CH 1, Rank 0
6068 22:50:10.798129 SW Impedance : PASS
6069 22:50:10.801094 DUTY Scan : NO K
6070 22:50:10.804671 ZQ Calibration : PASS
6071 22:50:10.804755 Jitter Meter : NO K
6072 22:50:10.807890 CBT Training : PASS
6073 22:50:10.811094 Write leveling : PASS
6074 22:50:10.811176 RX DQS gating : PASS
6075 22:50:10.814532 RX DQ/DQS(RDDQC) : PASS
6076 22:50:10.814615 TX DQ/DQS : PASS
6077 22:50:10.817647 RX DATLAT : PASS
6078 22:50:10.821133 RX DQ/DQS(Engine): PASS
6079 22:50:10.821223 TX OE : NO K
6080 22:50:10.824785 All Pass.
6081 22:50:10.824868
6082 22:50:10.824933 CH 1, Rank 1
6083 22:50:10.827786 SW Impedance : PASS
6084 22:50:10.827867 DUTY Scan : NO K
6085 22:50:10.831003 ZQ Calibration : PASS
6086 22:50:10.834410 Jitter Meter : NO K
6087 22:50:10.834492 CBT Training : PASS
6088 22:50:10.837563 Write leveling : PASS
6089 22:50:10.841004 RX DQS gating : PASS
6090 22:50:10.841086 RX DQ/DQS(RDDQC) : PASS
6091 22:50:10.845115 TX DQ/DQS : PASS
6092 22:50:10.845201 RX DATLAT : PASS
6093 22:50:10.848279 RX DQ/DQS(Engine): PASS
6094 22:50:10.851463 TX OE : NO K
6095 22:50:10.851545 All Pass.
6096 22:50:10.851610
6097 22:50:10.854698 DramC Write-DBI off
6098 22:50:10.857670 PER_BANK_REFRESH: Hybrid Mode
6099 22:50:10.857752 TX_TRACKING: ON
6100 22:50:10.867743 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6101 22:50:10.871027 [FAST_K] Save calibration result to emmc
6102 22:50:10.874314 dramc_set_vcore_voltage set vcore to 650000
6103 22:50:10.874397 Read voltage for 400, 6
6104 22:50:10.877665 Vio18 = 0
6105 22:50:10.877747 Vcore = 650000
6106 22:50:10.877812 Vdram = 0
6107 22:50:10.881212 Vddq = 0
6108 22:50:10.881327 Vmddr = 0
6109 22:50:10.884310 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6110 22:50:10.892424 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6111 22:50:10.894438 MEM_TYPE=3, freq_sel=20
6112 22:50:10.897895 sv_algorithm_assistance_LP4_800
6113 22:50:10.901419 ============ PULL DRAM RESETB DOWN ============
6114 22:50:10.904592 ========== PULL DRAM RESETB DOWN end =========
6115 22:50:10.911283 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6116 22:50:10.914862 ===================================
6117 22:50:10.914945 LPDDR4 DRAM CONFIGURATION
6118 22:50:10.917963 ===================================
6119 22:50:10.921484 EX_ROW_EN[0] = 0x0
6120 22:50:10.921566 EX_ROW_EN[1] = 0x0
6121 22:50:10.924550 LP4Y_EN = 0x0
6122 22:50:10.924632 WORK_FSP = 0x0
6123 22:50:10.927931 WL = 0x2
6124 22:50:10.928012 RL = 0x2
6125 22:50:10.932021 BL = 0x2
6126 22:50:10.935128 RPST = 0x0
6127 22:50:10.935211 RD_PRE = 0x0
6128 22:50:10.937688 WR_PRE = 0x1
6129 22:50:10.937769 WR_PST = 0x0
6130 22:50:10.941025 DBI_WR = 0x0
6131 22:50:10.941107 DBI_RD = 0x0
6132 22:50:10.944798 OTF = 0x1
6133 22:50:10.948173 ===================================
6134 22:50:10.951472 ===================================
6135 22:50:10.951554 ANA top config
6136 22:50:10.955077 ===================================
6137 22:50:10.958313 DLL_ASYNC_EN = 0
6138 22:50:10.958394 ALL_SLAVE_EN = 1
6139 22:50:10.961385 NEW_RANK_MODE = 1
6140 22:50:10.964724 DLL_IDLE_MODE = 1
6141 22:50:10.968172 LP45_APHY_COMB_EN = 1
6142 22:50:10.971300 TX_ODT_DIS = 1
6143 22:50:10.971382 NEW_8X_MODE = 1
6144 22:50:10.974940 ===================================
6145 22:50:10.978112 ===================================
6146 22:50:10.981776 data_rate = 800
6147 22:50:10.984501 CKR = 1
6148 22:50:10.988305 DQ_P2S_RATIO = 4
6149 22:50:10.991680 ===================================
6150 22:50:10.994927 CA_P2S_RATIO = 4
6151 22:50:10.998157 DQ_CA_OPEN = 0
6152 22:50:10.998239 DQ_SEMI_OPEN = 1
6153 22:50:11.001816 CA_SEMI_OPEN = 1
6154 22:50:11.004868 CA_FULL_RATE = 0
6155 22:50:11.008197 DQ_CKDIV4_EN = 0
6156 22:50:11.011441 CA_CKDIV4_EN = 1
6157 22:50:11.011523 CA_PREDIV_EN = 0
6158 22:50:11.014667 PH8_DLY = 0
6159 22:50:11.018704 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6160 22:50:11.021714 DQ_AAMCK_DIV = 0
6161 22:50:11.024448 CA_AAMCK_DIV = 0
6162 22:50:11.028099 CA_ADMCK_DIV = 4
6163 22:50:11.028180 DQ_TRACK_CA_EN = 0
6164 22:50:11.031198 CA_PICK = 800
6165 22:50:11.035003 CA_MCKIO = 400
6166 22:50:11.037812 MCKIO_SEMI = 400
6167 22:50:11.041562 PLL_FREQ = 3016
6168 22:50:11.045650 DQ_UI_PI_RATIO = 32
6169 22:50:11.048223 CA_UI_PI_RATIO = 32
6170 22:50:11.051628 ===================================
6171 22:50:11.055140 ===================================
6172 22:50:11.055222 memory_type:LPDDR4
6173 22:50:11.057937 GP_NUM : 10
6174 22:50:11.061402 SRAM_EN : 1
6175 22:50:11.061484 MD32_EN : 0
6176 22:50:11.064815 ===================================
6177 22:50:11.068102 [ANA_INIT] >>>>>>>>>>>>>>
6178 22:50:11.071432 <<<<<< [CONFIGURE PHASE]: ANA_TX
6179 22:50:11.075320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6180 22:50:11.078261 ===================================
6181 22:50:11.081814 data_rate = 800,PCW = 0X7400
6182 22:50:11.084625 ===================================
6183 22:50:11.088326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6184 22:50:11.091526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6185 22:50:11.105094 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6186 22:50:11.107917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6187 22:50:11.111256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6188 22:50:11.114866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6189 22:50:11.118165 [ANA_INIT] flow start
6190 22:50:11.118246 [ANA_INIT] PLL >>>>>>>>
6191 22:50:11.121388 [ANA_INIT] PLL <<<<<<<<
6192 22:50:11.124806 [ANA_INIT] MIDPI >>>>>>>>
6193 22:50:11.127972 [ANA_INIT] MIDPI <<<<<<<<
6194 22:50:11.128070 [ANA_INIT] DLL >>>>>>>>
6195 22:50:11.131592 [ANA_INIT] flow end
6196 22:50:11.134668 ============ LP4 DIFF to SE enter ============
6197 22:50:11.138351 ============ LP4 DIFF to SE exit ============
6198 22:50:11.141128 [ANA_INIT] <<<<<<<<<<<<<
6199 22:50:11.144851 [Flow] Enable top DCM control >>>>>
6200 22:50:11.148079 [Flow] Enable top DCM control <<<<<
6201 22:50:11.151434 Enable DLL master slave shuffle
6202 22:50:11.154853 ==============================================================
6203 22:50:11.157821 Gating Mode config
6204 22:50:11.164761 ==============================================================
6205 22:50:11.164843 Config description:
6206 22:50:11.174705 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6207 22:50:11.181615 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6208 22:50:11.187825 SELPH_MODE 0: By rank 1: By Phase
6209 22:50:11.191181 ==============================================================
6210 22:50:11.194716 GAT_TRACK_EN = 0
6211 22:50:11.197785 RX_GATING_MODE = 2
6212 22:50:11.201183 RX_GATING_TRACK_MODE = 2
6213 22:50:11.204489 SELPH_MODE = 1
6214 22:50:11.207865 PICG_EARLY_EN = 1
6215 22:50:11.211703 VALID_LAT_VALUE = 1
6216 22:50:11.214988 ==============================================================
6217 22:50:11.218321 Enter into Gating configuration >>>>
6218 22:50:11.221831 Exit from Gating configuration <<<<
6219 22:50:11.224766 Enter into DVFS_PRE_config >>>>>
6220 22:50:11.235992 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6221 22:50:11.238467 Exit from DVFS_PRE_config <<<<<
6222 22:50:11.241568 Enter into PICG configuration >>>>
6223 22:50:11.244719 Exit from PICG configuration <<<<
6224 22:50:11.248378 [RX_INPUT] configuration >>>>>
6225 22:50:11.251847 [RX_INPUT] configuration <<<<<
6226 22:50:11.258897 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6227 22:50:11.261737 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6228 22:50:11.268173 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6229 22:50:11.274845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6230 22:50:11.282379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6231 22:50:11.288735 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6232 22:50:11.291948 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6233 22:50:11.295026 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6234 22:50:11.298541 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6235 22:50:11.305710 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6236 22:50:11.309595 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6237 22:50:11.312373 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6238 22:50:11.315559 ===================================
6239 22:50:11.319269 LPDDR4 DRAM CONFIGURATION
6240 22:50:11.322437 ===================================
6241 22:50:11.322901 EX_ROW_EN[0] = 0x0
6242 22:50:11.325751 EX_ROW_EN[1] = 0x0
6243 22:50:11.326206 LP4Y_EN = 0x0
6244 22:50:11.329022 WORK_FSP = 0x0
6245 22:50:11.329413 WL = 0x2
6246 22:50:11.331859 RL = 0x2
6247 22:50:11.332254 BL = 0x2
6248 22:50:11.335564 RPST = 0x0
6249 22:50:11.335651 RD_PRE = 0x0
6250 22:50:11.338534 WR_PRE = 0x1
6251 22:50:11.338719 WR_PST = 0x0
6252 22:50:11.341630 DBI_WR = 0x0
6253 22:50:11.345180 DBI_RD = 0x0
6254 22:50:11.345342 OTF = 0x1
6255 22:50:11.349426 ===================================
6256 22:50:11.352109 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6257 22:50:11.355134 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6258 22:50:11.361979 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6259 22:50:11.365180 ===================================
6260 22:50:11.365319 LPDDR4 DRAM CONFIGURATION
6261 22:50:11.368641 ===================================
6262 22:50:11.372682 EX_ROW_EN[0] = 0x10
6263 22:50:11.375139 EX_ROW_EN[1] = 0x0
6264 22:50:11.375231 LP4Y_EN = 0x0
6265 22:50:11.378658 WORK_FSP = 0x0
6266 22:50:11.378757 WL = 0x2
6267 22:50:11.381841 RL = 0x2
6268 22:50:11.381938 BL = 0x2
6269 22:50:11.385609 RPST = 0x0
6270 22:50:11.385712 RD_PRE = 0x0
6271 22:50:11.388740 WR_PRE = 0x1
6272 22:50:11.388826 WR_PST = 0x0
6273 22:50:11.392340 DBI_WR = 0x0
6274 22:50:11.392422 DBI_RD = 0x0
6275 22:50:11.395375 OTF = 0x1
6276 22:50:11.398434 ===================================
6277 22:50:11.405246 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6278 22:50:11.408965 nWR fixed to 30
6279 22:50:11.409051 [ModeRegInit_LP4] CH0 RK0
6280 22:50:11.411976 [ModeRegInit_LP4] CH0 RK1
6281 22:50:11.415097 [ModeRegInit_LP4] CH1 RK0
6282 22:50:11.418645 [ModeRegInit_LP4] CH1 RK1
6283 22:50:11.418727 match AC timing 19
6284 22:50:11.425139 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6285 22:50:11.428558 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6286 22:50:11.432140 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6287 22:50:11.435552 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6288 22:50:11.441771 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6289 22:50:11.441854 ==
6290 22:50:11.445450 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 22:50:11.448628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 22:50:11.448710 ==
6293 22:50:11.455808 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6294 22:50:11.458700 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6295 22:50:11.462029 [CA 0] Center 36 (8~64) winsize 57
6296 22:50:11.465654 [CA 1] Center 36 (8~64) winsize 57
6297 22:50:11.469089 [CA 2] Center 36 (8~64) winsize 57
6298 22:50:11.472305 [CA 3] Center 36 (8~64) winsize 57
6299 22:50:11.475320 [CA 4] Center 36 (8~64) winsize 57
6300 22:50:11.478327 [CA 5] Center 36 (8~64) winsize 57
6301 22:50:11.478409
6302 22:50:11.481911 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6303 22:50:11.481993
6304 22:50:11.485076 [CATrainingPosCal] consider 1 rank data
6305 22:50:11.489358 u2DelayCellTimex100 = 270/100 ps
6306 22:50:11.492185 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 22:50:11.495902 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 22:50:11.499190 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 22:50:11.505180 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 22:50:11.508811 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 22:50:11.512087 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 22:50:11.512169
6313 22:50:11.515929 CA PerBit enable=1, Macro0, CA PI delay=36
6314 22:50:11.516011
6315 22:50:11.519070 [CBTSetCACLKResult] CA Dly = 36
6316 22:50:11.519152 CS Dly: 1 (0~32)
6317 22:50:11.519215 ==
6318 22:50:11.522200 Dram Type= 6, Freq= 0, CH_0, rank 1
6319 22:50:11.528945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 22:50:11.529027 ==
6321 22:50:11.532131 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6322 22:50:11.538710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6323 22:50:11.542106 [CA 0] Center 36 (8~64) winsize 57
6324 22:50:11.546285 [CA 1] Center 36 (8~64) winsize 57
6325 22:50:11.548714 [CA 2] Center 36 (8~64) winsize 57
6326 22:50:11.552123 [CA 3] Center 36 (8~64) winsize 57
6327 22:50:11.555403 [CA 4] Center 36 (8~64) winsize 57
6328 22:50:11.559014 [CA 5] Center 36 (8~64) winsize 57
6329 22:50:11.559124
6330 22:50:11.562342 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6331 22:50:11.562423
6332 22:50:11.565572 [CATrainingPosCal] consider 2 rank data
6333 22:50:11.568774 u2DelayCellTimex100 = 270/100 ps
6334 22:50:11.572591 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 22:50:11.575944 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 22:50:11.579095 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 22:50:11.582197 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 22:50:11.585483 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 22:50:11.589070 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 22:50:11.589149
6341 22:50:11.592032 CA PerBit enable=1, Macro0, CA PI delay=36
6342 22:50:11.595562
6343 22:50:11.595641 [CBTSetCACLKResult] CA Dly = 36
6344 22:50:11.600218 CS Dly: 1 (0~32)
6345 22:50:11.600313
6346 22:50:11.602254 ----->DramcWriteLeveling(PI) begin...
6347 22:50:11.602337 ==
6348 22:50:11.605566 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 22:50:11.609085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 22:50:11.609165 ==
6351 22:50:11.612229 Write leveling (Byte 0): 40 => 8
6352 22:50:11.615663 Write leveling (Byte 1): 32 => 0
6353 22:50:11.619830 DramcWriteLeveling(PI) end<-----
6354 22:50:11.619911
6355 22:50:11.619973 ==
6356 22:50:11.622190 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 22:50:11.625720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 22:50:11.625801 ==
6359 22:50:11.629096 [Gating] SW mode calibration
6360 22:50:11.635678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6361 22:50:11.642276 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6362 22:50:11.645740 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6363 22:50:11.652291 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6364 22:50:11.656095 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6365 22:50:11.658844 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6366 22:50:11.663160 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6367 22:50:11.668949 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6368 22:50:11.672442 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6369 22:50:11.676066 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6370 22:50:11.682474 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6371 22:50:11.686419 Total UI for P1: 0, mck2ui 16
6372 22:50:11.688699 best dqsien dly found for B0: ( 0, 14, 24)
6373 22:50:11.688780 Total UI for P1: 0, mck2ui 16
6374 22:50:11.695611 best dqsien dly found for B1: ( 0, 14, 24)
6375 22:50:11.698958 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6376 22:50:11.702631 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6377 22:50:11.702713
6378 22:50:11.705570 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6379 22:50:11.709121 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6380 22:50:11.712157 [Gating] SW calibration Done
6381 22:50:11.712238 ==
6382 22:50:11.716590 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 22:50:11.719054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 22:50:11.719292 ==
6385 22:50:11.722718 RX Vref Scan: 0
6386 22:50:11.722798
6387 22:50:11.722861 RX Vref 0 -> 0, step: 1
6388 22:50:11.722920
6389 22:50:11.726548 RX Delay -410 -> 252, step: 16
6390 22:50:11.732510 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6391 22:50:11.735770 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6392 22:50:11.738851 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6393 22:50:11.742174 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6394 22:50:11.748824 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6395 22:50:11.752594 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6396 22:50:11.755923 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6397 22:50:11.759483 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6398 22:50:11.766448 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6399 22:50:11.769715 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6400 22:50:11.772748 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6401 22:50:11.776128 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6402 22:50:11.782648 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6403 22:50:11.785889 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6404 22:50:11.789600 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6405 22:50:11.792639 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6406 22:50:11.792992 ==
6407 22:50:11.796027 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 22:50:11.802806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 22:50:11.803161 ==
6410 22:50:11.803439 DQS Delay:
6411 22:50:11.806371 DQS0 = 35, DQS1 = 51
6412 22:50:11.806727 DQM Delay:
6413 22:50:11.807007 DQM0 = 6, DQM1 = 10
6414 22:50:11.809509 DQ Delay:
6415 22:50:11.812783 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6416 22:50:11.813137 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6417 22:50:11.815909 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6418 22:50:11.819754 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6419 22:50:11.820109
6420 22:50:11.820388
6421 22:50:11.823557 ==
6422 22:50:11.826511 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 22:50:11.830369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 22:50:11.830899 ==
6425 22:50:11.831194
6426 22:50:11.831460
6427 22:50:11.833069 TX Vref Scan disable
6428 22:50:11.833490 == TX Byte 0 ==
6429 22:50:11.836789 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6430 22:50:11.843084 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6431 22:50:11.843579 == TX Byte 1 ==
6432 22:50:11.847070 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6433 22:50:11.853152 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6434 22:50:11.853640 ==
6435 22:50:11.856231 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 22:50:11.859360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 22:50:11.859813 ==
6438 22:50:11.860102
6439 22:50:11.860366
6440 22:50:11.863475 TX Vref Scan disable
6441 22:50:11.863952 == TX Byte 0 ==
6442 22:50:11.866321 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6443 22:50:11.873051 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6444 22:50:11.873665 == TX Byte 1 ==
6445 22:50:11.876324 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6446 22:50:11.883165 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6447 22:50:11.883551
6448 22:50:11.883857 [DATLAT]
6449 22:50:11.884140 Freq=400, CH0 RK0
6450 22:50:11.884416
6451 22:50:11.886445 DATLAT Default: 0xf
6452 22:50:11.890410 0, 0xFFFF, sum = 0
6453 22:50:11.890904 1, 0xFFFF, sum = 0
6454 22:50:11.893499 2, 0xFFFF, sum = 0
6455 22:50:11.893994 3, 0xFFFF, sum = 0
6456 22:50:11.897299 4, 0xFFFF, sum = 0
6457 22:50:11.897787 5, 0xFFFF, sum = 0
6458 22:50:11.899640 6, 0xFFFF, sum = 0
6459 22:50:11.900033 7, 0xFFFF, sum = 0
6460 22:50:11.903352 8, 0xFFFF, sum = 0
6461 22:50:11.903746 9, 0xFFFF, sum = 0
6462 22:50:11.906556 10, 0xFFFF, sum = 0
6463 22:50:11.906950 11, 0xFFFF, sum = 0
6464 22:50:11.909809 12, 0xFFFF, sum = 0
6465 22:50:11.910304 13, 0x0, sum = 1
6466 22:50:11.913453 14, 0x0, sum = 2
6467 22:50:11.913947 15, 0x0, sum = 3
6468 22:50:11.916928 16, 0x0, sum = 4
6469 22:50:11.917517 best_step = 14
6470 22:50:11.917860
6471 22:50:11.918168 ==
6472 22:50:11.920131 Dram Type= 6, Freq= 0, CH_0, rank 0
6473 22:50:11.923774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 22:50:11.926448 ==
6475 22:50:11.926872 RX Vref Scan: 1
6476 22:50:11.927202
6477 22:50:11.929933 RX Vref 0 -> 0, step: 1
6478 22:50:11.930355
6479 22:50:11.933098 RX Delay -343 -> 252, step: 8
6480 22:50:11.933547
6481 22:50:11.933877 Set Vref, RX VrefLevel [Byte0]: 53
6482 22:50:11.936404 [Byte1]: 51
6483 22:50:11.942288
6484 22:50:11.942771 Final RX Vref Byte 0 = 53 to rank0
6485 22:50:11.945953 Final RX Vref Byte 1 = 51 to rank0
6486 22:50:11.949157 Final RX Vref Byte 0 = 53 to rank1
6487 22:50:11.952506 Final RX Vref Byte 1 = 51 to rank1==
6488 22:50:11.956253 Dram Type= 6, Freq= 0, CH_0, rank 0
6489 22:50:11.962426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 22:50:11.962945 ==
6491 22:50:11.963278 DQS Delay:
6492 22:50:11.963610 DQS0 = 44, DQS1 = 60
6493 22:50:11.967378 DQM Delay:
6494 22:50:11.967796 DQM0 = 11, DQM1 = 15
6495 22:50:11.968589 DQ Delay:
6496 22:50:11.973000 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6497 22:50:11.973589 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6498 22:50:11.976406 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6499 22:50:11.979243 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6500 22:50:11.979631
6501 22:50:11.979936
6502 22:50:11.989126 [DQSOSCAuto] RK0, (LSB)MR18= 0x8654, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6503 22:50:11.992502 CH0 RK0: MR19=C0C, MR18=8654
6504 22:50:11.999293 CH0_RK0: MR19=0xC0C, MR18=0x8654, DQSOSC=393, MR23=63, INC=382, DEC=254
6505 22:50:11.999812 ==
6506 22:50:12.002439 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 22:50:12.006251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 22:50:12.006672 ==
6509 22:50:12.008909 [Gating] SW mode calibration
6510 22:50:12.015749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6511 22:50:12.019544 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6512 22:50:12.026059 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6513 22:50:12.029098 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6514 22:50:12.032533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6515 22:50:12.039252 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6516 22:50:12.042609 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6517 22:50:12.045992 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6518 22:50:12.052784 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6519 22:50:12.055874 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 22:50:12.059715 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6521 22:50:12.062293 Total UI for P1: 0, mck2ui 16
6522 22:50:12.065706 best dqsien dly found for B0: ( 0, 14, 24)
6523 22:50:12.068921 Total UI for P1: 0, mck2ui 16
6524 22:50:12.072962 best dqsien dly found for B1: ( 0, 14, 24)
6525 22:50:12.076124 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6526 22:50:12.079019 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6527 22:50:12.079400
6528 22:50:12.082915 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6529 22:50:12.089386 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6530 22:50:12.089984 [Gating] SW calibration Done
6531 22:50:12.090302 ==
6532 22:50:12.092510 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 22:50:12.099457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 22:50:12.100041 ==
6535 22:50:12.100383 RX Vref Scan: 0
6536 22:50:12.100689
6537 22:50:12.102722 RX Vref 0 -> 0, step: 1
6538 22:50:12.103238
6539 22:50:12.105747 RX Delay -410 -> 252, step: 16
6540 22:50:12.109446 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6541 22:50:12.112699 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6542 22:50:12.119464 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6543 22:50:12.123432 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6544 22:50:12.126130 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6545 22:50:12.129870 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6546 22:50:12.136057 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6547 22:50:12.139463 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6548 22:50:12.142672 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6549 22:50:12.145976 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6550 22:50:12.149535 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6551 22:50:12.156382 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6552 22:50:12.159517 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6553 22:50:12.163008 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6554 22:50:12.169435 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6555 22:50:12.173336 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6556 22:50:12.173928 ==
6557 22:50:12.176353 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 22:50:12.179523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 22:50:12.179921 ==
6560 22:50:12.183209 DQS Delay:
6561 22:50:12.183699 DQS0 = 43, DQS1 = 51
6562 22:50:12.184007 DQM Delay:
6563 22:50:12.186171 DQM0 = 11, DQM1 = 10
6564 22:50:12.186557 DQ Delay:
6565 22:50:12.189748 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6566 22:50:12.192796 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6567 22:50:12.196285 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6568 22:50:12.200132 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6569 22:50:12.200623
6570 22:50:12.200927
6571 22:50:12.201235 ==
6572 22:50:12.203008 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 22:50:12.206134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 22:50:12.206526 ==
6575 22:50:12.206831
6576 22:50:12.209315
6577 22:50:12.209832 TX Vref Scan disable
6578 22:50:12.213268 == TX Byte 0 ==
6579 22:50:12.216299 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6580 22:50:12.219810 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6581 22:50:12.223079 == TX Byte 1 ==
6582 22:50:12.226191 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6583 22:50:12.229703 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6584 22:50:12.230125 ==
6585 22:50:12.233128 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 22:50:12.236025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 22:50:12.236445 ==
6588 22:50:12.236773
6589 22:50:12.240097
6590 22:50:12.240615 TX Vref Scan disable
6591 22:50:12.242832 == TX Byte 0 ==
6592 22:50:12.246052 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6593 22:50:12.249559 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6594 22:50:12.252799 == TX Byte 1 ==
6595 22:50:12.256568 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6596 22:50:12.260161 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6597 22:50:12.260647
6598 22:50:12.260952 [DATLAT]
6599 22:50:12.263440 Freq=400, CH0 RK1
6600 22:50:12.263984
6601 22:50:12.264454 DATLAT Default: 0xe
6602 22:50:12.266123 0, 0xFFFF, sum = 0
6603 22:50:12.266511 1, 0xFFFF, sum = 0
6604 22:50:12.269510 2, 0xFFFF, sum = 0
6605 22:50:12.269894 3, 0xFFFF, sum = 0
6606 22:50:12.273107 4, 0xFFFF, sum = 0
6607 22:50:12.276403 5, 0xFFFF, sum = 0
6608 22:50:12.276789 6, 0xFFFF, sum = 0
6609 22:50:12.279389 7, 0xFFFF, sum = 0
6610 22:50:12.279775 8, 0xFFFF, sum = 0
6611 22:50:12.282805 9, 0xFFFF, sum = 0
6612 22:50:12.283299 10, 0xFFFF, sum = 0
6613 22:50:12.286528 11, 0xFFFF, sum = 0
6614 22:50:12.287068 12, 0xFFFF, sum = 0
6615 22:50:12.290066 13, 0x0, sum = 1
6616 22:50:12.290603 14, 0x0, sum = 2
6617 22:50:12.292771 15, 0x0, sum = 3
6618 22:50:12.293250 16, 0x0, sum = 4
6619 22:50:12.293601 best_step = 14
6620 22:50:12.296636
6621 22:50:12.297147 ==
6622 22:50:12.299975 Dram Type= 6, Freq= 0, CH_0, rank 1
6623 22:50:12.303134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 22:50:12.303658 ==
6625 22:50:12.303994 RX Vref Scan: 0
6626 22:50:12.304299
6627 22:50:12.306467 RX Vref 0 -> 0, step: 1
6628 22:50:12.306888
6629 22:50:12.309633 RX Delay -343 -> 252, step: 8
6630 22:50:12.316666 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6631 22:50:12.319895 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6632 22:50:12.323235 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6633 22:50:12.326979 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6634 22:50:12.333154 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6635 22:50:12.336833 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6636 22:50:12.339752 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6637 22:50:12.342981 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6638 22:50:12.350144 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6639 22:50:12.353423 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6640 22:50:12.356523 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6641 22:50:12.363313 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6642 22:50:12.366125 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6643 22:50:12.369439 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6644 22:50:12.372923 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6645 22:50:12.379750 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6646 22:50:12.380174 ==
6647 22:50:12.383186 Dram Type= 6, Freq= 0, CH_0, rank 1
6648 22:50:12.386137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 22:50:12.386663 ==
6650 22:50:12.386998 DQS Delay:
6651 22:50:12.390182 DQS0 = 48, DQS1 = 60
6652 22:50:12.390698 DQM Delay:
6653 22:50:12.393232 DQM0 = 13, DQM1 = 13
6654 22:50:12.393655 DQ Delay:
6655 22:50:12.396313 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6656 22:50:12.399378 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6657 22:50:12.402954 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6658 22:50:12.406136 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6659 22:50:12.406657
6660 22:50:12.406992
6661 22:50:12.412932 [DQSOSCAuto] RK1, (LSB)MR18= 0x9164, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6662 22:50:12.416446 CH0 RK1: MR19=C0C, MR18=9164
6663 22:50:12.423004 CH0_RK1: MR19=0xC0C, MR18=0x9164, DQSOSC=391, MR23=63, INC=386, DEC=257
6664 22:50:12.426239 [RxdqsGatingPostProcess] freq 400
6665 22:50:12.433558 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6666 22:50:12.436187 best DQS0 dly(2T, 0.5T) = (0, 10)
6667 22:50:12.436699 best DQS1 dly(2T, 0.5T) = (0, 10)
6668 22:50:12.439216 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6669 22:50:12.442615 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6670 22:50:12.446689 best DQS0 dly(2T, 0.5T) = (0, 10)
6671 22:50:12.449910 best DQS1 dly(2T, 0.5T) = (0, 10)
6672 22:50:12.452913 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6673 22:50:12.456485 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6674 22:50:12.459921 Pre-setting of DQS Precalculation
6675 22:50:12.466415 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6676 22:50:12.466943 ==
6677 22:50:12.469870 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 22:50:12.473515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 22:50:12.474032 ==
6680 22:50:12.479593 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6681 22:50:12.482878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6682 22:50:12.486149 [CA 0] Center 36 (8~64) winsize 57
6683 22:50:12.489651 [CA 1] Center 36 (8~64) winsize 57
6684 22:50:12.492901 [CA 2] Center 36 (8~64) winsize 57
6685 22:50:12.496183 [CA 3] Center 36 (8~64) winsize 57
6686 22:50:12.499674 [CA 4] Center 36 (8~64) winsize 57
6687 22:50:12.503148 [CA 5] Center 36 (8~64) winsize 57
6688 22:50:12.503665
6689 22:50:12.506360 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6690 22:50:12.506776
6691 22:50:12.509896 [CATrainingPosCal] consider 1 rank data
6692 22:50:12.513396 u2DelayCellTimex100 = 270/100 ps
6693 22:50:12.516637 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 22:50:12.520292 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 22:50:12.523676 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 22:50:12.527396 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 22:50:12.529909 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 22:50:12.536476 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 22:50:12.537014
6700 22:50:12.539791 CA PerBit enable=1, Macro0, CA PI delay=36
6701 22:50:12.540306
6702 22:50:12.543008 [CBTSetCACLKResult] CA Dly = 36
6703 22:50:12.543429 CS Dly: 1 (0~32)
6704 22:50:12.543757 ==
6705 22:50:12.546205 Dram Type= 6, Freq= 0, CH_1, rank 1
6706 22:50:12.549884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 22:50:12.553345 ==
6708 22:50:12.556393 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6709 22:50:12.563321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6710 22:50:12.566063 [CA 0] Center 36 (8~64) winsize 57
6711 22:50:12.569611 [CA 1] Center 36 (8~64) winsize 57
6712 22:50:12.572742 [CA 2] Center 36 (8~64) winsize 57
6713 22:50:12.576232 [CA 3] Center 36 (8~64) winsize 57
6714 22:50:12.579566 [CA 4] Center 36 (8~64) winsize 57
6715 22:50:12.583202 [CA 5] Center 36 (8~64) winsize 57
6716 22:50:12.583719
6717 22:50:12.586107 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6718 22:50:12.586524
6719 22:50:12.589556 [CATrainingPosCal] consider 2 rank data
6720 22:50:12.593328 u2DelayCellTimex100 = 270/100 ps
6721 22:50:12.596132 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 22:50:12.599602 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 22:50:12.603172 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 22:50:12.606679 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 22:50:12.609830 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 22:50:12.612995 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 22:50:12.613594
6728 22:50:12.616247 CA PerBit enable=1, Macro0, CA PI delay=36
6729 22:50:12.616662
6730 22:50:12.619771 [CBTSetCACLKResult] CA Dly = 36
6731 22:50:12.623471 CS Dly: 1 (0~32)
6732 22:50:12.624007
6733 22:50:12.626282 ----->DramcWriteLeveling(PI) begin...
6734 22:50:12.626810 ==
6735 22:50:12.630167 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 22:50:12.632845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 22:50:12.633299 ==
6738 22:50:12.636646 Write leveling (Byte 0): 40 => 8
6739 22:50:12.640096 Write leveling (Byte 1): 40 => 8
6740 22:50:12.643152 DramcWriteLeveling(PI) end<-----
6741 22:50:12.643570
6742 22:50:12.643899 ==
6743 22:50:12.646405 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 22:50:12.649488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 22:50:12.650011 ==
6746 22:50:12.653279 [Gating] SW mode calibration
6747 22:50:12.660188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6748 22:50:12.666195 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6749 22:50:12.670158 0 11 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
6750 22:50:12.673340 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6751 22:50:12.679759 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6752 22:50:12.683172 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6753 22:50:12.686463 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6754 22:50:12.692994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6755 22:50:12.696537 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6756 22:50:12.699334 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6757 22:50:12.705914 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6758 22:50:12.706336 Total UI for P1: 0, mck2ui 16
6759 22:50:12.712901 best dqsien dly found for B0: ( 0, 14, 24)
6760 22:50:12.713474 Total UI for P1: 0, mck2ui 16
6761 22:50:12.719515 best dqsien dly found for B1: ( 0, 14, 24)
6762 22:50:12.722747 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6763 22:50:12.726273 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6764 22:50:12.726690
6765 22:50:12.729670 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6766 22:50:12.733100 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6767 22:50:12.736656 [Gating] SW calibration Done
6768 22:50:12.737077 ==
6769 22:50:12.739870 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 22:50:12.742929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 22:50:12.743451 ==
6772 22:50:12.746786 RX Vref Scan: 0
6773 22:50:12.747301
6774 22:50:12.747639 RX Vref 0 -> 0, step: 1
6775 22:50:12.747951
6776 22:50:12.749950 RX Delay -410 -> 252, step: 16
6777 22:50:12.756362 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6778 22:50:12.760195 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6779 22:50:12.763662 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6780 22:50:12.766440 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6781 22:50:12.769982 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6782 22:50:12.776199 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6783 22:50:12.779354 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6784 22:50:12.783151 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6785 22:50:12.786082 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6786 22:50:12.793255 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6787 22:50:12.796917 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6788 22:50:12.799554 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6789 22:50:12.806138 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6790 22:50:12.809744 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6791 22:50:12.813194 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6792 22:50:12.816178 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6793 22:50:12.816597 ==
6794 22:50:12.819567 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 22:50:12.826518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 22:50:12.827043 ==
6797 22:50:12.827376 DQS Delay:
6798 22:50:12.830090 DQS0 = 51, DQS1 = 59
6799 22:50:12.830507 DQM Delay:
6800 22:50:12.830839 DQM0 = 18, DQM1 = 16
6801 22:50:12.832786 DQ Delay:
6802 22:50:12.836056 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6803 22:50:12.839657 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6804 22:50:12.843075 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6805 22:50:12.845988 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6806 22:50:12.846556
6807 22:50:12.847013
6808 22:50:12.847341 ==
6809 22:50:12.849266 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 22:50:12.853001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 22:50:12.853468 ==
6812 22:50:12.853843
6813 22:50:12.854407
6814 22:50:12.856086 TX Vref Scan disable
6815 22:50:12.856634 == TX Byte 0 ==
6816 22:50:12.859561 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6817 22:50:12.866137 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6818 22:50:12.866557 == TX Byte 1 ==
6819 22:50:12.869949 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 22:50:12.876171 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 22:50:12.876668 ==
6822 22:50:12.879289 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 22:50:12.883207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 22:50:12.883707 ==
6825 22:50:12.884021
6826 22:50:12.884304
6827 22:50:12.885811 TX Vref Scan disable
6828 22:50:12.886195 == TX Byte 0 ==
6829 22:50:12.892838 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6830 22:50:12.896647 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6831 22:50:12.897193 == TX Byte 1 ==
6832 22:50:12.900119 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6833 22:50:12.906246 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6834 22:50:12.906635
6835 22:50:12.906937 [DATLAT]
6836 22:50:12.909469 Freq=400, CH1 RK0
6837 22:50:12.909990
6838 22:50:12.910326 DATLAT Default: 0xf
6839 22:50:12.912806 0, 0xFFFF, sum = 0
6840 22:50:12.913199 1, 0xFFFF, sum = 0
6841 22:50:12.915990 2, 0xFFFF, sum = 0
6842 22:50:12.916442 3, 0xFFFF, sum = 0
6843 22:50:12.919273 4, 0xFFFF, sum = 0
6844 22:50:12.919661 5, 0xFFFF, sum = 0
6845 22:50:12.922821 6, 0xFFFF, sum = 0
6846 22:50:12.923314 7, 0xFFFF, sum = 0
6847 22:50:12.925649 8, 0xFFFF, sum = 0
6848 22:50:12.926041 9, 0xFFFF, sum = 0
6849 22:50:12.929372 10, 0xFFFF, sum = 0
6850 22:50:12.929869 11, 0xFFFF, sum = 0
6851 22:50:12.932636 12, 0xFFFF, sum = 0
6852 22:50:12.933157 13, 0x0, sum = 1
6853 22:50:12.935782 14, 0x0, sum = 2
6854 22:50:12.936361 15, 0x0, sum = 3
6855 22:50:12.939297 16, 0x0, sum = 4
6856 22:50:12.939682 best_step = 14
6857 22:50:12.939981
6858 22:50:12.940258 ==
6859 22:50:12.942669 Dram Type= 6, Freq= 0, CH_1, rank 0
6860 22:50:12.949627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 22:50:12.950129 ==
6862 22:50:12.950437 RX Vref Scan: 1
6863 22:50:12.950721
6864 22:50:12.953009 RX Vref 0 -> 0, step: 1
6865 22:50:12.953701
6866 22:50:12.956360 RX Delay -359 -> 252, step: 8
6867 22:50:12.956771
6868 22:50:12.959126 Set Vref, RX VrefLevel [Byte0]: 54
6869 22:50:12.962685 [Byte1]: 54
6870 22:50:12.963207
6871 22:50:12.966014 Final RX Vref Byte 0 = 54 to rank0
6872 22:50:12.969110 Final RX Vref Byte 1 = 54 to rank0
6873 22:50:12.972479 Final RX Vref Byte 0 = 54 to rank1
6874 22:50:12.975649 Final RX Vref Byte 1 = 54 to rank1==
6875 22:50:12.979069 Dram Type= 6, Freq= 0, CH_1, rank 0
6876 22:50:12.982391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 22:50:12.986154 ==
6878 22:50:12.986567 DQS Delay:
6879 22:50:12.986893 DQS0 = 48, DQS1 = 60
6880 22:50:12.989665 DQM Delay:
6881 22:50:12.990077 DQM0 = 12, DQM1 = 13
6882 22:50:12.993287 DQ Delay:
6883 22:50:12.993807 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6884 22:50:12.995843 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6885 22:50:12.999429 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =12
6886 22:50:13.002981 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6887 22:50:13.003460
6888 22:50:13.003796
6889 22:50:13.012806 [DQSOSCAuto] RK0, (LSB)MR18= 0x872e, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
6890 22:50:13.015872 CH1 RK0: MR19=C0C, MR18=872E
6891 22:50:13.022765 CH1_RK0: MR19=0xC0C, MR18=0x872E, DQSOSC=392, MR23=63, INC=384, DEC=256
6892 22:50:13.023292 ==
6893 22:50:13.026581 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 22:50:13.029590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 22:50:13.030124 ==
6896 22:50:13.032733 [Gating] SW mode calibration
6897 22:50:13.039040 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6898 22:50:13.043175 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6899 22:50:13.049739 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6900 22:50:13.053114 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6901 22:50:13.056087 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6902 22:50:13.062760 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6903 22:50:13.066138 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6904 22:50:13.069258 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6905 22:50:13.076189 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6906 22:50:13.078941 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6907 22:50:13.083176 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6908 22:50:13.085639 Total UI for P1: 0, mck2ui 16
6909 22:50:13.089364 best dqsien dly found for B0: ( 0, 14, 24)
6910 22:50:13.092670 Total UI for P1: 0, mck2ui 16
6911 22:50:13.095762 best dqsien dly found for B1: ( 0, 14, 24)
6912 22:50:13.099389 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6913 22:50:13.102737 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6914 22:50:13.103167
6915 22:50:13.109444 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6916 22:50:13.112545 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6917 22:50:13.113076 [Gating] SW calibration Done
6918 22:50:13.115778 ==
6919 22:50:13.116200 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 22:50:13.122994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 22:50:13.123531 ==
6922 22:50:13.123872 RX Vref Scan: 0
6923 22:50:13.124184
6924 22:50:13.126027 RX Vref 0 -> 0, step: 1
6925 22:50:13.126449
6926 22:50:13.129497 RX Delay -410 -> 252, step: 16
6927 22:50:13.132406 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6928 22:50:13.135783 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6929 22:50:13.142675 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6930 22:50:13.146078 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6931 22:50:13.149564 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6932 22:50:13.152289 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6933 22:50:13.159771 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6934 22:50:13.162690 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6935 22:50:13.165691 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6936 22:50:13.169760 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6937 22:50:13.176374 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6938 22:50:13.179650 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6939 22:50:13.182328 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6940 22:50:13.186158 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6941 22:50:13.193446 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6942 22:50:13.196282 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6943 22:50:13.196810 ==
6944 22:50:13.199546 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 22:50:13.203098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 22:50:13.203634 ==
6947 22:50:13.206149 DQS Delay:
6948 22:50:13.206681 DQS0 = 51, DQS1 = 59
6949 22:50:13.209681 DQM Delay:
6950 22:50:13.210240 DQM0 = 17, DQM1 = 20
6951 22:50:13.210583 DQ Delay:
6952 22:50:13.212800 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6953 22:50:13.215784 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6954 22:50:13.219082 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6955 22:50:13.222629 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6956 22:50:13.223167
6957 22:50:13.223504
6958 22:50:13.223817 ==
6959 22:50:13.225923 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 22:50:13.233296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 22:50:13.233840 ==
6962 22:50:13.234174
6963 22:50:13.234483
6964 22:50:13.234778 TX Vref Scan disable
6965 22:50:13.235721 == TX Byte 0 ==
6966 22:50:13.239575 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6967 22:50:13.242694 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6968 22:50:13.245623 == TX Byte 1 ==
6969 22:50:13.249119 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6970 22:50:13.252649 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6971 22:50:13.253067 ==
6972 22:50:13.256180 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 22:50:13.263034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 22:50:13.263553 ==
6975 22:50:13.263887
6976 22:50:13.264195
6977 22:50:13.264487 TX Vref Scan disable
6978 22:50:13.265719 == TX Byte 0 ==
6979 22:50:13.269453 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6980 22:50:13.272842 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6981 22:50:13.276639 == TX Byte 1 ==
6982 22:50:13.279545 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6983 22:50:13.282690 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6984 22:50:13.283113
6985 22:50:13.286415 [DATLAT]
6986 22:50:13.286931 Freq=400, CH1 RK1
6987 22:50:13.287268
6988 22:50:13.289542 DATLAT Default: 0xe
6989 22:50:13.289960 0, 0xFFFF, sum = 0
6990 22:50:13.292801 1, 0xFFFF, sum = 0
6991 22:50:13.293357 2, 0xFFFF, sum = 0
6992 22:50:13.295874 3, 0xFFFF, sum = 0
6993 22:50:13.296300 4, 0xFFFF, sum = 0
6994 22:50:13.299467 5, 0xFFFF, sum = 0
6995 22:50:13.299989 6, 0xFFFF, sum = 0
6996 22:50:13.302768 7, 0xFFFF, sum = 0
6997 22:50:13.303294 8, 0xFFFF, sum = 0
6998 22:50:13.306475 9, 0xFFFF, sum = 0
6999 22:50:13.307002 10, 0xFFFF, sum = 0
7000 22:50:13.309810 11, 0xFFFF, sum = 0
7001 22:50:13.310332 12, 0xFFFF, sum = 0
7002 22:50:13.313184 13, 0x0, sum = 1
7003 22:50:13.313743 14, 0x0, sum = 2
7004 22:50:13.316166 15, 0x0, sum = 3
7005 22:50:13.316589 16, 0x0, sum = 4
7006 22:50:13.319779 best_step = 14
7007 22:50:13.320295
7008 22:50:13.320627 ==
7009 22:50:13.322876 Dram Type= 6, Freq= 0, CH_1, rank 1
7010 22:50:13.326075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7011 22:50:13.326603 ==
7012 22:50:13.329305 RX Vref Scan: 0
7013 22:50:13.329723
7014 22:50:13.330056 RX Vref 0 -> 0, step: 1
7015 22:50:13.330365
7016 22:50:13.333064 RX Delay -359 -> 252, step: 8
7017 22:50:13.340461 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7018 22:50:13.344061 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7019 22:50:13.347544 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7020 22:50:13.350784 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
7021 22:50:13.357713 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
7022 22:50:13.360551 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7023 22:50:13.364311 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7024 22:50:13.367725 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7025 22:50:13.373804 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7026 22:50:13.377476 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7027 22:50:13.380842 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7028 22:50:13.384104 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
7029 22:50:13.390446 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
7030 22:50:13.394534 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7031 22:50:13.398147 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7032 22:50:13.401085 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7033 22:50:13.404077 ==
7034 22:50:13.407654 Dram Type= 6, Freq= 0, CH_1, rank 1
7035 22:50:13.410735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7036 22:50:13.411158 ==
7037 22:50:13.411489 DQS Delay:
7038 22:50:13.414607 DQS0 = 52, DQS1 = 56
7039 22:50:13.415133 DQM Delay:
7040 22:50:13.417350 DQM0 = 12, DQM1 = 9
7041 22:50:13.417772 DQ Delay:
7042 22:50:13.421185 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7043 22:50:13.424454 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7044 22:50:13.427703 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
7045 22:50:13.430723 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7046 22:50:13.431238
7047 22:50:13.431566
7048 22:50:13.437668 [DQSOSCAuto] RK1, (LSB)MR18= 0x7289, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
7049 22:50:13.440644 CH1 RK1: MR19=C0C, MR18=7289
7050 22:50:13.447581 CH1_RK1: MR19=0xC0C, MR18=0x7289, DQSOSC=392, MR23=63, INC=384, DEC=256
7051 22:50:13.451071 [RxdqsGatingPostProcess] freq 400
7052 22:50:13.453868 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7053 22:50:13.457319 best DQS0 dly(2T, 0.5T) = (0, 10)
7054 22:50:13.460576 best DQS1 dly(2T, 0.5T) = (0, 10)
7055 22:50:13.464155 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7056 22:50:13.467780 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7057 22:50:13.470620 best DQS0 dly(2T, 0.5T) = (0, 10)
7058 22:50:13.474107 best DQS1 dly(2T, 0.5T) = (0, 10)
7059 22:50:13.477225 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7060 22:50:13.480439 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7061 22:50:13.483882 Pre-setting of DQS Precalculation
7062 22:50:13.488044 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7063 22:50:13.494340 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7064 22:50:13.504069 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7065 22:50:13.504591
7066 22:50:13.504925
7067 22:50:13.507502 [Calibration Summary] 800 Mbps
7068 22:50:13.508055 CH 0, Rank 0
7069 22:50:13.511173 SW Impedance : PASS
7070 22:50:13.511698 DUTY Scan : NO K
7071 22:50:13.514300 ZQ Calibration : PASS
7072 22:50:13.514716 Jitter Meter : NO K
7073 22:50:13.517507 CBT Training : PASS
7074 22:50:13.521301 Write leveling : PASS
7075 22:50:13.521823 RX DQS gating : PASS
7076 22:50:13.524648 RX DQ/DQS(RDDQC) : PASS
7077 22:50:13.528444 TX DQ/DQS : PASS
7078 22:50:13.528964 RX DATLAT : PASS
7079 22:50:13.531028 RX DQ/DQS(Engine): PASS
7080 22:50:13.534442 TX OE : NO K
7081 22:50:13.534963 All Pass.
7082 22:50:13.535293
7083 22:50:13.535598 CH 0, Rank 1
7084 22:50:13.537578 SW Impedance : PASS
7085 22:50:13.540769 DUTY Scan : NO K
7086 22:50:13.541188 ZQ Calibration : PASS
7087 22:50:13.544783 Jitter Meter : NO K
7088 22:50:13.547506 CBT Training : PASS
7089 22:50:13.547923 Write leveling : NO K
7090 22:50:13.551467 RX DQS gating : PASS
7091 22:50:13.551987 RX DQ/DQS(RDDQC) : PASS
7092 22:50:13.554028 TX DQ/DQS : PASS
7093 22:50:13.557889 RX DATLAT : PASS
7094 22:50:13.558400 RX DQ/DQS(Engine): PASS
7095 22:50:13.560644 TX OE : NO K
7096 22:50:13.561062 All Pass.
7097 22:50:13.561426
7098 22:50:13.564489 CH 1, Rank 0
7099 22:50:13.564907 SW Impedance : PASS
7100 22:50:13.567472 DUTY Scan : NO K
7101 22:50:13.571195 ZQ Calibration : PASS
7102 22:50:13.571717 Jitter Meter : NO K
7103 22:50:13.574554 CBT Training : PASS
7104 22:50:13.577640 Write leveling : PASS
7105 22:50:13.578162 RX DQS gating : PASS
7106 22:50:13.580883 RX DQ/DQS(RDDQC) : PASS
7107 22:50:13.584426 TX DQ/DQS : PASS
7108 22:50:13.584948 RX DATLAT : PASS
7109 22:50:13.587611 RX DQ/DQS(Engine): PASS
7110 22:50:13.590978 TX OE : NO K
7111 22:50:13.591500 All Pass.
7112 22:50:13.591835
7113 22:50:13.592139 CH 1, Rank 1
7114 22:50:13.594053 SW Impedance : PASS
7115 22:50:13.594472 DUTY Scan : NO K
7116 22:50:13.597634 ZQ Calibration : PASS
7117 22:50:13.600710 Jitter Meter : NO K
7118 22:50:13.601129 CBT Training : PASS
7119 22:50:13.603987 Write leveling : NO K
7120 22:50:13.607925 RX DQS gating : PASS
7121 22:50:13.608453 RX DQ/DQS(RDDQC) : PASS
7122 22:50:13.611766 TX DQ/DQS : PASS
7123 22:50:13.614928 RX DATLAT : PASS
7124 22:50:13.615460 RX DQ/DQS(Engine): PASS
7125 22:50:13.617694 TX OE : NO K
7126 22:50:13.618120 All Pass.
7127 22:50:13.618452
7128 22:50:13.621422 DramC Write-DBI off
7129 22:50:13.624837 PER_BANK_REFRESH: Hybrid Mode
7130 22:50:13.625411 TX_TRACKING: ON
7131 22:50:13.634727 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7132 22:50:13.637898 [FAST_K] Save calibration result to emmc
7133 22:50:13.641146 dramc_set_vcore_voltage set vcore to 725000
7134 22:50:13.645038 Read voltage for 1600, 0
7135 22:50:13.645641 Vio18 = 0
7136 22:50:13.645985 Vcore = 725000
7137 22:50:13.647946 Vdram = 0
7138 22:50:13.648472 Vddq = 0
7139 22:50:13.648809 Vmddr = 0
7140 22:50:13.654656 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7141 22:50:13.657851 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7142 22:50:13.661725 MEM_TYPE=3, freq_sel=13
7143 22:50:13.664646 sv_algorithm_assistance_LP4_3733
7144 22:50:13.668093 ============ PULL DRAM RESETB DOWN ============
7145 22:50:13.671205 ========== PULL DRAM RESETB DOWN end =========
7146 22:50:13.678074 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7147 22:50:13.681383 ===================================
7148 22:50:13.681918 LPDDR4 DRAM CONFIGURATION
7149 22:50:13.685460 ===================================
7150 22:50:13.687814 EX_ROW_EN[0] = 0x0
7151 22:50:13.691119 EX_ROW_EN[1] = 0x0
7152 22:50:13.691543 LP4Y_EN = 0x0
7153 22:50:13.694137 WORK_FSP = 0x1
7154 22:50:13.694570 WL = 0x5
7155 22:50:13.698040 RL = 0x5
7156 22:50:13.698590 BL = 0x2
7157 22:50:13.701254 RPST = 0x0
7158 22:50:13.701678 RD_PRE = 0x0
7159 22:50:13.704249 WR_PRE = 0x1
7160 22:50:13.704667 WR_PST = 0x1
7161 22:50:13.709295 DBI_WR = 0x0
7162 22:50:13.709827 DBI_RD = 0x0
7163 22:50:13.711023 OTF = 0x1
7164 22:50:13.714515 ===================================
7165 22:50:13.717332 ===================================
7166 22:50:13.717854 ANA top config
7167 22:50:13.720728 ===================================
7168 22:50:13.724629 DLL_ASYNC_EN = 0
7169 22:50:13.727809 ALL_SLAVE_EN = 0
7170 22:50:13.728375 NEW_RANK_MODE = 1
7171 22:50:13.731258 DLL_IDLE_MODE = 1
7172 22:50:13.733990 LP45_APHY_COMB_EN = 1
7173 22:50:13.738519 TX_ODT_DIS = 0
7174 22:50:13.740919 NEW_8X_MODE = 1
7175 22:50:13.744237 ===================================
7176 22:50:13.744660 ===================================
7177 22:50:13.747841 data_rate = 3200
7178 22:50:13.751127 CKR = 1
7179 22:50:13.754513 DQ_P2S_RATIO = 8
7180 22:50:13.757650 ===================================
7181 22:50:13.761509 CA_P2S_RATIO = 8
7182 22:50:13.764953 DQ_CA_OPEN = 0
7183 22:50:13.768157 DQ_SEMI_OPEN = 0
7184 22:50:13.768676 CA_SEMI_OPEN = 0
7185 22:50:13.771073 CA_FULL_RATE = 0
7186 22:50:13.775024 DQ_CKDIV4_EN = 0
7187 22:50:13.778087 CA_CKDIV4_EN = 0
7188 22:50:13.780995 CA_PREDIV_EN = 0
7189 22:50:13.781466 PH8_DLY = 12
7190 22:50:13.784895 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7191 22:50:13.788068 DQ_AAMCK_DIV = 4
7192 22:50:13.791719 CA_AAMCK_DIV = 4
7193 22:50:13.794585 CA_ADMCK_DIV = 4
7194 22:50:13.798106 DQ_TRACK_CA_EN = 0
7195 22:50:13.801442 CA_PICK = 1600
7196 22:50:13.801993 CA_MCKIO = 1600
7197 22:50:13.804899 MCKIO_SEMI = 0
7198 22:50:13.807990 PLL_FREQ = 3068
7199 22:50:13.812212 DQ_UI_PI_RATIO = 32
7200 22:50:13.814753 CA_UI_PI_RATIO = 0
7201 22:50:13.818463 ===================================
7202 22:50:13.821586 ===================================
7203 22:50:13.822103 memory_type:LPDDR4
7204 22:50:13.824704 GP_NUM : 10
7205 22:50:13.828077 SRAM_EN : 1
7206 22:50:13.828497 MD32_EN : 0
7207 22:50:13.831799 ===================================
7208 22:50:13.835023 [ANA_INIT] >>>>>>>>>>>>>>
7209 22:50:13.837972 <<<<<< [CONFIGURE PHASE]: ANA_TX
7210 22:50:13.841684 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7211 22:50:13.844739 ===================================
7212 22:50:13.848207 data_rate = 3200,PCW = 0X7600
7213 22:50:13.852250 ===================================
7214 22:50:13.854622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7215 22:50:13.858838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7216 22:50:13.865291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7217 22:50:13.868070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7218 22:50:13.871427 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7219 22:50:13.874714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7220 22:50:13.878105 [ANA_INIT] flow start
7221 22:50:13.881592 [ANA_INIT] PLL >>>>>>>>
7222 22:50:13.882009 [ANA_INIT] PLL <<<<<<<<
7223 22:50:13.884528 [ANA_INIT] MIDPI >>>>>>>>
7224 22:50:13.888240 [ANA_INIT] MIDPI <<<<<<<<
7225 22:50:13.891435 [ANA_INIT] DLL >>>>>>>>
7226 22:50:13.892002 [ANA_INIT] DLL <<<<<<<<
7227 22:50:13.894855 [ANA_INIT] flow end
7228 22:50:13.898123 ============ LP4 DIFF to SE enter ============
7229 22:50:13.901757 ============ LP4 DIFF to SE exit ============
7230 22:50:13.905353 [ANA_INIT] <<<<<<<<<<<<<
7231 22:50:13.907839 [Flow] Enable top DCM control >>>>>
7232 22:50:13.911836 [Flow] Enable top DCM control <<<<<
7233 22:50:13.915223 Enable DLL master slave shuffle
7234 22:50:13.917952 ==============================================================
7235 22:50:13.921559 Gating Mode config
7236 22:50:13.928443 ==============================================================
7237 22:50:13.928963 Config description:
7238 22:50:13.938408 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7239 22:50:13.945046 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7240 22:50:13.951583 SELPH_MODE 0: By rank 1: By Phase
7241 22:50:13.954876 ==============================================================
7242 22:50:13.958473 GAT_TRACK_EN = 1
7243 22:50:13.961314 RX_GATING_MODE = 2
7244 22:50:13.964840 RX_GATING_TRACK_MODE = 2
7245 22:50:13.968127 SELPH_MODE = 1
7246 22:50:13.971503 PICG_EARLY_EN = 1
7247 22:50:13.974444 VALID_LAT_VALUE = 1
7248 22:50:13.978512 ==============================================================
7249 22:50:13.981306 Enter into Gating configuration >>>>
7250 22:50:13.984828 Exit from Gating configuration <<<<
7251 22:50:13.988238 Enter into DVFS_PRE_config >>>>>
7252 22:50:14.001487 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7253 22:50:14.002103 Exit from DVFS_PRE_config <<<<<
7254 22:50:14.004513 Enter into PICG configuration >>>>
7255 22:50:14.008682 Exit from PICG configuration <<<<
7256 22:50:14.010984 [RX_INPUT] configuration >>>>>
7257 22:50:14.014504 [RX_INPUT] configuration <<<<<
7258 22:50:14.021442 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7259 22:50:14.024580 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7260 22:50:14.031674 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7261 22:50:14.037904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7262 22:50:14.044517 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7263 22:50:14.051544 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7264 22:50:14.054635 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7265 22:50:14.058197 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7266 22:50:14.061233 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7267 22:50:14.068173 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7268 22:50:14.071170 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7269 22:50:14.075198 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7270 22:50:14.078138 ===================================
7271 22:50:14.081450 LPDDR4 DRAM CONFIGURATION
7272 22:50:14.085119 ===================================
7273 22:50:14.085550 EX_ROW_EN[0] = 0x0
7274 22:50:14.088192 EX_ROW_EN[1] = 0x0
7275 22:50:14.088574 LP4Y_EN = 0x0
7276 22:50:14.091322 WORK_FSP = 0x1
7277 22:50:14.091705 WL = 0x5
7278 22:50:14.094924 RL = 0x5
7279 22:50:14.095308 BL = 0x2
7280 22:50:14.098626 RPST = 0x0
7281 22:50:14.101647 RD_PRE = 0x0
7282 22:50:14.102033 WR_PRE = 0x1
7283 22:50:14.104915 WR_PST = 0x1
7284 22:50:14.105335 DBI_WR = 0x0
7285 22:50:14.109118 DBI_RD = 0x0
7286 22:50:14.109644 OTF = 0x1
7287 22:50:14.111579 ===================================
7288 22:50:14.114898 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7289 22:50:14.119072 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7290 22:50:14.125066 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7291 22:50:14.129120 ===================================
7292 22:50:14.129617 LPDDR4 DRAM CONFIGURATION
7293 22:50:14.131811 ===================================
7294 22:50:14.134972 EX_ROW_EN[0] = 0x10
7295 22:50:14.138773 EX_ROW_EN[1] = 0x0
7296 22:50:14.139260 LP4Y_EN = 0x0
7297 22:50:14.141966 WORK_FSP = 0x1
7298 22:50:14.142348 WL = 0x5
7299 22:50:14.145322 RL = 0x5
7300 22:50:14.145703 BL = 0x2
7301 22:50:14.148464 RPST = 0x0
7302 22:50:14.148948 RD_PRE = 0x0
7303 22:50:14.151923 WR_PRE = 0x1
7304 22:50:14.152467 WR_PST = 0x1
7305 22:50:14.155352 DBI_WR = 0x0
7306 22:50:14.155986 DBI_RD = 0x0
7307 22:50:14.158792 OTF = 0x1
7308 22:50:14.161715 ===================================
7309 22:50:14.168548 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7310 22:50:14.169026 ==
7311 22:50:14.171894 Dram Type= 6, Freq= 0, CH_0, rank 0
7312 22:50:14.175296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7313 22:50:14.175684 ==
7314 22:50:14.178806 [Duty_Offset_Calibration]
7315 22:50:14.179191 B0:2 B1:-1 CA:1
7316 22:50:14.179493
7317 22:50:14.182069 [DutyScan_Calibration_Flow] k_type=0
7318 22:50:14.191627
7319 22:50:14.192008 ==CLK 0==
7320 22:50:14.195324 Final CLK duty delay cell = -4
7321 22:50:14.198502 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7322 22:50:14.201442 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7323 22:50:14.205173 [-4] AVG Duty = 4937%(X100)
7324 22:50:14.205621
7325 22:50:14.208980 CH0 CLK Duty spec in!! Max-Min= 187%
7326 22:50:14.211549 [DutyScan_Calibration_Flow] ====Done====
7327 22:50:14.212062
7328 22:50:14.215295 [DutyScan_Calibration_Flow] k_type=1
7329 22:50:14.231043
7330 22:50:14.231561 ==DQS 0 ==
7331 22:50:14.234631 Final DQS duty delay cell = 0
7332 22:50:14.237938 [0] MAX Duty = 5125%(X100), DQS PI = 56
7333 22:50:14.241519 [0] MIN Duty = 5000%(X100), DQS PI = 14
7334 22:50:14.244585 [0] AVG Duty = 5062%(X100)
7335 22:50:14.245001
7336 22:50:14.245372 ==DQS 1 ==
7337 22:50:14.248139 Final DQS duty delay cell = -4
7338 22:50:14.251291 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7339 22:50:14.254784 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7340 22:50:14.258172 [-4] AVG Duty = 5046%(X100)
7341 22:50:14.258690
7342 22:50:14.261572 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7343 22:50:14.261989
7344 22:50:14.265090 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7345 22:50:14.268397 [DutyScan_Calibration_Flow] ====Done====
7346 22:50:14.268909
7347 22:50:14.271117 [DutyScan_Calibration_Flow] k_type=3
7348 22:50:14.288935
7349 22:50:14.289490 ==DQM 0 ==
7350 22:50:14.291928 Final DQM duty delay cell = 0
7351 22:50:14.295284 [0] MAX Duty = 5000%(X100), DQS PI = 20
7352 22:50:14.298668 [0] MIN Duty = 4875%(X100), DQS PI = 4
7353 22:50:14.299186 [0] AVG Duty = 4937%(X100)
7354 22:50:14.302286
7355 22:50:14.302801 ==DQM 1 ==
7356 22:50:14.305499 Final DQM duty delay cell = 0
7357 22:50:14.308910 [0] MAX Duty = 5187%(X100), DQS PI = 56
7358 22:50:14.312670 [0] MIN Duty = 4969%(X100), DQS PI = 18
7359 22:50:14.313186 [0] AVG Duty = 5078%(X100)
7360 22:50:14.315149
7361 22:50:14.318207 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7362 22:50:14.318637
7363 22:50:14.321879 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7364 22:50:14.325285 [DutyScan_Calibration_Flow] ====Done====
7365 22:50:14.325705
7366 22:50:14.328571 [DutyScan_Calibration_Flow] k_type=2
7367 22:50:14.344866
7368 22:50:14.345406 ==DQ 0 ==
7369 22:50:14.347979 Final DQ duty delay cell = -4
7370 22:50:14.351637 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7371 22:50:14.355048 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7372 22:50:14.358669 [-4] AVG Duty = 4937%(X100)
7373 22:50:14.359249
7374 22:50:14.359607 ==DQ 1 ==
7375 22:50:14.361468 Final DQ duty delay cell = 0
7376 22:50:14.365138 [0] MAX Duty = 5031%(X100), DQS PI = 30
7377 22:50:14.368981 [0] MIN Duty = 4907%(X100), DQS PI = 18
7378 22:50:14.369585 [0] AVG Duty = 4969%(X100)
7379 22:50:14.369931
7380 22:50:14.375703 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7381 22:50:14.376244
7382 22:50:14.378213 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7383 22:50:14.381848 [DutyScan_Calibration_Flow] ====Done====
7384 22:50:14.382388 ==
7385 22:50:14.384642 Dram Type= 6, Freq= 0, CH_1, rank 0
7386 22:50:14.388418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7387 22:50:14.388990 ==
7388 22:50:14.391615 [Duty_Offset_Calibration]
7389 22:50:14.392024 B0:1 B1:1 CA:2
7390 22:50:14.392351
7391 22:50:14.394526 [DutyScan_Calibration_Flow] k_type=0
7392 22:50:14.405648
7393 22:50:14.406162 ==CLK 0==
7394 22:50:14.408780 Final CLK duty delay cell = 0
7395 22:50:14.412269 [0] MAX Duty = 5187%(X100), DQS PI = 24
7396 22:50:14.415617 [0] MIN Duty = 4969%(X100), DQS PI = 40
7397 22:50:14.416128 [0] AVG Duty = 5078%(X100)
7398 22:50:14.418763
7399 22:50:14.419176 CH1 CLK Duty spec in!! Max-Min= 218%
7400 22:50:14.425484 [DutyScan_Calibration_Flow] ====Done====
7401 22:50:14.426019
7402 22:50:14.428758 [DutyScan_Calibration_Flow] k_type=1
7403 22:50:14.445357
7404 22:50:14.445870 ==DQS 0 ==
7405 22:50:14.448838 Final DQS duty delay cell = 0
7406 22:50:14.452195 [0] MAX Duty = 5062%(X100), DQS PI = 22
7407 22:50:14.455093 [0] MIN Duty = 4813%(X100), DQS PI = 50
7408 22:50:14.455509 [0] AVG Duty = 4937%(X100)
7409 22:50:14.458668
7410 22:50:14.459179 ==DQS 1 ==
7411 22:50:14.461994 Final DQS duty delay cell = 0
7412 22:50:14.465823 [0] MAX Duty = 5031%(X100), DQS PI = 34
7413 22:50:14.468633 [0] MIN Duty = 4938%(X100), DQS PI = 14
7414 22:50:14.469048 [0] AVG Duty = 4984%(X100)
7415 22:50:14.472000
7416 22:50:14.475258 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7417 22:50:14.475781
7418 22:50:14.479037 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7419 22:50:14.481978 [DutyScan_Calibration_Flow] ====Done====
7420 22:50:14.482395
7421 22:50:14.485123 [DutyScan_Calibration_Flow] k_type=3
7422 22:50:14.501989
7423 22:50:14.502634 ==DQM 0 ==
7424 22:50:14.505632 Final DQM duty delay cell = 0
7425 22:50:14.508923 [0] MAX Duty = 5156%(X100), DQS PI = 20
7426 22:50:14.512227 [0] MIN Duty = 4844%(X100), DQS PI = 50
7427 22:50:14.515491 [0] AVG Duty = 5000%(X100)
7428 22:50:14.516011
7429 22:50:14.516346 ==DQM 1 ==
7430 22:50:14.518371 Final DQM duty delay cell = 0
7431 22:50:14.521995 [0] MAX Duty = 5156%(X100), DQS PI = 60
7432 22:50:14.525034 [0] MIN Duty = 4907%(X100), DQS PI = 20
7433 22:50:14.528633 [0] AVG Duty = 5031%(X100)
7434 22:50:14.529148
7435 22:50:14.532504 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7436 22:50:14.533030
7437 22:50:14.535423 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7438 22:50:14.538530 [DutyScan_Calibration_Flow] ====Done====
7439 22:50:14.539049
7440 22:50:14.541927 [DutyScan_Calibration_Flow] k_type=2
7441 22:50:14.558809
7442 22:50:14.559322 ==DQ 0 ==
7443 22:50:14.562207 Final DQ duty delay cell = 0
7444 22:50:14.565286 [0] MAX Duty = 5125%(X100), DQS PI = 20
7445 22:50:14.569196 [0] MIN Duty = 4907%(X100), DQS PI = 52
7446 22:50:14.569752 [0] AVG Duty = 5016%(X100)
7447 22:50:14.570088
7448 22:50:14.571940 ==DQ 1 ==
7449 22:50:14.575756 Final DQ duty delay cell = 0
7450 22:50:14.579334 [0] MAX Duty = 5093%(X100), DQS PI = 26
7451 22:50:14.582064 [0] MIN Duty = 5031%(X100), DQS PI = 0
7452 22:50:14.582486 [0] AVG Duty = 5062%(X100)
7453 22:50:14.582817
7454 22:50:14.586299 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7455 22:50:14.586718
7456 22:50:14.589069 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7457 22:50:14.595502 [DutyScan_Calibration_Flow] ====Done====
7458 22:50:14.598817 nWR fixed to 30
7459 22:50:14.599369 [ModeRegInit_LP4] CH0 RK0
7460 22:50:14.602005 [ModeRegInit_LP4] CH0 RK1
7461 22:50:14.605881 [ModeRegInit_LP4] CH1 RK0
7462 22:50:14.606299 [ModeRegInit_LP4] CH1 RK1
7463 22:50:14.609435 match AC timing 5
7464 22:50:14.612577 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7465 22:50:14.616053 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7466 22:50:14.622177 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7467 22:50:14.625306 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7468 22:50:14.632576 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7469 22:50:14.633092 [MiockJmeterHQA]
7470 22:50:14.633460
7471 22:50:14.635299 [DramcMiockJmeter] u1RxGatingPI = 0
7472 22:50:14.635716 0 : 4366, 4139
7473 22:50:14.639044 4 : 4368, 4139
7474 22:50:14.639580 8 : 4252, 4027
7475 22:50:14.642439 12 : 4255, 4027
7476 22:50:14.642864 16 : 4260, 4032
7477 22:50:14.645716 20 : 4365, 4140
7478 22:50:14.646141 24 : 4255, 4029
7479 22:50:14.646478 28 : 4255, 4029
7480 22:50:14.649024 32 : 4363, 4137
7481 22:50:14.649476 36 : 4257, 4030
7482 22:50:14.652430 40 : 4258, 4029
7483 22:50:14.652852 44 : 4252, 4027
7484 22:50:14.655459 48 : 4368, 4142
7485 22:50:14.655879 52 : 4255, 4029
7486 22:50:14.659419 56 : 4255, 4029
7487 22:50:14.659943 60 : 4368, 4139
7488 22:50:14.660282 64 : 4252, 4027
7489 22:50:14.662113 68 : 4253, 4026
7490 22:50:14.662536 72 : 4254, 4030
7491 22:50:14.665863 76 : 4257, 4031
7492 22:50:14.666284 80 : 4255, 4029
7493 22:50:14.668910 84 : 4253, 4026
7494 22:50:14.669367 88 : 4255, 4032
7495 22:50:14.672494 92 : 4250, 4026
7496 22:50:14.673016 96 : 4252, 3175
7497 22:50:14.673393 100 : 4255, 0
7498 22:50:14.676392 104 : 4253, 0
7499 22:50:14.676917 108 : 4253, 0
7500 22:50:14.677295 112 : 4252, 0
7501 22:50:14.678893 116 : 4255, 0
7502 22:50:14.679315 120 : 4363, 0
7503 22:50:14.682254 124 : 4250, 0
7504 22:50:14.682678 128 : 4364, 0
7505 22:50:14.683013 132 : 4255, 0
7506 22:50:14.685883 136 : 4250, 0
7507 22:50:14.686307 140 : 4254, 0
7508 22:50:14.689358 144 : 4363, 0
7509 22:50:14.689947 148 : 4249, 0
7510 22:50:14.690292 152 : 4365, 0
7511 22:50:14.692144 156 : 4252, 0
7512 22:50:14.692568 160 : 4360, 0
7513 22:50:14.696211 164 : 4252, 0
7514 22:50:14.696741 168 : 4250, 0
7515 22:50:14.697084 172 : 4250, 0
7516 22:50:14.699296 176 : 4361, 0
7517 22:50:14.699720 180 : 4253, 0
7518 22:50:14.700057 184 : 4255, 0
7519 22:50:14.702305 188 : 4255, 0
7520 22:50:14.702829 192 : 4363, 0
7521 22:50:14.705920 196 : 4363, 0
7522 22:50:14.706449 200 : 4363, 0
7523 22:50:14.706785 204 : 4252, 0
7524 22:50:14.708789 208 : 4250, 0
7525 22:50:14.709241 212 : 4250, 112
7526 22:50:14.712524 216 : 4252, 3673
7527 22:50:14.713043 220 : 4250, 4027
7528 22:50:14.715688 224 : 4365, 4140
7529 22:50:14.716210 228 : 4361, 4137
7530 22:50:14.718811 232 : 4255, 4030
7531 22:50:14.719237 236 : 4250, 4027
7532 22:50:14.722414 240 : 4361, 4138
7533 22:50:14.722943 244 : 4252, 4029
7534 22:50:14.723281 248 : 4365, 4140
7535 22:50:14.725721 252 : 4254, 4030
7536 22:50:14.726189 256 : 4255, 4029
7537 22:50:14.729184 260 : 4254, 4030
7538 22:50:14.729761 264 : 4250, 4027
7539 22:50:14.732711 268 : 4257, 4032
7540 22:50:14.733273 272 : 4255, 4029
7541 22:50:14.735911 276 : 4250, 4027
7542 22:50:14.736441 280 : 4250, 4027
7543 22:50:14.738979 284 : 4250, 4027
7544 22:50:14.739499 288 : 4368, 4142
7545 22:50:14.742517 292 : 4366, 4140
7546 22:50:14.743051 296 : 4250, 4027
7547 22:50:14.743387 300 : 4255, 4029
7548 22:50:14.745966 304 : 4250, 4027
7549 22:50:14.746398 308 : 4250, 4027
7550 22:50:14.748675 312 : 4361, 4138
7551 22:50:14.749096 316 : 4364, 4140
7552 22:50:14.751859 320 : 4250, 4027
7553 22:50:14.752280 324 : 4363, 4139
7554 22:50:14.755182 328 : 4253, 4029
7555 22:50:14.755606 332 : 4363, 2986
7556 22:50:14.758618 336 : 4250, 40
7557 22:50:14.759040
7558 22:50:14.759370 MIOCK jitter meter ch=0
7559 22:50:14.759678
7560 22:50:14.762044 1T = (336-100) = 236 dly cells
7561 22:50:14.769694 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7562 22:50:14.770212 ==
7563 22:50:14.771922 Dram Type= 6, Freq= 0, CH_0, rank 0
7564 22:50:14.775798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 22:50:14.776340 ==
7566 22:50:14.782064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 22:50:14.785047 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 22:50:14.792618 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 22:50:14.795742 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 22:50:14.805365 [CA 0] Center 44 (14~75) winsize 62
7571 22:50:14.808591 [CA 1] Center 44 (13~75) winsize 63
7572 22:50:14.812040 [CA 2] Center 40 (11~69) winsize 59
7573 22:50:14.815475 [CA 3] Center 39 (10~69) winsize 60
7574 22:50:14.818690 [CA 4] Center 38 (8~68) winsize 61
7575 22:50:14.822110 [CA 5] Center 37 (7~67) winsize 61
7576 22:50:14.822626
7577 22:50:14.825425 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7578 22:50:14.825846
7579 22:50:14.828731 [CATrainingPosCal] consider 1 rank data
7580 22:50:14.832927 u2DelayCellTimex100 = 275/100 ps
7581 22:50:14.835782 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7582 22:50:14.841894 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7583 22:50:14.845263 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7584 22:50:14.848815 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7585 22:50:14.851670 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7586 22:50:14.855968 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7587 22:50:14.856490
7588 22:50:14.858610 CA PerBit enable=1, Macro0, CA PI delay=37
7589 22:50:14.859120
7590 22:50:14.862101 [CBTSetCACLKResult] CA Dly = 37
7591 22:50:14.865053 CS Dly: 10 (0~41)
7592 22:50:14.868822 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 22:50:14.871817 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 22:50:14.872232 ==
7595 22:50:14.875367 Dram Type= 6, Freq= 0, CH_0, rank 1
7596 22:50:14.879286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 22:50:14.881842 ==
7598 22:50:14.885302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7599 22:50:14.888964 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7600 22:50:14.895312 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7601 22:50:14.898704 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7602 22:50:14.909634 [CA 0] Center 44 (14~75) winsize 62
7603 22:50:14.912727 [CA 1] Center 44 (14~75) winsize 62
7604 22:50:14.916443 [CA 2] Center 40 (11~69) winsize 59
7605 22:50:14.919419 [CA 3] Center 39 (10~69) winsize 60
7606 22:50:14.922508 [CA 4] Center 37 (8~67) winsize 60
7607 22:50:14.925701 [CA 5] Center 37 (7~67) winsize 61
7608 22:50:14.926121
7609 22:50:14.929289 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7610 22:50:14.929821
7611 22:50:14.932168 [CATrainingPosCal] consider 2 rank data
7612 22:50:14.936149 u2DelayCellTimex100 = 275/100 ps
7613 22:50:14.939549 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7614 22:50:14.945702 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7615 22:50:14.949403 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7616 22:50:14.952663 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7617 22:50:14.956453 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7618 22:50:14.959340 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7619 22:50:14.959864
7620 22:50:14.962964 CA PerBit enable=1, Macro0, CA PI delay=37
7621 22:50:14.963382
7622 22:50:14.965742 [CBTSetCACLKResult] CA Dly = 37
7623 22:50:14.969034 CS Dly: 11 (0~43)
7624 22:50:14.972775 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7625 22:50:14.976241 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7626 22:50:14.976763
7627 22:50:14.979150 ----->DramcWriteLeveling(PI) begin...
7628 22:50:14.979574 ==
7629 22:50:14.982376 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 22:50:14.989618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 22:50:14.990173 ==
7632 22:50:14.993104 Write leveling (Byte 0): 33 => 33
7633 22:50:14.993589 Write leveling (Byte 1): 26 => 26
7634 22:50:14.995597 DramcWriteLeveling(PI) end<-----
7635 22:50:14.996015
7636 22:50:14.996342 ==
7637 22:50:14.998817 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 22:50:15.005758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 22:50:15.006177 ==
7640 22:50:15.009814 [Gating] SW mode calibration
7641 22:50:15.017048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7642 22:50:15.019273 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7643 22:50:15.025850 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 22:50:15.029538 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 22:50:15.032677 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 22:50:15.039673 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 22:50:15.042688 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 22:50:15.045930 1 4 20 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7649 22:50:15.049383 1 4 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7650 22:50:15.055943 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7651 22:50:15.059848 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7652 22:50:15.062566 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7653 22:50:15.069493 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 22:50:15.072846 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7655 22:50:15.076059 1 5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7656 22:50:15.083284 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7657 22:50:15.085836 1 5 24 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7658 22:50:15.089353 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 22:50:15.096286 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 22:50:15.099367 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 22:50:15.102293 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 22:50:15.109180 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 22:50:15.112504 1 6 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
7664 22:50:15.115943 1 6 20 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
7665 22:50:15.122913 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7666 22:50:15.125725 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 22:50:15.129134 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 22:50:15.135927 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 22:50:15.139485 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 22:50:15.143119 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 22:50:15.145650 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7672 22:50:15.152755 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7673 22:50:15.155989 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7674 22:50:15.159453 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 22:50:15.166152 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 22:50:15.169373 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 22:50:15.172846 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 22:50:15.179521 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 22:50:15.182988 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 22:50:15.185895 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 22:50:15.193284 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 22:50:15.195924 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 22:50:15.199770 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 22:50:15.206211 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 22:50:15.209484 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 22:50:15.212730 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7687 22:50:15.219613 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7688 22:50:15.222333 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7689 22:50:15.226430 Total UI for P1: 0, mck2ui 16
7690 22:50:15.229154 best dqsien dly found for B0: ( 1, 9, 14)
7691 22:50:15.232801 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7692 22:50:15.235979 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7693 22:50:15.239442 Total UI for P1: 0, mck2ui 16
7694 22:50:15.242457 best dqsien dly found for B1: ( 1, 9, 20)
7695 22:50:15.246608 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7696 22:50:15.249608 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7697 22:50:15.252490
7698 22:50:15.256615 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7699 22:50:15.259509 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7700 22:50:15.262765 [Gating] SW calibration Done
7701 22:50:15.263185 ==
7702 22:50:15.265751 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 22:50:15.269375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 22:50:15.269793 ==
7705 22:50:15.270125 RX Vref Scan: 0
7706 22:50:15.270433
7707 22:50:15.272814 RX Vref 0 -> 0, step: 1
7708 22:50:15.273552
7709 22:50:15.276268 RX Delay 0 -> 252, step: 8
7710 22:50:15.279723 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7711 22:50:15.283398 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7712 22:50:15.289690 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7713 22:50:15.292540 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7714 22:50:15.296057 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7715 22:50:15.299501 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7716 22:50:15.303693 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7717 22:50:15.305975 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7718 22:50:15.312335 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7719 22:50:15.316702 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7720 22:50:15.319703 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7721 22:50:15.322787 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7722 22:50:15.325843 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7723 22:50:15.332896 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7724 22:50:15.335876 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7725 22:50:15.340114 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7726 22:50:15.340625 ==
7727 22:50:15.342935 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 22:50:15.346057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 22:50:15.346474 ==
7730 22:50:15.349420 DQS Delay:
7731 22:50:15.349901 DQS0 = 0, DQS1 = 0
7732 22:50:15.353099 DQM Delay:
7733 22:50:15.353541 DQM0 = 132, DQM1 = 125
7734 22:50:15.355808 DQ Delay:
7735 22:50:15.359518 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7736 22:50:15.363229 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7737 22:50:15.365768 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7738 22:50:15.369386 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7739 22:50:15.369903
7740 22:50:15.370235
7741 22:50:15.370543 ==
7742 22:50:15.372988 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 22:50:15.376009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 22:50:15.376529 ==
7745 22:50:15.376863
7746 22:50:15.377170
7747 22:50:15.379265 TX Vref Scan disable
7748 22:50:15.382605 == TX Byte 0 ==
7749 22:50:15.386336 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7750 22:50:15.389375 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7751 22:50:15.392763 == TX Byte 1 ==
7752 22:50:15.395918 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7753 22:50:15.399137 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7754 22:50:15.399556 ==
7755 22:50:15.403353 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 22:50:15.406301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 22:50:15.409320 ==
7758 22:50:15.422730
7759 22:50:15.425636 TX Vref early break, caculate TX vref
7760 22:50:15.429146 TX Vref=16, minBit 1, minWin=21, winSum=354
7761 22:50:15.432253 TX Vref=18, minBit 4, minWin=22, winSum=368
7762 22:50:15.435957 TX Vref=20, minBit 1, minWin=23, winSum=378
7763 22:50:15.438910 TX Vref=22, minBit 4, minWin=22, winSum=382
7764 22:50:15.442548 TX Vref=24, minBit 4, minWin=23, winSum=392
7765 22:50:15.449305 TX Vref=26, minBit 4, minWin=24, winSum=409
7766 22:50:15.452552 TX Vref=28, minBit 4, minWin=24, winSum=409
7767 22:50:15.455765 TX Vref=30, minBit 0, minWin=25, winSum=412
7768 22:50:15.459476 TX Vref=32, minBit 9, minWin=24, winSum=405
7769 22:50:15.462489 TX Vref=34, minBit 4, minWin=23, winSum=395
7770 22:50:15.465736 TX Vref=36, minBit 0, minWin=23, winSum=387
7771 22:50:15.472480 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 30
7772 22:50:15.472999
7773 22:50:15.476163 Final TX Range 0 Vref 30
7774 22:50:15.476679
7775 22:50:15.477015 ==
7776 22:50:15.479465 Dram Type= 6, Freq= 0, CH_0, rank 0
7777 22:50:15.482855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7778 22:50:15.483287 ==
7779 22:50:15.483801
7780 22:50:15.484211
7781 22:50:15.486361 TX Vref Scan disable
7782 22:50:15.492894 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7783 22:50:15.493454 == TX Byte 0 ==
7784 22:50:15.495741 u2DelayCellOfst[0]=14 cells (4 PI)
7785 22:50:15.499214 u2DelayCellOfst[1]=17 cells (5 PI)
7786 22:50:15.502648 u2DelayCellOfst[2]=10 cells (3 PI)
7787 22:50:15.506033 u2DelayCellOfst[3]=14 cells (4 PI)
7788 22:50:15.509630 u2DelayCellOfst[4]=7 cells (2 PI)
7789 22:50:15.512640 u2DelayCellOfst[5]=0 cells (0 PI)
7790 22:50:15.516862 u2DelayCellOfst[6]=21 cells (6 PI)
7791 22:50:15.517404 u2DelayCellOfst[7]=17 cells (5 PI)
7792 22:50:15.522747 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7793 22:50:15.525866 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7794 22:50:15.526287 == TX Byte 1 ==
7795 22:50:15.529553 u2DelayCellOfst[8]=0 cells (0 PI)
7796 22:50:15.533015 u2DelayCellOfst[9]=0 cells (0 PI)
7797 22:50:15.536446 u2DelayCellOfst[10]=7 cells (2 PI)
7798 22:50:15.540728 u2DelayCellOfst[11]=0 cells (0 PI)
7799 22:50:15.542536 u2DelayCellOfst[12]=10 cells (3 PI)
7800 22:50:15.545887 u2DelayCellOfst[13]=10 cells (3 PI)
7801 22:50:15.550417 u2DelayCellOfst[14]=17 cells (5 PI)
7802 22:50:15.552628 u2DelayCellOfst[15]=10 cells (3 PI)
7803 22:50:15.556171 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7804 22:50:15.562642 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7805 22:50:15.563144 DramC Write-DBI on
7806 22:50:15.563559 ==
7807 22:50:15.566906 Dram Type= 6, Freq= 0, CH_0, rank 0
7808 22:50:15.569699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7809 22:50:15.570120 ==
7810 22:50:15.570455
7811 22:50:15.572874
7812 22:50:15.573318 TX Vref Scan disable
7813 22:50:15.576387 == TX Byte 0 ==
7814 22:50:15.579571 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7815 22:50:15.583024 == TX Byte 1 ==
7816 22:50:15.585896 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7817 22:50:15.586316 DramC Write-DBI off
7818 22:50:15.589484
7819 22:50:15.589993 [DATLAT]
7820 22:50:15.590325 Freq=1600, CH0 RK0
7821 22:50:15.590637
7822 22:50:15.592773 DATLAT Default: 0xf
7823 22:50:15.593324 0, 0xFFFF, sum = 0
7824 22:50:15.596034 1, 0xFFFF, sum = 0
7825 22:50:15.596459 2, 0xFFFF, sum = 0
7826 22:50:15.599552 3, 0xFFFF, sum = 0
7827 22:50:15.599978 4, 0xFFFF, sum = 0
7828 22:50:15.602873 5, 0xFFFF, sum = 0
7829 22:50:15.603296 6, 0xFFFF, sum = 0
7830 22:50:15.606530 7, 0xFFFF, sum = 0
7831 22:50:15.609870 8, 0xFFFF, sum = 0
7832 22:50:15.610390 9, 0xFFFF, sum = 0
7833 22:50:15.612544 10, 0xFFFF, sum = 0
7834 22:50:15.612988 11, 0xFFFF, sum = 0
7835 22:50:15.616223 12, 0xFFFF, sum = 0
7836 22:50:15.616751 13, 0xFFFF, sum = 0
7837 22:50:15.619380 14, 0x0, sum = 1
7838 22:50:15.619902 15, 0x0, sum = 2
7839 22:50:15.622732 16, 0x0, sum = 3
7840 22:50:15.623159 17, 0x0, sum = 4
7841 22:50:15.626047 best_step = 15
7842 22:50:15.626566
7843 22:50:15.626901 ==
7844 22:50:15.629356 Dram Type= 6, Freq= 0, CH_0, rank 0
7845 22:50:15.632754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7846 22:50:15.633327 ==
7847 22:50:15.633668 RX Vref Scan: 1
7848 22:50:15.633980
7849 22:50:15.635614 Set Vref Range= 24 -> 127
7850 22:50:15.636031
7851 22:50:15.639347 RX Vref 24 -> 127, step: 1
7852 22:50:15.639765
7853 22:50:15.642577 RX Delay 11 -> 252, step: 4
7854 22:50:15.643146
7855 22:50:15.646205 Set Vref, RX VrefLevel [Byte0]: 24
7856 22:50:15.648787 [Byte1]: 24
7857 22:50:15.649204
7858 22:50:15.652536 Set Vref, RX VrefLevel [Byte0]: 25
7859 22:50:15.656196 [Byte1]: 25
7860 22:50:15.656714
7861 22:50:15.659598 Set Vref, RX VrefLevel [Byte0]: 26
7862 22:50:15.662654 [Byte1]: 26
7863 22:50:15.666267
7864 22:50:15.666779 Set Vref, RX VrefLevel [Byte0]: 27
7865 22:50:15.669496 [Byte1]: 27
7866 22:50:15.674078
7867 22:50:15.674595 Set Vref, RX VrefLevel [Byte0]: 28
7868 22:50:15.677414 [Byte1]: 28
7869 22:50:15.681855
7870 22:50:15.682276 Set Vref, RX VrefLevel [Byte0]: 29
7871 22:50:15.685149 [Byte1]: 29
7872 22:50:15.689682
7873 22:50:15.690199 Set Vref, RX VrefLevel [Byte0]: 30
7874 22:50:15.692820 [Byte1]: 30
7875 22:50:15.697023
7876 22:50:15.697577 Set Vref, RX VrefLevel [Byte0]: 31
7877 22:50:15.699974 [Byte1]: 31
7878 22:50:15.705094
7879 22:50:15.705653 Set Vref, RX VrefLevel [Byte0]: 32
7880 22:50:15.707785 [Byte1]: 32
7881 22:50:15.712120
7882 22:50:15.712672 Set Vref, RX VrefLevel [Byte0]: 33
7883 22:50:15.715839 [Byte1]: 33
7884 22:50:15.719961
7885 22:50:15.720484 Set Vref, RX VrefLevel [Byte0]: 34
7886 22:50:15.723157 [Byte1]: 34
7887 22:50:15.726995
7888 22:50:15.727510 Set Vref, RX VrefLevel [Byte0]: 35
7889 22:50:15.730489 [Byte1]: 35
7890 22:50:15.735200
7891 22:50:15.735720 Set Vref, RX VrefLevel [Byte0]: 36
7892 22:50:15.737940 [Byte1]: 36
7893 22:50:15.742413
7894 22:50:15.742948 Set Vref, RX VrefLevel [Byte0]: 37
7895 22:50:15.745890 [Byte1]: 37
7896 22:50:15.749877
7897 22:50:15.750296 Set Vref, RX VrefLevel [Byte0]: 38
7898 22:50:15.753111 [Byte1]: 38
7899 22:50:15.757695
7900 22:50:15.758214 Set Vref, RX VrefLevel [Byte0]: 39
7901 22:50:15.761085 [Byte1]: 39
7902 22:50:15.765943
7903 22:50:15.766464 Set Vref, RX VrefLevel [Byte0]: 40
7904 22:50:15.768313 [Byte1]: 40
7905 22:50:15.773193
7906 22:50:15.773656 Set Vref, RX VrefLevel [Byte0]: 41
7907 22:50:15.776943 [Byte1]: 41
7908 22:50:15.780547
7909 22:50:15.781068 Set Vref, RX VrefLevel [Byte0]: 42
7910 22:50:15.783626 [Byte1]: 42
7911 22:50:15.788886
7912 22:50:15.789432 Set Vref, RX VrefLevel [Byte0]: 43
7913 22:50:15.791574 [Byte1]: 43
7914 22:50:15.795581
7915 22:50:15.796004 Set Vref, RX VrefLevel [Byte0]: 44
7916 22:50:15.799506 [Byte1]: 44
7917 22:50:15.803990
7918 22:50:15.804506 Set Vref, RX VrefLevel [Byte0]: 45
7919 22:50:15.806456 [Byte1]: 45
7920 22:50:15.811112
7921 22:50:15.811627 Set Vref, RX VrefLevel [Byte0]: 46
7922 22:50:15.814592 [Byte1]: 46
7923 22:50:15.818800
7924 22:50:15.819426 Set Vref, RX VrefLevel [Byte0]: 47
7925 22:50:15.822489 [Byte1]: 47
7926 22:50:15.826041
7927 22:50:15.826464 Set Vref, RX VrefLevel [Byte0]: 48
7928 22:50:15.829379 [Byte1]: 48
7929 22:50:15.834579
7930 22:50:15.835094 Set Vref, RX VrefLevel [Byte0]: 49
7931 22:50:15.837643 [Byte1]: 49
7932 22:50:15.841424
7933 22:50:15.841941 Set Vref, RX VrefLevel [Byte0]: 50
7934 22:50:15.844921 [Byte1]: 50
7935 22:50:15.848999
7936 22:50:15.849602 Set Vref, RX VrefLevel [Byte0]: 51
7937 22:50:15.852537 [Byte1]: 51
7938 22:50:15.856845
7939 22:50:15.857386 Set Vref, RX VrefLevel [Byte0]: 52
7940 22:50:15.860374 [Byte1]: 52
7941 22:50:15.864153
7942 22:50:15.864571 Set Vref, RX VrefLevel [Byte0]: 53
7943 22:50:15.867597 [Byte1]: 53
7944 22:50:15.871927
7945 22:50:15.872445 Set Vref, RX VrefLevel [Byte0]: 54
7946 22:50:15.874850 [Byte1]: 54
7947 22:50:15.879435
7948 22:50:15.879944 Set Vref, RX VrefLevel [Byte0]: 55
7949 22:50:15.882568 [Byte1]: 55
7950 22:50:15.886987
7951 22:50:15.887403 Set Vref, RX VrefLevel [Byte0]: 56
7952 22:50:15.890101 [Byte1]: 56
7953 22:50:15.894838
7954 22:50:15.895388 Set Vref, RX VrefLevel [Byte0]: 57
7955 22:50:15.898001 [Byte1]: 57
7956 22:50:15.902303
7957 22:50:15.902821 Set Vref, RX VrefLevel [Byte0]: 58
7958 22:50:15.905730 [Byte1]: 58
7959 22:50:15.910393
7960 22:50:15.910911 Set Vref, RX VrefLevel [Byte0]: 59
7961 22:50:15.913484 [Byte1]: 59
7962 22:50:15.918060
7963 22:50:15.918577 Set Vref, RX VrefLevel [Byte0]: 60
7964 22:50:15.920905 [Byte1]: 60
7965 22:50:15.925473
7966 22:50:15.925984 Set Vref, RX VrefLevel [Byte0]: 61
7967 22:50:15.928867 [Byte1]: 61
7968 22:50:15.932854
7969 22:50:15.933420 Set Vref, RX VrefLevel [Byte0]: 62
7970 22:50:15.936150 [Byte1]: 62
7971 22:50:15.940292
7972 22:50:15.940707 Set Vref, RX VrefLevel [Byte0]: 63
7973 22:50:15.943974 [Byte1]: 63
7974 22:50:15.948163
7975 22:50:15.948679 Set Vref, RX VrefLevel [Byte0]: 64
7976 22:50:15.951370 [Byte1]: 64
7977 22:50:15.955479
7978 22:50:15.955995 Set Vref, RX VrefLevel [Byte0]: 65
7979 22:50:15.958976 [Byte1]: 65
7980 22:50:15.963270
7981 22:50:15.963788 Set Vref, RX VrefLevel [Byte0]: 66
7982 22:50:15.966501 [Byte1]: 66
7983 22:50:15.971298
7984 22:50:15.971877 Set Vref, RX VrefLevel [Byte0]: 67
7985 22:50:15.973934 [Byte1]: 67
7986 22:50:15.978697
7987 22:50:15.979212 Set Vref, RX VrefLevel [Byte0]: 68
7988 22:50:15.981742 [Byte1]: 68
7989 22:50:15.985732
7990 22:50:15.986143 Set Vref, RX VrefLevel [Byte0]: 69
7991 22:50:15.989343 [Byte1]: 69
7992 22:50:15.993716
7993 22:50:15.994230 Set Vref, RX VrefLevel [Byte0]: 70
7994 22:50:15.996912 [Byte1]: 70
7995 22:50:16.001066
7996 22:50:16.001510 Set Vref, RX VrefLevel [Byte0]: 71
7997 22:50:16.005181 [Byte1]: 71
7998 22:50:16.008714
7999 22:50:16.009127 Set Vref, RX VrefLevel [Byte0]: 72
8000 22:50:16.012385 [Byte1]: 72
8001 22:50:16.016825
8002 22:50:16.017476 Set Vref, RX VrefLevel [Byte0]: 73
8003 22:50:16.020371 [Byte1]: 73
8004 22:50:16.024431
8005 22:50:16.024845 Set Vref, RX VrefLevel [Byte0]: 74
8006 22:50:16.027302 [Byte1]: 74
8007 22:50:16.031885
8008 22:50:16.032300 Set Vref, RX VrefLevel [Byte0]: 75
8009 22:50:16.035416 [Byte1]: 75
8010 22:50:16.039946
8011 22:50:16.040472 Set Vref, RX VrefLevel [Byte0]: 76
8012 22:50:16.042993 [Byte1]: 76
8013 22:50:16.047163
8014 22:50:16.047679 Final RX Vref Byte 0 = 57 to rank0
8015 22:50:16.050204 Final RX Vref Byte 1 = 60 to rank0
8016 22:50:16.053897 Final RX Vref Byte 0 = 57 to rank1
8017 22:50:16.057037 Final RX Vref Byte 1 = 60 to rank1==
8018 22:50:16.060682 Dram Type= 6, Freq= 0, CH_0, rank 0
8019 22:50:16.063739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 22:50:16.067653 ==
8021 22:50:16.068188 DQS Delay:
8022 22:50:16.068641 DQS0 = 0, DQS1 = 0
8023 22:50:16.070302 DQM Delay:
8024 22:50:16.070733 DQM0 = 128, DQM1 = 122
8025 22:50:16.073961 DQ Delay:
8026 22:50:16.077390 DQ0 =128, DQ1 =132, DQ2 =122, DQ3 =126
8027 22:50:16.080980 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =136
8028 22:50:16.083961 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
8029 22:50:16.087410 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
8030 22:50:16.087945
8031 22:50:16.088391
8032 22:50:16.088796
8033 22:50:16.090541 [DramC_TX_OE_Calibration] TA2
8034 22:50:16.093853 Original DQ_B0 (3 6) =30, OEN = 27
8035 22:50:16.097160 Original DQ_B1 (3 6) =30, OEN = 27
8036 22:50:16.100025 24, 0x0, End_B0=24 End_B1=24
8037 22:50:16.100521 25, 0x0, End_B0=25 End_B1=25
8038 22:50:16.103991 26, 0x0, End_B0=26 End_B1=26
8039 22:50:16.106946 27, 0x0, End_B0=27 End_B1=27
8040 22:50:16.110269 28, 0x0, End_B0=28 End_B1=28
8041 22:50:16.110714 29, 0x0, End_B0=29 End_B1=29
8042 22:50:16.113544 30, 0x0, End_B0=30 End_B1=30
8043 22:50:16.117358 31, 0x4141, End_B0=30 End_B1=30
8044 22:50:16.120103 Byte0 end_step=30 best_step=27
8045 22:50:16.123768 Byte1 end_step=30 best_step=27
8046 22:50:16.127864 Byte0 TX OE(2T, 0.5T) = (3, 3)
8047 22:50:16.128400 Byte1 TX OE(2T, 0.5T) = (3, 3)
8048 22:50:16.128846
8049 22:50:16.130653
8050 22:50:16.137449 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8051 22:50:16.140214 CH0 RK0: MR19=303, MR18=1408
8052 22:50:16.147158 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
8053 22:50:16.147690
8054 22:50:16.150098 ----->DramcWriteLeveling(PI) begin...
8055 22:50:16.150537 ==
8056 22:50:16.153411 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 22:50:16.157920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 22:50:16.158459 ==
8059 22:50:16.160621 Write leveling (Byte 0): 32 => 32
8060 22:50:16.164286 Write leveling (Byte 1): 28 => 28
8061 22:50:16.167448 DramcWriteLeveling(PI) end<-----
8062 22:50:16.167964
8063 22:50:16.168300 ==
8064 22:50:16.170298 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 22:50:16.173560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 22:50:16.174083 ==
8067 22:50:16.177484 [Gating] SW mode calibration
8068 22:50:16.184164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8069 22:50:16.190468 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8070 22:50:16.193870 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 22:50:16.197315 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 22:50:16.204154 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 22:50:16.207249 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8074 22:50:16.211240 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8075 22:50:16.214492 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8076 22:50:16.220410 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8077 22:50:16.224075 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 22:50:16.227180 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 22:50:16.233948 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8080 22:50:16.237383 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8081 22:50:16.240472 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8082 22:50:16.247393 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8083 22:50:16.250398 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8084 22:50:16.253994 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 22:50:16.261244 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 22:50:16.264510 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 22:50:16.267611 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 22:50:16.273645 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8089 22:50:16.276977 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8090 22:50:16.281285 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8091 22:50:16.287314 1 6 20 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8092 22:50:16.290902 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 22:50:16.294180 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 22:50:16.300484 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 22:50:16.303858 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 22:50:16.306894 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 22:50:16.313941 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8098 22:50:16.317650 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8099 22:50:16.320444 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8100 22:50:16.324322 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8101 22:50:16.330043 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 22:50:16.333791 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 22:50:16.337189 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 22:50:16.343436 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 22:50:16.346935 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 22:50:16.350179 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 22:50:16.356994 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 22:50:16.361005 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 22:50:16.363585 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 22:50:16.370522 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 22:50:16.373706 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 22:50:16.376733 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8113 22:50:16.384026 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8114 22:50:16.384450 Total UI for P1: 0, mck2ui 16
8115 22:50:16.390524 best dqsien dly found for B0: ( 1, 9, 8)
8116 22:50:16.393535 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8117 22:50:16.396958 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8118 22:50:16.400074 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 22:50:16.404084 Total UI for P1: 0, mck2ui 16
8120 22:50:16.407564 best dqsien dly found for B1: ( 1, 9, 18)
8121 22:50:16.410669 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8122 22:50:16.417279 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8123 22:50:16.417793
8124 22:50:16.420249 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8125 22:50:16.424115 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8126 22:50:16.427234 [Gating] SW calibration Done
8127 22:50:16.427938 ==
8128 22:50:16.430388 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 22:50:16.433660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 22:50:16.434100 ==
8131 22:50:16.434434 RX Vref Scan: 0
8132 22:50:16.436820
8133 22:50:16.437357 RX Vref 0 -> 0, step: 1
8134 22:50:16.438013
8135 22:50:16.440179 RX Delay 0 -> 252, step: 8
8136 22:50:16.444298 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8137 22:50:16.447758 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8138 22:50:16.453615 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8139 22:50:16.456708 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8140 22:50:16.460737 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8141 22:50:16.463760 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8142 22:50:16.466682 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8143 22:50:16.471010 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8144 22:50:16.476873 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8145 22:50:16.480651 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8146 22:50:16.484394 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8147 22:50:16.486953 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8148 22:50:16.494189 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8149 22:50:16.497184 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8150 22:50:16.501099 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8151 22:50:16.504097 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8152 22:50:16.504624 ==
8153 22:50:16.507184 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 22:50:16.511476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 22:50:16.513931 ==
8156 22:50:16.514349 DQS Delay:
8157 22:50:16.514677 DQS0 = 0, DQS1 = 0
8158 22:50:16.517327 DQM Delay:
8159 22:50:16.517854 DQM0 = 131, DQM1 = 125
8160 22:50:16.521041 DQ Delay:
8161 22:50:16.524327 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8162 22:50:16.527404 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8163 22:50:16.530476 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8164 22:50:16.533667 DQ12 =127, DQ13 =135, DQ14 =135, DQ15 =131
8165 22:50:16.534104
8166 22:50:16.534436
8167 22:50:16.534744 ==
8168 22:50:16.537238 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 22:50:16.541391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 22:50:16.541816 ==
8171 22:50:16.542153
8172 22:50:16.542463
8173 22:50:16.543694 TX Vref Scan disable
8174 22:50:16.547567 == TX Byte 0 ==
8175 22:50:16.550742 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8176 22:50:16.553651 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8177 22:50:16.557374 == TX Byte 1 ==
8178 22:50:16.560761 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8179 22:50:16.563764 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8180 22:50:16.564282 ==
8181 22:50:16.567354 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 22:50:16.573766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 22:50:16.574287 ==
8184 22:50:16.586858
8185 22:50:16.590306 TX Vref early break, caculate TX vref
8186 22:50:16.593276 TX Vref=16, minBit 2, minWin=22, winSum=371
8187 22:50:16.596768 TX Vref=18, minBit 0, minWin=23, winSum=386
8188 22:50:16.599874 TX Vref=20, minBit 1, minWin=22, winSum=385
8189 22:50:16.603493 TX Vref=22, minBit 0, minWin=24, winSum=398
8190 22:50:16.606733 TX Vref=24, minBit 4, minWin=24, winSum=414
8191 22:50:16.614110 TX Vref=26, minBit 0, minWin=25, winSum=420
8192 22:50:16.616939 TX Vref=28, minBit 4, minWin=25, winSum=421
8193 22:50:16.620795 TX Vref=30, minBit 0, minWin=24, winSum=420
8194 22:50:16.623642 TX Vref=32, minBit 0, minWin=25, winSum=414
8195 22:50:16.627110 TX Vref=34, minBit 1, minWin=23, winSum=404
8196 22:50:16.630528 TX Vref=36, minBit 4, minWin=23, winSum=394
8197 22:50:16.636684 [TxChooseVref] Worse bit 4, Min win 25, Win sum 421, Final Vref 28
8198 22:50:16.637245
8199 22:50:16.640302 Final TX Range 0 Vref 28
8200 22:50:16.640838
8201 22:50:16.641177 ==
8202 22:50:16.643386 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 22:50:16.646828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 22:50:16.647380 ==
8205 22:50:16.647726
8206 22:50:16.648035
8207 22:50:16.650554 TX Vref Scan disable
8208 22:50:16.656748 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8209 22:50:16.657301 == TX Byte 0 ==
8210 22:50:16.660088 u2DelayCellOfst[0]=10 cells (3 PI)
8211 22:50:16.663312 u2DelayCellOfst[1]=21 cells (6 PI)
8212 22:50:16.667351 u2DelayCellOfst[2]=10 cells (3 PI)
8213 22:50:16.670318 u2DelayCellOfst[3]=10 cells (3 PI)
8214 22:50:16.674007 u2DelayCellOfst[4]=7 cells (2 PI)
8215 22:50:16.676796 u2DelayCellOfst[5]=0 cells (0 PI)
8216 22:50:16.680878 u2DelayCellOfst[6]=21 cells (6 PI)
8217 22:50:16.683964 u2DelayCellOfst[7]=17 cells (5 PI)
8218 22:50:16.687073 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8219 22:50:16.690605 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8220 22:50:16.693599 == TX Byte 1 ==
8221 22:50:16.694125 u2DelayCellOfst[8]=0 cells (0 PI)
8222 22:50:16.697108 u2DelayCellOfst[9]=0 cells (0 PI)
8223 22:50:16.700645 u2DelayCellOfst[10]=10 cells (3 PI)
8224 22:50:16.703581 u2DelayCellOfst[11]=3 cells (1 PI)
8225 22:50:16.707103 u2DelayCellOfst[12]=10 cells (3 PI)
8226 22:50:16.710882 u2DelayCellOfst[13]=14 cells (4 PI)
8227 22:50:16.714098 u2DelayCellOfst[14]=17 cells (5 PI)
8228 22:50:16.717059 u2DelayCellOfst[15]=10 cells (3 PI)
8229 22:50:16.720621 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8230 22:50:16.723632 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8231 22:50:16.727001 DramC Write-DBI on
8232 22:50:16.727420 ==
8233 22:50:16.730394 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 22:50:16.733820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 22:50:16.734245 ==
8236 22:50:16.734630
8237 22:50:16.736850
8238 22:50:16.737310 TX Vref Scan disable
8239 22:50:16.740003 == TX Byte 0 ==
8240 22:50:16.744683 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8241 22:50:16.747090 == TX Byte 1 ==
8242 22:50:16.750335 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8243 22:50:16.750890 DramC Write-DBI off
8244 22:50:16.751237
8245 22:50:16.753511 [DATLAT]
8246 22:50:16.753924 Freq=1600, CH0 RK1
8247 22:50:16.754256
8248 22:50:16.756676 DATLAT Default: 0xf
8249 22:50:16.757094 0, 0xFFFF, sum = 0
8250 22:50:16.760369 1, 0xFFFF, sum = 0
8251 22:50:16.760794 2, 0xFFFF, sum = 0
8252 22:50:16.764237 3, 0xFFFF, sum = 0
8253 22:50:16.764761 4, 0xFFFF, sum = 0
8254 22:50:16.767498 5, 0xFFFF, sum = 0
8255 22:50:16.767921 6, 0xFFFF, sum = 0
8256 22:50:16.770153 7, 0xFFFF, sum = 0
8257 22:50:16.770576 8, 0xFFFF, sum = 0
8258 22:50:16.773822 9, 0xFFFF, sum = 0
8259 22:50:16.777148 10, 0xFFFF, sum = 0
8260 22:50:16.777617 11, 0xFFFF, sum = 0
8261 22:50:16.780242 12, 0xFFFF, sum = 0
8262 22:50:16.780678 13, 0xFFFF, sum = 0
8263 22:50:16.783558 14, 0x0, sum = 1
8264 22:50:16.783988 15, 0x0, sum = 2
8265 22:50:16.786808 16, 0x0, sum = 3
8266 22:50:16.787329 17, 0x0, sum = 4
8267 22:50:16.787763 best_step = 15
8268 22:50:16.788089
8269 22:50:16.790364 ==
8270 22:50:16.793647 Dram Type= 6, Freq= 0, CH_0, rank 1
8271 22:50:16.797056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 22:50:16.797623 ==
8273 22:50:16.798108 RX Vref Scan: 0
8274 22:50:16.798449
8275 22:50:16.800057 RX Vref 0 -> 0, step: 1
8276 22:50:16.800637
8277 22:50:16.803686 RX Delay 11 -> 252, step: 4
8278 22:50:16.807449 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8279 22:50:16.810310 iDelay=191, Bit 1, Center 128 (71 ~ 186) 116
8280 22:50:16.817525 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8281 22:50:16.820933 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8282 22:50:16.824408 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8283 22:50:16.827718 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8284 22:50:16.830872 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8285 22:50:16.837073 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8286 22:50:16.840571 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8287 22:50:16.843879 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8288 22:50:16.847242 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8289 22:50:16.850546 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8290 22:50:16.857204 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8291 22:50:16.860552 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8292 22:50:16.864466 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8293 22:50:16.867454 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8294 22:50:16.867975 ==
8295 22:50:16.870468 Dram Type= 6, Freq= 0, CH_0, rank 1
8296 22:50:16.874135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 22:50:16.877675 ==
8298 22:50:16.878201 DQS Delay:
8299 22:50:16.878537 DQS0 = 0, DQS1 = 0
8300 22:50:16.881434 DQM Delay:
8301 22:50:16.881950 DQM0 = 126, DQM1 = 122
8302 22:50:16.884571 DQ Delay:
8303 22:50:16.887611 DQ0 =126, DQ1 =128, DQ2 =122, DQ3 =126
8304 22:50:16.890416 DQ4 =124, DQ5 =116, DQ6 =134, DQ7 =134
8305 22:50:16.894503 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
8306 22:50:16.897159 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8307 22:50:16.897616
8308 22:50:16.897949
8309 22:50:16.898256
8310 22:50:16.900585 [DramC_TX_OE_Calibration] TA2
8311 22:50:16.904116 Original DQ_B0 (3 6) =30, OEN = 27
8312 22:50:16.907487 Original DQ_B1 (3 6) =30, OEN = 27
8313 22:50:16.910659 24, 0x0, End_B0=24 End_B1=24
8314 22:50:16.911185 25, 0x0, End_B0=25 End_B1=25
8315 22:50:16.913650 26, 0x0, End_B0=26 End_B1=26
8316 22:50:16.917055 27, 0x0, End_B0=27 End_B1=27
8317 22:50:16.920853 28, 0x0, End_B0=28 End_B1=28
8318 22:50:16.921434 29, 0x0, End_B0=29 End_B1=29
8319 22:50:16.924280 30, 0x0, End_B0=30 End_B1=30
8320 22:50:16.927204 31, 0x4141, End_B0=30 End_B1=30
8321 22:50:16.930683 Byte0 end_step=30 best_step=27
8322 22:50:16.934088 Byte1 end_step=30 best_step=27
8323 22:50:16.937603 Byte0 TX OE(2T, 0.5T) = (3, 3)
8324 22:50:16.938128 Byte1 TX OE(2T, 0.5T) = (3, 3)
8325 22:50:16.938525
8326 22:50:16.938857
8327 22:50:16.947157 [DQSOSCAuto] RK1, (LSB)MR18= 0x180c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8328 22:50:16.950834 CH0 RK1: MR19=303, MR18=180C
8329 22:50:16.953853 CH0_RK1: MR19=0x303, MR18=0x180C, DQSOSC=397, MR23=63, INC=23, DEC=15
8330 22:50:16.957191 [RxdqsGatingPostProcess] freq 1600
8331 22:50:16.964489 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8332 22:50:16.967208 best DQS0 dly(2T, 0.5T) = (1, 1)
8333 22:50:16.970703 best DQS1 dly(2T, 0.5T) = (1, 1)
8334 22:50:16.974625 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8335 22:50:16.977645 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8336 22:50:16.980758 best DQS0 dly(2T, 0.5T) = (1, 1)
8337 22:50:16.981380 best DQS1 dly(2T, 0.5T) = (1, 1)
8338 22:50:16.984226 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8339 22:50:16.987732 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8340 22:50:16.991066 Pre-setting of DQS Precalculation
8341 22:50:16.997692 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8342 22:50:16.998229 ==
8343 22:50:17.001513 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 22:50:17.004297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 22:50:17.004824 ==
8346 22:50:17.011216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8347 22:50:17.015156 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8348 22:50:17.017382 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8349 22:50:17.024396 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8350 22:50:17.033148 [CA 0] Center 43 (14~72) winsize 59
8351 22:50:17.036576 [CA 1] Center 43 (14~72) winsize 59
8352 22:50:17.040098 [CA 2] Center 39 (11~67) winsize 57
8353 22:50:17.043341 [CA 3] Center 37 (8~66) winsize 59
8354 22:50:17.046739 [CA 4] Center 38 (9~68) winsize 60
8355 22:50:17.050177 [CA 5] Center 37 (8~66) winsize 59
8356 22:50:17.050705
8357 22:50:17.053892 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8358 22:50:17.054418
8359 22:50:17.056376 [CATrainingPosCal] consider 1 rank data
8360 22:50:17.059691 u2DelayCellTimex100 = 275/100 ps
8361 22:50:17.063589 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8362 22:50:17.069712 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8363 22:50:17.072875 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8364 22:50:17.076593 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8365 22:50:17.080654 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8366 22:50:17.083784 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8367 22:50:17.084303
8368 22:50:17.086715 CA PerBit enable=1, Macro0, CA PI delay=37
8369 22:50:17.087141
8370 22:50:17.089762 [CBTSetCACLKResult] CA Dly = 37
8371 22:50:17.090307 CS Dly: 8 (0~39)
8372 22:50:17.096872 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8373 22:50:17.100230 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8374 22:50:17.100653 ==
8375 22:50:17.103332 Dram Type= 6, Freq= 0, CH_1, rank 1
8376 22:50:17.106479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 22:50:17.106902 ==
8378 22:50:17.113657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8379 22:50:17.116894 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8380 22:50:17.120303 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8381 22:50:17.126910 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8382 22:50:17.136393 [CA 0] Center 43 (14~72) winsize 59
8383 22:50:17.140124 [CA 1] Center 43 (14~72) winsize 59
8384 22:50:17.142878 [CA 2] Center 37 (8~67) winsize 60
8385 22:50:17.146453 [CA 3] Center 37 (8~66) winsize 59
8386 22:50:17.150160 [CA 4] Center 37 (8~67) winsize 60
8387 22:50:17.153190 [CA 5] Center 36 (7~66) winsize 60
8388 22:50:17.153746
8389 22:50:17.156598 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8390 22:50:17.157094
8391 22:50:17.159923 [CATrainingPosCal] consider 2 rank data
8392 22:50:17.163460 u2DelayCellTimex100 = 275/100 ps
8393 22:50:17.166498 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8394 22:50:17.173466 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8395 22:50:17.176713 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8396 22:50:17.179962 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8397 22:50:17.183514 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8398 22:50:17.186497 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8399 22:50:17.186918
8400 22:50:17.189814 CA PerBit enable=1, Macro0, CA PI delay=37
8401 22:50:17.190380
8402 22:50:17.193681 [CBTSetCACLKResult] CA Dly = 37
8403 22:50:17.196452 CS Dly: 11 (0~45)
8404 22:50:17.199933 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8405 22:50:17.203188 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8406 22:50:17.203622
8407 22:50:17.206406 ----->DramcWriteLeveling(PI) begin...
8408 22:50:17.206932 ==
8409 22:50:17.210333 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 22:50:17.213833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 22:50:17.214360 ==
8412 22:50:17.217264 Write leveling (Byte 0): 26 => 26
8413 22:50:17.219985 Write leveling (Byte 1): 28 => 28
8414 22:50:17.223082 DramcWriteLeveling(PI) end<-----
8415 22:50:17.223502
8416 22:50:17.223832 ==
8417 22:50:17.227261 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 22:50:17.230120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 22:50:17.233702 ==
8420 22:50:17.234224 [Gating] SW mode calibration
8421 22:50:17.243471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8422 22:50:17.246549 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8423 22:50:17.250236 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 22:50:17.256953 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 22:50:17.260603 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 22:50:17.263164 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 22:50:17.270150 1 4 16 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
8428 22:50:17.273894 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 22:50:17.276624 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 22:50:17.283783 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 22:50:17.286914 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 22:50:17.290004 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 22:50:17.296715 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 22:50:17.299766 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8435 22:50:17.302908 1 5 16 | B1->B0 | 2b2b 3030 | 0 0 | (0 0) (1 0)
8436 22:50:17.310249 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 22:50:17.313629 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 22:50:17.316720 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 22:50:17.323503 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 22:50:17.326498 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 22:50:17.330237 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 22:50:17.332814 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 22:50:17.339548 1 6 16 | B1->B0 | 3636 2d2d | 0 0 | (0 0) (1 1)
8444 22:50:17.343418 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 22:50:17.346980 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 22:50:17.353791 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 22:50:17.356607 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 22:50:17.360328 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 22:50:17.366887 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 22:50:17.370176 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8451 22:50:17.373461 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8452 22:50:17.379970 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8453 22:50:17.383503 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 22:50:17.386479 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 22:50:17.393091 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 22:50:17.396625 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 22:50:17.399969 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 22:50:17.406093 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 22:50:17.410050 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 22:50:17.413387 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 22:50:17.417046 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 22:50:17.423260 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 22:50:17.426658 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 22:50:17.430143 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 22:50:17.436672 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 22:50:17.440099 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8467 22:50:17.443139 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8468 22:50:17.450295 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8469 22:50:17.453698 Total UI for P1: 0, mck2ui 16
8470 22:50:17.456736 best dqsien dly found for B0: ( 1, 9, 16)
8471 22:50:17.459791 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 22:50:17.463559 Total UI for P1: 0, mck2ui 16
8473 22:50:17.466702 best dqsien dly found for B1: ( 1, 9, 16)
8474 22:50:17.470377 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8475 22:50:17.473358 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8476 22:50:17.473884
8477 22:50:17.476604 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8478 22:50:17.479882 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8479 22:50:17.483212 [Gating] SW calibration Done
8480 22:50:17.483754 ==
8481 22:50:17.486448 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 22:50:17.492927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 22:50:17.493378 ==
8484 22:50:17.493718 RX Vref Scan: 0
8485 22:50:17.494088
8486 22:50:17.496572 RX Vref 0 -> 0, step: 1
8487 22:50:17.496988
8488 22:50:17.499645 RX Delay 0 -> 252, step: 8
8489 22:50:17.503027 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8490 22:50:17.506151 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8491 22:50:17.509671 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8492 22:50:17.513240 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8493 22:50:17.519793 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8494 22:50:17.523640 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8495 22:50:17.526347 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8496 22:50:17.530124 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8497 22:50:17.533292 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8498 22:50:17.536515 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8499 22:50:17.543703 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8500 22:50:17.546406 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8501 22:50:17.549648 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8502 22:50:17.553319 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8503 22:50:17.560065 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8504 22:50:17.563331 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8505 22:50:17.563750 ==
8506 22:50:17.566970 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 22:50:17.569700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 22:50:17.570134 ==
8509 22:50:17.570662 DQS Delay:
8510 22:50:17.573085 DQS0 = 0, DQS1 = 0
8511 22:50:17.573534 DQM Delay:
8512 22:50:17.576266 DQM0 = 134, DQM1 = 127
8513 22:50:17.576682 DQ Delay:
8514 22:50:17.579953 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8515 22:50:17.583696 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8516 22:50:17.586289 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8517 22:50:17.590034 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8518 22:50:17.593368
8519 22:50:17.593882
8520 22:50:17.594225 ==
8521 22:50:17.596636 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 22:50:17.599514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 22:50:17.599938 ==
8524 22:50:17.600359
8525 22:50:17.600676
8526 22:50:17.603220 TX Vref Scan disable
8527 22:50:17.603642 == TX Byte 0 ==
8528 22:50:17.609985 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8529 22:50:17.613443 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8530 22:50:17.613974 == TX Byte 1 ==
8531 22:50:17.619969 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8532 22:50:17.623470 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8533 22:50:17.624002 ==
8534 22:50:17.626815 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 22:50:17.629807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 22:50:17.630341 ==
8537 22:50:17.644611
8538 22:50:17.647069 TX Vref early break, caculate TX vref
8539 22:50:17.650454 TX Vref=16, minBit 8, minWin=20, winSum=362
8540 22:50:17.654651 TX Vref=18, minBit 8, minWin=21, winSum=373
8541 22:50:17.657271 TX Vref=20, minBit 8, minWin=22, winSum=379
8542 22:50:17.660576 TX Vref=22, minBit 8, minWin=22, winSum=389
8543 22:50:17.663890 TX Vref=24, minBit 8, minWin=23, winSum=400
8544 22:50:17.670372 TX Vref=26, minBit 8, minWin=24, winSum=411
8545 22:50:17.674544 TX Vref=28, minBit 9, minWin=25, winSum=417
8546 22:50:17.677333 TX Vref=30, minBit 1, minWin=25, winSum=417
8547 22:50:17.680467 TX Vref=32, minBit 0, minWin=24, winSum=406
8548 22:50:17.684337 TX Vref=34, minBit 8, minWin=23, winSum=397
8549 22:50:17.687353 TX Vref=36, minBit 8, minWin=23, winSum=389
8550 22:50:17.693883 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 28
8551 22:50:17.694302
8552 22:50:17.697485 Final TX Range 0 Vref 28
8553 22:50:17.697904
8554 22:50:17.698232 ==
8555 22:50:17.700866 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 22:50:17.704553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 22:50:17.705083 ==
8558 22:50:17.705482
8559 22:50:17.705795
8560 22:50:17.707126 TX Vref Scan disable
8561 22:50:17.714583 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8562 22:50:17.715179 == TX Byte 0 ==
8563 22:50:17.717726 u2DelayCellOfst[0]=14 cells (4 PI)
8564 22:50:17.720552 u2DelayCellOfst[1]=10 cells (3 PI)
8565 22:50:17.724383 u2DelayCellOfst[2]=0 cells (0 PI)
8566 22:50:17.727216 u2DelayCellOfst[3]=7 cells (2 PI)
8567 22:50:17.730295 u2DelayCellOfst[4]=7 cells (2 PI)
8568 22:50:17.733930 u2DelayCellOfst[5]=17 cells (5 PI)
8569 22:50:17.737446 u2DelayCellOfst[6]=17 cells (5 PI)
8570 22:50:17.740799 u2DelayCellOfst[7]=7 cells (2 PI)
8571 22:50:17.743953 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8572 22:50:17.747153 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8573 22:50:17.750754 == TX Byte 1 ==
8574 22:50:17.751280 u2DelayCellOfst[8]=0 cells (0 PI)
8575 22:50:17.753675 u2DelayCellOfst[9]=7 cells (2 PI)
8576 22:50:17.757312 u2DelayCellOfst[10]=10 cells (3 PI)
8577 22:50:17.760461 u2DelayCellOfst[11]=7 cells (2 PI)
8578 22:50:17.764244 u2DelayCellOfst[12]=14 cells (4 PI)
8579 22:50:17.767615 u2DelayCellOfst[13]=17 cells (5 PI)
8580 22:50:17.770675 u2DelayCellOfst[14]=17 cells (5 PI)
8581 22:50:17.774052 u2DelayCellOfst[15]=17 cells (5 PI)
8582 22:50:17.777635 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8583 22:50:17.784199 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8584 22:50:17.784736 DramC Write-DBI on
8585 22:50:17.785082 ==
8586 22:50:17.787081 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 22:50:17.790702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 22:50:17.791125 ==
8589 22:50:17.793981
8590 22:50:17.794400
8591 22:50:17.794732 TX Vref Scan disable
8592 22:50:17.797595 == TX Byte 0 ==
8593 22:50:17.800259 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8594 22:50:17.803880 == TX Byte 1 ==
8595 22:50:17.807304 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8596 22:50:17.807821 DramC Write-DBI off
8597 22:50:17.810289
8598 22:50:17.810856 [DATLAT]
8599 22:50:17.811209 Freq=1600, CH1 RK0
8600 22:50:17.811526
8601 22:50:17.814140 DATLAT Default: 0xf
8602 22:50:17.814661 0, 0xFFFF, sum = 0
8603 22:50:17.817310 1, 0xFFFF, sum = 0
8604 22:50:17.817741 2, 0xFFFF, sum = 0
8605 22:50:17.821358 3, 0xFFFF, sum = 0
8606 22:50:17.821886 4, 0xFFFF, sum = 0
8607 22:50:17.823954 5, 0xFFFF, sum = 0
8608 22:50:17.827312 6, 0xFFFF, sum = 0
8609 22:50:17.827829 7, 0xFFFF, sum = 0
8610 22:50:17.830553 8, 0xFFFF, sum = 0
8611 22:50:17.830986 9, 0xFFFF, sum = 0
8612 22:50:17.833906 10, 0xFFFF, sum = 0
8613 22:50:17.834425 11, 0xFFFF, sum = 0
8614 22:50:17.837900 12, 0xFFFF, sum = 0
8615 22:50:17.838423 13, 0xFFFF, sum = 0
8616 22:50:17.840833 14, 0x0, sum = 1
8617 22:50:17.841291 15, 0x0, sum = 2
8618 22:50:17.844512 16, 0x0, sum = 3
8619 22:50:17.845032 17, 0x0, sum = 4
8620 22:50:17.845512 best_step = 15
8621 22:50:17.847189
8622 22:50:17.847607 ==
8623 22:50:17.851052 Dram Type= 6, Freq= 0, CH_1, rank 0
8624 22:50:17.854055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8625 22:50:17.854571 ==
8626 22:50:17.854914 RX Vref Scan: 1
8627 22:50:17.855225
8628 22:50:17.857043 Set Vref Range= 24 -> 127
8629 22:50:17.857499
8630 22:50:17.861283 RX Vref 24 -> 127, step: 1
8631 22:50:17.861707
8632 22:50:17.864372 RX Delay 19 -> 252, step: 4
8633 22:50:17.864883
8634 22:50:17.867244 Set Vref, RX VrefLevel [Byte0]: 24
8635 22:50:17.871137 [Byte1]: 24
8636 22:50:17.871568
8637 22:50:17.873678 Set Vref, RX VrefLevel [Byte0]: 25
8638 22:50:17.877872 [Byte1]: 25
8639 22:50:17.878392
8640 22:50:17.880365 Set Vref, RX VrefLevel [Byte0]: 26
8641 22:50:17.883737 [Byte1]: 26
8642 22:50:17.887232
8643 22:50:17.887657 Set Vref, RX VrefLevel [Byte0]: 27
8644 22:50:17.890450 [Byte1]: 27
8645 22:50:17.895334
8646 22:50:17.895845 Set Vref, RX VrefLevel [Byte0]: 28
8647 22:50:17.898057 [Byte1]: 28
8648 22:50:17.902418
8649 22:50:17.903039 Set Vref, RX VrefLevel [Byte0]: 29
8650 22:50:17.906465 [Byte1]: 29
8651 22:50:17.909732
8652 22:50:17.910329 Set Vref, RX VrefLevel [Byte0]: 30
8653 22:50:17.913194 [Byte1]: 30
8654 22:50:17.917573
8655 22:50:17.917985 Set Vref, RX VrefLevel [Byte0]: 31
8656 22:50:17.921047 [Byte1]: 31
8657 22:50:17.925158
8658 22:50:17.928027 Set Vref, RX VrefLevel [Byte0]: 32
8659 22:50:17.931783 [Byte1]: 32
8660 22:50:17.932329
8661 22:50:17.935256 Set Vref, RX VrefLevel [Byte0]: 33
8662 22:50:17.938407 [Byte1]: 33
8663 22:50:17.938823
8664 22:50:17.941739 Set Vref, RX VrefLevel [Byte0]: 34
8665 22:50:17.945026 [Byte1]: 34
8666 22:50:17.945577
8667 22:50:17.948455 Set Vref, RX VrefLevel [Byte0]: 35
8668 22:50:17.951908 [Byte1]: 35
8669 22:50:17.955745
8670 22:50:17.956362 Set Vref, RX VrefLevel [Byte0]: 36
8671 22:50:17.958636 [Byte1]: 36
8672 22:50:17.963316
8673 22:50:17.963888 Set Vref, RX VrefLevel [Byte0]: 37
8674 22:50:17.966341 [Byte1]: 37
8675 22:50:17.970479
8676 22:50:17.970991 Set Vref, RX VrefLevel [Byte0]: 38
8677 22:50:17.973976 [Byte1]: 38
8678 22:50:17.978227
8679 22:50:17.978642 Set Vref, RX VrefLevel [Byte0]: 39
8680 22:50:17.981648 [Byte1]: 39
8681 22:50:17.985719
8682 22:50:17.986140 Set Vref, RX VrefLevel [Byte0]: 40
8683 22:50:17.988958 [Byte1]: 40
8684 22:50:17.993696
8685 22:50:17.994112 Set Vref, RX VrefLevel [Byte0]: 41
8686 22:50:17.996880 [Byte1]: 41
8687 22:50:18.001310
8688 22:50:18.001725 Set Vref, RX VrefLevel [Byte0]: 42
8689 22:50:18.004415 [Byte1]: 42
8690 22:50:18.008694
8691 22:50:18.009276 Set Vref, RX VrefLevel [Byte0]: 43
8692 22:50:18.011811 [Byte1]: 43
8693 22:50:18.015874
8694 22:50:18.016536 Set Vref, RX VrefLevel [Byte0]: 44
8695 22:50:18.019408 [Byte1]: 44
8696 22:50:18.023880
8697 22:50:18.024335 Set Vref, RX VrefLevel [Byte0]: 45
8698 22:50:18.026973 [Byte1]: 45
8699 22:50:18.031135
8700 22:50:18.031612 Set Vref, RX VrefLevel [Byte0]: 46
8701 22:50:18.034566 [Byte1]: 46
8702 22:50:18.039020
8703 22:50:18.039586 Set Vref, RX VrefLevel [Byte0]: 47
8704 22:50:18.042509 [Byte1]: 47
8705 22:50:18.046280
8706 22:50:18.046691 Set Vref, RX VrefLevel [Byte0]: 48
8707 22:50:18.049571 [Byte1]: 48
8708 22:50:18.053842
8709 22:50:18.054251 Set Vref, RX VrefLevel [Byte0]: 49
8710 22:50:18.057345 [Byte1]: 49
8711 22:50:18.061250
8712 22:50:18.061682 Set Vref, RX VrefLevel [Byte0]: 50
8713 22:50:18.064630 [Byte1]: 50
8714 22:50:18.069020
8715 22:50:18.069489 Set Vref, RX VrefLevel [Byte0]: 51
8716 22:50:18.072907 [Byte1]: 51
8717 22:50:18.076918
8718 22:50:18.077502 Set Vref, RX VrefLevel [Byte0]: 52
8719 22:50:18.080165 [Byte1]: 52
8720 22:50:18.085048
8721 22:50:18.085707 Set Vref, RX VrefLevel [Byte0]: 53
8722 22:50:18.088034 [Byte1]: 53
8723 22:50:18.091584
8724 22:50:18.092034 Set Vref, RX VrefLevel [Byte0]: 54
8725 22:50:18.094896 [Byte1]: 54
8726 22:50:18.099756
8727 22:50:18.100167 Set Vref, RX VrefLevel [Byte0]: 55
8728 22:50:18.102930 [Byte1]: 55
8729 22:50:18.107533
8730 22:50:18.108051 Set Vref, RX VrefLevel [Byte0]: 56
8731 22:50:18.109938 [Byte1]: 56
8732 22:50:18.115758
8733 22:50:18.116447 Set Vref, RX VrefLevel [Byte0]: 57
8734 22:50:18.117501 [Byte1]: 57
8735 22:50:18.122210
8736 22:50:18.122812 Set Vref, RX VrefLevel [Byte0]: 58
8737 22:50:18.125579 [Byte1]: 58
8738 22:50:18.130162
8739 22:50:18.130681 Set Vref, RX VrefLevel [Byte0]: 59
8740 22:50:18.133102 [Byte1]: 59
8741 22:50:18.137573
8742 22:50:18.138155 Set Vref, RX VrefLevel [Byte0]: 60
8743 22:50:18.140535 [Byte1]: 60
8744 22:50:18.145376
8745 22:50:18.145892 Set Vref, RX VrefLevel [Byte0]: 61
8746 22:50:18.147895 [Byte1]: 61
8747 22:50:18.152691
8748 22:50:18.153256 Set Vref, RX VrefLevel [Byte0]: 62
8749 22:50:18.156211 [Byte1]: 62
8750 22:50:18.160232
8751 22:50:18.160746 Set Vref, RX VrefLevel [Byte0]: 63
8752 22:50:18.163309 [Byte1]: 63
8753 22:50:18.167615
8754 22:50:18.168129 Set Vref, RX VrefLevel [Byte0]: 64
8755 22:50:18.171196 [Byte1]: 64
8756 22:50:18.175705
8757 22:50:18.176221 Set Vref, RX VrefLevel [Byte0]: 65
8758 22:50:18.178520 [Byte1]: 65
8759 22:50:18.183010
8760 22:50:18.183535 Set Vref, RX VrefLevel [Byte0]: 66
8761 22:50:18.185968 [Byte1]: 66
8762 22:50:18.190035
8763 22:50:18.190459 Set Vref, RX VrefLevel [Byte0]: 67
8764 22:50:18.193517 [Byte1]: 67
8765 22:50:18.198738
8766 22:50:18.199263 Set Vref, RX VrefLevel [Byte0]: 68
8767 22:50:18.201357 [Byte1]: 68
8768 22:50:18.205662
8769 22:50:18.206181 Set Vref, RX VrefLevel [Byte0]: 69
8770 22:50:18.208816 [Byte1]: 69
8771 22:50:18.213029
8772 22:50:18.213579 Set Vref, RX VrefLevel [Byte0]: 70
8773 22:50:18.216613 [Byte1]: 70
8774 22:50:18.220749
8775 22:50:18.221283 Set Vref, RX VrefLevel [Byte0]: 71
8776 22:50:18.224751 [Byte1]: 71
8777 22:50:18.228702
8778 22:50:18.229255 Set Vref, RX VrefLevel [Byte0]: 72
8779 22:50:18.231410 [Byte1]: 72
8780 22:50:18.235942
8781 22:50:18.236357 Set Vref, RX VrefLevel [Byte0]: 73
8782 22:50:18.238934 [Byte1]: 73
8783 22:50:18.243054
8784 22:50:18.243473 Set Vref, RX VrefLevel [Byte0]: 74
8785 22:50:18.246439 [Byte1]: 74
8786 22:50:18.250798
8787 22:50:18.251212 Final RX Vref Byte 0 = 62 to rank0
8788 22:50:18.254002 Final RX Vref Byte 1 = 55 to rank0
8789 22:50:18.257511 Final RX Vref Byte 0 = 62 to rank1
8790 22:50:18.260667 Final RX Vref Byte 1 = 55 to rank1==
8791 22:50:18.264058 Dram Type= 6, Freq= 0, CH_1, rank 0
8792 22:50:18.270899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 22:50:18.271314 ==
8794 22:50:18.271638 DQS Delay:
8795 22:50:18.271940 DQS0 = 0, DQS1 = 0
8796 22:50:18.273909 DQM Delay:
8797 22:50:18.274322 DQM0 = 131, DQM1 = 124
8798 22:50:18.277708 DQ Delay:
8799 22:50:18.280997 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8800 22:50:18.284049 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8801 22:50:18.287474 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8802 22:50:18.290891 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8803 22:50:18.291318
8804 22:50:18.291663
8805 22:50:18.291993
8806 22:50:18.294093 [DramC_TX_OE_Calibration] TA2
8807 22:50:18.297322 Original DQ_B0 (3 6) =30, OEN = 27
8808 22:50:18.300776 Original DQ_B1 (3 6) =30, OEN = 27
8809 22:50:18.303760 24, 0x0, End_B0=24 End_B1=24
8810 22:50:18.304264 25, 0x0, End_B0=25 End_B1=25
8811 22:50:18.306887 26, 0x0, End_B0=26 End_B1=26
8812 22:50:18.310532 27, 0x0, End_B0=27 End_B1=27
8813 22:50:18.314031 28, 0x0, End_B0=28 End_B1=28
8814 22:50:18.314472 29, 0x0, End_B0=29 End_B1=29
8815 22:50:18.317249 30, 0x0, End_B0=30 End_B1=30
8816 22:50:18.320882 31, 0x4141, End_B0=30 End_B1=30
8817 22:50:18.323696 Byte0 end_step=30 best_step=27
8818 22:50:18.327156 Byte1 end_step=30 best_step=27
8819 22:50:18.330771 Byte0 TX OE(2T, 0.5T) = (3, 3)
8820 22:50:18.331187 Byte1 TX OE(2T, 0.5T) = (3, 3)
8821 22:50:18.333745
8822 22:50:18.334155
8823 22:50:18.340416 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fc, (MSB)MR19= 0x302, tDQSOscB0 = 412 ps tDQSOscB1 = 400 ps
8824 22:50:18.344010 CH1 RK0: MR19=302, MR18=12FC
8825 22:50:18.350159 CH1_RK0: MR19=0x302, MR18=0x12FC, DQSOSC=400, MR23=63, INC=23, DEC=15
8826 22:50:18.350582
8827 22:50:18.353680 ----->DramcWriteLeveling(PI) begin...
8828 22:50:18.354129 ==
8829 22:50:18.357205 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 22:50:18.360396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 22:50:18.360939 ==
8832 22:50:18.364009 Write leveling (Byte 0): 25 => 25
8833 22:50:18.367383 Write leveling (Byte 1): 26 => 26
8834 22:50:18.370624 DramcWriteLeveling(PI) end<-----
8835 22:50:18.371183
8836 22:50:18.371593 ==
8837 22:50:18.373742 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 22:50:18.377416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 22:50:18.377837 ==
8840 22:50:18.380280 [Gating] SW mode calibration
8841 22:50:18.387566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8842 22:50:18.393886 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8843 22:50:18.397251 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 22:50:18.400647 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 22:50:18.407240 1 4 8 | B1->B0 | 2322 2a2a | 1 0 | (0 0) (0 0)
8846 22:50:18.410472 1 4 12 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
8847 22:50:18.414048 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 22:50:18.420760 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 22:50:18.423870 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 22:50:18.427362 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 22:50:18.433939 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 22:50:18.437148 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8853 22:50:18.441330 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8854 22:50:18.447198 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8855 22:50:18.450361 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 22:50:18.453852 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 22:50:18.457019 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 22:50:18.463981 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 22:50:18.467591 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 22:50:18.470722 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 22:50:18.477546 1 6 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
8862 22:50:18.480557 1 6 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8863 22:50:18.483739 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 22:50:18.490617 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 22:50:18.493558 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 22:50:18.497111 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 22:50:18.504293 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 22:50:18.507544 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8869 22:50:18.510778 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8870 22:50:18.517567 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8871 22:50:18.520958 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 22:50:18.523931 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 22:50:18.530504 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 22:50:18.534368 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 22:50:18.537432 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 22:50:18.544245 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 22:50:18.547905 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 22:50:18.550829 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 22:50:18.554086 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 22:50:18.560548 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 22:50:18.563809 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 22:50:18.567941 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 22:50:18.573711 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 22:50:18.576960 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 22:50:18.580365 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8886 22:50:18.587069 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8887 22:50:18.590643 Total UI for P1: 0, mck2ui 16
8888 22:50:18.593946 best dqsien dly found for B0: ( 1, 9, 8)
8889 22:50:18.597132 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8890 22:50:18.600472 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 22:50:18.604429 Total UI for P1: 0, mck2ui 16
8892 22:50:18.607384 best dqsien dly found for B1: ( 1, 9, 12)
8893 22:50:18.610494 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8894 22:50:18.613972 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8895 22:50:18.614410
8896 22:50:18.620155 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8897 22:50:18.624011 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8898 22:50:18.624436 [Gating] SW calibration Done
8899 22:50:18.627246 ==
8900 22:50:18.630401 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 22:50:18.634089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 22:50:18.634672 ==
8903 22:50:18.635023 RX Vref Scan: 0
8904 22:50:18.635337
8905 22:50:18.637483 RX Vref 0 -> 0, step: 1
8906 22:50:18.637923
8907 22:50:18.640316 RX Delay 0 -> 252, step: 8
8908 22:50:18.643764 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8909 22:50:18.647135 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8910 22:50:18.650366 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8911 22:50:18.656998 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8912 22:50:18.660379 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8913 22:50:18.663925 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8914 22:50:18.667223 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8915 22:50:18.670361 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8916 22:50:18.674026 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8917 22:50:18.680968 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8918 22:50:18.684098 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8919 22:50:18.687141 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8920 22:50:18.690322 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8921 22:50:18.697777 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8922 22:50:18.700566 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8923 22:50:18.704132 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8924 22:50:18.704579 ==
8925 22:50:18.707045 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 22:50:18.710591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 22:50:18.711014 ==
8928 22:50:18.713890 DQS Delay:
8929 22:50:18.714314 DQS0 = 0, DQS1 = 0
8930 22:50:18.717397 DQM Delay:
8931 22:50:18.717842 DQM0 = 132, DQM1 = 127
8932 22:50:18.718184 DQ Delay:
8933 22:50:18.720888 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8934 22:50:18.723846 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8935 22:50:18.730708 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8936 22:50:18.734328 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8937 22:50:18.734794
8938 22:50:18.735434
8939 22:50:18.735852 ==
8940 22:50:18.737744 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 22:50:18.740681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 22:50:18.741104 ==
8943 22:50:18.741478
8944 22:50:18.741793
8945 22:50:18.744170 TX Vref Scan disable
8946 22:50:18.744590 == TX Byte 0 ==
8947 22:50:18.750852 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8948 22:50:18.754777 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8949 22:50:18.755309 == TX Byte 1 ==
8950 22:50:18.760996 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8951 22:50:18.764286 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8952 22:50:18.764916 ==
8953 22:50:18.768078 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 22:50:18.771207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 22:50:18.771631 ==
8956 22:50:18.784598
8957 22:50:18.788012 TX Vref early break, caculate TX vref
8958 22:50:18.791601 TX Vref=16, minBit 0, minWin=23, winSum=383
8959 22:50:18.794512 TX Vref=18, minBit 8, minWin=23, winSum=391
8960 22:50:18.797845 TX Vref=20, minBit 9, minWin=24, winSum=402
8961 22:50:18.801024 TX Vref=22, minBit 1, minWin=25, winSum=412
8962 22:50:18.804752 TX Vref=24, minBit 0, minWin=25, winSum=415
8963 22:50:18.811114 TX Vref=26, minBit 8, minWin=25, winSum=424
8964 22:50:18.814613 TX Vref=28, minBit 5, minWin=26, winSum=431
8965 22:50:18.817667 TX Vref=30, minBit 0, minWin=25, winSum=424
8966 22:50:18.820878 TX Vref=32, minBit 0, minWin=24, winSum=417
8967 22:50:18.824534 TX Vref=34, minBit 3, minWin=24, winSum=408
8968 22:50:18.831892 [TxChooseVref] Worse bit 5, Min win 26, Win sum 431, Final Vref 28
8969 22:50:18.832632
8970 22:50:18.834392 Final TX Range 0 Vref 28
8971 22:50:18.834978
8972 22:50:18.835538 ==
8973 22:50:18.837847 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 22:50:18.840833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 22:50:18.841466 ==
8976 22:50:18.841991
8977 22:50:18.842528
8978 22:50:18.844631 TX Vref Scan disable
8979 22:50:18.847795 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8980 22:50:18.851053 == TX Byte 0 ==
8981 22:50:18.855386 u2DelayCellOfst[0]=17 cells (5 PI)
8982 22:50:18.858227 u2DelayCellOfst[1]=10 cells (3 PI)
8983 22:50:18.860764 u2DelayCellOfst[2]=0 cells (0 PI)
8984 22:50:18.864018 u2DelayCellOfst[3]=7 cells (2 PI)
8985 22:50:18.867529 u2DelayCellOfst[4]=10 cells (3 PI)
8986 22:50:18.870946 u2DelayCellOfst[5]=21 cells (6 PI)
8987 22:50:18.871493 u2DelayCellOfst[6]=17 cells (5 PI)
8988 22:50:18.874201 u2DelayCellOfst[7]=3 cells (1 PI)
8989 22:50:18.880861 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8990 22:50:18.884304 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8991 22:50:18.884907 == TX Byte 1 ==
8992 22:50:18.887667 u2DelayCellOfst[8]=0 cells (0 PI)
8993 22:50:18.890978 u2DelayCellOfst[9]=7 cells (2 PI)
8994 22:50:18.894107 u2DelayCellOfst[10]=14 cells (4 PI)
8995 22:50:18.897408 u2DelayCellOfst[11]=7 cells (2 PI)
8996 22:50:18.901199 u2DelayCellOfst[12]=17 cells (5 PI)
8997 22:50:18.905124 u2DelayCellOfst[13]=17 cells (5 PI)
8998 22:50:18.907960 u2DelayCellOfst[14]=21 cells (6 PI)
8999 22:50:18.910951 u2DelayCellOfst[15]=17 cells (5 PI)
9000 22:50:18.914458 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9001 22:50:18.918071 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9002 22:50:18.921592 DramC Write-DBI on
9003 22:50:18.922196 ==
9004 22:50:18.924644 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 22:50:18.928708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 22:50:18.929174 ==
9007 22:50:18.929592
9008 22:50:18.930035
9009 22:50:18.931405 TX Vref Scan disable
9010 22:50:18.935148 == TX Byte 0 ==
9011 22:50:18.937818 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9012 22:50:18.938329 == TX Byte 1 ==
9013 22:50:18.944499 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9014 22:50:18.944952 DramC Write-DBI off
9015 22:50:18.945348
9016 22:50:18.947729 [DATLAT]
9017 22:50:18.948188 Freq=1600, CH1 RK1
9018 22:50:18.948684
9019 22:50:18.951728 DATLAT Default: 0xf
9020 22:50:18.952301 0, 0xFFFF, sum = 0
9021 22:50:18.954302 1, 0xFFFF, sum = 0
9022 22:50:18.954793 2, 0xFFFF, sum = 0
9023 22:50:18.957631 3, 0xFFFF, sum = 0
9024 22:50:18.958107 4, 0xFFFF, sum = 0
9025 22:50:18.961334 5, 0xFFFF, sum = 0
9026 22:50:18.961799 6, 0xFFFF, sum = 0
9027 22:50:18.964493 7, 0xFFFF, sum = 0
9028 22:50:18.965139 8, 0xFFFF, sum = 0
9029 22:50:18.967816 9, 0xFFFF, sum = 0
9030 22:50:18.968388 10, 0xFFFF, sum = 0
9031 22:50:18.971106 11, 0xFFFF, sum = 0
9032 22:50:18.971677 12, 0xFFFF, sum = 0
9033 22:50:18.974900 13, 0xFFFF, sum = 0
9034 22:50:18.975364 14, 0x0, sum = 1
9035 22:50:18.978635 15, 0x0, sum = 2
9036 22:50:18.979079 16, 0x0, sum = 3
9037 22:50:18.980988 17, 0x0, sum = 4
9038 22:50:18.981539 best_step = 15
9039 22:50:18.981912
9040 22:50:18.982220 ==
9041 22:50:18.984891 Dram Type= 6, Freq= 0, CH_1, rank 1
9042 22:50:18.991464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9043 22:50:18.992038 ==
9044 22:50:18.992626 RX Vref Scan: 0
9045 22:50:18.993144
9046 22:50:18.994755 RX Vref 0 -> 0, step: 1
9047 22:50:18.995352
9048 22:50:18.997901 RX Delay 11 -> 252, step: 4
9049 22:50:19.001160 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
9050 22:50:19.005056 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
9051 22:50:19.007984 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9052 22:50:19.014950 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
9053 22:50:19.018394 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9054 22:50:19.021748 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9055 22:50:19.024715 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9056 22:50:19.028244 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
9057 22:50:19.034667 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9058 22:50:19.037897 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9059 22:50:19.041538 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9060 22:50:19.044842 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
9061 22:50:19.048329 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9062 22:50:19.054642 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9063 22:50:19.057727 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9064 22:50:19.060957 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9065 22:50:19.061563 ==
9066 22:50:19.064846 Dram Type= 6, Freq= 0, CH_1, rank 1
9067 22:50:19.068192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9068 22:50:19.068680 ==
9069 22:50:19.071001 DQS Delay:
9070 22:50:19.071574 DQS0 = 0, DQS1 = 0
9071 22:50:19.074283 DQM Delay:
9072 22:50:19.074844 DQM0 = 129, DQM1 = 126
9073 22:50:19.075342 DQ Delay:
9074 22:50:19.081286 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
9075 22:50:19.084786 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9076 22:50:19.088417 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9077 22:50:19.091159 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9078 22:50:19.091739
9079 22:50:19.092269
9080 22:50:19.092805
9081 22:50:19.094559 [DramC_TX_OE_Calibration] TA2
9082 22:50:19.098063 Original DQ_B0 (3 6) =30, OEN = 27
9083 22:50:19.101410 Original DQ_B1 (3 6) =30, OEN = 27
9084 22:50:19.101852 24, 0x0, End_B0=24 End_B1=24
9085 22:50:19.104438 25, 0x0, End_B0=25 End_B1=25
9086 22:50:19.107813 26, 0x0, End_B0=26 End_B1=26
9087 22:50:19.111558 27, 0x0, End_B0=27 End_B1=27
9088 22:50:19.112004 28, 0x0, End_B0=28 End_B1=28
9089 22:50:19.114581 29, 0x0, End_B0=29 End_B1=29
9090 22:50:19.117844 30, 0x0, End_B0=30 End_B1=30
9091 22:50:19.121438 31, 0x4141, End_B0=30 End_B1=30
9092 22:50:19.124853 Byte0 end_step=30 best_step=27
9093 22:50:19.127849 Byte1 end_step=30 best_step=27
9094 22:50:19.128472 Byte0 TX OE(2T, 0.5T) = (3, 3)
9095 22:50:19.131300 Byte1 TX OE(2T, 0.5T) = (3, 3)
9096 22:50:19.131906
9097 22:50:19.132430
9098 22:50:19.140588 [DQSOSCAuto] RK1, (LSB)MR18= 0x1217, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 400 ps
9099 22:50:19.143971 CH1 RK1: MR19=303, MR18=1217
9100 22:50:19.147666 CH1_RK1: MR19=0x303, MR18=0x1217, DQSOSC=398, MR23=63, INC=23, DEC=15
9101 22:50:19.150762 [RxdqsGatingPostProcess] freq 1600
9102 22:50:19.157823 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9103 22:50:19.160694 best DQS0 dly(2T, 0.5T) = (1, 1)
9104 22:50:19.164163 best DQS1 dly(2T, 0.5T) = (1, 1)
9105 22:50:19.167646 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9106 22:50:19.171128 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9107 22:50:19.174519 best DQS0 dly(2T, 0.5T) = (1, 1)
9108 22:50:19.174631 best DQS1 dly(2T, 0.5T) = (1, 1)
9109 22:50:19.177261 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9110 22:50:19.181236 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9111 22:50:19.184070 Pre-setting of DQS Precalculation
9112 22:50:19.190863 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9113 22:50:19.197674 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9114 22:50:19.204172 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 22:50:19.204351
9116 22:50:19.204513
9117 22:50:19.207646 [Calibration Summary] 3200 Mbps
9118 22:50:19.207846 CH 0, Rank 0
9119 22:50:19.210712 SW Impedance : PASS
9120 22:50:19.214330 DUTY Scan : NO K
9121 22:50:19.214575 ZQ Calibration : PASS
9122 22:50:19.217926 Jitter Meter : NO K
9123 22:50:19.221325 CBT Training : PASS
9124 22:50:19.221562 Write leveling : PASS
9125 22:50:19.224624 RX DQS gating : PASS
9126 22:50:19.227945 RX DQ/DQS(RDDQC) : PASS
9127 22:50:19.228345 TX DQ/DQS : PASS
9128 22:50:19.231894 RX DATLAT : PASS
9129 22:50:19.234827 RX DQ/DQS(Engine): PASS
9130 22:50:19.235317 TX OE : PASS
9131 22:50:19.235666 All Pass.
9132 22:50:19.235957
9133 22:50:19.237769 CH 0, Rank 1
9134 22:50:19.238147 SW Impedance : PASS
9135 22:50:19.242342 DUTY Scan : NO K
9136 22:50:19.244569 ZQ Calibration : PASS
9137 22:50:19.244949 Jitter Meter : NO K
9138 22:50:19.247708 CBT Training : PASS
9139 22:50:19.251356 Write leveling : PASS
9140 22:50:19.251843 RX DQS gating : PASS
9141 22:50:19.254486 RX DQ/DQS(RDDQC) : PASS
9142 22:50:19.257992 TX DQ/DQS : PASS
9143 22:50:19.258370 RX DATLAT : PASS
9144 22:50:19.261436 RX DQ/DQS(Engine): PASS
9145 22:50:19.264505 TX OE : PASS
9146 22:50:19.264917 All Pass.
9147 22:50:19.265283
9148 22:50:19.265600 CH 1, Rank 0
9149 22:50:19.267726 SW Impedance : PASS
9150 22:50:19.271550 DUTY Scan : NO K
9151 22:50:19.272065 ZQ Calibration : PASS
9152 22:50:19.275045 Jitter Meter : NO K
9153 22:50:19.278262 CBT Training : PASS
9154 22:50:19.278679 Write leveling : PASS
9155 22:50:19.281513 RX DQS gating : PASS
9156 22:50:19.281928 RX DQ/DQS(RDDQC) : PASS
9157 22:50:19.285461 TX DQ/DQS : PASS
9158 22:50:19.288026 RX DATLAT : PASS
9159 22:50:19.288441 RX DQ/DQS(Engine): PASS
9160 22:50:19.291628 TX OE : PASS
9161 22:50:19.292042 All Pass.
9162 22:50:19.292370
9163 22:50:19.294993 CH 1, Rank 1
9164 22:50:19.295405 SW Impedance : PASS
9165 22:50:19.298437 DUTY Scan : NO K
9166 22:50:19.301485 ZQ Calibration : PASS
9167 22:50:19.301915 Jitter Meter : NO K
9168 22:50:19.305443 CBT Training : PASS
9169 22:50:19.308433 Write leveling : PASS
9170 22:50:19.308944 RX DQS gating : PASS
9171 22:50:19.312018 RX DQ/DQS(RDDQC) : PASS
9172 22:50:19.314815 TX DQ/DQS : PASS
9173 22:50:19.315329 RX DATLAT : PASS
9174 22:50:19.317954 RX DQ/DQS(Engine): PASS
9175 22:50:19.318367 TX OE : PASS
9176 22:50:19.321542 All Pass.
9177 22:50:19.322110
9178 22:50:19.322529 DramC Write-DBI on
9179 22:50:19.325084 PER_BANK_REFRESH: Hybrid Mode
9180 22:50:19.328119 TX_TRACKING: ON
9181 22:50:19.335003 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9182 22:50:19.344942 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9183 22:50:19.351656 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9184 22:50:19.354678 [FAST_K] Save calibration result to emmc
9185 22:50:19.357780 sync common calibartion params.
9186 22:50:19.358227 sync cbt_mode0:1, 1:1
9187 22:50:19.361570 dram_init: ddr_geometry: 2
9188 22:50:19.364905 dram_init: ddr_geometry: 2
9189 22:50:19.368090 dram_init: ddr_geometry: 2
9190 22:50:19.368518 0:dram_rank_size:100000000
9191 22:50:19.372304 1:dram_rank_size:100000000
9192 22:50:19.378592 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9193 22:50:19.379132 DFS_SHUFFLE_HW_MODE: ON
9194 22:50:19.384630 dramc_set_vcore_voltage set vcore to 725000
9195 22:50:19.385140 Read voltage for 1600, 0
9196 22:50:19.385528 Vio18 = 0
9197 22:50:19.388451 Vcore = 725000
9198 22:50:19.388963 Vdram = 0
9199 22:50:19.389349 Vddq = 0
9200 22:50:19.391706 Vmddr = 0
9201 22:50:19.392119 switch to 3200 Mbps bootup
9202 22:50:19.394761 [DramcRunTimeConfig]
9203 22:50:19.395171 PHYPLL
9204 22:50:19.397919 DPM_CONTROL_AFTERK: ON
9205 22:50:19.398331 PER_BANK_REFRESH: ON
9206 22:50:19.401815 REFRESH_OVERHEAD_REDUCTION: ON
9207 22:50:19.405451 CMD_PICG_NEW_MODE: OFF
9208 22:50:19.405970 XRTWTW_NEW_MODE: ON
9209 22:50:19.408539 XRTRTR_NEW_MODE: ON
9210 22:50:19.409058 TX_TRACKING: ON
9211 22:50:19.411224 RDSEL_TRACKING: OFF
9212 22:50:19.414831 DQS Precalculation for DVFS: ON
9213 22:50:19.415351 RX_TRACKING: OFF
9214 22:50:19.418340 HW_GATING DBG: ON
9215 22:50:19.418865 ZQCS_ENABLE_LP4: ON
9216 22:50:19.421280 RX_PICG_NEW_MODE: ON
9217 22:50:19.421695 TX_PICG_NEW_MODE: ON
9218 22:50:19.425148 ENABLE_RX_DCM_DPHY: ON
9219 22:50:19.428131 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9220 22:50:19.431445 DUMMY_READ_FOR_TRACKING: OFF
9221 22:50:19.431962 !!! SPM_CONTROL_AFTERK: OFF
9222 22:50:19.434814 !!! SPM could not control APHY
9223 22:50:19.437961 IMPEDANCE_TRACKING: ON
9224 22:50:19.438492 TEMP_SENSOR: ON
9225 22:50:19.441321 HW_SAVE_FOR_SR: OFF
9226 22:50:19.445262 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9227 22:50:19.448436 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9228 22:50:19.451258 Read ODT Tracking: ON
9229 22:50:19.451778 Refresh Rate DeBounce: ON
9230 22:50:19.455516 DFS_NO_QUEUE_FLUSH: ON
9231 22:50:19.458085 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9232 22:50:19.461410 ENABLE_DFS_RUNTIME_MRW: OFF
9233 22:50:19.461975 DDR_RESERVE_NEW_MODE: ON
9234 22:50:19.464458 MR_CBT_SWITCH_FREQ: ON
9235 22:50:19.467537 =========================
9236 22:50:19.485467 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9237 22:50:19.488446 dram_init: ddr_geometry: 2
9238 22:50:19.506419 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9239 22:50:19.510281 dram_init: dram init end (result: 0)
9240 22:50:19.516993 DRAM-K: Full calibration passed in 24581 msecs
9241 22:50:19.519942 MRC: failed to locate region type 0.
9242 22:50:19.520497 DRAM rank0 size:0x100000000,
9243 22:50:19.523534 DRAM rank1 size=0x100000000
9244 22:50:19.533455 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9245 22:50:19.540352 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9246 22:50:19.546175 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9247 22:50:19.552909 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9248 22:50:19.556036 DRAM rank0 size:0x100000000,
9249 22:50:19.559605 DRAM rank1 size=0x100000000
9250 22:50:19.560058 CBMEM:
9251 22:50:19.563089 IMD: root @ 0xfffff000 254 entries.
9252 22:50:19.566485 IMD: root @ 0xffffec00 62 entries.
9253 22:50:19.570083 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9254 22:50:19.573317 WARNING: RO_VPD is uninitialized or empty.
9255 22:50:19.579773 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9256 22:50:19.586380 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9257 22:50:19.599636 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9258 22:50:19.611016 BS: romstage times (exec / console): total (unknown) / 24088 ms
9259 22:50:19.611623
9260 22:50:19.612172
9261 22:50:19.620732 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9262 22:50:19.624197 ARM64: Exception handlers installed.
9263 22:50:19.627920 ARM64: Testing exception
9264 22:50:19.630826 ARM64: Done test exception
9265 22:50:19.631274 Enumerating buses...
9266 22:50:19.634412 Show all devs... Before device enumeration.
9267 22:50:19.637813 Root Device: enabled 1
9268 22:50:19.640844 CPU_CLUSTER: 0: enabled 1
9269 22:50:19.641389 CPU: 00: enabled 1
9270 22:50:19.643950 Compare with tree...
9271 22:50:19.644402 Root Device: enabled 1
9272 22:50:19.647476 CPU_CLUSTER: 0: enabled 1
9273 22:50:19.650920 CPU: 00: enabled 1
9274 22:50:19.651345 Root Device scanning...
9275 22:50:19.654165 scan_static_bus for Root Device
9276 22:50:19.657564 CPU_CLUSTER: 0 enabled
9277 22:50:19.660881 scan_static_bus for Root Device done
9278 22:50:19.663881 scan_bus: bus Root Device finished in 8 msecs
9279 22:50:19.664355 done
9280 22:50:19.671579 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9281 22:50:19.674636 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9282 22:50:19.680573 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9283 22:50:19.683847 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9284 22:50:19.687276 Allocating resources...
9285 22:50:19.690745 Reading resources...
9286 22:50:19.694576 Root Device read_resources bus 0 link: 0
9287 22:50:19.695070 DRAM rank0 size:0x100000000,
9288 22:50:19.697202 DRAM rank1 size=0x100000000
9289 22:50:19.701050 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9290 22:50:19.704100 CPU: 00 missing read_resources
9291 22:50:19.707114 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9292 22:50:19.714404 Root Device read_resources bus 0 link: 0 done
9293 22:50:19.714982 Done reading resources.
9294 22:50:19.720835 Show resources in subtree (Root Device)...After reading.
9295 22:50:19.723985 Root Device child on link 0 CPU_CLUSTER: 0
9296 22:50:19.727260 CPU_CLUSTER: 0 child on link 0 CPU: 00
9297 22:50:19.737516 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9298 22:50:19.737957 CPU: 00
9299 22:50:19.740733 Root Device assign_resources, bus 0 link: 0
9300 22:50:19.744070 CPU_CLUSTER: 0 missing set_resources
9301 22:50:19.747163 Root Device assign_resources, bus 0 link: 0 done
9302 22:50:19.750509 Done setting resources.
9303 22:50:19.757140 Show resources in subtree (Root Device)...After assigning values.
9304 22:50:19.760592 Root Device child on link 0 CPU_CLUSTER: 0
9305 22:50:19.764015 CPU_CLUSTER: 0 child on link 0 CPU: 00
9306 22:50:19.774289 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9307 22:50:19.774909 CPU: 00
9308 22:50:19.777317 Done allocating resources.
9309 22:50:19.780631 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9310 22:50:19.784074 Enabling resources...
9311 22:50:19.784738 done.
9312 22:50:19.790317 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9313 22:50:19.790894 Initializing devices...
9314 22:50:19.793945 Root Device init
9315 22:50:19.794379 init hardware done!
9316 22:50:19.797065 0x00000018: ctrlr->caps
9317 22:50:19.800571 52.000 MHz: ctrlr->f_max
9318 22:50:19.801449 0.400 MHz: ctrlr->f_min
9319 22:50:19.803821 0x40ff8080: ctrlr->voltages
9320 22:50:19.804663 sclk: 390625
9321 22:50:19.806980 Bus Width = 1
9322 22:50:19.807442 sclk: 390625
9323 22:50:19.807906 Bus Width = 1
9324 22:50:19.810667 Early init status = 3
9325 22:50:19.814095 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9326 22:50:19.818137 in-header: 03 fc 00 00 01 00 00 00
9327 22:50:19.821672 in-data: 00
9328 22:50:19.825084 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9329 22:50:19.829491 in-header: 03 fd 00 00 00 00 00 00
9330 22:50:19.832711 in-data:
9331 22:50:19.836251 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9332 22:50:19.840598 in-header: 03 fc 00 00 01 00 00 00
9333 22:50:19.843085 in-data: 00
9334 22:50:19.846082 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9335 22:50:19.850558 in-header: 03 fd 00 00 00 00 00 00
9336 22:50:19.854164 in-data:
9337 22:50:19.857369 [SSUSB] Setting up USB HOST controller...
9338 22:50:19.861044 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9339 22:50:19.864246 [SSUSB] phy power-on done.
9340 22:50:19.868171 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9341 22:50:19.874791 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9342 22:50:19.877169 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9343 22:50:19.884565 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9344 22:50:19.890645 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9345 22:50:19.897243 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9346 22:50:19.904534 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9347 22:50:19.910730 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9348 22:50:19.913893 SPM: binary array size = 0x9dc
9349 22:50:19.917178 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9350 22:50:19.924303 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9351 22:50:19.931045 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9352 22:50:19.934119 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9353 22:50:19.941128 configure_display: Starting display init
9354 22:50:19.974094 anx7625_power_on_init: Init interface.
9355 22:50:19.977407 anx7625_disable_pd_protocol: Disabled PD feature.
9356 22:50:19.980676 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9357 22:50:20.008647 anx7625_start_dp_work: Secure OCM version=00
9358 22:50:20.012089 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9359 22:50:20.026828 sp_tx_get_edid_block: EDID Block = 1
9360 22:50:20.129999 Extracted contents:
9361 22:50:20.132625 header: 00 ff ff ff ff ff ff 00
9362 22:50:20.136089 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9363 22:50:20.139460 version: 01 04
9364 22:50:20.142591 basic params: 95 1f 11 78 0a
9365 22:50:20.145952 chroma info: 76 90 94 55 54 90 27 21 50 54
9366 22:50:20.149366 established: 00 00 00
9367 22:50:20.156067 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9368 22:50:20.159428 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9369 22:50:20.165891 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 22:50:20.172331 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9371 22:50:20.179387 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9372 22:50:20.182961 extensions: 00
9373 22:50:20.183527 checksum: fb
9374 22:50:20.183885
9375 22:50:20.186226 Manufacturer: IVO Model 57d Serial Number 0
9376 22:50:20.189315 Made week 0 of 2020
9377 22:50:20.189729 EDID version: 1.4
9378 22:50:20.193239 Digital display
9379 22:50:20.195853 6 bits per primary color channel
9380 22:50:20.196278 DisplayPort interface
9381 22:50:20.199444 Maximum image size: 31 cm x 17 cm
9382 22:50:20.199963 Gamma: 220%
9383 22:50:20.202600 Check DPMS levels
9384 22:50:20.205763 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9385 22:50:20.209687 First detailed timing is preferred timing
9386 22:50:20.212644 Established timings supported:
9387 22:50:20.215847 Standard timings supported:
9388 22:50:20.216279 Detailed timings
9389 22:50:20.222938 Hex of detail: 383680a07038204018303c0035ae10000019
9390 22:50:20.225816 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9391 22:50:20.229252 0780 0798 07c8 0820 hborder 0
9392 22:50:20.236451 0438 043b 0447 0458 vborder 0
9393 22:50:20.236972 -hsync -vsync
9394 22:50:20.240139 Did detailed timing
9395 22:50:20.242845 Hex of detail: 000000000000000000000000000000000000
9396 22:50:20.246360 Manufacturer-specified data, tag 0
9397 22:50:20.253148 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9398 22:50:20.253720 ASCII string: InfoVision
9399 22:50:20.259723 Hex of detail: 000000fe00523134304e574635205248200a
9400 22:50:20.260263 ASCII string: R140NWF5 RH
9401 22:50:20.262714 Checksum
9402 22:50:20.263131 Checksum: 0xfb (valid)
9403 22:50:20.269681 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9404 22:50:20.270215 DSI data_rate: 832800000 bps
9405 22:50:20.277723 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9406 22:50:20.280663 anx7625_parse_edid: pixelclock(138800).
9407 22:50:20.284050 hactive(1920), hsync(48), hfp(24), hbp(88)
9408 22:50:20.287388 vactive(1080), vsync(12), vfp(3), vbp(17)
9409 22:50:20.290125 anx7625_dsi_config: config dsi.
9410 22:50:20.297014 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9411 22:50:20.311056 anx7625_dsi_config: success to config DSI
9412 22:50:20.314608 anx7625_dp_start: MIPI phy setup OK.
9413 22:50:20.318621 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9414 22:50:20.321413 mtk_ddp_mode_set invalid vrefresh 60
9415 22:50:20.325010 main_disp_path_setup
9416 22:50:20.325570 ovl_layer_smi_id_en
9417 22:50:20.328229 ovl_layer_smi_id_en
9418 22:50:20.328749 ccorr_config
9419 22:50:20.329097 aal_config
9420 22:50:20.331546 gamma_config
9421 22:50:20.332073 postmask_config
9422 22:50:20.334994 dither_config
9423 22:50:20.337882 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9424 22:50:20.344953 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9425 22:50:20.348439 Root Device init finished in 551 msecs
9426 22:50:20.348998 CPU_CLUSTER: 0 init
9427 22:50:20.358153 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9428 22:50:20.361507 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9429 22:50:20.364779 APU_MBOX 0x190000b0 = 0x10001
9430 22:50:20.368529 APU_MBOX 0x190001b0 = 0x10001
9431 22:50:20.371380 APU_MBOX 0x190005b0 = 0x10001
9432 22:50:20.375484 APU_MBOX 0x190006b0 = 0x10001
9433 22:50:20.378634 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9434 22:50:20.390370 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9435 22:50:20.402646 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9436 22:50:20.410388 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9437 22:50:20.421522 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9438 22:50:20.430020 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9439 22:50:20.433758 CPU_CLUSTER: 0 init finished in 81 msecs
9440 22:50:20.436935 Devices initialized
9441 22:50:20.440525 Show all devs... After init.
9442 22:50:20.441088 Root Device: enabled 1
9443 22:50:20.444055 CPU_CLUSTER: 0: enabled 1
9444 22:50:20.447202 CPU: 00: enabled 1
9445 22:50:20.450214 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9446 22:50:20.453634 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9447 22:50:20.457199 ELOG: NV offset 0x57f000 size 0x1000
9448 22:50:20.464255 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9449 22:50:20.470658 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9450 22:50:20.473410 ELOG: Event(17) added with size 13 at 2024-05-07 22:50:21 UTC
9451 22:50:20.477175 out: cmd=0x121: 03 db 21 01 00 00 00 00
9452 22:50:20.480719 in-header: 03 d8 00 00 2c 00 00 00
9453 22:50:20.493843 in-data: 87 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9454 22:50:20.501070 ELOG: Event(A1) added with size 10 at 2024-05-07 22:50:21 UTC
9455 22:50:20.507854 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9456 22:50:20.513909 ELOG: Event(A0) added with size 9 at 2024-05-07 22:50:21 UTC
9457 22:50:20.517404 elog_add_boot_reason: Logged dev mode boot
9458 22:50:20.521011 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9459 22:50:20.524527 Finalize devices...
9460 22:50:20.525084 Devices finalized
9461 22:50:20.532063 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9462 22:50:20.534189 Writing coreboot table at 0xffe64000
9463 22:50:20.537590 0. 000000000010a000-0000000000113fff: RAMSTAGE
9464 22:50:20.540917 1. 0000000040000000-00000000400fffff: RAM
9465 22:50:20.544377 2. 0000000040100000-000000004032afff: RAMSTAGE
9466 22:50:20.550717 3. 000000004032b000-00000000545fffff: RAM
9467 22:50:20.554775 4. 0000000054600000-000000005465ffff: BL31
9468 22:50:20.557317 5. 0000000054660000-00000000ffe63fff: RAM
9469 22:50:20.560679 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9470 22:50:20.567295 7. 0000000100000000-000000023fffffff: RAM
9471 22:50:20.567841 Passing 5 GPIOs to payload:
9472 22:50:20.574226 NAME | PORT | POLARITY | VALUE
9473 22:50:20.577802 EC in RW | 0x000000aa | low | undefined
9474 22:50:20.584405 EC interrupt | 0x00000005 | low | undefined
9475 22:50:20.587516 TPM interrupt | 0x000000ab | high | undefined
9476 22:50:20.590549 SD card detect | 0x00000011 | high | undefined
9477 22:50:20.597362 speaker enable | 0x00000093 | high | undefined
9478 22:50:20.601057 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9479 22:50:20.604128 in-header: 03 f9 00 00 02 00 00 00
9480 22:50:20.604551 in-data: 02 00
9481 22:50:20.607352 ADC[4]: Raw value=900959 ID=7
9482 22:50:20.610887 ADC[3]: Raw value=213336 ID=1
9483 22:50:20.611408 RAM Code: 0x71
9484 22:50:20.613980 ADC[6]: Raw value=74926 ID=0
9485 22:50:20.617876 ADC[5]: Raw value=211860 ID=1
9486 22:50:20.618396 SKU Code: 0x1
9487 22:50:20.623864 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ab9e
9488 22:50:20.627450 coreboot table: 964 bytes.
9489 22:50:20.630746 IMD ROOT 0. 0xfffff000 0x00001000
9490 22:50:20.634208 IMD SMALL 1. 0xffffe000 0x00001000
9491 22:50:20.637872 RO MCACHE 2. 0xffffc000 0x00001104
9492 22:50:20.640987 CONSOLE 3. 0xfff7c000 0x00080000
9493 22:50:20.644258 FMAP 4. 0xfff7b000 0x00000452
9494 22:50:20.648239 TIME STAMP 5. 0xfff7a000 0x00000910
9495 22:50:20.650818 VBOOT WORK 6. 0xfff66000 0x00014000
9496 22:50:20.654394 RAMOOPS 7. 0xffe66000 0x00100000
9497 22:50:20.658208 COREBOOT 8. 0xffe64000 0x00002000
9498 22:50:20.658630 IMD small region:
9499 22:50:20.660864 IMD ROOT 0. 0xffffec00 0x00000400
9500 22:50:20.664417 VPD 1. 0xffffeb80 0x0000006c
9501 22:50:20.667684 MMC STATUS 2. 0xffffeb60 0x00000004
9502 22:50:20.674253 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9503 22:50:20.674760 Probing TPM: done!
9504 22:50:20.681562 Connected to device vid:did:rid of 1ae0:0028:00
9505 22:50:20.688295 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9506 22:50:20.691186 Initialized TPM device CR50 revision 0
9507 22:50:20.694666 Checking cr50 for pending updates
9508 22:50:20.700494 Reading cr50 TPM mode
9509 22:50:20.708863 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9510 22:50:20.715754 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9511 22:50:20.755311 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9512 22:50:20.759213 Checking segment from ROM address 0x40100000
9513 22:50:20.762406 Checking segment from ROM address 0x4010001c
9514 22:50:20.768710 Loading segment from ROM address 0x40100000
9515 22:50:20.769261 code (compression=0)
9516 22:50:20.775836 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9517 22:50:20.785893 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9518 22:50:20.786577 it's not compressed!
9519 22:50:20.792781 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9520 22:50:20.796537 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9521 22:50:20.816295 Loading segment from ROM address 0x4010001c
9522 22:50:20.816814 Entry Point 0x80000000
9523 22:50:20.819368 Loaded segments
9524 22:50:20.822573 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9525 22:50:20.829731 Jumping to boot code at 0x80000000(0xffe64000)
9526 22:50:20.836369 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9527 22:50:20.843133 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9528 22:50:20.850458 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9529 22:50:20.853395 Checking segment from ROM address 0x40100000
9530 22:50:20.857052 Checking segment from ROM address 0x4010001c
9531 22:50:20.864106 Loading segment from ROM address 0x40100000
9532 22:50:20.864605 code (compression=1)
9533 22:50:20.870286 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9534 22:50:20.880580 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9535 22:50:20.881290 using LZMA
9536 22:50:20.889687 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9537 22:50:20.895447 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9538 22:50:20.898717 Loading segment from ROM address 0x4010001c
9539 22:50:20.899284 Entry Point 0x54601000
9540 22:50:20.901827 Loaded segments
9541 22:50:20.905320 NOTICE: MT8192 bl31_setup
9542 22:50:20.912460 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9543 22:50:20.915948 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9544 22:50:20.919144 WARNING: region 0:
9545 22:50:20.922738 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 22:50:20.923248 WARNING: region 1:
9547 22:50:20.928909 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9548 22:50:20.932154 WARNING: region 2:
9549 22:50:20.935469 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9550 22:50:20.939256 WARNING: region 3:
9551 22:50:20.942206 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9552 22:50:20.945724 WARNING: region 4:
9553 22:50:20.952837 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9554 22:50:20.953300 WARNING: region 5:
9555 22:50:20.956507 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9556 22:50:20.958954 WARNING: region 6:
9557 22:50:20.962720 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9558 22:50:20.963387 WARNING: region 7:
9559 22:50:20.968864 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9560 22:50:20.975425 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9561 22:50:20.979354 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9562 22:50:20.982563 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9563 22:50:20.989650 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9564 22:50:20.992461 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9565 22:50:20.995930 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9566 22:50:21.002464 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9567 22:50:21.005675 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9568 22:50:21.009512 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9569 22:50:21.016486 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9570 22:50:21.019621 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9571 22:50:21.022764 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9572 22:50:21.029190 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9573 22:50:21.033012 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9574 22:50:21.039623 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9575 22:50:21.042877 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9576 22:50:21.046657 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9577 22:50:21.053265 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9578 22:50:21.056021 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9579 22:50:21.059891 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9580 22:50:21.066742 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9581 22:50:21.069663 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9582 22:50:21.076023 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9583 22:50:21.079623 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9584 22:50:21.083095 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9585 22:50:21.090077 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9586 22:50:21.093032 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9587 22:50:21.096496 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9588 22:50:21.103369 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9589 22:50:21.107483 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9590 22:50:21.112987 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9591 22:50:21.116815 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9592 22:50:21.119995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9593 22:50:21.123076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9594 22:50:21.130184 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9595 22:50:21.133294 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9596 22:50:21.136922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9597 22:50:21.140249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9598 22:50:21.146740 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9599 22:50:21.149879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9600 22:50:21.153303 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9601 22:50:21.156647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9602 22:50:21.163351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9603 22:50:21.166814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9604 22:50:21.170430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9605 22:50:21.173779 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9606 22:50:21.179876 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9607 22:50:21.183814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9608 22:50:21.186766 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9609 22:50:21.193542 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9610 22:50:21.197564 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9611 22:50:21.204260 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9612 22:50:21.207164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9613 22:50:21.210424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9614 22:50:21.217761 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9615 22:50:21.221166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9616 22:50:21.227575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9617 22:50:21.230749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9618 22:50:21.233691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9619 22:50:21.240871 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9620 22:50:21.244056 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9621 22:50:21.251099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9622 22:50:21.254350 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9623 22:50:21.261403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9624 22:50:21.264710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9625 22:50:21.270751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9626 22:50:21.274498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9627 22:50:21.277517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9628 22:50:21.285193 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9629 22:50:21.287830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9630 22:50:21.294256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9631 22:50:21.297685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9632 22:50:21.301178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9633 22:50:21.307529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9634 22:50:21.311403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9635 22:50:21.317663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9636 22:50:21.321152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9637 22:50:21.327931 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9638 22:50:21.332044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9639 22:50:21.334769 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9640 22:50:21.341268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9641 22:50:21.344321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9642 22:50:21.350975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9643 22:50:21.354166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9644 22:50:21.361629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9645 22:50:21.365145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9646 22:50:21.367971 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9647 22:50:21.374831 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9648 22:50:21.377676 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9649 22:50:21.384714 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9650 22:50:21.387976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9651 22:50:21.391776 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9652 22:50:21.398657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9653 22:50:21.401176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9654 22:50:21.408463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9655 22:50:21.411473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9656 22:50:21.414876 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9657 22:50:21.421580 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9658 22:50:21.425392 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9659 22:50:21.428282 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9660 22:50:21.431990 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9661 22:50:21.438155 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9662 22:50:21.441719 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9663 22:50:21.448603 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9664 22:50:21.452004 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9665 22:50:21.455105 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9666 22:50:21.462017 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9667 22:50:21.465441 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9668 22:50:21.472430 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9669 22:50:21.475887 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9670 22:50:21.479427 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9671 22:50:21.485564 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9672 22:50:21.488586 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9673 22:50:21.492329 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9674 22:50:21.498794 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9675 22:50:21.502037 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9676 22:50:21.505956 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9677 22:50:21.512532 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9678 22:50:21.515637 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9679 22:50:21.518743 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9680 22:50:21.522137 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9681 22:50:21.529374 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9682 22:50:21.532247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9683 22:50:21.536096 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9684 22:50:21.542982 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9685 22:50:21.545986 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9686 22:50:21.549424 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9687 22:50:21.555574 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9688 22:50:21.558994 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9689 22:50:21.566024 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9690 22:50:21.568921 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9691 22:50:21.572475 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9692 22:50:21.579511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9693 22:50:21.582586 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9694 22:50:21.585960 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9695 22:50:21.592641 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9696 22:50:21.595930 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9697 22:50:21.602847 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9698 22:50:21.606048 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9699 22:50:21.609543 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9700 22:50:21.616488 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9701 22:50:21.619571 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9702 22:50:21.623604 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9703 22:50:21.629750 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9704 22:50:21.633111 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9705 22:50:21.639547 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9706 22:50:21.643558 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9707 22:50:21.646715 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9708 22:50:21.653166 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9709 22:50:21.656411 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9710 22:50:21.659757 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9711 22:50:21.666382 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9712 22:50:21.670160 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9713 22:50:21.676732 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9714 22:50:21.679732 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9715 22:50:21.683413 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9716 22:50:21.689766 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9717 22:50:21.693084 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9718 22:50:21.696324 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9719 22:50:21.703254 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9720 22:50:21.706731 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9721 22:50:21.713158 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9722 22:50:21.716803 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9723 22:50:21.719811 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9724 22:50:21.726139 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9725 22:50:21.729765 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9726 22:50:21.736743 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9727 22:50:21.739942 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9728 22:50:21.742975 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9729 22:50:21.750014 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9730 22:50:21.753667 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9731 22:50:21.760235 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9732 22:50:21.763315 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9733 22:50:21.766959 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9734 22:50:21.773330 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9735 22:50:21.777238 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9736 22:50:21.780226 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9737 22:50:21.786542 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9738 22:50:21.789916 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9739 22:50:21.793618 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9740 22:50:21.799601 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9741 22:50:21.803239 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9742 22:50:21.810361 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9743 22:50:21.813434 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9744 22:50:21.819698 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9745 22:50:21.823580 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9746 22:50:21.826062 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9747 22:50:21.833398 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9748 22:50:21.836470 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9749 22:50:21.843535 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9750 22:50:21.846343 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9751 22:50:21.849937 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9752 22:50:21.856247 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9753 22:50:21.859323 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9754 22:50:21.866325 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9755 22:50:21.870014 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9756 22:50:21.873188 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9757 22:50:21.879631 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9758 22:50:21.882733 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9759 22:50:21.889602 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9760 22:50:21.892973 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9761 22:50:21.896186 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9762 22:50:21.903268 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9763 22:50:21.906460 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9764 22:50:21.913410 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9765 22:50:21.915982 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9766 22:50:21.922796 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9767 22:50:21.925579 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9768 22:50:21.929357 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9769 22:50:21.935744 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9770 22:50:21.939356 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9771 22:50:21.945934 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9772 22:50:21.949404 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9773 22:50:21.952399 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9774 22:50:21.958946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9775 22:50:21.962837 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9776 22:50:21.969242 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9777 22:50:21.972536 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9778 22:50:21.975942 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9779 22:50:21.982493 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9780 22:50:21.985508 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9781 22:50:21.992207 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9782 22:50:21.995839 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9783 22:50:22.002543 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9784 22:50:22.006027 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9785 22:50:22.008917 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9786 22:50:22.015724 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9787 22:50:22.019398 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9788 22:50:22.025865 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9789 22:50:22.029841 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9790 22:50:22.032479 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9791 22:50:22.035841 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9792 22:50:22.038871 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9793 22:50:22.045779 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9794 22:50:22.049177 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9795 22:50:22.052549 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9796 22:50:22.059252 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9797 22:50:22.062675 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9798 22:50:22.065791 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9799 22:50:22.072549 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9800 22:50:22.075795 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9801 22:50:22.082482 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9802 22:50:22.085833 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9803 22:50:22.088959 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9804 22:50:22.096586 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9805 22:50:22.099193 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9806 22:50:22.102436 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9807 22:50:22.109343 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9808 22:50:22.112918 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9809 22:50:22.116151 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9810 22:50:22.123030 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9811 22:50:22.125925 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9812 22:50:22.132377 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9813 22:50:22.135782 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9814 22:50:22.139453 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9815 22:50:22.145744 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9816 22:50:22.148931 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9817 22:50:22.152608 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9818 22:50:22.159478 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9819 22:50:22.162185 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9820 22:50:22.165657 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9821 22:50:22.172413 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9822 22:50:22.175884 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9823 22:50:22.179243 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9824 22:50:22.185563 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9825 22:50:22.188977 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9826 22:50:22.195619 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9827 22:50:22.198975 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9828 22:50:22.202671 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9829 22:50:22.205517 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9830 22:50:22.212582 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9831 22:50:22.215884 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9832 22:50:22.219460 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9833 22:50:22.222664 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9834 22:50:22.229085 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9835 22:50:22.232888 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9836 22:50:22.235903 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9837 22:50:22.239359 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9838 22:50:22.242435 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9839 22:50:22.249331 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9840 22:50:22.252351 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9841 22:50:22.255775 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9842 22:50:22.263144 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9843 22:50:22.266071 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9844 22:50:22.272562 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9845 22:50:22.275979 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9846 22:50:22.279429 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9847 22:50:22.286206 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9848 22:50:22.289568 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9849 22:50:22.295941 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9850 22:50:22.299057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9851 22:50:22.302827 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9852 22:50:22.309184 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9853 22:50:22.312835 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9854 22:50:22.319287 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9855 22:50:22.322474 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9856 22:50:22.325911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9857 22:50:22.332379 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9858 22:50:22.335849 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9859 22:50:22.342580 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9860 22:50:22.345816 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9861 22:50:22.349407 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9862 22:50:22.355743 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9863 22:50:22.359182 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9864 22:50:22.365815 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9865 22:50:22.369125 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9866 22:50:22.372285 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9867 22:50:22.378992 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9868 22:50:22.382400 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9869 22:50:22.389055 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9870 22:50:22.392037 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9871 22:50:22.398838 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9872 22:50:22.402591 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9873 22:50:22.405711 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9874 22:50:22.412352 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9875 22:50:22.415677 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9876 22:50:22.422153 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9877 22:50:22.425247 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9878 22:50:22.428601 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9879 22:50:22.435729 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9880 22:50:22.438708 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9881 22:50:22.445254 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9882 22:50:22.448865 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9883 22:50:22.452170 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9884 22:50:22.458482 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9885 22:50:22.462136 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9886 22:50:22.468770 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9887 22:50:22.471911 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9888 22:50:22.479022 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9889 22:50:22.482569 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9890 22:50:22.485531 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9891 22:50:22.492411 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9892 22:50:22.495496 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9893 22:50:22.498777 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9894 22:50:22.505394 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9895 22:50:22.508819 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9896 22:50:22.515475 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9897 22:50:22.519008 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9898 22:50:22.522172 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9899 22:50:22.529183 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9900 22:50:22.532143 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9901 22:50:22.538617 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9902 22:50:22.542157 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9903 22:50:22.549030 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9904 22:50:22.552127 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9905 22:50:22.555461 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9906 22:50:22.561941 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9907 22:50:22.565094 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9908 22:50:22.571984 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9909 22:50:22.575136 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9910 22:50:22.578606 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9911 22:50:22.585918 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9912 22:50:22.588662 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9913 22:50:22.591994 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9914 22:50:22.598760 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9915 22:50:22.602112 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9916 22:50:22.609337 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9917 22:50:22.612035 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9918 22:50:22.618608 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9919 22:50:22.622272 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9920 22:50:22.628762 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9921 22:50:22.632094 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9922 22:50:22.635652 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9923 22:50:22.642450 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9924 22:50:22.645850 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9925 22:50:22.652741 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9926 22:50:22.655703 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9927 22:50:22.658762 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9928 22:50:22.665392 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9929 22:50:22.669401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9930 22:50:22.676191 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9931 22:50:22.679021 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9932 22:50:22.685420 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9933 22:50:22.688905 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9934 22:50:22.692389 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9935 22:50:22.698573 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9936 22:50:22.702107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9937 22:50:22.708583 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9938 22:50:22.712203 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9939 22:50:22.718984 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9940 22:50:22.722798 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9941 22:50:22.725404 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9942 22:50:22.732082 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9943 22:50:22.735626 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9944 22:50:22.742139 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9945 22:50:22.745525 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9946 22:50:22.752306 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9947 22:50:22.756245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9948 22:50:22.758785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9949 22:50:22.766004 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9950 22:50:22.768947 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9951 22:50:22.775863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9952 22:50:22.779226 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9953 22:50:22.782095 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9954 22:50:22.789030 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9955 22:50:22.792727 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9956 22:50:22.799467 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9957 22:50:22.802265 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9958 22:50:22.808886 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9959 22:50:22.812156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9960 22:50:22.819006 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9961 22:50:22.822744 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9962 22:50:22.825885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9963 22:50:22.833140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9964 22:50:22.836092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9965 22:50:22.842209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9966 22:50:22.845696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9967 22:50:22.852330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9968 22:50:22.855898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9969 22:50:22.859126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9970 22:50:22.866109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9971 22:50:22.869563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9972 22:50:22.876163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9973 22:50:22.879299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9974 22:50:22.885919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9975 22:50:22.889525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9976 22:50:22.895726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9977 22:50:22.899400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9978 22:50:22.905967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9979 22:50:22.909133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9980 22:50:22.915915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9981 22:50:22.919265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9982 22:50:22.925720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9983 22:50:22.929115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9984 22:50:22.935783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9985 22:50:22.939602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9986 22:50:22.946308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9987 22:50:22.949537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9988 22:50:22.956343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9989 22:50:22.959957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9990 22:50:22.966433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9991 22:50:22.969814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9992 22:50:22.975804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9993 22:50:22.980012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9994 22:50:22.982615 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9995 22:50:22.985811 INFO: [APUAPC] vio 0
9996 22:50:22.989069 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9997 22:50:22.995885 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9998 22:50:22.999636 INFO: [APUAPC] D0_APC_0: 0x400510
9999 22:50:23.003127 INFO: [APUAPC] D0_APC_1: 0x0
10000 22:50:23.006725 INFO: [APUAPC] D0_APC_2: 0x1540
10001 22:50:23.006827 INFO: [APUAPC] D0_APC_3: 0x0
10002 22:50:23.009341 INFO: [APUAPC] D1_APC_0: 0xffffffff
10003 22:50:23.012904 INFO: [APUAPC] D1_APC_1: 0xffffffff
10004 22:50:23.016090 INFO: [APUAPC] D1_APC_2: 0x3fffff
10005 22:50:23.019526 INFO: [APUAPC] D1_APC_3: 0x0
10006 22:50:23.023075 INFO: [APUAPC] D2_APC_0: 0xffffffff
10007 22:50:23.026589 INFO: [APUAPC] D2_APC_1: 0xffffffff
10008 22:50:23.030379 INFO: [APUAPC] D2_APC_2: 0x3fffff
10009 22:50:23.032755 INFO: [APUAPC] D2_APC_3: 0x0
10010 22:50:23.036259 INFO: [APUAPC] D3_APC_0: 0xffffffff
10011 22:50:23.039724 INFO: [APUAPC] D3_APC_1: 0xffffffff
10012 22:50:23.043019 INFO: [APUAPC] D3_APC_2: 0x3fffff
10013 22:50:23.046517 INFO: [APUAPC] D3_APC_3: 0x0
10014 22:50:23.049951 INFO: [APUAPC] D4_APC_0: 0xffffffff
10015 22:50:23.053258 INFO: [APUAPC] D4_APC_1: 0xffffffff
10016 22:50:23.056502 INFO: [APUAPC] D4_APC_2: 0x3fffff
10017 22:50:23.059883 INFO: [APUAPC] D4_APC_3: 0x0
10018 22:50:23.063482 INFO: [APUAPC] D5_APC_0: 0xffffffff
10019 22:50:23.066793 INFO: [APUAPC] D5_APC_1: 0xffffffff
10020 22:50:23.069838 INFO: [APUAPC] D5_APC_2: 0x3fffff
10021 22:50:23.073303 INFO: [APUAPC] D5_APC_3: 0x0
10022 22:50:23.076222 INFO: [APUAPC] D6_APC_0: 0xffffffff
10023 22:50:23.079680 INFO: [APUAPC] D6_APC_1: 0xffffffff
10024 22:50:23.082962 INFO: [APUAPC] D6_APC_2: 0x3fffff
10025 22:50:23.086334 INFO: [APUAPC] D6_APC_3: 0x0
10026 22:50:23.089508 INFO: [APUAPC] D7_APC_0: 0xffffffff
10027 22:50:23.093137 INFO: [APUAPC] D7_APC_1: 0xffffffff
10028 22:50:23.096538 INFO: [APUAPC] D7_APC_2: 0x3fffff
10029 22:50:23.099648 INFO: [APUAPC] D7_APC_3: 0x0
10030 22:50:23.103012 INFO: [APUAPC] D8_APC_0: 0xffffffff
10031 22:50:23.106563 INFO: [APUAPC] D8_APC_1: 0xffffffff
10032 22:50:23.110024 INFO: [APUAPC] D8_APC_2: 0x3fffff
10033 22:50:23.112914 INFO: [APUAPC] D8_APC_3: 0x0
10034 22:50:23.116535 INFO: [APUAPC] D9_APC_0: 0xffffffff
10035 22:50:23.119849 INFO: [APUAPC] D9_APC_1: 0xffffffff
10036 22:50:23.123310 INFO: [APUAPC] D9_APC_2: 0x3fffff
10037 22:50:23.123415 INFO: [APUAPC] D9_APC_3: 0x0
10038 22:50:23.126632 INFO: [APUAPC] D10_APC_0: 0xffffffff
10039 22:50:23.133378 INFO: [APUAPC] D10_APC_1: 0xffffffff
10040 22:50:23.136446 INFO: [APUAPC] D10_APC_2: 0x3fffff
10041 22:50:23.136543 INFO: [APUAPC] D10_APC_3: 0x0
10042 22:50:23.140770 INFO: [APUAPC] D11_APC_0: 0xffffffff
10043 22:50:23.146439 INFO: [APUAPC] D11_APC_1: 0xffffffff
10044 22:50:23.149797 INFO: [APUAPC] D11_APC_2: 0x3fffff
10045 22:50:23.149907 INFO: [APUAPC] D11_APC_3: 0x0
10046 22:50:23.156364 INFO: [APUAPC] D12_APC_0: 0xffffffff
10047 22:50:23.159737 INFO: [APUAPC] D12_APC_1: 0xffffffff
10048 22:50:23.162980 INFO: [APUAPC] D12_APC_2: 0x3fffff
10049 22:50:23.163075 INFO: [APUAPC] D12_APC_3: 0x0
10050 22:50:23.167145 INFO: [APUAPC] D13_APC_0: 0xffffffff
10051 22:50:23.173568 INFO: [APUAPC] D13_APC_1: 0xffffffff
10052 22:50:23.176814 INFO: [APUAPC] D13_APC_2: 0x3fffff
10053 22:50:23.176896 INFO: [APUAPC] D13_APC_3: 0x0
10054 22:50:23.183157 INFO: [APUAPC] D14_APC_0: 0xffffffff
10055 22:50:23.186552 INFO: [APUAPC] D14_APC_1: 0xffffffff
10056 22:50:23.190105 INFO: [APUAPC] D14_APC_2: 0x3fffff
10057 22:50:23.192882 INFO: [APUAPC] D14_APC_3: 0x0
10058 22:50:23.196089 INFO: [APUAPC] D15_APC_0: 0xffffffff
10059 22:50:23.199698 INFO: [APUAPC] D15_APC_1: 0xffffffff
10060 22:50:23.203213 INFO: [APUAPC] D15_APC_2: 0x3fffff
10061 22:50:23.206312 INFO: [APUAPC] D15_APC_3: 0x0
10062 22:50:23.206394 INFO: [APUAPC] APC_CON: 0x4
10063 22:50:23.209996 INFO: [NOCDAPC] D0_APC_0: 0x0
10064 22:50:23.213219 INFO: [NOCDAPC] D0_APC_1: 0x0
10065 22:50:23.216362 INFO: [NOCDAPC] D1_APC_0: 0x0
10066 22:50:23.220429 INFO: [NOCDAPC] D1_APC_1: 0xfff
10067 22:50:23.223349 INFO: [NOCDAPC] D2_APC_0: 0x0
10068 22:50:23.226454 INFO: [NOCDAPC] D2_APC_1: 0xfff
10069 22:50:23.229721 INFO: [NOCDAPC] D3_APC_0: 0x0
10070 22:50:23.233238 INFO: [NOCDAPC] D3_APC_1: 0xfff
10071 22:50:23.233326 INFO: [NOCDAPC] D4_APC_0: 0x0
10072 22:50:23.236676 INFO: [NOCDAPC] D4_APC_1: 0xfff
10073 22:50:23.239839 INFO: [NOCDAPC] D5_APC_0: 0x0
10074 22:50:23.243022 INFO: [NOCDAPC] D5_APC_1: 0xfff
10075 22:50:23.246427 INFO: [NOCDAPC] D6_APC_0: 0x0
10076 22:50:23.249701 INFO: [NOCDAPC] D6_APC_1: 0xfff
10077 22:50:23.253111 INFO: [NOCDAPC] D7_APC_0: 0x0
10078 22:50:23.256250 INFO: [NOCDAPC] D7_APC_1: 0xfff
10079 22:50:23.259520 INFO: [NOCDAPC] D8_APC_0: 0x0
10080 22:50:23.263138 INFO: [NOCDAPC] D8_APC_1: 0xfff
10081 22:50:23.263322 INFO: [NOCDAPC] D9_APC_0: 0x0
10082 22:50:23.266371 INFO: [NOCDAPC] D9_APC_1: 0xfff
10083 22:50:23.269511 INFO: [NOCDAPC] D10_APC_0: 0x0
10084 22:50:23.273537 INFO: [NOCDAPC] D10_APC_1: 0xfff
10085 22:50:23.276178 INFO: [NOCDAPC] D11_APC_0: 0x0
10086 22:50:23.279889 INFO: [NOCDAPC] D11_APC_1: 0xfff
10087 22:50:23.283058 INFO: [NOCDAPC] D12_APC_0: 0x0
10088 22:50:23.286405 INFO: [NOCDAPC] D12_APC_1: 0xfff
10089 22:50:23.289921 INFO: [NOCDAPC] D13_APC_0: 0x0
10090 22:50:23.293028 INFO: [NOCDAPC] D13_APC_1: 0xfff
10091 22:50:23.296496 INFO: [NOCDAPC] D14_APC_0: 0x0
10092 22:50:23.299610 INFO: [NOCDAPC] D14_APC_1: 0xfff
10093 22:50:23.302961 INFO: [NOCDAPC] D15_APC_0: 0x0
10094 22:50:23.306491 INFO: [NOCDAPC] D15_APC_1: 0xfff
10095 22:50:23.306605 INFO: [NOCDAPC] APC_CON: 0x4
10096 22:50:23.309470 INFO: [APUAPC] set_apusys_apc done
10097 22:50:23.312829 INFO: [DEVAPC] devapc_init done
10098 22:50:23.319430 INFO: GICv3 without legacy support detected.
10099 22:50:23.323179 INFO: ARM GICv3 driver initialized in EL3
10100 22:50:23.326831 INFO: Maximum SPI INTID supported: 639
10101 22:50:23.330012 INFO: BL31: Initializing runtime services
10102 22:50:23.336220 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10103 22:50:23.339853 INFO: SPM: enable CPC mode
10104 22:50:23.343119 INFO: mcdi ready for mcusys-off-idle and system suspend
10105 22:50:23.349969 INFO: BL31: Preparing for EL3 exit to normal world
10106 22:50:23.352995 INFO: Entry point address = 0x80000000
10107 22:50:23.353095 INFO: SPSR = 0x8
10108 22:50:23.359967
10109 22:50:23.360075
10110 22:50:23.360167
10111 22:50:23.363614 Starting depthcharge on Spherion...
10112 22:50:23.363721
10113 22:50:23.363812 Wipe memory regions:
10114 22:50:23.363898
10115 22:50:23.364756 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10116 22:50:23.364892 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10117 22:50:23.365007 Setting prompt string to ['asurada:']
10118 22:50:23.365128 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10119 22:50:23.366289 [0x00000040000000, 0x00000054600000)
10120 22:50:23.489398
10121 22:50:23.490107 [0x00000054660000, 0x00000080000000)
10122 22:50:23.749496
10123 22:50:23.749652 [0x000000821a7280, 0x000000ffe64000)
10124 22:50:24.493912
10125 22:50:24.494090 [0x00000100000000, 0x00000240000000)
10126 22:50:26.384679
10127 22:50:26.387496 Initializing XHCI USB controller at 0x11200000.
10128 22:50:27.425418
10129 22:50:27.428541 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10130 22:50:27.428649
10131 22:50:27.428741
10132 22:50:27.428828
10133 22:50:27.429139 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10135 22:50:27.529495 asurada: tftpboot 192.168.201.1 13683654/tftp-deploy-_j5d1c4q/kernel/image.itb 13683654/tftp-deploy-_j5d1c4q/kernel/cmdline
10136 22:50:27.529637 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10137 22:50:27.529732 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10138 22:50:27.534250 tftpboot 192.168.201.1 13683654/tftp-deploy-_j5d1c4q/kernel/image.itp-deploy-_j5d1c4q/kernel/cmdline
10139 22:50:27.534354
10140 22:50:27.534444 Waiting for link
10141 22:50:27.694226
10142 22:50:27.694344 R8152: Initializing
10143 22:50:27.694412
10144 22:50:27.697956 Version 6 (ocp_data = 5c30)
10145 22:50:27.698116
10146 22:50:27.701087 R8152: Done initializing
10147 22:50:27.701157
10148 22:50:27.701248 Adding net device
10149 22:50:29.792760
10150 22:50:29.792933 done.
10151 22:50:29.793035
10152 22:50:29.793125 MAC: 00:24:32:30:78:52
10153 22:50:29.793216
10154 22:50:29.796072 Sending DHCP discover... done.
10155 22:50:29.796166
10156 22:50:34.978310 Waiting for reply... done.
10157 22:50:34.978477
10158 22:50:34.978575 Sending DHCP request... done.
10159 22:50:34.981625
10160 22:50:34.986010 Waiting for reply... done.
10161 22:50:34.986099
10162 22:50:34.986197 My ip is 192.168.201.14
10163 22:50:34.986284
10164 22:50:34.989412 The DHCP server ip is 192.168.201.1
10165 22:50:34.989488
10166 22:50:34.995956 TFTP server IP predefined by user: 192.168.201.1
10167 22:50:34.996059
10168 22:50:35.002562 Bootfile predefined by user: 13683654/tftp-deploy-_j5d1c4q/kernel/image.itb
10169 22:50:35.002671
10170 22:50:35.002766 Sending tftp read request... done.
10171 22:50:35.006069
10172 22:50:35.009856 Waiting for the transfer...
10173 22:50:35.009952
10174 22:50:35.548750 00000000 ################################################################
10175 22:50:35.548891
10176 22:50:36.094438 00080000 ################################################################
10177 22:50:36.094584
10178 22:50:36.631302 00100000 ################################################################
10179 22:50:36.631467
10180 22:50:37.191332 00180000 ################################################################
10181 22:50:37.191536
10182 22:50:37.718482 00200000 ################################################################
10183 22:50:37.718625
10184 22:50:38.246554 00280000 ################################################################
10185 22:50:38.246695
10186 22:50:38.814551 00300000 ################################################################
10187 22:50:38.814689
10188 22:50:39.383346 00380000 ################################################################
10189 22:50:39.383486
10190 22:50:40.042300 00400000 ################################################################
10191 22:50:40.042812
10192 22:50:40.736591 00480000 ################################################################
10193 22:50:40.737108
10194 22:50:41.409069 00500000 ################################################################
10195 22:50:41.409271
10196 22:50:41.979169 00580000 ################################################################
10197 22:50:41.979308
10198 22:50:42.554179 00600000 ################################################################
10199 22:50:42.554310
10200 22:50:43.145158 00680000 ################################################################
10201 22:50:43.145316
10202 22:50:43.725345 00700000 ################################################################
10203 22:50:43.725487
10204 22:50:44.357421 00780000 ################################################################
10205 22:50:44.357552
10206 22:50:44.910968 00800000 ################################################################
10207 22:50:44.911166
10208 22:50:45.505122 00880000 ################################################################
10209 22:50:45.505306
10210 22:50:46.160956 00900000 ################################################################
10211 22:50:46.161506
10212 22:50:46.806173 00980000 ################################################################
10213 22:50:46.806321
10214 22:50:47.445556 00a00000 ################################################################
10215 22:50:47.445703
10216 22:50:48.089901 00a80000 ################################################################
10217 22:50:48.090048
10218 22:50:48.730427 00b00000 ################################################################
10219 22:50:48.730572
10220 22:50:49.306703 00b80000 ################################################################
10221 22:50:49.306856
10222 22:50:49.983574 00c00000 ################################################################
10223 22:50:49.984083
10224 22:50:50.631512 00c80000 ################################################################
10225 22:50:50.631658
10226 22:50:51.217427 00d00000 ################################################################
10227 22:50:51.217571
10228 22:50:51.836651 00d80000 ################################################################
10229 22:50:51.836799
10230 22:50:52.437745 00e00000 ################################################################
10231 22:50:52.437924
10232 22:50:53.023538 00e80000 ################################################################
10233 22:50:53.023682
10234 22:50:53.652799 00f00000 ################################################################
10235 22:50:53.652946
10236 22:50:54.243825 00f80000 ################################################################
10237 22:50:54.244022
10238 22:50:54.922051 01000000 ################################################################
10239 22:50:54.922574
10240 22:50:55.595333 01080000 ################################################################
10241 22:50:55.595884
10242 22:50:56.281006 01100000 ################################################################
10243 22:50:56.281555
10244 22:50:56.977631 01180000 ################################################################
10245 22:50:56.978145
10246 22:50:57.678723 01200000 ################################################################
10247 22:50:57.679233
10248 22:50:58.381562 01280000 ################################################################
10249 22:50:58.382076
10250 22:50:59.062860 01300000 ################################################################
10251 22:50:59.063369
10252 22:50:59.745093 01380000 ################################################################
10253 22:50:59.745781
10254 22:51:00.339918 01400000 ################################################################
10255 22:51:00.340064
10256 22:51:00.939235 01480000 ################################################################
10257 22:51:00.939378
10258 22:51:01.577493 01500000 ################################################################
10259 22:51:01.577634
10260 22:51:02.200502 01580000 ################################################################
10261 22:51:02.200655
10262 22:51:02.878138 01600000 ################################################################
10263 22:51:02.878283
10264 22:51:03.518685 01680000 ################################################################
10265 22:51:03.518831
10266 22:51:04.178364 01700000 ################################################################
10267 22:51:04.178862
10268 22:51:04.756967 01780000 ################################################################
10269 22:51:04.757140
10270 22:51:05.288576 01800000 ################################################################
10271 22:51:05.288717
10272 22:51:05.850935 01880000 ################################################################
10273 22:51:05.851092
10274 22:51:06.417878 01900000 ################################################################
10275 22:51:06.418025
10276 22:51:06.976192 01980000 ################################################################
10277 22:51:06.976345
10278 22:51:07.520268 01a00000 ################################################################
10279 22:51:07.520424
10280 22:51:08.067810 01a80000 ################################################################
10281 22:51:08.067957
10282 22:51:08.596966 01b00000 ################################################################
10283 22:51:08.597119
10284 22:51:09.159929 01b80000 ################################################################
10285 22:51:09.160079
10286 22:51:09.715600 01c00000 ################################################################
10287 22:51:09.715775
10288 22:51:10.263430 01c80000 ################################################################
10289 22:51:10.263577
10290 22:51:10.821476 01d00000 ################################################################
10291 22:51:10.821613
10292 22:51:11.374369 01d80000 ################################################################
10293 22:51:11.374517
10294 22:51:11.782636 01e00000 ############################################### done.
10295 22:51:11.782784
10296 22:51:11.785761 The bootfile was 31834350 bytes long.
10297 22:51:11.785846
10298 22:51:11.789247 Sending tftp read request... done.
10299 22:51:11.789331
10300 22:51:11.789396 Waiting for the transfer...
10301 22:51:11.789456
10302 22:51:11.792549 00000000 # done.
10303 22:51:11.792633
10304 22:51:11.798870 Command line loaded dynamically from TFTP file: 13683654/tftp-deploy-_j5d1c4q/kernel/cmdline
10305 22:51:11.798952
10306 22:51:11.822741 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683654/extract-nfsrootfs-a6eey1um,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10307 22:51:11.822829
10308 22:51:11.822894 Loading FIT.
10309 22:51:11.822954
10310 22:51:11.825792 Image ramdisk-1 has 18725504 bytes.
10311 22:51:11.825873
10312 22:51:11.829402 Image fdt-1 has 47258 bytes.
10313 22:51:11.829483
10314 22:51:11.832235 Image kernel-1 has 13059555 bytes.
10315 22:51:11.832315
10316 22:51:11.842184 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10317 22:51:11.842266
10318 22:51:11.859244 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10319 22:51:11.859332
10320 22:51:11.862353 Choosing best match conf-1 for compat google,spherion-rev2.
10321 22:51:11.868111
10322 22:51:11.872496 Connected to device vid:did:rid of 1ae0:0028:00
10323 22:51:11.880641
10324 22:51:11.883917 tpm_get_response: command 0x17b, return code 0x0
10325 22:51:11.884001
10326 22:51:11.887811 ec_init: CrosEC protocol v3 supported (256, 248)
10327 22:51:11.891314
10328 22:51:11.895155 tpm_cleanup: add release locality here.
10329 22:51:11.895238
10330 22:51:11.895302 Shutting down all USB controllers.
10331 22:51:11.897915
10332 22:51:11.897997 Removing current net device
10333 22:51:11.898062
10334 22:51:11.904808 Exiting depthcharge with code 4 at timestamp: 77944491
10335 22:51:11.904891
10336 22:51:11.908063 LZMA decompressing kernel-1 to 0x821a6718
10337 22:51:11.908145
10338 22:51:11.911357 LZMA decompressing kernel-1 to 0x40000000
10339 22:51:13.523073
10340 22:51:13.523229 jumping to kernel
10341 22:51:13.523686 end: 2.2.4 bootloader-commands (duration 00:00:50) [common]
10342 22:51:13.523786 start: 2.2.5 auto-login-action (timeout 00:03:35) [common]
10343 22:51:13.523860 Setting prompt string to ['Linux version [0-9]']
10344 22:51:13.523926 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10345 22:51:13.523992 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10346 22:51:13.605526
10347 22:51:13.609048 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10348 22:51:13.612036 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10349 22:51:13.612130 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10350 22:51:13.612200 Setting prompt string to []
10351 22:51:13.612277 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10352 22:51:13.612351 Using line separator: #'\n'#
10353 22:51:13.612409 No login prompt set.
10354 22:51:13.612468 Parsing kernel messages
10355 22:51:13.612522 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10356 22:51:13.612619 [login-action] Waiting for messages, (timeout 00:03:35)
10357 22:51:13.612681 Waiting using forced prompt support (timeout 00:01:47)
10358 22:51:13.631645 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10359 22:51:13.635146 [ 0.000000] random: crng init done
10360 22:51:13.642868 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10361 22:51:13.642959 [ 0.000000] efi: UEFI not found.
10362 22:51:13.652556 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10363 22:51:13.658436 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10364 22:51:13.668883 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10365 22:51:13.679269 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10366 22:51:13.685136 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10367 22:51:13.688685 [ 0.000000] printk: bootconsole [mtk8250] enabled
10368 22:51:13.697258 [ 0.000000] NUMA: No NUMA configuration found
10369 22:51:13.703920 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10370 22:51:13.710806 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10371 22:51:13.710889 [ 0.000000] Zone ranges:
10372 22:51:13.717251 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10373 22:51:13.720289 [ 0.000000] DMA32 empty
10374 22:51:13.726966 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10375 22:51:13.730984 [ 0.000000] Movable zone start for each node
10376 22:51:13.733760 [ 0.000000] Early memory node ranges
10377 22:51:13.740330 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10378 22:51:13.747422 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10379 22:51:13.754464 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10380 22:51:13.760779 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10381 22:51:13.764509 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10382 22:51:13.773908 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10383 22:51:13.830096 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10384 22:51:13.836201 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10385 22:51:13.842882 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10386 22:51:13.846255 [ 0.000000] psci: probing for conduit method from DT.
10387 22:51:13.852754 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10388 22:51:13.856133 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10389 22:51:13.862922 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10390 22:51:13.866271 [ 0.000000] psci: SMC Calling Convention v1.2
10391 22:51:13.872968 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10392 22:51:13.876207 [ 0.000000] Detected VIPT I-cache on CPU0
10393 22:51:13.883194 [ 0.000000] CPU features: detected: GIC system register CPU interface
10394 22:51:13.889243 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10395 22:51:13.896317 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10396 22:51:13.902710 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10397 22:51:13.909468 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10398 22:51:13.916219 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10399 22:51:13.922614 [ 0.000000] alternatives: applying boot alternatives
10400 22:51:13.929193 [ 0.000000] Fallback order for Node 0: 0
10401 22:51:13.936152 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10402 22:51:13.936238 [ 0.000000] Policy zone: Normal
10403 22:51:13.959505 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683654/extract-nfsrootfs-a6eey1um,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10404 22:51:13.972489 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10405 22:51:13.983072 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10406 22:51:13.992928 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10407 22:51:13.999260 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10408 22:51:14.002343 <6>[ 0.000000] software IO TLB: area num 8.
10409 22:51:14.059530 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10410 22:51:14.209695 <6>[ 0.000000] Memory: 7945904K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406864K reserved, 32768K cma-reserved)
10411 22:51:14.216748 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10412 22:51:14.223212 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10413 22:51:14.226934 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10414 22:51:14.232809 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10415 22:51:14.239299 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10416 22:51:14.242795 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10417 22:51:14.252631 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10418 22:51:14.259575 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10419 22:51:14.262724 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10420 22:51:14.270501 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10421 22:51:14.274125 <6>[ 0.000000] GICv3: 608 SPIs implemented
10422 22:51:14.281091 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10423 22:51:14.284043 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10424 22:51:14.287572 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10425 22:51:14.294130 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10426 22:51:14.307488 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10427 22:51:14.320696 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10428 22:51:14.327504 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10429 22:51:14.336460 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10430 22:51:14.349161 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10431 22:51:14.355897 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10432 22:51:14.362762 <6>[ 0.009183] Console: colour dummy device 80x25
10433 22:51:14.372626 <6>[ 0.013938] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10434 22:51:14.375846 <6>[ 0.024445] pid_max: default: 32768 minimum: 301
10435 22:51:14.382807 <6>[ 0.029346] LSM: Security Framework initializing
10436 22:51:14.389330 <6>[ 0.034283] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10437 22:51:14.399592 <6>[ 0.042097] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10438 22:51:14.405920 <6>[ 0.051521] cblist_init_generic: Setting adjustable number of callback queues.
10439 22:51:14.412989 <6>[ 0.058963] cblist_init_generic: Setting shift to 3 and lim to 1.
10440 22:51:14.419303 <6>[ 0.065304] cblist_init_generic: Setting adjustable number of callback queues.
10441 22:51:14.426389 <6>[ 0.072777] cblist_init_generic: Setting shift to 3 and lim to 1.
10442 22:51:14.432500 <6>[ 0.079216] rcu: Hierarchical SRCU implementation.
10443 22:51:14.439147 <6>[ 0.084230] rcu: Max phase no-delay instances is 1000.
10444 22:51:14.443023 <6>[ 0.091250] EFI services will not be available.
10445 22:51:14.449487 <6>[ 0.096210] smp: Bringing up secondary CPUs ...
10446 22:51:14.456756 <6>[ 0.101291] Detected VIPT I-cache on CPU1
10447 22:51:14.463525 <6>[ 0.101362] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10448 22:51:14.470165 <6>[ 0.101393] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10449 22:51:14.473523 <6>[ 0.101731] Detected VIPT I-cache on CPU2
10450 22:51:14.480281 <6>[ 0.101780] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10451 22:51:14.486702 <6>[ 0.101795] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10452 22:51:14.493626 <6>[ 0.102059] Detected VIPT I-cache on CPU3
10453 22:51:14.500267 <6>[ 0.102106] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10454 22:51:14.507135 <6>[ 0.102121] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10455 22:51:14.510328 <6>[ 0.102428] CPU features: detected: Spectre-v4
10456 22:51:14.517044 <6>[ 0.102434] CPU features: detected: Spectre-BHB
10457 22:51:14.519953 <6>[ 0.102439] Detected PIPT I-cache on CPU4
10458 22:51:14.526766 <6>[ 0.102499] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10459 22:51:14.533414 <6>[ 0.102515] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10460 22:51:14.540239 <6>[ 0.102811] Detected PIPT I-cache on CPU5
10461 22:51:14.546383 <6>[ 0.102874] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10462 22:51:14.553095 <6>[ 0.102890] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10463 22:51:14.556581 <6>[ 0.103172] Detected PIPT I-cache on CPU6
10464 22:51:14.563927 <6>[ 0.103236] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10465 22:51:14.570522 <6>[ 0.103252] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10466 22:51:14.573474 <6>[ 0.103549] Detected PIPT I-cache on CPU7
10467 22:51:14.583991 <6>[ 0.103614] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10468 22:51:14.590377 <6>[ 0.103630] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10469 22:51:14.593697 <6>[ 0.103678] smp: Brought up 1 node, 8 CPUs
10470 22:51:14.596735 <6>[ 0.245137] SMP: Total of 8 processors activated.
10471 22:51:14.603542 <6>[ 0.250089] CPU features: detected: 32-bit EL0 Support
10472 22:51:14.613552 <6>[ 0.255452] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10473 22:51:14.619925 <6>[ 0.264252] CPU features: detected: Common not Private translations
10474 22:51:14.623687 <6>[ 0.270768] CPU features: detected: CRC32 instructions
10475 22:51:14.630099 <6>[ 0.276153] CPU features: detected: RCpc load-acquire (LDAPR)
10476 22:51:14.636505 <6>[ 0.282120] CPU features: detected: LSE atomic instructions
10477 22:51:14.643708 <6>[ 0.287938] CPU features: detected: Privileged Access Never
10478 22:51:14.646702 <6>[ 0.293717] CPU features: detected: RAS Extension Support
10479 22:51:14.653484 <6>[ 0.299326] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10480 22:51:14.659685 <6>[ 0.306546] CPU: All CPU(s) started at EL2
10481 22:51:14.663184 <6>[ 0.310862] alternatives: applying system-wide alternatives
10482 22:51:14.674667 <6>[ 0.321737] devtmpfs: initialized
10483 22:51:14.687249 <6>[ 0.330677] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10484 22:51:14.698078 <6>[ 0.340640] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10485 22:51:14.703567 <6>[ 0.348852] pinctrl core: initialized pinctrl subsystem
10486 22:51:14.707154 <6>[ 0.355491] DMI not present or invalid.
10487 22:51:14.713949 <6>[ 0.359905] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10488 22:51:14.724738 <6>[ 0.366730] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10489 22:51:14.730320 <6>[ 0.374320] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10490 22:51:14.740438 <6>[ 0.382549] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10491 22:51:14.743561 <6>[ 0.390791] audit: initializing netlink subsys (disabled)
10492 22:51:14.753554 <5>[ 0.396484] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10493 22:51:14.760630 <6>[ 0.397182] thermal_sys: Registered thermal governor 'step_wise'
10494 22:51:14.767356 <6>[ 0.404451] thermal_sys: Registered thermal governor 'power_allocator'
10495 22:51:14.770511 <6>[ 0.410706] cpuidle: using governor menu
10496 22:51:14.773922 <6>[ 0.421666] NET: Registered PF_QIPCRTR protocol family
10497 22:51:14.783624 <6>[ 0.427152] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10498 22:51:14.786702 <6>[ 0.434258] ASID allocator initialised with 32768 entries
10499 22:51:14.793980 <6>[ 0.440824] Serial: AMBA PL011 UART driver
10500 22:51:14.803314 <4>[ 0.449540] Trying to register duplicate clock ID: 134
10501 22:51:14.861047 <6>[ 0.511015] KASLR enabled
10502 22:51:14.875371 <6>[ 0.518782] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10503 22:51:14.882078 <6>[ 0.525797] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10504 22:51:14.888600 <6>[ 0.532286] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10505 22:51:14.895675 <6>[ 0.539293] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10506 22:51:14.902167 <6>[ 0.545780] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10507 22:51:14.908858 <6>[ 0.552788] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10508 22:51:14.915302 <6>[ 0.559277] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10509 22:51:14.922096 <6>[ 0.566283] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10510 22:51:14.925491 <6>[ 0.573794] ACPI: Interpreter disabled.
10511 22:51:14.933365 <6>[ 0.580220] iommu: Default domain type: Translated
10512 22:51:14.940444 <6>[ 0.585335] iommu: DMA domain TLB invalidation policy: strict mode
10513 22:51:14.943258 <5>[ 0.591993] SCSI subsystem initialized
10514 22:51:14.950110 <6>[ 0.596156] usbcore: registered new interface driver usbfs
10515 22:51:14.956835 <6>[ 0.601887] usbcore: registered new interface driver hub
10516 22:51:14.959867 <6>[ 0.607437] usbcore: registered new device driver usb
10517 22:51:14.966587 <6>[ 0.613541] pps_core: LinuxPPS API ver. 1 registered
10518 22:51:14.976837 <6>[ 0.618735] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10519 22:51:14.980125 <6>[ 0.628083] PTP clock support registered
10520 22:51:14.983227 <6>[ 0.632325] EDAC MC: Ver: 3.0.0
10521 22:51:14.990718 <6>[ 0.637481] FPGA manager framework
10522 22:51:14.994081 <6>[ 0.641169] Advanced Linux Sound Architecture Driver Initialized.
10523 22:51:14.997529 <6>[ 0.647945] vgaarb: loaded
10524 22:51:15.004617 <6>[ 0.651044] clocksource: Switched to clocksource arch_sys_counter
10525 22:51:15.010995 <5>[ 0.657481] VFS: Disk quotas dquot_6.6.0
10526 22:51:15.018377 <6>[ 0.661664] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10527 22:51:15.021188 <6>[ 0.668851] pnp: PnP ACPI: disabled
10528 22:51:15.028411 <6>[ 0.675529] NET: Registered PF_INET protocol family
10529 22:51:15.039290 <6>[ 0.681126] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10530 22:51:15.050166 <6>[ 0.693448] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10531 22:51:15.059821 <6>[ 0.702266] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10532 22:51:15.066583 <6>[ 0.710239] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10533 22:51:15.072910 <6>[ 0.718938] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10534 22:51:15.085485 <6>[ 0.728694] TCP: Hash tables configured (established 65536 bind 65536)
10535 22:51:15.091714 <6>[ 0.735562] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10536 22:51:15.098619 <6>[ 0.742763] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10537 22:51:15.105078 <6>[ 0.750466] NET: Registered PF_UNIX/PF_LOCAL protocol family
10538 22:51:15.111677 <6>[ 0.756625] RPC: Registered named UNIX socket transport module.
10539 22:51:15.115327 <6>[ 0.762778] RPC: Registered udp transport module.
10540 22:51:15.122156 <6>[ 0.767713] RPC: Registered tcp transport module.
10541 22:51:15.128330 <6>[ 0.772643] RPC: Registered tcp NFSv4.1 backchannel transport module.
10542 22:51:15.131460 <6>[ 0.779309] PCI: CLS 0 bytes, default 64
10543 22:51:15.134866 <6>[ 0.783638] Unpacking initramfs...
10544 22:51:15.159698 <6>[ 0.803167] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10545 22:51:15.169998 <6>[ 0.811845] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10546 22:51:15.173001 <6>[ 0.820722] kvm [1]: IPA Size Limit: 40 bits
10547 22:51:15.179556 <6>[ 0.825252] kvm [1]: GICv3: no GICV resource entry
10548 22:51:15.183177 <6>[ 0.830273] kvm [1]: disabling GICv2 emulation
10549 22:51:15.189838 <6>[ 0.834962] kvm [1]: GIC system register CPU interface enabled
10550 22:51:15.192717 <6>[ 0.841134] kvm [1]: vgic interrupt IRQ18
10551 22:51:15.201019 <6>[ 0.845489] kvm [1]: VHE mode initialized successfully
10552 22:51:15.206361 <5>[ 0.851981] Initialise system trusted keyrings
10553 22:51:15.212757 <6>[ 0.856817] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10554 22:51:15.220332 <6>[ 0.866887] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10555 22:51:15.227073 <5>[ 0.873337] NFS: Registering the id_resolver key type
10556 22:51:15.230096 <5>[ 0.878643] Key type id_resolver registered
10557 22:51:15.236467 <5>[ 0.883057] Key type id_legacy registered
10558 22:51:15.243296 <6>[ 0.887336] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10559 22:51:15.250227 <6>[ 0.894257] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10560 22:51:15.257447 <6>[ 0.901978] 9p: Installing v9fs 9p2000 file system support
10561 22:51:15.293459 <5>[ 0.939976] Key type asymmetric registered
10562 22:51:15.296218 <5>[ 0.944307] Asymmetric key parser 'x509' registered
10563 22:51:15.306265 <6>[ 0.949473] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10564 22:51:15.309622 <6>[ 0.957094] io scheduler mq-deadline registered
10565 22:51:15.313149 <6>[ 0.961872] io scheduler kyber registered
10566 22:51:15.332148 <6>[ 0.978851] EINJ: ACPI disabled.
10567 22:51:15.364735 <4>[ 1.004905] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 22:51:15.374787 <4>[ 1.015538] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10569 22:51:15.389642 <6>[ 1.036596] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10570 22:51:15.397444 <6>[ 1.044610] printk: console [ttyS0] disabled
10571 22:51:15.426197 <6>[ 1.069238] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10572 22:51:15.432640 <6>[ 1.078714] printk: console [ttyS0] enabled
10573 22:51:15.436021 <6>[ 1.078714] printk: console [ttyS0] enabled
10574 22:51:15.442441 <6>[ 1.087610] printk: bootconsole [mtk8250] disabled
10575 22:51:15.445680 <6>[ 1.087610] printk: bootconsole [mtk8250] disabled
10576 22:51:15.452273 <6>[ 1.098857] SuperH (H)SCI(F) driver initialized
10577 22:51:15.455464 <6>[ 1.104142] msm_serial: driver initialized
10578 22:51:15.469796 <6>[ 1.113101] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10579 22:51:15.479927 <6>[ 1.121660] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10580 22:51:15.486367 <6>[ 1.130204] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10581 22:51:15.496517 <6>[ 1.138832] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10582 22:51:15.502675 <6>[ 1.147538] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10583 22:51:15.512690 <6>[ 1.156251] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10584 22:51:15.522442 <6>[ 1.164804] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10585 22:51:15.529995 <6>[ 1.173613] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10586 22:51:15.539143 <6>[ 1.182154] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10587 22:51:15.551048 <6>[ 1.197883] loop: module loaded
10588 22:51:15.557454 <6>[ 1.203868] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10589 22:51:15.580124 <4>[ 1.227199] mtk-pmic-keys: Failed to locate of_node [id: -1]
10590 22:51:15.587206 <6>[ 1.234151] megasas: 07.719.03.00-rc1
10591 22:51:15.596922 <6>[ 1.243874] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10592 22:51:15.603650 <6>[ 1.250433] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10593 22:51:15.620694 <6>[ 1.266881] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10594 22:51:15.676761 <6>[ 1.317103] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10595 22:51:15.929560 <6>[ 1.576162] Freeing initrd memory: 18280K
10596 22:51:15.940965 <6>[ 1.587781] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10597 22:51:15.951573 <6>[ 1.598678] tun: Universal TUN/TAP device driver, 1.6
10598 22:51:15.955367 <6>[ 1.604741] thunder_xcv, ver 1.0
10599 22:51:15.958548 <6>[ 1.608245] thunder_bgx, ver 1.0
10600 22:51:15.961981 <6>[ 1.611738] nicpf, ver 1.0
10601 22:51:15.972291 <6>[ 1.615757] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10602 22:51:15.975471 <6>[ 1.623234] hns3: Copyright (c) 2017 Huawei Corporation.
10603 22:51:15.978736 <6>[ 1.628824] hclge is initializing
10604 22:51:15.986010 <6>[ 1.632396] e1000: Intel(R) PRO/1000 Network Driver
10605 22:51:15.992045 <6>[ 1.637525] e1000: Copyright (c) 1999-2006 Intel Corporation.
10606 22:51:15.996516 <6>[ 1.643536] e1000e: Intel(R) PRO/1000 Network Driver
10607 22:51:16.002213 <6>[ 1.648752] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10608 22:51:16.008916 <6>[ 1.654940] igb: Intel(R) Gigabit Ethernet Network Driver
10609 22:51:16.015494 <6>[ 1.660590] igb: Copyright (c) 2007-2014 Intel Corporation.
10610 22:51:16.021963 <6>[ 1.666427] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10611 22:51:16.025620 <6>[ 1.672945] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10612 22:51:16.032483 <6>[ 1.679420] sky2: driver version 1.30
10613 22:51:16.039049 <6>[ 1.684345] usbcore: registered new device driver r8152-cfgselector
10614 22:51:16.045752 <6>[ 1.690879] usbcore: registered new interface driver r8152
10615 22:51:16.048848 <6>[ 1.696700] VFIO - User Level meta-driver version: 0.3
10616 22:51:16.058050 <6>[ 1.704925] usbcore: registered new interface driver usb-storage
10617 22:51:16.064889 <6>[ 1.711367] usbcore: registered new device driver onboard-usb-hub
10618 22:51:16.073571 <6>[ 1.720549] mt6397-rtc mt6359-rtc: registered as rtc0
10619 22:51:16.083672 <6>[ 1.726023] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:51:17 UTC (1715122277)
10620 22:51:16.087174 <6>[ 1.735614] i2c_dev: i2c /dev entries driver
10621 22:51:16.104004 <6>[ 1.747425] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10622 22:51:16.110750 <4>[ 1.756151] cpu cpu0: supply cpu not found, using dummy regulator
10623 22:51:16.117614 <4>[ 1.762581] cpu cpu1: supply cpu not found, using dummy regulator
10624 22:51:16.124026 <4>[ 1.768992] cpu cpu2: supply cpu not found, using dummy regulator
10625 22:51:16.130698 <4>[ 1.775408] cpu cpu3: supply cpu not found, using dummy regulator
10626 22:51:16.138178 <4>[ 1.781802] cpu cpu4: supply cpu not found, using dummy regulator
10627 22:51:16.144530 <4>[ 1.788201] cpu cpu5: supply cpu not found, using dummy regulator
10628 22:51:16.147461 <4>[ 1.794597] cpu cpu6: supply cpu not found, using dummy regulator
10629 22:51:16.153989 <4>[ 1.800992] cpu cpu7: supply cpu not found, using dummy regulator
10630 22:51:16.174711 <6>[ 1.821619] cpu cpu0: EM: created perf domain
10631 22:51:16.178305 <6>[ 1.826554] cpu cpu4: EM: created perf domain
10632 22:51:16.185574 <6>[ 1.832124] sdhci: Secure Digital Host Controller Interface driver
10633 22:51:16.191907 <6>[ 1.838557] sdhci: Copyright(c) Pierre Ossman
10634 22:51:16.198489 <6>[ 1.843516] Synopsys Designware Multimedia Card Interface Driver
10635 22:51:16.205202 <6>[ 1.850149] sdhci-pltfm: SDHCI platform and OF driver helper
10636 22:51:16.208526 <6>[ 1.850207] mmc0: CQHCI version 5.10
10637 22:51:16.215431 <6>[ 1.860247] ledtrig-cpu: registered to indicate activity on CPUs
10638 22:51:16.222737 <6>[ 1.867285] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10639 22:51:16.228551 <6>[ 1.874324] usbcore: registered new interface driver usbhid
10640 22:51:16.232135 <6>[ 1.880146] usbhid: USB HID core driver
10641 22:51:16.238659 <6>[ 1.884345] spi_master spi0: will run message pump with realtime priority
10642 22:51:16.282026 <6>[ 1.922209] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10643 22:51:16.301335 <6>[ 1.938140] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10644 22:51:16.304956 <6>[ 1.951714] mmc0: Command Queue Engine enabled
10645 22:51:16.311942 <6>[ 1.956481] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10646 22:51:16.318209 <6>[ 1.963408] cros-ec-spi spi0.0: Chrome EC device registered
10647 22:51:16.321875 <6>[ 1.963736] mmcblk0: mmc0:0001 DA4128 116 GiB
10648 22:51:16.331043 <6>[ 1.978046] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10649 22:51:16.338547 <6>[ 1.985405] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10650 22:51:16.345048 <6>[ 1.991268] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10651 22:51:16.351556 <6>[ 1.997147] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10652 22:51:16.368442 <6>[ 2.011605] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10653 22:51:16.375618 <6>[ 2.022607] NET: Registered PF_PACKET protocol family
10654 22:51:16.378765 <6>[ 2.028009] 9pnet: Installing 9P2000 support
10655 22:51:16.385765 <5>[ 2.032575] Key type dns_resolver registered
10656 22:51:16.388763 <6>[ 2.037550] registered taskstats version 1
10657 22:51:16.395640 <5>[ 2.041928] Loading compiled-in X.509 certificates
10658 22:51:16.427784 <4>[ 2.067911] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10659 22:51:16.437581 <4>[ 2.078747] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10660 22:51:16.444392 <3>[ 2.089300] debugfs: File 'uA_load' in directory '/' already present!
10661 22:51:16.451543 <3>[ 2.096011] debugfs: File 'min_uV' in directory '/' already present!
10662 22:51:16.457792 <3>[ 2.102623] debugfs: File 'max_uV' in directory '/' already present!
10663 22:51:16.464467 <3>[ 2.109233] debugfs: File 'constraint_flags' in directory '/' already present!
10664 22:51:16.479643 <6>[ 2.126627] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10665 22:51:16.487109 <6>[ 2.133569] xhci-mtk 11200000.usb: xHCI Host Controller
10666 22:51:16.493008 <6>[ 2.139064] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10667 22:51:16.503201 <6>[ 2.146916] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10668 22:51:16.509957 <6>[ 2.156341] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10669 22:51:16.517120 <6>[ 2.162405] xhci-mtk 11200000.usb: xHCI Host Controller
10670 22:51:16.523777 <6>[ 2.167883] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10671 22:51:16.530282 <6>[ 2.175532] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10672 22:51:16.536798 <6>[ 2.183208] hub 1-0:1.0: USB hub found
10673 22:51:16.540083 <6>[ 2.187225] hub 1-0:1.0: 1 port detected
10674 22:51:16.547273 <6>[ 2.191505] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10675 22:51:16.553849 <6>[ 2.200025] hub 2-0:1.0: USB hub found
10676 22:51:16.556785 <6>[ 2.204034] hub 2-0:1.0: 1 port detected
10677 22:51:16.563541 <6>[ 2.210349] mtk-msdc 11f70000.mmc: Got CD GPIO
10678 22:51:16.577336 <6>[ 2.220827] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10679 22:51:16.584078 <6>[ 2.228853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10680 22:51:16.593714 <4>[ 2.236766] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10681 22:51:16.603769 <6>[ 2.246299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10682 22:51:16.611180 <6>[ 2.254375] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10683 22:51:16.617198 <6>[ 2.262413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10684 22:51:16.627188 <6>[ 2.270334] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10685 22:51:16.634126 <6>[ 2.278150] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10686 22:51:16.644025 <6>[ 2.285967] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10687 22:51:16.654379 <6>[ 2.296229] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10688 22:51:16.660363 <6>[ 2.304588] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10689 22:51:16.670657 <6>[ 2.312942] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10690 22:51:16.677601 <6>[ 2.321281] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10691 22:51:16.687090 <6>[ 2.329618] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10692 22:51:16.694070 <6>[ 2.337955] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10693 22:51:16.703806 <6>[ 2.346293] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10694 22:51:16.710221 <6>[ 2.354632] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10695 22:51:16.720243 <6>[ 2.362969] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10696 22:51:16.726981 <6>[ 2.371308] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10697 22:51:16.736903 <6>[ 2.379646] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10698 22:51:16.743564 <6>[ 2.387983] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10699 22:51:16.753557 <6>[ 2.396320] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10700 22:51:16.760020 <6>[ 2.404658] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10701 22:51:16.770104 <6>[ 2.412995] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10702 22:51:16.776356 <6>[ 2.421734] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10703 22:51:16.783187 <6>[ 2.428969] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10704 22:51:16.790017 <6>[ 2.435819] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10705 22:51:16.796641 <6>[ 2.442649] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10706 22:51:16.803061 <6>[ 2.449675] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10707 22:51:16.812984 <6>[ 2.456582] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10708 22:51:16.823295 <6>[ 2.465727] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10709 22:51:16.832921 <6>[ 2.474846] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10710 22:51:16.843031 <6>[ 2.484145] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10711 22:51:16.849248 <6>[ 2.493612] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10712 22:51:16.859206 <6>[ 2.503079] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10713 22:51:16.869100 <6>[ 2.512198] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10714 22:51:16.879200 <6>[ 2.521664] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10715 22:51:16.888678 <6>[ 2.530785] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10716 22:51:16.898786 <6>[ 2.540079] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10717 22:51:16.908871 <6>[ 2.550239] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10718 22:51:16.918547 <6>[ 2.561655] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10719 22:51:16.925257 <6>[ 2.571446] Trying to probe devices needed for running init ...
10720 22:51:16.971256 <6>[ 2.615334] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10721 22:51:17.126034 <6>[ 2.772614] hub 1-1:1.0: USB hub found
10722 22:51:17.129001 <6>[ 2.777062] hub 1-1:1.0: 4 ports detected
10723 22:51:17.138361 <6>[ 2.785484] hub 1-1:1.0: USB hub found
10724 22:51:17.141312 <6>[ 2.789794] hub 1-1:1.0: 4 ports detected
10725 22:51:17.251971 <6>[ 2.895746] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10726 22:51:17.280245 <6>[ 2.926809] hub 2-1:1.0: USB hub found
10727 22:51:17.282966 <6>[ 2.931371] hub 2-1:1.0: 3 ports detected
10728 22:51:17.293229 <6>[ 2.940557] hub 2-1:1.0: USB hub found
10729 22:51:17.296472 <6>[ 2.945034] hub 2-1:1.0: 3 ports detected
10730 22:51:17.463301 <6>[ 3.107323] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10731 22:51:17.596416 <6>[ 3.243234] hub 1-1.4:1.0: USB hub found
10732 22:51:17.599789 <6>[ 3.247909] hub 1-1.4:1.0: 2 ports detected
10733 22:51:17.609088 <6>[ 3.256017] hub 1-1.4:1.0: USB hub found
10734 22:51:17.612372 <6>[ 3.260559] hub 1-1.4:1.0: 2 ports detected
10735 22:51:17.675699 <6>[ 3.319574] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10736 22:51:17.784238 <6>[ 3.428040] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10737 22:51:17.820281 <4>[ 3.464088] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10738 22:51:17.830409 <4>[ 3.473176] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10739 22:51:17.865350 <6>[ 3.512798] r8152 2-1.3:1.0 eth0: v1.12.13
10740 22:51:17.907505 <6>[ 3.551370] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10741 22:51:18.099785 <6>[ 3.743212] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10742 22:51:19.482179 <6>[ 5.129605] r8152 2-1.3:1.0 eth0: carrier on
10743 22:51:21.703232 <5>[ 5.151162] Sending DHCP requests .., OK
10744 22:51:21.710739 <6>[ 7.355480] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10745 22:51:21.713836 <6>[ 7.363775] IP-Config: Complete:
10746 22:51:21.726995 <6>[ 7.367269] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10747 22:51:21.734095 <6>[ 7.377976] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10748 22:51:21.740133 <6>[ 7.386594] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10749 22:51:21.746723 <6>[ 7.386603] nameserver0=192.168.201.1
10750 22:51:21.750397 <6>[ 7.398754] clk: Disabling unused clocks
10751 22:51:21.753951 <6>[ 7.404238] ALSA device list:
10752 22:51:21.756797 <6>[ 7.407494] No soundcards found.
10753 22:51:21.767711 <6>[ 7.415014] Freeing unused kernel memory: 8512K
10754 22:51:21.771250 <6>[ 7.420069] Run /init as init process
10755 22:51:21.781221 Loading, please wait...
10756 22:51:21.816101 Starting systemd-udevd version 252.22-1~deb12u1
10757 22:51:21.816253
10758 22:51:22.062933 <6>[ 7.706849] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10759 22:51:22.072272 <6>[ 7.716017] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10760 22:51:22.075656 <6>[ 7.717621] remoteproc remoteproc0: scp is available
10761 22:51:22.085823 <6>[ 7.724465] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10762 22:51:22.088787 <6>[ 7.729338] remoteproc remoteproc0: powering up scp
10763 22:51:22.099115 <6>[ 7.738211] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10764 22:51:22.108972 <6>[ 7.742847] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10765 22:51:22.112568 <6>[ 7.760024] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10766 22:51:22.119540 <6>[ 7.760656] mc: Linux media interface: v0.10
10767 22:51:22.125493 <4>[ 7.764534] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10768 22:51:22.132167 <4>[ 7.767626] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10769 22:51:22.139018 <3>[ 7.771879] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 22:51:22.149003 <3>[ 7.793249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 22:51:22.155329 <3>[ 7.801408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 22:51:22.162077 <6>[ 7.802304] videodev: Linux video capture interface: v2.00
10773 22:51:22.172315 <3>[ 7.811779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 22:51:22.178803 <6>[ 7.815762] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10775 22:51:22.185646 <3>[ 7.823869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 22:51:22.195566 <3>[ 7.839269] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10777 22:51:22.202134 <3>[ 7.847358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 22:51:22.212186 <3>[ 7.855438] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 22:51:22.221910 <6>[ 7.861077] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10780 22:51:22.229468 <3>[ 7.863572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 22:51:22.236618 <4>[ 7.865655] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10782 22:51:22.243387 <4>[ 7.865655] Fallback method does not support PEC.
10783 22:51:22.253749 <6>[ 7.873852] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10784 22:51:22.259772 <6>[ 7.876818] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10785 22:51:22.264064 <6>[ 7.876823] pci_bus 0000:00: root bus resource [bus 00-ff]
10786 22:51:22.269881 <6>[ 7.876829] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10787 22:51:22.279533 <6>[ 7.876831] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10788 22:51:22.286511 <6>[ 7.876857] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10789 22:51:22.296269 <6>[ 7.876870] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10790 22:51:22.299761 <6>[ 7.876935] pci 0000:00:00.0: supports D1 D2
10791 22:51:22.306625 <6>[ 7.876936] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10792 22:51:22.316015 <6>[ 7.877826] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10793 22:51:22.319855 <6>[ 7.877902] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10794 22:51:22.329575 <6>[ 7.877926] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10795 22:51:22.336336 <6>[ 7.877942] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10796 22:51:22.342592 <6>[ 7.877957] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10797 22:51:22.349186 <6>[ 7.878064] pci 0000:01:00.0: supports D1 D2
10798 22:51:22.355617 <6>[ 7.878065] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10799 22:51:22.362496 <3>[ 7.881227] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10800 22:51:22.372390 <3>[ 7.881698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10801 22:51:22.379388 <6>[ 7.887456] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10802 22:51:22.385792 <6>[ 7.891180] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10803 22:51:22.392094 <6>[ 7.891209] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10804 22:51:22.402616 <6>[ 7.891213] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10805 22:51:22.408565 <6>[ 7.891221] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10806 22:51:22.418834 <6>[ 7.891234] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10807 22:51:22.425197 <6>[ 7.891247] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10808 22:51:22.431790 <6>[ 7.891259] pci 0000:00:00.0: PCI bridge to [bus 01]
10809 22:51:22.438846 <6>[ 7.891264] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10810 22:51:22.448344 <6>[ 7.891296] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10811 22:51:22.454824 <6>[ 7.891426] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10812 22:51:22.461518 <6>[ 7.892011] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10813 22:51:22.464676 <6>[ 7.892319] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10814 22:51:22.474785 <6>[ 7.895313] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10815 22:51:22.481409 <3>[ 7.904339] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10816 22:51:22.488117 <6>[ 7.911208] remoteproc remoteproc0: remote processor scp is now up
10817 22:51:22.497857 <3>[ 7.911214] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10818 22:51:22.504827 <6>[ 7.913755] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10819 22:51:22.514602 <5>[ 7.913814] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10820 22:51:22.521177 <3>[ 7.916941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 22:51:22.527907 <5>[ 7.932629] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10822 22:51:22.537916 <3>[ 7.934052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 22:51:22.544701 <5>[ 7.940523] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10824 22:51:22.554206 <6>[ 7.940913] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10825 22:51:22.557331 <6>[ 7.941325] Bluetooth: Core ver 2.22
10826 22:51:22.564069 <6>[ 7.941572] NET: Registered PF_BLUETOOTH protocol family
10827 22:51:22.570998 <6>[ 7.941578] Bluetooth: HCI device and connection manager initialized
10828 22:51:22.574151 <6>[ 7.941629] Bluetooth: HCI socket layer initialized
10829 22:51:22.580689 <6>[ 7.941642] Bluetooth: L2CAP socket layer initialized
10830 22:51:22.583953 <6>[ 7.941657] Bluetooth: SCO socket layer initialized
10831 22:51:22.594397 <3>[ 7.947729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10832 22:51:22.603896 <4>[ 7.952376] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10833 22:51:22.610414 <3>[ 7.959139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10834 22:51:22.613916 <6>[ 7.967401] cfg80211: failed to load regulatory.db
10835 22:51:22.623660 <6>[ 7.968831] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10836 22:51:22.633918 <6>[ 7.970741] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10837 22:51:22.640665 <6>[ 7.970896] usbcore: registered new interface driver uvcvideo
10838 22:51:22.650304 <3>[ 7.973657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 22:51:22.653794 <6>[ 8.008858] usbcore: registered new interface driver btusb
10840 22:51:22.660290 <6>[ 8.009340] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10841 22:51:22.670831 <4>[ 8.009669] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10842 22:51:22.676904 <3>[ 8.009679] Bluetooth: hci0: Failed to load firmware file (-2)
10843 22:51:22.683664 <3>[ 8.009683] Bluetooth: hci0: Failed to set up firmware (-2)
10844 22:51:22.693550 <4>[ 8.009686] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10845 22:51:22.704094 <3>[ 8.016223] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 22:51:22.710122 <3>[ 8.016251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 22:51:22.716957 <6>[ 8.051516] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10848 22:51:22.723438 <6>[ 8.370364] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10849 22:51:22.747406 <6>[ 8.395226] mt7921e 0000:01:00.0: ASIC revision: 79610010
10850 22:51:22.850752 <6>[ 8.495035] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10851 22:51:22.854194 <6>[ 8.495035]
10852 22:51:22.857688 Begin: Loading essential drivers ... done.
10853 22:51:22.860939 Begin: Running /scripts/init-premount ... done.
10854 22:51:22.867504 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10855 22:51:22.877287 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10856 22:51:22.880533 Device /sys/class/net/eth0 found
10857 22:51:22.880616 done.
10858 22:51:22.892079 Begin: Waiting up to 180 secs for any network device to become available ... done.
10859 22:51:22.931604 IP-Config: eth0 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10860 22:51:22.938615 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10861 22:51:22.945077 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10862 22:51:22.951489 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10863 22:51:22.958162 host : mt8192-asurada-spherion-r0-cbg-3
10864 22:51:22.965281 domain : lava-rack
10865 22:51:22.968205 rootserver: 192.168.201.1 rootpath:
10866 22:51:22.971907 filename :
10867 22:51:23.070967 done.
10868 22:51:23.079148 Begin: Running /scripts/nfs-bottom ... done.
10869 22:51:23.103618 Begin: Running /scripts/init-bottom ... done.
10870 22:51:23.119513 <6>[ 8.764023] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10871 22:51:24.464469 <6>[ 10.112048] NET: Registered PF_INET6 protocol family
10872 22:51:24.471054 <6>[ 10.119034] Segment Routing with IPv6
10873 22:51:24.474724 <6>[ 10.122984] In-situ OAM (IOAM) with IPv6
10874 22:51:24.652157 <30>[ 10.273411] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10875 22:51:24.658728 <30>[ 10.306557] systemd[1]: Detected architecture arm64.
10876 22:51:24.667307
10877 22:51:24.670654 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10878 22:51:24.670739
10879 22:51:24.670803
10880 22:51:24.693234 <30>[ 10.341363] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10881 22:51:25.816265 <30>[ 11.460446] systemd[1]: Queued start job for default target graphical.target.
10882 22:51:25.851398 <30>[ 11.496175] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10883 22:51:25.857754 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10884 22:51:25.857880
10885 22:51:25.880466 <30>[ 11.525076] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10886 22:51:25.886755 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10887 22:51:25.890094
10888 22:51:25.908121 <30>[ 11.553049] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10889 22:51:25.918223 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10890 22:51:25.918387
10891 22:51:25.935932 <30>[ 11.580673] systemd[1]: Created slice user.slice - User and Session Slice.
10892 22:51:25.942232 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10893 22:51:25.942338
10894 22:51:25.966903 <30>[ 11.608189] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10895 22:51:25.973458 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10896 22:51:25.976609
10897 22:51:25.993899 <30>[ 11.635588] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10898 22:51:26.000472 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10899 22:51:26.000571
10900 22:51:26.028890 <30>[ 11.663996] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10901 22:51:26.039134 <30>[ 11.683907] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10902 22:51:26.045547 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10903 22:51:26.045642
10904 22:51:26.062701 <30>[ 11.707718] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10905 22:51:26.069664 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10906 22:51:26.072889
10907 22:51:26.091155 <30>[ 11.735871] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10908 22:51:26.100931 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10909 22:51:26.101035
10910 22:51:26.115705 <30>[ 11.763908] systemd[1]: Reached target paths.target - Path Units.
10911 22:51:26.122714 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10912 22:51:26.125708
10913 22:51:26.143050 <30>[ 11.787747] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10914 22:51:26.149177 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10915 22:51:26.149286
10916 22:51:26.163175 <30>[ 11.811330] systemd[1]: Reached target slices.target - Slice Units.
10917 22:51:26.174099 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10918 22:51:26.174204
10919 22:51:26.187708 <30>[ 11.835859] systemd[1]: Reached target swap.target - Swaps.
10920 22:51:26.194144 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10921 22:51:26.194228
10922 22:51:26.215199 <30>[ 11.859876] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10923 22:51:26.225016 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10924 22:51:26.225106
10925 22:51:26.244449 <30>[ 11.888336] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10926 22:51:26.253670 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10927 22:51:26.253791
10928 22:51:26.273730 <30>[ 11.918628] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10929 22:51:26.283554 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10930 22:51:26.283645
10931 22:51:26.300265 <30>[ 11.944911] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10932 22:51:26.310365 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10933 22:51:26.310449
10934 22:51:26.327218 <30>[ 11.972048] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10935 22:51:26.333612 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10936 22:51:26.333712
10937 22:51:26.352124 <30>[ 11.997017] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10938 22:51:26.361866 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10939 22:51:26.361953
10940 22:51:26.382523 <30>[ 12.027416] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10941 22:51:26.392477 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10942 22:51:26.392570
10943 22:51:26.411131 <30>[ 12.055840] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10944 22:51:26.420753 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10945 22:51:26.420861
10946 22:51:26.478829 <30>[ 12.123595] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10947 22:51:26.485542 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10948 22:51:26.485636
10949 22:51:26.507720 <30>[ 12.152248] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10950 22:51:26.513998 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10951 22:51:26.514105
10952 22:51:26.566848 <30>[ 12.211662] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10953 22:51:26.573363 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10954 22:51:26.573457
10955 22:51:26.601657 <30>[ 12.239784] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10956 22:51:26.616691 <30>[ 12.261390] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10957 22:51:26.623550 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10958 22:51:26.626543
10959 22:51:26.647108 <30>[ 12.291366] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10960 22:51:26.653041 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10961 22:51:26.653133
10962 22:51:26.679896 <30>[ 12.324695] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10963 22:51:26.686672 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10964 22:51:26.686773
10965 22:51:26.713963 <30>[ 12.358479] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10966 22:51:26.723553 Starting [0;1;39mmodpr<6>[ 12.369370] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10967 22:51:26.729898 obe@drm.service[0m - Load Kernel Module drm...
10968 22:51:26.729984
10969 22:51:26.787185 <30>[ 12.432105] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10970 22:51:26.797514 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10971 22:51:26.797632
10972 22:51:26.821949 <30>[ 12.466712] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10973 22:51:26.828183 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10974 22:51:26.828278
10975 22:51:26.855072 <30>[ 12.499814] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10976 22:51:26.861217 Starting [0;1;39mmodpr<6>[ 12.509992] fuse: init (API version 7.37)
10977 22:51:26.864761 obe@loop.ser…e[0m - Load Kernel Module loop...
10978 22:51:26.864847
10979 22:51:26.918777 <30>[ 12.563768] systemd[1]: Starting systemd-journald.service - Journal Service...
10980 22:51:26.925845 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10981 22:51:26.925943
10982 22:51:26.950864 <30>[ 12.595727] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10983 22:51:26.957309 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10984 22:51:26.957402
10985 22:51:26.986260 <30>[ 12.628097] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10986 22:51:26.992779 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10987 22:51:26.992879
10988 22:51:27.015955 <30>[ 12.660860] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10989 22:51:27.026391 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10990 22:51:27.026503
10991 22:51:27.090975 <30>[ 12.736024] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10992 22:51:27.098288 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10993 22:51:27.098405
10994 22:51:27.123674 <30>[ 12.768294] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10995 22:51:27.133720 [[0;32m OK [<3>[ 12.776426] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 22:51:27.140281 0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10997 22:51:27.140381
10998 22:51:27.159482 <30>[ 12.803757] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10999 22:51:27.166125 <3>[ 12.811612] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 22:51:27.176086 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11001 22:51:27.176198
11002 22:51:27.195830 <30>[ 12.839698] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11003 22:51:27.205266 [[0;32m OK [0m] Mounted [0;<3>[ 12.849676] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 22:51:27.211971 1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11005 22:51:27.212078
11006 22:51:27.231888 <30>[ 12.875936] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11007 22:51:27.241775 <3>[ 12.882298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 22:51:27.248492 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11009 22:51:27.248594
11010 22:51:27.267851 <30>[ 12.912371] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11011 22:51:27.274852 <3>[ 12.915207] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 22:51:27.284529 <30>[ 12.920467] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11013 22:51:27.291200 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11014 22:51:27.291297
11015 22:51:27.305627 <3>[ 12.950862] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11016 22:51:27.316654 <30>[ 12.961382] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11017 22:51:27.323441 <30>[ 12.969408] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11018 22:51:27.340788 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 12.982322] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 22:51:27.340900 - Load Kernel Module dm_mod.
11020 22:51:27.340970
11021 22:51:27.357746 <30>[ 13.005165] systemd[1]: modprobe@drm.service: Deactivated successfully.
11022 22:51:27.368506 <30>[ 13.013028] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11023 22:51:27.375331 <3>[ 13.016204] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 22:51:27.384944 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11025 22:51:27.385063
11026 22:51:27.405506 <30>[ 13.049713] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11027 22:51:27.412033 <3>[ 13.053183] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11028 22:51:27.421840 <30>[ 13.058232] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11029 22:51:27.428749 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11030 22:51:27.428842
11031 22:51:27.444237 <3>[ 13.088796] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 22:51:27.455392 <30>[ 13.100349] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11033 22:51:27.462529 <30>[ 13.108054] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11034 22:51:27.475679 [[0;32m OK [0m] Finished [0;1;39mmodprobe@f<3>[ 13.118859] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11035 22:51:27.479030 use.service[0m - Load Kernel Module fuse.
11036 22:51:27.479127
11037 22:51:27.496613 <30>[ 13.144541] systemd[1]: modprobe@loop.service: Deactivated successfully.
11038 22:51:27.507667 <30>[ 13.152292] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11039 22:51:27.514829 <3>[ 13.152515] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11040 22:51:27.525145 <3>[ 13.153268] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
11041 22:51:27.531513 <3>[ 13.175338] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11042 22:51:27.548659 <4>[ 13.177155] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11043 22:51:27.555177 <3>[ 13.201544] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11044 22:51:27.565426 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11045 22:51:27.565517
11046 22:51:27.585158 <30>[ 13.229836] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11047 22:51:27.591940 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11048 22:51:27.592031
11049 22:51:27.614789 <30>[ 13.256002] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11050 22:51:27.621628 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11051 22:51:27.621726
11052 22:51:27.638912 <30>[ 13.283703] systemd[1]: Started systemd-journald.service - Journal Service.
11053 22:51:27.645426 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11054 22:51:27.645520
11055 22:51:27.666862 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11056 22:51:27.666986
11057 22:51:27.684265 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11058 22:51:27.684379
11059 22:51:27.705347 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11060 22:51:27.705497
11061 22:51:27.763102 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11062 22:51:27.763253
11063 22:51:27.785908 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11064 22:51:27.786020
11065 22:51:27.807632 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11066 22:51:27.807758
11067 22:51:27.831243 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11068 22:51:27.831380
11069 22:51:27.886386 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables..<46>[ 13.530533] systemd-journald[309]: Received client request to flush runtime journal.
11070 22:51:27.886546 .
11071 22:51:27.886630
11072 22:51:27.913931 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11073 22:51:27.914075
11074 22:51:27.941247 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11075 22:51:27.941380
11076 22:51:27.959231 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11077 22:51:27.959372
11078 22:51:27.980128 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11079 22:51:27.980270
11080 22:51:29.003140 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11081 22:51:29.003328
11082 22:51:29.024377 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11083 22:51:29.024546
11084 22:51:29.079306 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11085 22:51:29.079478
11086 22:51:29.297628 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11087 22:51:29.297778
11088 22:51:29.417263 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11089 22:51:29.417446
11090 22:51:29.435274 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11091 22:51:29.435567
11092 22:51:29.450987 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11093 22:51:29.451479
11094 22:51:29.515640 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11095 22:51:29.516156
11096 22:51:29.538592 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11097 22:51:29.538982
11098 22:51:29.773965 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11099 22:51:29.774417
11100 22:51:29.828778 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11101 22:51:29.829186
11102 22:51:29.923210 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11103 22:51:29.923640
11104 22:51:30.198504 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11105 22:51:30.198948
11106 22:51:30.223138 <6>[ 15.871545] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11107 22:51:30.235039 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11108 22:51:30.235431
11109 22:51:30.278367 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11110 22:51:30.278773
11111 22:51:30.376909 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11112 22:51:30.377512
11113 22:51:30.400310 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11114 22:51:30.400768
11115 22:51:30.423878 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11116 22:51:30.424342
11117 22:51:30.487124 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11118 22:51:30.487629
11119 22:51:30.530407 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11120 22:51:30.530962
11121 22:51:30.572354 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11122 22:51:30.572831
11123 22:51:30.596741 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11124 22:51:30.597159
11125 22:51:30.617135 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11126 22:51:30.617725
11127 22:51:30.645110 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11128 22:51:30.645671
11129 22:51:30.672251 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11130 22:51:30.672928
11131 22:51:30.773343 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11132 22:51:30.773855
11133 22:51:30.795273 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11134 22:51:30.795776
11135 22:51:30.816530 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11136 22:51:30.817286
11137 22:51:30.835176 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11138 22:51:30.835593
11139 22:51:30.862631 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11140 22:51:30.863193
11141 22:51:30.883755 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11142 22:51:30.884284
11143 22:51:30.903441 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11144 22:51:30.904071
11145 22:51:30.927347 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11146 22:51:30.927901
11147 22:51:30.952161 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11148 22:51:30.952709
11149 22:51:30.971218 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11150 22:51:30.971752
11151 22:51:30.989656 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11152 22:51:30.990213
11153 22:51:31.007069 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11154 22:51:31.007603
11155 22:51:31.023270 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11156 22:51:31.023783
11157 22:51:31.076480 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11158 22:51:31.076991
11159 22:51:31.114844 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11160 22:51:31.115361
11161 22:51:31.207289 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11162 22:51:31.207786
11163 22:51:31.232895 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11164 22:51:31.233373
11165 22:51:31.388827 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11166 22:51:31.389383
11167 22:51:31.443807 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11168 22:51:31.444277
11169 22:51:31.488073 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11170 22:51:31.488505
11171 22:51:31.507571 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11172 22:51:31.507990
11173 22:51:31.528514 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11174 22:51:31.529022
11175 22:51:31.547946 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11176 22:51:31.548454
11177 22:51:31.583409 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11178 22:51:31.583925
11179 22:51:31.601067 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11180 22:51:31.601683
11181 22:51:31.619496 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11182 22:51:31.620065
11183 22:51:31.664265 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11184 22:51:31.664792
11185 22:51:31.718381 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11186 22:51:31.718887
11187 22:51:31.822924
11188 22:51:31.823481
11189 22:51:31.825950 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11190 22:51:31.826343
11191 22:51:31.829815 debian-bookworm-arm64 login: root (automatic login)
11192 22:51:31.830312
11193 22:51:31.830762
11194 22:51:32.163024 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
11195 22:51:32.163539
11196 22:51:32.169746 The programs included with the Debian GNU/Linux system are free software;
11197 22:51:32.176504 the exact distribution terms for each program are described in the
11198 22:51:32.179524 individual files in /usr/share/doc/*/copyright.
11199 22:51:32.179946
11200 22:51:32.186391 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11201 22:51:32.189678 permitted by applicable law.
11202 22:51:33.376526 Matched prompt #10: / #
11204 22:51:33.377721 Setting prompt string to ['/ #']
11205 22:51:33.378313 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11207 22:51:33.379396 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11208 22:51:33.379839 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11209 22:51:33.380276 Setting prompt string to ['/ #']
11210 22:51:33.380642 Forcing a shell prompt, looking for ['/ #']
11212 22:51:33.431630 / #
11213 22:51:33.432301 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11214 22:51:33.433038 Waiting using forced prompt support (timeout 00:02:30)
11215 22:51:33.437873
11216 22:51:33.438828 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11217 22:51:33.439495 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11219 22:51:33.540953 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683654/extract-nfsrootfs-a6eey1um'
11220 22:51:33.547857 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683654/extract-nfsrootfs-a6eey1um'
11222 22:51:33.649576 / # export NFS_SERVER_IP='192.168.201.1'
11223 22:51:33.656029 export NFS_SERVER_IP='192.168.201.1'
11224 22:51:33.656975 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11225 22:51:33.657589 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11226 22:51:33.658085 end: 2 depthcharge-action (duration 00:01:45) [common]
11227 22:51:33.658591 start: 3 lava-test-retry (timeout 00:07:32) [common]
11228 22:51:33.659081 start: 3.1 lava-test-shell (timeout 00:07:32) [common]
11229 22:51:33.659580 Using namespace: common
11231 22:51:33.760832 / # #
11232 22:51:33.761541 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11233 22:51:33.768250 #
11234 22:51:33.769135 Using /lava-13683654
11236 22:51:33.870358 / # export SHELL=/bin/bash
11237 22:51:33.876944 export SHELL=/bin/bash
11239 22:51:33.978825 / # . /lava-13683654/environment
11240 22:51:33.985669 . /lava-13683654/environment
11242 22:51:34.094484 / # /lava-13683654/bin/lava-test-runner /lava-13683654/0
11243 22:51:34.095136 Test shell timeout: 10s (minimum of the action and connection timeout)
11244 22:51:34.101485 /lava-13683654/bin/lava-test-runner /lava-13683654/0
11245 22:51:34.430661 + export TESTRUN_ID=0_timesync-off
11246 22:51:34.434128 + TESTRUN_ID=0_timesync-off
11247 22:51:34.437167 + cd /lava-13683654/0/tests/0_timesync-off
11248 22:51:34.440369 ++ cat uuid
11249 22:51:34.449658 + UUID=13683654_1.6.2.3.1
11250 22:51:34.450112 + set +x
11251 22:51:34.456216 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13683654_1.6.2.3.1>
11252 22:51:34.456915 Received signal: <STARTRUN> 0_timesync-off 13683654_1.6.2.3.1
11253 22:51:34.457321 Starting test lava.0_timesync-off (13683654_1.6.2.3.1)
11254 22:51:34.457752 Skipping test definition patterns.
11255 22:51:34.459600 + systemctl stop systemd-timesyncd
11256 22:51:34.550584 + set +x
11257 22:51:34.554135 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13683654_1.6.2.3.1>
11258 22:51:34.554836 Received signal: <ENDRUN> 0_timesync-off 13683654_1.6.2.3.1
11259 22:51:34.555264 Ending use of test pattern.
11260 22:51:34.555593 Ending test lava.0_timesync-off (13683654_1.6.2.3.1), duration 0.10
11262 22:51:34.655501 + export TESTRUN_ID=1_kselftest-tpm2
11263 22:51:34.658378 + TESTRUN_ID=1_kselftest-tpm2
11264 22:51:34.661857 + cd /lava-13683654/0/tests/1_kselftest-tpm2
11265 22:51:34.665186 ++ cat uuid
11266 22:51:34.674594 + UUID=13683654_1.6.2.3.5
11267 22:51:34.675021 + set +x
11268 22:51:34.681121 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 13683654_1.6.2.3.5>
11269 22:51:34.681832 Received signal: <STARTRUN> 1_kselftest-tpm2 13683654_1.6.2.3.5
11270 22:51:34.682190 Starting test lava.1_kselftest-tpm2 (13683654_1.6.2.3.5)
11271 22:51:34.682632 Skipping test definition patterns.
11272 22:51:34.684668 + cd ./automated/linux/kselftest/
11273 22:51:34.708047 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11274 22:51:34.771385 INFO: install_deps skipped
11275 22:51:35.293292 --2024-05-07 22:51:36-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11276 22:51:35.299885 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11277 22:51:35.430681 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11278 22:51:35.559950 HTTP request sent, awaiting response... 200 OK
11279 22:51:35.563382 Length: 1651624 (1.6M) [application/octet-stream]
11280 22:51:35.566568 Saving to: 'kselftest_armhf.tar.gz'
11281 22:51:35.566992
11282 22:51:35.567389
11283 22:51:35.821032 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11284 22:51:36.078651 kselftest_armhf.tar 3%[ ] 50.15K 193KB/s
11285 22:51:36.384245 kselftest_armhf.tar 13%[=> ] 219.84K 424KB/s
11286 22:51:36.520160 kselftest_armhf.tar 51%[=========> ] 824.13K 1001KB/s
11287 22:51:36.526557 kselftest_armhf.tar 100%[===================>] 1.57M 1.64MB/s in 1.0s
11288 22:51:36.526641
11289 22:51:36.671805 2024-05-07 22:51:37 (1.64 MB/s) - 'kselftest_armhf.tar.gz' saved [1651624/1651624]
11290 22:51:36.671938
11291 22:51:41.649577 skiplist:
11292 22:51:41.652306 ========================================
11293 22:51:41.655510 ========================================
11294 22:51:41.703853 tpm2:test_smoke.sh
11295 22:51:41.706890 tpm2:test_space.sh
11296 22:51:41.725428 ============== Tests to run ===============
11297 22:51:41.728384 tpm2:test_smoke.sh
11298 22:51:41.728456 tpm2:test_space.sh
11299 22:51:41.731498 ===========End Tests to run ===============
11300 22:51:41.734822 shardfile-tpm2 pass
11301 22:51:41.852487 <12>[ 27.502546] kselftest: Running tests in tpm2
11302 22:51:41.862988 TAP version 13
11303 22:51:41.878435 1..2
11304 22:51:41.911654 # selftests: tpm2: test_smoke.sh
11305 22:51:43.756382 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11306 22:51:43.763056 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11307 22:51:43.770047 # Exception ignored in: <function Client.__del__ at 0xffffacacccc0>
11308 22:51:43.773279 # Traceback (most recent call last):
11309 22:51:43.783503 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11310 22:51:43.783585 # if self.tpm:
11311 22:51:43.786137 # ^^^^^^^^
11312 22:51:43.789778 # AttributeError: 'Client' object has no attribute 'tpm'
11313 22:51:43.796312 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11314 22:51:43.803874 # Exception ignored in: <function Client.__del__ at 0xffffacacccc0>
11315 22:51:43.806424 # Traceback (most recent call last):
11316 22:51:43.816643 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11317 22:51:43.816722 # if self.tpm:
11318 22:51:43.819730 # ^^^^^^^^
11319 22:51:43.823161 # AttributeError: 'Client' object has no attribute 'tpm'
11320 22:51:43.830147 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11321 22:51:43.836429 # Exception ignored in: <function Client.__del__ at 0xffffacacccc0>
11322 22:51:43.839879 # Traceback (most recent call last):
11323 22:51:43.850653 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11324 22:51:43.853304 # if self.tpm:
11325 22:51:43.853382 # ^^^^^^^^
11326 22:51:43.859961 # AttributeError: 'Client' object has no attribute 'tpm'
11327 22:51:43.866798 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11328 22:51:43.873096 # Exception ignored in: <function Client.__del__ at 0xffffacacccc0>
11329 22:51:43.876565 # Traceback (most recent call last):
11330 22:51:43.886705 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11331 22:51:43.886790 # if self.tpm:
11332 22:51:43.889765 # ^^^^^^^^
11333 22:51:43.893443 # AttributeError: 'Client' object has no attribute 'tpm'
11334 22:51:43.899957 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11335 22:51:43.906677 # Exception ignored in: <function Client.__del__ at 0xffffacacccc0>
11336 22:51:43.909716 # Traceback (most recent call last):
11337 22:51:43.919754 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11338 22:51:43.919831 # if self.tpm:
11339 22:51:43.923695 # ^^^^^^^^
11340 22:51:43.927175 # AttributeError: 'Client' object has no attribute 'tpm'
11341 22:51:43.933590 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11342 22:51:43.940181 # Exception ignored in: <function Client.__del__ at 0xffffacacccc0>
11343 22:51:43.943273 # Traceback (most recent call last):
11344 22:51:43.953658 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11345 22:51:43.956944 # if self.tpm:
11346 22:51:43.957018 # ^^^^^^^^
11347 22:51:43.963392 # AttributeError: 'Client' object has no attribute 'tpm'
11348 22:51:43.970308 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11349 22:51:43.976766 # Exception ignored in: <function Client.__del__ at 0xffffacacccc0>
11350 22:51:43.980150 # Traceback (most recent call last):
11351 22:51:43.990019 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11352 22:51:43.990103 # if self.tpm:
11353 22:51:43.993348 # ^^^^^^^^
11354 22:51:43.996760 # AttributeError: 'Client' object has no attribute 'tpm'
11355 22:51:44.007102 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11356 22:51:44.013745 # Exception ignored in: <function Client.__del__ at 0xffffacacccc0>
11357 22:51:44.016567 # Traceback (most recent call last):
11358 22:51:44.023264 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11359 22:51:44.026930 # if self.tpm:
11360 22:51:44.030132 # ^^^^^^^^
11361 22:51:44.033156 # AttributeError: 'Client' object has no attribute 'tpm'
11362 22:51:44.033278 #
11363 22:51:44.039832 # ======================================================================
11364 22:51:44.046841 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11365 22:51:44.053588 # ----------------------------------------------------------------------
11366 22:51:44.057111 # Traceback (most recent call last):
11367 22:51:44.067025 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11368 22:51:44.074070 # self.root_key = self.client.create_root_key()
11369 22:51:44.076789 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11370 22:51:44.087055 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11371 22:51:44.093439 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11372 22:51:44.098426 # ^^^^^^^^^^^^^^^^^^
11373 22:51:44.108610 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11374 22:51:44.112427 # raise ProtocolError(cc, rc)
11375 22:51:44.115814 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11376 22:51:44.115896 #
11377 22:51:44.122434 # ======================================================================
11378 22:51:44.129283 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11379 22:51:44.135398 # ----------------------------------------------------------------------
11380 22:51:44.138948 # Traceback (most recent call last):
11381 22:51:44.148775 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11382 22:51:44.152346 # self.client = tpm2.Client()
11383 22:51:44.155524 # ^^^^^^^^^^^^^
11384 22:51:44.165863 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11385 22:51:44.172236 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11386 22:51:44.176170 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11387 22:51:44.182431 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11388 22:51:44.182513 #
11389 22:51:44.189283 # ======================================================================
11390 22:51:44.192735 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11391 22:51:44.199044 # ----------------------------------------------------------------------
11392 22:51:44.202840 # Traceback (most recent call last):
11393 22:51:44.212596 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11394 22:51:44.216043 # self.client = tpm2.Client()
11395 22:51:44.219234 # ^^^^^^^^^^^^^
11396 22:51:44.229375 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11397 22:51:44.236487 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11398 22:51:44.239356 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11399 22:51:44.245978 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11400 22:51:44.246055 #
11401 22:51:44.252801 # ======================================================================
11402 22:51:44.259726 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11403 22:51:44.263034 # ----------------------------------------------------------------------
11404 22:51:44.266264 # Traceback (most recent call last):
11405 22:51:44.276923 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11406 22:51:44.279595 # self.client = tpm2.Client()
11407 22:51:44.283128 # ^^^^^^^^^^^^^
11408 22:51:44.292951 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11409 22:51:44.299583 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11410 22:51:44.303171 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11411 22:51:44.309564 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11412 22:51:44.309638 #
11413 22:51:44.316544 # ======================================================================
11414 22:51:44.322840 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11415 22:51:44.329649 # ----------------------------------------------------------------------
11416 22:51:44.332949 # Traceback (most recent call last):
11417 22:51:44.343289 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11418 22:51:44.346326 # self.client = tpm2.Client()
11419 22:51:44.349301 # ^^^^^^^^^^^^^
11420 22:51:44.359638 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11421 22:51:44.362942 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11422 22:51:44.369632 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11423 22:51:44.373379 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11424 22:51:44.376907 #
11425 22:51:44.379429 # ======================================================================
11426 22:51:44.386567 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11427 22:51:44.393523 # ----------------------------------------------------------------------
11428 22:51:44.396377 # Traceback (most recent call last):
11429 22:51:44.406261 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11430 22:51:44.409661 # self.client = tpm2.Client()
11431 22:51:44.412919 # ^^^^^^^^^^^^^
11432 22:51:44.423005 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11433 22:51:44.426319 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11434 22:51:44.434682 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11435 22:51:44.438205 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11436 22:51:44.438281 #
11437 22:51:44.444843 # ======================================================================
11438 22:51:44.452307 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11439 22:51:44.455981 # ----------------------------------------------------------------------
11440 22:51:44.459626 # Traceback (most recent call last):
11441 22:51:44.470029 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11442 22:51:44.475503 # self.client = tpm2.Client()
11443 22:51:44.475578 # ^^^^^^^^^^^^^
11444 22:51:44.486748 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11445 22:51:44.491048 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11446 22:51:44.497180 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11447 22:51:44.500855 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11448 22:51:44.500932 #
11449 22:51:44.507496 # ======================================================================
11450 22:51:44.517368 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11451 22:51:44.520713 # ----------------------------------------------------------------------
11452 22:51:44.523870 # Traceback (most recent call last):
11453 22:51:44.534151 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11454 22:51:44.537156 # self.client = tpm2.Client()
11455 22:51:44.540838 # ^^^^^^^^^^^^^
11456 22:51:44.550813 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11457 22:51:44.557839 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11458 22:51:44.561175 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11459 22:51:44.567834 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11460 22:51:44.567911 #
11461 22:51:44.574108 # ======================================================================
11462 22:51:44.580944 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11463 22:51:44.587852 # ----------------------------------------------------------------------
11464 22:51:44.591215 # Traceback (most recent call last):
11465 22:51:44.601112 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11466 22:51:44.604382 # self.client = tpm2.Client()
11467 22:51:44.607889 # ^^^^^^^^^^^^^
11468 22:51:44.617600 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11469 22:51:44.621199 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11470 22:51:44.627682 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11471 22:51:44.630912 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11472 22:51:44.630980 #
11473 22:51:44.638336 # ----------------------------------------------------------------------
11474 22:51:44.641430 # Ran 9 tests in 0.060s
11475 22:51:44.641506 #
11476 22:51:44.644812 # FAILED (errors=9)
11477 22:51:44.648094 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11478 22:51:44.655001 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11479 22:51:44.655084 #
11480 22:51:44.661314 # ----------------------------------------------------------------------
11481 22:51:44.664484 # Ran 2 tests in 0.037s
11482 22:51:44.664592 #
11483 22:51:44.664688 # OK
11484 22:51:44.667747 ok 1 selftests: tpm2: test_smoke.sh
11485 22:51:44.671159 # selftests: tpm2: test_space.sh
11486 22:51:44.678472 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11487 22:51:44.684363 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11488 22:51:44.691234 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11489 22:51:44.697991 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11490 22:51:44.698071 #
11491 22:51:44.705182 # ======================================================================
11492 22:51:44.711118 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11493 22:51:44.714686 # ----------------------------------------------------------------------
11494 22:51:44.717633 # Traceback (most recent call last):
11495 22:51:44.731306 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11496 22:51:44.734749 # root1 = space1.create_root_key()
11497 22:51:44.738132 # ^^^^^^^^^^^^^^^^^^^^^^^^
11498 22:51:44.748158 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11499 22:51:44.754769 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11500 22:51:44.758443 # ^^^^^^^^^^^^^^^^^^
11501 22:51:44.768443 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11502 22:51:44.771320 # raise ProtocolError(cc, rc)
11503 22:51:44.778268 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11504 22:51:44.778359 #
11505 22:51:44.784751 # ======================================================================
11506 22:51:44.791365 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11507 22:51:44.795198 # ----------------------------------------------------------------------
11508 22:51:44.798362 # Traceback (most recent call last):
11509 22:51:44.811569 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11510 22:51:44.814973 # space1.create_root_key()
11511 22:51:44.824838 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11512 22:51:44.828706 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11513 22:51:44.834996 # ^^^^^^^^^^^^^^^^^^
11514 22:51:44.845373 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11515 22:51:44.848735 # raise ProtocolError(cc, rc)
11516 22:51:44.852024 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11517 22:51:44.854785 #
11518 22:51:44.858998 # ======================================================================
11519 22:51:44.865575 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11520 22:51:44.872091 # ----------------------------------------------------------------------
11521 22:51:44.875543 # Traceback (most recent call last):
11522 22:51:44.885421 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11523 22:51:44.888732 # root1 = space1.create_root_key()
11524 22:51:44.891414 # ^^^^^^^^^^^^^^^^^^^^^^^^
11525 22:51:44.904930 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11526 22:51:44.908144 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11527 22:51:44.914910 # ^^^^^^^^^^^^^^^^^^
11528 22:51:44.925029 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11529 22:51:44.928761 # raise ProtocolError(cc, rc)
11530 22:51:44.931913 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11531 22:51:44.932048 #
11532 22:51:44.938552 # ======================================================================
11533 22:51:44.944902 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11534 22:51:44.951932 # ----------------------------------------------------------------------
11535 22:51:44.954984 # Traceback (most recent call last):
11536 22:51:44.968352 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11537 22:51:44.971446 # root1 = space1.create_root_key()
11538 22:51:44.974810 # ^^^^^^^^^^^^^^^^^^^^^^^^
11539 22:51:44.984885 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11540 22:51:44.991279 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11541 22:51:44.994743 # ^^^^^^^^^^^^^^^^^^
11542 22:51:45.004826 # File "/lava-13683654/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11543 22:51:45.008190 # raise ProtocolError(cc, rc)
11544 22:51:45.015015 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11545 22:51:45.015097 #
11546 22:51:45.021954 # ----------------------------------------------------------------------
11547 22:51:45.022036 # Ran 4 tests in 0.078s
11548 22:51:45.022100 #
11549 22:51:45.024845 # FAILED (errors=4)
11550 22:51:45.028153 not ok 2 selftests: tpm2: test_space.sh # exit=1
11551 22:51:45.365465 tpm2_test_smoke_sh pass
11552 22:51:45.368531 tpm2_test_space_sh fail
11553 22:51:45.435936 + ../../utils/send-to-lava.sh ./output/result.txt
11554 22:51:45.514272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11555 22:51:45.514575 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11557 22:51:45.572817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11558 22:51:45.573082 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11560 22:51:45.624993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11561 22:51:45.625244 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11563 22:51:45.627753 + set +x
11564 22:51:45.631540 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 13683654_1.6.2.3.5>
11565 22:51:45.631791 Received signal: <ENDRUN> 1_kselftest-tpm2 13683654_1.6.2.3.5
11566 22:51:45.631864 Ending use of test pattern.
11567 22:51:45.631926 Ending test lava.1_kselftest-tpm2 (13683654_1.6.2.3.5), duration 10.95
11569 22:51:45.634238 <LAVA_TEST_RUNNER EXIT>
11570 22:51:45.634518 ok: lava_test_shell seems to have completed
11571 22:51:45.634628 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11572 22:51:45.634715 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11573 22:51:45.634797 end: 3 lava-test-retry (duration 00:00:12) [common]
11574 22:51:45.634883 start: 4 finalize (timeout 00:07:20) [common]
11575 22:51:45.634969 start: 4.1 power-off (timeout 00:00:30) [common]
11576 22:51:45.635122 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11577 22:51:45.711315 >> Command sent successfully.
11578 22:51:45.713791 Returned 0 in 0 seconds
11579 22:51:45.814157 end: 4.1 power-off (duration 00:00:00) [common]
11581 22:51:45.814465 start: 4.2 read-feedback (timeout 00:07:20) [common]
11582 22:51:45.814720 Listened to connection for namespace 'common' for up to 1s
11583 22:51:46.815677 Finalising connection for namespace 'common'
11584 22:51:46.815855 Disconnecting from shell: Finalise
11585 22:51:46.815936 / #
11586 22:51:46.916250 end: 4.2 read-feedback (duration 00:00:01) [common]
11587 22:51:46.916404 end: 4 finalize (duration 00:00:01) [common]
11588 22:51:46.916513 Cleaning after the job
11589 22:51:46.916610 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/ramdisk
11590 22:51:46.918738 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/kernel
11591 22:51:46.929136 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/dtb
11592 22:51:46.929325 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/nfsrootfs
11593 22:51:46.991682 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683654/tftp-deploy-_j5d1c4q/modules
11594 22:51:46.997181 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683654
11595 22:51:47.551127 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683654
11596 22:51:47.551328 Job finished correctly