Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 26
- Errors: 0
- Kernel Errors: 42
- Boot result: PASS
1 22:55:17.301905 lava-dispatcher, installed at version: 2024.01
2 22:55:17.302091 start: 0 validate
3 22:55:17.302226 Start time: 2024-05-07 22:55:17.302216+00:00 (UTC)
4 22:55:17.302337 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:55:17.302460 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:55:17.564077 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:55:17.564867 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:55:17.819286 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:55:17.820405 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:55:18.090341 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:55:18.091152 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:55:18.345409 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:55:18.346159 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:55:18.608459 validate duration: 1.31
16 22:55:18.608730 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:55:18.608828 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:55:18.608914 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:55:18.609033 Not decompressing ramdisk as can be used compressed.
20 22:55:18.609118 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 22:55:18.609183 saving as /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/ramdisk/initrd.cpio.gz
22 22:55:18.609245 total size: 5628151 (5 MB)
23 22:55:18.612049 progress 0 % (0 MB)
24 22:55:18.613498 progress 5 % (0 MB)
25 22:55:18.615034 progress 10 % (0 MB)
26 22:55:18.616421 progress 15 % (0 MB)
27 22:55:18.618000 progress 20 % (1 MB)
28 22:55:18.619424 progress 25 % (1 MB)
29 22:55:18.620930 progress 30 % (1 MB)
30 22:55:18.622483 progress 35 % (1 MB)
31 22:55:18.623841 progress 40 % (2 MB)
32 22:55:18.625604 progress 45 % (2 MB)
33 22:55:18.626965 progress 50 % (2 MB)
34 22:55:18.628453 progress 55 % (2 MB)
35 22:55:18.630074 progress 60 % (3 MB)
36 22:55:18.631656 progress 65 % (3 MB)
37 22:55:18.633257 progress 70 % (3 MB)
38 22:55:18.634651 progress 75 % (4 MB)
39 22:55:18.636185 progress 80 % (4 MB)
40 22:55:18.637581 progress 85 % (4 MB)
41 22:55:18.639172 progress 90 % (4 MB)
42 22:55:18.640670 progress 95 % (5 MB)
43 22:55:18.642164 progress 100 % (5 MB)
44 22:55:18.642373 5 MB downloaded in 0.03 s (162.03 MB/s)
45 22:55:18.642529 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:55:18.642809 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:55:18.642898 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:55:18.642995 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:55:18.643127 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:55:18.643216 saving as /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/kernel/Image
52 22:55:18.643329 total size: 54682112 (52 MB)
53 22:55:18.643420 No compression specified
54 22:55:18.644568 progress 0 % (0 MB)
55 22:55:18.659092 progress 5 % (2 MB)
56 22:55:18.672902 progress 10 % (5 MB)
57 22:55:18.686726 progress 15 % (7 MB)
58 22:55:18.700199 progress 20 % (10 MB)
59 22:55:18.713750 progress 25 % (13 MB)
60 22:55:18.727048 progress 30 % (15 MB)
61 22:55:18.740873 progress 35 % (18 MB)
62 22:55:18.754977 progress 40 % (20 MB)
63 22:55:18.768826 progress 45 % (23 MB)
64 22:55:18.782844 progress 50 % (26 MB)
65 22:55:18.796467 progress 55 % (28 MB)
66 22:55:18.810249 progress 60 % (31 MB)
67 22:55:18.823827 progress 65 % (33 MB)
68 22:55:18.838763 progress 70 % (36 MB)
69 22:55:18.854336 progress 75 % (39 MB)
70 22:55:18.869003 progress 80 % (41 MB)
71 22:55:18.882944 progress 85 % (44 MB)
72 22:55:18.896624 progress 90 % (46 MB)
73 22:55:18.910241 progress 95 % (49 MB)
74 22:55:18.923607 progress 100 % (52 MB)
75 22:55:18.923867 52 MB downloaded in 0.28 s (185.89 MB/s)
76 22:55:18.924024 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:55:18.924258 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:55:18.924344 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:55:18.924431 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:55:18.924566 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:55:18.924635 saving as /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/dtb/mt8192-asurada-spherion-r0.dtb
83 22:55:18.924694 total size: 47258 (0 MB)
84 22:55:18.924756 No compression specified
85 22:55:18.925912 progress 69 % (0 MB)
86 22:55:18.926188 progress 100 % (0 MB)
87 22:55:18.926342 0 MB downloaded in 0.00 s (27.40 MB/s)
88 22:55:18.926465 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:55:18.926683 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:55:18.926771 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:55:18.926854 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:55:18.926966 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 22:55:18.927034 saving as /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/nfsrootfs/full.rootfs.tar
95 22:55:18.927095 total size: 69067788 (65 MB)
96 22:55:18.927157 Using unxz to decompress xz
97 22:55:18.931415 progress 0 % (0 MB)
98 22:55:19.124295 progress 5 % (3 MB)
99 22:55:19.327351 progress 10 % (6 MB)
100 22:55:19.530649 progress 15 % (9 MB)
101 22:55:19.694311 progress 20 % (13 MB)
102 22:55:19.871582 progress 25 % (16 MB)
103 22:55:20.073061 progress 30 % (19 MB)
104 22:55:20.190472 progress 35 % (23 MB)
105 22:55:20.286703 progress 40 % (26 MB)
106 22:55:20.486265 progress 45 % (29 MB)
107 22:55:20.695657 progress 50 % (32 MB)
108 22:55:20.900799 progress 55 % (36 MB)
109 22:55:21.119260 progress 60 % (39 MB)
110 22:55:21.306815 progress 65 % (42 MB)
111 22:55:21.500549 progress 70 % (46 MB)
112 22:55:21.692323 progress 75 % (49 MB)
113 22:55:21.904991 progress 80 % (52 MB)
114 22:55:22.090079 progress 85 % (56 MB)
115 22:55:22.292316 progress 90 % (59 MB)
116 22:55:22.510112 progress 95 % (62 MB)
117 22:55:22.719706 progress 100 % (65 MB)
118 22:55:22.726077 65 MB downloaded in 3.80 s (17.34 MB/s)
119 22:55:22.726328 end: 1.4.1 http-download (duration 00:00:04) [common]
121 22:55:22.726591 end: 1.4 download-retry (duration 00:00:04) [common]
122 22:55:22.726680 start: 1.5 download-retry (timeout 00:09:56) [common]
123 22:55:22.726768 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 22:55:22.726919 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:55:22.726989 saving as /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/modules/modules.tar
126 22:55:22.727049 total size: 8594396 (8 MB)
127 22:55:22.727113 Using unxz to decompress xz
128 22:55:22.730723 progress 0 % (0 MB)
129 22:55:22.749951 progress 5 % (0 MB)
130 22:55:22.775406 progress 10 % (0 MB)
131 22:55:22.799039 progress 15 % (1 MB)
132 22:55:22.822045 progress 20 % (1 MB)
133 22:55:22.846557 progress 25 % (2 MB)
134 22:55:22.870519 progress 30 % (2 MB)
135 22:55:22.894203 progress 35 % (2 MB)
136 22:55:22.918793 progress 40 % (3 MB)
137 22:55:22.944037 progress 45 % (3 MB)
138 22:55:22.969516 progress 50 % (4 MB)
139 22:55:22.996500 progress 55 % (4 MB)
140 22:55:23.022827 progress 60 % (4 MB)
141 22:55:23.047713 progress 65 % (5 MB)
142 22:55:23.072728 progress 70 % (5 MB)
143 22:55:23.097013 progress 75 % (6 MB)
144 22:55:23.122101 progress 80 % (6 MB)
145 22:55:23.147628 progress 85 % (6 MB)
146 22:55:23.176374 progress 90 % (7 MB)
147 22:55:23.205186 progress 95 % (7 MB)
148 22:55:23.231037 progress 100 % (8 MB)
149 22:55:23.236259 8 MB downloaded in 0.51 s (16.10 MB/s)
150 22:55:23.236504 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:55:23.236772 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:55:23.236867 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 22:55:23.236966 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 22:55:24.703278 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13683739/extract-nfsrootfs-88_0ur2m
156 22:55:24.703486 end: 1.6.1 extract-nfsrootfs (duration 00:00:01) [common]
157 22:55:24.703587 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 22:55:24.703755 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z
159 22:55:24.703881 makedir: /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin
160 22:55:24.703986 makedir: /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/tests
161 22:55:24.704084 makedir: /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/results
162 22:55:24.704186 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-add-keys
163 22:55:24.704326 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-add-sources
164 22:55:24.704461 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-background-process-start
165 22:55:24.704594 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-background-process-stop
166 22:55:24.704726 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-common-functions
167 22:55:24.704857 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-echo-ipv4
168 22:55:24.704988 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-install-packages
169 22:55:24.705118 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-installed-packages
170 22:55:24.705248 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-os-build
171 22:55:24.705511 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-probe-channel
172 22:55:24.705645 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-probe-ip
173 22:55:24.705776 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-target-ip
174 22:55:24.705906 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-target-mac
175 22:55:24.706034 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-target-storage
176 22:55:24.706168 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-test-case
177 22:55:24.706299 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-test-event
178 22:55:24.706429 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-test-feedback
179 22:55:24.706559 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-test-raise
180 22:55:24.706688 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-test-reference
181 22:55:24.706819 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-test-runner
182 22:55:24.706949 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-test-set
183 22:55:24.707080 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-test-shell
184 22:55:24.707211 Updating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-install-packages (oe)
185 22:55:24.707370 Updating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/bin/lava-installed-packages (oe)
186 22:55:24.707498 Creating /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/environment
187 22:55:24.707599 LAVA metadata
188 22:55:24.707675 - LAVA_JOB_ID=13683739
189 22:55:24.707744 - LAVA_DISPATCHER_IP=192.168.201.1
190 22:55:24.707854 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 22:55:24.707926 skipped lava-vland-overlay
192 22:55:24.708002 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 22:55:24.708083 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 22:55:24.708145 skipped lava-multinode-overlay
195 22:55:24.708218 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 22:55:24.708306 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 22:55:24.708382 Loading test definitions
198 22:55:24.708475 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 22:55:24.708548 Using /lava-13683739 at stage 0
200 22:55:24.708828 uuid=13683739_1.6.2.3.1 testdef=None
201 22:55:24.708918 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 22:55:24.709004 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 22:55:24.709520 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 22:55:24.709743 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 22:55:24.710336 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 22:55:24.710566 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 22:55:24.711145 runner path: /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/0/tests/0_lc-compliance test_uuid 13683739_1.6.2.3.1
210 22:55:24.711302 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 22:55:24.711508 Creating lava-test-runner.conf files
213 22:55:24.711572 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683739/lava-overlay-04xbe5_z/lava-13683739/0 for stage 0
214 22:55:24.711660 - 0_lc-compliance
215 22:55:24.711759 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 22:55:24.711844 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 22:55:24.717648 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 22:55:24.717753 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 22:55:24.717840 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 22:55:24.717926 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 22:55:24.718013 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 22:55:24.878607 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 22:55:24.878963 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 22:55:24.879081 extracting modules file /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683739/extract-nfsrootfs-88_0ur2m
225 22:55:25.083469 extracting modules file /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683739/extract-overlay-ramdisk-mi8k2bzl/ramdisk
226 22:55:25.291898 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 22:55:25.292073 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 22:55:25.292168 [common] Applying overlay to NFS
229 22:55:25.292243 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683739/compress-overlay-qbt9xn14/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683739/extract-nfsrootfs-88_0ur2m
230 22:55:25.298590 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 22:55:25.298704 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 22:55:25.298801 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 22:55:25.298887 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 22:55:25.298970 Building ramdisk /var/lib/lava/dispatcher/tmp/13683739/extract-overlay-ramdisk-mi8k2bzl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683739/extract-overlay-ramdisk-mi8k2bzl/ramdisk
235 22:55:25.615272 >> 130327 blocks
236 22:55:27.638935 rename /var/lib/lava/dispatcher/tmp/13683739/extract-overlay-ramdisk-mi8k2bzl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/ramdisk/ramdisk.cpio.gz
237 22:55:27.639521 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 22:55:27.639735 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 22:55:27.639907 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 22:55:27.640096 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/kernel/Image'
241 22:55:40.634877 Returned 0 in 12 seconds
242 22:55:40.735492 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/kernel/image.itb
243 22:55:41.098410 output: FIT description: Kernel Image image with one or more FDT blobs
244 22:55:41.098772 output: Created: Tue May 7 23:55:41 2024
245 22:55:41.098847 output: Image 0 (kernel-1)
246 22:55:41.098914 output: Description:
247 22:55:41.098978 output: Created: Tue May 7 23:55:41 2024
248 22:55:41.099039 output: Type: Kernel Image
249 22:55:41.099102 output: Compression: lzma compressed
250 22:55:41.099160 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
251 22:55:41.099222 output: Architecture: AArch64
252 22:55:41.099282 output: OS: Linux
253 22:55:41.099348 output: Load Address: 0x00000000
254 22:55:41.099408 output: Entry Point: 0x00000000
255 22:55:41.099468 output: Hash algo: crc32
256 22:55:41.099526 output: Hash value: 727ee7c6
257 22:55:41.099604 output: Image 1 (fdt-1)
258 22:55:41.099663 output: Description: mt8192-asurada-spherion-r0
259 22:55:41.099721 output: Created: Tue May 7 23:55:41 2024
260 22:55:41.099778 output: Type: Flat Device Tree
261 22:55:41.099833 output: Compression: uncompressed
262 22:55:41.099888 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 22:55:41.099943 output: Architecture: AArch64
264 22:55:41.099997 output: Hash algo: crc32
265 22:55:41.100052 output: Hash value: 0f8e4d2e
266 22:55:41.100106 output: Image 2 (ramdisk-1)
267 22:55:41.100160 output: Description: unavailable
268 22:55:41.100214 output: Created: Tue May 7 23:55:41 2024
269 22:55:41.100269 output: Type: RAMDisk Image
270 22:55:41.100323 output: Compression: Unknown Compression
271 22:55:41.100377 output: Data Size: 18732252 Bytes = 18293.21 KiB = 17.86 MiB
272 22:55:41.100431 output: Architecture: AArch64
273 22:55:41.100486 output: OS: Linux
274 22:55:41.100540 output: Load Address: unavailable
275 22:55:41.100594 output: Entry Point: unavailable
276 22:55:41.100648 output: Hash algo: crc32
277 22:55:41.100702 output: Hash value: ba3c2c4c
278 22:55:41.100756 output: Default Configuration: 'conf-1'
279 22:55:41.100810 output: Configuration 0 (conf-1)
280 22:55:41.100864 output: Description: mt8192-asurada-spherion-r0
281 22:55:41.100918 output: Kernel: kernel-1
282 22:55:41.100972 output: Init Ramdisk: ramdisk-1
283 22:55:41.101026 output: FDT: fdt-1
284 22:55:41.101080 output: Loadables: kernel-1
285 22:55:41.101134 output:
286 22:55:41.101355 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 22:55:41.101478 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 22:55:41.101589 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 22:55:41.101684 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:38) [common]
290 22:55:41.101768 No LXC device requested
291 22:55:41.101849 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 22:55:41.101936 start: 1.8 deploy-device-env (timeout 00:09:38) [common]
293 22:55:41.102019 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 22:55:41.102088 Checking files for TFTP limit of 4294967296 bytes.
295 22:55:41.102579 end: 1 tftp-deploy (duration 00:00:22) [common]
296 22:55:41.102682 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 22:55:41.102779 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 22:55:41.102926 substitutions:
299 22:55:41.102996 - {DTB}: 13683739/tftp-deploy-o0ljxgg6/dtb/mt8192-asurada-spherion-r0.dtb
300 22:55:41.103063 - {INITRD}: 13683739/tftp-deploy-o0ljxgg6/ramdisk/ramdisk.cpio.gz
301 22:55:41.103125 - {KERNEL}: 13683739/tftp-deploy-o0ljxgg6/kernel/Image
302 22:55:41.103184 - {LAVA_MAC}: None
303 22:55:41.103243 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13683739/extract-nfsrootfs-88_0ur2m
304 22:55:41.103301 - {NFS_SERVER_IP}: 192.168.201.1
305 22:55:41.103357 - {PRESEED_CONFIG}: None
306 22:55:41.103414 - {PRESEED_LOCAL}: None
307 22:55:41.103469 - {RAMDISK}: 13683739/tftp-deploy-o0ljxgg6/ramdisk/ramdisk.cpio.gz
308 22:55:41.103525 - {ROOT_PART}: None
309 22:55:41.103603 - {ROOT}: None
310 22:55:41.103682 - {SERVER_IP}: 192.168.201.1
311 22:55:41.103759 - {TEE}: None
312 22:55:41.103835 Parsed boot commands:
313 22:55:41.103910 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 22:55:41.104127 Parsed boot commands: tftpboot 192.168.201.1 13683739/tftp-deploy-o0ljxgg6/kernel/image.itb 13683739/tftp-deploy-o0ljxgg6/kernel/cmdline
315 22:55:41.104254 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 22:55:41.104385 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 22:55:41.104523 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 22:55:41.104627 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 22:55:41.104711 Not connected, no need to disconnect.
320 22:55:41.104808 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 22:55:41.104910 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 22:55:41.105019 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
323 22:55:41.108610 Setting prompt string to ['lava-test: # ']
324 22:55:41.108958 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 22:55:41.109112 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 22:55:41.109256 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 22:55:41.109420 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 22:55:41.109623 Calling: '/usr/local/bin/chromebook-reboot.sh' 'mt8192-asurada-spherion-r0-cbg-1'
329 22:55:54.615969 Returned 0 in 13 seconds
330 22:55:54.716652 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 22:55:54.717066 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 22:55:54.717216 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 22:55:54.717391 Setting prompt string to 'Starting depthcharge on Spherion...'
335 22:55:54.717474 Changing prompt to 'Starting depthcharge on Spherion...'
336 22:55:54.717568 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 22:55:54.717961 [Enter `^Ec?' for help]
338 22:55:54.718076
339 22:55:54.718183
340 22:55:54.718290 F0: 102B 0000
341 22:55:54.718394
342 22:55:54.718502 F3: 1001 0000 [0200]
343 22:55:54.718606
344 22:55:54.718705 F3: 1001 0000
345 22:55:54.718804
346 22:55:54.718903 F7: 102D 0000
347 22:55:54.719000
348 22:55:54.719097 F1: 0000 0000
349 22:55:54.719193
350 22:55:54.719289 V0: 0000 0000 [0001]
351 22:55:54.719384
352 22:55:54.719480 00: 0007 8000
353 22:55:54.719580
354 22:55:54.719676 01: 0000 0000
355 22:55:54.719774
356 22:55:54.719869 BP: 0C00 0209 [0000]
357 22:55:54.719964
358 22:55:54.720060 G0: 1182 0000
359 22:55:54.720155
360 22:55:54.720250 EC: 0000 0021 [4000]
361 22:55:54.720345
362 22:55:54.720439 S7: 0000 0000 [0000]
363 22:55:54.720532
364 22:55:54.720626 CC: 0000 0000 [0001]
365 22:55:54.720720
366 22:55:54.720814 T0: 0000 0040 [010F]
367 22:55:54.720911
368 22:55:54.721006 Jump to BL
369 22:55:54.721101
370 22:55:54.721196
371 22:55:54.721290
372 22:55:54.721430
373 22:55:54.721526 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 22:55:54.721625 ARM64: Exception handlers installed.
375 22:55:54.721721 ARM64: Testing exception
376 22:55:54.721817 ARM64: Done test exception
377 22:55:54.721911 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 22:55:54.722008 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 22:55:54.722103 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 22:55:54.722199 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 22:55:54.722294 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 22:55:54.722390 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 22:55:54.722484 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 22:55:54.722580 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 22:55:54.722675 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 22:55:54.722770 WDT: Last reset was cold boot
387 22:55:54.722864 SPI1(PAD0) initialized at 2873684 Hz
388 22:55:54.722959 SPI5(PAD0) initialized at 992727 Hz
389 22:55:54.723052 VBOOT: Loading verstage.
390 22:55:54.723146 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 22:55:54.723241 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 22:55:54.723337 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 22:55:54.723432 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 22:55:54.723527 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 22:55:54.723621 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 22:55:54.723717 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
397 22:55:54.723811
398 22:55:54.723906
399 22:55:54.724000 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 22:55:54.724096 ARM64: Exception handlers installed.
401 22:55:54.724190 ARM64: Testing exception
402 22:55:54.724284 ARM64: Done test exception
403 22:55:54.724379 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 22:55:54.724474 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 22:55:54.724568 Probing TPM: . done!
406 22:55:54.724662 TPM ready after 0 ms
407 22:55:54.724757 Connected to device vid:did:rid of 1ae0:0028:00
408 22:55:54.724852 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 22:55:54.724948 Initialized TPM device CR50 revision 0
410 22:55:54.725042 tlcl_send_startup: Startup return code is 0
411 22:55:54.725137 TPM: setup succeeded
412 22:55:54.725233 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 22:55:54.725371 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 22:55:54.725468 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 22:55:54.725563 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 22:55:54.725658 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 22:55:54.725753 in-header: 03 07 00 00 08 00 00 00
418 22:55:54.725848 in-data: aa e4 47 04 13 02 00 00
419 22:55:54.725942 Chrome EC: UHEPI supported
420 22:55:54.726036 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 22:55:54.726131 in-header: 03 a9 00 00 08 00 00 00
422 22:55:54.726226 in-data: 84 60 60 08 00 00 00 00
423 22:55:54.726319 Phase 1
424 22:55:54.726415 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 22:55:54.726510 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 22:55:54.726606 VB2:vb2_check_recovery() Recovery was requested manually
427 22:55:54.726701 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
428 22:55:54.726796 Recovery requested (1009000e)
429 22:55:54.726890 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 22:55:54.726985 tlcl_extend: response is 0
431 22:55:54.727079 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 22:55:54.727174 tlcl_extend: response is 0
433 22:55:54.727268 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 22:55:54.727362 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 22:55:54.727457 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 22:55:54.727551
437 22:55:54.727645
438 22:55:54.727740 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 22:55:54.727834 ARM64: Exception handlers installed.
440 22:55:54.727929 ARM64: Testing exception
441 22:55:54.728023 ARM64: Done test exception
442 22:55:54.728117 pmic_efuse_setting: Set efuses in 11 msecs
443 22:55:54.728211 pmwrap_interface_init: Select PMIF_VLD_RDY
444 22:55:54.728305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 22:55:54.728399 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 22:55:54.728692 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 22:55:54.728789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 22:55:54.728887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 22:55:54.728983 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 22:55:54.729079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 22:55:54.729174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 22:55:54.729269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 22:55:54.729407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 22:55:54.729503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 22:55:54.729599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 22:55:54.729695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 22:55:54.729790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 22:55:54.729885 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 22:55:54.729980 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 22:55:54.730075 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 22:55:54.730169 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 22:55:54.730276 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 22:55:54.730369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 22:55:54.730461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 22:55:54.730554 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 22:55:54.730646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 22:55:54.730739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 22:55:54.730831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 22:55:54.730924 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 22:55:54.731016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 22:55:54.731109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 22:55:54.731201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 22:55:54.731293 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 22:55:54.731385 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 22:55:54.731478 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 22:55:54.731570 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 22:55:54.731663 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 22:55:54.731755 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 22:55:54.731847 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 22:55:54.731939 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 22:55:54.732032 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 22:55:54.732125 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 22:55:54.732217 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 22:55:54.732310 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 22:55:54.732402 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 22:55:54.732494 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 22:55:54.732586 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 22:55:54.732726 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 22:55:54.732832 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 22:55:54.732924 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 22:55:54.733016 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 22:55:54.733107 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 22:55:54.733200 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 22:55:54.733292 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 22:55:54.733428 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
496 22:55:54.733537 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 22:55:54.733630 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 22:55:54.733723 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 22:55:54.733816 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 22:55:54.733909 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 22:55:54.734002 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 22:55:54.734094 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 22:55:54.734186 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
504 22:55:54.734279 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 22:55:54.734372 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 22:55:54.734464 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 22:55:54.734556 [RTC]rtc_get_frequency_meter,154: input=15, output=773
508 22:55:54.734649 [RTC]rtc_get_frequency_meter,154: input=23, output=957
509 22:55:54.734741 [RTC]rtc_get_frequency_meter,154: input=19, output=866
510 22:55:54.734834 [RTC]rtc_get_frequency_meter,154: input=17, output=818
511 22:55:54.734926 [RTC]rtc_get_frequency_meter,154: input=16, output=795
512 22:55:54.735018 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
513 22:55:54.735111 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
514 22:55:54.735205 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
515 22:55:54.735297 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
516 22:55:54.735582 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
517 22:55:54.735737 ADC[4]: Raw value=902507 ID=7
518 22:55:54.735836 ADC[3]: Raw value=213179 ID=1
519 22:55:54.735933 RAM Code: 0x71
520 22:55:54.736029 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
521 22:55:54.736155 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
522 22:55:54.736263 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
523 22:55:54.736358 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
524 22:55:54.736453 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
525 22:55:54.736547 in-header: 03 07 00 00 08 00 00 00
526 22:55:54.736640 in-data: aa e4 47 04 13 02 00 00
527 22:55:54.736733 Chrome EC: UHEPI supported
528 22:55:54.736828 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
529 22:55:54.736923 in-header: 03 a9 00 00 08 00 00 00
530 22:55:54.737017 in-data: 84 60 60 08 00 00 00 00
531 22:55:54.737110 MRC: failed to locate region type 0.
532 22:55:54.737204 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
533 22:55:54.737324 DRAM-K: Running full calibration
534 22:55:54.737436 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
535 22:55:54.737531 header.status = 0x0
536 22:55:54.737638 header.version = 0x6 (expected: 0x6)
537 22:55:54.737732 header.size = 0xd00 (expected: 0xd00)
538 22:55:54.737825 header.flags = 0x0
539 22:55:54.737918 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
540 22:55:54.738012 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
541 22:55:54.738106 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
542 22:55:54.738199 dram_init: ddr_geometry: 2
543 22:55:54.738292 [EMI] MDL number = 2
544 22:55:54.738384 [EMI] Get MDL freq = 0
545 22:55:54.738476 dram_init: ddr_type: 0
546 22:55:54.738569 is_discrete_lpddr4: 1
547 22:55:54.738661 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
548 22:55:54.738753
549 22:55:54.738846
550 22:55:54.738939 [Bian_co] ETT version 0.0.0.1
551 22:55:54.739032 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
552 22:55:54.739125
553 22:55:54.739217 dramc_set_vcore_voltage set vcore to 650000
554 22:55:54.739326 Read voltage for 800, 4
555 22:55:54.739432 Vio18 = 0
556 22:55:54.739524 Vcore = 650000
557 22:55:54.739617 Vdram = 0
558 22:55:54.739710 Vddq = 0
559 22:55:54.739803 Vmddr = 0
560 22:55:54.739895 dram_init: config_dvfs: 1
561 22:55:54.739989 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
562 22:55:54.740082 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
563 22:55:54.740175 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
564 22:55:54.740269 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
565 22:55:54.740365 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
566 22:55:54.740459 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
567 22:55:54.740552 MEM_TYPE=3, freq_sel=18
568 22:55:54.740645 sv_algorithm_assistance_LP4_1600
569 22:55:54.740738 ============ PULL DRAM RESETB DOWN ============
570 22:55:54.740835 ========== PULL DRAM RESETB DOWN end =========
571 22:55:54.740928 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
572 22:55:54.741021 ===================================
573 22:55:54.741114 LPDDR4 DRAM CONFIGURATION
574 22:55:54.741207 ===================================
575 22:55:54.741303 EX_ROW_EN[0] = 0x0
576 22:55:54.741431 EX_ROW_EN[1] = 0x0
577 22:55:54.741524 LP4Y_EN = 0x0
578 22:55:54.741616 WORK_FSP = 0x0
579 22:55:54.741708 WL = 0x2
580 22:55:54.741801 RL = 0x2
581 22:55:54.741892 BL = 0x2
582 22:55:54.741984 RPST = 0x0
583 22:55:54.742077 RD_PRE = 0x0
584 22:55:54.742169 WR_PRE = 0x1
585 22:55:54.742261 WR_PST = 0x0
586 22:55:54.742353 DBI_WR = 0x0
587 22:55:54.742444 DBI_RD = 0x0
588 22:55:54.742537 OTF = 0x1
589 22:55:54.742695 ===================================
590 22:55:54.742789 ===================================
591 22:55:54.742882 ANA top config
592 22:55:54.742975 ===================================
593 22:55:54.743067 DLL_ASYNC_EN = 0
594 22:55:54.743161 ALL_SLAVE_EN = 1
595 22:55:54.743253 NEW_RANK_MODE = 1
596 22:55:54.743347 DLL_IDLE_MODE = 1
597 22:55:54.743439 LP45_APHY_COMB_EN = 1
598 22:55:54.743531 TX_ODT_DIS = 1
599 22:55:54.743624 NEW_8X_MODE = 1
600 22:55:54.743718 ===================================
601 22:55:54.743810 ===================================
602 22:55:54.743904 data_rate = 1600
603 22:55:54.743996 CKR = 1
604 22:55:54.744088 DQ_P2S_RATIO = 8
605 22:55:54.744181 ===================================
606 22:55:54.744273 CA_P2S_RATIO = 8
607 22:55:54.744366 DQ_CA_OPEN = 0
608 22:55:54.744458 DQ_SEMI_OPEN = 0
609 22:55:54.744550 CA_SEMI_OPEN = 0
610 22:55:54.744643 CA_FULL_RATE = 0
611 22:55:54.744735 DQ_CKDIV4_EN = 1
612 22:55:54.744827 CA_CKDIV4_EN = 1
613 22:55:54.744918 CA_PREDIV_EN = 0
614 22:55:54.745010 PH8_DLY = 0
615 22:55:54.745102 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
616 22:55:54.745194 DQ_AAMCK_DIV = 4
617 22:55:54.745286 CA_AAMCK_DIV = 4
618 22:55:54.745426 CA_ADMCK_DIV = 4
619 22:55:54.745518 DQ_TRACK_CA_EN = 0
620 22:55:54.745611 CA_PICK = 800
621 22:55:54.745703 CA_MCKIO = 800
622 22:55:54.745796 MCKIO_SEMI = 0
623 22:55:54.745887 PLL_FREQ = 3068
624 22:55:54.745980 DQ_UI_PI_RATIO = 32
625 22:55:54.746072 CA_UI_PI_RATIO = 0
626 22:55:54.746164 ===================================
627 22:55:54.746286 ===================================
628 22:55:54.746378 memory_type:LPDDR4
629 22:55:54.746470 GP_NUM : 10
630 22:55:54.746562 SRAM_EN : 1
631 22:55:54.746713 MD32_EN : 0
632 22:55:54.746805 ===================================
633 22:55:54.746898 [ANA_INIT] >>>>>>>>>>>>>>
634 22:55:54.746991 <<<<<< [CONFIGURE PHASE]: ANA_TX
635 22:55:54.747086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
636 22:55:54.747179 ===================================
637 22:55:54.747480 data_rate = 1600,PCW = 0X7600
638 22:55:54.747632 ===================================
639 22:55:54.747731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
640 22:55:54.747829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
641 22:55:54.747926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
642 22:55:54.748036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
643 22:55:54.748130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
644 22:55:54.748224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
645 22:55:54.748318 [ANA_INIT] flow start
646 22:55:54.748412 [ANA_INIT] PLL >>>>>>>>
647 22:55:54.748504 [ANA_INIT] PLL <<<<<<<<
648 22:55:54.748627 [ANA_INIT] MIDPI >>>>>>>>
649 22:55:54.748766 [ANA_INIT] MIDPI <<<<<<<<
650 22:55:54.748872 [ANA_INIT] DLL >>>>>>>>
651 22:55:54.748965 [ANA_INIT] flow end
652 22:55:54.749056 ============ LP4 DIFF to SE enter ============
653 22:55:54.749149 ============ LP4 DIFF to SE exit ============
654 22:55:54.749242 [ANA_INIT] <<<<<<<<<<<<<
655 22:55:54.749371 [Flow] Enable top DCM control >>>>>
656 22:55:54.749509 [Flow] Enable top DCM control <<<<<
657 22:55:54.749602 Enable DLL master slave shuffle
658 22:55:54.749695 ==============================================================
659 22:55:54.749788 Gating Mode config
660 22:55:54.749881 ==============================================================
661 22:55:54.749975 Config description:
662 22:55:54.750068 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
663 22:55:54.750162 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
664 22:55:54.750255 SELPH_MODE 0: By rank 1: By Phase
665 22:55:54.750354 ==============================================================
666 22:55:54.750447 GAT_TRACK_EN = 1
667 22:55:54.750540 RX_GATING_MODE = 2
668 22:55:54.750633 RX_GATING_TRACK_MODE = 2
669 22:55:54.750725 SELPH_MODE = 1
670 22:55:54.750817 PICG_EARLY_EN = 1
671 22:55:54.750909 VALID_LAT_VALUE = 1
672 22:55:54.751002 ==============================================================
673 22:55:54.751095 Enter into Gating configuration >>>>
674 22:55:54.751187 Exit from Gating configuration <<<<
675 22:55:54.751280 Enter into DVFS_PRE_config >>>>>
676 22:55:54.751372 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
677 22:55:54.751468 Exit from DVFS_PRE_config <<<<<
678 22:55:54.751561 Enter into PICG configuration >>>>
679 22:55:54.751653 Exit from PICG configuration <<<<
680 22:55:54.751746 [RX_INPUT] configuration >>>>>
681 22:55:54.751838 [RX_INPUT] configuration <<<<<
682 22:55:54.751930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
683 22:55:54.752022 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
684 22:55:54.752115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
685 22:55:54.752208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
686 22:55:54.752300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
687 22:55:54.752392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
688 22:55:54.752484 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
689 22:55:54.752605 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
690 22:55:54.752698 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
691 22:55:54.752790 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
692 22:55:54.752882 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
693 22:55:54.752974 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 22:55:54.753066 ===================================
695 22:55:54.753158 LPDDR4 DRAM CONFIGURATION
696 22:55:54.753250 ===================================
697 22:55:54.753380 EX_ROW_EN[0] = 0x0
698 22:55:54.753473 EX_ROW_EN[1] = 0x0
699 22:55:54.753565 LP4Y_EN = 0x0
700 22:55:54.753658 WORK_FSP = 0x0
701 22:55:54.753750 WL = 0x2
702 22:55:54.753843 RL = 0x2
703 22:55:54.753936 BL = 0x2
704 22:55:54.754028 RPST = 0x0
705 22:55:54.754120 RD_PRE = 0x0
706 22:55:54.754212 WR_PRE = 0x1
707 22:55:54.754303 WR_PST = 0x0
708 22:55:54.754395 DBI_WR = 0x0
709 22:55:54.754487 DBI_RD = 0x0
710 22:55:54.754579 OTF = 0x1
711 22:55:54.754671 ===================================
712 22:55:54.754767 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
713 22:55:54.754854 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
714 22:55:54.754959 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
715 22:55:54.755066 ===================================
716 22:55:54.755172 LPDDR4 DRAM CONFIGURATION
717 22:55:54.755273 ===================================
718 22:55:54.755380 EX_ROW_EN[0] = 0x10
719 22:55:54.755477 EX_ROW_EN[1] = 0x0
720 22:55:54.755577 LP4Y_EN = 0x0
721 22:55:54.755675 WORK_FSP = 0x0
722 22:55:54.755773 WL = 0x2
723 22:55:54.755870 RL = 0x2
724 22:55:54.755982 BL = 0x2
725 22:55:54.756107 RPST = 0x0
726 22:55:54.756216 RD_PRE = 0x0
727 22:55:54.756312 WR_PRE = 0x1
728 22:55:54.756408 WR_PST = 0x0
729 22:55:54.756502 DBI_WR = 0x0
730 22:55:54.756594 DBI_RD = 0x0
731 22:55:54.756683 OTF = 0x1
732 22:55:54.756778 ===================================
733 22:55:54.756874 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
734 22:55:54.756967 nWR fixed to 40
735 22:55:54.757061 [ModeRegInit_LP4] CH0 RK0
736 22:55:54.757155 [ModeRegInit_LP4] CH0 RK1
737 22:55:54.757247 [ModeRegInit_LP4] CH1 RK0
738 22:55:54.757377 [ModeRegInit_LP4] CH1 RK1
739 22:55:54.757472 match AC timing 13
740 22:55:54.757566 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
741 22:55:54.757660 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
742 22:55:54.757754 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
743 22:55:54.757848 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
744 22:55:54.758166 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
745 22:55:54.758271 [EMI DOE] emi_dcm 0
746 22:55:54.758372 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
747 22:55:54.758470 ==
748 22:55:54.758570 Dram Type= 6, Freq= 0, CH_0, rank 0
749 22:55:54.758670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 22:55:54.758770 ==
751 22:55:54.758869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 22:55:54.758969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 22:55:54.759069 [CA 0] Center 38 (7~69) winsize 63
754 22:55:54.759168 [CA 1] Center 38 (7~69) winsize 63
755 22:55:54.759267 [CA 2] Center 35 (5~66) winsize 62
756 22:55:54.759367 [CA 3] Center 35 (5~66) winsize 62
757 22:55:54.759461 [CA 4] Center 35 (4~66) winsize 63
758 22:55:54.759557 [CA 5] Center 33 (3~64) winsize 62
759 22:55:54.759669
760 22:55:54.759780 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 22:55:54.759898
762 22:55:54.760025 [CATrainingPosCal] consider 1 rank data
763 22:55:54.760159 u2DelayCellTimex100 = 270/100 ps
764 22:55:54.760268 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
765 22:55:54.760383 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
766 22:55:54.760495 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 22:55:54.760612 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
768 22:55:54.760745 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
769 22:55:54.760876 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 22:55:54.760991
771 22:55:54.761108 CA PerBit enable=1, Macro0, CA PI delay=33
772 22:55:54.761221
773 22:55:54.761333 [CBTSetCACLKResult] CA Dly = 33
774 22:55:54.761456 CS Dly: 5 (0~36)
775 22:55:54.761558 ==
776 22:55:54.761664 Dram Type= 6, Freq= 0, CH_0, rank 1
777 22:55:54.761775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 22:55:54.761922 ==
779 22:55:54.762055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
780 22:55:54.762162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
781 22:55:54.762274 [CA 0] Center 38 (7~69) winsize 63
782 22:55:54.762377 [CA 1] Center 38 (7~69) winsize 63
783 22:55:54.762501 [CA 2] Center 36 (5~67) winsize 63
784 22:55:54.762625 [CA 3] Center 36 (5~67) winsize 63
785 22:55:54.762749 [CA 4] Center 35 (4~66) winsize 63
786 22:55:54.762886 [CA 5] Center 34 (4~65) winsize 62
787 22:55:54.762982
788 22:55:54.763077 [CmdBusTrainingLP45] Vref(ca) range 1: 32
789 22:55:54.763172
790 22:55:54.763266 [CATrainingPosCal] consider 2 rank data
791 22:55:54.763361 u2DelayCellTimex100 = 270/100 ps
792 22:55:54.763456 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
793 22:55:54.763550 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
794 22:55:54.763644 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
795 22:55:54.763738 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
796 22:55:54.763831 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
797 22:55:54.763926 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
798 22:55:54.764039
799 22:55:54.764143 CA PerBit enable=1, Macro0, CA PI delay=34
800 22:55:54.764246
801 22:55:54.764342 [CBTSetCACLKResult] CA Dly = 34
802 22:55:54.764444 CS Dly: 6 (0~38)
803 22:55:54.764546
804 22:55:54.764647 ----->DramcWriteLeveling(PI) begin...
805 22:55:54.764745 ==
806 22:55:54.764838 Dram Type= 6, Freq= 0, CH_0, rank 0
807 22:55:54.764938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 22:55:54.765040 ==
809 22:55:54.765143 Write leveling (Byte 0): 30 => 30
810 22:55:54.765250 Write leveling (Byte 1): 29 => 29
811 22:55:54.765405 DramcWriteLeveling(PI) end<-----
812 22:55:54.765508
813 22:55:54.765613 ==
814 22:55:54.765724 Dram Type= 6, Freq= 0, CH_0, rank 0
815 22:55:54.765841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
816 22:55:54.765949 ==
817 22:55:54.766056 [Gating] SW mode calibration
818 22:55:54.766223 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
819 22:55:54.766331 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
820 22:55:54.766439 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
821 22:55:54.766549 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
822 22:55:54.766659 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
823 22:55:54.766768 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:55:54.766876 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:55:54.766984 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:55:54.767103 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:55:54.767223 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:55:54.767326 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 22:55:54.767415 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 22:55:54.767502 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 22:55:54.767587 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 22:55:54.767672 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 22:55:54.767757 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 22:55:54.767858 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 22:55:54.767957 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 22:55:54.768042 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
837 22:55:54.768126 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
838 22:55:54.768211 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
839 22:55:54.768295 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 22:55:54.768379 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 22:55:54.768464 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 22:55:54.768548 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 22:55:54.768633 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 22:55:54.768717 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 22:55:54.768801 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
846 22:55:54.768885 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
847 22:55:54.768970 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
848 22:55:54.769074 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 22:55:54.769202 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 22:55:54.769349 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 22:55:54.769442 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 22:55:54.769732 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 22:55:54.769848 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
854 22:55:54.769941 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (1 1) (0 0)
855 22:55:54.770047 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
856 22:55:54.770129 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:55:54.770208 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:55:54.770318 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:55:54.770410 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:55:54.770507 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:55:54.770604 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
862 22:55:54.770700 0 11 8 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
863 22:55:54.770796 0 11 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
864 22:55:54.770891 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 22:55:54.770987 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 22:55:54.771100 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 22:55:54.771197 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 22:55:54.771308 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 22:55:54.771403 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 22:55:54.771499 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
871 22:55:54.771594 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 22:55:54.771689 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 22:55:54.771783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 22:55:54.771902 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 22:55:54.772011 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 22:55:54.772106 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 22:55:54.772200 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 22:55:54.772295 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 22:55:54.772390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 22:55:54.772484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 22:55:54.772579 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 22:55:54.772673 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 22:55:54.772768 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 22:55:54.772862 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 22:55:54.772973 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
886 22:55:54.773070 Total UI for P1: 0, mck2ui 16
887 22:55:54.773181 best dqsien dly found for B0: ( 0, 14, 2)
888 22:55:54.773276 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 22:55:54.773411 Total UI for P1: 0, mck2ui 16
890 22:55:54.773508 best dqsien dly found for B1: ( 0, 14, 6)
891 22:55:54.773605 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
892 22:55:54.773737 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
893 22:55:54.773856
894 22:55:54.773955 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
895 22:55:54.774043 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
896 22:55:54.774157 [Gating] SW calibration Done
897 22:55:54.774242 ==
898 22:55:54.774329 Dram Type= 6, Freq= 0, CH_0, rank 0
899 22:55:54.774415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 22:55:54.774501 ==
901 22:55:54.774587 RX Vref Scan: 0
902 22:55:54.774672
903 22:55:54.774757 RX Vref 0 -> 0, step: 1
904 22:55:54.774842
905 22:55:54.774927 RX Delay -130 -> 252, step: 16
906 22:55:54.775013 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
907 22:55:54.775099 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 22:55:54.775185 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
909 22:55:54.775271 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
910 22:55:54.775356 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 22:55:54.775442 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
912 22:55:54.775527 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
913 22:55:54.775613 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
914 22:55:54.775699 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
915 22:55:54.775784 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
916 22:55:54.775881 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
917 22:55:54.775969 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
918 22:55:54.776055 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
919 22:55:54.776140 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
920 22:55:54.776226 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
921 22:55:54.776311 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 22:55:54.776422 ==
923 22:55:54.776520 Dram Type= 6, Freq= 0, CH_0, rank 0
924 22:55:54.776604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
925 22:55:54.776688 ==
926 22:55:54.776771 DQS Delay:
927 22:55:54.776854 DQS0 = 0, DQS1 = 0
928 22:55:54.776937 DQM Delay:
929 22:55:54.777020 DQM0 = 89, DQM1 = 79
930 22:55:54.777103 DQ Delay:
931 22:55:54.777187 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
932 22:55:54.777270 DQ4 =85, DQ5 =77, DQ6 =109, DQ7 =101
933 22:55:54.777397 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
934 22:55:54.777453 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
935 22:55:54.777508
936 22:55:54.777562
937 22:55:54.777617 ==
938 22:55:54.777672 Dram Type= 6, Freq= 0, CH_0, rank 0
939 22:55:54.777732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 22:55:54.777787 ==
941 22:55:54.777877
942 22:55:54.778000
943 22:55:54.778067 TX Vref Scan disable
944 22:55:54.778125 == TX Byte 0 ==
945 22:55:54.778181 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 22:55:54.778238 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 22:55:54.778293 == TX Byte 1 ==
948 22:55:54.778349 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 22:55:54.778405 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 22:55:54.778460 ==
951 22:55:54.778516 Dram Type= 6, Freq= 0, CH_0, rank 0
952 22:55:54.778571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 22:55:54.778627 ==
954 22:55:54.778682 TX Vref=22, minBit 6, minWin=27, winSum=442
955 22:55:54.778739 TX Vref=24, minBit 8, minWin=27, winSum=447
956 22:55:54.778794 TX Vref=26, minBit 8, minWin=27, winSum=450
957 22:55:54.778850 TX Vref=28, minBit 3, minWin=28, winSum=453
958 22:55:54.778906 TX Vref=30, minBit 5, minWin=28, winSum=457
959 22:55:54.778961 TX Vref=32, minBit 8, minWin=28, winSum=457
960 22:55:54.779229 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 30
961 22:55:54.779299
962 22:55:54.779357 Final TX Range 1 Vref 30
963 22:55:54.779412
964 22:55:54.779467 ==
965 22:55:54.779522 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:55:54.779577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:55:54.779634 ==
968 22:55:54.779688
969 22:55:54.779755
970 22:55:54.779825 TX Vref Scan disable
971 22:55:54.779923 == TX Byte 0 ==
972 22:55:54.780004 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 22:55:54.780062 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 22:55:54.780117 == TX Byte 1 ==
975 22:55:54.780172 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
976 22:55:54.780227 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
977 22:55:54.780281
978 22:55:54.780335 [DATLAT]
979 22:55:54.780389 Freq=800, CH0 RK0
980 22:55:54.780444
981 22:55:54.780498 DATLAT Default: 0xa
982 22:55:54.780552 0, 0xFFFF, sum = 0
983 22:55:54.780607 1, 0xFFFF, sum = 0
984 22:55:54.780663 2, 0xFFFF, sum = 0
985 22:55:54.780718 3, 0xFFFF, sum = 0
986 22:55:54.780776 4, 0xFFFF, sum = 0
987 22:55:54.780831 5, 0xFFFF, sum = 0
988 22:55:54.780886 6, 0xFFFF, sum = 0
989 22:55:54.780940 7, 0xFFFF, sum = 0
990 22:55:54.780994 8, 0xFFFF, sum = 0
991 22:55:54.781049 9, 0x0, sum = 1
992 22:55:54.781104 10, 0x0, sum = 2
993 22:55:54.781158 11, 0x0, sum = 3
994 22:55:54.781213 12, 0x0, sum = 4
995 22:55:54.781267 best_step = 10
996 22:55:54.781374
997 22:55:54.781444 ==
998 22:55:54.781499 Dram Type= 6, Freq= 0, CH_0, rank 0
999 22:55:54.781555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 22:55:54.781610 ==
1001 22:55:54.781663 RX Vref Scan: 1
1002 22:55:54.781716
1003 22:55:54.781770 Set Vref Range= 32 -> 127
1004 22:55:54.781839
1005 22:55:54.781916 RX Vref 32 -> 127, step: 1
1006 22:55:54.781971
1007 22:55:54.782025 RX Delay -79 -> 252, step: 8
1008 22:55:54.782079
1009 22:55:54.782134 Set Vref, RX VrefLevel [Byte0]: 32
1010 22:55:54.782188 [Byte1]: 32
1011 22:55:54.782242
1012 22:55:54.782296 Set Vref, RX VrefLevel [Byte0]: 33
1013 22:55:54.782350 [Byte1]: 33
1014 22:55:54.782404
1015 22:55:54.782473 Set Vref, RX VrefLevel [Byte0]: 34
1016 22:55:54.782528 [Byte1]: 34
1017 22:55:54.782612
1018 22:55:54.782668 Set Vref, RX VrefLevel [Byte0]: 35
1019 22:55:54.782737 [Byte1]: 35
1020 22:55:54.782807
1021 22:55:54.782934 Set Vref, RX VrefLevel [Byte0]: 36
1022 22:55:54.783020 [Byte1]: 36
1023 22:55:54.783076
1024 22:55:54.783130 Set Vref, RX VrefLevel [Byte0]: 37
1025 22:55:54.783210 [Byte1]: 37
1026 22:55:54.783288
1027 22:55:54.783344 Set Vref, RX VrefLevel [Byte0]: 38
1028 22:55:54.783400 [Byte1]: 38
1029 22:55:54.783454
1030 22:55:54.783511 Set Vref, RX VrefLevel [Byte0]: 39
1031 22:55:54.783566 [Byte1]: 39
1032 22:55:54.783620
1033 22:55:54.783676 Set Vref, RX VrefLevel [Byte0]: 40
1034 22:55:54.783730 [Byte1]: 40
1035 22:55:54.783784
1036 22:55:54.783838 Set Vref, RX VrefLevel [Byte0]: 41
1037 22:55:54.783892 [Byte1]: 41
1038 22:55:54.783946
1039 22:55:54.784000 Set Vref, RX VrefLevel [Byte0]: 42
1040 22:55:54.784055 [Byte1]: 42
1041 22:55:54.784109
1042 22:55:54.784164 Set Vref, RX VrefLevel [Byte0]: 43
1043 22:55:54.784236 [Byte1]: 43
1044 22:55:54.784305
1045 22:55:54.784359 Set Vref, RX VrefLevel [Byte0]: 44
1046 22:55:54.784413 [Byte1]: 44
1047 22:55:54.784467
1048 22:55:54.784520 Set Vref, RX VrefLevel [Byte0]: 45
1049 22:55:54.784574 [Byte1]: 45
1050 22:55:54.784628
1051 22:55:54.784682 Set Vref, RX VrefLevel [Byte0]: 46
1052 22:55:54.784736 [Byte1]: 46
1053 22:55:54.784840
1054 22:55:54.784934 Set Vref, RX VrefLevel [Byte0]: 47
1055 22:55:54.785004 [Byte1]: 47
1056 22:55:54.785058
1057 22:55:54.785112 Set Vref, RX VrefLevel [Byte0]: 48
1058 22:55:54.785166 [Byte1]: 48
1059 22:55:54.785219
1060 22:55:54.785273 Set Vref, RX VrefLevel [Byte0]: 49
1061 22:55:54.785365 [Byte1]: 49
1062 22:55:54.785419
1063 22:55:54.785473 Set Vref, RX VrefLevel [Byte0]: 50
1064 22:55:54.785527 [Byte1]: 50
1065 22:55:54.785581
1066 22:55:54.785634 Set Vref, RX VrefLevel [Byte0]: 51
1067 22:55:54.785688 [Byte1]: 51
1068 22:55:54.785741
1069 22:55:54.785795 Set Vref, RX VrefLevel [Byte0]: 52
1070 22:55:54.785849 [Byte1]: 52
1071 22:55:54.785933
1072 22:55:54.786060 Set Vref, RX VrefLevel [Byte0]: 53
1073 22:55:54.786149 [Byte1]: 53
1074 22:55:54.786233
1075 22:55:54.786317 Set Vref, RX VrefLevel [Byte0]: 54
1076 22:55:54.786401 [Byte1]: 54
1077 22:55:54.786484
1078 22:55:54.786568 Set Vref, RX VrefLevel [Byte0]: 55
1079 22:55:54.786625 [Byte1]: 55
1080 22:55:54.786680
1081 22:55:54.786735 Set Vref, RX VrefLevel [Byte0]: 56
1082 22:55:54.786789 [Byte1]: 56
1083 22:55:54.786844
1084 22:55:54.786898 Set Vref, RX VrefLevel [Byte0]: 57
1085 22:55:54.786969 [Byte1]: 57
1086 22:55:54.787095
1087 22:55:54.787182 Set Vref, RX VrefLevel [Byte0]: 58
1088 22:55:54.787269 [Byte1]: 58
1089 22:55:54.787324
1090 22:55:54.787379 Set Vref, RX VrefLevel [Byte0]: 59
1091 22:55:54.787434 [Byte1]: 59
1092 22:55:54.787490
1093 22:55:54.787545 Set Vref, RX VrefLevel [Byte0]: 60
1094 22:55:54.787600 [Byte1]: 60
1095 22:55:54.787655
1096 22:55:54.787710 Set Vref, RX VrefLevel [Byte0]: 61
1097 22:55:54.787765 [Byte1]: 61
1098 22:55:54.787820
1099 22:55:54.787875 Set Vref, RX VrefLevel [Byte0]: 62
1100 22:55:54.787930 [Byte1]: 62
1101 22:55:54.788015
1102 22:55:54.788083 Set Vref, RX VrefLevel [Byte0]: 63
1103 22:55:54.788138 [Byte1]: 63
1104 22:55:54.788191
1105 22:55:54.788246 Set Vref, RX VrefLevel [Byte0]: 64
1106 22:55:54.788300 [Byte1]: 64
1107 22:55:54.788353
1108 22:55:54.788456 Set Vref, RX VrefLevel [Byte0]: 65
1109 22:55:54.788526 [Byte1]: 65
1110 22:55:54.788579
1111 22:55:54.788633 Set Vref, RX VrefLevel [Byte0]: 66
1112 22:55:54.788687 [Byte1]: 66
1113 22:55:54.788740
1114 22:55:54.788794 Set Vref, RX VrefLevel [Byte0]: 67
1115 22:55:54.788848 [Byte1]: 67
1116 22:55:54.788902
1117 22:55:54.788956 Set Vref, RX VrefLevel [Byte0]: 68
1118 22:55:54.789014 [Byte1]: 68
1119 22:55:54.789069
1120 22:55:54.789123 Set Vref, RX VrefLevel [Byte0]: 69
1121 22:55:54.789177 [Byte1]: 69
1122 22:55:54.789231
1123 22:55:54.789285 Set Vref, RX VrefLevel [Byte0]: 70
1124 22:55:54.789380 [Byte1]: 70
1125 22:55:54.789435
1126 22:55:54.789488 Set Vref, RX VrefLevel [Byte0]: 71
1127 22:55:54.789543 [Byte1]: 71
1128 22:55:54.789597
1129 22:55:54.789651 Set Vref, RX VrefLevel [Byte0]: 72
1130 22:55:54.789704 [Byte1]: 72
1131 22:55:54.789758
1132 22:55:54.789812 Set Vref, RX VrefLevel [Byte0]: 73
1133 22:55:54.790079 [Byte1]: 73
1134 22:55:54.790148
1135 22:55:54.790243 Set Vref, RX VrefLevel [Byte0]: 74
1136 22:55:54.790334 [Byte1]: 74
1137 22:55:54.790408
1138 22:55:54.790482 Set Vref, RX VrefLevel [Byte0]: 75
1139 22:55:54.790559 [Byte1]: 75
1140 22:55:54.790632
1141 22:55:54.790725 Set Vref, RX VrefLevel [Byte0]: 76
1142 22:55:54.790819 [Byte1]: 76
1143 22:55:54.790912
1144 22:55:54.791005 Set Vref, RX VrefLevel [Byte0]: 77
1145 22:55:54.791098 [Byte1]: 77
1146 22:55:54.791191
1147 22:55:54.791283 Set Vref, RX VrefLevel [Byte0]: 78
1148 22:55:54.791375 [Byte1]: 78
1149 22:55:54.791467
1150 22:55:54.791559 Set Vref, RX VrefLevel [Byte0]: 79
1151 22:55:54.791652 [Byte1]: 79
1152 22:55:54.791744
1153 22:55:54.791838 Final RX Vref Byte 0 = 62 to rank0
1154 22:55:54.792005 Final RX Vref Byte 1 = 63 to rank0
1155 22:55:54.792132 Final RX Vref Byte 0 = 62 to rank1
1156 22:55:54.792242 Final RX Vref Byte 1 = 63 to rank1==
1157 22:55:54.792366 Dram Type= 6, Freq= 0, CH_0, rank 0
1158 22:55:54.792491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 22:55:54.792592 ==
1160 22:55:54.792699 DQS Delay:
1161 22:55:54.792806 DQS0 = 0, DQS1 = 0
1162 22:55:54.792900 DQM Delay:
1163 22:55:54.793003 DQM0 = 93, DQM1 = 82
1164 22:55:54.793094 DQ Delay:
1165 22:55:54.793185 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1166 22:55:54.793293 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1167 22:55:54.793420 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1168 22:55:54.793518 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1169 22:55:54.793672
1170 22:55:54.793811
1171 22:55:54.793908 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1172 22:55:54.794022 CH0 RK0: MR19=606, MR18=3D38
1173 22:55:54.794150 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1174 22:55:54.794296
1175 22:55:54.794427 ----->DramcWriteLeveling(PI) begin...
1176 22:55:54.794573 ==
1177 22:55:54.794665 Dram Type= 6, Freq= 0, CH_0, rank 1
1178 22:55:54.794790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 22:55:54.794881 ==
1180 22:55:54.794971 Write leveling (Byte 0): 29 => 29
1181 22:55:54.795064 Write leveling (Byte 1): 27 => 27
1182 22:55:54.795154 DramcWriteLeveling(PI) end<-----
1183 22:55:54.795243
1184 22:55:54.795332 ==
1185 22:55:54.795421 Dram Type= 6, Freq= 0, CH_0, rank 1
1186 22:55:54.795513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 22:55:54.795603 ==
1188 22:55:54.795693 [Gating] SW mode calibration
1189 22:55:54.795785 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1190 22:55:54.795876 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1191 22:55:54.795969 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1192 22:55:54.796059 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1193 22:55:54.796150 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:55:54.796240 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:55:54.796333 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:55:54.796430 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:55:54.796518 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 22:55:54.796605 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 22:55:54.796691 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 22:55:54.796780 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:55:54.796867 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 22:55:54.796958 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 22:55:54.797055 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:55:54.797160 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:55:54.797260 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 22:55:54.797417 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 22:55:54.797531 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 22:55:54.797625 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1209 22:55:54.797776 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1210 22:55:54.797904 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 22:55:54.798035 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 22:55:54.798164 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 22:55:54.798279 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 22:55:54.798365 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 22:55:54.798451 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 22:55:54.798537 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1217 22:55:54.798624 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1218 22:55:54.798725 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 22:55:54.798809 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 22:55:54.798893 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 22:55:54.798977 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 22:55:54.799061 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 22:55:54.799172 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 22:55:54.799295 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
1225 22:55:54.799419 0 10 8 | B1->B0 | 2b2b 2323 | 0 1 | (0 0) (1 0)
1226 22:55:54.799542 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:55:54.799627 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:55:54.799762 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:55:54.799848 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:55:54.799934 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:55:54.800020 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:55:54.800106 0 11 4 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
1233 22:55:54.800192 0 11 8 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
1234 22:55:54.800278 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 22:55:54.800364 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 22:55:54.800424 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 22:55:54.800481 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 22:55:54.800751 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 22:55:54.800818 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 22:55:54.800876 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1241 22:55:54.800932 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1242 22:55:54.800988 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 22:55:54.801044 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 22:55:54.801100 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 22:55:54.801155 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 22:55:54.801211 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 22:55:54.801265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 22:55:54.801349 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 22:55:54.801404 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 22:55:54.801458 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 22:55:54.801512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 22:55:54.801566 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 22:55:54.801620 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 22:55:54.801674 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 22:55:54.801728 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 22:55:54.801783 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1257 22:55:54.801837 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1258 22:55:54.801909 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 22:55:54.801983 Total UI for P1: 0, mck2ui 16
1260 22:55:54.802058 best dqsien dly found for B0: ( 0, 14, 6)
1261 22:55:54.802115 Total UI for P1: 0, mck2ui 16
1262 22:55:54.802171 best dqsien dly found for B1: ( 0, 14, 8)
1263 22:55:54.802244 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1264 22:55:54.802314 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1265 22:55:54.802368
1266 22:55:54.802422 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1267 22:55:54.802477 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1268 22:55:54.802531 [Gating] SW calibration Done
1269 22:55:54.802584 ==
1270 22:55:54.802639 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 22:55:54.802694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 22:55:54.802749 ==
1273 22:55:54.802803 RX Vref Scan: 0
1274 22:55:54.802857
1275 22:55:54.802912 RX Vref 0 -> 0, step: 1
1276 22:55:54.802966
1277 22:55:54.803019 RX Delay -130 -> 252, step: 16
1278 22:55:54.803073 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1279 22:55:54.803127 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1280 22:55:54.803194 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1281 22:55:54.803246 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1282 22:55:54.803299 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1283 22:55:54.803351 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1284 22:55:54.803404 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1285 22:55:54.803457 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1286 22:55:54.803510 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1287 22:55:54.803563 iDelay=206, Bit 9, Center 69 (-34 ~ 173) 208
1288 22:55:54.803616 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1289 22:55:54.803669 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1290 22:55:54.803722 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1291 22:55:54.803775 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1292 22:55:54.803828 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1293 22:55:54.803882 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1294 22:55:54.803935 ==
1295 22:55:54.803988 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 22:55:54.804041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 22:55:54.804095 ==
1298 22:55:54.804148 DQS Delay:
1299 22:55:54.804201 DQS0 = 0, DQS1 = 0
1300 22:55:54.804254 DQM Delay:
1301 22:55:54.804307 DQM0 = 88, DQM1 = 79
1302 22:55:54.804374 DQ Delay:
1303 22:55:54.804441 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1304 22:55:54.804494 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1305 22:55:54.804547 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1306 22:55:54.804600 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1307 22:55:54.804654
1308 22:55:54.804707
1309 22:55:54.804759 ==
1310 22:55:54.804812 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 22:55:54.804865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 22:55:54.804918 ==
1313 22:55:54.804971
1314 22:55:54.805024
1315 22:55:54.805076 TX Vref Scan disable
1316 22:55:54.805129 == TX Byte 0 ==
1317 22:55:54.805181 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1318 22:55:54.805235 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1319 22:55:54.805288 == TX Byte 1 ==
1320 22:55:54.805396 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1321 22:55:54.805468 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1322 22:55:54.805535 ==
1323 22:55:54.805588 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 22:55:54.805641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 22:55:54.805723 ==
1326 22:55:54.805777 TX Vref=22, minBit 3, minWin=27, winSum=445
1327 22:55:54.805831 TX Vref=24, minBit 1, minWin=28, winSum=451
1328 22:55:54.805884 TX Vref=26, minBit 1, minWin=28, winSum=452
1329 22:55:54.805937 TX Vref=28, minBit 8, minWin=27, winSum=450
1330 22:55:54.805991 TX Vref=30, minBit 6, minWin=28, winSum=456
1331 22:55:54.806043 TX Vref=32, minBit 1, minWin=28, winSum=459
1332 22:55:54.806094 [TxChooseVref] Worse bit 1, Min win 28, Win sum 459, Final Vref 32
1333 22:55:54.806146
1334 22:55:54.806198 Final TX Range 1 Vref 32
1335 22:55:54.806250
1336 22:55:54.806301 ==
1337 22:55:54.806352 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 22:55:54.806403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 22:55:54.806455 ==
1340 22:55:54.806507
1341 22:55:54.806586
1342 22:55:54.806637 TX Vref Scan disable
1343 22:55:54.806689 == TX Byte 0 ==
1344 22:55:54.806760 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1345 22:55:54.806815 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1346 22:55:54.806867 == TX Byte 1 ==
1347 22:55:54.806918 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1348 22:55:54.806970 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1349 22:55:54.807021
1350 22:55:54.807073 [DATLAT]
1351 22:55:54.807139 Freq=800, CH0 RK1
1352 22:55:54.807205
1353 22:55:54.807256 DATLAT Default: 0xa
1354 22:55:54.807324 0, 0xFFFF, sum = 0
1355 22:55:54.807390 1, 0xFFFF, sum = 0
1356 22:55:54.807443 2, 0xFFFF, sum = 0
1357 22:55:54.807495 3, 0xFFFF, sum = 0
1358 22:55:54.807548 4, 0xFFFF, sum = 0
1359 22:55:54.807600 5, 0xFFFF, sum = 0
1360 22:55:54.807653 6, 0xFFFF, sum = 0
1361 22:55:54.807706 7, 0xFFFF, sum = 0
1362 22:55:54.807774 8, 0xFFFF, sum = 0
1363 22:55:54.807868 9, 0x0, sum = 1
1364 22:55:54.807920 10, 0x0, sum = 2
1365 22:55:54.807972 11, 0x0, sum = 3
1366 22:55:54.808242 12, 0x0, sum = 4
1367 22:55:54.808372 best_step = 10
1368 22:55:54.808425
1369 22:55:54.808477 ==
1370 22:55:54.808546 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 22:55:54.808613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 22:55:54.808666 ==
1373 22:55:54.808750 RX Vref Scan: 0
1374 22:55:54.808851
1375 22:55:54.808933 RX Vref 0 -> 0, step: 1
1376 22:55:54.809015
1377 22:55:54.809096 RX Delay -79 -> 252, step: 8
1378 22:55:54.809178 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1379 22:55:54.809261 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1380 22:55:54.809369 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1381 22:55:54.809424 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1382 22:55:54.809477 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1383 22:55:54.809543 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1384 22:55:54.809594 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1385 22:55:54.809662 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1386 22:55:54.809726 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1387 22:55:54.809778 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1388 22:55:54.809829 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1389 22:55:54.809880 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1390 22:55:54.809947 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1391 22:55:54.810012 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1392 22:55:54.810063 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1393 22:55:54.810114 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1394 22:55:54.810165 ==
1395 22:55:54.810216 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 22:55:54.810268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 22:55:54.810320 ==
1398 22:55:54.810371 DQS Delay:
1399 22:55:54.810439 DQS0 = 0, DQS1 = 0
1400 22:55:54.810503 DQM Delay:
1401 22:55:54.810555 DQM0 = 90, DQM1 = 81
1402 22:55:54.810606 DQ Delay:
1403 22:55:54.810657 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1404 22:55:54.810709 DQ4 =88, DQ5 =80, DQ6 =100, DQ7 =100
1405 22:55:54.810813 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1406 22:55:54.810939 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1407 22:55:54.811000
1408 22:55:54.811052
1409 22:55:54.811103 [DQSOSCAuto] RK1, (LSB)MR18= 0x421d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1410 22:55:54.811156 CH0 RK1: MR19=606, MR18=421D
1411 22:55:54.811208 CH0_RK1: MR19=0x606, MR18=0x421D, DQSOSC=393, MR23=63, INC=95, DEC=63
1412 22:55:54.811283 [RxdqsGatingPostProcess] freq 800
1413 22:55:54.811348 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1414 22:55:54.811400 Pre-setting of DQS Precalculation
1415 22:55:54.811452 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1416 22:55:54.811504 ==
1417 22:55:54.811556 Dram Type= 6, Freq= 0, CH_1, rank 0
1418 22:55:54.811607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 22:55:54.811658 ==
1420 22:55:54.811710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1421 22:55:54.811762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1422 22:55:54.811814 [CA 0] Center 36 (6~67) winsize 62
1423 22:55:54.811879 [CA 1] Center 37 (6~68) winsize 63
1424 22:55:54.811931 [CA 2] Center 34 (4~65) winsize 62
1425 22:55:54.811995 [CA 3] Center 34 (4~65) winsize 62
1426 22:55:54.812046 [CA 4] Center 34 (4~65) winsize 62
1427 22:55:54.812097 [CA 5] Center 33 (3~64) winsize 62
1428 22:55:54.812149
1429 22:55:54.812200 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1430 22:55:54.812251
1431 22:55:54.812302 [CATrainingPosCal] consider 1 rank data
1432 22:55:54.812354 u2DelayCellTimex100 = 270/100 ps
1433 22:55:54.812422 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1434 22:55:54.812474 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1435 22:55:54.812538 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1436 22:55:54.812589 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1437 22:55:54.812640 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1438 22:55:54.812692 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1439 22:55:54.812759
1440 22:55:54.812823 CA PerBit enable=1, Macro0, CA PI delay=33
1441 22:55:54.812875
1442 22:55:54.812926 [CBTSetCACLKResult] CA Dly = 33
1443 22:55:54.812977 CS Dly: 5 (0~36)
1444 22:55:54.813042 ==
1445 22:55:54.813094 Dram Type= 6, Freq= 0, CH_1, rank 1
1446 22:55:54.813147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 22:55:54.813199 ==
1448 22:55:54.813252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 22:55:54.813325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 22:55:54.813408 [CA 0] Center 37 (7~68) winsize 62
1451 22:55:54.813460 [CA 1] Center 37 (6~68) winsize 63
1452 22:55:54.813513 [CA 2] Center 35 (5~66) winsize 62
1453 22:55:54.813579 [CA 3] Center 34 (4~65) winsize 62
1454 22:55:54.813631 [CA 4] Center 34 (4~65) winsize 62
1455 22:55:54.813695 [CA 5] Center 34 (4~64) winsize 61
1456 22:55:54.813746
1457 22:55:54.813797 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 22:55:54.813848
1459 22:55:54.813898 [CATrainingPosCal] consider 2 rank data
1460 22:55:54.813949 u2DelayCellTimex100 = 270/100 ps
1461 22:55:54.814001 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1462 22:55:54.814086 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1463 22:55:54.814165 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1464 22:55:54.814216 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 22:55:54.814268 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 22:55:54.814319 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 22:55:54.814370
1468 22:55:54.814421 CA PerBit enable=1, Macro0, CA PI delay=34
1469 22:55:54.814472
1470 22:55:54.814523 [CBTSetCACLKResult] CA Dly = 34
1471 22:55:54.814575 CS Dly: 6 (0~38)
1472 22:55:54.814626
1473 22:55:54.814677 ----->DramcWriteLeveling(PI) begin...
1474 22:55:54.814730 ==
1475 22:55:54.814781 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 22:55:54.814832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 22:55:54.814884 ==
1478 22:55:54.814935 Write leveling (Byte 0): 27 => 27
1479 22:55:54.814986 Write leveling (Byte 1): 29 => 29
1480 22:55:54.815038 DramcWriteLeveling(PI) end<-----
1481 22:55:54.815090
1482 22:55:54.815141 ==
1483 22:55:54.815192 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 22:55:54.815243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 22:55:54.815295 ==
1486 22:55:54.815346 [Gating] SW mode calibration
1487 22:55:54.815397 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1488 22:55:54.815449 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1489 22:55:54.815501 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1490 22:55:54.815552 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:55:54.815798 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:55:54.815911 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:55:54.816026 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:55:54.816109 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:55:54.816162 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 22:55:54.816230 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 22:55:54.816296 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 22:55:54.816348 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:55:54.816400 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 22:55:54.816451 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 22:55:54.816503 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:55:54.816555 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 22:55:54.816605 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 22:55:54.816657 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 22:55:54.816708 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1506 22:55:54.816760 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1507 22:55:54.816811 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 22:55:54.816862 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 22:55:54.816913 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 22:55:54.816965 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 22:55:54.817016 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 22:55:54.817068 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 22:55:54.817119 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 22:55:54.817170 0 9 4 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)
1515 22:55:54.817221 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1516 22:55:54.817272 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 22:55:54.817378 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 22:55:54.817463 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 22:55:54.817516 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 22:55:54.817568 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 22:55:54.817621 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1522 22:55:54.817674 0 10 4 | B1->B0 | 2d2d 2727 | 1 1 | (1 1) (1 0)
1523 22:55:54.817726 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:55:54.817779 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:55:54.817832 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:55:54.817885 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:55:54.817937 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:55:54.817989 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:55:54.818041 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:55:54.818093 0 11 4 | B1->B0 | 2c2c 3b3b | 1 1 | (0 0) (0 0)
1531 22:55:54.818146 0 11 8 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1532 22:55:54.818231 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 22:55:54.818283 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 22:55:54.818335 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 22:55:54.818388 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 22:55:54.818440 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 22:55:54.818493 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1538 22:55:54.818546 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1539 22:55:54.818599 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1540 22:55:54.818651 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 22:55:54.818704 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 22:55:54.818756 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 22:55:54.818808 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 22:55:54.818860 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 22:55:54.818913 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 22:55:54.818965 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 22:55:54.819030 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 22:55:54.819098 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 22:55:54.819177 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 22:55:54.819229 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 22:55:54.819281 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 22:55:54.819333 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 22:55:54.819385 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 22:55:54.819437 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1555 22:55:54.819506 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 22:55:54.819573 Total UI for P1: 0, mck2ui 16
1557 22:55:54.819626 best dqsien dly found for B0: ( 0, 14, 4)
1558 22:55:54.819679 Total UI for P1: 0, mck2ui 16
1559 22:55:54.819733 best dqsien dly found for B1: ( 0, 14, 4)
1560 22:55:54.819786 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1561 22:55:54.819838 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1562 22:55:54.819891
1563 22:55:54.819943 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1564 22:55:54.819995 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1565 22:55:54.820047 [Gating] SW calibration Done
1566 22:55:54.820099 ==
1567 22:55:54.820152 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 22:55:54.820223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 22:55:54.820292 ==
1570 22:55:54.820344 RX Vref Scan: 0
1571 22:55:54.820397
1572 22:55:54.820468 RX Vref 0 -> 0, step: 1
1573 22:55:54.820527
1574 22:55:54.820580 RX Delay -130 -> 252, step: 16
1575 22:55:54.820648 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1576 22:55:54.820701 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1577 22:55:54.820753 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1578 22:55:54.820805 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1579 22:55:54.820857 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1580 22:55:54.821145 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1581 22:55:54.821208 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1582 22:55:54.821263 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1583 22:55:54.821343 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1584 22:55:54.821402 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1585 22:55:54.821488 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1586 22:55:54.821542 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1587 22:55:54.821595 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1588 22:55:54.821662 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1589 22:55:54.821729 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1590 22:55:54.821783 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1591 22:55:54.821836 ==
1592 22:55:54.821890 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 22:55:54.821943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 22:55:54.822028 ==
1595 22:55:54.822112 DQS Delay:
1596 22:55:54.822166 DQS0 = 0, DQS1 = 0
1597 22:55:54.822223 DQM Delay:
1598 22:55:54.822276 DQM0 = 91, DQM1 = 85
1599 22:55:54.822332 DQ Delay:
1600 22:55:54.822386 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1601 22:55:54.822438 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1602 22:55:54.822505 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1603 22:55:54.822556 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1604 22:55:54.822608
1605 22:55:54.822675
1606 22:55:54.822727 ==
1607 22:55:54.822779 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 22:55:54.822832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 22:55:54.822884 ==
1610 22:55:54.822937
1611 22:55:54.822989
1612 22:55:54.823072 TX Vref Scan disable
1613 22:55:54.823124 == TX Byte 0 ==
1614 22:55:54.823177 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1615 22:55:54.823229 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1616 22:55:54.823282 == TX Byte 1 ==
1617 22:55:54.823334 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1618 22:55:54.823405 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1619 22:55:54.823459 ==
1620 22:55:54.823513 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 22:55:54.823566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 22:55:54.823620 ==
1623 22:55:54.823712 TX Vref=22, minBit 8, minWin=27, winSum=448
1624 22:55:54.823780 TX Vref=24, minBit 15, minWin=27, winSum=454
1625 22:55:54.823832 TX Vref=26, minBit 15, minWin=27, winSum=454
1626 22:55:54.823884 TX Vref=28, minBit 0, minWin=28, winSum=458
1627 22:55:54.823936 TX Vref=30, minBit 1, minWin=28, winSum=458
1628 22:55:54.823989 TX Vref=32, minBit 8, minWin=28, winSum=459
1629 22:55:54.824041 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 32
1630 22:55:54.824094
1631 22:55:54.824146 Final TX Range 1 Vref 32
1632 22:55:54.824199
1633 22:55:54.824251 ==
1634 22:55:54.824303 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 22:55:54.824355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 22:55:54.824408 ==
1637 22:55:54.824460
1638 22:55:54.824511
1639 22:55:54.824563 TX Vref Scan disable
1640 22:55:54.824616 == TX Byte 0 ==
1641 22:55:54.824669 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1642 22:55:54.824721 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1643 22:55:54.824802 == TX Byte 1 ==
1644 22:55:54.824854 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1645 22:55:54.824906 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1646 22:55:54.824958
1647 22:55:54.825009 [DATLAT]
1648 22:55:54.825061 Freq=800, CH1 RK0
1649 22:55:54.825112
1650 22:55:54.825164 DATLAT Default: 0xa
1651 22:55:54.825216 0, 0xFFFF, sum = 0
1652 22:55:54.825269 1, 0xFFFF, sum = 0
1653 22:55:54.825374 2, 0xFFFF, sum = 0
1654 22:55:54.825426 3, 0xFFFF, sum = 0
1655 22:55:54.825479 4, 0xFFFF, sum = 0
1656 22:55:54.825531 5, 0xFFFF, sum = 0
1657 22:55:54.825583 6, 0xFFFF, sum = 0
1658 22:55:54.825635 7, 0xFFFF, sum = 0
1659 22:55:54.825687 8, 0xFFFF, sum = 0
1660 22:55:54.825739 9, 0x0, sum = 1
1661 22:55:54.825821 10, 0x0, sum = 2
1662 22:55:54.825892 11, 0x0, sum = 3
1663 22:55:54.826007 12, 0x0, sum = 4
1664 22:55:54.826114 best_step = 10
1665 22:55:54.826179
1666 22:55:54.826231 ==
1667 22:55:54.826282 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 22:55:54.826390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 22:55:54.826531 ==
1670 22:55:54.826695 RX Vref Scan: 1
1671 22:55:54.826778
1672 22:55:54.826835 Set Vref Range= 32 -> 127
1673 22:55:54.826891
1674 22:55:54.826946 RX Vref 32 -> 127, step: 1
1675 22:55:54.827000
1676 22:55:54.827054 RX Delay -95 -> 252, step: 8
1677 22:55:54.827108
1678 22:55:54.827161 Set Vref, RX VrefLevel [Byte0]: 32
1679 22:55:54.827215 [Byte1]: 32
1680 22:55:54.827269
1681 22:55:54.827323 Set Vref, RX VrefLevel [Byte0]: 33
1682 22:55:54.827376 [Byte1]: 33
1683 22:55:54.827430
1684 22:55:54.827484 Set Vref, RX VrefLevel [Byte0]: 34
1685 22:55:54.827539 [Byte1]: 34
1686 22:55:54.827594
1687 22:55:54.827647 Set Vref, RX VrefLevel [Byte0]: 35
1688 22:55:54.827701 [Byte1]: 35
1689 22:55:54.827755
1690 22:55:54.827808 Set Vref, RX VrefLevel [Byte0]: 36
1691 22:55:54.827862 [Byte1]: 36
1692 22:55:54.827916
1693 22:55:54.827969 Set Vref, RX VrefLevel [Byte0]: 37
1694 22:55:54.828023 [Byte1]: 37
1695 22:55:54.828076
1696 22:55:54.828129 Set Vref, RX VrefLevel [Byte0]: 38
1697 22:55:54.828182 [Byte1]: 38
1698 22:55:54.828236
1699 22:55:54.828289 Set Vref, RX VrefLevel [Byte0]: 39
1700 22:55:54.828343 [Byte1]: 39
1701 22:55:54.828396
1702 22:55:54.828450 Set Vref, RX VrefLevel [Byte0]: 40
1703 22:55:54.828503 [Byte1]: 40
1704 22:55:54.828557
1705 22:55:54.828610 Set Vref, RX VrefLevel [Byte0]: 41
1706 22:55:54.828663 [Byte1]: 41
1707 22:55:54.828716
1708 22:55:54.828769 Set Vref, RX VrefLevel [Byte0]: 42
1709 22:55:54.828823 [Byte1]: 42
1710 22:55:54.828876
1711 22:55:54.828930 Set Vref, RX VrefLevel [Byte0]: 43
1712 22:55:54.828983 [Byte1]: 43
1713 22:55:54.829037
1714 22:55:54.829089 Set Vref, RX VrefLevel [Byte0]: 44
1715 22:55:54.829143 [Byte1]: 44
1716 22:55:54.829196
1717 22:55:54.829249 Set Vref, RX VrefLevel [Byte0]: 45
1718 22:55:54.829313 [Byte1]: 45
1719 22:55:54.829400
1720 22:55:54.829499 Set Vref, RX VrefLevel [Byte0]: 46
1721 22:55:54.829570 [Byte1]: 46
1722 22:55:54.829624
1723 22:55:54.829692 Set Vref, RX VrefLevel [Byte0]: 47
1724 22:55:54.829776 [Byte1]: 47
1725 22:55:54.829828
1726 22:55:54.829880 Set Vref, RX VrefLevel [Byte0]: 48
1727 22:55:54.829934 [Byte1]: 48
1728 22:55:54.829986
1729 22:55:54.830071 Set Vref, RX VrefLevel [Byte0]: 49
1730 22:55:54.830124 [Byte1]: 49
1731 22:55:54.830176
1732 22:55:54.830228 Set Vref, RX VrefLevel [Byte0]: 50
1733 22:55:54.830296 [Byte1]: 50
1734 22:55:54.830350
1735 22:55:54.830403 Set Vref, RX VrefLevel [Byte0]: 51
1736 22:55:54.830457 [Byte1]: 51
1737 22:55:54.830510
1738 22:55:54.830563 Set Vref, RX VrefLevel [Byte0]: 52
1739 22:55:54.830616 [Byte1]: 52
1740 22:55:54.830669
1741 22:55:54.830937 Set Vref, RX VrefLevel [Byte0]: 53
1742 22:55:54.831004 [Byte1]: 53
1743 22:55:54.831059
1744 22:55:54.831113 Set Vref, RX VrefLevel [Byte0]: 54
1745 22:55:54.831166 [Byte1]: 54
1746 22:55:54.831220
1747 22:55:54.831274 Set Vref, RX VrefLevel [Byte0]: 55
1748 22:55:54.831328 [Byte1]: 55
1749 22:55:54.831382
1750 22:55:54.831436 Set Vref, RX VrefLevel [Byte0]: 56
1751 22:55:54.831489 [Byte1]: 56
1752 22:55:54.831543
1753 22:55:54.831595 Set Vref, RX VrefLevel [Byte0]: 57
1754 22:55:54.831649 [Byte1]: 57
1755 22:55:54.831703
1756 22:55:54.831757 Set Vref, RX VrefLevel [Byte0]: 58
1757 22:55:54.831810 [Byte1]: 58
1758 22:55:54.831863
1759 22:55:54.831917 Set Vref, RX VrefLevel [Byte0]: 59
1760 22:55:54.831971 [Byte1]: 59
1761 22:55:54.832025
1762 22:55:54.832078 Set Vref, RX VrefLevel [Byte0]: 60
1763 22:55:54.832132 [Byte1]: 60
1764 22:55:54.832186
1765 22:55:54.832239 Set Vref, RX VrefLevel [Byte0]: 61
1766 22:55:54.832292 [Byte1]: 61
1767 22:55:54.832345
1768 22:55:54.832399 Set Vref, RX VrefLevel [Byte0]: 62
1769 22:55:54.832453 [Byte1]: 62
1770 22:55:54.832507
1771 22:55:54.832561 Set Vref, RX VrefLevel [Byte0]: 63
1772 22:55:54.832615 [Byte1]: 63
1773 22:55:54.832668
1774 22:55:54.832721 Set Vref, RX VrefLevel [Byte0]: 64
1775 22:55:54.832774 [Byte1]: 64
1776 22:55:54.832828
1777 22:55:54.832881 Set Vref, RX VrefLevel [Byte0]: 65
1778 22:55:54.832935 [Byte1]: 65
1779 22:55:54.832989
1780 22:55:54.833042 Set Vref, RX VrefLevel [Byte0]: 66
1781 22:55:54.833095 [Byte1]: 66
1782 22:55:54.833149
1783 22:55:54.833203 Set Vref, RX VrefLevel [Byte0]: 67
1784 22:55:54.833256 [Byte1]: 67
1785 22:55:54.833318
1786 22:55:54.833373 Set Vref, RX VrefLevel [Byte0]: 68
1787 22:55:54.833427 [Byte1]: 68
1788 22:55:54.833480
1789 22:55:54.833533 Set Vref, RX VrefLevel [Byte0]: 69
1790 22:55:54.833588 [Byte1]: 69
1791 22:55:54.833641
1792 22:55:54.833694 Set Vref, RX VrefLevel [Byte0]: 70
1793 22:55:54.833748 [Byte1]: 70
1794 22:55:54.833801
1795 22:55:54.833855 Set Vref, RX VrefLevel [Byte0]: 71
1796 22:55:54.833909 [Byte1]: 71
1797 22:55:54.833962
1798 22:55:54.834015 Set Vref, RX VrefLevel [Byte0]: 72
1799 22:55:54.834068 [Byte1]: 72
1800 22:55:54.834122
1801 22:55:54.834176 Set Vref, RX VrefLevel [Byte0]: 73
1802 22:55:54.834229 [Byte1]: 73
1803 22:55:54.834283
1804 22:55:54.834336 Set Vref, RX VrefLevel [Byte0]: 74
1805 22:55:54.834389 [Byte1]: 74
1806 22:55:54.834442
1807 22:55:54.834495 Set Vref, RX VrefLevel [Byte0]: 75
1808 22:55:54.834549 [Byte1]: 75
1809 22:55:54.834602
1810 22:55:54.834656 Set Vref, RX VrefLevel [Byte0]: 76
1811 22:55:54.834710 [Byte1]: 76
1812 22:55:54.834763
1813 22:55:54.834816 Set Vref, RX VrefLevel [Byte0]: 77
1814 22:55:54.834870 [Byte1]: 77
1815 22:55:54.834923
1816 22:55:54.834977 Set Vref, RX VrefLevel [Byte0]: 78
1817 22:55:54.835030 [Byte1]: 78
1818 22:55:54.835084
1819 22:55:54.835137 Final RX Vref Byte 0 = 54 to rank0
1820 22:55:54.835192 Final RX Vref Byte 1 = 61 to rank0
1821 22:55:54.835246 Final RX Vref Byte 0 = 54 to rank1
1822 22:55:54.835300 Final RX Vref Byte 1 = 61 to rank1==
1823 22:55:54.835353 Dram Type= 6, Freq= 0, CH_1, rank 0
1824 22:55:54.835406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1825 22:55:54.835461 ==
1826 22:55:54.835514 DQS Delay:
1827 22:55:54.835567 DQS0 = 0, DQS1 = 0
1828 22:55:54.835621 DQM Delay:
1829 22:55:54.835674 DQM0 = 90, DQM1 = 82
1830 22:55:54.835728 DQ Delay:
1831 22:55:54.835782 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =92
1832 22:55:54.835836 DQ4 =88, DQ5 =104, DQ6 =100, DQ7 =84
1833 22:55:54.835890 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1834 22:55:54.835943 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1835 22:55:54.835996
1836 22:55:54.836049
1837 22:55:54.836102 [DQSOSCAuto] RK0, (LSB)MR18= 0x304d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1838 22:55:54.836157 CH1 RK0: MR19=606, MR18=304D
1839 22:55:54.836211 CH1_RK0: MR19=0x606, MR18=0x304D, DQSOSC=390, MR23=63, INC=97, DEC=64
1840 22:55:54.836266
1841 22:55:54.836319 ----->DramcWriteLeveling(PI) begin...
1842 22:55:54.836375 ==
1843 22:55:54.836429 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 22:55:54.836483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1845 22:55:54.836537 ==
1846 22:55:54.836590 Write leveling (Byte 0): 26 => 26
1847 22:55:54.836644 Write leveling (Byte 1): 29 => 29
1848 22:55:54.836697 DramcWriteLeveling(PI) end<-----
1849 22:55:54.836751
1850 22:55:54.836804 ==
1851 22:55:54.836858 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 22:55:54.836913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 22:55:54.836967 ==
1854 22:55:54.837020 [Gating] SW mode calibration
1855 22:55:54.837074 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1856 22:55:54.837128 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1857 22:55:54.837182 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1858 22:55:54.837236 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1859 22:55:54.837290 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 22:55:54.837355 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 22:55:54.837409 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 22:55:54.837462 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 22:55:54.837516 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 22:55:54.837570 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 22:55:54.837624 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 22:55:54.837677 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 22:55:54.837730 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 22:55:54.837783 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 22:55:54.837836 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 22:55:54.837890 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:55:54.837944 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 22:55:54.837998 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 22:55:54.838051 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 22:55:54.838105 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1875 22:55:54.838359 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1876 22:55:54.838420 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:55:54.838474 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 22:55:54.838528 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 22:55:54.838582 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:55:54.838636 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:55:54.838690 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:55:54.838743 0 9 4 | B1->B0 | 2626 2525 | 0 1 | (0 0) (1 1)
1883 22:55:54.838796 0 9 8 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1884 22:55:54.838850 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 22:55:54.838903 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 22:55:54.838957 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 22:55:54.839010 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 22:55:54.839064 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 22:55:54.839117 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 22:55:54.839170 0 10 4 | B1->B0 | 2a2a 2f2f | 1 1 | (1 1) (1 1)
1891 22:55:54.839223 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:55:54.839276 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:55:54.839330 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:55:54.839383 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:55:54.839436 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:55:54.839489 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:55:54.839542 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 22:55:54.839596 0 11 4 | B1->B0 | 3130 2f2f | 1 0 | (0 0) (0 0)
1899 22:55:54.839649 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 22:55:54.839703 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 22:55:54.839756 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 22:55:54.839809 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 22:55:54.839863 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 22:55:54.839916 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 22:55:54.839969 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 22:55:54.840022 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1907 22:55:54.840076 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1908 22:55:54.840129 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 22:55:54.840182 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 22:55:54.840236 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 22:55:54.840289 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 22:55:54.840342 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 22:55:54.840395 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 22:55:54.840448 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 22:55:54.840501 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 22:55:54.840554 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 22:55:54.840607 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 22:55:54.840660 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 22:55:54.840714 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 22:55:54.840767 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 22:55:54.840820 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 22:55:54.840874 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 22:55:54.840927 Total UI for P1: 0, mck2ui 16
1924 22:55:54.840982 best dqsien dly found for B0: ( 0, 14, 2)
1925 22:55:54.841035 Total UI for P1: 0, mck2ui 16
1926 22:55:54.841089 best dqsien dly found for B1: ( 0, 14, 2)
1927 22:55:54.841142 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1928 22:55:54.841195 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1929 22:55:54.841248
1930 22:55:54.841305 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1931 22:55:54.841361 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1932 22:55:54.841415 [Gating] SW calibration Done
1933 22:55:54.841468 ==
1934 22:55:54.841522 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 22:55:54.841576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 22:55:54.841630 ==
1937 22:55:54.841683 RX Vref Scan: 0
1938 22:55:54.841736
1939 22:55:54.841789 RX Vref 0 -> 0, step: 1
1940 22:55:54.841843
1941 22:55:54.841896 RX Delay -130 -> 252, step: 16
1942 22:55:54.841949 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1943 22:55:54.842002 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1944 22:55:54.842056 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1945 22:55:54.842109 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1946 22:55:54.842162 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1947 22:55:54.842215 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1948 22:55:54.842268 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1949 22:55:54.842321 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1950 22:55:54.842374 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1951 22:55:54.842427 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1952 22:55:54.842481 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1953 22:55:54.842534 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1954 22:55:54.842587 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1955 22:55:54.842640 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1956 22:55:54.842693 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1957 22:55:54.961911 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1958 22:55:54.962055 ==
1959 22:55:54.962121 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 22:55:54.962182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 22:55:54.962241 ==
1962 22:55:54.962297 DQS Delay:
1963 22:55:54.962352 DQS0 = 0, DQS1 = 0
1964 22:55:54.962406 DQM Delay:
1965 22:55:54.962460 DQM0 = 89, DQM1 = 82
1966 22:55:54.962513 DQ Delay:
1967 22:55:54.962566 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1968 22:55:54.962619 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1969 22:55:54.962671 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1970 22:55:54.962724 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1971 22:55:54.962777
1972 22:55:54.962829
1973 22:55:54.962880 ==
1974 22:55:54.962932 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 22:55:54.962985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 22:55:54.963252 ==
1977 22:55:54.963311
1978 22:55:54.963365
1979 22:55:54.963417 TX Vref Scan disable
1980 22:55:54.963470 == TX Byte 0 ==
1981 22:55:54.963522 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1982 22:55:54.963575 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1983 22:55:54.963627 == TX Byte 1 ==
1984 22:55:54.963679 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1985 22:55:54.963732 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1986 22:55:54.963784 ==
1987 22:55:54.963836 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 22:55:54.963888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 22:55:54.963941 ==
1990 22:55:54.963993 TX Vref=22, minBit 12, minWin=27, winSum=452
1991 22:55:54.964047 TX Vref=24, minBit 13, minWin=27, winSum=453
1992 22:55:54.964099 TX Vref=26, minBit 3, minWin=28, winSum=457
1993 22:55:54.964152 TX Vref=28, minBit 3, minWin=28, winSum=459
1994 22:55:54.964203 TX Vref=30, minBit 13, minWin=27, winSum=458
1995 22:55:54.964256 TX Vref=32, minBit 8, minWin=28, winSum=459
1996 22:55:54.964308 [TxChooseVref] Worse bit 3, Min win 28, Win sum 459, Final Vref 28
1997 22:55:54.964361
1998 22:55:54.964412 Final TX Range 1 Vref 28
1999 22:55:54.964464
2000 22:55:54.964516 ==
2001 22:55:54.964568 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 22:55:54.964620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 22:55:54.964672 ==
2004 22:55:54.964724
2005 22:55:54.964775
2006 22:55:54.964826 TX Vref Scan disable
2007 22:55:54.964878 == TX Byte 0 ==
2008 22:55:54.964930 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2009 22:55:54.964982 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2010 22:55:54.965034 == TX Byte 1 ==
2011 22:55:54.965085 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2012 22:55:54.965137 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2013 22:55:54.965188
2014 22:55:54.965239 [DATLAT]
2015 22:55:54.965290 Freq=800, CH1 RK1
2016 22:55:54.965392
2017 22:55:54.965444 DATLAT Default: 0xa
2018 22:55:54.965496 0, 0xFFFF, sum = 0
2019 22:55:54.965550 1, 0xFFFF, sum = 0
2020 22:55:54.965603 2, 0xFFFF, sum = 0
2021 22:55:54.965656 3, 0xFFFF, sum = 0
2022 22:55:54.965710 4, 0xFFFF, sum = 0
2023 22:55:54.965763 5, 0xFFFF, sum = 0
2024 22:55:54.965816 6, 0xFFFF, sum = 0
2025 22:55:54.965868 7, 0xFFFF, sum = 0
2026 22:55:54.965921 8, 0xFFFF, sum = 0
2027 22:55:54.965973 9, 0x0, sum = 1
2028 22:55:54.966025 10, 0x0, sum = 2
2029 22:55:54.966078 11, 0x0, sum = 3
2030 22:55:54.966130 12, 0x0, sum = 4
2031 22:55:54.966183 best_step = 10
2032 22:55:54.966235
2033 22:55:54.966286 ==
2034 22:55:54.966338 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 22:55:54.966390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 22:55:54.966442 ==
2037 22:55:54.966494 RX Vref Scan: 0
2038 22:55:54.966545
2039 22:55:54.966596 RX Vref 0 -> 0, step: 1
2040 22:55:54.966649
2041 22:55:54.966700 RX Delay -79 -> 252, step: 8
2042 22:55:54.966752 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2043 22:55:54.966805 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2044 22:55:54.966857 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2045 22:55:54.966908 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2046 22:55:54.966960 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2047 22:55:54.967012 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2048 22:55:54.967063 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2049 22:55:54.967114 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2050 22:55:54.967166 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2051 22:55:54.967218 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2052 22:55:54.967270 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2053 22:55:54.967322 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2054 22:55:54.967373 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2055 22:55:54.967424 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2056 22:55:54.967476 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2057 22:55:54.967528 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2058 22:55:54.967581 ==
2059 22:55:54.967635 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 22:55:54.967688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 22:55:54.967741 ==
2062 22:55:54.967794 DQS Delay:
2063 22:55:54.967845 DQS0 = 0, DQS1 = 0
2064 22:55:54.967898 DQM Delay:
2065 22:55:54.967950 DQM0 = 91, DQM1 = 83
2066 22:55:54.968002 DQ Delay:
2067 22:55:54.968055 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2068 22:55:54.968108 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2069 22:55:54.968160 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2070 22:55:54.968213 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2071 22:55:54.968267
2072 22:55:54.968320
2073 22:55:54.968372 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2074 22:55:54.968427 CH1 RK1: MR19=606, MR18=3D13
2075 22:55:54.968481 CH1_RK1: MR19=0x606, MR18=0x3D13, DQSOSC=394, MR23=63, INC=95, DEC=63
2076 22:55:54.968535 [RxdqsGatingPostProcess] freq 800
2077 22:55:54.968588 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2078 22:55:54.968641 Pre-setting of DQS Precalculation
2079 22:55:54.968695 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2080 22:55:54.968748 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2081 22:55:54.968803 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2082 22:55:54.968857
2083 22:55:54.968909
2084 22:55:54.968962 [Calibration Summary] 1600 Mbps
2085 22:55:54.969015 CH 0, Rank 0
2086 22:55:54.969068 SW Impedance : PASS
2087 22:55:54.969122 DUTY Scan : NO K
2088 22:55:54.969175 ZQ Calibration : PASS
2089 22:55:54.969228 Jitter Meter : NO K
2090 22:55:54.969282 CBT Training : PASS
2091 22:55:54.969369 Write leveling : PASS
2092 22:55:54.969423 RX DQS gating : PASS
2093 22:55:54.969476 RX DQ/DQS(RDDQC) : PASS
2094 22:55:54.969530 TX DQ/DQS : PASS
2095 22:55:54.969583 RX DATLAT : PASS
2096 22:55:54.969636 RX DQ/DQS(Engine): PASS
2097 22:55:54.969689 TX OE : NO K
2098 22:55:54.969743 All Pass.
2099 22:55:54.969796
2100 22:55:54.969849 CH 0, Rank 1
2101 22:55:54.969902 SW Impedance : PASS
2102 22:55:54.969955 DUTY Scan : NO K
2103 22:55:54.970008 ZQ Calibration : PASS
2104 22:55:54.970062 Jitter Meter : NO K
2105 22:55:54.970114 CBT Training : PASS
2106 22:55:54.970167 Write leveling : PASS
2107 22:55:54.970220 RX DQS gating : PASS
2108 22:55:54.970273 RX DQ/DQS(RDDQC) : PASS
2109 22:55:54.970349 TX DQ/DQS : PASS
2110 22:55:54.970405 RX DATLAT : PASS
2111 22:55:54.970459 RX DQ/DQS(Engine): PASS
2112 22:55:54.970513 TX OE : NO K
2113 22:55:54.970567 All Pass.
2114 22:55:54.970621
2115 22:55:54.970675 CH 1, Rank 0
2116 22:55:54.970728 SW Impedance : PASS
2117 22:55:54.970782 DUTY Scan : NO K
2118 22:55:54.970835 ZQ Calibration : PASS
2119 22:55:54.970889 Jitter Meter : NO K
2120 22:55:54.970942 CBT Training : PASS
2121 22:55:54.970996 Write leveling : PASS
2122 22:55:54.971049 RX DQS gating : PASS
2123 22:55:54.971294 RX DQ/DQS(RDDQC) : PASS
2124 22:55:54.971354 TX DQ/DQS : PASS
2125 22:55:54.971409 RX DATLAT : PASS
2126 22:55:54.971463 RX DQ/DQS(Engine): PASS
2127 22:55:54.971516 TX OE : NO K
2128 22:55:54.971571 All Pass.
2129 22:55:54.971624
2130 22:55:54.971678 CH 1, Rank 1
2131 22:55:54.971732 SW Impedance : PASS
2132 22:55:54.971817 DUTY Scan : NO K
2133 22:55:54.971871 ZQ Calibration : PASS
2134 22:55:54.971925 Jitter Meter : NO K
2135 22:55:54.971979 CBT Training : PASS
2136 22:55:54.972033 Write leveling : PASS
2137 22:55:54.972087 RX DQS gating : PASS
2138 22:55:54.972140 RX DQ/DQS(RDDQC) : PASS
2139 22:55:54.972194 TX DQ/DQS : PASS
2140 22:55:54.972248 RX DATLAT : PASS
2141 22:55:54.972301 RX DQ/DQS(Engine): PASS
2142 22:55:54.972355 TX OE : NO K
2143 22:55:54.972409 All Pass.
2144 22:55:54.972462
2145 22:55:54.972516 DramC Write-DBI off
2146 22:55:54.972569 PER_BANK_REFRESH: Hybrid Mode
2147 22:55:54.972623 TX_TRACKING: ON
2148 22:55:54.972676 [GetDramInforAfterCalByMRR] Vendor 6.
2149 22:55:54.972730 [GetDramInforAfterCalByMRR] Revision 606.
2150 22:55:54.972784 [GetDramInforAfterCalByMRR] Revision 2 0.
2151 22:55:54.972838 MR0 0x3b3b
2152 22:55:54.972891 MR8 0x5151
2153 22:55:54.972945 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2154 22:55:54.972999
2155 22:55:54.973053 MR0 0x3b3b
2156 22:55:54.973106 MR8 0x5151
2157 22:55:54.973159 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2158 22:55:54.973213
2159 22:55:54.973267 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2160 22:55:54.973349 [FAST_K] Save calibration result to emmc
2161 22:55:54.973418 [FAST_K] Save calibration result to emmc
2162 22:55:54.973473 dram_init: config_dvfs: 1
2163 22:55:54.973526 dramc_set_vcore_voltage set vcore to 662500
2164 22:55:54.973580 Read voltage for 1200, 2
2165 22:55:54.973633 Vio18 = 0
2166 22:55:54.973687 Vcore = 662500
2167 22:55:54.973741 Vdram = 0
2168 22:55:54.973795 Vddq = 0
2169 22:55:54.973847 Vmddr = 0
2170 22:55:54.973918 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2171 22:55:54.973976 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2172 22:55:54.974031 MEM_TYPE=3, freq_sel=15
2173 22:55:54.974085 sv_algorithm_assistance_LP4_1600
2174 22:55:54.974140 ============ PULL DRAM RESETB DOWN ============
2175 22:55:54.974194 ========== PULL DRAM RESETB DOWN end =========
2176 22:55:54.974249 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2177 22:55:54.974303 ===================================
2178 22:55:54.974356 LPDDR4 DRAM CONFIGURATION
2179 22:55:54.974410 ===================================
2180 22:55:54.974464 EX_ROW_EN[0] = 0x0
2181 22:55:54.974517 EX_ROW_EN[1] = 0x0
2182 22:55:54.974571 LP4Y_EN = 0x0
2183 22:55:54.974624 WORK_FSP = 0x0
2184 22:55:54.974677 WL = 0x4
2185 22:55:54.974730 RL = 0x4
2186 22:55:54.974783 BL = 0x2
2187 22:55:54.974837 RPST = 0x0
2188 22:55:54.974890 RD_PRE = 0x0
2189 22:55:54.974944 WR_PRE = 0x1
2190 22:55:54.974997 WR_PST = 0x0
2191 22:55:54.975050 DBI_WR = 0x0
2192 22:55:54.975103 DBI_RD = 0x0
2193 22:55:54.975157 OTF = 0x1
2194 22:55:54.975210 ===================================
2195 22:55:54.975264 ===================================
2196 22:55:54.975317 ANA top config
2197 22:55:54.975371 ===================================
2198 22:55:54.975425 DLL_ASYNC_EN = 0
2199 22:55:54.975478 ALL_SLAVE_EN = 0
2200 22:55:54.975531 NEW_RANK_MODE = 1
2201 22:55:54.975585 DLL_IDLE_MODE = 1
2202 22:55:54.975678 LP45_APHY_COMB_EN = 1
2203 22:55:54.975731 TX_ODT_DIS = 1
2204 22:55:54.975785 NEW_8X_MODE = 1
2205 22:55:54.975840 ===================================
2206 22:55:54.975894 ===================================
2207 22:55:54.975948 data_rate = 2400
2208 22:55:54.976001 CKR = 1
2209 22:55:54.976055 DQ_P2S_RATIO = 8
2210 22:55:54.976109 ===================================
2211 22:55:54.976163 CA_P2S_RATIO = 8
2212 22:55:54.976217 DQ_CA_OPEN = 0
2213 22:55:54.976270 DQ_SEMI_OPEN = 0
2214 22:55:54.976324 CA_SEMI_OPEN = 0
2215 22:55:54.976377 CA_FULL_RATE = 0
2216 22:55:54.976445 DQ_CKDIV4_EN = 0
2217 22:55:54.976499 CA_CKDIV4_EN = 0
2218 22:55:54.976553 CA_PREDIV_EN = 0
2219 22:55:54.976607 PH8_DLY = 17
2220 22:55:54.976661 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2221 22:55:54.976714 DQ_AAMCK_DIV = 4
2222 22:55:54.976768 CA_AAMCK_DIV = 4
2223 22:55:54.976822 CA_ADMCK_DIV = 4
2224 22:55:54.976875 DQ_TRACK_CA_EN = 0
2225 22:55:54.976929 CA_PICK = 1200
2226 22:55:54.976983 CA_MCKIO = 1200
2227 22:55:54.977037 MCKIO_SEMI = 0
2228 22:55:54.977090 PLL_FREQ = 2366
2229 22:55:54.977143 DQ_UI_PI_RATIO = 32
2230 22:55:54.977197 CA_UI_PI_RATIO = 0
2231 22:55:54.977251 ===================================
2232 22:55:54.977309 ===================================
2233 22:55:54.977364 memory_type:LPDDR4
2234 22:55:54.977418 GP_NUM : 10
2235 22:55:54.977471 SRAM_EN : 1
2236 22:55:54.977525 MD32_EN : 0
2237 22:55:54.977578 ===================================
2238 22:55:54.977631 [ANA_INIT] >>>>>>>>>>>>>>
2239 22:55:54.977685 <<<<<< [CONFIGURE PHASE]: ANA_TX
2240 22:55:54.977739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2241 22:55:54.977792 ===================================
2242 22:55:54.977845 data_rate = 2400,PCW = 0X5b00
2243 22:55:54.977899 ===================================
2244 22:55:54.977953 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2245 22:55:54.978006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2246 22:55:54.978060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2247 22:55:54.978114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2248 22:55:54.978168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2249 22:55:54.978221 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2250 22:55:54.978276 [ANA_INIT] flow start
2251 22:55:54.978329 [ANA_INIT] PLL >>>>>>>>
2252 22:55:54.978383 [ANA_INIT] PLL <<<<<<<<
2253 22:55:54.978436 [ANA_INIT] MIDPI >>>>>>>>
2254 22:55:54.978490 [ANA_INIT] MIDPI <<<<<<<<
2255 22:55:54.978544 [ANA_INIT] DLL >>>>>>>>
2256 22:55:54.978596 [ANA_INIT] DLL <<<<<<<<
2257 22:55:54.978650 [ANA_INIT] flow end
2258 22:55:54.978702 ============ LP4 DIFF to SE enter ============
2259 22:55:54.978757 ============ LP4 DIFF to SE exit ============
2260 22:55:54.979007 [ANA_INIT] <<<<<<<<<<<<<
2261 22:55:54.979070 [Flow] Enable top DCM control >>>>>
2262 22:55:54.979125 [Flow] Enable top DCM control <<<<<
2263 22:55:54.979180 Enable DLL master slave shuffle
2264 22:55:54.979234 ==============================================================
2265 22:55:54.979289 Gating Mode config
2266 22:55:54.979342 ==============================================================
2267 22:55:54.979396 Config description:
2268 22:55:54.979450 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2269 22:55:54.979505 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2270 22:55:54.979560 SELPH_MODE 0: By rank 1: By Phase
2271 22:55:54.979615 ==============================================================
2272 22:55:54.979669 GAT_TRACK_EN = 1
2273 22:55:54.979723 RX_GATING_MODE = 2
2274 22:55:54.979777 RX_GATING_TRACK_MODE = 2
2275 22:55:54.979830 SELPH_MODE = 1
2276 22:55:54.979884 PICG_EARLY_EN = 1
2277 22:55:54.979938 VALID_LAT_VALUE = 1
2278 22:55:54.979993 ==============================================================
2279 22:55:54.980047 Enter into Gating configuration >>>>
2280 22:55:54.980102 Exit from Gating configuration <<<<
2281 22:55:54.980155 Enter into DVFS_PRE_config >>>>>
2282 22:55:54.980210 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2283 22:55:54.980265 Exit from DVFS_PRE_config <<<<<
2284 22:55:54.980319 Enter into PICG configuration >>>>
2285 22:55:54.980373 Exit from PICG configuration <<<<
2286 22:55:54.980426 [RX_INPUT] configuration >>>>>
2287 22:55:54.980480 [RX_INPUT] configuration <<<<<
2288 22:55:54.980533 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2289 22:55:54.980588 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2290 22:55:54.980642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2291 22:55:54.980696 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2292 22:55:54.980750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2293 22:55:54.980804 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2294 22:55:54.980857 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2295 22:55:54.980911 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2296 22:55:54.980965 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2297 22:55:54.981019 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2298 22:55:54.981073 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2299 22:55:54.981126 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2300 22:55:54.981180 ===================================
2301 22:55:54.981235 LPDDR4 DRAM CONFIGURATION
2302 22:55:54.981288 ===================================
2303 22:55:54.981387 EX_ROW_EN[0] = 0x0
2304 22:55:54.981441 EX_ROW_EN[1] = 0x0
2305 22:55:54.981494 LP4Y_EN = 0x0
2306 22:55:54.981548 WORK_FSP = 0x0
2307 22:55:54.981601 WL = 0x4
2308 22:55:54.981655 RL = 0x4
2309 22:55:54.981708 BL = 0x2
2310 22:55:54.981762 RPST = 0x0
2311 22:55:54.981815 RD_PRE = 0x0
2312 22:55:54.981869 WR_PRE = 0x1
2313 22:55:54.981922 WR_PST = 0x0
2314 22:55:54.981976 DBI_WR = 0x0
2315 22:55:54.982029 DBI_RD = 0x0
2316 22:55:54.982082 OTF = 0x1
2317 22:55:54.982136 ===================================
2318 22:55:54.982190 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2319 22:55:54.982245 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2320 22:55:54.982299 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2321 22:55:54.982353 ===================================
2322 22:55:54.982407 LPDDR4 DRAM CONFIGURATION
2323 22:55:54.982461 ===================================
2324 22:55:54.982514 EX_ROW_EN[0] = 0x10
2325 22:55:54.982567 EX_ROW_EN[1] = 0x0
2326 22:55:54.982621 LP4Y_EN = 0x0
2327 22:55:54.982674 WORK_FSP = 0x0
2328 22:55:54.982727 WL = 0x4
2329 22:55:54.982780 RL = 0x4
2330 22:55:54.982834 BL = 0x2
2331 22:55:54.982886 RPST = 0x0
2332 22:55:54.982939 RD_PRE = 0x0
2333 22:55:54.982990 WR_PRE = 0x1
2334 22:55:54.983042 WR_PST = 0x0
2335 22:55:54.983094 DBI_WR = 0x0
2336 22:55:54.983146 DBI_RD = 0x0
2337 22:55:54.983198 OTF = 0x1
2338 22:55:54.983250 ===================================
2339 22:55:54.983303 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2340 22:55:54.983355 ==
2341 22:55:54.983408 Dram Type= 6, Freq= 0, CH_0, rank 0
2342 22:55:54.983461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2343 22:55:54.983514 ==
2344 22:55:54.983566 [Duty_Offset_Calibration]
2345 22:55:54.983618 B0:2 B1:0 CA:1
2346 22:55:54.983670
2347 22:55:54.983722 [DutyScan_Calibration_Flow] k_type=0
2348 22:55:54.983774
2349 22:55:54.983826 ==CLK 0==
2350 22:55:54.983879 Final CLK duty delay cell = -4
2351 22:55:54.983931 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2352 22:55:54.983984 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2353 22:55:54.984036 [-4] AVG Duty = 4953%(X100)
2354 22:55:54.984088
2355 22:55:54.984140 CH0 CLK Duty spec in!! Max-Min= 156%
2356 22:55:54.984193 [DutyScan_Calibration_Flow] ====Done====
2357 22:55:54.984245
2358 22:55:54.984296 [DutyScan_Calibration_Flow] k_type=1
2359 22:55:54.984348
2360 22:55:54.984400 ==DQS 0 ==
2361 22:55:54.984453 Final DQS duty delay cell = 0
2362 22:55:54.984505 [0] MAX Duty = 5187%(X100), DQS PI = 32
2363 22:55:54.984558 [0] MIN Duty = 4938%(X100), DQS PI = 0
2364 22:55:54.984610 [0] AVG Duty = 5062%(X100)
2365 22:55:54.984662
2366 22:55:54.984714 ==DQS 1 ==
2367 22:55:54.984767 Final DQS duty delay cell = -4
2368 22:55:54.984819 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2369 22:55:54.984872 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2370 22:55:54.984924 [-4] AVG Duty = 5031%(X100)
2371 22:55:54.984976
2372 22:55:54.985027 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2373 22:55:54.985079
2374 22:55:54.985132 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2375 22:55:54.985185 [DutyScan_Calibration_Flow] ====Done====
2376 22:55:54.985237
2377 22:55:54.985288 [DutyScan_Calibration_Flow] k_type=3
2378 22:55:54.985378
2379 22:55:54.985430 ==DQM 0 ==
2380 22:55:54.985482 Final DQM duty delay cell = 0
2381 22:55:54.985534 [0] MAX Duty = 5062%(X100), DQS PI = 26
2382 22:55:54.985779 [0] MIN Duty = 4813%(X100), DQS PI = 0
2383 22:55:54.985838 [0] AVG Duty = 4937%(X100)
2384 22:55:54.985891
2385 22:55:54.985943 ==DQM 1 ==
2386 22:55:54.985996 Final DQM duty delay cell = 0
2387 22:55:54.986049 [0] MAX Duty = 5187%(X100), DQS PI = 48
2388 22:55:54.986101 [0] MIN Duty = 5000%(X100), DQS PI = 10
2389 22:55:54.986153 [0] AVG Duty = 5093%(X100)
2390 22:55:54.986205
2391 22:55:54.986316 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2392 22:55:54.986370
2393 22:55:54.986421 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2394 22:55:54.986473 [DutyScan_Calibration_Flow] ====Done====
2395 22:55:54.986526
2396 22:55:54.986578 [DutyScan_Calibration_Flow] k_type=2
2397 22:55:54.986630
2398 22:55:54.986682 ==DQ 0 ==
2399 22:55:54.986735 Final DQ duty delay cell = -4
2400 22:55:54.986787 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2401 22:55:54.986858 [-4] MIN Duty = 4844%(X100), DQS PI = 14
2402 22:55:54.986912 [-4] AVG Duty = 4937%(X100)
2403 22:55:54.986965
2404 22:55:54.987016 ==DQ 1 ==
2405 22:55:54.987069 Final DQ duty delay cell = 4
2406 22:55:54.987121 [4] MAX Duty = 5093%(X100), DQS PI = 6
2407 22:55:54.987174 [4] MIN Duty = 5031%(X100), DQS PI = 0
2408 22:55:54.987226 [4] AVG Duty = 5062%(X100)
2409 22:55:54.987278
2410 22:55:54.987330 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2411 22:55:54.987382
2412 22:55:54.987434 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2413 22:55:54.987486 [DutyScan_Calibration_Flow] ====Done====
2414 22:55:54.987538 ==
2415 22:55:54.987590 Dram Type= 6, Freq= 0, CH_1, rank 0
2416 22:55:54.987642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2417 22:55:54.987695 ==
2418 22:55:54.987748 [Duty_Offset_Calibration]
2419 22:55:54.987800 B0:0 B1:-1 CA:2
2420 22:55:54.987852
2421 22:55:54.987904 [DutyScan_Calibration_Flow] k_type=0
2422 22:55:54.987956
2423 22:55:54.988008 ==CLK 0==
2424 22:55:54.988060 Final CLK duty delay cell = 0
2425 22:55:54.988112 [0] MAX Duty = 5156%(X100), DQS PI = 16
2426 22:55:54.988164 [0] MIN Duty = 4938%(X100), DQS PI = 44
2427 22:55:54.988224 [0] AVG Duty = 5047%(X100)
2428 22:55:54.988281
2429 22:55:54.988333 CH1 CLK Duty spec in!! Max-Min= 218%
2430 22:55:54.988385 [DutyScan_Calibration_Flow] ====Done====
2431 22:55:54.988437
2432 22:55:54.988488 [DutyScan_Calibration_Flow] k_type=1
2433 22:55:54.988540
2434 22:55:54.988591 ==DQS 0 ==
2435 22:55:54.988643 Final DQS duty delay cell = 0
2436 22:55:54.988695 [0] MAX Duty = 5093%(X100), DQS PI = 24
2437 22:55:54.988746 [0] MIN Duty = 4969%(X100), DQS PI = 0
2438 22:55:54.988797 [0] AVG Duty = 5031%(X100)
2439 22:55:54.988849
2440 22:55:54.988901 ==DQS 1 ==
2441 22:55:54.988952 Final DQS duty delay cell = 0
2442 22:55:54.989004 [0] MAX Duty = 5156%(X100), DQS PI = 0
2443 22:55:54.989055 [0] MIN Duty = 4844%(X100), DQS PI = 36
2444 22:55:54.989107 [0] AVG Duty = 5000%(X100)
2445 22:55:54.989158
2446 22:55:54.989209 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2447 22:55:54.989260
2448 22:55:54.989358 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2449 22:55:54.989411 [DutyScan_Calibration_Flow] ====Done====
2450 22:55:54.989463
2451 22:55:54.989515 [DutyScan_Calibration_Flow] k_type=3
2452 22:55:54.989567
2453 22:55:54.989619 ==DQM 0 ==
2454 22:55:54.989671 Final DQM duty delay cell = 4
2455 22:55:54.989723 [4] MAX Duty = 5093%(X100), DQS PI = 20
2456 22:55:54.989775 [4] MIN Duty = 4938%(X100), DQS PI = 48
2457 22:55:54.989827 [4] AVG Duty = 5015%(X100)
2458 22:55:54.989879
2459 22:55:54.989930 ==DQM 1 ==
2460 22:55:54.989983 Final DQM duty delay cell = 0
2461 22:55:54.990036 [0] MAX Duty = 5249%(X100), DQS PI = 0
2462 22:55:54.990089 [0] MIN Duty = 4875%(X100), DQS PI = 36
2463 22:55:54.990140 [0] AVG Duty = 5062%(X100)
2464 22:55:54.990192
2465 22:55:54.990249 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2466 22:55:54.990301
2467 22:55:54.990353 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2468 22:55:54.990405 [DutyScan_Calibration_Flow] ====Done====
2469 22:55:54.990457
2470 22:55:54.990508 [DutyScan_Calibration_Flow] k_type=2
2471 22:55:54.990560
2472 22:55:54.990612 ==DQ 0 ==
2473 22:55:54.990664 Final DQ duty delay cell = 0
2474 22:55:54.990716 [0] MAX Duty = 5031%(X100), DQS PI = 18
2475 22:55:54.990768 [0] MIN Duty = 4938%(X100), DQS PI = 0
2476 22:55:54.990820 [0] AVG Duty = 4984%(X100)
2477 22:55:54.990872
2478 22:55:54.990924 ==DQ 1 ==
2479 22:55:54.990975 Final DQ duty delay cell = 0
2480 22:55:54.991028 [0] MAX Duty = 5031%(X100), DQS PI = 2
2481 22:55:54.991079 [0] MIN Duty = 4813%(X100), DQS PI = 34
2482 22:55:54.991131 [0] AVG Duty = 4922%(X100)
2483 22:55:54.991183
2484 22:55:54.991235 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2485 22:55:54.991286
2486 22:55:54.991338 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2487 22:55:54.991390 [DutyScan_Calibration_Flow] ====Done====
2488 22:55:54.991442 nWR fixed to 30
2489 22:55:54.991495 [ModeRegInit_LP4] CH0 RK0
2490 22:55:54.991546 [ModeRegInit_LP4] CH0 RK1
2491 22:55:54.991598 [ModeRegInit_LP4] CH1 RK0
2492 22:55:54.991650 [ModeRegInit_LP4] CH1 RK1
2493 22:55:54.991701 match AC timing 7
2494 22:55:54.991753 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2495 22:55:54.991805 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2496 22:55:54.991858 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2497 22:55:54.991910 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2498 22:55:54.991961 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2499 22:55:54.992014 ==
2500 22:55:54.992066 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 22:55:54.992119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2502 22:55:54.992172 ==
2503 22:55:54.992231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2504 22:55:54.992317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2505 22:55:54.992386 [CA 0] Center 38 (8~69) winsize 62
2506 22:55:54.992441 [CA 1] Center 38 (7~69) winsize 63
2507 22:55:54.992494 [CA 2] Center 35 (5~66) winsize 62
2508 22:55:54.992546 [CA 3] Center 35 (5~66) winsize 62
2509 22:55:54.992599 [CA 4] Center 34 (4~65) winsize 62
2510 22:55:54.992650 [CA 5] Center 33 (3~63) winsize 61
2511 22:55:54.992703
2512 22:55:54.992755 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2513 22:55:54.992808
2514 22:55:54.992859 [CATrainingPosCal] consider 1 rank data
2515 22:55:54.992911 u2DelayCellTimex100 = 270/100 ps
2516 22:55:54.992963 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2517 22:55:54.993015 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2518 22:55:54.993067 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2519 22:55:54.993118 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2520 22:55:54.993171 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2521 22:55:54.993223 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2522 22:55:54.993275
2523 22:55:54.993359 CA PerBit enable=1, Macro0, CA PI delay=33
2524 22:55:54.993426
2525 22:55:54.993478 [CBTSetCACLKResult] CA Dly = 33
2526 22:55:54.993530 CS Dly: 6 (0~37)
2527 22:55:54.993582 ==
2528 22:55:54.993635 Dram Type= 6, Freq= 0, CH_0, rank 1
2529 22:55:54.993687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 22:55:54.993740 ==
2531 22:55:54.993992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 22:55:54.994055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2533 22:55:54.994109 [CA 0] Center 39 (8~70) winsize 63
2534 22:55:54.994162 [CA 1] Center 38 (8~69) winsize 62
2535 22:55:54.994215 [CA 2] Center 35 (5~66) winsize 62
2536 22:55:54.994286 [CA 3] Center 35 (5~66) winsize 62
2537 22:55:54.994339 [CA 4] Center 34 (4~65) winsize 62
2538 22:55:54.994391 [CA 5] Center 34 (4~64) winsize 61
2539 22:55:54.994443
2540 22:55:54.994496 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2541 22:55:54.994548
2542 22:55:54.994600 [CATrainingPosCal] consider 2 rank data
2543 22:55:54.994653 u2DelayCellTimex100 = 270/100 ps
2544 22:55:54.994705 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2545 22:55:54.994757 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2546 22:55:54.994810 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 22:55:54.994862 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2548 22:55:54.994914 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2549 22:55:54.994966 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2550 22:55:54.995018
2551 22:55:54.995069 CA PerBit enable=1, Macro0, CA PI delay=33
2552 22:55:54.995122
2553 22:55:54.995173 [CBTSetCACLKResult] CA Dly = 33
2554 22:55:54.995225 CS Dly: 7 (0~39)
2555 22:55:54.995277
2556 22:55:54.995329 ----->DramcWriteLeveling(PI) begin...
2557 22:55:54.995382 ==
2558 22:55:54.995435 Dram Type= 6, Freq= 0, CH_0, rank 0
2559 22:55:54.995487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 22:55:54.995540 ==
2561 22:55:54.995592 Write leveling (Byte 0): 33 => 33
2562 22:55:54.995644 Write leveling (Byte 1): 31 => 31
2563 22:55:54.995696 DramcWriteLeveling(PI) end<-----
2564 22:55:54.995748
2565 22:55:54.995799 ==
2566 22:55:54.995851 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 22:55:54.995903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 22:55:54.995955 ==
2569 22:55:54.996007 [Gating] SW mode calibration
2570 22:55:54.996059 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2571 22:55:54.996112 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2572 22:55:54.996164 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2573 22:55:54.996220 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2574 22:55:54.996287 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 22:55:54.996340 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 22:55:54.996393 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 22:55:54.996445 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 22:55:54.996496 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2579 22:55:54.996549 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2580 22:55:54.996601 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2581 22:55:54.996654 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 22:55:54.996706 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 22:55:54.996758 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 22:55:54.996810 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 22:55:54.996862 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 22:55:54.996914 1 0 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2587 22:55:54.996965 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2588 22:55:54.997017 1 1 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
2589 22:55:54.997070 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 22:55:54.997122 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 22:55:54.997174 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 22:55:54.997226 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 22:55:54.997278 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 22:55:54.997367 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2595 22:55:54.997434 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2596 22:55:54.997487 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2597 22:55:54.997538 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 22:55:54.997590 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 22:55:54.997642 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 22:55:54.997694 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 22:55:54.997746 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 22:55:54.997798 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 22:55:54.997849 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 22:55:54.997901 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 22:55:54.997968 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 22:55:54.998024 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 22:55:54.998076 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 22:55:54.998128 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 22:55:54.998180 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 22:55:54.998236 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2611 22:55:54.998290 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2612 22:55:54.998343 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2613 22:55:54.998395 Total UI for P1: 0, mck2ui 16
2614 22:55:54.998447 best dqsien dly found for B0: ( 1, 3, 26)
2615 22:55:54.998499 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 22:55:54.998551 Total UI for P1: 0, mck2ui 16
2617 22:55:54.998603 best dqsien dly found for B1: ( 1, 3, 30)
2618 22:55:54.998655 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2619 22:55:54.998707 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2620 22:55:54.998758
2621 22:55:54.998810 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2622 22:55:54.998863 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2623 22:55:54.998915 [Gating] SW calibration Done
2624 22:55:54.998966 ==
2625 22:55:54.999018 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 22:55:54.999070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 22:55:54.999122 ==
2628 22:55:54.999174 RX Vref Scan: 0
2629 22:55:54.999225
2630 22:55:54.999277 RX Vref 0 -> 0, step: 1
2631 22:55:54.999329
2632 22:55:54.999381 RX Delay -40 -> 252, step: 8
2633 22:55:54.999432 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2634 22:55:54.999484 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2635 22:55:54.999536 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2636 22:55:54.999783 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2637 22:55:54.999841 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2638 22:55:54.999895 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2639 22:55:54.999949 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2640 22:55:55.000001 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2641 22:55:55.000054 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2642 22:55:55.000107 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2643 22:55:55.000159 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2644 22:55:55.000211 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2645 22:55:55.000295 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2646 22:55:55.000375 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2647 22:55:55.000430 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2648 22:55:55.000483 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2649 22:55:55.000535 ==
2650 22:55:55.000590 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 22:55:55.000643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 22:55:55.000696 ==
2653 22:55:55.000749 DQS Delay:
2654 22:55:55.000801 DQS0 = 0, DQS1 = 0
2655 22:55:55.000853 DQM Delay:
2656 22:55:55.000905 DQM0 = 122, DQM1 = 110
2657 22:55:55.000957 DQ Delay:
2658 22:55:55.001009 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2659 22:55:55.001062 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2660 22:55:55.001114 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2661 22:55:55.001166 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2662 22:55:55.001218
2663 22:55:55.001270
2664 22:55:55.001354 ==
2665 22:55:55.001422 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 22:55:55.001474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 22:55:55.001527 ==
2668 22:55:55.001579
2669 22:55:55.001631
2670 22:55:55.001683 TX Vref Scan disable
2671 22:55:55.001736 == TX Byte 0 ==
2672 22:55:55.001789 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2673 22:55:55.001841 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2674 22:55:55.001894 == TX Byte 1 ==
2675 22:55:55.001946 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2676 22:55:55.001999 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2677 22:55:55.002051 ==
2678 22:55:55.002104 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 22:55:55.002156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 22:55:55.002209 ==
2681 22:55:55.002262 TX Vref=22, minBit 6, minWin=24, winSum=408
2682 22:55:55.002315 TX Vref=24, minBit 7, minWin=24, winSum=415
2683 22:55:55.002367 TX Vref=26, minBit 0, minWin=25, winSum=415
2684 22:55:55.002420 TX Vref=28, minBit 1, minWin=25, winSum=424
2685 22:55:55.002472 TX Vref=30, minBit 1, minWin=25, winSum=423
2686 22:55:55.002525 TX Vref=32, minBit 1, minWin=25, winSum=419
2687 22:55:55.002578 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 28
2688 22:55:55.002630
2689 22:55:55.002682 Final TX Range 1 Vref 28
2690 22:55:55.002735
2691 22:55:55.002787 ==
2692 22:55:55.002841 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 22:55:55.002894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 22:55:55.002946 ==
2695 22:55:55.002999
2696 22:55:55.003050
2697 22:55:55.003103 TX Vref Scan disable
2698 22:55:55.003155 == TX Byte 0 ==
2699 22:55:55.003207 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2700 22:55:55.003260 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2701 22:55:55.003313 == TX Byte 1 ==
2702 22:55:55.003364 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2703 22:55:55.003417 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2704 22:55:55.003468
2705 22:55:55.003521 [DATLAT]
2706 22:55:55.003573 Freq=1200, CH0 RK0
2707 22:55:55.003625
2708 22:55:55.003677 DATLAT Default: 0xd
2709 22:55:55.003729 0, 0xFFFF, sum = 0
2710 22:55:55.003783 1, 0xFFFF, sum = 0
2711 22:55:55.003836 2, 0xFFFF, sum = 0
2712 22:55:55.003889 3, 0xFFFF, sum = 0
2713 22:55:55.003942 4, 0xFFFF, sum = 0
2714 22:55:55.003996 5, 0xFFFF, sum = 0
2715 22:55:55.004049 6, 0xFFFF, sum = 0
2716 22:55:55.004101 7, 0xFFFF, sum = 0
2717 22:55:55.004154 8, 0xFFFF, sum = 0
2718 22:55:55.004206 9, 0xFFFF, sum = 0
2719 22:55:55.004258 10, 0xFFFF, sum = 0
2720 22:55:55.004311 11, 0xFFFF, sum = 0
2721 22:55:55.004363 12, 0x0, sum = 1
2722 22:55:55.004416 13, 0x0, sum = 2
2723 22:55:55.004469 14, 0x0, sum = 3
2724 22:55:55.004520 15, 0x0, sum = 4
2725 22:55:55.004573 best_step = 13
2726 22:55:55.004624
2727 22:55:55.004676 ==
2728 22:55:55.004727 Dram Type= 6, Freq= 0, CH_0, rank 0
2729 22:55:55.004780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2730 22:55:55.004833 ==
2731 22:55:55.004885 RX Vref Scan: 1
2732 22:55:55.004937
2733 22:55:55.004989 Set Vref Range= 32 -> 127
2734 22:55:55.005041
2735 22:55:55.005093 RX Vref 32 -> 127, step: 1
2736 22:55:55.005145
2737 22:55:55.005198 RX Delay -13 -> 252, step: 4
2738 22:55:55.005251
2739 22:55:55.005307 Set Vref, RX VrefLevel [Byte0]: 32
2740 22:55:55.005396 [Byte1]: 32
2741 22:55:55.005449
2742 22:55:55.005501 Set Vref, RX VrefLevel [Byte0]: 33
2743 22:55:55.005554 [Byte1]: 33
2744 22:55:55.005606
2745 22:55:55.005658 Set Vref, RX VrefLevel [Byte0]: 34
2746 22:55:55.005710 [Byte1]: 34
2747 22:55:55.005762
2748 22:55:55.005814 Set Vref, RX VrefLevel [Byte0]: 35
2749 22:55:55.005866 [Byte1]: 35
2750 22:55:55.005919
2751 22:55:55.005971 Set Vref, RX VrefLevel [Byte0]: 36
2752 22:55:55.006023 [Byte1]: 36
2753 22:55:55.006075
2754 22:55:55.006127 Set Vref, RX VrefLevel [Byte0]: 37
2755 22:55:55.006179 [Byte1]: 37
2756 22:55:55.006231
2757 22:55:55.006283 Set Vref, RX VrefLevel [Byte0]: 38
2758 22:55:55.006336 [Byte1]: 38
2759 22:55:55.006387
2760 22:55:55.006440 Set Vref, RX VrefLevel [Byte0]: 39
2761 22:55:55.006492 [Byte1]: 39
2762 22:55:55.006544
2763 22:55:55.006595 Set Vref, RX VrefLevel [Byte0]: 40
2764 22:55:55.006647 [Byte1]: 40
2765 22:55:55.006699
2766 22:55:55.006751 Set Vref, RX VrefLevel [Byte0]: 41
2767 22:55:55.006803 [Byte1]: 41
2768 22:55:55.006854
2769 22:55:55.006906 Set Vref, RX VrefLevel [Byte0]: 42
2770 22:55:55.006958 [Byte1]: 42
2771 22:55:55.007011
2772 22:55:55.007062 Set Vref, RX VrefLevel [Byte0]: 43
2773 22:55:55.007114 [Byte1]: 43
2774 22:55:55.007166
2775 22:55:55.007217 Set Vref, RX VrefLevel [Byte0]: 44
2776 22:55:55.007270 [Byte1]: 44
2777 22:55:55.007321
2778 22:55:55.007373 Set Vref, RX VrefLevel [Byte0]: 45
2779 22:55:55.007425 [Byte1]: 45
2780 22:55:55.007477
2781 22:55:55.007529 Set Vref, RX VrefLevel [Byte0]: 46
2782 22:55:55.007582 [Byte1]: 46
2783 22:55:55.007633
2784 22:55:55.007685 Set Vref, RX VrefLevel [Byte0]: 47
2785 22:55:55.007737 [Byte1]: 47
2786 22:55:55.007788
2787 22:55:55.007840 Set Vref, RX VrefLevel [Byte0]: 48
2788 22:55:55.007892 [Byte1]: 48
2789 22:55:55.007944
2790 22:55:55.007996 Set Vref, RX VrefLevel [Byte0]: 49
2791 22:55:55.008048 [Byte1]: 49
2792 22:55:55.008100
2793 22:55:55.008152 Set Vref, RX VrefLevel [Byte0]: 50
2794 22:55:55.008397 [Byte1]: 50
2795 22:55:55.008456
2796 22:55:55.008509 Set Vref, RX VrefLevel [Byte0]: 51
2797 22:55:55.008562 [Byte1]: 51
2798 22:55:55.008614
2799 22:55:55.008666 Set Vref, RX VrefLevel [Byte0]: 52
2800 22:55:55.008718 [Byte1]: 52
2801 22:55:55.008770
2802 22:55:55.008821 Set Vref, RX VrefLevel [Byte0]: 53
2803 22:55:55.008873 [Byte1]: 53
2804 22:55:55.008925
2805 22:55:55.008977 Set Vref, RX VrefLevel [Byte0]: 54
2806 22:55:55.009029 [Byte1]: 54
2807 22:55:55.009081
2808 22:55:55.009133 Set Vref, RX VrefLevel [Byte0]: 55
2809 22:55:55.009185 [Byte1]: 55
2810 22:55:55.009237
2811 22:55:55.009288 Set Vref, RX VrefLevel [Byte0]: 56
2812 22:55:55.009385 [Byte1]: 56
2813 22:55:55.009437
2814 22:55:55.009489 Set Vref, RX VrefLevel [Byte0]: 57
2815 22:55:55.009541 [Byte1]: 57
2816 22:55:55.009592
2817 22:55:55.009644 Set Vref, RX VrefLevel [Byte0]: 58
2818 22:55:55.009696 [Byte1]: 58
2819 22:55:55.009748
2820 22:55:55.009799 Set Vref, RX VrefLevel [Byte0]: 59
2821 22:55:55.009851 [Byte1]: 59
2822 22:55:55.009903
2823 22:55:55.009955 Set Vref, RX VrefLevel [Byte0]: 60
2824 22:55:55.010006 [Byte1]: 60
2825 22:55:55.010058
2826 22:55:55.010109 Set Vref, RX VrefLevel [Byte0]: 61
2827 22:55:55.010161 [Byte1]: 61
2828 22:55:55.010212
2829 22:55:55.010269 Set Vref, RX VrefLevel [Byte0]: 62
2830 22:55:55.010323 [Byte1]: 62
2831 22:55:55.010375
2832 22:55:55.010427 Set Vref, RX VrefLevel [Byte0]: 63
2833 22:55:55.010479 [Byte1]: 63
2834 22:55:55.010531
2835 22:55:55.010582 Set Vref, RX VrefLevel [Byte0]: 64
2836 22:55:55.010633 [Byte1]: 64
2837 22:55:55.010685
2838 22:55:55.010737 Set Vref, RX VrefLevel [Byte0]: 65
2839 22:55:55.010788 [Byte1]: 65
2840 22:55:55.010840
2841 22:55:55.010892 Set Vref, RX VrefLevel [Byte0]: 66
2842 22:55:55.010944 [Byte1]: 66
2843 22:55:55.010996
2844 22:55:55.011047 Set Vref, RX VrefLevel [Byte0]: 67
2845 22:55:55.011099 [Byte1]: 67
2846 22:55:55.011150
2847 22:55:55.011202 Set Vref, RX VrefLevel [Byte0]: 68
2848 22:55:55.011254 [Byte1]: 68
2849 22:55:55.011305
2850 22:55:55.011358 Set Vref, RX VrefLevel [Byte0]: 69
2851 22:55:55.011409 [Byte1]: 69
2852 22:55:55.011461
2853 22:55:55.011512 Set Vref, RX VrefLevel [Byte0]: 70
2854 22:55:55.011565 [Byte1]: 70
2855 22:55:55.011616
2856 22:55:55.011668 Final RX Vref Byte 0 = 58 to rank0
2857 22:55:55.011720 Final RX Vref Byte 1 = 50 to rank0
2858 22:55:55.011773 Final RX Vref Byte 0 = 58 to rank1
2859 22:55:55.011825 Final RX Vref Byte 1 = 50 to rank1==
2860 22:55:55.011878 Dram Type= 6, Freq= 0, CH_0, rank 0
2861 22:55:55.011930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 22:55:55.011982 ==
2863 22:55:55.012034 DQS Delay:
2864 22:55:55.012087 DQS0 = 0, DQS1 = 0
2865 22:55:55.012139 DQM Delay:
2866 22:55:55.012191 DQM0 = 122, DQM1 = 109
2867 22:55:55.012242 DQ Delay:
2868 22:55:55.012294 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2869 22:55:55.012346 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2870 22:55:55.012399 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2871 22:55:55.012450 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2872 22:55:55.012503
2873 22:55:55.012554
2874 22:55:55.012606 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
2875 22:55:55.012659 CH0 RK0: MR19=404, MR18=F0B
2876 22:55:55.012711 CH0_RK0: MR19=0x404, MR18=0xF0B, DQSOSC=404, MR23=63, INC=40, DEC=26
2877 22:55:55.012763
2878 22:55:55.012815 ----->DramcWriteLeveling(PI) begin...
2879 22:55:55.012868 ==
2880 22:55:55.012921 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 22:55:55.012972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 22:55:55.013024 ==
2883 22:55:55.013076 Write leveling (Byte 0): 35 => 35
2884 22:55:55.013128 Write leveling (Byte 1): 29 => 29
2885 22:55:55.013180 DramcWriteLeveling(PI) end<-----
2886 22:55:55.013232
2887 22:55:55.013284 ==
2888 22:55:55.013380 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 22:55:55.013433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 22:55:55.013486 ==
2891 22:55:55.013538 [Gating] SW mode calibration
2892 22:55:55.013589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2893 22:55:55.013642 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2894 22:55:55.013694 0 15 0 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
2895 22:55:55.013747 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 22:55:55.013799 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 22:55:55.013851 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 22:55:55.013902 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 22:55:55.013955 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 22:55:55.014007 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2901 22:55:55.014059 0 15 28 | B1->B0 | 2e2e 2b2b | 1 1 | (1 1) (1 0)
2902 22:55:55.014111 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2903 22:55:55.014164 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 22:55:55.014216 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 22:55:55.014278 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 22:55:55.014346 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 22:55:55.014424 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 22:55:55.014479 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2909 22:55:55.014531 1 0 28 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
2910 22:55:55.014584 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 22:55:55.014637 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 22:55:55.014689 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 22:55:55.014740 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 22:55:55.014793 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 22:55:55.014845 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 22:55:55.014896 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 22:55:55.014948 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2918 22:55:55.015000 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2919 22:55:55.015052 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 22:55:55.015300 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 22:55:55.015362 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 22:55:55.015416 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 22:55:55.015468 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 22:55:55.015520 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 22:55:55.015572 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 22:55:55.015625 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 22:55:55.015677 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 22:55:55.015729 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 22:55:55.015781 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 22:55:55.015833 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 22:55:55.015886 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 22:55:55.015938 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2933 22:55:55.015990 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2934 22:55:55.016042 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 22:55:55.016094 Total UI for P1: 0, mck2ui 16
2936 22:55:55.016164 best dqsien dly found for B0: ( 1, 3, 26)
2937 22:55:55.016252 Total UI for P1: 0, mck2ui 16
2938 22:55:55.016339 best dqsien dly found for B1: ( 1, 3, 28)
2939 22:55:55.016396 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2940 22:55:55.016449 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2941 22:55:55.016502
2942 22:55:55.016554 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2943 22:55:55.016607 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2944 22:55:55.016659 [Gating] SW calibration Done
2945 22:55:55.016711 ==
2946 22:55:55.016764 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 22:55:55.016816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 22:55:55.016869 ==
2949 22:55:55.016921 RX Vref Scan: 0
2950 22:55:55.016973
2951 22:55:55.017034 RX Vref 0 -> 0, step: 1
2952 22:55:55.017116
2953 22:55:55.017197 RX Delay -40 -> 252, step: 8
2954 22:55:55.017279 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2955 22:55:55.017383 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2956 22:55:55.017437 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2957 22:55:55.017490 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2958 22:55:55.017542 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2959 22:55:55.017595 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2960 22:55:55.017647 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2961 22:55:55.017699 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2962 22:55:55.017751 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2963 22:55:55.017804 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2964 22:55:55.017856 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2965 22:55:55.017908 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2966 22:55:55.017960 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2967 22:55:55.018012 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2968 22:55:55.018064 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2969 22:55:55.018116 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2970 22:55:55.018168 ==
2971 22:55:55.018220 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 22:55:55.018273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 22:55:55.018325 ==
2974 22:55:55.018377 DQS Delay:
2975 22:55:55.018429 DQS0 = 0, DQS1 = 0
2976 22:55:55.134369 DQM Delay:
2977 22:55:55.134515 DQM0 = 120, DQM1 = 108
2978 22:55:55.134583 DQ Delay:
2979 22:55:55.134646 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2980 22:55:55.134707 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2981 22:55:55.134766 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2982 22:55:55.134823 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2983 22:55:55.134879
2984 22:55:55.134934
2985 22:55:55.134989 ==
2986 22:55:55.135044 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 22:55:55.135099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 22:55:55.135154 ==
2989 22:55:55.135208
2990 22:55:55.135261
2991 22:55:55.135315 TX Vref Scan disable
2992 22:55:55.135369 == TX Byte 0 ==
2993 22:55:55.135422 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2994 22:55:55.135477 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2995 22:55:55.135530 == TX Byte 1 ==
2996 22:55:55.135584 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2997 22:55:55.135637 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2998 22:55:55.135690 ==
2999 22:55:55.135744 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 22:55:55.135797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 22:55:55.135851 ==
3002 22:55:55.135905 TX Vref=22, minBit 0, minWin=24, winSum=407
3003 22:55:55.135959 TX Vref=24, minBit 1, minWin=24, winSum=415
3004 22:55:55.136013 TX Vref=26, minBit 1, minWin=25, winSum=423
3005 22:55:55.136066 TX Vref=28, minBit 3, minWin=25, winSum=429
3006 22:55:55.136119 TX Vref=30, minBit 0, minWin=25, winSum=422
3007 22:55:55.136173 TX Vref=32, minBit 2, minWin=25, winSum=425
3008 22:55:55.136226 [TxChooseVref] Worse bit 3, Min win 25, Win sum 429, Final Vref 28
3009 22:55:55.136280
3010 22:55:55.136333 Final TX Range 1 Vref 28
3011 22:55:55.136387
3012 22:55:55.136440 ==
3013 22:55:55.136493 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 22:55:55.136547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 22:55:55.136600 ==
3016 22:55:55.136653
3017 22:55:55.136706
3018 22:55:55.136758 TX Vref Scan disable
3019 22:55:55.136811 == TX Byte 0 ==
3020 22:55:55.136865 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3021 22:55:55.136919 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3022 22:55:55.136972 == TX Byte 1 ==
3023 22:55:55.137025 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3024 22:55:55.137078 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3025 22:55:55.137131
3026 22:55:55.137184 [DATLAT]
3027 22:55:55.137237 Freq=1200, CH0 RK1
3028 22:55:55.137290
3029 22:55:55.137372 DATLAT Default: 0xd
3030 22:55:55.137425 0, 0xFFFF, sum = 0
3031 22:55:55.137479 1, 0xFFFF, sum = 0
3032 22:55:55.137532 2, 0xFFFF, sum = 0
3033 22:55:55.137585 3, 0xFFFF, sum = 0
3034 22:55:55.137639 4, 0xFFFF, sum = 0
3035 22:55:55.137692 5, 0xFFFF, sum = 0
3036 22:55:55.137744 6, 0xFFFF, sum = 0
3037 22:55:55.137797 7, 0xFFFF, sum = 0
3038 22:55:55.137850 8, 0xFFFF, sum = 0
3039 22:55:55.137903 9, 0xFFFF, sum = 0
3040 22:55:55.137956 10, 0xFFFF, sum = 0
3041 22:55:55.138009 11, 0xFFFF, sum = 0
3042 22:55:55.138062 12, 0x0, sum = 1
3043 22:55:55.138114 13, 0x0, sum = 2
3044 22:55:55.138166 14, 0x0, sum = 3
3045 22:55:55.138219 15, 0x0, sum = 4
3046 22:55:55.138271 best_step = 13
3047 22:55:55.138323
3048 22:55:55.138375 ==
3049 22:55:55.138427 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 22:55:55.138480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 22:55:55.138532 ==
3052 22:55:55.138585 RX Vref Scan: 0
3053 22:55:55.138637
3054 22:55:55.138689 RX Vref 0 -> 0, step: 1
3055 22:55:55.138741
3056 22:55:55.138793 RX Delay -21 -> 252, step: 4
3057 22:55:55.139057 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3058 22:55:55.139118 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3059 22:55:55.139173 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3060 22:55:55.139226 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3061 22:55:55.139279 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3062 22:55:55.139332 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3063 22:55:55.139384 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3064 22:55:55.139436 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3065 22:55:55.139489 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3066 22:55:55.139541 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3067 22:55:55.139593 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3068 22:55:55.139644 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3069 22:55:55.139696 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3070 22:55:55.139749 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3071 22:55:55.139819 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3072 22:55:55.139911 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3073 22:55:55.139995 ==
3074 22:55:55.140062 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 22:55:55.140114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 22:55:55.140167 ==
3077 22:55:55.140220 DQS Delay:
3078 22:55:55.140272 DQS0 = 0, DQS1 = 0
3079 22:55:55.140324 DQM Delay:
3080 22:55:55.140376 DQM0 = 119, DQM1 = 107
3081 22:55:55.140428 DQ Delay:
3082 22:55:55.140480 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3083 22:55:55.140569 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3084 22:55:55.140621 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3085 22:55:55.140673 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3086 22:55:55.140725
3087 22:55:55.140777
3088 22:55:55.140830 [DQSOSCAuto] RK1, (LSB)MR18= 0xef5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3089 22:55:55.140885 CH0 RK1: MR19=403, MR18=EF5
3090 22:55:55.140938 CH0_RK1: MR19=0x403, MR18=0xEF5, DQSOSC=404, MR23=63, INC=40, DEC=26
3091 22:55:55.140992 [RxdqsGatingPostProcess] freq 1200
3092 22:55:55.141045 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3093 22:55:55.141099 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 22:55:55.141153 best DQS1 dly(2T, 0.5T) = (0, 11)
3095 22:55:55.141233 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 22:55:55.141288 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3097 22:55:55.141368 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 22:55:55.141440 best DQS1 dly(2T, 0.5T) = (0, 11)
3099 22:55:55.141527 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 22:55:55.141594 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3101 22:55:55.141648 Pre-setting of DQS Precalculation
3102 22:55:55.141702 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3103 22:55:55.141773 ==
3104 22:55:55.141845 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 22:55:55.141961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 22:55:55.142089 ==
3107 22:55:55.142192 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 22:55:55.142282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3109 22:55:55.142373 [CA 0] Center 37 (7~68) winsize 62
3110 22:55:55.142438 [CA 1] Center 37 (7~68) winsize 62
3111 22:55:55.142499 [CA 2] Center 35 (5~65) winsize 61
3112 22:55:55.142572 [CA 3] Center 34 (4~65) winsize 62
3113 22:55:55.142661 [CA 4] Center 33 (3~64) winsize 62
3114 22:55:55.142758 [CA 5] Center 33 (3~64) winsize 62
3115 22:55:55.142852
3116 22:55:55.142946 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3117 22:55:55.143037
3118 22:55:55.143127 [CATrainingPosCal] consider 1 rank data
3119 22:55:55.143218 u2DelayCellTimex100 = 270/100 ps
3120 22:55:55.143310 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 22:55:55.143456 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 22:55:55.143547 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3123 22:55:55.143640 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3124 22:55:55.143744 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3125 22:55:55.143828 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3126 22:55:55.143908
3127 22:55:55.143987 CA PerBit enable=1, Macro0, CA PI delay=33
3128 22:55:55.144065
3129 22:55:55.144153 [CBTSetCACLKResult] CA Dly = 33
3130 22:55:55.144248 CS Dly: 5 (0~36)
3131 22:55:55.144340 ==
3132 22:55:55.144432 Dram Type= 6, Freq= 0, CH_1, rank 1
3133 22:55:55.144521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 22:55:55.144613 ==
3135 22:55:55.144702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 22:55:55.144793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3137 22:55:55.144881 [CA 0] Center 38 (8~68) winsize 61
3138 22:55:55.144969 [CA 1] Center 38 (7~69) winsize 63
3139 22:55:55.145058 [CA 2] Center 35 (5~66) winsize 62
3140 22:55:55.145146 [CA 3] Center 35 (5~65) winsize 61
3141 22:55:55.145234 [CA 4] Center 34 (4~64) winsize 61
3142 22:55:55.145348 [CA 5] Center 34 (4~64) winsize 61
3143 22:55:55.145443
3144 22:55:55.145539 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3145 22:55:55.145637
3146 22:55:55.145733 [CATrainingPosCal] consider 2 rank data
3147 22:55:55.145829 u2DelayCellTimex100 = 270/100 ps
3148 22:55:55.145924 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3149 22:55:55.146020 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3150 22:55:55.146130 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3151 22:55:55.146269 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3152 22:55:55.146363 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3153 22:55:55.146486 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3154 22:55:55.146578
3155 22:55:55.146670 CA PerBit enable=1, Macro0, CA PI delay=34
3156 22:55:55.146809
3157 22:55:55.146916 [CBTSetCACLKResult] CA Dly = 34
3158 22:55:55.147009 CS Dly: 6 (0~39)
3159 22:55:55.147102
3160 22:55:55.147195 ----->DramcWriteLeveling(PI) begin...
3161 22:55:55.147289 ==
3162 22:55:55.147398 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 22:55:55.147507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 22:55:55.147600 ==
3165 22:55:55.147710 Write leveling (Byte 0): 25 => 25
3166 22:55:55.147834 Write leveling (Byte 1): 29 => 29
3167 22:55:55.147929 DramcWriteLeveling(PI) end<-----
3168 22:55:55.148023
3169 22:55:55.148117 ==
3170 22:55:55.148211 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 22:55:55.148305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 22:55:55.148400 ==
3173 22:55:55.148495 [Gating] SW mode calibration
3174 22:55:55.148603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3175 22:55:55.148697 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3176 22:55:55.149017 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 22:55:55.149114 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 22:55:55.149225 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 22:55:55.149348 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 22:55:55.149445 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 22:55:55.149539 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3182 22:55:55.149633 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
3183 22:55:55.149743 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3184 22:55:55.149869 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 22:55:55.149964 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 22:55:55.150058 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 22:55:55.150165 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 22:55:55.150257 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 22:55:55.150348 1 0 20 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
3190 22:55:55.150440 1 0 24 | B1->B0 | 4040 4544 | 0 1 | (0 0) (0 0)
3191 22:55:55.150531 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 22:55:55.150623 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 22:55:55.150715 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 22:55:55.150812 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 22:55:55.150904 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 22:55:55.150995 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 22:55:55.151087 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 22:55:55.151179 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3199 22:55:55.151308 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3200 22:55:55.151400 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 22:55:55.151547 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 22:55:55.151684 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 22:55:55.151810 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 22:55:55.151903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 22:55:55.151995 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 22:55:55.152087 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 22:55:55.152180 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 22:55:55.152273 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 22:55:55.152389 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 22:55:55.152527 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 22:55:55.152648 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 22:55:55.152740 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 22:55:55.152831 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3214 22:55:55.152923 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 22:55:55.153014 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3216 22:55:55.153123 Total UI for P1: 0, mck2ui 16
3217 22:55:55.153218 best dqsien dly found for B0: ( 1, 3, 22)
3218 22:55:55.153318 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 22:55:55.153426 Total UI for P1: 0, mck2ui 16
3220 22:55:55.153519 best dqsien dly found for B1: ( 1, 3, 24)
3221 22:55:55.153630 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3222 22:55:55.153737 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3223 22:55:55.153828
3224 22:55:55.153920 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3225 22:55:55.154013 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3226 22:55:55.154105 [Gating] SW calibration Done
3227 22:55:55.154228 ==
3228 22:55:55.154321 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 22:55:55.154413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 22:55:55.154506 ==
3231 22:55:55.154598 RX Vref Scan: 0
3232 22:55:55.154723
3233 22:55:55.154815 RX Vref 0 -> 0, step: 1
3234 22:55:55.154907
3235 22:55:55.154998 RX Delay -40 -> 252, step: 8
3236 22:55:55.155090 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3237 22:55:55.155183 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3238 22:55:55.155308 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3239 22:55:55.155400 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3240 22:55:55.155492 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3241 22:55:55.155584 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3242 22:55:55.155676 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3243 22:55:55.155799 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3244 22:55:55.155891 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3245 22:55:55.155982 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3246 22:55:55.156074 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3247 22:55:55.156165 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3248 22:55:55.156274 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3249 22:55:55.156382 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3250 22:55:55.156474 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3251 22:55:55.156566 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3252 22:55:55.156658 ==
3253 22:55:55.156781 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 22:55:55.156912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 22:55:55.157049 ==
3256 22:55:55.157149 DQS Delay:
3257 22:55:55.157245 DQS0 = 0, DQS1 = 0
3258 22:55:55.157353 DQM Delay:
3259 22:55:55.157449 DQM0 = 120, DQM1 = 112
3260 22:55:55.157545 DQ Delay:
3261 22:55:55.157641 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3262 22:55:55.157736 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3263 22:55:55.157831 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3264 22:55:55.157925 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3265 22:55:55.158019
3266 22:55:55.158113
3267 22:55:55.158209 ==
3268 22:55:55.158304 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 22:55:55.158399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 22:55:55.158494 ==
3271 22:55:55.158588
3272 22:55:55.158682
3273 22:55:55.158775 TX Vref Scan disable
3274 22:55:55.158869 == TX Byte 0 ==
3275 22:55:55.158963 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3276 22:55:55.159058 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3277 22:55:55.159152 == TX Byte 1 ==
3278 22:55:55.159246 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3279 22:55:55.159340 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3280 22:55:55.159434 ==
3281 22:55:55.159528 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 22:55:55.159839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 22:55:55.159936 ==
3284 22:55:55.160033 TX Vref=22, minBit 11, minWin=24, winSum=408
3285 22:55:55.160131 TX Vref=24, minBit 10, minWin=24, winSum=406
3286 22:55:55.160227 TX Vref=26, minBit 3, minWin=25, winSum=415
3287 22:55:55.160323 TX Vref=28, minBit 9, minWin=25, winSum=422
3288 22:55:55.160418 TX Vref=30, minBit 1, minWin=26, winSum=424
3289 22:55:55.160514 TX Vref=32, minBit 9, minWin=24, winSum=420
3290 22:55:55.160610 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 30
3291 22:55:55.160705
3292 22:55:55.160800 Final TX Range 1 Vref 30
3293 22:55:55.160895
3294 22:55:55.160990 ==
3295 22:55:55.161084 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 22:55:55.161178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 22:55:55.161273 ==
3298 22:55:55.161377
3299 22:55:55.161472
3300 22:55:55.161567 TX Vref Scan disable
3301 22:55:55.161662 == TX Byte 0 ==
3302 22:55:55.161756 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3303 22:55:55.161851 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3304 22:55:55.161945 == TX Byte 1 ==
3305 22:55:55.162039 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3306 22:55:55.162133 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3307 22:55:55.162227
3308 22:55:55.162321 [DATLAT]
3309 22:55:55.162415 Freq=1200, CH1 RK0
3310 22:55:55.162510
3311 22:55:55.162603 DATLAT Default: 0xd
3312 22:55:55.162697 0, 0xFFFF, sum = 0
3313 22:55:55.162793 1, 0xFFFF, sum = 0
3314 22:55:55.162888 2, 0xFFFF, sum = 0
3315 22:55:55.162984 3, 0xFFFF, sum = 0
3316 22:55:55.163079 4, 0xFFFF, sum = 0
3317 22:55:55.163174 5, 0xFFFF, sum = 0
3318 22:55:55.163270 6, 0xFFFF, sum = 0
3319 22:55:55.163365 7, 0xFFFF, sum = 0
3320 22:55:55.163460 8, 0xFFFF, sum = 0
3321 22:55:55.163555 9, 0xFFFF, sum = 0
3322 22:55:55.163651 10, 0xFFFF, sum = 0
3323 22:55:55.163746 11, 0xFFFF, sum = 0
3324 22:55:55.163841 12, 0x0, sum = 1
3325 22:55:55.163936 13, 0x0, sum = 2
3326 22:55:55.164032 14, 0x0, sum = 3
3327 22:55:55.164127 15, 0x0, sum = 4
3328 22:55:55.164222 best_step = 13
3329 22:55:55.164315
3330 22:55:55.164408 ==
3331 22:55:55.164501 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 22:55:55.164595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 22:55:55.164688 ==
3334 22:55:55.164784 RX Vref Scan: 1
3335 22:55:55.164877
3336 22:55:55.164963 Set Vref Range= 32 -> 127
3337 22:55:55.165048
3338 22:55:55.165132 RX Vref 32 -> 127, step: 1
3339 22:55:55.165215
3340 22:55:55.165303 RX Delay -13 -> 252, step: 4
3341 22:55:55.165387
3342 22:55:55.165470 Set Vref, RX VrefLevel [Byte0]: 32
3343 22:55:55.165553 [Byte1]: 32
3344 22:55:55.165636
3345 22:55:55.165717 Set Vref, RX VrefLevel [Byte0]: 33
3346 22:55:55.165798 [Byte1]: 33
3347 22:55:55.165879
3348 22:55:55.165960 Set Vref, RX VrefLevel [Byte0]: 34
3349 22:55:55.166041 [Byte1]: 34
3350 22:55:55.166123
3351 22:55:55.166204 Set Vref, RX VrefLevel [Byte0]: 35
3352 22:55:55.166286 [Byte1]: 35
3353 22:55:55.166367
3354 22:55:55.166447 Set Vref, RX VrefLevel [Byte0]: 36
3355 22:55:55.166529 [Byte1]: 36
3356 22:55:55.166608
3357 22:55:55.166688 Set Vref, RX VrefLevel [Byte0]: 37
3358 22:55:55.166769 [Byte1]: 37
3359 22:55:55.166850
3360 22:55:55.166930 Set Vref, RX VrefLevel [Byte0]: 38
3361 22:55:55.167011 [Byte1]: 38
3362 22:55:55.167092
3363 22:55:55.167171 Set Vref, RX VrefLevel [Byte0]: 39
3364 22:55:55.167264 [Byte1]: 39
3365 22:55:55.167343
3366 22:55:55.167422 Set Vref, RX VrefLevel [Byte0]: 40
3367 22:55:55.167501 [Byte1]: 40
3368 22:55:55.167580
3369 22:55:55.167659 Set Vref, RX VrefLevel [Byte0]: 41
3370 22:55:55.167738 [Byte1]: 41
3371 22:55:55.167817
3372 22:55:55.167896 Set Vref, RX VrefLevel [Byte0]: 42
3373 22:55:55.167975 [Byte1]: 42
3374 22:55:55.168055
3375 22:55:55.168133 Set Vref, RX VrefLevel [Byte0]: 43
3376 22:55:55.168212 [Byte1]: 43
3377 22:55:55.168290
3378 22:55:55.168369 Set Vref, RX VrefLevel [Byte0]: 44
3379 22:55:55.168448 [Byte1]: 44
3380 22:55:55.168526
3381 22:55:55.168604 Set Vref, RX VrefLevel [Byte0]: 45
3382 22:55:55.168683 [Byte1]: 45
3383 22:55:55.168762
3384 22:55:55.168840 Set Vref, RX VrefLevel [Byte0]: 46
3385 22:55:55.168919 [Byte1]: 46
3386 22:55:55.168997
3387 22:55:55.169075 Set Vref, RX VrefLevel [Byte0]: 47
3388 22:55:55.169153 [Byte1]: 47
3389 22:55:55.169232
3390 22:55:55.169338 Set Vref, RX VrefLevel [Byte0]: 48
3391 22:55:55.169432 [Byte1]: 48
3392 22:55:55.169511
3393 22:55:55.169589 Set Vref, RX VrefLevel [Byte0]: 49
3394 22:55:55.169668 [Byte1]: 49
3395 22:55:55.169747
3396 22:55:55.169826 Set Vref, RX VrefLevel [Byte0]: 50
3397 22:55:55.169904 [Byte1]: 50
3398 22:55:55.169983
3399 22:55:55.170062 Set Vref, RX VrefLevel [Byte0]: 51
3400 22:55:55.170140 [Byte1]: 51
3401 22:55:55.170219
3402 22:55:55.170297 Set Vref, RX VrefLevel [Byte0]: 52
3403 22:55:55.170375 [Byte1]: 52
3404 22:55:55.170452
3405 22:55:55.170529 Set Vref, RX VrefLevel [Byte0]: 53
3406 22:55:55.170605 [Byte1]: 53
3407 22:55:55.170684
3408 22:55:55.170769 Set Vref, RX VrefLevel [Byte0]: 54
3409 22:55:55.170852 [Byte1]: 54
3410 22:55:55.170935
3411 22:55:55.171019 Set Vref, RX VrefLevel [Byte0]: 55
3412 22:55:55.171135 [Byte1]: 55
3413 22:55:55.171217
3414 22:55:55.171300 Set Vref, RX VrefLevel [Byte0]: 56
3415 22:55:55.171384 [Byte1]: 56
3416 22:55:55.171467
3417 22:55:55.171547 Set Vref, RX VrefLevel [Byte0]: 57
3418 22:55:55.171626 [Byte1]: 57
3419 22:55:55.171713
3420 22:55:55.171805 Set Vref, RX VrefLevel [Byte0]: 58
3421 22:55:55.171899 [Byte1]: 58
3422 22:55:55.171995
3423 22:55:55.172091 Set Vref, RX VrefLevel [Byte0]: 59
3424 22:55:55.172185 [Byte1]: 59
3425 22:55:55.172285
3426 22:55:55.172393 Set Vref, RX VrefLevel [Byte0]: 60
3427 22:55:55.172488 [Byte1]: 60
3428 22:55:55.172576
3429 22:55:55.172662 Set Vref, RX VrefLevel [Byte0]: 61
3430 22:55:55.172747 [Byte1]: 61
3431 22:55:55.172830
3432 22:55:55.172913 Set Vref, RX VrefLevel [Byte0]: 62
3433 22:55:55.172996 [Byte1]: 62
3434 22:55:55.173078
3435 22:55:55.173160 Set Vref, RX VrefLevel [Byte0]: 63
3436 22:55:55.173243 [Byte1]: 63
3437 22:55:55.173333
3438 22:55:55.173417 Set Vref, RX VrefLevel [Byte0]: 64
3439 22:55:55.173499 [Byte1]: 64
3440 22:55:55.173580
3441 22:55:55.173663 Set Vref, RX VrefLevel [Byte0]: 65
3442 22:55:55.173745 [Byte1]: 65
3443 22:55:55.173826
3444 22:55:55.173908 Set Vref, RX VrefLevel [Byte0]: 66
3445 22:55:55.173990 [Byte1]: 66
3446 22:55:55.174071
3447 22:55:55.174153 Set Vref, RX VrefLevel [Byte0]: 67
3448 22:55:55.174236 [Byte1]: 67
3449 22:55:55.174322
3450 22:55:55.174617 Set Vref, RX VrefLevel [Byte0]: 68
3451 22:55:55.174707 [Byte1]: 68
3452 22:55:55.174790
3453 22:55:55.174872 Final RX Vref Byte 0 = 50 to rank0
3454 22:55:55.174956 Final RX Vref Byte 1 = 53 to rank0
3455 22:55:55.175039 Final RX Vref Byte 0 = 50 to rank1
3456 22:55:55.175122 Final RX Vref Byte 1 = 53 to rank1==
3457 22:55:55.175204 Dram Type= 6, Freq= 0, CH_1, rank 0
3458 22:55:55.175287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 22:55:55.175370 ==
3460 22:55:55.175452 DQS Delay:
3461 22:55:55.175534 DQS0 = 0, DQS1 = 0
3462 22:55:55.175616 DQM Delay:
3463 22:55:55.175697 DQM0 = 119, DQM1 = 112
3464 22:55:55.175778 DQ Delay:
3465 22:55:55.175861 DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =116
3466 22:55:55.175943 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3467 22:55:55.176025 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3468 22:55:55.176106 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3469 22:55:55.176187
3470 22:55:55.176268
3471 22:55:55.176351 [DQSOSCAuto] RK0, (LSB)MR18= 0x61a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3472 22:55:55.176434 CH1 RK0: MR19=404, MR18=61A
3473 22:55:55.176517 CH1_RK0: MR19=0x404, MR18=0x61A, DQSOSC=400, MR23=63, INC=40, DEC=27
3474 22:55:55.176599
3475 22:55:55.176681 ----->DramcWriteLeveling(PI) begin...
3476 22:55:55.176754 ==
3477 22:55:55.176808 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 22:55:55.176861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 22:55:55.176914 ==
3480 22:55:55.176967 Write leveling (Byte 0): 25 => 25
3481 22:55:55.177019 Write leveling (Byte 1): 28 => 28
3482 22:55:55.177072 DramcWriteLeveling(PI) end<-----
3483 22:55:55.177124
3484 22:55:55.177176 ==
3485 22:55:55.177229 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 22:55:55.177281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 22:55:55.177374 ==
3488 22:55:55.177427 [Gating] SW mode calibration
3489 22:55:55.177480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3490 22:55:55.177533 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3491 22:55:55.177586 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 22:55:55.177639 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 22:55:55.177691 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 22:55:55.177744 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 22:55:55.177796 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 22:55:55.177848 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 22:55:55.177907 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (0 1) (0 0)
3498 22:55:55.177959 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3499 22:55:55.178011 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 22:55:55.178064 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 22:55:55.178116 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 22:55:55.178168 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 22:55:55.178220 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 22:55:55.178272 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 22:55:55.178324 1 0 24 | B1->B0 | 3837 2323 | 1 0 | (1 1) (0 0)
3506 22:55:55.178376 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3507 22:55:55.178428 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 22:55:55.178480 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 22:55:55.178532 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 22:55:55.178585 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 22:55:55.178637 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 22:55:55.178690 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 22:55:55.178742 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3514 22:55:55.178794 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3515 22:55:55.178847 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 22:55:55.178899 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 22:55:55.178951 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 22:55:55.179003 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 22:55:55.179055 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 22:55:55.179107 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 22:55:55.179158 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 22:55:55.179211 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 22:55:55.179262 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 22:55:55.179315 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 22:55:55.179367 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 22:55:55.179419 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 22:55:55.179471 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 22:55:55.179522 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 22:55:55.179575 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3530 22:55:55.179628 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 22:55:55.179680 Total UI for P1: 0, mck2ui 16
3532 22:55:55.179733 best dqsien dly found for B0: ( 1, 3, 24)
3533 22:55:55.179785 Total UI for P1: 0, mck2ui 16
3534 22:55:55.179837 best dqsien dly found for B1: ( 1, 3, 24)
3535 22:55:55.179889 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3536 22:55:55.179941 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3537 22:55:55.179993
3538 22:55:55.180044 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3539 22:55:55.180097 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3540 22:55:55.180149 [Gating] SW calibration Done
3541 22:55:55.180201 ==
3542 22:55:55.180253 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 22:55:55.180305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 22:55:55.180358 ==
3545 22:55:55.180410 RX Vref Scan: 0
3546 22:55:55.180462
3547 22:55:55.180513 RX Vref 0 -> 0, step: 1
3548 22:55:55.180565
3549 22:55:55.180617 RX Delay -40 -> 252, step: 8
3550 22:55:55.180669 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3551 22:55:55.180722 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3552 22:55:55.180774 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3553 22:55:55.180826 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3554 22:55:55.180878 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3555 22:55:55.180931 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3556 22:55:55.181184 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3557 22:55:55.181243 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3558 22:55:55.181303 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3559 22:55:55.181388 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3560 22:55:55.181441 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3561 22:55:55.181493 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3562 22:55:55.181546 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3563 22:55:55.181598 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3564 22:55:55.181650 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3565 22:55:55.181702 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3566 22:55:55.181754 ==
3567 22:55:55.181806 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 22:55:55.181859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 22:55:55.181911 ==
3570 22:55:55.181963 DQS Delay:
3571 22:55:55.182016 DQS0 = 0, DQS1 = 0
3572 22:55:55.182068 DQM Delay:
3573 22:55:55.182120 DQM0 = 119, DQM1 = 112
3574 22:55:55.182172 DQ Delay:
3575 22:55:55.182224 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3576 22:55:55.182276 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3577 22:55:55.182328 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3578 22:55:55.182379 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3579 22:55:55.182431
3580 22:55:55.182483
3581 22:55:55.182535 ==
3582 22:55:55.182587 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 22:55:55.182639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 22:55:55.182691 ==
3585 22:55:55.182743
3586 22:55:55.182795
3587 22:55:55.182847 TX Vref Scan disable
3588 22:55:55.182899 == TX Byte 0 ==
3589 22:55:55.182952 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3590 22:55:55.183004 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3591 22:55:55.183056 == TX Byte 1 ==
3592 22:55:55.183108 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3593 22:55:55.183160 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3594 22:55:55.183212 ==
3595 22:55:55.183264 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 22:55:55.183316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 22:55:55.183368 ==
3598 22:55:55.183419 TX Vref=22, minBit 0, minWin=25, winSum=412
3599 22:55:55.183472 TX Vref=24, minBit 1, minWin=25, winSum=421
3600 22:55:55.183524 TX Vref=26, minBit 0, minWin=26, winSum=423
3601 22:55:55.183577 TX Vref=28, minBit 1, minWin=26, winSum=426
3602 22:55:55.183629 TX Vref=30, minBit 1, minWin=26, winSum=426
3603 22:55:55.183681 TX Vref=32, minBit 0, minWin=26, winSum=427
3604 22:55:55.183734 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 32
3605 22:55:55.183786
3606 22:55:55.183837 Final TX Range 1 Vref 32
3607 22:55:55.183889
3608 22:55:55.183940 ==
3609 22:55:55.183992 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 22:55:55.184045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 22:55:55.184097 ==
3612 22:55:55.184150
3613 22:55:55.184201
3614 22:55:55.184253 TX Vref Scan disable
3615 22:55:55.184305 == TX Byte 0 ==
3616 22:55:55.184357 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3617 22:55:55.184409 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3618 22:55:55.184461 == TX Byte 1 ==
3619 22:55:55.184513 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3620 22:55:55.184566 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3621 22:55:55.184617
3622 22:55:55.184669 [DATLAT]
3623 22:55:55.184721 Freq=1200, CH1 RK1
3624 22:55:55.184774
3625 22:55:55.184826 DATLAT Default: 0xd
3626 22:55:55.184877 0, 0xFFFF, sum = 0
3627 22:55:55.184931 1, 0xFFFF, sum = 0
3628 22:55:55.184984 2, 0xFFFF, sum = 0
3629 22:55:55.185037 3, 0xFFFF, sum = 0
3630 22:55:55.185090 4, 0xFFFF, sum = 0
3631 22:55:55.185142 5, 0xFFFF, sum = 0
3632 22:55:55.185195 6, 0xFFFF, sum = 0
3633 22:55:55.185247 7, 0xFFFF, sum = 0
3634 22:55:55.185307 8, 0xFFFF, sum = 0
3635 22:55:55.185400 9, 0xFFFF, sum = 0
3636 22:55:55.185453 10, 0xFFFF, sum = 0
3637 22:55:55.185506 11, 0xFFFF, sum = 0
3638 22:55:55.185558 12, 0x0, sum = 1
3639 22:55:55.185610 13, 0x0, sum = 2
3640 22:55:55.185663 14, 0x0, sum = 3
3641 22:55:55.185715 15, 0x0, sum = 4
3642 22:55:55.185767 best_step = 13
3643 22:55:55.185819
3644 22:55:55.185871 ==
3645 22:55:55.185923 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 22:55:55.185975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 22:55:55.186027 ==
3648 22:55:55.186079 RX Vref Scan: 0
3649 22:55:55.186130
3650 22:55:55.186182 RX Vref 0 -> 0, step: 1
3651 22:55:55.186233
3652 22:55:55.186285 RX Delay -13 -> 252, step: 4
3653 22:55:55.186337 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3654 22:55:55.186390 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3655 22:55:55.186442 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3656 22:55:55.186495 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3657 22:55:55.186547 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3658 22:55:55.186599 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3659 22:55:55.186651 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3660 22:55:55.186703 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3661 22:55:55.186755 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3662 22:55:55.186807 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3663 22:55:55.186858 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3664 22:55:55.186910 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3665 22:55:55.186962 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3666 22:55:55.187014 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3667 22:55:55.187066 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3668 22:55:55.187117 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3669 22:55:55.187182 ==
3670 22:55:55.187240 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 22:55:55.187293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 22:55:55.187346 ==
3673 22:55:55.187398 DQS Delay:
3674 22:55:55.187450 DQS0 = 0, DQS1 = 0
3675 22:55:55.187502 DQM Delay:
3676 22:55:55.187553 DQM0 = 119, DQM1 = 113
3677 22:55:55.187604 DQ Delay:
3678 22:55:55.187656 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3679 22:55:55.187709 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3680 22:55:55.187762 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3681 22:55:55.187814 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3682 22:55:55.187866
3683 22:55:55.187918
3684 22:55:55.187970 [DQSOSCAuto] RK1, (LSB)MR18= 0xaef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3685 22:55:55.188023 CH1 RK1: MR19=403, MR18=AEF
3686 22:55:55.188075 CH1_RK1: MR19=0x403, MR18=0xAEF, DQSOSC=406, MR23=63, INC=39, DEC=26
3687 22:55:55.188128 [RxdqsGatingPostProcess] freq 1200
3688 22:55:55.188180 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3689 22:55:55.188232 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 22:55:55.188284 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 22:55:55.188337 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 22:55:55.188389 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 22:55:55.188440 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 22:55:55.188492 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 22:55:55.188747 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 22:55:55.188809 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 22:55:55.188862 Pre-setting of DQS Precalculation
3698 22:55:55.188915 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3699 22:55:55.188968 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3700 22:55:55.189022 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3701 22:55:55.189075
3702 22:55:55.189127
3703 22:55:55.189179 [Calibration Summary] 2400 Mbps
3704 22:55:55.189231 CH 0, Rank 0
3705 22:55:55.189283 SW Impedance : PASS
3706 22:55:55.189376 DUTY Scan : NO K
3707 22:55:55.189429 ZQ Calibration : PASS
3708 22:55:55.189481 Jitter Meter : NO K
3709 22:55:55.189533 CBT Training : PASS
3710 22:55:55.189585 Write leveling : PASS
3711 22:55:55.189637 RX DQS gating : PASS
3712 22:55:55.189689 RX DQ/DQS(RDDQC) : PASS
3713 22:55:55.189741 TX DQ/DQS : PASS
3714 22:55:55.189793 RX DATLAT : PASS
3715 22:55:55.189844 RX DQ/DQS(Engine): PASS
3716 22:55:55.189896 TX OE : NO K
3717 22:55:55.189949 All Pass.
3718 22:55:55.190000
3719 22:55:55.190052 CH 0, Rank 1
3720 22:55:55.190104 SW Impedance : PASS
3721 22:55:55.190156 DUTY Scan : NO K
3722 22:55:55.190208 ZQ Calibration : PASS
3723 22:55:55.190260 Jitter Meter : NO K
3724 22:55:55.190312 CBT Training : PASS
3725 22:55:55.190363 Write leveling : PASS
3726 22:55:55.190415 RX DQS gating : PASS
3727 22:55:55.190467 RX DQ/DQS(RDDQC) : PASS
3728 22:55:55.190519 TX DQ/DQS : PASS
3729 22:55:55.190571 RX DATLAT : PASS
3730 22:55:55.190623 RX DQ/DQS(Engine): PASS
3731 22:55:55.190674 TX OE : NO K
3732 22:55:55.190727 All Pass.
3733 22:55:55.190779
3734 22:55:55.190830 CH 1, Rank 0
3735 22:55:55.190882 SW Impedance : PASS
3736 22:55:55.190934 DUTY Scan : NO K
3737 22:55:55.190986 ZQ Calibration : PASS
3738 22:55:55.191038 Jitter Meter : NO K
3739 22:55:55.191090 CBT Training : PASS
3740 22:55:55.191142 Write leveling : PASS
3741 22:55:55.191194 RX DQS gating : PASS
3742 22:55:55.191245 RX DQ/DQS(RDDQC) : PASS
3743 22:55:55.191297 TX DQ/DQS : PASS
3744 22:55:55.191349 RX DATLAT : PASS
3745 22:55:55.191400 RX DQ/DQS(Engine): PASS
3746 22:55:55.191451 TX OE : NO K
3747 22:55:55.191502 All Pass.
3748 22:55:55.191554
3749 22:55:55.191605 CH 1, Rank 1
3750 22:55:55.191657 SW Impedance : PASS
3751 22:55:55.191708 DUTY Scan : NO K
3752 22:55:55.191761 ZQ Calibration : PASS
3753 22:55:55.191813 Jitter Meter : NO K
3754 22:55:55.191864 CBT Training : PASS
3755 22:55:55.191917 Write leveling : PASS
3756 22:55:55.191968 RX DQS gating : PASS
3757 22:55:55.192021 RX DQ/DQS(RDDQC) : PASS
3758 22:55:55.192072 TX DQ/DQS : PASS
3759 22:55:55.192124 RX DATLAT : PASS
3760 22:55:55.192176 RX DQ/DQS(Engine): PASS
3761 22:55:55.192228 TX OE : NO K
3762 22:55:55.192280 All Pass.
3763 22:55:55.192331
3764 22:55:55.192383 DramC Write-DBI off
3765 22:55:55.192434 PER_BANK_REFRESH: Hybrid Mode
3766 22:55:55.192486 TX_TRACKING: ON
3767 22:55:55.192538 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3768 22:55:55.192592 [FAST_K] Save calibration result to emmc
3769 22:55:55.192644 dramc_set_vcore_voltage set vcore to 650000
3770 22:55:55.192697 Read voltage for 600, 5
3771 22:55:55.192749 Vio18 = 0
3772 22:55:55.192800 Vcore = 650000
3773 22:55:55.192852 Vdram = 0
3774 22:55:55.192904 Vddq = 0
3775 22:55:55.192957 Vmddr = 0
3776 22:55:55.193009 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3777 22:55:55.193061 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3778 22:55:55.193113 MEM_TYPE=3, freq_sel=19
3779 22:55:55.193165 sv_algorithm_assistance_LP4_1600
3780 22:55:55.193218 ============ PULL DRAM RESETB DOWN ============
3781 22:55:55.193270 ========== PULL DRAM RESETB DOWN end =========
3782 22:55:55.193361 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3783 22:55:55.193429 ===================================
3784 22:55:55.193481 LPDDR4 DRAM CONFIGURATION
3785 22:55:55.193534 ===================================
3786 22:55:55.193586 EX_ROW_EN[0] = 0x0
3787 22:55:55.193638 EX_ROW_EN[1] = 0x0
3788 22:55:55.193690 LP4Y_EN = 0x0
3789 22:55:55.193742 WORK_FSP = 0x0
3790 22:55:55.193793 WL = 0x2
3791 22:55:55.193845 RL = 0x2
3792 22:55:55.193897 BL = 0x2
3793 22:55:55.193949 RPST = 0x0
3794 22:55:55.194000 RD_PRE = 0x0
3795 22:55:55.194052 WR_PRE = 0x1
3796 22:55:55.194103 WR_PST = 0x0
3797 22:55:55.194155 DBI_WR = 0x0
3798 22:55:55.194206 DBI_RD = 0x0
3799 22:55:55.194257 OTF = 0x1
3800 22:55:55.194310 ===================================
3801 22:55:55.194362 ===================================
3802 22:55:55.194413 ANA top config
3803 22:55:55.194465 ===================================
3804 22:55:55.194517 DLL_ASYNC_EN = 0
3805 22:55:55.194569 ALL_SLAVE_EN = 1
3806 22:55:55.194620 NEW_RANK_MODE = 1
3807 22:55:55.194673 DLL_IDLE_MODE = 1
3808 22:55:55.194725 LP45_APHY_COMB_EN = 1
3809 22:55:55.194777 TX_ODT_DIS = 1
3810 22:55:55.194829 NEW_8X_MODE = 1
3811 22:55:55.194882 ===================================
3812 22:55:55.194934 ===================================
3813 22:55:55.194987 data_rate = 1200
3814 22:55:55.195039 CKR = 1
3815 22:55:55.195091 DQ_P2S_RATIO = 8
3816 22:55:55.195143 ===================================
3817 22:55:55.195196 CA_P2S_RATIO = 8
3818 22:55:55.195247 DQ_CA_OPEN = 0
3819 22:55:55.195299 DQ_SEMI_OPEN = 0
3820 22:55:55.195351 CA_SEMI_OPEN = 0
3821 22:55:55.195403 CA_FULL_RATE = 0
3822 22:55:55.195455 DQ_CKDIV4_EN = 1
3823 22:55:55.195506 CA_CKDIV4_EN = 1
3824 22:55:55.195557 CA_PREDIV_EN = 0
3825 22:55:55.195609 PH8_DLY = 0
3826 22:55:55.195661 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3827 22:55:55.195713 DQ_AAMCK_DIV = 4
3828 22:55:55.195764 CA_AAMCK_DIV = 4
3829 22:55:55.195816 CA_ADMCK_DIV = 4
3830 22:55:55.195868 DQ_TRACK_CA_EN = 0
3831 22:55:55.195919 CA_PICK = 600
3832 22:55:55.195971 CA_MCKIO = 600
3833 22:55:55.196023 MCKIO_SEMI = 0
3834 22:55:55.196075 PLL_FREQ = 2288
3835 22:55:55.196126 DQ_UI_PI_RATIO = 32
3836 22:55:55.196178 CA_UI_PI_RATIO = 0
3837 22:55:55.196229 ===================================
3838 22:55:55.196298 ===================================
3839 22:55:55.196353 memory_type:LPDDR4
3840 22:55:55.196406 GP_NUM : 10
3841 22:55:55.197376 SRAM_EN : 1
3842 22:55:55.200737 MD32_EN : 0
3843 22:55:55.204293 ===================================
3844 22:55:55.204376 [ANA_INIT] >>>>>>>>>>>>>>
3845 22:55:55.207488 <<<<<< [CONFIGURE PHASE]: ANA_TX
3846 22:55:55.211150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3847 22:55:55.214197 ===================================
3848 22:55:55.217579 data_rate = 1200,PCW = 0X5800
3849 22:55:55.220955 ===================================
3850 22:55:55.224113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3851 22:55:55.230896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3852 22:55:55.234001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 22:55:55.240462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3854 22:55:55.244174 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3855 22:55:55.247340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3856 22:55:55.247431 [ANA_INIT] flow start
3857 22:55:55.250743 [ANA_INIT] PLL >>>>>>>>
3858 22:55:55.254068 [ANA_INIT] PLL <<<<<<<<
3859 22:55:55.257179 [ANA_INIT] MIDPI >>>>>>>>
3860 22:55:55.257276 [ANA_INIT] MIDPI <<<<<<<<
3861 22:55:55.260853 [ANA_INIT] DLL >>>>>>>>
3862 22:55:55.263755 [ANA_INIT] flow end
3863 22:55:55.267297 ============ LP4 DIFF to SE enter ============
3864 22:55:55.270315 ============ LP4 DIFF to SE exit ============
3865 22:55:55.273754 [ANA_INIT] <<<<<<<<<<<<<
3866 22:55:55.277160 [Flow] Enable top DCM control >>>>>
3867 22:55:55.280351 [Flow] Enable top DCM control <<<<<
3868 22:55:55.283891 Enable DLL master slave shuffle
3869 22:55:55.287381 ==============================================================
3870 22:55:55.290879 Gating Mode config
3871 22:55:55.294078 ==============================================================
3872 22:55:55.297130 Config description:
3873 22:55:55.307036 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3874 22:55:55.313894 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3875 22:55:55.316987 SELPH_MODE 0: By rank 1: By Phase
3876 22:55:55.323768 ==============================================================
3877 22:55:55.326960 GAT_TRACK_EN = 1
3878 22:55:55.330392 RX_GATING_MODE = 2
3879 22:55:55.333750 RX_GATING_TRACK_MODE = 2
3880 22:55:55.336842 SELPH_MODE = 1
3881 22:55:55.340500 PICG_EARLY_EN = 1
3882 22:55:55.340744 VALID_LAT_VALUE = 1
3883 22:55:55.347099 ==============================================================
3884 22:55:55.350464 Enter into Gating configuration >>>>
3885 22:55:55.353565 Exit from Gating configuration <<<<
3886 22:55:55.356946 Enter into DVFS_PRE_config >>>>>
3887 22:55:55.367008 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3888 22:55:55.370533 Exit from DVFS_PRE_config <<<<<
3889 22:55:55.373401 Enter into PICG configuration >>>>
3890 22:55:55.376751 Exit from PICG configuration <<<<
3891 22:55:55.380429 [RX_INPUT] configuration >>>>>
3892 22:55:55.383682 [RX_INPUT] configuration <<<<<
3893 22:55:55.386557 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3894 22:55:55.393689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3895 22:55:55.400085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3896 22:55:55.406373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3897 22:55:55.413581 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 22:55:55.420308 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 22:55:55.423280 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3900 22:55:55.426544 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3901 22:55:55.429684 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3902 22:55:55.436401 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3903 22:55:55.439845 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3904 22:55:55.443483 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 22:55:55.446352 ===================================
3906 22:55:55.449841 LPDDR4 DRAM CONFIGURATION
3907 22:55:55.453104 ===================================
3908 22:55:55.453196 EX_ROW_EN[0] = 0x0
3909 22:55:55.456228 EX_ROW_EN[1] = 0x0
3910 22:55:55.456361 LP4Y_EN = 0x0
3911 22:55:55.459893 WORK_FSP = 0x0
3912 22:55:55.459972 WL = 0x2
3913 22:55:55.463294 RL = 0x2
3914 22:55:55.466980 BL = 0x2
3915 22:55:55.467402 RPST = 0x0
3916 22:55:55.470166 RD_PRE = 0x0
3917 22:55:55.470589 WR_PRE = 0x1
3918 22:55:55.473133 WR_PST = 0x0
3919 22:55:55.473593 DBI_WR = 0x0
3920 22:55:55.476515 DBI_RD = 0x0
3921 22:55:55.476950 OTF = 0x1
3922 22:55:55.479861 ===================================
3923 22:55:55.483264 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3924 22:55:55.490070 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3925 22:55:55.493190 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 22:55:55.496531 ===================================
3927 22:55:55.499526 LPDDR4 DRAM CONFIGURATION
3928 22:55:55.503118 ===================================
3929 22:55:55.503306 EX_ROW_EN[0] = 0x10
3930 22:55:55.506730 EX_ROW_EN[1] = 0x0
3931 22:55:55.506916 LP4Y_EN = 0x0
3932 22:55:55.509818 WORK_FSP = 0x0
3933 22:55:55.509974 WL = 0x2
3934 22:55:55.513123 RL = 0x2
3935 22:55:55.513260 BL = 0x2
3936 22:55:55.516359 RPST = 0x0
3937 22:55:55.516495 RD_PRE = 0x0
3938 22:55:55.519465 WR_PRE = 0x1
3939 22:55:55.519602 WR_PST = 0x0
3940 22:55:55.523173 DBI_WR = 0x0
3941 22:55:55.526436 DBI_RD = 0x0
3942 22:55:55.526569 OTF = 0x1
3943 22:55:55.529599 ===================================
3944 22:55:55.536303 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3945 22:55:55.539920 nWR fixed to 30
3946 22:55:55.543001 [ModeRegInit_LP4] CH0 RK0
3947 22:55:55.543137 [ModeRegInit_LP4] CH0 RK1
3948 22:55:55.546190 [ModeRegInit_LP4] CH1 RK0
3949 22:55:55.549516 [ModeRegInit_LP4] CH1 RK1
3950 22:55:55.549650 match AC timing 17
3951 22:55:55.556225 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3952 22:55:55.560007 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3953 22:55:55.563304 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3954 22:55:55.570391 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3955 22:55:55.573072 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3956 22:55:55.573540 ==
3957 22:55:55.576642 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 22:55:55.579886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 22:55:55.580319 ==
3960 22:55:55.586619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 22:55:55.593182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3962 22:55:55.596590 [CA 0] Center 36 (6~67) winsize 62
3963 22:55:55.599697 [CA 1] Center 36 (6~67) winsize 62
3964 22:55:55.603021 [CA 2] Center 34 (4~65) winsize 62
3965 22:55:55.606324 [CA 3] Center 34 (3~65) winsize 63
3966 22:55:55.609325 [CA 4] Center 33 (3~64) winsize 62
3967 22:55:55.612864 [CA 5] Center 33 (2~64) winsize 63
3968 22:55:55.613023
3969 22:55:55.616117 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3970 22:55:55.616276
3971 22:55:55.619184 [CATrainingPosCal] consider 1 rank data
3972 22:55:55.622480 u2DelayCellTimex100 = 270/100 ps
3973 22:55:55.625558 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3974 22:55:55.629304 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3975 22:55:55.632554 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 22:55:55.635636 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3977 22:55:55.639338 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 22:55:55.645796 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3979 22:55:55.645943
3980 22:55:55.649101 CA PerBit enable=1, Macro0, CA PI delay=33
3981 22:55:55.649219
3982 22:55:55.652294 [CBTSetCACLKResult] CA Dly = 33
3983 22:55:55.652412 CS Dly: 4 (0~35)
3984 22:55:55.652506 ==
3985 22:55:55.655964 Dram Type= 6, Freq= 0, CH_0, rank 1
3986 22:55:55.658839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 22:55:55.662435 ==
3988 22:55:55.665792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 22:55:55.672582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3990 22:55:55.675790 [CA 0] Center 36 (6~67) winsize 62
3991 22:55:55.679003 [CA 1] Center 36 (6~67) winsize 62
3992 22:55:55.682491 [CA 2] Center 34 (4~65) winsize 62
3993 22:55:55.685739 [CA 3] Center 34 (4~65) winsize 62
3994 22:55:55.689114 [CA 4] Center 34 (3~65) winsize 63
3995 22:55:55.692821 [CA 5] Center 33 (3~64) winsize 62
3996 22:55:55.693253
3997 22:55:55.695833 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3998 22:55:55.696409
3999 22:55:55.699026 [CATrainingPosCal] consider 2 rank data
4000 22:55:55.702552 u2DelayCellTimex100 = 270/100 ps
4001 22:55:55.705932 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4002 22:55:55.709176 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4003 22:55:55.712509 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 22:55:55.719162 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4005 22:55:55.722662 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 22:55:55.725801 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 22:55:55.726224
4008 22:55:55.729399 CA PerBit enable=1, Macro0, CA PI delay=33
4009 22:55:55.729842
4010 22:55:55.732334 [CBTSetCACLKResult] CA Dly = 33
4011 22:55:55.732757 CS Dly: 5 (0~38)
4012 22:55:55.733097
4013 22:55:55.735961 ----->DramcWriteLeveling(PI) begin...
4014 22:55:55.736387 ==
4015 22:55:55.739065 Dram Type= 6, Freq= 0, CH_0, rank 0
4016 22:55:55.745662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 22:55:55.746089 ==
4018 22:55:55.748885 Write leveling (Byte 0): 35 => 35
4019 22:55:55.752619 Write leveling (Byte 1): 30 => 30
4020 22:55:55.753044 DramcWriteLeveling(PI) end<-----
4021 22:55:55.753413
4022 22:55:55.756008 ==
4023 22:55:55.759099 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 22:55:55.762388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 22:55:55.762815 ==
4026 22:55:55.766168 [Gating] SW mode calibration
4027 22:55:55.772586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4028 22:55:55.775993 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4029 22:55:55.782562 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 22:55:55.785524 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 22:55:55.789204 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 22:55:55.795709 0 9 12 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 0)
4033 22:55:55.798711 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
4034 22:55:55.802476 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 22:55:55.809018 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 22:55:55.812529 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 22:55:55.815758 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 22:55:55.822394 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 22:55:55.825530 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4040 22:55:55.828853 0 10 12 | B1->B0 | 2929 4040 | 0 1 | (1 1) (0 0)
4041 22:55:55.835673 0 10 16 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
4042 22:55:55.839043 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 22:55:55.842663 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 22:55:55.848985 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 22:55:55.852283 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 22:55:55.855197 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 22:55:55.858761 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 22:55:55.865517 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4049 22:55:55.869107 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4050 22:55:55.871813 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 22:55:55.878528 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 22:55:55.882049 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 22:55:55.885040 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 22:55:55.891508 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 22:55:55.895133 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 22:55:55.898327 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 22:55:55.905047 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 22:55:55.908200 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 22:55:55.911749 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 22:55:55.918330 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 22:55:55.921221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 22:55:55.924665 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 22:55:55.931164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 22:55:55.934643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4065 22:55:55.937632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 22:55:55.941400 Total UI for P1: 0, mck2ui 16
4067 22:55:55.944584 best dqsien dly found for B0: ( 0, 13, 12)
4068 22:55:55.947701 Total UI for P1: 0, mck2ui 16
4069 22:55:55.950972 best dqsien dly found for B1: ( 0, 13, 14)
4070 22:55:55.954574 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4071 22:55:55.960896 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4072 22:55:55.961353
4073 22:55:55.964432 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4074 22:55:55.967711 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4075 22:55:55.971414 [Gating] SW calibration Done
4076 22:55:55.971963 ==
4077 22:55:55.974496 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 22:55:55.977848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 22:55:55.978315 ==
4080 22:55:55.980747 RX Vref Scan: 0
4081 22:55:55.981171
4082 22:55:55.981531 RX Vref 0 -> 0, step: 1
4083 22:55:55.981845
4084 22:55:55.983922 RX Delay -230 -> 252, step: 16
4085 22:55:55.987503 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4086 22:55:55.994148 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4087 22:55:55.997663 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4088 22:55:56.000852 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4089 22:55:56.004466 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4090 22:55:56.010993 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4091 22:55:56.013995 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4092 22:55:56.017413 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4093 22:55:56.020686 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4094 22:55:56.024156 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4095 22:55:56.030685 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4096 22:55:56.034225 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4097 22:55:56.037125 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4098 22:55:56.040716 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4099 22:55:56.047069 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4100 22:55:56.050669 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4101 22:55:56.051103 ==
4102 22:55:56.053621 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 22:55:56.057208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 22:55:56.057790 ==
4105 22:55:56.060829 DQS Delay:
4106 22:55:56.061517 DQS0 = 0, DQS1 = 0
4107 22:55:56.062038 DQM Delay:
4108 22:55:56.064117 DQM0 = 53, DQM1 = 40
4109 22:55:56.064587 DQ Delay:
4110 22:55:56.066951 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4111 22:55:56.070794 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4112 22:55:56.073780 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =25
4113 22:55:56.077453 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4114 22:55:56.077883
4115 22:55:56.078219
4116 22:55:56.078588 ==
4117 22:55:56.080686 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 22:55:56.086986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 22:55:56.087423 ==
4120 22:55:56.087799
4121 22:55:56.088137
4122 22:55:56.088443 TX Vref Scan disable
4123 22:55:56.090597 == TX Byte 0 ==
4124 22:55:56.094227 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4125 22:55:56.101009 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4126 22:55:56.101539 == TX Byte 1 ==
4127 22:55:56.104089 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4128 22:55:56.110617 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4129 22:55:56.111182 ==
4130 22:55:56.113830 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 22:55:56.117282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 22:55:56.117835 ==
4133 22:55:56.118187
4134 22:55:56.118505
4135 22:55:56.120582 TX Vref Scan disable
4136 22:55:56.123928 == TX Byte 0 ==
4137 22:55:56.127405 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4138 22:55:56.130612 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4139 22:55:56.133929 == TX Byte 1 ==
4140 22:55:56.137542 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4141 22:55:56.140802 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4142 22:55:56.141338
4143 22:55:56.141698 [DATLAT]
4144 22:55:56.144101 Freq=600, CH0 RK0
4145 22:55:56.144637
4146 22:55:56.144980 DATLAT Default: 0x9
4147 22:55:56.147438 0, 0xFFFF, sum = 0
4148 22:55:56.150619 1, 0xFFFF, sum = 0
4149 22:55:56.151108 2, 0xFFFF, sum = 0
4150 22:55:56.154108 3, 0xFFFF, sum = 0
4151 22:55:56.154547 4, 0xFFFF, sum = 0
4152 22:55:56.157388 5, 0xFFFF, sum = 0
4153 22:55:56.157826 6, 0xFFFF, sum = 0
4154 22:55:56.160533 7, 0xFFFF, sum = 0
4155 22:55:56.160972 8, 0x0, sum = 1
4156 22:55:56.164316 9, 0x0, sum = 2
4157 22:55:56.164831 10, 0x0, sum = 3
4158 22:55:56.165181 11, 0x0, sum = 4
4159 22:55:56.167267 best_step = 9
4160 22:55:56.167697
4161 22:55:56.168034 ==
4162 22:55:56.170495 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 22:55:56.173596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 22:55:56.174030 ==
4165 22:55:56.177340 RX Vref Scan: 1
4166 22:55:56.177873
4167 22:55:56.178217 RX Vref 0 -> 0, step: 1
4168 22:55:56.178560
4169 22:55:56.180272 RX Delay -179 -> 252, step: 8
4170 22:55:56.180704
4171 22:55:56.184196 Set Vref, RX VrefLevel [Byte0]: 58
4172 22:55:56.187443 [Byte1]: 50
4173 22:55:56.191376
4174 22:55:56.191910 Final RX Vref Byte 0 = 58 to rank0
4175 22:55:56.195319 Final RX Vref Byte 1 = 50 to rank0
4176 22:55:56.198172 Final RX Vref Byte 0 = 58 to rank1
4177 22:55:56.201266 Final RX Vref Byte 1 = 50 to rank1==
4178 22:55:56.204725 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 22:55:56.211374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 22:55:56.211896 ==
4181 22:55:56.212240 DQS Delay:
4182 22:55:56.212559 DQS0 = 0, DQS1 = 0
4183 22:55:56.214465 DQM Delay:
4184 22:55:56.214895 DQM0 = 50, DQM1 = 37
4185 22:55:56.217621 DQ Delay:
4186 22:55:56.221194 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =44
4187 22:55:56.224500 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4188 22:55:56.228232 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4189 22:55:56.231093 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4190 22:55:56.231552
4191 22:55:56.231901
4192 22:55:56.238117 [DQSOSCAuto] RK0, (LSB)MR18= 0x6059, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
4193 22:55:56.241180 CH0 RK0: MR19=808, MR18=6059
4194 22:55:56.248097 CH0_RK0: MR19=0x808, MR18=0x6059, DQSOSC=391, MR23=63, INC=171, DEC=114
4195 22:55:56.248645
4196 22:55:56.251220 ----->DramcWriteLeveling(PI) begin...
4197 22:55:56.251719 ==
4198 22:55:56.254569 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 22:55:56.257954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 22:55:56.258484 ==
4201 22:55:56.261195 Write leveling (Byte 0): 36 => 36
4202 22:55:56.264494 Write leveling (Byte 1): 32 => 32
4203 22:55:56.267921 DramcWriteLeveling(PI) end<-----
4204 22:55:56.268452
4205 22:55:56.268899 ==
4206 22:55:56.271468 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 22:55:56.274819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 22:55:56.275351 ==
4209 22:55:56.277826 [Gating] SW mode calibration
4210 22:55:56.284501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4211 22:55:56.291164 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4212 22:55:56.294744 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 22:55:56.297802 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 22:55:56.305131 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 22:55:56.308016 0 9 12 | B1->B0 | 3232 3131 | 0 1 | (0 0) (1 1)
4216 22:55:56.311394 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4217 22:55:56.317707 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 22:55:56.321185 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 22:55:56.324211 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 22:55:56.331287 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 22:55:56.334298 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 22:55:56.337817 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 22:55:56.344704 0 10 12 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
4224 22:55:56.347323 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4225 22:55:56.350576 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 22:55:56.357704 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 22:55:56.360655 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 22:55:56.364033 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 22:55:56.370558 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 22:55:56.373867 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 22:55:56.377443 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4232 22:55:56.383494 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 22:55:56.387375 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 22:55:56.390417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 22:55:56.396820 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 22:55:56.400171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 22:55:56.403526 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 22:55:56.410253 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 22:55:56.413465 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 22:55:56.416915 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 22:55:56.423260 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 22:55:56.426645 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 22:55:56.430474 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 22:55:56.436988 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 22:55:56.440397 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 22:55:56.443518 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4247 22:55:56.450219 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4248 22:55:56.453447 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 22:55:56.456333 Total UI for P1: 0, mck2ui 16
4250 22:55:56.459825 best dqsien dly found for B0: ( 0, 13, 12)
4251 22:55:56.463370 Total UI for P1: 0, mck2ui 16
4252 22:55:56.466809 best dqsien dly found for B1: ( 0, 13, 10)
4253 22:55:56.469902 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4254 22:55:56.473336 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4255 22:55:56.473767
4256 22:55:56.476333 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4257 22:55:56.479561 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4258 22:55:56.482769 [Gating] SW calibration Done
4259 22:55:56.483201 ==
4260 22:55:56.486257 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 22:55:56.489666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 22:55:56.493044 ==
4263 22:55:56.493501 RX Vref Scan: 0
4264 22:55:56.493841
4265 22:55:56.496611 RX Vref 0 -> 0, step: 1
4266 22:55:56.497133
4267 22:55:56.499842 RX Delay -230 -> 252, step: 16
4268 22:55:56.503175 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4269 22:55:56.506018 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4270 22:55:56.509836 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4271 22:55:56.516178 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4272 22:55:56.519246 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4273 22:55:56.522547 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4274 22:55:56.526379 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4275 22:55:56.529667 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4276 22:55:56.535996 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4277 22:55:56.539185 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4278 22:55:56.542436 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4279 22:55:56.545954 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4280 22:55:56.552820 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4281 22:55:56.555939 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4282 22:55:56.559162 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4283 22:55:56.562663 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4284 22:55:56.563237 ==
4285 22:55:56.565850 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 22:55:56.572802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 22:55:56.573411 ==
4288 22:55:56.573907 DQS Delay:
4289 22:55:56.575757 DQS0 = 0, DQS1 = 0
4290 22:55:56.576233 DQM Delay:
4291 22:55:56.576604 DQM0 = 48, DQM1 = 42
4292 22:55:56.578923 DQ Delay:
4293 22:55:56.582393 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4294 22:55:56.585650 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4295 22:55:56.589114 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4296 22:55:56.592387 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4297 22:55:56.592818
4298 22:55:56.593251
4299 22:55:56.593639 ==
4300 22:55:56.596017 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 22:55:56.599051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 22:55:56.599486 ==
4303 22:55:56.599844
4304 22:55:56.600157
4305 22:55:56.602417 TX Vref Scan disable
4306 22:55:56.605953 == TX Byte 0 ==
4307 22:55:56.608995 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4308 22:55:56.612112 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4309 22:55:56.615501 == TX Byte 1 ==
4310 22:55:56.618802 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4311 22:55:56.622094 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4312 22:55:56.622580 ==
4313 22:55:56.625416 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 22:55:56.628774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 22:55:56.632208 ==
4316 22:55:56.632854
4317 22:55:56.633421
4318 22:55:56.633764 TX Vref Scan disable
4319 22:55:56.636047 == TX Byte 0 ==
4320 22:55:56.639659 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4321 22:55:56.646069 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4322 22:55:56.646505 == TX Byte 1 ==
4323 22:55:56.649184 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4324 22:55:56.656027 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4325 22:55:56.656545
4326 22:55:56.656888 [DATLAT]
4327 22:55:56.657206 Freq=600, CH0 RK1
4328 22:55:56.657605
4329 22:55:56.659137 DATLAT Default: 0x9
4330 22:55:56.659566 0, 0xFFFF, sum = 0
4331 22:55:56.662815 1, 0xFFFF, sum = 0
4332 22:55:56.663241 2, 0xFFFF, sum = 0
4333 22:55:56.665849 3, 0xFFFF, sum = 0
4334 22:55:56.669344 4, 0xFFFF, sum = 0
4335 22:55:56.669876 5, 0xFFFF, sum = 0
4336 22:55:56.672349 6, 0xFFFF, sum = 0
4337 22:55:56.672775 7, 0xFFFF, sum = 0
4338 22:55:56.675598 8, 0x0, sum = 1
4339 22:55:56.676023 9, 0x0, sum = 2
4340 22:55:56.676361 10, 0x0, sum = 3
4341 22:55:56.679208 11, 0x0, sum = 4
4342 22:55:56.679637 best_step = 9
4343 22:55:56.679971
4344 22:55:56.680278 ==
4345 22:55:56.682413 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 22:55:56.688906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 22:55:56.689355 ==
4348 22:55:56.689693 RX Vref Scan: 0
4349 22:55:56.690001
4350 22:55:56.692145 RX Vref 0 -> 0, step: 1
4351 22:55:56.692564
4352 22:55:56.695797 RX Delay -179 -> 252, step: 8
4353 22:55:56.699078 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4354 22:55:56.705800 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4355 22:55:56.709278 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4356 22:55:56.712725 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4357 22:55:56.715636 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4358 22:55:56.719173 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4359 22:55:56.725821 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4360 22:55:56.729344 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4361 22:55:56.732425 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4362 22:55:56.736004 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4363 22:55:56.739444 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4364 22:55:56.745890 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4365 22:55:56.749499 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4366 22:55:56.753052 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4367 22:55:56.756069 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4368 22:55:56.762504 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4369 22:55:56.763060 ==
4370 22:55:56.766069 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 22:55:56.769203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 22:55:56.769790 ==
4373 22:55:56.770159 DQS Delay:
4374 22:55:56.772439 DQS0 = 0, DQS1 = 0
4375 22:55:56.772903 DQM Delay:
4376 22:55:56.778613 DQM0 = 48, DQM1 = 41
4377 22:55:56.779079 DQ Delay:
4378 22:55:56.779772 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4379 22:55:56.782636 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4380 22:55:56.785821 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4381 22:55:56.788920 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4382 22:55:56.789381
4383 22:55:56.789723
4384 22:55:56.796697 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4385 22:55:56.798718 CH0 RK1: MR19=808, MR18=6A37
4386 22:55:56.805431 CH0_RK1: MR19=0x808, MR18=0x6A37, DQSOSC=389, MR23=63, INC=173, DEC=115
4387 22:55:56.808834 [RxdqsGatingPostProcess] freq 600
4388 22:55:56.815708 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4389 22:55:56.818677 Pre-setting of DQS Precalculation
4390 22:55:56.822156 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4391 22:55:56.822701 ==
4392 22:55:56.825357 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 22:55:56.828986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 22:55:56.829542 ==
4395 22:55:56.835621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4396 22:55:56.842190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4397 22:55:56.845583 [CA 0] Center 35 (5~66) winsize 62
4398 22:55:56.849036 [CA 1] Center 35 (5~66) winsize 62
4399 22:55:56.852238 [CA 2] Center 34 (4~65) winsize 62
4400 22:55:56.855788 [CA 3] Center 33 (3~64) winsize 62
4401 22:55:56.859099 [CA 4] Center 33 (3~64) winsize 62
4402 22:55:56.862314 [CA 5] Center 33 (3~64) winsize 62
4403 22:55:56.862781
4404 22:55:56.865541 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4405 22:55:56.866100
4406 22:55:56.869157 [CATrainingPosCal] consider 1 rank data
4407 22:55:56.872393 u2DelayCellTimex100 = 270/100 ps
4408 22:55:56.875076 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4409 22:55:56.878688 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4410 22:55:56.882265 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 22:55:56.885401 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 22:55:56.888542 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4413 22:55:56.891791 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 22:55:56.895150
4415 22:55:56.898475 CA PerBit enable=1, Macro0, CA PI delay=33
4416 22:55:56.898895
4417 22:55:56.901788 [CBTSetCACLKResult] CA Dly = 33
4418 22:55:56.902211 CS Dly: 4 (0~35)
4419 22:55:56.902540 ==
4420 22:55:56.905082 Dram Type= 6, Freq= 0, CH_1, rank 1
4421 22:55:56.908589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 22:55:56.909152 ==
4423 22:55:56.915018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4424 22:55:56.921622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4425 22:55:56.925197 [CA 0] Center 35 (5~66) winsize 62
4426 22:55:56.928685 [CA 1] Center 35 (5~66) winsize 62
4427 22:55:56.931820 [CA 2] Center 34 (4~65) winsize 62
4428 22:55:56.935591 [CA 3] Center 34 (4~64) winsize 61
4429 22:55:56.938489 [CA 4] Center 34 (4~64) winsize 61
4430 22:55:56.941713 [CA 5] Center 33 (3~64) winsize 62
4431 22:55:56.942141
4432 22:55:56.945244 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4433 22:55:56.945800
4434 22:55:56.948755 [CATrainingPosCal] consider 2 rank data
4435 22:55:56.952055 u2DelayCellTimex100 = 270/100 ps
4436 22:55:56.955018 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4437 22:55:56.958247 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4438 22:55:56.961753 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4439 22:55:56.964936 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4440 22:55:56.968162 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4441 22:55:56.975153 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 22:55:56.975726
4443 22:55:56.978181 CA PerBit enable=1, Macro0, CA PI delay=33
4444 22:55:56.978686
4445 22:55:56.981401 [CBTSetCACLKResult] CA Dly = 33
4446 22:55:56.981833 CS Dly: 4 (0~36)
4447 22:55:56.982172
4448 22:55:56.984975 ----->DramcWriteLeveling(PI) begin...
4449 22:55:56.985549 ==
4450 22:55:56.988212 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 22:55:56.991626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 22:55:56.994825 ==
4453 22:55:56.998449 Write leveling (Byte 0): 30 => 30
4454 22:55:56.998883 Write leveling (Byte 1): 31 => 31
4455 22:55:57.001641 DramcWriteLeveling(PI) end<-----
4456 22:55:57.002088
4457 22:55:57.002508 ==
4458 22:55:57.005158 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 22:55:57.011690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 22:55:57.012207 ==
4461 22:55:57.014783 [Gating] SW mode calibration
4462 22:55:57.021528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4463 22:55:57.024973 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4464 22:55:57.031865 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4465 22:55:57.034746 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4466 22:55:57.038038 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (0 1) (0 1)
4467 22:55:57.045186 0 9 12 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
4468 22:55:57.048164 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 22:55:57.051591 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 22:55:57.058618 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 22:55:57.061055 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 22:55:57.065031 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 22:55:57.068311 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 22:55:57.074957 0 10 8 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (0 0)
4475 22:55:57.078025 0 10 12 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
4476 22:55:57.081293 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 22:55:57.087826 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 22:55:57.091696 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 22:55:57.094600 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 22:55:57.101276 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 22:55:57.104572 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 22:55:57.108052 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4483 22:55:57.114378 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4484 22:55:57.117743 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 22:55:57.121084 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 22:55:57.127693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 22:55:57.130926 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 22:55:57.134195 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 22:55:57.140703 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 22:55:57.144069 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 22:55:57.147253 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 22:55:57.154236 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 22:55:57.158032 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 22:55:57.160958 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 22:55:57.167634 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 22:55:57.171084 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 22:55:57.173753 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 22:55:57.180306 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 22:55:57.183478 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4500 22:55:57.187074 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 22:55:57.190345 Total UI for P1: 0, mck2ui 16
4502 22:55:57.193647 best dqsien dly found for B0: ( 0, 13, 12)
4503 22:55:57.196946 Total UI for P1: 0, mck2ui 16
4504 22:55:57.200457 best dqsien dly found for B1: ( 0, 13, 12)
4505 22:55:57.203304 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4506 22:55:57.206867 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4507 22:55:57.210066
4508 22:55:57.213681 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4509 22:55:57.216680 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4510 22:55:57.220140 [Gating] SW calibration Done
4511 22:55:57.220619 ==
4512 22:55:57.223340 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 22:55:57.226747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 22:55:57.227360 ==
4515 22:55:57.227745 RX Vref Scan: 0
4516 22:55:57.228099
4517 22:55:57.230116 RX Vref 0 -> 0, step: 1
4518 22:55:57.230591
4519 22:55:57.233423 RX Delay -230 -> 252, step: 16
4520 22:55:57.236512 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4521 22:55:57.243328 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4522 22:55:57.246600 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4523 22:55:57.250080 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4524 22:55:57.253270 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4525 22:55:57.256515 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4526 22:55:57.263511 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4527 22:55:57.266568 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4528 22:55:57.269909 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4529 22:55:57.273273 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4530 22:55:57.276973 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4531 22:55:57.283315 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4532 22:55:57.286104 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4533 22:55:57.290112 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4534 22:55:57.292786 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4535 22:55:57.299877 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4536 22:55:57.300392 ==
4537 22:55:57.303198 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 22:55:57.306650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 22:55:57.307175 ==
4540 22:55:57.307517 DQS Delay:
4541 22:55:57.309800 DQS0 = 0, DQS1 = 0
4542 22:55:57.310323 DQM Delay:
4543 22:55:57.313001 DQM0 = 54, DQM1 = 45
4544 22:55:57.313618 DQ Delay:
4545 22:55:57.315997 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4546 22:55:57.319465 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4547 22:55:57.322915 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4548 22:55:57.326188 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4549 22:55:57.326621
4550 22:55:57.326959
4551 22:55:57.327349 ==
4552 22:55:57.329525 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 22:55:57.333228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 22:55:57.333699 ==
4555 22:55:57.336117
4556 22:55:57.336543
4557 22:55:57.336881 TX Vref Scan disable
4558 22:55:57.339664 == TX Byte 0 ==
4559 22:55:57.343096 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4560 22:55:57.346458 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4561 22:55:57.349672 == TX Byte 1 ==
4562 22:55:57.353464 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4563 22:55:57.356283 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4564 22:55:57.356806 ==
4565 22:55:57.359723 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 22:55:57.366320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 22:55:57.366831 ==
4568 22:55:57.367173
4569 22:55:57.367488
4570 22:55:57.367790 TX Vref Scan disable
4571 22:55:57.370777 == TX Byte 0 ==
4572 22:55:57.374648 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4573 22:55:57.380903 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4574 22:55:57.381470 == TX Byte 1 ==
4575 22:55:57.384438 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4576 22:55:57.390818 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4577 22:55:57.391354
4578 22:55:57.391699 [DATLAT]
4579 22:55:57.392013 Freq=600, CH1 RK0
4580 22:55:57.392321
4581 22:55:57.393944 DATLAT Default: 0x9
4582 22:55:57.394376 0, 0xFFFF, sum = 0
4583 22:55:57.397898 1, 0xFFFF, sum = 0
4584 22:55:57.398471 2, 0xFFFF, sum = 0
4585 22:55:57.400935 3, 0xFFFF, sum = 0
4586 22:55:57.401491 4, 0xFFFF, sum = 0
4587 22:55:57.403859 5, 0xFFFF, sum = 0
4588 22:55:57.407492 6, 0xFFFF, sum = 0
4589 22:55:57.408033 7, 0xFFFF, sum = 0
4590 22:55:57.408391 8, 0x0, sum = 1
4591 22:55:57.410848 9, 0x0, sum = 2
4592 22:55:57.411381 10, 0x0, sum = 3
4593 22:55:57.413946 11, 0x0, sum = 4
4594 22:55:57.414385 best_step = 9
4595 22:55:57.414725
4596 22:55:57.415035 ==
4597 22:55:57.417593 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 22:55:57.423927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 22:55:57.424361 ==
4600 22:55:57.424706 RX Vref Scan: 1
4601 22:55:57.425021
4602 22:55:57.427440 RX Vref 0 -> 0, step: 1
4603 22:55:57.427870
4604 22:55:57.430846 RX Delay -163 -> 252, step: 8
4605 22:55:57.431277
4606 22:55:57.434151 Set Vref, RX VrefLevel [Byte0]: 50
4607 22:55:57.437328 [Byte1]: 53
4608 22:55:57.437756
4609 22:55:57.440650 Final RX Vref Byte 0 = 50 to rank0
4610 22:55:57.444538 Final RX Vref Byte 1 = 53 to rank0
4611 22:55:57.447933 Final RX Vref Byte 0 = 50 to rank1
4612 22:55:57.451054 Final RX Vref Byte 1 = 53 to rank1==
4613 22:55:57.454309 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 22:55:57.457705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 22:55:57.458182 ==
4616 22:55:57.461030 DQS Delay:
4617 22:55:57.461524 DQS0 = 0, DQS1 = 0
4618 22:55:57.461900 DQM Delay:
4619 22:55:57.464455 DQM0 = 49, DQM1 = 40
4620 22:55:57.465023 DQ Delay:
4621 22:55:57.467692 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =48
4622 22:55:57.470876 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4623 22:55:57.474000 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4624 22:55:57.477511 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4625 22:55:57.478074
4626 22:55:57.478446
4627 22:55:57.487799 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4628 22:55:57.488368 CH1 RK0: MR19=808, MR18=4A71
4629 22:55:57.493911 CH1_RK0: MR19=0x808, MR18=0x4A71, DQSOSC=388, MR23=63, INC=174, DEC=116
4630 22:55:57.494482
4631 22:55:57.497351 ----->DramcWriteLeveling(PI) begin...
4632 22:55:57.500588 ==
4633 22:55:57.503492 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 22:55:57.507306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 22:55:57.507890 ==
4636 22:55:57.510616 Write leveling (Byte 0): 27 => 27
4637 22:55:57.513899 Write leveling (Byte 1): 27 => 27
4638 22:55:57.516936 DramcWriteLeveling(PI) end<-----
4639 22:55:57.517440
4640 22:55:57.517818 ==
4641 22:55:57.520486 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 22:55:57.523541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 22:55:57.524035 ==
4644 22:55:57.526818 [Gating] SW mode calibration
4645 22:55:57.533701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4646 22:55:57.540281 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4647 22:55:57.543528 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4648 22:55:57.546729 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4649 22:55:57.553332 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4650 22:55:57.556904 0 9 12 | B1->B0 | 2d2d 3232 | 1 1 | (1 0) (0 1)
4651 22:55:57.560136 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 22:55:57.563722 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 22:55:57.570116 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 22:55:57.573665 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 22:55:57.576699 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 22:55:57.583693 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 22:55:57.586632 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4658 22:55:57.590214 0 10 12 | B1->B0 | 4343 3333 | 0 0 | (0 0) (0 0)
4659 22:55:57.596928 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 22:55:57.600021 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 22:55:57.603309 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 22:55:57.609944 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 22:55:57.613218 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 22:55:57.616282 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 22:55:57.623431 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4666 22:55:57.626113 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4667 22:55:57.629583 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 22:55:57.636263 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 22:55:57.639247 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 22:55:57.643097 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 22:55:57.649961 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 22:55:57.653070 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 22:55:57.655964 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 22:55:57.662678 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 22:55:57.666548 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 22:55:57.669139 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 22:55:57.675973 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 22:55:57.679315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 22:55:57.682633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 22:55:57.689418 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 22:55:57.692345 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 22:55:57.695660 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4683 22:55:57.702234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 22:55:57.702839 Total UI for P1: 0, mck2ui 16
4685 22:55:57.708914 best dqsien dly found for B0: ( 0, 13, 12)
4686 22:55:57.709536 Total UI for P1: 0, mck2ui 16
4687 22:55:57.715545 best dqsien dly found for B1: ( 0, 13, 12)
4688 22:55:57.718761 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4689 22:55:57.721974 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4690 22:55:57.722485
4691 22:55:57.725492 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4692 22:55:57.729028 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4693 22:55:57.732149 [Gating] SW calibration Done
4694 22:55:57.732714 ==
4695 22:55:57.735581 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 22:55:57.738651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 22:55:57.739172 ==
4698 22:55:57.741917 RX Vref Scan: 0
4699 22:55:57.742391
4700 22:55:57.742765 RX Vref 0 -> 0, step: 1
4701 22:55:57.743116
4702 22:55:57.745289 RX Delay -230 -> 252, step: 16
4703 22:55:57.752114 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4704 22:55:57.755450 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4705 22:55:57.758758 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4706 22:55:57.762228 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4707 22:55:57.765618 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4708 22:55:57.772307 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4709 22:55:57.775930 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4710 22:55:57.778619 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4711 22:55:57.782097 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4712 22:55:57.788816 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4713 22:55:57.791939 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4714 22:55:57.795605 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4715 22:55:57.798832 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4716 22:55:57.805426 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4717 22:55:57.808880 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4718 22:55:57.812005 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4719 22:55:57.812570 ==
4720 22:55:57.815011 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 22:55:57.818334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 22:55:57.818809 ==
4723 22:55:57.822134 DQS Delay:
4724 22:55:57.822724 DQS0 = 0, DQS1 = 0
4725 22:55:57.824903 DQM Delay:
4726 22:55:57.825402 DQM0 = 49, DQM1 = 46
4727 22:55:57.825777 DQ Delay:
4728 22:55:57.828285 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4729 22:55:57.831909 DQ4 =49, DQ5 =57, DQ6 =49, DQ7 =49
4730 22:55:57.835132 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4731 22:55:57.838202 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4732 22:55:57.838674
4733 22:55:57.839041
4734 22:55:57.841863 ==
4735 22:55:57.842333 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 22:55:57.848209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 22:55:57.848685 ==
4738 22:55:57.849060
4739 22:55:57.849448
4740 22:55:57.851381 TX Vref Scan disable
4741 22:55:57.851848 == TX Byte 0 ==
4742 22:55:57.855113 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4743 22:55:57.861746 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4744 22:55:57.862275 == TX Byte 1 ==
4745 22:55:57.864762 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4746 22:55:57.871812 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4747 22:55:57.872337 ==
4748 22:55:57.875166 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 22:55:57.878155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 22:55:57.878677 ==
4751 22:55:57.879014
4752 22:55:57.879325
4753 22:55:57.881466 TX Vref Scan disable
4754 22:55:57.885357 == TX Byte 0 ==
4755 22:55:57.888392 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4756 22:55:57.891362 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4757 22:55:57.894881 == TX Byte 1 ==
4758 22:55:57.898009 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4759 22:55:57.901847 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4760 22:55:57.902420
4761 22:55:57.904659 [DATLAT]
4762 22:55:57.905121 Freq=600, CH1 RK1
4763 22:55:57.905551
4764 22:55:57.907980 DATLAT Default: 0x9
4765 22:55:57.908445 0, 0xFFFF, sum = 0
4766 22:55:57.911442 1, 0xFFFF, sum = 0
4767 22:55:57.912015 2, 0xFFFF, sum = 0
4768 22:55:57.914560 3, 0xFFFF, sum = 0
4769 22:55:57.915034 4, 0xFFFF, sum = 0
4770 22:55:57.918013 5, 0xFFFF, sum = 0
4771 22:55:57.918488 6, 0xFFFF, sum = 0
4772 22:55:57.921362 7, 0xFFFF, sum = 0
4773 22:55:57.921947 8, 0x0, sum = 1
4774 22:55:57.924956 9, 0x0, sum = 2
4775 22:55:57.925563 10, 0x0, sum = 3
4776 22:55:57.928036 11, 0x0, sum = 4
4777 22:55:57.928515 best_step = 9
4778 22:55:57.928882
4779 22:55:57.929222 ==
4780 22:55:57.931340 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 22:55:57.934667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 22:55:57.935146 ==
4783 22:55:57.937792 RX Vref Scan: 0
4784 22:55:57.938263
4785 22:55:57.941349 RX Vref 0 -> 0, step: 1
4786 22:55:57.941826
4787 22:55:57.942197 RX Delay -163 -> 252, step: 8
4788 22:55:57.949557 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4789 22:55:57.952496 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4790 22:55:57.956478 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4791 22:55:57.959611 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4792 22:55:57.962807 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4793 22:55:57.969602 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4794 22:55:57.972886 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4795 22:55:57.976241 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4796 22:55:57.979532 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4797 22:55:57.982706 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4798 22:55:57.989481 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4799 22:55:57.992624 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4800 22:55:57.995709 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4801 22:55:57.999154 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4802 22:55:58.005618 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4803 22:55:58.009065 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4804 22:55:58.009586 ==
4805 22:55:58.012378 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 22:55:58.015721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 22:55:58.016376 ==
4808 22:55:58.019000 DQS Delay:
4809 22:55:58.019497 DQS0 = 0, DQS1 = 0
4810 22:55:58.019884 DQM Delay:
4811 22:55:58.022511 DQM0 = 49, DQM1 = 44
4812 22:55:58.022999 DQ Delay:
4813 22:55:58.025360 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4814 22:55:58.028885 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4815 22:55:58.032393 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4816 22:55:58.035470 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =56
4817 22:55:58.035891
4818 22:55:58.036220
4819 22:55:58.045526 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
4820 22:55:58.046076 CH1 RK1: MR19=808, MR18=5E25
4821 22:55:58.052545 CH1_RK1: MR19=0x808, MR18=0x5E25, DQSOSC=392, MR23=63, INC=170, DEC=113
4822 22:55:58.055906 [RxdqsGatingPostProcess] freq 600
4823 22:55:58.062701 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4824 22:55:58.065629 Pre-setting of DQS Precalculation
4825 22:55:58.069135 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4826 22:55:58.075686 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4827 22:55:58.085649 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4828 22:55:58.086219
4829 22:55:58.086594
4830 22:55:58.088743 [Calibration Summary] 1200 Mbps
4831 22:55:58.089336 CH 0, Rank 0
4832 22:55:58.092268 SW Impedance : PASS
4833 22:55:58.092841 DUTY Scan : NO K
4834 22:55:58.095410 ZQ Calibration : PASS
4835 22:55:58.098618 Jitter Meter : NO K
4836 22:55:58.099212 CBT Training : PASS
4837 22:55:58.102240 Write leveling : PASS
4838 22:55:58.102802 RX DQS gating : PASS
4839 22:55:58.105245 RX DQ/DQS(RDDQC) : PASS
4840 22:55:58.108773 TX DQ/DQS : PASS
4841 22:55:58.109379 RX DATLAT : PASS
4842 22:55:58.112159 RX DQ/DQS(Engine): PASS
4843 22:55:58.115280 TX OE : NO K
4844 22:55:58.115858 All Pass.
4845 22:55:58.116275
4846 22:55:58.116670 CH 0, Rank 1
4847 22:55:58.118321 SW Impedance : PASS
4848 22:55:58.121995 DUTY Scan : NO K
4849 22:55:58.122562 ZQ Calibration : PASS
4850 22:55:58.125124 Jitter Meter : NO K
4851 22:55:58.128300 CBT Training : PASS
4852 22:55:58.128778 Write leveling : PASS
4853 22:55:58.131509 RX DQS gating : PASS
4854 22:55:58.134612 RX DQ/DQS(RDDQC) : PASS
4855 22:55:58.135088 TX DQ/DQS : PASS
4856 22:55:58.138182 RX DATLAT : PASS
4857 22:55:58.141626 RX DQ/DQS(Engine): PASS
4858 22:55:58.142106 TX OE : NO K
4859 22:55:58.145017 All Pass.
4860 22:55:58.145615
4861 22:55:58.145990 CH 1, Rank 0
4862 22:55:58.148256 SW Impedance : PASS
4863 22:55:58.148835 DUTY Scan : NO K
4864 22:55:58.151380 ZQ Calibration : PASS
4865 22:55:58.154796 Jitter Meter : NO K
4866 22:55:58.155273 CBT Training : PASS
4867 22:55:58.158122 Write leveling : PASS
4868 22:55:58.161408 RX DQS gating : PASS
4869 22:55:58.161969 RX DQ/DQS(RDDQC) : PASS
4870 22:55:58.164750 TX DQ/DQS : PASS
4871 22:55:58.165521 RX DATLAT : PASS
4872 22:55:58.168361 RX DQ/DQS(Engine): PASS
4873 22:55:58.171443 TX OE : NO K
4874 22:55:58.172006 All Pass.
4875 22:55:58.172384
4876 22:55:58.172730 CH 1, Rank 1
4877 22:55:58.174915 SW Impedance : PASS
4878 22:55:58.177931 DUTY Scan : NO K
4879 22:55:58.178406 ZQ Calibration : PASS
4880 22:55:58.181892 Jitter Meter : NO K
4881 22:55:58.185043 CBT Training : PASS
4882 22:55:58.185661 Write leveling : PASS
4883 22:55:58.188333 RX DQS gating : PASS
4884 22:55:58.191608 RX DQ/DQS(RDDQC) : PASS
4885 22:55:58.192179 TX DQ/DQS : PASS
4886 22:55:58.194920 RX DATLAT : PASS
4887 22:55:58.198355 RX DQ/DQS(Engine): PASS
4888 22:55:58.198921 TX OE : NO K
4889 22:55:58.201359 All Pass.
4890 22:55:58.201925
4891 22:55:58.202301 DramC Write-DBI off
4892 22:55:58.204894 PER_BANK_REFRESH: Hybrid Mode
4893 22:55:58.205506 TX_TRACKING: ON
4894 22:55:58.214655 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4895 22:55:58.217828 [FAST_K] Save calibration result to emmc
4896 22:55:58.221366 dramc_set_vcore_voltage set vcore to 662500
4897 22:55:58.224691 Read voltage for 933, 3
4898 22:55:58.225256 Vio18 = 0
4899 22:55:58.227738 Vcore = 662500
4900 22:55:58.228381 Vdram = 0
4901 22:55:58.228772 Vddq = 0
4902 22:55:58.229209 Vmddr = 0
4903 22:55:58.234823 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4904 22:55:58.240988 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4905 22:55:58.241492 MEM_TYPE=3, freq_sel=17
4906 22:55:58.244362 sv_algorithm_assistance_LP4_1600
4907 22:55:58.248025 ============ PULL DRAM RESETB DOWN ============
4908 22:55:58.254750 ========== PULL DRAM RESETB DOWN end =========
4909 22:55:58.257834 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4910 22:55:58.261631 ===================================
4911 22:55:58.264636 LPDDR4 DRAM CONFIGURATION
4912 22:55:58.267723 ===================================
4913 22:55:58.268292 EX_ROW_EN[0] = 0x0
4914 22:55:58.271640 EX_ROW_EN[1] = 0x0
4915 22:55:58.272207 LP4Y_EN = 0x0
4916 22:55:58.274525 WORK_FSP = 0x0
4917 22:55:58.275088 WL = 0x3
4918 22:55:58.277669 RL = 0x3
4919 22:55:58.281042 BL = 0x2
4920 22:55:58.281560 RPST = 0x0
4921 22:55:58.284252 RD_PRE = 0x0
4922 22:55:58.284719 WR_PRE = 0x1
4923 22:55:58.287746 WR_PST = 0x0
4924 22:55:58.288310 DBI_WR = 0x0
4925 22:55:58.290967 DBI_RD = 0x0
4926 22:55:58.291432 OTF = 0x1
4927 22:55:58.294231 ===================================
4928 22:55:58.297937 ===================================
4929 22:55:58.301318 ANA top config
4930 22:55:58.301892 ===================================
4931 22:55:58.304298 DLL_ASYNC_EN = 0
4932 22:55:58.308317 ALL_SLAVE_EN = 1
4933 22:55:58.311722 NEW_RANK_MODE = 1
4934 22:55:58.314567 DLL_IDLE_MODE = 1
4935 22:55:58.315132 LP45_APHY_COMB_EN = 1
4936 22:55:58.318061 TX_ODT_DIS = 1
4937 22:55:58.321019 NEW_8X_MODE = 1
4938 22:55:58.324341 ===================================
4939 22:55:58.327837 ===================================
4940 22:55:58.331003 data_rate = 1866
4941 22:55:58.334160 CKR = 1
4942 22:55:58.334627 DQ_P2S_RATIO = 8
4943 22:55:58.337658 ===================================
4944 22:55:58.340920 CA_P2S_RATIO = 8
4945 22:55:58.344638 DQ_CA_OPEN = 0
4946 22:55:58.347687 DQ_SEMI_OPEN = 0
4947 22:55:58.350933 CA_SEMI_OPEN = 0
4948 22:55:58.354318 CA_FULL_RATE = 0
4949 22:55:58.354788 DQ_CKDIV4_EN = 1
4950 22:55:58.357603 CA_CKDIV4_EN = 1
4951 22:55:58.360677 CA_PREDIV_EN = 0
4952 22:55:58.364011 PH8_DLY = 0
4953 22:55:58.367645 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4954 22:55:58.371111 DQ_AAMCK_DIV = 4
4955 22:55:58.371714 CA_AAMCK_DIV = 4
4956 22:55:58.374456 CA_ADMCK_DIV = 4
4957 22:55:58.378003 DQ_TRACK_CA_EN = 0
4958 22:55:58.381457 CA_PICK = 933
4959 22:55:58.384582 CA_MCKIO = 933
4960 22:55:58.387844 MCKIO_SEMI = 0
4961 22:55:58.388315 PLL_FREQ = 3732
4962 22:55:58.391126 DQ_UI_PI_RATIO = 32
4963 22:55:58.394080 CA_UI_PI_RATIO = 0
4964 22:55:58.397903 ===================================
4965 22:55:58.401145 ===================================
4966 22:55:58.404497 memory_type:LPDDR4
4967 22:55:58.407967 GP_NUM : 10
4968 22:55:58.408532 SRAM_EN : 1
4969 22:55:58.411049 MD32_EN : 0
4970 22:55:58.414608 ===================================
4971 22:55:58.415177 [ANA_INIT] >>>>>>>>>>>>>>
4972 22:55:58.417397 <<<<<< [CONFIGURE PHASE]: ANA_TX
4973 22:55:58.421083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4974 22:55:58.424552 ===================================
4975 22:55:58.427348 data_rate = 1866,PCW = 0X8f00
4976 22:55:58.430718 ===================================
4977 22:55:58.434128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4978 22:55:58.440816 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4979 22:55:58.447471 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4980 22:55:58.451170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4981 22:55:58.453981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4982 22:55:58.457714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4983 22:55:58.460762 [ANA_INIT] flow start
4984 22:55:58.461358 [ANA_INIT] PLL >>>>>>>>
4985 22:55:58.464423 [ANA_INIT] PLL <<<<<<<<
4986 22:55:58.467609 [ANA_INIT] MIDPI >>>>>>>>
4987 22:55:58.468180 [ANA_INIT] MIDPI <<<<<<<<
4988 22:55:58.470967 [ANA_INIT] DLL >>>>>>>>
4989 22:55:58.473971 [ANA_INIT] flow end
4990 22:55:58.477477 ============ LP4 DIFF to SE enter ============
4991 22:55:58.480798 ============ LP4 DIFF to SE exit ============
4992 22:55:58.484086 [ANA_INIT] <<<<<<<<<<<<<
4993 22:55:58.487388 [Flow] Enable top DCM control >>>>>
4994 22:55:58.490697 [Flow] Enable top DCM control <<<<<
4995 22:55:58.494563 Enable DLL master slave shuffle
4996 22:55:58.497782 ==============================================================
4997 22:55:58.501187 Gating Mode config
4998 22:55:58.507831 ==============================================================
4999 22:55:58.508402 Config description:
5000 22:55:58.517413 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5001 22:55:58.524322 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5002 22:55:58.527370 SELPH_MODE 0: By rank 1: By Phase
5003 22:55:58.534045 ==============================================================
5004 22:55:58.537089 GAT_TRACK_EN = 1
5005 22:55:58.540596 RX_GATING_MODE = 2
5006 22:55:58.543838 RX_GATING_TRACK_MODE = 2
5007 22:55:58.547345 SELPH_MODE = 1
5008 22:55:58.550304 PICG_EARLY_EN = 1
5009 22:55:58.553999 VALID_LAT_VALUE = 1
5010 22:55:58.556938 ==============================================================
5011 22:55:58.560301 Enter into Gating configuration >>>>
5012 22:55:58.563819 Exit from Gating configuration <<<<
5013 22:55:58.567140 Enter into DVFS_PRE_config >>>>>
5014 22:55:58.580138 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5015 22:55:58.580701 Exit from DVFS_PRE_config <<<<<
5016 22:55:58.583512 Enter into PICG configuration >>>>
5017 22:55:58.587020 Exit from PICG configuration <<<<
5018 22:55:58.590179 [RX_INPUT] configuration >>>>>
5019 22:55:58.593497 [RX_INPUT] configuration <<<<<
5020 22:55:58.600111 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5021 22:55:58.603427 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5022 22:55:58.610208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5023 22:55:58.616714 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5024 22:55:58.623800 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 22:55:58.630174 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 22:55:58.633289 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5027 22:55:58.636714 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5028 22:55:58.640068 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5029 22:55:58.647135 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5030 22:55:58.649905 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5031 22:55:58.653594 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 22:55:58.656843 ===================================
5033 22:55:58.660324 LPDDR4 DRAM CONFIGURATION
5034 22:55:58.663276 ===================================
5035 22:55:58.663745 EX_ROW_EN[0] = 0x0
5036 22:55:58.666508 EX_ROW_EN[1] = 0x0
5037 22:55:58.670036 LP4Y_EN = 0x0
5038 22:55:58.670506 WORK_FSP = 0x0
5039 22:55:58.673504 WL = 0x3
5040 22:55:58.674198 RL = 0x3
5041 22:55:58.676552 BL = 0x2
5042 22:55:58.677117 RPST = 0x0
5043 22:55:58.679947 RD_PRE = 0x0
5044 22:55:58.680414 WR_PRE = 0x1
5045 22:55:58.683071 WR_PST = 0x0
5046 22:55:58.683576 DBI_WR = 0x0
5047 22:55:58.686263 DBI_RD = 0x0
5048 22:55:58.686728 OTF = 0x1
5049 22:55:58.689739 ===================================
5050 22:55:58.693345 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5051 22:55:58.699507 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5052 22:55:58.703090 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5053 22:55:58.706246 ===================================
5054 22:55:58.710123 LPDDR4 DRAM CONFIGURATION
5055 22:55:58.713198 ===================================
5056 22:55:58.713799 EX_ROW_EN[0] = 0x10
5057 22:55:58.716364 EX_ROW_EN[1] = 0x0
5058 22:55:58.719402 LP4Y_EN = 0x0
5059 22:55:58.719868 WORK_FSP = 0x0
5060 22:55:58.723273 WL = 0x3
5061 22:55:58.723838 RL = 0x3
5062 22:55:58.726606 BL = 0x2
5063 22:55:58.727173 RPST = 0x0
5064 22:55:58.729626 RD_PRE = 0x0
5065 22:55:58.730094 WR_PRE = 0x1
5066 22:55:58.732954 WR_PST = 0x0
5067 22:55:58.733446 DBI_WR = 0x0
5068 22:55:58.736799 DBI_RD = 0x0
5069 22:55:58.737428 OTF = 0x1
5070 22:55:58.740090 ===================================
5071 22:55:58.746642 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5072 22:55:58.750245 nWR fixed to 30
5073 22:55:58.753375 [ModeRegInit_LP4] CH0 RK0
5074 22:55:58.753841 [ModeRegInit_LP4] CH0 RK1
5075 22:55:58.756878 [ModeRegInit_LP4] CH1 RK0
5076 22:55:58.760165 [ModeRegInit_LP4] CH1 RK1
5077 22:55:58.760728 match AC timing 9
5078 22:55:58.766614 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5079 22:55:58.769918 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5080 22:55:58.773193 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5081 22:55:58.780006 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5082 22:55:58.783430 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5083 22:55:58.783900 ==
5084 22:55:58.787050 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 22:55:58.790279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5086 22:55:58.790751 ==
5087 22:55:58.796782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5088 22:55:58.803640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5089 22:55:58.806957 [CA 0] Center 38 (7~69) winsize 63
5090 22:55:58.810465 [CA 1] Center 38 (7~69) winsize 63
5091 22:55:58.813770 [CA 2] Center 35 (5~66) winsize 62
5092 22:55:58.817065 [CA 3] Center 34 (4~65) winsize 62
5093 22:55:58.820017 [CA 4] Center 34 (4~65) winsize 62
5094 22:55:58.823671 [CA 5] Center 33 (3~64) winsize 62
5095 22:55:58.824235
5096 22:55:58.826463 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5097 22:55:58.826932
5098 22:55:58.829876 [CATrainingPosCal] consider 1 rank data
5099 22:55:58.833586 u2DelayCellTimex100 = 270/100 ps
5100 22:55:58.836774 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5101 22:55:58.840489 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5102 22:55:58.843488 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5103 22:55:58.846628 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5104 22:55:58.850064 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5105 22:55:58.853911 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5106 22:55:58.854479
5107 22:55:58.859768 CA PerBit enable=1, Macro0, CA PI delay=33
5108 22:55:58.860334
5109 22:55:58.863548 [CBTSetCACLKResult] CA Dly = 33
5110 22:55:58.864126 CS Dly: 6 (0~37)
5111 22:55:58.864498 ==
5112 22:55:58.866536 Dram Type= 6, Freq= 0, CH_0, rank 1
5113 22:55:58.869675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 22:55:58.870142 ==
5115 22:55:58.876888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5116 22:55:58.883213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5117 22:55:58.886744 [CA 0] Center 38 (8~69) winsize 62
5118 22:55:58.889817 [CA 1] Center 38 (8~69) winsize 62
5119 22:55:58.893416 [CA 2] Center 36 (6~66) winsize 61
5120 22:55:58.896594 [CA 3] Center 35 (5~66) winsize 62
5121 22:55:58.899975 [CA 4] Center 34 (4~65) winsize 62
5122 22:55:58.903783 [CA 5] Center 34 (4~65) winsize 62
5123 22:55:58.904354
5124 22:55:58.906890 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5125 22:55:58.907362
5126 22:55:58.909910 [CATrainingPosCal] consider 2 rank data
5127 22:55:58.913280 u2DelayCellTimex100 = 270/100 ps
5128 22:55:58.916321 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5129 22:55:58.919352 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5130 22:55:58.923078 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5131 22:55:58.926442 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5132 22:55:58.929813 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5133 22:55:58.936614 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5134 22:55:58.937190
5135 22:55:58.939786 CA PerBit enable=1, Macro0, CA PI delay=34
5136 22:55:58.940356
5137 22:55:58.943031 [CBTSetCACLKResult] CA Dly = 34
5138 22:55:58.943588 CS Dly: 7 (0~39)
5139 22:55:58.943961
5140 22:55:58.946607 ----->DramcWriteLeveling(PI) begin...
5141 22:55:58.947171 ==
5142 22:55:58.949569 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 22:55:58.952915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 22:55:58.956309 ==
5145 22:55:58.956869 Write leveling (Byte 0): 30 => 30
5146 22:55:58.959789 Write leveling (Byte 1): 30 => 30
5147 22:55:58.963467 DramcWriteLeveling(PI) end<-----
5148 22:55:58.964025
5149 22:55:58.964395 ==
5150 22:55:58.966069 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 22:55:58.973043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 22:55:58.973645 ==
5153 22:55:58.976258 [Gating] SW mode calibration
5154 22:55:58.982632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5155 22:55:58.986392 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5156 22:55:58.993070 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5157 22:55:58.996052 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 22:55:58.999530 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 22:55:59.006271 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 22:55:59.009553 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 22:55:59.012934 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 22:55:59.019019 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
5163 22:55:59.022768 0 14 28 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
5164 22:55:59.026245 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
5165 22:55:59.029766 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 22:55:59.035953 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 22:55:59.039017 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 22:55:59.042521 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 22:55:59.048989 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 22:55:59.052384 0 15 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5171 22:55:59.055871 0 15 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
5172 22:55:59.062193 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 22:55:59.065709 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 22:55:59.069185 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 22:55:59.075785 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 22:55:59.079266 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 22:55:59.082251 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 22:55:59.088968 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5179 22:55:59.092645 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5180 22:55:59.095305 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 22:55:59.102003 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 22:55:59.105442 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 22:55:59.109202 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 22:55:59.115772 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 22:55:59.118752 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 22:55:59.122358 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 22:55:59.129044 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 22:55:59.132200 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 22:55:59.135024 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 22:55:59.142197 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 22:55:59.145214 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 22:55:59.148773 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 22:55:59.155395 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5194 22:55:59.158316 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5195 22:55:59.161904 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5196 22:55:59.165108 Total UI for P1: 0, mck2ui 16
5197 22:55:59.168554 best dqsien dly found for B0: ( 1, 2, 22)
5198 22:55:59.175057 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 22:55:59.175620 Total UI for P1: 0, mck2ui 16
5200 22:55:59.178546 best dqsien dly found for B1: ( 1, 2, 28)
5201 22:55:59.185341 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5202 22:55:59.188371 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5203 22:55:59.188967
5204 22:55:59.191531 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5205 22:55:59.195072 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5206 22:55:59.198275 [Gating] SW calibration Done
5207 22:55:59.198749 ==
5208 22:55:59.201911 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 22:55:59.205200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 22:55:59.205842 ==
5211 22:55:59.208431 RX Vref Scan: 0
5212 22:55:59.208899
5213 22:55:59.209267 RX Vref 0 -> 0, step: 1
5214 22:55:59.209645
5215 22:55:59.211552 RX Delay -80 -> 252, step: 8
5216 22:55:59.215080 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5217 22:55:59.221620 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5218 22:55:59.224710 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5219 22:55:59.228308 iDelay=208, Bit 3, Center 107 (24 ~ 191) 168
5220 22:55:59.231673 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5221 22:55:59.234528 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5222 22:55:59.238171 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5223 22:55:59.245015 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5224 22:55:59.248577 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5225 22:55:59.251842 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5226 22:55:59.254729 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5227 22:55:59.257915 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5228 22:55:59.261617 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5229 22:55:59.268280 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5230 22:55:59.271604 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5231 22:55:59.275053 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5232 22:55:59.275616 ==
5233 22:55:59.278240 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 22:55:59.281421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 22:55:59.281986 ==
5236 22:55:59.284884 DQS Delay:
5237 22:55:59.285481 DQS0 = 0, DQS1 = 0
5238 22:55:59.288047 DQM Delay:
5239 22:55:59.288610 DQM0 = 108, DQM1 = 90
5240 22:55:59.288983 DQ Delay:
5241 22:55:59.291448 DQ0 =107, DQ1 =111, DQ2 =103, DQ3 =107
5242 22:55:59.294650 DQ4 =111, DQ5 =99, DQ6 =115, DQ7 =115
5243 22:55:59.297980 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87
5244 22:55:59.304823 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5245 22:55:59.305450
5246 22:55:59.305940
5247 22:55:59.306388 ==
5248 22:55:59.307893 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 22:55:59.311165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 22:55:59.311641 ==
5251 22:55:59.312014
5252 22:55:59.312356
5253 22:55:59.314771 TX Vref Scan disable
5254 22:55:59.315335 == TX Byte 0 ==
5255 22:55:59.321265 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5256 22:55:59.324598 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5257 22:55:59.325069 == TX Byte 1 ==
5258 22:55:59.331016 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5259 22:55:59.334303 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5260 22:55:59.334780 ==
5261 22:55:59.337644 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 22:55:59.341183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 22:55:59.341805 ==
5264 22:55:59.342187
5265 22:55:59.342555
5266 22:55:59.344115 TX Vref Scan disable
5267 22:55:59.347735 == TX Byte 0 ==
5268 22:55:59.351019 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5269 22:55:59.353998 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5270 22:55:59.358111 == TX Byte 1 ==
5271 22:55:59.360887 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5272 22:55:59.364750 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5273 22:55:59.365351
5274 22:55:59.368130 [DATLAT]
5275 22:55:59.368695 Freq=933, CH0 RK0
5276 22:55:59.369068
5277 22:55:59.371163 DATLAT Default: 0xd
5278 22:55:59.371733 0, 0xFFFF, sum = 0
5279 22:55:59.374637 1, 0xFFFF, sum = 0
5280 22:55:59.375219 2, 0xFFFF, sum = 0
5281 22:55:59.377607 3, 0xFFFF, sum = 0
5282 22:55:59.378186 4, 0xFFFF, sum = 0
5283 22:55:59.380919 5, 0xFFFF, sum = 0
5284 22:55:59.381537 6, 0xFFFF, sum = 0
5285 22:55:59.384514 7, 0xFFFF, sum = 0
5286 22:55:59.385095 8, 0xFFFF, sum = 0
5287 22:55:59.387738 9, 0xFFFF, sum = 0
5288 22:55:59.388315 10, 0x0, sum = 1
5289 22:55:59.391054 11, 0x0, sum = 2
5290 22:55:59.391642 12, 0x0, sum = 3
5291 22:55:59.394405 13, 0x0, sum = 4
5292 22:55:59.394987 best_step = 11
5293 22:55:59.395360
5294 22:55:59.395700 ==
5295 22:55:59.397457 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 22:55:59.404194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 22:55:59.404831 ==
5298 22:55:59.405207 RX Vref Scan: 1
5299 22:55:59.405646
5300 22:55:59.407420 RX Vref 0 -> 0, step: 1
5301 22:55:59.407885
5302 22:55:59.410620 RX Delay -53 -> 252, step: 4
5303 22:55:59.411106
5304 22:55:59.414056 Set Vref, RX VrefLevel [Byte0]: 58
5305 22:55:59.417414 [Byte1]: 50
5306 22:55:59.417882
5307 22:55:59.420580 Final RX Vref Byte 0 = 58 to rank0
5308 22:55:59.424220 Final RX Vref Byte 1 = 50 to rank0
5309 22:55:59.427459 Final RX Vref Byte 0 = 58 to rank1
5310 22:55:59.430841 Final RX Vref Byte 1 = 50 to rank1==
5311 22:55:59.434109 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 22:55:59.437689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 22:55:59.438166 ==
5314 22:55:59.440776 DQS Delay:
5315 22:55:59.441248 DQS0 = 0, DQS1 = 0
5316 22:55:59.441663 DQM Delay:
5317 22:55:59.444098 DQM0 = 107, DQM1 = 92
5318 22:55:59.444571 DQ Delay:
5319 22:55:59.447638 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5320 22:55:59.450719 DQ4 =106, DQ5 =98, DQ6 =118, DQ7 =116
5321 22:55:59.453980 DQ8 =88, DQ9 =78, DQ10 =92, DQ11 =90
5322 22:55:59.457548 DQ12 =94, DQ13 =92, DQ14 =102, DQ15 =100
5323 22:55:59.460773
5324 22:55:59.461444
5325 22:55:59.467343 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5326 22:55:59.470647 CH0 RK0: MR19=505, MR18=2622
5327 22:55:59.477228 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5328 22:55:59.477842
5329 22:55:59.480607 ----->DramcWriteLeveling(PI) begin...
5330 22:55:59.481214 ==
5331 22:55:59.483832 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 22:55:59.487083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 22:55:59.487549 ==
5334 22:55:59.490209 Write leveling (Byte 0): 30 => 30
5335 22:55:59.493503 Write leveling (Byte 1): 29 => 29
5336 22:55:59.497438 DramcWriteLeveling(PI) end<-----
5337 22:55:59.498007
5338 22:55:59.498378 ==
5339 22:55:59.500703 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 22:55:59.503656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 22:55:59.504274 ==
5342 22:55:59.506870 [Gating] SW mode calibration
5343 22:55:59.513876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5344 22:55:59.520418 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5345 22:55:59.524035 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 22:55:59.527179 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 22:55:59.534198 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 22:55:59.537152 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 22:55:59.540289 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 22:55:59.546756 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 22:55:59.550020 0 14 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
5352 22:55:59.553662 0 14 28 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (0 0)
5353 22:55:59.560060 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 22:55:59.563681 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 22:55:59.567089 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 22:55:59.573581 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 22:55:59.577058 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 22:55:59.580234 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 22:55:59.586990 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5360 22:55:59.590567 0 15 28 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
5361 22:55:59.593237 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 22:55:59.600545 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 22:55:59.603660 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 22:55:59.606543 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 22:55:59.613671 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 22:55:59.616797 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 22:55:59.620529 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 22:55:59.623668 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5369 22:55:59.630332 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 22:55:59.633457 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 22:55:59.636493 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 22:55:59.643270 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 22:55:59.646560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 22:55:59.650114 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 22:55:59.656659 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 22:55:59.659898 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 22:55:59.663193 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 22:55:59.670206 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 22:55:59.673255 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 22:55:59.676786 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 22:55:59.683500 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 22:55:59.686839 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 22:55:59.690058 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 22:55:59.696699 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5385 22:55:59.699952 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 22:55:59.703319 Total UI for P1: 0, mck2ui 16
5387 22:55:59.706193 best dqsien dly found for B0: ( 1, 2, 28)
5388 22:55:59.709666 Total UI for P1: 0, mck2ui 16
5389 22:55:59.712918 best dqsien dly found for B1: ( 1, 2, 28)
5390 22:55:59.716684 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5391 22:55:59.719430 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5392 22:55:59.719985
5393 22:55:59.722868 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5394 22:55:59.726192 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5395 22:55:59.729491 [Gating] SW calibration Done
5396 22:55:59.730035 ==
5397 22:55:59.732733 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 22:55:59.739308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 22:55:59.739902 ==
5400 22:55:59.740273 RX Vref Scan: 0
5401 22:55:59.740608
5402 22:55:59.743256 RX Vref 0 -> 0, step: 1
5403 22:55:59.743727
5404 22:55:59.745988 RX Delay -80 -> 252, step: 8
5405 22:55:59.748951 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5406 22:55:59.752536 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5407 22:55:59.756045 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5408 22:55:59.759251 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5409 22:55:59.766029 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5410 22:55:59.769525 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5411 22:55:59.772267 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5412 22:55:59.775628 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5413 22:55:59.779153 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5414 22:55:59.782247 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5415 22:55:59.789523 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5416 22:55:59.792946 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5417 22:55:59.795652 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5418 22:55:59.799028 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5419 22:55:59.802693 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5420 22:55:59.806020 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5421 22:55:59.809194 ==
5422 22:55:59.809800 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 22:55:59.815588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 22:55:59.816221 ==
5425 22:55:59.816608 DQS Delay:
5426 22:55:59.818924 DQS0 = 0, DQS1 = 0
5427 22:55:59.819487 DQM Delay:
5428 22:55:59.822033 DQM0 = 104, DQM1 = 91
5429 22:55:59.822503 DQ Delay:
5430 22:55:59.825555 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5431 22:55:59.828703 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5432 22:55:59.831978 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5433 22:55:59.835471 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5434 22:55:59.836116
5435 22:55:59.836496
5436 22:55:59.836846 ==
5437 22:55:59.838753 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 22:55:59.842112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 22:55:59.842588 ==
5440 22:55:59.842970
5441 22:55:59.845467
5442 22:55:59.845937 TX Vref Scan disable
5443 22:55:59.848647 == TX Byte 0 ==
5444 22:55:59.852039 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5445 22:55:59.855314 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5446 22:55:59.858497 == TX Byte 1 ==
5447 22:55:59.861600 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5448 22:55:59.864889 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5449 22:55:59.865402 ==
5450 22:55:59.868506 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 22:55:59.874740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 22:55:59.875216 ==
5453 22:55:59.875590
5454 22:55:59.875931
5455 22:55:59.876262 TX Vref Scan disable
5456 22:55:59.879403 == TX Byte 0 ==
5457 22:55:59.882384 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5458 22:55:59.889285 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5459 22:55:59.889871 == TX Byte 1 ==
5460 22:55:59.892596 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5461 22:55:59.899499 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5462 22:55:59.900065
5463 22:55:59.900439 [DATLAT]
5464 22:55:59.900782 Freq=933, CH0 RK1
5465 22:55:59.901112
5466 22:55:59.902366 DATLAT Default: 0xb
5467 22:55:59.902831 0, 0xFFFF, sum = 0
5468 22:55:59.905877 1, 0xFFFF, sum = 0
5469 22:55:59.906350 2, 0xFFFF, sum = 0
5470 22:55:59.909135 3, 0xFFFF, sum = 0
5471 22:55:59.912707 4, 0xFFFF, sum = 0
5472 22:55:59.913278 5, 0xFFFF, sum = 0
5473 22:55:59.916095 6, 0xFFFF, sum = 0
5474 22:55:59.916663 7, 0xFFFF, sum = 0
5475 22:55:59.918802 8, 0xFFFF, sum = 0
5476 22:55:59.919276 9, 0xFFFF, sum = 0
5477 22:55:59.922232 10, 0x0, sum = 1
5478 22:55:59.922704 11, 0x0, sum = 2
5479 22:55:59.925403 12, 0x0, sum = 3
5480 22:55:59.925881 13, 0x0, sum = 4
5481 22:55:59.926259 best_step = 11
5482 22:55:59.926602
5483 22:55:59.928913 ==
5484 22:55:59.932439 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 22:55:59.935920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 22:55:59.936489 ==
5487 22:55:59.936861 RX Vref Scan: 0
5488 22:55:59.937226
5489 22:55:59.938826 RX Vref 0 -> 0, step: 1
5490 22:55:59.939301
5491 22:55:59.942384 RX Delay -53 -> 252, step: 4
5492 22:55:59.945477 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5493 22:55:59.952452 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5494 22:55:59.955756 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5495 22:55:59.958763 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5496 22:55:59.962104 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5497 22:55:59.965601 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5498 22:55:59.972164 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5499 22:55:59.975647 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5500 22:55:59.978807 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5501 22:55:59.982217 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5502 22:55:59.985691 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5503 22:55:59.988822 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5504 22:55:59.995518 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5505 22:55:59.998680 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5506 22:56:00.002195 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5507 22:56:00.005473 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5508 22:56:00.006039 ==
5509 22:56:00.008600 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 22:56:00.015473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 22:56:00.016043 ==
5512 22:56:00.016418 DQS Delay:
5513 22:56:00.016761 DQS0 = 0, DQS1 = 0
5514 22:56:00.018870 DQM Delay:
5515 22:56:00.019436 DQM0 = 103, DQM1 = 92
5516 22:56:00.021905 DQ Delay:
5517 22:56:00.025588 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5518 22:56:00.029036 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5519 22:56:00.032480 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5520 22:56:00.035284 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5521 22:56:00.035754
5522 22:56:00.036124
5523 22:56:00.041818 [DQSOSCAuto] RK1, (LSB)MR18= 0x2808, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5524 22:56:00.045576 CH0 RK1: MR19=505, MR18=2808
5525 22:56:00.052077 CH0_RK1: MR19=0x505, MR18=0x2808, DQSOSC=409, MR23=63, INC=64, DEC=43
5526 22:56:00.055908 [RxdqsGatingPostProcess] freq 933
5527 22:56:00.061954 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5528 22:56:00.062425 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 22:56:00.065177 best DQS1 dly(2T, 0.5T) = (0, 10)
5530 22:56:00.068735 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 22:56:00.071661 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5532 22:56:00.075136 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 22:56:00.078254 best DQS1 dly(2T, 0.5T) = (0, 10)
5534 22:56:00.081236 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 22:56:00.084643 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5536 22:56:00.088119 Pre-setting of DQS Precalculation
5537 22:56:00.091545 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5538 22:56:00.094754 ==
5539 22:56:00.098464 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 22:56:00.101545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 22:56:00.102017 ==
5542 22:56:00.104840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5543 22:56:00.112227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5544 22:56:00.115654 [CA 0] Center 37 (7~68) winsize 62
5545 22:56:00.119033 [CA 1] Center 37 (7~68) winsize 62
5546 22:56:00.122088 [CA 2] Center 36 (6~66) winsize 61
5547 22:56:00.125861 [CA 3] Center 35 (5~65) winsize 61
5548 22:56:00.128882 [CA 4] Center 35 (5~66) winsize 62
5549 22:56:00.132217 [CA 5] Center 34 (4~65) winsize 62
5550 22:56:00.132795
5551 22:56:00.135560 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5552 22:56:00.136030
5553 22:56:00.138761 [CATrainingPosCal] consider 1 rank data
5554 22:56:00.141956 u2DelayCellTimex100 = 270/100 ps
5555 22:56:00.145134 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5556 22:56:00.148797 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5557 22:56:00.155667 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5558 22:56:00.159201 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5559 22:56:00.162513 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5560 22:56:00.165732 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5561 22:56:00.166290
5562 22:56:00.168681 CA PerBit enable=1, Macro0, CA PI delay=34
5563 22:56:00.169286
5564 22:56:00.172408 [CBTSetCACLKResult] CA Dly = 34
5565 22:56:00.172968 CS Dly: 6 (0~37)
5566 22:56:00.175102 ==
5567 22:56:00.175598 Dram Type= 6, Freq= 0, CH_1, rank 1
5568 22:56:00.181585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 22:56:00.182082 ==
5570 22:56:00.185154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5571 22:56:00.191854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5572 22:56:00.195425 [CA 0] Center 37 (7~68) winsize 62
5573 22:56:00.198824 [CA 1] Center 38 (8~68) winsize 61
5574 22:56:00.201729 [CA 2] Center 35 (5~66) winsize 62
5575 22:56:00.205004 [CA 3] Center 35 (6~65) winsize 60
5576 22:56:00.208823 [CA 4] Center 35 (6~65) winsize 60
5577 22:56:00.211967 [CA 5] Center 35 (5~65) winsize 61
5578 22:56:00.212526
5579 22:56:00.215394 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5580 22:56:00.215974
5581 22:56:00.218479 [CATrainingPosCal] consider 2 rank data
5582 22:56:00.221685 u2DelayCellTimex100 = 270/100 ps
5583 22:56:00.225356 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5584 22:56:00.231836 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5585 22:56:00.235327 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5586 22:56:00.238341 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5587 22:56:00.241837 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5588 22:56:00.245076 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5589 22:56:00.245795
5590 22:56:00.248238 CA PerBit enable=1, Macro0, CA PI delay=35
5591 22:56:00.248805
5592 22:56:00.251639 [CBTSetCACLKResult] CA Dly = 35
5593 22:56:00.252102 CS Dly: 7 (0~40)
5594 22:56:00.255143
5595 22:56:00.258507 ----->DramcWriteLeveling(PI) begin...
5596 22:56:00.258979 ==
5597 22:56:00.261751 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 22:56:00.264696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 22:56:00.265164 ==
5600 22:56:00.268472 Write leveling (Byte 0): 26 => 26
5601 22:56:00.271727 Write leveling (Byte 1): 31 => 31
5602 22:56:00.274679 DramcWriteLeveling(PI) end<-----
5603 22:56:00.275233
5604 22:56:00.275601 ==
5605 22:56:00.278326 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 22:56:00.281362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 22:56:00.281927 ==
5608 22:56:00.285223 [Gating] SW mode calibration
5609 22:56:00.291477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5610 22:56:00.298252 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5611 22:56:00.301452 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 22:56:00.304734 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 22:56:00.311422 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 22:56:00.314696 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 22:56:00.318415 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 22:56:00.325166 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 22:56:00.328253 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (1 0) (0 1)
5618 22:56:00.331571 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5619 22:56:00.338705 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 22:56:00.341281 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 22:56:00.344587 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 22:56:00.347934 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 22:56:00.354756 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 22:56:00.358524 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 22:56:00.361485 0 15 24 | B1->B0 | 2c2c 2f2f | 0 0 | (0 0) (0 0)
5626 22:56:00.368073 0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
5627 22:56:00.371017 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 22:56:00.374795 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 22:56:00.381165 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 22:56:00.384724 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 22:56:00.388344 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 22:56:00.394425 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 22:56:00.397945 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5634 22:56:00.401141 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5635 22:56:00.408023 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 22:56:00.411068 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 22:56:00.414275 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 22:56:00.421089 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 22:56:00.424227 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 22:56:00.427629 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 22:56:00.434319 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 22:56:00.437680 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 22:56:00.441541 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 22:56:00.448310 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 22:56:00.451260 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 22:56:00.454703 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 22:56:00.461186 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 22:56:00.464550 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 22:56:00.467925 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5650 22:56:00.471333 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5651 22:56:00.474721 Total UI for P1: 0, mck2ui 16
5652 22:56:00.478211 best dqsien dly found for B0: ( 1, 2, 24)
5653 22:56:00.484831 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 22:56:00.487818 Total UI for P1: 0, mck2ui 16
5655 22:56:00.491042 best dqsien dly found for B1: ( 1, 2, 28)
5656 22:56:00.494173 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5657 22:56:00.497754 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5658 22:56:00.498328
5659 22:56:00.501072 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5660 22:56:00.504096 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5661 22:56:00.507386 [Gating] SW calibration Done
5662 22:56:00.507885 ==
5663 22:56:00.510650 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 22:56:00.514270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 22:56:00.514878 ==
5666 22:56:00.517267 RX Vref Scan: 0
5667 22:56:00.517823
5668 22:56:00.518296 RX Vref 0 -> 0, step: 1
5669 22:56:00.520587
5670 22:56:00.521086 RX Delay -80 -> 252, step: 8
5671 22:56:00.527511 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5672 22:56:00.531049 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5673 22:56:00.534074 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5674 22:56:00.537798 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5675 22:56:00.540586 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5676 22:56:00.544117 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5677 22:56:00.550956 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5678 22:56:00.554072 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5679 22:56:00.557066 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5680 22:56:00.560930 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5681 22:56:00.564061 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5682 22:56:00.567608 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5683 22:56:00.574150 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5684 22:56:00.577473 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5685 22:56:00.581021 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5686 22:56:00.584061 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5687 22:56:00.584532 ==
5688 22:56:00.587275 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 22:56:00.590854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 22:56:00.594240 ==
5691 22:56:00.594706 DQS Delay:
5692 22:56:00.595076 DQS0 = 0, DQS1 = 0
5693 22:56:00.597325 DQM Delay:
5694 22:56:00.597890 DQM0 = 101, DQM1 = 94
5695 22:56:00.600362 DQ Delay:
5696 22:56:00.603970 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5697 22:56:00.607419 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5698 22:56:00.607984 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5699 22:56:00.613997 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5700 22:56:00.614561
5701 22:56:00.614931
5702 22:56:00.615272 ==
5703 22:56:00.617424 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 22:56:00.620756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 22:56:00.621230 ==
5706 22:56:00.621654
5707 22:56:00.622003
5708 22:56:00.623875 TX Vref Scan disable
5709 22:56:00.624342 == TX Byte 0 ==
5710 22:56:00.630785 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5711 22:56:00.634116 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5712 22:56:00.634589 == TX Byte 1 ==
5713 22:56:00.640769 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5714 22:56:00.643823 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5715 22:56:00.644290 ==
5716 22:56:00.647549 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 22:56:00.650818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 22:56:00.651293 ==
5719 22:56:00.651667
5720 22:56:00.652012
5721 22:56:00.653846 TX Vref Scan disable
5722 22:56:00.657398 == TX Byte 0 ==
5723 22:56:00.660774 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5724 22:56:00.663808 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5725 22:56:00.667645 == TX Byte 1 ==
5726 22:56:00.670690 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5727 22:56:00.673676 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5728 22:56:00.674146
5729 22:56:00.677274 [DATLAT]
5730 22:56:00.677765 Freq=933, CH1 RK0
5731 22:56:00.678129
5732 22:56:00.680427 DATLAT Default: 0xd
5733 22:56:00.680895 0, 0xFFFF, sum = 0
5734 22:56:00.683987 1, 0xFFFF, sum = 0
5735 22:56:00.684459 2, 0xFFFF, sum = 0
5736 22:56:00.686989 3, 0xFFFF, sum = 0
5737 22:56:00.687466 4, 0xFFFF, sum = 0
5738 22:56:00.690726 5, 0xFFFF, sum = 0
5739 22:56:00.691294 6, 0xFFFF, sum = 0
5740 22:56:00.694008 7, 0xFFFF, sum = 0
5741 22:56:00.694484 8, 0xFFFF, sum = 0
5742 22:56:00.697093 9, 0xFFFF, sum = 0
5743 22:56:00.697591 10, 0x0, sum = 1
5744 22:56:00.700770 11, 0x0, sum = 2
5745 22:56:00.701371 12, 0x0, sum = 3
5746 22:56:00.703961 13, 0x0, sum = 4
5747 22:56:00.704532 best_step = 11
5748 22:56:00.704901
5749 22:56:00.705243 ==
5750 22:56:00.707082 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 22:56:00.713820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 22:56:00.714297 ==
5753 22:56:00.714668 RX Vref Scan: 1
5754 22:56:00.715015
5755 22:56:00.717212 RX Vref 0 -> 0, step: 1
5756 22:56:00.717810
5757 22:56:00.720095 RX Delay -53 -> 252, step: 4
5758 22:56:00.720563
5759 22:56:00.723514 Set Vref, RX VrefLevel [Byte0]: 50
5760 22:56:00.727008 [Byte1]: 53
5761 22:56:00.727584
5762 22:56:00.730315 Final RX Vref Byte 0 = 50 to rank0
5763 22:56:00.733659 Final RX Vref Byte 1 = 53 to rank0
5764 22:56:00.736890 Final RX Vref Byte 0 = 50 to rank1
5765 22:56:00.740225 Final RX Vref Byte 1 = 53 to rank1==
5766 22:56:00.743295 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 22:56:00.746904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 22:56:00.747470 ==
5769 22:56:00.749819 DQS Delay:
5770 22:56:00.750314 DQS0 = 0, DQS1 = 0
5771 22:56:00.753102 DQM Delay:
5772 22:56:00.753599 DQM0 = 104, DQM1 = 98
5773 22:56:00.753970 DQ Delay:
5774 22:56:00.756446 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =104
5775 22:56:00.760285 DQ4 =104, DQ5 =112, DQ6 =116, DQ7 =100
5776 22:56:00.763368 DQ8 =90, DQ9 =88, DQ10 =100, DQ11 =94
5777 22:56:00.769962 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =104
5778 22:56:00.770515
5779 22:56:00.770887
5780 22:56:00.776919 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5781 22:56:00.779828 CH1 RK0: MR19=505, MR18=1A32
5782 22:56:00.786851 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5783 22:56:00.787417
5784 22:56:00.790154 ----->DramcWriteLeveling(PI) begin...
5785 22:56:00.790717 ==
5786 22:56:00.793284 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 22:56:00.796766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 22:56:00.797371 ==
5789 22:56:00.799864 Write leveling (Byte 0): 26 => 26
5790 22:56:00.803093 Write leveling (Byte 1): 30 => 30
5791 22:56:00.806377 DramcWriteLeveling(PI) end<-----
5792 22:56:00.806937
5793 22:56:00.807308 ==
5794 22:56:00.809534 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 22:56:00.813025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 22:56:00.813657 ==
5797 22:56:00.816584 [Gating] SW mode calibration
5798 22:56:00.823236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5799 22:56:00.829937 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5800 22:56:00.833244 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5801 22:56:00.839458 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 22:56:00.842646 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 22:56:00.846024 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 22:56:00.852957 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 22:56:00.856106 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 22:56:00.859506 0 14 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 0)
5807 22:56:00.866016 0 14 28 | B1->B0 | 2626 2e2e | 0 0 | (1 1) (1 1)
5808 22:56:00.869419 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 22:56:00.872772 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 22:56:00.876222 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 22:56:00.882612 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 22:56:00.885877 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 22:56:00.889380 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 22:56:00.896389 0 15 24 | B1->B0 | 2f2f 2a2a | 1 0 | (0 0) (0 0)
5815 22:56:00.899420 0 15 28 | B1->B0 | 4242 3434 | 0 0 | (0 0) (1 1)
5816 22:56:00.902661 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5817 22:56:00.909384 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 22:56:00.912697 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 22:56:00.915734 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 22:56:00.922324 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 22:56:00.925766 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 22:56:00.928832 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 22:56:00.935941 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5824 22:56:00.939117 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 22:56:00.942044 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 22:56:00.949052 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 22:56:00.952002 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 22:56:00.955677 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 22:56:00.962306 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 22:56:00.965248 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 22:56:00.968908 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 22:56:00.975470 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 22:56:00.978858 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 22:56:00.982333 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 22:56:00.985850 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 22:56:00.991964 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 22:56:00.995672 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 22:56:00.999037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5839 22:56:01.005576 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 22:56:01.008829 Total UI for P1: 0, mck2ui 16
5841 22:56:01.011974 best dqsien dly found for B0: ( 1, 2, 26)
5842 22:56:01.015596 Total UI for P1: 0, mck2ui 16
5843 22:56:01.018691 best dqsien dly found for B1: ( 1, 2, 24)
5844 22:56:01.021895 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5845 22:56:01.025585 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5846 22:56:01.025733
5847 22:56:01.028517 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5848 22:56:01.031963 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5849 22:56:01.035504 [Gating] SW calibration Done
5850 22:56:01.035653 ==
5851 22:56:01.038839 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 22:56:01.041934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 22:56:01.042082 ==
5854 22:56:01.045517 RX Vref Scan: 0
5855 22:56:01.045676
5856 22:56:01.045799 RX Vref 0 -> 0, step: 1
5857 22:56:01.048602
5858 22:56:01.048781 RX Delay -80 -> 252, step: 8
5859 22:56:01.055235 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5860 22:56:01.058529 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5861 22:56:01.061530 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5862 22:56:01.065166 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5863 22:56:01.068262 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5864 22:56:01.071573 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5865 22:56:01.078191 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5866 22:56:01.081655 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5867 22:56:01.084877 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5868 22:56:01.088430 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5869 22:56:01.091458 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5870 22:56:01.095040 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5871 22:56:01.101401 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5872 22:56:01.104701 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5873 22:56:01.108565 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5874 22:56:01.111414 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5875 22:56:01.111654 ==
5876 22:56:01.114810 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 22:56:01.118011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 22:56:01.121383 ==
5879 22:56:01.121541 DQS Delay:
5880 22:56:01.121660 DQS0 = 0, DQS1 = 0
5881 22:56:01.125115 DQM Delay:
5882 22:56:01.125263 DQM0 = 101, DQM1 = 95
5883 22:56:01.127966 DQ Delay:
5884 22:56:01.131546 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5885 22:56:01.131694 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5886 22:56:01.134893 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5887 22:56:01.141609 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5888 22:56:01.141757
5889 22:56:01.141872
5890 22:56:01.141980 ==
5891 22:56:01.144659 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 22:56:01.148119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 22:56:01.148269 ==
5894 22:56:01.148386
5895 22:56:01.148491
5896 22:56:01.151081 TX Vref Scan disable
5897 22:56:01.151228 == TX Byte 0 ==
5898 22:56:01.158153 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5899 22:56:01.161030 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5900 22:56:01.161114 == TX Byte 1 ==
5901 22:56:01.167988 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5902 22:56:01.171361 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5903 22:56:01.171451 ==
5904 22:56:01.174971 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 22:56:01.177661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 22:56:01.177757 ==
5907 22:56:01.177832
5908 22:56:01.181126
5909 22:56:01.181227 TX Vref Scan disable
5910 22:56:01.184336 == TX Byte 0 ==
5911 22:56:01.187993 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5912 22:56:01.191357 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5913 22:56:01.194708 == TX Byte 1 ==
5914 22:56:01.197569 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5915 22:56:01.201173 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5916 22:56:01.204278
5917 22:56:01.204431 [DATLAT]
5918 22:56:01.204550 Freq=933, CH1 RK1
5919 22:56:01.204663
5920 22:56:01.207622 DATLAT Default: 0xb
5921 22:56:01.207775 0, 0xFFFF, sum = 0
5922 22:56:01.210822 1, 0xFFFF, sum = 0
5923 22:56:01.210979 2, 0xFFFF, sum = 0
5924 22:56:01.214118 3, 0xFFFF, sum = 0
5925 22:56:01.217760 4, 0xFFFF, sum = 0
5926 22:56:01.217938 5, 0xFFFF, sum = 0
5927 22:56:01.221307 6, 0xFFFF, sum = 0
5928 22:56:01.221512 7, 0xFFFF, sum = 0
5929 22:56:01.224262 8, 0xFFFF, sum = 0
5930 22:56:01.224509 9, 0xFFFF, sum = 0
5931 22:56:01.227557 10, 0x0, sum = 1
5932 22:56:01.227806 11, 0x0, sum = 2
5933 22:56:01.228002 12, 0x0, sum = 3
5934 22:56:01.230730 13, 0x0, sum = 4
5935 22:56:01.230975 best_step = 11
5936 22:56:01.231175
5937 22:56:01.234659 ==
5938 22:56:01.234902 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 22:56:01.241096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 22:56:01.241363 ==
5941 22:56:01.241562 RX Vref Scan: 0
5942 22:56:01.241741
5943 22:56:01.244238 RX Vref 0 -> 0, step: 1
5944 22:56:01.244484
5945 22:56:01.247675 RX Delay -53 -> 252, step: 4
5946 22:56:01.250951 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5947 22:56:01.257683 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5948 22:56:01.260913 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5949 22:56:01.264286 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5950 22:56:01.267880 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5951 22:56:01.271011 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5952 22:56:01.277412 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5953 22:56:01.280821 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5954 22:56:01.284282 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5955 22:56:01.287438 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5956 22:56:01.290892 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5957 22:56:01.294068 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5958 22:56:01.300694 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5959 22:56:01.304389 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5960 22:56:01.307407 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5961 22:56:01.310969 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5962 22:56:01.311216 ==
5963 22:56:01.314165 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 22:56:01.320721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 22:56:01.320969 ==
5966 22:56:01.321163 DQS Delay:
5967 22:56:01.324039 DQS0 = 0, DQS1 = 0
5968 22:56:01.324244 DQM Delay:
5969 22:56:01.324398 DQM0 = 105, DQM1 = 97
5970 22:56:01.327524 DQ Delay:
5971 22:56:01.330736 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =102
5972 22:56:01.333812 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5973 22:56:01.337144 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5974 22:56:01.340380 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5975 22:56:01.340520
5976 22:56:01.340629
5977 22:56:01.347451 [DQSOSCAuto] RK1, (LSB)MR18= 0x2703, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5978 22:56:01.350443 CH1 RK1: MR19=505, MR18=2703
5979 22:56:01.357293 CH1_RK1: MR19=0x505, MR18=0x2703, DQSOSC=409, MR23=63, INC=64, DEC=43
5980 22:56:01.360304 [RxdqsGatingPostProcess] freq 933
5981 22:56:01.366922 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5982 22:56:01.370364 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 22:56:01.373543 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 22:56:01.376959 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 22:56:01.380230 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 22:56:01.380476 best DQS0 dly(2T, 0.5T) = (0, 10)
5987 22:56:01.383581 best DQS1 dly(2T, 0.5T) = (0, 10)
5988 22:56:01.386922 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5989 22:56:01.390620 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5990 22:56:01.393809 Pre-setting of DQS Precalculation
5991 22:56:01.400675 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5992 22:56:01.407332 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5993 22:56:01.413786 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5994 22:56:01.414067
5995 22:56:01.414284
5996 22:56:01.416882 [Calibration Summary] 1866 Mbps
5997 22:56:01.417157 CH 0, Rank 0
5998 22:56:01.420280 SW Impedance : PASS
5999 22:56:01.423382 DUTY Scan : NO K
6000 22:56:01.423556 ZQ Calibration : PASS
6001 22:56:01.426704 Jitter Meter : NO K
6002 22:56:01.430335 CBT Training : PASS
6003 22:56:01.430482 Write leveling : PASS
6004 22:56:01.433383 RX DQS gating : PASS
6005 22:56:01.436522 RX DQ/DQS(RDDQC) : PASS
6006 22:56:01.436652 TX DQ/DQS : PASS
6007 22:56:01.440102 RX DATLAT : PASS
6008 22:56:01.440217 RX DQ/DQS(Engine): PASS
6009 22:56:01.443244 TX OE : NO K
6010 22:56:01.443348 All Pass.
6011 22:56:01.443427
6012 22:56:01.446665 CH 0, Rank 1
6013 22:56:01.446770 SW Impedance : PASS
6014 22:56:01.450055 DUTY Scan : NO K
6015 22:56:01.453186 ZQ Calibration : PASS
6016 22:56:01.453290 Jitter Meter : NO K
6017 22:56:01.456363 CBT Training : PASS
6018 22:56:01.460171 Write leveling : PASS
6019 22:56:01.460266 RX DQS gating : PASS
6020 22:56:01.463509 RX DQ/DQS(RDDQC) : PASS
6021 22:56:01.466313 TX DQ/DQS : PASS
6022 22:56:01.466406 RX DATLAT : PASS
6023 22:56:01.470122 RX DQ/DQS(Engine): PASS
6024 22:56:01.473074 TX OE : NO K
6025 22:56:01.473168 All Pass.
6026 22:56:01.473234
6027 22:56:01.473300 CH 1, Rank 0
6028 22:56:01.476767 SW Impedance : PASS
6029 22:56:01.480059 DUTY Scan : NO K
6030 22:56:01.480148 ZQ Calibration : PASS
6031 22:56:01.483158 Jitter Meter : NO K
6032 22:56:01.486332 CBT Training : PASS
6033 22:56:01.486420 Write leveling : PASS
6034 22:56:01.490027 RX DQS gating : PASS
6035 22:56:01.493077 RX DQ/DQS(RDDQC) : PASS
6036 22:56:01.493159 TX DQ/DQS : PASS
6037 22:56:01.496391 RX DATLAT : PASS
6038 22:56:01.496474 RX DQ/DQS(Engine): PASS
6039 22:56:01.499812 TX OE : NO K
6040 22:56:01.499896 All Pass.
6041 22:56:01.499962
6042 22:56:01.502784 CH 1, Rank 1
6043 22:56:01.502868 SW Impedance : PASS
6044 22:56:01.506298 DUTY Scan : NO K
6045 22:56:01.509893 ZQ Calibration : PASS
6046 22:56:01.510361 Jitter Meter : NO K
6047 22:56:01.513230 CBT Training : PASS
6048 22:56:01.516673 Write leveling : PASS
6049 22:56:01.517146 RX DQS gating : PASS
6050 22:56:01.520271 RX DQ/DQS(RDDQC) : PASS
6051 22:56:01.523612 TX DQ/DQS : PASS
6052 22:56:01.524160 RX DATLAT : PASS
6053 22:56:01.526818 RX DQ/DQS(Engine): PASS
6054 22:56:01.529987 TX OE : NO K
6055 22:56:01.530455 All Pass.
6056 22:56:01.531103
6057 22:56:01.531752 DramC Write-DBI off
6058 22:56:01.533467 PER_BANK_REFRESH: Hybrid Mode
6059 22:56:01.536894 TX_TRACKING: ON
6060 22:56:01.543229 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6061 22:56:01.546667 [FAST_K] Save calibration result to emmc
6062 22:56:01.553352 dramc_set_vcore_voltage set vcore to 650000
6063 22:56:01.553788 Read voltage for 400, 6
6064 22:56:01.556583 Vio18 = 0
6065 22:56:01.557010 Vcore = 650000
6066 22:56:01.557388 Vdram = 0
6067 22:56:01.557714 Vddq = 0
6068 22:56:01.560160 Vmddr = 0
6069 22:56:01.563626 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6070 22:56:01.570119 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6071 22:56:01.573427 MEM_TYPE=3, freq_sel=20
6072 22:56:01.573859 sv_algorithm_assistance_LP4_800
6073 22:56:01.579972 ============ PULL DRAM RESETB DOWN ============
6074 22:56:01.583322 ========== PULL DRAM RESETB DOWN end =========
6075 22:56:01.586378 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6076 22:56:01.589384 ===================================
6077 22:56:01.593151 LPDDR4 DRAM CONFIGURATION
6078 22:56:01.596459 ===================================
6079 22:56:01.599453 EX_ROW_EN[0] = 0x0
6080 22:56:01.599644 EX_ROW_EN[1] = 0x0
6081 22:56:01.602771 LP4Y_EN = 0x0
6082 22:56:01.602929 WORK_FSP = 0x0
6083 22:56:01.606054 WL = 0x2
6084 22:56:01.606170 RL = 0x2
6085 22:56:01.609522 BL = 0x2
6086 22:56:01.609618 RPST = 0x0
6087 22:56:01.612957 RD_PRE = 0x0
6088 22:56:01.613081 WR_PRE = 0x1
6089 22:56:01.616094 WR_PST = 0x0
6090 22:56:01.616182 DBI_WR = 0x0
6091 22:56:01.619582 DBI_RD = 0x0
6092 22:56:01.619668 OTF = 0x1
6093 22:56:01.622517 ===================================
6094 22:56:01.626376 ===================================
6095 22:56:01.629363 ANA top config
6096 22:56:01.632949 ===================================
6097 22:56:01.635996 DLL_ASYNC_EN = 0
6098 22:56:01.636349 ALL_SLAVE_EN = 1
6099 22:56:01.639493 NEW_RANK_MODE = 1
6100 22:56:01.642779 DLL_IDLE_MODE = 1
6101 22:56:01.646049 LP45_APHY_COMB_EN = 1
6102 22:56:01.649369 TX_ODT_DIS = 1
6103 22:56:01.649702 NEW_8X_MODE = 1
6104 22:56:01.652640 ===================================
6105 22:56:01.656026 ===================================
6106 22:56:01.659327 data_rate = 800
6107 22:56:01.662406 CKR = 1
6108 22:56:01.665901 DQ_P2S_RATIO = 4
6109 22:56:01.669279 ===================================
6110 22:56:01.672391 CA_P2S_RATIO = 4
6111 22:56:01.675750 DQ_CA_OPEN = 0
6112 22:56:01.676104 DQ_SEMI_OPEN = 1
6113 22:56:01.679221 CA_SEMI_OPEN = 1
6114 22:56:01.682194 CA_FULL_RATE = 0
6115 22:56:01.685823 DQ_CKDIV4_EN = 0
6116 22:56:01.689085 CA_CKDIV4_EN = 1
6117 22:56:01.692614 CA_PREDIV_EN = 0
6118 22:56:01.692949 PH8_DLY = 0
6119 22:56:01.695547 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6120 22:56:01.698827 DQ_AAMCK_DIV = 0
6121 22:56:01.702088 CA_AAMCK_DIV = 0
6122 22:56:01.705387 CA_ADMCK_DIV = 4
6123 22:56:01.708819 DQ_TRACK_CA_EN = 0
6124 22:56:01.708907 CA_PICK = 800
6125 22:56:01.712224 CA_MCKIO = 400
6126 22:56:01.715683 MCKIO_SEMI = 400
6127 22:56:01.719194 PLL_FREQ = 3016
6128 22:56:01.722294 DQ_UI_PI_RATIO = 32
6129 22:56:01.725557 CA_UI_PI_RATIO = 32
6130 22:56:01.728860 ===================================
6131 22:56:01.731891 ===================================
6132 22:56:01.731974 memory_type:LPDDR4
6133 22:56:01.735198 GP_NUM : 10
6134 22:56:01.739067 SRAM_EN : 1
6135 22:56:01.739150 MD32_EN : 0
6136 22:56:01.742154 ===================================
6137 22:56:01.745408 [ANA_INIT] >>>>>>>>>>>>>>
6138 22:56:01.748969 <<<<<< [CONFIGURE PHASE]: ANA_TX
6139 22:56:01.752099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6140 22:56:01.755302 ===================================
6141 22:56:01.758854 data_rate = 800,PCW = 0X7400
6142 22:56:01.762209 ===================================
6143 22:56:01.765876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6144 22:56:01.768982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6145 22:56:01.782185 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6146 22:56:01.785676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6147 22:56:01.788837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6148 22:56:01.792416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6149 22:56:01.795596 [ANA_INIT] flow start
6150 22:56:01.799189 [ANA_INIT] PLL >>>>>>>>
6151 22:56:01.799390 [ANA_INIT] PLL <<<<<<<<
6152 22:56:01.802175 [ANA_INIT] MIDPI >>>>>>>>
6153 22:56:01.806119 [ANA_INIT] MIDPI <<<<<<<<
6154 22:56:01.806339 [ANA_INIT] DLL >>>>>>>>
6155 22:56:01.809172 [ANA_INIT] flow end
6156 22:56:01.812178 ============ LP4 DIFF to SE enter ============
6157 22:56:01.815528 ============ LP4 DIFF to SE exit ============
6158 22:56:01.818839 [ANA_INIT] <<<<<<<<<<<<<
6159 22:56:01.821963 [Flow] Enable top DCM control >>>>>
6160 22:56:01.825670 [Flow] Enable top DCM control <<<<<
6161 22:56:01.828943 Enable DLL master slave shuffle
6162 22:56:01.835745 ==============================================================
6163 22:56:01.836133 Gating Mode config
6164 22:56:01.842560 ==============================================================
6165 22:56:01.843130 Config description:
6166 22:56:01.852309 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6167 22:56:01.859166 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6168 22:56:01.865884 SELPH_MODE 0: By rank 1: By Phase
6169 22:56:01.869019 ==============================================================
6170 22:56:01.872307 GAT_TRACK_EN = 0
6171 22:56:01.875853 RX_GATING_MODE = 2
6172 22:56:01.879213 RX_GATING_TRACK_MODE = 2
6173 22:56:01.882163 SELPH_MODE = 1
6174 22:56:01.885807 PICG_EARLY_EN = 1
6175 22:56:01.888736 VALID_LAT_VALUE = 1
6176 22:56:01.895299 ==============================================================
6177 22:56:01.898758 Enter into Gating configuration >>>>
6178 22:56:01.902034 Exit from Gating configuration <<<<
6179 22:56:01.902652 Enter into DVFS_PRE_config >>>>>
6180 22:56:01.915419 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6181 22:56:01.918756 Exit from DVFS_PRE_config <<<<<
6182 22:56:01.922175 Enter into PICG configuration >>>>
6183 22:56:01.925008 Exit from PICG configuration <<<<
6184 22:56:01.925518 [RX_INPUT] configuration >>>>>
6185 22:56:01.928128 [RX_INPUT] configuration <<<<<
6186 22:56:01.935044 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6187 22:56:01.941901 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6188 22:56:01.945202 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6189 22:56:01.951549 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6190 22:56:01.958689 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6191 22:56:01.965350 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6192 22:56:01.968717 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6193 22:56:01.972006 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6194 22:56:01.978377 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6195 22:56:01.981846 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6196 22:56:01.985338 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6197 22:56:01.988122 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6198 22:56:01.991743 ===================================
6199 22:56:01.994928 LPDDR4 DRAM CONFIGURATION
6200 22:56:01.998454 ===================================
6201 22:56:02.001541 EX_ROW_EN[0] = 0x0
6202 22:56:02.002018 EX_ROW_EN[1] = 0x0
6203 22:56:02.004797 LP4Y_EN = 0x0
6204 22:56:02.005268 WORK_FSP = 0x0
6205 22:56:02.008333 WL = 0x2
6206 22:56:02.008903 RL = 0x2
6207 22:56:02.011836 BL = 0x2
6208 22:56:02.012411 RPST = 0x0
6209 22:56:02.015407 RD_PRE = 0x0
6210 22:56:02.015993 WR_PRE = 0x1
6211 22:56:02.018063 WR_PST = 0x0
6212 22:56:02.021446 DBI_WR = 0x0
6213 22:56:02.021919 DBI_RD = 0x0
6214 22:56:02.024719 OTF = 0x1
6215 22:56:02.028332 ===================================
6216 22:56:02.031430 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6217 22:56:02.034881 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6218 22:56:02.038414 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6219 22:56:02.041260 ===================================
6220 22:56:02.044967 LPDDR4 DRAM CONFIGURATION
6221 22:56:02.047792 ===================================
6222 22:56:02.051288 EX_ROW_EN[0] = 0x10
6223 22:56:02.051762 EX_ROW_EN[1] = 0x0
6224 22:56:02.055092 LP4Y_EN = 0x0
6225 22:56:02.055672 WORK_FSP = 0x0
6226 22:56:02.058120 WL = 0x2
6227 22:56:02.058615 RL = 0x2
6228 22:56:02.061201 BL = 0x2
6229 22:56:02.061776 RPST = 0x0
6230 22:56:02.064547 RD_PRE = 0x0
6231 22:56:02.065044 WR_PRE = 0x1
6232 22:56:02.068146 WR_PST = 0x0
6233 22:56:02.068617 DBI_WR = 0x0
6234 22:56:02.071517 DBI_RD = 0x0
6235 22:56:02.074497 OTF = 0x1
6236 22:56:02.077709 ===================================
6237 22:56:02.081248 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6238 22:56:02.086324 nWR fixed to 30
6239 22:56:02.089501 [ModeRegInit_LP4] CH0 RK0
6240 22:56:02.089976 [ModeRegInit_LP4] CH0 RK1
6241 22:56:02.093197 [ModeRegInit_LP4] CH1 RK0
6242 22:56:02.096307 [ModeRegInit_LP4] CH1 RK1
6243 22:56:02.096778 match AC timing 19
6244 22:56:02.103061 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6245 22:56:02.106468 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6246 22:56:02.109445 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6247 22:56:02.116283 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6248 22:56:02.119550 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6249 22:56:02.120118 ==
6250 22:56:02.123120 Dram Type= 6, Freq= 0, CH_0, rank 0
6251 22:56:02.126167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 22:56:02.126647 ==
6253 22:56:02.132905 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6254 22:56:02.140110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6255 22:56:02.143130 [CA 0] Center 36 (8~64) winsize 57
6256 22:56:02.146219 [CA 1] Center 36 (8~64) winsize 57
6257 22:56:02.146713 [CA 2] Center 36 (8~64) winsize 57
6258 22:56:02.149879 [CA 3] Center 36 (8~64) winsize 57
6259 22:56:02.153221 [CA 4] Center 36 (8~64) winsize 57
6260 22:56:02.156521 [CA 5] Center 36 (8~64) winsize 57
6261 22:56:02.156986
6262 22:56:02.159682 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6263 22:56:02.162801
6264 22:56:02.166039 [CATrainingPosCal] consider 1 rank data
6265 22:56:02.166508 u2DelayCellTimex100 = 270/100 ps
6266 22:56:02.172611 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 22:56:02.176735 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 22:56:02.180029 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 22:56:02.183217 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 22:56:02.186434 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 22:56:02.189620 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 22:56:02.190102
6273 22:56:02.193207 CA PerBit enable=1, Macro0, CA PI delay=36
6274 22:56:02.193833
6275 22:56:02.195989 [CBTSetCACLKResult] CA Dly = 36
6276 22:56:02.200073 CS Dly: 1 (0~32)
6277 22:56:02.200634 ==
6278 22:56:02.202624 Dram Type= 6, Freq= 0, CH_0, rank 1
6279 22:56:02.206463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 22:56:02.207037 ==
6281 22:56:02.213105 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6282 22:56:02.216244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6283 22:56:02.219348 [CA 0] Center 36 (8~64) winsize 57
6284 22:56:02.222999 [CA 1] Center 36 (8~64) winsize 57
6285 22:56:02.225912 [CA 2] Center 36 (8~64) winsize 57
6286 22:56:02.229611 [CA 3] Center 36 (8~64) winsize 57
6287 22:56:02.232930 [CA 4] Center 36 (8~64) winsize 57
6288 22:56:02.235918 [CA 5] Center 36 (8~64) winsize 57
6289 22:56:02.236482
6290 22:56:02.238985 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6291 22:56:02.239465
6292 22:56:02.242771 [CATrainingPosCal] consider 2 rank data
6293 22:56:02.246123 u2DelayCellTimex100 = 270/100 ps
6294 22:56:02.249473 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 22:56:02.252566 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 22:56:02.256238 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 22:56:02.259288 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 22:56:02.265985 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 22:56:02.269404 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 22:56:02.269876
6301 22:56:02.272462 CA PerBit enable=1, Macro0, CA PI delay=36
6302 22:56:02.272935
6303 22:56:02.275787 [CBTSetCACLKResult] CA Dly = 36
6304 22:56:02.276326 CS Dly: 1 (0~32)
6305 22:56:02.276832
6306 22:56:02.278951 ----->DramcWriteLeveling(PI) begin...
6307 22:56:02.279427 ==
6308 22:56:02.282686 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 22:56:02.289684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 22:56:02.290257 ==
6311 22:56:02.292788 Write leveling (Byte 0): 40 => 8
6312 22:56:02.293409 Write leveling (Byte 1): 32 => 0
6313 22:56:02.296125 DramcWriteLeveling(PI) end<-----
6314 22:56:02.296700
6315 22:56:02.299537 ==
6316 22:56:02.300114 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 22:56:02.305831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 22:56:02.306404 ==
6319 22:56:02.309174 [Gating] SW mode calibration
6320 22:56:02.315707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6321 22:56:02.319212 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6322 22:56:02.325643 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6323 22:56:02.329709 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6324 22:56:02.332373 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 22:56:02.339515 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6326 22:56:02.342085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 22:56:02.345937 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 22:56:02.352410 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 22:56:02.355675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 22:56:02.358674 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 22:56:02.362210 Total UI for P1: 0, mck2ui 16
6332 22:56:02.365493 best dqsien dly found for B0: ( 0, 14, 24)
6333 22:56:02.368884 Total UI for P1: 0, mck2ui 16
6334 22:56:02.372090 best dqsien dly found for B1: ( 0, 14, 24)
6335 22:56:02.375339 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6336 22:56:02.379051 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6337 22:56:02.379508
6338 22:56:02.382528 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6339 22:56:02.389070 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6340 22:56:02.389664 [Gating] SW calibration Done
6341 22:56:02.392301 ==
6342 22:56:02.392857 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 22:56:02.398933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 22:56:02.399496 ==
6345 22:56:02.399863 RX Vref Scan: 0
6346 22:56:02.400198
6347 22:56:02.402078 RX Vref 0 -> 0, step: 1
6348 22:56:02.402532
6349 22:56:02.405756 RX Delay -410 -> 252, step: 16
6350 22:56:02.408845 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6351 22:56:02.412511 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6352 22:56:02.418418 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6353 22:56:02.421696 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6354 22:56:02.425129 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6355 22:56:02.428846 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6356 22:56:02.435616 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6357 22:56:02.438921 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6358 22:56:02.442202 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6359 22:56:02.445644 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6360 22:56:02.452184 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6361 22:56:02.455553 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6362 22:56:02.458410 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6363 22:56:02.462081 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6364 22:56:02.468447 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6365 22:56:02.471710 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6366 22:56:02.472268 ==
6367 22:56:02.474942 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 22:56:02.478436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 22:56:02.479009 ==
6370 22:56:02.481643 DQS Delay:
6371 22:56:02.482199 DQS0 = 27, DQS1 = 43
6372 22:56:02.484908 DQM Delay:
6373 22:56:02.485465 DQM0 = 11, DQM1 = 11
6374 22:56:02.485863 DQ Delay:
6375 22:56:02.488200 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6376 22:56:02.491818 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6377 22:56:02.494950 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6378 22:56:02.498404 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6379 22:56:02.498960
6380 22:56:02.499319
6381 22:56:02.499651 ==
6382 22:56:02.502185 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 22:56:02.508400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 22:56:02.508961 ==
6385 22:56:02.509357
6386 22:56:02.509692
6387 22:56:02.510009 TX Vref Scan disable
6388 22:56:02.511348 == TX Byte 0 ==
6389 22:56:02.514966 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 22:56:02.518443 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 22:56:02.521586 == TX Byte 1 ==
6392 22:56:02.525032 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6393 22:56:02.528528 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6394 22:56:02.531569 ==
6395 22:56:02.532127 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 22:56:02.537966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 22:56:02.538515 ==
6398 22:56:02.538876
6399 22:56:02.539209
6400 22:56:02.541211 TX Vref Scan disable
6401 22:56:02.541702 == TX Byte 0 ==
6402 22:56:02.544663 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 22:56:02.551218 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 22:56:02.551693 == TX Byte 1 ==
6405 22:56:02.554960 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6406 22:56:02.561891 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6407 22:56:02.562454
6408 22:56:02.562826 [DATLAT]
6409 22:56:02.563170 Freq=400, CH0 RK0
6410 22:56:02.563506
6411 22:56:02.564859 DATLAT Default: 0xf
6412 22:56:02.565386 0, 0xFFFF, sum = 0
6413 22:56:02.568146 1, 0xFFFF, sum = 0
6414 22:56:02.568722 2, 0xFFFF, sum = 0
6415 22:56:02.571792 3, 0xFFFF, sum = 0
6416 22:56:02.574640 4, 0xFFFF, sum = 0
6417 22:56:02.575126 5, 0xFFFF, sum = 0
6418 22:56:02.578010 6, 0xFFFF, sum = 0
6419 22:56:02.578698 7, 0xFFFF, sum = 0
6420 22:56:02.581404 8, 0xFFFF, sum = 0
6421 22:56:02.581983 9, 0xFFFF, sum = 0
6422 22:56:02.584644 10, 0xFFFF, sum = 0
6423 22:56:02.585124 11, 0xFFFF, sum = 0
6424 22:56:02.588072 12, 0xFFFF, sum = 0
6425 22:56:02.588550 13, 0x0, sum = 1
6426 22:56:02.591336 14, 0x0, sum = 2
6427 22:56:02.591816 15, 0x0, sum = 3
6428 22:56:02.594639 16, 0x0, sum = 4
6429 22:56:02.595211 best_step = 14
6430 22:56:02.595589
6431 22:56:02.595932 ==
6432 22:56:02.598223 Dram Type= 6, Freq= 0, CH_0, rank 0
6433 22:56:02.601332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 22:56:02.601815 ==
6435 22:56:02.604823 RX Vref Scan: 1
6436 22:56:02.605293
6437 22:56:02.608354 RX Vref 0 -> 0, step: 1
6438 22:56:02.608912
6439 22:56:02.609285 RX Delay -327 -> 252, step: 8
6440 22:56:02.611508
6441 22:56:02.612068 Set Vref, RX VrefLevel [Byte0]: 58
6442 22:56:02.614434 [Byte1]: 50
6443 22:56:02.620496
6444 22:56:02.621059 Final RX Vref Byte 0 = 58 to rank0
6445 22:56:02.623328 Final RX Vref Byte 1 = 50 to rank0
6446 22:56:02.626570 Final RX Vref Byte 0 = 58 to rank1
6447 22:56:02.630449 Final RX Vref Byte 1 = 50 to rank1==
6448 22:56:02.633259 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 22:56:02.640321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 22:56:02.640876 ==
6451 22:56:02.641252 DQS Delay:
6452 22:56:02.643739 DQS0 = 28, DQS1 = 48
6453 22:56:02.644337 DQM Delay:
6454 22:56:02.644721 DQM0 = 12, DQM1 = 15
6455 22:56:02.646855 DQ Delay:
6456 22:56:02.650149 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6457 22:56:02.650846 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6458 22:56:02.653414 DQ8 =12, DQ9 =0, DQ10 =16, DQ11 =8
6459 22:56:02.656503 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =20
6460 22:56:02.656976
6461 22:56:02.660133
6462 22:56:02.667036 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaa3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6463 22:56:02.669909 CH0 RK0: MR19=C0C, MR18=AAA3
6464 22:56:02.676793 CH0_RK0: MR19=0xC0C, MR18=0xAAA3, DQSOSC=388, MR23=63, INC=392, DEC=261
6465 22:56:02.677430 ==
6466 22:56:02.680258 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 22:56:02.683450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 22:56:02.684016 ==
6469 22:56:02.686766 [Gating] SW mode calibration
6470 22:56:02.693487 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6471 22:56:02.697121 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6472 22:56:02.703365 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6473 22:56:02.706853 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6474 22:56:02.710581 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 22:56:02.716957 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6476 22:56:02.720279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 22:56:02.723680 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 22:56:02.730223 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 22:56:02.733440 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 22:56:02.737015 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 22:56:02.739952 Total UI for P1: 0, mck2ui 16
6482 22:56:02.743242 best dqsien dly found for B0: ( 0, 14, 24)
6483 22:56:02.746723 Total UI for P1: 0, mck2ui 16
6484 22:56:02.750074 best dqsien dly found for B1: ( 0, 14, 24)
6485 22:56:02.753251 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6486 22:56:02.756773 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6487 22:56:02.757392
6488 22:56:02.763590 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6489 22:56:02.767136 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6490 22:56:02.770111 [Gating] SW calibration Done
6491 22:56:02.770578 ==
6492 22:56:02.773685 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 22:56:02.776766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 22:56:02.777360 ==
6495 22:56:02.777876 RX Vref Scan: 0
6496 22:56:02.778380
6497 22:56:02.779796 RX Vref 0 -> 0, step: 1
6498 22:56:02.780264
6499 22:56:02.783661 RX Delay -410 -> 252, step: 16
6500 22:56:02.786977 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6501 22:56:02.789941 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6502 22:56:02.797143 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6503 22:56:02.800431 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6504 22:56:02.803403 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6505 22:56:02.807199 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6506 22:56:02.813750 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6507 22:56:02.816874 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6508 22:56:02.820476 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6509 22:56:02.823672 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6510 22:56:02.830170 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6511 22:56:02.833588 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6512 22:56:02.837060 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6513 22:56:02.840511 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6514 22:56:02.847044 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6515 22:56:02.849810 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6516 22:56:02.850301 ==
6517 22:56:02.853269 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 22:56:02.856742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 22:56:02.857354 ==
6520 22:56:02.859753 DQS Delay:
6521 22:56:02.860234 DQS0 = 27, DQS1 = 43
6522 22:56:02.863494 DQM Delay:
6523 22:56:02.863996 DQM0 = 9, DQM1 = 14
6524 22:56:02.864370 DQ Delay:
6525 22:56:02.866660 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6526 22:56:02.869688 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6527 22:56:02.873278 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6528 22:56:02.876709 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6529 22:56:02.877272
6530 22:56:02.877686
6531 22:56:02.878031 ==
6532 22:56:02.880149 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 22:56:02.886409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 22:56:02.886998 ==
6535 22:56:02.887387
6536 22:56:02.887732
6537 22:56:02.888066 TX Vref Scan disable
6538 22:56:02.889710 == TX Byte 0 ==
6539 22:56:02.893048 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6540 22:56:02.896371 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6541 22:56:02.900187 == TX Byte 1 ==
6542 22:56:02.903310 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6543 22:56:02.906227 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6544 22:56:02.906718 ==
6545 22:56:02.910073 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 22:56:02.916438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 22:56:02.916995 ==
6548 22:56:02.917418
6549 22:56:02.917776
6550 22:56:02.918112 TX Vref Scan disable
6551 22:56:02.920089 == TX Byte 0 ==
6552 22:56:02.922953 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6553 22:56:02.926530 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6554 22:56:02.929726 == TX Byte 1 ==
6555 22:56:02.933147 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6556 22:56:02.936702 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6557 22:56:02.937270
6558 22:56:02.939934 [DATLAT]
6559 22:56:02.940494 Freq=400, CH0 RK1
6560 22:56:02.940869
6561 22:56:02.943050 DATLAT Default: 0xe
6562 22:56:02.943518 0, 0xFFFF, sum = 0
6563 22:56:02.946245 1, 0xFFFF, sum = 0
6564 22:56:02.946720 2, 0xFFFF, sum = 0
6565 22:56:02.949639 3, 0xFFFF, sum = 0
6566 22:56:02.950112 4, 0xFFFF, sum = 0
6567 22:56:02.952871 5, 0xFFFF, sum = 0
6568 22:56:02.953366 6, 0xFFFF, sum = 0
6569 22:56:02.956387 7, 0xFFFF, sum = 0
6570 22:56:02.956958 8, 0xFFFF, sum = 0
6571 22:56:02.960129 9, 0xFFFF, sum = 0
6572 22:56:02.960720 10, 0xFFFF, sum = 0
6573 22:56:02.962936 11, 0xFFFF, sum = 0
6574 22:56:02.966160 12, 0xFFFF, sum = 0
6575 22:56:02.966637 13, 0x0, sum = 1
6576 22:56:02.967016 14, 0x0, sum = 2
6577 22:56:02.969877 15, 0x0, sum = 3
6578 22:56:02.970452 16, 0x0, sum = 4
6579 22:56:02.973093 best_step = 14
6580 22:56:02.973705
6581 22:56:02.974081 ==
6582 22:56:02.976618 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 22:56:02.979725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 22:56:02.980300 ==
6585 22:56:02.983165 RX Vref Scan: 0
6586 22:56:02.983724
6587 22:56:02.984098 RX Vref 0 -> 0, step: 1
6588 22:56:02.984440
6589 22:56:02.985815 RX Delay -327 -> 252, step: 8
6590 22:56:02.994321 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6591 22:56:02.997671 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6592 22:56:03.001019 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6593 22:56:03.004401 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6594 22:56:03.010948 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6595 22:56:03.014393 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6596 22:56:03.017944 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6597 22:56:03.021285 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6598 22:56:03.027668 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6599 22:56:03.031263 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6600 22:56:03.034125 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6601 22:56:03.037498 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6602 22:56:03.044625 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6603 22:56:03.047732 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6604 22:56:03.051035 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6605 22:56:03.054088 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6606 22:56:03.057737 ==
6607 22:56:03.061095 Dram Type= 6, Freq= 0, CH_0, rank 1
6608 22:56:03.064465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 22:56:03.065030 ==
6610 22:56:03.065467 DQS Delay:
6611 22:56:03.067799 DQS0 = 28, DQS1 = 44
6612 22:56:03.068363 DQM Delay:
6613 22:56:03.071184 DQM0 = 10, DQM1 = 15
6614 22:56:03.071748 DQ Delay:
6615 22:56:03.074002 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6616 22:56:03.077889 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6617 22:56:03.081167 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6618 22:56:03.084681 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6619 22:56:03.085247
6620 22:56:03.085654
6621 22:56:03.090903 [DQSOSCAuto] RK1, (LSB)MR18= 0xb96c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6622 22:56:03.094037 CH0 RK1: MR19=C0C, MR18=B96C
6623 22:56:03.101047 CH0_RK1: MR19=0xC0C, MR18=0xB96C, DQSOSC=386, MR23=63, INC=396, DEC=264
6624 22:56:03.104515 [RxdqsGatingPostProcess] freq 400
6625 22:56:03.108131 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6626 22:56:03.111085 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 22:56:03.114637 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 22:56:03.117632 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 22:56:03.121442 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 22:56:03.124170 best DQS0 dly(2T, 0.5T) = (0, 10)
6631 22:56:03.127460 best DQS1 dly(2T, 0.5T) = (0, 10)
6632 22:56:03.131106 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6633 22:56:03.134329 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6634 22:56:03.137793 Pre-setting of DQS Precalculation
6635 22:56:03.141106 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6636 22:56:03.141710 ==
6637 22:56:03.144139 Dram Type= 6, Freq= 0, CH_1, rank 0
6638 22:56:03.150809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 22:56:03.151378 ==
6640 22:56:03.154079 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6641 22:56:03.160873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6642 22:56:03.164302 [CA 0] Center 36 (8~64) winsize 57
6643 22:56:03.167865 [CA 1] Center 36 (8~64) winsize 57
6644 22:56:03.171046 [CA 2] Center 36 (8~64) winsize 57
6645 22:56:03.174203 [CA 3] Center 36 (8~64) winsize 57
6646 22:56:03.177720 [CA 4] Center 36 (8~64) winsize 57
6647 22:56:03.180723 [CA 5] Center 36 (8~64) winsize 57
6648 22:56:03.181194
6649 22:56:03.184246 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6650 22:56:03.184912
6651 22:56:03.187612 [CATrainingPosCal] consider 1 rank data
6652 22:56:03.191078 u2DelayCellTimex100 = 270/100 ps
6653 22:56:03.194057 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 22:56:03.197177 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 22:56:03.200946 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 22:56:03.204068 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 22:56:03.207959 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 22:56:03.210964 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 22:56:03.211588
6660 22:56:03.217157 CA PerBit enable=1, Macro0, CA PI delay=36
6661 22:56:03.217665
6662 22:56:03.220817 [CBTSetCACLKResult] CA Dly = 36
6663 22:56:03.221421 CS Dly: 1 (0~32)
6664 22:56:03.221803 ==
6665 22:56:03.223797 Dram Type= 6, Freq= 0, CH_1, rank 1
6666 22:56:03.227488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 22:56:03.227973 ==
6668 22:56:03.234241 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6669 22:56:03.241058 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6670 22:56:03.244438 [CA 0] Center 36 (8~64) winsize 57
6671 22:56:03.247634 [CA 1] Center 36 (8~64) winsize 57
6672 22:56:03.251047 [CA 2] Center 36 (8~64) winsize 57
6673 22:56:03.253650 [CA 3] Center 36 (8~64) winsize 57
6674 22:56:03.254242 [CA 4] Center 36 (8~64) winsize 57
6675 22:56:03.257147 [CA 5] Center 36 (8~64) winsize 57
6676 22:56:03.257777
6677 22:56:03.263689 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6678 22:56:03.264156
6679 22:56:03.267399 [CATrainingPosCal] consider 2 rank data
6680 22:56:03.270757 u2DelayCellTimex100 = 270/100 ps
6681 22:56:03.273912 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 22:56:03.277262 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 22:56:03.280688 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 22:56:03.284017 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 22:56:03.287385 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 22:56:03.290382 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 22:56:03.290856
6688 22:56:03.294026 CA PerBit enable=1, Macro0, CA PI delay=36
6689 22:56:03.294588
6690 22:56:03.297405 [CBTSetCACLKResult] CA Dly = 36
6691 22:56:03.300700 CS Dly: 1 (0~32)
6692 22:56:03.301266
6693 22:56:03.304101 ----->DramcWriteLeveling(PI) begin...
6694 22:56:03.304673 ==
6695 22:56:03.307147 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 22:56:03.310415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 22:56:03.311001 ==
6698 22:56:03.313623 Write leveling (Byte 0): 40 => 8
6699 22:56:03.317025 Write leveling (Byte 1): 32 => 0
6700 22:56:03.320765 DramcWriteLeveling(PI) end<-----
6701 22:56:03.321373
6702 22:56:03.321763 ==
6703 22:56:03.323898 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 22:56:03.326835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 22:56:03.327308 ==
6706 22:56:03.330687 [Gating] SW mode calibration
6707 22:56:03.337405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6708 22:56:03.344010 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6709 22:56:03.346767 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6710 22:56:03.350125 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6711 22:56:03.357619 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 22:56:03.360242 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6713 22:56:03.363729 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 22:56:03.370195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 22:56:03.373619 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 22:56:03.376883 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 22:56:03.383860 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 22:56:03.384432 Total UI for P1: 0, mck2ui 16
6719 22:56:03.390376 best dqsien dly found for B0: ( 0, 14, 24)
6720 22:56:03.390950 Total UI for P1: 0, mck2ui 16
6721 22:56:03.397093 best dqsien dly found for B1: ( 0, 14, 24)
6722 22:56:03.399895 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6723 22:56:03.403521 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6724 22:56:03.404093
6725 22:56:03.406929 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6726 22:56:03.410027 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6727 22:56:03.413601 [Gating] SW calibration Done
6728 22:56:03.414175 ==
6729 22:56:03.416506 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 22:56:03.420214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 22:56:03.420876 ==
6732 22:56:03.423681 RX Vref Scan: 0
6733 22:56:03.424242
6734 22:56:03.424609 RX Vref 0 -> 0, step: 1
6735 22:56:03.424950
6736 22:56:03.426695 RX Delay -410 -> 252, step: 16
6737 22:56:03.433624 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6738 22:56:03.436607 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6739 22:56:03.439800 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6740 22:56:03.443593 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6741 22:56:03.450241 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6742 22:56:03.453662 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6743 22:56:03.456761 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6744 22:56:03.460433 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6745 22:56:03.466930 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6746 22:56:03.470015 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6747 22:56:03.473616 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6748 22:56:03.477018 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6749 22:56:03.483808 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6750 22:56:03.487178 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6751 22:56:03.489945 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6752 22:56:03.493661 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6753 22:56:03.494288 ==
6754 22:56:03.496966 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 22:56:03.503592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 22:56:03.504161 ==
6757 22:56:03.504538 DQS Delay:
6758 22:56:03.507153 DQS0 = 27, DQS1 = 43
6759 22:56:03.507718 DQM Delay:
6760 22:56:03.508094 DQM0 = 5, DQM1 = 16
6761 22:56:03.510111 DQ Delay:
6762 22:56:03.513638 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6763 22:56:03.514203 DQ4 =0, DQ5 =8, DQ6 =16, DQ7 =0
6764 22:56:03.516770 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6765 22:56:03.520060 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6766 22:56:03.520537
6767 22:56:03.523197
6768 22:56:03.523758 ==
6769 22:56:03.526660 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 22:56:03.529983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 22:56:03.530464 ==
6772 22:56:03.530838
6773 22:56:03.531183
6774 22:56:03.533348 TX Vref Scan disable
6775 22:56:03.533841 == TX Byte 0 ==
6776 22:56:03.536561 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 22:56:03.543498 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 22:56:03.544067 == TX Byte 1 ==
6779 22:56:03.546557 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6780 22:56:03.553711 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6781 22:56:03.554484 ==
6782 22:56:03.556471 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 22:56:03.559972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 22:56:03.560543 ==
6785 22:56:03.560914
6786 22:56:03.561250
6787 22:56:03.563648 TX Vref Scan disable
6788 22:56:03.564206 == TX Byte 0 ==
6789 22:56:03.569664 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 22:56:03.572796 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 22:56:03.573261 == TX Byte 1 ==
6792 22:56:03.579637 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6793 22:56:03.582890 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6794 22:56:03.583465
6795 22:56:03.583836 [DATLAT]
6796 22:56:03.586147 Freq=400, CH1 RK0
6797 22:56:03.586684
6798 22:56:03.587056 DATLAT Default: 0xf
6799 22:56:03.589630 0, 0xFFFF, sum = 0
6800 22:56:03.590229 1, 0xFFFF, sum = 0
6801 22:56:03.592922 2, 0xFFFF, sum = 0
6802 22:56:03.593452 3, 0xFFFF, sum = 0
6803 22:56:03.596326 4, 0xFFFF, sum = 0
6804 22:56:03.596913 5, 0xFFFF, sum = 0
6805 22:56:03.599331 6, 0xFFFF, sum = 0
6806 22:56:03.599821 7, 0xFFFF, sum = 0
6807 22:56:03.602737 8, 0xFFFF, sum = 0
6808 22:56:03.603323 9, 0xFFFF, sum = 0
6809 22:56:03.606117 10, 0xFFFF, sum = 0
6810 22:56:03.609522 11, 0xFFFF, sum = 0
6811 22:56:03.610101 12, 0xFFFF, sum = 0
6812 22:56:03.612860 13, 0x0, sum = 1
6813 22:56:03.613503 14, 0x0, sum = 2
6814 22:56:03.613999 15, 0x0, sum = 3
6815 22:56:03.616203 16, 0x0, sum = 4
6816 22:56:03.616791 best_step = 14
6817 22:56:03.617279
6818 22:56:03.619185 ==
6819 22:56:03.619666 Dram Type= 6, Freq= 0, CH_1, rank 0
6820 22:56:03.626087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 22:56:03.626656 ==
6822 22:56:03.627148 RX Vref Scan: 1
6823 22:56:03.627597
6824 22:56:03.629023 RX Vref 0 -> 0, step: 1
6825 22:56:03.629510
6826 22:56:03.632530 RX Delay -327 -> 252, step: 8
6827 22:56:03.632994
6828 22:56:03.635762 Set Vref, RX VrefLevel [Byte0]: 50
6829 22:56:03.638786 [Byte1]: 53
6830 22:56:03.642663
6831 22:56:03.643228 Final RX Vref Byte 0 = 50 to rank0
6832 22:56:03.645825 Final RX Vref Byte 1 = 53 to rank0
6833 22:56:03.649171 Final RX Vref Byte 0 = 50 to rank1
6834 22:56:03.652516 Final RX Vref Byte 1 = 53 to rank1==
6835 22:56:03.655519 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 22:56:03.662399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 22:56:03.662971 ==
6838 22:56:03.663387 DQS Delay:
6839 22:56:03.665740 DQS0 = 32, DQS1 = 40
6840 22:56:03.666205 DQM Delay:
6841 22:56:03.666566 DQM0 = 11, DQM1 = 12
6842 22:56:03.669240 DQ Delay:
6843 22:56:03.672528 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6844 22:56:03.676005 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6845 22:56:03.676569 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6846 22:56:03.679550 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6847 22:56:03.680122
6848 22:56:03.682386
6849 22:56:03.689060 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ed9, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6850 22:56:03.692409 CH1 RK0: MR19=C0C, MR18=9ED9
6851 22:56:03.699007 CH1_RK0: MR19=0xC0C, MR18=0x9ED9, DQSOSC=383, MR23=63, INC=402, DEC=268
6852 22:56:03.699560 ==
6853 22:56:03.702178 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 22:56:03.705733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 22:56:03.706308 ==
6856 22:56:03.709158 [Gating] SW mode calibration
6857 22:56:03.715905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6858 22:56:03.722188 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6859 22:56:03.725624 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6860 22:56:03.728727 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6861 22:56:03.735732 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 22:56:03.738728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6863 22:56:03.741900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 22:56:03.745400 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 22:56:03.752624 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 22:56:03.755687 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 22:56:03.758593 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 22:56:03.762298 Total UI for P1: 0, mck2ui 16
6869 22:56:03.765587 best dqsien dly found for B0: ( 0, 14, 24)
6870 22:56:03.768981 Total UI for P1: 0, mck2ui 16
6871 22:56:03.772363 best dqsien dly found for B1: ( 0, 14, 24)
6872 22:56:03.775645 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6873 22:56:03.781972 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6874 22:56:03.782446
6875 22:56:03.785151 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6876 22:56:03.788667 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6877 22:56:03.792141 [Gating] SW calibration Done
6878 22:56:03.792808 ==
6879 22:56:03.795393 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 22:56:03.798871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 22:56:03.799413 ==
6882 22:56:03.799791 RX Vref Scan: 0
6883 22:56:03.801757
6884 22:56:03.802220 RX Vref 0 -> 0, step: 1
6885 22:56:03.802589
6886 22:56:03.805026 RX Delay -410 -> 252, step: 16
6887 22:56:03.808627 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6888 22:56:03.815105 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6889 22:56:03.818212 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6890 22:56:03.821844 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6891 22:56:03.825429 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6892 22:56:03.831788 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6893 22:56:03.835060 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6894 22:56:03.838337 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6895 22:56:03.841915 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6896 22:56:03.848129 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6897 22:56:03.851764 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6898 22:56:03.854968 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6899 22:56:03.858116 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6900 22:56:03.865233 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6901 22:56:03.868328 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6902 22:56:03.871670 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6903 22:56:03.872299 ==
6904 22:56:03.875080 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 22:56:03.881790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 22:56:03.882259 ==
6907 22:56:03.882627 DQS Delay:
6908 22:56:03.884829 DQS0 = 35, DQS1 = 43
6909 22:56:03.885288 DQM Delay:
6910 22:56:03.885711 DQM0 = 16, DQM1 = 18
6911 22:56:03.888521 DQ Delay:
6912 22:56:03.891731 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6913 22:56:03.894982 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6914 22:56:03.895458 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6915 22:56:03.901450 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6916 22:56:03.901928
6917 22:56:03.902296
6918 22:56:03.902641 ==
6919 22:56:03.904656 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 22:56:03.908194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 22:56:03.908671 ==
6922 22:56:03.909045
6923 22:56:03.909439
6924 22:56:03.911387 TX Vref Scan disable
6925 22:56:03.911815 == TX Byte 0 ==
6926 22:56:03.915005 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6927 22:56:03.921268 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6928 22:56:03.921838 == TX Byte 1 ==
6929 22:56:03.924708 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6930 22:56:03.931603 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6931 22:56:03.932033 ==
6932 22:56:03.935028 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 22:56:03.938207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 22:56:03.938639 ==
6935 22:56:03.938979
6936 22:56:03.939288
6937 22:56:03.941496 TX Vref Scan disable
6938 22:56:03.941925 == TX Byte 0 ==
6939 22:56:03.944946 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6940 22:56:03.951248 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6941 22:56:03.951681 == TX Byte 1 ==
6942 22:56:03.954819 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6943 22:56:03.961183 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6944 22:56:03.961661
6945 22:56:03.961995 [DATLAT]
6946 22:56:03.962302 Freq=400, CH1 RK1
6947 22:56:03.964647
6948 22:56:03.965062 DATLAT Default: 0xe
6949 22:56:03.968096 0, 0xFFFF, sum = 0
6950 22:56:03.968525 1, 0xFFFF, sum = 0
6951 22:56:03.971521 2, 0xFFFF, sum = 0
6952 22:56:03.971947 3, 0xFFFF, sum = 0
6953 22:56:03.974893 4, 0xFFFF, sum = 0
6954 22:56:03.975419 5, 0xFFFF, sum = 0
6955 22:56:03.978332 6, 0xFFFF, sum = 0
6956 22:56:03.978858 7, 0xFFFF, sum = 0
6957 22:56:03.981647 8, 0xFFFF, sum = 0
6958 22:56:03.982075 9, 0xFFFF, sum = 0
6959 22:56:03.984620 10, 0xFFFF, sum = 0
6960 22:56:03.985048 11, 0xFFFF, sum = 0
6961 22:56:03.987833 12, 0xFFFF, sum = 0
6962 22:56:03.988257 13, 0x0, sum = 1
6963 22:56:03.991161 14, 0x0, sum = 2
6964 22:56:03.991630 15, 0x0, sum = 3
6965 22:56:03.995017 16, 0x0, sum = 4
6966 22:56:03.995443 best_step = 14
6967 22:56:03.995853
6968 22:56:03.996214 ==
6969 22:56:03.998025 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 22:56:04.001156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 22:56:04.005068 ==
6972 22:56:04.005557 RX Vref Scan: 0
6973 22:56:04.005997
6974 22:56:04.008157 RX Vref 0 -> 0, step: 1
6975 22:56:04.008782
6976 22:56:04.011312 RX Delay -327 -> 252, step: 8
6977 22:56:04.017887 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6978 22:56:04.021444 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6979 22:56:04.024363 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6980 22:56:04.027623 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6981 22:56:04.034804 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6982 22:56:04.037617 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6983 22:56:04.041060 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6984 22:56:04.044227 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6985 22:56:04.047774 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6986 22:56:04.054344 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6987 22:56:04.057427 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6988 22:56:04.061179 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6989 22:56:04.067808 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6990 22:56:04.071546 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6991 22:56:04.074593 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6992 22:56:04.077836 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6993 22:56:04.078268 ==
6994 22:56:04.081278 Dram Type= 6, Freq= 0, CH_1, rank 1
6995 22:56:04.088126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6996 22:56:04.088659 ==
6997 22:56:04.089003 DQS Delay:
6998 22:56:04.091178 DQS0 = 32, DQS1 = 36
6999 22:56:04.091602 DQM Delay:
7000 22:56:04.093945 DQM0 = 12, DQM1 = 11
7001 22:56:04.094366 DQ Delay:
7002 22:56:04.097676 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7003 22:56:04.101031 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =8
7004 22:56:04.101494 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7005 22:56:04.107750 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7006 22:56:04.108272
7007 22:56:04.108637
7008 22:56:04.114247 [DQSOSCAuto] RK1, (LSB)MR18= 0xb15a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
7009 22:56:04.117838 CH1 RK1: MR19=C0C, MR18=B15A
7010 22:56:04.124337 CH1_RK1: MR19=0xC0C, MR18=0xB15A, DQSOSC=387, MR23=63, INC=394, DEC=262
7011 22:56:04.127401 [RxdqsGatingPostProcess] freq 400
7012 22:56:04.130977 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7013 22:56:04.134235 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 22:56:04.137573 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 22:56:04.141331 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 22:56:04.144163 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 22:56:04.147403 best DQS0 dly(2T, 0.5T) = (0, 10)
7018 22:56:04.150893 best DQS1 dly(2T, 0.5T) = (0, 10)
7019 22:56:04.154720 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7020 22:56:04.157529 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7021 22:56:04.160633 Pre-setting of DQS Precalculation
7022 22:56:04.164467 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7023 22:56:04.170895 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7024 22:56:04.181038 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7025 22:56:04.181635
7026 22:56:04.182000
7027 22:56:04.183935 [Calibration Summary] 800 Mbps
7028 22:56:04.184407 CH 0, Rank 0
7029 22:56:04.187742 SW Impedance : PASS
7030 22:56:04.188317 DUTY Scan : NO K
7031 22:56:04.191056 ZQ Calibration : PASS
7032 22:56:04.194038 Jitter Meter : NO K
7033 22:56:04.194614 CBT Training : PASS
7034 22:56:04.197138 Write leveling : PASS
7035 22:56:04.197625 RX DQS gating : PASS
7036 22:56:04.200796 RX DQ/DQS(RDDQC) : PASS
7037 22:56:04.204466 TX DQ/DQS : PASS
7038 22:56:04.205038 RX DATLAT : PASS
7039 22:56:04.207477 RX DQ/DQS(Engine): PASS
7040 22:56:04.210653 TX OE : NO K
7041 22:56:04.211355 All Pass.
7042 22:56:04.211767
7043 22:56:04.212419 CH 0, Rank 1
7044 22:56:04.213812 SW Impedance : PASS
7045 22:56:04.216960 DUTY Scan : NO K
7046 22:56:04.217465 ZQ Calibration : PASS
7047 22:56:04.220140 Jitter Meter : NO K
7048 22:56:04.223771 CBT Training : PASS
7049 22:56:04.224499 Write leveling : NO K
7050 22:56:04.226853 RX DQS gating : PASS
7051 22:56:04.230192 RX DQ/DQS(RDDQC) : PASS
7052 22:56:04.230686 TX DQ/DQS : PASS
7053 22:56:04.233468 RX DATLAT : PASS
7054 22:56:04.236612 RX DQ/DQS(Engine): PASS
7055 22:56:04.237077 TX OE : NO K
7056 22:56:04.240210 All Pass.
7057 22:56:04.240677
7058 22:56:04.241040 CH 1, Rank 0
7059 22:56:04.243520 SW Impedance : PASS
7060 22:56:04.243947 DUTY Scan : NO K
7061 22:56:04.246952 ZQ Calibration : PASS
7062 22:56:04.250119 Jitter Meter : NO K
7063 22:56:04.250617 CBT Training : PASS
7064 22:56:04.253461 Write leveling : PASS
7065 22:56:04.253885 RX DQS gating : PASS
7066 22:56:04.256827 RX DQ/DQS(RDDQC) : PASS
7067 22:56:04.260350 TX DQ/DQS : PASS
7068 22:56:04.260776 RX DATLAT : PASS
7069 22:56:04.263376 RX DQ/DQS(Engine): PASS
7070 22:56:04.267018 TX OE : NO K
7071 22:56:04.267446 All Pass.
7072 22:56:04.267775
7073 22:56:04.268083 CH 1, Rank 1
7074 22:56:04.270452 SW Impedance : PASS
7075 22:56:04.273458 DUTY Scan : NO K
7076 22:56:04.273881 ZQ Calibration : PASS
7077 22:56:04.276991 Jitter Meter : NO K
7078 22:56:04.280490 CBT Training : PASS
7079 22:56:04.280917 Write leveling : NO K
7080 22:56:04.283385 RX DQS gating : PASS
7081 22:56:04.286979 RX DQ/DQS(RDDQC) : PASS
7082 22:56:04.287515 TX DQ/DQS : PASS
7083 22:56:04.290036 RX DATLAT : PASS
7084 22:56:04.293558 RX DQ/DQS(Engine): PASS
7085 22:56:04.294027 TX OE : NO K
7086 22:56:04.294368 All Pass.
7087 22:56:04.296888
7088 22:56:04.297460 DramC Write-DBI off
7089 22:56:04.300269 PER_BANK_REFRESH: Hybrid Mode
7090 22:56:04.300830 TX_TRACKING: ON
7091 22:56:04.310011 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7092 22:56:04.313475 [FAST_K] Save calibration result to emmc
7093 22:56:04.316961 dramc_set_vcore_voltage set vcore to 725000
7094 22:56:04.319907 Read voltage for 1600, 0
7095 22:56:04.320335 Vio18 = 0
7096 22:56:04.323264 Vcore = 725000
7097 22:56:04.323794 Vdram = 0
7098 22:56:04.324129 Vddq = 0
7099 22:56:04.324439 Vmddr = 0
7100 22:56:04.329965 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7101 22:56:04.336820 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7102 22:56:04.337529 MEM_TYPE=3, freq_sel=13
7103 22:56:04.339863 sv_algorithm_assistance_LP4_3733
7104 22:56:04.343726 ============ PULL DRAM RESETB DOWN ============
7105 22:56:04.350038 ========== PULL DRAM RESETB DOWN end =========
7106 22:56:04.353554 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7107 22:56:04.356541 ===================================
7108 22:56:04.359737 LPDDR4 DRAM CONFIGURATION
7109 22:56:04.362946 ===================================
7110 22:56:04.363419 EX_ROW_EN[0] = 0x0
7111 22:56:04.366135 EX_ROW_EN[1] = 0x0
7112 22:56:04.369412 LP4Y_EN = 0x0
7113 22:56:04.369885 WORK_FSP = 0x1
7114 22:56:04.373088 WL = 0x5
7115 22:56:04.373665 RL = 0x5
7116 22:56:04.376508 BL = 0x2
7117 22:56:04.377087 RPST = 0x0
7118 22:56:04.379799 RD_PRE = 0x0
7119 22:56:04.380380 WR_PRE = 0x1
7120 22:56:04.382940 WR_PST = 0x1
7121 22:56:04.383580 DBI_WR = 0x0
7122 22:56:04.386613 DBI_RD = 0x0
7123 22:56:04.387190 OTF = 0x1
7124 22:56:04.389761 ===================================
7125 22:56:04.393187 ===================================
7126 22:56:04.396550 ANA top config
7127 22:56:04.399548 ===================================
7128 22:56:04.400127 DLL_ASYNC_EN = 0
7129 22:56:04.403217 ALL_SLAVE_EN = 0
7130 22:56:04.406309 NEW_RANK_MODE = 1
7131 22:56:04.409634 DLL_IDLE_MODE = 1
7132 22:56:04.410107 LP45_APHY_COMB_EN = 1
7133 22:56:04.413117 TX_ODT_DIS = 0
7134 22:56:04.416496 NEW_8X_MODE = 1
7135 22:56:04.419302 ===================================
7136 22:56:04.423247 ===================================
7137 22:56:04.426420 data_rate = 3200
7138 22:56:04.429447 CKR = 1
7139 22:56:04.433237 DQ_P2S_RATIO = 8
7140 22:56:04.435926 ===================================
7141 22:56:04.436501 CA_P2S_RATIO = 8
7142 22:56:04.439445 DQ_CA_OPEN = 0
7143 22:56:04.442574 DQ_SEMI_OPEN = 0
7144 22:56:04.446107 CA_SEMI_OPEN = 0
7145 22:56:04.449682 CA_FULL_RATE = 0
7146 22:56:04.452576 DQ_CKDIV4_EN = 0
7147 22:56:04.453049 CA_CKDIV4_EN = 0
7148 22:56:04.456460 CA_PREDIV_EN = 0
7149 22:56:04.459296 PH8_DLY = 12
7150 22:56:04.462465 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7151 22:56:04.465911 DQ_AAMCK_DIV = 4
7152 22:56:04.469545 CA_AAMCK_DIV = 4
7153 22:56:04.470116 CA_ADMCK_DIV = 4
7154 22:56:04.472776 DQ_TRACK_CA_EN = 0
7155 22:56:04.476160 CA_PICK = 1600
7156 22:56:04.479719 CA_MCKIO = 1600
7157 22:56:04.482559 MCKIO_SEMI = 0
7158 22:56:04.486090 PLL_FREQ = 3068
7159 22:56:04.489280 DQ_UI_PI_RATIO = 32
7160 22:56:04.489774 CA_UI_PI_RATIO = 0
7161 22:56:04.492610 ===================================
7162 22:56:04.495941 ===================================
7163 22:56:04.499444 memory_type:LPDDR4
7164 22:56:04.502645 GP_NUM : 10
7165 22:56:04.503329 SRAM_EN : 1
7166 22:56:04.506266 MD32_EN : 0
7167 22:56:04.509593 ===================================
7168 22:56:04.512521 [ANA_INIT] >>>>>>>>>>>>>>
7169 22:56:04.515786 <<<<<< [CONFIGURE PHASE]: ANA_TX
7170 22:56:04.519120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7171 22:56:04.522378 ===================================
7172 22:56:04.522933 data_rate = 3200,PCW = 0X7600
7173 22:56:04.525993 ===================================
7174 22:56:04.529343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7175 22:56:04.535534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7176 22:56:04.542154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7177 22:56:04.546112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7178 22:56:04.548695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7179 22:56:04.552506 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7180 22:56:04.555878 [ANA_INIT] flow start
7181 22:56:04.559181 [ANA_INIT] PLL >>>>>>>>
7182 22:56:04.559854 [ANA_INIT] PLL <<<<<<<<
7183 22:56:04.562299 [ANA_INIT] MIDPI >>>>>>>>
7184 22:56:04.565340 [ANA_INIT] MIDPI <<<<<<<<
7185 22:56:04.565813 [ANA_INIT] DLL >>>>>>>>
7186 22:56:04.568822 [ANA_INIT] DLL <<<<<<<<
7187 22:56:04.572180 [ANA_INIT] flow end
7188 22:56:04.575666 ============ LP4 DIFF to SE enter ============
7189 22:56:04.578921 ============ LP4 DIFF to SE exit ============
7190 22:56:04.582171 [ANA_INIT] <<<<<<<<<<<<<
7191 22:56:04.585460 [Flow] Enable top DCM control >>>>>
7192 22:56:04.588915 [Flow] Enable top DCM control <<<<<
7193 22:56:04.592542 Enable DLL master slave shuffle
7194 22:56:04.595202 ==============================================================
7195 22:56:04.598811 Gating Mode config
7196 22:56:04.605672 ==============================================================
7197 22:56:04.606242 Config description:
7198 22:56:04.615329 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7199 22:56:04.622295 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7200 22:56:04.625424 SELPH_MODE 0: By rank 1: By Phase
7201 22:56:04.631961 ==============================================================
7202 22:56:04.635375 GAT_TRACK_EN = 1
7203 22:56:04.639026 RX_GATING_MODE = 2
7204 22:56:04.642146 RX_GATING_TRACK_MODE = 2
7205 22:56:04.645293 SELPH_MODE = 1
7206 22:56:04.648458 PICG_EARLY_EN = 1
7207 22:56:04.651521 VALID_LAT_VALUE = 1
7208 22:56:04.655306 ==============================================================
7209 22:56:04.658465 Enter into Gating configuration >>>>
7210 22:56:04.661815 Exit from Gating configuration <<<<
7211 22:56:04.665055 Enter into DVFS_PRE_config >>>>>
7212 22:56:04.675036 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7213 22:56:04.678454 Exit from DVFS_PRE_config <<<<<
7214 22:56:04.681837 Enter into PICG configuration >>>>
7215 22:56:04.685269 Exit from PICG configuration <<<<
7216 22:56:04.688097 [RX_INPUT] configuration >>>>>
7217 22:56:04.691758 [RX_INPUT] configuration <<<<<
7218 22:56:04.698207 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7219 22:56:04.701718 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7220 22:56:04.708384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7221 22:56:04.715236 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7222 22:56:04.721632 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7223 22:56:04.728611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7224 22:56:04.731581 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7225 22:56:04.735023 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7226 22:56:04.738385 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7227 22:56:04.745417 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7228 22:56:04.748215 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7229 22:56:04.751924 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7230 22:56:04.755127 ===================================
7231 22:56:04.758222 LPDDR4 DRAM CONFIGURATION
7232 22:56:04.761705 ===================================
7233 22:56:04.762321 EX_ROW_EN[0] = 0x0
7234 22:56:04.764640 EX_ROW_EN[1] = 0x0
7235 22:56:04.765196 LP4Y_EN = 0x0
7236 22:56:04.768488 WORK_FSP = 0x1
7237 22:56:04.771311 WL = 0x5
7238 22:56:04.771879 RL = 0x5
7239 22:56:04.775194 BL = 0x2
7240 22:56:04.775763 RPST = 0x0
7241 22:56:04.778011 RD_PRE = 0x0
7242 22:56:04.778522 WR_PRE = 0x1
7243 22:56:04.781455 WR_PST = 0x1
7244 22:56:04.781919 DBI_WR = 0x0
7245 22:56:04.784893 DBI_RD = 0x0
7246 22:56:04.785555 OTF = 0x1
7247 22:56:04.788352 ===================================
7248 22:56:04.791712 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7249 22:56:04.798019 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7250 22:56:04.801456 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7251 22:56:04.804660 ===================================
7252 22:56:04.808014 LPDDR4 DRAM CONFIGURATION
7253 22:56:04.811347 ===================================
7254 22:56:04.811914 EX_ROW_EN[0] = 0x10
7255 22:56:04.815135 EX_ROW_EN[1] = 0x0
7256 22:56:04.815697 LP4Y_EN = 0x0
7257 22:56:04.818085 WORK_FSP = 0x1
7258 22:56:04.818649 WL = 0x5
7259 22:56:04.821447 RL = 0x5
7260 22:56:04.822010 BL = 0x2
7261 22:56:04.824757 RPST = 0x0
7262 22:56:04.828009 RD_PRE = 0x0
7263 22:56:04.828574 WR_PRE = 0x1
7264 22:56:04.831008 WR_PST = 0x1
7265 22:56:04.831469 DBI_WR = 0x0
7266 22:56:04.834573 DBI_RD = 0x0
7267 22:56:04.835137 OTF = 0x1
7268 22:56:04.837679 ===================================
7269 22:56:04.844185 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7270 22:56:04.844694 ==
7271 22:56:04.849473 Dram Type= 6, Freq= 0, CH_0, rank 0
7272 22:56:04.850772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7273 22:56:04.851238 ==
7274 22:56:04.854463 [Duty_Offset_Calibration]
7275 22:56:04.857766 B0:2 B1:0 CA:1
7276 22:56:04.858231
7277 22:56:04.860772 [DutyScan_Calibration_Flow] k_type=0
7278 22:56:04.868936
7279 22:56:04.869540 ==CLK 0==
7280 22:56:04.872161 Final CLK duty delay cell = -4
7281 22:56:04.875505 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7282 22:56:04.878475 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7283 22:56:04.882045 [-4] AVG Duty = 4906%(X100)
7284 22:56:04.882611
7285 22:56:04.885347 CH0 CLK Duty spec in!! Max-Min= 187%
7286 22:56:04.888684 [DutyScan_Calibration_Flow] ====Done====
7287 22:56:04.889247
7288 22:56:04.891732 [DutyScan_Calibration_Flow] k_type=1
7289 22:56:04.908176
7290 22:56:04.908739 ==DQS 0 ==
7291 22:56:04.911757 Final DQS duty delay cell = 0
7292 22:56:04.914841 [0] MAX Duty = 5249%(X100), DQS PI = 34
7293 22:56:04.918055 [0] MIN Duty = 4938%(X100), DQS PI = 62
7294 22:56:04.918624 [0] AVG Duty = 5093%(X100)
7295 22:56:04.921407
7296 22:56:04.921961 ==DQS 1 ==
7297 22:56:04.924723 Final DQS duty delay cell = -4
7298 22:56:04.928164 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7299 22:56:04.931178 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7300 22:56:04.934563 [-4] AVG Duty = 4984%(X100)
7301 22:56:04.935132
7302 22:56:04.938275 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7303 22:56:04.938741
7304 22:56:04.940931 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7305 22:56:04.944741 [DutyScan_Calibration_Flow] ====Done====
7306 22:56:04.945366
7307 22:56:04.947756 [DutyScan_Calibration_Flow] k_type=3
7308 22:56:04.965728
7309 22:56:04.966287 ==DQM 0 ==
7310 22:56:04.969094 Final DQM duty delay cell = 0
7311 22:56:04.972353 [0] MAX Duty = 5062%(X100), DQS PI = 26
7312 22:56:04.975808 [0] MIN Duty = 4813%(X100), DQS PI = 50
7313 22:56:04.979115 [0] AVG Duty = 4937%(X100)
7314 22:56:04.979680
7315 22:56:04.980185 ==DQM 1 ==
7316 22:56:04.981798 Final DQM duty delay cell = 0
7317 22:56:04.985474 [0] MAX Duty = 5249%(X100), DQS PI = 44
7318 22:56:04.988812 [0] MIN Duty = 5000%(X100), DQS PI = 20
7319 22:56:04.991920 [0] AVG Duty = 5124%(X100)
7320 22:56:04.992396
7321 22:56:04.995434 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7322 22:56:04.995959
7323 22:56:04.998412 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7324 22:56:05.001937 [DutyScan_Calibration_Flow] ====Done====
7325 22:56:05.002518
7326 22:56:05.005544 [DutyScan_Calibration_Flow] k_type=2
7327 22:56:05.022921
7328 22:56:05.023494 ==DQ 0 ==
7329 22:56:05.026203 Final DQ duty delay cell = 0
7330 22:56:05.029484 [0] MAX Duty = 5124%(X100), DQS PI = 34
7331 22:56:05.032808 [0] MIN Duty = 5000%(X100), DQS PI = 0
7332 22:56:05.033272 [0] AVG Duty = 5062%(X100)
7333 22:56:05.033692
7334 22:56:05.035865 ==DQ 1 ==
7335 22:56:05.039427 Final DQ duty delay cell = 0
7336 22:56:05.042498 [0] MAX Duty = 4969%(X100), DQS PI = 52
7337 22:56:05.046002 [0] MIN Duty = 4875%(X100), DQS PI = 0
7338 22:56:05.046463 [0] AVG Duty = 4922%(X100)
7339 22:56:05.046818
7340 22:56:05.049243 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7341 22:56:05.049779
7342 22:56:05.052769 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7343 22:56:05.059615 [DutyScan_Calibration_Flow] ====Done====
7344 22:56:05.060180 ==
7345 22:56:05.062659 Dram Type= 6, Freq= 0, CH_1, rank 0
7346 22:56:05.065711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7347 22:56:05.066176 ==
7348 22:56:05.069208 [Duty_Offset_Calibration]
7349 22:56:05.069710 B0:0 B1:-1 CA:2
7350 22:56:05.070079
7351 22:56:05.072448 [DutyScan_Calibration_Flow] k_type=0
7352 22:56:05.082812
7353 22:56:05.083368 ==CLK 0==
7354 22:56:05.086293 Final CLK duty delay cell = 0
7355 22:56:05.089368 [0] MAX Duty = 5156%(X100), DQS PI = 10
7356 22:56:05.093227 [0] MIN Duty = 4906%(X100), DQS PI = 46
7357 22:56:05.093844 [0] AVG Duty = 5031%(X100)
7358 22:56:05.096082
7359 22:56:05.099966 CH1 CLK Duty spec in!! Max-Min= 250%
7360 22:56:05.102520 [DutyScan_Calibration_Flow] ====Done====
7361 22:56:05.102982
7362 22:56:05.106191 [DutyScan_Calibration_Flow] k_type=1
7363 22:56:05.122890
7364 22:56:05.123451 ==DQS 0 ==
7365 22:56:05.126156 Final DQS duty delay cell = 0
7366 22:56:05.129717 [0] MAX Duty = 5093%(X100), DQS PI = 26
7367 22:56:05.132578 [0] MIN Duty = 4969%(X100), DQS PI = 0
7368 22:56:05.133037 [0] AVG Duty = 5031%(X100)
7369 22:56:05.135752
7370 22:56:05.136209 ==DQS 1 ==
7371 22:56:05.139518 Final DQS duty delay cell = 0
7372 22:56:05.142459 [0] MAX Duty = 5187%(X100), DQS PI = 0
7373 22:56:05.145993 [0] MIN Duty = 4844%(X100), DQS PI = 32
7374 22:56:05.146556 [0] AVG Duty = 5015%(X100)
7375 22:56:05.149083
7376 22:56:05.152512 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7377 22:56:05.153068
7378 22:56:05.156186 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7379 22:56:05.159438 [DutyScan_Calibration_Flow] ====Done====
7380 22:56:05.159990
7381 22:56:05.162111 [DutyScan_Calibration_Flow] k_type=3
7382 22:56:05.180251
7383 22:56:05.180795 ==DQM 0 ==
7384 22:56:05.183665 Final DQM duty delay cell = 4
7385 22:56:05.186834 [4] MAX Duty = 5125%(X100), DQS PI = 24
7386 22:56:05.190107 [4] MIN Duty = 4938%(X100), DQS PI = 46
7387 22:56:05.193725 [4] AVG Duty = 5031%(X100)
7388 22:56:05.194276
7389 22:56:05.194633 ==DQM 1 ==
7390 22:56:05.196564 Final DQM duty delay cell = 0
7391 22:56:05.200174 [0] MAX Duty = 5281%(X100), DQS PI = 58
7392 22:56:05.203154 [0] MIN Duty = 4876%(X100), DQS PI = 34
7393 22:56:05.206888 [0] AVG Duty = 5078%(X100)
7394 22:56:05.207454
7395 22:56:05.210218 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7396 22:56:05.210691
7397 22:56:05.213562 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7398 22:56:05.216766 [DutyScan_Calibration_Flow] ====Done====
7399 22:56:05.217373
7400 22:56:05.220255 [DutyScan_Calibration_Flow] k_type=2
7401 22:56:05.237475
7402 22:56:05.238042 ==DQ 0 ==
7403 22:56:05.240755 Final DQ duty delay cell = 0
7404 22:56:05.244117 [0] MAX Duty = 5062%(X100), DQS PI = 20
7405 22:56:05.246675 [0] MIN Duty = 4969%(X100), DQS PI = 2
7406 22:56:05.247204 [0] AVG Duty = 5015%(X100)
7407 22:56:05.250442
7408 22:56:05.250911 ==DQ 1 ==
7409 22:56:05.253811 Final DQ duty delay cell = 0
7410 22:56:05.256657 [0] MAX Duty = 5062%(X100), DQS PI = 2
7411 22:56:05.260365 [0] MIN Duty = 4813%(X100), DQS PI = 34
7412 22:56:05.260954 [0] AVG Duty = 4937%(X100)
7413 22:56:05.261559
7414 22:56:05.263668 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7415 22:56:05.264351
7416 22:56:05.267166 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7417 22:56:05.273584 [DutyScan_Calibration_Flow] ====Done====
7418 22:56:05.277006 nWR fixed to 30
7419 22:56:05.277529 [ModeRegInit_LP4] CH0 RK0
7420 22:56:05.280368 [ModeRegInit_LP4] CH0 RK1
7421 22:56:05.283526 [ModeRegInit_LP4] CH1 RK0
7422 22:56:05.284093 [ModeRegInit_LP4] CH1 RK1
7423 22:56:05.287540 match AC timing 5
7424 22:56:05.289967 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7425 22:56:05.293763 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7426 22:56:05.300212 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7427 22:56:05.303332 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7428 22:56:05.310426 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7429 22:56:05.310987 [MiockJmeterHQA]
7430 22:56:05.311562
7431 22:56:05.313383 [DramcMiockJmeter] u1RxGatingPI = 0
7432 22:56:05.317018 0 : 4252, 4027
7433 22:56:05.317652 4 : 4257, 4029
7434 22:56:05.318037 8 : 4252, 4027
7435 22:56:05.320143 12 : 4252, 4027
7436 22:56:05.320625 16 : 4253, 4027
7437 22:56:05.323625 20 : 4252, 4027
7438 22:56:05.324106 24 : 4253, 4027
7439 22:56:05.327013 28 : 4365, 4140
7440 22:56:05.327589 32 : 4252, 4027
7441 22:56:05.327964 36 : 4255, 4029
7442 22:56:05.330293 40 : 4253, 4026
7443 22:56:05.330774 44 : 4363, 4138
7444 22:56:05.333705 48 : 4252, 4027
7445 22:56:05.334183 52 : 4363, 4138
7446 22:56:05.336985 56 : 4250, 4027
7447 22:56:05.337595 60 : 4250, 4027
7448 22:56:05.337978 64 : 4250, 4027
7449 22:56:05.340086 68 : 4252, 4030
7450 22:56:05.340567 72 : 4360, 4137
7451 22:56:05.343643 76 : 4250, 4027
7452 22:56:05.344214 80 : 4361, 4137
7453 22:56:05.347457 84 : 4252, 4027
7454 22:56:05.348028 88 : 4250, 3471
7455 22:56:05.350285 92 : 4249, 0
7456 22:56:05.350763 96 : 4363, 0
7457 22:56:05.351140 100 : 4250, 0
7458 22:56:05.353618 104 : 4360, 0
7459 22:56:05.354200 108 : 4250, 0
7460 22:56:05.354582 112 : 4249, 0
7461 22:56:05.356697 116 : 4250, 0
7462 22:56:05.357178 120 : 4360, 0
7463 22:56:05.360301 124 : 4250, 0
7464 22:56:05.360874 128 : 4250, 0
7465 22:56:05.361254 132 : 4250, 0
7466 22:56:05.363341 136 : 4250, 0
7467 22:56:05.363820 140 : 4253, 0
7468 22:56:05.367088 144 : 4250, 0
7469 22:56:05.367665 148 : 4250, 0
7470 22:56:05.368050 152 : 4252, 0
7471 22:56:05.369949 156 : 4360, 0
7472 22:56:05.370432 160 : 4250, 0
7473 22:56:05.373795 164 : 4250, 0
7474 22:56:05.374370 168 : 4250, 0
7475 22:56:05.374749 172 : 4361, 0
7476 22:56:05.376679 176 : 4360, 0
7477 22:56:05.377161 180 : 4253, 0
7478 22:56:05.377576 184 : 4250, 0
7479 22:56:05.380434 188 : 4250, 0
7480 22:56:05.381007 192 : 4363, 0
7481 22:56:05.383722 196 : 4250, 0
7482 22:56:05.384291 200 : 4250, 9
7483 22:56:05.384670 204 : 4250, 2742
7484 22:56:05.386561 208 : 4252, 4029
7485 22:56:05.387038 212 : 4363, 4140
7486 22:56:05.390525 216 : 4360, 4137
7487 22:56:05.391097 220 : 4250, 4026
7488 22:56:05.393222 224 : 4363, 4140
7489 22:56:05.393756 228 : 4360, 4137
7490 22:56:05.396909 232 : 4250, 4027
7491 22:56:05.397517 236 : 4250, 4027
7492 22:56:05.399740 240 : 4252, 4029
7493 22:56:05.400223 244 : 4250, 4027
7494 22:56:05.403081 248 : 4250, 4027
7495 22:56:05.403562 252 : 4250, 4027
7496 22:56:05.406400 256 : 4252, 4029
7497 22:56:05.406882 260 : 4250, 4027
7498 22:56:05.407257 264 : 4360, 4137
7499 22:56:05.409832 268 : 4360, 4138
7500 22:56:05.410409 272 : 4250, 4027
7501 22:56:05.413364 276 : 4362, 4140
7502 22:56:05.414001 280 : 4360, 4138
7503 22:56:05.416448 284 : 4250, 4027
7504 22:56:05.417014 288 : 4250, 4027
7505 22:56:05.419581 292 : 4252, 4029
7506 22:56:05.420060 296 : 4250, 4026
7507 22:56:05.423142 300 : 4250, 4027
7508 22:56:05.423616 304 : 4250, 4027
7509 22:56:05.426398 308 : 4252, 4029
7510 22:56:05.426876 312 : 4250, 3912
7511 22:56:05.429811 316 : 4360, 1765
7512 22:56:05.430289
7513 22:56:05.430654 MIOCK jitter meter ch=0
7514 22:56:05.430999
7515 22:56:05.433172 1T = (316-92) = 224 dly cells
7516 22:56:05.440008 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7517 22:56:05.440581 ==
7518 22:56:05.442826 Dram Type= 6, Freq= 0, CH_0, rank 0
7519 22:56:05.446746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7520 22:56:05.447316 ==
7521 22:56:05.453000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7522 22:56:05.456290 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7523 22:56:05.459982 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7524 22:56:05.466277 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7525 22:56:05.475765 [CA 0] Center 42 (12~73) winsize 62
7526 22:56:05.479201 [CA 1] Center 42 (12~72) winsize 61
7527 22:56:05.482706 [CA 2] Center 37 (7~67) winsize 61
7528 22:56:05.485764 [CA 3] Center 37 (7~67) winsize 61
7529 22:56:05.489016 [CA 4] Center 36 (6~66) winsize 61
7530 22:56:05.492460 [CA 5] Center 35 (5~65) winsize 61
7531 22:56:05.493017
7532 22:56:05.495703 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7533 22:56:05.496170
7534 22:56:05.499472 [CATrainingPosCal] consider 1 rank data
7535 22:56:05.502709 u2DelayCellTimex100 = 290/100 ps
7536 22:56:05.505657 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7537 22:56:05.512312 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7538 22:56:05.515620 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7539 22:56:05.519357 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7540 22:56:05.522021 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7541 22:56:05.525614 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7542 22:56:05.526182
7543 22:56:05.528716 CA PerBit enable=1, Macro0, CA PI delay=35
7544 22:56:05.529183
7545 22:56:05.532658 [CBTSetCACLKResult] CA Dly = 35
7546 22:56:05.535836 CS Dly: 10 (0~41)
7547 22:56:05.538870 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7548 22:56:05.541971 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7549 22:56:05.542439 ==
7550 22:56:05.545602 Dram Type= 6, Freq= 0, CH_0, rank 1
7551 22:56:05.549192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 22:56:05.549859 ==
7553 22:56:05.555520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7554 22:56:05.558781 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7555 22:56:05.565607 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7556 22:56:05.568734 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7557 22:56:05.578970 [CA 0] Center 43 (13~73) winsize 61
7558 22:56:05.582376 [CA 1] Center 43 (13~73) winsize 61
7559 22:56:05.586195 [CA 2] Center 38 (8~68) winsize 61
7560 22:56:05.589162 [CA 3] Center 37 (8~67) winsize 60
7561 22:56:05.592116 [CA 4] Center 36 (6~66) winsize 61
7562 22:56:05.595872 [CA 5] Center 36 (6~66) winsize 61
7563 22:56:05.596488
7564 22:56:05.598967 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7565 22:56:05.599432
7566 22:56:05.602313 [CATrainingPosCal] consider 2 rank data
7567 22:56:05.605573 u2DelayCellTimex100 = 290/100 ps
7568 22:56:05.608984 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7569 22:56:05.615386 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7570 22:56:05.619115 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7571 22:56:05.622211 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7572 22:56:05.625421 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7573 22:56:05.628699 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7574 22:56:05.629264
7575 22:56:05.632158 CA PerBit enable=1, Macro0, CA PI delay=35
7576 22:56:05.632622
7577 22:56:05.635708 [CBTSetCACLKResult] CA Dly = 35
7578 22:56:05.638941 CS Dly: 11 (0~43)
7579 22:56:05.642168 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7580 22:56:05.645429 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7581 22:56:05.645895
7582 22:56:05.649190 ----->DramcWriteLeveling(PI) begin...
7583 22:56:05.649832 ==
7584 22:56:05.652432 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 22:56:05.655793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 22:56:05.659157 ==
7587 22:56:05.659721 Write leveling (Byte 0): 38 => 38
7588 22:56:05.662156 Write leveling (Byte 1): 31 => 31
7589 22:56:05.665225 DramcWriteLeveling(PI) end<-----
7590 22:56:05.665732
7591 22:56:05.666102 ==
7592 22:56:05.668912 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 22:56:05.675379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 22:56:05.675923 ==
7595 22:56:05.676294 [Gating] SW mode calibration
7596 22:56:05.685604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7597 22:56:05.688863 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7598 22:56:05.695106 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 22:56:05.698592 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 22:56:05.701862 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
7601 22:56:05.705651 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7602 22:56:05.711904 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7603 22:56:05.715549 1 4 20 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7604 22:56:05.718366 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 22:56:05.725216 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 22:56:05.728551 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 22:56:05.731876 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 22:56:05.738757 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
7609 22:56:05.741757 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7610 22:56:05.745331 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7611 22:56:05.751580 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7612 22:56:05.754776 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7613 22:56:05.758373 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 22:56:05.765435 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 22:56:05.768179 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7616 22:56:05.771498 1 6 8 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
7617 22:56:05.778613 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7618 22:56:05.781896 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7619 22:56:05.785041 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7620 22:56:05.791594 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 22:56:05.794798 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 22:56:05.798467 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 22:56:05.804910 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 22:56:05.808279 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7625 22:56:05.811711 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7626 22:56:05.818328 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7627 22:56:05.821365 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7628 22:56:05.824408 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 22:56:05.831167 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 22:56:05.834844 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 22:56:05.837870 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 22:56:05.844951 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 22:56:05.848292 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 22:56:05.851434 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 22:56:05.857971 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 22:56:05.861041 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 22:56:05.864594 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 22:56:05.870976 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 22:56:05.874369 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 22:56:05.877541 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 22:56:05.884446 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7642 22:56:05.887859 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7643 22:56:05.890966 Total UI for P1: 0, mck2ui 16
7644 22:56:05.894218 best dqsien dly found for B0: ( 1, 9, 12)
7645 22:56:05.897705 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7646 22:56:05.900856 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 22:56:05.904012 Total UI for P1: 0, mck2ui 16
7648 22:56:05.907527 best dqsien dly found for B1: ( 1, 9, 20)
7649 22:56:05.910936 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7650 22:56:05.917678 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7651 22:56:05.918251
7652 22:56:05.921094 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7653 22:56:05.923732 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7654 22:56:05.927321 [Gating] SW calibration Done
7655 22:56:05.927896 ==
7656 22:56:05.930526 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 22:56:05.933728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 22:56:05.934198 ==
7659 22:56:05.937236 RX Vref Scan: 0
7660 22:56:05.937847
7661 22:56:05.938216 RX Vref 0 -> 0, step: 1
7662 22:56:05.938561
7663 22:56:05.940733 RX Delay 0 -> 252, step: 8
7664 22:56:05.943812 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7665 22:56:05.947210 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7666 22:56:05.953877 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7667 22:56:05.957482 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7668 22:56:05.960691 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7669 22:56:05.963967 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7670 22:56:05.967152 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7671 22:56:05.973926 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7672 22:56:05.977180 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7673 22:56:05.980489 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7674 22:56:05.984021 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7675 22:56:05.987410 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7676 22:56:05.994094 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7677 22:56:05.997427 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7678 22:56:06.000353 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7679 22:56:06.003689 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7680 22:56:06.004361 ==
7681 22:56:06.007049 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 22:56:06.013872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 22:56:06.014448 ==
7684 22:56:06.014819 DQS Delay:
7685 22:56:06.015156 DQS0 = 0, DQS1 = 0
7686 22:56:06.017677 DQM Delay:
7687 22:56:06.018247 DQM0 = 138, DQM1 = 127
7688 22:56:06.021023 DQ Delay:
7689 22:56:06.023528 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7690 22:56:06.027439 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7691 22:56:06.030197 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7692 22:56:06.033945 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7693 22:56:06.034416
7694 22:56:06.034788
7695 22:56:06.035124 ==
7696 22:56:06.037660 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 22:56:06.040809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 22:56:06.041426 ==
7699 22:56:06.043546
7700 22:56:06.044011
7701 22:56:06.044373 TX Vref Scan disable
7702 22:56:06.047266 == TX Byte 0 ==
7703 22:56:06.050200 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7704 22:56:06.053602 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7705 22:56:06.057563 == TX Byte 1 ==
7706 22:56:06.060545 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7707 22:56:06.064217 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7708 22:56:06.064817 ==
7709 22:56:06.066796 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 22:56:06.073424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 22:56:06.073973 ==
7712 22:56:06.086177
7713 22:56:06.089492 TX Vref early break, caculate TX vref
7714 22:56:06.093019 TX Vref=16, minBit 12, minWin=22, winSum=378
7715 22:56:06.096041 TX Vref=18, minBit 8, minWin=23, winSum=389
7716 22:56:06.099010 TX Vref=20, minBit 12, minWin=23, winSum=395
7717 22:56:06.102841 TX Vref=22, minBit 4, minWin=24, winSum=408
7718 22:56:06.106135 TX Vref=24, minBit 12, minWin=25, winSum=418
7719 22:56:06.112583 TX Vref=26, minBit 4, minWin=25, winSum=424
7720 22:56:06.116244 TX Vref=28, minBit 0, minWin=26, winSum=433
7721 22:56:06.119285 TX Vref=30, minBit 0, minWin=26, winSum=424
7722 22:56:06.122375 TX Vref=32, minBit 2, minWin=25, winSum=416
7723 22:56:06.125865 TX Vref=34, minBit 4, minWin=24, winSum=402
7724 22:56:06.132174 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
7725 22:56:06.132921
7726 22:56:06.135442 Final TX Range 0 Vref 28
7727 22:56:06.135909
7728 22:56:06.136272 ==
7729 22:56:06.139206 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 22:56:06.142298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 22:56:06.142768 ==
7732 22:56:06.143135
7733 22:56:06.143471
7734 22:56:06.145637 TX Vref Scan disable
7735 22:56:06.152141 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7736 22:56:06.152611 == TX Byte 0 ==
7737 22:56:06.155647 u2DelayCellOfst[0]=13 cells (4 PI)
7738 22:56:06.159054 u2DelayCellOfst[1]=20 cells (6 PI)
7739 22:56:06.162572 u2DelayCellOfst[2]=13 cells (4 PI)
7740 22:56:06.165926 u2DelayCellOfst[3]=13 cells (4 PI)
7741 22:56:06.168656 u2DelayCellOfst[4]=10 cells (3 PI)
7742 22:56:06.172267 u2DelayCellOfst[5]=0 cells (0 PI)
7743 22:56:06.175747 u2DelayCellOfst[6]=20 cells (6 PI)
7744 22:56:06.178642 u2DelayCellOfst[7]=16 cells (5 PI)
7745 22:56:06.182339 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7746 22:56:06.185718 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7747 22:56:06.189116 == TX Byte 1 ==
7748 22:56:06.192597 u2DelayCellOfst[8]=0 cells (0 PI)
7749 22:56:06.193212 u2DelayCellOfst[9]=0 cells (0 PI)
7750 22:56:06.195608 u2DelayCellOfst[10]=10 cells (3 PI)
7751 22:56:06.198798 u2DelayCellOfst[11]=3 cells (1 PI)
7752 22:56:06.202177 u2DelayCellOfst[12]=10 cells (3 PI)
7753 22:56:06.205213 u2DelayCellOfst[13]=13 cells (4 PI)
7754 22:56:06.209202 u2DelayCellOfst[14]=13 cells (4 PI)
7755 22:56:06.212012 u2DelayCellOfst[15]=10 cells (3 PI)
7756 22:56:06.215871 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7757 22:56:06.221733 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7758 22:56:06.222202 DramC Write-DBI on
7759 22:56:06.222566 ==
7760 22:56:06.225157 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 22:56:06.231905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 22:56:06.232473 ==
7763 22:56:06.232924
7764 22:56:06.233276
7765 22:56:06.233655 TX Vref Scan disable
7766 22:56:06.235711 == TX Byte 0 ==
7767 22:56:06.239274 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7768 22:56:06.242405 == TX Byte 1 ==
7769 22:56:06.245957 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7770 22:56:06.249230 DramC Write-DBI off
7771 22:56:06.249749
7772 22:56:06.250115 [DATLAT]
7773 22:56:06.250458 Freq=1600, CH0 RK0
7774 22:56:06.250787
7775 22:56:06.252344 DATLAT Default: 0xf
7776 22:56:06.252807 0, 0xFFFF, sum = 0
7777 22:56:06.255774 1, 0xFFFF, sum = 0
7778 22:56:06.258792 2, 0xFFFF, sum = 0
7779 22:56:06.259263 3, 0xFFFF, sum = 0
7780 22:56:06.262621 4, 0xFFFF, sum = 0
7781 22:56:06.263191 5, 0xFFFF, sum = 0
7782 22:56:06.265534 6, 0xFFFF, sum = 0
7783 22:56:06.266011 7, 0xFFFF, sum = 0
7784 22:56:06.268692 8, 0xFFFF, sum = 0
7785 22:56:06.269261 9, 0xFFFF, sum = 0
7786 22:56:06.272392 10, 0xFFFF, sum = 0
7787 22:56:06.272884 11, 0xFFFF, sum = 0
7788 22:56:06.275651 12, 0xFFFF, sum = 0
7789 22:56:06.276128 13, 0xFFFF, sum = 0
7790 22:56:06.278922 14, 0x0, sum = 1
7791 22:56:06.279396 15, 0x0, sum = 2
7792 22:56:06.282145 16, 0x0, sum = 3
7793 22:56:06.282618 17, 0x0, sum = 4
7794 22:56:06.285888 best_step = 15
7795 22:56:06.286356
7796 22:56:06.286721 ==
7797 22:56:06.288769 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 22:56:06.292343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 22:56:06.292917 ==
7800 22:56:06.295481 RX Vref Scan: 1
7801 22:56:06.295945
7802 22:56:06.296309 Set Vref Range= 24 -> 127
7803 22:56:06.296648
7804 22:56:06.298866 RX Vref 24 -> 127, step: 1
7805 22:56:06.299331
7806 22:56:06.302167 RX Delay 19 -> 252, step: 4
7807 22:56:06.302634
7808 22:56:06.305364 Set Vref, RX VrefLevel [Byte0]: 24
7809 22:56:06.309005 [Byte1]: 24
7810 22:56:06.309619
7811 22:56:06.312534 Set Vref, RX VrefLevel [Byte0]: 25
7812 22:56:06.315487 [Byte1]: 25
7813 22:56:06.316004
7814 22:56:06.318993 Set Vref, RX VrefLevel [Byte0]: 26
7815 22:56:06.322270 [Byte1]: 26
7816 22:56:06.326296
7817 22:56:06.326852 Set Vref, RX VrefLevel [Byte0]: 27
7818 22:56:06.329280 [Byte1]: 27
7819 22:56:06.333914
7820 22:56:06.334487 Set Vref, RX VrefLevel [Byte0]: 28
7821 22:56:06.337424 [Byte1]: 28
7822 22:56:06.341686
7823 22:56:06.342433 Set Vref, RX VrefLevel [Byte0]: 29
7824 22:56:06.344679 [Byte1]: 29
7825 22:56:06.348992
7826 22:56:06.349621 Set Vref, RX VrefLevel [Byte0]: 30
7827 22:56:06.352369 [Byte1]: 30
7828 22:56:06.356352
7829 22:56:06.356818 Set Vref, RX VrefLevel [Byte0]: 31
7830 22:56:06.360097 [Byte1]: 31
7831 22:56:06.364531
7832 22:56:06.365137 Set Vref, RX VrefLevel [Byte0]: 32
7833 22:56:06.367556 [Byte1]: 32
7834 22:56:06.371432
7835 22:56:06.371899 Set Vref, RX VrefLevel [Byte0]: 33
7836 22:56:06.374961 [Byte1]: 33
7837 22:56:06.379190
7838 22:56:06.379755 Set Vref, RX VrefLevel [Byte0]: 34
7839 22:56:06.382787 [Byte1]: 34
7840 22:56:06.387266
7841 22:56:06.387830 Set Vref, RX VrefLevel [Byte0]: 35
7842 22:56:06.389965 [Byte1]: 35
7843 22:56:06.394621
7844 22:56:06.395187 Set Vref, RX VrefLevel [Byte0]: 36
7845 22:56:06.397503 [Byte1]: 36
7846 22:56:06.402122
7847 22:56:06.402691 Set Vref, RX VrefLevel [Byte0]: 37
7848 22:56:06.405151 [Byte1]: 37
7849 22:56:06.409751
7850 22:56:06.410327 Set Vref, RX VrefLevel [Byte0]: 38
7851 22:56:06.412560 [Byte1]: 38
7852 22:56:06.417122
7853 22:56:06.417633 Set Vref, RX VrefLevel [Byte0]: 39
7854 22:56:06.420427 [Byte1]: 39
7855 22:56:06.424690
7856 22:56:06.425155 Set Vref, RX VrefLevel [Byte0]: 40
7857 22:56:06.428405 [Byte1]: 40
7858 22:56:06.432335
7859 22:56:06.432904 Set Vref, RX VrefLevel [Byte0]: 41
7860 22:56:06.435260 [Byte1]: 41
7861 22:56:06.439736
7862 22:56:06.440307 Set Vref, RX VrefLevel [Byte0]: 42
7863 22:56:06.442877 [Byte1]: 42
7864 22:56:06.447250
7865 22:56:06.447713 Set Vref, RX VrefLevel [Byte0]: 43
7866 22:56:06.450775 [Byte1]: 43
7867 22:56:06.454919
7868 22:56:06.455490 Set Vref, RX VrefLevel [Byte0]: 44
7869 22:56:06.458456 [Byte1]: 44
7870 22:56:06.462628
7871 22:56:06.463209 Set Vref, RX VrefLevel [Byte0]: 45
7872 22:56:06.465638 [Byte1]: 45
7873 22:56:06.470059
7874 22:56:06.470641 Set Vref, RX VrefLevel [Byte0]: 46
7875 22:56:06.473496 [Byte1]: 46
7876 22:56:06.477893
7877 22:56:06.478457 Set Vref, RX VrefLevel [Byte0]: 47
7878 22:56:06.480925 [Byte1]: 47
7879 22:56:06.485466
7880 22:56:06.486044 Set Vref, RX VrefLevel [Byte0]: 48
7881 22:56:06.488652 [Byte1]: 48
7882 22:56:06.493093
7883 22:56:06.493693 Set Vref, RX VrefLevel [Byte0]: 49
7884 22:56:06.496398 [Byte1]: 49
7885 22:56:06.500393
7886 22:56:06.500961 Set Vref, RX VrefLevel [Byte0]: 50
7887 22:56:06.503621 [Byte1]: 50
7888 22:56:06.507701
7889 22:56:06.508259 Set Vref, RX VrefLevel [Byte0]: 51
7890 22:56:06.511328 [Byte1]: 51
7891 22:56:06.515629
7892 22:56:06.516189 Set Vref, RX VrefLevel [Byte0]: 52
7893 22:56:06.518598 [Byte1]: 52
7894 22:56:06.522848
7895 22:56:06.523406 Set Vref, RX VrefLevel [Byte0]: 53
7896 22:56:06.526720 [Byte1]: 53
7897 22:56:06.530614
7898 22:56:06.531225 Set Vref, RX VrefLevel [Byte0]: 54
7899 22:56:06.534145 [Byte1]: 54
7900 22:56:06.538236
7901 22:56:06.538802 Set Vref, RX VrefLevel [Byte0]: 55
7902 22:56:06.541646 [Byte1]: 55
7903 22:56:06.545819
7904 22:56:06.546281 Set Vref, RX VrefLevel [Byte0]: 56
7905 22:56:06.549482 [Byte1]: 56
7906 22:56:06.553460
7907 22:56:06.554094 Set Vref, RX VrefLevel [Byte0]: 57
7908 22:56:06.556370 [Byte1]: 57
7909 22:56:06.561198
7910 22:56:06.561809 Set Vref, RX VrefLevel [Byte0]: 58
7911 22:56:06.564084 [Byte1]: 58
7912 22:56:06.568650
7913 22:56:06.569217 Set Vref, RX VrefLevel [Byte0]: 59
7914 22:56:06.571633 [Byte1]: 59
7915 22:56:06.575958
7916 22:56:06.576425 Set Vref, RX VrefLevel [Byte0]: 60
7917 22:56:06.579087 [Byte1]: 60
7918 22:56:06.583627
7919 22:56:06.584091 Set Vref, RX VrefLevel [Byte0]: 61
7920 22:56:06.587001 [Byte1]: 61
7921 22:56:06.591069
7922 22:56:06.591535 Set Vref, RX VrefLevel [Byte0]: 62
7923 22:56:06.594177 [Byte1]: 62
7924 22:56:06.598735
7925 22:56:06.599231 Set Vref, RX VrefLevel [Byte0]: 63
7926 22:56:06.602331 [Byte1]: 63
7927 22:56:06.606254
7928 22:56:06.606720 Set Vref, RX VrefLevel [Byte0]: 64
7929 22:56:06.609648 [Byte1]: 64
7930 22:56:06.613608
7931 22:56:06.614077 Set Vref, RX VrefLevel [Byte0]: 65
7932 22:56:06.617457 [Byte1]: 65
7933 22:56:06.621346
7934 22:56:06.621816 Set Vref, RX VrefLevel [Byte0]: 66
7935 22:56:06.624595 [Byte1]: 66
7936 22:56:06.628985
7937 22:56:06.629601 Set Vref, RX VrefLevel [Byte0]: 67
7938 22:56:06.632300 [Byte1]: 67
7939 22:56:06.636447
7940 22:56:06.636917 Set Vref, RX VrefLevel [Byte0]: 68
7941 22:56:06.639999 [Byte1]: 68
7942 22:56:06.643974
7943 22:56:06.644443 Set Vref, RX VrefLevel [Byte0]: 69
7944 22:56:06.647459 [Byte1]: 69
7945 22:56:06.651801
7946 22:56:06.652292 Set Vref, RX VrefLevel [Byte0]: 70
7947 22:56:06.655250 [Byte1]: 70
7948 22:56:06.659384
7949 22:56:06.659850 Set Vref, RX VrefLevel [Byte0]: 71
7950 22:56:06.662252 [Byte1]: 71
7951 22:56:06.666946
7952 22:56:06.667415 Set Vref, RX VrefLevel [Byte0]: 72
7953 22:56:06.670198 [Byte1]: 72
7954 22:56:06.674529
7955 22:56:06.675052 Set Vref, RX VrefLevel [Byte0]: 73
7956 22:56:06.677455 [Byte1]: 73
7957 22:56:06.681948
7958 22:56:06.682455 Set Vref, RX VrefLevel [Byte0]: 74
7959 22:56:06.685390 [Byte1]: 74
7960 22:56:06.689541
7961 22:56:06.690009 Set Vref, RX VrefLevel [Byte0]: 75
7962 22:56:06.692812 [Byte1]: 75
7963 22:56:06.697091
7964 22:56:06.697703 Set Vref, RX VrefLevel [Byte0]: 76
7965 22:56:06.700483 [Byte1]: 76
7966 22:56:06.704648
7967 22:56:06.705219 Set Vref, RX VrefLevel [Byte0]: 77
7968 22:56:06.707968 [Byte1]: 77
7969 22:56:06.712115
7970 22:56:06.712590 Set Vref, RX VrefLevel [Byte0]: 78
7971 22:56:06.715459 [Byte1]: 78
7972 22:56:06.719725
7973 22:56:06.720300 Set Vref, RX VrefLevel [Byte0]: 79
7974 22:56:06.722949 [Byte1]: 79
7975 22:56:06.727266
7976 22:56:06.727839 Set Vref, RX VrefLevel [Byte0]: 80
7977 22:56:06.730840 [Byte1]: 80
7978 22:56:06.734914
7979 22:56:06.735421 Set Vref, RX VrefLevel [Byte0]: 81
7980 22:56:06.738284 [Byte1]: 81
7981 22:56:06.742678
7982 22:56:06.743122 Final RX Vref Byte 0 = 58 to rank0
7983 22:56:06.745779 Final RX Vref Byte 1 = 62 to rank0
7984 22:56:06.749827 Final RX Vref Byte 0 = 58 to rank1
7985 22:56:06.752394 Final RX Vref Byte 1 = 62 to rank1==
7986 22:56:06.756118 Dram Type= 6, Freq= 0, CH_0, rank 0
7987 22:56:06.762608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 22:56:06.763204 ==
7989 22:56:06.763555 DQS Delay:
7990 22:56:06.763872 DQS0 = 0, DQS1 = 0
7991 22:56:06.766080 DQM Delay:
7992 22:56:06.766507 DQM0 = 136, DQM1 = 124
7993 22:56:06.769091 DQ Delay:
7994 22:56:06.772309 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =132
7995 22:56:06.776433 DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144
7996 22:56:06.779875 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7997 22:56:06.782683 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =134
7998 22:56:06.783112
7999 22:56:06.783447
8000 22:56:06.783760
8001 22:56:06.785823 [DramC_TX_OE_Calibration] TA2
8002 22:56:06.789036 Original DQ_B0 (3 6) =30, OEN = 27
8003 22:56:06.792776 Original DQ_B1 (3 6) =30, OEN = 27
8004 22:56:06.795855 24, 0x0, End_B0=24 End_B1=24
8005 22:56:06.796403 25, 0x0, End_B0=25 End_B1=25
8006 22:56:06.799209 26, 0x0, End_B0=26 End_B1=26
8007 22:56:06.802489 27, 0x0, End_B0=27 End_B1=27
8008 22:56:06.805768 28, 0x0, End_B0=28 End_B1=28
8009 22:56:06.806305 29, 0x0, End_B0=29 End_B1=29
8010 22:56:06.809335 30, 0x0, End_B0=30 End_B1=30
8011 22:56:06.812398 31, 0x4141, End_B0=30 End_B1=30
8012 22:56:06.816163 Byte0 end_step=30 best_step=27
8013 22:56:06.819424 Byte1 end_step=30 best_step=27
8014 22:56:06.822406 Byte0 TX OE(2T, 0.5T) = (3, 3)
8015 22:56:06.822933 Byte1 TX OE(2T, 0.5T) = (3, 3)
8016 22:56:06.825659
8017 22:56:06.826083
8018 22:56:06.832576 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8019 22:56:06.835760 CH0 RK0: MR19=303, MR18=1C1B
8020 22:56:06.842561 CH0_RK0: MR19=0x303, MR18=0x1C1B, DQSOSC=395, MR23=63, INC=23, DEC=15
8021 22:56:06.843090
8022 22:56:06.845947 ----->DramcWriteLeveling(PI) begin...
8023 22:56:06.846482 ==
8024 22:56:06.849523 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 22:56:06.852428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 22:56:06.852973 ==
8027 22:56:06.855922 Write leveling (Byte 0): 37 => 37
8028 22:56:06.859137 Write leveling (Byte 1): 30 => 30
8029 22:56:06.862534 DramcWriteLeveling(PI) end<-----
8030 22:56:06.863064
8031 22:56:06.863405 ==
8032 22:56:06.865594 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 22:56:06.869161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 22:56:06.869650 ==
8035 22:56:06.872155 [Gating] SW mode calibration
8036 22:56:06.879647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8037 22:56:06.885764 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8038 22:56:06.889185 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 22:56:06.892675 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 22:56:06.899007 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8041 22:56:06.902349 1 4 12 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8042 22:56:06.906011 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 22:56:06.912749 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 22:56:06.915874 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 22:56:06.919315 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 22:56:06.925850 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 22:56:06.928886 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 22:56:06.932308 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 22:56:06.938887 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8050 22:56:06.942222 1 5 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
8051 22:56:06.945516 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 22:56:06.952363 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 22:56:06.955571 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 22:56:06.959184 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 22:56:06.965927 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 22:56:06.969131 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
8057 22:56:06.972172 1 6 12 | B1->B0 | 2929 3e3e | 0 1 | (0 0) (0 0)
8058 22:56:06.975584 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 22:56:06.981954 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 22:56:06.985480 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 22:56:06.988738 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 22:56:06.995357 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 22:56:06.998693 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 22:56:07.001966 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 22:56:07.009159 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8066 22:56:07.012163 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8067 22:56:07.015478 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 22:56:07.022176 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 22:56:07.025032 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 22:56:07.028372 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 22:56:07.034885 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 22:56:07.038398 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 22:56:07.041946 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 22:56:07.048387 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 22:56:07.052194 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 22:56:07.054740 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 22:56:07.061805 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 22:56:07.065364 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 22:56:07.068437 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 22:56:07.074785 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8081 22:56:07.078228 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8082 22:56:07.081467 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8083 22:56:07.085181 Total UI for P1: 0, mck2ui 16
8084 22:56:07.088224 best dqsien dly found for B0: ( 1, 9, 10)
8085 22:56:07.095000 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 22:56:07.095590 Total UI for P1: 0, mck2ui 16
8087 22:56:07.101258 best dqsien dly found for B1: ( 1, 9, 14)
8088 22:56:07.104519 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8089 22:56:07.108394 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8090 22:56:07.108969
8091 22:56:07.111678 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8092 22:56:07.115301 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8093 22:56:07.118476 [Gating] SW calibration Done
8094 22:56:07.119050 ==
8095 22:56:07.121668 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 22:56:07.124916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 22:56:07.125533 ==
8098 22:56:07.128696 RX Vref Scan: 0
8099 22:56:07.129268
8100 22:56:07.129701 RX Vref 0 -> 0, step: 1
8101 22:56:07.130051
8102 22:56:07.131197 RX Delay 0 -> 252, step: 8
8103 22:56:07.134822 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8104 22:56:07.141740 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8105 22:56:07.144452 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8106 22:56:07.148060 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8107 22:56:07.151654 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8108 22:56:07.154798 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8109 22:56:07.158154 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8110 22:56:07.164716 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8111 22:56:07.167941 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8112 22:56:07.171575 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8113 22:56:07.174565 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8114 22:56:07.178035 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8115 22:56:07.184789 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8116 22:56:07.187944 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8117 22:56:07.191340 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8118 22:56:07.194684 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8119 22:56:07.195246 ==
8120 22:56:07.198095 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 22:56:07.204604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 22:56:07.205175 ==
8123 22:56:07.205581 DQS Delay:
8124 22:56:07.208250 DQS0 = 0, DQS1 = 0
8125 22:56:07.208933 DQM Delay:
8126 22:56:07.211526 DQM0 = 136, DQM1 = 125
8127 22:56:07.212090 DQ Delay:
8128 22:56:07.214721 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8129 22:56:07.218159 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8130 22:56:07.221386 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8131 22:56:07.224631 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8132 22:56:07.225197
8133 22:56:07.225600
8134 22:56:07.225938 ==
8135 22:56:07.227980 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 22:56:07.234820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 22:56:07.235389 ==
8138 22:56:07.235757
8139 22:56:07.236091
8140 22:56:07.236413 TX Vref Scan disable
8141 22:56:07.237706 == TX Byte 0 ==
8142 22:56:07.241282 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8143 22:56:07.244439 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8144 22:56:07.247745 == TX Byte 1 ==
8145 22:56:07.251226 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8146 22:56:07.255004 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8147 22:56:07.257963 ==
8148 22:56:07.261719 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 22:56:07.265014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 22:56:07.265628 ==
8151 22:56:07.277455
8152 22:56:07.280844 TX Vref early break, caculate TX vref
8153 22:56:07.284059 TX Vref=16, minBit 3, minWin=23, winSum=388
8154 22:56:07.287246 TX Vref=18, minBit 0, minWin=23, winSum=399
8155 22:56:07.290875 TX Vref=20, minBit 1, minWin=24, winSum=405
8156 22:56:07.294144 TX Vref=22, minBit 8, minWin=24, winSum=413
8157 22:56:07.297502 TX Vref=24, minBit 1, minWin=25, winSum=421
8158 22:56:07.304112 TX Vref=26, minBit 0, minWin=26, winSum=431
8159 22:56:07.307179 TX Vref=28, minBit 0, minWin=26, winSum=433
8160 22:56:07.310701 TX Vref=30, minBit 0, minWin=25, winSum=427
8161 22:56:07.313654 TX Vref=32, minBit 0, minWin=25, winSum=412
8162 22:56:07.317041 TX Vref=34, minBit 0, minWin=24, winSum=407
8163 22:56:07.324010 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
8164 22:56:07.324564
8165 22:56:07.326872 Final TX Range 0 Vref 28
8166 22:56:07.327340
8167 22:56:07.327703 ==
8168 22:56:07.330886 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 22:56:07.333846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 22:56:07.334321 ==
8171 22:56:07.334688
8172 22:56:07.335027
8173 22:56:07.336960 TX Vref Scan disable
8174 22:56:07.343973 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8175 22:56:07.344547 == TX Byte 0 ==
8176 22:56:07.347006 u2DelayCellOfst[0]=10 cells (3 PI)
8177 22:56:07.350570 u2DelayCellOfst[1]=16 cells (5 PI)
8178 22:56:07.353886 u2DelayCellOfst[2]=10 cells (3 PI)
8179 22:56:07.357450 u2DelayCellOfst[3]=10 cells (3 PI)
8180 22:56:07.360765 u2DelayCellOfst[4]=6 cells (2 PI)
8181 22:56:07.364205 u2DelayCellOfst[5]=0 cells (0 PI)
8182 22:56:07.367187 u2DelayCellOfst[6]=16 cells (5 PI)
8183 22:56:07.367662 u2DelayCellOfst[7]=16 cells (5 PI)
8184 22:56:07.374123 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8185 22:56:07.377162 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8186 22:56:07.377689 == TX Byte 1 ==
8187 22:56:07.380436 u2DelayCellOfst[8]=3 cells (1 PI)
8188 22:56:07.383606 u2DelayCellOfst[9]=0 cells (0 PI)
8189 22:56:07.387335 u2DelayCellOfst[10]=6 cells (2 PI)
8190 22:56:07.390279 u2DelayCellOfst[11]=3 cells (1 PI)
8191 22:56:07.394174 u2DelayCellOfst[12]=13 cells (4 PI)
8192 22:56:07.397661 u2DelayCellOfst[13]=13 cells (4 PI)
8193 22:56:07.400415 u2DelayCellOfst[14]=16 cells (5 PI)
8194 22:56:07.403839 u2DelayCellOfst[15]=10 cells (3 PI)
8195 22:56:07.407041 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8196 22:56:07.413976 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8197 22:56:07.414533 DramC Write-DBI on
8198 22:56:07.414898 ==
8199 22:56:07.417433 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 22:56:07.420546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 22:56:07.421112 ==
8202 22:56:07.424315
8203 22:56:07.424872
8204 22:56:07.425235 TX Vref Scan disable
8205 22:56:07.426789 == TX Byte 0 ==
8206 22:56:07.430582 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8207 22:56:07.433673 == TX Byte 1 ==
8208 22:56:07.437020 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8209 22:56:07.437522 DramC Write-DBI off
8210 22:56:07.440396
8211 22:56:07.440954 [DATLAT]
8212 22:56:07.441372 Freq=1600, CH0 RK1
8213 22:56:07.441738
8214 22:56:07.443855 DATLAT Default: 0xf
8215 22:56:07.444416 0, 0xFFFF, sum = 0
8216 22:56:07.446883 1, 0xFFFF, sum = 0
8217 22:56:07.447354 2, 0xFFFF, sum = 0
8218 22:56:07.450153 3, 0xFFFF, sum = 0
8219 22:56:07.453587 4, 0xFFFF, sum = 0
8220 22:56:07.454177 5, 0xFFFF, sum = 0
8221 22:56:07.457087 6, 0xFFFF, sum = 0
8222 22:56:07.457699 7, 0xFFFF, sum = 0
8223 22:56:07.460182 8, 0xFFFF, sum = 0
8224 22:56:07.460752 9, 0xFFFF, sum = 0
8225 22:56:07.463442 10, 0xFFFF, sum = 0
8226 22:56:07.464012 11, 0xFFFF, sum = 0
8227 22:56:07.466533 12, 0xFFFF, sum = 0
8228 22:56:07.467004 13, 0xFFFF, sum = 0
8229 22:56:07.470192 14, 0x0, sum = 1
8230 22:56:07.470764 15, 0x0, sum = 2
8231 22:56:07.473486 16, 0x0, sum = 3
8232 22:56:07.474053 17, 0x0, sum = 4
8233 22:56:07.476636 best_step = 15
8234 22:56:07.477094
8235 22:56:07.477522 ==
8236 22:56:07.480168 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 22:56:07.483314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 22:56:07.483904 ==
8239 22:56:07.486980 RX Vref Scan: 0
8240 22:56:07.487543
8241 22:56:07.487908 RX Vref 0 -> 0, step: 1
8242 22:56:07.488249
8243 22:56:07.489766 RX Delay 11 -> 252, step: 4
8244 22:56:07.493714 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8245 22:56:07.499731 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8246 22:56:07.503315 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8247 22:56:07.506786 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8248 22:56:07.509716 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8249 22:56:07.513427 iDelay=191, Bit 5, Center 122 (71 ~ 174) 104
8250 22:56:07.519814 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8251 22:56:07.523191 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8252 22:56:07.526832 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8253 22:56:07.529897 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8254 22:56:07.533256 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8255 22:56:07.539989 iDelay=191, Bit 11, Center 118 (71 ~ 166) 96
8256 22:56:07.543066 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8257 22:56:07.546415 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8258 22:56:07.549979 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8259 22:56:07.553202 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8260 22:56:07.556408 ==
8261 22:56:07.556968 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 22:56:07.563313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 22:56:07.563881 ==
8264 22:56:07.564260 DQS Delay:
8265 22:56:07.566198 DQS0 = 0, DQS1 = 0
8266 22:56:07.566669 DQM Delay:
8267 22:56:07.570179 DQM0 = 132, DQM1 = 123
8268 22:56:07.570741 DQ Delay:
8269 22:56:07.573071 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8270 22:56:07.576461 DQ4 =132, DQ5 =122, DQ6 =138, DQ7 =138
8271 22:56:07.579868 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =118
8272 22:56:07.583252 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8273 22:56:07.583818
8274 22:56:07.584183
8275 22:56:07.584522
8276 22:56:07.586512 [DramC_TX_OE_Calibration] TA2
8277 22:56:07.589767 Original DQ_B0 (3 6) =30, OEN = 27
8278 22:56:07.593488 Original DQ_B1 (3 6) =30, OEN = 27
8279 22:56:07.596741 24, 0x0, End_B0=24 End_B1=24
8280 22:56:07.599755 25, 0x0, End_B0=25 End_B1=25
8281 22:56:07.600329 26, 0x0, End_B0=26 End_B1=26
8282 22:56:07.602784 27, 0x0, End_B0=27 End_B1=27
8283 22:56:07.606198 28, 0x0, End_B0=28 End_B1=28
8284 22:56:07.609838 29, 0x0, End_B0=29 End_B1=29
8285 22:56:07.610495 30, 0x0, End_B0=30 End_B1=30
8286 22:56:07.612986 31, 0x4141, End_B0=30 End_B1=30
8287 22:56:07.615961 Byte0 end_step=30 best_step=27
8288 22:56:07.619700 Byte1 end_step=30 best_step=27
8289 22:56:07.622946 Byte0 TX OE(2T, 0.5T) = (3, 3)
8290 22:56:07.626230 Byte1 TX OE(2T, 0.5T) = (3, 3)
8291 22:56:07.626723
8292 22:56:07.627094
8293 22:56:07.632928 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8294 22:56:07.635940 CH0 RK1: MR19=303, MR18=220F
8295 22:56:07.642831 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8296 22:56:07.646166 [RxdqsGatingPostProcess] freq 1600
8297 22:56:07.652949 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8298 22:56:07.653541 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 22:56:07.656331 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 22:56:07.658960 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 22:56:07.662638 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 22:56:07.665907 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 22:56:07.669275 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 22:56:07.672898 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 22:56:07.675983 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 22:56:07.679059 Pre-setting of DQS Precalculation
8307 22:56:07.682482 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8308 22:56:07.682949 ==
8309 22:56:07.685619 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 22:56:07.692473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 22:56:07.693039 ==
8312 22:56:07.695551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 22:56:07.702239 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 22:56:07.705580 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 22:56:07.712274 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 22:56:07.720073 [CA 0] Center 40 (11~70) winsize 60
8317 22:56:07.723482 [CA 1] Center 41 (11~71) winsize 61
8318 22:56:07.726556 [CA 2] Center 37 (8~67) winsize 60
8319 22:56:07.729915 [CA 3] Center 36 (6~66) winsize 61
8320 22:56:07.733284 [CA 4] Center 37 (7~67) winsize 61
8321 22:56:07.736664 [CA 5] Center 36 (6~66) winsize 61
8322 22:56:07.737127
8323 22:56:07.739810 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8324 22:56:07.740273
8325 22:56:07.743504 [CATrainingPosCal] consider 1 rank data
8326 22:56:07.746424 u2DelayCellTimex100 = 290/100 ps
8327 22:56:07.749614 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8328 22:56:07.756925 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8329 22:56:07.759646 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8330 22:56:07.762829 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8331 22:56:07.766209 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8332 22:56:07.770114 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8333 22:56:07.770575
8334 22:56:07.773325 CA PerBit enable=1, Macro0, CA PI delay=36
8335 22:56:07.773793
8336 22:56:07.776248 [CBTSetCACLKResult] CA Dly = 36
8337 22:56:07.776706 CS Dly: 8 (0~39)
8338 22:56:07.783212 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 22:56:07.786877 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 22:56:07.787466 ==
8341 22:56:07.789851 Dram Type= 6, Freq= 0, CH_1, rank 1
8342 22:56:07.793222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 22:56:07.793805 ==
8344 22:56:07.799576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 22:56:07.802917 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 22:56:07.809288 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 22:56:07.812686 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 22:56:07.823381 [CA 0] Center 42 (13~72) winsize 60
8349 22:56:07.826517 [CA 1] Center 42 (13~72) winsize 60
8350 22:56:07.829502 [CA 2] Center 39 (9~69) winsize 61
8351 22:56:07.833051 [CA 3] Center 37 (8~67) winsize 60
8352 22:56:07.836254 [CA 4] Center 38 (9~68) winsize 60
8353 22:56:07.839475 [CA 5] Center 37 (8~67) winsize 60
8354 22:56:07.839928
8355 22:56:07.842520 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8356 22:56:07.842975
8357 22:56:07.849406 [CATrainingPosCal] consider 2 rank data
8358 22:56:07.849975 u2DelayCellTimex100 = 290/100 ps
8359 22:56:07.856331 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8360 22:56:07.859358 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8361 22:56:07.862616 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8362 22:56:07.866319 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8363 22:56:07.869236 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8364 22:56:07.872618 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8365 22:56:07.873178
8366 22:56:07.875590 CA PerBit enable=1, Macro0, CA PI delay=37
8367 22:56:07.876047
8368 22:56:07.878927 [CBTSetCACLKResult] CA Dly = 37
8369 22:56:07.882781 CS Dly: 9 (0~42)
8370 22:56:07.886008 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 22:56:07.889161 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 22:56:07.889654
8373 22:56:07.892786 ----->DramcWriteLeveling(PI) begin...
8374 22:56:07.893390 ==
8375 22:56:07.896056 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 22:56:07.902228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 22:56:07.902775 ==
8378 22:56:07.905454 Write leveling (Byte 0): 26 => 26
8379 22:56:07.905922 Write leveling (Byte 1): 27 => 27
8380 22:56:07.908812 DramcWriteLeveling(PI) end<-----
8381 22:56:07.909264
8382 22:56:07.912130 ==
8383 22:56:07.912583 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 22:56:07.919057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 22:56:07.919617 ==
8386 22:56:07.922729 [Gating] SW mode calibration
8387 22:56:07.928699 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8388 22:56:07.932548 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8389 22:56:07.938477 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 22:56:07.941814 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 22:56:07.945115 1 4 8 | B1->B0 | 2b2b 3333 | 1 0 | (1 1) (0 0)
8392 22:56:07.951990 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 22:56:07.954984 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 22:56:07.958683 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 22:56:07.965520 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 22:56:07.968585 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 22:56:07.972226 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 22:56:07.978989 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8399 22:56:07.982206 1 5 8 | B1->B0 | 2e2e 2929 | 1 1 | (1 1) (1 0)
8400 22:56:07.985199 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8401 22:56:07.991702 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 22:56:07.995174 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 22:56:07.998312 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 22:56:08.004733 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 22:56:08.008305 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 22:56:08.011907 1 6 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
8407 22:56:08.018484 1 6 8 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
8408 22:56:08.021276 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 22:56:08.025117 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 22:56:08.028072 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 22:56:08.035226 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 22:56:08.038116 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 22:56:08.041572 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 22:56:08.048074 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8415 22:56:08.051640 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8416 22:56:08.054779 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8417 22:56:08.061797 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 22:56:08.064791 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 22:56:08.068418 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 22:56:08.074850 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 22:56:08.077880 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 22:56:08.081292 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 22:56:08.088038 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 22:56:08.091557 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 22:56:08.094905 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 22:56:08.101199 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 22:56:08.104560 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 22:56:08.107965 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 22:56:08.114231 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 22:56:08.118015 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 22:56:08.121431 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8432 22:56:08.127702 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8433 22:56:08.128289 Total UI for P1: 0, mck2ui 16
8434 22:56:08.134455 best dqsien dly found for B0: ( 1, 9, 8)
8435 22:56:08.137768 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 22:56:08.141009 Total UI for P1: 0, mck2ui 16
8437 22:56:08.144456 best dqsien dly found for B1: ( 1, 9, 12)
8438 22:56:08.147506 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8439 22:56:08.151102 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8440 22:56:08.151568
8441 22:56:08.154508 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8442 22:56:08.158102 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8443 22:56:08.160903 [Gating] SW calibration Done
8444 22:56:08.161391 ==
8445 22:56:08.164784 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 22:56:08.167960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 22:56:08.168429 ==
8448 22:56:08.171562 RX Vref Scan: 0
8449 22:56:08.172123
8450 22:56:08.174264 RX Vref 0 -> 0, step: 1
8451 22:56:08.174727
8452 22:56:08.175090 RX Delay 0 -> 252, step: 8
8453 22:56:08.181008 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8454 22:56:08.184526 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8455 22:56:08.187882 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8456 22:56:08.191001 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8457 22:56:08.194440 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8458 22:56:08.197690 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8459 22:56:08.204465 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8460 22:56:08.207770 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8461 22:56:08.211019 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8462 22:56:08.214294 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8463 22:56:08.217662 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8464 22:56:08.224400 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8465 22:56:08.227675 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8466 22:56:08.231174 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8467 22:56:08.234261 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8468 22:56:08.237959 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8469 22:56:08.241152 ==
8470 22:56:08.241635 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 22:56:08.247718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 22:56:08.248186 ==
8473 22:56:08.248550 DQS Delay:
8474 22:56:08.250999 DQS0 = 0, DQS1 = 0
8475 22:56:08.251573 DQM Delay:
8476 22:56:08.254382 DQM0 = 138, DQM1 = 130
8477 22:56:08.254844 DQ Delay:
8478 22:56:08.257702 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8479 22:56:08.260989 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8480 22:56:08.264223 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8481 22:56:08.267629 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8482 22:56:08.268049
8483 22:56:08.268376
8484 22:56:08.268682 ==
8485 22:56:08.271550 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 22:56:08.277587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 22:56:08.278079 ==
8488 22:56:08.278414
8489 22:56:08.278966
8490 22:56:08.279312 TX Vref Scan disable
8491 22:56:08.281175 == TX Byte 0 ==
8492 22:56:08.284577 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8493 22:56:08.291400 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8494 22:56:08.291921 == TX Byte 1 ==
8495 22:56:08.294256 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8496 22:56:08.301195 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8497 22:56:08.301753 ==
8498 22:56:08.304183 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 22:56:08.307848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 22:56:08.308276 ==
8501 22:56:08.319775
8502 22:56:08.322768 TX Vref early break, caculate TX vref
8503 22:56:08.326144 TX Vref=16, minBit 10, minWin=22, winSum=373
8504 22:56:08.329463 TX Vref=18, minBit 10, minWin=22, winSum=381
8505 22:56:08.332922 TX Vref=20, minBit 15, minWin=22, winSum=392
8506 22:56:08.336089 TX Vref=22, minBit 10, minWin=23, winSum=400
8507 22:56:08.342740 TX Vref=24, minBit 1, minWin=25, winSum=414
8508 22:56:08.345916 TX Vref=26, minBit 13, minWin=25, winSum=418
8509 22:56:08.349141 TX Vref=28, minBit 14, minWin=25, winSum=424
8510 22:56:08.352883 TX Vref=30, minBit 8, minWin=25, winSum=416
8511 22:56:08.355884 TX Vref=32, minBit 10, minWin=24, winSum=407
8512 22:56:08.359281 TX Vref=34, minBit 14, minWin=23, winSum=398
8513 22:56:08.365799 [TxChooseVref] Worse bit 14, Min win 25, Win sum 424, Final Vref 28
8514 22:56:08.366281
8515 22:56:08.369336 Final TX Range 0 Vref 28
8516 22:56:08.369801
8517 22:56:08.370172 ==
8518 22:56:08.372667 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 22:56:08.375624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 22:56:08.376057 ==
8521 22:56:08.376579
8522 22:56:08.378982
8523 22:56:08.379576 TX Vref Scan disable
8524 22:56:08.386018 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8525 22:56:08.386450 == TX Byte 0 ==
8526 22:56:08.389484 u2DelayCellOfst[0]=13 cells (4 PI)
8527 22:56:08.392457 u2DelayCellOfst[1]=6 cells (2 PI)
8528 22:56:08.395970 u2DelayCellOfst[2]=0 cells (0 PI)
8529 22:56:08.399382 u2DelayCellOfst[3]=6 cells (2 PI)
8530 22:56:08.402634 u2DelayCellOfst[4]=3 cells (1 PI)
8531 22:56:08.406310 u2DelayCellOfst[5]=16 cells (5 PI)
8532 22:56:08.409070 u2DelayCellOfst[6]=16 cells (5 PI)
8533 22:56:08.412664 u2DelayCellOfst[7]=3 cells (1 PI)
8534 22:56:08.415938 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8535 22:56:08.419023 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8536 22:56:08.422491 == TX Byte 1 ==
8537 22:56:08.425681 u2DelayCellOfst[8]=0 cells (0 PI)
8538 22:56:08.426192 u2DelayCellOfst[9]=3 cells (1 PI)
8539 22:56:08.429276 u2DelayCellOfst[10]=10 cells (3 PI)
8540 22:56:08.432618 u2DelayCellOfst[11]=3 cells (1 PI)
8541 22:56:08.435992 u2DelayCellOfst[12]=13 cells (4 PI)
8542 22:56:08.438966 u2DelayCellOfst[13]=16 cells (5 PI)
8543 22:56:08.442960 u2DelayCellOfst[14]=16 cells (5 PI)
8544 22:56:08.445568 u2DelayCellOfst[15]=16 cells (5 PI)
8545 22:56:08.449051 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8546 22:56:08.456024 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8547 22:56:08.456530 DramC Write-DBI on
8548 22:56:08.457005 ==
8549 22:56:08.458918 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 22:56:08.465752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 22:56:08.466245 ==
8552 22:56:08.466579
8553 22:56:08.466884
8554 22:56:08.467178 TX Vref Scan disable
8555 22:56:08.469397 == TX Byte 0 ==
8556 22:56:08.473067 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8557 22:56:08.476044 == TX Byte 1 ==
8558 22:56:08.479473 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8559 22:56:08.483100 DramC Write-DBI off
8560 22:56:08.483666
8561 22:56:08.484030 [DATLAT]
8562 22:56:08.484369 Freq=1600, CH1 RK0
8563 22:56:08.484695
8564 22:56:08.486200 DATLAT Default: 0xf
8565 22:56:08.486662 0, 0xFFFF, sum = 0
8566 22:56:08.489651 1, 0xFFFF, sum = 0
8567 22:56:08.492761 2, 0xFFFF, sum = 0
8568 22:56:08.493230 3, 0xFFFF, sum = 0
8569 22:56:08.496361 4, 0xFFFF, sum = 0
8570 22:56:08.496932 5, 0xFFFF, sum = 0
8571 22:56:08.499472 6, 0xFFFF, sum = 0
8572 22:56:08.500046 7, 0xFFFF, sum = 0
8573 22:56:08.502660 8, 0xFFFF, sum = 0
8574 22:56:08.503128 9, 0xFFFF, sum = 0
8575 22:56:08.505883 10, 0xFFFF, sum = 0
8576 22:56:08.506353 11, 0xFFFF, sum = 0
8577 22:56:08.509459 12, 0xFFFF, sum = 0
8578 22:56:08.509930 13, 0xFFFF, sum = 0
8579 22:56:08.513223 14, 0x0, sum = 1
8580 22:56:08.513843 15, 0x0, sum = 2
8581 22:56:08.516488 16, 0x0, sum = 3
8582 22:56:08.517066 17, 0x0, sum = 4
8583 22:56:08.519577 best_step = 15
8584 22:56:08.520146
8585 22:56:08.520513 ==
8586 22:56:08.523086 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 22:56:08.525893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 22:56:08.526458 ==
8589 22:56:08.526826 RX Vref Scan: 1
8590 22:56:08.529387
8591 22:56:08.529862 Set Vref Range= 24 -> 127
8592 22:56:08.530227
8593 22:56:08.532842 RX Vref 24 -> 127, step: 1
8594 22:56:08.533441
8595 22:56:08.536181 RX Delay 19 -> 252, step: 4
8596 22:56:08.536743
8597 22:56:08.539497 Set Vref, RX VrefLevel [Byte0]: 24
8598 22:56:08.542720 [Byte1]: 24
8599 22:56:08.543288
8600 22:56:08.545959 Set Vref, RX VrefLevel [Byte0]: 25
8601 22:56:08.549522 [Byte1]: 25
8602 22:56:08.550089
8603 22:56:08.553008 Set Vref, RX VrefLevel [Byte0]: 26
8604 22:56:08.556010 [Byte1]: 26
8605 22:56:08.559689
8606 22:56:08.560247 Set Vref, RX VrefLevel [Byte0]: 27
8607 22:56:08.563197 [Byte1]: 27
8608 22:56:08.567737
8609 22:56:08.568299 Set Vref, RX VrefLevel [Byte0]: 28
8610 22:56:08.571002 [Byte1]: 28
8611 22:56:08.575193
8612 22:56:08.575755 Set Vref, RX VrefLevel [Byte0]: 29
8613 22:56:08.578375 [Byte1]: 29
8614 22:56:08.582514
8615 22:56:08.582979 Set Vref, RX VrefLevel [Byte0]: 30
8616 22:56:08.585906 [Byte1]: 30
8617 22:56:08.590269
8618 22:56:08.590828 Set Vref, RX VrefLevel [Byte0]: 31
8619 22:56:08.593228 [Byte1]: 31
8620 22:56:08.597726
8621 22:56:08.598286 Set Vref, RX VrefLevel [Byte0]: 32
8622 22:56:08.601216 [Byte1]: 32
8623 22:56:08.605601
8624 22:56:08.606170 Set Vref, RX VrefLevel [Byte0]: 33
8625 22:56:08.608607 [Byte1]: 33
8626 22:56:08.613051
8627 22:56:08.613666 Set Vref, RX VrefLevel [Byte0]: 34
8628 22:56:08.616228 [Byte1]: 34
8629 22:56:08.620445
8630 22:56:08.621004 Set Vref, RX VrefLevel [Byte0]: 35
8631 22:56:08.623746 [Byte1]: 35
8632 22:56:08.628237
8633 22:56:08.628799 Set Vref, RX VrefLevel [Byte0]: 36
8634 22:56:08.631384 [Byte1]: 36
8635 22:56:08.635674
8636 22:56:08.636237 Set Vref, RX VrefLevel [Byte0]: 37
8637 22:56:08.638648 [Byte1]: 37
8638 22:56:08.643342
8639 22:56:08.643917 Set Vref, RX VrefLevel [Byte0]: 38
8640 22:56:08.646247 [Byte1]: 38
8641 22:56:08.650956
8642 22:56:08.651528 Set Vref, RX VrefLevel [Byte0]: 39
8643 22:56:08.653995 [Byte1]: 39
8644 22:56:08.658156
8645 22:56:08.658615 Set Vref, RX VrefLevel [Byte0]: 40
8646 22:56:08.661636 [Byte1]: 40
8647 22:56:08.665829
8648 22:56:08.666527 Set Vref, RX VrefLevel [Byte0]: 41
8649 22:56:08.669343 [Byte1]: 41
8650 22:56:08.673551
8651 22:56:08.674107 Set Vref, RX VrefLevel [Byte0]: 42
8652 22:56:08.676697 [Byte1]: 42
8653 22:56:08.681216
8654 22:56:08.682098 Set Vref, RX VrefLevel [Byte0]: 43
8655 22:56:08.684633 [Byte1]: 43
8656 22:56:08.688885
8657 22:56:08.689491 Set Vref, RX VrefLevel [Byte0]: 44
8658 22:56:08.691826 [Byte1]: 44
8659 22:56:08.696055
8660 22:56:08.696619 Set Vref, RX VrefLevel [Byte0]: 45
8661 22:56:08.699696 [Byte1]: 45
8662 22:56:08.703646
8663 22:56:08.704212 Set Vref, RX VrefLevel [Byte0]: 46
8664 22:56:08.706837 [Byte1]: 46
8665 22:56:08.711626
8666 22:56:08.712184 Set Vref, RX VrefLevel [Byte0]: 47
8667 22:56:08.714452 [Byte1]: 47
8668 22:56:08.719119
8669 22:56:08.719680 Set Vref, RX VrefLevel [Byte0]: 48
8670 22:56:08.721898 [Byte1]: 48
8671 22:56:08.726795
8672 22:56:08.727356 Set Vref, RX VrefLevel [Byte0]: 49
8673 22:56:08.730165 [Byte1]: 49
8674 22:56:08.734378
8675 22:56:08.734983 Set Vref, RX VrefLevel [Byte0]: 50
8676 22:56:08.737258 [Byte1]: 50
8677 22:56:08.741739
8678 22:56:08.742315 Set Vref, RX VrefLevel [Byte0]: 51
8679 22:56:08.744812 [Byte1]: 51
8680 22:56:08.749153
8681 22:56:08.749764 Set Vref, RX VrefLevel [Byte0]: 52
8682 22:56:08.752286 [Byte1]: 52
8683 22:56:08.756387
8684 22:56:08.756846 Set Vref, RX VrefLevel [Byte0]: 53
8685 22:56:08.759827 [Byte1]: 53
8686 22:56:08.764204
8687 22:56:08.764765 Set Vref, RX VrefLevel [Byte0]: 54
8688 22:56:08.767546 [Byte1]: 54
8689 22:56:08.771980
8690 22:56:08.772608 Set Vref, RX VrefLevel [Byte0]: 55
8691 22:56:08.775155 [Byte1]: 55
8692 22:56:08.779190
8693 22:56:08.779652 Set Vref, RX VrefLevel [Byte0]: 56
8694 22:56:08.782894 [Byte1]: 56
8695 22:56:08.786724
8696 22:56:08.787181 Set Vref, RX VrefLevel [Byte0]: 57
8697 22:56:08.790530 [Byte1]: 57
8698 22:56:08.794664
8699 22:56:08.795224 Set Vref, RX VrefLevel [Byte0]: 58
8700 22:56:08.797810 [Byte1]: 58
8701 22:56:08.802461
8702 22:56:08.803061 Set Vref, RX VrefLevel [Byte0]: 59
8703 22:56:08.805942 [Byte1]: 59
8704 22:56:08.809764
8705 22:56:08.810326 Set Vref, RX VrefLevel [Byte0]: 60
8706 22:56:08.813037 [Byte1]: 60
8707 22:56:08.817502
8708 22:56:08.818067 Set Vref, RX VrefLevel [Byte0]: 61
8709 22:56:08.820836 [Byte1]: 61
8710 22:56:08.825013
8711 22:56:08.825626 Set Vref, RX VrefLevel [Byte0]: 62
8712 22:56:08.828522 [Byte1]: 62
8713 22:56:08.832551
8714 22:56:08.833113 Set Vref, RX VrefLevel [Byte0]: 63
8715 22:56:08.835919 [Byte1]: 63
8716 22:56:08.840183
8717 22:56:08.840744 Set Vref, RX VrefLevel [Byte0]: 64
8718 22:56:08.843422 [Byte1]: 64
8719 22:56:08.847749
8720 22:56:08.848315 Set Vref, RX VrefLevel [Byte0]: 65
8721 22:56:08.851275 [Byte1]: 65
8722 22:56:08.854886
8723 22:56:08.855351 Set Vref, RX VrefLevel [Byte0]: 66
8724 22:56:08.858322 [Byte1]: 66
8725 22:56:08.862793
8726 22:56:08.863256 Set Vref, RX VrefLevel [Byte0]: 67
8727 22:56:08.865647 [Byte1]: 67
8728 22:56:08.870258
8729 22:56:08.870894 Set Vref, RX VrefLevel [Byte0]: 68
8730 22:56:08.873685 [Byte1]: 68
8731 22:56:08.877966
8732 22:56:08.878426 Set Vref, RX VrefLevel [Byte0]: 69
8733 22:56:08.880960 [Byte1]: 69
8734 22:56:08.885477
8735 22:56:08.885957 Set Vref, RX VrefLevel [Byte0]: 70
8736 22:56:08.888723 [Byte1]: 70
8737 22:56:08.893441
8738 22:56:08.893990 Set Vref, RX VrefLevel [Byte0]: 71
8739 22:56:08.899440 [Byte1]: 71
8740 22:56:08.900004
8741 22:56:08.902739 Set Vref, RX VrefLevel [Byte0]: 72
8742 22:56:08.906373 [Byte1]: 72
8743 22:56:08.906961
8744 22:56:08.909589 Set Vref, RX VrefLevel [Byte0]: 73
8745 22:56:08.912779 [Byte1]: 73
8746 22:56:08.913389
8747 22:56:08.916378 Set Vref, RX VrefLevel [Byte0]: 74
8748 22:56:08.918998 [Byte1]: 74
8749 22:56:08.923695
8750 22:56:08.924267 Set Vref, RX VrefLevel [Byte0]: 75
8751 22:56:08.926631 [Byte1]: 75
8752 22:56:08.930708
8753 22:56:08.931269 Final RX Vref Byte 0 = 53 to rank0
8754 22:56:08.934197 Final RX Vref Byte 1 = 66 to rank0
8755 22:56:08.937980 Final RX Vref Byte 0 = 53 to rank1
8756 22:56:08.940952 Final RX Vref Byte 1 = 66 to rank1==
8757 22:56:08.944637 Dram Type= 6, Freq= 0, CH_1, rank 0
8758 22:56:08.950908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 22:56:08.951562 ==
8760 22:56:08.951939 DQS Delay:
8761 22:56:08.952281 DQS0 = 0, DQS1 = 0
8762 22:56:08.953977 DQM Delay:
8763 22:56:08.954443 DQM0 = 133, DQM1 = 129
8764 22:56:08.957523 DQ Delay:
8765 22:56:08.960826 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8766 22:56:08.964192 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8767 22:56:08.967229 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =120
8768 22:56:08.970732 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8769 22:56:08.971306
8770 22:56:08.971669
8771 22:56:08.972005
8772 22:56:08.973665 [DramC_TX_OE_Calibration] TA2
8773 22:56:08.977553 Original DQ_B0 (3 6) =30, OEN = 27
8774 22:56:08.980639 Original DQ_B1 (3 6) =30, OEN = 27
8775 22:56:08.983859 24, 0x0, End_B0=24 End_B1=24
8776 22:56:08.984328 25, 0x0, End_B0=25 End_B1=25
8777 22:56:08.987125 26, 0x0, End_B0=26 End_B1=26
8778 22:56:08.991370 27, 0x0, End_B0=27 End_B1=27
8779 22:56:08.994008 28, 0x0, End_B0=28 End_B1=28
8780 22:56:08.997585 29, 0x0, End_B0=29 End_B1=29
8781 22:56:08.998144 30, 0x0, End_B0=30 End_B1=30
8782 22:56:09.000531 31, 0x5151, End_B0=30 End_B1=30
8783 22:56:09.004383 Byte0 end_step=30 best_step=27
8784 22:56:09.006956 Byte1 end_step=30 best_step=27
8785 22:56:09.010671 Byte0 TX OE(2T, 0.5T) = (3, 3)
8786 22:56:09.014074 Byte1 TX OE(2T, 0.5T) = (3, 3)
8787 22:56:09.014538
8788 22:56:09.014900
8789 22:56:09.020391 [DQSOSCAuto] RK0, (LSB)MR18= 0x1928, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 397 ps
8790 22:56:09.023789 CH1 RK0: MR19=303, MR18=1928
8791 22:56:09.030275 CH1_RK0: MR19=0x303, MR18=0x1928, DQSOSC=389, MR23=63, INC=24, DEC=16
8792 22:56:09.030852
8793 22:56:09.033731 ----->DramcWriteLeveling(PI) begin...
8794 22:56:09.034303 ==
8795 22:56:09.037499 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 22:56:09.040551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 22:56:09.041020 ==
8798 22:56:09.043949 Write leveling (Byte 0): 25 => 25
8799 22:56:09.047046 Write leveling (Byte 1): 28 => 28
8800 22:56:09.050187 DramcWriteLeveling(PI) end<-----
8801 22:56:09.050650
8802 22:56:09.051090 ==
8803 22:56:09.053816 Dram Type= 6, Freq= 0, CH_1, rank 1
8804 22:56:09.057120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8805 22:56:09.057726 ==
8806 22:56:09.060053 [Gating] SW mode calibration
8807 22:56:09.067203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8808 22:56:09.073550 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8809 22:56:09.076860 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 22:56:09.080220 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 22:56:09.086912 1 4 8 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
8812 22:56:09.090076 1 4 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
8813 22:56:09.093283 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 22:56:09.100474 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 22:56:09.103567 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 22:56:09.106816 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 22:56:09.113559 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 22:56:09.116865 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 22:56:09.119968 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8820 22:56:09.126819 1 5 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 0)
8821 22:56:09.129829 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 22:56:09.133478 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 22:56:09.139863 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 22:56:09.142905 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 22:56:09.146472 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 22:56:09.153340 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8827 22:56:09.156438 1 6 8 | B1->B0 | 4545 2727 | 0 0 | (0 0) (0 0)
8828 22:56:09.159872 1 6 12 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
8829 22:56:09.166441 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 22:56:09.169839 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 22:56:09.173122 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 22:56:09.179565 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 22:56:09.183368 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 22:56:09.186442 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 22:56:09.193196 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8836 22:56:09.196506 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8837 22:56:09.199785 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 22:56:09.203188 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 22:56:09.210111 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 22:56:09.212912 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 22:56:09.216442 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 22:56:09.223523 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 22:56:09.226664 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 22:56:09.229754 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 22:56:09.236684 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 22:56:09.239490 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 22:56:09.242708 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 22:56:09.249812 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 22:56:09.253005 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 22:56:09.256134 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 22:56:09.262769 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8852 22:56:09.266205 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8853 22:56:09.269520 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 22:56:09.273020 Total UI for P1: 0, mck2ui 16
8855 22:56:09.276288 best dqsien dly found for B0: ( 1, 9, 10)
8856 22:56:09.279588 Total UI for P1: 0, mck2ui 16
8857 22:56:09.283233 best dqsien dly found for B1: ( 1, 9, 10)
8858 22:56:09.286008 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8859 22:56:09.289660 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8860 22:56:09.290253
8861 22:56:09.296411 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8862 22:56:09.299402 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8863 22:56:09.302478 [Gating] SW calibration Done
8864 22:56:09.302951 ==
8865 22:56:09.305957 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 22:56:09.309451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 22:56:09.310024 ==
8868 22:56:09.310432 RX Vref Scan: 0
8869 22:56:09.310776
8870 22:56:09.312724 RX Vref 0 -> 0, step: 1
8871 22:56:09.313281
8872 22:56:09.316266 RX Delay 0 -> 252, step: 8
8873 22:56:09.319291 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8874 22:56:09.322744 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8875 22:56:09.325729 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8876 22:56:09.333069 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8877 22:56:09.335853 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8878 22:56:09.339403 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8879 22:56:09.342536 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8880 22:56:09.346030 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8881 22:56:09.352607 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8882 22:56:09.356063 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8883 22:56:09.359097 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8884 22:56:09.363117 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8885 22:56:09.366311 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8886 22:56:09.372496 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8887 22:56:09.376110 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8888 22:56:09.378886 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8889 22:56:09.379352 ==
8890 22:56:09.382297 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 22:56:09.385888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 22:56:09.388978 ==
8893 22:56:09.389516 DQS Delay:
8894 22:56:09.389902 DQS0 = 0, DQS1 = 0
8895 22:56:09.392568 DQM Delay:
8896 22:56:09.393041 DQM0 = 136, DQM1 = 132
8897 22:56:09.395622 DQ Delay:
8898 22:56:09.398984 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8899 22:56:09.402395 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =139
8900 22:56:09.405508 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8901 22:56:09.408968 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8902 22:56:09.409701
8903 22:56:09.410087
8904 22:56:09.410431 ==
8905 22:56:09.412446 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 22:56:09.415669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 22:56:09.416144 ==
8908 22:56:09.416582
8909 22:56:09.419012
8910 22:56:09.419470 TX Vref Scan disable
8911 22:56:09.422114 == TX Byte 0 ==
8912 22:56:09.425343 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8913 22:56:09.429189 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8914 22:56:09.432453 == TX Byte 1 ==
8915 22:56:09.435676 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8916 22:56:09.439136 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8917 22:56:09.439604 ==
8918 22:56:09.442087 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 22:56:09.448879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 22:56:09.449489 ==
8921 22:56:09.461736
8922 22:56:09.464695 TX Vref early break, caculate TX vref
8923 22:56:09.468100 TX Vref=16, minBit 10, minWin=22, winSum=385
8924 22:56:09.471010 TX Vref=18, minBit 8, minWin=23, winSum=393
8925 22:56:09.474445 TX Vref=20, minBit 9, minWin=23, winSum=397
8926 22:56:09.477888 TX Vref=22, minBit 9, minWin=23, winSum=406
8927 22:56:09.481345 TX Vref=24, minBit 9, minWin=25, winSum=416
8928 22:56:09.487604 TX Vref=26, minBit 10, minWin=24, winSum=419
8929 22:56:09.491234 TX Vref=28, minBit 9, minWin=24, winSum=421
8930 22:56:09.494303 TX Vref=30, minBit 0, minWin=25, winSum=413
8931 22:56:09.497748 TX Vref=32, minBit 0, minWin=25, winSum=408
8932 22:56:09.500942 TX Vref=34, minBit 9, minWin=23, winSum=399
8933 22:56:09.504681 TX Vref=36, minBit 10, minWin=22, winSum=393
8934 22:56:09.510845 [TxChooseVref] Worse bit 9, Min win 25, Win sum 416, Final Vref 24
8935 22:56:09.511396
8936 22:56:09.514557 Final TX Range 0 Vref 24
8937 22:56:09.515136
8938 22:56:09.515500 ==
8939 22:56:09.517696 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 22:56:09.521070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 22:56:09.521656 ==
8942 22:56:09.524510
8943 22:56:09.525072
8944 22:56:09.525480 TX Vref Scan disable
8945 22:56:09.530992 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8946 22:56:09.531559 == TX Byte 0 ==
8947 22:56:09.534547 u2DelayCellOfst[0]=13 cells (4 PI)
8948 22:56:09.537896 u2DelayCellOfst[1]=10 cells (3 PI)
8949 22:56:09.540748 u2DelayCellOfst[2]=0 cells (0 PI)
8950 22:56:09.544340 u2DelayCellOfst[3]=3 cells (1 PI)
8951 22:56:09.547265 u2DelayCellOfst[4]=6 cells (2 PI)
8952 22:56:09.550761 u2DelayCellOfst[5]=16 cells (5 PI)
8953 22:56:09.554363 u2DelayCellOfst[6]=13 cells (4 PI)
8954 22:56:09.557764 u2DelayCellOfst[7]=3 cells (1 PI)
8955 22:56:09.560993 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8956 22:56:09.564920 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8957 22:56:09.567904 == TX Byte 1 ==
8958 22:56:09.570760 u2DelayCellOfst[8]=0 cells (0 PI)
8959 22:56:09.574527 u2DelayCellOfst[9]=6 cells (2 PI)
8960 22:56:09.575243 u2DelayCellOfst[10]=10 cells (3 PI)
8961 22:56:09.577785 u2DelayCellOfst[11]=6 cells (2 PI)
8962 22:56:09.580579 u2DelayCellOfst[12]=13 cells (4 PI)
8963 22:56:09.584210 u2DelayCellOfst[13]=16 cells (5 PI)
8964 22:56:09.587480 u2DelayCellOfst[14]=16 cells (5 PI)
8965 22:56:09.590529 u2DelayCellOfst[15]=20 cells (6 PI)
8966 22:56:09.597212 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8967 22:56:09.600612 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8968 22:56:09.601081 DramC Write-DBI on
8969 22:56:09.601489 ==
8970 22:56:09.604483 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 22:56:09.610653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 22:56:09.611210 ==
8973 22:56:09.611574
8974 22:56:09.611907
8975 22:56:09.612224 TX Vref Scan disable
8976 22:56:09.614539 == TX Byte 0 ==
8977 22:56:09.618096 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8978 22:56:09.621164 == TX Byte 1 ==
8979 22:56:09.624658 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8980 22:56:09.627984 DramC Write-DBI off
8981 22:56:09.628550
8982 22:56:09.628915 [DATLAT]
8983 22:56:09.629252 Freq=1600, CH1 RK1
8984 22:56:09.629611
8985 22:56:09.631612 DATLAT Default: 0xf
8986 22:56:09.632181 0, 0xFFFF, sum = 0
8987 22:56:09.634840 1, 0xFFFF, sum = 0
8988 22:56:09.635411 2, 0xFFFF, sum = 0
8989 22:56:09.638045 3, 0xFFFF, sum = 0
8990 22:56:09.641059 4, 0xFFFF, sum = 0
8991 22:56:09.641551 5, 0xFFFF, sum = 0
8992 22:56:09.645075 6, 0xFFFF, sum = 0
8993 22:56:09.645679 7, 0xFFFF, sum = 0
8994 22:56:09.648474 8, 0xFFFF, sum = 0
8995 22:56:09.649045 9, 0xFFFF, sum = 0
8996 22:56:09.651518 10, 0xFFFF, sum = 0
8997 22:56:09.651988 11, 0xFFFF, sum = 0
8998 22:56:09.654709 12, 0xFFFF, sum = 0
8999 22:56:09.655181 13, 0xFFFF, sum = 0
9000 22:56:09.657802 14, 0x0, sum = 1
9001 22:56:09.658272 15, 0x0, sum = 2
9002 22:56:09.661365 16, 0x0, sum = 3
9003 22:56:09.661832 17, 0x0, sum = 4
9004 22:56:09.664639 best_step = 15
9005 22:56:09.665198
9006 22:56:09.665603 ==
9007 22:56:09.667983 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 22:56:09.671684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 22:56:09.672251 ==
9010 22:56:09.672624 RX Vref Scan: 0
9011 22:56:09.674608
9012 22:56:09.675173 RX Vref 0 -> 0, step: 1
9013 22:56:09.675542
9014 22:56:09.677909 RX Delay 19 -> 252, step: 4
9015 22:56:09.681208 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9016 22:56:09.687813 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
9017 22:56:09.691372 iDelay=195, Bit 2, Center 118 (71 ~ 166) 96
9018 22:56:09.694845 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9019 22:56:09.697414 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9020 22:56:09.700986 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9021 22:56:09.704717 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9022 22:56:09.711096 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9023 22:56:09.714440 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
9024 22:56:09.717683 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9025 22:56:09.721014 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9026 22:56:09.724590 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9027 22:56:09.731022 iDelay=195, Bit 12, Center 138 (91 ~ 186) 96
9028 22:56:09.734354 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9029 22:56:09.737462 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9030 22:56:09.740963 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9031 22:56:09.741557 ==
9032 22:56:09.744473 Dram Type= 6, Freq= 0, CH_1, rank 1
9033 22:56:09.747783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9034 22:56:09.750994 ==
9035 22:56:09.751561 DQS Delay:
9036 22:56:09.751927 DQS0 = 0, DQS1 = 0
9037 22:56:09.754482 DQM Delay:
9038 22:56:09.755050 DQM0 = 133, DQM1 = 130
9039 22:56:09.757584 DQ Delay:
9040 22:56:09.761172 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =130
9041 22:56:09.764203 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9042 22:56:09.767724 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =126
9043 22:56:09.770928 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
9044 22:56:09.771496
9045 22:56:09.771861
9046 22:56:09.772195
9047 22:56:09.774585 [DramC_TX_OE_Calibration] TA2
9048 22:56:09.777699 Original DQ_B0 (3 6) =30, OEN = 27
9049 22:56:09.780790 Original DQ_B1 (3 6) =30, OEN = 27
9050 22:56:09.784287 24, 0x0, End_B0=24 End_B1=24
9051 22:56:09.784856 25, 0x0, End_B0=25 End_B1=25
9052 22:56:09.787194 26, 0x0, End_B0=26 End_B1=26
9053 22:56:09.790629 27, 0x0, End_B0=27 End_B1=27
9054 22:56:09.794533 28, 0x0, End_B0=28 End_B1=28
9055 22:56:09.795101 29, 0x0, End_B0=29 End_B1=29
9056 22:56:09.797473 30, 0x0, End_B0=30 End_B1=30
9057 22:56:09.801100 31, 0x4141, End_B0=30 End_B1=30
9058 22:56:09.804257 Byte0 end_step=30 best_step=27
9059 22:56:09.807646 Byte1 end_step=30 best_step=27
9060 22:56:09.810584 Byte0 TX OE(2T, 0.5T) = (3, 3)
9061 22:56:09.811074 Byte1 TX OE(2T, 0.5T) = (3, 3)
9062 22:56:09.811448
9063 22:56:09.813731
9064 22:56:09.820866 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9065 22:56:09.824593 CH1 RK1: MR19=303, MR18=1E09
9066 22:56:09.830588 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9067 22:56:09.833904 [RxdqsGatingPostProcess] freq 1600
9068 22:56:09.837322 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9069 22:56:09.840902 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 22:56:09.843757 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 22:56:09.847992 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 22:56:09.852537 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 22:56:09.854260 best DQS0 dly(2T, 0.5T) = (1, 1)
9074 22:56:09.857615 best DQS1 dly(2T, 0.5T) = (1, 1)
9075 22:56:09.860717 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9076 22:56:09.863894 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9077 22:56:09.864362 Pre-setting of DQS Precalculation
9078 22:56:09.870337 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9079 22:56:09.877352 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9080 22:56:09.883884 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 22:56:09.884448
9082 22:56:09.884815
9083 22:56:09.886726 [Calibration Summary] 3200 Mbps
9084 22:56:09.890517 CH 0, Rank 0
9085 22:56:09.891078 SW Impedance : PASS
9086 22:56:09.893973 DUTY Scan : NO K
9087 22:56:09.897186 ZQ Calibration : PASS
9088 22:56:09.897827 Jitter Meter : NO K
9089 22:56:09.900376 CBT Training : PASS
9090 22:56:09.903715 Write leveling : PASS
9091 22:56:09.904280 RX DQS gating : PASS
9092 22:56:09.907068 RX DQ/DQS(RDDQC) : PASS
9093 22:56:09.910150 TX DQ/DQS : PASS
9094 22:56:09.910617 RX DATLAT : PASS
9095 22:56:09.914116 RX DQ/DQS(Engine): PASS
9096 22:56:09.914683 TX OE : PASS
9097 22:56:09.917108 All Pass.
9098 22:56:09.917713
9099 22:56:09.918078 CH 0, Rank 1
9100 22:56:09.920094 SW Impedance : PASS
9101 22:56:09.920601 DUTY Scan : NO K
9102 22:56:09.923405 ZQ Calibration : PASS
9103 22:56:09.927313 Jitter Meter : NO K
9104 22:56:09.927883 CBT Training : PASS
9105 22:56:09.930058 Write leveling : PASS
9106 22:56:09.933822 RX DQS gating : PASS
9107 22:56:09.934430 RX DQ/DQS(RDDQC) : PASS
9108 22:56:09.936668 TX DQ/DQS : PASS
9109 22:56:09.940417 RX DATLAT : PASS
9110 22:56:09.940886 RX DQ/DQS(Engine): PASS
9111 22:56:09.943645 TX OE : PASS
9112 22:56:09.944115 All Pass.
9113 22:56:09.944481
9114 22:56:09.947034 CH 1, Rank 0
9115 22:56:09.947604 SW Impedance : PASS
9116 22:56:09.950552 DUTY Scan : NO K
9117 22:56:09.953741 ZQ Calibration : PASS
9118 22:56:09.954310 Jitter Meter : NO K
9119 22:56:09.956983 CBT Training : PASS
9120 22:56:09.960262 Write leveling : PASS
9121 22:56:09.960832 RX DQS gating : PASS
9122 22:56:09.963595 RX DQ/DQS(RDDQC) : PASS
9123 22:56:09.966725 TX DQ/DQS : PASS
9124 22:56:09.967347 RX DATLAT : PASS
9125 22:56:09.970396 RX DQ/DQS(Engine): PASS
9126 22:56:09.970969 TX OE : PASS
9127 22:56:09.973477 All Pass.
9128 22:56:09.974045
9129 22:56:09.974413 CH 1, Rank 1
9130 22:56:09.977145 SW Impedance : PASS
9131 22:56:09.977747 DUTY Scan : NO K
9132 22:56:09.980394 ZQ Calibration : PASS
9133 22:56:09.983527 Jitter Meter : NO K
9134 22:56:09.984098 CBT Training : PASS
9135 22:56:09.986698 Write leveling : PASS
9136 22:56:09.989860 RX DQS gating : PASS
9137 22:56:09.990328 RX DQ/DQS(RDDQC) : PASS
9138 22:56:09.993140 TX DQ/DQS : PASS
9139 22:56:09.997163 RX DATLAT : PASS
9140 22:56:09.997955 RX DQ/DQS(Engine): PASS
9141 22:56:10.000154 TX OE : PASS
9142 22:56:10.000719 All Pass.
9143 22:56:10.001085
9144 22:56:10.003816 DramC Write-DBI on
9145 22:56:10.007036 PER_BANK_REFRESH: Hybrid Mode
9146 22:56:10.007609 TX_TRACKING: ON
9147 22:56:10.016792 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9148 22:56:10.023386 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9149 22:56:10.030001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9150 22:56:10.033193 [FAST_K] Save calibration result to emmc
9151 22:56:10.036729 sync common calibartion params.
9152 22:56:10.039919 sync cbt_mode0:1, 1:1
9153 22:56:10.043089 dram_init: ddr_geometry: 2
9154 22:56:10.043556 dram_init: ddr_geometry: 2
9155 22:56:10.046636 dram_init: ddr_geometry: 2
9156 22:56:10.049869 0:dram_rank_size:100000000
9157 22:56:10.050450 1:dram_rank_size:100000000
9158 22:56:10.056784 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9159 22:56:10.060304 DFS_SHUFFLE_HW_MODE: ON
9160 22:56:10.063112 dramc_set_vcore_voltage set vcore to 725000
9161 22:56:10.067038 Read voltage for 1600, 0
9162 22:56:10.067606 Vio18 = 0
9163 22:56:10.067981 Vcore = 725000
9164 22:56:10.069730 Vdram = 0
9165 22:56:10.070199 Vddq = 0
9166 22:56:10.070565 Vmddr = 0
9167 22:56:10.073397 switch to 3200 Mbps bootup
9168 22:56:10.073968 [DramcRunTimeConfig]
9169 22:56:10.076740 PHYPLL
9170 22:56:10.077350 DPM_CONTROL_AFTERK: ON
9171 22:56:10.079817 PER_BANK_REFRESH: ON
9172 22:56:10.082899 REFRESH_OVERHEAD_REDUCTION: ON
9173 22:56:10.083371 CMD_PICG_NEW_MODE: OFF
9174 22:56:10.086345 XRTWTW_NEW_MODE: ON
9175 22:56:10.086912 XRTRTR_NEW_MODE: ON
9176 22:56:10.089789 TX_TRACKING: ON
9177 22:56:10.090266 RDSEL_TRACKING: OFF
9178 22:56:10.092925 DQS Precalculation for DVFS: ON
9179 22:56:10.096960 RX_TRACKING: OFF
9180 22:56:10.097576 HW_GATING DBG: ON
9181 22:56:10.099980 ZQCS_ENABLE_LP4: ON
9182 22:56:10.100561 RX_PICG_NEW_MODE: ON
9183 22:56:10.103197 TX_PICG_NEW_MODE: ON
9184 22:56:10.106001 ENABLE_RX_DCM_DPHY: ON
9185 22:56:10.106477 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9186 22:56:10.109470 DUMMY_READ_FOR_TRACKING: OFF
9187 22:56:10.112745 !!! SPM_CONTROL_AFTERK: OFF
9188 22:56:10.116130 !!! SPM could not control APHY
9189 22:56:10.116694 IMPEDANCE_TRACKING: ON
9190 22:56:10.119572 TEMP_SENSOR: ON
9191 22:56:10.120037 HW_SAVE_FOR_SR: OFF
9192 22:56:10.122660 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9193 22:56:10.126060 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9194 22:56:10.129390 Read ODT Tracking: ON
9195 22:56:10.133047 Refresh Rate DeBounce: ON
9196 22:56:10.133657 DFS_NO_QUEUE_FLUSH: ON
9197 22:56:10.135985 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9198 22:56:10.139731 ENABLE_DFS_RUNTIME_MRW: OFF
9199 22:56:10.142727 DDR_RESERVE_NEW_MODE: ON
9200 22:56:10.143195 MR_CBT_SWITCH_FREQ: ON
9201 22:56:10.145809 =========================
9202 22:56:10.165227 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9203 22:56:10.168822 dram_init: ddr_geometry: 2
9204 22:56:10.187021 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9205 22:56:10.190288 dram_init: dram init end (result: 0)
9206 22:56:10.196864 DRAM-K: Full calibration passed in 24540 msecs
9207 22:56:10.200364 MRC: failed to locate region type 0.
9208 22:56:10.200925 DRAM rank0 size:0x100000000,
9209 22:56:10.204014 DRAM rank1 size=0x100000000
9210 22:56:10.213885 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9211 22:56:10.219833 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9212 22:56:10.226731 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9213 22:56:10.233655 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9214 22:56:10.236999 DRAM rank0 size:0x100000000,
9215 22:56:10.239721 DRAM rank1 size=0x100000000
9216 22:56:10.240183 CBMEM:
9217 22:56:10.243483 IMD: root @ 0xfffff000 254 entries.
9218 22:56:10.246680 IMD: root @ 0xffffec00 62 entries.
9219 22:56:10.250001 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9220 22:56:10.253063 WARNING: RO_VPD is uninitialized or empty.
9221 22:56:10.259904 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9222 22:56:10.266609 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9223 22:56:10.279962 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9224 22:56:10.290912 BS: romstage times (exec / console): total (unknown) / 24032 ms
9225 22:56:10.291462
9226 22:56:10.291824
9227 22:56:10.301175 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9228 22:56:10.304479 ARM64: Exception handlers installed.
9229 22:56:10.307521 ARM64: Testing exception
9230 22:56:10.311378 ARM64: Done test exception
9231 22:56:10.312003 Enumerating buses...
9232 22:56:10.313968 Show all devs... Before device enumeration.
9233 22:56:10.317756 Root Device: enabled 1
9234 22:56:10.321120 CPU_CLUSTER: 0: enabled 1
9235 22:56:10.321623 CPU: 00: enabled 1
9236 22:56:10.324449 Compare with tree...
9237 22:56:10.324910 Root Device: enabled 1
9238 22:56:10.327480 CPU_CLUSTER: 0: enabled 1
9239 22:56:10.331140 CPU: 00: enabled 1
9240 22:56:10.331702 Root Device scanning...
9241 22:56:10.334081 scan_static_bus for Root Device
9242 22:56:10.337610 CPU_CLUSTER: 0 enabled
9243 22:56:10.340680 scan_static_bus for Root Device done
9244 22:56:10.344043 scan_bus: bus Root Device finished in 8 msecs
9245 22:56:10.344510 done
9246 22:56:10.350644 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9247 22:56:10.354139 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9248 22:56:10.360988 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9249 22:56:10.364020 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9250 22:56:10.367646 Allocating resources...
9251 22:56:10.370758 Reading resources...
9252 22:56:10.373958 Root Device read_resources bus 0 link: 0
9253 22:56:10.374425 DRAM rank0 size:0x100000000,
9254 22:56:10.377264 DRAM rank1 size=0x100000000
9255 22:56:10.380686 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9256 22:56:10.383846 CPU: 00 missing read_resources
9257 22:56:10.387150 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9258 22:56:10.394188 Root Device read_resources bus 0 link: 0 done
9259 22:56:10.394739 Done reading resources.
9260 22:56:10.400313 Show resources in subtree (Root Device)...After reading.
9261 22:56:10.404109 Root Device child on link 0 CPU_CLUSTER: 0
9262 22:56:10.407412 CPU_CLUSTER: 0 child on link 0 CPU: 00
9263 22:56:10.417137 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9264 22:56:10.417771 CPU: 00
9265 22:56:10.420284 Root Device assign_resources, bus 0 link: 0
9266 22:56:10.423977 CPU_CLUSTER: 0 missing set_resources
9267 22:56:10.430409 Root Device assign_resources, bus 0 link: 0 done
9268 22:56:10.431202 Done setting resources.
9269 22:56:10.436647 Show resources in subtree (Root Device)...After assigning values.
9270 22:56:10.439934 Root Device child on link 0 CPU_CLUSTER: 0
9271 22:56:10.443341 CPU_CLUSTER: 0 child on link 0 CPU: 00
9272 22:56:10.453207 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9273 22:56:10.453347 CPU: 00
9274 22:56:10.456658 Done allocating resources.
9275 22:56:10.460001 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9276 22:56:10.463756 Enabling resources...
9277 22:56:10.463929 done.
9278 22:56:10.469905 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9279 22:56:10.470084 Initializing devices...
9280 22:56:10.473680 Root Device init
9281 22:56:10.473865 init hardware done!
9282 22:56:10.476556 0x00000018: ctrlr->caps
9283 22:56:10.480343 52.000 MHz: ctrlr->f_max
9284 22:56:10.480558 0.400 MHz: ctrlr->f_min
9285 22:56:10.483719 0x40ff8080: ctrlr->voltages
9286 22:56:10.483935 sclk: 390625
9287 22:56:10.486877 Bus Width = 1
9288 22:56:10.487105 sclk: 390625
9289 22:56:10.490294 Bus Width = 1
9290 22:56:10.490542 Early init status = 3
9291 22:56:10.496643 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9292 22:56:10.499845 in-header: 03 fc 00 00 01 00 00 00
9293 22:56:10.500052 in-data: 00
9294 22:56:10.507516 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9295 22:56:10.510507 in-header: 03 fd 00 00 00 00 00 00
9296 22:56:10.513112 in-data:
9297 22:56:10.517186 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9298 22:56:10.520038 in-header: 03 fc 00 00 01 00 00 00
9299 22:56:10.523638 in-data: 00
9300 22:56:10.526718 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9301 22:56:10.531281 in-header: 03 fd 00 00 00 00 00 00
9302 22:56:10.534301 in-data:
9303 22:56:10.537761 [SSUSB] Setting up USB HOST controller...
9304 22:56:10.541285 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9305 22:56:10.544371 [SSUSB] phy power-on done.
9306 22:56:10.547683 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9307 22:56:10.553915 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9308 22:56:10.557335 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9309 22:56:10.564177 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9310 22:56:10.570806 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9311 22:56:10.577548 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9312 22:56:10.584042 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9313 22:56:10.590585 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9314 22:56:10.593843 SPM: binary array size = 0x9dc
9315 22:56:10.597451 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9316 22:56:10.604185 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9317 22:56:10.610792 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9318 22:56:10.613977 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9319 22:56:10.620478 configure_display: Starting display init
9320 22:56:10.654323 anx7625_power_on_init: Init interface.
9321 22:56:10.657700 anx7625_disable_pd_protocol: Disabled PD feature.
9322 22:56:10.660786 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9323 22:56:10.688955 anx7625_start_dp_work: Secure OCM version=00
9324 22:56:10.691636 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9325 22:56:10.706861 sp_tx_get_edid_block: EDID Block = 1
9326 22:56:10.809438 Extracted contents:
9327 22:56:10.812876 header: 00 ff ff ff ff ff ff 00
9328 22:56:10.816101 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9329 22:56:10.819351 version: 01 04
9330 22:56:10.822364 basic params: 95 1f 11 78 0a
9331 22:56:10.825654 chroma info: 76 90 94 55 54 90 27 21 50 54
9332 22:56:10.829015 established: 00 00 00
9333 22:56:10.835884 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9334 22:56:10.839045 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9335 22:56:10.845583 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9336 22:56:10.852577 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9337 22:56:10.859267 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9338 22:56:10.862342 extensions: 00
9339 22:56:10.862803 checksum: fb
9340 22:56:10.863167
9341 22:56:10.865523 Manufacturer: IVO Model 57d Serial Number 0
9342 22:56:10.869094 Made week 0 of 2020
9343 22:56:10.869888 EDID version: 1.4
9344 22:56:10.872205 Digital display
9345 22:56:10.875652 6 bits per primary color channel
9346 22:56:10.876119 DisplayPort interface
9347 22:56:10.879103 Maximum image size: 31 cm x 17 cm
9348 22:56:10.882156 Gamma: 220%
9349 22:56:10.882616 Check DPMS levels
9350 22:56:10.885279 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9351 22:56:10.888907 First detailed timing is preferred timing
9352 22:56:10.892068 Established timings supported:
9353 22:56:10.895890 Standard timings supported:
9354 22:56:10.899362 Detailed timings
9355 22:56:10.902461 Hex of detail: 383680a07038204018303c0035ae10000019
9356 22:56:10.905736 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9357 22:56:10.912374 0780 0798 07c8 0820 hborder 0
9358 22:56:10.915544 0438 043b 0447 0458 vborder 0
9359 22:56:10.919038 -hsync -vsync
9360 22:56:10.919590 Did detailed timing
9361 22:56:10.922145 Hex of detail: 000000000000000000000000000000000000
9362 22:56:10.925441 Manufacturer-specified data, tag 0
9363 22:56:10.932171 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9364 22:56:10.932723 ASCII string: InfoVision
9365 22:56:10.938748 Hex of detail: 000000fe00523134304e574635205248200a
9366 22:56:10.942238 ASCII string: R140NWF5 RH
9367 22:56:10.942793 Checksum
9368 22:56:10.943235 Checksum: 0xfb (valid)
9369 22:56:10.948849 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9370 22:56:10.952311 DSI data_rate: 832800000 bps
9371 22:56:10.955369 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9372 22:56:10.962309 anx7625_parse_edid: pixelclock(138800).
9373 22:56:10.965276 hactive(1920), hsync(48), hfp(24), hbp(88)
9374 22:56:10.968643 vactive(1080), vsync(12), vfp(3), vbp(17)
9375 22:56:10.972127 anx7625_dsi_config: config dsi.
9376 22:56:10.978636 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9377 22:56:10.991462 anx7625_dsi_config: success to config DSI
9378 22:56:10.994549 anx7625_dp_start: MIPI phy setup OK.
9379 22:56:10.998184 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9380 22:56:11.001497 mtk_ddp_mode_set invalid vrefresh 60
9381 22:56:11.004773 main_disp_path_setup
9382 22:56:11.005372 ovl_layer_smi_id_en
9383 22:56:11.007969 ovl_layer_smi_id_en
9384 22:56:11.008429 ccorr_config
9385 22:56:11.008785 aal_config
9386 22:56:11.011406 gamma_config
9387 22:56:11.011958 postmask_config
9388 22:56:11.014733 dither_config
9389 22:56:11.017847 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9390 22:56:11.024444 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9391 22:56:11.027995 Root Device init finished in 551 msecs
9392 22:56:11.028552 CPU_CLUSTER: 0 init
9393 22:56:11.038112 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9394 22:56:11.041213 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9395 22:56:11.044663 APU_MBOX 0x190000b0 = 0x10001
9396 22:56:11.048276 APU_MBOX 0x190001b0 = 0x10001
9397 22:56:11.051329 APU_MBOX 0x190005b0 = 0x10001
9398 22:56:11.054598 APU_MBOX 0x190006b0 = 0x10001
9399 22:56:11.057655 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9400 22:56:11.070056 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9401 22:56:11.083143 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9402 22:56:11.089341 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9403 22:56:11.101396 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9404 22:56:11.110005 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9405 22:56:11.113821 CPU_CLUSTER: 0 init finished in 81 msecs
9406 22:56:11.116926 Devices initialized
9407 22:56:11.120555 Show all devs... After init.
9408 22:56:11.121119 Root Device: enabled 1
9409 22:56:11.123560 CPU_CLUSTER: 0: enabled 1
9410 22:56:11.127248 CPU: 00: enabled 1
9411 22:56:11.130043 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9412 22:56:11.133631 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9413 22:56:11.136583 ELOG: NV offset 0x57f000 size 0x1000
9414 22:56:11.143421 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9415 22:56:11.150203 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9416 22:56:11.153551 ELOG: Event(17) added with size 13 at 2024-05-07 22:54:59 UTC
9417 22:56:11.156364 out: cmd=0x121: 03 db 21 01 00 00 00 00
9418 22:56:11.161423 in-header: 03 40 00 00 2c 00 00 00
9419 22:56:11.174636 in-data: ff 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9420 22:56:11.181414 ELOG: Event(A1) added with size 10 at 2024-05-07 22:54:59 UTC
9421 22:56:11.187900 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9422 22:56:11.194377 ELOG: Event(A0) added with size 9 at 2024-05-07 22:54:59 UTC
9423 22:56:11.197872 elog_add_boot_reason: Logged dev mode boot
9424 22:56:11.201148 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9425 22:56:11.204783 Finalize devices...
9426 22:56:11.205393 Devices finalized
9427 22:56:11.211203 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9428 22:56:11.214219 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9429 22:56:11.217984 in-header: 03 07 00 00 08 00 00 00
9430 22:56:11.221248 in-data: aa e4 47 04 13 02 00 00
9431 22:56:11.224453 Chrome EC: UHEPI supported
9432 22:56:11.231000 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9433 22:56:11.234304 in-header: 03 a9 00 00 08 00 00 00
9434 22:56:11.237746 in-data: 84 60 60 08 00 00 00 00
9435 22:56:11.240821 ELOG: Event(91) added with size 10 at 2024-05-07 22:54:59 UTC
9436 22:56:11.247483 Chrome EC: clear events_b mask to 0x0000000020004000
9437 22:56:11.254281 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9438 22:56:11.257895 in-header: 03 fd 00 00 00 00 00 00
9439 22:56:11.258499 in-data:
9440 22:56:11.264663 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9441 22:56:11.268056 Writing coreboot table at 0xffe64000
9442 22:56:11.271272 0. 000000000010a000-0000000000113fff: RAMSTAGE
9443 22:56:11.274132 1. 0000000040000000-00000000400fffff: RAM
9444 22:56:11.277996 2. 0000000040100000-000000004032afff: RAMSTAGE
9445 22:56:11.280905 3. 000000004032b000-00000000545fffff: RAM
9446 22:56:11.287923 4. 0000000054600000-000000005465ffff: BL31
9447 22:56:11.290714 5. 0000000054660000-00000000ffe63fff: RAM
9448 22:56:11.293938 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9449 22:56:11.300978 7. 0000000100000000-000000023fffffff: RAM
9450 22:56:11.301589 Passing 5 GPIOs to payload:
9451 22:56:11.308070 NAME | PORT | POLARITY | VALUE
9452 22:56:11.310516 EC in RW | 0x000000aa | low | undefined
9453 22:56:11.313876 EC interrupt | 0x00000005 | low | undefined
9454 22:56:11.320739 TPM interrupt | 0x000000ab | high | undefined
9455 22:56:11.323815 SD card detect | 0x00000011 | high | undefined
9456 22:56:11.330868 speaker enable | 0x00000093 | high | undefined
9457 22:56:11.334163 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9458 22:56:11.337343 in-header: 03 f9 00 00 02 00 00 00
9459 22:56:11.337922 in-data: 02 00
9460 22:56:11.340913 ADC[4]: Raw value=900295 ID=7
9461 22:56:11.344077 ADC[3]: Raw value=213179 ID=1
9462 22:56:11.344651 RAM Code: 0x71
9463 22:56:11.347572 ADC[6]: Raw value=74502 ID=0
9464 22:56:11.350635 ADC[5]: Raw value=212441 ID=1
9465 22:56:11.351208 SKU Code: 0x1
9466 22:56:11.357575 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ac7a
9467 22:56:11.360576 coreboot table: 964 bytes.
9468 22:56:11.364085 IMD ROOT 0. 0xfffff000 0x00001000
9469 22:56:11.367531 IMD SMALL 1. 0xffffe000 0x00001000
9470 22:56:11.370542 RO MCACHE 2. 0xffffc000 0x00001104
9471 22:56:11.374208 CONSOLE 3. 0xfff7c000 0x00080000
9472 22:56:11.377234 FMAP 4. 0xfff7b000 0x00000452
9473 22:56:11.380278 TIME STAMP 5. 0xfff7a000 0x00000910
9474 22:56:11.383804 VBOOT WORK 6. 0xfff66000 0x00014000
9475 22:56:11.387283 RAMOOPS 7. 0xffe66000 0x00100000
9476 22:56:11.390924 COREBOOT 8. 0xffe64000 0x00002000
9477 22:56:11.391496 IMD small region:
9478 22:56:11.393846 IMD ROOT 0. 0xffffec00 0x00000400
9479 22:56:11.397081 VPD 1. 0xffffeb80 0x0000006c
9480 22:56:11.400394 MMC STATUS 2. 0xffffeb60 0x00000004
9481 22:56:11.407238 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9482 22:56:11.414024 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9483 22:56:11.452979 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9484 22:56:11.456268 Checking segment from ROM address 0x40100000
9485 22:56:11.459702 Checking segment from ROM address 0x4010001c
9486 22:56:11.466012 Loading segment from ROM address 0x40100000
9487 22:56:11.466584 code (compression=0)
9488 22:56:11.475954 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9489 22:56:11.482737 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9490 22:56:11.483260 it's not compressed!
9491 22:56:11.489228 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9492 22:56:11.493112 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9493 22:56:11.513628 Loading segment from ROM address 0x4010001c
9494 22:56:11.514196 Entry Point 0x80000000
9495 22:56:11.516220 Loaded segments
9496 22:56:11.520154 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9497 22:56:11.526961 Jumping to boot code at 0x80000000(0xffe64000)
9498 22:56:11.533240 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9499 22:56:11.539990 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9500 22:56:11.547994 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9501 22:56:11.551127 Checking segment from ROM address 0x40100000
9502 22:56:11.554280 Checking segment from ROM address 0x4010001c
9503 22:56:11.561138 Loading segment from ROM address 0x40100000
9504 22:56:11.561760 code (compression=1)
9505 22:56:11.568176 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9506 22:56:11.578210 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9507 22:56:11.578782 using LZMA
9508 22:56:11.585996 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9509 22:56:11.592549 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9510 22:56:11.595827 Loading segment from ROM address 0x4010001c
9511 22:56:11.596295 Entry Point 0x54601000
9512 22:56:11.599066 Loaded segments
9513 22:56:11.602477 NOTICE: MT8192 bl31_setup
9514 22:56:11.609253 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9515 22:56:11.612869 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9516 22:56:11.616210 WARNING: region 0:
9517 22:56:11.619604 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 22:56:11.620072 WARNING: region 1:
9519 22:56:11.626714 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9520 22:56:11.629456 WARNING: region 2:
9521 22:56:11.633224 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9522 22:56:11.636518 WARNING: region 3:
9523 22:56:11.639564 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 22:56:11.642785 WARNING: region 4:
9525 22:56:11.649656 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9526 22:56:11.650188 WARNING: region 5:
9527 22:56:11.653169 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 22:56:11.656559 WARNING: region 6:
9529 22:56:11.659453 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 22:56:11.663060 WARNING: region 7:
9531 22:56:11.666228 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 22:56:11.672732 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9533 22:56:11.675903 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9534 22:56:11.679786 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9535 22:56:11.686195 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9536 22:56:11.689599 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9537 22:56:11.692815 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9538 22:56:11.699192 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9539 22:56:11.702351 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9540 22:56:11.709152 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9541 22:56:11.712669 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9542 22:56:11.715927 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9543 22:56:11.722148 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9544 22:56:11.725612 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9545 22:56:11.729057 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9546 22:56:11.735366 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9547 22:56:11.739130 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9548 22:56:11.745551 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9549 22:56:11.748720 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9550 22:56:11.752069 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9551 22:56:11.759377 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9552 22:56:11.762332 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9553 22:56:11.769151 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9554 22:56:11.772515 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9555 22:56:11.775570 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9556 22:56:11.782267 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9557 22:56:11.785525 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9558 22:56:11.792484 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9559 22:56:11.795761 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9560 22:56:11.799192 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9561 22:56:11.805457 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9562 22:56:11.809205 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9563 22:56:11.812243 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9564 22:56:11.819069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9565 22:56:11.822182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9566 22:56:11.825528 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9567 22:56:11.829409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9568 22:56:11.835609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9569 22:56:11.838958 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9570 22:56:11.842112 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9571 22:56:11.845830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9572 22:56:11.852949 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9573 22:56:11.855650 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9574 22:56:11.859093 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9575 22:56:11.862263 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9576 22:56:11.869183 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9577 22:56:11.872496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9578 22:56:11.875409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9579 22:56:11.879395 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9580 22:56:11.885908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9581 22:56:11.889048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9582 22:56:11.896202 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9583 22:56:11.899180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9584 22:56:11.905634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9585 22:56:11.908817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9586 22:56:11.912471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9587 22:56:11.918718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9588 22:56:11.922163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9589 22:56:11.929358 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9590 22:56:11.931942 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9591 22:56:11.939275 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9592 22:56:11.942145 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9593 22:56:11.948668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9594 22:56:11.952095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9595 22:56:11.955480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9596 22:56:11.961690 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9597 22:56:11.965212 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9598 22:56:11.971910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9599 22:56:11.975524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9600 22:56:11.982207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9601 22:56:11.985050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9602 22:56:11.988805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9603 22:56:11.995160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9604 22:56:11.998381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9605 22:56:12.005281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9606 22:56:12.008656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9607 22:56:12.014875 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9608 22:56:12.018696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9609 22:56:12.021793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9610 22:56:12.028437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9611 22:56:12.031509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9612 22:56:12.038049 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9613 22:56:12.041632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9614 22:56:12.048178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9615 22:56:12.051546 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9616 22:56:12.055143 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9617 22:56:12.061875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9618 22:56:12.065165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9619 22:56:12.071491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9620 22:56:12.074868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9621 22:56:12.081727 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9622 22:56:12.084867 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9623 22:56:12.091549 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9624 22:56:12.095081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9625 22:56:12.098198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9626 22:56:12.104693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9627 22:56:12.107919 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9628 22:56:12.114808 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9629 22:56:12.118138 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9630 22:56:12.121318 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9631 22:56:12.124376 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9632 22:56:12.131275 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9633 22:56:12.134686 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9634 22:56:12.138100 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9635 22:56:12.144876 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9636 22:56:12.148340 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9637 22:56:12.154688 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9638 22:56:12.158397 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9639 22:56:12.161506 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9640 22:56:12.168408 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9641 22:56:12.171264 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9642 22:56:12.178470 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9643 22:56:12.181826 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9644 22:56:12.184774 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9645 22:56:12.191442 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9646 22:56:12.194832 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9647 22:56:12.201102 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9648 22:56:12.204659 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9649 22:56:12.208208 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9650 22:56:12.214848 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9651 22:56:12.217793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9652 22:56:12.221254 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9653 22:56:12.224599 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9654 22:56:12.228276 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9655 22:56:12.234539 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9656 22:56:12.238138 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9657 22:56:12.244346 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9658 22:56:12.247932 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9659 22:56:12.250824 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9660 22:56:12.257769 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9661 22:56:12.261132 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9662 22:56:12.267603 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9663 22:56:12.271347 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9664 22:56:12.274090 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9665 22:56:12.281292 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9666 22:56:12.284398 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9667 22:56:12.287737 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9668 22:56:12.294347 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9669 22:56:12.297711 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9670 22:56:12.304379 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9671 22:56:12.307942 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9672 22:56:12.311048 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9673 22:56:12.317932 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9674 22:56:12.320882 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9675 22:56:12.327469 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9676 22:56:12.331129 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9677 22:56:12.334611 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9678 22:56:12.341348 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9679 22:56:12.344589 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9680 22:56:12.347795 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9681 22:56:12.354569 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9682 22:56:12.357549 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9683 22:56:12.364287 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9684 22:56:12.367444 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9685 22:56:12.370925 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9686 22:56:12.377586 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9687 22:56:12.380655 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9688 22:56:12.387524 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9689 22:56:12.390550 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9690 22:56:12.394220 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9691 22:56:12.400722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9692 22:56:12.403970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9693 22:56:12.410530 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9694 22:56:12.413915 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9695 22:56:12.417293 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9696 22:56:12.424427 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9697 22:56:12.427497 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9698 22:56:12.430710 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9699 22:56:12.437515 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9700 22:56:12.441290 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9701 22:56:12.447696 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9702 22:56:12.450834 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9703 22:56:12.454134 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9704 22:56:12.461140 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9705 22:56:12.464661 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9706 22:56:12.467948 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9707 22:56:12.474374 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9708 22:56:12.477714 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9709 22:56:12.484281 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9710 22:56:12.487675 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9711 22:56:12.491179 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9712 22:56:12.497143 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9713 22:56:12.500755 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9714 22:56:12.507234 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9715 22:56:12.510637 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9716 22:56:12.514172 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9717 22:56:12.520853 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9718 22:56:12.524014 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9719 22:56:12.530805 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9720 22:56:12.534468 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9721 22:56:12.537893 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9722 22:56:12.544555 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9723 22:56:12.547375 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9724 22:56:12.554129 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9725 22:56:12.557579 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9726 22:56:12.560581 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9727 22:56:12.567471 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9728 22:56:12.570995 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9729 22:56:12.577165 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9730 22:56:12.580907 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9731 22:56:12.587666 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9732 22:56:12.590840 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9733 22:56:12.593784 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9734 22:56:12.600409 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9735 22:56:12.603933 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9736 22:56:12.610355 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9737 22:56:12.613575 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9738 22:56:12.617457 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9739 22:56:12.623866 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9740 22:56:12.627376 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9741 22:56:12.634015 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9742 22:56:12.637267 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9743 22:56:12.640876 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9744 22:56:12.647139 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9745 22:56:12.650726 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9746 22:56:12.657029 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9747 22:56:12.660521 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9748 22:56:12.667055 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9749 22:56:12.670522 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9750 22:56:12.673646 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9751 22:56:12.680818 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9752 22:56:12.684305 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9753 22:56:12.690631 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9754 22:56:12.693953 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9755 22:56:12.697663 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9756 22:56:12.704211 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9757 22:56:12.707537 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9758 22:56:12.713898 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9759 22:56:12.717344 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9760 22:56:12.721098 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9761 22:56:12.727269 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9762 22:56:12.730574 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9763 22:56:12.734027 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9764 22:56:12.737186 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9765 22:56:12.743796 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9766 22:56:12.746966 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9767 22:56:12.750556 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9768 22:56:12.757152 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9769 22:56:12.760116 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9770 22:56:12.763667 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9771 22:56:12.770784 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9772 22:56:12.774011 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9773 22:56:12.780206 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9774 22:56:12.784044 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9775 22:56:12.787437 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9776 22:56:12.793842 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9777 22:56:12.796973 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9778 22:56:12.800080 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9779 22:56:12.807130 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9780 22:56:12.810323 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9781 22:56:12.813519 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9782 22:56:12.820114 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9783 22:56:12.823657 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9784 22:56:12.830338 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9785 22:56:12.833554 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9786 22:56:12.837084 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9787 22:56:12.843353 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9788 22:56:12.846807 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9789 22:56:12.850346 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9790 22:56:12.856689 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9791 22:56:12.860011 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9792 22:56:12.863485 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9793 22:56:12.870502 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9794 22:56:12.873593 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9795 22:56:12.876948 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9796 22:56:12.883546 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9797 22:56:12.886584 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9798 22:56:12.893667 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9799 22:56:12.896931 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9800 22:56:12.900507 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9801 22:56:12.903411 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9802 22:56:12.910191 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9803 22:56:12.913251 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9804 22:56:12.916391 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9805 22:56:12.920294 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9806 22:56:12.926999 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9807 22:56:12.930139 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9808 22:56:12.933275 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9809 22:56:12.936612 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9810 22:56:12.943134 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9811 22:56:12.946649 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9812 22:56:12.949655 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9813 22:56:12.953130 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9814 22:56:12.960100 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9815 22:56:12.963220 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9816 22:56:12.969790 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9817 22:56:12.973122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9818 22:56:12.979742 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9819 22:56:12.983227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9820 22:56:12.986448 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9821 22:56:12.992719 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9822 22:56:12.996119 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9823 22:56:13.002674 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9824 22:56:13.006009 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9825 22:56:13.012586 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9826 22:56:13.015680 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9827 22:56:13.018950 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9828 22:56:13.025906 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9829 22:56:13.029105 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9830 22:56:13.036050 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9831 22:56:13.038956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9832 22:56:13.042287 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9833 22:56:13.049519 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9834 22:56:13.052505 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9835 22:56:13.059290 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9836 22:56:13.062238 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9837 22:56:13.065936 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9838 22:56:13.072145 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9839 22:56:13.075645 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9840 22:56:13.082540 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9841 22:56:13.085664 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9842 22:56:13.092375 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9843 22:56:13.095888 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9844 22:56:13.098932 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9845 22:56:13.105375 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9846 22:56:13.108948 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9847 22:56:13.112616 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9848 22:56:13.118668 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9849 22:56:13.121540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9850 22:56:13.128654 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9851 22:56:13.131863 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9852 22:56:13.138444 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9853 22:56:13.141531 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9854 22:56:13.145113 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9855 22:56:13.152116 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9856 22:56:13.155147 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9857 22:56:13.161724 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9858 22:56:13.164927 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9859 22:56:13.171406 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9860 22:56:13.174854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9861 22:56:13.178239 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9862 22:56:13.184840 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9863 22:56:13.188236 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9864 22:56:13.194886 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9865 22:56:13.198523 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9866 22:56:13.201336 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9867 22:56:13.207953 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9868 22:56:13.211109 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9869 22:56:13.214671 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9870 22:56:13.221291 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9871 22:56:13.224647 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9872 22:56:13.231271 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9873 22:56:13.234618 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9874 22:56:13.241156 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9875 22:56:13.244627 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9876 22:56:13.251085 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9877 22:56:13.254217 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9878 22:56:13.257659 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9879 22:56:13.264367 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9880 22:56:13.267718 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9881 22:56:13.271182 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9882 22:56:13.277622 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9883 22:56:13.281024 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9884 22:56:13.287707 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9885 22:56:13.291426 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9886 22:56:13.294653 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9887 22:56:13.300972 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9888 22:56:13.304363 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9889 22:56:13.311101 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9890 22:56:13.313985 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9891 22:56:13.321036 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9892 22:56:13.324783 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9893 22:56:13.327496 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9894 22:56:13.333985 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9895 22:56:13.337382 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9896 22:56:13.344026 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9897 22:56:13.347708 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9898 22:56:13.354373 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9899 22:56:13.357423 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9900 22:56:13.364456 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9901 22:56:13.367538 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9902 22:56:13.370840 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9903 22:56:13.377953 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9904 22:56:13.380906 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9905 22:56:13.387666 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9906 22:56:13.391088 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9907 22:56:13.397472 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9908 22:56:13.400860 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9909 22:56:13.404563 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9910 22:56:13.411168 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9911 22:56:13.414648 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9912 22:56:13.421050 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9913 22:56:13.424685 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9914 22:56:13.431011 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9915 22:56:13.434438 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9916 22:56:13.437407 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9917 22:56:13.444610 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9918 22:56:13.447687 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9919 22:56:13.454123 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9920 22:56:13.457903 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9921 22:56:13.463989 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9922 22:56:13.467693 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9923 22:56:13.473824 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9924 22:56:13.477261 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9925 22:56:13.480718 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9926 22:56:13.487143 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9927 22:56:13.491001 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9928 22:56:13.497021 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9929 22:56:13.500626 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9930 22:56:13.507352 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9931 22:56:13.510354 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9932 22:56:13.514056 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9933 22:56:13.520711 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9934 22:56:13.523881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9935 22:56:13.527199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9936 22:56:13.533988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9937 22:56:13.537092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9938 22:56:13.543675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9939 22:56:13.547195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9940 22:56:13.554076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9941 22:56:13.557465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9942 22:56:13.563911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9943 22:56:13.567252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9944 22:56:13.574097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9945 22:56:13.577200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9946 22:56:13.583911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9947 22:56:13.587145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9948 22:56:13.593679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9949 22:56:13.597393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9950 22:56:13.603488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9951 22:56:13.607433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9952 22:56:13.613716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9953 22:56:13.616744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9954 22:56:13.623560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9955 22:56:13.626975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9956 22:56:13.633459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9957 22:56:13.637237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9958 22:56:13.643430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9959 22:56:13.646644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9960 22:56:13.653439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9961 22:56:13.656318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9962 22:56:13.662862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9963 22:56:13.666752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9964 22:56:13.673157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9965 22:56:13.676573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9966 22:56:13.679569 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9967 22:56:13.683307 INFO: [APUAPC] vio 0
9968 22:56:13.689787 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9969 22:56:13.692705 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9970 22:56:13.696241 INFO: [APUAPC] D0_APC_0: 0x400510
9971 22:56:13.699686 INFO: [APUAPC] D0_APC_1: 0x0
9972 22:56:13.702771 INFO: [APUAPC] D0_APC_2: 0x1540
9973 22:56:13.706104 INFO: [APUAPC] D0_APC_3: 0x0
9974 22:56:13.709885 INFO: [APUAPC] D1_APC_0: 0xffffffff
9975 22:56:13.713253 INFO: [APUAPC] D1_APC_1: 0xffffffff
9976 22:56:13.716588 INFO: [APUAPC] D1_APC_2: 0x3fffff
9977 22:56:13.716762 INFO: [APUAPC] D1_APC_3: 0x0
9978 22:56:13.723126 INFO: [APUAPC] D2_APC_0: 0xffffffff
9979 22:56:13.726135 INFO: [APUAPC] D2_APC_1: 0xffffffff
9980 22:56:13.729277 INFO: [APUAPC] D2_APC_2: 0x3fffff
9981 22:56:13.729460 INFO: [APUAPC] D2_APC_3: 0x0
9982 22:56:13.732759 INFO: [APUAPC] D3_APC_0: 0xffffffff
9983 22:56:13.736446 INFO: [APUAPC] D3_APC_1: 0xffffffff
9984 22:56:13.739543 INFO: [APUAPC] D3_APC_2: 0x3fffff
9985 22:56:13.742680 INFO: [APUAPC] D3_APC_3: 0x0
9986 22:56:13.746087 INFO: [APUAPC] D4_APC_0: 0xffffffff
9987 22:56:13.749222 INFO: [APUAPC] D4_APC_1: 0xffffffff
9988 22:56:13.752546 INFO: [APUAPC] D4_APC_2: 0x3fffff
9989 22:56:13.756033 INFO: [APUAPC] D4_APC_3: 0x0
9990 22:56:13.759389 INFO: [APUAPC] D5_APC_0: 0xffffffff
9991 22:56:13.763179 INFO: [APUAPC] D5_APC_1: 0xffffffff
9992 22:56:13.766243 INFO: [APUAPC] D5_APC_2: 0x3fffff
9993 22:56:13.769539 INFO: [APUAPC] D5_APC_3: 0x0
9994 22:56:13.773141 INFO: [APUAPC] D6_APC_0: 0xffffffff
9995 22:56:13.776147 INFO: [APUAPC] D6_APC_1: 0xffffffff
9996 22:56:13.779559 INFO: [APUAPC] D6_APC_2: 0x3fffff
9997 22:56:13.782930 INFO: [APUAPC] D6_APC_3: 0x0
9998 22:56:13.786050 INFO: [APUAPC] D7_APC_0: 0xffffffff
9999 22:56:13.789097 INFO: [APUAPC] D7_APC_1: 0xffffffff
10000 22:56:13.792302 INFO: [APUAPC] D7_APC_2: 0x3fffff
10001 22:56:13.795795 INFO: [APUAPC] D7_APC_3: 0x0
10002 22:56:13.799081 INFO: [APUAPC] D8_APC_0: 0xffffffff
10003 22:56:13.802590 INFO: [APUAPC] D8_APC_1: 0xffffffff
10004 22:56:13.806097 INFO: [APUAPC] D8_APC_2: 0x3fffff
10005 22:56:13.809203 INFO: [APUAPC] D8_APC_3: 0x0
10006 22:56:13.812307 INFO: [APUAPC] D9_APC_0: 0xffffffff
10007 22:56:13.816260 INFO: [APUAPC] D9_APC_1: 0xffffffff
10008 22:56:13.819112 INFO: [APUAPC] D9_APC_2: 0x3fffff
10009 22:56:13.822590 INFO: [APUAPC] D9_APC_3: 0x0
10010 22:56:13.825891 INFO: [APUAPC] D10_APC_0: 0xffffffff
10011 22:56:13.829344 INFO: [APUAPC] D10_APC_1: 0xffffffff
10012 22:56:13.832899 INFO: [APUAPC] D10_APC_2: 0x3fffff
10013 22:56:13.835938 INFO: [APUAPC] D10_APC_3: 0x0
10014 22:56:13.839663 INFO: [APUAPC] D11_APC_0: 0xffffffff
10015 22:56:13.843020 INFO: [APUAPC] D11_APC_1: 0xffffffff
10016 22:56:13.846048 INFO: [APUAPC] D11_APC_2: 0x3fffff
10017 22:56:13.849246 INFO: [APUAPC] D11_APC_3: 0x0
10018 22:56:13.852937 INFO: [APUAPC] D12_APC_0: 0xffffffff
10019 22:56:13.856121 INFO: [APUAPC] D12_APC_1: 0xffffffff
10020 22:56:13.859115 INFO: [APUAPC] D12_APC_2: 0x3fffff
10021 22:56:13.862745 INFO: [APUAPC] D12_APC_3: 0x0
10022 22:56:13.866374 INFO: [APUAPC] D13_APC_0: 0xffffffff
10023 22:56:13.869196 INFO: [APUAPC] D13_APC_1: 0xffffffff
10024 22:56:13.873174 INFO: [APUAPC] D13_APC_2: 0x3fffff
10025 22:56:13.876008 INFO: [APUAPC] D13_APC_3: 0x0
10026 22:56:13.879301 INFO: [APUAPC] D14_APC_0: 0xffffffff
10027 22:56:13.882493 INFO: [APUAPC] D14_APC_1: 0xffffffff
10028 22:56:13.886060 INFO: [APUAPC] D14_APC_2: 0x3fffff
10029 22:56:13.889396 INFO: [APUAPC] D14_APC_3: 0x0
10030 22:56:13.892603 INFO: [APUAPC] D15_APC_0: 0xffffffff
10031 22:56:13.895671 INFO: [APUAPC] D15_APC_1: 0xffffffff
10032 22:56:13.899115 INFO: [APUAPC] D15_APC_2: 0x3fffff
10033 22:56:13.902379 INFO: [APUAPC] D15_APC_3: 0x0
10034 22:56:13.905776 INFO: [APUAPC] APC_CON: 0x4
10035 22:56:13.908906 INFO: [NOCDAPC] D0_APC_0: 0x0
10036 22:56:13.912426 INFO: [NOCDAPC] D0_APC_1: 0x0
10037 22:56:13.912859 INFO: [NOCDAPC] D1_APC_0: 0x0
10038 22:56:13.915822 INFO: [NOCDAPC] D1_APC_1: 0xfff
10039 22:56:13.919466 INFO: [NOCDAPC] D2_APC_0: 0x0
10040 22:56:13.922559 INFO: [NOCDAPC] D2_APC_1: 0xfff
10041 22:56:13.926008 INFO: [NOCDAPC] D3_APC_0: 0x0
10042 22:56:13.929328 INFO: [NOCDAPC] D3_APC_1: 0xfff
10043 22:56:13.932422 INFO: [NOCDAPC] D4_APC_0: 0x0
10044 22:56:13.935828 INFO: [NOCDAPC] D4_APC_1: 0xfff
10045 22:56:13.939284 INFO: [NOCDAPC] D5_APC_0: 0x0
10046 22:56:13.942626 INFO: [NOCDAPC] D5_APC_1: 0xfff
10047 22:56:13.943102 INFO: [NOCDAPC] D6_APC_0: 0x0
10048 22:56:13.945854 INFO: [NOCDAPC] D6_APC_1: 0xfff
10049 22:56:13.949453 INFO: [NOCDAPC] D7_APC_0: 0x0
10050 22:56:13.952843 INFO: [NOCDAPC] D7_APC_1: 0xfff
10051 22:56:13.955739 INFO: [NOCDAPC] D8_APC_0: 0x0
10052 22:56:13.958962 INFO: [NOCDAPC] D8_APC_1: 0xfff
10053 22:56:13.962426 INFO: [NOCDAPC] D9_APC_0: 0x0
10054 22:56:13.965928 INFO: [NOCDAPC] D9_APC_1: 0xfff
10055 22:56:13.969227 INFO: [NOCDAPC] D10_APC_0: 0x0
10056 22:56:13.972897 INFO: [NOCDAPC] D10_APC_1: 0xfff
10057 22:56:13.975935 INFO: [NOCDAPC] D11_APC_0: 0x0
10058 22:56:13.979299 INFO: [NOCDAPC] D11_APC_1: 0xfff
10059 22:56:13.979883 INFO: [NOCDAPC] D12_APC_0: 0x0
10060 22:56:13.982329 INFO: [NOCDAPC] D12_APC_1: 0xfff
10061 22:56:13.985864 INFO: [NOCDAPC] D13_APC_0: 0x0
10062 22:56:13.989120 INFO: [NOCDAPC] D13_APC_1: 0xfff
10063 22:56:13.992575 INFO: [NOCDAPC] D14_APC_0: 0x0
10064 22:56:13.996016 INFO: [NOCDAPC] D14_APC_1: 0xfff
10065 22:56:13.999395 INFO: [NOCDAPC] D15_APC_0: 0x0
10066 22:56:14.002524 INFO: [NOCDAPC] D15_APC_1: 0xfff
10067 22:56:14.005945 INFO: [NOCDAPC] APC_CON: 0x4
10068 22:56:14.008981 INFO: [APUAPC] set_apusys_apc done
10069 22:56:14.012703 INFO: [DEVAPC] devapc_init done
10070 22:56:14.015429 INFO: GICv3 without legacy support detected.
10071 22:56:14.018742 INFO: ARM GICv3 driver initialized in EL3
10072 22:56:14.022383 INFO: Maximum SPI INTID supported: 639
10073 22:56:14.028630 INFO: BL31: Initializing runtime services
10074 22:56:14.032473 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10075 22:56:14.035909 INFO: SPM: enable CPC mode
10076 22:56:14.042474 INFO: mcdi ready for mcusys-off-idle and system suspend
10077 22:56:14.045867 INFO: BL31: Preparing for EL3 exit to normal world
10078 22:56:14.049519 INFO: Entry point address = 0x80000000
10079 22:56:14.051951 INFO: SPSR = 0x8
10080 22:56:14.057621
10081 22:56:14.058180
10082 22:56:14.058547
10083 22:56:14.061013 Starting depthcharge on Spherion...
10084 22:56:14.061608
10085 22:56:14.062035 Wipe memory regions:
10086 22:56:14.062403
10087 22:56:14.064766 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10088 22:56:14.065382 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10089 22:56:14.065852 Setting prompt string to ['asurada:']
10090 22:56:14.066295 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10091 22:56:14.067065 [0x00000040000000, 0x00000054600000)
10092 22:56:14.186694
10093 22:56:14.187307 [0x00000054660000, 0x00000080000000)
10094 22:56:14.446358
10095 22:56:14.446623 [0x000000821a7280, 0x000000ffe64000)
10096 22:56:15.192015
10097 22:56:15.192588 [0x00000100000000, 0x00000240000000)
10098 22:56:17.082209
10099 22:56:17.085664 Initializing XHCI USB controller at 0x11200000.
10100 22:56:18.123559
10101 22:56:18.126672 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10102 22:56:18.126916
10103 22:56:18.127051
10104 22:56:18.127177
10105 22:56:18.127575 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10107 22:56:18.228159 asurada: tftpboot 192.168.201.1 13683739/tftp-deploy-o0ljxgg6/kernel/image.itb 13683739/tftp-deploy-o0ljxgg6/kernel/cmdline
10108 22:56:18.228375 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10109 22:56:18.228489 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10110 22:56:18.232976 tftpboot 192.168.201.1 13683739/tftp-deploy-o0ljxgg6/kernel/image.ittp-deploy-o0ljxgg6/kernel/cmdline
10111 22:56:18.233173
10112 22:56:18.233275 Waiting for link
10113 22:56:18.391584
10114 22:56:18.392152 R8152: Initializing
10115 22:56:18.392523
10116 22:56:18.394591 Version 9 (ocp_data = 6010)
10117 22:56:18.395062
10118 22:56:18.397943 R8152: Done initializing
10119 22:56:18.398513
10120 22:56:18.398883 Adding net device
10121 22:56:20.344872
10122 22:56:20.345422 done.
10123 22:56:20.345780
10124 22:56:20.346181 MAC: 00:e0:4c:72:2d:d6
10125 22:56:20.346571
10126 22:56:20.347923 Sending DHCP discover... done.
10127 22:56:20.348008
10128 22:56:20.350893 Waiting for reply... done.
10129 22:56:20.350976
10130 22:56:20.354166 Sending DHCP request... done.
10131 22:56:20.354250
10132 22:56:20.354316 Waiting for reply... done.
10133 22:56:20.354377
10134 22:56:20.357539 My ip is 192.168.201.21
10135 22:56:20.357623
10136 22:56:20.361108 The DHCP server ip is 192.168.201.1
10137 22:56:20.361193
10138 22:56:20.364204 TFTP server IP predefined by user: 192.168.201.1
10139 22:56:20.364288
10140 22:56:20.370717 Bootfile predefined by user: 13683739/tftp-deploy-o0ljxgg6/kernel/image.itb
10141 22:56:20.370802
10142 22:56:20.374171 Sending tftp read request... done.
10143 22:56:20.374255
10144 22:56:20.377842 Waiting for the transfer...
10145 22:56:20.377925
10146 22:56:20.637369 00000000 ################################################################
10147 22:56:20.637499
10148 22:56:20.884400 00080000 ################################################################
10149 22:56:20.884545
10150 22:56:21.131168 00100000 ################################################################
10151 22:56:21.131299
10152 22:56:21.378014 00180000 ################################################################
10153 22:56:21.378148
10154 22:56:21.626232 00200000 ################################################################
10155 22:56:21.626359
10156 22:56:21.872148 00280000 ################################################################
10157 22:56:21.872314
10158 22:56:22.119577 00300000 ################################################################
10159 22:56:22.119705
10160 22:56:22.366991 00380000 ################################################################
10161 22:56:22.367124
10162 22:56:22.620003 00400000 ################################################################
10163 22:56:22.620131
10164 22:56:22.866056 00480000 ################################################################
10165 22:56:22.866194
10166 22:56:23.113170 00500000 ################################################################
10167 22:56:23.113303
10168 22:56:23.360448 00580000 ################################################################
10169 22:56:23.360584
10170 22:56:23.608829 00600000 ################################################################
10171 22:56:23.608959
10172 22:56:23.857254 00680000 ################################################################
10173 22:56:23.857411
10174 22:56:24.104292 00700000 ################################################################
10175 22:56:24.104454
10176 22:56:24.351121 00780000 ################################################################
10177 22:56:24.351273
10178 22:56:24.600346 00800000 ################################################################
10179 22:56:24.600495
10180 22:56:24.847504 00880000 ################################################################
10181 22:56:24.847662
10182 22:56:25.092830 00900000 ################################################################
10183 22:56:25.092987
10184 22:56:25.337940 00980000 ################################################################
10185 22:56:25.338113
10186 22:56:25.586017 00a00000 ################################################################
10187 22:56:25.586164
10188 22:56:25.833304 00a80000 ################################################################
10189 22:56:25.833464
10190 22:56:26.081250 00b00000 ################################################################
10191 22:56:26.081421
10192 22:56:26.329530 00b80000 ################################################################
10193 22:56:26.329662
10194 22:56:26.577664 00c00000 ################################################################
10195 22:56:26.577811
10196 22:56:26.824574 00c80000 ################################################################
10197 22:56:26.824709
10198 22:56:27.075806 00d00000 ################################################################
10199 22:56:27.075975
10200 22:56:27.320623 00d80000 ################################################################
10201 22:56:27.320758
10202 22:56:27.567062 00e00000 ################################################################
10203 22:56:27.567230
10204 22:56:27.814675 00e80000 ################################################################
10205 22:56:27.814838
10206 22:56:28.064876 00f00000 ################################################################
10207 22:56:28.065024
10208 22:56:28.315295 00f80000 ################################################################
10209 22:56:28.315426
10210 22:56:28.564506 01000000 ################################################################
10211 22:56:28.564642
10212 22:56:28.813214 01080000 ################################################################
10213 22:56:28.813364
10214 22:56:29.060407 01100000 ################################################################
10215 22:56:29.060546
10216 22:56:29.308410 01180000 ################################################################
10217 22:56:29.308539
10218 22:56:29.556204 01200000 ################################################################
10219 22:56:29.556336
10220 22:56:29.802150 01280000 ################################################################
10221 22:56:29.802279
10222 22:56:30.051515 01300000 ################################################################
10223 22:56:30.051641
10224 22:56:30.298853 01380000 ################################################################
10225 22:56:30.298982
10226 22:56:30.545852 01400000 ################################################################
10227 22:56:30.545980
10228 22:56:30.795616 01480000 ################################################################
10229 22:56:30.795743
10230 22:56:31.043626 01500000 ################################################################
10231 22:56:31.043776
10232 22:56:31.290359 01580000 ################################################################
10233 22:56:31.290499
10234 22:56:31.537170 01600000 ################################################################
10235 22:56:31.537341
10236 22:56:31.784447 01680000 ################################################################
10237 22:56:31.784595
10238 22:56:32.031304 01700000 ################################################################
10239 22:56:32.031464
10240 22:56:32.278620 01780000 ################################################################
10241 22:56:32.278748
10242 22:56:32.525603 01800000 ################################################################
10243 22:56:32.525728
10244 22:56:32.772208 01880000 ################################################################
10245 22:56:32.772336
10246 22:56:33.020609 01900000 ################################################################
10247 22:56:33.020732
10248 22:56:33.264703 01980000 ################################################################
10249 22:56:33.264836
10250 22:56:33.511856 01a00000 ################################################################
10251 22:56:33.511981
10252 22:56:33.758749 01a80000 ################################################################
10253 22:56:33.758927
10254 22:56:34.006598 01b00000 ################################################################
10255 22:56:34.006717
10256 22:56:34.252689 01b80000 ################################################################
10257 22:56:34.252820
10258 22:56:34.502045 01c00000 ################################################################
10259 22:56:34.502175
10260 22:56:34.749630 01c80000 ################################################################
10261 22:56:34.749754
10262 22:56:34.998447 01d00000 ################################################################
10263 22:56:34.998574
10264 22:56:35.245939 01d80000 ################################################################
10265 22:56:35.246070
10266 22:56:35.433798 01e00000 ############################################### done.
10267 22:56:35.434297
10268 22:56:35.437193 The bootfile was 31841098 bytes long.
10269 22:56:35.437717
10270 22:56:35.440257 Sending tftp read request... done.
10271 22:56:35.440903
10272 22:56:35.441281 Waiting for the transfer...
10273 22:56:35.441683
10274 22:56:35.443533 00000000 # done.
10275 22:56:35.444008
10276 22:56:35.450433 Command line loaded dynamically from TFTP file: 13683739/tftp-deploy-o0ljxgg6/kernel/cmdline
10277 22:56:35.450993
10278 22:56:35.473420 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683739/extract-nfsrootfs-88_0ur2m,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10279 22:56:35.473985
10280 22:56:35.474361 Loading FIT.
10281 22:56:35.474714
10282 22:56:35.476400 Image ramdisk-1 has 18732252 bytes.
10283 22:56:35.476906
10284 22:56:35.479868 Image fdt-1 has 47258 bytes.
10285 22:56:35.480366
10286 22:56:35.483410 Image kernel-1 has 13059555 bytes.
10287 22:56:35.483884
10288 22:56:35.493369 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10289 22:56:35.493952
10290 22:56:35.509896 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10291 22:56:35.510492
10292 22:56:35.516330 Choosing best match conf-1 for compat google,spherion-rev2.
10293 22:56:35.516903
10294 22:56:35.524397 Connected to device vid:did:rid of 1ae0:0028:00
10295 22:56:35.532345
10296 22:56:35.535922 tpm_get_response: command 0x17b, return code 0x0
10297 22:56:35.536487
10298 22:56:35.538948 ec_init: CrosEC protocol v3 supported (256, 248)
10299 22:56:35.542676
10300 22:56:35.546148 tpm_cleanup: add release locality here.
10301 22:56:35.546628
10302 22:56:35.546997 Shutting down all USB controllers.
10303 22:56:35.549597
10304 22:56:35.550071 Removing current net device
10305 22:56:35.550437
10306 22:56:35.556184 Exiting depthcharge with code 4 at timestamp: 50841624
10307 22:56:35.556660
10308 22:56:35.559514 LZMA decompressing kernel-1 to 0x821a6718
10309 22:56:35.559987
10310 22:56:35.562798 LZMA decompressing kernel-1 to 0x40000000
10311 22:56:37.174209
10312 22:56:37.174765 jumping to kernel
10313 22:56:37.176510 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10314 22:56:37.177068 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10315 22:56:37.177531 Setting prompt string to ['Linux version [0-9]']
10316 22:56:37.177921 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10317 22:56:37.178306 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10318 22:56:37.257234
10319 22:56:37.260805 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10320 22:56:37.264120 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10321 22:56:37.264638 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10322 22:56:37.265044 Setting prompt string to []
10323 22:56:37.265489 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10324 22:56:37.265889 Using line separator: #'\n'#
10325 22:56:37.266230 No login prompt set.
10326 22:56:37.266574 Parsing kernel messages
10327 22:56:37.266890 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10328 22:56:37.267455 [login-action] Waiting for messages, (timeout 00:04:04)
10329 22:56:37.267817 Waiting using forced prompt support (timeout 00:02:02)
10330 22:56:37.283550 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10331 22:56:37.286717 [ 0.000000] random: crng init done
10332 22:56:37.293704 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10333 22:56:37.297122 [ 0.000000] efi: UEFI not found.
10334 22:56:37.303847 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10335 22:56:37.310154 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10336 22:56:37.320271 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10337 22:56:37.330151 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10338 22:56:37.336852 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10339 22:56:37.343808 [ 0.000000] printk: bootconsole [mtk8250] enabled
10340 22:56:37.349806 [ 0.000000] NUMA: No NUMA configuration found
10341 22:56:37.356643 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10342 22:56:37.360033 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10343 22:56:37.363132 [ 0.000000] Zone ranges:
10344 22:56:37.369609 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10345 22:56:37.373093 [ 0.000000] DMA32 empty
10346 22:56:37.379930 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10347 22:56:37.383477 [ 0.000000] Movable zone start for each node
10348 22:56:37.386361 [ 0.000000] Early memory node ranges
10349 22:56:37.393128 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10350 22:56:37.399638 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10351 22:56:37.406226 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10352 22:56:37.412807 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10353 22:56:37.416333 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10354 22:56:37.426155 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10355 22:56:37.482136 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10356 22:56:37.488633 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10357 22:56:37.495170 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10358 22:56:37.498659 [ 0.000000] psci: probing for conduit method from DT.
10359 22:56:37.504996 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10360 22:56:37.508640 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10361 22:56:37.515431 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10362 22:56:37.518236 [ 0.000000] psci: SMC Calling Convention v1.2
10363 22:56:37.524988 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10364 22:56:37.528356 [ 0.000000] Detected VIPT I-cache on CPU0
10365 22:56:37.535174 [ 0.000000] CPU features: detected: GIC system register CPU interface
10366 22:56:37.541448 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10367 22:56:37.548571 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10368 22:56:37.554783 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10369 22:56:37.564690 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10370 22:56:37.570996 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10371 22:56:37.574501 [ 0.000000] alternatives: applying boot alternatives
10372 22:56:37.581343 [ 0.000000] Fallback order for Node 0: 0
10373 22:56:37.587720 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10374 22:56:37.590793 [ 0.000000] Policy zone: Normal
10375 22:56:37.614229 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683739/extract-nfsrootfs-88_0ur2m,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10376 22:56:37.623938 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10377 22:56:37.634885 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10378 22:56:37.645258 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10379 22:56:37.651616 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10380 22:56:37.655336 <6>[ 0.000000] software IO TLB: area num 8.
10381 22:56:37.711522 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10382 22:56:37.861052 <6>[ 0.000000] Memory: 7945896K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406872K reserved, 32768K cma-reserved)
10383 22:56:37.867534 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10384 22:56:37.874214 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10385 22:56:37.877468 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10386 22:56:37.884400 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10387 22:56:37.890605 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10388 22:56:37.894162 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10389 22:56:37.904054 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10390 22:56:37.910557 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10391 22:56:37.917389 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10392 22:56:37.923815 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10393 22:56:37.926862 <6>[ 0.000000] GICv3: 608 SPIs implemented
10394 22:56:37.930851 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10395 22:56:37.937045 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10396 22:56:37.940484 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10397 22:56:37.946725 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10398 22:56:37.960093 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10399 22:56:37.970118 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10400 22:56:37.980533 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10401 22:56:37.987320 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10402 22:56:38.000592 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10403 22:56:38.007174 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10404 22:56:38.014198 <6>[ 0.009181] Console: colour dummy device 80x25
10405 22:56:38.023807 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10406 22:56:38.027456 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10407 22:56:38.034160 <6>[ 0.029221] LSM: Security Framework initializing
10408 22:56:38.040895 <6>[ 0.034188] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 22:56:38.051056 <6>[ 0.042048] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 22:56:38.057671 <6>[ 0.051481] cblist_init_generic: Setting adjustable number of callback queues.
10411 22:56:38.064030 <6>[ 0.058924] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 22:56:38.073580 <6>[ 0.065302] cblist_init_generic: Setting adjustable number of callback queues.
10413 22:56:38.080622 <6>[ 0.072728] cblist_init_generic: Setting shift to 3 and lim to 1.
10414 22:56:38.083850 <6>[ 0.079167] rcu: Hierarchical SRCU implementation.
10415 22:56:38.090382 <6>[ 0.084213] rcu: Max phase no-delay instances is 1000.
10416 22:56:38.096950 <6>[ 0.091238] EFI services will not be available.
10417 22:56:38.100473 <6>[ 0.096201] smp: Bringing up secondary CPUs ...
10418 22:56:38.108392 <6>[ 0.101250] Detected VIPT I-cache on CPU1
10419 22:56:38.115048 <6>[ 0.101322] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10420 22:56:38.121201 <6>[ 0.101351] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10421 22:56:38.124540 <6>[ 0.101687] Detected VIPT I-cache on CPU2
10422 22:56:38.131476 <6>[ 0.101736] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10423 22:56:38.141135 <6>[ 0.101752] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10424 22:56:38.144375 <6>[ 0.102009] Detected VIPT I-cache on CPU3
10425 22:56:38.151270 <6>[ 0.102057] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10426 22:56:38.158373 <6>[ 0.102070] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10427 22:56:38.161146 <6>[ 0.102378] CPU features: detected: Spectre-v4
10428 22:56:38.168318 <6>[ 0.102384] CPU features: detected: Spectre-BHB
10429 22:56:38.171509 <6>[ 0.102389] Detected PIPT I-cache on CPU4
10430 22:56:38.177777 <6>[ 0.102449] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10431 22:56:38.184524 <6>[ 0.102466] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10432 22:56:38.191506 <6>[ 0.102761] Detected PIPT I-cache on CPU5
10433 22:56:38.198145 <6>[ 0.102826] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10434 22:56:38.204718 <6>[ 0.102842] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10435 22:56:38.207642 <6>[ 0.103125] Detected PIPT I-cache on CPU6
10436 22:56:38.214412 <6>[ 0.103192] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10437 22:56:38.221366 <6>[ 0.103208] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10438 22:56:38.227258 <6>[ 0.103506] Detected PIPT I-cache on CPU7
10439 22:56:38.234247 <6>[ 0.103573] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10440 22:56:38.241088 <6>[ 0.103589] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10441 22:56:38.244086 <6>[ 0.103636] smp: Brought up 1 node, 8 CPUs
10442 22:56:38.250951 <6>[ 0.244992] SMP: Total of 8 processors activated.
10443 22:56:38.254170 <6>[ 0.249912] CPU features: detected: 32-bit EL0 Support
10444 22:56:38.264366 <6>[ 0.255275] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10445 22:56:38.271059 <6>[ 0.264130] CPU features: detected: Common not Private translations
10446 22:56:38.277253 <6>[ 0.270646] CPU features: detected: CRC32 instructions
10447 22:56:38.280815 <6>[ 0.275997] CPU features: detected: RCpc load-acquire (LDAPR)
10448 22:56:38.287156 <6>[ 0.281958] CPU features: detected: LSE atomic instructions
10449 22:56:38.293978 <6>[ 0.287739] CPU features: detected: Privileged Access Never
10450 22:56:38.300258 <6>[ 0.293554] CPU features: detected: RAS Extension Support
10451 22:56:38.307268 <6>[ 0.299197] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10452 22:56:38.310441 <6>[ 0.306415] CPU: All CPU(s) started at EL2
10453 22:56:38.317021 <6>[ 0.310731] alternatives: applying system-wide alternatives
10454 22:56:38.326265 <6>[ 0.321614] devtmpfs: initialized
10455 22:56:38.341817 <6>[ 0.330616] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10456 22:56:38.348413 <6>[ 0.340575] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10457 22:56:38.355080 <6>[ 0.348832] pinctrl core: initialized pinctrl subsystem
10458 22:56:38.358419 <6>[ 0.355703] DMI not present or invalid.
10459 22:56:38.365135 <6>[ 0.360122] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10460 22:56:38.374798 <6>[ 0.366959] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10461 22:56:38.381655 <6>[ 0.374542] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10462 22:56:38.391406 <6>[ 0.382761] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10463 22:56:38.394614 <6>[ 0.391002] audit: initializing netlink subsys (disabled)
10464 22:56:38.404713 <5>[ 0.396694] audit: type=2000 audit(0.284:1): state=initialized audit_enabled=0 res=1
10465 22:56:38.411521 <6>[ 0.397464] thermal_sys: Registered thermal governor 'step_wise'
10466 22:56:38.417859 <6>[ 0.404661] thermal_sys: Registered thermal governor 'power_allocator'
10467 22:56:38.421167 <6>[ 0.410915] cpuidle: using governor menu
10468 22:56:38.427557 <6>[ 0.421876] NET: Registered PF_QIPCRTR protocol family
10469 22:56:38.434428 <6>[ 0.427361] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10470 22:56:38.441159 <6>[ 0.434465] ASID allocator initialised with 32768 entries
10471 22:56:38.444247 <6>[ 0.441128] Serial: AMBA PL011 UART driver
10472 22:56:38.454666 <4>[ 0.450213] Trying to register duplicate clock ID: 134
10473 22:56:38.515075 <6>[ 0.513972] KASLR enabled
10474 22:56:38.529995 <6>[ 0.521784] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10475 22:56:38.536251 <6>[ 0.528795] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10476 22:56:38.543104 <6>[ 0.535280] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10477 22:56:38.550137 <6>[ 0.542286] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10478 22:56:38.556584 <6>[ 0.548774] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10479 22:56:38.563117 <6>[ 0.555781] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10480 22:56:38.569441 <6>[ 0.562271] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10481 22:56:38.576407 <6>[ 0.569274] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10482 22:56:38.579412 <6>[ 0.576809] ACPI: Interpreter disabled.
10483 22:56:38.588118 <6>[ 0.583308] iommu: Default domain type: Translated
10484 22:56:38.594692 <6>[ 0.588421] iommu: DMA domain TLB invalidation policy: strict mode
10485 22:56:38.598167 <5>[ 0.595083] SCSI subsystem initialized
10486 22:56:38.604971 <6>[ 0.599249] usbcore: registered new interface driver usbfs
10487 22:56:38.611151 <6>[ 0.604980] usbcore: registered new interface driver hub
10488 22:56:38.614626 <6>[ 0.610532] usbcore: registered new device driver usb
10489 22:56:38.621288 <6>[ 0.616670] pps_core: LinuxPPS API ver. 1 registered
10490 22:56:38.631046 <6>[ 0.621864] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10491 22:56:38.634683 <6>[ 0.631212] PTP clock support registered
10492 22:56:38.637869 <6>[ 0.635456] EDAC MC: Ver: 3.0.0
10493 22:56:38.645322 <6>[ 0.640656] FPGA manager framework
10494 22:56:38.651647 <6>[ 0.644340] Advanced Linux Sound Architecture Driver Initialized.
10495 22:56:38.655360 <6>[ 0.651083] vgaarb: loaded
10496 22:56:38.658420 <6>[ 0.654242] clocksource: Switched to clocksource arch_sys_counter
10497 22:56:38.665223 <5>[ 0.660687] VFS: Disk quotas dquot_6.6.0
10498 22:56:38.671968 <6>[ 0.664875] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10499 22:56:38.675167 <6>[ 0.672065] pnp: PnP ACPI: disabled
10500 22:56:38.683441 <6>[ 0.678783] NET: Registered PF_INET protocol family
10501 22:56:38.693273 <6>[ 0.684304] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10502 22:56:38.704440 <6>[ 0.696633] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10503 22:56:38.714090 <6>[ 0.705451] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10504 22:56:38.720916 <6>[ 0.713419] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10505 22:56:38.730383 <6>[ 0.722121] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10506 22:56:38.737606 <6>[ 0.731880] TCP: Hash tables configured (established 65536 bind 65536)
10507 22:56:38.744279 <6>[ 0.738748] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 22:56:38.753683 <6>[ 0.745947] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10509 22:56:38.760498 <6>[ 0.753648] NET: Registered PF_UNIX/PF_LOCAL protocol family
10510 22:56:38.767057 <6>[ 0.759799] RPC: Registered named UNIX socket transport module.
10511 22:56:38.770427 <6>[ 0.765955] RPC: Registered udp transport module.
10512 22:56:38.776856 <6>[ 0.770887] RPC: Registered tcp transport module.
10513 22:56:38.783844 <6>[ 0.775820] RPC: Registered tcp NFSv4.1 backchannel transport module.
10514 22:56:38.787050 <6>[ 0.782487] PCI: CLS 0 bytes, default 64
10515 22:56:38.790151 <6>[ 0.786811] Unpacking initramfs...
10516 22:56:38.806493 <6>[ 0.798769] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10517 22:56:38.816472 <6>[ 0.807430] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10518 22:56:38.819589 <6>[ 0.816299] kvm [1]: IPA Size Limit: 40 bits
10519 22:56:38.826302 <6>[ 0.820827] kvm [1]: GICv3: no GICV resource entry
10520 22:56:38.829371 <6>[ 0.825847] kvm [1]: disabling GICv2 emulation
10521 22:56:38.836139 <6>[ 0.830537] kvm [1]: GIC system register CPU interface enabled
10522 22:56:38.839621 <6>[ 0.836701] kvm [1]: vgic interrupt IRQ18
10523 22:56:38.846790 <6>[ 0.841055] kvm [1]: VHE mode initialized successfully
10524 22:56:38.853368 <5>[ 0.847478] Initialise system trusted keyrings
10525 22:56:38.859806 <6>[ 0.852257] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10526 22:56:38.866908 <6>[ 0.862346] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10527 22:56:38.873650 <5>[ 0.868768] NFS: Registering the id_resolver key type
10528 22:56:38.877004 <5>[ 0.874080] Key type id_resolver registered
10529 22:56:38.883267 <5>[ 0.878494] Key type id_legacy registered
10530 22:56:38.889715 <6>[ 0.882772] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10531 22:56:38.896391 <6>[ 0.889690] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10532 22:56:38.902802 <6>[ 0.897434] 9p: Installing v9fs 9p2000 file system support
10533 22:56:38.940519 <5>[ 0.936091] Key type asymmetric registered
10534 22:56:38.944053 <5>[ 0.940421] Asymmetric key parser 'x509' registered
10535 22:56:38.954175 <6>[ 0.945565] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10536 22:56:38.956985 <6>[ 0.953180] io scheduler mq-deadline registered
10537 22:56:38.960156 <6>[ 0.957958] io scheduler kyber registered
10538 22:56:38.979590 <6>[ 0.975419] EINJ: ACPI disabled.
10539 22:56:39.013260 <4>[ 1.002092] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 22:56:39.023614 <4>[ 1.012739] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10541 22:56:39.038638 <6>[ 1.034348] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10542 22:56:39.047256 <6>[ 1.042692] printk: console [ttyS0] disabled
10543 22:56:39.075261 <6>[ 1.067326] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10544 22:56:39.082163 <6>[ 1.076801] printk: console [ttyS0] enabled
10545 22:56:39.085196 <6>[ 1.076801] printk: console [ttyS0] enabled
10546 22:56:39.091907 <6>[ 1.085699] printk: bootconsole [mtk8250] disabled
10547 22:56:39.095233 <6>[ 1.085699] printk: bootconsole [mtk8250] disabled
10548 22:56:39.102017 <6>[ 1.097036] SuperH (H)SCI(F) driver initialized
10549 22:56:39.105150 <6>[ 1.102354] msm_serial: driver initialized
10550 22:56:39.119468 <6>[ 1.111439] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10551 22:56:39.129700 <6>[ 1.119986] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10552 22:56:39.136238 <6>[ 1.128530] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10553 22:56:39.146135 <6>[ 1.137158] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10554 22:56:39.152747 <6>[ 1.145865] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10555 22:56:39.162920 <6>[ 1.154581] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10556 22:56:39.172958 <6>[ 1.163123] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10557 22:56:39.179268 <6>[ 1.171933] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10558 22:56:39.189073 <6>[ 1.180479] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10559 22:56:39.201333 <6>[ 1.196438] loop: module loaded
10560 22:56:39.207929 <6>[ 1.202389] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10561 22:56:39.230550 <4>[ 1.225785] mtk-pmic-keys: Failed to locate of_node [id: -1]
10562 22:56:39.237165 <6>[ 1.232684] megasas: 07.719.03.00-rc1
10563 22:56:39.246792 <6>[ 1.242343] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10564 22:56:39.254397 <6>[ 1.249639] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10565 22:56:39.271307 <6>[ 1.266417] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10566 22:56:39.327722 <6>[ 1.316378] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10567 22:56:39.580867 <6>[ 1.576138] Freeing initrd memory: 18288K
10568 22:56:39.592774 <6>[ 1.587686] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10569 22:56:39.603970 <6>[ 1.598835] tun: Universal TUN/TAP device driver, 1.6
10570 22:56:39.606974 <6>[ 1.604935] thunder_xcv, ver 1.0
10571 22:56:39.610102 <6>[ 1.608443] thunder_bgx, ver 1.0
10572 22:56:39.613604 <6>[ 1.611940] nicpf, ver 1.0
10573 22:56:39.624160 <6>[ 1.616007] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10574 22:56:39.627082 <6>[ 1.623483] hns3: Copyright (c) 2017 Huawei Corporation.
10575 22:56:39.633870 <6>[ 1.629072] hclge is initializing
10576 22:56:39.637193 <6>[ 1.632653] e1000: Intel(R) PRO/1000 Network Driver
10577 22:56:39.643567 <6>[ 1.637782] e1000: Copyright (c) 1999-2006 Intel Corporation.
10578 22:56:39.647330 <6>[ 1.643794] e1000e: Intel(R) PRO/1000 Network Driver
10579 22:56:39.653450 <6>[ 1.649008] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10580 22:56:39.660435 <6>[ 1.655199] igb: Intel(R) Gigabit Ethernet Network Driver
10581 22:56:39.666920 <6>[ 1.660849] igb: Copyright (c) 2007-2014 Intel Corporation.
10582 22:56:39.673576 <6>[ 1.666686] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10583 22:56:39.680265 <6>[ 1.673203] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10584 22:56:39.683277 <6>[ 1.679668] sky2: driver version 1.30
10585 22:56:39.690292 <6>[ 1.684637] usbcore: registered new device driver r8152-cfgselector
10586 22:56:39.696527 <6>[ 1.691171] usbcore: registered new interface driver r8152
10587 22:56:39.703459 <6>[ 1.696990] VFIO - User Level meta-driver version: 0.3
10588 22:56:39.709991 <6>[ 1.705310] usbcore: registered new interface driver usb-storage
10589 22:56:39.716732 <6>[ 1.711762] usbcore: registered new device driver onboard-usb-hub
10590 22:56:39.725243 <6>[ 1.720967] mt6397-rtc mt6359-rtc: registered as rtc0
10591 22:56:39.735716 <6>[ 1.726427] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:55:28 UTC (1715122528)
10592 22:56:39.738698 <6>[ 1.736011] i2c_dev: i2c /dev entries driver
10593 22:56:39.756081 <6>[ 1.748051] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10594 22:56:39.762660 <4>[ 1.756792] cpu cpu0: supply cpu not found, using dummy regulator
10595 22:56:39.768854 <4>[ 1.763217] cpu cpu1: supply cpu not found, using dummy regulator
10596 22:56:39.775551 <4>[ 1.769628] cpu cpu2: supply cpu not found, using dummy regulator
10597 22:56:39.782897 <4>[ 1.776048] cpu cpu3: supply cpu not found, using dummy regulator
10598 22:56:39.789006 <4>[ 1.782444] cpu cpu4: supply cpu not found, using dummy regulator
10599 22:56:39.796137 <4>[ 1.788838] cpu cpu5: supply cpu not found, using dummy regulator
10600 22:56:39.802438 <4>[ 1.795239] cpu cpu6: supply cpu not found, using dummy regulator
10601 22:56:39.809243 <4>[ 1.801640] cpu cpu7: supply cpu not found, using dummy regulator
10602 22:56:39.826781 <6>[ 1.822301] cpu cpu0: EM: created perf domain
10603 22:56:39.830374 <6>[ 1.827225] cpu cpu4: EM: created perf domain
10604 22:56:39.837589 <6>[ 1.832870] sdhci: Secure Digital Host Controller Interface driver
10605 22:56:39.844350 <6>[ 1.839303] sdhci: Copyright(c) Pierre Ossman
10606 22:56:39.851048 <6>[ 1.844263] Synopsys Designware Multimedia Card Interface Driver
10607 22:56:39.857772 <6>[ 1.850914] sdhci-pltfm: SDHCI platform and OF driver helper
10608 22:56:39.860623 <6>[ 1.850955] mmc0: CQHCI version 5.10
10609 22:56:39.867800 <6>[ 1.861272] ledtrig-cpu: registered to indicate activity on CPUs
10610 22:56:39.874326 <6>[ 1.868400] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10611 22:56:39.880816 <6>[ 1.875464] usbcore: registered new interface driver usbhid
10612 22:56:39.884155 <6>[ 1.881286] usbhid: USB HID core driver
10613 22:56:39.890558 <6>[ 1.885484] spi_master spi0: will run message pump with realtime priority
10614 22:56:39.939668 <6>[ 1.928440] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10615 22:56:39.955147 <6>[ 1.943960] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10616 22:56:39.962836 <6>[ 1.958094] mmc0: Command Queue Engine enabled
10617 22:56:39.969598 <6>[ 1.959095] cros-ec-spi spi0.0: Chrome EC device registered
10618 22:56:39.973172 <6>[ 1.962853] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10619 22:56:39.980514 <6>[ 1.975885] mmcblk0: mmc0:0001 DA4128 116 GiB
10620 22:56:39.990177 <6>[ 1.982584] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10621 22:56:39.996974 <6>[ 1.992439] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10622 22:56:40.003456 <6>[ 1.992966] NET: Registered PF_PACKET protocol family
10623 22:56:40.006730 <6>[ 1.999742] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10624 22:56:40.013112 <6>[ 2.003740] 9pnet: Installing 9P2000 support
10625 22:56:40.016865 <6>[ 2.009532] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10626 22:56:40.023056 <5>[ 2.013442] Key type dns_resolver registered
10627 22:56:40.029779 <6>[ 2.019319] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10628 22:56:40.033338 <6>[ 2.023558] registered taskstats version 1
10629 22:56:40.039560 <5>[ 2.034043] Loading compiled-in X.509 certificates
10630 22:56:40.068398 <4>[ 2.056980] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 22:56:40.078534 <4>[ 2.067693] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 22:56:40.085173 <3>[ 2.078218] debugfs: File 'uA_load' in directory '/' already present!
10633 22:56:40.091658 <3>[ 2.084917] debugfs: File 'min_uV' in directory '/' already present!
10634 22:56:40.098301 <3>[ 2.091586] debugfs: File 'max_uV' in directory '/' already present!
10635 22:56:40.105276 <3>[ 2.098203] debugfs: File 'constraint_flags' in directory '/' already present!
10636 22:56:40.118631 <6>[ 2.113534] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10637 22:56:40.125259 <6>[ 2.120565] xhci-mtk 11200000.usb: xHCI Host Controller
10638 22:56:40.131771 <6>[ 2.126109] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10639 22:56:40.142551 <6>[ 2.133992] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10640 22:56:40.149177 <6>[ 2.143432] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10641 22:56:40.155695 <6>[ 2.149612] xhci-mtk 11200000.usb: xHCI Host Controller
10642 22:56:40.162288 <6>[ 2.155112] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10643 22:56:40.169141 <6>[ 2.162763] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10644 22:56:40.175610 <6>[ 2.170577] hub 1-0:1.0: USB hub found
10645 22:56:40.179168 <6>[ 2.174603] hub 1-0:1.0: 1 port detected
10646 22:56:40.185813 <6>[ 2.178865] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10647 22:56:40.192662 <6>[ 2.187576] hub 2-0:1.0: USB hub found
10648 22:56:40.196001 <6>[ 2.191594] hub 2-0:1.0: 1 port detected
10649 22:56:40.204994 <6>[ 2.199929] mtk-msdc 11f70000.mmc: Got CD GPIO
10650 22:56:40.216182 <6>[ 2.208193] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10651 22:56:40.223083 <6>[ 2.216226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10652 22:56:40.233135 <4>[ 2.224146] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10653 22:56:40.242941 <6>[ 2.233666] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10654 22:56:40.249709 <6>[ 2.241742] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10655 22:56:40.256415 <6>[ 2.249840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10656 22:56:40.266224 <6>[ 2.257776] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10657 22:56:40.273074 <6>[ 2.265601] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10658 22:56:40.283088 <6>[ 2.273421] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10659 22:56:40.293140 <6>[ 2.283825] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10660 22:56:40.299512 <6>[ 2.292185] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10661 22:56:40.309781 <6>[ 2.300525] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10662 22:56:40.316669 <6>[ 2.308863] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10663 22:56:40.326169 <6>[ 2.317202] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10664 22:56:40.332908 <6>[ 2.325540] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10665 22:56:40.342855 <6>[ 2.333881] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10666 22:56:40.349295 <6>[ 2.342218] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10667 22:56:40.358800 <6>[ 2.350556] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10668 22:56:40.365577 <6>[ 2.358894] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10669 22:56:40.375557 <6>[ 2.367232] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10670 22:56:40.382507 <6>[ 2.375569] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10671 22:56:40.392506 <6>[ 2.383907] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10672 22:56:40.399355 <6>[ 2.392245] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10673 22:56:40.408795 <6>[ 2.400583] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10674 22:56:40.415548 <6>[ 2.409308] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10675 22:56:40.421819 <6>[ 2.416472] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10676 22:56:40.428816 <6>[ 2.423227] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10677 22:56:40.435417 <6>[ 2.429999] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10678 22:56:40.441915 <6>[ 2.436934] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10679 22:56:40.451946 <6>[ 2.443792] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10680 22:56:40.461936 <6>[ 2.452921] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10681 22:56:40.471561 <6>[ 2.462040] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10682 22:56:40.481521 <6>[ 2.471334] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10683 22:56:40.491992 <6>[ 2.480801] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10684 22:56:40.498317 <6>[ 2.490269] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10685 22:56:40.507834 <6>[ 2.499409] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10686 22:56:40.518341 <6>[ 2.508876] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10687 22:56:40.528217 <6>[ 2.517996] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10688 22:56:40.537903 <6>[ 2.527292] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10689 22:56:40.547436 <6>[ 2.537452] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10690 22:56:40.557396 <6>[ 2.549397] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10691 22:56:40.563777 <6>[ 2.559085] Trying to probe devices needed for running init ...
10692 22:56:40.586765 <6>[ 2.578579] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10693 22:56:40.614927 <6>[ 2.610158] hub 2-1:1.0: USB hub found
10694 22:56:40.618339 <6>[ 2.614646] hub 2-1:1.0: 3 ports detected
10695 22:56:40.626612 <6>[ 2.622019] hub 2-1:1.0: USB hub found
10696 22:56:40.630087 <6>[ 2.626467] hub 2-1:1.0: 3 ports detected
10697 22:56:40.738050 <6>[ 2.730514] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10698 22:56:40.893633 <6>[ 2.888511] hub 1-1:1.0: USB hub found
10699 22:56:40.896784 <6>[ 2.893007] hub 1-1:1.0: 4 ports detected
10700 22:56:40.906591 <6>[ 2.901774] hub 1-1:1.0: USB hub found
10701 22:56:40.909852 <6>[ 2.906377] hub 1-1:1.0: 4 ports detected
10702 22:56:40.978258 <6>[ 2.970771] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10703 22:56:41.086717 <6>[ 3.079204] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10704 22:56:41.122421 <4>[ 3.114725] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10705 22:56:41.132257 <4>[ 3.123878] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10706 22:56:41.171631 <6>[ 3.167153] r8152 2-1.3:1.0 eth0: v1.12.13
10707 22:56:41.246471 <6>[ 3.238508] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10708 22:56:41.379859 <6>[ 3.374571] hub 1-1.4:1.0: USB hub found
10709 22:56:41.382726 <6>[ 3.379256] hub 1-1.4:1.0: 2 ports detected
10710 22:56:41.392419 <6>[ 3.387835] hub 1-1.4:1.0: USB hub found
10711 22:56:41.395394 <6>[ 3.392445] hub 1-1.4:1.0: 2 ports detected
10712 22:56:41.699087 <6>[ 3.690605] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10713 22:56:41.890386 <6>[ 3.882367] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10714 22:56:42.851646 <6>[ 4.847033] r8152 2-1.3:1.0 eth0: carrier on
10715 22:56:44.914629 <5>[ 4.878301] Sending DHCP requests .., OK
10716 22:56:44.921090 <6>[ 6.914702] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10717 22:56:44.924615 <6>[ 6.922993] IP-Config: Complete:
10718 22:56:44.937898 <6>[ 6.926493] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10719 22:56:44.944418 <6>[ 6.937212] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10720 22:56:44.951544 <6>[ 6.945830] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10721 22:56:44.958045 <6>[ 6.945839] nameserver0=192.168.201.1
10722 22:56:44.960909 <6>[ 6.958012] clk: Disabling unused clocks
10723 22:56:44.964444 <6>[ 6.963514] ALSA device list:
10724 22:56:44.970788 <6>[ 6.966795] No soundcards found.
10725 22:56:44.978999 <6>[ 6.974390] Freeing unused kernel memory: 8512K
10726 22:56:44.981974 <6>[ 6.979293] Run /init as init process
10727 22:56:44.991787 Loading, please wait...
10728 22:56:45.017613 Starting systemd-udevd version 252.22-1~deb12u1
10729 22:56:45.018181
10730 22:56:45.286879 <6>[ 7.279205] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10731 22:56:45.308626 <6>[ 7.304852] remoteproc remoteproc0: scp is available
10732 22:56:45.315063 <6>[ 7.310358] remoteproc remoteproc0: powering up scp
10733 22:56:45.321873 <6>[ 7.315551] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10734 22:56:45.328275 <6>[ 7.324008] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10735 22:56:45.334828 <3>[ 7.324058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 22:56:45.345117 <6>[ 7.324910] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10737 22:56:45.351442 <6>[ 7.324977] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10738 22:56:45.361272 <6>[ 7.324993] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10739 22:56:45.368232 <4>[ 7.331335] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10740 22:56:45.378085 <3>[ 7.338144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 22:56:45.385030 <4>[ 7.348270] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10742 22:56:45.387915 <6>[ 7.353126] mc: Linux media interface: v0.10
10743 22:56:45.398030 <3>[ 7.354362] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 22:56:45.404508 <6>[ 7.380779] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10745 22:56:45.411295 <3>[ 7.387054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 22:56:45.417822 <6>[ 7.402359] videodev: Linux video capture interface: v2.00
10747 22:56:45.427842 <3>[ 7.406268] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 22:56:45.434916 <4>[ 7.415850] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10749 22:56:45.441964 <4>[ 7.415850] Fallback method does not support PEC.
10750 22:56:45.448941 <3>[ 7.420116] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 22:56:45.458890 <6>[ 7.438826] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10752 22:56:45.466137 <3>[ 7.441624] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 22:56:45.475930 <3>[ 7.443090] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10754 22:56:45.482855 <6>[ 7.443622] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10755 22:56:45.489385 <6>[ 7.443630] pci_bus 0000:00: root bus resource [bus 00-ff]
10756 22:56:45.495928 <6>[ 7.443639] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10757 22:56:45.506131 <6>[ 7.443645] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10758 22:56:45.512083 <6>[ 7.443684] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10759 22:56:45.519277 <6>[ 7.443709] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10760 22:56:45.522266 <6>[ 7.443802] pci 0000:00:00.0: supports D1 D2
10761 22:56:45.532474 <6>[ 7.443807] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10762 22:56:45.538984 <6>[ 7.445488] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10763 22:56:45.545892 <6>[ 7.445598] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10764 22:56:45.552589 <6>[ 7.445631] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10765 22:56:45.558723 <6>[ 7.445652] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10766 22:56:45.568485 <6>[ 7.445672] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10767 22:56:45.571977 <6>[ 7.445798] pci 0000:01:00.0: supports D1 D2
10768 22:56:45.578576 <6>[ 7.445801] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10769 22:56:45.588854 <6>[ 7.450074] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10770 22:56:45.595033 <6>[ 7.458350] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10771 22:56:45.601763 <6>[ 7.458379] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10772 22:56:45.611951 <6>[ 7.458386] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10773 22:56:45.618617 <6>[ 7.458399] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10774 22:56:45.628296 <6>[ 7.458415] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10775 22:56:45.635182 <6>[ 7.458431] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10776 22:56:45.641837 <6>[ 7.458448] pci 0000:00:00.0: PCI bridge to [bus 01]
10777 22:56:45.648515 <6>[ 7.458456] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10778 22:56:45.655219 <6>[ 7.458574] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10779 22:56:45.661975 <6>[ 7.459350] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10780 22:56:45.671744 <6>[ 7.459439] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10781 22:56:45.674727 <6>[ 7.459447] remoteproc remoteproc0: remote processor scp is now up
10782 22:56:45.681456 <6>[ 7.459585] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10783 22:56:45.691706 <3>[ 7.459773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 22:56:45.698337 <3>[ 7.459834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 22:56:45.705039 <6>[ 7.460067] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10786 22:56:45.714833 <3>[ 7.465962] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10787 22:56:45.721445 <6>[ 7.468634] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10788 22:56:45.731397 <3>[ 7.476657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 22:56:45.737375 <5>[ 7.508371] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10790 22:56:45.747822 <3>[ 7.512560] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 22:56:45.754469 <3>[ 7.512576] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 22:56:45.757710 <6>[ 7.513752] Bluetooth: Core ver 2.22
10793 22:56:45.764579 <6>[ 7.513803] NET: Registered PF_BLUETOOTH protocol family
10794 22:56:45.771034 <6>[ 7.513805] Bluetooth: HCI device and connection manager initialized
10795 22:56:45.777508 <6>[ 7.513816] Bluetooth: HCI socket layer initialized
10796 22:56:45.781059 <6>[ 7.513819] Bluetooth: L2CAP socket layer initialized
10797 22:56:45.787768 <6>[ 7.513825] Bluetooth: SCO socket layer initialized
10798 22:56:45.794398 <6>[ 7.521839] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10799 22:56:45.803815 <3>[ 7.524699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 22:56:45.810893 <6>[ 7.535078] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10801 22:56:45.817235 <5>[ 7.535671] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10802 22:56:45.827361 <5>[ 7.536162] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10803 22:56:45.833996 <4>[ 7.536241] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10804 22:56:45.840425 <6>[ 7.536249] cfg80211: failed to load regulatory.db
10805 22:56:45.847042 <3>[ 7.539724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10806 22:56:45.856919 <3>[ 7.539730] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 22:56:45.863818 <3>[ 7.539737] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 22:56:45.870208 <6>[ 7.547659] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10809 22:56:45.880506 <3>[ 7.553470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 22:56:45.886667 <3>[ 7.553537] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10811 22:56:45.900280 <6>[ 7.562207] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10812 22:56:45.906641 <6>[ 7.569969] usbcore: registered new interface driver btusb
10813 22:56:45.916662 <4>[ 7.570728] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10814 22:56:45.923240 <3>[ 7.570737] Bluetooth: hci0: Failed to load firmware file (-2)
10815 22:56:45.926638 <3>[ 7.570740] Bluetooth: hci0: Failed to set up firmware (-2)
10816 22:56:45.939671 <4>[ 7.570743] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10817 22:56:45.943109 <6>[ 7.573395] usbcore: registered new interface driver uvcvideo
10818 22:56:45.949505 <6>[ 7.581186] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10819 22:56:45.986866 <6>[ 7.979312] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10820 22:56:45.993673 <6>[ 7.986820] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10821 22:56:46.017669 <6>[ 8.013485] mt7921e 0000:01:00.0: ASIC revision: 79610010
10822 22:56:46.122002 <6>[ 8.114157] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10823 22:56:46.125557 <6>[ 8.114157]
10824 22:56:46.128504 Begin: Loading essential drivers ... done.
10825 22:56:46.131594 Begin: Running /scripts/init-premount ... done.
10826 22:56:46.138218 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10827 22:56:46.148333 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10828 22:56:46.151334 Device /sys/class/net/eth0 found
10829 22:56:46.151928 done.
10830 22:56:46.164315 Begin: Waiting up to 180 secs for any network device to become available ... done.
10831 22:56:46.202773 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10832 22:56:46.209813 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10833 22:56:46.215744 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10834 22:56:46.222581 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10835 22:56:46.229061 host : mt8192-asurada-spherion-r0-cbg-1
10836 22:56:46.235830 domain : lava-rack
10837 22:56:46.239164 rootserver: 192.168.201.1 rootpath:
10838 22:56:46.239727 filename :
10839 22:56:46.375111 done.
10840 22:56:46.382066 Begin: Running /scripts/nfs-bottom ... done.
10841 22:56:46.388909 Be<6>[ 8.381545] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10842 22:56:46.411587 gin: Running /scripts/init-bottom ... done.
10843 22:56:47.754182 <6>[ 9.750086] NET: Registered PF_INET6 protocol family
10844 22:56:47.761708 <6>[ 9.757181] Segment Routing with IPv6
10845 22:56:47.764324 <6>[ 9.761168] In-situ OAM (IOAM) with IPv6
10846 22:56:47.929850 <30>[ 9.899559] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10847 22:56:47.936362 <30>[ 9.932708] systemd[1]: Detected architecture arm64.
10848 22:56:47.944285
10849 22:56:47.947603 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10850 22:56:47.948029
10851 22:56:47.948360
10852 22:56:47.975200 <30>[ 9.971568] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10853 22:56:48.915540 <30>[ 10.908413] systemd[1]: Queued start job for default target graphical.target.
10854 22:56:48.966122 <30>[ 10.959248] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10855 22:56:48.972625 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10856 22:56:48.973051
10857 22:56:48.995110 <30>[ 10.988272] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10858 22:56:49.005059 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10859 22:56:49.005517
10860 22:56:49.023073 <30>[ 11.016234] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10861 22:56:49.032768 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10862 22:56:49.033203
10863 22:56:49.052075 <30>[ 11.044731] systemd[1]: Created slice user.slice - User and Session Slice.
10864 22:56:49.058406 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10865 22:56:49.058875
10866 22:56:49.081497 <30>[ 11.071017] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10867 22:56:49.088373 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10868 22:56:49.088945
10869 22:56:49.109025 <30>[ 11.098767] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10870 22:56:49.115885 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10871 22:56:49.116359
10872 22:56:49.143829 <30>[ 11.127172] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10873 22:56:49.153888 <30>[ 11.147064] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10874 22:56:49.160769 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10875 22:56:49.161240
10876 22:56:49.177387 <30>[ 11.170537] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10877 22:56:49.184179 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10878 22:56:49.184675
10879 22:56:49.201425 <30>[ 11.194589] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10880 22:56:49.211321 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10881 22:56:49.211798
10882 22:56:49.226101 <30>[ 11.222632] systemd[1]: Reached target paths.target - Path Units.
10883 22:56:49.232973 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10884 22:56:49.233492
10885 22:56:49.253758 <30>[ 11.246562] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10886 22:56:49.260128 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10887 22:56:49.260614
10888 22:56:49.274113 <30>[ 11.270518] systemd[1]: Reached target slices.target - Slice Units.
10889 22:56:49.284066 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10890 22:56:49.284552
10891 22:56:49.298325 <30>[ 11.294582] systemd[1]: Reached target swap.target - Swaps.
10892 22:56:49.305129 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10893 22:56:49.305762
10894 22:56:49.326182 <30>[ 11.319051] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10895 22:56:49.336220 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10896 22:56:49.336782
10897 22:56:49.355096 <30>[ 11.347560] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10898 22:56:49.364611 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10899 22:56:49.365244
10900 22:56:49.383976 <30>[ 11.376645] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10901 22:56:49.394031 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10902 22:56:49.394613
10903 22:56:49.411077 <30>[ 11.404224] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10904 22:56:49.421168 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10905 22:56:49.421782
10906 22:56:49.438928 <30>[ 11.432077] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10907 22:56:49.445531 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10908 22:56:49.446049
10909 22:56:49.466880 <30>[ 11.460070] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10910 22:56:49.476396 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10911 22:56:49.476494
10912 22:56:49.496030 <30>[ 11.489279] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10913 22:56:49.505751 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10914 22:56:49.505930
10915 22:56:49.522468 <30>[ 11.515753] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10916 22:56:49.532403 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10917 22:56:49.532884
10918 22:56:49.581708 <30>[ 11.574774] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10919 22:56:49.588277 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10920 22:56:49.588843
10921 22:56:49.609565 <30>[ 11.603146] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10922 22:56:49.616421 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10923 22:56:49.616532
10924 22:56:49.642122 <30>[ 11.635395] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10925 22:56:49.648851 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10926 22:56:49.649482
10927 22:56:49.676593 <30>[ 11.663195] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10928 22:56:49.738046 <30>[ 11.731173] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10929 22:56:49.748239 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10930 22:56:49.748716
10931 22:56:49.771184 <30>[ 11.764049] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10932 22:56:49.777727 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10933 22:56:49.778253
10934 22:56:49.801727 <30>[ 11.794536] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10935 22:56:49.807966 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10936 22:56:49.808443
10937 22:56:49.829443 <30>[ 11.822750] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10938 22:56:49.836204 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10939 22:56:49.846259 <6>[ 11.836542] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10940 22:56:49.846691
10941 22:56:49.868983 <30>[ 11.861869] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10942 22:56:49.878532 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10943 22:56:49.879005
10944 22:56:49.901119 <30>[ 11.894226] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10945 22:56:49.908014 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10946 22:56:49.908491
10947 22:56:49.930063 <30>[ 11.923318] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10948 22:56:49.936809 Startin<6>[ 11.932153] fuse: init (API version 7.37)
10949 22:56:49.943382 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10950 22:56:49.943807
10951 22:56:49.990579 <30>[ 11.983440] systemd[1]: Starting systemd-journald.service - Journal Service...
10952 22:56:49.996871 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10953 22:56:49.997376
10954 22:56:50.030020 <30>[ 12.023037] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10955 22:56:50.036842 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10956 22:56:50.037530
10957 22:56:50.064601 <30>[ 12.054768] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10958 22:56:50.070968 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10959 22:56:50.071078
10960 22:56:50.093706 <30>[ 12.087283] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10961 22:56:50.103475 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10962 22:56:50.103625
10963 22:56:50.141269 <3>[ 12.134317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 22:56:50.153922 <30>[ 12.146884] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10965 22:56:50.160082 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10966 22:56:50.160683
10967 22:56:50.182449 <3>[ 12.175441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 22:56:50.188664 <30>[ 12.179736] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10969 22:56:50.198755 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10970 22:56:50.199253
10971 22:56:50.218063 <30>[ 12.210995] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10972 22:56:50.227724 <3>[ 12.213779] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 22:56:50.234768 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10974 22:56:50.235218
10975 22:56:50.254594 <30>[ 12.247169] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10976 22:56:50.261101 <3>[ 12.248760] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 22:56:50.271010 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10978 22:56:50.271574
10979 22:56:50.291195 <30>[ 12.284231] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10980 22:56:50.301291 <3>[ 12.288252] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 22:56:50.307935 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10982 22:56:50.308402
10983 22:56:50.326929 <30>[ 12.319876] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10984 22:56:50.333639 <3>[ 12.324213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 22:56:50.343574 <30>[ 12.328001] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10986 22:56:50.350663 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10987 22:56:50.351146
10988 22:56:50.364050 <3>[ 12.357118] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 22:56:50.374755 <30>[ 12.367518] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10990 22:56:50.381263 <30>[ 12.375118] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10991 22:56:50.395104 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 12.387156] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 22:56:50.398383 m_mod.s…e[0m - Load Kernel Module dm_mod.
10993 22:56:50.398950
10994 22:56:50.416424 <30>[ 12.411841] systemd[1]: modprobe@drm.service: Deactivated successfully.
10995 22:56:50.426429 <30>[ 12.419379] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10996 22:56:50.432963 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10997 22:56:50.433485
10998 22:56:50.450433 <30>[ 12.443373] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10999 22:56:50.457240 <30>[ 12.451251] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11000 22:56:50.467330 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11001 22:56:50.467947
11002 22:56:50.485842 <30>[ 12.479058] systemd[1]: Started systemd-journald.service - Journal Service.
11003 22:56:50.492633 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11004 22:56:50.493098
11005 22:56:50.511678 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11006 22:56:50.512268
11007 22:56:50.531022 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11008 22:56:50.531575
11009 22:56:50.550660 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11010 22:56:50.551215
11011 22:56:50.567703 <4>[ 12.563831] power_supply_show_property: 2 callbacks suppressed
11012 22:56:50.577568 <3>[ 12.563847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 22:56:50.591424 <4>[ 12.578744] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11014 22:56:50.604626 [[0;32m OK [<3>[ 12.590447] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 22:56:50.611408 <3>[ 12.594373] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11016 22:56:50.618165 0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11017 22:56:50.618753
11018 22:56:50.641853 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel F<3>[ 12.632941] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 22:56:50.642390 ile Systems.
11020 22:56:50.642773
11021 22:56:50.662604 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11022 22:56:50.663186
11023 22:56:50.668920 <3>[ 12.663315] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 22:56:50.680490 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11025 22:56:50.681053
11026 22:56:50.700335 <3>[ 12.693510] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11027 22:56:50.713655 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11028 22:56:50.714312
11029 22:56:50.729983 <3>[ 12.722530] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 22:56:50.736133 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11031 22:56:50.736677
11032 22:56:50.759185 <3>[ 12.752453] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11033 22:56:50.788829 <3>[ 12.782101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11034 22:56:50.802425 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11035 22:56:50.802980
11036 22:56:50.819645 <3>[ 12.812480] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11037 22:56:50.832615 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11038 22:56:50.833050
11039 22:56:50.848597 <3>[ 12.841828] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11040 22:56:50.866176 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11041 22:56:50.866605
11042 22:56:50.893192 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11043 22:56:50.893698
11044 22:56:50.910513 <46>[ 12.903777] systemd-journald[308]: Received client request to flush runtime journal.
11045 22:56:50.927888 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11046 22:56:50.928569
11047 22:56:50.947729 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11048 22:56:50.948341
11049 22:56:50.966826 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11050 22:56:50.967257
11051 22:56:50.986840 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11052 22:56:50.987147
11053 22:56:51.702371 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11054 22:56:51.702511
11055 22:56:51.746389 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11056 22:56:51.746493
11057 22:56:52.341070 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11058 22:56:52.341219
11059 22:56:52.380907 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11060 22:56:52.381076
11061 22:56:52.397417 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11062 22:56:52.397636
11063 22:56:52.413358 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11064 22:56:52.413577
11065 22:56:52.474101 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11066 22:56:52.474706
11067 22:56:52.498721 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11068 22:56:52.499218
11069 22:56:52.696169 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11070 22:56:52.696304
11071 22:56:52.752358 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11072 22:56:52.752512
11073 22:56:52.794379 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11074 22:56:52.794475
11075 22:56:52.822215 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11076 22:56:52.822330
11077 22:56:52.962884 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11078 22:56:52.963096
11079 22:56:52.988439 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11080 22:56:52.988563
11081 22:56:53.136161 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11082 22:56:53.136328
11083 22:56:53.149994 <6>[ 15.147030] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11084 22:56:53.183152 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11085 22:56:53.183278
11086 22:56:53.249244 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11087 22:56:53.249408
11088 22:56:53.317598 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11089 22:56:53.317716
11090 22:56:53.343523 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11091 22:56:53.343646
11092 22:56:53.361615 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11093 22:56:53.361724
11094 22:56:53.389192 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11095 22:56:53.389307
11096 22:56:53.417611 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11097 22:56:53.417721
11098 22:56:53.436907 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11099 22:56:53.437014
11100 22:56:53.457512 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11101 22:56:53.457593
11102 22:56:53.472699 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11103 22:56:53.472806
11104 22:56:53.493873 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11105 22:56:53.493962
11106 22:56:53.519694 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11107 22:56:53.519893
11108 22:56:53.536896 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11109 22:56:53.537036
11110 22:56:53.586025 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11111 22:56:53.586134
11112 22:56:53.607805 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11113 22:56:53.607925
11114 22:56:53.624991 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11115 22:56:53.625100
11116 22:56:53.642610 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11117 22:56:53.642723
11118 22:56:53.660516 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11119 22:56:53.660623
11120 22:56:53.677162 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11121 22:56:53.677272
11122 22:56:53.692870 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11123 22:56:53.692975
11124 22:56:53.729683 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11125 22:56:53.729800
11126 22:56:53.806119 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11127 22:56:53.806265
11128 22:56:53.914667 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11129 22:56:53.914827
11130 22:56:53.940919 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11131 22:56:53.941047
11132 22:56:53.958784 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11133 22:56:53.958868
11134 22:56:53.991883 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11135 22:56:53.991969
11136 22:56:54.059038 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11137 22:56:54.059170
11138 22:56:54.109549 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11139 22:56:54.109666
11140 22:56:54.128980 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11141 22:56:54.129092
11142 22:56:54.149050 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11143 22:56:54.149161
11144 22:56:54.167717 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11145 22:56:54.167824
11146 22:56:54.277615 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11147 22:56:54.277732
11148 22:56:54.296554 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11149 22:56:54.296639
11150 22:56:54.317066 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11151 22:56:54.317161
11152 22:56:54.336141 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11153 22:56:54.336317
11154 22:56:54.386117 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11155 22:56:54.386693
11156 22:56:54.440681 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11157 22:56:54.441481
11158 22:56:54.508084
11159 22:56:54.508179
11160 22:56:54.511599 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11161 22:56:54.511688
11162 22:56:54.514901 debian-bookworm-arm64 login: root (automatic login)
11163 22:56:54.514992
11164 22:56:54.515073
11165 22:56:54.724820 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
11166 22:56:54.724944
11167 22:56:54.731537 The programs included with the Debian GNU/Linux system are free software;
11168 22:56:54.738132 the exact distribution terms for each program are described in the
11169 22:56:54.741666 individual files in /usr/share/doc/*/copyright.
11170 22:56:54.741751
11171 22:56:54.748173 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11172 22:56:54.751273 permitted by applicable law.
11173 22:56:54.803055 Matched prompt #10: / #
11175 22:56:54.803345 Setting prompt string to ['/ #']
11176 22:56:54.803478 end: 2.2.5.1 login-action (duration 00:00:18) [common]
11178 22:56:54.803709 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
11179 22:56:54.803838 start: 2.2.6 expect-shell-connection (timeout 00:03:46) [common]
11180 22:56:54.803945 Setting prompt string to ['/ #']
11181 22:56:54.804036 Forcing a shell prompt, looking for ['/ #']
11183 22:56:54.854264 / #
11184 22:56:54.854500 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11185 22:56:54.854644 Waiting using forced prompt support (timeout 00:02:30)
11186 22:56:54.859699
11187 22:56:54.860091 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11188 22:56:54.860295 start: 2.2.7 export-device-env (timeout 00:03:46) [common]
11190 22:56:54.960747 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683739/extract-nfsrootfs-88_0ur2m'
11191 22:56:54.965548 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683739/extract-nfsrootfs-88_0ur2m'
11193 22:56:55.066146 / # export NFS_SERVER_IP='192.168.201.1'
11194 22:56:55.072257 export NFS_SERVER_IP='192.168.201.1'
11195 22:56:55.073071 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11196 22:56:55.073632 end: 2.2 depthcharge-retry (duration 00:01:14) [common]
11197 22:56:55.074146 end: 2 depthcharge-action (duration 00:01:14) [common]
11198 22:56:55.074661 start: 3 lava-test-retry (timeout 00:30:00) [common]
11199 22:56:55.075157 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11200 22:56:55.075565 Using namespace: common
11202 22:56:55.176650 / # #
11203 22:56:55.177189 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11204 22:56:55.182915 #
11205 22:56:55.183623 Using /lava-13683739
11207 22:56:55.284600 / # export SHELL=/bin/sh
11208 22:56:55.291168 export SHELL=/bin/sh
11210 22:56:55.392624 / # . /lava-13683739/environment
11211 22:56:55.398768 . /lava-13683739/environment
11213 22:56:55.506278 / # /lava-13683739/bin/lava-test-runner /lava-13683739/0
11214 22:56:55.506916 Test shell timeout: 10s (minimum of the action and connection timeout)
11215 22:56:55.512442 /lava-13683739/bin/lava-test-runner /lava-13683739/0
11216 22:56:55.711280 + export TESTRUN_ID=0_lc-compliance
11217 22:56:55.718114 + cd /lava-13683739/0/tests/0_lc-compliance
11218 22:56:55.718215 + cat uuid
11219 22:56:55.722430 + UUID=13683739_1.6.2.3.1
11220 22:56:55.722514 + set +x
11221 22:56:55.729108 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 13683739_1.6.2.3.1>
11222 22:56:55.729324 Received signal: <STARTRUN> 0_lc-compliance 13683739_1.6.2.3.1
11223 22:56:55.729399 Starting test lava.0_lc-compliance (13683739_1.6.2.3.1)
11224 22:56:55.729485 Skipping test definition patterns.
11225 22:56:55.732561 + /usr/bin/lc-compliance-parser.sh
11226 22:56:57.335481 [0:00:19.150407652] [416] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11227 22:56:57.338476 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11228 22:56:57.351883 [0:00:19.166854443] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11229 22:56:57.413873 [0:00:19.227822628] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11230 22:56:57.421754 [==========] Running 120 tests from 1 test suite.
11231 22:56:57.466886 [0:00:19.280209421] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11232 22:56:57.497747 [----------] Global test environment set-up.
11233 22:56:57.521816 [0:00:19.334560612] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11234 22:56:57.566421 [----------] 120 tests from CaptureTests/SingleStream
11235 22:56:57.636103 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11236 22:56:57.697717 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11237 22:56:57.698541 Received signal: <TESTSET> START CaptureTests/SingleStream
11238 22:56:57.698975 Starting test_set CaptureTests/SingleStream
11239 22:56:57.700770 Camera needs 4 requests, can't test only 1
11240 22:56:57.772196 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11241 22:56:57.844932
11242 22:56:57.917610 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (61 ms)
11243 22:56:57.948177 [0:00:19.754611886] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11244 22:56:57.997800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11245 22:56:57.998066 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11247 22:56:58.009022 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11248 22:56:58.047232 Camera needs 4 requests, can't test only 2
11249 22:56:58.098795 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11250 22:56:58.149145
11251 22:56:58.213603 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (53 ms)
11252 22:56:58.280736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11253 22:56:58.281056 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11255 22:56:58.291211 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11256 22:56:58.328237 Camera needs 4 requests, can't test only 3
11257 22:56:58.375950 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11258 22:56:58.425779
11259 22:56:58.484807 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (52 ms)
11260 22:56:58.545695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11261 22:56:58.545983 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11263 22:56:58.556822 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11264 22:56:58.591188 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (421 ms)
11265 22:56:58.640679 [0:00:20.437715550] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11266 22:56:58.648010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11267 22:56:58.648271 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11269 22:56:58.657478 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11270 22:56:58.696805 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (682 ms)
11271 22:56:58.767348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11272 22:56:58.767621 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11274 22:56:58.779753 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11275 22:56:59.887458 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1238 ms)
11276 22:56:59.897828 [0:00:21.677455868] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11277 22:56:59.973435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11278 22:56:59.974323 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11280 22:56:59.987115 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11281 22:57:01.704084 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1797 ms)
11282 22:57:01.713334 [0:00:23.475373499] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11283 22:57:01.803847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11284 22:57:01.804133 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11286 22:57:01.817105 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11287 22:57:04.430265 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2705 ms)
11288 22:57:04.440017 [0:00:26.181215887] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11289 22:57:04.513325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11290 22:57:04.513598 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11292 22:57:04.528047 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11293 22:57:08.626504 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4176 ms)
11294 22:57:08.636294 [0:00:30.358025553] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11295 22:57:08.730518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11296 22:57:08.731222 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11298 22:57:08.745248 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11299 22:57:15.202514 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6561 ms)
11300 22:57:15.212519 [0:00:36.919355799] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11301 22:57:15.267422 [0:00:36.974601854] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11302 22:57:15.314556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11303 22:57:15.315388 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11305 22:57:15.324604 [0:00:37.030282617] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11306 22:57:15.335819 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11307 22:57:15.378483 [0:00:37.085823213] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11308 22:57:15.391561 Camera needs 4 requests, can't test only 1
11309 22:57:15.465572 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11310 22:57:15.539704
11311 22:57:15.606704 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (54 ms)
11312 22:57:15.693896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11313 22:57:15.694623 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11315 22:57:15.706846 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11316 22:57:15.759191 Camera needs 4 requests, can't test only 2
11317 22:57:15.837677 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11318 22:57:15.913664
11319 22:57:16.000155 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (56 ms)
11320 22:57:16.073939 [0:00:37.780887604] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11321 22:57:16.101218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11322 22:57:16.101935 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11324 22:57:16.116419 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11325 22:57:16.135661 <6>[ 38.138405] vpu: disabling
11326 22:57:16.138833 <6>[ 38.141499] vproc2: disabling
11327 22:57:16.142424 <6>[ 38.144851] vproc1: disabling
11328 22:57:16.145452 <6>[ 38.148158] vaud18: disabling
11329 22:57:16.153089 <6>[ 38.152729] vsram_others: disabling
11330 22:57:16.156419 <6>[ 38.156747] va09: disabling
11331 22:57:16.159820 <6>[ 38.159940] vsram_md: disabling
11332 22:57:16.163281 <6>[ 38.163525] Vgpu: disabling
11333 22:57:16.166573 Camera needs 4 requests, can't test only 3
11334 22:57:16.245118 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11335 22:57:16.318637
11336 22:57:16.392380 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (55 ms)
11337 22:57:16.477230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11338 22:57:16.477566 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11340 22:57:16.490297 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11341 22:57:16.541108 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (694 ms)
11342 22:57:16.619908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11343 22:57:16.620202 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11345 22:57:16.635031 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11346 22:57:16.974515 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (907 ms)
11347 22:57:16.987471 [0:00:38.688425967] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11348 22:57:17.076506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11349 22:57:17.077261 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11351 22:57:17.093715 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11352 22:57:18.230142 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1254 ms)
11353 22:57:18.243393 [0:00:39.943350757] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11354 22:57:18.323638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11355 22:57:18.324454 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11357 22:57:18.337579 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11358 22:57:20.047283 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1815 ms)
11359 22:57:20.059672 [0:00:41.758754754] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11360 22:57:20.138997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11361 22:57:20.139762 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11363 22:57:20.152940 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11364 22:57:22.774167 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2725 ms)
11365 22:57:22.787469 [0:00:44.484902975] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11366 22:57:22.865251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11367 22:57:22.866044 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11369 22:57:22.879468 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11370 22:57:26.971001 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4194 ms)
11371 22:57:26.983647 [0:00:48.679872930] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11372 22:57:27.080870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11373 22:57:27.081682 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11375 22:57:27.098162 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11376 22:57:33.547104 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6575 ms)
11377 22:57:33.560067 [0:00:55.255530545] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11378 22:57:33.609391 [0:00:55.309423385] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11379 22:57:33.646369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11380 22:57:33.647118 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11382 22:57:33.664998 [0:00:55.364805965] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11383 22:57:33.668313 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11384 22:57:33.719440 [0:00:55.419138596] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11385 22:57:33.722856 Camera needs 4 requests, can't test only 1
11386 22:57:33.790624 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11387 22:57:33.863270
11388 22:57:33.945123 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (54 ms)
11389 22:57:34.027396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11390 22:57:34.028130 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11392 22:57:34.040698 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11393 22:57:34.090331 Camera needs 4 requests, can't test only 2
11394 22:57:34.167084 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11395 22:57:34.238523
11396 22:57:34.322225 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (55 ms)
11397 22:57:34.414045 [0:00:56.113923765] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11398 22:57:34.420796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11399 22:57:34.421535 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11401 22:57:34.429108 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11402 22:57:34.479904 Camera needs 4 requests, can't test only 3
11403 22:57:34.554501 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11404 22:57:34.625820
11405 22:57:34.706808 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (54 ms)
11406 22:57:34.799199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11407 22:57:34.799919 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11409 22:57:34.814296 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11410 22:57:34.867353 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (694 ms)
11411 22:57:34.954492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11412 22:57:34.955264 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11414 22:57:34.972257 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11415 22:57:35.313052 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (907 ms)
11416 22:57:35.326573 [0:00:57.021527464] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11417 22:57:35.410687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11418 22:57:35.411525 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11420 22:57:35.426617 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11421 22:57:36.568729 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1255 ms)
11422 22:57:36.582113 [0:00:58.277510934] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11423 22:57:36.667011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11424 22:57:36.667858 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11426 22:57:36.684188 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11427 22:57:38.388209 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1816 ms)
11428 22:57:38.398112 [0:01:00.093696112] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11429 22:57:38.482308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11430 22:57:38.483139 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11432 22:57:38.498411 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11433 22:57:41.112686 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2727 ms)
11434 22:57:41.125596 [0:01:02.821420920] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11435 22:57:41.206462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11436 22:57:41.206737 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11438 22:57:41.220261 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11439 22:57:45.308702 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4196 ms)
11440 22:57:45.321744 [0:01:07.017915949] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11441 22:57:45.407121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11442 22:57:45.407870 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11444 22:57:45.424821 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11445 22:57:51.884803 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6576 ms)
11446 22:57:51.897978 [0:01:13.594225738] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11447 22:57:51.946397 [0:01:13.647618914] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11448 22:57:51.979256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11449 22:57:51.979947 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11451 22:57:52.001462 [0:01:13.702527612] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11452 22:57:52.004450 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11453 22:57:52.054572 [0:01:13.755722406] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11454 22:57:52.058116 Camera needs 4 requests, can't test only 1
11455 22:57:52.118737 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11456 22:57:52.177055
11457 22:57:52.245815 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (53 ms)
11458 22:57:52.328510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11459 22:57:52.328867 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11461 22:57:52.342951 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11462 22:57:52.392658 Camera needs 4 requests, can't test only 2
11463 22:57:52.468327 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11464 22:57:52.537493
11465 22:57:52.612428 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (54 ms)
11466 22:57:52.701465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11467 22:57:52.702178 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11469 22:57:52.717331 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11470 22:57:52.749107 [0:01:14.450511462] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11471 22:57:52.774671 Camera needs 4 requests, can't test only 3
11472 22:57:52.842415 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11473 22:57:52.912025
11474 22:57:52.993811 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (54 ms)
11475 22:57:53.086396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11476 22:57:53.087100 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11478 22:57:53.101066 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11479 22:57:53.148319 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (693 ms)
11480 22:57:53.234184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11481 22:57:53.234538 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11483 22:57:53.248613 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11484 22:57:53.645428 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (904 ms)
11485 22:57:53.655670 [0:01:15.355555880] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11486 22:57:53.745159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11487 22:57:53.745444 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11489 22:57:53.763078 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11490 22:57:54.901703 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1256 ms)
11491 22:57:54.914878 [0:01:16.612295416] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11492 22:57:54.991696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11493 22:57:54.992501 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11495 22:57:55.005423 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11496 22:57:56.718484 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1817 ms)
11497 22:57:56.731716 [0:01:18.430051831] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11498 22:57:56.807931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11499 22:57:56.808281 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11501 22:57:56.823397 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11502 22:57:59.446268 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11503 22:57:59.459259 [0:01:21.157970802] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11504 22:57:59.543220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11505 22:57:59.543946 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11507 22:57:59.558846 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11508 22:58:03.643449 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4197 ms)
11509 22:58:03.656703 [0:01:25.355976943] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11510 22:58:03.739949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11511 22:58:03.740754 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11513 22:58:03.752934 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11514 22:58:10.222004 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6579 ms)
11515 22:58:10.235584 [0:01:31.935121486] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11516 22:58:10.289230 [0:01:31.992121967] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11517 22:58:10.322698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11518 22:58:10.323053 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11520 22:58:10.343380 [0:01:32.046463374] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11521 22:58:10.346642 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11522 22:58:10.390956 Camera needs 4 requests, can't test only 1
11523 22:58:10.400491 [0:01:32.103804393] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11524 22:58:10.460383 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11525 22:58:10.531578
11526 22:58:10.604281 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (57 ms)
11527 22:58:10.687919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11528 22:58:10.688255 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11530 22:58:10.703252 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11531 22:58:10.750667 Camera needs 4 requests, can't test only 2
11532 22:58:10.829292 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11533 22:58:10.897009
11534 22:58:10.977573 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (55 ms)
11535 22:58:11.065601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11536 22:58:11.066347 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11538 22:58:11.080652 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11539 22:58:11.133821 Camera needs 4 requests, can't test only 3
11540 22:58:11.213275 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11541 22:58:11.291103
11542 22:58:11.374480 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (54 ms)
11543 22:58:11.468786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11544 22:58:11.469602 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11546 22:58:11.484979 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11547 22:58:12.471737 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2082 ms)
11548 22:58:12.484635 [0:01:34.183525766] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11549 22:58:12.558962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11550 22:58:12.559776 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11552 22:58:12.574232 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11553 22:58:15.186571 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2714 ms)
11554 22:58:15.199614 [0:01:36.899994300] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11555 22:58:15.281930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11556 22:58:15.282979 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11558 22:58:15.298944 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11559 22:58:18.946798 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3760 ms)
11560 22:58:18.960359 [0:01:40.661361296] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11561 22:58:19.046296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11562 22:58:19.047118 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11564 22:58:19.062954 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11565 22:58:24.386495 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5439 ms)
11566 22:58:24.399276 [0:01:46.101305979] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11567 22:58:24.477181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11568 22:58:24.477562 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11570 22:58:24.492501 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11571 22:58:32.560408 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8174 ms)
11572 22:58:32.573621 [0:01:54.276382797] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11573 22:58:32.653837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11574 22:58:32.654587 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11576 22:58:32.667535 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11577 22:58:45.141006 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12581 ms)
11578 22:58:45.153805 [0:02:06.858612654] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11579 22:58:45.232921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11580 22:58:45.233208 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11582 22:58:45.247125 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11583 22:59:04.861624 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19721 ms)
11584 22:59:04.874766 [0:02:26.582276285] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11585 22:59:04.925865 [0:02:26.635575746] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11586 22:59:04.955717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11587 22:59:04.955995 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11589 22:59:04.969587 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11590 22:59:04.983001 [0:02:26.691785285] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11591 22:59:05.017174 Camera needs 4 requests, can't test only 1
11592 22:59:05.035417 [0:02:26.744964746] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11593 22:59:05.091357 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11594 22:59:05.158041
11595 22:59:05.235636 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (53 ms)
11596 22:59:05.320742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11597 22:59:05.321509 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11599 22:59:05.332304 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11600 22:59:05.387596 Camera needs 4 requests, can't test only 2
11601 22:59:05.466932 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11602 22:59:05.539511
11603 22:59:05.617373 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (56 ms)
11604 22:59:05.702852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11605 22:59:05.703647 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11607 22:59:05.712485 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11608 22:59:05.763335 Camera needs 4 requests, can't test only 3
11609 22:59:05.832729 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11610 22:59:05.900828
11611 22:59:05.963563 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (53 ms)
11612 22:59:06.046153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11613 22:59:06.046920 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11615 22:59:06.059252 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11616 22:59:07.107550 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2076 ms)
11617 22:59:07.117956 [0:02:28.822991976] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 22:59:07.200982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11619 22:59:07.201795 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11621 22:59:07.214197 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11622 22:59:09.817813 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2710 ms)
11623 22:59:09.827818 [0:02:31.534634283] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 22:59:09.915780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11625 22:59:09.916471 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11627 22:59:09.930123 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11628 22:59:13.578288 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3760 ms)
11629 22:59:13.588098 [0:02:35.295832743] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 22:59:13.675966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11631 22:59:13.676290 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11633 22:59:13.687110 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11634 22:59:19.019427 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5441 ms)
11635 22:59:19.028995 [0:02:40.737457820] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 22:59:19.108753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11637 22:59:19.109596 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11639 22:59:19.122511 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11640 22:59:27.192097 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8173 ms)
11641 22:59:27.201781 [0:02:48.911154743] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 22:59:27.285872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11643 22:59:27.286632 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11645 22:59:27.298052 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11646 22:59:39.773105 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12582 ms)
11647 22:59:39.783023 [0:03:01.494341743] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11648 22:59:39.872934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11649 22:59:39.873764 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11651 22:59:39.884639 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11652 22:59:59.494767 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19724 ms)
11653 22:59:59.504544 [0:03:21.218210206] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11654 22:59:59.555992 [0:03:21.271387591] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11655 22:59:59.595029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11656 22:59:59.595797 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11658 22:59:59.608981 [0:03:21.325031206] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11659 22:59:59.615347 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11660 22:59:59.656649 Camera needs 4 requests, can't test only 1
11661 22:59:59.666415 [0:03:21.382597898] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11662 22:59:59.739944 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11663 22:59:59.812157
11664 22:59:59.893319 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (53 ms)
11665 22:59:59.992034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11666 22:59:59.992735 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11668 23:00:00.006198 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11669 23:00:00.058043 Camera needs 4 requests, can't test only 2
11670 23:00:00.131502 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11671 23:00:00.205832
11672 23:00:00.291090 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (53 ms)
11673 23:00:00.393669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11674 23:00:00.394749 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11676 23:00:00.406383 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11677 23:00:00.456495 Camera needs 4 requests, can't test only 3
11678 23:00:00.528940 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11679 23:00:00.598254
11680 23:00:00.680621 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (55 ms)
11681 23:00:00.766065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11682 23:00:00.766836 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11684 23:00:00.779106 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11685 23:00:01.738708 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2078 ms)
11686 23:00:01.748281 [0:03:23.460131899] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11687 23:00:01.834408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11688 23:00:01.835238 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11690 23:00:01.845699 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11691 23:00:04.446944 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2709 ms)
11692 23:00:04.456678 [0:03:26.171028053] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11693 23:00:04.520596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11694 23:00:04.520895 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11696 23:00:04.529207 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11697 23:00:08.204384 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3757 ms)
11698 23:00:08.214410 [0:03:29.929109668] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11699 23:00:08.286853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11700 23:00:08.287208 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11702 23:00:08.297747 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11703 23:00:13.644456 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5439 ms)
11704 23:00:13.653760 [0:03:35.368861899] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11705 23:00:13.743008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11706 23:00:13.743704 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11708 23:00:13.756002 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11709 23:00:21.815986 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8172 ms)
11710 23:00:21.825616 [0:03:43.540810977] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11711 23:00:21.900393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11712 23:00:21.901094 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11714 23:00:21.913193 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11715 23:00:34.393697 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12579 ms)
11716 23:00:34.403490 [0:03:56.121028824] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11717 23:00:34.488703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11718 23:00:34.489407 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11720 23:00:34.502427 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11721 23:00:54.113013 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19721 ms)
11722 23:00:54.122654 [0:04:15.842116825] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11723 23:00:54.173399 [0:04:15.895779440] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11724 23:00:54.218501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11725 23:00:54.219328 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11727 23:00:54.228744 [0:04:15.951321748] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11728 23:00:54.235137 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11729 23:00:54.280983 [0:04:16.003521056] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11730 23:00:54.290534 Camera needs 4 requests, can't test only 1
11731 23:00:54.375325 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11732 23:00:54.453739
11733 23:00:54.545279 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (54 ms)
11734 23:00:54.640289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11735 23:00:54.640666 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11737 23:00:54.652496 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11738 23:00:54.703937 Camera needs 4 requests, can't test only 2
11739 23:00:54.787821 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11740 23:00:54.870345
11741 23:00:54.959208 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (56 ms)
11742 23:00:55.062916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11743 23:00:55.063761 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11745 23:00:55.074690 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11746 23:00:55.124938 Camera needs 4 requests, can't test only 3
11747 23:00:55.195049 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11748 23:00:55.255479
11749 23:00:55.327057 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (52 ms)
11750 23:00:55.415472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11751 23:00:55.416214 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11753 23:00:55.427968 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11754 23:00:56.352213 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2075 ms)
11755 23:00:56.362126 [0:04:18.079859517] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11756 23:00:56.459399 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11758 23:00:56.462546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11759 23:00:56.474773 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11760 23:00:59.060392 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2708 ms)
11761 23:00:59.070007 [0:04:20.790205056] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11762 23:00:59.161996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11763 23:00:59.162780 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11765 23:00:59.173174 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11766 23:01:02.819248 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3759 ms)
11767 23:01:02.828900 [0:04:24.549213748] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11768 23:01:02.916901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11769 23:01:02.917745 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11771 23:01:02.928269 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11772 23:01:08.256743 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5438 ms)
11773 23:01:08.266428 [0:04:29.987750441] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11774 23:01:08.360873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11775 23:01:08.361770 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11777 23:01:08.373170 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11778 23:01:16.428491 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8172 ms)
11779 23:01:16.438355 [0:04:38.159818595] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11780 23:01:16.520339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11781 23:01:16.521160 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11783 23:01:16.530466 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11784 23:01:29.007558 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12580 ms)
11785 23:01:29.017063 [0:04:50.740593673] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11786 23:01:29.105699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11787 23:01:29.106040 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11789 23:01:29.116817 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11790 23:01:48.726653 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19721 ms)
11791 23:01:48.736606 [0:05:10.462687059] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11792 23:01:48.815807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11793 23:01:48.816160 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11795 23:01:48.828107 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11796 23:01:49.140329 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (416 ms)
11797 23:01:49.153409 [0:05:10.877925982] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11798 23:01:49.233783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11799 23:01:49.234179 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11801 23:01:49.247802 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11802 23:01:49.628328 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (487 ms)
11803 23:01:49.641098 [0:05:11.365767828] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11804 23:01:49.723177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11805 23:01:49.723957 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11807 23:01:49.738440 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11808 23:01:50.184603 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (555 ms)
11809 23:01:50.196844 [0:05:11.921670751] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11810 23:01:50.280819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11811 23:01:50.281615 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11813 23:01:50.296740 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11814 23:01:50.880318 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (696 ms)
11815 23:01:50.893438 [0:05:12.617852597] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11816 23:01:50.974869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11817 23:01:50.975876 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11819 23:01:50.987859 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11820 23:01:51.786105 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (905 ms)
11821 23:01:51.795895 [0:05:13.523879751] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11822 23:01:51.879982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11823 23:01:51.880796 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11825 23:01:51.892984 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11826 23:01:53.041999 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1255 ms)
11827 23:01:53.055197 [0:05:14.779945059] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11828 23:01:53.128977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11829 23:01:53.129764 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11831 23:01:53.145116 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11832 23:01:54.857902 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1816 ms)
11833 23:01:54.870918 [0:05:16.596197213] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11834 23:01:54.965710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11835 23:01:54.966527 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11837 23:01:54.982992 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11838 23:01:57.583920 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2726 ms)
11839 23:01:57.597134 [0:05:19.323648982] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11840 23:01:57.672002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11841 23:01:57.672690 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11843 23:01:57.684526 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11844 23:02:01.780399 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4196 ms)
11845 23:02:01.793474 [0:05:23.520819367] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11846 23:02:01.878236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11847 23:02:01.879048 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11849 23:02:01.894082 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11850 23:02:08.356920 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6577 ms)
11851 23:02:08.370206 [0:05:30.097875983] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11852 23:02:08.459018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11853 23:02:08.459839 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11855 23:02:08.475297 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11856 23:02:08.775674 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (415 ms)
11857 23:02:08.785366 [0:05:30.512277829] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11858 23:02:08.875922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11859 23:02:08.876827 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11861 23:02:08.890289 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11862 23:02:09.262512 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (485 ms)
11863 23:02:09.272089 [0:05:30.998276368] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11864 23:02:09.352088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11865 23:02:09.353089 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11867 23:02:09.363598 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11868 23:02:09.817461 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (555 ms)
11869 23:02:09.827461 [0:05:31.554038752] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11870 23:02:09.910414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11871 23:02:09.911413 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11873 23:02:09.921047 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11874 23:02:10.513256 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (695 ms)
11875 23:02:10.522945 [0:05:32.250028060] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11876 23:02:10.603785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11877 23:02:10.604584 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11879 23:02:10.618194 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11880 23:02:11.420916 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (907 ms)
11881 23:02:11.430484 [0:05:33.157442291] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11882 23:02:11.525624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11883 23:02:11.526502 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11885 23:02:11.536782 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11886 23:02:12.676629 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1255 ms)
11887 23:02:12.686147 [0:05:34.413213522] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11888 23:02:12.771903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11889 23:02:12.772749 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11891 23:02:12.783812 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11892 23:02:14.492264 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1815 ms)
11893 23:02:14.501667 [0:05:36.228823830] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11894 23:02:14.587525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11895 23:02:14.588361 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11897 23:02:14.600238 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11898 23:02:17.219237 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2727 ms)
11899 23:02:17.228812 [0:05:38.958354907] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11900 23:02:17.322206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11901 23:02:17.323078 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11903 23:02:17.336719 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11904 23:02:21.416089 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4197 ms)
11905 23:02:21.425781 [0:05:43.155683368] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11906 23:02:21.518374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11907 23:02:21.519242 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11909 23:02:21.531469 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11910 23:02:27.993082 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6577 ms)
11911 23:02:28.003210 [0:05:49.733411600] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11912 23:02:28.082312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11913 23:02:28.083196 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11915 23:02:28.095693 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11916 23:02:28.409695 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (416 ms)
11917 23:02:28.418918 [0:05:50.148264369] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11918 23:02:28.497582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11919 23:02:28.498453 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11921 23:02:28.512100 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11922 23:02:28.895655 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (486 ms)
11923 23:02:28.905538 [0:05:50.634345907] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11924 23:02:28.994897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11925 23:02:28.995715 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11927 23:02:29.007393 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11928 23:02:29.451285 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (555 ms)
11929 23:02:29.461019 [0:05:51.190159061] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11930 23:02:29.541630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11931 23:02:29.542383 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11933 23:02:29.553609 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11934 23:02:30.146850 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (695 ms)
11935 23:02:30.156579 [0:05:51.885754292] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11936 23:02:30.252739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11937 23:02:30.253728 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11939 23:02:30.267386 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11940 23:02:31.054484 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (907 ms)
11941 23:02:31.064153 [0:05:52.793360831] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11942 23:02:31.152309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11943 23:02:31.153169 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11945 23:02:31.162627 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11946 23:02:32.309679 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1255 ms)
11947 23:02:32.319731 [0:05:54.048911984] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11948 23:02:32.405112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11949 23:02:32.405909 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11951 23:02:32.418930 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11952 23:02:34.125029 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1815 ms)
11953 23:02:34.135685 [0:05:55.864804215] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11954 23:02:34.217453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11955 23:02:34.217781 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11957 23:02:34.226768 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11958 23:02:36.851336 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2726 ms)
11959 23:02:36.861216 [0:05:58.592478369] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11960 23:02:36.953293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11961 23:02:36.954014 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11963 23:02:36.966650 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11964 23:02:41.048157 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4197 ms)
11965 23:02:41.057784 [0:06:02.789871985] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11966 23:02:41.147582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11967 23:02:41.148385 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11969 23:02:41.160606 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11970 23:02:47.624790 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6577 ms)
11971 23:02:47.634606 [0:06:09.367545524] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11972 23:02:47.719463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11973 23:02:47.720286 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11975 23:02:47.735086 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11976 23:02:48.041782 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (416 ms)
11977 23:02:48.051638 [0:06:09.782820447] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11978 23:02:48.141629 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11980 23:02:48.143941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11981 23:02:48.158358 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11982 23:02:48.527897 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (485 ms)
11983 23:02:48.537657 [0:06:10.268854293] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11984 23:02:48.615847 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11986 23:02:48.618938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11987 23:02:48.634472 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11988 23:02:49.083278 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (555 ms)
11989 23:02:49.093124 [0:06:10.824672139] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11990 23:02:49.177988 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11992 23:02:49.180656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11993 23:02:49.193953 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11994 23:02:49.779194 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (695 ms)
11995 23:02:49.788789 [0:06:11.520464293] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11996 23:02:49.868928 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11998 23:02:49.871477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11999 23:02:49.883527 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
12000 23:02:50.685473 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (906 ms)
12001 23:02:50.695194 [0:06:12.426650293] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12002 23:02:50.781292 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
12004 23:02:50.784470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
12005 23:02:50.796963 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
12006 23:02:51.940877 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1255 ms)
12007 23:02:51.951003 [0:06:13.682649601] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12008 23:02:52.029224 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
12010 23:02:52.032352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
12011 23:02:52.044592 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
12012 23:02:53.756917 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1815 ms)
12013 23:02:53.766629 [0:06:15.498360370] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12014 23:02:53.857234 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
12016 23:02:53.859807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
12017 23:02:53.874199 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
12018 23:02:56.482928 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2726 ms)
12019 23:02:56.492652 [0:06:18.226741217] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12020 23:02:56.581542 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
12022 23:02:56.584659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
12023 23:02:56.598130 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
12024 23:03:00.680020 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4197 ms)
12025 23:03:00.689427 [0:06:22.424144678] [416] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12026 23:03:00.768266 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
12028 23:03:00.771208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
12029 23:03:00.784752 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
12030 23:03:07.257871 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6578 ms)
12031 23:03:07.342969 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
12033 23:03:07.345911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
12034 23:03:07.358209 [----------] 120 tests from CaptureTests/SingleStream (369834 ms total)
12035 23:03:07.428667
12036 23:03:07.501407 [----------] Global test environment tear-down
12037 23:03:07.572561 [==========] 120 tests from 1 test suite ran. (369834 ms total)
12038 23:03:07.645685 <LAVA_SIGNAL_TESTSET STOP>
12039 23:03:07.646371 Received signal: <TESTSET> STOP
12040 23:03:07.646724 Closing test_set CaptureTests/SingleStream
12041 23:03:07.649701 + set +x
12042 23:03:07.652380 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 13683739_1.6.2.3.1>
12043 23:03:07.653049 Received signal: <ENDRUN> 0_lc-compliance 13683739_1.6.2.3.1
12044 23:03:07.653487 Ending use of test pattern.
12045 23:03:07.653813 Ending test lava.0_lc-compliance (13683739_1.6.2.3.1), duration 371.92
12047 23:03:07.655490 <LAVA_TEST_RUNNER EXIT>
12048 23:03:07.656153 ok: lava_test_shell seems to have completed
12049 23:03:07.665671 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
12050 23:03:07.666644 end: 3.1 lava-test-shell (duration 00:06:13) [common]
12051 23:03:07.667095 end: 3 lava-test-retry (duration 00:06:13) [common]
12052 23:03:07.667523 start: 4 finalize (timeout 00:10:00) [common]
12053 23:03:07.667968 start: 4.1 power-off (timeout 00:00:30) [common]
12054 23:03:07.668689 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
12055 23:03:07.928498 >> Command sent successfully.
12056 23:03:07.939200 Returned 0 in 0 seconds
12057 23:03:08.040666 end: 4.1 power-off (duration 00:00:00) [common]
12059 23:03:08.042242 start: 4.2 read-feedback (timeout 00:10:00) [common]
12060 23:03:08.043518 Listened to connection for namespace 'common' for up to 1s
12061 23:03:09.044284 Finalising connection for namespace 'common'
12062 23:03:09.044995 Disconnecting from shell: Finalise
12063 23:03:09.045468 / #
12064 23:03:09.146672 end: 4.2 read-feedback (duration 00:00:01) [common]
12065 23:03:09.147458 end: 4 finalize (duration 00:00:01) [common]
12066 23:03:09.148099 Cleaning after the job
12067 23:03:09.148634 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/ramdisk
12068 23:03:09.153176 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/kernel
12069 23:03:09.163345 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/dtb
12070 23:03:09.163578 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/nfsrootfs
12071 23:03:09.202478 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683739/tftp-deploy-o0ljxgg6/modules
12072 23:03:09.208011 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683739
12073 23:03:09.448491 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683739
12074 23:03:09.448680 Job finished correctly