Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 21
- Errors: 2
- Kernel Errors: 26
- Boot result: PASS
1 22:48:37.223842 lava-dispatcher, installed at version: 2024.01
2 22:48:37.224048 start: 0 validate
3 22:48:37.224173 Start time: 2024-05-07 22:48:37.224166+00:00 (UTC)
4 22:48:37.224299 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:48:37.224427 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 22:48:37.483017 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:48:37.483740 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:48:37.746830 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:48:37.747568 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:49:20.879358 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:49:20.880266 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:49:21.411041 validate duration: 44.19
14 22:49:21.412305 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:49:21.412867 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:49:21.413352 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:49:21.413946 Not decompressing ramdisk as can be used compressed.
18 22:49:21.414480 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 22:49:21.414836 saving as /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/ramdisk/rootfs.cpio.gz
20 22:49:21.415182 total size: 28105535 (26 MB)
21 22:49:32.721820 progress 0 % (0 MB)
22 22:49:32.732244 progress 5 % (1 MB)
23 22:49:32.739204 progress 10 % (2 MB)
24 22:49:32.746161 progress 15 % (4 MB)
25 22:49:32.753121 progress 20 % (5 MB)
26 22:49:32.760097 progress 25 % (6 MB)
27 22:49:32.767137 progress 30 % (8 MB)
28 22:49:32.774255 progress 35 % (9 MB)
29 22:49:32.781432 progress 40 % (10 MB)
30 22:49:32.788625 progress 45 % (12 MB)
31 22:49:32.795700 progress 50 % (13 MB)
32 22:49:32.802763 progress 55 % (14 MB)
33 22:49:32.809829 progress 60 % (16 MB)
34 22:49:32.816954 progress 65 % (17 MB)
35 22:49:32.823941 progress 70 % (18 MB)
36 22:49:32.830885 progress 75 % (20 MB)
37 22:49:32.837961 progress 80 % (21 MB)
38 22:49:32.845101 progress 85 % (22 MB)
39 22:49:32.852057 progress 90 % (24 MB)
40 22:49:32.859028 progress 95 % (25 MB)
41 22:49:32.865881 progress 100 % (26 MB)
42 22:49:32.866119 26 MB downloaded in 11.45 s (2.34 MB/s)
43 22:49:32.866293 end: 1.1.1 http-download (duration 00:00:11) [common]
45 22:49:32.866554 end: 1.1 download-retry (duration 00:00:11) [common]
46 22:49:32.866655 start: 1.2 download-retry (timeout 00:09:49) [common]
47 22:49:32.866753 start: 1.2.1 http-download (timeout 00:09:49) [common]
48 22:49:32.866901 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:49:32.866974 saving as /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/kernel/Image
50 22:49:32.867069 total size: 54682112 (52 MB)
51 22:49:32.867167 No compression specified
52 22:49:33.126163 progress 0 % (0 MB)
53 22:49:33.173160 progress 5 % (2 MB)
54 22:49:33.191326 progress 10 % (5 MB)
55 22:49:33.205409 progress 15 % (7 MB)
56 22:49:33.219576 progress 20 % (10 MB)
57 22:49:33.233497 progress 25 % (13 MB)
58 22:49:33.247390 progress 30 % (15 MB)
59 22:49:33.261425 progress 35 % (18 MB)
60 22:49:33.274919 progress 40 % (20 MB)
61 22:49:33.288919 progress 45 % (23 MB)
62 22:49:33.302827 progress 50 % (26 MB)
63 22:49:33.316633 progress 55 % (28 MB)
64 22:49:33.330702 progress 60 % (31 MB)
65 22:49:33.344329 progress 65 % (33 MB)
66 22:49:33.358158 progress 70 % (36 MB)
67 22:49:33.371829 progress 75 % (39 MB)
68 22:49:33.385919 progress 80 % (41 MB)
69 22:49:33.399855 progress 85 % (44 MB)
70 22:49:33.413887 progress 90 % (46 MB)
71 22:49:33.427568 progress 95 % (49 MB)
72 22:49:33.441108 progress 100 % (52 MB)
73 22:49:33.441362 52 MB downloaded in 0.57 s (90.81 MB/s)
74 22:49:33.441533 end: 1.2.1 http-download (duration 00:00:01) [common]
76 22:49:33.441787 end: 1.2 download-retry (duration 00:00:01) [common]
77 22:49:33.441889 start: 1.3 download-retry (timeout 00:09:48) [common]
78 22:49:33.442013 start: 1.3.1 http-download (timeout 00:09:48) [common]
79 22:49:33.442178 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:49:33.442275 saving as /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/dtb/mt8192-asurada-spherion-r0.dtb
81 22:49:33.442373 total size: 47258 (0 MB)
82 22:49:33.442471 No compression specified
83 22:49:33.693507 progress 69 % (0 MB)
84 22:49:33.695192 progress 100 % (0 MB)
85 22:49:33.696141 0 MB downloaded in 0.25 s (0.18 MB/s)
86 22:49:33.696956 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:49:33.698433 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:49:33.699013 start: 1.4 download-retry (timeout 00:09:48) [common]
90 22:49:33.699573 start: 1.4.1 http-download (timeout 00:09:48) [common]
91 22:49:33.700314 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:49:33.700730 saving as /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/modules/modules.tar
93 22:49:33.701200 total size: 8594396 (8 MB)
94 22:49:33.701651 Using unxz to decompress xz
95 22:49:33.713990 progress 0 % (0 MB)
96 22:49:33.732763 progress 5 % (0 MB)
97 22:49:33.756752 progress 10 % (0 MB)
98 22:49:33.779851 progress 15 % (1 MB)
99 22:49:33.802751 progress 20 % (1 MB)
100 22:49:33.826791 progress 25 % (2 MB)
101 22:49:33.849804 progress 30 % (2 MB)
102 22:49:33.873070 progress 35 % (2 MB)
103 22:49:33.897651 progress 40 % (3 MB)
104 22:49:33.922754 progress 45 % (3 MB)
105 22:49:33.946899 progress 50 % (4 MB)
106 22:49:33.970814 progress 55 % (4 MB)
107 22:49:33.996357 progress 60 % (4 MB)
108 22:49:34.021053 progress 65 % (5 MB)
109 22:49:34.045337 progress 70 % (5 MB)
110 22:49:34.068993 progress 75 % (6 MB)
111 22:49:34.094088 progress 80 % (6 MB)
112 22:49:34.119827 progress 85 % (6 MB)
113 22:49:34.148770 progress 90 % (7 MB)
114 22:49:34.178287 progress 95 % (7 MB)
115 22:49:34.204717 progress 100 % (8 MB)
116 22:49:34.209839 8 MB downloaded in 0.51 s (16.11 MB/s)
117 22:49:34.210113 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:49:34.210429 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:49:34.210522 start: 1.5 prepare-tftp-overlay (timeout 00:09:47) [common]
121 22:49:34.210615 start: 1.5.1 extract-nfsrootfs (timeout 00:09:47) [common]
122 22:49:34.210695 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:49:34.210779 start: 1.5.2 lava-overlay (timeout 00:09:47) [common]
124 22:49:34.210994 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_
125 22:49:34.211124 makedir: /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin
126 22:49:34.211223 makedir: /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/tests
127 22:49:34.211319 makedir: /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/results
128 22:49:34.211431 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-add-keys
129 22:49:34.211572 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-add-sources
130 22:49:34.211698 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-background-process-start
131 22:49:34.211888 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-background-process-stop
132 22:49:34.212058 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-common-functions
133 22:49:34.212224 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-echo-ipv4
134 22:49:34.212433 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-install-packages
135 22:49:34.212556 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-installed-packages
136 22:49:34.212677 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-os-build
137 22:49:34.212797 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-probe-channel
138 22:49:34.212918 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-probe-ip
139 22:49:34.213040 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-target-ip
140 22:49:34.213158 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-target-mac
141 22:49:34.213277 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-target-storage
142 22:49:34.213399 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-test-case
143 22:49:34.213519 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-test-event
144 22:49:34.213637 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-test-feedback
145 22:49:34.213756 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-test-raise
146 22:49:34.213876 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-test-reference
147 22:49:34.213994 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-test-runner
148 22:49:34.214163 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-test-set
149 22:49:34.214291 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-test-shell
150 22:49:34.214416 Updating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-install-packages (oe)
151 22:49:34.214565 Updating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/bin/lava-installed-packages (oe)
152 22:49:34.214684 Creating /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/environment
153 22:49:34.214781 LAVA metadata
154 22:49:34.214856 - LAVA_JOB_ID=13683663
155 22:49:34.214918 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:49:34.215018 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:47) [common]
157 22:49:34.215083 skipped lava-vland-overlay
158 22:49:34.215154 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:49:34.215234 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
160 22:49:34.215294 skipped lava-multinode-overlay
161 22:49:34.215365 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:49:34.215454 start: 1.5.2.3 test-definition (timeout 00:09:47) [common]
163 22:49:34.215528 Loading test definitions
164 22:49:34.215614 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:47) [common]
165 22:49:34.215685 Using /lava-13683663 at stage 0
166 22:49:34.215978 uuid=13683663_1.5.2.3.1 testdef=None
167 22:49:34.216063 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:49:34.216148 start: 1.5.2.3.2 test-overlay (timeout 00:09:47) [common]
169 22:49:34.216652 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:49:34.216871 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:47) [common]
172 22:49:34.217463 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:49:34.217703 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
175 22:49:34.218843 runner path: /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 13683663_1.5.2.3.1
176 22:49:34.219001 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:49:34.219203 Creating lava-test-runner.conf files
179 22:49:34.219264 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683663/lava-overlay-3pw_rml_/lava-13683663/0 for stage 0
180 22:49:34.219350 - 0_v4l2-compliance-mtk-vcodec-enc
181 22:49:34.219445 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:49:34.219526 start: 1.5.2.4 compress-overlay (timeout 00:09:47) [common]
183 22:49:34.226758 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:49:34.226865 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:47) [common]
185 22:49:34.226951 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:49:34.227034 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:49:34.227117 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:47) [common]
188 22:49:35.103237 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:49:35.103620 start: 1.5.4 extract-modules (timeout 00:09:46) [common]
190 22:49:35.103731 extracting modules file /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683663/extract-overlay-ramdisk-vxfl9e6l/ramdisk
191 22:49:35.320927 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:49:35.321103 start: 1.5.5 apply-overlay-tftp (timeout 00:09:46) [common]
193 22:49:35.321200 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683663/compress-overlay-y63sj4b1/overlay-1.5.2.4.tar.gz to ramdisk
194 22:49:35.321272 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683663/compress-overlay-y63sj4b1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683663/extract-overlay-ramdisk-vxfl9e6l/ramdisk
195 22:49:35.327931 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:49:35.328053 start: 1.5.6 configure-preseed-file (timeout 00:09:46) [common]
197 22:49:35.328147 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:49:35.328241 start: 1.5.7 compress-ramdisk (timeout 00:09:46) [common]
199 22:49:35.328322 Building ramdisk /var/lib/lava/dispatcher/tmp/13683663/extract-overlay-ramdisk-vxfl9e6l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683663/extract-overlay-ramdisk-vxfl9e6l/ramdisk
200 22:49:36.070934 >> 275874 blocks
201 22:49:40.112111 rename /var/lib/lava/dispatcher/tmp/13683663/extract-overlay-ramdisk-vxfl9e6l/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/ramdisk/ramdisk.cpio.gz
202 22:49:40.112565 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:49:40.112685 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
204 22:49:40.112782 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
205 22:49:40.112887 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/kernel/Image'
206 22:49:53.176159 Returned 0 in 13 seconds
207 22:49:53.276773 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/kernel/image.itb
208 22:49:53.914939 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:49:53.915322 output: Created: Tue May 7 23:49:53 2024
210 22:49:53.915397 output: Image 0 (kernel-1)
211 22:49:53.915462 output: Description:
212 22:49:53.915523 output: Created: Tue May 7 23:49:53 2024
213 22:49:53.915586 output: Type: Kernel Image
214 22:49:53.915647 output: Compression: lzma compressed
215 22:49:53.915706 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
216 22:49:53.915764 output: Architecture: AArch64
217 22:49:53.915824 output: OS: Linux
218 22:49:53.915880 output: Load Address: 0x00000000
219 22:49:53.915933 output: Entry Point: 0x00000000
220 22:49:53.915987 output: Hash algo: crc32
221 22:49:53.916044 output: Hash value: 727ee7c6
222 22:49:53.916098 output: Image 1 (fdt-1)
223 22:49:53.916153 output: Description: mt8192-asurada-spherion-r0
224 22:49:53.916210 output: Created: Tue May 7 23:49:53 2024
225 22:49:53.916262 output: Type: Flat Device Tree
226 22:49:53.916315 output: Compression: uncompressed
227 22:49:53.916367 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 22:49:53.916419 output: Architecture: AArch64
229 22:49:53.916470 output: Hash algo: crc32
230 22:49:53.916522 output: Hash value: 0f8e4d2e
231 22:49:53.916574 output: Image 2 (ramdisk-1)
232 22:49:53.916625 output: Description: unavailable
233 22:49:53.916676 output: Created: Tue May 7 23:49:53 2024
234 22:49:53.916727 output: Type: RAMDisk Image
235 22:49:53.916778 output: Compression: Unknown Compression
236 22:49:53.916830 output: Data Size: 41212176 Bytes = 40246.27 KiB = 39.30 MiB
237 22:49:53.916881 output: Architecture: AArch64
238 22:49:53.916932 output: OS: Linux
239 22:49:53.916984 output: Load Address: unavailable
240 22:49:53.917035 output: Entry Point: unavailable
241 22:49:53.917086 output: Hash algo: crc32
242 22:49:53.917137 output: Hash value: b824d118
243 22:49:53.917188 output: Default Configuration: 'conf-1'
244 22:49:53.917239 output: Configuration 0 (conf-1)
245 22:49:53.917290 output: Description: mt8192-asurada-spherion-r0
246 22:49:53.917342 output: Kernel: kernel-1
247 22:49:53.917393 output: Init Ramdisk: ramdisk-1
248 22:49:53.917445 output: FDT: fdt-1
249 22:49:53.917495 output: Loadables: kernel-1
250 22:49:53.917546 output:
251 22:49:53.917748 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 22:49:53.917845 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 22:49:53.917944 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 22:49:53.918067 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
255 22:49:53.918166 No LXC device requested
256 22:49:53.918246 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:49:53.918333 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
258 22:49:53.918412 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:49:53.918488 Checking files for TFTP limit of 4294967296 bytes.
260 22:49:53.918986 end: 1 tftp-deploy (duration 00:00:33) [common]
261 22:49:53.919089 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:49:53.919179 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:49:53.919305 substitutions:
264 22:49:53.919371 - {DTB}: 13683663/tftp-deploy-80lgk2y2/dtb/mt8192-asurada-spherion-r0.dtb
265 22:49:53.919434 - {INITRD}: 13683663/tftp-deploy-80lgk2y2/ramdisk/ramdisk.cpio.gz
266 22:49:53.919492 - {KERNEL}: 13683663/tftp-deploy-80lgk2y2/kernel/Image
267 22:49:53.919549 - {LAVA_MAC}: None
268 22:49:53.919606 - {PRESEED_CONFIG}: None
269 22:49:53.919660 - {PRESEED_LOCAL}: None
270 22:49:53.919715 - {RAMDISK}: 13683663/tftp-deploy-80lgk2y2/ramdisk/ramdisk.cpio.gz
271 22:49:53.919770 - {ROOT_PART}: None
272 22:49:53.919823 - {ROOT}: None
273 22:49:53.919876 - {SERVER_IP}: 192.168.201.1
274 22:49:53.919929 - {TEE}: None
275 22:49:53.919982 Parsed boot commands:
276 22:49:53.920035 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:49:53.920257 Parsed boot commands: tftpboot 192.168.201.1 13683663/tftp-deploy-80lgk2y2/kernel/image.itb 13683663/tftp-deploy-80lgk2y2/kernel/cmdline
278 22:49:53.920347 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:49:53.920432 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:49:53.920538 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:49:53.920625 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:49:53.920696 Not connected, no need to disconnect.
283 22:49:53.920769 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:49:53.920850 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:49:53.920919 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 22:49:53.924741 Setting prompt string to ['lava-test: # ']
287 22:49:53.925094 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:49:53.925201 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:49:53.925299 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:49:53.925406 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:49:53.925618 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 22:49:59.059520 >> Command sent successfully.
293 22:49:59.061898 Returned 0 in 5 seconds
294 22:49:59.162306 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:49:59.162638 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:49:59.162736 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:49:59.162825 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:49:59.162890 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:49:59.162957 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:49:59.163220 [Enter `^Ec?' for help]
302 22:49:59.341876
303 22:49:59.342112
304 22:49:59.342189 F0: 102B 0000
305 22:49:59.342254
306 22:49:59.342315 F3: 1001 0000 [0200]
307 22:49:59.342376
308 22:49:59.345531 F3: 1001 0000
309 22:49:59.345619
310 22:49:59.345685 F7: 102D 0000
311 22:49:59.345746
312 22:49:59.345806 F1: 0000 0000
313 22:49:59.345864
314 22:49:59.348907 V0: 0000 0000 [0001]
315 22:49:59.348996
316 22:49:59.349061 00: 0007 8000
317 22:49:59.349124
318 22:49:59.352459 01: 0000 0000
319 22:49:59.352555
320 22:49:59.352621 BP: 0C00 0209 [0000]
321 22:49:59.352682
322 22:49:59.356588 G0: 1182 0000
323 22:49:59.356677
324 22:49:59.356746 EC: 0000 0021 [4000]
325 22:49:59.356808
326 22:49:59.360321 S7: 0000 0000 [0000]
327 22:49:59.360411
328 22:49:59.360477 CC: 0000 0000 [0001]
329 22:49:59.360538
330 22:49:59.363896 T0: 0000 0040 [010F]
331 22:49:59.363984
332 22:49:59.364050 Jump to BL
333 22:49:59.364110
334 22:49:59.388466
335 22:49:59.388623
336 22:49:59.388691
337 22:49:59.395628 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:49:59.399313 ARM64: Exception handlers installed.
339 22:49:59.402938 ARM64: Testing exception
340 22:49:59.406675 ARM64: Done test exception
341 22:49:59.413939 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:49:59.421066 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:49:59.428333 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:49:59.438950 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:49:59.445933 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:49:59.456123 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:49:59.466689 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:49:59.473364 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:49:59.491221 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:49:59.494361 WDT: Last reset was cold boot
351 22:49:59.497753 SPI1(PAD0) initialized at 2873684 Hz
352 22:49:59.500999 SPI5(PAD0) initialized at 992727 Hz
353 22:49:59.504546 VBOOT: Loading verstage.
354 22:49:59.511177 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:49:59.514498 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:49:59.517539 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:49:59.520876 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:49:59.528623 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:49:59.535317 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:49:59.546168 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 22:49:59.546333
362 22:49:59.546428
363 22:49:59.556148 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:49:59.559810 ARM64: Exception handlers installed.
365 22:49:59.563142 ARM64: Testing exception
366 22:49:59.563234 ARM64: Done test exception
367 22:49:59.569953 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:49:59.573015 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:49:59.587213 Probing TPM: . done!
370 22:49:59.587364 TPM ready after 0 ms
371 22:49:59.594330 Connected to device vid:did:rid of 1ae0:0028:00
372 22:49:59.601235 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 22:49:59.652068 Initialized TPM device CR50 revision 0
374 22:49:59.655371 tlcl_send_startup: Startup return code is 0
375 22:49:59.664665 TPM: setup succeeded
376 22:49:59.675190 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:49:59.684814 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:49:59.693984 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:49:59.702846 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:49:59.706018 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:49:59.709479 in-header: 03 07 00 00 08 00 00 00
382 22:49:59.712766 in-data: aa e4 47 04 13 02 00 00
383 22:49:59.716197 Chrome EC: UHEPI supported
384 22:49:59.723207 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:49:59.726481 in-header: 03 95 00 00 08 00 00 00
386 22:49:59.730033 in-data: 18 20 20 08 00 00 00 00
387 22:49:59.730190 Phase 1
388 22:49:59.733516 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:49:59.740736 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:49:59.744535 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:49:59.748168 Recovery requested (1009000e)
392 22:49:59.757477 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:49:59.763102 tlcl_extend: response is 0
394 22:49:59.772342 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:49:59.778176 tlcl_extend: response is 0
396 22:49:59.784807 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:49:59.805838 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:49:59.813144 BS: bootblock times (exec / console): total (unknown) / 149 ms
399 22:49:59.813271
400 22:49:59.813339
401 22:49:59.820374 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:49:59.824073 ARM64: Exception handlers installed.
403 22:49:59.827594 ARM64: Testing exception
404 22:49:59.831051 ARM64: Done test exception
405 22:49:59.850423 pmic_efuse_setting: Set efuses in 11 msecs
406 22:49:59.853813 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:49:59.860638 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:49:59.863834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:49:59.870625 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:49:59.873730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:49:59.880341 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:49:59.883588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:49:59.890167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:49:59.893643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:49:59.897063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:49:59.903483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:49:59.906965 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:49:59.913600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:49:59.916846 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:49:59.923510 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:49:59.927462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:49:59.934551 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:49:59.938251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:49:59.945433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:49:59.953063 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:49:59.956418 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:49:59.963961 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:49:59.967305 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:49:59.974757 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:49:59.978153 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:49:59.985577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:49:59.989030 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:49:59.996557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:50:00.000370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:50:00.003687 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:50:00.010955 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:50:00.014942 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:50:00.018679 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:50:00.026434 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:50:00.029633 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:50:00.033125 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:50:00.040248 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:50:00.044082 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:50:00.051457 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:50:00.055326 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:50:00.058451 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:50:00.061947 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:50:00.065614 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:50:00.072798 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:50:00.076612 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:50:00.080156 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:50:00.083710 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:50:00.087315 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:50:00.094235 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:50:00.098019 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:50:00.101656 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:50:00.105305 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:50:00.112537 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:50:00.123511 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:50:00.126997 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:50:00.134335 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:50:00.141657 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:50:00.149146 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:50:00.152529 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:50:00.155814 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:50:00.163940 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 22:50:00.170984 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:50:00.174647 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 22:50:00.177960 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:50:00.188092 [RTC]rtc_get_frequency_meter,154: input=15, output=765
471 22:50:00.198129 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 22:50:00.206885 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 22:50:00.216352 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 22:50:00.226260 [RTC]rtc_get_frequency_meter,154: input=16, output=786
475 22:50:00.235847 [RTC]rtc_get_frequency_meter,154: input=16, output=788
476 22:50:00.245511 [RTC]rtc_get_frequency_meter,154: input=17, output=811
477 22:50:00.249037 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 22:50:00.256516 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 22:50:00.259799 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:50:00.263377 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:50:00.266953 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:50:00.270852 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:50:00.274560 ADC[4]: Raw value=670432 ID=5
484 22:50:00.277917 ADC[3]: Raw value=212549 ID=1
485 22:50:00.278010 RAM Code: 0x51
486 22:50:00.281563 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:50:00.288750 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:50:00.295701 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 22:50:00.302902 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 22:50:00.306692 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:50:00.310171 in-header: 03 07 00 00 08 00 00 00
492 22:50:00.314151 in-data: aa e4 47 04 13 02 00 00
493 22:50:00.314247 Chrome EC: UHEPI supported
494 22:50:00.321352 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:50:00.324627 in-header: 03 95 00 00 08 00 00 00
496 22:50:00.328205 in-data: 18 20 20 08 00 00 00 00
497 22:50:00.331914 MRC: failed to locate region type 0.
498 22:50:00.339112 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:50:00.339245 DRAM-K: Running full calibration
500 22:50:00.346447 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 22:50:00.350077 header.status = 0x0
502 22:50:00.350195 header.version = 0x6 (expected: 0x6)
503 22:50:00.354141 header.size = 0xd00 (expected: 0xd00)
504 22:50:00.357438 header.flags = 0x0
505 22:50:00.361202 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:50:00.380678 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 22:50:00.387949 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:50:00.391640 dram_init: ddr_geometry: 0
509 22:50:00.391757 [EMI] MDL number = 0
510 22:50:00.395169 [EMI] Get MDL freq = 0
511 22:50:00.395259 dram_init: ddr_type: 0
512 22:50:00.399039 is_discrete_lpddr4: 1
513 22:50:00.403051 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:50:00.403146
515 22:50:00.403214
516 22:50:00.403275 [Bian_co] ETT version 0.0.0.1
517 22:50:00.410571 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 22:50:00.410686
519 22:50:00.414017 dramc_set_vcore_voltage set vcore to 650000
520 22:50:00.414149 Read voltage for 800, 4
521 22:50:00.417810 Vio18 = 0
522 22:50:00.417901 Vcore = 650000
523 22:50:00.417966 Vdram = 0
524 22:50:00.418037 Vddq = 0
525 22:50:00.421437 Vmddr = 0
526 22:50:00.421524 dram_init: config_dvfs: 1
527 22:50:00.428714 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:50:00.432373 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:50:00.436245 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 22:50:00.439932 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 22:50:00.443769 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 22:50:00.447215 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 22:50:00.451307 MEM_TYPE=3, freq_sel=18
534 22:50:00.454800 sv_algorithm_assistance_LP4_1600
535 22:50:00.458288 ============ PULL DRAM RESETB DOWN ============
536 22:50:00.462248 ========== PULL DRAM RESETB DOWN end =========
537 22:50:00.465702 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:50:00.469615 ===================================
539 22:50:00.473156 LPDDR4 DRAM CONFIGURATION
540 22:50:00.476799 ===================================
541 22:50:00.476901 EX_ROW_EN[0] = 0x0
542 22:50:00.480656 EX_ROW_EN[1] = 0x0
543 22:50:00.480745 LP4Y_EN = 0x0
544 22:50:00.483906 WORK_FSP = 0x0
545 22:50:00.483995 WL = 0x2
546 22:50:00.487645 RL = 0x2
547 22:50:00.487740 BL = 0x2
548 22:50:00.491251 RPST = 0x0
549 22:50:00.491339 RD_PRE = 0x0
550 22:50:00.494814 WR_PRE = 0x1
551 22:50:00.494901 WR_PST = 0x0
552 22:50:00.494968 DBI_WR = 0x0
553 22:50:00.498480 DBI_RD = 0x0
554 22:50:00.498568 OTF = 0x1
555 22:50:00.501982 ===================================
556 22:50:00.505529 ===================================
557 22:50:00.509483 ANA top config
558 22:50:00.513251 ===================================
559 22:50:00.513336 DLL_ASYNC_EN = 0
560 22:50:00.516835 ALL_SLAVE_EN = 1
561 22:50:00.520342 NEW_RANK_MODE = 1
562 22:50:00.520436 DLL_IDLE_MODE = 1
563 22:50:00.523805 LP45_APHY_COMB_EN = 1
564 22:50:00.527231 TX_ODT_DIS = 1
565 22:50:00.530252 NEW_8X_MODE = 1
566 22:50:00.533547 ===================================
567 22:50:00.537190 ===================================
568 22:50:00.540690 data_rate = 1600
569 22:50:00.540786 CKR = 1
570 22:50:00.544511 DQ_P2S_RATIO = 8
571 22:50:00.548255 ===================================
572 22:50:00.551652 CA_P2S_RATIO = 8
573 22:50:00.551748 DQ_CA_OPEN = 0
574 22:50:00.555512 DQ_SEMI_OPEN = 0
575 22:50:00.559321 CA_SEMI_OPEN = 0
576 22:50:00.562670 CA_FULL_RATE = 0
577 22:50:00.562765 DQ_CKDIV4_EN = 1
578 22:50:00.565928 CA_CKDIV4_EN = 1
579 22:50:00.569235 CA_PREDIV_EN = 0
580 22:50:00.572566 PH8_DLY = 0
581 22:50:00.576483 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:50:00.580130 DQ_AAMCK_DIV = 4
583 22:50:00.580225 CA_AAMCK_DIV = 4
584 22:50:00.583594 CA_ADMCK_DIV = 4
585 22:50:00.586955 DQ_TRACK_CA_EN = 0
586 22:50:00.590725 CA_PICK = 800
587 22:50:00.590826 CA_MCKIO = 800
588 22:50:00.594406 MCKIO_SEMI = 0
589 22:50:00.597920 PLL_FREQ = 3068
590 22:50:00.601173 DQ_UI_PI_RATIO = 32
591 22:50:00.604285 CA_UI_PI_RATIO = 0
592 22:50:00.607613 ===================================
593 22:50:00.611621 ===================================
594 22:50:00.611717 memory_type:LPDDR4
595 22:50:00.614994 GP_NUM : 10
596 22:50:00.615085 SRAM_EN : 1
597 22:50:00.618967 MD32_EN : 0
598 22:50:00.622407 ===================================
599 22:50:00.626416 [ANA_INIT] >>>>>>>>>>>>>>
600 22:50:00.626519 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:50:00.629903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:50:00.633650 ===================================
603 22:50:00.637247 data_rate = 1600,PCW = 0X7600
604 22:50:00.641201 ===================================
605 22:50:00.644898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:50:00.647924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:50:00.654860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:50:00.658039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:50:00.661471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:50:00.664716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:50:00.668371 [ANA_INIT] flow start
612 22:50:00.671571 [ANA_INIT] PLL >>>>>>>>
613 22:50:00.671665 [ANA_INIT] PLL <<<<<<<<
614 22:50:00.674719 [ANA_INIT] MIDPI >>>>>>>>
615 22:50:00.677978 [ANA_INIT] MIDPI <<<<<<<<
616 22:50:00.678122 [ANA_INIT] DLL >>>>>>>>
617 22:50:00.681583 [ANA_INIT] flow end
618 22:50:00.684664 ============ LP4 DIFF to SE enter ============
619 22:50:00.687931 ============ LP4 DIFF to SE exit ============
620 22:50:00.691761 [ANA_INIT] <<<<<<<<<<<<<
621 22:50:00.694720 [Flow] Enable top DCM control >>>>>
622 22:50:00.698049 [Flow] Enable top DCM control <<<<<
623 22:50:00.701395 Enable DLL master slave shuffle
624 22:50:00.708132 ==============================================================
625 22:50:00.708249 Gating Mode config
626 22:50:00.714683 ==============================================================
627 22:50:00.714792 Config description:
628 22:50:00.724649 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:50:00.731615 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:50:00.738005 SELPH_MODE 0: By rank 1: By Phase
631 22:50:00.741301 ==============================================================
632 22:50:00.744691 GAT_TRACK_EN = 1
633 22:50:00.748055 RX_GATING_MODE = 2
634 22:50:00.751355 RX_GATING_TRACK_MODE = 2
635 22:50:00.754696 SELPH_MODE = 1
636 22:50:00.758233 PICG_EARLY_EN = 1
637 22:50:00.761603 VALID_LAT_VALUE = 1
638 22:50:00.765317 ==============================================================
639 22:50:00.768167 Enter into Gating configuration >>>>
640 22:50:00.771449 Exit from Gating configuration <<<<
641 22:50:00.774913 Enter into DVFS_PRE_config >>>>>
642 22:50:00.788660 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:50:00.791609 Exit from DVFS_PRE_config <<<<<
644 22:50:00.795074 Enter into PICG configuration >>>>
645 22:50:00.795169 Exit from PICG configuration <<<<
646 22:50:00.798341 [RX_INPUT] configuration >>>>>
647 22:50:00.801617 [RX_INPUT] configuration <<<<<
648 22:50:00.808318 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:50:00.811659 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:50:00.818295 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:50:00.825053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:50:00.831506 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:50:00.838077 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:50:00.841799 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:50:00.844824 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:50:00.848433 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:50:00.854952 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:50:00.858280 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:50:00.861711 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:50:00.865063 ===================================
661 22:50:00.868267 LPDDR4 DRAM CONFIGURATION
662 22:50:00.871581 ===================================
663 22:50:00.871669 EX_ROW_EN[0] = 0x0
664 22:50:00.875109 EX_ROW_EN[1] = 0x0
665 22:50:00.878321 LP4Y_EN = 0x0
666 22:50:00.878408 WORK_FSP = 0x0
667 22:50:00.881962 WL = 0x2
668 22:50:00.882087 RL = 0x2
669 22:50:00.885092 BL = 0x2
670 22:50:00.885175 RPST = 0x0
671 22:50:00.888340 RD_PRE = 0x0
672 22:50:00.888424 WR_PRE = 0x1
673 22:50:00.891806 WR_PST = 0x0
674 22:50:00.891922 DBI_WR = 0x0
675 22:50:00.895065 DBI_RD = 0x0
676 22:50:00.895148 OTF = 0x1
677 22:50:00.898408 ===================================
678 22:50:00.901799 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:50:00.908344 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:50:00.911833 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:50:00.915155 ===================================
682 22:50:00.918500 LPDDR4 DRAM CONFIGURATION
683 22:50:00.921775 ===================================
684 22:50:00.921867 EX_ROW_EN[0] = 0x10
685 22:50:00.925175 EX_ROW_EN[1] = 0x0
686 22:50:00.925263 LP4Y_EN = 0x0
687 22:50:00.928746 WORK_FSP = 0x0
688 22:50:00.928857 WL = 0x2
689 22:50:00.931886 RL = 0x2
690 22:50:00.931975 BL = 0x2
691 22:50:00.935396 RPST = 0x0
692 22:50:00.935482 RD_PRE = 0x0
693 22:50:00.938513 WR_PRE = 0x1
694 22:50:00.938606 WR_PST = 0x0
695 22:50:00.941833 DBI_WR = 0x0
696 22:50:00.945427 DBI_RD = 0x0
697 22:50:00.945518 OTF = 0x1
698 22:50:00.948826 ===================================
699 22:50:00.955088 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:50:00.958651 nWR fixed to 40
701 22:50:00.961860 [ModeRegInit_LP4] CH0 RK0
702 22:50:00.961953 [ModeRegInit_LP4] CH0 RK1
703 22:50:00.965077 [ModeRegInit_LP4] CH1 RK0
704 22:50:00.968522 [ModeRegInit_LP4] CH1 RK1
705 22:50:00.968611 match AC timing 12
706 22:50:00.975319 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 22:50:00.978735 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:50:00.982071 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:50:00.988452 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:50:00.991724 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:50:00.995166 [EMI DOE] emi_dcm 0
712 22:50:00.998383 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:50:00.998473 ==
714 22:50:01.002068 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:50:01.005088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 22:50:01.005178 ==
717 22:50:01.011942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:50:01.018581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:50:01.025928 [CA 0] Center 37 (7~68) winsize 62
720 22:50:01.029166 [CA 1] Center 37 (7~68) winsize 62
721 22:50:01.032540 [CA 2] Center 35 (5~66) winsize 62
722 22:50:01.036156 [CA 3] Center 35 (4~66) winsize 63
723 22:50:01.039427 [CA 4] Center 34 (4~65) winsize 62
724 22:50:01.042606 [CA 5] Center 34 (4~65) winsize 62
725 22:50:01.042702
726 22:50:01.046060 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 22:50:01.046165
728 22:50:01.049654 [CATrainingPosCal] consider 1 rank data
729 22:50:01.052680 u2DelayCellTimex100 = 270/100 ps
730 22:50:01.055969 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 22:50:01.059398 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 22:50:01.062675 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 22:50:01.069553 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
734 22:50:01.072800 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 22:50:01.076036 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
736 22:50:01.076130
737 22:50:01.079181 CA PerBit enable=1, Macro0, CA PI delay=34
738 22:50:01.079270
739 22:50:01.082551 [CBTSetCACLKResult] CA Dly = 34
740 22:50:01.082642 CS Dly: 6 (0~37)
741 22:50:01.082730 ==
742 22:50:01.085851 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:50:01.092811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 22:50:01.092915 ==
745 22:50:01.095764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:50:01.102731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:50:01.111820 [CA 0] Center 37 (7~68) winsize 62
748 22:50:01.115156 [CA 1] Center 37 (6~68) winsize 63
749 22:50:01.118367 [CA 2] Center 35 (4~66) winsize 63
750 22:50:01.121945 [CA 3] Center 35 (4~66) winsize 63
751 22:50:01.125251 [CA 4] Center 33 (3~64) winsize 62
752 22:50:01.128460 [CA 5] Center 34 (3~65) winsize 63
753 22:50:01.128556
754 22:50:01.132026 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 22:50:01.132116
756 22:50:01.135107 [CATrainingPosCal] consider 2 rank data
757 22:50:01.138598 u2DelayCellTimex100 = 270/100 ps
758 22:50:01.141931 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 22:50:01.145110 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 22:50:01.151944 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 22:50:01.155355 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
762 22:50:01.158599 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
763 22:50:01.161968 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
764 22:50:01.162119
765 22:50:01.165150 CA PerBit enable=1, Macro0, CA PI delay=34
766 22:50:01.165239
767 22:50:01.168474 [CBTSetCACLKResult] CA Dly = 34
768 22:50:01.168562 CS Dly: 6 (0~37)
769 22:50:01.168648
770 22:50:01.171836 ----->DramcWriteLeveling(PI) begin...
771 22:50:01.175415 ==
772 22:50:01.175506 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:50:01.181652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 22:50:01.181766 ==
775 22:50:01.185203 Write leveling (Byte 0): 27 => 27
776 22:50:01.188271 Write leveling (Byte 1): 28 => 28
777 22:50:01.191842 DramcWriteLeveling(PI) end<-----
778 22:50:01.191936
779 22:50:01.192022 ==
780 22:50:01.195656 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:50:01.199235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 22:50:01.199332 ==
783 22:50:01.202674 [Gating] SW mode calibration
784 22:50:01.209785 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:50:01.213212 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:50:01.216695 0 6 0 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
787 22:50:01.223739 0 6 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
788 22:50:01.227083 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:50:01.230271 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:50:01.233694 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:50:01.240296 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:50:01.243828 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:50:01.247021 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:50:01.253624 0 7 0 | B1->B0 | 2828 2c2c | 0 0 | (1 1) (1 1)
795 22:50:01.257170 0 7 4 | B1->B0 | 3939 3e3e | 0 0 | (0 0) (0 0)
796 22:50:01.260586 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 22:50:01.267166 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 22:50:01.270408 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 22:50:01.273800 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 22:50:01.280459 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 22:50:01.283912 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 22:50:01.287109 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 22:50:01.293721 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 22:50:01.297155 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 22:50:01.300720 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 22:50:01.307103 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 22:50:01.310430 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 22:50:01.313725 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 22:50:01.316949 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 22:50:01.323782 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 22:50:01.326924 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 22:50:01.330508 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 22:50:01.336929 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 22:50:01.340434 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 22:50:01.343503 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 22:50:01.350461 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 22:50:01.353679 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 22:50:01.356952 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
819 22:50:01.363634 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 22:50:01.363749 Total UI for P1: 0, mck2ui 16
821 22:50:01.370328 best dqsien dly found for B0: ( 0, 10, 0)
822 22:50:01.370434 Total UI for P1: 0, mck2ui 16
823 22:50:01.376936 best dqsien dly found for B1: ( 0, 10, 2)
824 22:50:01.380340 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
825 22:50:01.383561 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
826 22:50:01.383654
827 22:50:01.387113 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 22:50:01.390567 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 22:50:01.393703 [Gating] SW calibration Done
830 22:50:01.393794 ==
831 22:50:01.397197 Dram Type= 6, Freq= 0, CH_0, rank 0
832 22:50:01.400627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 22:50:01.400715 ==
834 22:50:01.403779 RX Vref Scan: 0
835 22:50:01.403865
836 22:50:01.403930 RX Vref 0 -> 0, step: 1
837 22:50:01.403991
838 22:50:01.407044 RX Delay -130 -> 252, step: 16
839 22:50:01.410225 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 22:50:01.416992 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 22:50:01.420197 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 22:50:01.423470 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 22:50:01.426785 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 22:50:01.430308 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 22:50:01.436688 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 22:50:01.440194 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 22:50:01.443409 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 22:50:01.446717 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
849 22:50:01.450123 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 22:50:01.456969 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 22:50:01.460120 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 22:50:01.463386 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 22:50:01.466969 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 22:50:01.470064 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 22:50:01.473455 ==
856 22:50:01.476895 Dram Type= 6, Freq= 0, CH_0, rank 0
857 22:50:01.480057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 22:50:01.480146 ==
859 22:50:01.480212 DQS Delay:
860 22:50:01.483574 DQS0 = 0, DQS1 = 0
861 22:50:01.483657 DQM Delay:
862 22:50:01.486827 DQM0 = 82, DQM1 = 75
863 22:50:01.486912 DQ Delay:
864 22:50:01.490397 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 22:50:01.493778 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 22:50:01.497007 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
867 22:50:01.500591 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 22:50:01.500684
869 22:50:01.500750
870 22:50:01.500810 ==
871 22:50:01.504707 Dram Type= 6, Freq= 0, CH_0, rank 0
872 22:50:01.506763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 22:50:01.506851 ==
874 22:50:01.506917
875 22:50:01.507017
876 22:50:01.510223 TX Vref Scan disable
877 22:50:01.513294 == TX Byte 0 ==
878 22:50:01.516806 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
879 22:50:01.520147 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
880 22:50:01.523572 == TX Byte 1 ==
881 22:50:01.526960 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
882 22:50:01.530170 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
883 22:50:01.530265 ==
884 22:50:01.533579 Dram Type= 6, Freq= 0, CH_0, rank 0
885 22:50:01.536804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 22:50:01.536893 ==
887 22:50:01.551017 TX Vref=22, minBit 2, minWin=27, winSum=444
888 22:50:01.554230 TX Vref=24, minBit 4, minWin=27, winSum=448
889 22:50:01.557568 TX Vref=26, minBit 4, minWin=27, winSum=448
890 22:50:01.560860 TX Vref=28, minBit 4, minWin=27, winSum=452
891 22:50:01.564290 TX Vref=30, minBit 4, minWin=27, winSum=452
892 22:50:01.567631 TX Vref=32, minBit 1, minWin=27, winSum=450
893 22:50:01.574536 [TxChooseVref] Worse bit 4, Min win 27, Win sum 452, Final Vref 28
894 22:50:01.574655
895 22:50:01.577663 Final TX Range 1 Vref 28
896 22:50:01.577751
897 22:50:01.577817 ==
898 22:50:01.581179 Dram Type= 6, Freq= 0, CH_0, rank 0
899 22:50:01.584404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 22:50:01.584494 ==
901 22:50:01.584560
902 22:50:01.584621
903 22:50:01.588135 TX Vref Scan disable
904 22:50:01.591649 == TX Byte 0 ==
905 22:50:01.594969 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
906 22:50:01.598469 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
907 22:50:01.601673 == TX Byte 1 ==
908 22:50:01.605129 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
909 22:50:01.608282 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
910 22:50:01.608378
911 22:50:01.611714 [DATLAT]
912 22:50:01.611803 Freq=800, CH0 RK0
913 22:50:01.611869
914 22:50:01.615019 DATLAT Default: 0xa
915 22:50:01.615104 0, 0xFFFF, sum = 0
916 22:50:01.618660 1, 0xFFFF, sum = 0
917 22:50:01.618749 2, 0xFFFF, sum = 0
918 22:50:01.621901 3, 0xFFFF, sum = 0
919 22:50:01.622017 4, 0xFFFF, sum = 0
920 22:50:01.625044 5, 0xFFFF, sum = 0
921 22:50:01.625131 6, 0xFFFF, sum = 0
922 22:50:01.628389 7, 0xFFFF, sum = 0
923 22:50:01.628476 8, 0x0, sum = 1
924 22:50:01.631699 9, 0x0, sum = 2
925 22:50:01.631787 10, 0x0, sum = 3
926 22:50:01.635159 11, 0x0, sum = 4
927 22:50:01.635247 best_step = 9
928 22:50:01.635312
929 22:50:01.635372 ==
930 22:50:01.638363 Dram Type= 6, Freq= 0, CH_0, rank 0
931 22:50:01.641885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 22:50:01.641986 ==
933 22:50:01.645349 RX Vref Scan: 1
934 22:50:01.645436
935 22:50:01.648168 Set Vref Range= 32 -> 127
936 22:50:01.648272
937 22:50:01.648338 RX Vref 32 -> 127, step: 1
938 22:50:01.648400
939 22:50:01.651523 RX Delay -95 -> 252, step: 8
940 22:50:01.651610
941 22:50:01.654971 Set Vref, RX VrefLevel [Byte0]: 32
942 22:50:01.658277 [Byte1]: 32
943 22:50:01.661573
944 22:50:01.661660 Set Vref, RX VrefLevel [Byte0]: 33
945 22:50:01.665010 [Byte1]: 33
946 22:50:01.669449
947 22:50:01.669539 Set Vref, RX VrefLevel [Byte0]: 34
948 22:50:01.672734 [Byte1]: 34
949 22:50:01.676850
950 22:50:01.676944 Set Vref, RX VrefLevel [Byte0]: 35
951 22:50:01.680322 [Byte1]: 35
952 22:50:01.684564
953 22:50:01.684654 Set Vref, RX VrefLevel [Byte0]: 36
954 22:50:01.687660 [Byte1]: 36
955 22:50:01.692039
956 22:50:01.692128 Set Vref, RX VrefLevel [Byte0]: 37
957 22:50:01.695403 [Byte1]: 37
958 22:50:01.699573
959 22:50:01.699661 Set Vref, RX VrefLevel [Byte0]: 38
960 22:50:01.703033 [Byte1]: 38
961 22:50:01.707064
962 22:50:01.707151 Set Vref, RX VrefLevel [Byte0]: 39
963 22:50:01.710402 [Byte1]: 39
964 22:50:01.714878
965 22:50:01.714970 Set Vref, RX VrefLevel [Byte0]: 40
966 22:50:01.718034 [Byte1]: 40
967 22:50:01.722346
968 22:50:01.722434 Set Vref, RX VrefLevel [Byte0]: 41
969 22:50:01.725874 [Byte1]: 41
970 22:50:01.730031
971 22:50:01.730122 Set Vref, RX VrefLevel [Byte0]: 42
972 22:50:01.733202 [Byte1]: 42
973 22:50:01.737462
974 22:50:01.737551 Set Vref, RX VrefLevel [Byte0]: 43
975 22:50:01.740853 [Byte1]: 43
976 22:50:01.745443
977 22:50:01.745540 Set Vref, RX VrefLevel [Byte0]: 44
978 22:50:01.748397 [Byte1]: 44
979 22:50:01.752646
980 22:50:01.752743 Set Vref, RX VrefLevel [Byte0]: 45
981 22:50:01.755930 [Byte1]: 45
982 22:50:01.760551
983 22:50:01.760648 Set Vref, RX VrefLevel [Byte0]: 46
984 22:50:01.763587 [Byte1]: 46
985 22:50:01.768010
986 22:50:01.768103 Set Vref, RX VrefLevel [Byte0]: 47
987 22:50:01.771425 [Byte1]: 47
988 22:50:01.775584
989 22:50:01.775705 Set Vref, RX VrefLevel [Byte0]: 48
990 22:50:01.778931 [Byte1]: 48
991 22:50:01.783195
992 22:50:01.783285 Set Vref, RX VrefLevel [Byte0]: 49
993 22:50:01.786996 [Byte1]: 49
994 22:50:01.790737
995 22:50:01.790828 Set Vref, RX VrefLevel [Byte0]: 50
996 22:50:01.794043 [Byte1]: 50
997 22:50:01.798334
998 22:50:01.798432 Set Vref, RX VrefLevel [Byte0]: 51
999 22:50:01.801723 [Byte1]: 51
1000 22:50:01.806239
1001 22:50:01.806331 Set Vref, RX VrefLevel [Byte0]: 52
1002 22:50:01.809107 [Byte1]: 52
1003 22:50:01.813464
1004 22:50:01.813557 Set Vref, RX VrefLevel [Byte0]: 53
1005 22:50:01.816966 [Byte1]: 53
1006 22:50:01.821053
1007 22:50:01.821145 Set Vref, RX VrefLevel [Byte0]: 54
1008 22:50:01.824310 [Byte1]: 54
1009 22:50:01.828682
1010 22:50:01.828773 Set Vref, RX VrefLevel [Byte0]: 55
1011 22:50:01.831933 [Byte1]: 55
1012 22:50:01.836310
1013 22:50:01.836401 Set Vref, RX VrefLevel [Byte0]: 56
1014 22:50:01.839686 [Byte1]: 56
1015 22:50:01.843840
1016 22:50:01.843935 Set Vref, RX VrefLevel [Byte0]: 57
1017 22:50:01.847309 [Byte1]: 57
1018 22:50:01.851455
1019 22:50:01.851549 Set Vref, RX VrefLevel [Byte0]: 58
1020 22:50:01.855084 [Byte1]: 58
1021 22:50:01.859387
1022 22:50:01.859487 Set Vref, RX VrefLevel [Byte0]: 59
1023 22:50:01.863068 [Byte1]: 59
1024 22:50:01.867090
1025 22:50:01.867191 Set Vref, RX VrefLevel [Byte0]: 60
1026 22:50:01.870819 [Byte1]: 60
1027 22:50:01.875028
1028 22:50:01.875123 Set Vref, RX VrefLevel [Byte0]: 61
1029 22:50:01.878484 [Byte1]: 61
1030 22:50:01.882746
1031 22:50:01.882837 Set Vref, RX VrefLevel [Byte0]: 62
1032 22:50:01.885911 [Byte1]: 62
1033 22:50:01.889770
1034 22:50:01.889866 Set Vref, RX VrefLevel [Byte0]: 63
1035 22:50:01.892918 [Byte1]: 63
1036 22:50:01.897319
1037 22:50:01.897415 Set Vref, RX VrefLevel [Byte0]: 64
1038 22:50:01.900618 [Byte1]: 64
1039 22:50:01.904584
1040 22:50:01.904677 Set Vref, RX VrefLevel [Byte0]: 65
1041 22:50:01.907958 [Byte1]: 65
1042 22:50:01.912161
1043 22:50:01.912252 Set Vref, RX VrefLevel [Byte0]: 66
1044 22:50:01.915637 [Byte1]: 66
1045 22:50:01.919997
1046 22:50:01.920089 Set Vref, RX VrefLevel [Byte0]: 67
1047 22:50:01.923039 [Byte1]: 67
1048 22:50:01.927448
1049 22:50:01.927536 Set Vref, RX VrefLevel [Byte0]: 68
1050 22:50:01.930755 [Byte1]: 68
1051 22:50:01.935085
1052 22:50:01.935175 Set Vref, RX VrefLevel [Byte0]: 69
1053 22:50:01.938349 [Byte1]: 69
1054 22:50:01.942566
1055 22:50:01.942667 Set Vref, RX VrefLevel [Byte0]: 70
1056 22:50:01.946012 [Byte1]: 70
1057 22:50:01.950288
1058 22:50:01.950378 Set Vref, RX VrefLevel [Byte0]: 71
1059 22:50:01.953402 [Byte1]: 71
1060 22:50:01.957849
1061 22:50:01.957964 Set Vref, RX VrefLevel [Byte0]: 72
1062 22:50:01.961199 [Byte1]: 72
1063 22:50:01.965498
1064 22:50:01.965588 Set Vref, RX VrefLevel [Byte0]: 73
1065 22:50:01.968688 [Byte1]: 73
1066 22:50:01.972894
1067 22:50:01.972982 Set Vref, RX VrefLevel [Byte0]: 74
1068 22:50:01.976651 [Byte1]: 74
1069 22:50:01.980642
1070 22:50:01.980731 Final RX Vref Byte 0 = 54 to rank0
1071 22:50:01.983996 Final RX Vref Byte 1 = 55 to rank0
1072 22:50:01.987243 Final RX Vref Byte 0 = 54 to rank1
1073 22:50:01.990716 Final RX Vref Byte 1 = 55 to rank1==
1074 22:50:01.994035 Dram Type= 6, Freq= 0, CH_0, rank 0
1075 22:50:02.000610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1076 22:50:02.000715 ==
1077 22:50:02.000782 DQS Delay:
1078 22:50:02.000843 DQS0 = 0, DQS1 = 0
1079 22:50:02.003915 DQM Delay:
1080 22:50:02.003999 DQM0 = 83, DQM1 = 72
1081 22:50:02.007350 DQ Delay:
1082 22:50:02.010580 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1083 22:50:02.010665 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1084 22:50:02.013941 DQ8 =60, DQ9 =56, DQ10 =76, DQ11 =64
1085 22:50:02.020658 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1086 22:50:02.020774
1087 22:50:02.020841
1088 22:50:02.027118 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1089 22:50:02.030454 CH0 RK0: MR19=606, MR18=3232
1090 22:50:02.037302 CH0_RK0: MR19=0x606, MR18=0x3232, DQSOSC=397, MR23=63, INC=93, DEC=62
1091 22:50:02.037408
1092 22:50:02.040551 ----->DramcWriteLeveling(PI) begin...
1093 22:50:02.040644 ==
1094 22:50:02.043804 Dram Type= 6, Freq= 0, CH_0, rank 1
1095 22:50:02.047038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1096 22:50:02.047126 ==
1097 22:50:02.050338 Write leveling (Byte 0): 30 => 30
1098 22:50:02.053750 Write leveling (Byte 1): 30 => 30
1099 22:50:02.057098 DramcWriteLeveling(PI) end<-----
1100 22:50:02.057185
1101 22:50:02.057250 ==
1102 22:50:02.060455 Dram Type= 6, Freq= 0, CH_0, rank 1
1103 22:50:02.063727 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1104 22:50:02.063815 ==
1105 22:50:02.067129 [Gating] SW mode calibration
1106 22:50:02.073948 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1107 22:50:02.080712 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1108 22:50:02.083989 0 6 0 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 0)
1109 22:50:02.087425 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 22:50:02.094119 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 22:50:02.097570 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 22:50:02.100471 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 22:50:02.107312 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 22:50:02.110879 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 22:50:02.113868 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 22:50:02.120416 0 7 0 | B1->B0 | 2626 2e2e | 0 1 | (0 0) (0 0)
1117 22:50:02.123962 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 22:50:02.127086 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 22:50:02.133829 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 22:50:02.137156 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 22:50:02.140458 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 22:50:02.147009 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 22:50:02.150464 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 22:50:02.153943 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1125 22:50:02.157199 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 22:50:02.163752 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 22:50:02.167029 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 22:50:02.170464 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 22:50:02.177094 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 22:50:02.180403 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 22:50:02.183786 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 22:50:02.190454 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 22:50:02.193817 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 22:50:02.197375 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 22:50:02.203940 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 22:50:02.207167 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 22:50:02.210445 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 22:50:02.217278 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 22:50:02.220430 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 22:50:02.223844 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 22:50:02.230378 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1142 22:50:02.230482 Total UI for P1: 0, mck2ui 16
1143 22:50:02.233970 best dqsien dly found for B0: ( 0, 10, 2)
1144 22:50:02.237082 Total UI for P1: 0, mck2ui 16
1145 22:50:02.240514 best dqsien dly found for B1: ( 0, 10, 2)
1146 22:50:02.244334 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1147 22:50:02.250530 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1148 22:50:02.250635
1149 22:50:02.253983 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1150 22:50:02.257287 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1151 22:50:02.260525 [Gating] SW calibration Done
1152 22:50:02.260612 ==
1153 22:50:02.263971 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 22:50:02.267583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1155 22:50:02.267671 ==
1156 22:50:02.267735 RX Vref Scan: 0
1157 22:50:02.311423
1158 22:50:02.311667 RX Vref 0 -> 0, step: 1
1159 22:50:02.311774
1160 22:50:02.311863 RX Delay -130 -> 252, step: 16
1161 22:50:02.311934 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1162 22:50:02.312231 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1163 22:50:02.312311 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1164 22:50:02.312370 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1165 22:50:02.312425 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1166 22:50:02.312489 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1167 22:50:02.312545 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1168 22:50:02.312867 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1169 22:50:02.313218 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1170 22:50:02.322996 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1171 22:50:02.323153 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1172 22:50:02.323473 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1173 22:50:02.326416 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1174 22:50:02.329501 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1175 22:50:02.332820 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1176 22:50:02.339530 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1177 22:50:02.339634 ==
1178 22:50:02.343040 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 22:50:02.346470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1180 22:50:02.346563 ==
1181 22:50:02.346628 DQS Delay:
1182 22:50:02.349615 DQS0 = 0, DQS1 = 0
1183 22:50:02.349699 DQM Delay:
1184 22:50:02.353039 DQM0 = 84, DQM1 = 74
1185 22:50:02.353124 DQ Delay:
1186 22:50:02.356193 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1187 22:50:02.359586 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1188 22:50:02.362964 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1189 22:50:02.366233 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1190 22:50:02.366322
1191 22:50:02.366386
1192 22:50:02.366447 ==
1193 22:50:02.369641 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 22:50:02.373305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1195 22:50:02.373393 ==
1196 22:50:02.373458
1197 22:50:02.373518
1198 22:50:02.376276 TX Vref Scan disable
1199 22:50:02.379881 == TX Byte 0 ==
1200 22:50:02.382909 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1201 22:50:02.386403 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1202 22:50:02.389622 == TX Byte 1 ==
1203 22:50:02.393086 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1204 22:50:02.396385 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1205 22:50:02.396470 ==
1206 22:50:02.399587 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 22:50:02.406409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1208 22:50:02.406506 ==
1209 22:50:02.417753 TX Vref=22, minBit 10, minWin=27, winSum=448
1210 22:50:02.420880 TX Vref=24, minBit 0, minWin=28, winSum=449
1211 22:50:02.424495 TX Vref=26, minBit 0, minWin=28, winSum=451
1212 22:50:02.427552 TX Vref=28, minBit 2, minWin=28, winSum=460
1213 22:50:02.431050 TX Vref=30, minBit 2, minWin=28, winSum=460
1214 22:50:02.434746 TX Vref=32, minBit 2, minWin=28, winSum=458
1215 22:50:02.441727 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 28
1216 22:50:02.441852
1217 22:50:02.445109 Final TX Range 1 Vref 28
1218 22:50:02.445197
1219 22:50:02.445260 ==
1220 22:50:02.448899 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 22:50:02.452565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 22:50:02.452659 ==
1223 22:50:02.452724
1224 22:50:02.452783
1225 22:50:02.456056 TX Vref Scan disable
1226 22:50:02.456142 == TX Byte 0 ==
1227 22:50:02.462657 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1228 22:50:02.466587 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1229 22:50:02.466686 == TX Byte 1 ==
1230 22:50:02.473060 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1231 22:50:02.476207 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1232 22:50:02.476299
1233 22:50:02.476363 [DATLAT]
1234 22:50:02.479621 Freq=800, CH0 RK1
1235 22:50:02.479704
1236 22:50:02.479768 DATLAT Default: 0x9
1237 22:50:02.482945 0, 0xFFFF, sum = 0
1238 22:50:02.483030 1, 0xFFFF, sum = 0
1239 22:50:02.486652 2, 0xFFFF, sum = 0
1240 22:50:02.486737 3, 0xFFFF, sum = 0
1241 22:50:02.489538 4, 0xFFFF, sum = 0
1242 22:50:02.489621 5, 0xFFFF, sum = 0
1243 22:50:02.492851 6, 0xFFFF, sum = 0
1244 22:50:02.492934 7, 0xFFFF, sum = 0
1245 22:50:02.496222 8, 0x0, sum = 1
1246 22:50:02.496305 9, 0x0, sum = 2
1247 22:50:02.499641 10, 0x0, sum = 3
1248 22:50:02.499724 11, 0x0, sum = 4
1249 22:50:02.503040 best_step = 9
1250 22:50:02.503122
1251 22:50:02.503185 ==
1252 22:50:02.506274 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 22:50:02.509834 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1254 22:50:02.509921 ==
1255 22:50:02.512958 RX Vref Scan: 0
1256 22:50:02.513041
1257 22:50:02.513104 RX Vref 0 -> 0, step: 1
1258 22:50:02.513163
1259 22:50:02.516591 RX Delay -111 -> 252, step: 8
1260 22:50:02.523045 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1261 22:50:02.526394 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1262 22:50:02.529613 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1263 22:50:02.533195 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1264 22:50:02.536395 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1265 22:50:02.539724 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1266 22:50:02.546328 iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240
1267 22:50:02.549831 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1268 22:50:02.553020 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1269 22:50:02.556375 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1270 22:50:02.559946 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1271 22:50:02.566337 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1272 22:50:02.569684 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1273 22:50:02.572966 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1274 22:50:02.576464 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1275 22:50:02.583059 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1276 22:50:02.583156 ==
1277 22:50:02.586265 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 22:50:02.589886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1279 22:50:02.589996 ==
1280 22:50:02.590082 DQS Delay:
1281 22:50:02.593435 DQS0 = 0, DQS1 = 0
1282 22:50:02.593518 DQM Delay:
1283 22:50:02.596436 DQM0 = 86, DQM1 = 74
1284 22:50:02.596518 DQ Delay:
1285 22:50:02.599571 DQ0 =80, DQ1 =92, DQ2 =84, DQ3 =80
1286 22:50:02.603214 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1287 22:50:02.606278 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1288 22:50:02.609564 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1289 22:50:02.609647
1290 22:50:02.609710
1291 22:50:02.616525 [DQSOSCAuto] RK1, (LSB)MR18= 0x4646, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1292 22:50:02.619643 CH0 RK1: MR19=606, MR18=4646
1293 22:50:02.626271 CH0_RK1: MR19=0x606, MR18=0x4646, DQSOSC=392, MR23=63, INC=96, DEC=64
1294 22:50:02.629297 [RxdqsGatingPostProcess] freq 800
1295 22:50:02.635979 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1296 22:50:02.636091 Pre-setting of DQS Precalculation
1297 22:50:02.642817 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1298 22:50:02.642930 ==
1299 22:50:02.646331 Dram Type= 6, Freq= 0, CH_1, rank 0
1300 22:50:02.649518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1301 22:50:02.649603 ==
1302 22:50:02.656074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1303 22:50:02.662595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1304 22:50:02.670535 [CA 0] Center 37 (6~68) winsize 63
1305 22:50:02.673598 [CA 1] Center 37 (6~68) winsize 63
1306 22:50:02.677395 [CA 2] Center 34 (4~65) winsize 62
1307 22:50:02.680357 [CA 3] Center 34 (4~65) winsize 62
1308 22:50:02.684200 [CA 4] Center 33 (3~64) winsize 62
1309 22:50:02.687128 [CA 5] Center 33 (3~64) winsize 62
1310 22:50:02.687215
1311 22:50:02.690439 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1312 22:50:02.690520
1313 22:50:02.694000 [CATrainingPosCal] consider 1 rank data
1314 22:50:02.697309 u2DelayCellTimex100 = 270/100 ps
1315 22:50:02.700559 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1316 22:50:02.703736 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1317 22:50:02.710252 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1318 22:50:02.713784 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1319 22:50:02.717367 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1320 22:50:02.720483 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1321 22:50:02.720567
1322 22:50:02.723866 CA PerBit enable=1, Macro0, CA PI delay=33
1323 22:50:02.723949
1324 22:50:02.726970 [CBTSetCACLKResult] CA Dly = 33
1325 22:50:02.727055 CS Dly: 4 (0~35)
1326 22:50:02.727118 ==
1327 22:50:02.730693 Dram Type= 6, Freq= 0, CH_1, rank 1
1328 22:50:02.736972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1329 22:50:02.737069 ==
1330 22:50:02.740407 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1331 22:50:02.747072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1332 22:50:02.756394 [CA 0] Center 37 (6~68) winsize 63
1333 22:50:02.759468 [CA 1] Center 37 (6~68) winsize 63
1334 22:50:02.762770 [CA 2] Center 34 (4~65) winsize 62
1335 22:50:02.766392 [CA 3] Center 34 (4~65) winsize 62
1336 22:50:02.769629 [CA 4] Center 33 (3~64) winsize 62
1337 22:50:02.773191 [CA 5] Center 33 (3~64) winsize 62
1338 22:50:02.773279
1339 22:50:02.776111 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1340 22:50:02.776195
1341 22:50:02.779712 [CATrainingPosCal] consider 2 rank data
1342 22:50:02.782851 u2DelayCellTimex100 = 270/100 ps
1343 22:50:02.786092 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1344 22:50:02.789568 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1345 22:50:02.796144 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1346 22:50:02.799499 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1347 22:50:02.802822 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1348 22:50:02.806320 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1349 22:50:02.806406
1350 22:50:02.809769 CA PerBit enable=1, Macro0, CA PI delay=33
1351 22:50:02.809853
1352 22:50:02.812720 [CBTSetCACLKResult] CA Dly = 33
1353 22:50:02.812804 CS Dly: 4 (0~36)
1354 22:50:02.812868
1355 22:50:02.816095 ----->DramcWriteLeveling(PI) begin...
1356 22:50:02.819500 ==
1357 22:50:02.819584 Dram Type= 6, Freq= 0, CH_1, rank 0
1358 22:50:02.826240 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1359 22:50:02.826326 ==
1360 22:50:02.829568 Write leveling (Byte 0): 26 => 26
1361 22:50:02.833123 Write leveling (Byte 1): 25 => 25
1362 22:50:02.836281 DramcWriteLeveling(PI) end<-----
1363 22:50:02.836376
1364 22:50:02.836440 ==
1365 22:50:02.839351 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 22:50:02.842674 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1367 22:50:02.842767 ==
1368 22:50:02.846208 [Gating] SW mode calibration
1369 22:50:02.852922 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1370 22:50:02.856241 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1371 22:50:02.862719 0 6 0 | B1->B0 | 2f2f 2828 | 1 1 | (1 0) (1 0)
1372 22:50:02.866220 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1373 22:50:02.869474 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 22:50:02.876276 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 22:50:02.879576 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 22:50:02.883192 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 22:50:02.889498 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 22:50:02.892840 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 22:50:02.896195 0 7 0 | B1->B0 | 2727 3d3d | 0 0 | (0 0) (0 0)
1380 22:50:02.903182 0 7 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1381 22:50:02.906305 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 22:50:02.909764 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 22:50:02.916534 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 22:50:02.919516 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 22:50:02.923057 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 22:50:02.926353 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1387 22:50:02.932979 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1388 22:50:02.936232 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 22:50:02.939515 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 22:50:02.946464 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 22:50:02.949735 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 22:50:02.953260 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 22:50:02.959851 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 22:50:02.963045 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 22:50:02.966253 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 22:50:02.973445 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 22:50:02.976420 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 22:50:02.979802 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 22:50:02.986248 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 22:50:02.989553 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 22:50:02.992996 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 22:50:02.999670 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1403 22:50:03.003089 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1404 22:50:03.006417 Total UI for P1: 0, mck2ui 16
1405 22:50:03.009709 best dqsien dly found for B1: ( 0, 9, 30)
1406 22:50:03.013068 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1407 22:50:03.016429 Total UI for P1: 0, mck2ui 16
1408 22:50:03.019889 best dqsien dly found for B0: ( 0, 9, 30)
1409 22:50:03.023096 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1410 22:50:03.026355 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1411 22:50:03.026446
1412 22:50:03.030016 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1413 22:50:03.036458 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1414 22:50:03.036561 [Gating] SW calibration Done
1415 22:50:03.036627 ==
1416 22:50:03.040070 Dram Type= 6, Freq= 0, CH_1, rank 0
1417 22:50:03.046280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1418 22:50:03.046388 ==
1419 22:50:03.046454 RX Vref Scan: 0
1420 22:50:03.046517
1421 22:50:03.049625 RX Vref 0 -> 0, step: 1
1422 22:50:03.049709
1423 22:50:03.053059 RX Delay -130 -> 252, step: 16
1424 22:50:03.056254 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1425 22:50:03.059643 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1426 22:50:03.062976 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1427 22:50:03.069696 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1428 22:50:03.073021 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1429 22:50:03.076225 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1430 22:50:03.079593 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1431 22:50:03.083058 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1432 22:50:03.089544 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1433 22:50:03.092809 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1434 22:50:03.096261 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1435 22:50:03.099891 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1436 22:50:03.103545 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1437 22:50:03.107156 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1438 22:50:03.110892 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1439 22:50:03.118135 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1440 22:50:03.118249 ==
1441 22:50:03.121851 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 22:50:03.125637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1443 22:50:03.125733 ==
1444 22:50:03.125799 DQS Delay:
1445 22:50:03.125859 DQS0 = 0, DQS1 = 0
1446 22:50:03.129279 DQM Delay:
1447 22:50:03.129366 DQM0 = 81, DQM1 = 74
1448 22:50:03.132761 DQ Delay:
1449 22:50:03.132847 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1450 22:50:03.136394 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1451 22:50:03.139894 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1452 22:50:03.143179 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1453 22:50:03.143274
1454 22:50:03.143340
1455 22:50:03.143399 ==
1456 22:50:03.146828 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 22:50:03.152995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1458 22:50:03.153105 ==
1459 22:50:03.153169
1460 22:50:03.153228
1461 22:50:03.153284 TX Vref Scan disable
1462 22:50:03.156786 == TX Byte 0 ==
1463 22:50:03.160252 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1464 22:50:03.163347 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1465 22:50:03.166860 == TX Byte 1 ==
1466 22:50:03.170154 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1467 22:50:03.173364 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1468 22:50:03.176811 ==
1469 22:50:03.180058 Dram Type= 6, Freq= 0, CH_1, rank 0
1470 22:50:03.183227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1471 22:50:03.183315 ==
1472 22:50:03.195861 TX Vref=22, minBit 3, minWin=27, winSum=446
1473 22:50:03.198944 TX Vref=24, minBit 3, minWin=27, winSum=448
1474 22:50:03.202456 TX Vref=26, minBit 3, minWin=27, winSum=454
1475 22:50:03.205605 TX Vref=28, minBit 0, minWin=28, winSum=456
1476 22:50:03.209127 TX Vref=30, minBit 0, minWin=28, winSum=459
1477 22:50:03.212397 TX Vref=32, minBit 0, minWin=28, winSum=461
1478 22:50:03.219156 [TxChooseVref] Worse bit 0, Min win 28, Win sum 461, Final Vref 32
1479 22:50:03.219265
1480 22:50:03.222481 Final TX Range 1 Vref 32
1481 22:50:03.222566
1482 22:50:03.222630 ==
1483 22:50:03.225695 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 22:50:03.229126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1485 22:50:03.229214 ==
1486 22:50:03.229277
1487 22:50:03.232682
1488 22:50:03.232765 TX Vref Scan disable
1489 22:50:03.235669 == TX Byte 0 ==
1490 22:50:03.239072 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1491 22:50:03.242670 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1492 22:50:03.245742 == TX Byte 1 ==
1493 22:50:03.249053 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1494 22:50:03.252352 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1495 22:50:03.252461
1496 22:50:03.255576 [DATLAT]
1497 22:50:03.255675 Freq=800, CH1 RK0
1498 22:50:03.255771
1499 22:50:03.258972 DATLAT Default: 0xa
1500 22:50:03.259074 0, 0xFFFF, sum = 0
1501 22:50:03.262510 1, 0xFFFF, sum = 0
1502 22:50:03.262622 2, 0xFFFF, sum = 0
1503 22:50:03.265591 3, 0xFFFF, sum = 0
1504 22:50:03.265691 4, 0xFFFF, sum = 0
1505 22:50:03.269091 5, 0xFFFF, sum = 0
1506 22:50:03.269180 6, 0xFFFF, sum = 0
1507 22:50:03.272426 7, 0xFFFF, sum = 0
1508 22:50:03.272528 8, 0x0, sum = 1
1509 22:50:03.275474 9, 0x0, sum = 2
1510 22:50:03.275575 10, 0x0, sum = 3
1511 22:50:03.279009 11, 0x0, sum = 4
1512 22:50:03.279109 best_step = 9
1513 22:50:03.279202
1514 22:50:03.279274 ==
1515 22:50:03.282284 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 22:50:03.288913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1517 22:50:03.289037 ==
1518 22:50:03.289119 RX Vref Scan: 1
1519 22:50:03.289208
1520 22:50:03.292457 Set Vref Range= 32 -> 127
1521 22:50:03.292559
1522 22:50:03.295744 RX Vref 32 -> 127, step: 1
1523 22:50:03.295844
1524 22:50:03.295937 RX Delay -95 -> 252, step: 8
1525 22:50:03.296012
1526 22:50:03.298917 Set Vref, RX VrefLevel [Byte0]: 32
1527 22:50:03.302289 [Byte1]: 32
1528 22:50:03.306485
1529 22:50:03.306576 Set Vref, RX VrefLevel [Byte0]: 33
1530 22:50:03.309589 [Byte1]: 33
1531 22:50:03.313887
1532 22:50:03.313992 Set Vref, RX VrefLevel [Byte0]: 34
1533 22:50:03.317313 [Byte1]: 34
1534 22:50:03.321474
1535 22:50:03.321582 Set Vref, RX VrefLevel [Byte0]: 35
1536 22:50:03.324864 [Byte1]: 35
1537 22:50:03.329513
1538 22:50:03.329621 Set Vref, RX VrefLevel [Byte0]: 36
1539 22:50:03.332476 [Byte1]: 36
1540 22:50:03.337139
1541 22:50:03.337236 Set Vref, RX VrefLevel [Byte0]: 37
1542 22:50:03.340177 [Byte1]: 37
1543 22:50:03.344296
1544 22:50:03.344395 Set Vref, RX VrefLevel [Byte0]: 38
1545 22:50:03.348182 [Byte1]: 38
1546 22:50:03.352094
1547 22:50:03.352220 Set Vref, RX VrefLevel [Byte0]: 39
1548 22:50:03.355499 [Byte1]: 39
1549 22:50:03.359678
1550 22:50:03.359771 Set Vref, RX VrefLevel [Byte0]: 40
1551 22:50:03.362905 [Byte1]: 40
1552 22:50:03.367102
1553 22:50:03.367195 Set Vref, RX VrefLevel [Byte0]: 41
1554 22:50:03.370469 [Byte1]: 41
1555 22:50:03.374679
1556 22:50:03.374772 Set Vref, RX VrefLevel [Byte0]: 42
1557 22:50:03.378144 [Byte1]: 42
1558 22:50:03.382368
1559 22:50:03.382462 Set Vref, RX VrefLevel [Byte0]: 43
1560 22:50:03.385750 [Byte1]: 43
1561 22:50:03.389855
1562 22:50:03.389950 Set Vref, RX VrefLevel [Byte0]: 44
1563 22:50:03.393476 [Byte1]: 44
1564 22:50:03.397801
1565 22:50:03.397893 Set Vref, RX VrefLevel [Byte0]: 45
1566 22:50:03.400808 [Byte1]: 45
1567 22:50:03.405048
1568 22:50:03.405137 Set Vref, RX VrefLevel [Byte0]: 46
1569 22:50:03.408801 [Byte1]: 46
1570 22:50:03.412860
1571 22:50:03.412949 Set Vref, RX VrefLevel [Byte0]: 47
1572 22:50:03.416033 [Byte1]: 47
1573 22:50:03.420517
1574 22:50:03.420609 Set Vref, RX VrefLevel [Byte0]: 48
1575 22:50:03.423836 [Byte1]: 48
1576 22:50:03.427907
1577 22:50:03.427997 Set Vref, RX VrefLevel [Byte0]: 49
1578 22:50:03.431243 [Byte1]: 49
1579 22:50:03.435548
1580 22:50:03.435637 Set Vref, RX VrefLevel [Byte0]: 50
1581 22:50:03.438914 [Byte1]: 50
1582 22:50:03.443093
1583 22:50:03.443221 Set Vref, RX VrefLevel [Byte0]: 51
1584 22:50:03.446334 [Byte1]: 51
1585 22:50:03.450748
1586 22:50:03.450868 Set Vref, RX VrefLevel [Byte0]: 52
1587 22:50:03.453918 [Byte1]: 52
1588 22:50:03.458589
1589 22:50:03.458679 Set Vref, RX VrefLevel [Byte0]: 53
1590 22:50:03.461859 [Byte1]: 53
1591 22:50:03.466144
1592 22:50:03.466237 Set Vref, RX VrefLevel [Byte0]: 54
1593 22:50:03.469200 [Byte1]: 54
1594 22:50:03.473450
1595 22:50:03.473541 Set Vref, RX VrefLevel [Byte0]: 55
1596 22:50:03.476864 [Byte1]: 55
1597 22:50:03.481161
1598 22:50:03.481255 Set Vref, RX VrefLevel [Byte0]: 56
1599 22:50:03.484722 [Byte1]: 56
1600 22:50:03.488793
1601 22:50:03.488882 Set Vref, RX VrefLevel [Byte0]: 57
1602 22:50:03.492161 [Byte1]: 57
1603 22:50:03.496416
1604 22:50:03.496506 Set Vref, RX VrefLevel [Byte0]: 58
1605 22:50:03.499677 [Byte1]: 58
1606 22:50:03.503920
1607 22:50:03.504008 Set Vref, RX VrefLevel [Byte0]: 59
1608 22:50:03.507246 [Byte1]: 59
1609 22:50:03.511711
1610 22:50:03.511800 Set Vref, RX VrefLevel [Byte0]: 60
1611 22:50:03.514925 [Byte1]: 60
1612 22:50:03.519103
1613 22:50:03.519191 Set Vref, RX VrefLevel [Byte0]: 61
1614 22:50:03.522620 [Byte1]: 61
1615 22:50:03.526578
1616 22:50:03.526667 Set Vref, RX VrefLevel [Byte0]: 62
1617 22:50:03.529920 [Byte1]: 62
1618 22:50:03.534370
1619 22:50:03.534476 Set Vref, RX VrefLevel [Byte0]: 63
1620 22:50:03.537729 [Byte1]: 63
1621 22:50:03.541999
1622 22:50:03.542132 Set Vref, RX VrefLevel [Byte0]: 64
1623 22:50:03.548497 [Byte1]: 64
1624 22:50:03.548607
1625 22:50:03.551780 Set Vref, RX VrefLevel [Byte0]: 65
1626 22:50:03.555116 [Byte1]: 65
1627 22:50:03.555208
1628 22:50:03.558337 Set Vref, RX VrefLevel [Byte0]: 66
1629 22:50:03.561872 [Byte1]: 66
1630 22:50:03.561983
1631 22:50:03.565117 Set Vref, RX VrefLevel [Byte0]: 67
1632 22:50:03.568573 [Byte1]: 67
1633 22:50:03.572323
1634 22:50:03.572411 Set Vref, RX VrefLevel [Byte0]: 68
1635 22:50:03.575496 [Byte1]: 68
1636 22:50:03.579871
1637 22:50:03.579961 Set Vref, RX VrefLevel [Byte0]: 69
1638 22:50:03.583325 [Byte1]: 69
1639 22:50:03.587519
1640 22:50:03.587608 Set Vref, RX VrefLevel [Byte0]: 70
1641 22:50:03.590693 [Byte1]: 70
1642 22:50:03.595241
1643 22:50:03.595331 Set Vref, RX VrefLevel [Byte0]: 71
1644 22:50:03.598438 [Byte1]: 71
1645 22:50:03.602851
1646 22:50:03.602938 Set Vref, RX VrefLevel [Byte0]: 72
1647 22:50:03.606141 [Byte1]: 72
1648 22:50:03.610471
1649 22:50:03.610558 Set Vref, RX VrefLevel [Byte0]: 73
1650 22:50:03.613670 [Byte1]: 73
1651 22:50:03.617926
1652 22:50:03.618060 Set Vref, RX VrefLevel [Byte0]: 74
1653 22:50:03.621307 [Byte1]: 74
1654 22:50:03.625597
1655 22:50:03.625685 Set Vref, RX VrefLevel [Byte0]: 75
1656 22:50:03.628720 [Byte1]: 75
1657 22:50:03.633046
1658 22:50:03.633132 Final RX Vref Byte 0 = 57 to rank0
1659 22:50:03.636258 Final RX Vref Byte 1 = 57 to rank0
1660 22:50:03.639604 Final RX Vref Byte 0 = 57 to rank1
1661 22:50:03.643005 Final RX Vref Byte 1 = 57 to rank1==
1662 22:50:03.646248 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 22:50:03.652827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1664 22:50:03.652939 ==
1665 22:50:03.653003 DQS Delay:
1666 22:50:03.653063 DQS0 = 0, DQS1 = 0
1667 22:50:03.656336 DQM Delay:
1668 22:50:03.656418 DQM0 = 81, DQM1 = 74
1669 22:50:03.659494 DQ Delay:
1670 22:50:03.662841 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1671 22:50:03.666252 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1672 22:50:03.669491 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1673 22:50:03.672843 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1674 22:50:03.672931
1675 22:50:03.672994
1676 22:50:03.680218 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1677 22:50:03.683896 CH1 RK0: MR19=606, MR18=4D4D
1678 22:50:03.687251 CH1_RK0: MR19=0x606, MR18=0x4D4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1679 22:50:03.687339
1680 22:50:03.690437 ----->DramcWriteLeveling(PI) begin...
1681 22:50:03.693941 ==
1682 22:50:03.697043 Dram Type= 6, Freq= 0, CH_1, rank 1
1683 22:50:03.700446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1684 22:50:03.700533 ==
1685 22:50:03.703776 Write leveling (Byte 0): 26 => 26
1686 22:50:03.707191 Write leveling (Byte 1): 26 => 26
1687 22:50:03.710614 DramcWriteLeveling(PI) end<-----
1688 22:50:03.710702
1689 22:50:03.710766 ==
1690 22:50:03.713900 Dram Type= 6, Freq= 0, CH_1, rank 1
1691 22:50:03.717154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1692 22:50:03.717256 ==
1693 22:50:03.720629 [Gating] SW mode calibration
1694 22:50:03.727384 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1695 22:50:03.730784 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1696 22:50:03.737160 0 6 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
1697 22:50:03.740598 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 22:50:03.743888 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 22:50:03.750448 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 22:50:03.753760 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1701 22:50:03.757027 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1702 22:50:03.763759 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 22:50:03.767091 0 6 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1704 22:50:03.770742 0 7 0 | B1->B0 | 3434 4646 | 1 0 | (1 1) (0 0)
1705 22:50:03.777186 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 22:50:03.780566 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 22:50:03.783785 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 22:50:03.790598 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 22:50:03.793839 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1710 22:50:03.797219 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 22:50:03.803952 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1712 22:50:03.807343 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1713 22:50:03.810587 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 22:50:03.814217 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 22:50:03.820460 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 22:50:03.824032 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 22:50:03.827048 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 22:50:03.833599 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 22:50:03.837182 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 22:50:03.840333 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 22:50:03.846920 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 22:50:03.850392 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 22:50:03.853787 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 22:50:03.860383 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 22:50:03.863668 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 22:50:03.867117 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 22:50:03.873587 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1728 22:50:03.877036 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1729 22:50:03.880501 Total UI for P1: 0, mck2ui 16
1730 22:50:03.883917 best dqsien dly found for B0: ( 0, 9, 28)
1731 22:50:03.886836 Total UI for P1: 0, mck2ui 16
1732 22:50:03.890225 best dqsien dly found for B1: ( 0, 9, 28)
1733 22:50:03.893752 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1734 22:50:03.896932 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1735 22:50:03.897023
1736 22:50:03.900315 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1737 22:50:03.903543 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1738 22:50:03.906790 [Gating] SW calibration Done
1739 22:50:03.906878 ==
1740 22:50:03.910391 Dram Type= 6, Freq= 0, CH_1, rank 1
1741 22:50:03.913874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1742 22:50:03.917006 ==
1743 22:50:03.917099 RX Vref Scan: 0
1744 22:50:03.917165
1745 22:50:03.920313 RX Vref 0 -> 0, step: 1
1746 22:50:03.920398
1747 22:50:03.923978 RX Delay -130 -> 252, step: 16
1748 22:50:03.926856 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1749 22:50:03.930212 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1750 22:50:03.933960 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1751 22:50:03.936782 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1752 22:50:03.943479 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1753 22:50:03.946865 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1754 22:50:03.950343 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1755 22:50:03.953426 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1756 22:50:03.956900 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1757 22:50:03.963584 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1758 22:50:03.966746 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1759 22:50:03.970610 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1760 22:50:03.973544 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1761 22:50:03.976915 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1762 22:50:03.983558 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1763 22:50:03.987011 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1764 22:50:03.987105 ==
1765 22:50:03.990413 Dram Type= 6, Freq= 0, CH_1, rank 1
1766 22:50:03.993579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1767 22:50:03.993666 ==
1768 22:50:03.997102 DQS Delay:
1769 22:50:03.997186 DQS0 = 0, DQS1 = 0
1770 22:50:03.997252 DQM Delay:
1771 22:50:04.000189 DQM0 = 85, DQM1 = 75
1772 22:50:04.000272 DQ Delay:
1773 22:50:04.003570 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1774 22:50:04.006713 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1775 22:50:04.009856 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1776 22:50:04.013413 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1777 22:50:04.013501
1778 22:50:04.013566
1779 22:50:04.013626 ==
1780 22:50:04.016805 Dram Type= 6, Freq= 0, CH_1, rank 1
1781 22:50:04.023288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1782 22:50:04.023388 ==
1783 22:50:04.023456
1784 22:50:04.023517
1785 22:50:04.023575 TX Vref Scan disable
1786 22:50:04.026801 == TX Byte 0 ==
1787 22:50:04.030086 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1788 22:50:04.036841 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1789 22:50:04.036945 == TX Byte 1 ==
1790 22:50:04.039955 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1791 22:50:04.046608 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1792 22:50:04.046718 ==
1793 22:50:04.050324 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 22:50:04.053100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1795 22:50:04.053195 ==
1796 22:50:04.065844 TX Vref=22, minBit 0, minWin=27, winSum=448
1797 22:50:04.069026 TX Vref=24, minBit 0, minWin=28, winSum=454
1798 22:50:04.072255 TX Vref=26, minBit 8, minWin=27, winSum=452
1799 22:50:04.075859 TX Vref=28, minBit 0, minWin=28, winSum=458
1800 22:50:04.079174 TX Vref=30, minBit 9, minWin=27, winSum=455
1801 22:50:04.082154 TX Vref=32, minBit 9, minWin=27, winSum=454
1802 22:50:04.088718 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1803 22:50:04.088820
1804 22:50:04.092279 Final TX Range 1 Vref 28
1805 22:50:04.092365
1806 22:50:04.092429 ==
1807 22:50:04.095555 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 22:50:04.099142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1809 22:50:04.099228 ==
1810 22:50:04.099292
1811 22:50:04.099350
1812 22:50:04.102247 TX Vref Scan disable
1813 22:50:04.105919 == TX Byte 0 ==
1814 22:50:04.109015 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1815 22:50:04.112455 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1816 22:50:04.115693 == TX Byte 1 ==
1817 22:50:04.118865 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1818 22:50:04.122301 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1819 22:50:04.122403
1820 22:50:04.125760 [DATLAT]
1821 22:50:04.125843 Freq=800, CH1 RK1
1822 22:50:04.125906
1823 22:50:04.129141 DATLAT Default: 0x9
1824 22:50:04.129224 0, 0xFFFF, sum = 0
1825 22:50:04.132228 1, 0xFFFF, sum = 0
1826 22:50:04.132314 2, 0xFFFF, sum = 0
1827 22:50:04.135817 3, 0xFFFF, sum = 0
1828 22:50:04.135902 4, 0xFFFF, sum = 0
1829 22:50:04.138928 5, 0xFFFF, sum = 0
1830 22:50:04.139012 6, 0xFFFF, sum = 0
1831 22:50:04.142525 7, 0xFFFF, sum = 0
1832 22:50:04.142610 8, 0x0, sum = 1
1833 22:50:04.145594 9, 0x0, sum = 2
1834 22:50:04.145682 10, 0x0, sum = 3
1835 22:50:04.148933 11, 0x0, sum = 4
1836 22:50:04.149020 best_step = 9
1837 22:50:04.149085
1838 22:50:04.149145 ==
1839 22:50:04.152225 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 22:50:04.159015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1841 22:50:04.159118 ==
1842 22:50:04.159184 RX Vref Scan: 0
1843 22:50:04.159245
1844 22:50:04.162228 RX Vref 0 -> 0, step: 1
1845 22:50:04.162312
1846 22:50:04.165522 RX Delay -95 -> 252, step: 8
1847 22:50:04.168771 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1848 22:50:04.172420 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1849 22:50:04.175531 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1850 22:50:04.182280 iDelay=217, Bit 3, Center 80 (-31 ~ 192) 224
1851 22:50:04.185587 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1852 22:50:04.188871 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1853 22:50:04.192313 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1854 22:50:04.195428 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1855 22:50:04.202302 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1856 22:50:04.205730 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1857 22:50:04.209195 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1858 22:50:04.212243 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1859 22:50:04.215382 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1860 22:50:04.222189 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1861 22:50:04.225465 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1862 22:50:04.228745 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1863 22:50:04.228833 ==
1864 22:50:04.232031 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 22:50:04.235367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1866 22:50:04.238666 ==
1867 22:50:04.238751 DQS Delay:
1868 22:50:04.238814 DQS0 = 0, DQS1 = 0
1869 22:50:04.242001 DQM Delay:
1870 22:50:04.242148 DQM0 = 84, DQM1 = 74
1871 22:50:04.245412 DQ Delay:
1872 22:50:04.245498 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =80
1873 22:50:04.248690 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1874 22:50:04.252222 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1875 22:50:04.255474 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1876 22:50:04.255563
1877 22:50:04.258895
1878 22:50:04.265353 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1879 22:50:04.268837 CH1 RK1: MR19=606, MR18=3D3D
1880 22:50:04.275342 CH1_RK1: MR19=0x606, MR18=0x3D3D, DQSOSC=394, MR23=63, INC=95, DEC=63
1881 22:50:04.275450 [RxdqsGatingPostProcess] freq 800
1882 22:50:04.282126 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1883 22:50:04.285388 Pre-setting of DQS Precalculation
1884 22:50:04.288718 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1885 22:50:04.298805 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1886 22:50:04.305341 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1887 22:50:04.305455
1888 22:50:04.305521
1889 22:50:04.308739 [Calibration Summary] 1600 Mbps
1890 22:50:04.308857 CH 0, Rank 0
1891 22:50:04.312100 SW Impedance : PASS
1892 22:50:04.312182 DUTY Scan : NO K
1893 22:50:04.315330 ZQ Calibration : PASS
1894 22:50:04.318957 Jitter Meter : NO K
1895 22:50:04.319042 CBT Training : PASS
1896 22:50:04.321985 Write leveling : PASS
1897 22:50:04.325341 RX DQS gating : PASS
1898 22:50:04.325424 RX DQ/DQS(RDDQC) : PASS
1899 22:50:04.328604 TX DQ/DQS : PASS
1900 22:50:04.332160 RX DATLAT : PASS
1901 22:50:04.332244 RX DQ/DQS(Engine): PASS
1902 22:50:04.335137 TX OE : NO K
1903 22:50:04.335220 All Pass.
1904 22:50:04.335285
1905 22:50:04.338508 CH 0, Rank 1
1906 22:50:04.338591 SW Impedance : PASS
1907 22:50:04.341819 DUTY Scan : NO K
1908 22:50:04.345236 ZQ Calibration : PASS
1909 22:50:04.345325 Jitter Meter : NO K
1910 22:50:04.348862 CBT Training : PASS
1911 22:50:04.348947 Write leveling : PASS
1912 22:50:04.351970 RX DQS gating : PASS
1913 22:50:04.355153 RX DQ/DQS(RDDQC) : PASS
1914 22:50:04.355238 TX DQ/DQS : PASS
1915 22:50:04.358999 RX DATLAT : PASS
1916 22:50:04.361942 RX DQ/DQS(Engine): PASS
1917 22:50:04.362036 TX OE : NO K
1918 22:50:04.365352 All Pass.
1919 22:50:04.365434
1920 22:50:04.365498 CH 1, Rank 0
1921 22:50:04.368751 SW Impedance : PASS
1922 22:50:04.368892 DUTY Scan : NO K
1923 22:50:04.372134 ZQ Calibration : PASS
1924 22:50:04.375437 Jitter Meter : NO K
1925 22:50:04.375521 CBT Training : PASS
1926 22:50:04.378729 Write leveling : PASS
1927 22:50:04.381838 RX DQS gating : PASS
1928 22:50:04.381921 RX DQ/DQS(RDDQC) : PASS
1929 22:50:04.385484 TX DQ/DQS : PASS
1930 22:50:04.385567 RX DATLAT : PASS
1931 22:50:04.388446 RX DQ/DQS(Engine): PASS
1932 22:50:04.391812 TX OE : NO K
1933 22:50:04.391896 All Pass.
1934 22:50:04.391960
1935 22:50:04.392020 CH 1, Rank 1
1936 22:50:04.395269 SW Impedance : PASS
1937 22:50:04.398570 DUTY Scan : NO K
1938 22:50:04.398655 ZQ Calibration : PASS
1939 22:50:04.401833 Jitter Meter : NO K
1940 22:50:04.405101 CBT Training : PASS
1941 22:50:04.405185 Write leveling : PASS
1942 22:50:04.408608 RX DQS gating : PASS
1943 22:50:04.412009 RX DQ/DQS(RDDQC) : PASS
1944 22:50:04.412094 TX DQ/DQS : PASS
1945 22:50:04.415349 RX DATLAT : PASS
1946 22:50:04.418534 RX DQ/DQS(Engine): PASS
1947 22:50:04.418617 TX OE : NO K
1948 22:50:04.421898 All Pass.
1949 22:50:04.421996
1950 22:50:04.422112 DramC Write-DBI off
1951 22:50:04.425145 PER_BANK_REFRESH: Hybrid Mode
1952 22:50:04.425227 TX_TRACKING: ON
1953 22:50:04.428393 [GetDramInforAfterCalByMRR] Vendor 6.
1954 22:50:04.435147 [GetDramInforAfterCalByMRR] Revision 606.
1955 22:50:04.438427 [GetDramInforAfterCalByMRR] Revision 2 0.
1956 22:50:04.438517 MR0 0x3939
1957 22:50:04.438581 MR8 0x1111
1958 22:50:04.441881 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1959 22:50:04.441963
1960 22:50:04.445150 MR0 0x3939
1961 22:50:04.445257 MR8 0x1111
1962 22:50:04.448626 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1963 22:50:04.448741
1964 22:50:04.458450 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1965 22:50:04.462263 [FAST_K] Save calibration result to emmc
1966 22:50:04.465352 [FAST_K] Save calibration result to emmc
1967 22:50:04.468589 dram_init: config_dvfs: 1
1968 22:50:04.471793 dramc_set_vcore_voltage set vcore to 662500
1969 22:50:04.475216 Read voltage for 1200, 2
1970 22:50:04.475301 Vio18 = 0
1971 22:50:04.475369 Vcore = 662500
1972 22:50:04.478497 Vdram = 0
1973 22:50:04.478578 Vddq = 0
1974 22:50:04.478642 Vmddr = 0
1975 22:50:04.485236 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1976 22:50:04.488749 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1977 22:50:04.491927 MEM_TYPE=3, freq_sel=15
1978 22:50:04.495182 sv_algorithm_assistance_LP4_1600
1979 22:50:04.498677 ============ PULL DRAM RESETB DOWN ============
1980 22:50:04.502416 ========== PULL DRAM RESETB DOWN end =========
1981 22:50:04.508610 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1982 22:50:04.512065 ===================================
1983 22:50:04.512155 LPDDR4 DRAM CONFIGURATION
1984 22:50:04.515384 ===================================
1985 22:50:04.518630 EX_ROW_EN[0] = 0x0
1986 22:50:04.518715 EX_ROW_EN[1] = 0x0
1987 22:50:04.522349 LP4Y_EN = 0x0
1988 22:50:04.522432 WORK_FSP = 0x0
1989 22:50:04.525586 WL = 0x4
1990 22:50:04.525668 RL = 0x4
1991 22:50:04.529012 BL = 0x2
1992 22:50:04.532163 RPST = 0x0
1993 22:50:04.532248 RD_PRE = 0x0
1994 22:50:04.535295 WR_PRE = 0x1
1995 22:50:04.535378 WR_PST = 0x0
1996 22:50:04.538960 DBI_WR = 0x0
1997 22:50:04.539044 DBI_RD = 0x0
1998 22:50:04.542399 OTF = 0x1
1999 22:50:04.545395 ===================================
2000 22:50:04.548679 ===================================
2001 22:50:04.548780 ANA top config
2002 22:50:04.551807 ===================================
2003 22:50:04.555341 DLL_ASYNC_EN = 0
2004 22:50:04.558604 ALL_SLAVE_EN = 0
2005 22:50:04.558688 NEW_RANK_MODE = 1
2006 22:50:04.561800 DLL_IDLE_MODE = 1
2007 22:50:04.565283 LP45_APHY_COMB_EN = 1
2008 22:50:04.568718 TX_ODT_DIS = 1
2009 22:50:04.568805 NEW_8X_MODE = 1
2010 22:50:04.571874 ===================================
2011 22:50:04.575087 ===================================
2012 22:50:04.578524 data_rate = 2400
2013 22:50:04.581839 CKR = 1
2014 22:50:04.585102 DQ_P2S_RATIO = 8
2015 22:50:04.588661 ===================================
2016 22:50:04.591936 CA_P2S_RATIO = 8
2017 22:50:04.595217 DQ_CA_OPEN = 0
2018 22:50:04.595375 DQ_SEMI_OPEN = 0
2019 22:50:04.598547 CA_SEMI_OPEN = 0
2020 22:50:04.601684 CA_FULL_RATE = 0
2021 22:50:04.605025 DQ_CKDIV4_EN = 0
2022 22:50:04.608296 CA_CKDIV4_EN = 0
2023 22:50:04.611541 CA_PREDIV_EN = 0
2024 22:50:04.611626 PH8_DLY = 17
2025 22:50:04.615017 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2026 22:50:04.618329 DQ_AAMCK_DIV = 4
2027 22:50:04.621578 CA_AAMCK_DIV = 4
2028 22:50:04.624914 CA_ADMCK_DIV = 4
2029 22:50:04.628253 DQ_TRACK_CA_EN = 0
2030 22:50:04.631643 CA_PICK = 1200
2031 22:50:04.631729 CA_MCKIO = 1200
2032 22:50:04.635012 MCKIO_SEMI = 0
2033 22:50:04.638557 PLL_FREQ = 2366
2034 22:50:04.641671 DQ_UI_PI_RATIO = 32
2035 22:50:04.645083 CA_UI_PI_RATIO = 0
2036 22:50:04.648205 ===================================
2037 22:50:04.651846 ===================================
2038 22:50:04.654861 memory_type:LPDDR4
2039 22:50:04.654962 GP_NUM : 10
2040 22:50:04.658235 SRAM_EN : 1
2041 22:50:04.658320 MD32_EN : 0
2042 22:50:04.661598 ===================================
2043 22:50:04.664768 [ANA_INIT] >>>>>>>>>>>>>>
2044 22:50:04.668162 <<<<<< [CONFIGURE PHASE]: ANA_TX
2045 22:50:04.671573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2046 22:50:04.675035 ===================================
2047 22:50:04.678133 data_rate = 2400,PCW = 0X5b00
2048 22:50:04.681416 ===================================
2049 22:50:04.684816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2050 22:50:04.688227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2051 22:50:04.694817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2052 22:50:04.701344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2053 22:50:04.704858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2054 22:50:04.708089 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2055 22:50:04.708177 [ANA_INIT] flow start
2056 22:50:04.711548 [ANA_INIT] PLL >>>>>>>>
2057 22:50:04.715134 [ANA_INIT] PLL <<<<<<<<
2058 22:50:04.715220 [ANA_INIT] MIDPI >>>>>>>>
2059 22:50:04.718215 [ANA_INIT] MIDPI <<<<<<<<
2060 22:50:04.721801 [ANA_INIT] DLL >>>>>>>>
2061 22:50:04.721888 [ANA_INIT] DLL <<<<<<<<
2062 22:50:04.724765 [ANA_INIT] flow end
2063 22:50:04.728266 ============ LP4 DIFF to SE enter ============
2064 22:50:04.731395 ============ LP4 DIFF to SE exit ============
2065 22:50:04.734613 [ANA_INIT] <<<<<<<<<<<<<
2066 22:50:04.738155 [Flow] Enable top DCM control >>>>>
2067 22:50:04.741189 [Flow] Enable top DCM control <<<<<
2068 22:50:04.744995 Enable DLL master slave shuffle
2069 22:50:04.751427 ==============================================================
2070 22:50:04.751543 Gating Mode config
2071 22:50:04.757979 ==============================================================
2072 22:50:04.758128 Config description:
2073 22:50:04.768402 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2074 22:50:04.774617 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2075 22:50:04.781342 SELPH_MODE 0: By rank 1: By Phase
2076 22:50:04.784731 ==============================================================
2077 22:50:04.787971 GAT_TRACK_EN = 1
2078 22:50:04.791408 RX_GATING_MODE = 2
2079 22:50:04.794836 RX_GATING_TRACK_MODE = 2
2080 22:50:04.798032 SELPH_MODE = 1
2081 22:50:04.801639 PICG_EARLY_EN = 1
2082 22:50:04.805084 VALID_LAT_VALUE = 1
2083 22:50:04.808285 ==============================================================
2084 22:50:04.811704 Enter into Gating configuration >>>>
2085 22:50:04.814804 Exit from Gating configuration <<<<
2086 22:50:04.818312 Enter into DVFS_PRE_config >>>>>
2087 22:50:04.831414 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2088 22:50:04.834874 Exit from DVFS_PRE_config <<<<<
2089 22:50:04.838333 Enter into PICG configuration >>>>
2090 22:50:04.838424 Exit from PICG configuration <<<<
2091 22:50:04.841921 [RX_INPUT] configuration >>>>>
2092 22:50:04.844873 [RX_INPUT] configuration <<<<<
2093 22:50:04.851486 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2094 22:50:04.854757 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2095 22:50:04.861447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2096 22:50:04.868231 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2097 22:50:04.874726 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2098 22:50:04.881444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2099 22:50:04.885125 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2100 22:50:04.888089 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2101 22:50:04.891682 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2102 22:50:04.898008 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2103 22:50:04.901481 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2104 22:50:04.905217 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2105 22:50:04.908221 ===================================
2106 22:50:04.911334 LPDDR4 DRAM CONFIGURATION
2107 22:50:04.914965 ===================================
2108 22:50:04.918288 EX_ROW_EN[0] = 0x0
2109 22:50:04.918375 EX_ROW_EN[1] = 0x0
2110 22:50:04.921607 LP4Y_EN = 0x0
2111 22:50:04.921710 WORK_FSP = 0x0
2112 22:50:04.924726 WL = 0x4
2113 22:50:04.924810 RL = 0x4
2114 22:50:04.928053 BL = 0x2
2115 22:50:04.928136 RPST = 0x0
2116 22:50:04.931927 RD_PRE = 0x0
2117 22:50:04.932016 WR_PRE = 0x1
2118 22:50:04.934889 WR_PST = 0x0
2119 22:50:04.934975 DBI_WR = 0x0
2120 22:50:04.938065 DBI_RD = 0x0
2121 22:50:04.938165 OTF = 0x1
2122 22:50:04.941597 ===================================
2123 22:50:04.945082 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2124 22:50:04.951637 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2125 22:50:04.954962 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2126 22:50:04.958175 ===================================
2127 22:50:04.961643 LPDDR4 DRAM CONFIGURATION
2128 22:50:04.964666 ===================================
2129 22:50:04.964757 EX_ROW_EN[0] = 0x10
2130 22:50:04.968039 EX_ROW_EN[1] = 0x0
2131 22:50:04.968126 LP4Y_EN = 0x0
2132 22:50:04.971750 WORK_FSP = 0x0
2133 22:50:04.975032 WL = 0x4
2134 22:50:04.975119 RL = 0x4
2135 22:50:04.978086 BL = 0x2
2136 22:50:04.978171 RPST = 0x0
2137 22:50:04.981445 RD_PRE = 0x0
2138 22:50:04.981530 WR_PRE = 0x1
2139 22:50:04.984683 WR_PST = 0x0
2140 22:50:04.984767 DBI_WR = 0x0
2141 22:50:04.987952 DBI_RD = 0x0
2142 22:50:04.988055 OTF = 0x1
2143 22:50:04.991395 ===================================
2144 22:50:04.997958 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2145 22:50:04.998064 ==
2146 22:50:05.001140 Dram Type= 6, Freq= 0, CH_0, rank 0
2147 22:50:05.004733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2148 22:50:05.004822 ==
2149 22:50:05.007920 [Duty_Offset_Calibration]
2150 22:50:05.011229 B0:0 B1:2 CA:1
2151 22:50:05.011313
2152 22:50:05.014396 [DutyScan_Calibration_Flow] k_type=0
2153 22:50:05.022797
2154 22:50:05.022901 ==CLK 0==
2155 22:50:05.026151 Final CLK duty delay cell = 0
2156 22:50:05.029386 [0] MAX Duty = 5093%(X100), DQS PI = 12
2157 22:50:05.032665 [0] MIN Duty = 4938%(X100), DQS PI = 52
2158 22:50:05.032747 [0] AVG Duty = 5015%(X100)
2159 22:50:05.036094
2160 22:50:05.036209 CH0 CLK Duty spec in!! Max-Min= 155%
2161 22:50:05.042721 [DutyScan_Calibration_Flow] ====Done====
2162 22:50:05.042802
2163 22:50:05.046138 [DutyScan_Calibration_Flow] k_type=1
2164 22:50:05.062091
2165 22:50:05.062198 ==DQS 0 ==
2166 22:50:05.065340 Final DQS duty delay cell = 0
2167 22:50:05.068762 [0] MAX Duty = 5125%(X100), DQS PI = 30
2168 22:50:05.072532 [0] MIN Duty = 5031%(X100), DQS PI = 4
2169 22:50:05.072614 [0] AVG Duty = 5078%(X100)
2170 22:50:05.075100
2171 22:50:05.075181 ==DQS 1 ==
2172 22:50:05.078565 Final DQS duty delay cell = 0
2173 22:50:05.081881 [0] MAX Duty = 5062%(X100), DQS PI = 58
2174 22:50:05.085275 [0] MIN Duty = 4906%(X100), DQS PI = 14
2175 22:50:05.088947 [0] AVG Duty = 4984%(X100)
2176 22:50:05.089029
2177 22:50:05.092211 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2178 22:50:05.092294
2179 22:50:05.095230 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2180 22:50:05.098507 [DutyScan_Calibration_Flow] ====Done====
2181 22:50:05.098589
2182 22:50:05.101832 [DutyScan_Calibration_Flow] k_type=3
2183 22:50:05.119031
2184 22:50:05.119113 ==DQM 0 ==
2185 22:50:05.122360 Final DQM duty delay cell = 0
2186 22:50:05.125703 [0] MAX Duty = 5156%(X100), DQS PI = 22
2187 22:50:05.129076 [0] MIN Duty = 4969%(X100), DQS PI = 40
2188 22:50:05.132484 [0] AVG Duty = 5062%(X100)
2189 22:50:05.132565
2190 22:50:05.132628 ==DQM 1 ==
2191 22:50:05.135814 Final DQM duty delay cell = 4
2192 22:50:05.139146 [4] MAX Duty = 5187%(X100), DQS PI = 52
2193 22:50:05.142443 [4] MIN Duty = 5000%(X100), DQS PI = 18
2194 22:50:05.145670 [4] AVG Duty = 5093%(X100)
2195 22:50:05.145755
2196 22:50:05.149207 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2197 22:50:05.149315
2198 22:50:05.152907 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2199 22:50:05.155880 [DutyScan_Calibration_Flow] ====Done====
2200 22:50:05.155962
2201 22:50:05.159052 [DutyScan_Calibration_Flow] k_type=2
2202 22:50:05.174147
2203 22:50:05.174229 ==DQ 0 ==
2204 22:50:05.177554 Final DQ duty delay cell = -4
2205 22:50:05.180781 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2206 22:50:05.184076 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2207 22:50:05.187542 [-4] AVG Duty = 4937%(X100)
2208 22:50:05.187624
2209 22:50:05.187688 ==DQ 1 ==
2210 22:50:05.190895 Final DQ duty delay cell = -4
2211 22:50:05.194302 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2212 22:50:05.197422 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2213 22:50:05.200750 [-4] AVG Duty = 4969%(X100)
2214 22:50:05.200832
2215 22:50:05.204152 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2216 22:50:05.204235
2217 22:50:05.207527 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2218 22:50:05.210677 [DutyScan_Calibration_Flow] ====Done====
2219 22:50:05.210759 ==
2220 22:50:05.214057 Dram Type= 6, Freq= 0, CH_1, rank 0
2221 22:50:05.217298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2222 22:50:05.217381 ==
2223 22:50:05.220794 [Duty_Offset_Calibration]
2224 22:50:05.220876 B0:0 B1:4 CA:-5
2225 22:50:05.220940
2226 22:50:05.223984 [DutyScan_Calibration_Flow] k_type=0
2227 22:50:05.234613
2228 22:50:05.234695 ==CLK 0==
2229 22:50:05.238225 Final CLK duty delay cell = 0
2230 22:50:05.241419 [0] MAX Duty = 5094%(X100), DQS PI = 24
2231 22:50:05.244849 [0] MIN Duty = 4907%(X100), DQS PI = 42
2232 22:50:05.244931 [0] AVG Duty = 5000%(X100)
2233 22:50:05.248266
2234 22:50:05.251267 CH1 CLK Duty spec in!! Max-Min= 187%
2235 22:50:05.254842 [DutyScan_Calibration_Flow] ====Done====
2236 22:50:05.254925
2237 22:50:05.257981 [DutyScan_Calibration_Flow] k_type=1
2238 22:50:05.273304
2239 22:50:05.273399 ==DQS 0 ==
2240 22:50:05.276737 Final DQS duty delay cell = 0
2241 22:50:05.279779 [0] MAX Duty = 5125%(X100), DQS PI = 16
2242 22:50:05.283087 [0] MIN Duty = 4907%(X100), DQS PI = 38
2243 22:50:05.286664 [0] AVG Duty = 5016%(X100)
2244 22:50:05.286746
2245 22:50:05.286810 ==DQS 1 ==
2246 22:50:05.289885 Final DQS duty delay cell = -4
2247 22:50:05.293464 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2248 22:50:05.296704 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2249 22:50:05.299842 [-4] AVG Duty = 4953%(X100)
2250 22:50:05.299924
2251 22:50:05.303244 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2252 22:50:05.303326
2253 22:50:05.306592 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2254 22:50:05.309976 [DutyScan_Calibration_Flow] ====Done====
2255 22:50:05.310065
2256 22:50:05.313232 [DutyScan_Calibration_Flow] k_type=3
2257 22:50:05.328363
2258 22:50:05.328446 ==DQM 0 ==
2259 22:50:05.331745 Final DQM duty delay cell = -4
2260 22:50:05.335087 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2261 22:50:05.338539 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2262 22:50:05.341840 [-4] AVG Duty = 4953%(X100)
2263 22:50:05.341921
2264 22:50:05.341984 ==DQM 1 ==
2265 22:50:05.344913 Final DQM duty delay cell = -4
2266 22:50:05.348441 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2267 22:50:05.351709 [-4] MIN Duty = 4907%(X100), DQS PI = 56
2268 22:50:05.355067 [-4] AVG Duty = 4984%(X100)
2269 22:50:05.355149
2270 22:50:05.358540 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2271 22:50:05.358621
2272 22:50:05.361611 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2273 22:50:05.365373 [DutyScan_Calibration_Flow] ====Done====
2274 22:50:05.365454
2275 22:50:05.368506 [DutyScan_Calibration_Flow] k_type=2
2276 22:50:05.385461
2277 22:50:05.385542 ==DQ 0 ==
2278 22:50:05.388800 Final DQ duty delay cell = 0
2279 22:50:05.392138 [0] MAX Duty = 5093%(X100), DQS PI = 0
2280 22:50:05.395466 [0] MIN Duty = 4938%(X100), DQS PI = 44
2281 22:50:05.395546 [0] AVG Duty = 5015%(X100)
2282 22:50:05.395609
2283 22:50:05.398917 ==DQ 1 ==
2284 22:50:05.402383 Final DQ duty delay cell = 0
2285 22:50:05.405791 [0] MAX Duty = 5000%(X100), DQS PI = 6
2286 22:50:05.408942 [0] MIN Duty = 4907%(X100), DQS PI = 0
2287 22:50:05.409022 [0] AVG Duty = 4953%(X100)
2288 22:50:05.409085
2289 22:50:05.412268 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2290 22:50:05.412348
2291 22:50:05.415467 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2292 22:50:05.422012 [DutyScan_Calibration_Flow] ====Done====
2293 22:50:05.425520 nWR fixed to 30
2294 22:50:05.425600 [ModeRegInit_LP4] CH0 RK0
2295 22:50:05.428790 [ModeRegInit_LP4] CH0 RK1
2296 22:50:05.432138 [ModeRegInit_LP4] CH1 RK0
2297 22:50:05.432219 [ModeRegInit_LP4] CH1 RK1
2298 22:50:05.435495 match AC timing 6
2299 22:50:05.438773 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2300 22:50:05.442140 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2301 22:50:05.448864 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2302 22:50:05.452357 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2303 22:50:05.458816 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2304 22:50:05.458899 ==
2305 22:50:05.462209 Dram Type= 6, Freq= 0, CH_0, rank 0
2306 22:50:05.465494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2307 22:50:05.465576 ==
2308 22:50:05.472227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2309 22:50:05.475729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2310 22:50:05.485134 [CA 0] Center 39 (9~70) winsize 62
2311 22:50:05.488532 [CA 1] Center 39 (8~70) winsize 63
2312 22:50:05.491761 [CA 2] Center 36 (5~67) winsize 63
2313 22:50:05.495136 [CA 3] Center 35 (4~66) winsize 63
2314 22:50:05.498315 [CA 4] Center 34 (3~65) winsize 63
2315 22:50:05.501642 [CA 5] Center 33 (3~64) winsize 62
2316 22:50:05.501723
2317 22:50:05.505041 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2318 22:50:05.505123
2319 22:50:05.508250 [CATrainingPosCal] consider 1 rank data
2320 22:50:05.511886 u2DelayCellTimex100 = 270/100 ps
2321 22:50:05.515153 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2322 22:50:05.518200 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2323 22:50:05.525053 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2324 22:50:05.528507 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2325 22:50:05.531959 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2326 22:50:05.534880 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2327 22:50:05.534962
2328 22:50:05.538286 CA PerBit enable=1, Macro0, CA PI delay=33
2329 22:50:05.538366
2330 22:50:05.541633 [CBTSetCACLKResult] CA Dly = 33
2331 22:50:05.541714 CS Dly: 7 (0~38)
2332 22:50:05.544980 ==
2333 22:50:05.545060 Dram Type= 6, Freq= 0, CH_0, rank 1
2334 22:50:05.551460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2335 22:50:05.551544 ==
2336 22:50:05.554783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2337 22:50:05.561429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2338 22:50:05.570398 [CA 0] Center 39 (8~70) winsize 63
2339 22:50:05.573833 [CA 1] Center 39 (8~70) winsize 63
2340 22:50:05.577387 [CA 2] Center 35 (5~66) winsize 62
2341 22:50:05.580457 [CA 3] Center 35 (4~66) winsize 63
2342 22:50:05.584357 [CA 4] Center 33 (3~64) winsize 62
2343 22:50:05.587267 [CA 5] Center 34 (3~65) winsize 63
2344 22:50:05.587350
2345 22:50:05.590857 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2346 22:50:05.590940
2347 22:50:05.593897 [CATrainingPosCal] consider 2 rank data
2348 22:50:05.597305 u2DelayCellTimex100 = 270/100 ps
2349 22:50:05.600410 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2350 22:50:05.603632 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2351 22:50:05.610571 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2352 22:50:05.613624 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2353 22:50:05.617100 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2354 22:50:05.620545 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2355 22:50:05.620627
2356 22:50:05.623609 CA PerBit enable=1, Macro0, CA PI delay=33
2357 22:50:05.623692
2358 22:50:05.627011 [CBTSetCACLKResult] CA Dly = 33
2359 22:50:05.627093 CS Dly: 7 (0~39)
2360 22:50:05.627159
2361 22:50:05.630425 ----->DramcWriteLeveling(PI) begin...
2362 22:50:05.633590 ==
2363 22:50:05.637010 Dram Type= 6, Freq= 0, CH_0, rank 0
2364 22:50:05.640734 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2365 22:50:05.640817 ==
2366 22:50:05.643780 Write leveling (Byte 0): 29 => 29
2367 22:50:05.647338 Write leveling (Byte 1): 25 => 25
2368 22:50:05.650212 DramcWriteLeveling(PI) end<-----
2369 22:50:05.650307
2370 22:50:05.650370 ==
2371 22:50:05.653703 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 22:50:05.657113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2373 22:50:05.657196 ==
2374 22:50:05.660341 [Gating] SW mode calibration
2375 22:50:05.667225 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2376 22:50:05.670532 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2377 22:50:05.676945 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2378 22:50:05.680505 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2379 22:50:05.683707 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2380 22:50:05.690614 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2381 22:50:05.693657 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2382 22:50:05.697118 0 11 20 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 1)
2383 22:50:05.704040 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 22:50:05.707707 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 22:50:05.710356 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 22:50:05.716959 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 22:50:05.720559 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2388 22:50:05.723730 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2389 22:50:05.730173 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2390 22:50:05.733604 0 12 20 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
2391 22:50:05.736828 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 22:50:05.743562 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 22:50:05.746900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 22:50:05.750227 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 22:50:05.756871 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 22:50:05.760312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2397 22:50:05.763507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2398 22:50:05.770432 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2399 22:50:05.773503 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 22:50:05.776728 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 22:50:05.783650 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 22:50:05.786750 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 22:50:05.790146 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 22:50:05.793545 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 22:50:05.800662 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 22:50:05.803684 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 22:50:05.806820 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 22:50:05.813502 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 22:50:05.816713 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 22:50:05.820153 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 22:50:05.827123 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 22:50:05.830231 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 22:50:05.833818 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 22:50:05.840656 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2415 22:50:05.843735 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2416 22:50:05.847163 Total UI for P1: 0, mck2ui 16
2417 22:50:05.850192 best dqsien dly found for B0: ( 0, 15, 20)
2418 22:50:05.853515 Total UI for P1: 0, mck2ui 16
2419 22:50:05.856823 best dqsien dly found for B1: ( 0, 15, 20)
2420 22:50:05.860275 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2421 22:50:05.863679 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2422 22:50:05.863761
2423 22:50:05.867585 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2424 22:50:05.870286 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2425 22:50:05.873540 [Gating] SW calibration Done
2426 22:50:05.873622 ==
2427 22:50:05.876920 Dram Type= 6, Freq= 0, CH_0, rank 0
2428 22:50:05.880083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2429 22:50:05.883749 ==
2430 22:50:05.883833 RX Vref Scan: 0
2431 22:50:05.883898
2432 22:50:05.886786 RX Vref 0 -> 0, step: 1
2433 22:50:05.886871
2434 22:50:05.886937 RX Delay -40 -> 252, step: 8
2435 22:50:05.893579 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2436 22:50:05.896982 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2437 22:50:05.900191 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2438 22:50:05.903649 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2439 22:50:05.906818 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2440 22:50:05.913455 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2441 22:50:05.917533 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2442 22:50:05.920219 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2443 22:50:05.923658 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2444 22:50:05.927269 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2445 22:50:05.934008 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2446 22:50:05.937206 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2447 22:50:05.940240 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2448 22:50:05.943584 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2449 22:50:05.947208 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2450 22:50:05.953453 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2451 22:50:05.953581 ==
2452 22:50:05.956854 Dram Type= 6, Freq= 0, CH_0, rank 0
2453 22:50:05.960289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2454 22:50:05.960387 ==
2455 22:50:05.960454 DQS Delay:
2456 22:50:05.963731 DQS0 = 0, DQS1 = 0
2457 22:50:05.963816 DQM Delay:
2458 22:50:05.966683 DQM0 = 115, DQM1 = 106
2459 22:50:05.966769 DQ Delay:
2460 22:50:05.970272 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2461 22:50:05.973479 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2462 22:50:05.976923 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2463 22:50:05.980090 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2464 22:50:05.980174
2465 22:50:05.980237
2466 22:50:05.983358 ==
2467 22:50:05.983440 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 22:50:05.990130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2469 22:50:05.990213 ==
2470 22:50:05.990277
2471 22:50:05.990336
2472 22:50:05.993629 TX Vref Scan disable
2473 22:50:05.993709 == TX Byte 0 ==
2474 22:50:05.996725 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2475 22:50:06.003221 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2476 22:50:06.003309 == TX Byte 1 ==
2477 22:50:06.006811 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2478 22:50:06.013296 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2479 22:50:06.013380 ==
2480 22:50:06.016667 Dram Type= 6, Freq= 0, CH_0, rank 0
2481 22:50:06.020030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2482 22:50:06.020113 ==
2483 22:50:06.032024 TX Vref=22, minBit 9, minWin=25, winSum=413
2484 22:50:06.035389 TX Vref=24, minBit 9, minWin=25, winSum=420
2485 22:50:06.038560 TX Vref=26, minBit 9, minWin=25, winSum=422
2486 22:50:06.041994 TX Vref=28, minBit 8, minWin=26, winSum=434
2487 22:50:06.045274 TX Vref=30, minBit 8, minWin=26, winSum=434
2488 22:50:06.048695 TX Vref=32, minBit 8, minWin=26, winSum=437
2489 22:50:06.055092 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 32
2490 22:50:06.055192
2491 22:50:06.058497 Final TX Range 1 Vref 32
2492 22:50:06.058589
2493 22:50:06.058653 ==
2494 22:50:06.061902 Dram Type= 6, Freq= 0, CH_0, rank 0
2495 22:50:06.065263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2496 22:50:06.065348 ==
2497 22:50:06.065412
2498 22:50:06.068492
2499 22:50:06.068574 TX Vref Scan disable
2500 22:50:06.071826 == TX Byte 0 ==
2501 22:50:06.075375 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2502 22:50:06.078621 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2503 22:50:06.082014 == TX Byte 1 ==
2504 22:50:06.085262 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2505 22:50:06.088633 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2506 22:50:06.088717
2507 22:50:06.091842 [DATLAT]
2508 22:50:06.091924 Freq=1200, CH0 RK0
2509 22:50:06.091989
2510 22:50:06.095177 DATLAT Default: 0xd
2511 22:50:06.095259 0, 0xFFFF, sum = 0
2512 22:50:06.098441 1, 0xFFFF, sum = 0
2513 22:50:06.098526 2, 0xFFFF, sum = 0
2514 22:50:06.101949 3, 0xFFFF, sum = 0
2515 22:50:06.102047 4, 0xFFFF, sum = 0
2516 22:50:06.105213 5, 0xFFFF, sum = 0
2517 22:50:06.105298 6, 0xFFFF, sum = 0
2518 22:50:06.108416 7, 0xFFFF, sum = 0
2519 22:50:06.112167 8, 0xFFFF, sum = 0
2520 22:50:06.112252 9, 0xFFFF, sum = 0
2521 22:50:06.115236 10, 0xFFFF, sum = 0
2522 22:50:06.115319 11, 0x0, sum = 1
2523 22:50:06.115384 12, 0x0, sum = 2
2524 22:50:06.118579 13, 0x0, sum = 3
2525 22:50:06.118663 14, 0x0, sum = 4
2526 22:50:06.121976 best_step = 12
2527 22:50:06.122098
2528 22:50:06.122162 ==
2529 22:50:06.125173 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 22:50:06.128390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2531 22:50:06.128497 ==
2532 22:50:06.131998 RX Vref Scan: 1
2533 22:50:06.132079
2534 22:50:06.132143 Set Vref Range= 32 -> 127
2535 22:50:06.135200
2536 22:50:06.135281 RX Vref 32 -> 127, step: 1
2537 22:50:06.135345
2538 22:50:06.138683 RX Delay -21 -> 252, step: 4
2539 22:50:06.138764
2540 22:50:06.141821 Set Vref, RX VrefLevel [Byte0]: 32
2541 22:50:06.145006 [Byte1]: 32
2542 22:50:06.148454
2543 22:50:06.148538 Set Vref, RX VrefLevel [Byte0]: 33
2544 22:50:06.151830 [Byte1]: 33
2545 22:50:06.156322
2546 22:50:06.156441 Set Vref, RX VrefLevel [Byte0]: 34
2547 22:50:06.159702 [Byte1]: 34
2548 22:50:06.164299
2549 22:50:06.164379 Set Vref, RX VrefLevel [Byte0]: 35
2550 22:50:06.167528 [Byte1]: 35
2551 22:50:06.172311
2552 22:50:06.172396 Set Vref, RX VrefLevel [Byte0]: 36
2553 22:50:06.175755 [Byte1]: 36
2554 22:50:06.180230
2555 22:50:06.180314 Set Vref, RX VrefLevel [Byte0]: 37
2556 22:50:06.183412 [Byte1]: 37
2557 22:50:06.188636
2558 22:50:06.188717 Set Vref, RX VrefLevel [Byte0]: 38
2559 22:50:06.191301 [Byte1]: 38
2560 22:50:06.195913
2561 22:50:06.196015 Set Vref, RX VrefLevel [Byte0]: 39
2562 22:50:06.199157 [Byte1]: 39
2563 22:50:06.204022
2564 22:50:06.204104 Set Vref, RX VrefLevel [Byte0]: 40
2565 22:50:06.207192 [Byte1]: 40
2566 22:50:06.211827
2567 22:50:06.211908 Set Vref, RX VrefLevel [Byte0]: 41
2568 22:50:06.215159 [Byte1]: 41
2569 22:50:06.219756
2570 22:50:06.219838 Set Vref, RX VrefLevel [Byte0]: 42
2571 22:50:06.223119 [Byte1]: 42
2572 22:50:06.227691
2573 22:50:06.227772 Set Vref, RX VrefLevel [Byte0]: 43
2574 22:50:06.231008 [Byte1]: 43
2575 22:50:06.235512
2576 22:50:06.235593 Set Vref, RX VrefLevel [Byte0]: 44
2577 22:50:06.238965 [Byte1]: 44
2578 22:50:06.243376
2579 22:50:06.243457 Set Vref, RX VrefLevel [Byte0]: 45
2580 22:50:06.246675 [Byte1]: 45
2581 22:50:06.251742
2582 22:50:06.251827 Set Vref, RX VrefLevel [Byte0]: 46
2583 22:50:06.254845 [Byte1]: 46
2584 22:50:06.259752
2585 22:50:06.259836 Set Vref, RX VrefLevel [Byte0]: 47
2586 22:50:06.262704 [Byte1]: 47
2587 22:50:06.267392
2588 22:50:06.267474 Set Vref, RX VrefLevel [Byte0]: 48
2589 22:50:06.270584 [Byte1]: 48
2590 22:50:06.275101
2591 22:50:06.275182 Set Vref, RX VrefLevel [Byte0]: 49
2592 22:50:06.278425 [Byte1]: 49
2593 22:50:06.283195
2594 22:50:06.283278 Set Vref, RX VrefLevel [Byte0]: 50
2595 22:50:06.289549 [Byte1]: 50
2596 22:50:06.289635
2597 22:50:06.293082 Set Vref, RX VrefLevel [Byte0]: 51
2598 22:50:06.296247 [Byte1]: 51
2599 22:50:06.296330
2600 22:50:06.299777 Set Vref, RX VrefLevel [Byte0]: 52
2601 22:50:06.302803 [Byte1]: 52
2602 22:50:06.306998
2603 22:50:06.307082 Set Vref, RX VrefLevel [Byte0]: 53
2604 22:50:06.310161 [Byte1]: 53
2605 22:50:06.314935
2606 22:50:06.315017 Set Vref, RX VrefLevel [Byte0]: 54
2607 22:50:06.318201 [Byte1]: 54
2608 22:50:06.322684
2609 22:50:06.322766 Set Vref, RX VrefLevel [Byte0]: 55
2610 22:50:06.325997 [Byte1]: 55
2611 22:50:06.330640
2612 22:50:06.330721 Set Vref, RX VrefLevel [Byte0]: 56
2613 22:50:06.334020 [Byte1]: 56
2614 22:50:06.338853
2615 22:50:06.338935 Set Vref, RX VrefLevel [Byte0]: 57
2616 22:50:06.342160 [Byte1]: 57
2617 22:50:06.346498
2618 22:50:06.346580 Set Vref, RX VrefLevel [Byte0]: 58
2619 22:50:06.349840 [Byte1]: 58
2620 22:50:06.354506
2621 22:50:06.354594 Set Vref, RX VrefLevel [Byte0]: 59
2622 22:50:06.357901 [Byte1]: 59
2623 22:50:06.362379
2624 22:50:06.362463 Set Vref, RX VrefLevel [Byte0]: 60
2625 22:50:06.365657 [Byte1]: 60
2626 22:50:06.370254
2627 22:50:06.370336 Set Vref, RX VrefLevel [Byte0]: 61
2628 22:50:06.373713 [Byte1]: 61
2629 22:50:06.378239
2630 22:50:06.378322 Set Vref, RX VrefLevel [Byte0]: 62
2631 22:50:06.381484 [Byte1]: 62
2632 22:50:06.386406
2633 22:50:06.386489 Set Vref, RX VrefLevel [Byte0]: 63
2634 22:50:06.389642 [Byte1]: 63
2635 22:50:06.394387
2636 22:50:06.394471 Set Vref, RX VrefLevel [Byte0]: 64
2637 22:50:06.397434 [Byte1]: 64
2638 22:50:06.401940
2639 22:50:06.402085 Set Vref, RX VrefLevel [Byte0]: 65
2640 22:50:06.405334 [Byte1]: 65
2641 22:50:06.409901
2642 22:50:06.409982 Set Vref, RX VrefLevel [Byte0]: 66
2643 22:50:06.413168 [Byte1]: 66
2644 22:50:06.417947
2645 22:50:06.418058 Set Vref, RX VrefLevel [Byte0]: 67
2646 22:50:06.421034 [Byte1]: 67
2647 22:50:06.425601
2648 22:50:06.425684 Final RX Vref Byte 0 = 47 to rank0
2649 22:50:06.429070 Final RX Vref Byte 1 = 49 to rank0
2650 22:50:06.432316 Final RX Vref Byte 0 = 47 to rank1
2651 22:50:06.435841 Final RX Vref Byte 1 = 49 to rank1==
2652 22:50:06.439027 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 22:50:06.445776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2654 22:50:06.445863 ==
2655 22:50:06.445928 DQS Delay:
2656 22:50:06.445988 DQS0 = 0, DQS1 = 0
2657 22:50:06.448965 DQM Delay:
2658 22:50:06.449047 DQM0 = 114, DQM1 = 105
2659 22:50:06.452474 DQ Delay:
2660 22:50:06.456003 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2661 22:50:06.459037 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2662 22:50:06.462391 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2663 22:50:06.465789 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2664 22:50:06.465871
2665 22:50:06.465934
2666 22:50:06.472177 [DQSOSCAuto] RK0, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2667 22:50:06.475640 CH0 RK0: MR19=404, MR18=909
2668 22:50:06.482381 CH0_RK0: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
2669 22:50:06.482465
2670 22:50:06.485867 ----->DramcWriteLeveling(PI) begin...
2671 22:50:06.485977 ==
2672 22:50:06.488901 Dram Type= 6, Freq= 0, CH_0, rank 1
2673 22:50:06.492443 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2674 22:50:06.492526 ==
2675 22:50:06.495561 Write leveling (Byte 0): 27 => 27
2676 22:50:06.499072 Write leveling (Byte 1): 24 => 24
2677 22:50:06.502350 DramcWriteLeveling(PI) end<-----
2678 22:50:06.502432
2679 22:50:06.502496 ==
2680 22:50:06.507214 Dram Type= 6, Freq= 0, CH_0, rank 1
2681 22:50:06.509288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2682 22:50:06.512432 ==
2683 22:50:06.512672 [Gating] SW mode calibration
2684 22:50:06.522517 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2685 22:50:06.525704 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2686 22:50:06.528884 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2687 22:50:06.535620 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2688 22:50:06.538781 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2689 22:50:06.542151 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2690 22:50:06.548774 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2691 22:50:06.552237 0 11 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2692 22:50:06.555618 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 22:50:06.562269 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2694 22:50:06.565411 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2695 22:50:06.568744 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2696 22:50:06.575661 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2697 22:50:06.578760 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2698 22:50:06.582158 0 12 16 | B1->B0 | 2727 3a3a | 0 0 | (0 0) (0 0)
2699 22:50:06.588878 0 12 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2700 22:50:06.592118 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2701 22:50:06.595413 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2702 22:50:06.602087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2703 22:50:06.605624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2704 22:50:06.608811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2705 22:50:06.612090 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2706 22:50:06.618644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2707 22:50:06.621986 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2708 22:50:06.625248 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 22:50:06.632128 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 22:50:06.635734 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 22:50:06.638605 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 22:50:06.645554 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 22:50:06.648967 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 22:50:06.651933 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 22:50:06.658588 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 22:50:06.662185 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 22:50:06.665328 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 22:50:06.672191 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 22:50:06.675281 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 22:50:06.678692 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 22:50:06.685320 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 22:50:06.688641 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2723 22:50:06.691869 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2724 22:50:06.695174 Total UI for P1: 0, mck2ui 16
2725 22:50:06.699129 best dqsien dly found for B0: ( 0, 15, 16)
2726 22:50:06.705260 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2727 22:50:06.705345 Total UI for P1: 0, mck2ui 16
2728 22:50:06.708631 best dqsien dly found for B1: ( 0, 15, 18)
2729 22:50:06.715187 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2730 22:50:06.718544 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2731 22:50:06.718628
2732 22:50:06.721994 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2733 22:50:06.725282 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2734 22:50:06.728598 [Gating] SW calibration Done
2735 22:50:06.728679 ==
2736 22:50:06.731817 Dram Type= 6, Freq= 0, CH_0, rank 1
2737 22:50:06.735131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2738 22:50:06.735215 ==
2739 22:50:06.738704 RX Vref Scan: 0
2740 22:50:06.738785
2741 22:50:06.738848 RX Vref 0 -> 0, step: 1
2742 22:50:06.738907
2743 22:50:06.741864 RX Delay -40 -> 252, step: 8
2744 22:50:06.745094 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2745 22:50:06.752050 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2746 22:50:06.755245 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2747 22:50:06.758305 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2748 22:50:06.761896 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2749 22:50:06.765318 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2750 22:50:06.771860 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2751 22:50:06.774945 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2752 22:50:06.778285 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2753 22:50:06.781531 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2754 22:50:06.785016 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2755 22:50:06.788284 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2756 22:50:06.794945 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2757 22:50:06.798041 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2758 22:50:06.801641 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2759 22:50:06.804757 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2760 22:50:06.804840 ==
2761 22:50:06.808134 Dram Type= 6, Freq= 0, CH_0, rank 1
2762 22:50:06.814803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2763 22:50:06.814887 ==
2764 22:50:06.814951 DQS Delay:
2765 22:50:06.818004 DQS0 = 0, DQS1 = 0
2766 22:50:06.818102 DQM Delay:
2767 22:50:06.821288 DQM0 = 114, DQM1 = 107
2768 22:50:06.821370 DQ Delay:
2769 22:50:06.824652 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2770 22:50:06.827822 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2771 22:50:06.831357 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2772 22:50:06.834699 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2773 22:50:06.834778
2774 22:50:06.834841
2775 22:50:06.834898 ==
2776 22:50:06.838001 Dram Type= 6, Freq= 0, CH_0, rank 1
2777 22:50:06.841352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2778 22:50:06.844546 ==
2779 22:50:06.844625
2780 22:50:06.844687
2781 22:50:06.844745 TX Vref Scan disable
2782 22:50:06.847911 == TX Byte 0 ==
2783 22:50:06.851267 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2784 22:50:06.854693 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2785 22:50:06.857818 == TX Byte 1 ==
2786 22:50:06.861007 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2787 22:50:06.864592 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2788 22:50:06.867989 ==
2789 22:50:06.871013 Dram Type= 6, Freq= 0, CH_0, rank 1
2790 22:50:06.874399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2791 22:50:06.874479 ==
2792 22:50:06.885683 TX Vref=22, minBit 8, minWin=25, winSum=416
2793 22:50:06.888998 TX Vref=24, minBit 5, minWin=25, winSum=419
2794 22:50:06.892407 TX Vref=26, minBit 1, minWin=26, winSum=430
2795 22:50:06.895767 TX Vref=28, minBit 9, minWin=25, winSum=428
2796 22:50:06.899203 TX Vref=30, minBit 8, minWin=26, winSum=435
2797 22:50:06.902360 TX Vref=32, minBit 9, minWin=26, winSum=430
2798 22:50:06.908950 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
2799 22:50:06.909029
2800 22:50:06.912363 Final TX Range 1 Vref 30
2801 22:50:06.912443
2802 22:50:06.912504 ==
2803 22:50:06.915803 Dram Type= 6, Freq= 0, CH_0, rank 1
2804 22:50:06.919132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2805 22:50:06.919213 ==
2806 22:50:06.919276
2807 22:50:06.922251
2808 22:50:06.922329 TX Vref Scan disable
2809 22:50:06.925601 == TX Byte 0 ==
2810 22:50:06.929019 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2811 22:50:06.932197 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2812 22:50:06.935676 == TX Byte 1 ==
2813 22:50:06.938983 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2814 22:50:06.942167 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2815 22:50:06.942247
2816 22:50:06.945470 [DATLAT]
2817 22:50:06.945550 Freq=1200, CH0 RK1
2818 22:50:06.945613
2819 22:50:06.948973 DATLAT Default: 0xc
2820 22:50:06.949052 0, 0xFFFF, sum = 0
2821 22:50:06.952158 1, 0xFFFF, sum = 0
2822 22:50:06.952240 2, 0xFFFF, sum = 0
2823 22:50:06.955657 3, 0xFFFF, sum = 0
2824 22:50:06.955738 4, 0xFFFF, sum = 0
2825 22:50:06.959039 5, 0xFFFF, sum = 0
2826 22:50:06.959120 6, 0xFFFF, sum = 0
2827 22:50:06.962148 7, 0xFFFF, sum = 0
2828 22:50:06.965510 8, 0xFFFF, sum = 0
2829 22:50:06.965590 9, 0xFFFF, sum = 0
2830 22:50:06.968755 10, 0xFFFF, sum = 0
2831 22:50:06.968836 11, 0x0, sum = 1
2832 22:50:06.972218 12, 0x0, sum = 2
2833 22:50:06.972291 13, 0x0, sum = 3
2834 22:50:06.972352 14, 0x0, sum = 4
2835 22:50:06.975545 best_step = 12
2836 22:50:06.975623
2837 22:50:06.975685 ==
2838 22:50:06.978848 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 22:50:06.982390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2840 22:50:06.982470 ==
2841 22:50:06.985691 RX Vref Scan: 0
2842 22:50:06.985770
2843 22:50:06.985832 RX Vref 0 -> 0, step: 1
2844 22:50:06.985891
2845 22:50:06.988951 RX Delay -21 -> 252, step: 4
2846 22:50:06.995761 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2847 22:50:06.999253 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2848 22:50:07.002502 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2849 22:50:07.006301 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2850 22:50:07.009232 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2851 22:50:07.015951 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2852 22:50:07.019291 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2853 22:50:07.022513 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2854 22:50:07.026256 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2855 22:50:07.029107 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2856 22:50:07.036003 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
2857 22:50:07.039123 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2858 22:50:07.042440 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2859 22:50:07.045926 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
2860 22:50:07.049326 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2861 22:50:07.055880 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2862 22:50:07.055963 ==
2863 22:50:07.059265 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 22:50:07.062697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2865 22:50:07.062779 ==
2866 22:50:07.062842 DQS Delay:
2867 22:50:07.066019 DQS0 = 0, DQS1 = 0
2868 22:50:07.066141 DQM Delay:
2869 22:50:07.069448 DQM0 = 115, DQM1 = 106
2870 22:50:07.069531 DQ Delay:
2871 22:50:07.072647 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2872 22:50:07.076120 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2873 22:50:07.079078 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2874 22:50:07.082304 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =114
2875 22:50:07.082384
2876 22:50:07.082447
2877 22:50:07.092341 [DQSOSCAuto] RK1, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
2878 22:50:07.095856 CH0 RK1: MR19=404, MR18=1515
2879 22:50:07.099118 CH0_RK1: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
2880 22:50:07.102275 [RxdqsGatingPostProcess] freq 1200
2881 22:50:07.109105 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2882 22:50:07.112779 Pre-setting of DQS Precalculation
2883 22:50:07.115889 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2884 22:50:07.119118 ==
2885 22:50:07.119199 Dram Type= 6, Freq= 0, CH_1, rank 0
2886 22:50:07.125687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2887 22:50:07.125769 ==
2888 22:50:07.129072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2889 22:50:07.135872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2890 22:50:07.144546 [CA 0] Center 37 (7~68) winsize 62
2891 22:50:07.147784 [CA 1] Center 37 (7~68) winsize 62
2892 22:50:07.151270 [CA 2] Center 34 (4~65) winsize 62
2893 22:50:07.154776 [CA 3] Center 33 (3~64) winsize 62
2894 22:50:07.157931 [CA 4] Center 32 (2~63) winsize 62
2895 22:50:07.161013 [CA 5] Center 32 (1~63) winsize 63
2896 22:50:07.161094
2897 22:50:07.164558 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2898 22:50:07.164639
2899 22:50:07.167873 [CATrainingPosCal] consider 1 rank data
2900 22:50:07.171093 u2DelayCellTimex100 = 270/100 ps
2901 22:50:07.174495 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2902 22:50:07.177957 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2903 22:50:07.184727 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2904 22:50:07.188068 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2905 22:50:07.191209 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2906 22:50:07.194587 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2907 22:50:07.194669
2908 22:50:07.197970 CA PerBit enable=1, Macro0, CA PI delay=32
2909 22:50:07.198101
2910 22:50:07.201246 [CBTSetCACLKResult] CA Dly = 32
2911 22:50:07.201331 CS Dly: 6 (0~37)
2912 22:50:07.201394 ==
2913 22:50:07.204660 Dram Type= 6, Freq= 0, CH_1, rank 1
2914 22:50:07.211143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2915 22:50:07.211244 ==
2916 22:50:07.214378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2917 22:50:07.220953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2918 22:50:07.229724 [CA 0] Center 37 (6~68) winsize 63
2919 22:50:07.233236 [CA 1] Center 37 (7~68) winsize 62
2920 22:50:07.236690 [CA 2] Center 34 (3~65) winsize 63
2921 22:50:07.240024 [CA 3] Center 33 (3~64) winsize 62
2922 22:50:07.243175 [CA 4] Center 32 (2~63) winsize 62
2923 22:50:07.246474 [CA 5] Center 32 (2~62) winsize 61
2924 22:50:07.246559
2925 22:50:07.249773 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2926 22:50:07.249861
2927 22:50:07.253099 [CATrainingPosCal] consider 2 rank data
2928 22:50:07.256593 u2DelayCellTimex100 = 270/100 ps
2929 22:50:07.259928 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2930 22:50:07.263458 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2931 22:50:07.269677 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2932 22:50:07.273105 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2933 22:50:07.276546 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2934 22:50:07.279648 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2935 22:50:07.279731
2936 22:50:07.283050 CA PerBit enable=1, Macro0, CA PI delay=32
2937 22:50:07.283133
2938 22:50:07.286454 [CBTSetCACLKResult] CA Dly = 32
2939 22:50:07.286537 CS Dly: 6 (0~38)
2940 22:50:07.286602
2941 22:50:07.289795 ----->DramcWriteLeveling(PI) begin...
2942 22:50:07.292995 ==
2943 22:50:07.296435 Dram Type= 6, Freq= 0, CH_1, rank 0
2944 22:50:07.299609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2945 22:50:07.299694 ==
2946 22:50:07.302798 Write leveling (Byte 0): 21 => 21
2947 22:50:07.306184 Write leveling (Byte 1): 23 => 23
2948 22:50:07.309920 DramcWriteLeveling(PI) end<-----
2949 22:50:07.310035
2950 22:50:07.310115 ==
2951 22:50:07.312844 Dram Type= 6, Freq= 0, CH_1, rank 0
2952 22:50:07.316199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2953 22:50:07.316283 ==
2954 22:50:07.319767 [Gating] SW mode calibration
2955 22:50:07.326158 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2956 22:50:07.329581 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2957 22:50:07.336668 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 22:50:07.339817 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2959 22:50:07.342822 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2960 22:50:07.349504 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2961 22:50:07.352878 0 11 16 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (1 0)
2962 22:50:07.356225 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2963 22:50:07.363257 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 22:50:07.366791 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 22:50:07.369971 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 22:50:07.376258 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 22:50:07.379677 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 22:50:07.382833 0 12 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2969 22:50:07.389699 0 12 16 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
2970 22:50:07.392997 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 22:50:07.396360 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 22:50:07.402851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 22:50:07.406327 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 22:50:07.409704 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 22:50:07.416182 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 22:50:07.419822 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 22:50:07.422933 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2978 22:50:07.429499 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2979 22:50:07.432826 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 22:50:07.436336 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 22:50:07.439451 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 22:50:07.446189 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 22:50:07.449548 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 22:50:07.452962 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 22:50:07.459514 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 22:50:07.462972 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 22:50:07.466071 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 22:50:07.472726 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 22:50:07.476340 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 22:50:07.479558 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 22:50:07.486209 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 22:50:07.489726 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 22:50:07.492967 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2994 22:50:07.499310 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2995 22:50:07.499393 Total UI for P1: 0, mck2ui 16
2996 22:50:07.505944 best dqsien dly found for B0: ( 0, 15, 16)
2997 22:50:07.509453 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2998 22:50:07.513027 Total UI for P1: 0, mck2ui 16
2999 22:50:07.516124 best dqsien dly found for B1: ( 0, 15, 18)
3000 22:50:07.519343 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3001 22:50:07.522638 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3002 22:50:07.522719
3003 22:50:07.526082 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3004 22:50:07.529603 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3005 22:50:07.532600 [Gating] SW calibration Done
3006 22:50:07.532682 ==
3007 22:50:07.535965 Dram Type= 6, Freq= 0, CH_1, rank 0
3008 22:50:07.539294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3009 22:50:07.542737 ==
3010 22:50:07.542818 RX Vref Scan: 0
3011 22:50:07.542882
3012 22:50:07.546047 RX Vref 0 -> 0, step: 1
3013 22:50:07.546128
3014 22:50:07.549282 RX Delay -40 -> 252, step: 8
3015 22:50:07.552499 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3016 22:50:07.556045 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3017 22:50:07.559521 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3018 22:50:07.562640 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3019 22:50:07.569230 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3020 22:50:07.572688 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3021 22:50:07.575909 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3022 22:50:07.579799 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3023 22:50:07.582701 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3024 22:50:07.586166 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3025 22:50:07.592604 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3026 22:50:07.596039 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3027 22:50:07.599636 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3028 22:50:07.603096 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3029 22:50:07.606535 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3030 22:50:07.612557 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3031 22:50:07.612644 ==
3032 22:50:07.616095 Dram Type= 6, Freq= 0, CH_1, rank 0
3033 22:50:07.619285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3034 22:50:07.619366 ==
3035 22:50:07.619429 DQS Delay:
3036 22:50:07.622804 DQS0 = 0, DQS1 = 0
3037 22:50:07.622885 DQM Delay:
3038 22:50:07.626059 DQM0 = 115, DQM1 = 107
3039 22:50:07.626179 DQ Delay:
3040 22:50:07.629352 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3041 22:50:07.632836 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3042 22:50:07.635923 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3043 22:50:07.639473 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3044 22:50:07.639555
3045 22:50:07.639618
3046 22:50:07.642708 ==
3047 22:50:07.642789 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 22:50:07.649396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3049 22:50:07.649478 ==
3050 22:50:07.649541
3051 22:50:07.649599
3052 22:50:07.652663 TX Vref Scan disable
3053 22:50:07.652763 == TX Byte 0 ==
3054 22:50:07.655929 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3055 22:50:07.662490 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3056 22:50:07.662575 == TX Byte 1 ==
3057 22:50:07.666051 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3058 22:50:07.672473 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3059 22:50:07.672563 ==
3060 22:50:07.675852 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 22:50:07.679107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3062 22:50:07.679190 ==
3063 22:50:07.690929 TX Vref=22, minBit 3, minWin=25, winSum=412
3064 22:50:07.694381 TX Vref=24, minBit 8, minWin=25, winSum=415
3065 22:50:07.697843 TX Vref=26, minBit 0, minWin=26, winSum=426
3066 22:50:07.700939 TX Vref=28, minBit 0, minWin=26, winSum=425
3067 22:50:07.704247 TX Vref=30, minBit 5, minWin=26, winSum=428
3068 22:50:07.707943 TX Vref=32, minBit 9, minWin=25, winSum=424
3069 22:50:07.714348 [TxChooseVref] Worse bit 5, Min win 26, Win sum 428, Final Vref 30
3070 22:50:07.714434
3071 22:50:07.717827 Final TX Range 1 Vref 30
3072 22:50:07.717907
3073 22:50:07.717970 ==
3074 22:50:07.721174 Dram Type= 6, Freq= 0, CH_1, rank 0
3075 22:50:07.724646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3076 22:50:07.724735 ==
3077 22:50:07.724810
3078 22:50:07.727873
3079 22:50:07.727953 TX Vref Scan disable
3080 22:50:07.731124 == TX Byte 0 ==
3081 22:50:07.734237 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3082 22:50:07.737676 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3083 22:50:07.741273 == TX Byte 1 ==
3084 22:50:07.744333 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3085 22:50:07.747589 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3086 22:50:07.747670
3087 22:50:07.750977 [DATLAT]
3088 22:50:07.751103 Freq=1200, CH1 RK0
3089 22:50:07.751186
3090 22:50:07.754339 DATLAT Default: 0xd
3091 22:50:07.754420 0, 0xFFFF, sum = 0
3092 22:50:07.757626 1, 0xFFFF, sum = 0
3093 22:50:07.757709 2, 0xFFFF, sum = 0
3094 22:50:07.760930 3, 0xFFFF, sum = 0
3095 22:50:07.761012 4, 0xFFFF, sum = 0
3096 22:50:07.764371 5, 0xFFFF, sum = 0
3097 22:50:07.764454 6, 0xFFFF, sum = 0
3098 22:50:07.767570 7, 0xFFFF, sum = 0
3099 22:50:07.767652 8, 0xFFFF, sum = 0
3100 22:50:07.771095 9, 0xFFFF, sum = 0
3101 22:50:07.771178 10, 0xFFFF, sum = 0
3102 22:50:07.774440 11, 0x0, sum = 1
3103 22:50:07.774522 12, 0x0, sum = 2
3104 22:50:07.777654 13, 0x0, sum = 3
3105 22:50:07.777737 14, 0x0, sum = 4
3106 22:50:07.781038 best_step = 12
3107 22:50:07.781118
3108 22:50:07.781182 ==
3109 22:50:07.784430 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 22:50:07.787677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3111 22:50:07.787760 ==
3112 22:50:07.791067 RX Vref Scan: 1
3113 22:50:07.791149
3114 22:50:07.791212 Set Vref Range= 32 -> 127
3115 22:50:07.791271
3116 22:50:07.794507 RX Vref 32 -> 127, step: 1
3117 22:50:07.794588
3118 22:50:07.798223 RX Delay -29 -> 252, step: 4
3119 22:50:07.798305
3120 22:50:07.801141 Set Vref, RX VrefLevel [Byte0]: 32
3121 22:50:07.804468 [Byte1]: 32
3122 22:50:07.804550
3123 22:50:07.807685 Set Vref, RX VrefLevel [Byte0]: 33
3124 22:50:07.811138 [Byte1]: 33
3125 22:50:07.815543
3126 22:50:07.815625 Set Vref, RX VrefLevel [Byte0]: 34
3127 22:50:07.818582 [Byte1]: 34
3128 22:50:07.823330
3129 22:50:07.823410 Set Vref, RX VrefLevel [Byte0]: 35
3130 22:50:07.826645 [Byte1]: 35
3131 22:50:07.831536
3132 22:50:07.831618 Set Vref, RX VrefLevel [Byte0]: 36
3133 22:50:07.834991 [Byte1]: 36
3134 22:50:07.839308
3135 22:50:07.839390 Set Vref, RX VrefLevel [Byte0]: 37
3136 22:50:07.842812 [Byte1]: 37
3137 22:50:07.847149
3138 22:50:07.847231 Set Vref, RX VrefLevel [Byte0]: 38
3139 22:50:07.850532 [Byte1]: 38
3140 22:50:07.855224
3141 22:50:07.855322 Set Vref, RX VrefLevel [Byte0]: 39
3142 22:50:07.858408 [Byte1]: 39
3143 22:50:07.863151
3144 22:50:07.863236 Set Vref, RX VrefLevel [Byte0]: 40
3145 22:50:07.866481 [Byte1]: 40
3146 22:50:07.871277
3147 22:50:07.871361 Set Vref, RX VrefLevel [Byte0]: 41
3148 22:50:07.874577 [Byte1]: 41
3149 22:50:07.879106
3150 22:50:07.879188 Set Vref, RX VrefLevel [Byte0]: 42
3151 22:50:07.882326 [Byte1]: 42
3152 22:50:07.887068
3153 22:50:07.887149 Set Vref, RX VrefLevel [Byte0]: 43
3154 22:50:07.890545 [Byte1]: 43
3155 22:50:07.894997
3156 22:50:07.895078 Set Vref, RX VrefLevel [Byte0]: 44
3157 22:50:07.898536 [Byte1]: 44
3158 22:50:07.902976
3159 22:50:07.903057 Set Vref, RX VrefLevel [Byte0]: 45
3160 22:50:07.906091 [Byte1]: 45
3161 22:50:07.910880
3162 22:50:07.910977 Set Vref, RX VrefLevel [Byte0]: 46
3163 22:50:07.914156 [Byte1]: 46
3164 22:50:07.919051
3165 22:50:07.919132 Set Vref, RX VrefLevel [Byte0]: 47
3166 22:50:07.922161 [Byte1]: 47
3167 22:50:07.927074
3168 22:50:07.927156 Set Vref, RX VrefLevel [Byte0]: 48
3169 22:50:07.930208 [Byte1]: 48
3170 22:50:07.934623
3171 22:50:07.934705 Set Vref, RX VrefLevel [Byte0]: 49
3172 22:50:07.937924 [Byte1]: 49
3173 22:50:07.942814
3174 22:50:07.942895 Set Vref, RX VrefLevel [Byte0]: 50
3175 22:50:07.945918 [Byte1]: 50
3176 22:50:07.950841
3177 22:50:07.950923 Set Vref, RX VrefLevel [Byte0]: 51
3178 22:50:07.953863 [Byte1]: 51
3179 22:50:07.958661
3180 22:50:07.958744 Set Vref, RX VrefLevel [Byte0]: 52
3181 22:50:07.962359 [Byte1]: 52
3182 22:50:07.966433
3183 22:50:07.966514 Set Vref, RX VrefLevel [Byte0]: 53
3184 22:50:07.969680 [Byte1]: 53
3185 22:50:07.974619
3186 22:50:07.974700 Set Vref, RX VrefLevel [Byte0]: 54
3187 22:50:07.977811 [Byte1]: 54
3188 22:50:07.982498
3189 22:50:07.982578 Set Vref, RX VrefLevel [Byte0]: 55
3190 22:50:07.985920 [Byte1]: 55
3191 22:50:07.990356
3192 22:50:07.990436 Set Vref, RX VrefLevel [Byte0]: 56
3193 22:50:07.993782 [Byte1]: 56
3194 22:50:07.998554
3195 22:50:07.998633 Set Vref, RX VrefLevel [Byte0]: 57
3196 22:50:08.001576 [Byte1]: 57
3197 22:50:08.006285
3198 22:50:08.006366 Set Vref, RX VrefLevel [Byte0]: 58
3199 22:50:08.009740 [Byte1]: 58
3200 22:50:08.014392
3201 22:50:08.014474 Set Vref, RX VrefLevel [Byte0]: 59
3202 22:50:08.017664 [Byte1]: 59
3203 22:50:08.022370
3204 22:50:08.022452 Set Vref, RX VrefLevel [Byte0]: 60
3205 22:50:08.025637 [Byte1]: 60
3206 22:50:08.030157
3207 22:50:08.030240 Set Vref, RX VrefLevel [Byte0]: 61
3208 22:50:08.033625 [Byte1]: 61
3209 22:50:08.038270
3210 22:50:08.038352 Set Vref, RX VrefLevel [Byte0]: 62
3211 22:50:08.041342 [Byte1]: 62
3212 22:50:08.046153
3213 22:50:08.046235 Set Vref, RX VrefLevel [Byte0]: 63
3214 22:50:08.049367 [Byte1]: 63
3215 22:50:08.053954
3216 22:50:08.054080 Set Vref, RX VrefLevel [Byte0]: 64
3217 22:50:08.057293 [Byte1]: 64
3218 22:50:08.062083
3219 22:50:08.062168 Set Vref, RX VrefLevel [Byte0]: 65
3220 22:50:08.065747 [Byte1]: 65
3221 22:50:08.070167
3222 22:50:08.070251 Final RX Vref Byte 0 = 56 to rank0
3223 22:50:08.073358 Final RX Vref Byte 1 = 49 to rank0
3224 22:50:08.076685 Final RX Vref Byte 0 = 56 to rank1
3225 22:50:08.080313 Final RX Vref Byte 1 = 49 to rank1==
3226 22:50:08.083468 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 22:50:08.090030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3228 22:50:08.090117 ==
3229 22:50:08.090182 DQS Delay:
3230 22:50:08.090240 DQS0 = 0, DQS1 = 0
3231 22:50:08.093277 DQM Delay:
3232 22:50:08.093357 DQM0 = 115, DQM1 = 105
3233 22:50:08.096682 DQ Delay:
3234 22:50:08.099954 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3235 22:50:08.103478 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3236 22:50:08.106590 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3237 22:50:08.109950 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =116
3238 22:50:08.110041
3239 22:50:08.110106
3240 22:50:08.116562 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3241 22:50:08.120211 CH1 RK0: MR19=404, MR18=1414
3242 22:50:08.126458 CH1_RK0: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
3243 22:50:08.126546
3244 22:50:08.130057 ----->DramcWriteLeveling(PI) begin...
3245 22:50:08.130154 ==
3246 22:50:08.133462 Dram Type= 6, Freq= 0, CH_1, rank 1
3247 22:50:08.136565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3248 22:50:08.139812 ==
3249 22:50:08.139895 Write leveling (Byte 0): 22 => 22
3250 22:50:08.143539 Write leveling (Byte 1): 22 => 22
3251 22:50:08.146455 DramcWriteLeveling(PI) end<-----
3252 22:50:08.146538
3253 22:50:08.146601 ==
3254 22:50:08.149909 Dram Type= 6, Freq= 0, CH_1, rank 1
3255 22:50:08.156467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3256 22:50:08.156561 ==
3257 22:50:08.156627 [Gating] SW mode calibration
3258 22:50:08.166540 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3259 22:50:08.169829 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3260 22:50:08.173330 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3261 22:50:08.180300 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3262 22:50:08.183140 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3263 22:50:08.186583 0 11 12 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (0 0)
3264 22:50:08.193449 0 11 16 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
3265 22:50:08.196458 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3266 22:50:08.200188 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3267 22:50:08.206590 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3268 22:50:08.210130 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3269 22:50:08.213255 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3270 22:50:08.219731 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3271 22:50:08.223091 0 12 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (1 1)
3272 22:50:08.226567 0 12 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3273 22:50:08.233272 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3274 22:50:08.236607 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 22:50:08.239850 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3276 22:50:08.246491 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 22:50:08.249994 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 22:50:08.253375 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3279 22:50:08.256777 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3280 22:50:08.263115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3281 22:50:08.266614 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 22:50:08.269739 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 22:50:08.276630 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 22:50:08.279764 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 22:50:08.283224 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 22:50:08.289972 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 22:50:08.293146 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 22:50:08.296606 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 22:50:08.303310 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 22:50:08.306754 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 22:50:08.309885 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 22:50:08.316527 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 22:50:08.319901 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 22:50:08.323208 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 22:50:08.329804 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3296 22:50:08.333336 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3297 22:50:08.336802 Total UI for P1: 0, mck2ui 16
3298 22:50:08.339886 best dqsien dly found for B0: ( 0, 15, 12)
3299 22:50:08.343741 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3300 22:50:08.346573 Total UI for P1: 0, mck2ui 16
3301 22:50:08.350147 best dqsien dly found for B1: ( 0, 15, 16)
3302 22:50:08.353284 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3303 22:50:08.356858 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3304 22:50:08.356950
3305 22:50:08.360067 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3306 22:50:08.366588 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3307 22:50:08.366685 [Gating] SW calibration Done
3308 22:50:08.366750 ==
3309 22:50:08.369745 Dram Type= 6, Freq= 0, CH_1, rank 1
3310 22:50:08.376513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3311 22:50:08.376609 ==
3312 22:50:08.376674 RX Vref Scan: 0
3313 22:50:08.376734
3314 22:50:08.380066 RX Vref 0 -> 0, step: 1
3315 22:50:08.380158
3316 22:50:08.382985 RX Delay -40 -> 252, step: 8
3317 22:50:08.386421 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3318 22:50:08.389691 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3319 22:50:08.393021 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3320 22:50:08.399557 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3321 22:50:08.402980 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3322 22:50:08.406275 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3323 22:50:08.410075 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3324 22:50:08.413425 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3325 22:50:08.419650 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3326 22:50:08.423094 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3327 22:50:08.426513 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3328 22:50:08.429756 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3329 22:50:08.433075 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3330 22:50:08.439785 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3331 22:50:08.443008 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3332 22:50:08.446332 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
3333 22:50:08.446417 ==
3334 22:50:08.449657 Dram Type= 6, Freq= 0, CH_1, rank 1
3335 22:50:08.453003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3336 22:50:08.453094 ==
3337 22:50:08.456536 DQS Delay:
3338 22:50:08.456610 DQS0 = 0, DQS1 = 0
3339 22:50:08.456670 DQM Delay:
3340 22:50:08.459559 DQM0 = 116, DQM1 = 106
3341 22:50:08.459666 DQ Delay:
3342 22:50:08.463232 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3343 22:50:08.466329 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3344 22:50:08.469864 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3345 22:50:08.476319 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3346 22:50:08.476437
3347 22:50:08.476528
3348 22:50:08.476614 ==
3349 22:50:08.479857 Dram Type= 6, Freq= 0, CH_1, rank 1
3350 22:50:08.483005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3351 22:50:08.483089 ==
3352 22:50:08.483161
3353 22:50:08.483248
3354 22:50:08.486661 TX Vref Scan disable
3355 22:50:08.486743 == TX Byte 0 ==
3356 22:50:08.493135 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3357 22:50:08.496647 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3358 22:50:08.496730 == TX Byte 1 ==
3359 22:50:08.503174 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3360 22:50:08.506302 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3361 22:50:08.506384 ==
3362 22:50:08.509706 Dram Type= 6, Freq= 0, CH_1, rank 1
3363 22:50:08.512846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3364 22:50:08.512927 ==
3365 22:50:08.525542 TX Vref=22, minBit 9, minWin=25, winSum=421
3366 22:50:08.528809 TX Vref=24, minBit 9, minWin=25, winSum=427
3367 22:50:08.532093 TX Vref=26, minBit 9, minWin=25, winSum=427
3368 22:50:08.535535 TX Vref=28, minBit 9, minWin=26, winSum=432
3369 22:50:08.538832 TX Vref=30, minBit 9, minWin=26, winSum=431
3370 22:50:08.542192 TX Vref=32, minBit 0, minWin=26, winSum=431
3371 22:50:08.548819 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3372 22:50:08.548910
3373 22:50:08.552130 Final TX Range 1 Vref 28
3374 22:50:08.552212
3375 22:50:08.552275 ==
3376 22:50:08.555325 Dram Type= 6, Freq= 0, CH_1, rank 1
3377 22:50:08.558756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3378 22:50:08.558846 ==
3379 22:50:08.558909
3380 22:50:08.562281
3381 22:50:08.562361 TX Vref Scan disable
3382 22:50:08.565477 == TX Byte 0 ==
3383 22:50:08.568757 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3384 22:50:08.572189 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3385 22:50:08.575744 == TX Byte 1 ==
3386 22:50:08.578807 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3387 22:50:08.582152 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3388 22:50:08.582235
3389 22:50:08.585588 [DATLAT]
3390 22:50:08.585693 Freq=1200, CH1 RK1
3391 22:50:08.585784
3392 22:50:08.588969 DATLAT Default: 0xc
3393 22:50:08.589050 0, 0xFFFF, sum = 0
3394 22:50:08.592364 1, 0xFFFF, sum = 0
3395 22:50:08.592446 2, 0xFFFF, sum = 0
3396 22:50:08.595501 3, 0xFFFF, sum = 0
3397 22:50:08.595583 4, 0xFFFF, sum = 0
3398 22:50:08.598812 5, 0xFFFF, sum = 0
3399 22:50:08.598894 6, 0xFFFF, sum = 0
3400 22:50:08.602145 7, 0xFFFF, sum = 0
3401 22:50:08.602226 8, 0xFFFF, sum = 0
3402 22:50:08.605521 9, 0xFFFF, sum = 0
3403 22:50:08.608862 10, 0xFFFF, sum = 0
3404 22:50:08.608944 11, 0x0, sum = 1
3405 22:50:08.609009 12, 0x0, sum = 2
3406 22:50:08.612375 13, 0x0, sum = 3
3407 22:50:08.612456 14, 0x0, sum = 4
3408 22:50:08.615704 best_step = 12
3409 22:50:08.615784
3410 22:50:08.615847 ==
3411 22:50:08.619042 Dram Type= 6, Freq= 0, CH_1, rank 1
3412 22:50:08.622217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3413 22:50:08.622298 ==
3414 22:50:08.625612 RX Vref Scan: 0
3415 22:50:08.625696
3416 22:50:08.625764 RX Vref 0 -> 0, step: 1
3417 22:50:08.625825
3418 22:50:08.628929 RX Delay -29 -> 252, step: 4
3419 22:50:08.635769 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3420 22:50:08.638911 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3421 22:50:08.642605 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3422 22:50:08.645665 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3423 22:50:08.649146 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3424 22:50:08.655788 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3425 22:50:08.659032 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3426 22:50:08.662273 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3427 22:50:08.665880 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3428 22:50:08.669097 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3429 22:50:08.675795 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3430 22:50:08.679216 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3431 22:50:08.682419 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3432 22:50:08.685866 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3433 22:50:08.689040 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3434 22:50:08.696031 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3435 22:50:08.696116 ==
3436 22:50:08.699019 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 22:50:08.702493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3438 22:50:08.702579 ==
3439 22:50:08.702643 DQS Delay:
3440 22:50:08.705737 DQS0 = 0, DQS1 = 0
3441 22:50:08.705816 DQM Delay:
3442 22:50:08.709487 DQM0 = 114, DQM1 = 103
3443 22:50:08.709567 DQ Delay:
3444 22:50:08.712447 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =112
3445 22:50:08.715841 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3446 22:50:08.719261 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3447 22:50:08.722418 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3448 22:50:08.722529
3449 22:50:08.722628
3450 22:50:08.732743 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3451 22:50:08.732825 CH1 RK1: MR19=404, MR18=D0D
3452 22:50:08.739320 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3453 22:50:08.742399 [RxdqsGatingPostProcess] freq 1200
3454 22:50:08.749328 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3455 22:50:08.752740 Pre-setting of DQS Precalculation
3456 22:50:08.755928 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3457 22:50:08.762705 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3458 22:50:08.772733 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3459 22:50:08.772846
3460 22:50:08.772910
3461 22:50:08.772970 [Calibration Summary] 2400 Mbps
3462 22:50:08.775983 CH 0, Rank 0
3463 22:50:08.776063 SW Impedance : PASS
3464 22:50:08.779520 DUTY Scan : NO K
3465 22:50:08.782714 ZQ Calibration : PASS
3466 22:50:08.782796 Jitter Meter : NO K
3467 22:50:08.786155 CBT Training : PASS
3468 22:50:08.789415 Write leveling : PASS
3469 22:50:08.789496 RX DQS gating : PASS
3470 22:50:08.792897 RX DQ/DQS(RDDQC) : PASS
3471 22:50:08.796149 TX DQ/DQS : PASS
3472 22:50:08.796230 RX DATLAT : PASS
3473 22:50:08.799402 RX DQ/DQS(Engine): PASS
3474 22:50:08.802695 TX OE : NO K
3475 22:50:08.802775 All Pass.
3476 22:50:08.802837
3477 22:50:08.802895 CH 0, Rank 1
3478 22:50:08.806364 SW Impedance : PASS
3479 22:50:08.809348 DUTY Scan : NO K
3480 22:50:08.809428 ZQ Calibration : PASS
3481 22:50:08.812968 Jitter Meter : NO K
3482 22:50:08.816163 CBT Training : PASS
3483 22:50:08.816243 Write leveling : PASS
3484 22:50:08.819482 RX DQS gating : PASS
3485 22:50:08.819562 RX DQ/DQS(RDDQC) : PASS
3486 22:50:08.822819 TX DQ/DQS : PASS
3487 22:50:08.826164 RX DATLAT : PASS
3488 22:50:08.826244 RX DQ/DQS(Engine): PASS
3489 22:50:08.829179 TX OE : NO K
3490 22:50:08.829259 All Pass.
3491 22:50:08.829321
3492 22:50:08.832549 CH 1, Rank 0
3493 22:50:08.832628 SW Impedance : PASS
3494 22:50:08.835940 DUTY Scan : NO K
3495 22:50:08.839405 ZQ Calibration : PASS
3496 22:50:08.839487 Jitter Meter : NO K
3497 22:50:08.842766 CBT Training : PASS
3498 22:50:08.845973 Write leveling : PASS
3499 22:50:08.846094 RX DQS gating : PASS
3500 22:50:08.849324 RX DQ/DQS(RDDQC) : PASS
3501 22:50:08.852488 TX DQ/DQS : PASS
3502 22:50:08.852571 RX DATLAT : PASS
3503 22:50:08.855951 RX DQ/DQS(Engine): PASS
3504 22:50:08.859128 TX OE : NO K
3505 22:50:08.859217 All Pass.
3506 22:50:08.859281
3507 22:50:08.859341 CH 1, Rank 1
3508 22:50:08.862639 SW Impedance : PASS
3509 22:50:08.866060 DUTY Scan : NO K
3510 22:50:08.866155 ZQ Calibration : PASS
3511 22:50:08.869389 Jitter Meter : NO K
3512 22:50:08.869470 CBT Training : PASS
3513 22:50:08.872737 Write leveling : PASS
3514 22:50:08.875924 RX DQS gating : PASS
3515 22:50:08.876004 RX DQ/DQS(RDDQC) : PASS
3516 22:50:08.879157 TX DQ/DQS : PASS
3517 22:50:08.882438 RX DATLAT : PASS
3518 22:50:08.882518 RX DQ/DQS(Engine): PASS
3519 22:50:08.886029 TX OE : NO K
3520 22:50:08.886110 All Pass.
3521 22:50:08.886173
3522 22:50:08.889567 DramC Write-DBI off
3523 22:50:08.892613 PER_BANK_REFRESH: Hybrid Mode
3524 22:50:08.892696 TX_TRACKING: ON
3525 22:50:08.902787 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3526 22:50:08.905953 [FAST_K] Save calibration result to emmc
3527 22:50:08.909205 dramc_set_vcore_voltage set vcore to 650000
3528 22:50:08.912761 Read voltage for 600, 5
3529 22:50:08.912866 Vio18 = 0
3530 22:50:08.912944 Vcore = 650000
3531 22:50:08.916089 Vdram = 0
3532 22:50:08.916169 Vddq = 0
3533 22:50:08.916232 Vmddr = 0
3534 22:50:08.922557 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3535 22:50:08.925788 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3536 22:50:08.929555 MEM_TYPE=3, freq_sel=19
3537 22:50:08.932567 sv_algorithm_assistance_LP4_1600
3538 22:50:08.935821 ============ PULL DRAM RESETB DOWN ============
3539 22:50:08.939305 ========== PULL DRAM RESETB DOWN end =========
3540 22:50:08.945864 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3541 22:50:08.949419 ===================================
3542 22:50:08.949499 LPDDR4 DRAM CONFIGURATION
3543 22:50:08.952820 ===================================
3544 22:50:08.956392 EX_ROW_EN[0] = 0x0
3545 22:50:08.959749 EX_ROW_EN[1] = 0x0
3546 22:50:08.959831 LP4Y_EN = 0x0
3547 22:50:08.962565 WORK_FSP = 0x0
3548 22:50:08.962647 WL = 0x2
3549 22:50:08.966064 RL = 0x2
3550 22:50:08.966159 BL = 0x2
3551 22:50:08.969400 RPST = 0x0
3552 22:50:08.969480 RD_PRE = 0x0
3553 22:50:08.972583 WR_PRE = 0x1
3554 22:50:08.972664 WR_PST = 0x0
3555 22:50:08.976122 DBI_WR = 0x0
3556 22:50:08.976202 DBI_RD = 0x0
3557 22:50:08.979327 OTF = 0x1
3558 22:50:08.982291 ===================================
3559 22:50:08.985867 ===================================
3560 22:50:08.985948 ANA top config
3561 22:50:08.988966 ===================================
3562 22:50:08.992296 DLL_ASYNC_EN = 0
3563 22:50:08.995723 ALL_SLAVE_EN = 1
3564 22:50:08.999073 NEW_RANK_MODE = 1
3565 22:50:08.999155 DLL_IDLE_MODE = 1
3566 22:50:09.002433 LP45_APHY_COMB_EN = 1
3567 22:50:09.005843 TX_ODT_DIS = 1
3568 22:50:09.009150 NEW_8X_MODE = 1
3569 22:50:09.012441 ===================================
3570 22:50:09.015656 ===================================
3571 22:50:09.018966 data_rate = 1200
3572 22:50:09.019048 CKR = 1
3573 22:50:09.022285 DQ_P2S_RATIO = 8
3574 22:50:09.025711 ===================================
3575 22:50:09.029097 CA_P2S_RATIO = 8
3576 22:50:09.032310 DQ_CA_OPEN = 0
3577 22:50:09.035598 DQ_SEMI_OPEN = 0
3578 22:50:09.038763 CA_SEMI_OPEN = 0
3579 22:50:09.038843 CA_FULL_RATE = 0
3580 22:50:09.042152 DQ_CKDIV4_EN = 1
3581 22:50:09.045395 CA_CKDIV4_EN = 1
3582 22:50:09.048873 CA_PREDIV_EN = 0
3583 22:50:09.051974 PH8_DLY = 0
3584 22:50:09.055481 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3585 22:50:09.055562 DQ_AAMCK_DIV = 4
3586 22:50:09.058986 CA_AAMCK_DIV = 4
3587 22:50:09.062175 CA_ADMCK_DIV = 4
3588 22:50:09.065633 DQ_TRACK_CA_EN = 0
3589 22:50:09.068538 CA_PICK = 600
3590 22:50:09.071877 CA_MCKIO = 600
3591 22:50:09.071956 MCKIO_SEMI = 0
3592 22:50:09.075246 PLL_FREQ = 2288
3593 22:50:09.078631 DQ_UI_PI_RATIO = 32
3594 22:50:09.081865 CA_UI_PI_RATIO = 0
3595 22:50:09.085328 ===================================
3596 22:50:09.088532 ===================================
3597 22:50:09.091993 memory_type:LPDDR4
3598 22:50:09.092073 GP_NUM : 10
3599 22:50:09.095256 SRAM_EN : 1
3600 22:50:09.098666 MD32_EN : 0
3601 22:50:09.101809 ===================================
3602 22:50:09.101889 [ANA_INIT] >>>>>>>>>>>>>>
3603 22:50:09.105186 <<<<<< [CONFIGURE PHASE]: ANA_TX
3604 22:50:09.108416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3605 22:50:09.111961 ===================================
3606 22:50:09.115269 data_rate = 1200,PCW = 0X5800
3607 22:50:09.118565 ===================================
3608 22:50:09.121853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3609 22:50:09.128214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3610 22:50:09.131645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3611 22:50:09.138234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3612 22:50:09.141942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3613 22:50:09.144946 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3614 22:50:09.145027 [ANA_INIT] flow start
3615 22:50:09.148247 [ANA_INIT] PLL >>>>>>>>
3616 22:50:09.151600 [ANA_INIT] PLL <<<<<<<<
3617 22:50:09.154907 [ANA_INIT] MIDPI >>>>>>>>
3618 22:50:09.154990 [ANA_INIT] MIDPI <<<<<<<<
3619 22:50:09.158160 [ANA_INIT] DLL >>>>>>>>
3620 22:50:09.161744 [ANA_INIT] flow end
3621 22:50:09.164974 ============ LP4 DIFF to SE enter ============
3622 22:50:09.168135 ============ LP4 DIFF to SE exit ============
3623 22:50:09.171593 [ANA_INIT] <<<<<<<<<<<<<
3624 22:50:09.174688 [Flow] Enable top DCM control >>>>>
3625 22:50:09.178525 [Flow] Enable top DCM control <<<<<
3626 22:50:09.181317 Enable DLL master slave shuffle
3627 22:50:09.184598 ==============================================================
3628 22:50:09.188102 Gating Mode config
3629 22:50:09.191485 ==============================================================
3630 22:50:09.194670 Config description:
3631 22:50:09.204713 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3632 22:50:09.211245 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3633 22:50:09.214505 SELPH_MODE 0: By rank 1: By Phase
3634 22:50:09.221451 ==============================================================
3635 22:50:09.224743 GAT_TRACK_EN = 1
3636 22:50:09.228195 RX_GATING_MODE = 2
3637 22:50:09.231462 RX_GATING_TRACK_MODE = 2
3638 22:50:09.234482 SELPH_MODE = 1
3639 22:50:09.237803 PICG_EARLY_EN = 1
3640 22:50:09.241258 VALID_LAT_VALUE = 1
3641 22:50:09.244290 ==============================================================
3642 22:50:09.247616 Enter into Gating configuration >>>>
3643 22:50:09.251229 Exit from Gating configuration <<<<
3644 22:50:09.254426 Enter into DVFS_PRE_config >>>>>
3645 22:50:09.264226 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3646 22:50:09.267470 Exit from DVFS_PRE_config <<<<<
3647 22:50:09.270872 Enter into PICG configuration >>>>
3648 22:50:09.274365 Exit from PICG configuration <<<<
3649 22:50:09.277485 [RX_INPUT] configuration >>>>>
3650 22:50:09.280903 [RX_INPUT] configuration <<<<<
3651 22:50:09.287542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3652 22:50:09.290756 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3653 22:50:09.297640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3654 22:50:09.304190 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3655 22:50:09.310789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3656 22:50:09.317427 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3657 22:50:09.320666 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3658 22:50:09.324149 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3659 22:50:09.327285 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3660 22:50:09.334010 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3661 22:50:09.337251 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3662 22:50:09.340642 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3663 22:50:09.344108 ===================================
3664 22:50:09.347127 LPDDR4 DRAM CONFIGURATION
3665 22:50:09.350558 ===================================
3666 22:50:09.350637 EX_ROW_EN[0] = 0x0
3667 22:50:09.353736 EX_ROW_EN[1] = 0x0
3668 22:50:09.357193 LP4Y_EN = 0x0
3669 22:50:09.357274 WORK_FSP = 0x0
3670 22:50:09.360528 WL = 0x2
3671 22:50:09.360608 RL = 0x2
3672 22:50:09.364116 BL = 0x2
3673 22:50:09.364195 RPST = 0x0
3674 22:50:09.367265 RD_PRE = 0x0
3675 22:50:09.367345 WR_PRE = 0x1
3676 22:50:09.370790 WR_PST = 0x0
3677 22:50:09.370869 DBI_WR = 0x0
3678 22:50:09.374528 DBI_RD = 0x0
3679 22:50:09.374607 OTF = 0x1
3680 22:50:09.377432 ===================================
3681 22:50:09.380861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3682 22:50:09.387092 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3683 22:50:09.390239 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3684 22:50:09.393550 ===================================
3685 22:50:09.396905 LPDDR4 DRAM CONFIGURATION
3686 22:50:09.400156 ===================================
3687 22:50:09.400236 EX_ROW_EN[0] = 0x10
3688 22:50:09.403713 EX_ROW_EN[1] = 0x0
3689 22:50:09.403792 LP4Y_EN = 0x0
3690 22:50:09.407001 WORK_FSP = 0x0
3691 22:50:09.407080 WL = 0x2
3692 22:50:09.410131 RL = 0x2
3693 22:50:09.413540 BL = 0x2
3694 22:50:09.413619 RPST = 0x0
3695 22:50:09.416685 RD_PRE = 0x0
3696 22:50:09.416764 WR_PRE = 0x1
3697 22:50:09.420070 WR_PST = 0x0
3698 22:50:09.420149 DBI_WR = 0x0
3699 22:50:09.423222 DBI_RD = 0x0
3700 22:50:09.423301 OTF = 0x1
3701 22:50:09.426615 ===================================
3702 22:50:09.433151 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3703 22:50:09.437447 nWR fixed to 30
3704 22:50:09.440849 [ModeRegInit_LP4] CH0 RK0
3705 22:50:09.440928 [ModeRegInit_LP4] CH0 RK1
3706 22:50:09.443905 [ModeRegInit_LP4] CH1 RK0
3707 22:50:09.447407 [ModeRegInit_LP4] CH1 RK1
3708 22:50:09.447486 match AC timing 16
3709 22:50:09.454105 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3710 22:50:09.457247 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3711 22:50:09.460546 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3712 22:50:09.467195 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3713 22:50:09.470465 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3714 22:50:09.470545 ==
3715 22:50:09.473779 Dram Type= 6, Freq= 0, CH_0, rank 0
3716 22:50:09.477073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3717 22:50:09.477153 ==
3718 22:50:09.483803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3719 22:50:09.490373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3720 22:50:09.493872 [CA 0] Center 35 (5~66) winsize 62
3721 22:50:09.497015 [CA 1] Center 35 (5~66) winsize 62
3722 22:50:09.500230 [CA 2] Center 34 (4~65) winsize 62
3723 22:50:09.503783 [CA 3] Center 34 (3~65) winsize 63
3724 22:50:09.506879 [CA 4] Center 33 (3~64) winsize 62
3725 22:50:09.510289 [CA 5] Center 33 (3~64) winsize 62
3726 22:50:09.510369
3727 22:50:09.513418 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3728 22:50:09.513498
3729 22:50:09.516841 [CATrainingPosCal] consider 1 rank data
3730 22:50:09.519997 u2DelayCellTimex100 = 270/100 ps
3731 22:50:09.523395 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3732 22:50:09.526981 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3733 22:50:09.530185 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3734 22:50:09.533544 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3735 22:50:09.536658 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3736 22:50:09.543352 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3737 22:50:09.543551
3738 22:50:09.546694 CA PerBit enable=1, Macro0, CA PI delay=33
3739 22:50:09.546836
3740 22:50:09.549938 [CBTSetCACLKResult] CA Dly = 33
3741 22:50:09.550051 CS Dly: 4 (0~35)
3742 22:50:09.550131 ==
3743 22:50:09.553592 Dram Type= 6, Freq= 0, CH_0, rank 1
3744 22:50:09.556644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3745 22:50:09.559964 ==
3746 22:50:09.563268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3747 22:50:09.569875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3748 22:50:09.573443 [CA 0] Center 35 (5~66) winsize 62
3749 22:50:09.576620 [CA 1] Center 35 (5~66) winsize 62
3750 22:50:09.579856 [CA 2] Center 34 (4~65) winsize 62
3751 22:50:09.583264 [CA 3] Center 34 (4~65) winsize 62
3752 22:50:09.586838 [CA 4] Center 33 (3~64) winsize 62
3753 22:50:09.590071 [CA 5] Center 33 (3~64) winsize 62
3754 22:50:09.590152
3755 22:50:09.593185 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3756 22:50:09.593266
3757 22:50:09.596488 [CATrainingPosCal] consider 2 rank data
3758 22:50:09.599827 u2DelayCellTimex100 = 270/100 ps
3759 22:50:09.603032 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3760 22:50:09.606504 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3761 22:50:09.609744 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3762 22:50:09.616456 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3763 22:50:09.619603 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3764 22:50:09.622912 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3765 22:50:09.622992
3766 22:50:09.626194 CA PerBit enable=1, Macro0, CA PI delay=33
3767 22:50:09.626275
3768 22:50:09.629533 [CBTSetCACLKResult] CA Dly = 33
3769 22:50:09.629614 CS Dly: 4 (0~35)
3770 22:50:09.629678
3771 22:50:09.633004 ----->DramcWriteLeveling(PI) begin...
3772 22:50:09.633087 ==
3773 22:50:09.636350 Dram Type= 6, Freq= 0, CH_0, rank 0
3774 22:50:09.643065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3775 22:50:09.643147 ==
3776 22:50:09.646268 Write leveling (Byte 0): 32 => 32
3777 22:50:09.649877 Write leveling (Byte 1): 31 => 31
3778 22:50:09.649958 DramcWriteLeveling(PI) end<-----
3779 22:50:09.650028
3780 22:50:09.653079 ==
3781 22:50:09.656328 Dram Type= 6, Freq= 0, CH_0, rank 0
3782 22:50:09.659612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3783 22:50:09.659694 ==
3784 22:50:09.662973 [Gating] SW mode calibration
3785 22:50:09.669569 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3786 22:50:09.673311 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3787 22:50:09.679599 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3788 22:50:09.682868 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3789 22:50:09.686074 0 5 8 | B1->B0 | 3030 2f2f | 1 1 | (1 0) (1 0)
3790 22:50:09.692780 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3791 22:50:09.696035 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3792 22:50:09.699342 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3793 22:50:09.706170 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3794 22:50:09.709229 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3795 22:50:09.712749 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3796 22:50:09.719293 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3797 22:50:09.722659 0 6 8 | B1->B0 | 2f2f 3535 | 0 0 | (0 0) (0 0)
3798 22:50:09.725827 0 6 12 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
3799 22:50:09.732454 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3800 22:50:09.735903 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3801 22:50:09.739015 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3802 22:50:09.745670 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3803 22:50:09.749156 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3804 22:50:09.752442 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 22:50:09.758990 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3806 22:50:09.762206 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3807 22:50:09.765709 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 22:50:09.772172 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 22:50:09.775631 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 22:50:09.778958 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 22:50:09.785565 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 22:50:09.788924 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 22:50:09.792531 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 22:50:09.795544 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 22:50:09.802132 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 22:50:09.805393 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 22:50:09.808735 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 22:50:09.815337 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 22:50:09.818877 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 22:50:09.822161 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 22:50:09.828854 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3822 22:50:09.832060 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3823 22:50:09.835305 Total UI for P1: 0, mck2ui 16
3824 22:50:09.838735 best dqsien dly found for B0: ( 0, 9, 10)
3825 22:50:09.842007 Total UI for P1: 0, mck2ui 16
3826 22:50:09.845313 best dqsien dly found for B1: ( 0, 9, 8)
3827 22:50:09.848583 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3828 22:50:09.852089 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3829 22:50:09.852168
3830 22:50:09.855420 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3831 22:50:09.858585 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3832 22:50:09.862006 [Gating] SW calibration Done
3833 22:50:09.862136 ==
3834 22:50:09.865319 Dram Type= 6, Freq= 0, CH_0, rank 0
3835 22:50:09.868510 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3836 22:50:09.871998 ==
3837 22:50:09.872077 RX Vref Scan: 0
3838 22:50:09.872139
3839 22:50:09.875199 RX Vref 0 -> 0, step: 1
3840 22:50:09.875278
3841 22:50:09.878382 RX Delay -230 -> 252, step: 16
3842 22:50:09.881695 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3843 22:50:09.885008 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3844 22:50:09.888343 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3845 22:50:09.895284 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3846 22:50:09.898362 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3847 22:50:09.901768 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3848 22:50:09.904971 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3849 22:50:09.908158 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3850 22:50:09.914842 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3851 22:50:09.918275 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3852 22:50:09.921550 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3853 22:50:09.924917 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3854 22:50:09.931373 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3855 22:50:09.934672 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3856 22:50:09.937980 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3857 22:50:09.941413 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3858 22:50:09.944634 ==
3859 22:50:09.944714 Dram Type= 6, Freq= 0, CH_0, rank 0
3860 22:50:09.951373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3861 22:50:09.951455 ==
3862 22:50:09.951518 DQS Delay:
3863 22:50:09.954721 DQS0 = 0, DQS1 = 0
3864 22:50:09.954801 DQM Delay:
3865 22:50:09.957948 DQM0 = 39, DQM1 = 33
3866 22:50:09.958055 DQ Delay:
3867 22:50:09.961530 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3868 22:50:09.964812 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3869 22:50:09.968216 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3870 22:50:09.971591 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3871 22:50:09.971672
3872 22:50:09.971734
3873 22:50:09.971793 ==
3874 22:50:09.974590 Dram Type= 6, Freq= 0, CH_0, rank 0
3875 22:50:09.977909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3876 22:50:09.977990 ==
3877 22:50:09.978061
3878 22:50:09.978120
3879 22:50:09.981064 TX Vref Scan disable
3880 22:50:09.984562 == TX Byte 0 ==
3881 22:50:09.987851 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3882 22:50:09.991038 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3883 22:50:09.994268 == TX Byte 1 ==
3884 22:50:09.997736 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3885 22:50:10.001030 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3886 22:50:10.001111 ==
3887 22:50:10.004406 Dram Type= 6, Freq= 0, CH_0, rank 0
3888 22:50:10.011057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3889 22:50:10.011139 ==
3890 22:50:10.011202
3891 22:50:10.011260
3892 22:50:10.011316 TX Vref Scan disable
3893 22:50:10.014918 == TX Byte 0 ==
3894 22:50:10.018302 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3895 22:50:10.021619 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3896 22:50:10.024955 == TX Byte 1 ==
3897 22:50:10.028661 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3898 22:50:10.035199 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3899 22:50:10.035280
3900 22:50:10.035341 [DATLAT]
3901 22:50:10.035399 Freq=600, CH0 RK0
3902 22:50:10.035455
3903 22:50:10.038208 DATLAT Default: 0x9
3904 22:50:10.038287 0, 0xFFFF, sum = 0
3905 22:50:10.041564 1, 0xFFFF, sum = 0
3906 22:50:10.041646 2, 0xFFFF, sum = 0
3907 22:50:10.044973 3, 0xFFFF, sum = 0
3908 22:50:10.048350 4, 0xFFFF, sum = 0
3909 22:50:10.048430 5, 0xFFFF, sum = 0
3910 22:50:10.051750 6, 0xFFFF, sum = 0
3911 22:50:10.051830 7, 0x0, sum = 1
3912 22:50:10.051893 8, 0x0, sum = 2
3913 22:50:10.054806 9, 0x0, sum = 3
3914 22:50:10.054885 10, 0x0, sum = 4
3915 22:50:10.058308 best_step = 8
3916 22:50:10.058389
3917 22:50:10.058451 ==
3918 22:50:10.061394 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 22:50:10.064670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3920 22:50:10.064750 ==
3921 22:50:10.068131 RX Vref Scan: 1
3922 22:50:10.068209
3923 22:50:10.068271 RX Vref 0 -> 0, step: 1
3924 22:50:10.068329
3925 22:50:10.071268 RX Delay -195 -> 252, step: 8
3926 22:50:10.071347
3927 22:50:10.074608 Set Vref, RX VrefLevel [Byte0]: 47
3928 22:50:10.078065 [Byte1]: 49
3929 22:50:10.082222
3930 22:50:10.082301 Final RX Vref Byte 0 = 47 to rank0
3931 22:50:10.085388 Final RX Vref Byte 1 = 49 to rank0
3932 22:50:10.088711 Final RX Vref Byte 0 = 47 to rank1
3933 22:50:10.092034 Final RX Vref Byte 1 = 49 to rank1==
3934 22:50:10.095297 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 22:50:10.101860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3936 22:50:10.101940 ==
3937 22:50:10.102002 DQS Delay:
3938 22:50:10.102096 DQS0 = 0, DQS1 = 0
3939 22:50:10.105289 DQM Delay:
3940 22:50:10.105366 DQM0 = 41, DQM1 = 30
3941 22:50:10.108582 DQ Delay:
3942 22:50:10.111891 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
3943 22:50:10.115324 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
3944 22:50:10.118416 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3945 22:50:10.121647 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
3946 22:50:10.121725
3947 22:50:10.121786
3948 22:50:10.128251 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
3949 22:50:10.131842 CH0 RK0: MR19=808, MR18=5151
3950 22:50:10.138488 CH0_RK0: MR19=0x808, MR18=0x5151, DQSOSC=394, MR23=63, INC=168, DEC=112
3951 22:50:10.138573
3952 22:50:10.141519 ----->DramcWriteLeveling(PI) begin...
3953 22:50:10.141603 ==
3954 22:50:10.145057 Dram Type= 6, Freq= 0, CH_0, rank 1
3955 22:50:10.148172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3956 22:50:10.148256 ==
3957 22:50:10.151620 Write leveling (Byte 0): 30 => 30
3958 22:50:10.154816 Write leveling (Byte 1): 29 => 29
3959 22:50:10.158363 DramcWriteLeveling(PI) end<-----
3960 22:50:10.158449
3961 22:50:10.158533 ==
3962 22:50:10.161444 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 22:50:10.164887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3964 22:50:10.164972 ==
3965 22:50:10.168235 [Gating] SW mode calibration
3966 22:50:10.174729 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3967 22:50:10.181305 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3968 22:50:10.184696 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 22:50:10.191682 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 22:50:10.194735 0 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
3971 22:50:10.197918 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 22:50:10.204798 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 22:50:10.208196 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 22:50:10.211194 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 22:50:10.217953 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 22:50:10.221056 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 22:50:10.224460 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 22:50:10.231494 0 6 8 | B1->B0 | 2626 2c2c | 0 1 | (0 0) (0 0)
3979 22:50:10.234394 0 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3980 22:50:10.237888 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 22:50:10.241028 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 22:50:10.247595 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 22:50:10.251152 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 22:50:10.254400 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 22:50:10.261164 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 22:50:10.264301 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3987 22:50:10.267549 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 22:50:10.274134 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 22:50:10.277351 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 22:50:10.280714 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 22:50:10.287354 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 22:50:10.290587 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 22:50:10.294029 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 22:50:10.300598 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 22:50:10.303891 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 22:50:10.307294 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 22:50:10.313880 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 22:50:10.317208 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 22:50:10.320726 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 22:50:10.327081 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 22:50:10.330397 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 22:50:10.333751 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4003 22:50:10.340550 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 22:50:10.340635 Total UI for P1: 0, mck2ui 16
4005 22:50:10.347245 best dqsien dly found for B0: ( 0, 9, 8)
4006 22:50:10.347333 Total UI for P1: 0, mck2ui 16
4007 22:50:10.353512 best dqsien dly found for B1: ( 0, 9, 8)
4008 22:50:10.356884 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4009 22:50:10.360187 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4010 22:50:10.360274
4011 22:50:10.363640 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4012 22:50:10.367250 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4013 22:50:10.370313 [Gating] SW calibration Done
4014 22:50:10.370398 ==
4015 22:50:10.373512 Dram Type= 6, Freq= 0, CH_0, rank 1
4016 22:50:10.376673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4017 22:50:10.376759 ==
4018 22:50:10.379979 RX Vref Scan: 0
4019 22:50:10.380062
4020 22:50:10.380145 RX Vref 0 -> 0, step: 1
4021 22:50:10.380224
4022 22:50:10.383338 RX Delay -230 -> 252, step: 16
4023 22:50:10.390201 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4024 22:50:10.393279 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4025 22:50:10.396628 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4026 22:50:10.399837 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4027 22:50:10.403159 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4028 22:50:10.409805 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4029 22:50:10.413077 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4030 22:50:10.416319 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4031 22:50:10.419794 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4032 22:50:10.426389 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4033 22:50:10.429527 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4034 22:50:10.432971 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4035 22:50:10.436128 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4036 22:50:10.442904 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4037 22:50:10.446433 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4038 22:50:10.449653 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4039 22:50:10.449733 ==
4040 22:50:10.452734 Dram Type= 6, Freq= 0, CH_0, rank 1
4041 22:50:10.456290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4042 22:50:10.456370 ==
4043 22:50:10.459485 DQS Delay:
4044 22:50:10.459566 DQS0 = 0, DQS1 = 0
4045 22:50:10.462814 DQM Delay:
4046 22:50:10.462894 DQM0 = 40, DQM1 = 33
4047 22:50:10.462956 DQ Delay:
4048 22:50:10.465967 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4049 22:50:10.469387 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4050 22:50:10.472898 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4051 22:50:10.476109 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4052 22:50:10.476188
4053 22:50:10.476250
4054 22:50:10.479497 ==
4055 22:50:10.479634 Dram Type= 6, Freq= 0, CH_0, rank 1
4056 22:50:10.486155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4057 22:50:10.486235 ==
4058 22:50:10.486297
4059 22:50:10.486355
4060 22:50:10.489287 TX Vref Scan disable
4061 22:50:10.489366 == TX Byte 0 ==
4062 22:50:10.492736 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4063 22:50:10.499343 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4064 22:50:10.499423 == TX Byte 1 ==
4065 22:50:10.506087 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4066 22:50:10.509229 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4067 22:50:10.509308 ==
4068 22:50:10.512413 Dram Type= 6, Freq= 0, CH_0, rank 1
4069 22:50:10.515769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4070 22:50:10.515849 ==
4071 22:50:10.515911
4072 22:50:10.515968
4073 22:50:10.519019 TX Vref Scan disable
4074 22:50:10.522465 == TX Byte 0 ==
4075 22:50:10.526013 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4076 22:50:10.529160 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4077 22:50:10.532491 == TX Byte 1 ==
4078 22:50:10.535712 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4079 22:50:10.539112 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4080 22:50:10.539192
4081 22:50:10.542375 [DATLAT]
4082 22:50:10.542455 Freq=600, CH0 RK1
4083 22:50:10.542519
4084 22:50:10.545792 DATLAT Default: 0x8
4085 22:50:10.545906 0, 0xFFFF, sum = 0
4086 22:50:10.549101 1, 0xFFFF, sum = 0
4087 22:50:10.549183 2, 0xFFFF, sum = 0
4088 22:50:10.552318 3, 0xFFFF, sum = 0
4089 22:50:10.552400 4, 0xFFFF, sum = 0
4090 22:50:10.555618 5, 0xFFFF, sum = 0
4091 22:50:10.555699 6, 0xFFFF, sum = 0
4092 22:50:10.559396 7, 0x0, sum = 1
4093 22:50:10.559479 8, 0x0, sum = 2
4094 22:50:10.562292 9, 0x0, sum = 3
4095 22:50:10.562400 10, 0x0, sum = 4
4096 22:50:10.565554 best_step = 8
4097 22:50:10.565637
4098 22:50:10.565736 ==
4099 22:50:10.568884 Dram Type= 6, Freq= 0, CH_0, rank 1
4100 22:50:10.572108 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4101 22:50:10.572193 ==
4102 22:50:10.572277 RX Vref Scan: 0
4103 22:50:10.575655
4104 22:50:10.575739 RX Vref 0 -> 0, step: 1
4105 22:50:10.575822
4106 22:50:10.578647 RX Delay -195 -> 252, step: 8
4107 22:50:10.585581 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4108 22:50:10.588912 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4109 22:50:10.592065 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4110 22:50:10.595482 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4111 22:50:10.601866 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4112 22:50:10.605212 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4113 22:50:10.608775 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4114 22:50:10.611816 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4115 22:50:10.618200 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4116 22:50:10.621757 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4117 22:50:10.625089 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4118 22:50:10.628629 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4119 22:50:10.634989 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4120 22:50:10.638132 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4121 22:50:10.641544 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4122 22:50:10.644775 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4123 22:50:10.644857 ==
4124 22:50:10.648318 Dram Type= 6, Freq= 0, CH_0, rank 1
4125 22:50:10.654942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4126 22:50:10.655026 ==
4127 22:50:10.655090 DQS Delay:
4128 22:50:10.658391 DQS0 = 0, DQS1 = 0
4129 22:50:10.658501 DQM Delay:
4130 22:50:10.658593 DQM0 = 40, DQM1 = 32
4131 22:50:10.661599 DQ Delay:
4132 22:50:10.664746 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4133 22:50:10.668052 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4134 22:50:10.671336 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4135 22:50:10.674702 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4136 22:50:10.674785
4137 22:50:10.674848
4138 22:50:10.681439 [DQSOSCAuto] RK1, (LSB)MR18= 0x6868, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4139 22:50:10.684510 CH0 RK1: MR19=808, MR18=6868
4140 22:50:10.691365 CH0_RK1: MR19=0x808, MR18=0x6868, DQSOSC=390, MR23=63, INC=172, DEC=114
4141 22:50:10.694565 [RxdqsGatingPostProcess] freq 600
4142 22:50:10.697871 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4143 22:50:10.701113 Pre-setting of DQS Precalculation
4144 22:50:10.707751 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4145 22:50:10.707833 ==
4146 22:50:10.711086 Dram Type= 6, Freq= 0, CH_1, rank 0
4147 22:50:10.714281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4148 22:50:10.714364 ==
4149 22:50:10.721095 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4150 22:50:10.727471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4151 22:50:10.730935 [CA 0] Center 35 (5~66) winsize 62
4152 22:50:10.734397 [CA 1] Center 35 (5~66) winsize 62
4153 22:50:10.737546 [CA 2] Center 33 (3~64) winsize 62
4154 22:50:10.740836 [CA 3] Center 33 (3~64) winsize 62
4155 22:50:10.743913 [CA 4] Center 33 (2~64) winsize 63
4156 22:50:10.747249 [CA 5] Center 33 (2~64) winsize 63
4157 22:50:10.747330
4158 22:50:10.750531 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4159 22:50:10.750612
4160 22:50:10.753808 [CATrainingPosCal] consider 1 rank data
4161 22:50:10.757166 u2DelayCellTimex100 = 270/100 ps
4162 22:50:10.760461 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4163 22:50:10.763920 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4164 22:50:10.767194 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4165 22:50:10.770522 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4166 22:50:10.773924 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4167 22:50:10.777221 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4168 22:50:10.777303
4169 22:50:10.783895 CA PerBit enable=1, Macro0, CA PI delay=33
4170 22:50:10.783978
4171 22:50:10.784042 [CBTSetCACLKResult] CA Dly = 33
4172 22:50:10.787163 CS Dly: 4 (0~35)
4173 22:50:10.787248 ==
4174 22:50:10.790478 Dram Type= 6, Freq= 0, CH_1, rank 1
4175 22:50:10.793771 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4176 22:50:10.793852 ==
4177 22:50:10.800251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4178 22:50:10.807368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4179 22:50:10.810383 [CA 0] Center 35 (5~66) winsize 62
4180 22:50:10.813677 [CA 1] Center 34 (4~65) winsize 62
4181 22:50:10.817071 [CA 2] Center 33 (3~64) winsize 62
4182 22:50:10.820289 [CA 3] Center 33 (3~64) winsize 62
4183 22:50:10.823651 [CA 4] Center 32 (2~63) winsize 62
4184 22:50:10.827309 [CA 5] Center 33 (2~64) winsize 63
4185 22:50:10.827391
4186 22:50:10.830410 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4187 22:50:10.830493
4188 22:50:10.833822 [CATrainingPosCal] consider 2 rank data
4189 22:50:10.836915 u2DelayCellTimex100 = 270/100 ps
4190 22:50:10.840413 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4191 22:50:10.843645 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4192 22:50:10.846921 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4193 22:50:10.850312 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4194 22:50:10.853616 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4195 22:50:10.856843 CA5 delay=33 (2~64),Diff = 1 PI (9 cell)
4196 22:50:10.860175
4197 22:50:10.863423 CA PerBit enable=1, Macro0, CA PI delay=32
4198 22:50:10.863506
4199 22:50:10.866855 [CBTSetCACLKResult] CA Dly = 32
4200 22:50:10.866937 CS Dly: 4 (0~35)
4201 22:50:10.867002
4202 22:50:10.870253 ----->DramcWriteLeveling(PI) begin...
4203 22:50:10.870337 ==
4204 22:50:10.873545 Dram Type= 6, Freq= 0, CH_1, rank 0
4205 22:50:10.876837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4206 22:50:10.880051 ==
4207 22:50:10.880133 Write leveling (Byte 0): 28 => 28
4208 22:50:10.883549 Write leveling (Byte 1): 28 => 28
4209 22:50:10.886897 DramcWriteLeveling(PI) end<-----
4210 22:50:10.886979
4211 22:50:10.887042 ==
4212 22:50:10.890175 Dram Type= 6, Freq= 0, CH_1, rank 0
4213 22:50:10.896911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4214 22:50:10.896996 ==
4215 22:50:10.897061 [Gating] SW mode calibration
4216 22:50:10.906685 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4217 22:50:10.910073 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4218 22:50:10.916602 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4219 22:50:10.920038 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4220 22:50:10.923210 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
4221 22:50:10.927153 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4222 22:50:10.933366 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 22:50:10.936259 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 22:50:10.939591 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 22:50:10.946691 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 22:50:10.949803 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 22:50:10.953093 0 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4228 22:50:10.959553 0 6 8 | B1->B0 | 3636 4242 | 0 0 | (1 1) (0 0)
4229 22:50:10.963144 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 22:50:10.966380 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 22:50:10.972819 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 22:50:10.976134 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 22:50:10.979505 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 22:50:10.986222 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 22:50:10.989986 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 22:50:10.992734 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4237 22:50:10.999426 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4238 22:50:11.002693 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 22:50:11.005841 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 22:50:11.012607 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 22:50:11.015845 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 22:50:11.019120 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 22:50:11.025781 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 22:50:11.029203 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 22:50:11.032458 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 22:50:11.039147 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 22:50:11.042411 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 22:50:11.045753 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 22:50:11.052321 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 22:50:11.055681 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 22:50:11.059234 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4252 22:50:11.065603 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 22:50:11.065683 Total UI for P1: 0, mck2ui 16
4254 22:50:11.072314 best dqsien dly found for B0: ( 0, 9, 4)
4255 22:50:11.072393 Total UI for P1: 0, mck2ui 16
4256 22:50:11.075557 best dqsien dly found for B1: ( 0, 9, 6)
4257 22:50:11.082173 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4258 22:50:11.085467 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4259 22:50:11.085546
4260 22:50:11.088736 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4261 22:50:11.092282 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4262 22:50:11.095528 [Gating] SW calibration Done
4263 22:50:11.095608 ==
4264 22:50:11.099095 Dram Type= 6, Freq= 0, CH_1, rank 0
4265 22:50:11.102229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4266 22:50:11.102309 ==
4267 22:50:11.105522 RX Vref Scan: 0
4268 22:50:11.105600
4269 22:50:11.105662 RX Vref 0 -> 0, step: 1
4270 22:50:11.105720
4271 22:50:11.108803 RX Delay -230 -> 252, step: 16
4272 22:50:11.112055 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4273 22:50:11.118550 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4274 22:50:11.121862 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4275 22:50:11.125525 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4276 22:50:11.128881 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4277 22:50:11.135225 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4278 22:50:11.138461 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4279 22:50:11.141698 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4280 22:50:11.145165 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4281 22:50:11.148462 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4282 22:50:11.154984 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4283 22:50:11.158564 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4284 22:50:11.161573 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4285 22:50:11.165134 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4286 22:50:11.171631 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4287 22:50:11.175409 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4288 22:50:11.175491 ==
4289 22:50:11.178240 Dram Type= 6, Freq= 0, CH_1, rank 0
4290 22:50:11.181903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4291 22:50:11.181985 ==
4292 22:50:11.185532 DQS Delay:
4293 22:50:11.185613 DQS0 = 0, DQS1 = 0
4294 22:50:11.185676 DQM Delay:
4295 22:50:11.188333 DQM0 = 39, DQM1 = 32
4296 22:50:11.188415 DQ Delay:
4297 22:50:11.191583 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4298 22:50:11.194974 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4299 22:50:11.198395 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4300 22:50:11.201388 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4301 22:50:11.201468
4302 22:50:11.201531
4303 22:50:11.201591 ==
4304 22:50:11.204883 Dram Type= 6, Freq= 0, CH_1, rank 0
4305 22:50:11.211402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4306 22:50:11.211483 ==
4307 22:50:11.211547
4308 22:50:11.211606
4309 22:50:11.211662 TX Vref Scan disable
4310 22:50:11.215171 == TX Byte 0 ==
4311 22:50:11.218405 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4312 22:50:11.225052 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4313 22:50:11.225133 == TX Byte 1 ==
4314 22:50:11.228379 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4315 22:50:11.234982 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4316 22:50:11.235062 ==
4317 22:50:11.238183 Dram Type= 6, Freq= 0, CH_1, rank 0
4318 22:50:11.241579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4319 22:50:11.241660 ==
4320 22:50:11.241723
4321 22:50:11.241781
4322 22:50:11.245133 TX Vref Scan disable
4323 22:50:11.248466 == TX Byte 0 ==
4324 22:50:11.251629 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4325 22:50:11.254980 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4326 22:50:11.258636 == TX Byte 1 ==
4327 22:50:11.261640 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4328 22:50:11.265043 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4329 22:50:11.265126
4330 22:50:11.265189 [DATLAT]
4331 22:50:11.268198 Freq=600, CH1 RK0
4332 22:50:11.268279
4333 22:50:11.268343 DATLAT Default: 0x9
4334 22:50:11.271602 0, 0xFFFF, sum = 0
4335 22:50:11.271685 1, 0xFFFF, sum = 0
4336 22:50:11.274858 2, 0xFFFF, sum = 0
4337 22:50:11.278065 3, 0xFFFF, sum = 0
4338 22:50:11.278147 4, 0xFFFF, sum = 0
4339 22:50:11.281648 5, 0xFFFF, sum = 0
4340 22:50:11.281729 6, 0xFFFF, sum = 0
4341 22:50:11.284844 7, 0x0, sum = 1
4342 22:50:11.284926 8, 0x0, sum = 2
4343 22:50:11.284990 9, 0x0, sum = 3
4344 22:50:11.288020 10, 0x0, sum = 4
4345 22:50:11.288101 best_step = 8
4346 22:50:11.288164
4347 22:50:11.288223 ==
4348 22:50:11.291764 Dram Type= 6, Freq= 0, CH_1, rank 0
4349 22:50:11.298135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4350 22:50:11.298217 ==
4351 22:50:11.298281 RX Vref Scan: 1
4352 22:50:11.298341
4353 22:50:11.301467 RX Vref 0 -> 0, step: 1
4354 22:50:11.301547
4355 22:50:11.304631 RX Delay -195 -> 252, step: 8
4356 22:50:11.304713
4357 22:50:11.307931 Set Vref, RX VrefLevel [Byte0]: 56
4358 22:50:11.311207 [Byte1]: 49
4359 22:50:11.311288
4360 22:50:11.314789 Final RX Vref Byte 0 = 56 to rank0
4361 22:50:11.317856 Final RX Vref Byte 1 = 49 to rank0
4362 22:50:11.321148 Final RX Vref Byte 0 = 56 to rank1
4363 22:50:11.324699 Final RX Vref Byte 1 = 49 to rank1==
4364 22:50:11.327802 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 22:50:11.331191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 22:50:11.331271 ==
4367 22:50:11.334406 DQS Delay:
4368 22:50:11.334486 DQS0 = 0, DQS1 = 0
4369 22:50:11.337793 DQM Delay:
4370 22:50:11.337872 DQM0 = 38, DQM1 = 30
4371 22:50:11.337933 DQ Delay:
4372 22:50:11.341189 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4373 22:50:11.344329 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4374 22:50:11.347636 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4375 22:50:11.350994 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4376 22:50:11.351074
4377 22:50:11.351135
4378 22:50:11.361053 [DQSOSCAuto] RK0, (LSB)MR18= 0x8080, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4379 22:50:11.364422 CH1 RK0: MR19=808, MR18=8080
4380 22:50:11.370904 CH1_RK0: MR19=0x808, MR18=0x8080, DQSOSC=386, MR23=63, INC=176, DEC=117
4381 22:50:11.370985
4382 22:50:11.374243 ----->DramcWriteLeveling(PI) begin...
4383 22:50:11.374324 ==
4384 22:50:11.377772 Dram Type= 6, Freq= 0, CH_1, rank 1
4385 22:50:11.380937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4386 22:50:11.381017 ==
4387 22:50:11.384231 Write leveling (Byte 0): 27 => 27
4388 22:50:11.387322 Write leveling (Byte 1): 27 => 27
4389 22:50:11.391054 DramcWriteLeveling(PI) end<-----
4390 22:50:11.391133
4391 22:50:11.391196 ==
4392 22:50:11.394241 Dram Type= 6, Freq= 0, CH_1, rank 1
4393 22:50:11.397595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4394 22:50:11.397676 ==
4395 22:50:11.400656 [Gating] SW mode calibration
4396 22:50:11.407706 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4397 22:50:11.414443 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4398 22:50:11.417743 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4399 22:50:11.421357 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4400 22:50:11.427735 0 5 8 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
4401 22:50:11.431026 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 22:50:11.434189 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 22:50:11.440746 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 22:50:11.444361 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 22:50:11.447517 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 22:50:11.453999 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 22:50:11.457270 0 6 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4408 22:50:11.460754 0 6 8 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
4409 22:50:11.467273 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 22:50:11.470605 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 22:50:11.474095 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 22:50:11.480787 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 22:50:11.483918 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 22:50:11.487396 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 22:50:11.493875 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4416 22:50:11.497138 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4417 22:50:11.500256 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 22:50:11.509411 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 22:50:11.510445 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 22:50:11.513541 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 22:50:11.520359 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 22:50:11.523585 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 22:50:11.526784 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 22:50:11.533504 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 22:50:11.536661 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 22:50:11.540011 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 22:50:11.546434 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 22:50:11.549668 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 22:50:11.553297 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 22:50:11.556385 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 22:50:11.563000 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 22:50:11.566427 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 22:50:11.569570 Total UI for P1: 0, mck2ui 16
4434 22:50:11.573038 best dqsien dly found for B0: ( 0, 9, 6)
4435 22:50:11.576221 Total UI for P1: 0, mck2ui 16
4436 22:50:11.579543 best dqsien dly found for B1: ( 0, 9, 6)
4437 22:50:11.583025 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4438 22:50:11.586247 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4439 22:50:11.586350
4440 22:50:11.589449 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4441 22:50:11.592902 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4442 22:50:11.596214 [Gating] SW calibration Done
4443 22:50:11.596316 ==
4444 22:50:11.599383 Dram Type= 6, Freq= 0, CH_1, rank 1
4445 22:50:11.605994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4446 22:50:11.606091 ==
4447 22:50:11.606156 RX Vref Scan: 0
4448 22:50:11.606216
4449 22:50:11.609200 RX Vref 0 -> 0, step: 1
4450 22:50:11.609280
4451 22:50:11.612539 RX Delay -230 -> 252, step: 16
4452 22:50:11.615847 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4453 22:50:11.619002 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4454 22:50:11.622580 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4455 22:50:11.629184 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4456 22:50:11.632672 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4457 22:50:11.635666 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4458 22:50:11.639024 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4459 22:50:11.645684 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4460 22:50:11.648860 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4461 22:50:11.652159 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4462 22:50:11.655733 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4463 22:50:11.662180 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4464 22:50:11.665394 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4465 22:50:11.668823 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4466 22:50:11.672068 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4467 22:50:11.679030 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4468 22:50:11.679114 ==
4469 22:50:11.682034 Dram Type= 6, Freq= 0, CH_1, rank 1
4470 22:50:11.685330 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4471 22:50:11.685414 ==
4472 22:50:11.685478 DQS Delay:
4473 22:50:11.688832 DQS0 = 0, DQS1 = 0
4474 22:50:11.688913 DQM Delay:
4475 22:50:11.692091 DQM0 = 40, DQM1 = 34
4476 22:50:11.692174 DQ Delay:
4477 22:50:11.695351 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4478 22:50:11.698760 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4479 22:50:11.702020 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4480 22:50:11.705392 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4481 22:50:11.705473
4482 22:50:11.705537
4483 22:50:11.705597 ==
4484 22:50:11.708852 Dram Type= 6, Freq= 0, CH_1, rank 1
4485 22:50:11.711813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4486 22:50:11.711896 ==
4487 22:50:11.711960
4488 22:50:11.712019
4489 22:50:11.715110 TX Vref Scan disable
4490 22:50:11.718634 == TX Byte 0 ==
4491 22:50:11.721722 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4492 22:50:11.725157 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4493 22:50:11.728435 == TX Byte 1 ==
4494 22:50:11.731723 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4495 22:50:11.735199 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4496 22:50:11.735281 ==
4497 22:50:11.738464 Dram Type= 6, Freq= 0, CH_1, rank 1
4498 22:50:11.744958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4499 22:50:11.745041 ==
4500 22:50:11.745105
4501 22:50:11.745165
4502 22:50:11.745222 TX Vref Scan disable
4503 22:50:11.749350 == TX Byte 0 ==
4504 22:50:11.752511 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4505 22:50:11.759061 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4506 22:50:11.759145 == TX Byte 1 ==
4507 22:50:11.762359 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4508 22:50:11.769031 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4509 22:50:11.769115
4510 22:50:11.769179 [DATLAT]
4511 22:50:11.769239 Freq=600, CH1 RK1
4512 22:50:11.769297
4513 22:50:11.772576 DATLAT Default: 0x8
4514 22:50:11.772657 0, 0xFFFF, sum = 0
4515 22:50:11.775769 1, 0xFFFF, sum = 0
4516 22:50:11.779046 2, 0xFFFF, sum = 0
4517 22:50:11.779128 3, 0xFFFF, sum = 0
4518 22:50:11.782246 4, 0xFFFF, sum = 0
4519 22:50:11.782330 5, 0xFFFF, sum = 0
4520 22:50:11.785791 6, 0xFFFF, sum = 0
4521 22:50:11.785898 7, 0x0, sum = 1
4522 22:50:11.785987 8, 0x0, sum = 2
4523 22:50:11.788822 9, 0x0, sum = 3
4524 22:50:11.788904 10, 0x0, sum = 4
4525 22:50:11.792231 best_step = 8
4526 22:50:11.792313
4527 22:50:11.792377 ==
4528 22:50:11.795780 Dram Type= 6, Freq= 0, CH_1, rank 1
4529 22:50:11.798873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4530 22:50:11.798955 ==
4531 22:50:11.802223 RX Vref Scan: 0
4532 22:50:11.802307
4533 22:50:11.802374 RX Vref 0 -> 0, step: 1
4534 22:50:11.802435
4535 22:50:11.805355 RX Delay -195 -> 252, step: 8
4536 22:50:11.813156 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4537 22:50:11.816168 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4538 22:50:11.819379 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4539 22:50:11.822854 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4540 22:50:11.829356 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4541 22:50:11.832805 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4542 22:50:11.836082 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4543 22:50:11.839292 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4544 22:50:11.845942 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4545 22:50:11.849369 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4546 22:50:11.852591 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4547 22:50:11.855889 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4548 22:50:11.859357 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4549 22:50:11.865745 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4550 22:50:11.869191 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4551 22:50:11.872389 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4552 22:50:11.872472 ==
4553 22:50:11.875678 Dram Type= 6, Freq= 0, CH_1, rank 1
4554 22:50:11.882253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4555 22:50:11.882338 ==
4556 22:50:11.882423 DQS Delay:
4557 22:50:11.885638 DQS0 = 0, DQS1 = 0
4558 22:50:11.885722 DQM Delay:
4559 22:50:11.885806 DQM0 = 37, DQM1 = 29
4560 22:50:11.888722 DQ Delay:
4561 22:50:11.892203 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4562 22:50:11.895618 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4563 22:50:11.898893 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4564 22:50:11.902289 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4565 22:50:11.902372
4566 22:50:11.902459
4567 22:50:11.908914 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4568 22:50:11.912117 CH1 RK1: MR19=808, MR18=6464
4569 22:50:11.918890 CH1_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4570 22:50:11.922299 [RxdqsGatingPostProcess] freq 600
4571 22:50:11.925480 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4572 22:50:11.928680 Pre-setting of DQS Precalculation
4573 22:50:11.935361 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4574 22:50:11.942001 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4575 22:50:11.948898 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4576 22:50:11.949070
4577 22:50:11.949194
4578 22:50:11.952401 [Calibration Summary] 1200 Mbps
4579 22:50:11.952542 CH 0, Rank 0
4580 22:50:11.955360 SW Impedance : PASS
4581 22:50:11.958503 DUTY Scan : NO K
4582 22:50:11.958693 ZQ Calibration : PASS
4583 22:50:11.962135 Jitter Meter : NO K
4584 22:50:11.965588 CBT Training : PASS
4585 22:50:11.965712 Write leveling : PASS
4586 22:50:11.969270 RX DQS gating : PASS
4587 22:50:11.972279 RX DQ/DQS(RDDQC) : PASS
4588 22:50:11.972494 TX DQ/DQS : PASS
4589 22:50:11.975577 RX DATLAT : PASS
4590 22:50:11.975810 RX DQ/DQS(Engine): PASS
4591 22:50:11.978797 TX OE : NO K
4592 22:50:11.978961 All Pass.
4593 22:50:11.979081
4594 22:50:11.982068 CH 0, Rank 1
4595 22:50:11.982237 SW Impedance : PASS
4596 22:50:11.985715 DUTY Scan : NO K
4597 22:50:11.988903 ZQ Calibration : PASS
4598 22:50:11.989187 Jitter Meter : NO K
4599 22:50:11.992207 CBT Training : PASS
4600 22:50:11.995559 Write leveling : PASS
4601 22:50:11.995948 RX DQS gating : PASS
4602 22:50:11.999105 RX DQ/DQS(RDDQC) : PASS
4603 22:50:12.002414 TX DQ/DQS : PASS
4604 22:50:12.002898 RX DATLAT : PASS
4605 22:50:12.005725 RX DQ/DQS(Engine): PASS
4606 22:50:12.009546 TX OE : NO K
4607 22:50:12.010101 All Pass.
4608 22:50:12.010440
4609 22:50:12.010746 CH 1, Rank 0
4610 22:50:12.012372 SW Impedance : PASS
4611 22:50:12.015641 DUTY Scan : NO K
4612 22:50:12.016153 ZQ Calibration : PASS
4613 22:50:12.018825 Jitter Meter : NO K
4614 22:50:12.022216 CBT Training : PASS
4615 22:50:12.022732 Write leveling : PASS
4616 22:50:12.025584 RX DQS gating : PASS
4617 22:50:12.028925 RX DQ/DQS(RDDQC) : PASS
4618 22:50:12.029445 TX DQ/DQS : PASS
4619 22:50:12.032206 RX DATLAT : PASS
4620 22:50:12.035337 RX DQ/DQS(Engine): PASS
4621 22:50:12.035752 TX OE : NO K
4622 22:50:12.036078 All Pass.
4623 22:50:12.038517
4624 22:50:12.038940 CH 1, Rank 1
4625 22:50:12.041887 SW Impedance : PASS
4626 22:50:12.042429 DUTY Scan : NO K
4627 22:50:12.045374 ZQ Calibration : PASS
4628 22:50:12.045896 Jitter Meter : NO K
4629 22:50:12.048548 CBT Training : PASS
4630 22:50:12.052158 Write leveling : PASS
4631 22:50:12.052671 RX DQS gating : PASS
4632 22:50:12.055323 RX DQ/DQS(RDDQC) : PASS
4633 22:50:12.058470 TX DQ/DQS : PASS
4634 22:50:12.058909 RX DATLAT : PASS
4635 22:50:12.061656 RX DQ/DQS(Engine): PASS
4636 22:50:12.065441 TX OE : NO K
4637 22:50:12.065969 All Pass.
4638 22:50:12.066461
4639 22:50:12.068279 DramC Write-DBI off
4640 22:50:12.068711 PER_BANK_REFRESH: Hybrid Mode
4641 22:50:12.071654 TX_TRACKING: ON
4642 22:50:12.081789 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4643 22:50:12.084956 [FAST_K] Save calibration result to emmc
4644 22:50:12.088301 dramc_set_vcore_voltage set vcore to 662500
4645 22:50:12.088831 Read voltage for 933, 3
4646 22:50:12.091707 Vio18 = 0
4647 22:50:12.092235 Vcore = 662500
4648 22:50:12.092678 Vdram = 0
4649 22:50:12.094624 Vddq = 0
4650 22:50:12.095056 Vmddr = 0
4651 22:50:12.098298 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4652 22:50:12.105335 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4653 22:50:12.108284 MEM_TYPE=3, freq_sel=17
4654 22:50:12.111595 sv_algorithm_assistance_LP4_1600
4655 22:50:12.114663 ============ PULL DRAM RESETB DOWN ============
4656 22:50:12.118148 ========== PULL DRAM RESETB DOWN end =========
4657 22:50:12.124774 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4658 22:50:12.127952 ===================================
4659 22:50:12.128484 LPDDR4 DRAM CONFIGURATION
4660 22:50:12.131308 ===================================
4661 22:50:12.134966 EX_ROW_EN[0] = 0x0
4662 22:50:12.137903 EX_ROW_EN[1] = 0x0
4663 22:50:12.138484 LP4Y_EN = 0x0
4664 22:50:12.141093 WORK_FSP = 0x0
4665 22:50:12.141541 WL = 0x3
4666 22:50:12.144577 RL = 0x3
4667 22:50:12.145103 BL = 0x2
4668 22:50:12.147600 RPST = 0x0
4669 22:50:12.148058 RD_PRE = 0x0
4670 22:50:12.150911 WR_PRE = 0x1
4671 22:50:12.151434 WR_PST = 0x0
4672 22:50:12.154104 DBI_WR = 0x0
4673 22:50:12.154626 DBI_RD = 0x0
4674 22:50:12.157457 OTF = 0x1
4675 22:50:12.160679 ===================================
4676 22:50:12.164096 ===================================
4677 22:50:12.164532 ANA top config
4678 22:50:12.167287 ===================================
4679 22:50:12.170589 DLL_ASYNC_EN = 0
4680 22:50:12.173831 ALL_SLAVE_EN = 1
4681 22:50:12.177466 NEW_RANK_MODE = 1
4682 22:50:12.177904 DLL_IDLE_MODE = 1
4683 22:50:12.180812 LP45_APHY_COMB_EN = 1
4684 22:50:12.184040 TX_ODT_DIS = 1
4685 22:50:12.187645 NEW_8X_MODE = 1
4686 22:50:12.190754 ===================================
4687 22:50:12.193870 ===================================
4688 22:50:12.197381 data_rate = 1866
4689 22:50:12.197910 CKR = 1
4690 22:50:12.200250 DQ_P2S_RATIO = 8
4691 22:50:12.204206 ===================================
4692 22:50:12.207428 CA_P2S_RATIO = 8
4693 22:50:12.210180 DQ_CA_OPEN = 0
4694 22:50:12.213871 DQ_SEMI_OPEN = 0
4695 22:50:12.217143 CA_SEMI_OPEN = 0
4696 22:50:12.217672 CA_FULL_RATE = 0
4697 22:50:12.220518 DQ_CKDIV4_EN = 1
4698 22:50:12.223550 CA_CKDIV4_EN = 1
4699 22:50:12.227201 CA_PREDIV_EN = 0
4700 22:50:12.230270 PH8_DLY = 0
4701 22:50:12.233878 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4702 22:50:12.234449 DQ_AAMCK_DIV = 4
4703 22:50:12.236918 CA_AAMCK_DIV = 4
4704 22:50:12.239908 CA_ADMCK_DIV = 4
4705 22:50:12.243522 DQ_TRACK_CA_EN = 0
4706 22:50:12.246809 CA_PICK = 933
4707 22:50:12.250798 CA_MCKIO = 933
4708 22:50:12.251327 MCKIO_SEMI = 0
4709 22:50:12.253715 PLL_FREQ = 3732
4710 22:50:12.256578 DQ_UI_PI_RATIO = 32
4711 22:50:12.260507 CA_UI_PI_RATIO = 0
4712 22:50:12.263305 ===================================
4713 22:50:12.266497 ===================================
4714 22:50:12.269915 memory_type:LPDDR4
4715 22:50:12.270380 GP_NUM : 10
4716 22:50:12.273474 SRAM_EN : 1
4717 22:50:12.276520 MD32_EN : 0
4718 22:50:12.279880 ===================================
4719 22:50:12.280299 [ANA_INIT] >>>>>>>>>>>>>>
4720 22:50:12.283143 <<<<<< [CONFIGURE PHASE]: ANA_TX
4721 22:50:12.286335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4722 22:50:12.290131 ===================================
4723 22:50:12.293356 data_rate = 1866,PCW = 0X8f00
4724 22:50:12.296599 ===================================
4725 22:50:12.299911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4726 22:50:12.306480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4727 22:50:12.309570 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4728 22:50:12.316491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4729 22:50:12.319901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4730 22:50:12.323320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4731 22:50:12.323804 [ANA_INIT] flow start
4732 22:50:12.326758 [ANA_INIT] PLL >>>>>>>>
4733 22:50:12.329717 [ANA_INIT] PLL <<<<<<<<
4734 22:50:12.332912 [ANA_INIT] MIDPI >>>>>>>>
4735 22:50:12.333392 [ANA_INIT] MIDPI <<<<<<<<
4736 22:50:12.336096 [ANA_INIT] DLL >>>>>>>>
4737 22:50:12.339734 [ANA_INIT] flow end
4738 22:50:12.342939 ============ LP4 DIFF to SE enter ============
4739 22:50:12.346179 ============ LP4 DIFF to SE exit ============
4740 22:50:12.349397 [ANA_INIT] <<<<<<<<<<<<<
4741 22:50:12.352502 [Flow] Enable top DCM control >>>>>
4742 22:50:12.356428 [Flow] Enable top DCM control <<<<<
4743 22:50:12.359378 Enable DLL master slave shuffle
4744 22:50:12.362378 ==============================================================
4745 22:50:12.365748 Gating Mode config
4746 22:50:12.372646 ==============================================================
4747 22:50:12.373167 Config description:
4748 22:50:12.382598 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4749 22:50:12.389103 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4750 22:50:12.392585 SELPH_MODE 0: By rank 1: By Phase
4751 22:50:12.399394 ==============================================================
4752 22:50:12.402472 GAT_TRACK_EN = 1
4753 22:50:12.406000 RX_GATING_MODE = 2
4754 22:50:12.409088 RX_GATING_TRACK_MODE = 2
4755 22:50:12.412340 SELPH_MODE = 1
4756 22:50:12.415738 PICG_EARLY_EN = 1
4757 22:50:12.419434 VALID_LAT_VALUE = 1
4758 22:50:12.422555 ==============================================================
4759 22:50:12.425607 Enter into Gating configuration >>>>
4760 22:50:12.428994 Exit from Gating configuration <<<<
4761 22:50:12.431894 Enter into DVFS_PRE_config >>>>>
4762 22:50:12.445677 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4763 22:50:12.446267 Exit from DVFS_PRE_config <<<<<
4764 22:50:12.448630 Enter into PICG configuration >>>>
4765 22:50:12.452078 Exit from PICG configuration <<<<
4766 22:50:12.455787 [RX_INPUT] configuration >>>>>
4767 22:50:12.459052 [RX_INPUT] configuration <<<<<
4768 22:50:12.465208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4769 22:50:12.468687 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4770 22:50:12.475593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4771 22:50:12.481873 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4772 22:50:12.488540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4773 22:50:12.495252 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4774 22:50:12.498619 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4775 22:50:12.501882 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4776 22:50:12.504862 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4777 22:50:12.511611 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4778 22:50:12.514673 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4779 22:50:12.518558 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4780 22:50:12.521759 ===================================
4781 22:50:12.524785 LPDDR4 DRAM CONFIGURATION
4782 22:50:12.528161 ===================================
4783 22:50:12.531548 EX_ROW_EN[0] = 0x0
4784 22:50:12.532061 EX_ROW_EN[1] = 0x0
4785 22:50:12.534676 LP4Y_EN = 0x0
4786 22:50:12.535190 WORK_FSP = 0x0
4787 22:50:12.538190 WL = 0x3
4788 22:50:12.538705 RL = 0x3
4789 22:50:12.541035 BL = 0x2
4790 22:50:12.541451 RPST = 0x0
4791 22:50:12.544600 RD_PRE = 0x0
4792 22:50:12.545142 WR_PRE = 0x1
4793 22:50:12.547857 WR_PST = 0x0
4794 22:50:12.548277 DBI_WR = 0x0
4795 22:50:12.551236 DBI_RD = 0x0
4796 22:50:12.551752 OTF = 0x1
4797 22:50:12.554641 ===================================
4798 22:50:12.561066 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4799 22:50:12.564173 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4800 22:50:12.567372 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4801 22:50:12.571226 ===================================
4802 22:50:12.574546 LPDDR4 DRAM CONFIGURATION
4803 22:50:12.577550 ===================================
4804 22:50:12.581038 EX_ROW_EN[0] = 0x10
4805 22:50:12.581456 EX_ROW_EN[1] = 0x0
4806 22:50:12.584466 LP4Y_EN = 0x0
4807 22:50:12.584980 WORK_FSP = 0x0
4808 22:50:12.587295 WL = 0x3
4809 22:50:12.587813 RL = 0x3
4810 22:50:12.590949 BL = 0x2
4811 22:50:12.591467 RPST = 0x0
4812 22:50:12.594004 RD_PRE = 0x0
4813 22:50:12.594563 WR_PRE = 0x1
4814 22:50:12.597121 WR_PST = 0x0
4815 22:50:12.597639 DBI_WR = 0x0
4816 22:50:12.600737 DBI_RD = 0x0
4817 22:50:12.603702 OTF = 0x1
4818 22:50:12.604124 ===================================
4819 22:50:12.610341 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4820 22:50:12.615875 nWR fixed to 30
4821 22:50:12.619157 [ModeRegInit_LP4] CH0 RK0
4822 22:50:12.619676 [ModeRegInit_LP4] CH0 RK1
4823 22:50:12.622457 [ModeRegInit_LP4] CH1 RK0
4824 22:50:12.625632 [ModeRegInit_LP4] CH1 RK1
4825 22:50:12.626171 match AC timing 8
4826 22:50:12.632427 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4827 22:50:12.635645 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4828 22:50:12.638848 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4829 22:50:12.645684 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4830 22:50:12.648646 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4831 22:50:12.649080 ==
4832 22:50:12.652155 Dram Type= 6, Freq= 0, CH_0, rank 0
4833 22:50:12.655466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4834 22:50:12.656000 ==
4835 22:50:12.661899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4836 22:50:12.668577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4837 22:50:12.671727 [CA 0] Center 38 (8~69) winsize 62
4838 22:50:12.675370 [CA 1] Center 38 (8~69) winsize 62
4839 22:50:12.678697 [CA 2] Center 36 (6~67) winsize 62
4840 22:50:12.681779 [CA 3] Center 36 (5~67) winsize 63
4841 22:50:12.685417 [CA 4] Center 34 (4~65) winsize 62
4842 22:50:12.688541 [CA 5] Center 34 (4~65) winsize 62
4843 22:50:12.689060
4844 22:50:12.691928 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4845 22:50:12.692447
4846 22:50:12.695473 [CATrainingPosCal] consider 1 rank data
4847 22:50:12.698981 u2DelayCellTimex100 = 270/100 ps
4848 22:50:12.701920 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4849 22:50:12.705367 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4850 22:50:12.708763 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4851 22:50:12.711914 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4852 22:50:12.715018 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4853 22:50:12.721812 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4854 22:50:12.722377
4855 22:50:12.724684 CA PerBit enable=1, Macro0, CA PI delay=34
4856 22:50:12.725100
4857 22:50:12.728352 [CBTSetCACLKResult] CA Dly = 34
4858 22:50:12.728873 CS Dly: 7 (0~38)
4859 22:50:12.729261 ==
4860 22:50:12.731625 Dram Type= 6, Freq= 0, CH_0, rank 1
4861 22:50:12.734996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4862 22:50:12.738348 ==
4863 22:50:12.741593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4864 22:50:12.748178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4865 22:50:12.751758 [CA 0] Center 38 (8~69) winsize 62
4866 22:50:12.754807 [CA 1] Center 38 (8~69) winsize 62
4867 22:50:12.758350 [CA 2] Center 36 (5~67) winsize 63
4868 22:50:12.761269 [CA 3] Center 35 (5~66) winsize 62
4869 22:50:12.764513 [CA 4] Center 34 (4~65) winsize 62
4870 22:50:12.767779 [CA 5] Center 34 (4~65) winsize 62
4871 22:50:12.768201
4872 22:50:12.771133 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4873 22:50:12.771598
4874 22:50:12.774469 [CATrainingPosCal] consider 2 rank data
4875 22:50:12.777639 u2DelayCellTimex100 = 270/100 ps
4876 22:50:12.781476 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4877 22:50:12.784554 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4878 22:50:12.788017 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4879 22:50:12.791442 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4880 22:50:12.797711 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4881 22:50:12.801239 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4882 22:50:12.801758
4883 22:50:12.804630 CA PerBit enable=1, Macro0, CA PI delay=34
4884 22:50:12.805157
4885 22:50:12.807879 [CBTSetCACLKResult] CA Dly = 34
4886 22:50:12.808403 CS Dly: 7 (0~39)
4887 22:50:12.808736
4888 22:50:12.811195 ----->DramcWriteLeveling(PI) begin...
4889 22:50:12.811729 ==
4890 22:50:12.814372 Dram Type= 6, Freq= 0, CH_0, rank 0
4891 22:50:12.820714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4892 22:50:12.821222 ==
4893 22:50:12.824253 Write leveling (Byte 0): 28 => 28
4894 22:50:12.827449 Write leveling (Byte 1): 26 => 26
4895 22:50:12.827975 DramcWriteLeveling(PI) end<-----
4896 22:50:12.830761
4897 22:50:12.831176 ==
4898 22:50:12.834238 Dram Type= 6, Freq= 0, CH_0, rank 0
4899 22:50:12.837672 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4900 22:50:12.838262 ==
4901 22:50:12.840895 [Gating] SW mode calibration
4902 22:50:12.847949 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4903 22:50:12.850532 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4904 22:50:12.857024 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4905 22:50:12.860794 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4906 22:50:12.863708 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4907 22:50:12.870565 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4908 22:50:12.873884 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4909 22:50:12.877026 0 10 20 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 1)
4910 22:50:12.883729 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4911 22:50:12.887410 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4912 22:50:12.890649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4913 22:50:12.897360 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4914 22:50:12.900326 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4915 22:50:12.903933 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 22:50:12.910565 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4917 22:50:12.913868 0 11 20 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
4918 22:50:12.917304 0 11 24 | B1->B0 | 3838 3d3d | 0 0 | (0 0) (0 0)
4919 22:50:12.923754 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4920 22:50:12.926854 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4921 22:50:12.930117 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4922 22:50:12.937095 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4923 22:50:12.940610 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4924 22:50:12.943568 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 22:50:12.949892 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 22:50:12.953325 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4927 22:50:12.956940 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4928 22:50:12.963323 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 22:50:12.966654 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 22:50:12.970066 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 22:50:12.976637 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 22:50:12.980011 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 22:50:12.983191 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 22:50:12.990129 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 22:50:12.993304 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 22:50:12.996875 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 22:50:13.000356 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 22:50:13.007065 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 22:50:13.010178 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 22:50:13.013686 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 22:50:13.020444 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4942 22:50:13.023306 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4943 22:50:13.026646 Total UI for P1: 0, mck2ui 16
4944 22:50:13.029782 best dqsien dly found for B0: ( 0, 14, 20)
4945 22:50:13.033254 Total UI for P1: 0, mck2ui 16
4946 22:50:13.037021 best dqsien dly found for B1: ( 0, 14, 20)
4947 22:50:13.040337 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4948 22:50:13.043019 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4949 22:50:13.043439
4950 22:50:13.046836 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4951 22:50:13.049906 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4952 22:50:13.053513 [Gating] SW calibration Done
4953 22:50:13.054074 ==
4954 22:50:13.056651 Dram Type= 6, Freq= 0, CH_0, rank 0
4955 22:50:13.063100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4956 22:50:13.063646 ==
4957 22:50:13.064006 RX Vref Scan: 0
4958 22:50:13.064320
4959 22:50:13.066489 RX Vref 0 -> 0, step: 1
4960 22:50:13.066909
4961 22:50:13.069851 RX Delay -80 -> 252, step: 8
4962 22:50:13.073085 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4963 22:50:13.076738 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4964 22:50:13.079654 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4965 22:50:13.082825 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4966 22:50:13.086207 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4967 22:50:13.092967 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4968 22:50:13.095928 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4969 22:50:13.099933 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4970 22:50:13.102609 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4971 22:50:13.105935 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
4972 22:50:13.113053 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4973 22:50:13.115991 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4974 22:50:13.119312 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4975 22:50:13.122729 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4976 22:50:13.126021 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4977 22:50:13.132405 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4978 22:50:13.132930 ==
4979 22:50:13.135547 Dram Type= 6, Freq= 0, CH_0, rank 0
4980 22:50:13.138664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4981 22:50:13.139088 ==
4982 22:50:13.139414 DQS Delay:
4983 22:50:13.142697 DQS0 = 0, DQS1 = 0
4984 22:50:13.143220 DQM Delay:
4985 22:50:13.145490 DQM0 = 96, DQM1 = 87
4986 22:50:13.145905 DQ Delay:
4987 22:50:13.149268 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =91
4988 22:50:13.152607 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
4989 22:50:13.155516 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
4990 22:50:13.158808 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
4991 22:50:13.159333
4992 22:50:13.159668
4993 22:50:13.160186 ==
4994 22:50:13.162161 Dram Type= 6, Freq= 0, CH_0, rank 0
4995 22:50:13.165450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4996 22:50:13.168456 ==
4997 22:50:13.168878
4998 22:50:13.169203
4999 22:50:13.169507 TX Vref Scan disable
5000 22:50:13.172334 == TX Byte 0 ==
5001 22:50:13.175375 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5002 22:50:13.178614 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5003 22:50:13.181982 == TX Byte 1 ==
5004 22:50:13.185291 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5005 22:50:13.188576 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5006 22:50:13.191912 ==
5007 22:50:13.195251 Dram Type= 6, Freq= 0, CH_0, rank 0
5008 22:50:13.198661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5009 22:50:13.199185 ==
5010 22:50:13.199512
5011 22:50:13.199813
5012 22:50:13.201891 TX Vref Scan disable
5013 22:50:13.202374 == TX Byte 0 ==
5014 22:50:13.208676 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5015 22:50:13.211944 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5016 22:50:13.212466 == TX Byte 1 ==
5017 22:50:13.218323 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5018 22:50:13.221904 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5019 22:50:13.222472
5020 22:50:13.222801 [DATLAT]
5021 22:50:13.224740 Freq=933, CH0 RK0
5022 22:50:13.225151
5023 22:50:13.225479 DATLAT Default: 0xd
5024 22:50:13.228406 0, 0xFFFF, sum = 0
5025 22:50:13.228943 1, 0xFFFF, sum = 0
5026 22:50:13.231516 2, 0xFFFF, sum = 0
5027 22:50:13.232040 3, 0xFFFF, sum = 0
5028 22:50:13.234693 4, 0xFFFF, sum = 0
5029 22:50:13.235114 5, 0xFFFF, sum = 0
5030 22:50:13.237926 6, 0xFFFF, sum = 0
5031 22:50:13.241392 7, 0xFFFF, sum = 0
5032 22:50:13.241917 8, 0xFFFF, sum = 0
5033 22:50:13.245182 9, 0xFFFF, sum = 0
5034 22:50:13.245756 10, 0x0, sum = 1
5035 22:50:13.246154 11, 0x0, sum = 2
5036 22:50:13.247906 12, 0x0, sum = 3
5037 22:50:13.248325 13, 0x0, sum = 4
5038 22:50:13.251529 best_step = 11
5039 22:50:13.252046
5040 22:50:13.252370 ==
5041 22:50:13.254944 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 22:50:13.257915 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5043 22:50:13.258376 ==
5044 22:50:13.261663 RX Vref Scan: 1
5045 22:50:13.262231
5046 22:50:13.262570 RX Vref 0 -> 0, step: 1
5047 22:50:13.262877
5048 22:50:13.264583 RX Delay -61 -> 252, step: 4
5049 22:50:13.264998
5050 22:50:13.267653 Set Vref, RX VrefLevel [Byte0]: 47
5051 22:50:13.271493 [Byte1]: 49
5052 22:50:13.275767
5053 22:50:13.276279 Final RX Vref Byte 0 = 47 to rank0
5054 22:50:13.279034 Final RX Vref Byte 1 = 49 to rank0
5055 22:50:13.282466 Final RX Vref Byte 0 = 47 to rank1
5056 22:50:13.285991 Final RX Vref Byte 1 = 49 to rank1==
5057 22:50:13.289089 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 22:50:13.295429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5059 22:50:13.295950 ==
5060 22:50:13.296326 DQS Delay:
5061 22:50:13.298953 DQS0 = 0, DQS1 = 0
5062 22:50:13.299472 DQM Delay:
5063 22:50:13.299807 DQM0 = 97, DQM1 = 87
5064 22:50:13.302216 DQ Delay:
5065 22:50:13.305284 DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =94
5066 22:50:13.309124 DQ4 =100, DQ5 =88, DQ6 =102, DQ7 =104
5067 22:50:13.312156 DQ8 =78, DQ9 =70, DQ10 =88, DQ11 =78
5068 22:50:13.315444 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =98
5069 22:50:13.315957
5070 22:50:13.316347
5071 22:50:13.321906 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5072 22:50:13.325390 CH0 RK0: MR19=505, MR18=2323
5073 22:50:13.332167 CH0_RK0: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5074 22:50:13.332847
5075 22:50:13.335187 ----->DramcWriteLeveling(PI) begin...
5076 22:50:13.335610 ==
5077 22:50:13.338516 Dram Type= 6, Freq= 0, CH_0, rank 1
5078 22:50:13.341968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5079 22:50:13.342526 ==
5080 22:50:13.345519 Write leveling (Byte 0): 26 => 26
5081 22:50:13.349243 Write leveling (Byte 1): 25 => 25
5082 22:50:13.352054 DramcWriteLeveling(PI) end<-----
5083 22:50:13.352616
5084 22:50:13.352950 ==
5085 22:50:13.355410 Dram Type= 6, Freq= 0, CH_0, rank 1
5086 22:50:13.358677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5087 22:50:13.359200 ==
5088 22:50:13.362174 [Gating] SW mode calibration
5089 22:50:13.368702 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5090 22:50:13.375611 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5091 22:50:13.378276 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 22:50:13.385169 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 22:50:13.388889 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 22:50:13.391948 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 22:50:13.398467 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5096 22:50:13.401781 0 10 20 | B1->B0 | 3232 3030 | 1 0 | (1 0) (0 0)
5097 22:50:13.405269 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5098 22:50:13.411879 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 22:50:13.415092 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 22:50:13.418226 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 22:50:13.425136 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 22:50:13.428197 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 22:50:13.431304 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 22:50:13.437793 0 11 20 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (0 0)
5105 22:50:13.441716 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5106 22:50:13.444843 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 22:50:13.451622 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 22:50:13.454818 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 22:50:13.458323 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 22:50:13.461410 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 22:50:13.467804 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 22:50:13.471831 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5113 22:50:13.474511 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 22:50:13.481343 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 22:50:13.485301 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 22:50:13.487757 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 22:50:13.494981 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 22:50:13.498156 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 22:50:13.501741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 22:50:13.508060 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 22:50:13.511378 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 22:50:13.514705 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 22:50:13.521573 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 22:50:13.524901 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 22:50:13.527606 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 22:50:13.534394 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 22:50:13.537809 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 22:50:13.540914 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5129 22:50:13.547636 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5130 22:50:13.548154 Total UI for P1: 0, mck2ui 16
5131 22:50:13.554081 best dqsien dly found for B1: ( 0, 14, 20)
5132 22:50:13.557591 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 22:50:13.560739 Total UI for P1: 0, mck2ui 16
5134 22:50:13.563845 best dqsien dly found for B0: ( 0, 14, 22)
5135 22:50:13.567292 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5136 22:50:13.570963 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5137 22:50:13.571390
5138 22:50:13.573898 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5139 22:50:13.577236 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5140 22:50:13.581322 [Gating] SW calibration Done
5141 22:50:13.581843 ==
5142 22:50:13.584278 Dram Type= 6, Freq= 0, CH_0, rank 1
5143 22:50:13.590492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5144 22:50:13.591018 ==
5145 22:50:13.591348 RX Vref Scan: 0
5146 22:50:13.591658
5147 22:50:13.593568 RX Vref 0 -> 0, step: 1
5148 22:50:13.593983
5149 22:50:13.597184 RX Delay -80 -> 252, step: 8
5150 22:50:13.600471 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5151 22:50:13.603886 iDelay=200, Bit 1, Center 95 (-8 ~ 199) 208
5152 22:50:13.607346 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5153 22:50:13.610694 iDelay=200, Bit 3, Center 87 (-8 ~ 183) 192
5154 22:50:13.617179 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5155 22:50:13.620287 iDelay=200, Bit 5, Center 91 (-8 ~ 191) 200
5156 22:50:13.623592 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5157 22:50:13.627012 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5158 22:50:13.630415 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5159 22:50:13.636679 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5160 22:50:13.639745 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5161 22:50:13.643444 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5162 22:50:13.646608 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5163 22:50:13.649900 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5164 22:50:13.656409 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5165 22:50:13.659855 iDelay=200, Bit 15, Center 91 (-8 ~ 191) 200
5166 22:50:13.660378 ==
5167 22:50:13.662964 Dram Type= 6, Freq= 0, CH_0, rank 1
5168 22:50:13.666297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5169 22:50:13.666820 ==
5170 22:50:13.667148 DQS Delay:
5171 22:50:13.669520 DQS0 = 0, DQS1 = 0
5172 22:50:13.670190 DQM Delay:
5173 22:50:13.672855 DQM0 = 96, DQM1 = 85
5174 22:50:13.673374 DQ Delay:
5175 22:50:13.676594 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =87
5176 22:50:13.679519 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =107
5177 22:50:13.682685 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5178 22:50:13.686323 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5179 22:50:13.686853
5180 22:50:13.687180
5181 22:50:13.687482 ==
5182 22:50:13.689365 Dram Type= 6, Freq= 0, CH_0, rank 1
5183 22:50:13.696143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5184 22:50:13.696663 ==
5185 22:50:13.696995
5186 22:50:13.697304
5187 22:50:13.697596 TX Vref Scan disable
5188 22:50:13.700046 == TX Byte 0 ==
5189 22:50:13.702532 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5190 22:50:13.709341 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5191 22:50:13.709861 == TX Byte 1 ==
5192 22:50:13.712378 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5193 22:50:13.719297 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5194 22:50:13.719813 ==
5195 22:50:13.722651 Dram Type= 6, Freq= 0, CH_0, rank 1
5196 22:50:13.725674 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5197 22:50:13.726132 ==
5198 22:50:13.726464
5199 22:50:13.726769
5200 22:50:13.729204 TX Vref Scan disable
5201 22:50:13.729718 == TX Byte 0 ==
5202 22:50:13.735885 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5203 22:50:13.738948 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5204 22:50:13.739406 == TX Byte 1 ==
5205 22:50:13.745499 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5206 22:50:13.749056 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5207 22:50:13.749576
5208 22:50:13.749903 [DATLAT]
5209 22:50:13.752526 Freq=933, CH0 RK1
5210 22:50:13.752939
5211 22:50:13.753261 DATLAT Default: 0xb
5212 22:50:13.756017 0, 0xFFFF, sum = 0
5213 22:50:13.756543 1, 0xFFFF, sum = 0
5214 22:50:13.759242 2, 0xFFFF, sum = 0
5215 22:50:13.761975 3, 0xFFFF, sum = 0
5216 22:50:13.762448 4, 0xFFFF, sum = 0
5217 22:50:13.765411 5, 0xFFFF, sum = 0
5218 22:50:13.765832 6, 0xFFFF, sum = 0
5219 22:50:13.768898 7, 0xFFFF, sum = 0
5220 22:50:13.769392 8, 0xFFFF, sum = 0
5221 22:50:13.772209 9, 0xFFFF, sum = 0
5222 22:50:13.772727 10, 0x0, sum = 1
5223 22:50:13.775438 11, 0x0, sum = 2
5224 22:50:13.775958 12, 0x0, sum = 3
5225 22:50:13.776291 13, 0x0, sum = 4
5226 22:50:13.778667 best_step = 11
5227 22:50:13.779077
5228 22:50:13.779400 ==
5229 22:50:13.781886 Dram Type= 6, Freq= 0, CH_0, rank 1
5230 22:50:13.785514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5231 22:50:13.786092 ==
5232 22:50:13.788735 RX Vref Scan: 0
5233 22:50:13.789269
5234 22:50:13.789607 RX Vref 0 -> 0, step: 1
5235 22:50:13.792364
5236 22:50:13.792882 RX Delay -69 -> 252, step: 4
5237 22:50:13.799787 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5238 22:50:13.802603 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5239 22:50:13.806532 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5240 22:50:13.809653 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5241 22:50:13.813198 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5242 22:50:13.819581 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5243 22:50:13.823270 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5244 22:50:13.826120 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5245 22:50:13.829486 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5246 22:50:13.833181 iDelay=199, Bit 9, Center 74 (-13 ~ 162) 176
5247 22:50:13.836357 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5248 22:50:13.842959 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5249 22:50:13.845935 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5250 22:50:13.849404 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5251 22:50:13.852727 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5252 22:50:13.856160 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5253 22:50:13.859201 ==
5254 22:50:13.859717 Dram Type= 6, Freq= 0, CH_0, rank 1
5255 22:50:13.865973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5256 22:50:13.866535 ==
5257 22:50:13.866863 DQS Delay:
5258 22:50:13.869246 DQS0 = 0, DQS1 = 0
5259 22:50:13.869709 DQM Delay:
5260 22:50:13.872157 DQM0 = 97, DQM1 = 86
5261 22:50:13.872567 DQ Delay:
5262 22:50:13.875644 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =92
5263 22:50:13.878879 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =106
5264 22:50:13.882598 DQ8 =76, DQ9 =74, DQ10 =88, DQ11 =78
5265 22:50:13.886257 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5266 22:50:13.886668
5267 22:50:13.886988
5268 22:50:13.892366 [DQSOSCAuto] RK1, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5269 22:50:13.895742 CH0 RK1: MR19=505, MR18=3131
5270 22:50:13.902364 CH0_RK1: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5271 22:50:13.905751 [RxdqsGatingPostProcess] freq 933
5272 22:50:13.916051 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5273 22:50:13.916470 Pre-setting of DQS Precalculation
5274 22:50:13.918388 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5275 22:50:13.918799 ==
5276 22:50:13.921683 Dram Type= 6, Freq= 0, CH_1, rank 0
5277 22:50:13.925049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5278 22:50:13.925466 ==
5279 22:50:13.931725 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5280 22:50:13.939901 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5281 22:50:13.941655 [CA 0] Center 37 (7~68) winsize 62
5282 22:50:13.945030 [CA 1] Center 37 (7~68) winsize 62
5283 22:50:13.948948 [CA 2] Center 35 (5~65) winsize 61
5284 22:50:13.951655 [CA 3] Center 34 (4~65) winsize 62
5285 22:50:13.954895 [CA 4] Center 33 (3~64) winsize 62
5286 22:50:13.958526 [CA 5] Center 33 (3~64) winsize 62
5287 22:50:13.958960
5288 22:50:13.961499 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5289 22:50:13.961952
5290 22:50:13.964777 [CATrainingPosCal] consider 1 rank data
5291 22:50:13.968282 u2DelayCellTimex100 = 270/100 ps
5292 22:50:13.971974 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5293 22:50:13.975162 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5294 22:50:13.978529 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5295 22:50:13.981460 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5296 22:50:13.987930 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5297 22:50:13.991072 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5298 22:50:13.991807
5299 22:50:13.994562 CA PerBit enable=1, Macro0, CA PI delay=33
5300 22:50:13.995204
5301 22:50:13.997847 [CBTSetCACLKResult] CA Dly = 33
5302 22:50:13.998324 CS Dly: 5 (0~36)
5303 22:50:13.998641 ==
5304 22:50:14.001282 Dram Type= 6, Freq= 0, CH_1, rank 1
5305 22:50:14.007855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5306 22:50:14.008278 ==
5307 22:50:14.011178 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5308 22:50:14.017780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5309 22:50:14.021004 [CA 0] Center 37 (7~68) winsize 62
5310 22:50:14.024642 [CA 1] Center 37 (7~68) winsize 62
5311 22:50:14.027358 [CA 2] Center 35 (5~65) winsize 61
5312 22:50:14.030601 [CA 3] Center 34 (4~65) winsize 62
5313 22:50:14.033826 [CA 4] Center 33 (3~64) winsize 62
5314 22:50:14.037376 [CA 5] Center 33 (2~64) winsize 63
5315 22:50:14.037611
5316 22:50:14.040718 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5317 22:50:14.040940
5318 22:50:14.044159 [CATrainingPosCal] consider 2 rank data
5319 22:50:14.047228 u2DelayCellTimex100 = 270/100 ps
5320 22:50:14.050382 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5321 22:50:14.053911 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5322 22:50:14.060502 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5323 22:50:14.064170 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5324 22:50:14.067015 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5325 22:50:14.070216 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5326 22:50:14.070505
5327 22:50:14.073870 CA PerBit enable=1, Macro0, CA PI delay=33
5328 22:50:14.074152
5329 22:50:14.077067 [CBTSetCACLKResult] CA Dly = 33
5330 22:50:14.077215 CS Dly: 5 (0~37)
5331 22:50:14.077331
5332 22:50:14.083464 ----->DramcWriteLeveling(PI) begin...
5333 22:50:14.083618 ==
5334 22:50:14.086735 Dram Type= 6, Freq= 0, CH_1, rank 0
5335 22:50:14.090053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5336 22:50:14.090173 ==
5337 22:50:14.093624 Write leveling (Byte 0): 23 => 23
5338 22:50:14.097315 Write leveling (Byte 1): 24 => 24
5339 22:50:14.100541 DramcWriteLeveling(PI) end<-----
5340 22:50:14.101049
5341 22:50:14.101522 ==
5342 22:50:14.103635 Dram Type= 6, Freq= 0, CH_1, rank 0
5343 22:50:14.106998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5344 22:50:14.107683 ==
5345 22:50:14.110286 [Gating] SW mode calibration
5346 22:50:14.116992 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5347 22:50:14.123666 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5348 22:50:14.126661 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 22:50:14.129953 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 22:50:14.136558 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 22:50:14.139845 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5352 22:50:14.143220 0 10 16 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
5353 22:50:14.149574 0 10 20 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
5354 22:50:14.153243 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 22:50:14.156698 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 22:50:14.162884 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 22:50:14.166138 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 22:50:14.169548 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 22:50:14.176222 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 22:50:14.179133 0 11 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5361 22:50:14.182523 0 11 20 | B1->B0 | 2f2f 4343 | 0 0 | (0 0) (0 0)
5362 22:50:14.189198 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5363 22:50:14.192516 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 22:50:14.195943 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 22:50:14.202564 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 22:50:14.205693 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 22:50:14.209086 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 22:50:14.215755 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5369 22:50:14.218894 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5370 22:50:14.222272 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 22:50:14.228882 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 22:50:14.232298 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 22:50:14.235572 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 22:50:14.238781 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 22:50:14.245336 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 22:50:14.248885 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 22:50:14.252305 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 22:50:14.258729 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 22:50:14.262019 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 22:50:14.265432 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 22:50:14.271883 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 22:50:14.275523 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 22:50:14.278732 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 22:50:14.285273 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5385 22:50:14.288276 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 22:50:14.291841 Total UI for P1: 0, mck2ui 16
5387 22:50:14.294939 best dqsien dly found for B0: ( 0, 14, 16)
5388 22:50:14.298242 Total UI for P1: 0, mck2ui 16
5389 22:50:14.301516 best dqsien dly found for B1: ( 0, 14, 18)
5390 22:50:14.305018 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5391 22:50:14.308411 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5392 22:50:14.308492
5393 22:50:14.311675 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5394 22:50:14.318509 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5395 22:50:14.318591 [Gating] SW calibration Done
5396 22:50:14.318655 ==
5397 22:50:14.321488 Dram Type= 6, Freq= 0, CH_1, rank 0
5398 22:50:14.328292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5399 22:50:14.328373 ==
5400 22:50:14.328436 RX Vref Scan: 0
5401 22:50:14.328495
5402 22:50:14.331652 RX Vref 0 -> 0, step: 1
5403 22:50:14.331731
5404 22:50:14.334932 RX Delay -80 -> 252, step: 8
5405 22:50:14.338114 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5406 22:50:14.341512 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5407 22:50:14.344539 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5408 22:50:14.351816 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5409 22:50:14.355134 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5410 22:50:14.358302 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5411 22:50:14.361569 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5412 22:50:14.364814 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5413 22:50:14.368065 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5414 22:50:14.374754 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5415 22:50:14.377737 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5416 22:50:14.381160 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5417 22:50:14.384308 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5418 22:50:14.387625 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5419 22:50:14.394737 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5420 22:50:14.397758 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5421 22:50:14.397906 ==
5422 22:50:14.400920 Dram Type= 6, Freq= 0, CH_1, rank 0
5423 22:50:14.404221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5424 22:50:14.404350 ==
5425 22:50:14.407414 DQS Delay:
5426 22:50:14.407540 DQS0 = 0, DQS1 = 0
5427 22:50:14.407641 DQM Delay:
5428 22:50:14.411018 DQM0 = 98, DQM1 = 91
5429 22:50:14.411224 DQ Delay:
5430 22:50:14.414145 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =91
5431 22:50:14.417601 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5432 22:50:14.420631 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5433 22:50:14.423860 DQ12 =99, DQ13 =107, DQ14 =99, DQ15 =103
5434 22:50:14.424074
5435 22:50:14.424226
5436 22:50:14.424395 ==
5437 22:50:14.427317 Dram Type= 6, Freq= 0, CH_1, rank 0
5438 22:50:14.434073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5439 22:50:14.434202 ==
5440 22:50:14.434303
5441 22:50:14.434396
5442 22:50:14.434486 TX Vref Scan disable
5443 22:50:14.438135 == TX Byte 0 ==
5444 22:50:14.441122 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5445 22:50:14.447616 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5446 22:50:14.447745 == TX Byte 1 ==
5447 22:50:14.451025 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5448 22:50:14.457612 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5449 22:50:14.457782 ==
5450 22:50:14.460894 Dram Type= 6, Freq= 0, CH_1, rank 0
5451 22:50:14.464440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5452 22:50:14.464567 ==
5453 22:50:14.464668
5454 22:50:14.464762
5455 22:50:14.467574 TX Vref Scan disable
5456 22:50:14.467702 == TX Byte 0 ==
5457 22:50:14.474428 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5458 22:50:14.477419 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5459 22:50:14.477508 == TX Byte 1 ==
5460 22:50:14.484043 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5461 22:50:14.487332 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5462 22:50:14.487425
5463 22:50:14.487497 [DATLAT]
5464 22:50:14.490668 Freq=933, CH1 RK0
5465 22:50:14.490761
5466 22:50:14.490834 DATLAT Default: 0xd
5467 22:50:14.493953 0, 0xFFFF, sum = 0
5468 22:50:14.494082 1, 0xFFFF, sum = 0
5469 22:50:14.497413 2, 0xFFFF, sum = 0
5470 22:50:14.500522 3, 0xFFFF, sum = 0
5471 22:50:14.500625 4, 0xFFFF, sum = 0
5472 22:50:14.504147 5, 0xFFFF, sum = 0
5473 22:50:14.504241 6, 0xFFFF, sum = 0
5474 22:50:14.507482 7, 0xFFFF, sum = 0
5475 22:50:14.507576 8, 0xFFFF, sum = 0
5476 22:50:14.510627 9, 0xFFFF, sum = 0
5477 22:50:14.510721 10, 0x0, sum = 1
5478 22:50:14.513869 11, 0x0, sum = 2
5479 22:50:14.513963 12, 0x0, sum = 3
5480 22:50:14.514046 13, 0x0, sum = 4
5481 22:50:14.517209 best_step = 11
5482 22:50:14.517301
5483 22:50:14.517372 ==
5484 22:50:14.520923 Dram Type= 6, Freq= 0, CH_1, rank 0
5485 22:50:14.524257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5486 22:50:14.524429 ==
5487 22:50:14.527343 RX Vref Scan: 1
5488 22:50:14.527515
5489 22:50:14.527596 RX Vref 0 -> 0, step: 1
5490 22:50:14.530771
5491 22:50:14.530940 RX Delay -61 -> 252, step: 4
5492 22:50:14.531017
5493 22:50:14.533920 Set Vref, RX VrefLevel [Byte0]: 56
5494 22:50:14.537220 [Byte1]: 49
5495 22:50:14.541639
5496 22:50:14.541809 Final RX Vref Byte 0 = 56 to rank0
5497 22:50:14.545139 Final RX Vref Byte 1 = 49 to rank0
5498 22:50:14.548298 Final RX Vref Byte 0 = 56 to rank1
5499 22:50:14.551578 Final RX Vref Byte 1 = 49 to rank1==
5500 22:50:14.555129 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 22:50:14.561904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5502 22:50:14.562092 ==
5503 22:50:14.562231 DQS Delay:
5504 22:50:14.562375 DQS0 = 0, DQS1 = 0
5505 22:50:14.565321 DQM Delay:
5506 22:50:14.565428 DQM0 = 96, DQM1 = 89
5507 22:50:14.568470 DQ Delay:
5508 22:50:14.571686 DQ0 =98, DQ1 =92, DQ2 =88, DQ3 =94
5509 22:50:14.575090 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =94
5510 22:50:14.578427 DQ8 =74, DQ9 =78, DQ10 =90, DQ11 =82
5511 22:50:14.581705 DQ12 =96, DQ13 =100, DQ14 =98, DQ15 =100
5512 22:50:14.581935
5513 22:50:14.582079
5514 22:50:14.588358 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5515 22:50:14.591813 CH1 RK0: MR19=505, MR18=3838
5516 22:50:14.598498 CH1_RK0: MR19=0x505, MR18=0x3838, DQSOSC=404, MR23=63, INC=66, DEC=44
5517 22:50:14.598779
5518 22:50:14.601421 ----->DramcWriteLeveling(PI) begin...
5519 22:50:14.601719 ==
5520 22:50:14.605205 Dram Type= 6, Freq= 0, CH_1, rank 1
5521 22:50:14.608418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5522 22:50:14.608898 ==
5523 22:50:14.612293 Write leveling (Byte 0): 25 => 25
5524 22:50:14.615063 Write leveling (Byte 1): 25 => 25
5525 22:50:14.618325 DramcWriteLeveling(PI) end<-----
5526 22:50:14.618734
5527 22:50:14.619057 ==
5528 22:50:14.621985 Dram Type= 6, Freq= 0, CH_1, rank 1
5529 22:50:14.625205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5530 22:50:14.628438 ==
5531 22:50:14.628947 [Gating] SW mode calibration
5532 22:50:14.634712 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5533 22:50:14.641457 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5534 22:50:14.644910 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5535 22:50:14.651623 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5536 22:50:14.655013 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5537 22:50:14.658195 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5538 22:50:14.664993 0 10 16 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
5539 22:50:14.668074 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5540 22:50:14.671308 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5541 22:50:14.677752 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5542 22:50:14.681554 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5543 22:50:14.684653 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5544 22:50:14.691500 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5545 22:50:14.694369 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5546 22:50:14.697658 0 11 16 | B1->B0 | 2525 4040 | 0 0 | (0 0) (1 1)
5547 22:50:14.704245 0 11 20 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
5548 22:50:14.707832 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5549 22:50:14.711302 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5550 22:50:14.717727 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5551 22:50:14.720928 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5552 22:50:14.724564 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 22:50:14.731157 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 22:50:14.734285 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5555 22:50:14.737675 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5556 22:50:14.741184 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 22:50:14.747868 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 22:50:14.751234 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 22:50:14.754152 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 22:50:14.761083 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 22:50:14.764794 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 22:50:14.767397 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 22:50:14.774098 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 22:50:14.777603 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 22:50:14.780748 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 22:50:14.787795 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 22:50:14.790609 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 22:50:14.794181 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 22:50:14.801017 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 22:50:14.804301 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5571 22:50:14.807322 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5572 22:50:14.810557 Total UI for P1: 0, mck2ui 16
5573 22:50:14.813942 best dqsien dly found for B0: ( 0, 14, 16)
5574 22:50:14.820383 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 22:50:14.823986 Total UI for P1: 0, mck2ui 16
5576 22:50:14.827110 best dqsien dly found for B1: ( 0, 14, 18)
5577 22:50:14.830487 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5578 22:50:14.834077 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5579 22:50:14.834644
5580 22:50:14.837159 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5581 22:50:14.840219 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5582 22:50:14.843703 [Gating] SW calibration Done
5583 22:50:14.844253 ==
5584 22:50:14.846807 Dram Type= 6, Freq= 0, CH_1, rank 1
5585 22:50:14.850101 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5586 22:50:14.850567 ==
5587 22:50:14.853194 RX Vref Scan: 0
5588 22:50:14.853647
5589 22:50:14.856729 RX Vref 0 -> 0, step: 1
5590 22:50:14.857244
5591 22:50:14.857603 RX Delay -80 -> 252, step: 8
5592 22:50:14.863228 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5593 22:50:14.867048 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5594 22:50:14.870410 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5595 22:50:14.873218 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5596 22:50:14.876738 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5597 22:50:14.880141 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5598 22:50:14.886784 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5599 22:50:14.889919 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5600 22:50:14.893633 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5601 22:50:14.896541 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5602 22:50:14.899957 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5603 22:50:14.906530 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5604 22:50:14.909809 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5605 22:50:14.913061 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5606 22:50:14.916478 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5607 22:50:14.919965 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5608 22:50:14.920607 ==
5609 22:50:14.923147 Dram Type= 6, Freq= 0, CH_1, rank 1
5610 22:50:14.929877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5611 22:50:14.930478 ==
5612 22:50:14.930845 DQS Delay:
5613 22:50:14.931183 DQS0 = 0, DQS1 = 0
5614 22:50:14.933541 DQM Delay:
5615 22:50:14.934129 DQM0 = 97, DQM1 = 88
5616 22:50:14.936559 DQ Delay:
5617 22:50:14.939365 DQ0 =95, DQ1 =95, DQ2 =87, DQ3 =95
5618 22:50:14.943004 DQ4 =95, DQ5 =111, DQ6 =103, DQ7 =95
5619 22:50:14.946142 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5620 22:50:14.949622 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5621 22:50:14.950229
5622 22:50:14.950593
5623 22:50:14.950928 ==
5624 22:50:14.952450 Dram Type= 6, Freq= 0, CH_1, rank 1
5625 22:50:14.956055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5626 22:50:14.956612 ==
5627 22:50:14.956977
5628 22:50:14.957315
5629 22:50:14.959420 TX Vref Scan disable
5630 22:50:14.962478 == TX Byte 0 ==
5631 22:50:14.965682 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5632 22:50:14.969242 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5633 22:50:14.972533 == TX Byte 1 ==
5634 22:50:14.975414 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5635 22:50:14.978842 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5636 22:50:14.979305 ==
5637 22:50:14.982159 Dram Type= 6, Freq= 0, CH_1, rank 1
5638 22:50:14.985577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5639 22:50:14.986077 ==
5640 22:50:14.988963
5641 22:50:14.989511
5642 22:50:14.989872 TX Vref Scan disable
5643 22:50:14.992208 == TX Byte 0 ==
5644 22:50:14.995516 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5645 22:50:14.998984 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5646 22:50:15.002705 == TX Byte 1 ==
5647 22:50:15.005687 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5648 22:50:15.012577 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5649 22:50:15.013108
5650 22:50:15.013441 [DATLAT]
5651 22:50:15.013745 Freq=933, CH1 RK1
5652 22:50:15.014063
5653 22:50:15.015795 DATLAT Default: 0xb
5654 22:50:15.016303 0, 0xFFFF, sum = 0
5655 22:50:15.018688 1, 0xFFFF, sum = 0
5656 22:50:15.019110 2, 0xFFFF, sum = 0
5657 22:50:15.022501 3, 0xFFFF, sum = 0
5658 22:50:15.025792 4, 0xFFFF, sum = 0
5659 22:50:15.026352 5, 0xFFFF, sum = 0
5660 22:50:15.028915 6, 0xFFFF, sum = 0
5661 22:50:15.029335 7, 0xFFFF, sum = 0
5662 22:50:15.032286 8, 0xFFFF, sum = 0
5663 22:50:15.032805 9, 0xFFFF, sum = 0
5664 22:50:15.035500 10, 0x0, sum = 1
5665 22:50:15.035918 11, 0x0, sum = 2
5666 22:50:15.038748 12, 0x0, sum = 3
5667 22:50:15.039268 13, 0x0, sum = 4
5668 22:50:15.039607 best_step = 11
5669 22:50:15.039912
5670 22:50:15.042080 ==
5671 22:50:15.046104 Dram Type= 6, Freq= 0, CH_1, rank 1
5672 22:50:15.048535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5673 22:50:15.049045 ==
5674 22:50:15.049377 RX Vref Scan: 0
5675 22:50:15.049685
5676 22:50:15.051623 RX Vref 0 -> 0, step: 1
5677 22:50:15.052036
5678 22:50:15.055180 RX Delay -69 -> 252, step: 4
5679 22:50:15.062017 iDelay=203, Bit 0, Center 100 (11 ~ 190) 180
5680 22:50:15.065163 iDelay=203, Bit 1, Center 94 (3 ~ 186) 184
5681 22:50:15.068620 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5682 22:50:15.071754 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5683 22:50:15.074845 iDelay=203, Bit 4, Center 98 (7 ~ 190) 184
5684 22:50:15.078518 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5685 22:50:15.084883 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5686 22:50:15.088799 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5687 22:50:15.091912 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5688 22:50:15.094773 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180
5689 22:50:15.098604 iDelay=203, Bit 10, Center 88 (-1 ~ 178) 180
5690 22:50:15.105075 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5691 22:50:15.108554 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5692 22:50:15.111396 iDelay=203, Bit 13, Center 100 (15 ~ 186) 172
5693 22:50:15.114797 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5694 22:50:15.117895 iDelay=203, Bit 15, Center 98 (11 ~ 186) 176
5695 22:50:15.118392 ==
5696 22:50:15.121504 Dram Type= 6, Freq= 0, CH_1, rank 1
5697 22:50:15.127697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5698 22:50:15.128243 ==
5699 22:50:15.128609 DQS Delay:
5700 22:50:15.131516 DQS0 = 0, DQS1 = 0
5701 22:50:15.132070 DQM Delay:
5702 22:50:15.132431 DQM0 = 98, DQM1 = 89
5703 22:50:15.134409 DQ Delay:
5704 22:50:15.137690 DQ0 =100, DQ1 =94, DQ2 =90, DQ3 =94
5705 22:50:15.141227 DQ4 =98, DQ5 =108, DQ6 =106, DQ7 =96
5706 22:50:15.144440 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =82
5707 22:50:15.147947 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =98
5708 22:50:15.148519
5709 22:50:15.148883
5710 22:50:15.154591 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5711 22:50:15.158006 CH1 RK1: MR19=505, MR18=2222
5712 22:50:15.164275 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5713 22:50:15.167619 [RxdqsGatingPostProcess] freq 933
5714 22:50:15.171120 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5715 22:50:15.174267 Pre-setting of DQS Precalculation
5716 22:50:15.181083 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5717 22:50:15.188118 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5718 22:50:15.194384 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5719 22:50:15.194989
5720 22:50:15.195355
5721 22:50:15.197592 [Calibration Summary] 1866 Mbps
5722 22:50:15.201804 CH 0, Rank 0
5723 22:50:15.202410 SW Impedance : PASS
5724 22:50:15.203927 DUTY Scan : NO K
5725 22:50:15.207442 ZQ Calibration : PASS
5726 22:50:15.207902 Jitter Meter : NO K
5727 22:50:15.210552 CBT Training : PASS
5728 22:50:15.211010 Write leveling : PASS
5729 22:50:15.214097 RX DQS gating : PASS
5730 22:50:15.217138 RX DQ/DQS(RDDQC) : PASS
5731 22:50:15.217546 TX DQ/DQS : PASS
5732 22:50:15.220569 RX DATLAT : PASS
5733 22:50:15.224181 RX DQ/DQS(Engine): PASS
5734 22:50:15.224698 TX OE : NO K
5735 22:50:15.227139 All Pass.
5736 22:50:15.227554
5737 22:50:15.227877 CH 0, Rank 1
5738 22:50:15.231074 SW Impedance : PASS
5739 22:50:15.231597 DUTY Scan : NO K
5740 22:50:15.233662 ZQ Calibration : PASS
5741 22:50:15.236914 Jitter Meter : NO K
5742 22:50:15.237328 CBT Training : PASS
5743 22:50:15.240263 Write leveling : PASS
5744 22:50:15.244085 RX DQS gating : PASS
5745 22:50:15.244618 RX DQ/DQS(RDDQC) : PASS
5746 22:50:15.246703 TX DQ/DQS : PASS
5747 22:50:15.250250 RX DATLAT : PASS
5748 22:50:15.250666 RX DQ/DQS(Engine): PASS
5749 22:50:15.253351 TX OE : NO K
5750 22:50:15.253823 All Pass.
5751 22:50:15.254196
5752 22:50:15.256506 CH 1, Rank 0
5753 22:50:15.256917 SW Impedance : PASS
5754 22:50:15.259985 DUTY Scan : NO K
5755 22:50:15.263211 ZQ Calibration : PASS
5756 22:50:15.263630 Jitter Meter : NO K
5757 22:50:15.266576 CBT Training : PASS
5758 22:50:15.269653 Write leveling : PASS
5759 22:50:15.270088 RX DQS gating : PASS
5760 22:50:15.273236 RX DQ/DQS(RDDQC) : PASS
5761 22:50:15.276205 TX DQ/DQS : PASS
5762 22:50:15.276684 RX DATLAT : PASS
5763 22:50:15.279828 RX DQ/DQS(Engine): PASS
5764 22:50:15.280243 TX OE : NO K
5765 22:50:15.282820 All Pass.
5766 22:50:15.283248
5767 22:50:15.283664 CH 1, Rank 1
5768 22:50:15.286447 SW Impedance : PASS
5769 22:50:15.286863 DUTY Scan : NO K
5770 22:50:15.289528 ZQ Calibration : PASS
5771 22:50:15.293097 Jitter Meter : NO K
5772 22:50:15.293508 CBT Training : PASS
5773 22:50:15.296061 Write leveling : PASS
5774 22:50:15.299452 RX DQS gating : PASS
5775 22:50:15.299978 RX DQ/DQS(RDDQC) : PASS
5776 22:50:15.303022 TX DQ/DQS : PASS
5777 22:50:15.306426 RX DATLAT : PASS
5778 22:50:15.306839 RX DQ/DQS(Engine): PASS
5779 22:50:15.309845 TX OE : NO K
5780 22:50:15.310407 All Pass.
5781 22:50:15.310744
5782 22:50:15.313174 DramC Write-DBI off
5783 22:50:15.316422 PER_BANK_REFRESH: Hybrid Mode
5784 22:50:15.316944 TX_TRACKING: ON
5785 22:50:15.326288 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5786 22:50:15.329276 [FAST_K] Save calibration result to emmc
5787 22:50:15.332690 dramc_set_vcore_voltage set vcore to 650000
5788 22:50:15.336149 Read voltage for 400, 6
5789 22:50:15.336661 Vio18 = 0
5790 22:50:15.336992 Vcore = 650000
5791 22:50:15.339640 Vdram = 0
5792 22:50:15.340050 Vddq = 0
5793 22:50:15.340374 Vmddr = 0
5794 22:50:15.346646 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5795 22:50:15.349572 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5796 22:50:15.352785 MEM_TYPE=3, freq_sel=20
5797 22:50:15.355767 sv_algorithm_assistance_LP4_800
5798 22:50:15.359309 ============ PULL DRAM RESETB DOWN ============
5799 22:50:15.362891 ========== PULL DRAM RESETB DOWN end =========
5800 22:50:15.369537 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5801 22:50:15.372435 ===================================
5802 22:50:15.376079 LPDDR4 DRAM CONFIGURATION
5803 22:50:15.379166 ===================================
5804 22:50:15.379588 EX_ROW_EN[0] = 0x0
5805 22:50:15.382500 EX_ROW_EN[1] = 0x0
5806 22:50:15.382917 LP4Y_EN = 0x0
5807 22:50:15.385976 WORK_FSP = 0x0
5808 22:50:15.386428 WL = 0x2
5809 22:50:15.389033 RL = 0x2
5810 22:50:15.389444 BL = 0x2
5811 22:50:15.392787 RPST = 0x0
5812 22:50:15.393327 RD_PRE = 0x0
5813 22:50:15.396343 WR_PRE = 0x1
5814 22:50:15.396905 WR_PST = 0x0
5815 22:50:15.399046 DBI_WR = 0x0
5816 22:50:15.399504 DBI_RD = 0x0
5817 22:50:15.402587 OTF = 0x1
5818 22:50:15.406195 ===================================
5819 22:50:15.409520 ===================================
5820 22:50:15.410120 ANA top config
5821 22:50:15.412613 ===================================
5822 22:50:15.416054 DLL_ASYNC_EN = 0
5823 22:50:15.419374 ALL_SLAVE_EN = 1
5824 22:50:15.422964 NEW_RANK_MODE = 1
5825 22:50:15.423538 DLL_IDLE_MODE = 1
5826 22:50:15.426096 LP45_APHY_COMB_EN = 1
5827 22:50:15.429561 TX_ODT_DIS = 1
5828 22:50:15.432954 NEW_8X_MODE = 1
5829 22:50:15.435653 ===================================
5830 22:50:15.439616 ===================================
5831 22:50:15.442354 data_rate = 800
5832 22:50:15.445730 CKR = 1
5833 22:50:15.446320 DQ_P2S_RATIO = 4
5834 22:50:15.449353 ===================================
5835 22:50:15.452180 CA_P2S_RATIO = 4
5836 22:50:15.455775 DQ_CA_OPEN = 0
5837 22:50:15.458939 DQ_SEMI_OPEN = 1
5838 22:50:15.462437 CA_SEMI_OPEN = 1
5839 22:50:15.462998 CA_FULL_RATE = 0
5840 22:50:15.465384 DQ_CKDIV4_EN = 0
5841 22:50:15.468826 CA_CKDIV4_EN = 1
5842 22:50:15.472161 CA_PREDIV_EN = 0
5843 22:50:15.475464 PH8_DLY = 0
5844 22:50:15.478861 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5845 22:50:15.479338 DQ_AAMCK_DIV = 0
5846 22:50:15.481938 CA_AAMCK_DIV = 0
5847 22:50:15.485540 CA_ADMCK_DIV = 4
5848 22:50:15.488540 DQ_TRACK_CA_EN = 0
5849 22:50:15.492087 CA_PICK = 800
5850 22:50:15.495702 CA_MCKIO = 400
5851 22:50:15.498709 MCKIO_SEMI = 400
5852 22:50:15.502086 PLL_FREQ = 3016
5853 22:50:15.502503 DQ_UI_PI_RATIO = 32
5854 22:50:15.505715 CA_UI_PI_RATIO = 32
5855 22:50:15.508421 ===================================
5856 22:50:15.512154 ===================================
5857 22:50:15.515454 memory_type:LPDDR4
5858 22:50:15.518561 GP_NUM : 10
5859 22:50:15.518972 SRAM_EN : 1
5860 22:50:15.521778 MD32_EN : 0
5861 22:50:15.525559 ===================================
5862 22:50:15.526116 [ANA_INIT] >>>>>>>>>>>>>>
5863 22:50:15.528869 <<<<<< [CONFIGURE PHASE]: ANA_TX
5864 22:50:15.532107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5865 22:50:15.535519 ===================================
5866 22:50:15.538217 data_rate = 800,PCW = 0X7400
5867 22:50:15.541747 ===================================
5868 22:50:15.545393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5869 22:50:15.551766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5870 22:50:15.561909 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5871 22:50:15.568821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5872 22:50:15.571618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5873 22:50:15.574953 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5874 22:50:15.575431 [ANA_INIT] flow start
5875 22:50:15.577960 [ANA_INIT] PLL >>>>>>>>
5876 22:50:15.581499 [ANA_INIT] PLL <<<<<<<<
5877 22:50:15.585262 [ANA_INIT] MIDPI >>>>>>>>
5878 22:50:15.585770 [ANA_INIT] MIDPI <<<<<<<<
5879 22:50:15.588080 [ANA_INIT] DLL >>>>>>>>
5880 22:50:15.588487 [ANA_INIT] flow end
5881 22:50:15.594560 ============ LP4 DIFF to SE enter ============
5882 22:50:15.597735 ============ LP4 DIFF to SE exit ============
5883 22:50:15.601560 [ANA_INIT] <<<<<<<<<<<<<
5884 22:50:15.604691 [Flow] Enable top DCM control >>>>>
5885 22:50:15.607925 [Flow] Enable top DCM control <<<<<
5886 22:50:15.611562 Enable DLL master slave shuffle
5887 22:50:15.614521 ==============================================================
5888 22:50:15.617798 Gating Mode config
5889 22:50:15.621265 ==============================================================
5890 22:50:15.624416 Config description:
5891 22:50:15.634457 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5892 22:50:15.641052 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5893 22:50:15.644539 SELPH_MODE 0: By rank 1: By Phase
5894 22:50:15.650958 ==============================================================
5895 22:50:15.654467 GAT_TRACK_EN = 0
5896 22:50:15.657829 RX_GATING_MODE = 2
5897 22:50:15.661178 RX_GATING_TRACK_MODE = 2
5898 22:50:15.664070 SELPH_MODE = 1
5899 22:50:15.667380 PICG_EARLY_EN = 1
5900 22:50:15.670804 VALID_LAT_VALUE = 1
5901 22:50:15.674281 ==============================================================
5902 22:50:15.677375 Enter into Gating configuration >>>>
5903 22:50:15.681005 Exit from Gating configuration <<<<
5904 22:50:15.684137 Enter into DVFS_PRE_config >>>>>
5905 22:50:15.694114 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5906 22:50:15.697600 Exit from DVFS_PRE_config <<<<<
5907 22:50:15.700973 Enter into PICG configuration >>>>
5908 22:50:15.704104 Exit from PICG configuration <<<<
5909 22:50:15.707346 [RX_INPUT] configuration >>>>>
5910 22:50:15.710534 [RX_INPUT] configuration <<<<<
5911 22:50:15.717072 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5912 22:50:15.720562 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5913 22:50:15.727350 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5914 22:50:15.733811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5915 22:50:15.740463 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5916 22:50:15.746832 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5917 22:50:15.750091 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5918 22:50:15.753390 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5919 22:50:15.756720 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5920 22:50:15.763729 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5921 22:50:15.766597 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5922 22:50:15.769835 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5923 22:50:15.773257 ===================================
5924 22:50:15.777313 LPDDR4 DRAM CONFIGURATION
5925 22:50:15.779712 ===================================
5926 22:50:15.783146 EX_ROW_EN[0] = 0x0
5927 22:50:15.783654 EX_ROW_EN[1] = 0x0
5928 22:50:15.786337 LP4Y_EN = 0x0
5929 22:50:15.786748 WORK_FSP = 0x0
5930 22:50:15.789848 WL = 0x2
5931 22:50:15.790407 RL = 0x2
5932 22:50:15.793121 BL = 0x2
5933 22:50:15.793633 RPST = 0x0
5934 22:50:15.796677 RD_PRE = 0x0
5935 22:50:15.797188 WR_PRE = 0x1
5936 22:50:15.799619 WR_PST = 0x0
5937 22:50:15.800029 DBI_WR = 0x0
5938 22:50:15.803041 DBI_RD = 0x0
5939 22:50:15.803699 OTF = 0x1
5940 22:50:15.806202 ===================================
5941 22:50:15.812804 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5942 22:50:15.816681 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5943 22:50:15.819529 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5944 22:50:15.822856 ===================================
5945 22:50:15.826317 LPDDR4 DRAM CONFIGURATION
5946 22:50:15.829429 ===================================
5947 22:50:15.832856 EX_ROW_EN[0] = 0x10
5948 22:50:15.833392 EX_ROW_EN[1] = 0x0
5949 22:50:15.836155 LP4Y_EN = 0x0
5950 22:50:15.836704 WORK_FSP = 0x0
5951 22:50:15.839236 WL = 0x2
5952 22:50:15.839787 RL = 0x2
5953 22:50:15.842937 BL = 0x2
5954 22:50:15.843487 RPST = 0x0
5955 22:50:15.846107 RD_PRE = 0x0
5956 22:50:15.846661 WR_PRE = 0x1
5957 22:50:15.849113 WR_PST = 0x0
5958 22:50:15.849568 DBI_WR = 0x0
5959 22:50:15.852553 DBI_RD = 0x0
5960 22:50:15.853107 OTF = 0x1
5961 22:50:15.855801 ===================================
5962 22:50:15.862419 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5963 22:50:15.866938 nWR fixed to 30
5964 22:50:15.870365 [ModeRegInit_LP4] CH0 RK0
5965 22:50:15.870780 [ModeRegInit_LP4] CH0 RK1
5966 22:50:15.873678 [ModeRegInit_LP4] CH1 RK0
5967 22:50:15.876980 [ModeRegInit_LP4] CH1 RK1
5968 22:50:15.877394 match AC timing 18
5969 22:50:15.883829 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5970 22:50:15.886781 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5971 22:50:15.890139 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5972 22:50:15.897291 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5973 22:50:15.900583 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5974 22:50:15.901096 ==
5975 22:50:15.903656 Dram Type= 6, Freq= 0, CH_0, rank 0
5976 22:50:15.906705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5977 22:50:15.907121 ==
5978 22:50:15.913627 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5979 22:50:15.920439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5980 22:50:15.923621 [CA 0] Center 36 (8~64) winsize 57
5981 22:50:15.927124 [CA 1] Center 36 (8~64) winsize 57
5982 22:50:15.930368 [CA 2] Center 36 (8~64) winsize 57
5983 22:50:15.933621 [CA 3] Center 36 (8~64) winsize 57
5984 22:50:15.934214 [CA 4] Center 36 (8~64) winsize 57
5985 22:50:15.936743 [CA 5] Center 36 (8~64) winsize 57
5986 22:50:15.937297
5987 22:50:15.943409 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5988 22:50:15.943959
5989 22:50:15.946862 [CATrainingPosCal] consider 1 rank data
5990 22:50:15.950085 u2DelayCellTimex100 = 270/100 ps
5991 22:50:15.953538 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5992 22:50:15.956655 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5993 22:50:15.960281 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5994 22:50:15.963183 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5995 22:50:15.966211 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5996 22:50:15.969603 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5997 22:50:15.970103
5998 22:50:15.973028 CA PerBit enable=1, Macro0, CA PI delay=36
5999 22:50:15.973456
6000 22:50:15.976476 [CBTSetCACLKResult] CA Dly = 36
6001 22:50:15.979983 CS Dly: 1 (0~32)
6002 22:50:15.980619 ==
6003 22:50:15.982912 Dram Type= 6, Freq= 0, CH_0, rank 1
6004 22:50:15.986141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6005 22:50:15.986659 ==
6006 22:50:15.992780 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6007 22:50:16.000356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6008 22:50:16.002570 [CA 0] Center 36 (8~64) winsize 57
6009 22:50:16.003197 [CA 1] Center 36 (8~64) winsize 57
6010 22:50:16.006599 [CA 2] Center 36 (8~64) winsize 57
6011 22:50:16.009670 [CA 3] Center 36 (8~64) winsize 57
6012 22:50:16.013233 [CA 4] Center 36 (8~64) winsize 57
6013 22:50:16.016352 [CA 5] Center 36 (8~64) winsize 57
6014 22:50:16.016910
6015 22:50:16.019454 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6016 22:50:16.020012
6017 22:50:16.026229 [CATrainingPosCal] consider 2 rank data
6018 22:50:16.026798 u2DelayCellTimex100 = 270/100 ps
6019 22:50:16.032524 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6020 22:50:16.036096 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 22:50:16.038964 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6022 22:50:16.042785 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6023 22:50:16.046257 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6024 22:50:16.048793 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 22:50:16.049254
6026 22:50:16.052259 CA PerBit enable=1, Macro0, CA PI delay=36
6027 22:50:16.052809
6028 22:50:16.055696 [CBTSetCACLKResult] CA Dly = 36
6029 22:50:16.058896 CS Dly: 1 (0~32)
6030 22:50:16.059443
6031 22:50:16.062331 ----->DramcWriteLeveling(PI) begin...
6032 22:50:16.062889 ==
6033 22:50:16.065593 Dram Type= 6, Freq= 0, CH_0, rank 0
6034 22:50:16.068716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6035 22:50:16.069132 ==
6036 22:50:16.072308 Write leveling (Byte 0): 32 => 0
6037 22:50:16.075363 Write leveling (Byte 1): 32 => 0
6038 22:50:16.078637 DramcWriteLeveling(PI) end<-----
6039 22:50:16.079053
6040 22:50:16.079377 ==
6041 22:50:16.082127 Dram Type= 6, Freq= 0, CH_0, rank 0
6042 22:50:16.085638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6043 22:50:16.086220 ==
6044 22:50:16.088932 [Gating] SW mode calibration
6045 22:50:16.095477 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6046 22:50:16.102289 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6047 22:50:16.105354 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6048 22:50:16.108585 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6049 22:50:16.115291 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6050 22:50:16.118622 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6051 22:50:16.121732 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6052 22:50:16.128382 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6053 22:50:16.131804 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6054 22:50:16.135296 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6055 22:50:16.141749 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6056 22:50:16.142339 Total UI for P1: 0, mck2ui 16
6057 22:50:16.148533 best dqsien dly found for B0: ( 0, 10, 16)
6058 22:50:16.149088 Total UI for P1: 0, mck2ui 16
6059 22:50:16.154917 best dqsien dly found for B1: ( 0, 10, 16)
6060 22:50:16.158320 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6061 22:50:16.161363 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6062 22:50:16.161914
6063 22:50:16.165015 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6064 22:50:16.167960 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6065 22:50:16.171933 [Gating] SW calibration Done
6066 22:50:16.172490 ==
6067 22:50:16.174691 Dram Type= 6, Freq= 0, CH_0, rank 0
6068 22:50:16.177936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6069 22:50:16.178547 ==
6070 22:50:16.181068 RX Vref Scan: 0
6071 22:50:16.181726
6072 22:50:16.184445 RX Vref 0 -> 0, step: 1
6073 22:50:16.184999
6074 22:50:16.185399 RX Delay -410 -> 252, step: 16
6075 22:50:16.190932 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6076 22:50:16.194442 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6077 22:50:16.197617 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6078 22:50:16.204385 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6079 22:50:16.207739 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6080 22:50:16.210957 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6081 22:50:16.214639 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6082 22:50:16.217778 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6083 22:50:16.224409 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6084 22:50:16.227489 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6085 22:50:16.230909 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6086 22:50:16.237557 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6087 22:50:16.241441 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6088 22:50:16.244349 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6089 22:50:16.247608 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6090 22:50:16.254086 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6091 22:50:16.254656 ==
6092 22:50:16.257516 Dram Type= 6, Freq= 0, CH_0, rank 0
6093 22:50:16.260712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6094 22:50:16.261268 ==
6095 22:50:16.261629 DQS Delay:
6096 22:50:16.264708 DQS0 = 43, DQS1 = 59
6097 22:50:16.265262 DQM Delay:
6098 22:50:16.267458 DQM0 = 5, DQM1 = 13
6099 22:50:16.268011 DQ Delay:
6100 22:50:16.270580 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6101 22:50:16.273985 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6102 22:50:16.276912 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6103 22:50:16.280756 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6104 22:50:16.281342
6105 22:50:16.281756
6106 22:50:16.282352 ==
6107 22:50:16.284034 Dram Type= 6, Freq= 0, CH_0, rank 0
6108 22:50:16.286912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6109 22:50:16.287447 ==
6110 22:50:16.287814
6111 22:50:16.288152
6112 22:50:16.290363 TX Vref Scan disable
6113 22:50:16.290819 == TX Byte 0 ==
6114 22:50:16.296770 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6115 22:50:16.300557 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6116 22:50:16.303616 == TX Byte 1 ==
6117 22:50:16.306861 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6118 22:50:16.310117 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6119 22:50:16.310500 ==
6120 22:50:16.313304 Dram Type= 6, Freq= 0, CH_0, rank 0
6121 22:50:16.317297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6122 22:50:16.317812 ==
6123 22:50:16.320194
6124 22:50:16.320700
6125 22:50:16.321026 TX Vref Scan disable
6126 22:50:16.323317 == TX Byte 0 ==
6127 22:50:16.326906 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6128 22:50:16.330125 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6129 22:50:16.333684 == TX Byte 1 ==
6130 22:50:16.336979 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6131 22:50:16.339867 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6132 22:50:16.340388
6133 22:50:16.343236 [DATLAT]
6134 22:50:16.343750 Freq=400, CH0 RK0
6135 22:50:16.344077
6136 22:50:16.346925 DATLAT Default: 0xf
6137 22:50:16.347442 0, 0xFFFF, sum = 0
6138 22:50:16.349651 1, 0xFFFF, sum = 0
6139 22:50:16.350091 2, 0xFFFF, sum = 0
6140 22:50:16.353417 3, 0xFFFF, sum = 0
6141 22:50:16.353965 4, 0xFFFF, sum = 0
6142 22:50:16.356364 5, 0xFFFF, sum = 0
6143 22:50:16.356782 6, 0xFFFF, sum = 0
6144 22:50:16.359807 7, 0xFFFF, sum = 0
6145 22:50:16.360327 8, 0xFFFF, sum = 0
6146 22:50:16.362912 9, 0xFFFF, sum = 0
6147 22:50:16.363431 10, 0xFFFF, sum = 0
6148 22:50:16.366109 11, 0xFFFF, sum = 0
6149 22:50:16.366566 12, 0x0, sum = 1
6150 22:50:16.369494 13, 0x0, sum = 2
6151 22:50:16.369915 14, 0x0, sum = 3
6152 22:50:16.372619 15, 0x0, sum = 4
6153 22:50:16.373036 best_step = 13
6154 22:50:16.373362
6155 22:50:16.373665 ==
6156 22:50:16.376016 Dram Type= 6, Freq= 0, CH_0, rank 0
6157 22:50:16.382647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6158 22:50:16.383085 ==
6159 22:50:16.383419 RX Vref Scan: 1
6160 22:50:16.383727
6161 22:50:16.385777 RX Vref 0 -> 0, step: 1
6162 22:50:16.386299
6163 22:50:16.389477 RX Delay -359 -> 252, step: 8
6164 22:50:16.389989
6165 22:50:16.392846 Set Vref, RX VrefLevel [Byte0]: 47
6166 22:50:16.396158 [Byte1]: 49
6167 22:50:16.399401
6168 22:50:16.399912 Final RX Vref Byte 0 = 47 to rank0
6169 22:50:16.402488 Final RX Vref Byte 1 = 49 to rank0
6170 22:50:16.405772 Final RX Vref Byte 0 = 47 to rank1
6171 22:50:16.409346 Final RX Vref Byte 1 = 49 to rank1==
6172 22:50:16.412364 Dram Type= 6, Freq= 0, CH_0, rank 0
6173 22:50:16.419605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6174 22:50:16.420126 ==
6175 22:50:16.420456 DQS Delay:
6176 22:50:16.422534 DQS0 = 52, DQS1 = 68
6177 22:50:16.422948 DQM Delay:
6178 22:50:16.423273 DQM0 = 10, DQM1 = 17
6179 22:50:16.425763 DQ Delay:
6180 22:50:16.429162 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6181 22:50:16.429577 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6182 22:50:16.432654 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6183 22:50:16.436574 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6184 22:50:16.437107
6185 22:50:16.437435
6186 22:50:16.445778 [DQSOSCAuto] RK0, (LSB)MR18= 0xacac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6187 22:50:16.449157 CH0 RK0: MR19=C0C, MR18=ACAC
6188 22:50:16.455423 CH0_RK0: MR19=0xC0C, MR18=0xACAC, DQSOSC=388, MR23=63, INC=392, DEC=261
6189 22:50:16.456080 ==
6190 22:50:16.458832 Dram Type= 6, Freq= 0, CH_0, rank 1
6191 22:50:16.462658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6192 22:50:16.463089 ==
6193 22:50:16.465596 [Gating] SW mode calibration
6194 22:50:16.472493 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6195 22:50:16.478824 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6196 22:50:16.482236 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6197 22:50:16.485783 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6198 22:50:16.489206 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6199 22:50:16.495813 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6200 22:50:16.498757 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6201 22:50:16.505455 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6202 22:50:16.508820 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6203 22:50:16.511767 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6204 22:50:16.515692 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6205 22:50:16.518455 Total UI for P1: 0, mck2ui 16
6206 22:50:16.521698 best dqsien dly found for B0: ( 0, 10, 16)
6207 22:50:16.525437 Total UI for P1: 0, mck2ui 16
6208 22:50:16.528934 best dqsien dly found for B1: ( 0, 10, 16)
6209 22:50:16.532469 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6210 22:50:16.538821 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6211 22:50:16.539329
6212 22:50:16.542384 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6213 22:50:16.545300 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6214 22:50:16.548211 [Gating] SW calibration Done
6215 22:50:16.548627 ==
6216 22:50:16.551755 Dram Type= 6, Freq= 0, CH_0, rank 1
6217 22:50:16.554866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6218 22:50:16.555285 ==
6219 22:50:16.558116 RX Vref Scan: 0
6220 22:50:16.558531
6221 22:50:16.558854 RX Vref 0 -> 0, step: 1
6222 22:50:16.559156
6223 22:50:16.561853 RX Delay -410 -> 252, step: 16
6224 22:50:16.569136 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6225 22:50:16.571741 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6226 22:50:16.574777 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6227 22:50:16.578231 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6228 22:50:16.584935 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6229 22:50:16.587931 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6230 22:50:16.591671 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6231 22:50:16.594561 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6232 22:50:16.601777 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6233 22:50:16.604744 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6234 22:50:16.608258 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6235 22:50:16.611416 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6236 22:50:16.618020 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6237 22:50:16.621539 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6238 22:50:16.624887 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6239 22:50:16.627643 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6240 22:50:16.631193 ==
6241 22:50:16.631699 Dram Type= 6, Freq= 0, CH_0, rank 1
6242 22:50:16.638165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6243 22:50:16.638681 ==
6244 22:50:16.639014 DQS Delay:
6245 22:50:16.641136 DQS0 = 43, DQS1 = 59
6246 22:50:16.641550 DQM Delay:
6247 22:50:16.644138 DQM0 = 7, DQM1 = 15
6248 22:50:16.644553 DQ Delay:
6249 22:50:16.647863 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6250 22:50:16.650877 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6251 22:50:16.654355 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6252 22:50:16.657471 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6253 22:50:16.657884
6254 22:50:16.658261
6255 22:50:16.658570 ==
6256 22:50:16.660881 Dram Type= 6, Freq= 0, CH_0, rank 1
6257 22:50:16.664447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6258 22:50:16.664954 ==
6259 22:50:16.665288
6260 22:50:16.665593
6261 22:50:16.667328 TX Vref Scan disable
6262 22:50:16.667741 == TX Byte 0 ==
6263 22:50:16.674158 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6264 22:50:16.677632 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6265 22:50:16.678071 == TX Byte 1 ==
6266 22:50:16.683970 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6267 22:50:16.687167 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6268 22:50:16.687579 ==
6269 22:50:16.690603 Dram Type= 6, Freq= 0, CH_0, rank 1
6270 22:50:16.694149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6271 22:50:16.694711 ==
6272 22:50:16.695071
6273 22:50:16.695407
6274 22:50:16.697369 TX Vref Scan disable
6275 22:50:16.697777 == TX Byte 0 ==
6276 22:50:16.704052 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6277 22:50:16.707630 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6278 22:50:16.708187 == TX Byte 1 ==
6279 22:50:16.714426 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6280 22:50:16.717373 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6281 22:50:16.717949
6282 22:50:16.718350 [DATLAT]
6283 22:50:16.721028 Freq=400, CH0 RK1
6284 22:50:16.721585
6285 22:50:16.721941 DATLAT Default: 0xd
6286 22:50:16.723983 0, 0xFFFF, sum = 0
6287 22:50:16.724543 1, 0xFFFF, sum = 0
6288 22:50:16.727503 2, 0xFFFF, sum = 0
6289 22:50:16.728065 3, 0xFFFF, sum = 0
6290 22:50:16.730673 4, 0xFFFF, sum = 0
6291 22:50:16.731133 5, 0xFFFF, sum = 0
6292 22:50:16.733828 6, 0xFFFF, sum = 0
6293 22:50:16.734316 7, 0xFFFF, sum = 0
6294 22:50:16.737153 8, 0xFFFF, sum = 0
6295 22:50:16.737608 9, 0xFFFF, sum = 0
6296 22:50:16.740428 10, 0xFFFF, sum = 0
6297 22:50:16.743357 11, 0xFFFF, sum = 0
6298 22:50:16.743814 12, 0x0, sum = 1
6299 22:50:16.744283 13, 0x0, sum = 2
6300 22:50:16.746863 14, 0x0, sum = 3
6301 22:50:16.747275 15, 0x0, sum = 4
6302 22:50:16.749981 best_step = 13
6303 22:50:16.750549
6304 22:50:16.750929 ==
6305 22:50:16.753356 Dram Type= 6, Freq= 0, CH_0, rank 1
6306 22:50:16.756716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6307 22:50:16.757186 ==
6308 22:50:16.760466 RX Vref Scan: 0
6309 22:50:16.760852
6310 22:50:16.761082 RX Vref 0 -> 0, step: 1
6311 22:50:16.761292
6312 22:50:16.763446 RX Delay -359 -> 252, step: 8
6313 22:50:16.771776 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6314 22:50:16.774903 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6315 22:50:16.778148 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6316 22:50:16.782125 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6317 22:50:16.788766 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6318 22:50:16.791672 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6319 22:50:16.795046 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6320 22:50:16.798211 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6321 22:50:16.804948 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6322 22:50:16.808552 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6323 22:50:16.812042 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6324 22:50:16.818175 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6325 22:50:16.821765 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6326 22:50:16.825050 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6327 22:50:16.828275 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6328 22:50:16.834669 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6329 22:50:16.835227 ==
6330 22:50:16.838016 Dram Type= 6, Freq= 0, CH_0, rank 1
6331 22:50:16.841337 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6332 22:50:16.841896 ==
6333 22:50:16.842307 DQS Delay:
6334 22:50:16.844673 DQS0 = 52, DQS1 = 64
6335 22:50:16.845118 DQM Delay:
6336 22:50:16.847824 DQM0 = 10, DQM1 = 13
6337 22:50:16.848273 DQ Delay:
6338 22:50:16.851283 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6339 22:50:16.854900 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6340 22:50:16.858087 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6341 22:50:16.861468 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6342 22:50:16.862018
6343 22:50:16.862434
6344 22:50:16.867797 [DQSOSCAuto] RK1, (LSB)MR18= 0xc9c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6345 22:50:16.871224 CH0 RK1: MR19=C0C, MR18=C9C9
6346 22:50:16.878060 CH0_RK1: MR19=0xC0C, MR18=0xC9C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6347 22:50:16.881450 [RxdqsGatingPostProcess] freq 400
6348 22:50:16.887710 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6349 22:50:16.888205 Pre-setting of DQS Precalculation
6350 22:50:16.894526 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6351 22:50:16.895063 ==
6352 22:50:16.897665 Dram Type= 6, Freq= 0, CH_1, rank 0
6353 22:50:16.901434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6354 22:50:16.901943 ==
6355 22:50:16.907669 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6356 22:50:16.914139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6357 22:50:16.917582 [CA 0] Center 36 (8~64) winsize 57
6358 22:50:16.921104 [CA 1] Center 36 (8~64) winsize 57
6359 22:50:16.924029 [CA 2] Center 36 (8~64) winsize 57
6360 22:50:16.927946 [CA 3] Center 36 (8~64) winsize 57
6361 22:50:16.930869 [CA 4] Center 36 (8~64) winsize 57
6362 22:50:16.931421 [CA 5] Center 36 (8~64) winsize 57
6363 22:50:16.934193
6364 22:50:16.937717 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6365 22:50:16.938324
6366 22:50:16.940612 [CATrainingPosCal] consider 1 rank data
6367 22:50:16.944003 u2DelayCellTimex100 = 270/100 ps
6368 22:50:16.947082 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 22:50:16.950931 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 22:50:16.954018 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6371 22:50:16.957277 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 22:50:16.961005 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 22:50:16.963842 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 22:50:16.964302
6375 22:50:16.967294 CA PerBit enable=1, Macro0, CA PI delay=36
6376 22:50:16.967781
6377 22:50:16.970611 [CBTSetCACLKResult] CA Dly = 36
6378 22:50:16.973660 CS Dly: 1 (0~32)
6379 22:50:16.974162 ==
6380 22:50:16.977075 Dram Type= 6, Freq= 0, CH_1, rank 1
6381 22:50:16.980691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6382 22:50:16.981151 ==
6383 22:50:16.987147 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6384 22:50:16.993390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6385 22:50:16.996653 [CA 0] Center 36 (8~64) winsize 57
6386 22:50:17.000159 [CA 1] Center 36 (8~64) winsize 57
6387 22:50:17.000677 [CA 2] Center 36 (8~64) winsize 57
6388 22:50:17.003777 [CA 3] Center 36 (8~64) winsize 57
6389 22:50:17.006616 [CA 4] Center 36 (8~64) winsize 57
6390 22:50:17.009707 [CA 5] Center 36 (8~64) winsize 57
6391 22:50:17.010168
6392 22:50:17.013359 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6393 22:50:17.016867
6394 22:50:17.019898 [CATrainingPosCal] consider 2 rank data
6395 22:50:17.020313 u2DelayCellTimex100 = 270/100 ps
6396 22:50:17.026357 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6397 22:50:17.029986 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 22:50:17.033195 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6399 22:50:17.036532 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6400 22:50:17.039467 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6401 22:50:17.042934 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 22:50:17.043349
6403 22:50:17.046246 CA PerBit enable=1, Macro0, CA PI delay=36
6404 22:50:17.046687
6405 22:50:17.049383 [CBTSetCACLKResult] CA Dly = 36
6406 22:50:17.053073 CS Dly: 1 (0~32)
6407 22:50:17.053490
6408 22:50:17.056522 ----->DramcWriteLeveling(PI) begin...
6409 22:50:17.056981 ==
6410 22:50:17.059491 Dram Type= 6, Freq= 0, CH_1, rank 0
6411 22:50:17.062895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6412 22:50:17.063400 ==
6413 22:50:17.066100 Write leveling (Byte 0): 32 => 0
6414 22:50:17.069518 Write leveling (Byte 1): 32 => 0
6415 22:50:17.072882 DramcWriteLeveling(PI) end<-----
6416 22:50:17.073472
6417 22:50:17.073874 ==
6418 22:50:17.075934 Dram Type= 6, Freq= 0, CH_1, rank 0
6419 22:50:17.079546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6420 22:50:17.079959 ==
6421 22:50:17.082736 [Gating] SW mode calibration
6422 22:50:17.089458 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6423 22:50:17.096462 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6424 22:50:17.099636 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 22:50:17.102477 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 22:50:17.109904 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 22:50:17.112529 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6428 22:50:17.116271 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 22:50:17.122623 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 22:50:17.125844 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 22:50:17.129259 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6432 22:50:17.135694 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 22:50:17.136258 Total UI for P1: 0, mck2ui 16
6434 22:50:17.142516 best dqsien dly found for B0: ( 0, 10, 16)
6435 22:50:17.143070 Total UI for P1: 0, mck2ui 16
6436 22:50:17.149128 best dqsien dly found for B1: ( 0, 10, 16)
6437 22:50:17.152573 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6438 22:50:17.155711 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6439 22:50:17.156265
6440 22:50:17.159230 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6441 22:50:17.162138 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6442 22:50:17.165400 [Gating] SW calibration Done
6443 22:50:17.165880 ==
6444 22:50:17.168673 Dram Type= 6, Freq= 0, CH_1, rank 0
6445 22:50:17.172022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6446 22:50:17.172555 ==
6447 22:50:17.175717 RX Vref Scan: 0
6448 22:50:17.176375
6449 22:50:17.176837 RX Vref 0 -> 0, step: 1
6450 22:50:17.178732
6451 22:50:17.179182 RX Delay -410 -> 252, step: 16
6452 22:50:17.185145 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6453 22:50:17.188616 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6454 22:50:17.191729 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6455 22:50:17.195485 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6456 22:50:17.202173 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6457 22:50:17.205215 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6458 22:50:17.208718 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6459 22:50:17.212419 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6460 22:50:17.219014 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6461 22:50:17.221639 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6462 22:50:17.224983 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6463 22:50:17.231550 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6464 22:50:17.235391 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6465 22:50:17.238346 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6466 22:50:17.241712 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6467 22:50:17.248262 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6468 22:50:17.248675 ==
6469 22:50:17.251172 Dram Type= 6, Freq= 0, CH_1, rank 0
6470 22:50:17.254885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6471 22:50:17.255406 ==
6472 22:50:17.255734 DQS Delay:
6473 22:50:17.258088 DQS0 = 43, DQS1 = 59
6474 22:50:17.258505 DQM Delay:
6475 22:50:17.261265 DQM0 = 9, DQM1 = 16
6476 22:50:17.261677 DQ Delay:
6477 22:50:17.264618 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6478 22:50:17.267902 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6479 22:50:17.271165 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6480 22:50:17.274533 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6481 22:50:17.275079
6482 22:50:17.275438
6483 22:50:17.275744 ==
6484 22:50:17.277881 Dram Type= 6, Freq= 0, CH_1, rank 0
6485 22:50:17.281344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6486 22:50:17.281829 ==
6487 22:50:17.282313
6488 22:50:17.282630
6489 22:50:17.284592 TX Vref Scan disable
6490 22:50:17.287635 == TX Byte 0 ==
6491 22:50:17.291069 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6492 22:50:17.294522 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6493 22:50:17.297877 == TX Byte 1 ==
6494 22:50:17.301121 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6495 22:50:17.304357 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6496 22:50:17.304881 ==
6497 22:50:17.307773 Dram Type= 6, Freq= 0, CH_1, rank 0
6498 22:50:17.310794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6499 22:50:17.314565 ==
6500 22:50:17.315079
6501 22:50:17.315403
6502 22:50:17.315703 TX Vref Scan disable
6503 22:50:17.317304 == TX Byte 0 ==
6504 22:50:17.321069 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6505 22:50:17.324111 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6506 22:50:17.327449 == TX Byte 1 ==
6507 22:50:17.331112 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6508 22:50:17.334108 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6509 22:50:17.334674
6510 22:50:17.337836 [DATLAT]
6511 22:50:17.338451 Freq=400, CH1 RK0
6512 22:50:17.338818
6513 22:50:17.340799 DATLAT Default: 0xf
6514 22:50:17.341350 0, 0xFFFF, sum = 0
6515 22:50:17.344097 1, 0xFFFF, sum = 0
6516 22:50:17.344569 2, 0xFFFF, sum = 0
6517 22:50:17.347516 3, 0xFFFF, sum = 0
6518 22:50:17.348100 4, 0xFFFF, sum = 0
6519 22:50:17.350559 5, 0xFFFF, sum = 0
6520 22:50:17.351112 6, 0xFFFF, sum = 0
6521 22:50:17.354080 7, 0xFFFF, sum = 0
6522 22:50:17.354690 8, 0xFFFF, sum = 0
6523 22:50:17.357211 9, 0xFFFF, sum = 0
6524 22:50:17.360791 10, 0xFFFF, sum = 0
6525 22:50:17.361351 11, 0xFFFF, sum = 0
6526 22:50:17.364074 12, 0x0, sum = 1
6527 22:50:17.364643 13, 0x0, sum = 2
6528 22:50:17.365014 14, 0x0, sum = 3
6529 22:50:17.367012 15, 0x0, sum = 4
6530 22:50:17.367475 best_step = 13
6531 22:50:17.367840
6532 22:50:17.368284 ==
6533 22:50:17.370384 Dram Type= 6, Freq= 0, CH_1, rank 0
6534 22:50:17.376897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6535 22:50:17.377450 ==
6536 22:50:17.377835 RX Vref Scan: 1
6537 22:50:17.378233
6538 22:50:17.380379 RX Vref 0 -> 0, step: 1
6539 22:50:17.380838
6540 22:50:17.384151 RX Delay -359 -> 252, step: 8
6541 22:50:17.384712
6542 22:50:17.387033 Set Vref, RX VrefLevel [Byte0]: 56
6543 22:50:17.390366 [Byte1]: 49
6544 22:50:17.394007
6545 22:50:17.394649 Final RX Vref Byte 0 = 56 to rank0
6546 22:50:17.397167 Final RX Vref Byte 1 = 49 to rank0
6547 22:50:17.401137 Final RX Vref Byte 0 = 56 to rank1
6548 22:50:17.404095 Final RX Vref Byte 1 = 49 to rank1==
6549 22:50:17.407342 Dram Type= 6, Freq= 0, CH_1, rank 0
6550 22:50:17.413781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6551 22:50:17.414453 ==
6552 22:50:17.414829 DQS Delay:
6553 22:50:17.416952 DQS0 = 48, DQS1 = 68
6554 22:50:17.417514 DQM Delay:
6555 22:50:17.417881 DQM0 = 8, DQM1 = 21
6556 22:50:17.420054 DQ Delay:
6557 22:50:17.423535 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =8
6558 22:50:17.424176 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6559 22:50:17.426667 DQ8 =0, DQ9 =12, DQ10 =24, DQ11 =12
6560 22:50:17.430485 DQ12 =28, DQ13 =32, DQ14 =28, DQ15 =32
6561 22:50:17.431072
6562 22:50:17.433299
6563 22:50:17.440439 [DQSOSCAuto] RK0, (LSB)MR18= 0xcfcf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6564 22:50:17.443384 CH1 RK0: MR19=C0C, MR18=CFCF
6565 22:50:17.450319 CH1_RK0: MR19=0xC0C, MR18=0xCFCF, DQSOSC=384, MR23=63, INC=400, DEC=267
6566 22:50:17.450884 ==
6567 22:50:17.453314 Dram Type= 6, Freq= 0, CH_1, rank 1
6568 22:50:17.456716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6569 22:50:17.457282 ==
6570 22:50:17.460032 [Gating] SW mode calibration
6571 22:50:17.466558 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6572 22:50:17.473453 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6573 22:50:17.476329 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6574 22:50:17.479672 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6575 22:50:17.486606 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6576 22:50:17.489270 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6577 22:50:17.492740 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6578 22:50:17.499119 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6579 22:50:17.502981 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6580 22:50:17.505792 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6581 22:50:17.512464 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6582 22:50:17.512886 Total UI for P1: 0, mck2ui 16
6583 22:50:17.518919 best dqsien dly found for B0: ( 0, 10, 16)
6584 22:50:17.519337 Total UI for P1: 0, mck2ui 16
6585 22:50:17.525579 best dqsien dly found for B1: ( 0, 10, 16)
6586 22:50:17.528856 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6587 22:50:17.532482 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6588 22:50:17.532921
6589 22:50:17.535864 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6590 22:50:17.539279 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6591 22:50:17.542418 [Gating] SW calibration Done
6592 22:50:17.542834 ==
6593 22:50:17.545658 Dram Type= 6, Freq= 0, CH_1, rank 1
6594 22:50:17.549137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6595 22:50:17.549554 ==
6596 22:50:17.552352 RX Vref Scan: 0
6597 22:50:17.552765
6598 22:50:17.553090 RX Vref 0 -> 0, step: 1
6599 22:50:17.553395
6600 22:50:17.555877 RX Delay -410 -> 252, step: 16
6601 22:50:17.562593 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6602 22:50:17.565864 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6603 22:50:17.568739 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6604 22:50:17.572031 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6605 22:50:17.578989 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6606 22:50:17.582177 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6607 22:50:17.585797 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6608 22:50:17.588577 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6609 22:50:17.595360 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6610 22:50:17.598519 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6611 22:50:17.601723 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6612 22:50:17.605522 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6613 22:50:17.612074 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6614 22:50:17.614842 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6615 22:50:17.618389 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6616 22:50:17.625389 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6617 22:50:17.625904 ==
6618 22:50:17.628249 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 22:50:17.631569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6620 22:50:17.631986 ==
6621 22:50:17.632312 DQS Delay:
6622 22:50:17.634953 DQS0 = 43, DQS1 = 59
6623 22:50:17.635370 DQM Delay:
6624 22:50:17.638148 DQM0 = 9, DQM1 = 17
6625 22:50:17.638559 DQ Delay:
6626 22:50:17.641772 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6627 22:50:17.645071 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6628 22:50:17.648394 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6629 22:50:17.651433 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6630 22:50:17.651988
6631 22:50:17.652407
6632 22:50:17.652798 ==
6633 22:50:17.654753 Dram Type= 6, Freq= 0, CH_1, rank 1
6634 22:50:17.658069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6635 22:50:17.658543 ==
6636 22:50:17.658966
6637 22:50:17.659352
6638 22:50:17.661200 TX Vref Scan disable
6639 22:50:17.661655 == TX Byte 0 ==
6640 22:50:17.667939 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6641 22:50:17.671218 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6642 22:50:17.671677 == TX Byte 1 ==
6643 22:50:17.677754 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6644 22:50:17.681269 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6645 22:50:17.681827 ==
6646 22:50:17.684485 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 22:50:17.687880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6648 22:50:17.688513 ==
6649 22:50:17.688965
6650 22:50:17.689314
6651 22:50:17.691612 TX Vref Scan disable
6652 22:50:17.692063 == TX Byte 0 ==
6653 22:50:17.697908 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6654 22:50:17.701334 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6655 22:50:17.701799 == TX Byte 1 ==
6656 22:50:17.708256 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6657 22:50:17.710923 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6658 22:50:17.711386
6659 22:50:17.711745 [DATLAT]
6660 22:50:17.714337 Freq=400, CH1 RK1
6661 22:50:17.714794
6662 22:50:17.715149 DATLAT Default: 0xd
6663 22:50:17.717467 0, 0xFFFF, sum = 0
6664 22:50:17.717931 1, 0xFFFF, sum = 0
6665 22:50:17.721286 2, 0xFFFF, sum = 0
6666 22:50:17.721844 3, 0xFFFF, sum = 0
6667 22:50:17.724016 4, 0xFFFF, sum = 0
6668 22:50:17.724480 5, 0xFFFF, sum = 0
6669 22:50:17.727690 6, 0xFFFF, sum = 0
6670 22:50:17.730612 7, 0xFFFF, sum = 0
6671 22:50:17.731075 8, 0xFFFF, sum = 0
6672 22:50:17.734431 9, 0xFFFF, sum = 0
6673 22:50:17.735005 10, 0xFFFF, sum = 0
6674 22:50:17.737446 11, 0xFFFF, sum = 0
6675 22:50:17.738008 12, 0x0, sum = 1
6676 22:50:17.740540 13, 0x0, sum = 2
6677 22:50:17.741002 14, 0x0, sum = 3
6678 22:50:17.744137 15, 0x0, sum = 4
6679 22:50:17.744607 best_step = 13
6680 22:50:17.744966
6681 22:50:17.745306 ==
6682 22:50:17.747395 Dram Type= 6, Freq= 0, CH_1, rank 1
6683 22:50:17.750798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6684 22:50:17.751353 ==
6685 22:50:17.754245 RX Vref Scan: 0
6686 22:50:17.754793
6687 22:50:17.757012 RX Vref 0 -> 0, step: 1
6688 22:50:17.757474
6689 22:50:17.757837 RX Delay -359 -> 252, step: 8
6690 22:50:17.766082 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6691 22:50:17.769374 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6692 22:50:17.772675 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6693 22:50:17.779348 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6694 22:50:17.782685 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6695 22:50:17.785929 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6696 22:50:17.789204 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6697 22:50:17.795975 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6698 22:50:17.799059 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6699 22:50:17.802581 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6700 22:50:17.805723 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6701 22:50:17.812606 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6702 22:50:17.815876 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6703 22:50:17.819132 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6704 22:50:17.822464 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6705 22:50:17.829698 iDelay=225, Bit 15, Center -44 (-287 ~ 200) 488
6706 22:50:17.830389 ==
6707 22:50:17.832261 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 22:50:17.835588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6709 22:50:17.836051 ==
6710 22:50:17.836408 DQS Delay:
6711 22:50:17.839156 DQS0 = 48, DQS1 = 64
6712 22:50:17.839707 DQM Delay:
6713 22:50:17.842876 DQM0 = 9, DQM1 = 15
6714 22:50:17.843635 DQ Delay:
6715 22:50:17.845381 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6716 22:50:17.849146 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6717 22:50:17.852404 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6718 22:50:17.855495 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6719 22:50:17.856051
6720 22:50:17.856407
6721 22:50:17.862202 [DQSOSCAuto] RK1, (LSB)MR18= 0xa9a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6722 22:50:17.865534 CH1 RK1: MR19=C0C, MR18=A9A9
6723 22:50:17.872252 CH1_RK1: MR19=0xC0C, MR18=0xA9A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6724 22:50:17.875282 [RxdqsGatingPostProcess] freq 400
6725 22:50:17.882285 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6726 22:50:17.882853 Pre-setting of DQS Precalculation
6727 22:50:17.888646 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6728 22:50:17.895834 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6729 22:50:17.901838 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6730 22:50:17.902372
6731 22:50:17.902776
6732 22:50:17.904901 [Calibration Summary] 800 Mbps
6733 22:50:17.908312 CH 0, Rank 0
6734 22:50:17.908772 SW Impedance : PASS
6735 22:50:17.911850 DUTY Scan : NO K
6736 22:50:17.915194 ZQ Calibration : PASS
6737 22:50:17.915657 Jitter Meter : NO K
6738 22:50:17.918236 CBT Training : PASS
6739 22:50:17.921684 Write leveling : PASS
6740 22:50:17.922279 RX DQS gating : PASS
6741 22:50:17.925364 RX DQ/DQS(RDDQC) : PASS
6742 22:50:17.928483 TX DQ/DQS : PASS
6743 22:50:17.929091 RX DATLAT : PASS
6744 22:50:17.931481 RX DQ/DQS(Engine): PASS
6745 22:50:17.931938 TX OE : NO K
6746 22:50:17.934883 All Pass.
6747 22:50:17.935343
6748 22:50:17.935703 CH 0, Rank 1
6749 22:50:17.938168 SW Impedance : PASS
6750 22:50:17.938631 DUTY Scan : NO K
6751 22:50:17.941472 ZQ Calibration : PASS
6752 22:50:17.945202 Jitter Meter : NO K
6753 22:50:17.945661 CBT Training : PASS
6754 22:50:17.948105 Write leveling : NO K
6755 22:50:17.951386 RX DQS gating : PASS
6756 22:50:17.951855 RX DQ/DQS(RDDQC) : PASS
6757 22:50:17.955187 TX DQ/DQS : PASS
6758 22:50:17.958099 RX DATLAT : PASS
6759 22:50:17.958566 RX DQ/DQS(Engine): PASS
6760 22:50:17.961456 TX OE : NO K
6761 22:50:17.962048 All Pass.
6762 22:50:17.962416
6763 22:50:17.964630 CH 1, Rank 0
6764 22:50:17.965086 SW Impedance : PASS
6765 22:50:17.968069 DUTY Scan : NO K
6766 22:50:17.971493 ZQ Calibration : PASS
6767 22:50:17.971954 Jitter Meter : NO K
6768 22:50:17.974519 CBT Training : PASS
6769 22:50:17.977949 Write leveling : PASS
6770 22:50:17.978434 RX DQS gating : PASS
6771 22:50:17.981570 RX DQ/DQS(RDDQC) : PASS
6772 22:50:17.985013 TX DQ/DQS : PASS
6773 22:50:17.985568 RX DATLAT : PASS
6774 22:50:17.987824 RX DQ/DQS(Engine): PASS
6775 22:50:17.988297 TX OE : NO K
6776 22:50:17.991401 All Pass.
6777 22:50:17.991862
6778 22:50:17.992225 CH 1, Rank 1
6779 22:50:17.994807 SW Impedance : PASS
6780 22:50:17.995268 DUTY Scan : NO K
6781 22:50:17.997615 ZQ Calibration : PASS
6782 22:50:18.000872 Jitter Meter : NO K
6783 22:50:18.001383 CBT Training : PASS
6784 22:50:18.004220 Write leveling : NO K
6785 22:50:18.007838 RX DQS gating : PASS
6786 22:50:18.008508 RX DQ/DQS(RDDQC) : PASS
6787 22:50:18.011737 TX DQ/DQS : PASS
6788 22:50:18.014447 RX DATLAT : PASS
6789 22:50:18.014867 RX DQ/DQS(Engine): PASS
6790 22:50:18.017767 TX OE : NO K
6791 22:50:18.018317 All Pass.
6792 22:50:18.018657
6793 22:50:18.021046 DramC Write-DBI off
6794 22:50:18.024619 PER_BANK_REFRESH: Hybrid Mode
6795 22:50:18.025130 TX_TRACKING: ON
6796 22:50:18.034233 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6797 22:50:18.037655 [FAST_K] Save calibration result to emmc
6798 22:50:18.040719 dramc_set_vcore_voltage set vcore to 725000
6799 22:50:18.044129 Read voltage for 1600, 0
6800 22:50:18.044545 Vio18 = 0
6801 22:50:18.044873 Vcore = 725000
6802 22:50:18.047572 Vdram = 0
6803 22:50:18.047989 Vddq = 0
6804 22:50:18.048317 Vmddr = 0
6805 22:50:18.053776 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6806 22:50:18.057680 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6807 22:50:18.061060 MEM_TYPE=3, freq_sel=13
6808 22:50:18.064216 sv_algorithm_assistance_LP4_3733
6809 22:50:18.067070 ============ PULL DRAM RESETB DOWN ============
6810 22:50:18.074008 ========== PULL DRAM RESETB DOWN end =========
6811 22:50:18.077395 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6812 22:50:18.080350 ===================================
6813 22:50:18.083895 LPDDR4 DRAM CONFIGURATION
6814 22:50:18.087387 ===================================
6815 22:50:18.087901 EX_ROW_EN[0] = 0x0
6816 22:50:18.090212 EX_ROW_EN[1] = 0x0
6817 22:50:18.090895 LP4Y_EN = 0x0
6818 22:50:18.093381 WORK_FSP = 0x1
6819 22:50:18.093796 WL = 0x5
6820 22:50:18.096857 RL = 0x5
6821 22:50:18.097269 BL = 0x2
6822 22:50:18.100642 RPST = 0x0
6823 22:50:18.101055 RD_PRE = 0x0
6824 22:50:18.104005 WR_PRE = 0x1
6825 22:50:18.106753 WR_PST = 0x1
6826 22:50:18.107174 DBI_WR = 0x0
6827 22:50:18.110309 DBI_RD = 0x0
6828 22:50:18.110724 OTF = 0x1
6829 22:50:18.113475 ===================================
6830 22:50:18.116744 ===================================
6831 22:50:18.119942 ANA top config
6832 22:50:18.123832 ===================================
6833 22:50:18.124373 DLL_ASYNC_EN = 0
6834 22:50:18.126688 ALL_SLAVE_EN = 0
6835 22:50:18.129979 NEW_RANK_MODE = 1
6836 22:50:18.133924 DLL_IDLE_MODE = 1
6837 22:50:18.134480 LP45_APHY_COMB_EN = 1
6838 22:50:18.136667 TX_ODT_DIS = 0
6839 22:50:18.140191 NEW_8X_MODE = 1
6840 22:50:18.143252 ===================================
6841 22:50:18.147026 ===================================
6842 22:50:18.149653 data_rate = 3200
6843 22:50:18.153106 CKR = 1
6844 22:50:18.156464 DQ_P2S_RATIO = 8
6845 22:50:18.159558 ===================================
6846 22:50:18.160041 CA_P2S_RATIO = 8
6847 22:50:18.162950 DQ_CA_OPEN = 0
6848 22:50:18.166388 DQ_SEMI_OPEN = 0
6849 22:50:18.169893 CA_SEMI_OPEN = 0
6850 22:50:18.172700 CA_FULL_RATE = 0
6851 22:50:18.175939 DQ_CKDIV4_EN = 0
6852 22:50:18.176394 CA_CKDIV4_EN = 0
6853 22:50:18.179612 CA_PREDIV_EN = 0
6854 22:50:18.183224 PH8_DLY = 12
6855 22:50:18.186728 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6856 22:50:18.190010 DQ_AAMCK_DIV = 4
6857 22:50:18.192826 CA_AAMCK_DIV = 4
6858 22:50:18.193289 CA_ADMCK_DIV = 4
6859 22:50:18.196573 DQ_TRACK_CA_EN = 0
6860 22:50:18.199422 CA_PICK = 1600
6861 22:50:18.202858 CA_MCKIO = 1600
6862 22:50:18.206208 MCKIO_SEMI = 0
6863 22:50:18.209337 PLL_FREQ = 3068
6864 22:50:18.212947 DQ_UI_PI_RATIO = 32
6865 22:50:18.216102 CA_UI_PI_RATIO = 0
6866 22:50:18.219286 ===================================
6867 22:50:18.222551 ===================================
6868 22:50:18.223105 memory_type:LPDDR4
6869 22:50:18.225877 GP_NUM : 10
6870 22:50:18.229010 SRAM_EN : 1
6871 22:50:18.229558 MD32_EN : 0
6872 22:50:18.232525 ===================================
6873 22:50:18.235739 [ANA_INIT] >>>>>>>>>>>>>>
6874 22:50:18.239582 <<<<<< [CONFIGURE PHASE]: ANA_TX
6875 22:50:18.242350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6876 22:50:18.245793 ===================================
6877 22:50:18.249307 data_rate = 3200,PCW = 0X7600
6878 22:50:18.252348 ===================================
6879 22:50:18.255576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6880 22:50:18.258983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6881 22:50:18.265850 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6882 22:50:18.269307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6883 22:50:18.272231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6884 22:50:18.276161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6885 22:50:18.278826 [ANA_INIT] flow start
6886 22:50:18.282130 [ANA_INIT] PLL >>>>>>>>
6887 22:50:18.282588 [ANA_INIT] PLL <<<<<<<<
6888 22:50:18.285589 [ANA_INIT] MIDPI >>>>>>>>
6889 22:50:18.288816 [ANA_INIT] MIDPI <<<<<<<<
6890 22:50:18.289271 [ANA_INIT] DLL >>>>>>>>
6891 22:50:18.292363 [ANA_INIT] DLL <<<<<<<<
6892 22:50:18.295357 [ANA_INIT] flow end
6893 22:50:18.298859 ============ LP4 DIFF to SE enter ============
6894 22:50:18.301843 ============ LP4 DIFF to SE exit ============
6895 22:50:18.305266 [ANA_INIT] <<<<<<<<<<<<<
6896 22:50:18.308591 [Flow] Enable top DCM control >>>>>
6897 22:50:18.311895 [Flow] Enable top DCM control <<<<<
6898 22:50:18.315195 Enable DLL master slave shuffle
6899 22:50:18.318411 ==============================================================
6900 22:50:18.321872 Gating Mode config
6901 22:50:18.328794 ==============================================================
6902 22:50:18.329364 Config description:
6903 22:50:18.338507 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6904 22:50:18.344870 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6905 22:50:18.351442 SELPH_MODE 0: By rank 1: By Phase
6906 22:50:18.355152 ==============================================================
6907 22:50:18.357961 GAT_TRACK_EN = 1
6908 22:50:18.361275 RX_GATING_MODE = 2
6909 22:50:18.364736 RX_GATING_TRACK_MODE = 2
6910 22:50:18.367786 SELPH_MODE = 1
6911 22:50:18.371171 PICG_EARLY_EN = 1
6912 22:50:18.374390 VALID_LAT_VALUE = 1
6913 22:50:18.378127 ==============================================================
6914 22:50:18.381068 Enter into Gating configuration >>>>
6915 22:50:18.384860 Exit from Gating configuration <<<<
6916 22:50:18.387978 Enter into DVFS_PRE_config >>>>>
6917 22:50:18.401183 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6918 22:50:18.404633 Exit from DVFS_PRE_config <<<<<
6919 22:50:18.408030 Enter into PICG configuration >>>>
6920 22:50:18.408586 Exit from PICG configuration <<<<
6921 22:50:18.411291 [RX_INPUT] configuration >>>>>
6922 22:50:18.414422 [RX_INPUT] configuration <<<<<
6923 22:50:18.421354 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6924 22:50:18.424453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6925 22:50:18.431079 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6926 22:50:18.437889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6927 22:50:18.444347 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6928 22:50:18.451073 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6929 22:50:18.454478 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6930 22:50:18.457834 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6931 22:50:18.461763 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6932 22:50:18.468028 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6933 22:50:18.470837 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6934 22:50:18.474451 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6935 22:50:18.477718 ===================================
6936 22:50:18.480816 LPDDR4 DRAM CONFIGURATION
6937 22:50:18.484507 ===================================
6938 22:50:18.487521 EX_ROW_EN[0] = 0x0
6939 22:50:18.487984 EX_ROW_EN[1] = 0x0
6940 22:50:18.490893 LP4Y_EN = 0x0
6941 22:50:18.491354 WORK_FSP = 0x1
6942 22:50:18.494167 WL = 0x5
6943 22:50:18.494584 RL = 0x5
6944 22:50:18.497463 BL = 0x2
6945 22:50:18.497879 RPST = 0x0
6946 22:50:18.500551 RD_PRE = 0x0
6947 22:50:18.500968 WR_PRE = 0x1
6948 22:50:18.504064 WR_PST = 0x1
6949 22:50:18.504481 DBI_WR = 0x0
6950 22:50:18.507381 DBI_RD = 0x0
6951 22:50:18.507799 OTF = 0x1
6952 22:50:18.510795 ===================================
6953 22:50:18.517523 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6954 22:50:18.520673 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6955 22:50:18.523981 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6956 22:50:18.527762 ===================================
6957 22:50:18.530682 LPDDR4 DRAM CONFIGURATION
6958 22:50:18.533947 ===================================
6959 22:50:18.537416 EX_ROW_EN[0] = 0x10
6960 22:50:18.537920 EX_ROW_EN[1] = 0x0
6961 22:50:18.540658 LP4Y_EN = 0x0
6962 22:50:18.541136 WORK_FSP = 0x1
6963 22:50:18.543723 WL = 0x5
6964 22:50:18.544313 RL = 0x5
6965 22:50:18.546937 BL = 0x2
6966 22:50:18.547355 RPST = 0x0
6967 22:50:18.550630 RD_PRE = 0x0
6968 22:50:18.551134 WR_PRE = 0x1
6969 22:50:18.553575 WR_PST = 0x1
6970 22:50:18.554097 DBI_WR = 0x0
6971 22:50:18.556978 DBI_RD = 0x0
6972 22:50:18.557483 OTF = 0x1
6973 22:50:18.560434 ===================================
6974 22:50:18.567015 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6975 22:50:18.567431 ==
6976 22:50:18.570284 Dram Type= 6, Freq= 0, CH_0, rank 0
6977 22:50:18.576899 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6978 22:50:18.577317 ==
6979 22:50:18.577646 [Duty_Offset_Calibration]
6980 22:50:18.580199 B0:0 B1:2 CA:1
6981 22:50:18.580616
6982 22:50:18.583572 [DutyScan_Calibration_Flow] k_type=0
6983 22:50:18.592715
6984 22:50:18.593264 ==CLK 0==
6985 22:50:18.596043 Final CLK duty delay cell = 0
6986 22:50:18.599764 [0] MAX Duty = 5187%(X100), DQS PI = 24
6987 22:50:18.602862 [0] MIN Duty = 4938%(X100), DQS PI = 54
6988 22:50:18.603325 [0] AVG Duty = 5062%(X100)
6989 22:50:18.606141
6990 22:50:18.609460 CH0 CLK Duty spec in!! Max-Min= 249%
6991 22:50:18.612663 [DutyScan_Calibration_Flow] ====Done====
6992 22:50:18.613121
6993 22:50:18.615922 [DutyScan_Calibration_Flow] k_type=1
6994 22:50:18.633095
6995 22:50:18.633627 ==DQS 0 ==
6996 22:50:18.636080 Final DQS duty delay cell = 0
6997 22:50:18.639161 [0] MAX Duty = 5156%(X100), DQS PI = 34
6998 22:50:18.643061 [0] MIN Duty = 5000%(X100), DQS PI = 10
6999 22:50:18.645905 [0] AVG Duty = 5078%(X100)
7000 22:50:18.646369
7001 22:50:18.646697 ==DQS 1 ==
7002 22:50:18.649558 Final DQS duty delay cell = 0
7003 22:50:18.652577 [0] MAX Duty = 5031%(X100), DQS PI = 2
7004 22:50:18.655917 [0] MIN Duty = 4876%(X100), DQS PI = 16
7005 22:50:18.659299 [0] AVG Duty = 4953%(X100)
7006 22:50:18.659751
7007 22:50:18.662299 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7008 22:50:18.662719
7009 22:50:18.665544 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7010 22:50:18.669314 [DutyScan_Calibration_Flow] ====Done====
7011 22:50:18.669841
7012 22:50:18.672178 [DutyScan_Calibration_Flow] k_type=3
7013 22:50:18.690052
7014 22:50:18.690556 ==DQM 0 ==
7015 22:50:18.693144 Final DQM duty delay cell = 0
7016 22:50:18.696333 [0] MAX Duty = 5187%(X100), DQS PI = 22
7017 22:50:18.699937 [0] MIN Duty = 4907%(X100), DQS PI = 42
7018 22:50:18.703308 [0] AVG Duty = 5047%(X100)
7019 22:50:18.703723
7020 22:50:18.704045 ==DQM 1 ==
7021 22:50:18.706761 Final DQM duty delay cell = 0
7022 22:50:18.709926 [0] MAX Duty = 5031%(X100), DQS PI = 50
7023 22:50:18.713254 [0] MIN Duty = 4782%(X100), DQS PI = 14
7024 22:50:18.716638 [0] AVG Duty = 4906%(X100)
7025 22:50:18.717182
7026 22:50:18.720174 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7027 22:50:18.720681
7028 22:50:18.723474 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7029 22:50:18.726508 [DutyScan_Calibration_Flow] ====Done====
7030 22:50:18.727157
7031 22:50:18.729599 [DutyScan_Calibration_Flow] k_type=2
7032 22:50:18.746401
7033 22:50:18.746910 ==DQ 0 ==
7034 22:50:18.749930 Final DQ duty delay cell = 0
7035 22:50:18.753328 [0] MAX Duty = 5218%(X100), DQS PI = 18
7036 22:50:18.756465 [0] MIN Duty = 4938%(X100), DQS PI = 56
7037 22:50:18.757017 [0] AVG Duty = 5078%(X100)
7038 22:50:18.759540
7039 22:50:18.759997 ==DQ 1 ==
7040 22:50:18.763322 Final DQ duty delay cell = -4
7041 22:50:18.766495 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7042 22:50:18.769853 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7043 22:50:18.773080 [-4] AVG Duty = 4953%(X100)
7044 22:50:18.773560
7045 22:50:18.776415 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7046 22:50:18.776877
7047 22:50:18.779858 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7048 22:50:18.783086 [DutyScan_Calibration_Flow] ====Done====
7049 22:50:18.783504 ==
7050 22:50:18.786628 Dram Type= 6, Freq= 0, CH_1, rank 0
7051 22:50:18.790121 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7052 22:50:18.790701 ==
7053 22:50:18.793016 [Duty_Offset_Calibration]
7054 22:50:18.793478 B0:0 B1:5 CA:-5
7055 22:50:18.793841
7056 22:50:18.796028 [DutyScan_Calibration_Flow] k_type=0
7057 22:50:18.807614
7058 22:50:18.808175 ==CLK 0==
7059 22:50:18.810261 Final CLK duty delay cell = 0
7060 22:50:18.814295 [0] MAX Duty = 5156%(X100), DQS PI = 18
7061 22:50:18.817071 [0] MIN Duty = 4906%(X100), DQS PI = 50
7062 22:50:18.817627 [0] AVG Duty = 5031%(X100)
7063 22:50:18.820487
7064 22:50:18.823528 CH1 CLK Duty spec in!! Max-Min= 250%
7065 22:50:18.826938 [DutyScan_Calibration_Flow] ====Done====
7066 22:50:18.827520
7067 22:50:18.830338 [DutyScan_Calibration_Flow] k_type=1
7068 22:50:18.846383
7069 22:50:18.847111 ==DQS 0 ==
7070 22:50:18.849189 Final DQS duty delay cell = 0
7071 22:50:18.852484 [0] MAX Duty = 5156%(X100), DQS PI = 18
7072 22:50:18.856362 [0] MIN Duty = 4876%(X100), DQS PI = 44
7073 22:50:18.859658 [0] AVG Duty = 5016%(X100)
7074 22:50:18.860200
7075 22:50:18.860581 ==DQS 1 ==
7076 22:50:18.862344 Final DQS duty delay cell = -4
7077 22:50:18.865859 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7078 22:50:18.869146 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7079 22:50:18.872650 [-4] AVG Duty = 4922%(X100)
7080 22:50:18.873111
7081 22:50:18.876183 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7082 22:50:18.876755
7083 22:50:18.879179 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7084 22:50:18.882393 [DutyScan_Calibration_Flow] ====Done====
7085 22:50:18.882856
7086 22:50:18.885733 [DutyScan_Calibration_Flow] k_type=3
7087 22:50:18.901505
7088 22:50:18.902021 ==DQM 0 ==
7089 22:50:18.905203 Final DQM duty delay cell = -4
7090 22:50:18.908073 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7091 22:50:18.911433 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7092 22:50:18.914751 [-4] AVG Duty = 4937%(X100)
7093 22:50:18.915166
7094 22:50:18.915490 ==DQM 1 ==
7095 22:50:18.918309 Final DQM duty delay cell = -4
7096 22:50:18.921507 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7097 22:50:18.925058 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7098 22:50:18.928453 [-4] AVG Duty = 4984%(X100)
7099 22:50:18.929128
7100 22:50:18.931326 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7101 22:50:18.931746
7102 22:50:18.934585 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7103 22:50:18.938332 [DutyScan_Calibration_Flow] ====Done====
7104 22:50:18.938845
7105 22:50:18.941331 [DutyScan_Calibration_Flow] k_type=2
7106 22:50:18.959320
7107 22:50:18.959863 ==DQ 0 ==
7108 22:50:18.962433 Final DQ duty delay cell = 0
7109 22:50:18.965750 [0] MAX Duty = 5093%(X100), DQS PI = 18
7110 22:50:18.969257 [0] MIN Duty = 4938%(X100), DQS PI = 46
7111 22:50:18.969786 [0] AVG Duty = 5015%(X100)
7112 22:50:18.972497
7113 22:50:18.972949 ==DQ 1 ==
7114 22:50:18.975722 Final DQ duty delay cell = 0
7115 22:50:18.979048 [0] MAX Duty = 5031%(X100), DQS PI = 4
7116 22:50:18.982542 [0] MIN Duty = 4907%(X100), DQS PI = 22
7117 22:50:18.983004 [0] AVG Duty = 4969%(X100)
7118 22:50:18.983368
7119 22:50:18.985799 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7120 22:50:18.989061
7121 22:50:18.992499 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7122 22:50:18.995713 [DutyScan_Calibration_Flow] ====Done====
7123 22:50:18.998929 nWR fixed to 30
7124 22:50:18.999388 [ModeRegInit_LP4] CH0 RK0
7125 22:50:19.002391 [ModeRegInit_LP4] CH0 RK1
7126 22:50:19.005723 [ModeRegInit_LP4] CH1 RK0
7127 22:50:19.008780 [ModeRegInit_LP4] CH1 RK1
7128 22:50:19.009197 match AC timing 4
7129 22:50:19.015575 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7130 22:50:19.018728 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7131 22:50:19.022853 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7132 22:50:19.028497 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7133 22:50:19.032347 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7134 22:50:19.032902 [MiockJmeterHQA]
7135 22:50:19.033357
7136 22:50:19.035525 [DramcMiockJmeter] u1RxGatingPI = 0
7137 22:50:19.038593 0 : 4366, 4140
7138 22:50:19.039061 4 : 4253, 4026
7139 22:50:19.041588 8 : 4363, 4138
7140 22:50:19.042080 12 : 4363, 4138
7141 22:50:19.044871 16 : 4252, 4026
7142 22:50:19.045337 20 : 4363, 4137
7143 22:50:19.045701 24 : 4252, 4027
7144 22:50:19.048418 28 : 4253, 4027
7145 22:50:19.048883 32 : 4252, 4027
7146 22:50:19.051841 36 : 4255, 4029
7147 22:50:19.052260 40 : 4363, 4138
7148 22:50:19.054988 44 : 4253, 4026
7149 22:50:19.055410 48 : 4363, 4138
7150 22:50:19.055742 52 : 4253, 4029
7151 22:50:19.058265 56 : 4252, 4027
7152 22:50:19.058684 60 : 4250, 4027
7153 22:50:19.062427 64 : 4360, 4138
7154 22:50:19.062947 68 : 4250, 4027
7155 22:50:19.065575 72 : 4360, 4138
7156 22:50:19.066127 76 : 4250, 4027
7157 22:50:19.068755 80 : 4250, 4027
7158 22:50:19.069291 84 : 4250, 4026
7159 22:50:19.069632 88 : 4252, 4029
7160 22:50:19.071709 92 : 4250, 4027
7161 22:50:19.072133 96 : 4249, 4027
7162 22:50:19.075123 100 : 4363, 2032
7163 22:50:19.075547 104 : 4252, 0
7164 22:50:19.078524 108 : 4250, 0
7165 22:50:19.079033 112 : 4360, 0
7166 22:50:19.079366 116 : 4361, 0
7167 22:50:19.081353 120 : 4363, 0
7168 22:50:19.081777 124 : 4250, 0
7169 22:50:19.084890 128 : 4250, 0
7170 22:50:19.085309 132 : 4250, 0
7171 22:50:19.085640 136 : 4252, 0
7172 22:50:19.088042 140 : 4250, 0
7173 22:50:19.088539 144 : 4250, 0
7174 22:50:19.088876 148 : 4252, 0
7175 22:50:19.091542 152 : 4361, 0
7176 22:50:19.091964 156 : 4250, 0
7177 22:50:19.094773 160 : 4250, 0
7178 22:50:19.095194 164 : 4250, 0
7179 22:50:19.095526 168 : 4361, 0
7180 22:50:19.098064 172 : 4360, 0
7181 22:50:19.098505 176 : 4249, 0
7182 22:50:19.101547 180 : 4250, 0
7183 22:50:19.101967 184 : 4250, 0
7184 22:50:19.102345 188 : 4252, 0
7185 22:50:19.105320 192 : 4252, 0
7186 22:50:19.105741 196 : 4250, 0
7187 22:50:19.107962 200 : 4252, 0
7188 22:50:19.108384 204 : 4360, 0
7189 22:50:19.108714 208 : 4250, 0
7190 22:50:19.111120 212 : 4250, 0
7191 22:50:19.111539 216 : 4360, 0
7192 22:50:19.114500 220 : 4361, 702
7193 22:50:19.114922 224 : 4249, 4009
7194 22:50:19.115253 228 : 4250, 4027
7195 22:50:19.117867 232 : 4250, 4027
7196 22:50:19.118400 236 : 4250, 4027
7197 22:50:19.121206 240 : 4250, 4027
7198 22:50:19.121715 244 : 4252, 4029
7199 22:50:19.124680 248 : 4250, 4027
7200 22:50:19.125177 252 : 4361, 4137
7201 22:50:19.127871 256 : 4360, 4138
7202 22:50:19.128292 260 : 4250, 4027
7203 22:50:19.131070 264 : 4363, 4140
7204 22:50:19.131579 268 : 4250, 4027
7205 22:50:19.134698 272 : 4250, 4027
7206 22:50:19.135198 276 : 4250, 4027
7207 22:50:19.137635 280 : 4252, 4029
7208 22:50:19.138089 284 : 4250, 4027
7209 22:50:19.141350 288 : 4250, 4027
7210 22:50:19.141868 292 : 4252, 4027
7211 22:50:19.142275 296 : 4252, 4029
7212 22:50:19.144445 300 : 4250, 4026
7213 22:50:19.144865 304 : 4361, 4137
7214 22:50:19.147773 308 : 4360, 4138
7215 22:50:19.148199 312 : 4250, 4027
7216 22:50:19.151617 316 : 4363, 4140
7217 22:50:19.152153 320 : 4250, 4027
7218 22:50:19.154600 324 : 4250, 4027
7219 22:50:19.155021 328 : 4249, 4027
7220 22:50:19.157982 332 : 4252, 4029
7221 22:50:19.158434 336 : 4250, 3709
7222 22:50:19.160923 340 : 4250, 1435
7223 22:50:19.161342
7224 22:50:19.161741 MIOCK jitter meter ch=0
7225 22:50:19.162099
7226 22:50:19.164206 1T = (340-100) = 240 dly cells
7227 22:50:19.171123 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7228 22:50:19.171621 ==
7229 22:50:19.174237 Dram Type= 6, Freq= 0, CH_0, rank 0
7230 22:50:19.177514 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7231 22:50:19.177935 ==
7232 22:50:19.184159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7233 22:50:19.187270 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7234 22:50:19.190750 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7235 22:50:19.197192 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7236 22:50:19.206321 [CA 0] Center 42 (12~73) winsize 62
7237 22:50:19.210396 [CA 1] Center 42 (12~73) winsize 62
7238 22:50:19.213107 [CA 2] Center 39 (9~69) winsize 61
7239 22:50:19.216568 [CA 3] Center 38 (9~68) winsize 60
7240 22:50:19.219824 [CA 4] Center 37 (7~67) winsize 61
7241 22:50:19.223241 [CA 5] Center 36 (6~66) winsize 61
7242 22:50:19.223735
7243 22:50:19.226304 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7244 22:50:19.226723
7245 22:50:19.230098 [CATrainingPosCal] consider 1 rank data
7246 22:50:19.233002 u2DelayCellTimex100 = 271/100 ps
7247 22:50:19.236482 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7248 22:50:19.243168 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7249 22:50:19.246544 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7250 22:50:19.249861 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7251 22:50:19.252860 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7252 22:50:19.256301 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7253 22:50:19.256719
7254 22:50:19.259777 CA PerBit enable=1, Macro0, CA PI delay=36
7255 22:50:19.260307
7256 22:50:19.263475 [CBTSetCACLKResult] CA Dly = 36
7257 22:50:19.266426 CS Dly: 10 (0~41)
7258 22:50:19.269464 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7259 22:50:19.272767 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7260 22:50:19.273184 ==
7261 22:50:19.276034 Dram Type= 6, Freq= 0, CH_0, rank 1
7262 22:50:19.279616 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7263 22:50:19.282732 ==
7264 22:50:19.286091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7265 22:50:19.289657 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7266 22:50:19.296014 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7267 22:50:19.302411 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7268 22:50:19.309208 [CA 0] Center 42 (12~73) winsize 62
7269 22:50:19.312654 [CA 1] Center 42 (12~73) winsize 62
7270 22:50:19.316277 [CA 2] Center 38 (9~68) winsize 60
7271 22:50:19.319493 [CA 3] Center 38 (8~68) winsize 61
7272 22:50:19.322903 [CA 4] Center 36 (6~66) winsize 61
7273 22:50:19.325909 [CA 5] Center 36 (6~66) winsize 61
7274 22:50:19.326472
7275 22:50:19.329338 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7276 22:50:19.329815
7277 22:50:19.332428 [CATrainingPosCal] consider 2 rank data
7278 22:50:19.336165 u2DelayCellTimex100 = 271/100 ps
7279 22:50:19.342392 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7280 22:50:19.346049 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7281 22:50:19.349018 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7282 22:50:19.353109 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7283 22:50:19.356100 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7284 22:50:19.358817 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7285 22:50:19.359238
7286 22:50:19.362098 CA PerBit enable=1, Macro0, CA PI delay=36
7287 22:50:19.362568
7288 22:50:19.365314 [CBTSetCACLKResult] CA Dly = 36
7289 22:50:19.369098 CS Dly: 10 (0~42)
7290 22:50:19.371873 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7291 22:50:19.375149 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7292 22:50:19.375619
7293 22:50:19.378510 ----->DramcWriteLeveling(PI) begin...
7294 22:50:19.378927 ==
7295 22:50:19.382000 Dram Type= 6, Freq= 0, CH_0, rank 0
7296 22:50:19.388387 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7297 22:50:19.388811 ==
7298 22:50:19.391742 Write leveling (Byte 0): 30 => 30
7299 22:50:19.395057 Write leveling (Byte 1): 27 => 27
7300 22:50:19.395448 DramcWriteLeveling(PI) end<-----
7301 22:50:19.395766
7302 22:50:19.398647 ==
7303 22:50:19.401871 Dram Type= 6, Freq= 0, CH_0, rank 0
7304 22:50:19.404944 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7305 22:50:19.405526 ==
7306 22:50:19.408306 [Gating] SW mode calibration
7307 22:50:19.414906 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7308 22:50:19.418577 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7309 22:50:19.424898 0 12 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7310 22:50:19.428230 0 12 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
7311 22:50:19.431705 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7312 22:50:19.438413 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7313 22:50:19.441505 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7314 22:50:19.444905 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7315 22:50:19.451279 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7316 22:50:19.454931 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7317 22:50:19.458365 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7318 22:50:19.464968 0 13 4 | B1->B0 | 3030 2424 | 1 0 | (0 1) (0 0)
7319 22:50:19.468265 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7320 22:50:19.471497 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7321 22:50:19.478123 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7322 22:50:19.481389 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7323 22:50:19.484609 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7324 22:50:19.491490 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7325 22:50:19.494595 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7326 22:50:19.497850 0 14 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7327 22:50:19.504973 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7328 22:50:19.507851 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7329 22:50:19.511359 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7330 22:50:19.517694 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7331 22:50:19.521255 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7332 22:50:19.524337 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7333 22:50:19.530953 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7334 22:50:19.534400 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7335 22:50:19.537903 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7336 22:50:19.544618 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7337 22:50:19.547523 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7338 22:50:19.551057 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 22:50:19.554532 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 22:50:19.561235 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 22:50:19.564612 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 22:50:19.567845 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 22:50:19.574319 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 22:50:19.577776 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 22:50:19.580583 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 22:50:19.587817 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 22:50:19.590584 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 22:50:19.593851 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7349 22:50:19.600652 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7350 22:50:19.604218 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7351 22:50:19.607480 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7352 22:50:19.610555 Total UI for P1: 0, mck2ui 16
7353 22:50:19.613778 best dqsien dly found for B0: ( 1, 1, 0)
7354 22:50:19.620241 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7355 22:50:19.620785 Total UI for P1: 0, mck2ui 16
7356 22:50:19.627186 best dqsien dly found for B1: ( 1, 1, 6)
7357 22:50:19.630251 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7358 22:50:19.633514 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7359 22:50:19.633972
7360 22:50:19.636958 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7361 22:50:19.639860 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7362 22:50:19.643292 [Gating] SW calibration Done
7363 22:50:19.643530 ==
7364 22:50:19.646728 Dram Type= 6, Freq= 0, CH_0, rank 0
7365 22:50:19.649633 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7366 22:50:19.649824 ==
7367 22:50:19.653123 RX Vref Scan: 0
7368 22:50:19.653307
7369 22:50:19.653430 RX Vref 0 -> 0, step: 1
7370 22:50:19.653545
7371 22:50:19.656427 RX Delay 0 -> 252, step: 8
7372 22:50:19.659871 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7373 22:50:19.666099 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7374 22:50:19.670053 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7375 22:50:19.672802 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7376 22:50:19.676188 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7377 22:50:19.679787 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7378 22:50:19.686097 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7379 22:50:19.689314 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7380 22:50:19.692895 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7381 22:50:19.696015 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7382 22:50:19.699593 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7383 22:50:19.706181 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7384 22:50:19.709746 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7385 22:50:19.712953 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7386 22:50:19.716273 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7387 22:50:19.723171 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7388 22:50:19.723587 ==
7389 22:50:19.726049 Dram Type= 6, Freq= 0, CH_0, rank 0
7390 22:50:19.730076 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7391 22:50:19.730596 ==
7392 22:50:19.730927 DQS Delay:
7393 22:50:19.732718 DQS0 = 0, DQS1 = 0
7394 22:50:19.733132 DQM Delay:
7395 22:50:19.736186 DQM0 = 129, DQM1 = 124
7396 22:50:19.736619 DQ Delay:
7397 22:50:19.739893 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7398 22:50:19.742948 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =135
7399 22:50:19.746414 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7400 22:50:19.749600 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7401 22:50:19.750020
7402 22:50:19.750407
7403 22:50:19.750836 ==
7404 22:50:19.752578 Dram Type= 6, Freq= 0, CH_0, rank 0
7405 22:50:19.759444 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7406 22:50:19.760041 ==
7407 22:50:19.760381
7408 22:50:19.760776
7409 22:50:19.762505 TX Vref Scan disable
7410 22:50:19.763007 == TX Byte 0 ==
7411 22:50:19.765908 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7412 22:50:19.772618 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7413 22:50:19.773239 == TX Byte 1 ==
7414 22:50:19.776390 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7415 22:50:19.782483 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7416 22:50:19.783029 ==
7417 22:50:19.786098 Dram Type= 6, Freq= 0, CH_0, rank 0
7418 22:50:19.789150 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7419 22:50:19.789566 ==
7420 22:50:19.803274
7421 22:50:19.806404 TX Vref early break, caculate TX vref
7422 22:50:19.809789 TX Vref=16, minBit 8, minWin=22, winSum=373
7423 22:50:19.813018 TX Vref=18, minBit 8, minWin=22, winSum=379
7424 22:50:19.816346 TX Vref=20, minBit 10, minWin=23, winSum=390
7425 22:50:19.820077 TX Vref=22, minBit 4, minWin=24, winSum=403
7426 22:50:19.823003 TX Vref=24, minBit 8, minWin=24, winSum=406
7427 22:50:19.829831 TX Vref=26, minBit 11, minWin=24, winSum=409
7428 22:50:19.832928 TX Vref=28, minBit 8, minWin=25, winSum=416
7429 22:50:19.836161 TX Vref=30, minBit 0, minWin=25, winSum=407
7430 22:50:19.840082 TX Vref=32, minBit 1, minWin=24, winSum=403
7431 22:50:19.842967 TX Vref=34, minBit 2, minWin=24, winSum=395
7432 22:50:19.846553 TX Vref=36, minBit 3, minWin=23, winSum=386
7433 22:50:19.853223 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 28
7434 22:50:19.853753
7435 22:50:19.856862 Final TX Range 0 Vref 28
7436 22:50:19.857383
7437 22:50:19.857716 ==
7438 22:50:19.859659 Dram Type= 6, Freq= 0, CH_0, rank 0
7439 22:50:19.862869 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7440 22:50:19.863287 ==
7441 22:50:19.863616
7442 22:50:19.866159
7443 22:50:19.866570 TX Vref Scan disable
7444 22:50:19.873223 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7445 22:50:19.873637 == TX Byte 0 ==
7446 22:50:19.875916 u2DelayCellOfst[0]=14 cells (4 PI)
7447 22:50:19.879418 u2DelayCellOfst[1]=18 cells (5 PI)
7448 22:50:19.882680 u2DelayCellOfst[2]=14 cells (4 PI)
7449 22:50:19.886071 u2DelayCellOfst[3]=14 cells (4 PI)
7450 22:50:19.889921 u2DelayCellOfst[4]=7 cells (2 PI)
7451 22:50:19.892414 u2DelayCellOfst[5]=0 cells (0 PI)
7452 22:50:19.895834 u2DelayCellOfst[6]=21 cells (6 PI)
7453 22:50:19.899179 u2DelayCellOfst[7]=18 cells (5 PI)
7454 22:50:19.902550 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7455 22:50:19.905697 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7456 22:50:19.909099 == TX Byte 1 ==
7457 22:50:19.912268 u2DelayCellOfst[8]=0 cells (0 PI)
7458 22:50:19.915808 u2DelayCellOfst[9]=0 cells (0 PI)
7459 22:50:19.919366 u2DelayCellOfst[10]=7 cells (2 PI)
7460 22:50:19.922260 u2DelayCellOfst[11]=0 cells (0 PI)
7461 22:50:19.925774 u2DelayCellOfst[12]=14 cells (4 PI)
7462 22:50:19.926279 u2DelayCellOfst[13]=10 cells (3 PI)
7463 22:50:19.929671 u2DelayCellOfst[14]=14 cells (4 PI)
7464 22:50:19.932466 u2DelayCellOfst[15]=10 cells (3 PI)
7465 22:50:19.938848 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7466 22:50:19.942299 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7467 22:50:19.942783 DramC Write-DBI on
7468 22:50:19.946212 ==
7469 22:50:19.946625 Dram Type= 6, Freq= 0, CH_0, rank 0
7470 22:50:19.952989 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7471 22:50:19.953504 ==
7472 22:50:19.953833
7473 22:50:19.954161
7474 22:50:19.955452 TX Vref Scan disable
7475 22:50:19.955868 == TX Byte 0 ==
7476 22:50:19.962238 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7477 22:50:19.962736 == TX Byte 1 ==
7478 22:50:19.965466 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7479 22:50:19.968734 DramC Write-DBI off
7480 22:50:19.969242
7481 22:50:19.969566 [DATLAT]
7482 22:50:19.971849 Freq=1600, CH0 RK0
7483 22:50:19.972261
7484 22:50:19.972583 DATLAT Default: 0xf
7485 22:50:19.975411 0, 0xFFFF, sum = 0
7486 22:50:19.975831 1, 0xFFFF, sum = 0
7487 22:50:19.978815 2, 0xFFFF, sum = 0
7488 22:50:19.979330 3, 0xFFFF, sum = 0
7489 22:50:19.981760 4, 0xFFFF, sum = 0
7490 22:50:19.982238 5, 0xFFFF, sum = 0
7491 22:50:19.985045 6, 0xFFFF, sum = 0
7492 22:50:19.988364 7, 0xFFFF, sum = 0
7493 22:50:19.988784 8, 0xFFFF, sum = 0
7494 22:50:19.991975 9, 0xFFFF, sum = 0
7495 22:50:19.992488 10, 0xFFFF, sum = 0
7496 22:50:19.994887 11, 0xFFFF, sum = 0
7497 22:50:19.995306 12, 0x8FFF, sum = 0
7498 22:50:19.998559 13, 0x0, sum = 1
7499 22:50:19.999085 14, 0x0, sum = 2
7500 22:50:20.001580 15, 0x0, sum = 3
7501 22:50:20.002213 16, 0x0, sum = 4
7502 22:50:20.002562 best_step = 14
7503 22:50:20.005360
7504 22:50:20.005771 ==
7505 22:50:20.008196 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 22:50:20.011998 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7507 22:50:20.012510 ==
7508 22:50:20.012837 RX Vref Scan: 1
7509 22:50:20.013142
7510 22:50:20.015144 Set Vref Range= 24 -> 127
7511 22:50:20.015654
7512 22:50:20.018256 RX Vref 24 -> 127, step: 1
7513 22:50:20.018672
7514 22:50:20.021599 RX Delay 11 -> 252, step: 4
7515 22:50:20.022160
7516 22:50:20.025271 Set Vref, RX VrefLevel [Byte0]: 24
7517 22:50:20.028124 [Byte1]: 24
7518 22:50:20.028541
7519 22:50:20.031635 Set Vref, RX VrefLevel [Byte0]: 25
7520 22:50:20.034786 [Byte1]: 25
7521 22:50:20.035297
7522 22:50:20.038315 Set Vref, RX VrefLevel [Byte0]: 26
7523 22:50:20.041635 [Byte1]: 26
7524 22:50:20.045358
7525 22:50:20.045874 Set Vref, RX VrefLevel [Byte0]: 27
7526 22:50:20.049010 [Byte1]: 27
7527 22:50:20.052938
7528 22:50:20.053451 Set Vref, RX VrefLevel [Byte0]: 28
7529 22:50:20.056391 [Byte1]: 28
7530 22:50:20.060547
7531 22:50:20.061058 Set Vref, RX VrefLevel [Byte0]: 29
7532 22:50:20.063693 [Byte1]: 29
7533 22:50:20.068051
7534 22:50:20.068561 Set Vref, RX VrefLevel [Byte0]: 30
7535 22:50:20.071640 [Byte1]: 30
7536 22:50:20.075743
7537 22:50:20.076301 Set Vref, RX VrefLevel [Byte0]: 31
7538 22:50:20.078799 [Byte1]: 31
7539 22:50:20.083607
7540 22:50:20.084118 Set Vref, RX VrefLevel [Byte0]: 32
7541 22:50:20.086440 [Byte1]: 32
7542 22:50:20.091286
7543 22:50:20.094315 Set Vref, RX VrefLevel [Byte0]: 33
7544 22:50:20.094732 [Byte1]: 33
7545 22:50:20.098694
7546 22:50:20.099280 Set Vref, RX VrefLevel [Byte0]: 34
7547 22:50:20.101996 [Byte1]: 34
7548 22:50:20.106269
7549 22:50:20.106807 Set Vref, RX VrefLevel [Byte0]: 35
7550 22:50:20.109213 [Byte1]: 35
7551 22:50:20.114120
7552 22:50:20.114695 Set Vref, RX VrefLevel [Byte0]: 36
7553 22:50:20.117344 [Byte1]: 36
7554 22:50:20.121750
7555 22:50:20.122403 Set Vref, RX VrefLevel [Byte0]: 37
7556 22:50:20.124522 [Byte1]: 37
7557 22:50:20.129161
7558 22:50:20.129636 Set Vref, RX VrefLevel [Byte0]: 38
7559 22:50:20.132272 [Byte1]: 38
7560 22:50:20.136612
7561 22:50:20.137088 Set Vref, RX VrefLevel [Byte0]: 39
7562 22:50:20.140147 [Byte1]: 39
7563 22:50:20.144353
7564 22:50:20.144926 Set Vref, RX VrefLevel [Byte0]: 40
7565 22:50:20.147449 [Byte1]: 40
7566 22:50:20.151898
7567 22:50:20.152459 Set Vref, RX VrefLevel [Byte0]: 41
7568 22:50:20.155047 [Byte1]: 41
7569 22:50:20.159778
7570 22:50:20.160342 Set Vref, RX VrefLevel [Byte0]: 42
7571 22:50:20.162702 [Byte1]: 42
7572 22:50:20.167360
7573 22:50:20.167922 Set Vref, RX VrefLevel [Byte0]: 43
7574 22:50:20.170678 [Byte1]: 43
7575 22:50:20.174625
7576 22:50:20.175106 Set Vref, RX VrefLevel [Byte0]: 44
7577 22:50:20.177859 [Byte1]: 44
7578 22:50:20.182861
7579 22:50:20.183575 Set Vref, RX VrefLevel [Byte0]: 45
7580 22:50:20.185897 [Byte1]: 45
7581 22:50:20.190696
7582 22:50:20.191272 Set Vref, RX VrefLevel [Byte0]: 46
7583 22:50:20.193283 [Byte1]: 46
7584 22:50:20.197387
7585 22:50:20.197858 Set Vref, RX VrefLevel [Byte0]: 47
7586 22:50:20.201043 [Byte1]: 47
7587 22:50:20.204976
7588 22:50:20.205456 Set Vref, RX VrefLevel [Byte0]: 48
7589 22:50:20.208872 [Byte1]: 48
7590 22:50:20.212922
7591 22:50:20.213511 Set Vref, RX VrefLevel [Byte0]: 49
7592 22:50:20.216387 [Byte1]: 49
7593 22:50:20.220456
7594 22:50:20.221032 Set Vref, RX VrefLevel [Byte0]: 50
7595 22:50:20.223758 [Byte1]: 50
7596 22:50:20.228036
7597 22:50:20.228614 Set Vref, RX VrefLevel [Byte0]: 51
7598 22:50:20.231058 [Byte1]: 51
7599 22:50:20.235448
7600 22:50:20.235920 Set Vref, RX VrefLevel [Byte0]: 52
7601 22:50:20.239067 [Byte1]: 52
7602 22:50:20.243320
7603 22:50:20.243900 Set Vref, RX VrefLevel [Byte0]: 53
7604 22:50:20.246696 [Byte1]: 53
7605 22:50:20.250859
7606 22:50:20.251437 Set Vref, RX VrefLevel [Byte0]: 54
7607 22:50:20.254206 [Byte1]: 54
7608 22:50:20.258639
7609 22:50:20.259219 Set Vref, RX VrefLevel [Byte0]: 55
7610 22:50:20.261813 [Byte1]: 55
7611 22:50:20.266492
7612 22:50:20.267071 Set Vref, RX VrefLevel [Byte0]: 56
7613 22:50:20.269830 [Byte1]: 56
7614 22:50:20.273559
7615 22:50:20.274263 Set Vref, RX VrefLevel [Byte0]: 57
7616 22:50:20.277066 [Byte1]: 57
7617 22:50:20.281450
7618 22:50:20.282079 Set Vref, RX VrefLevel [Byte0]: 58
7619 22:50:20.284481 [Byte1]: 58
7620 22:50:20.289260
7621 22:50:20.289835 Set Vref, RX VrefLevel [Byte0]: 59
7622 22:50:20.292395 [Byte1]: 59
7623 22:50:20.296789
7624 22:50:20.297366 Set Vref, RX VrefLevel [Byte0]: 60
7625 22:50:20.300032 [Byte1]: 60
7626 22:50:20.304069
7627 22:50:20.304545 Set Vref, RX VrefLevel [Byte0]: 61
7628 22:50:20.307490 [Byte1]: 61
7629 22:50:20.312200
7630 22:50:20.312778 Set Vref, RX VrefLevel [Byte0]: 62
7631 22:50:20.315036 [Byte1]: 62
7632 22:50:20.319325
7633 22:50:20.319799 Set Vref, RX VrefLevel [Byte0]: 63
7634 22:50:20.325896 [Byte1]: 63
7635 22:50:20.326486
7636 22:50:20.329142 Set Vref, RX VrefLevel [Byte0]: 64
7637 22:50:20.332727 [Byte1]: 64
7638 22:50:20.333265
7639 22:50:20.335527 Set Vref, RX VrefLevel [Byte0]: 65
7640 22:50:20.339122 [Byte1]: 65
7641 22:50:20.339657
7642 22:50:20.342499 Set Vref, RX VrefLevel [Byte0]: 66
7643 22:50:20.346412 [Byte1]: 66
7644 22:50:20.349949
7645 22:50:20.350534 Set Vref, RX VrefLevel [Byte0]: 67
7646 22:50:20.352989 [Byte1]: 67
7647 22:50:20.357647
7648 22:50:20.358231 Set Vref, RX VrefLevel [Byte0]: 68
7649 22:50:20.360668 [Byte1]: 68
7650 22:50:20.365126
7651 22:50:20.365663 Set Vref, RX VrefLevel [Byte0]: 69
7652 22:50:20.368330 [Byte1]: 69
7653 22:50:20.372770
7654 22:50:20.373307 Set Vref, RX VrefLevel [Byte0]: 70
7655 22:50:20.376185 [Byte1]: 70
7656 22:50:20.380242
7657 22:50:20.380781 Set Vref, RX VrefLevel [Byte0]: 71
7658 22:50:20.383315 [Byte1]: 71
7659 22:50:20.387933
7660 22:50:20.388363 Final RX Vref Byte 0 = 54 to rank0
7661 22:50:20.390913 Final RX Vref Byte 1 = 56 to rank0
7662 22:50:20.394726 Final RX Vref Byte 0 = 54 to rank1
7663 22:50:20.398014 Final RX Vref Byte 1 = 56 to rank1==
7664 22:50:20.401041 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 22:50:20.407717 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7666 22:50:20.408263 ==
7667 22:50:20.408709 DQS Delay:
7668 22:50:20.409120 DQS0 = 0, DQS1 = 0
7669 22:50:20.411252 DQM Delay:
7670 22:50:20.411785 DQM0 = 126, DQM1 = 120
7671 22:50:20.414153 DQ Delay:
7672 22:50:20.417585 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7673 22:50:20.421015 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7674 22:50:20.424663 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7675 22:50:20.427914 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7676 22:50:20.428482
7677 22:50:20.428820
7678 22:50:20.429122
7679 22:50:20.430850 [DramC_TX_OE_Calibration] TA2
7680 22:50:20.434468 Original DQ_B0 (3 6) =30, OEN = 27
7681 22:50:20.437674 Original DQ_B1 (3 6) =30, OEN = 27
7682 22:50:20.440940 24, 0x0, End_B0=24 End_B1=24
7683 22:50:20.441500 25, 0x0, End_B0=25 End_B1=25
7684 22:50:20.444891 26, 0x0, End_B0=26 End_B1=26
7685 22:50:20.447628 27, 0x0, End_B0=27 End_B1=27
7686 22:50:20.451077 28, 0x0, End_B0=28 End_B1=28
7687 22:50:20.451544 29, 0x0, End_B0=29 End_B1=29
7688 22:50:20.454091 30, 0x0, End_B0=30 End_B1=30
7689 22:50:20.457746 31, 0x4141, End_B0=30 End_B1=30
7690 22:50:20.461068 Byte0 end_step=30 best_step=27
7691 22:50:20.464109 Byte1 end_step=30 best_step=27
7692 22:50:20.467866 Byte0 TX OE(2T, 0.5T) = (3, 3)
7693 22:50:20.470613 Byte1 TX OE(2T, 0.5T) = (3, 3)
7694 22:50:20.471070
7695 22:50:20.471425
7696 22:50:20.477486 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7697 22:50:20.481225 CH0 RK0: MR19=303, MR18=1C1C
7698 22:50:20.487513 CH0_RK0: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7699 22:50:20.488071
7700 22:50:20.490906 ----->DramcWriteLeveling(PI) begin...
7701 22:50:20.491467 ==
7702 22:50:20.494178 Dram Type= 6, Freq= 0, CH_0, rank 1
7703 22:50:20.497384 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7704 22:50:20.497845 ==
7705 22:50:20.500845 Write leveling (Byte 0): 31 => 31
7706 22:50:20.504025 Write leveling (Byte 1): 26 => 26
7707 22:50:20.507343 DramcWriteLeveling(PI) end<-----
7708 22:50:20.507898
7709 22:50:20.508258 ==
7710 22:50:20.511092 Dram Type= 6, Freq= 0, CH_0, rank 1
7711 22:50:20.513903 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7712 22:50:20.514424 ==
7713 22:50:20.517465 [Gating] SW mode calibration
7714 22:50:20.523609 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7715 22:50:20.530485 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7716 22:50:20.533543 0 12 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7717 22:50:20.540769 0 12 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7718 22:50:20.543872 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7719 22:50:20.547436 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7720 22:50:20.550597 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7721 22:50:20.557196 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7722 22:50:20.560183 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7723 22:50:20.563617 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
7724 22:50:20.570540 0 13 0 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7725 22:50:20.573649 0 13 4 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
7726 22:50:20.576706 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7727 22:50:20.583201 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7728 22:50:20.586680 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7729 22:50:20.589918 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7730 22:50:20.596647 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7731 22:50:20.600117 0 13 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7732 22:50:20.603372 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7733 22:50:20.610086 0 14 4 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7734 22:50:20.613226 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7735 22:50:20.616097 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7736 22:50:20.623124 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7737 22:50:20.625985 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7738 22:50:20.629287 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7739 22:50:20.635940 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7740 22:50:20.639174 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7741 22:50:20.642581 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7742 22:50:20.649321 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7743 22:50:20.652742 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7744 22:50:20.656081 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 22:50:20.662616 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 22:50:20.666223 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 22:50:20.669021 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 22:50:20.675649 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 22:50:20.679020 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 22:50:20.682587 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 22:50:20.688819 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 22:50:20.692277 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 22:50:20.695546 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 22:50:20.702334 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7755 22:50:20.705537 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7756 22:50:20.709122 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7757 22:50:20.715558 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7758 22:50:20.718987 Total UI for P1: 0, mck2ui 16
7759 22:50:20.722134 best dqsien dly found for B0: ( 1, 0, 28)
7760 22:50:20.725397 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7761 22:50:20.728867 Total UI for P1: 0, mck2ui 16
7762 22:50:20.731895 best dqsien dly found for B1: ( 1, 1, 2)
7763 22:50:20.734993 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7764 22:50:20.738383 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7765 22:50:20.738941
7766 22:50:20.742499 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7767 22:50:20.745149 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7768 22:50:20.748535 [Gating] SW calibration Done
7769 22:50:20.749202 ==
7770 22:50:20.751459 Dram Type= 6, Freq= 0, CH_0, rank 1
7771 22:50:20.758406 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7772 22:50:20.758966 ==
7773 22:50:20.759330 RX Vref Scan: 0
7774 22:50:20.759665
7775 22:50:20.761765 RX Vref 0 -> 0, step: 1
7776 22:50:20.762378
7777 22:50:20.765158 RX Delay 0 -> 252, step: 8
7778 22:50:20.768168 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7779 22:50:20.771761 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7780 22:50:20.774961 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7781 22:50:20.778327 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7782 22:50:20.784784 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7783 22:50:20.788037 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7784 22:50:20.791343 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7785 22:50:20.794876 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7786 22:50:20.798261 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7787 22:50:20.804693 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7788 22:50:20.808107 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7789 22:50:20.811324 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7790 22:50:20.814694 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7791 22:50:20.821139 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7792 22:50:20.824380 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7793 22:50:20.827906 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7794 22:50:20.828458 ==
7795 22:50:20.831308 Dram Type= 6, Freq= 0, CH_0, rank 1
7796 22:50:20.834278 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7797 22:50:20.834740 ==
7798 22:50:20.837719 DQS Delay:
7799 22:50:20.838240 DQS0 = 0, DQS1 = 0
7800 22:50:20.838603 DQM Delay:
7801 22:50:20.841361 DQM0 = 130, DQM1 = 124
7802 22:50:20.841908 DQ Delay:
7803 22:50:20.844629 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7804 22:50:20.847865 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7805 22:50:20.854585 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7806 22:50:20.857858 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7807 22:50:20.858474
7808 22:50:20.858841
7809 22:50:20.859177 ==
7810 22:50:20.861025 Dram Type= 6, Freq= 0, CH_0, rank 1
7811 22:50:20.864491 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7812 22:50:20.865069 ==
7813 22:50:20.865430
7814 22:50:20.865764
7815 22:50:20.867818 TX Vref Scan disable
7816 22:50:20.870737 == TX Byte 0 ==
7817 22:50:20.874417 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7818 22:50:20.877607 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7819 22:50:20.881167 == TX Byte 1 ==
7820 22:50:20.884021 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7821 22:50:20.887327 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7822 22:50:20.887920 ==
7823 22:50:20.890780 Dram Type= 6, Freq= 0, CH_0, rank 1
7824 22:50:20.894522 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7825 22:50:20.895084 ==
7826 22:50:20.909751
7827 22:50:20.913324 TX Vref early break, caculate TX vref
7828 22:50:20.917070 TX Vref=16, minBit 8, minWin=22, winSum=373
7829 22:50:20.919803 TX Vref=18, minBit 0, minWin=23, winSum=381
7830 22:50:20.922875 TX Vref=20, minBit 7, minWin=23, winSum=389
7831 22:50:20.926270 TX Vref=22, minBit 8, minWin=24, winSum=399
7832 22:50:20.929920 TX Vref=24, minBit 1, minWin=24, winSum=404
7833 22:50:20.936549 TX Vref=26, minBit 8, minWin=24, winSum=411
7834 22:50:20.939623 TX Vref=28, minBit 1, minWin=25, winSum=414
7835 22:50:20.942987 TX Vref=30, minBit 8, minWin=24, winSum=408
7836 22:50:20.946378 TX Vref=32, minBit 1, minWin=24, winSum=399
7837 22:50:20.949517 TX Vref=34, minBit 8, minWin=23, winSum=393
7838 22:50:20.952998 TX Vref=36, minBit 8, minWin=22, winSum=383
7839 22:50:20.959781 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 28
7840 22:50:20.960462
7841 22:50:20.962653 Final TX Range 0 Vref 28
7842 22:50:20.963098
7843 22:50:20.963423 ==
7844 22:50:20.965930 Dram Type= 6, Freq= 0, CH_0, rank 1
7845 22:50:20.969243 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7846 22:50:20.969661 ==
7847 22:50:20.970208
7848 22:50:20.972283
7849 22:50:20.972831 TX Vref Scan disable
7850 22:50:20.979047 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7851 22:50:20.979596 == TX Byte 0 ==
7852 22:50:20.982714 u2DelayCellOfst[0]=10 cells (3 PI)
7853 22:50:20.985695 u2DelayCellOfst[1]=18 cells (5 PI)
7854 22:50:20.989188 u2DelayCellOfst[2]=10 cells (3 PI)
7855 22:50:20.992691 u2DelayCellOfst[3]=10 cells (3 PI)
7856 22:50:20.996207 u2DelayCellOfst[4]=7 cells (2 PI)
7857 22:50:20.998997 u2DelayCellOfst[5]=0 cells (0 PI)
7858 22:50:21.002144 u2DelayCellOfst[6]=14 cells (4 PI)
7859 22:50:21.005821 u2DelayCellOfst[7]=14 cells (4 PI)
7860 22:50:21.008816 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7861 22:50:21.012308 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7862 22:50:21.015855 == TX Byte 1 ==
7863 22:50:21.018792 u2DelayCellOfst[8]=7 cells (2 PI)
7864 22:50:21.022566 u2DelayCellOfst[9]=0 cells (0 PI)
7865 22:50:21.025607 u2DelayCellOfst[10]=10 cells (3 PI)
7866 22:50:21.028737 u2DelayCellOfst[11]=7 cells (2 PI)
7867 22:50:21.032380 u2DelayCellOfst[12]=18 cells (5 PI)
7868 22:50:21.033013 u2DelayCellOfst[13]=18 cells (5 PI)
7869 22:50:21.035411 u2DelayCellOfst[14]=21 cells (6 PI)
7870 22:50:21.038655 u2DelayCellOfst[15]=18 cells (5 PI)
7871 22:50:21.045134 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7872 22:50:21.048562 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7873 22:50:21.049103 DramC Write-DBI on
7874 22:50:21.051916 ==
7875 22:50:21.055425 Dram Type= 6, Freq= 0, CH_0, rank 1
7876 22:50:21.058375 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7877 22:50:21.058975 ==
7878 22:50:21.059314
7879 22:50:21.059621
7880 22:50:21.061760 TX Vref Scan disable
7881 22:50:21.062278 == TX Byte 0 ==
7882 22:50:21.068894 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7883 22:50:21.069402 == TX Byte 1 ==
7884 22:50:21.071878 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7885 22:50:21.075036 DramC Write-DBI off
7886 22:50:21.075718
7887 22:50:21.076064 [DATLAT]
7888 22:50:21.078447 Freq=1600, CH0 RK1
7889 22:50:21.078863
7890 22:50:21.079185 DATLAT Default: 0xe
7891 22:50:21.081755 0, 0xFFFF, sum = 0
7892 22:50:21.082213 1, 0xFFFF, sum = 0
7893 22:50:21.085218 2, 0xFFFF, sum = 0
7894 22:50:21.085705 3, 0xFFFF, sum = 0
7895 22:50:21.088511 4, 0xFFFF, sum = 0
7896 22:50:21.089025 5, 0xFFFF, sum = 0
7897 22:50:21.092047 6, 0xFFFF, sum = 0
7898 22:50:21.092649 7, 0xFFFF, sum = 0
7899 22:50:21.095018 8, 0xFFFF, sum = 0
7900 22:50:21.098157 9, 0xFFFF, sum = 0
7901 22:50:21.098690 10, 0xFFFF, sum = 0
7902 22:50:21.101796 11, 0xFFFF, sum = 0
7903 22:50:21.102402 12, 0xCFFF, sum = 0
7904 22:50:21.104891 13, 0x0, sum = 1
7905 22:50:21.105609 14, 0x0, sum = 2
7906 22:50:21.108188 15, 0x0, sum = 3
7907 22:50:21.108609 16, 0x0, sum = 4
7908 22:50:21.108938 best_step = 14
7909 22:50:21.112033
7910 22:50:21.112539 ==
7911 22:50:21.114813 Dram Type= 6, Freq= 0, CH_0, rank 1
7912 22:50:21.118169 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7913 22:50:21.118588 ==
7914 22:50:21.118916 RX Vref Scan: 0
7915 22:50:21.119216
7916 22:50:21.121348 RX Vref 0 -> 0, step: 1
7917 22:50:21.121760
7918 22:50:21.124945 RX Delay 11 -> 252, step: 4
7919 22:50:21.128048 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7920 22:50:21.134876 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7921 22:50:21.137943 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7922 22:50:21.141177 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7923 22:50:21.144636 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7924 22:50:21.147769 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7925 22:50:21.154471 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7926 22:50:21.157818 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7927 22:50:21.161273 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7928 22:50:21.164680 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7929 22:50:21.167678 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7930 22:50:21.174133 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7931 22:50:21.177560 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7932 22:50:21.181358 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7933 22:50:21.184623 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7934 22:50:21.191227 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7935 22:50:21.191757 ==
7936 22:50:21.194003 Dram Type= 6, Freq= 0, CH_0, rank 1
7937 22:50:21.197719 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7938 22:50:21.198348 ==
7939 22:50:21.198798 DQS Delay:
7940 22:50:21.200922 DQS0 = 0, DQS1 = 0
7941 22:50:21.201472 DQM Delay:
7942 22:50:21.204255 DQM0 = 127, DQM1 = 120
7943 22:50:21.204809 DQ Delay:
7944 22:50:21.207441 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
7945 22:50:21.211124 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
7946 22:50:21.213970 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7947 22:50:21.217361 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
7948 22:50:21.217952
7949 22:50:21.218465
7950 22:50:21.218973
7951 22:50:21.220542 [DramC_TX_OE_Calibration] TA2
7952 22:50:21.223853 Original DQ_B0 (3 6) =30, OEN = 27
7953 22:50:21.227087 Original DQ_B1 (3 6) =30, OEN = 27
7954 22:50:21.230677 24, 0x0, End_B0=24 End_B1=24
7955 22:50:21.233796 25, 0x0, End_B0=25 End_B1=25
7956 22:50:21.237415 26, 0x0, End_B0=26 End_B1=26
7957 22:50:21.237848 27, 0x0, End_B0=27 End_B1=27
7958 22:50:21.240461 28, 0x0, End_B0=28 End_B1=28
7959 22:50:21.243669 29, 0x0, End_B0=29 End_B1=29
7960 22:50:21.247167 30, 0x0, End_B0=30 End_B1=30
7961 22:50:21.247716 31, 0x4545, End_B0=30 End_B1=30
7962 22:50:21.250481 Byte0 end_step=30 best_step=27
7963 22:50:21.253555 Byte1 end_step=30 best_step=27
7964 22:50:21.257251 Byte0 TX OE(2T, 0.5T) = (3, 3)
7965 22:50:21.260560 Byte1 TX OE(2T, 0.5T) = (3, 3)
7966 22:50:21.261087
7967 22:50:21.261520
7968 22:50:21.267011 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7969 22:50:21.270906 CH0 RK1: MR19=303, MR18=2121
7970 22:50:21.276868 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
7971 22:50:21.279825 [RxdqsGatingPostProcess] freq 1600
7972 22:50:21.286476 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7973 22:50:21.289776 Pre-setting of DQS Precalculation
7974 22:50:21.293601 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7975 22:50:21.294177 ==
7976 22:50:21.297004 Dram Type= 6, Freq= 0, CH_1, rank 0
7977 22:50:21.300059 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7978 22:50:21.300476 ==
7979 22:50:21.306360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7980 22:50:21.309624 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7981 22:50:21.316597 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7982 22:50:21.320043 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7983 22:50:21.329359 [CA 0] Center 41 (11~71) winsize 61
7984 22:50:21.332663 [CA 1] Center 41 (11~72) winsize 62
7985 22:50:21.335988 [CA 2] Center 37 (8~67) winsize 60
7986 22:50:21.339902 [CA 3] Center 36 (7~66) winsize 60
7987 22:50:21.342808 [CA 4] Center 34 (4~64) winsize 61
7988 22:50:21.345839 [CA 5] Center 34 (4~64) winsize 61
7989 22:50:21.346326
7990 22:50:21.349482 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7991 22:50:21.350098
7992 22:50:21.352658 [CATrainingPosCal] consider 1 rank data
7993 22:50:21.355998 u2DelayCellTimex100 = 271/100 ps
7994 22:50:21.358991 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
7995 22:50:21.365858 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
7996 22:50:21.369175 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
7997 22:50:21.372854 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
7998 22:50:21.375760 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
7999 22:50:21.379265 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8000 22:50:21.379828
8001 22:50:21.382893 CA PerBit enable=1, Macro0, CA PI delay=34
8002 22:50:21.383456
8003 22:50:21.385665 [CBTSetCACLKResult] CA Dly = 34
8004 22:50:21.388946 CS Dly: 8 (0~39)
8005 22:50:21.392390 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8006 22:50:21.395807 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8007 22:50:21.396371 ==
8008 22:50:21.398719 Dram Type= 6, Freq= 0, CH_1, rank 1
8009 22:50:21.402402 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8010 22:50:21.405760 ==
8011 22:50:21.409464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8012 22:50:21.412147 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8013 22:50:21.418815 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8014 22:50:21.422476 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8015 22:50:21.431757 [CA 0] Center 41 (11~71) winsize 61
8016 22:50:21.435193 [CA 1] Center 40 (10~71) winsize 62
8017 22:50:21.438345 [CA 2] Center 36 (7~66) winsize 60
8018 22:50:21.441573 [CA 3] Center 36 (7~65) winsize 59
8019 22:50:21.444930 [CA 4] Center 34 (4~64) winsize 61
8020 22:50:21.448591 [CA 5] Center 34 (5~64) winsize 60
8021 22:50:21.449116
8022 22:50:21.451463 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8023 22:50:21.451889
8024 22:50:21.454934 [CATrainingPosCal] consider 2 rank data
8025 22:50:21.458379 u2DelayCellTimex100 = 271/100 ps
8026 22:50:21.461812 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8027 22:50:21.468191 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8028 22:50:21.471680 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8029 22:50:21.474988 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8030 22:50:21.478130 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8031 22:50:21.481651 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8032 22:50:21.482224
8033 22:50:21.484744 CA PerBit enable=1, Macro0, CA PI delay=34
8034 22:50:21.485271
8035 22:50:21.487999 [CBTSetCACLKResult] CA Dly = 34
8036 22:50:21.491938 CS Dly: 9 (0~41)
8037 22:50:21.494969 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8038 22:50:21.498179 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8039 22:50:21.498763
8040 22:50:21.501441 ----->DramcWriteLeveling(PI) begin...
8041 22:50:21.501974 ==
8042 22:50:21.504797 Dram Type= 6, Freq= 0, CH_1, rank 0
8043 22:50:21.511475 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8044 22:50:21.512008 ==
8045 22:50:21.516466 Write leveling (Byte 0): 23 => 23
8046 22:50:21.516891 Write leveling (Byte 1): 20 => 20
8047 22:50:21.517901 DramcWriteLeveling(PI) end<-----
8048 22:50:21.518382
8049 22:50:21.518709 ==
8050 22:50:21.521130 Dram Type= 6, Freq= 0, CH_1, rank 0
8051 22:50:21.528192 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8052 22:50:21.528707 ==
8053 22:50:21.531132 [Gating] SW mode calibration
8054 22:50:21.537967 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8055 22:50:21.541426 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8056 22:50:21.547730 0 12 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8057 22:50:21.550657 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 22:50:21.554328 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 22:50:21.560908 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 22:50:21.563927 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 22:50:21.567417 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8062 22:50:21.574197 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8063 22:50:21.577231 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8064 22:50:21.580627 0 13 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8065 22:50:21.587036 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8066 22:50:21.590829 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 22:50:21.593893 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 22:50:21.600901 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 22:50:21.603983 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 22:50:21.607211 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 22:50:21.613713 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8072 22:50:21.617026 0 14 0 | B1->B0 | 3c3c 4646 | 1 0 | (1 1) (0 0)
8073 22:50:21.620486 0 14 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8074 22:50:21.626901 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 22:50:21.630248 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 22:50:21.633517 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 22:50:21.640149 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 22:50:21.643342 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 22:50:21.646790 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8080 22:50:21.653528 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8081 22:50:21.656683 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8082 22:50:21.660044 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 22:50:21.666724 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 22:50:21.669975 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 22:50:21.673304 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 22:50:21.679572 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 22:50:21.683208 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 22:50:21.686352 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 22:50:21.692929 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 22:50:21.696894 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 22:50:21.699525 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 22:50:21.706654 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 22:50:21.709319 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 22:50:21.712886 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8095 22:50:21.719429 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8096 22:50:21.722976 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8097 22:50:21.726272 Total UI for P1: 0, mck2ui 16
8098 22:50:21.729456 best dqsien dly found for B0: ( 1, 0, 26)
8099 22:50:21.732723 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 22:50:21.735898 Total UI for P1: 0, mck2ui 16
8101 22:50:21.739554 best dqsien dly found for B1: ( 1, 0, 30)
8102 22:50:21.742768 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8103 22:50:21.745847 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8104 22:50:21.746452
8105 22:50:21.749476 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8106 22:50:21.756048 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8107 22:50:21.756602 [Gating] SW calibration Done
8108 22:50:21.756964 ==
8109 22:50:21.759283 Dram Type= 6, Freq= 0, CH_1, rank 0
8110 22:50:21.765737 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8111 22:50:21.766320 ==
8112 22:50:21.766780 RX Vref Scan: 0
8113 22:50:21.767126
8114 22:50:21.769419 RX Vref 0 -> 0, step: 1
8115 22:50:21.769966
8116 22:50:21.772520 RX Delay 0 -> 252, step: 8
8117 22:50:21.775686 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8118 22:50:21.778884 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8119 22:50:21.782593 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8120 22:50:21.788943 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8121 22:50:21.792145 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8122 22:50:21.795788 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8123 22:50:21.798673 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8124 22:50:21.801958 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8125 22:50:21.805255 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8126 22:50:21.812156 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8127 22:50:21.815348 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8128 22:50:21.818569 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8129 22:50:21.822103 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8130 22:50:21.828794 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8131 22:50:21.832223 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8132 22:50:21.834938 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8133 22:50:21.835356 ==
8134 22:50:21.838735 Dram Type= 6, Freq= 0, CH_1, rank 0
8135 22:50:21.841643 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8136 22:50:21.842219 ==
8137 22:50:21.844950 DQS Delay:
8138 22:50:21.845437 DQS0 = 0, DQS1 = 0
8139 22:50:21.848321 DQM Delay:
8140 22:50:21.848828 DQM0 = 130, DQM1 = 125
8141 22:50:21.852066 DQ Delay:
8142 22:50:21.855463 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8143 22:50:21.858182 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8144 22:50:21.861718 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8145 22:50:21.865065 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8146 22:50:21.865610
8147 22:50:21.865949
8148 22:50:21.866346 ==
8149 22:50:21.868174 Dram Type= 6, Freq= 0, CH_1, rank 0
8150 22:50:21.871162 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8151 22:50:21.871248 ==
8152 22:50:21.871310
8153 22:50:21.871369
8154 22:50:21.874233 TX Vref Scan disable
8155 22:50:21.877511 == TX Byte 0 ==
8156 22:50:21.881149 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8157 22:50:21.884418 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8158 22:50:21.887493 == TX Byte 1 ==
8159 22:50:21.890862 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8160 22:50:21.894329 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8161 22:50:21.894402 ==
8162 22:50:21.897374 Dram Type= 6, Freq= 0, CH_1, rank 0
8163 22:50:21.904105 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8164 22:50:21.904183 ==
8165 22:50:21.915535
8166 22:50:21.919057 TX Vref early break, caculate TX vref
8167 22:50:21.922088 TX Vref=16, minBit 3, minWin=21, winSum=371
8168 22:50:21.925304 TX Vref=18, minBit 3, minWin=21, winSum=376
8169 22:50:21.928573 TX Vref=20, minBit 3, minWin=22, winSum=388
8170 22:50:21.932013 TX Vref=22, minBit 3, minWin=23, winSum=397
8171 22:50:21.935182 TX Vref=24, minBit 3, minWin=23, winSum=408
8172 22:50:21.941849 TX Vref=26, minBit 0, minWin=25, winSum=416
8173 22:50:21.945052 TX Vref=28, minBit 3, minWin=24, winSum=414
8174 22:50:21.948369 TX Vref=30, minBit 0, minWin=24, winSum=408
8175 22:50:21.951655 TX Vref=32, minBit 3, minWin=23, winSum=402
8176 22:50:21.954953 TX Vref=34, minBit 0, minWin=23, winSum=391
8177 22:50:21.961750 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
8178 22:50:21.961824
8179 22:50:21.965373 Final TX Range 0 Vref 26
8180 22:50:21.965471
8181 22:50:21.965557 ==
8182 22:50:21.968268 Dram Type= 6, Freq= 0, CH_1, rank 0
8183 22:50:21.971708 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8184 22:50:21.971779 ==
8185 22:50:21.971838
8186 22:50:21.971894
8187 22:50:21.974972 TX Vref Scan disable
8188 22:50:21.981533 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8189 22:50:21.981607 == TX Byte 0 ==
8190 22:50:21.984726 u2DelayCellOfst[0]=14 cells (4 PI)
8191 22:50:21.988223 u2DelayCellOfst[1]=10 cells (3 PI)
8192 22:50:21.991422 u2DelayCellOfst[2]=0 cells (0 PI)
8193 22:50:21.994723 u2DelayCellOfst[3]=3 cells (1 PI)
8194 22:50:21.997960 u2DelayCellOfst[4]=7 cells (2 PI)
8195 22:50:22.001449 u2DelayCellOfst[5]=14 cells (4 PI)
8196 22:50:22.004887 u2DelayCellOfst[6]=14 cells (4 PI)
8197 22:50:22.004958 u2DelayCellOfst[7]=3 cells (1 PI)
8198 22:50:22.011629 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8199 22:50:22.015030 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8200 22:50:22.018115 == TX Byte 1 ==
8201 22:50:22.018191 u2DelayCellOfst[8]=0 cells (0 PI)
8202 22:50:22.021256 u2DelayCellOfst[9]=3 cells (1 PI)
8203 22:50:22.024781 u2DelayCellOfst[10]=7 cells (2 PI)
8204 22:50:22.028067 u2DelayCellOfst[11]=0 cells (0 PI)
8205 22:50:22.031226 u2DelayCellOfst[12]=14 cells (4 PI)
8206 22:50:22.034830 u2DelayCellOfst[13]=14 cells (4 PI)
8207 22:50:22.038225 u2DelayCellOfst[14]=14 cells (4 PI)
8208 22:50:22.041169 u2DelayCellOfst[15]=14 cells (4 PI)
8209 22:50:22.044628 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8210 22:50:22.051238 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8211 22:50:22.051338 DramC Write-DBI on
8212 22:50:22.051435 ==
8213 22:50:22.054486 Dram Type= 6, Freq= 0, CH_1, rank 0
8214 22:50:22.057950 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8215 22:50:22.061038 ==
8216 22:50:22.061108
8217 22:50:22.061167
8218 22:50:22.061227 TX Vref Scan disable
8219 22:50:22.064551 == TX Byte 0 ==
8220 22:50:22.068157 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8221 22:50:22.071037 == TX Byte 1 ==
8222 22:50:22.074330 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8223 22:50:22.077596 DramC Write-DBI off
8224 22:50:22.077695
8225 22:50:22.077782 [DATLAT]
8226 22:50:22.077866 Freq=1600, CH1 RK0
8227 22:50:22.077959
8228 22:50:22.080964 DATLAT Default: 0xf
8229 22:50:22.081032 0, 0xFFFF, sum = 0
8230 22:50:22.084330 1, 0xFFFF, sum = 0
8231 22:50:22.087914 2, 0xFFFF, sum = 0
8232 22:50:22.087987 3, 0xFFFF, sum = 0
8233 22:50:22.091077 4, 0xFFFF, sum = 0
8234 22:50:22.091148 5, 0xFFFF, sum = 0
8235 22:50:22.094353 6, 0xFFFF, sum = 0
8236 22:50:22.094422 7, 0xFFFF, sum = 0
8237 22:50:22.097458 8, 0xFFFF, sum = 0
8238 22:50:22.097554 9, 0xFFFF, sum = 0
8239 22:50:22.100698 10, 0xFFFF, sum = 0
8240 22:50:22.100775 11, 0xFFFF, sum = 0
8241 22:50:22.104242 12, 0xF7F, sum = 0
8242 22:50:22.104315 13, 0x0, sum = 1
8243 22:50:22.107483 14, 0x0, sum = 2
8244 22:50:22.107556 15, 0x0, sum = 3
8245 22:50:22.110870 16, 0x0, sum = 4
8246 22:50:22.110967 best_step = 14
8247 22:50:22.111055
8248 22:50:22.111139 ==
8249 22:50:22.114453 Dram Type= 6, Freq= 0, CH_1, rank 0
8250 22:50:22.117356 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8251 22:50:22.120957 ==
8252 22:50:22.121054 RX Vref Scan: 1
8253 22:50:22.121141
8254 22:50:22.123889 Set Vref Range= 24 -> 127
8255 22:50:22.123985
8256 22:50:22.127216 RX Vref 24 -> 127, step: 1
8257 22:50:22.127285
8258 22:50:22.127342 RX Delay 3 -> 252, step: 4
8259 22:50:22.127401
8260 22:50:22.131082 Set Vref, RX VrefLevel [Byte0]: 24
8261 22:50:22.133849 [Byte1]: 24
8262 22:50:22.137997
8263 22:50:22.138113 Set Vref, RX VrefLevel [Byte0]: 25
8264 22:50:22.141107 [Byte1]: 25
8265 22:50:22.145110
8266 22:50:22.145180 Set Vref, RX VrefLevel [Byte0]: 26
8267 22:50:22.148730 [Byte1]: 26
8268 22:50:22.152908
8269 22:50:22.152983 Set Vref, RX VrefLevel [Byte0]: 27
8270 22:50:22.156121 [Byte1]: 27
8271 22:50:22.160625
8272 22:50:22.160722 Set Vref, RX VrefLevel [Byte0]: 28
8273 22:50:22.164103 [Byte1]: 28
8274 22:50:22.168099
8275 22:50:22.168175 Set Vref, RX VrefLevel [Byte0]: 29
8276 22:50:22.171625 [Byte1]: 29
8277 22:50:22.175909
8278 22:50:22.176024 Set Vref, RX VrefLevel [Byte0]: 30
8279 22:50:22.179342 [Byte1]: 30
8280 22:50:22.184047
8281 22:50:22.184170 Set Vref, RX VrefLevel [Byte0]: 31
8282 22:50:22.186762 [Byte1]: 31
8283 22:50:22.191343
8284 22:50:22.191450 Set Vref, RX VrefLevel [Byte0]: 32
8285 22:50:22.194461 [Byte1]: 32
8286 22:50:22.199112
8287 22:50:22.199209 Set Vref, RX VrefLevel [Byte0]: 33
8288 22:50:22.202206 [Byte1]: 33
8289 22:50:22.206534
8290 22:50:22.206641 Set Vref, RX VrefLevel [Byte0]: 34
8291 22:50:22.209730 [Byte1]: 34
8292 22:50:22.214205
8293 22:50:22.214318 Set Vref, RX VrefLevel [Byte0]: 35
8294 22:50:22.217418 [Byte1]: 35
8295 22:50:22.221878
8296 22:50:22.221987 Set Vref, RX VrefLevel [Byte0]: 36
8297 22:50:22.225461 [Byte1]: 36
8298 22:50:22.229629
8299 22:50:22.229754 Set Vref, RX VrefLevel [Byte0]: 37
8300 22:50:22.232936 [Byte1]: 37
8301 22:50:22.237546
8302 22:50:22.237681 Set Vref, RX VrefLevel [Byte0]: 38
8303 22:50:22.240459 [Byte1]: 38
8304 22:50:22.244814
8305 22:50:22.244922 Set Vref, RX VrefLevel [Byte0]: 39
8306 22:50:22.248021 [Byte1]: 39
8307 22:50:22.252433
8308 22:50:22.252649 Set Vref, RX VrefLevel [Byte0]: 40
8309 22:50:22.256164 [Byte1]: 40
8310 22:50:22.260209
8311 22:50:22.260437 Set Vref, RX VrefLevel [Byte0]: 41
8312 22:50:22.263694 [Byte1]: 41
8313 22:50:22.267803
8314 22:50:22.268119 Set Vref, RX VrefLevel [Byte0]: 42
8315 22:50:22.271194 [Byte1]: 42
8316 22:50:22.275760
8317 22:50:22.276152 Set Vref, RX VrefLevel [Byte0]: 43
8318 22:50:22.278776 [Byte1]: 43
8319 22:50:22.283309
8320 22:50:22.283869 Set Vref, RX VrefLevel [Byte0]: 44
8321 22:50:22.286620 [Byte1]: 44
8322 22:50:22.291087
8323 22:50:22.291591 Set Vref, RX VrefLevel [Byte0]: 45
8324 22:50:22.294239 [Byte1]: 45
8325 22:50:22.298761
8326 22:50:22.299323 Set Vref, RX VrefLevel [Byte0]: 46
8327 22:50:22.302254 [Byte1]: 46
8328 22:50:22.306243
8329 22:50:22.306706 Set Vref, RX VrefLevel [Byte0]: 47
8330 22:50:22.309899 [Byte1]: 47
8331 22:50:22.313940
8332 22:50:22.314424 Set Vref, RX VrefLevel [Byte0]: 48
8333 22:50:22.317165 [Byte1]: 48
8334 22:50:22.321550
8335 22:50:22.321997 Set Vref, RX VrefLevel [Byte0]: 49
8336 22:50:22.324968 [Byte1]: 49
8337 22:50:22.329378
8338 22:50:22.329822 Set Vref, RX VrefLevel [Byte0]: 50
8339 22:50:22.332574 [Byte1]: 50
8340 22:50:22.336706
8341 22:50:22.340486 Set Vref, RX VrefLevel [Byte0]: 51
8342 22:50:22.343566 [Byte1]: 51
8343 22:50:22.343645
8344 22:50:22.346502 Set Vref, RX VrefLevel [Byte0]: 52
8345 22:50:22.349833 [Byte1]: 52
8346 22:50:22.349913
8347 22:50:22.353053 Set Vref, RX VrefLevel [Byte0]: 53
8348 22:50:22.356192 [Byte1]: 53
8349 22:50:22.360032
8350 22:50:22.360126 Set Vref, RX VrefLevel [Byte0]: 54
8351 22:50:22.363283 [Byte1]: 54
8352 22:50:22.367502
8353 22:50:22.367597 Set Vref, RX VrefLevel [Byte0]: 55
8354 22:50:22.370524 [Byte1]: 55
8355 22:50:22.374949
8356 22:50:22.375022 Set Vref, RX VrefLevel [Byte0]: 56
8357 22:50:22.378063 [Byte1]: 56
8358 22:50:22.382741
8359 22:50:22.382812 Set Vref, RX VrefLevel [Byte0]: 57
8360 22:50:22.385755 [Byte1]: 57
8361 22:50:22.390349
8362 22:50:22.390420 Set Vref, RX VrefLevel [Byte0]: 58
8363 22:50:22.393510 [Byte1]: 58
8364 22:50:22.397923
8365 22:50:22.397992 Set Vref, RX VrefLevel [Byte0]: 59
8366 22:50:22.401122 [Byte1]: 59
8367 22:50:22.405662
8368 22:50:22.405734 Set Vref, RX VrefLevel [Byte0]: 60
8369 22:50:22.408874 [Byte1]: 60
8370 22:50:22.413206
8371 22:50:22.413294 Set Vref, RX VrefLevel [Byte0]: 61
8372 22:50:22.416420 [Byte1]: 61
8373 22:50:22.420932
8374 22:50:22.421032 Set Vref, RX VrefLevel [Byte0]: 62
8375 22:50:22.424230 [Byte1]: 62
8376 22:50:22.428519
8377 22:50:22.428617 Set Vref, RX VrefLevel [Byte0]: 63
8378 22:50:22.431694 [Byte1]: 63
8379 22:50:22.436417
8380 22:50:22.436516 Set Vref, RX VrefLevel [Byte0]: 64
8381 22:50:22.439815 [Byte1]: 64
8382 22:50:22.443748
8383 22:50:22.443819 Set Vref, RX VrefLevel [Byte0]: 65
8384 22:50:22.447118 [Byte1]: 65
8385 22:50:22.451796
8386 22:50:22.451895 Set Vref, RX VrefLevel [Byte0]: 66
8387 22:50:22.454892 [Byte1]: 66
8388 22:50:22.459148
8389 22:50:22.459244 Set Vref, RX VrefLevel [Byte0]: 67
8390 22:50:22.462582 [Byte1]: 67
8391 22:50:22.466929
8392 22:50:22.467003 Set Vref, RX VrefLevel [Byte0]: 68
8393 22:50:22.470094 [Byte1]: 68
8394 22:50:22.474478
8395 22:50:22.474571 Set Vref, RX VrefLevel [Byte0]: 69
8396 22:50:22.477699 [Byte1]: 69
8397 22:50:22.482084
8398 22:50:22.482165 Set Vref, RX VrefLevel [Byte0]: 70
8399 22:50:22.485408 [Byte1]: 70
8400 22:50:22.489552
8401 22:50:22.489632 Set Vref, RX VrefLevel [Byte0]: 71
8402 22:50:22.493045 [Byte1]: 71
8403 22:50:22.497595
8404 22:50:22.497679 Set Vref, RX VrefLevel [Byte0]: 72
8405 22:50:22.500694 [Byte1]: 72
8406 22:50:22.504832
8407 22:50:22.504913 Set Vref, RX VrefLevel [Byte0]: 73
8408 22:50:22.508249 [Byte1]: 73
8409 22:50:22.512638
8410 22:50:22.512719 Set Vref, RX VrefLevel [Byte0]: 74
8411 22:50:22.515764 [Byte1]: 74
8412 22:50:22.520263
8413 22:50:22.520343 Set Vref, RX VrefLevel [Byte0]: 75
8414 22:50:22.523544 [Byte1]: 75
8415 22:50:22.527816
8416 22:50:22.527896 Set Vref, RX VrefLevel [Byte0]: 76
8417 22:50:22.531413 [Byte1]: 76
8418 22:50:22.535595
8419 22:50:22.535675 Final RX Vref Byte 0 = 62 to rank0
8420 22:50:22.539125 Final RX Vref Byte 1 = 55 to rank0
8421 22:50:22.542648 Final RX Vref Byte 0 = 62 to rank1
8422 22:50:22.545826 Final RX Vref Byte 1 = 55 to rank1==
8423 22:50:22.549421 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 22:50:22.555495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8425 22:50:22.555577 ==
8426 22:50:22.555642 DQS Delay:
8427 22:50:22.555701 DQS0 = 0, DQS1 = 0
8428 22:50:22.558831 DQM Delay:
8429 22:50:22.558912 DQM0 = 129, DQM1 = 123
8430 22:50:22.562087 DQ Delay:
8431 22:50:22.565421 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8432 22:50:22.568788 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8433 22:50:22.572053 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =112
8434 22:50:22.575602 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8435 22:50:22.575682
8436 22:50:22.575746
8437 22:50:22.575804
8438 22:50:22.578861 [DramC_TX_OE_Calibration] TA2
8439 22:50:22.582153 Original DQ_B0 (3 6) =30, OEN = 27
8440 22:50:22.585743 Original DQ_B1 (3 6) =30, OEN = 27
8441 22:50:22.588846 24, 0x0, End_B0=24 End_B1=24
8442 22:50:22.588928 25, 0x0, End_B0=25 End_B1=25
8443 22:50:22.591981 26, 0x0, End_B0=26 End_B1=26
8444 22:50:22.595296 27, 0x0, End_B0=27 End_B1=27
8445 22:50:22.598572 28, 0x0, End_B0=28 End_B1=28
8446 22:50:22.598674 29, 0x0, End_B0=29 End_B1=29
8447 22:50:22.602033 30, 0x0, End_B0=30 End_B1=30
8448 22:50:22.605285 31, 0x4141, End_B0=30 End_B1=30
8449 22:50:22.608626 Byte0 end_step=30 best_step=27
8450 22:50:22.611950 Byte1 end_step=30 best_step=27
8451 22:50:22.615540 Byte0 TX OE(2T, 0.5T) = (3, 3)
8452 22:50:22.618437 Byte1 TX OE(2T, 0.5T) = (3, 3)
8453 22:50:22.618513
8454 22:50:22.618574
8455 22:50:22.625434 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8456 22:50:22.628546 CH1 RK0: MR19=303, MR18=2727
8457 22:50:22.635095 CH1_RK0: MR19=0x303, MR18=0x2727, DQSOSC=390, MR23=63, INC=24, DEC=16
8458 22:50:22.635167
8459 22:50:22.638631 ----->DramcWriteLeveling(PI) begin...
8460 22:50:22.638703 ==
8461 22:50:22.641830 Dram Type= 6, Freq= 0, CH_1, rank 1
8462 22:50:22.645238 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8463 22:50:22.645324 ==
8464 22:50:22.648461 Write leveling (Byte 0): 20 => 20
8465 22:50:22.652215 Write leveling (Byte 1): 20 => 20
8466 22:50:22.654931 DramcWriteLeveling(PI) end<-----
8467 22:50:22.655000
8468 22:50:22.655058 ==
8469 22:50:22.658204 Dram Type= 6, Freq= 0, CH_1, rank 1
8470 22:50:22.661563 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8471 22:50:22.661662 ==
8472 22:50:22.664816 [Gating] SW mode calibration
8473 22:50:22.671644 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8474 22:50:22.678199 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8475 22:50:22.681660 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 22:50:22.684974 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8477 22:50:22.691826 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8478 22:50:22.694798 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 22:50:22.698237 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 22:50:22.704979 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8481 22:50:22.708096 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8482 22:50:22.711751 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8483 22:50:22.718127 0 13 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8484 22:50:22.721659 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 22:50:22.724806 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8486 22:50:22.731283 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8487 22:50:22.734592 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 22:50:22.738349 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 22:50:22.744556 0 13 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8490 22:50:22.748323 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8491 22:50:22.751160 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 22:50:22.757759 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 22:50:22.761083 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 22:50:22.764631 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 22:50:22.770836 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 22:50:22.774161 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 22:50:22.777617 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8498 22:50:22.784085 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8499 22:50:22.787433 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8500 22:50:22.790954 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 22:50:22.797573 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 22:50:22.800970 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 22:50:22.804085 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 22:50:22.810542 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 22:50:22.813853 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 22:50:22.817559 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 22:50:22.823815 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 22:50:22.827313 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 22:50:22.830597 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 22:50:22.837407 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 22:50:22.840325 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 22:50:22.843705 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 22:50:22.850430 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8514 22:50:22.853634 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8515 22:50:22.857071 Total UI for P1: 0, mck2ui 16
8516 22:50:22.860566 best dqsien dly found for B0: ( 1, 0, 24)
8517 22:50:22.863897 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8518 22:50:22.870564 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8519 22:50:22.870645 Total UI for P1: 0, mck2ui 16
8520 22:50:22.873647 best dqsien dly found for B1: ( 1, 0, 30)
8521 22:50:22.880370 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8522 22:50:22.883896 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8523 22:50:22.883977
8524 22:50:22.886923 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8525 22:50:22.890117 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8526 22:50:22.893608 [Gating] SW calibration Done
8527 22:50:22.893689 ==
8528 22:50:22.896694 Dram Type= 6, Freq= 0, CH_1, rank 1
8529 22:50:22.900112 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8530 22:50:22.900193 ==
8531 22:50:22.903315 RX Vref Scan: 0
8532 22:50:22.903396
8533 22:50:22.903459 RX Vref 0 -> 0, step: 1
8534 22:50:22.903518
8535 22:50:22.906789 RX Delay 0 -> 252, step: 8
8536 22:50:22.909885 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8537 22:50:22.916831 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8538 22:50:22.920069 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8539 22:50:22.923206 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8540 22:50:22.926434 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8541 22:50:22.929990 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8542 22:50:22.933368 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8543 22:50:22.939968 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8544 22:50:22.943120 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8545 22:50:22.946658 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8546 22:50:22.949853 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8547 22:50:22.953224 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8548 22:50:22.959992 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8549 22:50:22.963208 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8550 22:50:22.966705 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8551 22:50:22.969845 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8552 22:50:22.973616 ==
8553 22:50:22.973692 Dram Type= 6, Freq= 0, CH_1, rank 1
8554 22:50:22.979937 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8555 22:50:22.980013 ==
8556 22:50:22.980082 DQS Delay:
8557 22:50:22.983274 DQS0 = 0, DQS1 = 0
8558 22:50:22.983349 DQM Delay:
8559 22:50:22.986709 DQM0 = 130, DQM1 = 124
8560 22:50:22.986776 DQ Delay:
8561 22:50:22.990280 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8562 22:50:22.993114 DQ4 =123, DQ5 =143, DQ6 =139, DQ7 =131
8563 22:50:22.996337 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8564 22:50:22.999871 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8565 22:50:22.999939
8566 22:50:23.000003
8567 22:50:23.000059 ==
8568 22:50:23.002861 Dram Type= 6, Freq= 0, CH_1, rank 1
8569 22:50:23.009852 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8570 22:50:23.009922 ==
8571 22:50:23.009981
8572 22:50:23.010043
8573 22:50:23.010143 TX Vref Scan disable
8574 22:50:23.013088 == TX Byte 0 ==
8575 22:50:23.016099 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8576 22:50:23.022605 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8577 22:50:23.022684 == TX Byte 1 ==
8578 22:50:23.026307 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8579 22:50:23.032894 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8580 22:50:23.032968 ==
8581 22:50:23.036061 Dram Type= 6, Freq= 0, CH_1, rank 1
8582 22:50:23.039049 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8583 22:50:23.039117 ==
8584 22:50:23.052391
8585 22:50:23.055735 TX Vref early break, caculate TX vref
8586 22:50:23.059218 TX Vref=16, minBit 3, minWin=23, winSum=386
8587 22:50:23.062339 TX Vref=18, minBit 1, minWin=23, winSum=391
8588 22:50:23.065674 TX Vref=20, minBit 3, minWin=23, winSum=396
8589 22:50:23.069264 TX Vref=22, minBit 1, minWin=24, winSum=411
8590 22:50:23.072119 TX Vref=24, minBit 7, minWin=24, winSum=415
8591 22:50:23.078856 TX Vref=26, minBit 1, minWin=25, winSum=423
8592 22:50:23.082464 TX Vref=28, minBit 7, minWin=25, winSum=425
8593 22:50:23.085911 TX Vref=30, minBit 0, minWin=25, winSum=423
8594 22:50:23.088736 TX Vref=32, minBit 0, minWin=25, winSum=419
8595 22:50:23.092145 TX Vref=34, minBit 0, minWin=24, winSum=407
8596 22:50:23.095403 TX Vref=36, minBit 4, minWin=23, winSum=397
8597 22:50:23.101997 [TxChooseVref] Worse bit 7, Min win 25, Win sum 425, Final Vref 28
8598 22:50:23.102114
8599 22:50:23.105466 Final TX Range 0 Vref 28
8600 22:50:23.105534
8601 22:50:23.105599 ==
8602 22:50:23.108989 Dram Type= 6, Freq= 0, CH_1, rank 1
8603 22:50:23.111900 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8604 22:50:23.111969 ==
8605 22:50:23.112026
8606 22:50:23.115335
8607 22:50:23.115416 TX Vref Scan disable
8608 22:50:23.121720 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8609 22:50:23.121797 == TX Byte 0 ==
8610 22:50:23.125318 u2DelayCellOfst[0]=18 cells (5 PI)
8611 22:50:23.128572 u2DelayCellOfst[1]=10 cells (3 PI)
8612 22:50:23.131709 u2DelayCellOfst[2]=0 cells (0 PI)
8613 22:50:23.135031 u2DelayCellOfst[3]=7 cells (2 PI)
8614 22:50:23.138223 u2DelayCellOfst[4]=10 cells (3 PI)
8615 22:50:23.141389 u2DelayCellOfst[5]=14 cells (4 PI)
8616 22:50:23.144946 u2DelayCellOfst[6]=14 cells (4 PI)
8617 22:50:23.148110 u2DelayCellOfst[7]=3 cells (1 PI)
8618 22:50:23.151630 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8619 22:50:23.155326 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8620 22:50:23.158031 == TX Byte 1 ==
8621 22:50:23.161441 u2DelayCellOfst[8]=0 cells (0 PI)
8622 22:50:23.164676 u2DelayCellOfst[9]=3 cells (1 PI)
8623 22:50:23.168122 u2DelayCellOfst[10]=10 cells (3 PI)
8624 22:50:23.168202 u2DelayCellOfst[11]=3 cells (1 PI)
8625 22:50:23.171306 u2DelayCellOfst[12]=14 cells (4 PI)
8626 22:50:23.174712 u2DelayCellOfst[13]=18 cells (5 PI)
8627 22:50:23.178183 u2DelayCellOfst[14]=18 cells (5 PI)
8628 22:50:23.181302 u2DelayCellOfst[15]=18 cells (5 PI)
8629 22:50:23.188114 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8630 22:50:23.191354 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8631 22:50:23.191428 DramC Write-DBI on
8632 22:50:23.194379 ==
8633 22:50:23.198220 Dram Type= 6, Freq= 0, CH_1, rank 1
8634 22:50:23.200939 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8635 22:50:23.201008 ==
8636 22:50:23.201074
8637 22:50:23.201130
8638 22:50:23.204590 TX Vref Scan disable
8639 22:50:23.204659 == TX Byte 0 ==
8640 22:50:23.211117 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8641 22:50:23.211192 == TX Byte 1 ==
8642 22:50:23.214215 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8643 22:50:23.218015 DramC Write-DBI off
8644 22:50:23.218123
8645 22:50:23.218183 [DATLAT]
8646 22:50:23.221194 Freq=1600, CH1 RK1
8647 22:50:23.221267
8648 22:50:23.221326 DATLAT Default: 0xe
8649 22:50:23.224462 0, 0xFFFF, sum = 0
8650 22:50:23.224529 1, 0xFFFF, sum = 0
8651 22:50:23.227861 2, 0xFFFF, sum = 0
8652 22:50:23.227928 3, 0xFFFF, sum = 0
8653 22:50:23.230826 4, 0xFFFF, sum = 0
8654 22:50:23.230904 5, 0xFFFF, sum = 0
8655 22:50:23.234188 6, 0xFFFF, sum = 0
8656 22:50:23.234258 7, 0xFFFF, sum = 0
8657 22:50:23.237567 8, 0xFFFF, sum = 0
8658 22:50:23.237640 9, 0xFFFF, sum = 0
8659 22:50:23.240804 10, 0xFFFF, sum = 0
8660 22:50:23.244072 11, 0xFFFF, sum = 0
8661 22:50:23.244150 12, 0x8F7F, sum = 0
8662 22:50:23.247543 13, 0x0, sum = 1
8663 22:50:23.247612 14, 0x0, sum = 2
8664 22:50:23.250628 15, 0x0, sum = 3
8665 22:50:23.250696 16, 0x0, sum = 4
8666 22:50:23.250755 best_step = 14
8667 22:50:23.250816
8668 22:50:23.254296 ==
8669 22:50:23.257356 Dram Type= 6, Freq= 0, CH_1, rank 1
8670 22:50:23.260467 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8671 22:50:23.260542 ==
8672 22:50:23.260601 RX Vref Scan: 0
8673 22:50:23.260657
8674 22:50:23.263902 RX Vref 0 -> 0, step: 1
8675 22:50:23.263968
8676 22:50:23.267298 RX Delay 3 -> 252, step: 4
8677 22:50:23.270466 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8678 22:50:23.277112 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8679 22:50:23.280724 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8680 22:50:23.283765 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8681 22:50:23.287143 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8682 22:50:23.290458 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8683 22:50:23.293756 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8684 22:50:23.300317 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8685 22:50:23.303533 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8686 22:50:23.306876 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8687 22:50:23.310306 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8688 22:50:23.316702 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8689 22:50:23.320236 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8690 22:50:23.323607 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8691 22:50:23.326609 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8692 22:50:23.330057 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8693 22:50:23.333296 ==
8694 22:50:23.336582 Dram Type= 6, Freq= 0, CH_1, rank 1
8695 22:50:23.339917 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8696 22:50:23.339990 ==
8697 22:50:23.340051 DQS Delay:
8698 22:50:23.343119 DQS0 = 0, DQS1 = 0
8699 22:50:23.343189 DQM Delay:
8700 22:50:23.346417 DQM0 = 127, DQM1 = 122
8701 22:50:23.346490 DQ Delay:
8702 22:50:23.349880 DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =124
8703 22:50:23.353365 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8704 22:50:23.356635 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8705 22:50:23.359870 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8706 22:50:23.359944
8707 22:50:23.360012
8708 22:50:23.360069
8709 22:50:23.362933 [DramC_TX_OE_Calibration] TA2
8710 22:50:23.366367 Original DQ_B0 (3 6) =30, OEN = 27
8711 22:50:23.369682 Original DQ_B1 (3 6) =30, OEN = 27
8712 22:50:23.373297 24, 0x0, End_B0=24 End_B1=24
8713 22:50:23.376741 25, 0x0, End_B0=25 End_B1=25
8714 22:50:23.376815 26, 0x0, End_B0=26 End_B1=26
8715 22:50:23.380070 27, 0x0, End_B0=27 End_B1=27
8716 22:50:23.382963 28, 0x0, End_B0=28 End_B1=28
8717 22:50:23.386247 29, 0x0, End_B0=29 End_B1=29
8718 22:50:23.389882 30, 0x0, End_B0=30 End_B1=30
8719 22:50:23.389962 31, 0x4141, End_B0=30 End_B1=30
8720 22:50:23.392992 Byte0 end_step=30 best_step=27
8721 22:50:23.396313 Byte1 end_step=30 best_step=27
8722 22:50:23.399757 Byte0 TX OE(2T, 0.5T) = (3, 3)
8723 22:50:23.403074 Byte1 TX OE(2T, 0.5T) = (3, 3)
8724 22:50:23.403152
8725 22:50:23.403213
8726 22:50:23.409392 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8727 22:50:23.412743 CH1 RK1: MR19=303, MR18=1B1B
8728 22:50:23.419323 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8729 22:50:23.422665 [RxdqsGatingPostProcess] freq 1600
8730 22:50:23.429107 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8731 22:50:23.432651 Pre-setting of DQS Precalculation
8732 22:50:23.435862 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8733 22:50:23.442559 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8734 22:50:23.449300 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8735 22:50:23.449371
8736 22:50:23.449437
8737 22:50:23.452714 [Calibration Summary] 3200 Mbps
8738 22:50:23.455701 CH 0, Rank 0
8739 22:50:23.455777 SW Impedance : PASS
8740 22:50:23.459006 DUTY Scan : NO K
8741 22:50:23.462217 ZQ Calibration : PASS
8742 22:50:23.462293 Jitter Meter : NO K
8743 22:50:23.465817 CBT Training : PASS
8744 22:50:23.468831 Write leveling : PASS
8745 22:50:23.468905 RX DQS gating : PASS
8746 22:50:23.472400 RX DQ/DQS(RDDQC) : PASS
8747 22:50:23.475612 TX DQ/DQS : PASS
8748 22:50:23.475686 RX DATLAT : PASS
8749 22:50:23.478953 RX DQ/DQS(Engine): PASS
8750 22:50:23.482246 TX OE : PASS
8751 22:50:23.482319 All Pass.
8752 22:50:23.482379
8753 22:50:23.482436 CH 0, Rank 1
8754 22:50:23.485524 SW Impedance : PASS
8755 22:50:23.488754 DUTY Scan : NO K
8756 22:50:23.488827 ZQ Calibration : PASS
8757 22:50:23.492058 Jitter Meter : NO K
8758 22:50:23.492137 CBT Training : PASS
8759 22:50:23.495592 Write leveling : PASS
8760 22:50:23.498547 RX DQS gating : PASS
8761 22:50:23.498627 RX DQ/DQS(RDDQC) : PASS
8762 22:50:23.502345 TX DQ/DQS : PASS
8763 22:50:23.505298 RX DATLAT : PASS
8764 22:50:23.505377 RX DQ/DQS(Engine): PASS
8765 22:50:23.508761 TX OE : PASS
8766 22:50:23.508841 All Pass.
8767 22:50:23.508903
8768 22:50:23.511946 CH 1, Rank 0
8769 22:50:23.512025 SW Impedance : PASS
8770 22:50:23.515128 DUTY Scan : NO K
8771 22:50:23.518461 ZQ Calibration : PASS
8772 22:50:23.518540 Jitter Meter : NO K
8773 22:50:23.522008 CBT Training : PASS
8774 22:50:23.525329 Write leveling : PASS
8775 22:50:23.525407 RX DQS gating : PASS
8776 22:50:23.528682 RX DQ/DQS(RDDQC) : PASS
8777 22:50:23.531866 TX DQ/DQS : PASS
8778 22:50:23.531947 RX DATLAT : PASS
8779 22:50:23.535158 RX DQ/DQS(Engine): PASS
8780 22:50:23.538545 TX OE : PASS
8781 22:50:23.538625 All Pass.
8782 22:50:23.538687
8783 22:50:23.538746 CH 1, Rank 1
8784 22:50:23.541781 SW Impedance : PASS
8785 22:50:23.545048 DUTY Scan : NO K
8786 22:50:23.545128 ZQ Calibration : PASS
8787 22:50:23.548310 Jitter Meter : NO K
8788 22:50:23.551724 CBT Training : PASS
8789 22:50:23.551804 Write leveling : PASS
8790 22:50:23.555226 RX DQS gating : PASS
8791 22:50:23.555306 RX DQ/DQS(RDDQC) : PASS
8792 22:50:23.558243 TX DQ/DQS : PASS
8793 22:50:23.561516 RX DATLAT : PASS
8794 22:50:23.561602 RX DQ/DQS(Engine): PASS
8795 22:50:23.564842 TX OE : PASS
8796 22:50:23.564926 All Pass.
8797 22:50:23.564988
8798 22:50:23.568389 DramC Write-DBI on
8799 22:50:23.572054 PER_BANK_REFRESH: Hybrid Mode
8800 22:50:23.572127 TX_TRACKING: ON
8801 22:50:23.581333 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8802 22:50:23.588122 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8803 22:50:23.598187 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8804 22:50:23.601242 [FAST_K] Save calibration result to emmc
8805 22:50:23.601318 sync common calibartion params.
8806 22:50:23.604455 sync cbt_mode0:0, 1:0
8807 22:50:23.607963 dram_init: ddr_geometry: 0
8808 22:50:23.611216 dram_init: ddr_geometry: 0
8809 22:50:23.611284 dram_init: ddr_geometry: 0
8810 22:50:23.614537 0:dram_rank_size:80000000
8811 22:50:23.617932 1:dram_rank_size:80000000
8812 22:50:23.621156 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8813 22:50:23.624462 DFS_SHUFFLE_HW_MODE: ON
8814 22:50:23.627764 dramc_set_vcore_voltage set vcore to 725000
8815 22:50:23.631491 Read voltage for 1600, 0
8816 22:50:23.631561 Vio18 = 0
8817 22:50:23.631620 Vcore = 725000
8818 22:50:23.634400 Vdram = 0
8819 22:50:23.634474 Vddq = 0
8820 22:50:23.634531 Vmddr = 0
8821 22:50:23.637741 switch to 3200 Mbps bootup
8822 22:50:23.641285 [DramcRunTimeConfig]
8823 22:50:23.641355 PHYPLL
8824 22:50:23.641414 DPM_CONTROL_AFTERK: ON
8825 22:50:23.644400 PER_BANK_REFRESH: ON
8826 22:50:23.647817 REFRESH_OVERHEAD_REDUCTION: ON
8827 22:50:23.647886 CMD_PICG_NEW_MODE: OFF
8828 22:50:23.650959 XRTWTW_NEW_MODE: ON
8829 22:50:23.654248 XRTRTR_NEW_MODE: ON
8830 22:50:23.654325 TX_TRACKING: ON
8831 22:50:23.657589 RDSEL_TRACKING: OFF
8832 22:50:23.657656 DQS Precalculation for DVFS: ON
8833 22:50:23.661346 RX_TRACKING: OFF
8834 22:50:23.661413 HW_GATING DBG: ON
8835 22:50:23.664124 ZQCS_ENABLE_LP4: ON
8836 22:50:23.664196 RX_PICG_NEW_MODE: ON
8837 22:50:23.667555 TX_PICG_NEW_MODE: ON
8838 22:50:23.670896 ENABLE_RX_DCM_DPHY: ON
8839 22:50:23.674356 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8840 22:50:23.674424 DUMMY_READ_FOR_TRACKING: OFF
8841 22:50:23.677779 !!! SPM_CONTROL_AFTERK: OFF
8842 22:50:23.681114 !!! SPM could not control APHY
8843 22:50:23.684399 IMPEDANCE_TRACKING: ON
8844 22:50:23.684473 TEMP_SENSOR: ON
8845 22:50:23.687475 HW_SAVE_FOR_SR: OFF
8846 22:50:23.687542 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8847 22:50:23.694326 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8848 22:50:23.694398 Read ODT Tracking: ON
8849 22:50:23.697636 Refresh Rate DeBounce: ON
8850 22:50:23.701212 DFS_NO_QUEUE_FLUSH: ON
8851 22:50:23.701289 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8852 22:50:23.704314 ENABLE_DFS_RUNTIME_MRW: OFF
8853 22:50:23.707268 DDR_RESERVE_NEW_MODE: ON
8854 22:50:23.711301 MR_CBT_SWITCH_FREQ: ON
8855 22:50:23.711369 =========================
8856 22:50:23.730056 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8857 22:50:23.733519 dram_init: ddr_geometry: 0
8858 22:50:23.751376 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8859 22:50:23.754603 dram_init: dram init end (result: 0)
8860 22:50:23.761290 DRAM-K: Full calibration passed in 23409 msecs
8861 22:50:23.764843 MRC: failed to locate region type 0.
8862 22:50:23.764944 DRAM rank0 size:0x80000000,
8863 22:50:23.767970 DRAM rank1 size=0x80000000
8864 22:50:23.777988 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8865 22:50:23.784541 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8866 22:50:23.791032 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8867 22:50:23.797713 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8868 22:50:23.801248 DRAM rank0 size:0x80000000,
8869 22:50:23.804396 DRAM rank1 size=0x80000000
8870 22:50:23.804467 CBMEM:
8871 22:50:23.807723 IMD: root @ 0xfffff000 254 entries.
8872 22:50:23.810985 IMD: root @ 0xffffec00 62 entries.
8873 22:50:23.814156 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8874 22:50:23.817621 WARNING: RO_VPD is uninitialized or empty.
8875 22:50:23.824011 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8876 22:50:23.831443 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8877 22:50:23.843758 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8878 22:50:23.855117 BS: romstage times (exec / console): total (unknown) / 22950 ms
8879 22:50:23.855192
8880 22:50:23.855254
8881 22:50:23.865141 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8882 22:50:23.868463 ARM64: Exception handlers installed.
8883 22:50:23.871978 ARM64: Testing exception
8884 22:50:23.874993 ARM64: Done test exception
8885 22:50:23.875096 Enumerating buses...
8886 22:50:23.878649 Show all devs... Before device enumeration.
8887 22:50:23.881702 Root Device: enabled 1
8888 22:50:23.885233 CPU_CLUSTER: 0: enabled 1
8889 22:50:23.885302 CPU: 00: enabled 1
8890 22:50:23.888641 Compare with tree...
8891 22:50:23.888709 Root Device: enabled 1
8892 22:50:23.891732 CPU_CLUSTER: 0: enabled 1
8893 22:50:23.895315 CPU: 00: enabled 1
8894 22:50:23.895384 Root Device scanning...
8895 22:50:23.898000 scan_static_bus for Root Device
8896 22:50:23.901410 CPU_CLUSTER: 0 enabled
8897 22:50:23.904695 scan_static_bus for Root Device done
8898 22:50:23.908182 scan_bus: bus Root Device finished in 8 msecs
8899 22:50:23.908252 done
8900 22:50:23.915102 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8901 22:50:23.918135 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8902 22:50:23.924626 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8903 22:50:23.928058 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8904 22:50:23.931159 Allocating resources...
8905 22:50:23.934461 Reading resources...
8906 22:50:23.938135 Root Device read_resources bus 0 link: 0
8907 22:50:23.938204 DRAM rank0 size:0x80000000,
8908 22:50:23.941497 DRAM rank1 size=0x80000000
8909 22:50:23.944601 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8910 22:50:23.948037 CPU: 00 missing read_resources
8911 22:50:23.954323 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8912 22:50:23.957840 Root Device read_resources bus 0 link: 0 done
8913 22:50:23.957917 Done reading resources.
8914 22:50:23.964434 Show resources in subtree (Root Device)...After reading.
8915 22:50:23.968082 Root Device child on link 0 CPU_CLUSTER: 0
8916 22:50:23.971182 CPU_CLUSTER: 0 child on link 0 CPU: 00
8917 22:50:23.981199 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8918 22:50:23.981273 CPU: 00
8919 22:50:23.984187 Root Device assign_resources, bus 0 link: 0
8920 22:50:23.987783 CPU_CLUSTER: 0 missing set_resources
8921 22:50:23.994142 Root Device assign_resources, bus 0 link: 0 done
8922 22:50:23.994216 Done setting resources.
8923 22:50:24.000709 Show resources in subtree (Root Device)...After assigning values.
8924 22:50:24.004037 Root Device child on link 0 CPU_CLUSTER: 0
8925 22:50:24.007351 CPU_CLUSTER: 0 child on link 0 CPU: 00
8926 22:50:24.017343 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8927 22:50:24.017422 CPU: 00
8928 22:50:24.021416 Done allocating resources.
8929 22:50:24.027162 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8930 22:50:24.027236 Enabling resources...
8931 22:50:24.027298 done.
8932 22:50:24.033868 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8933 22:50:24.033938 Initializing devices...
8934 22:50:24.037205 Root Device init
8935 22:50:24.037272 init hardware done!
8936 22:50:24.040471 0x00000018: ctrlr->caps
8937 22:50:24.043866 52.000 MHz: ctrlr->f_max
8938 22:50:24.043936 0.400 MHz: ctrlr->f_min
8939 22:50:24.046984 0x40ff8080: ctrlr->voltages
8940 22:50:24.050321 sclk: 390625
8941 22:50:24.050388 Bus Width = 1
8942 22:50:24.050452 sclk: 390625
8943 22:50:24.053674 Bus Width = 1
8944 22:50:24.053745 Early init status = 3
8945 22:50:24.060055 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8946 22:50:24.063405 in-header: 03 fc 00 00 01 00 00 00
8947 22:50:24.066684 in-data: 00
8948 22:50:24.069989 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8949 22:50:24.074568 in-header: 03 fd 00 00 00 00 00 00
8950 22:50:24.078011 in-data:
8951 22:50:24.081191 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8952 22:50:24.085480 in-header: 03 fc 00 00 01 00 00 00
8953 22:50:24.088729 in-data: 00
8954 22:50:24.091973 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8955 22:50:24.097765 in-header: 03 fd 00 00 00 00 00 00
8956 22:50:24.101158 in-data:
8957 22:50:24.104200 [SSUSB] Setting up USB HOST controller...
8958 22:50:24.107312 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8959 22:50:24.110825 [SSUSB] phy power-on done.
8960 22:50:24.114460 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8961 22:50:24.120659 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8962 22:50:24.123952 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8963 22:50:24.130703 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8964 22:50:24.137153 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8965 22:50:24.144232 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8966 22:50:24.150715 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8967 22:50:24.157121 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8968 22:50:24.160604 SPM: binary array size = 0x9dc
8969 22:50:24.164040 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8970 22:50:24.170336 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8971 22:50:24.176942 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8972 22:50:24.183646 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8973 22:50:24.186778 configure_display: Starting display init
8974 22:50:24.220750 anx7625_power_on_init: Init interface.
8975 22:50:24.224059 anx7625_disable_pd_protocol: Disabled PD feature.
8976 22:50:24.227520 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8977 22:50:24.254980 anx7625_start_dp_work: Secure OCM version=00
8978 22:50:24.259001 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8979 22:50:24.273492 sp_tx_get_edid_block: EDID Block = 1
8980 22:50:24.376078 Extracted contents:
8981 22:50:24.379099 header: 00 ff ff ff ff ff ff 00
8982 22:50:24.382524 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8983 22:50:24.385770 version: 01 04
8984 22:50:24.389013 basic params: 95 1f 11 78 0a
8985 22:50:24.392605 chroma info: 76 90 94 55 54 90 27 21 50 54
8986 22:50:24.395928 established: 00 00 00
8987 22:50:24.402345 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8988 22:50:24.405468 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8989 22:50:24.412382 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8990 22:50:24.418799 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8991 22:50:24.425517 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8992 22:50:24.428847 extensions: 00
8993 22:50:24.428918 checksum: fb
8994 22:50:24.428979
8995 22:50:24.432053 Manufacturer: IVO Model 57d Serial Number 0
8996 22:50:24.435644 Made week 0 of 2020
8997 22:50:24.435713 EDID version: 1.4
8998 22:50:24.438647 Digital display
8999 22:50:24.442242 6 bits per primary color channel
9000 22:50:24.442311 DisplayPort interface
9001 22:50:24.445171 Maximum image size: 31 cm x 17 cm
9002 22:50:24.448461 Gamma: 220%
9003 22:50:24.448535 Check DPMS levels
9004 22:50:24.451746 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9005 22:50:24.458427 First detailed timing is preferred timing
9006 22:50:24.458501 Established timings supported:
9007 22:50:24.461753 Standard timings supported:
9008 22:50:24.464948 Detailed timings
9009 22:50:24.468459 Hex of detail: 383680a07038204018303c0035ae10000019
9010 22:50:24.475111 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9011 22:50:24.478220 0780 0798 07c8 0820 hborder 0
9012 22:50:24.481862 0438 043b 0447 0458 vborder 0
9013 22:50:24.484996 -hsync -vsync
9014 22:50:24.485070 Did detailed timing
9015 22:50:24.491764 Hex of detail: 000000000000000000000000000000000000
9016 22:50:24.494902 Manufacturer-specified data, tag 0
9017 22:50:24.498404 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9018 22:50:24.501751 ASCII string: InfoVision
9019 22:50:24.505020 Hex of detail: 000000fe00523134304e574635205248200a
9020 22:50:24.508601 ASCII string: R140NWF5 RH
9021 22:50:24.508676 Checksum
9022 22:50:24.511920 Checksum: 0xfb (valid)
9023 22:50:24.515116 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9024 22:50:24.518128 DSI data_rate: 832800000 bps
9025 22:50:24.524821 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9026 22:50:24.528195 anx7625_parse_edid: pixelclock(138800).
9027 22:50:24.531550 hactive(1920), hsync(48), hfp(24), hbp(88)
9028 22:50:24.534627 vactive(1080), vsync(12), vfp(3), vbp(17)
9029 22:50:24.538092 anx7625_dsi_config: config dsi.
9030 22:50:24.544509 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9031 22:50:24.557821 anx7625_dsi_config: success to config DSI
9032 22:50:24.561140 anx7625_dp_start: MIPI phy setup OK.
9033 22:50:24.564533 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9034 22:50:24.567668 mtk_ddp_mode_set invalid vrefresh 60
9035 22:50:24.571268 main_disp_path_setup
9036 22:50:24.571341 ovl_layer_smi_id_en
9037 22:50:24.574211 ovl_layer_smi_id_en
9038 22:50:24.574298 ccorr_config
9039 22:50:24.574396 aal_config
9040 22:50:24.577384 gamma_config
9041 22:50:24.577451 postmask_config
9042 22:50:24.580970 dither_config
9043 22:50:24.584158 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9044 22:50:24.590868 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9045 22:50:24.594315 Root Device init finished in 553 msecs
9046 22:50:24.597414 CPU_CLUSTER: 0 init
9047 22:50:24.603976 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9048 22:50:24.610628 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9049 22:50:24.610704 APU_MBOX 0x190000b0 = 0x10001
9050 22:50:24.613981 APU_MBOX 0x190001b0 = 0x10001
9051 22:50:24.617435 APU_MBOX 0x190005b0 = 0x10001
9052 22:50:24.620636 APU_MBOX 0x190006b0 = 0x10001
9053 22:50:24.627009 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9054 22:50:24.636704 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9055 22:50:24.649455 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9056 22:50:24.655897 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9057 22:50:24.667543 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9058 22:50:24.676565 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9059 22:50:24.680149 CPU_CLUSTER: 0 init finished in 81 msecs
9060 22:50:24.683129 Devices initialized
9061 22:50:24.686704 Show all devs... After init.
9062 22:50:24.686773 Root Device: enabled 1
9063 22:50:24.689705 CPU_CLUSTER: 0: enabled 1
9064 22:50:24.692964 CPU: 00: enabled 1
9065 22:50:24.696319 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9066 22:50:24.699643 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9067 22:50:24.702950 ELOG: NV offset 0x57f000 size 0x1000
9068 22:50:24.709638 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9069 22:50:24.716737 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9070 22:50:24.719692 ELOG: Event(17) added with size 13 at 2024-05-07 22:50:26 UTC
9071 22:50:24.722987 out: cmd=0x121: 03 db 21 01 00 00 00 00
9072 22:50:24.728062 in-header: 03 02 00 00 2c 00 00 00
9073 22:50:24.741498 in-data: 61 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9074 22:50:24.747793 ELOG: Event(A1) added with size 10 at 2024-05-07 22:50:26 UTC
9075 22:50:24.754817 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9076 22:50:24.760969 ELOG: Event(A0) added with size 9 at 2024-05-07 22:50:26 UTC
9077 22:50:24.764448 elog_add_boot_reason: Logged dev mode boot
9078 22:50:24.768014 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9079 22:50:24.770899 Finalize devices...
9080 22:50:24.770973 Devices finalized
9081 22:50:24.777573 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9082 22:50:24.780825 Writing coreboot table at 0xffe64000
9083 22:50:24.784139 0. 000000000010a000-0000000000113fff: RAMSTAGE
9084 22:50:24.787418 1. 0000000040000000-00000000400fffff: RAM
9085 22:50:24.794370 2. 0000000040100000-000000004032afff: RAMSTAGE
9086 22:50:24.797510 3. 000000004032b000-00000000545fffff: RAM
9087 22:50:24.800986 4. 0000000054600000-000000005465ffff: BL31
9088 22:50:24.804082 5. 0000000054660000-00000000ffe63fff: RAM
9089 22:50:24.810737 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9090 22:50:24.813997 7. 0000000100000000-000000013fffffff: RAM
9091 22:50:24.814093 Passing 5 GPIOs to payload:
9092 22:50:24.820685 NAME | PORT | POLARITY | VALUE
9093 22:50:24.823959 EC in RW | 0x000000aa | low | undefined
9094 22:50:24.830777 EC interrupt | 0x00000005 | low | undefined
9095 22:50:24.834150 TPM interrupt | 0x000000ab | high | undefined
9096 22:50:24.840911 SD card detect | 0x00000011 | high | undefined
9097 22:50:24.843941 speaker enable | 0x00000093 | high | undefined
9098 22:50:24.847262 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9099 22:50:24.850854 in-header: 03 f4 00 00 02 00 00 00
9100 22:50:24.850922 in-data: 07 00
9101 22:50:24.853935 ADC[4]: Raw value=668222 ID=5
9102 22:50:24.857124 ADC[3]: Raw value=212549 ID=1
9103 22:50:24.860421 RAM Code: 0x51
9104 22:50:24.860494 ADC[6]: Raw value=74410 ID=0
9105 22:50:24.864173 ADC[5]: Raw value=211444 ID=1
9106 22:50:24.867140 SKU Code: 0x1
9107 22:50:24.870465 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 212a
9108 22:50:24.873792 coreboot table: 964 bytes.
9109 22:50:24.876953 IMD ROOT 0. 0xfffff000 0x00001000
9110 22:50:24.880186 IMD SMALL 1. 0xffffe000 0x00001000
9111 22:50:24.883485 RO MCACHE 2. 0xffffc000 0x00001104
9112 22:50:24.886842 CONSOLE 3. 0xfff7c000 0x00080000
9113 22:50:24.890061 FMAP 4. 0xfff7b000 0x00000452
9114 22:50:24.893585 TIME STAMP 5. 0xfff7a000 0x00000910
9115 22:50:24.896807 VBOOT WORK 6. 0xfff66000 0x00014000
9116 22:50:24.900332 RAMOOPS 7. 0xffe66000 0x00100000
9117 22:50:24.903294 COREBOOT 8. 0xffe64000 0x00002000
9118 22:50:24.903363 IMD small region:
9119 22:50:24.906650 IMD ROOT 0. 0xffffec00 0x00000400
9120 22:50:24.910174 VPD 1. 0xffffeb80 0x0000006c
9121 22:50:24.916454 MMC STATUS 2. 0xffffeb60 0x00000004
9122 22:50:24.919960 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9123 22:50:24.923276 Probing TPM: done!
9124 22:50:24.926838 Connected to device vid:did:rid of 1ae0:0028:00
9125 22:50:24.936740 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9126 22:50:24.939963 Initialized TPM device CR50 revision 0
9127 22:50:24.943433 Checking cr50 for pending updates
9128 22:50:24.947248 Reading cr50 TPM mode
9129 22:50:24.956016 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9130 22:50:24.962547 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9131 22:50:25.002561 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9132 22:50:25.005979 Checking segment from ROM address 0x40100000
9133 22:50:25.009701 Checking segment from ROM address 0x4010001c
9134 22:50:25.015924 Loading segment from ROM address 0x40100000
9135 22:50:25.016006 code (compression=0)
9136 22:50:25.025741 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9137 22:50:25.032420 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9138 22:50:25.032493 it's not compressed!
9139 22:50:25.039033 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9140 22:50:25.045770 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9141 22:50:25.063063 Loading segment from ROM address 0x4010001c
9142 22:50:25.063138 Entry Point 0x80000000
9143 22:50:25.066375 Loaded segments
9144 22:50:25.069868 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9145 22:50:25.076572 Jumping to boot code at 0x80000000(0xffe64000)
9146 22:50:25.083300 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9147 22:50:25.089823 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9148 22:50:25.097417 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9149 22:50:25.100609 Checking segment from ROM address 0x40100000
9150 22:50:25.103867 Checking segment from ROM address 0x4010001c
9151 22:50:25.110700 Loading segment from ROM address 0x40100000
9152 22:50:25.110773 code (compression=1)
9153 22:50:25.117463 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9154 22:50:25.127313 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9155 22:50:25.127390 using LZMA
9156 22:50:25.135714 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9157 22:50:25.142500 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9158 22:50:25.145691 Loading segment from ROM address 0x4010001c
9159 22:50:25.145760 Entry Point 0x54601000
9160 22:50:25.149009 Loaded segments
9161 22:50:25.152312 NOTICE: MT8192 bl31_setup
9162 22:50:25.159567 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9163 22:50:25.162737 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9164 22:50:25.166146 WARNING: region 0:
9165 22:50:25.169327 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9166 22:50:25.169397 WARNING: region 1:
9167 22:50:25.176228 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9168 22:50:25.179493 WARNING: region 2:
9169 22:50:25.182892 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9170 22:50:25.186199 WARNING: region 3:
9171 22:50:25.189288 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9172 22:50:25.193020 WARNING: region 4:
9173 22:50:25.199556 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9174 22:50:25.199628 WARNING: region 5:
9175 22:50:25.202751 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9176 22:50:25.206346 WARNING: region 6:
9177 22:50:25.209508 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9178 22:50:25.212991 WARNING: region 7:
9179 22:50:25.215942 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 22:50:25.222818 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9181 22:50:25.225873 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9182 22:50:25.229499 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9183 22:50:25.236094 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9184 22:50:25.239459 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9185 22:50:25.242776 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9186 22:50:25.249101 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9187 22:50:25.252493 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9188 22:50:25.259040 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9189 22:50:25.262474 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9190 22:50:25.265653 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9191 22:50:25.272345 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9192 22:50:25.275744 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9193 22:50:25.279372 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9194 22:50:25.285553 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9195 22:50:25.289240 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9196 22:50:25.295586 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9197 22:50:25.299070 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9198 22:50:25.302355 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9199 22:50:25.308873 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9200 22:50:25.312320 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9201 22:50:25.315636 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9202 22:50:25.322573 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9203 22:50:25.325775 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9204 22:50:25.332413 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9205 22:50:25.335503 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9206 22:50:25.339103 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9207 22:50:25.345633 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9208 22:50:25.349257 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9209 22:50:25.355789 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9210 22:50:25.359043 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9211 22:50:25.362733 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9212 22:50:25.369067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9213 22:50:25.372696 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9214 22:50:25.375515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9215 22:50:25.378991 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9216 22:50:25.385679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9217 22:50:25.388943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9218 22:50:25.392272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9219 22:50:25.395961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9220 22:50:25.402501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9221 22:50:25.406130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9222 22:50:25.408994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9223 22:50:25.412241 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9224 22:50:25.418972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9225 22:50:25.422251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9226 22:50:25.425569 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9227 22:50:25.429073 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9228 22:50:25.435463 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9229 22:50:25.438938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9230 22:50:25.445406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9231 22:50:25.449068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9232 22:50:25.455722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9233 22:50:25.458749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9234 22:50:25.462246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9235 22:50:25.469147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9236 22:50:25.472281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9237 22:50:25.479036 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9238 22:50:25.482159 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9239 22:50:25.488764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9240 22:50:25.492855 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9241 22:50:25.495383 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9242 22:50:25.502226 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9243 22:50:25.505477 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9244 22:50:25.512124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9245 22:50:25.515593 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9246 22:50:25.522346 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9247 22:50:25.525491 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9248 22:50:25.528669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9249 22:50:25.535814 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9250 22:50:25.539115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9251 22:50:25.545582 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9252 22:50:25.548883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9253 22:50:25.555484 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9254 22:50:25.558885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9255 22:50:25.562338 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9256 22:50:25.569005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9257 22:50:25.572295 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9258 22:50:25.579093 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9259 22:50:25.582211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9260 22:50:25.588909 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9261 22:50:25.592106 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9262 22:50:25.599000 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9263 22:50:25.602276 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9264 22:50:25.605274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9265 22:50:25.612177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9266 22:50:25.615505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9267 22:50:25.622418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9268 22:50:25.625411 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9269 22:50:25.632162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9270 22:50:25.635579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9271 22:50:25.638832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9272 22:50:25.645350 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9273 22:50:25.648910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9274 22:50:25.655482 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9275 22:50:25.659138 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9276 22:50:25.661896 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9277 22:50:25.668836 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9278 22:50:25.672059 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9279 22:50:25.675113 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9280 22:50:25.678821 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9281 22:50:25.685881 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9282 22:50:25.688612 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9283 22:50:25.695677 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9284 22:50:25.698377 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9285 22:50:25.701920 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9286 22:50:25.708491 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9287 22:50:25.711937 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9288 22:50:25.718715 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9289 22:50:25.721849 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9290 22:50:25.725262 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9291 22:50:25.731828 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9292 22:50:25.735038 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9293 22:50:25.741727 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9294 22:50:25.745225 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9295 22:50:25.748450 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9296 22:50:25.755410 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9297 22:50:25.758852 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9298 22:50:25.761909 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9299 22:50:25.768752 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9300 22:50:25.772247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9301 22:50:25.775486 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9302 22:50:25.779290 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9303 22:50:25.782215 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9304 22:50:25.788793 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9305 22:50:25.791838 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9306 22:50:25.798546 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9307 22:50:25.801775 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9308 22:50:25.805391 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9309 22:50:25.811775 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9310 22:50:25.815356 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9311 22:50:25.821836 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9312 22:50:25.825224 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9313 22:50:25.828395 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9314 22:50:25.835281 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9315 22:50:25.838504 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9316 22:50:25.844904 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9317 22:50:25.848465 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9318 22:50:25.851845 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9319 22:50:25.858570 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9320 22:50:25.861730 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9321 22:50:25.864964 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9322 22:50:25.871813 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9323 22:50:25.875059 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9324 22:50:25.881640 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9325 22:50:25.885090 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9326 22:50:25.888260 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9327 22:50:25.894982 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9328 22:50:25.898149 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9329 22:50:25.905100 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9330 22:50:25.908378 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9331 22:50:25.911531 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9332 22:50:25.918228 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9333 22:50:25.921611 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9334 22:50:25.928286 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9335 22:50:25.931652 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9336 22:50:25.934966 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9337 22:50:25.941760 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9338 22:50:25.944746 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9339 22:50:25.951400 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9340 22:50:25.954627 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9341 22:50:25.957911 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9342 22:50:25.964691 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9343 22:50:25.968035 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9344 22:50:25.974418 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9345 22:50:25.977990 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9346 22:50:25.981235 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9347 22:50:25.988144 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9348 22:50:25.991324 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9349 22:50:25.994499 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9350 22:50:26.001043 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9351 22:50:26.004483 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9352 22:50:26.011164 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9353 22:50:26.014524 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9354 22:50:26.017976 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9355 22:50:26.024565 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9356 22:50:26.027734 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9357 22:50:26.034912 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9358 22:50:26.037978 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9359 22:50:26.041351 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9360 22:50:26.047796 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9361 22:50:26.051294 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9362 22:50:26.054332 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9363 22:50:26.060973 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9364 22:50:26.064251 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9365 22:50:26.070877 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9366 22:50:26.074202 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9367 22:50:26.077818 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9368 22:50:26.084324 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9369 22:50:26.087534 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9370 22:50:26.094056 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9371 22:50:26.097488 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9372 22:50:26.104247 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9373 22:50:26.107494 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9374 22:50:26.110835 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9375 22:50:26.117419 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9376 22:50:26.120712 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9377 22:50:26.127740 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9378 22:50:26.130526 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9379 22:50:26.137063 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9380 22:50:26.140635 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9381 22:50:26.143659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9382 22:50:26.150308 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9383 22:50:26.153801 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9384 22:50:26.160375 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9385 22:50:26.163572 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9386 22:50:26.169976 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9387 22:50:26.173344 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9388 22:50:26.176678 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9389 22:50:26.183480 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9390 22:50:26.186887 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9391 22:50:26.193023 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9392 22:50:26.196478 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9393 22:50:26.203264 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9394 22:50:26.206264 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9395 22:50:26.209653 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9396 22:50:26.216234 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9397 22:50:26.219490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9398 22:50:26.226878 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9399 22:50:26.229484 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9400 22:50:26.233209 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9401 22:50:26.239546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9402 22:50:26.243324 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9403 22:50:26.249488 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9404 22:50:26.252962 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9405 22:50:26.259421 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9406 22:50:26.262731 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9407 22:50:26.265920 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9408 22:50:26.272590 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9409 22:50:26.276346 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9410 22:50:26.279327 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9411 22:50:26.282715 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9412 22:50:26.289020 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9413 22:50:26.292507 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9414 22:50:26.296171 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9415 22:50:26.302909 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9416 22:50:26.305759 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9417 22:50:26.312442 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9418 22:50:26.315534 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9419 22:50:26.318903 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9420 22:50:26.325732 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9421 22:50:26.328830 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9422 22:50:26.331812 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9423 22:50:26.338543 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9424 22:50:26.341989 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9425 22:50:26.345369 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9426 22:50:26.351949 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9427 22:50:26.355302 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9428 22:50:26.358604 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9429 22:50:26.365430 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9430 22:50:26.368442 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9431 22:50:26.375199 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9432 22:50:26.378623 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9433 22:50:26.382217 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9434 22:50:26.388367 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9435 22:50:26.391615 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9436 22:50:26.398095 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9437 22:50:26.401589 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9438 22:50:26.404812 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9439 22:50:26.411409 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9440 22:50:26.415159 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9441 22:50:26.418197 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9442 22:50:26.424808 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9443 22:50:26.428085 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9444 22:50:26.431511 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9445 22:50:26.437747 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9446 22:50:26.441297 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9447 22:50:26.447730 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9448 22:50:26.451489 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9449 22:50:26.454300 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9450 22:50:26.457849 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9451 22:50:26.464351 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9452 22:50:26.467983 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9453 22:50:26.470952 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9454 22:50:26.474499 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9455 22:50:26.477915 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9456 22:50:26.484193 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9457 22:50:26.487639 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9458 22:50:26.491045 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9459 22:50:26.494178 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9460 22:50:26.501043 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9461 22:50:26.504342 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9462 22:50:26.510814 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9463 22:50:26.514517 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9464 22:50:26.517672 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9465 22:50:26.524013 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9466 22:50:26.527491 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9467 22:50:26.533853 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9468 22:50:26.537366 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9469 22:50:26.540514 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9470 22:50:26.546978 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9471 22:50:26.550443 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9472 22:50:26.557046 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9473 22:50:26.560595 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9474 22:50:26.567058 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9475 22:50:26.570526 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9476 22:50:26.573845 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9477 22:50:26.580211 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9478 22:50:26.583671 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9479 22:50:26.590459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9480 22:50:26.593479 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9481 22:50:26.596758 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9482 22:50:26.603419 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9483 22:50:26.606737 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9484 22:50:26.613362 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9485 22:50:26.616598 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9486 22:50:26.620007 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9487 22:50:26.626667 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9488 22:50:26.630259 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9489 22:50:26.636560 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9490 22:50:26.639893 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9491 22:50:26.646472 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9492 22:50:26.649781 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9493 22:50:26.653020 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9494 22:50:26.659855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9495 22:50:26.662968 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9496 22:50:26.669585 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9497 22:50:26.672879 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9498 22:50:26.676639 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9499 22:50:26.682786 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9500 22:50:26.686055 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9501 22:50:26.693061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9502 22:50:26.696103 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9503 22:50:26.702467 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9504 22:50:26.705919 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9505 22:50:26.709257 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9506 22:50:26.715832 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9507 22:50:26.719429 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9508 22:50:26.726045 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9509 22:50:26.729002 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9510 22:50:26.732740 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9511 22:50:26.739402 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9512 22:50:26.742336 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9513 22:50:26.749147 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9514 22:50:26.752213 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9515 22:50:26.758939 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9516 22:50:26.762153 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9517 22:50:26.765527 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9518 22:50:26.772297 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9519 22:50:26.775457 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9520 22:50:26.778929 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9521 22:50:26.785919 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9522 22:50:26.788968 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9523 22:50:26.795769 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9524 22:50:26.798774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9525 22:50:26.801990 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9526 22:50:26.812604 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9527 22:50:26.812685 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9528 22:50:26.818556 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9529 22:50:26.821872 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9530 22:50:26.828546 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9531 22:50:26.831733 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9532 22:50:26.838533 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9533 22:50:26.841930 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9534 22:50:26.845145 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9535 22:50:26.851547 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9536 22:50:26.855243 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9537 22:50:26.861817 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9538 22:50:26.864760 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9539 22:50:26.871732 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9540 22:50:26.874975 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9541 22:50:26.878134 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9542 22:50:26.884859 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9543 22:50:26.888083 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9544 22:50:26.895064 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9545 22:50:26.898410 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9546 22:50:26.904981 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9547 22:50:26.908118 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9548 22:50:26.911375 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9549 22:50:26.918082 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9550 22:50:26.921727 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9551 22:50:26.927984 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9552 22:50:26.931186 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9553 22:50:26.937669 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9554 22:50:26.941545 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9555 22:50:26.947831 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9556 22:50:26.951212 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9557 22:50:26.954414 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9558 22:50:26.961311 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9559 22:50:26.964381 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9560 22:50:26.970830 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9561 22:50:26.974414 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9562 22:50:26.981003 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9563 22:50:26.984116 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9564 22:50:26.987367 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9565 22:50:26.994052 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9566 22:50:26.997866 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9567 22:50:27.004112 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9568 22:50:27.007483 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9569 22:50:27.014129 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9570 22:50:27.017378 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9571 22:50:27.024266 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9572 22:50:27.027226 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9573 22:50:27.030515 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9574 22:50:27.037172 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9575 22:50:27.040433 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9576 22:50:27.047272 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9577 22:50:27.050446 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9578 22:50:27.057018 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9579 22:50:27.060374 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9580 22:50:27.063761 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9581 22:50:27.070296 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9582 22:50:27.073960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9583 22:50:27.080322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9584 22:50:27.083697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9585 22:50:27.090011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9586 22:50:27.093662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9587 22:50:27.096804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9588 22:50:27.103204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9589 22:50:27.106951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9590 22:50:27.113178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9591 22:50:27.116484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9592 22:50:27.123348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9593 22:50:27.126650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9594 22:50:27.133124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9595 22:50:27.136426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9596 22:50:27.143410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9597 22:50:27.146327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9598 22:50:27.153183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9599 22:50:27.156316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9600 22:50:27.163075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9601 22:50:27.166521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9602 22:50:27.173073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9603 22:50:27.176414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9604 22:50:27.183017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9605 22:50:27.186497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9606 22:50:27.192713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9607 22:50:27.196173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9608 22:50:27.202785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9609 22:50:27.205951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9610 22:50:27.212730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9611 22:50:27.216182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9612 22:50:27.222510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9613 22:50:27.226151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9614 22:50:27.232971 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9615 22:50:27.233050 INFO: [APUAPC] vio 0
9616 22:50:27.239141 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9617 22:50:27.242499 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9618 22:50:27.246222 INFO: [APUAPC] D0_APC_0: 0x400510
9619 22:50:27.249097 INFO: [APUAPC] D0_APC_1: 0x0
9620 22:50:27.252449 INFO: [APUAPC] D0_APC_2: 0x1540
9621 22:50:27.255821 INFO: [APUAPC] D0_APC_3: 0x0
9622 22:50:27.259096 INFO: [APUAPC] D1_APC_0: 0xffffffff
9623 22:50:27.262263 INFO: [APUAPC] D1_APC_1: 0xffffffff
9624 22:50:27.265790 INFO: [APUAPC] D1_APC_2: 0x3fffff
9625 22:50:27.268967 INFO: [APUAPC] D1_APC_3: 0x0
9626 22:50:27.272447 INFO: [APUAPC] D2_APC_0: 0xffffffff
9627 22:50:27.275398 INFO: [APUAPC] D2_APC_1: 0xffffffff
9628 22:50:27.278795 INFO: [APUAPC] D2_APC_2: 0x3fffff
9629 22:50:27.281940 INFO: [APUAPC] D2_APC_3: 0x0
9630 22:50:27.285321 INFO: [APUAPC] D3_APC_0: 0xffffffff
9631 22:50:27.288691 INFO: [APUAPC] D3_APC_1: 0xffffffff
9632 22:50:27.292239 INFO: [APUAPC] D3_APC_2: 0x3fffff
9633 22:50:27.295266 INFO: [APUAPC] D3_APC_3: 0x0
9634 22:50:27.298640 INFO: [APUAPC] D4_APC_0: 0xffffffff
9635 22:50:27.302015 INFO: [APUAPC] D4_APC_1: 0xffffffff
9636 22:50:27.305272 INFO: [APUAPC] D4_APC_2: 0x3fffff
9637 22:50:27.308443 INFO: [APUAPC] D4_APC_3: 0x0
9638 22:50:27.312321 INFO: [APUAPC] D5_APC_0: 0xffffffff
9639 22:50:27.314967 INFO: [APUAPC] D5_APC_1: 0xffffffff
9640 22:50:27.318528 INFO: [APUAPC] D5_APC_2: 0x3fffff
9641 22:50:27.321752 INFO: [APUAPC] D5_APC_3: 0x0
9642 22:50:27.325111 INFO: [APUAPC] D6_APC_0: 0xffffffff
9643 22:50:27.328316 INFO: [APUAPC] D6_APC_1: 0xffffffff
9644 22:50:27.331483 INFO: [APUAPC] D6_APC_2: 0x3fffff
9645 22:50:27.331555 INFO: [APUAPC] D6_APC_3: 0x0
9646 22:50:27.335173 INFO: [APUAPC] D7_APC_0: 0xffffffff
9647 22:50:27.341532 INFO: [APUAPC] D7_APC_1: 0xffffffff
9648 22:50:27.344874 INFO: [APUAPC] D7_APC_2: 0x3fffff
9649 22:50:27.344953 INFO: [APUAPC] D7_APC_3: 0x0
9650 22:50:27.348082 INFO: [APUAPC] D8_APC_0: 0xffffffff
9651 22:50:27.351397 INFO: [APUAPC] D8_APC_1: 0xffffffff
9652 22:50:27.355295 INFO: [APUAPC] D8_APC_2: 0x3fffff
9653 22:50:27.358159 INFO: [APUAPC] D8_APC_3: 0x0
9654 22:50:27.361443 INFO: [APUAPC] D9_APC_0: 0xffffffff
9655 22:50:27.364657 INFO: [APUAPC] D9_APC_1: 0xffffffff
9656 22:50:27.367954 INFO: [APUAPC] D9_APC_2: 0x3fffff
9657 22:50:27.371704 INFO: [APUAPC] D9_APC_3: 0x0
9658 22:50:27.374547 INFO: [APUAPC] D10_APC_0: 0xffffffff
9659 22:50:27.377863 INFO: [APUAPC] D10_APC_1: 0xffffffff
9660 22:50:27.381382 INFO: [APUAPC] D10_APC_2: 0x3fffff
9661 22:50:27.384674 INFO: [APUAPC] D10_APC_3: 0x0
9662 22:50:27.388316 INFO: [APUAPC] D11_APC_0: 0xffffffff
9663 22:50:27.391573 INFO: [APUAPC] D11_APC_1: 0xffffffff
9664 22:50:27.394524 INFO: [APUAPC] D11_APC_2: 0x3fffff
9665 22:50:27.398103 INFO: [APUAPC] D11_APC_3: 0x0
9666 22:50:27.401138 INFO: [APUAPC] D12_APC_0: 0xffffffff
9667 22:50:27.404741 INFO: [APUAPC] D12_APC_1: 0xffffffff
9668 22:50:27.408088 INFO: [APUAPC] D12_APC_2: 0x3fffff
9669 22:50:27.411525 INFO: [APUAPC] D12_APC_3: 0x0
9670 22:50:27.414571 INFO: [APUAPC] D13_APC_0: 0xffffffff
9671 22:50:27.417848 INFO: [APUAPC] D13_APC_1: 0xffffffff
9672 22:50:27.421090 INFO: [APUAPC] D13_APC_2: 0x3fffff
9673 22:50:27.424501 INFO: [APUAPC] D13_APC_3: 0x0
9674 22:50:27.427538 INFO: [APUAPC] D14_APC_0: 0xffffffff
9675 22:50:27.431031 INFO: [APUAPC] D14_APC_1: 0xffffffff
9676 22:50:27.434295 INFO: [APUAPC] D14_APC_2: 0x3fffff
9677 22:50:27.437679 INFO: [APUAPC] D14_APC_3: 0x0
9678 22:50:27.440879 INFO: [APUAPC] D15_APC_0: 0xffffffff
9679 22:50:27.447876 INFO: [APUAPC] D15_APC_1: 0xffffffff
9680 22:50:27.450905 INFO: [APUAPC] D15_APC_2: 0x3fffff
9681 22:50:27.450981 INFO: [APUAPC] D15_APC_3: 0x0
9682 22:50:27.454537 INFO: [APUAPC] APC_CON: 0x4
9683 22:50:27.457572 INFO: [NOCDAPC] D0_APC_0: 0x0
9684 22:50:27.460878 INFO: [NOCDAPC] D0_APC_1: 0x0
9685 22:50:27.464225 INFO: [NOCDAPC] D1_APC_0: 0x0
9686 22:50:27.467556 INFO: [NOCDAPC] D1_APC_1: 0xfff
9687 22:50:27.470931 INFO: [NOCDAPC] D2_APC_0: 0x0
9688 22:50:27.474422 INFO: [NOCDAPC] D2_APC_1: 0xfff
9689 22:50:27.474495 INFO: [NOCDAPC] D3_APC_0: 0x0
9690 22:50:27.477660 INFO: [NOCDAPC] D3_APC_1: 0xfff
9691 22:50:27.480880 INFO: [NOCDAPC] D4_APC_0: 0x0
9692 22:50:27.484010 INFO: [NOCDAPC] D4_APC_1: 0xfff
9693 22:50:27.487460 INFO: [NOCDAPC] D5_APC_0: 0x0
9694 22:50:27.490770 INFO: [NOCDAPC] D5_APC_1: 0xfff
9695 22:50:27.494172 INFO: [NOCDAPC] D6_APC_0: 0x0
9696 22:50:27.497796 INFO: [NOCDAPC] D6_APC_1: 0xfff
9697 22:50:27.500698 INFO: [NOCDAPC] D7_APC_0: 0x0
9698 22:50:27.503871 INFO: [NOCDAPC] D7_APC_1: 0xfff
9699 22:50:27.507616 INFO: [NOCDAPC] D8_APC_0: 0x0
9700 22:50:27.510762 INFO: [NOCDAPC] D8_APC_1: 0xfff
9701 22:50:27.510833 INFO: [NOCDAPC] D9_APC_0: 0x0
9702 22:50:27.514000 INFO: [NOCDAPC] D9_APC_1: 0xfff
9703 22:50:27.517295 INFO: [NOCDAPC] D10_APC_0: 0x0
9704 22:50:27.520844 INFO: [NOCDAPC] D10_APC_1: 0xfff
9705 22:50:27.524024 INFO: [NOCDAPC] D11_APC_0: 0x0
9706 22:50:27.527483 INFO: [NOCDAPC] D11_APC_1: 0xfff
9707 22:50:27.530609 INFO: [NOCDAPC] D12_APC_0: 0x0
9708 22:50:27.533937 INFO: [NOCDAPC] D12_APC_1: 0xfff
9709 22:50:27.537303 INFO: [NOCDAPC] D13_APC_0: 0x0
9710 22:50:27.540377 INFO: [NOCDAPC] D13_APC_1: 0xfff
9711 22:50:27.543657 INFO: [NOCDAPC] D14_APC_0: 0x0
9712 22:50:27.547233 INFO: [NOCDAPC] D14_APC_1: 0xfff
9713 22:50:27.550721 INFO: [NOCDAPC] D15_APC_0: 0x0
9714 22:50:27.553731 INFO: [NOCDAPC] D15_APC_1: 0xfff
9715 22:50:27.553805 INFO: [NOCDAPC] APC_CON: 0x4
9716 22:50:27.556937 INFO: [APUAPC] set_apusys_apc done
9717 22:50:27.560577 INFO: [DEVAPC] devapc_init done
9718 22:50:27.567258 INFO: GICv3 without legacy support detected.
9719 22:50:27.570465 INFO: ARM GICv3 driver initialized in EL3
9720 22:50:27.573647 INFO: Maximum SPI INTID supported: 639
9721 22:50:27.576988 INFO: BL31: Initializing runtime services
9722 22:50:27.583500 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9723 22:50:27.587171 INFO: SPM: enable CPC mode
9724 22:50:27.590418 INFO: mcdi ready for mcusys-off-idle and system suspend
9725 22:50:27.596977 INFO: BL31: Preparing for EL3 exit to normal world
9726 22:50:27.600030 INFO: Entry point address = 0x80000000
9727 22:50:27.600107 INFO: SPSR = 0x8
9728 22:50:27.607763
9729 22:50:27.607841
9730 22:50:27.607918
9731 22:50:27.610475 Starting depthcharge on Spherion...
9732 22:50:27.610569
9733 22:50:27.610647 Wipe memory regions:
9734 22:50:27.610720
9735 22:50:27.611388 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9736 22:50:27.611499 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9737 22:50:27.611587 Setting prompt string to ['asurada:']
9738 22:50:27.611676 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9739 22:50:27.613790 [0x00000040000000, 0x00000054600000)
9740 22:50:27.736294
9741 22:50:27.736414 [0x00000054660000, 0x00000080000000)
9742 22:50:27.996911
9743 22:50:27.997060 [0x000000821a7280, 0x000000ffe64000)
9744 22:50:28.741709
9745 22:50:28.741844 [0x00000100000000, 0x00000140000000)
9746 22:50:29.123254
9747 22:50:29.126119 Initializing XHCI USB controller at 0x11200000.
9748 22:50:30.164076
9749 22:50:30.167105 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9750 22:50:30.167185
9751 22:50:30.167268
9752 22:50:30.167342
9753 22:50:30.167662 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9755 22:50:30.268025 asurada: tftpboot 192.168.201.1 13683663/tftp-deploy-80lgk2y2/kernel/image.itb 13683663/tftp-deploy-80lgk2y2/kernel/cmdline
9756 22:50:30.268161 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9757 22:50:30.268258 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9758 22:50:30.272183 tftpboot 192.168.201.1 13683663/tftp-deploy-80lgk2y2/kernel/image.itbtp-deploy-80lgk2y2/kernel/cmdline
9759 22:50:30.272270
9760 22:50:30.272350 Waiting for link
9761 22:50:30.432594
9762 22:50:30.432727 R8152: Initializing
9763 22:50:30.432823
9764 22:50:30.436107 Version 9 (ocp_data = 6010)
9765 22:50:30.436183
9766 22:50:30.439060 R8152: Done initializing
9767 22:50:30.439140
9768 22:50:30.439221 Adding net device
9769 22:50:32.451322
9770 22:50:32.451457 done.
9771 22:50:32.451561
9772 22:50:32.451660 MAC: 00:e0:4c:68:03:bd
9773 22:50:32.451757
9774 22:50:32.454856 Sending DHCP discover... done.
9775 22:50:32.454942
9776 22:50:32.457926 Waiting for reply... done.
9777 22:50:32.458041
9778 22:50:32.461345 Sending DHCP request... done.
9779 22:50:32.461417
9780 22:50:32.461479 Waiting for reply... done.
9781 22:50:32.461541
9782 22:50:32.464828 My ip is 192.168.201.16
9783 22:50:32.464899
9784 22:50:32.468462 The DHCP server ip is 192.168.201.1
9785 22:50:32.468536
9786 22:50:32.471439 TFTP server IP predefined by user: 192.168.201.1
9787 22:50:32.471512
9788 22:50:32.477920 Bootfile predefined by user: 13683663/tftp-deploy-80lgk2y2/kernel/image.itb
9789 22:50:32.478035
9790 22:50:32.481212 Sending tftp read request... done.
9791 22:50:32.481282
9792 22:50:32.484716 Waiting for the transfer...
9793 22:50:32.484791
9794 22:50:32.753412 00000000 ################################################################
9795 22:50:32.753543
9796 22:50:33.004716 00080000 ################################################################
9797 22:50:33.004842
9798 22:50:33.260006 00100000 ################################################################
9799 22:50:33.260134
9800 22:50:33.519273 00180000 ################################################################
9801 22:50:33.519408
9802 22:50:33.778662 00200000 ################################################################
9803 22:50:33.778805
9804 22:50:34.041746 00280000 ################################################################
9805 22:50:34.041883
9806 22:50:34.294879 00300000 ################################################################
9807 22:50:34.295009
9808 22:50:34.557998 00380000 ################################################################
9809 22:50:34.558139
9810 22:50:34.811561 00400000 ################################################################
9811 22:50:34.811693
9812 22:50:35.082439 00480000 ################################################################
9813 22:50:35.082574
9814 22:50:35.359417 00500000 ################################################################
9815 22:50:35.359555
9816 22:50:35.630182 00580000 ################################################################
9817 22:50:35.630319
9818 22:50:35.907728 00600000 ################################################################
9819 22:50:35.907864
9820 22:50:36.164209 00680000 ################################################################
9821 22:50:36.164351
9822 22:50:36.437519 00700000 ################################################################
9823 22:50:36.437658
9824 22:50:36.696545 00780000 ################################################################
9825 22:50:36.696675
9826 22:50:36.951873 00800000 ################################################################
9827 22:50:36.952009
9828 22:50:37.203378 00880000 ################################################################
9829 22:50:37.203511
9830 22:50:37.469374 00900000 ################################################################
9831 22:50:37.469517
9832 22:50:37.727136 00980000 ################################################################
9833 22:50:37.727278
9834 22:50:37.989071 00a00000 ################################################################
9835 22:50:37.989243
9836 22:50:38.263942 00a80000 ################################################################
9837 22:50:38.264085
9838 22:50:38.536008 00b00000 ################################################################
9839 22:50:38.536155
9840 22:50:38.831075 00b80000 ################################################################
9841 22:50:38.831213
9842 22:50:39.105207 00c00000 ################################################################
9843 22:50:39.105339
9844 22:50:39.368632 00c80000 ################################################################
9845 22:50:39.368764
9846 22:50:39.627152 00d00000 ################################################################
9847 22:50:39.627285
9848 22:50:39.889712 00d80000 ################################################################
9849 22:50:39.889852
9850 22:50:40.150816 00e00000 ################################################################
9851 22:50:40.150960
9852 22:50:40.409421 00e80000 ################################################################
9853 22:50:40.409562
9854 22:50:40.690213 00f00000 ################################################################
9855 22:50:40.690341
9856 22:50:40.955305 00f80000 ################################################################
9857 22:50:40.955440
9858 22:50:41.228682 01000000 ################################################################
9859 22:50:41.228811
9860 22:50:41.490679 01080000 ################################################################
9861 22:50:41.490807
9862 22:50:41.777708 01100000 ################################################################
9863 22:50:41.777837
9864 22:50:42.040665 01180000 ################################################################
9865 22:50:42.040799
9866 22:50:42.313522 01200000 ################################################################
9867 22:50:42.313653
9868 22:50:42.596244 01280000 ################################################################
9869 22:50:42.596375
9870 22:50:42.865187 01300000 ################################################################
9871 22:50:42.865320
9872 22:50:43.152100 01380000 ################################################################
9873 22:50:43.152281
9874 22:50:43.403692 01400000 ################################################################
9875 22:50:43.403823
9876 22:50:43.681736 01480000 ################################################################
9877 22:50:43.681897
9878 22:50:43.947112 01500000 ################################################################
9879 22:50:43.947247
9880 22:50:44.221147 01580000 ################################################################
9881 22:50:44.221276
9882 22:50:44.486554 01600000 ################################################################
9883 22:50:44.486699
9884 22:50:44.736826 01680000 ################################################################
9885 22:50:44.736965
9886 22:50:44.987158 01700000 ################################################################
9887 22:50:44.987293
9888 22:50:45.245469 01780000 ################################################################
9889 22:50:45.245596
9890 22:50:45.520420 01800000 ################################################################
9891 22:50:45.520566
9892 22:50:45.776329 01880000 ################################################################
9893 22:50:45.776461
9894 22:50:46.027174 01900000 ################################################################
9895 22:50:46.027305
9896 22:50:46.278463 01980000 ################################################################
9897 22:50:46.278594
9898 22:50:46.536369 01a00000 ################################################################
9899 22:50:46.536540
9900 22:50:46.823401 01a80000 ################################################################
9901 22:50:46.823531
9902 22:50:47.106091 01b00000 ################################################################
9903 22:50:47.106237
9904 22:50:47.400552 01b80000 ################################################################
9905 22:50:47.400684
9906 22:50:47.695224 01c00000 ################################################################
9907 22:50:47.695357
9908 22:50:47.972491 01c80000 ################################################################
9909 22:50:47.972632
9910 22:50:48.223366 01d00000 ################################################################
9911 22:50:48.223493
9912 22:50:48.473838 01d80000 ################################################################
9913 22:50:48.473962
9914 22:50:48.737413 01e00000 ################################################################
9915 22:50:48.737543
9916 22:50:48.994839 01e80000 ################################################################
9917 22:50:48.994972
9918 22:50:49.243736 01f00000 ################################################################
9919 22:50:49.243875
9920 22:50:49.515840 01f80000 ################################################################
9921 22:50:49.515966
9922 22:50:49.780070 02000000 ################################################################
9923 22:50:49.780196
9924 22:50:50.053814 02080000 ################################################################
9925 22:50:50.053966
9926 22:50:50.327953 02100000 ################################################################
9927 22:50:50.328094
9928 22:50:50.581185 02180000 ################################################################
9929 22:50:50.581322
9930 22:50:50.836240 02200000 ################################################################
9931 22:50:50.836377
9932 22:50:51.095122 02280000 ################################################################
9933 22:50:51.095259
9934 22:50:51.355348 02300000 ################################################################
9935 22:50:51.355502
9936 22:50:51.611130 02380000 ################################################################
9937 22:50:51.611259
9938 22:50:51.868063 02400000 ################################################################
9939 22:50:51.868197
9940 22:50:52.118351 02480000 ################################################################
9941 22:50:52.118520
9942 22:50:52.377995 02500000 ################################################################
9943 22:50:52.378142
9944 22:50:52.627719 02580000 ################################################################
9945 22:50:52.627874
9946 22:50:52.879414 02600000 ################################################################
9947 22:50:52.879554
9948 22:50:53.163752 02680000 ################################################################
9949 22:50:53.163880
9950 22:50:53.460913 02700000 ################################################################
9951 22:50:53.461040
9952 22:50:53.744086 02780000 ################################################################
9953 22:50:53.744222
9954 22:50:54.020863 02800000 ################################################################
9955 22:50:54.020998
9956 22:50:54.285289 02880000 ################################################################
9957 22:50:54.285421
9958 22:50:54.563478 02900000 ################################################################
9959 22:50:54.563612
9960 22:50:54.840980 02980000 ################################################################
9961 22:50:54.841163
9962 22:50:55.097295 02a00000 ################################################################
9963 22:50:55.097479
9964 22:50:55.355164 02a80000 ################################################################
9965 22:50:55.355312
9966 22:50:55.602224 02b00000 ################################################################
9967 22:50:55.602374
9968 22:50:55.848137 02b80000 ################################################################
9969 22:50:55.848284
9970 22:50:56.098702 02c00000 ################################################################
9971 22:50:56.098879
9972 22:50:56.347544 02c80000 ################################################################
9973 22:50:56.347678
9974 22:50:56.598400 02d00000 ################################################################
9975 22:50:56.598531
9976 22:50:56.845815 02d80000 ################################################################
9977 22:50:56.845947
9978 22:50:57.112740 02e00000 ################################################################
9979 22:50:57.112906
9980 22:50:57.383147 02e80000 ################################################################
9981 22:50:57.383293
9982 22:50:57.638493 02f00000 ################################################################
9983 22:50:57.638629
9984 22:50:57.892894 02f80000 ################################################################
9985 22:50:57.893031
9986 22:50:58.156102 03000000 ################################################################
9987 22:50:58.156236
9988 22:50:58.409107 03080000 ################################################################
9989 22:50:58.409240
9990 22:50:58.668329 03100000 ################################################################
9991 22:50:58.668488
9992 22:50:58.929954 03180000 ################################################################
9993 22:50:58.930140
9994 22:50:59.189620 03200000 ################################################################
9995 22:50:59.189766
9996 22:50:59.439695 03280000 ################################################################
9997 22:50:59.439837
9998 22:50:59.700556 03300000 ################################################################
9999 22:50:59.700701
10000 22:50:59.874056 03380000 ####################################### done.
10001 22:50:59.874212
10002 22:50:59.877705 The bootfile was 54321022 bytes long.
10003 22:50:59.877872
10004 22:50:59.880827 Sending tftp read request... done.
10005 22:50:59.880971
10006 22:50:59.881048 Waiting for the transfer...
10007 22:50:59.881114
10008 22:50:59.884231 00000000 # done.
10009 22:50:59.884403
10010 22:50:59.891191 Command line loaded dynamically from TFTP file: 13683663/tftp-deploy-80lgk2y2/kernel/cmdline
10011 22:50:59.891374
10012 22:50:59.904280 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10013 22:50:59.904504
10014 22:50:59.907759 Loading FIT.
10015 22:50:59.907990
10016 22:50:59.911210 Image ramdisk-1 has 41212176 bytes.
10017 22:50:59.911443
10018 22:50:59.911573 Image fdt-1 has 47258 bytes.
10019 22:50:59.911689
10020 22:50:59.914122 Image kernel-1 has 13059555 bytes.
10021 22:50:59.914297
10022 22:50:59.924274 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
10023 22:50:59.924589
10024 22:50:59.941298 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
10025 22:50:59.941884
10026 22:50:59.947482 Choosing best match conf-1 for compat google,spherion.
10027 22:50:59.951141
10028 22:50:59.955889 Connected to device vid:did:rid of 1ae0:0028:00
10029 22:50:59.962928
10030 22:50:59.965961 tpm_get_response: command 0x17b, return code 0x0
10031 22:50:59.966476
10032 22:50:59.969527 ec_init: CrosEC protocol v3 supported (256, 248)
10033 22:50:59.973418
10034 22:50:59.977106 tpm_cleanup: add release locality here.
10035 22:50:59.977664
10036 22:50:59.978064 Shutting down all USB controllers.
10037 22:50:59.980061
10038 22:50:59.980522 Removing current net device
10039 22:50:59.980884
10040 22:50:59.986825 Exiting depthcharge with code 4 at timestamp: 60594433
10041 22:50:59.987368
10042 22:50:59.989891 LZMA decompressing kernel-1 to 0x821a6718
10043 22:50:59.990376
10044 22:50:59.993299 LZMA decompressing kernel-1 to 0x40000000
10045 22:51:01.603822
10046 22:51:01.604008 jumping to kernel
10047 22:51:01.604709 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10048 22:51:01.604864 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10049 22:51:01.604992 Setting prompt string to ['Linux version [0-9]']
10050 22:51:01.605102 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10051 22:51:01.605203 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10052 22:51:01.654216
10053 22:51:01.657640 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10054 22:51:01.661340 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10055 22:51:01.661528 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10056 22:51:01.661656 Setting prompt string to []
10057 22:51:01.661794 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10058 22:51:01.661920 Using line separator: #'\n'#
10059 22:51:01.662019 No login prompt set.
10060 22:51:01.662134 Parsing kernel messages
10061 22:51:01.662225 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10062 22:51:01.662416 [login-action] Waiting for messages, (timeout 00:03:52)
10063 22:51:01.662533 Waiting using forced prompt support (timeout 00:01:56)
10064 22:51:01.680781 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10065 22:51:01.684709 [ 0.000000] random: crng init done
10066 22:51:01.690913 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10067 22:51:01.694285 [ 0.000000] efi: UEFI not found.
10068 22:51:01.701063 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10069 22:51:01.707490 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10070 22:51:01.717471 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10071 22:51:01.727270 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10072 22:51:01.733868 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10073 22:51:01.740630 [ 0.000000] printk: bootconsole [mtk8250] enabled
10074 22:51:01.747125 [ 0.000000] NUMA: No NUMA configuration found
10075 22:51:01.753939 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10076 22:51:01.757001 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10077 22:51:01.760318 [ 0.000000] Zone ranges:
10078 22:51:01.766777 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10079 22:51:01.770085 [ 0.000000] DMA32 empty
10080 22:51:01.776799 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10081 22:51:01.780208 [ 0.000000] Movable zone start for each node
10082 22:51:01.783834 [ 0.000000] Early memory node ranges
10083 22:51:01.790337 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10084 22:51:01.796937 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10085 22:51:01.803200 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10086 22:51:01.809717 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10087 22:51:01.816494 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10088 22:51:01.823508 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10089 22:51:01.853254 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10090 22:51:01.860030 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10091 22:51:01.866824 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10092 22:51:01.869827 [ 0.000000] psci: probing for conduit method from DT.
10093 22:51:01.876244 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10094 22:51:01.879847 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10095 22:51:01.886579 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10096 22:51:01.889539 [ 0.000000] psci: SMC Calling Convention v1.2
10097 22:51:01.896476 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10098 22:51:01.899583 [ 0.000000] Detected VIPT I-cache on CPU0
10099 22:51:01.906207 [ 0.000000] CPU features: detected: GIC system register CPU interface
10100 22:51:01.913207 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10101 22:51:01.919496 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10102 22:51:01.926174 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10103 22:51:01.932557 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10104 22:51:01.942628 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10105 22:51:01.945792 [ 0.000000] alternatives: applying boot alternatives
10106 22:51:01.952348 [ 0.000000] Fallback order for Node 0: 0
10107 22:51:01.959036 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10108 22:51:01.962416 [ 0.000000] Policy zone: Normal
10109 22:51:01.975719 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10110 22:51:01.985260 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10111 22:51:01.995143 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10112 22:51:02.005255 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10113 22:51:02.012035 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10114 22:51:02.015369 <6>[ 0.000000] software IO TLB: area num 8.
10115 22:51:02.070655 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10116 22:51:02.150978 <6>[ 0.000000] Memory: 3809528K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 348936K reserved, 32768K cma-reserved)
10117 22:51:02.157490 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10118 22:51:02.164165 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10119 22:51:02.167962 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10120 22:51:02.174088 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10121 22:51:02.180715 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10122 22:51:02.183911 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10123 22:51:02.194213 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10124 22:51:02.200860 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10125 22:51:02.207058 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10126 22:51:02.213971 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10127 22:51:02.217044 <6>[ 0.000000] GICv3: 608 SPIs implemented
10128 22:51:02.220624 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10129 22:51:02.227082 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10130 22:51:02.230709 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10131 22:51:02.237361 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10132 22:51:02.250638 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10133 22:51:02.263633 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10134 22:51:02.270340 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10135 22:51:02.278148 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10136 22:51:02.291364 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10137 22:51:02.298155 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10138 22:51:02.304902 <6>[ 0.009229] Console: colour dummy device 80x25
10139 22:51:02.314965 <6>[ 0.013987] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10140 22:51:02.322292 <6>[ 0.024494] pid_max: default: 32768 minimum: 301
10141 22:51:02.324651 <6>[ 0.029365] LSM: Security Framework initializing
10142 22:51:02.331168 <6>[ 0.034309] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10143 22:51:02.341121 <6>[ 0.041916] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10144 22:51:02.348231 <6>[ 0.051213] cblist_init_generic: Setting adjustable number of callback queues.
10145 22:51:02.354564 <6>[ 0.058656] cblist_init_generic: Setting shift to 3 and lim to 1.
10146 22:51:02.365111 <6>[ 0.064995] cblist_init_generic: Setting adjustable number of callback queues.
10147 22:51:02.368207 <6>[ 0.072421] cblist_init_generic: Setting shift to 3 and lim to 1.
10148 22:51:02.374957 <6>[ 0.078822] rcu: Hierarchical SRCU implementation.
10149 22:51:02.381126 <6>[ 0.083837] rcu: Max phase no-delay instances is 1000.
10150 22:51:02.387581 <6>[ 0.090855] EFI services will not be available.
10151 22:51:02.390708 <6>[ 0.095841] smp: Bringing up secondary CPUs ...
10152 22:51:02.399029 <6>[ 0.100918] Detected VIPT I-cache on CPU1
10153 22:51:02.405881 <6>[ 0.100988] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10154 22:51:02.412318 <6>[ 0.101019] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10155 22:51:02.415591 <6>[ 0.101351] Detected VIPT I-cache on CPU2
10156 22:51:02.425470 <6>[ 0.101399] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10157 22:51:02.431691 <6>[ 0.101415] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10158 22:51:02.435122 <6>[ 0.101671] Detected VIPT I-cache on CPU3
10159 22:51:02.441622 <6>[ 0.101718] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10160 22:51:02.448389 <6>[ 0.101732] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10161 22:51:02.455051 <6>[ 0.102038] CPU features: detected: Spectre-v4
10162 22:51:02.458001 <6>[ 0.102045] CPU features: detected: Spectre-BHB
10163 22:51:02.461599 <6>[ 0.102050] Detected PIPT I-cache on CPU4
10164 22:51:02.468137 <6>[ 0.102109] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10165 22:51:02.477542 <6>[ 0.102126] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10166 22:51:02.480923 <6>[ 0.102416] Detected PIPT I-cache on CPU5
10167 22:51:02.488201 <6>[ 0.102478] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10168 22:51:02.494411 <6>[ 0.102494] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10169 22:51:02.497909 <6>[ 0.102777] Detected PIPT I-cache on CPU6
10170 22:51:02.504468 <6>[ 0.102839] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10171 22:51:02.511359 <6>[ 0.102855] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10172 22:51:02.517908 <6>[ 0.103157] Detected PIPT I-cache on CPU7
10173 22:51:02.524396 <6>[ 0.103223] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10174 22:51:02.530681 <6>[ 0.103239] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10175 22:51:02.533803 <6>[ 0.103286] smp: Brought up 1 node, 8 CPUs
10176 22:51:02.540461 <6>[ 0.244611] SMP: Total of 8 processors activated.
10177 22:51:02.544073 <6>[ 0.249562] CPU features: detected: 32-bit EL0 Support
10178 22:51:02.554196 <6>[ 0.254958] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10179 22:51:02.560713 <6>[ 0.263758] CPU features: detected: Common not Private translations
10180 22:51:02.566916 <6>[ 0.270234] CPU features: detected: CRC32 instructions
10181 22:51:02.573630 <6>[ 0.275585] CPU features: detected: RCpc load-acquire (LDAPR)
10182 22:51:02.576870 <6>[ 0.281582] CPU features: detected: LSE atomic instructions
10183 22:51:02.583712 <6>[ 0.287400] CPU features: detected: Privileged Access Never
10184 22:51:02.590637 <6>[ 0.293179] CPU features: detected: RAS Extension Support
10185 22:51:02.596630 <6>[ 0.298788] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10186 22:51:02.600065 <6>[ 0.306009] CPU: All CPU(s) started at EL2
10187 22:51:02.606672 <6>[ 0.310326] alternatives: applying system-wide alternatives
10188 22:51:02.615895 <6>[ 0.320269] devtmpfs: initialized
10189 22:51:02.630486 <6>[ 0.328531] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10190 22:51:02.637330 <6>[ 0.338495] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10191 22:51:02.643904 <6>[ 0.346710] pinctrl core: initialized pinctrl subsystem
10192 22:51:02.646895 <6>[ 0.353360] DMI not present or invalid.
10193 22:51:02.653818 <6>[ 0.357766] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10194 22:51:02.663789 <6>[ 0.364624] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10195 22:51:02.670580 <6>[ 0.372067] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10196 22:51:02.679962 <6>[ 0.380161] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10197 22:51:02.683429 <6>[ 0.388317] audit: initializing netlink subsys (disabled)
10198 22:51:02.693599 <5>[ 0.394010] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10199 22:51:02.700227 <6>[ 0.394705] thermal_sys: Registered thermal governor 'step_wise'
10200 22:51:02.706485 <6>[ 0.401976] thermal_sys: Registered thermal governor 'power_allocator'
10201 22:51:02.710125 <6>[ 0.408233] cpuidle: using governor menu
10202 22:51:02.716538 <6>[ 0.419196] NET: Registered PF_QIPCRTR protocol family
10203 22:51:02.722949 <6>[ 0.424676] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10204 22:51:02.729545 <6>[ 0.431776] ASID allocator initialised with 32768 entries
10205 22:51:02.732684 <6>[ 0.438333] Serial: AMBA PL011 UART driver
10206 22:51:02.742365 <4>[ 0.447062] Trying to register duplicate clock ID: 134
10207 22:51:02.800679 <6>[ 0.508553] KASLR enabled
10208 22:51:02.815348 <6>[ 0.516291] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10209 22:51:02.821949 <6>[ 0.523306] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10210 22:51:02.828427 <6>[ 0.529795] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10211 22:51:02.835351 <6>[ 0.536800] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10212 22:51:02.841285 <6>[ 0.543286] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10213 22:51:02.848155 <6>[ 0.550290] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10214 22:51:02.854632 <6>[ 0.556777] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10215 22:51:02.861664 <6>[ 0.563779] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10216 22:51:02.864690 <6>[ 0.571278] ACPI: Interpreter disabled.
10217 22:51:02.873289 <6>[ 0.577688] iommu: Default domain type: Translated
10218 22:51:02.879587 <6>[ 0.582800] iommu: DMA domain TLB invalidation policy: strict mode
10219 22:51:02.883345 <5>[ 0.589453] SCSI subsystem initialized
10220 22:51:02.889680 <6>[ 0.593616] usbcore: registered new interface driver usbfs
10221 22:51:02.896336 <6>[ 0.599349] usbcore: registered new interface driver hub
10222 22:51:02.899344 <6>[ 0.604899] usbcore: registered new device driver usb
10223 22:51:02.906161 <6>[ 0.610990] pps_core: LinuxPPS API ver. 1 registered
10224 22:51:02.916038 <6>[ 0.616184] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10225 22:51:02.920025 <6>[ 0.625529] PTP clock support registered
10226 22:51:02.923190 <6>[ 0.629773] EDAC MC: Ver: 3.0.0
10227 22:51:02.930603 <6>[ 0.634912] FPGA manager framework
10228 22:51:02.937397 <6>[ 0.638599] Advanced Linux Sound Architecture Driver Initialized.
10229 22:51:02.940473 <6>[ 0.645375] vgaarb: loaded
10230 22:51:02.946869 <6>[ 0.648516] clocksource: Switched to clocksource arch_sys_counter
10231 22:51:02.950616 <5>[ 0.654951] VFS: Disk quotas dquot_6.6.0
10232 22:51:02.956735 <6>[ 0.659138] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10233 22:51:02.959873 <6>[ 0.666326] pnp: PnP ACPI: disabled
10234 22:51:02.968981 <6>[ 0.673085] NET: Registered PF_INET protocol family
10235 22:51:02.975412 <6>[ 0.678473] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10236 22:51:02.987304 <6>[ 0.688501] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10237 22:51:02.997099 <6>[ 0.697284] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10238 22:51:03.003635 <6>[ 0.705247] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10239 22:51:03.010227 <6>[ 0.713649] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10240 22:51:03.021403 <6>[ 0.722314] TCP: Hash tables configured (established 32768 bind 32768)
10241 22:51:03.027664 <6>[ 0.729174] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10242 22:51:03.034221 <6>[ 0.736191] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10243 22:51:03.041329 <6>[ 0.743713] NET: Registered PF_UNIX/PF_LOCAL protocol family
10244 22:51:03.047510 <6>[ 0.749781] RPC: Registered named UNIX socket transport module.
10245 22:51:03.050954 <6>[ 0.755928] RPC: Registered udp transport module.
10246 22:51:03.058088 <6>[ 0.760860] RPC: Registered tcp transport module.
10247 22:51:03.064460 <6>[ 0.765791] RPC: Registered tcp NFSv4.1 backchannel transport module.
10248 22:51:03.067484 <6>[ 0.772457] PCI: CLS 0 bytes, default 64
10249 22:51:03.071147 <6>[ 0.776868] Unpacking initramfs...
10250 22:51:03.083394 <6>[ 0.784590] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10251 22:51:03.093300 <6>[ 0.793271] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10252 22:51:03.096764 <6>[ 0.802103] kvm [1]: IPA Size Limit: 40 bits
10253 22:51:03.103190 <6>[ 0.806626] kvm [1]: GICv3: no GICV resource entry
10254 22:51:03.106546 <6>[ 0.811648] kvm [1]: disabling GICv2 emulation
10255 22:51:03.112896 <6>[ 0.816334] kvm [1]: GIC system register CPU interface enabled
10256 22:51:03.116270 <6>[ 0.822503] kvm [1]: vgic interrupt IRQ18
10257 22:51:03.122806 <6>[ 0.826858] kvm [1]: VHE mode initialized successfully
10258 22:51:03.129603 <5>[ 0.833202] Initialise system trusted keyrings
10259 22:51:03.136008 <6>[ 0.838001] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10260 22:51:03.143236 <6>[ 0.848009] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10261 22:51:03.150132 <5>[ 0.854418] NFS: Registering the id_resolver key type
10262 22:51:03.153256 <5>[ 0.859720] Key type id_resolver registered
10263 22:51:03.160355 <5>[ 0.864136] Key type id_legacy registered
10264 22:51:03.166886 <6>[ 0.868411] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10265 22:51:03.173174 <6>[ 0.875333] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10266 22:51:03.179821 <6>[ 0.883044] 9p: Installing v9fs 9p2000 file system support
10267 22:51:03.216201 <5>[ 0.920774] Key type asymmetric registered
10268 22:51:03.219723 <5>[ 0.925102] Asymmetric key parser 'x509' registered
10269 22:51:03.229587 <6>[ 0.930245] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10270 22:51:03.232510 <6>[ 0.937860] io scheduler mq-deadline registered
10271 22:51:03.235660 <6>[ 0.942637] io scheduler kyber registered
10272 22:51:03.254833 <6>[ 0.959504] EINJ: ACPI disabled.
10273 22:51:03.287592 <4>[ 0.985649] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10274 22:51:03.297362 <4>[ 0.996275] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10275 22:51:03.312641 <6>[ 1.017407] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10276 22:51:03.320785 <6>[ 1.025419] printk: console [ttyS0] disabled
10277 22:51:03.348666 <6>[ 1.050047] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10278 22:51:03.355852 <6>[ 1.059526] printk: console [ttyS0] enabled
10279 22:51:03.358709 <6>[ 1.059526] printk: console [ttyS0] enabled
10280 22:51:03.365331 <6>[ 1.068421] printk: bootconsole [mtk8250] disabled
10281 22:51:03.368511 <6>[ 1.068421] printk: bootconsole [mtk8250] disabled
10282 22:51:03.375217 <6>[ 1.079671] SuperH (H)SCI(F) driver initialized
10283 22:51:03.378362 <6>[ 1.084956] msm_serial: driver initialized
10284 22:51:03.392934 <6>[ 1.093908] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10285 22:51:03.402953 <6>[ 1.102455] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10286 22:51:03.409236 <6>[ 1.110998] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10287 22:51:03.419024 <6>[ 1.119626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10288 22:51:03.429059 <6>[ 1.128335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10289 22:51:03.435453 <6>[ 1.137052] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10290 22:51:03.445507 <6>[ 1.145596] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10291 22:51:03.452007 <6>[ 1.154397] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10292 22:51:03.461811 <6>[ 1.162940] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10293 22:51:03.473363 <6>[ 1.178607] loop: module loaded
10294 22:51:03.480077 <6>[ 1.184522] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10295 22:51:03.503287 <4>[ 1.208119] mtk-pmic-keys: Failed to locate of_node [id: -1]
10296 22:51:03.509977 <6>[ 1.215212] megasas: 07.719.03.00-rc1
10297 22:51:03.519781 <6>[ 1.225018] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10298 22:51:03.526853 <6>[ 1.231914] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10299 22:51:03.543294 <6>[ 1.248272] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10300 22:51:03.598628 <6>[ 1.296977] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10301 22:51:04.821291 <6>[ 2.526498] Freeing initrd memory: 40240K
10302 22:51:04.832734 <6>[ 2.538216] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10303 22:51:04.844158 <6>[ 2.549419] tun: Universal TUN/TAP device driver, 1.6
10304 22:51:04.847382 <6>[ 2.555491] thunder_xcv, ver 1.0
10305 22:51:04.850824 <6>[ 2.559000] thunder_bgx, ver 1.0
10306 22:51:04.853952 <6>[ 2.562495] nicpf, ver 1.0
10307 22:51:04.864550 <6>[ 2.566523] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10308 22:51:04.867913 <6>[ 2.573999] hns3: Copyright (c) 2017 Huawei Corporation.
10309 22:51:04.874500 <6>[ 2.579591] hclge is initializing
10310 22:51:04.877868 <6>[ 2.583172] e1000: Intel(R) PRO/1000 Network Driver
10311 22:51:04.884481 <6>[ 2.588301] e1000: Copyright (c) 1999-2006 Intel Corporation.
10312 22:51:04.887737 <6>[ 2.594314] e1000e: Intel(R) PRO/1000 Network Driver
10313 22:51:04.894290 <6>[ 2.599529] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10314 22:51:04.901086 <6>[ 2.605713] igb: Intel(R) Gigabit Ethernet Network Driver
10315 22:51:04.907692 <6>[ 2.611363] igb: Copyright (c) 2007-2014 Intel Corporation.
10316 22:51:04.914260 <6>[ 2.617198] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10317 22:51:04.920835 <6>[ 2.623716] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10318 22:51:04.924243 <6>[ 2.630179] sky2: driver version 1.30
10319 22:51:04.930640 <6>[ 2.635104] usbcore: registered new device driver r8152-cfgselector
10320 22:51:04.937765 <6>[ 2.641641] usbcore: registered new interface driver r8152
10321 22:51:04.944057 <6>[ 2.647461] VFIO - User Level meta-driver version: 0.3
10322 22:51:04.950507 <6>[ 2.655685] usbcore: registered new interface driver usb-storage
10323 22:51:04.957551 <6>[ 2.662134] usbcore: registered new device driver onboard-usb-hub
10324 22:51:04.965982 <6>[ 2.671266] mt6397-rtc mt6359-rtc: registered as rtc0
10325 22:51:04.975993 <6>[ 2.676725] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:51:06 UTC (1715122266)
10326 22:51:04.979113 <6>[ 2.686289] i2c_dev: i2c /dev entries driver
10327 22:51:04.996133 <6>[ 2.698083] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10328 22:51:05.002990 <4>[ 2.706804] cpu cpu0: supply cpu not found, using dummy regulator
10329 22:51:05.009369 <4>[ 2.713221] cpu cpu1: supply cpu not found, using dummy regulator
10330 22:51:05.016065 <4>[ 2.719641] cpu cpu2: supply cpu not found, using dummy regulator
10331 22:51:05.022679 <4>[ 2.726054] cpu cpu3: supply cpu not found, using dummy regulator
10332 22:51:05.029202 <4>[ 2.732449] cpu cpu4: supply cpu not found, using dummy regulator
10333 22:51:05.036103 <4>[ 2.738849] cpu cpu5: supply cpu not found, using dummy regulator
10334 22:51:05.042679 <4>[ 2.745245] cpu cpu6: supply cpu not found, using dummy regulator
10335 22:51:05.048772 <4>[ 2.751644] cpu cpu7: supply cpu not found, using dummy regulator
10336 22:51:05.068163 <6>[ 2.773287] cpu cpu0: EM: created perf domain
10337 22:51:05.071563 <6>[ 2.778190] cpu cpu4: EM: created perf domain
10338 22:51:05.078768 <6>[ 2.783780] sdhci: Secure Digital Host Controller Interface driver
10339 22:51:05.084891 <6>[ 2.790212] sdhci: Copyright(c) Pierre Ossman
10340 22:51:05.091918 <6>[ 2.795122] Synopsys Designware Multimedia Card Interface Driver
10341 22:51:05.098468 <6>[ 2.801729] sdhci-pltfm: SDHCI platform and OF driver helper
10342 22:51:05.102019 <6>[ 2.801897] mmc0: CQHCI version 5.10
10343 22:51:05.108254 <6>[ 2.811947] ledtrig-cpu: registered to indicate activity on CPUs
10344 22:51:05.114872 <6>[ 2.819044] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10345 22:51:05.121534 <6>[ 2.826079] usbcore: registered new interface driver usbhid
10346 22:51:05.124605 <6>[ 2.831900] usbhid: USB HID core driver
10347 22:51:05.131465 <6>[ 2.836082] spi_master spi0: will run message pump with realtime priority
10348 22:51:05.175232 <6>[ 2.874020] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10349 22:51:05.194886 <6>[ 2.890152] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10350 22:51:05.198883 <6>[ 2.903766] mmc0: Command Queue Engine enabled
10351 22:51:05.204939 <6>[ 2.908543] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10352 22:51:05.211999 <6>[ 2.915461] cros-ec-spi spi0.0: Chrome EC device registered
10353 22:51:05.214709 <6>[ 2.915786] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10354 22:51:05.226134 <6>[ 2.931432] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10355 22:51:05.233389 <6>[ 2.938619] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10356 22:51:05.240063 <6>[ 2.944541] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10357 22:51:05.250009 <6>[ 2.948040] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10358 22:51:05.256542 <6>[ 2.950429] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10359 22:51:05.259887 <6>[ 2.960115] NET: Registered PF_PACKET protocol family
10360 22:51:05.266604 <6>[ 2.970989] 9pnet: Installing 9P2000 support
10361 22:51:05.269513 <5>[ 2.975554] Key type dns_resolver registered
10362 22:51:05.272882 <6>[ 2.980485] registered taskstats version 1
10363 22:51:05.279303 <5>[ 2.984862] Loading compiled-in X.509 certificates
10364 22:51:05.306742 <4>[ 3.005412] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10365 22:51:05.316923 <4>[ 3.016121] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10366 22:51:05.323340 <3>[ 3.026706] debugfs: File 'uA_load' in directory '/' already present!
10367 22:51:05.330218 <3>[ 3.033419] debugfs: File 'min_uV' in directory '/' already present!
10368 22:51:05.336653 <3>[ 3.040031] debugfs: File 'max_uV' in directory '/' already present!
10369 22:51:05.346733 <3>[ 3.046643] debugfs: File 'constraint_flags' in directory '/' already present!
10370 22:51:05.356114 <6>[ 3.061411] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10371 22:51:05.363551 <6>[ 3.068406] xhci-mtk 11200000.usb: xHCI Host Controller
10372 22:51:05.369835 <6>[ 3.073930] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10373 22:51:05.379986 <6>[ 3.081793] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10374 22:51:05.386813 <6>[ 3.091260] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10375 22:51:05.393415 <6>[ 3.097435] xhci-mtk 11200000.usb: xHCI Host Controller
10376 22:51:05.399647 <6>[ 3.102920] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10377 22:51:05.406340 <6>[ 3.110572] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10378 22:51:05.413805 <6>[ 3.118358] hub 1-0:1.0: USB hub found
10379 22:51:05.416778 <6>[ 3.122392] hub 1-0:1.0: 1 port detected
10380 22:51:05.426363 <6>[ 3.126664] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10381 22:51:05.430051 <6>[ 3.135454] hub 2-0:1.0: USB hub found
10382 22:51:05.433208 <6>[ 3.139487] hub 2-0:1.0: 1 port detected
10383 22:51:05.441602 <6>[ 3.146741] mtk-msdc 11f70000.mmc: Got CD GPIO
10384 22:51:05.452810 <6>[ 3.154112] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10385 22:51:05.459035 <6>[ 3.162132] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10386 22:51:05.468928 <4>[ 3.170017] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10387 22:51:05.478913 <6>[ 3.179543] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10388 22:51:05.485435 <6>[ 3.187621] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10389 22:51:05.492428 <6>[ 3.195733] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10390 22:51:05.502319 <6>[ 3.203772] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10391 22:51:05.508603 <6>[ 3.211604] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10392 22:51:05.518933 <6>[ 3.219445] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10393 22:51:05.528538 <6>[ 3.229867] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10394 22:51:05.535496 <6>[ 3.238262] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10395 22:51:05.545383 <6>[ 3.246603] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10396 22:51:05.552062 <6>[ 3.254952] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10397 22:51:05.561805 <6>[ 3.263290] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10398 22:51:05.568401 <6>[ 3.271637] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10399 22:51:05.578192 <6>[ 3.279974] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10400 22:51:05.588140 <6>[ 3.288321] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10401 22:51:05.594725 <6>[ 3.296658] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10402 22:51:05.604848 <6>[ 3.305005] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10403 22:51:05.611200 <6>[ 3.313342] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10404 22:51:05.621427 <6>[ 3.321678] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10405 22:51:05.628244 <6>[ 3.330015] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10406 22:51:05.637574 <6>[ 3.338353] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10407 22:51:05.644487 <6>[ 3.346690] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10408 22:51:05.651097 <6>[ 3.355432] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10409 22:51:05.657738 <6>[ 3.362617] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10410 22:51:05.664327 <6>[ 3.369403] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10411 22:51:05.674764 <6>[ 3.376173] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10412 22:51:05.680823 <6>[ 3.383092] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10413 22:51:05.687614 <6>[ 3.389930] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10414 22:51:05.697684 <6>[ 3.399059] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10415 22:51:05.707497 <6>[ 3.408178] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10416 22:51:05.717767 <6>[ 3.417493] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10417 22:51:05.727343 <6>[ 3.426966] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10418 22:51:05.737122 <6>[ 3.436435] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10419 22:51:05.743695 <6>[ 3.445554] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10420 22:51:05.753619 <6>[ 3.455019] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10421 22:51:05.763636 <6>[ 3.464137] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10422 22:51:05.773580 <6>[ 3.473431] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10423 22:51:05.783300 <6>[ 3.483590] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10424 22:51:05.793357 <6>[ 3.495078] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10425 22:51:05.823337 <6>[ 3.525017] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10426 22:51:05.852198 <6>[ 3.556356] hub 2-1:1.0: USB hub found
10427 22:51:05.854776 <6>[ 3.560837] hub 2-1:1.0: 3 ports detected
10428 22:51:05.863448 <6>[ 3.568057] hub 2-1:1.0: USB hub found
10429 22:51:05.866522 <6>[ 3.572436] hub 2-1:1.0: 3 ports detected
10430 22:51:05.974682 <6>[ 3.676721] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10431 22:51:06.129644 <6>[ 3.834727] hub 1-1:1.0: USB hub found
10432 22:51:06.132933 <6>[ 3.839174] hub 1-1:1.0: 4 ports detected
10433 22:51:06.142571 <6>[ 3.847803] hub 1-1:1.0: USB hub found
10434 22:51:06.145747 <6>[ 3.852130] hub 1-1:1.0: 4 ports detected
10435 22:51:06.206924 <6>[ 3.909115] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10436 22:51:06.315849 <6>[ 4.017455] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10437 22:51:06.350419 <4>[ 4.052281] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10438 22:51:06.360537 <4>[ 4.061364] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10439 22:51:06.400367 <6>[ 4.105587] r8152 2-1.3:1.0 eth0: v1.12.13
10440 22:51:06.467099 <6>[ 4.168829] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10441 22:51:06.599615 <6>[ 4.304623] hub 1-1.4:1.0: USB hub found
10442 22:51:06.602845 <6>[ 4.309290] hub 1-1.4:1.0: 2 ports detected
10443 22:51:06.612592 <6>[ 4.317446] hub 1-1.4:1.0: USB hub found
10444 22:51:06.615915 <6>[ 4.322130] hub 1-1.4:1.0: 2 ports detected
10445 22:51:06.915043 <6>[ 4.616822] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10446 22:51:07.106510 <6>[ 4.808642] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10447 22:51:08.073355 <6>[ 5.778690] r8152 2-1.3:1.0 eth0: carrier on
10448 22:51:10.307105 <5>[ 5.804628] Sending DHCP requests .., OK
10449 22:51:10.314236 <6>[ 8.017016] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10450 22:51:10.317002 <6>[ 8.025294] IP-Config: Complete:
10451 22:51:10.330630 <6>[ 8.028787] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10452 22:51:10.337082 <6>[ 8.039509] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10453 22:51:10.343629 <6>[ 8.048121] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10454 22:51:10.350577 <6>[ 8.048129] nameserver0=192.168.201.1
10455 22:51:10.353943 <6>[ 8.060230] clk: Disabling unused clocks
10456 22:51:10.357043 <6>[ 8.065434] ALSA device list:
10457 22:51:10.360382 <6>[ 8.068728] No soundcards found.
10458 22:51:10.370752 <6>[ 8.076046] Freeing unused kernel memory: 8512K
10459 22:51:10.373777 <6>[ 8.081048] Run /init as init process
10460 22:51:10.401166 <6>[ 8.106727] NET: Registered PF_INET6 protocol family
10461 22:51:10.407974 <6>[ 8.113469] Segment Routing with IPv6
10462 22:51:10.411265 <6>[ 8.117426] In-situ OAM (IOAM) with IPv6
10463 22:51:10.457864 <30>[ 8.133527] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10464 22:51:10.461303 <30>[ 8.166696] systemd[1]: Detected architecture arm64.
10465 22:51:10.461818
10466 22:51:10.467697 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10467 22:51:10.468227
10468 22:51:10.468557
10469 22:51:10.483849 <30>[ 8.188885] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10470 22:51:10.597462 <30>[ 8.299567] systemd[1]: Queued start job for default target graphical.target.
10471 22:51:10.648426 <30>[ 8.350323] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10472 22:51:10.654944 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10473 22:51:10.655502
10474 22:51:10.675518 <30>[ 8.377346] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10475 22:51:10.685293 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10476 22:51:10.685868
10477 22:51:10.704187 <30>[ 8.406118] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10478 22:51:10.713762 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10479 22:51:10.714222
10480 22:51:10.731698 <30>[ 8.433853] systemd[1]: Created slice user.slice - User and Session Slice.
10481 22:51:10.738637 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10482 22:51:10.739160
10483 22:51:10.758988 <30>[ 8.457472] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10484 22:51:10.768730 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10485 22:51:10.769289
10486 22:51:10.786306 <30>[ 8.484924] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10487 22:51:10.792932 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10488 22:51:10.793492
10489 22:51:10.821015 <30>[ 8.512882] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10490 22:51:10.830787 <30>[ 8.532699] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10491 22:51:10.837242 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10492 22:51:10.837801
10493 22:51:10.854523 <30>[ 8.556744] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10494 22:51:10.861115 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10495 22:51:10.861583
10496 22:51:10.878956 <30>[ 8.580863] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10497 22:51:10.888767 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10498 22:51:10.889328
10499 22:51:10.904133 <30>[ 8.609331] systemd[1]: Reached target paths.target - Path Units.
10500 22:51:10.910646 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10501 22:51:10.913879
10502 22:51:10.931283 <30>[ 8.633244] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10503 22:51:10.937884 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10504 22:51:10.938324
10505 22:51:10.951871 <30>[ 8.656806] systemd[1]: Reached target slices.target - Slice Units.
10506 22:51:10.961274 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10507 22:51:10.961837
10508 22:51:10.976181 <30>[ 8.681291] systemd[1]: Reached target swap.target - Swaps.
10509 22:51:10.982530 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10510 22:51:10.983046
10511 22:51:11.003359 <30>[ 8.705323] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10512 22:51:11.013173 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10513 22:51:11.013739
10514 22:51:11.031115 <30>[ 8.733350] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10515 22:51:11.041019 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10516 22:51:11.041575
10517 22:51:11.060644 <30>[ 8.762899] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10518 22:51:11.070729 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10519 22:51:11.071305
10520 22:51:11.087239 <30>[ 8.789482] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10521 22:51:11.097330 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10522 22:51:11.097867
10523 22:51:11.115435 <30>[ 8.817456] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10524 22:51:11.121909 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10525 22:51:11.122524
10526 22:51:11.139561 <30>[ 8.841486] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10527 22:51:11.149545 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10528 22:51:11.150196
10529 22:51:11.168147 <30>[ 8.870195] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10530 22:51:11.178076 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10531 22:51:11.178647
10532 22:51:11.196209 <30>[ 8.897919] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10533 22:51:11.206215 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10534 22:51:11.206791
10535 22:51:11.262947 <30>[ 8.965030] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10536 22:51:11.269547 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10537 22:51:11.270148
10538 22:51:11.283077 <30>[ 8.985106] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10539 22:51:11.289867 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10540 22:51:11.290493
10541 22:51:11.315030 <30>[ 9.017293] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10542 22:51:11.321848 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10543 22:51:11.322489
10544 22:51:11.354234 <30>[ 9.049394] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10545 22:51:11.367465 <30>[ 9.069838] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10546 22:51:11.377488 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10547 22:51:11.378088
10548 22:51:11.400050 <30>[ 9.102055] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10549 22:51:11.406622 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10550 22:51:11.407183
10551 22:51:11.431944 <30>[ 9.134011] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10552 22:51:11.445033 Starting [0;1;39mmodpr<6>[ 9.145156] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10553 22:51:11.448281 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10554 22:51:11.448750
10555 22:51:11.472136 <30>[ 9.174272] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10556 22:51:11.478806 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10557 22:51:11.479375
10558 22:51:11.508323 <30>[ 9.210223] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10559 22:51:11.514461 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10560 22:51:11.514930
10561 22:51:11.543876 <30>[ 9.246095] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10562 22:51:11.550498 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10563 22:51:11.550967
10564 22:51:11.579522 <30>[ 9.281672] systemd[1]: Starting systemd-journald.service - Journal Service...
10565 22:51:11.586017 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10566 22:51:11.586579
10567 22:51:11.605913 <30>[ 9.307664] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10568 22:51:11.611863 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10569 22:51:11.612496
10570 22:51:11.637425 <30>[ 9.336150] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10571 22:51:11.643427 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10572 22:51:11.643855
10573 22:51:11.666144 <30>[ 9.368353] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10574 22:51:11.675871 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10575 22:51:11.676486
10576 22:51:11.698269 <30>[ 9.400299] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10577 22:51:11.704810 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10578 22:51:11.705374
10579 22:51:11.732029 <30>[ 9.434159] systemd[1]: Started systemd-journald.service - Journal Service.
10580 22:51:11.738545 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10581 22:51:11.739092
10582 22:51:11.761575 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10583 22:51:11.762164
10584 22:51:11.780648 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10585 22:51:11.781214
10586 22:51:11.799873 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10587 22:51:11.800457
10588 22:51:11.820266 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10589 22:51:11.820835
10590 22:51:11.841528 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10591 22:51:11.842157
10592 22:51:11.859989 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10593 22:51:11.860537
10594 22:51:11.879909 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10595 22:51:11.880483
10596 22:51:11.902529 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10597 22:51:11.903110
10598 22:51:11.925570 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10599 22:51:11.926199
10600 22:51:11.944178 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10601 22:51:11.944756
10602 22:51:11.963827 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10603 22:51:11.964520
10604 22:51:11.989179 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10605 22:51:11.989746
10606 22:51:11.996037 See 'systemctl status systemd-remount-fs.service' for details.
10607 22:51:11.996596
10608 22:51:12.005521 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10609 22:51:12.006121
10610 22:51:12.025213 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10611 22:51:12.025776
10612 22:51:12.075361 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10613 22:51:12.075926
10614 22:51:12.097716 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10615 22:51:12.098319
10616 22:51:12.108436 <46>[ 9.810556] systemd-journald[193]: Received client request to flush runtime journal.
10617 22:51:12.121069 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10618 22:51:12.121636
10619 22:51:12.179881 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10620 22:51:12.180449
10621 22:51:12.208105 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10622 22:51:12.208672
10623 22:51:12.234360 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10624 22:51:12.234925
10625 22:51:12.252145 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10626 22:51:12.252720
10627 22:51:12.271983 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10628 22:51:12.272559
10629 22:51:12.292174 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10630 22:51:12.292746
10631 22:51:12.312205 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10632 22:51:12.312791
10633 22:51:12.359413 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10634 22:51:12.359988
10635 22:51:12.382204 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10636 22:51:12.382790
10637 22:51:12.403355 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10638 22:51:12.403932
10639 22:51:12.422625 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10640 22:51:12.423178
10641 22:51:12.459133 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10642 22:51:12.459704
10643 22:51:12.479749 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10644 22:51:12.480320
10645 22:51:12.506623 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10646 22:51:12.507197
10647 22:51:12.525952 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10648 22:51:12.526571
10649 22:51:12.551150 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10650 22:51:12.551723
10651 22:51:12.721394 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10652 22:51:12.721939
10653 22:51:12.745714 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10654 22:51:12.746364
10655 22:51:12.769216 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10656 22:51:12.769772
10657 22:51:12.803533 <5>[ 10.506155] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10658 22:51:12.818931 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10659 22:51:12.819552
10660 22:51:12.836985 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10661 22:51:12.837553
10662 22:51:12.846933 <5>[ 10.549169] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10663 22:51:12.853780 <46>[ 10.551596] systemd-journald[193]: Time jumped backwards, rotating.
10664 22:51:12.860375 <5>[ 10.556471] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10665 22:51:12.873726 [[0;32m OK [<4>[ 10.572444] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10666 22:51:12.876772 0m] Reached targ<6>[ 10.582723] cfg80211: failed to load regulatory.db
10667 22:51:12.883468 et [0;1;39msysinit.target[0m - System Initialization.
10668 22:51:12.884037
10669 22:51:12.905344 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10670 22:51:12.905955
10671 22:51:12.916718 <6>[ 10.618982] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10672 22:51:12.930302 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Se<6>[ 10.633140] remoteproc remoteproc0: scp is available
10673 22:51:12.930874 t.
10674 22:51:12.931243
10675 22:51:12.936779 <3>[ 10.633850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 22:51:12.943598 <6>[ 10.639553] remoteproc remoteproc0: powering up scp
10677 22:51:12.949544 <3>[ 10.647898] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 22:51:12.959584 <6>[ 10.653034] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10679 22:51:12.965893 <6>[ 10.654051] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10680 22:51:12.976092 <6>[ 10.654112] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10681 22:51:12.982771 <6>[ 10.654127] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10682 22:51:12.992683 <3>[ 10.661106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 22:51:12.999301 <6>[ 10.669540] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10684 22:51:13.005977 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10685 22:51:13.006567
10686 22:51:13.015406 <6>[ 10.717036] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10687 22:51:13.025411 [[0;32m OK [<3>[ 10.726849] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 22:51:13.035507 0m] Reached targ<3>[ 10.735562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 22:51:13.045323 et [0;1;39mtime<4>[ 10.741456] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10690 22:51:13.048625 <4>[ 10.741456] Fallback method does not support PEC.
10691 22:51:13.058577 <3>[ 10.744996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 22:51:13.065216 rs.target[0m - <4>[ 10.761788] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10693 22:51:13.075068 <3>[ 10.768093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 22:51:13.081909 <3>[ 10.768097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 22:51:13.088547 <6>[ 10.789532] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10696 22:51:13.092167 Timer Units.
10697 22:51:13.092718
10698 22:51:13.095706 <6>[ 10.799945] pci_bus 0000:00: root bus resource [bus 00-ff]
10699 22:51:13.102234 <6>[ 10.806887] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10700 22:51:13.112164 <3>[ 10.808384] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10701 22:51:13.121860 <6>[ 10.814219] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10702 22:51:13.128304 <6>[ 10.832877] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10703 22:51:13.136376 <6>[ 10.834010] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10704 22:51:13.142361 <6>[ 10.834010] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10705 22:51:13.152334 <6>[ 10.839165] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10706 22:51:13.159127 <3>[ 10.847472] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 22:51:13.165751 <6>[ 10.847663] remoteproc remoteproc0: remote processor scp is now up
10708 22:51:13.175962 <3>[ 10.866516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 22:51:13.182162 <4>[ 10.866598] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10710 22:51:13.185882 <6>[ 10.871122] pci 0000:00:00.0: supports D1 D2
10711 22:51:13.191937 <6>[ 10.897366] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10712 22:51:13.202208 [[0;32m OK [<3>[ 10.905146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 22:51:13.212419 0m] Listening on<3>[ 10.914017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 22:51:13.221580 [0;1;39mdbus.s<3>[ 10.923470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 22:51:13.224995 ocket[…- D-Bus System Message Bus Socket.
10716 22:51:13.225466
10717 22:51:13.238632 <6>[ 10.940888] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10718 22:51:13.245161 <3>[ 10.942490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 22:51:13.255096 <3>[ 10.957295] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 22:51:13.262081 <3>[ 10.957301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 22:51:13.271836 <3>[ 10.957306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 22:51:13.278199 <3>[ 10.957310] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 22:51:13.285050 <6>[ 10.965831] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10724 22:51:13.291380 <6>[ 10.996177] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10725 22:51:13.301588 <6>[ 11.003669] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10726 22:51:13.308655 <6>[ 11.011154] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10727 22:51:13.314786 [[0;32m OK [<6>[ 11.018750] pci 0000:01:00.0: supports D1 D2
10728 22:51:13.321137 0m] Reached targ<6>[ 11.019168] mc: Linux media interface: v0.10
10729 22:51:13.328194 et [0;1;39msock<6>[ 11.024593] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10730 22:51:13.331329 ets.target[0m - Socket Units.
10731 22:51:13.331880
10732 22:51:13.337847 <3>[ 11.041066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 22:51:13.347490 <6>[ 11.041122] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10734 22:51:13.348085
10735 22:51:13.359537 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10736 22:51:13.360096
10737 22:51:13.372016 <6>[ 11.074368] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10738 22:51:13.378779 <6>[ 11.081302] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10739 22:51:13.385369 <6>[ 11.089391] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10740 22:51:13.395389 <6>[ 11.097398] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10741 22:51:13.402127 <6>[ 11.105405] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10742 22:51:13.411770 <6>[ 11.113415] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10743 22:51:13.415046 <6>[ 11.121418] pci 0000:00:00.0: PCI bridge to [bus 01]
10744 22:51:13.425008 <6>[ 11.126636] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10745 22:51:13.431671 <6>[ 11.134800] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10746 22:51:13.438099 <6>[ 11.142870] videodev: Linux video capture interface: v2.00
10747 22:51:13.459442 <6>[ 11.158600] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10748 22:51:13.473332 <6>[ 11.175790] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10749 22:51:13.509479 <6>[ 11.215223] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10750 22:51:13.516670 <6>[ 11.222250] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10751 22:51:13.532698 <6>[ 11.238552] Bluetooth: Core ver 2.22
10752 22:51:13.539620 Startin<6>[ 11.242634] NET: Registered PF_BLUETOOTH protocol family
10753 22:51:13.549256 g [0;1;39mdbus.service[0m - D-<6>[ 11.250993] Bluetooth: HCI device and connection manager initialized
10754 22:51:13.555877 Bus System Messa<6>[ 11.259456] Bluetooth: HCI socket layer initialized
10755 22:51:13.556363 ge Bus...
10756 22:51:13.556726
10757 22:51:13.562650 <6>[ 11.266033] Bluetooth: L2CAP socket layer initialized
10758 22:51:13.565707 <6>[ 11.272059] Bluetooth: SCO socket layer initialized
10759 22:51:13.597508 Starting [0;1;39msystemd-logind.se…ice[0m - User Lo<3>[ 11.298153] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10760 22:51:13.598128 gin Management...
10761 22:51:13.598501
10762 22:51:13.621172 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10763 22:51:13.621759
10764 22:51:13.643495 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10765 22:51:13.644048
10766 22:51:13.732089 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10767 22:51:13.732667
10768 22:51:13.750811 <3>[ 11.447487] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10769 22:51:13.763304 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10770 22:51:13.763877
10771 22:51:13.775741 <3>[ 11.475569] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10772 22:51:13.785788 <6>[ 11.478609] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10773 22:51:13.812966 <6>[ 11.504281] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10774 22:51:13.822556 <4>[ 11.506598] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10775 22:51:13.829606 <3>[ 11.506617] Bluetooth: hci0: Failed to load firmware file (-2)
10776 22:51:13.832601 <3>[ 11.506620] Bluetooth: hci0: Failed to set up firmware (-2)
10777 22:51:13.845883 <4>[ 11.506625] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10778 22:51:13.852121 <3>[ 11.509647] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10779 22:51:13.858630 <6>[ 11.525157] usbcore: registered new interface driver btusb
10780 22:51:13.891763 <6>[ 11.590703] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10781 22:51:13.901993 <6>[ 11.607826] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10782 22:51:13.914403 <6>[ 11.616973] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10783 22:51:13.922408 <6>[ 11.628383] usbcore: registered new interface driver uvcvideo
10784 22:51:13.951510 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10785 22:51:13.952082
10786 22:51:13.978655 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10787 22:51:13.979227
10788 22:51:13.998136 [[0;32m OK [<3>[ 11.700954] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10789 22:51:14.008463 <6>[ 11.705531] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10790 22:51:14.015155 0m] Finished [0<6>[ 11.718264] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10791 22:51:14.022052 ;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10792 22:51:14.022535
10793 22:51:14.032174 <3>[ 11.733179] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10794 22:51:14.038606 [[0;32m OK [<6>[ 11.744716] mt7921e 0000:01:00.0: ASIC revision: 79610010
10795 22:51:14.048563 0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10796 22:51:14.049201
10797 22:51:14.061560 <3>[ 11.763827] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10798 22:51:14.095178 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Man<3>[ 11.797190] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10799 22:51:14.095733 agement.
10800 22:51:14.096100
10801 22:51:14.116264 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10802 22:51:14.116823
10803 22:51:14.145276 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/r<6>[ 11.846306] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10804 22:51:14.145843 <6>[ 11.846306]
10805 22:51:14.148432 fkill Watch.
10806 22:51:14.148893
10807 22:51:14.191346 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10808 22:51:14.191957
10809 22:51:14.213735 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10810 22:51:14.214378
10811 22:51:14.231216 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10812 22:51:14.231799
10813 22:51:14.247285 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10814 22:51:14.247859
10815 22:51:14.267497 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10816 22:51:14.268062
10817 22:51:14.316055 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10818 22:51:14.316643
10819 22:51:14.362825 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10820 22:51:14.363384
10821 22:51:14.385135 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10822 22:51:14.385714
10823 22:51:14.417459 [[0;32m OK [<6>[ 12.117095] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10824 22:51:14.423687 0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10825 22:51:14.424286
10826 22:51:14.454823
10827 22:51:14.455376
10828 22:51:14.458399 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10829 22:51:14.458963
10830 22:51:14.461492 debian-bookworm-arm64 login: root (automatic login)
10831 22:51:14.462102
10832 22:51:14.462478
10833 22:51:14.484438 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
10834 22:51:14.484987
10835 22:51:14.491045 The programs included with the Debian GNU/Linux system are free software;
10836 22:51:14.497669 the exact distribution terms for each program are described in the
10837 22:51:14.500850 individual files in /usr/share/doc/*/copyright.
10838 22:51:14.501409
10839 22:51:14.507476 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10840 22:51:14.510799 permitted by applicable law.
10841 22:51:14.512340 Matched prompt #10: / #
10843 22:51:14.513431 Setting prompt string to ['/ #']
10844 22:51:14.513947 end: 2.2.5.1 login-action (duration 00:00:13) [common]
10846 22:51:14.515088 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
10847 22:51:14.515564 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
10848 22:51:14.515947 Setting prompt string to ['/ #']
10849 22:51:14.516282 Forcing a shell prompt, looking for ['/ #']
10851 22:51:14.567080 / #
10852 22:51:14.567755 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10853 22:51:14.568185 Waiting using forced prompt support (timeout 00:02:30)
10854 22:51:14.573291
10855 22:51:14.574281 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10856 22:51:14.574831 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
10857 22:51:14.575332 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10858 22:51:14.575892 end: 2.2 depthcharge-retry (duration 00:01:21) [common]
10859 22:51:14.576353 end: 2 depthcharge-action (duration 00:01:21) [common]
10860 22:51:14.576833 start: 3 lava-test-retry (timeout 00:08:07) [common]
10861 22:51:14.577306 start: 3.1 lava-test-shell (timeout 00:08:07) [common]
10862 22:51:14.577750 Using namespace: common
10864 22:51:14.679034 / # #
10865 22:51:14.679702 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10866 22:51:14.685419 #
10867 22:51:14.686300 Using /lava-13683663
10869 22:51:14.787661 / # export SHELL=/bin/sh
10870 22:51:14.793918 export SHELL=/bin/sh
10872 22:51:14.895777 / # . /lava-13683663/environment
10873 22:51:14.902200 . /lava-13683663/environment
10875 22:51:15.003906 / # /lava-13683663/bin/lava-test-runner /lava-13683663/0
10876 22:51:15.004559 Test shell timeout: 10s (minimum of the action and connection timeout)
10877 22:51:15.010390 /lava-13683663/bin/lava-test-runner /lava-13683663/0
10878 22:51:15.033337 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10879 22:51:15.039543 + cd /lava-13683663/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10880 22:51:15.040115 + cat uuid
10881 22:51:15.042878 + UUID=13683663_1.5.2.3.1
10882 22:51:15.043361 + set +x
10883 22:51:15.049809 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 13683663_1.5.2.3.1>
10884 22:51:15.050713 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 13683663_1.5.2.3.1
10885 22:51:15.051121 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (13683663_1.5.2.3.1)
10886 22:51:15.051633 Skipping test definition patterns.
10887 22:51:15.052879 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10888 22:51:15.056708 Received signal: <TESTCASE> TEST_CASE_ID=device-presence<4
10889 22:51:15.057371 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'device-presence<4', 'result': 'unknown'}
10890 22:51:15.066281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence<4>[ 12.767647] use of bytesused == 0 is deprecated and will be removed in the future,
10891 22:51:15.066854 RESULT=pass>
10892 22:51:15.069442 d<4>[ 12.776074] use the actual size instead.
10893 22:51:15.072736 evice: /dev/video2
10894 22:51:15.084340 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
10895 22:51:15.093949 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
10896 22:51:15.099803
10897 22:51:15.112650 Compliance test for mtk-vcodec-enc device /dev/video2:
10898 22:51:15.118958
10899 22:51:15.129296 Driver Info:
10900 22:51:15.139142 Driver name : mtk-vcodec-enc
10901 22:51:15.152082 Card type : MT8192 video encoder
10902 22:51:15.163059 Bus info : platform:17020000.vcodec
10903 22:51:15.169295 Driver version : 6.1.90
10904 22:51:15.181841 Capabilities : 0x84204000
10905 22:51:15.195452 Video Memory-to-Memory Multiplanar
10906 22:51:15.206410 Streaming
10907 22:51:15.217070 Extended Pix Format
10908 22:51:15.226630 Device Capabilities
10909 22:51:15.237373 Device Caps : 0x04204000
10910 22:51:15.251493 Video Memory-to-Memory Multiplanar
10911 22:51:15.262893 <6>[ 12.969148] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10912 22:51:15.266385 Streaming
10913 22:51:15.280984 Extended Pix Format
10914 22:51:15.293580 Detected Stateful Encoder
10915 22:51:15.306802
10916 22:51:15.325889 Required ioctls:
10917 22:51:15.342007 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10918 22:51:15.342611 test VIDIOC_QUERYCAP: OK
10919 22:51:15.343267 Received signal: <TESTSET> START Required-ioctls
10920 22:51:15.343661 Starting test_set Required-ioctls
10921 22:51:15.363888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10922 22:51:15.364739 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10924 22:51:15.366627 test invalid ioctls: OK
10925 22:51:15.389984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
10926 22:51:15.390592
10927 22:51:15.391230 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
10929 22:51:15.401046 Allow for multiple opens:
10930 22:51:15.407430 <LAVA_SIGNAL_TESTSET STOP>
10931 22:51:15.408293 Received signal: <TESTSET> STOP
10932 22:51:15.408696 Closing test_set Required-ioctls
10933 22:51:15.416532 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
10934 22:51:15.417372 Received signal: <TESTSET> START Allow-for-multiple-opens
10935 22:51:15.417768 Starting test_set Allow-for-multiple-opens
10936 22:51:15.419887 test second /dev/video2 open: OK
10937 22:51:15.440457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
10938 22:51:15.441441 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
10940 22:51:15.443779 test VIDIOC_QUERYCAP: OK
10941 22:51:15.461118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10942 22:51:15.461957 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10944 22:51:15.464391 test VIDIOC_G/S_PRIORITY: OK
10945 22:51:15.484852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
10946 22:51:15.485698 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
10948 22:51:15.487729 test for unlimited opens: OK
10949 22:51:15.509111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
10950 22:51:15.509678
10951 22:51:15.510375 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
10953 22:51:15.524593 Debug ioctls:
10954 22:51:15.530419 <LAVA_SIGNAL_TESTSET STOP>
10955 22:51:15.531267 Received signal: <TESTSET> STOP
10956 22:51:15.531648 Closing test_set Allow-for-multiple-opens
10957 22:51:15.539572 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
10958 22:51:15.540417 Received signal: <TESTSET> START Debug-ioctls
10959 22:51:15.540822 Starting test_set Debug-ioctls
10960 22:51:15.542732 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
10961 22:51:15.561743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
10962 22:51:15.562642 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
10964 22:51:15.568369 test VIDIOC_LOG_STATUS: OK (Not Supported)
10965 22:51:15.585744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
10966 22:51:15.586416
10967 22:51:15.587103 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
10969 22:51:15.596433 Input ioctls:
10970 22:51:15.602454 <LAVA_SIGNAL_TESTSET STOP>
10971 22:51:15.603288 Received signal: <TESTSET> STOP
10972 22:51:15.603684 Closing test_set Debug-ioctls
10973 22:51:15.611292 <LAVA_SIGNAL_TESTSET START Input-ioctls>
10974 22:51:15.612111 Received signal: <TESTSET> START Input-ioctls
10975 22:51:15.612504 Starting test_set Input-ioctls
10976 22:51:15.614923 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
10977 22:51:15.641381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
10978 22:51:15.642246 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
10980 22:51:15.644521 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
10981 22:51:15.662562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
10982 22:51:15.663452 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
10984 22:51:15.669202 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
10985 22:51:15.693384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
10986 22:51:15.694233 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
10988 22:51:15.699658 test VIDIOC_ENUMAUDIO: OK (Not Supported)
10989 22:51:15.716159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
10990 22:51:15.717002 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
10992 22:51:15.718853 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
10993 22:51:15.745456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
10994 22:51:15.746329 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
10996 22:51:15.748591 test VIDIOC_G/S_AUDIO: OK (Not Supported)
10997 22:51:15.769420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
10998 22:51:15.770375 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11000 22:51:15.772419 Inputs: 0 Audio Inputs: 0 Tuners: 0
11001 22:51:15.781345
11002 22:51:15.798501 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11003 22:51:15.823755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11004 22:51:15.824606 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11006 22:51:15.830432 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11007 22:51:15.851681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11008 22:51:15.852520 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11010 22:51:15.857778 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11011 22:51:15.875560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11012 22:51:15.876392 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11014 22:51:15.881681 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11015 22:51:15.900349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11016 22:51:15.901191 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11018 22:51:15.906371 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11019 22:51:15.925055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11020 22:51:15.925623
11021 22:51:15.926265 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11023 22:51:15.944538 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11024 22:51:15.968700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11025 22:51:15.969543 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11027 22:51:15.975279 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11028 22:51:15.996649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11029 22:51:15.997520 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11031 22:51:15.999076 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11032 22:51:16.015684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11033 22:51:16.016048 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11035 22:51:16.019093 test VIDIOC_G/S_EDID: OK (Not Supported)
11036 22:51:16.040391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11037 22:51:16.040630
11038 22:51:16.040961 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11040 22:51:16.055729 Control ioctls:
11041 22:51:16.061664 <LAVA_SIGNAL_TESTSET STOP>
11042 22:51:16.062334 Received signal: <TESTSET> STOP
11043 22:51:16.062675 Closing test_set Input-ioctls
11044 22:51:16.070483 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11045 22:51:16.071433 Received signal: <TESTSET> START Control-ioctls
11046 22:51:16.071832 Starting test_set Control-ioctls
11047 22:51:16.074090 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11048 22:51:16.096740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11049 22:51:16.097308 test VIDIOC_QUERYCTRL: OK
11050 22:51:16.097954 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11052 22:51:16.119686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11053 22:51:16.120503 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11055 22:51:16.122740 test VIDIOC_G/S_CTRL: OK
11056 22:51:16.142304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11057 22:51:16.143143 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11059 22:51:16.145399 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11060 22:51:16.165884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11061 22:51:16.166776 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11063 22:51:16.172553 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11064 22:51:16.179106 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11065 22:51:16.201340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11066 22:51:16.202172 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11068 22:51:16.204676 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11069 22:51:16.225485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11070 22:51:16.226359 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11072 22:51:16.228609 Standard Controls: 16 Private Controls: 0
11073 22:51:16.234451
11074 22:51:16.244722 Format ioctls:
11075 22:51:16.252014 <LAVA_SIGNAL_TESTSET STOP>
11076 22:51:16.252856 Received signal: <TESTSET> STOP
11077 22:51:16.253245 Closing test_set Control-ioctls
11078 22:51:16.261506 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11079 22:51:16.262431 Received signal: <TESTSET> START Format-ioctls
11080 22:51:16.262832 Starting test_set Format-ioctls
11081 22:51:16.264684 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11082 22:51:16.287989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11083 22:51:16.288845 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11085 22:51:16.291265 test VIDIOC_G/S_PARM: OK
11086 22:51:16.309252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11087 22:51:16.310155 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11089 22:51:16.312560 test VIDIOC_G_FBUF: OK (Not Supported)
11090 22:51:16.334110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11091 22:51:16.334960 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11093 22:51:16.337505 test VIDIOC_G_FMT: OK
11094 22:51:16.358434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11095 22:51:16.359267 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11097 22:51:16.361397 test VIDIOC_TRY_FMT: OK
11098 22:51:16.381509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11099 22:51:16.382377 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11101 22:51:16.387551 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11102 22:51:16.391989 test VIDIOC_S_FMT: FAIL
11103 22:51:16.421321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11104 22:51:16.422142 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11106 22:51:16.424693 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11107 22:51:16.444216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11108 22:51:16.445221 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11110 22:51:16.447321 test Cropping: OK
11111 22:51:16.469235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11112 22:51:16.470081 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11114 22:51:16.472216 test Composing: OK (Not Supported)
11115 22:51:16.493314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11116 22:51:16.494150 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11118 22:51:16.496586 test Scaling: OK (Not Supported)
11119 22:51:16.521504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11120 22:51:16.522103
11121 22:51:16.522755 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11123 22:51:16.531567 Codec ioctls:
11124 22:51:16.537647 <LAVA_SIGNAL_TESTSET STOP>
11125 22:51:16.538641 Received signal: <TESTSET> STOP
11126 22:51:16.539135 Closing test_set Format-ioctls
11127 22:51:16.546652 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11128 22:51:16.547482 Received signal: <TESTSET> START Codec-ioctls
11129 22:51:16.547867 Starting test_set Codec-ioctls
11130 22:51:16.549649 test VIDIOC_(TRY_)ENCODER_CMD: OK
11131 22:51:16.569591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11132 22:51:16.570495 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11134 22:51:16.575952 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11135 22:51:16.597229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11136 22:51:16.598067 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11138 22:51:16.603864 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11139 22:51:16.625254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11140 22:51:16.625843
11141 22:51:16.626552 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11143 22:51:16.638707 Buffer ioctls:
11144 22:51:16.644996 <LAVA_SIGNAL_TESTSET STOP>
11145 22:51:16.645825 Received signal: <TESTSET> STOP
11146 22:51:16.646261 Closing test_set Codec-ioctls
11147 22:51:16.653531 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11148 22:51:16.654384 Received signal: <TESTSET> START Buffer-ioctls
11149 22:51:16.654774 Starting test_set Buffer-ioctls
11150 22:51:16.657058 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11151 22:51:16.680802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11152 22:51:16.681646 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11154 22:51:16.683760 test CREATE_BUFS maximum buffers: OK
11155 22:51:16.702410 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11157 22:51:16.705335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11158 22:51:16.705942 test VIDIOC_EXPBUF: OK
11159 22:51:16.725691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11160 22:51:16.726560 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11162 22:51:16.729256 test Requests: OK (Not Supported)
11163 22:51:16.748584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11164 22:51:16.749146
11165 22:51:16.749788 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11167 22:51:16.757772 Test input 0:
11168 22:51:16.768009
11169 22:51:16.779518 Streaming ioctls:
11170 22:51:16.786773 <LAVA_SIGNAL_TESTSET STOP>
11171 22:51:16.787633 Received signal: <TESTSET> STOP
11172 22:51:16.788021 Closing test_set Buffer-ioctls
11173 22:51:16.796113 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11174 22:51:16.796945 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11175 22:51:16.797342 Starting test_set Streaming-ioctls_Test-input-0
11176 22:51:16.799315 test read/write: OK (Not Supported)
11177 22:51:16.818457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11178 22:51:16.819333 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11180 22:51:16.825439 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11181 22:51:16.832833 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11182 22:51:16.838733 test blocking wait: FAIL
11183 22:51:16.864552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11184 22:51:16.865393 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11186 22:51:16.870937 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11187 22:51:16.874134 test MMAP (select): FAIL
11188 22:51:16.898592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11189 22:51:16.899469 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11191 22:51:16.904802 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11192 22:51:16.909176 test MMAP (epoll): FAIL
11193 22:51:16.935444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11194 22:51:16.936258 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11196 22:51:16.942164 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11197 22:51:16.949329 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11198 22:51:16.958014 test USERPTR (select): FAIL
11199 22:51:16.982954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11200 22:51:16.983790 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11202 22:51:16.989463 test DMABUF: Cannot test, specify --expbuf-device
11203 22:51:16.993834
11204 22:51:17.013191 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11205 22:51:17.018073 <LAVA_TEST_RUNNER EXIT>
11206 22:51:17.018806 ok: lava_test_shell seems to have completed
11207 22:51:17.019210 Marking unfinished test run as failed
11209 22:51:17.024531 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11210 22:51:17.025176 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11211 22:51:17.025643 end: 3 lava-test-retry (duration 00:00:02) [common]
11212 22:51:17.026134 start: 4 finalize (timeout 00:08:04) [common]
11213 22:51:17.026626 start: 4.1 power-off (timeout 00:00:30) [common]
11214 22:51:17.027436 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11215 22:51:17.118697 >> Command sent successfully.
11216 22:51:17.129639 Returned 0 in 0 seconds
11217 22:51:17.231010 end: 4.1 power-off (duration 00:00:00) [common]
11219 22:51:17.232509 start: 4.2 read-feedback (timeout 00:08:04) [common]
11220 22:51:17.233773 Listened to connection for namespace 'common' for up to 1s
11221 22:51:18.234329 Finalising connection for namespace 'common'
11222 22:51:18.235085 Disconnecting from shell: Finalise
11223 22:51:18.235662 / #
11224 22:51:18.336775 end: 4.2 read-feedback (duration 00:00:01) [common]
11225 22:51:18.337452 end: 4 finalize (duration 00:00:01) [common]
11226 22:51:18.338130 Cleaning after the job
11227 22:51:18.338784 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/ramdisk
11228 22:51:18.360889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/kernel
11229 22:51:18.389497 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/dtb
11230 22:51:18.389771 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683663/tftp-deploy-80lgk2y2/modules
11231 22:51:18.396986 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683663
11232 22:51:18.458633 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683663
11233 22:51:18.458811 Job finished correctly