Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 23
- Errors: 1
- Kernel Errors: 26
- Boot result: PASS
1 22:49:57.214262 lava-dispatcher, installed at version: 2024.01
2 22:49:57.214457 start: 0 validate
3 22:49:57.214583 Start time: 2024-05-07 22:49:57.214576+00:00 (UTC)
4 22:49:57.214700 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:49:57.214828 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 22:49:57.475895 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:49:57.476778 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:50:15.242243 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:50:15.243016 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:50:15.503636 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:50:15.504380 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:50:21.265660 validate duration: 24.05
14 22:50:21.265927 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:50:21.266035 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:50:21.266186 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:50:21.266345 Not decompressing ramdisk as can be used compressed.
18 22:50:21.266467 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 22:50:21.266538 saving as /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/ramdisk/rootfs.cpio.gz
20 22:50:21.266604 total size: 28105535 (26 MB)
21 22:50:21.522881 progress 0 % (0 MB)
22 22:50:21.530035 progress 5 % (1 MB)
23 22:50:21.537181 progress 10 % (2 MB)
24 22:50:21.544500 progress 15 % (4 MB)
25 22:50:21.551948 progress 20 % (5 MB)
26 22:50:21.559191 progress 25 % (6 MB)
27 22:50:21.566606 progress 30 % (8 MB)
28 22:50:21.574001 progress 35 % (9 MB)
29 22:50:21.581168 progress 40 % (10 MB)
30 22:50:21.588169 progress 45 % (12 MB)
31 22:50:21.595334 progress 50 % (13 MB)
32 22:50:21.602552 progress 55 % (14 MB)
33 22:50:21.609797 progress 60 % (16 MB)
34 22:50:21.616955 progress 65 % (17 MB)
35 22:50:21.624151 progress 70 % (18 MB)
36 22:50:21.631332 progress 75 % (20 MB)
37 22:50:21.638569 progress 80 % (21 MB)
38 22:50:21.645765 progress 85 % (22 MB)
39 22:50:21.652743 progress 90 % (24 MB)
40 22:50:21.659919 progress 95 % (25 MB)
41 22:50:21.667155 progress 100 % (26 MB)
42 22:50:21.667389 26 MB downloaded in 0.40 s (66.88 MB/s)
43 22:50:21.667555 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:50:21.667798 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:50:21.667886 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:50:21.668000 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:50:21.668160 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:50:21.668232 saving as /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/kernel/Image
50 22:50:21.668296 total size: 54682112 (52 MB)
51 22:50:21.668359 No compression specified
52 22:50:21.669475 progress 0 % (0 MB)
53 22:50:21.683429 progress 5 % (2 MB)
54 22:50:21.697190 progress 10 % (5 MB)
55 22:50:21.711123 progress 15 % (7 MB)
56 22:50:21.724792 progress 20 % (10 MB)
57 22:50:21.738547 progress 25 % (13 MB)
58 22:50:21.752179 progress 30 % (15 MB)
59 22:50:21.766401 progress 35 % (18 MB)
60 22:50:21.780577 progress 40 % (20 MB)
61 22:50:21.794579 progress 45 % (23 MB)
62 22:50:21.808547 progress 50 % (26 MB)
63 22:50:21.822297 progress 55 % (28 MB)
64 22:50:21.836202 progress 60 % (31 MB)
65 22:50:21.849986 progress 65 % (33 MB)
66 22:50:21.863987 progress 70 % (36 MB)
67 22:50:21.878157 progress 75 % (39 MB)
68 22:50:21.892212 progress 80 % (41 MB)
69 22:50:21.906344 progress 85 % (44 MB)
70 22:50:21.920068 progress 90 % (46 MB)
71 22:50:21.933925 progress 95 % (49 MB)
72 22:50:21.947380 progress 100 % (52 MB)
73 22:50:21.947644 52 MB downloaded in 0.28 s (186.68 MB/s)
74 22:50:21.947801 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:50:21.948031 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:50:21.948119 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:50:21.948264 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:50:21.948435 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:50:21.948520 saving as /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/dtb/mt8192-asurada-spherion-r0.dtb
81 22:50:21.948584 total size: 47258 (0 MB)
82 22:50:21.948647 No compression specified
83 22:50:21.949783 progress 69 % (0 MB)
84 22:50:21.950058 progress 100 % (0 MB)
85 22:50:21.950213 0 MB downloaded in 0.00 s (27.70 MB/s)
86 22:50:21.950337 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:50:21.950558 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:50:21.950644 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:50:21.950727 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:50:21.950837 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:50:21.950906 saving as /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/modules/modules.tar
93 22:50:21.950967 total size: 8594396 (8 MB)
94 22:50:21.951029 Using unxz to decompress xz
95 22:50:21.954728 progress 0 % (0 MB)
96 22:50:21.974384 progress 5 % (0 MB)
97 22:50:22.000083 progress 10 % (0 MB)
98 22:50:22.024278 progress 15 % (1 MB)
99 22:50:22.047742 progress 20 % (1 MB)
100 22:50:22.073147 progress 25 % (2 MB)
101 22:50:22.097242 progress 30 % (2 MB)
102 22:50:22.121188 progress 35 % (2 MB)
103 22:50:22.146153 progress 40 % (3 MB)
104 22:50:22.171540 progress 45 % (3 MB)
105 22:50:22.196546 progress 50 % (4 MB)
106 22:50:22.222677 progress 55 % (4 MB)
107 22:50:22.248567 progress 60 % (4 MB)
108 22:50:22.273596 progress 65 % (5 MB)
109 22:50:22.298661 progress 70 % (5 MB)
110 22:50:22.322976 progress 75 % (6 MB)
111 22:50:22.348636 progress 80 % (6 MB)
112 22:50:22.375232 progress 85 % (6 MB)
113 22:50:22.405318 progress 90 % (7 MB)
114 22:50:22.434138 progress 95 % (7 MB)
115 22:50:22.460045 progress 100 % (8 MB)
116 22:50:22.465350 8 MB downloaded in 0.51 s (15.93 MB/s)
117 22:50:22.465603 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:50:22.465861 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:50:22.465957 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:50:22.466049 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:50:22.466130 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:50:22.466218 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:50:22.466437 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e
125 22:50:22.466567 makedir: /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin
126 22:50:22.466668 makedir: /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/tests
127 22:50:22.466763 makedir: /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/results
128 22:50:22.466878 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-add-keys
129 22:50:22.467022 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-add-sources
130 22:50:22.467148 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-background-process-start
131 22:50:22.467273 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-background-process-stop
132 22:50:22.467393 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-common-functions
133 22:50:22.467512 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-echo-ipv4
134 22:50:22.467708 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-install-packages
135 22:50:22.467892 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-installed-packages
136 22:50:22.468038 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-os-build
137 22:50:22.468175 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-probe-channel
138 22:50:22.468295 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-probe-ip
139 22:50:22.468414 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-target-ip
140 22:50:22.468532 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-target-mac
141 22:50:22.468650 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-target-storage
142 22:50:22.468774 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-test-case
143 22:50:22.468893 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-test-event
144 22:50:22.469011 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-test-feedback
145 22:50:22.469129 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-test-raise
146 22:50:22.469248 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-test-reference
147 22:50:22.469401 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-test-runner
148 22:50:22.469519 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-test-set
149 22:50:22.469639 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-test-shell
150 22:50:22.469761 Updating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-install-packages (oe)
151 22:50:22.469909 Updating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/bin/lava-installed-packages (oe)
152 22:50:22.470037 Creating /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/environment
153 22:50:22.470134 LAVA metadata
154 22:50:22.470213 - LAVA_JOB_ID=13683698
155 22:50:22.470278 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:50:22.470381 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:50:22.470447 skipped lava-vland-overlay
158 22:50:22.470520 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:50:22.470598 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:50:22.470659 skipped lava-multinode-overlay
161 22:50:22.470732 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:50:22.470813 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:50:22.470884 Loading test definitions
164 22:50:22.470973 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:50:22.471047 Using /lava-13683698 at stage 0
166 22:50:22.471341 uuid=13683698_1.5.2.3.1 testdef=None
167 22:50:22.471428 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:50:22.471515 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:50:22.472021 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:50:22.472242 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:50:22.472868 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:50:22.473097 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:50:22.473710 runner path: /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/0/tests/0_v4l2-compliance-uvc test_uuid 13683698_1.5.2.3.1
176 22:50:22.473865 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:50:22.474071 Creating lava-test-runner.conf files
179 22:50:22.474135 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683698/lava-overlay-omq6448e/lava-13683698/0 for stage 0
180 22:50:22.474221 - 0_v4l2-compliance-uvc
181 22:50:22.474316 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:50:22.474400 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:50:22.481476 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:50:22.481596 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:50:22.481687 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:50:22.481774 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:50:22.481858 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:50:23.347516 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:50:23.347885 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:50:23.348002 extracting modules file /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683698/extract-overlay-ramdisk-7tg37pfa/ramdisk
191 22:50:23.566233 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:50:23.566410 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 22:50:23.566509 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683698/compress-overlay-xtmfsnxn/overlay-1.5.2.4.tar.gz to ramdisk
194 22:50:23.566584 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683698/compress-overlay-xtmfsnxn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683698/extract-overlay-ramdisk-7tg37pfa/ramdisk
195 22:50:23.573106 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:50:23.573230 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 22:50:23.573345 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:50:23.573451 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 22:50:23.573536 Building ramdisk /var/lib/lava/dispatcher/tmp/13683698/extract-overlay-ramdisk-7tg37pfa/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683698/extract-overlay-ramdisk-7tg37pfa/ramdisk
200 22:50:24.291712 >> 275873 blocks
201 22:50:28.348767 rename /var/lib/lava/dispatcher/tmp/13683698/extract-overlay-ramdisk-7tg37pfa/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/ramdisk/ramdisk.cpio.gz
202 22:50:28.349197 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:50:28.349346 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 22:50:28.349460 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 22:50:28.349568 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/kernel/Image'
206 22:50:41.910558 Returned 0 in 13 seconds
207 22:50:42.011179 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/kernel/image.itb
208 22:50:42.640698 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:50:42.641053 output: Created: Tue May 7 23:50:42 2024
210 22:50:42.641132 output: Image 0 (kernel-1)
211 22:50:42.641198 output: Description:
212 22:50:42.641261 output: Created: Tue May 7 23:50:42 2024
213 22:50:42.641370 output: Type: Kernel Image
214 22:50:42.641434 output: Compression: lzma compressed
215 22:50:42.641495 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
216 22:50:42.641555 output: Architecture: AArch64
217 22:50:42.641615 output: OS: Linux
218 22:50:42.641676 output: Load Address: 0x00000000
219 22:50:42.641736 output: Entry Point: 0x00000000
220 22:50:42.641793 output: Hash algo: crc32
221 22:50:42.641850 output: Hash value: 727ee7c6
222 22:50:42.641904 output: Image 1 (fdt-1)
223 22:50:42.641960 output: Description: mt8192-asurada-spherion-r0
224 22:50:42.642014 output: Created: Tue May 7 23:50:42 2024
225 22:50:42.642069 output: Type: Flat Device Tree
226 22:50:42.642122 output: Compression: uncompressed
227 22:50:42.642176 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 22:50:42.642230 output: Architecture: AArch64
229 22:50:42.642284 output: Hash algo: crc32
230 22:50:42.642337 output: Hash value: 0f8e4d2e
231 22:50:42.642391 output: Image 2 (ramdisk-1)
232 22:50:42.642444 output: Description: unavailable
233 22:50:42.642498 output: Created: Tue May 7 23:50:42 2024
234 22:50:42.642552 output: Type: RAMDisk Image
235 22:50:42.642605 output: Compression: Unknown Compression
236 22:50:42.642659 output: Data Size: 41208333 Bytes = 40242.51 KiB = 39.30 MiB
237 22:50:42.642713 output: Architecture: AArch64
238 22:50:42.642766 output: OS: Linux
239 22:50:42.642820 output: Load Address: unavailable
240 22:50:42.642873 output: Entry Point: unavailable
241 22:50:42.642926 output: Hash algo: crc32
242 22:50:42.642980 output: Hash value: c5721967
243 22:50:42.643033 output: Default Configuration: 'conf-1'
244 22:50:42.643087 output: Configuration 0 (conf-1)
245 22:50:42.643140 output: Description: mt8192-asurada-spherion-r0
246 22:50:42.643193 output: Kernel: kernel-1
247 22:50:42.643246 output: Init Ramdisk: ramdisk-1
248 22:50:42.643300 output: FDT: fdt-1
249 22:50:42.643353 output: Loadables: kernel-1
250 22:50:42.643419 output:
251 22:50:42.643613 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 22:50:42.643714 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 22:50:42.643813 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 22:50:42.643910 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 22:50:42.643989 No LXC device requested
256 22:50:42.644070 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:50:42.644154 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 22:50:42.644234 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:50:42.644305 Checking files for TFTP limit of 4294967296 bytes.
260 22:50:42.644796 end: 1 tftp-deploy (duration 00:00:21) [common]
261 22:50:42.644900 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:50:42.644991 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:50:42.645116 substitutions:
264 22:50:42.645184 - {DTB}: 13683698/tftp-deploy-ddvax7wk/dtb/mt8192-asurada-spherion-r0.dtb
265 22:50:42.645249 - {INITRD}: 13683698/tftp-deploy-ddvax7wk/ramdisk/ramdisk.cpio.gz
266 22:50:42.645336 - {KERNEL}: 13683698/tftp-deploy-ddvax7wk/kernel/Image
267 22:50:42.645433 - {LAVA_MAC}: None
268 22:50:42.645496 - {PRESEED_CONFIG}: None
269 22:50:42.645554 - {PRESEED_LOCAL}: None
270 22:50:42.645611 - {RAMDISK}: 13683698/tftp-deploy-ddvax7wk/ramdisk/ramdisk.cpio.gz
271 22:50:42.645668 - {ROOT_PART}: None
272 22:50:42.645725 - {ROOT}: None
273 22:50:42.645781 - {SERVER_IP}: 192.168.201.1
274 22:50:42.645837 - {TEE}: None
275 22:50:42.645892 Parsed boot commands:
276 22:50:42.645948 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:50:42.646116 Parsed boot commands: tftpboot 192.168.201.1 13683698/tftp-deploy-ddvax7wk/kernel/image.itb 13683698/tftp-deploy-ddvax7wk/kernel/cmdline
278 22:50:42.646208 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:50:42.646295 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:50:42.646388 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:50:42.646477 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:50:42.646550 Not connected, no need to disconnect.
283 22:50:42.646624 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:50:42.646704 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:50:42.646774 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 22:50:42.650291 Setting prompt string to ['lava-test: # ']
287 22:50:42.650650 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:50:42.650778 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:50:42.650881 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:50:42.650977 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:50:42.651169 Calling: '/usr/local/bin/chromebook-reboot.sh' 'mt8192-asurada-spherion-r0-cbg-1'
292 22:50:56.169316 Returned 0 in 13 seconds
293 22:50:56.270022 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 22:50:56.270617 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 22:50:56.270718 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 22:50:56.270810 Setting prompt string to 'Starting depthcharge on Spherion...'
298 22:50:56.270879 Changing prompt to 'Starting depthcharge on Spherion...'
299 22:50:56.270947 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 22:50:56.271221 [Enter `^Ec?' for help]
301 22:50:56.271308
302 22:50:56.271452
303 22:50:56.271561 F0: 102B 0000
304 22:50:56.271623
305 22:50:56.271683 F3: 1001 0000 [0200]
306 22:50:56.271743
307 22:50:56.271802 F3: 1001 0000
308 22:50:56.271857
309 22:50:56.271912 F7: 102D 0000
310 22:50:56.271968
311 22:50:56.272023 F1: 0000 0000
312 22:50:56.272078
313 22:50:56.272133 V0: 0000 0000 [0001]
314 22:50:56.272187
315 22:50:56.272242 00: 0007 8000
316 22:50:56.272298
317 22:50:56.272353 01: 0000 0000
318 22:50:56.272409
319 22:50:56.272464 BP: 0C00 0209 [0000]
320 22:50:56.272518
321 22:50:56.272573 G0: 1182 0000
322 22:50:56.272627
323 22:50:56.272681 EC: 0000 0021 [4000]
324 22:50:56.272735
325 22:50:56.272790 S7: 0000 0000 [0000]
326 22:50:56.272844
327 22:50:56.272898 CC: 0000 0000 [0001]
328 22:50:56.272952
329 22:50:56.273005 T0: 0000 0040 [010F]
330 22:50:56.273060
331 22:50:56.273114 Jump to BL
332 22:50:56.273167
333 22:50:56.273221
334 22:50:56.273275
335 22:50:56.273375
336 22:50:56.273430 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 22:50:56.273488 ARM64: Exception handlers installed.
338 22:50:56.273543 ARM64: Testing exception
339 22:50:56.273597 ARM64: Done test exception
340 22:50:56.273651 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 22:50:56.273707 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 22:50:56.273763 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 22:50:56.273818 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 22:50:56.273873 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 22:50:56.273928 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 22:50:56.273983 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 22:50:56.274038 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 22:50:56.274092 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 22:50:56.274147 WDT: Last reset was cold boot
350 22:50:56.274208 SPI1(PAD0) initialized at 2873684 Hz
351 22:50:56.274265 SPI5(PAD0) initialized at 992727 Hz
352 22:50:56.274319 VBOOT: Loading verstage.
353 22:50:56.274374 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 22:50:56.274428 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 22:50:56.274483 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 22:50:56.274539 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 22:50:56.274594 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 22:50:56.274649 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 22:50:56.274704 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 22:50:56.274759
361 22:50:56.274813
362 22:50:56.274867 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 22:50:56.274922 ARM64: Exception handlers installed.
364 22:50:56.274977 ARM64: Testing exception
365 22:50:56.275031 ARM64: Done test exception
366 22:50:56.275085 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 22:50:56.275140 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 22:50:56.275195 Probing TPM: . done!
369 22:50:56.275248 TPM ready after 0 ms
370 22:50:56.275303 Connected to device vid:did:rid of 1ae0:0028:00
371 22:50:56.275358 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 22:50:56.275413 Initialized TPM device CR50 revision 0
373 22:50:56.275467 tlcl_send_startup: Startup return code is 0
374 22:50:56.275522 TPM: setup succeeded
375 22:50:56.275577 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 22:50:56.275631 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 22:50:56.275686 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 22:50:56.275740 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 22:50:56.275795 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 22:50:56.275850 in-header: 03 07 00 00 08 00 00 00
381 22:50:56.275904 in-data: aa e4 47 04 13 02 00 00
382 22:50:56.275958 Chrome EC: UHEPI supported
383 22:50:56.276012 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 22:50:56.276067 in-header: 03 a9 00 00 08 00 00 00
385 22:50:56.276121 in-data: 84 60 60 08 00 00 00 00
386 22:50:56.276175 Phase 1
387 22:50:56.276229 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 22:50:56.276283 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 22:50:56.276338 VB2:vb2_check_recovery() Recovery was requested manually
390 22:50:56.276394 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 22:50:56.276448 Recovery requested (1009000e)
392 22:50:56.276502 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:50:56.276557 tlcl_extend: response is 0
394 22:50:56.276612 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:50:56.276666 tlcl_extend: response is 0
396 22:50:56.276720 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:50:56.276775 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:50:56.276830 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:50:56.276884
400 22:50:56.276938
401 22:50:56.276992 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:50:56.277047 ARM64: Exception handlers installed.
403 22:50:56.277101 ARM64: Testing exception
404 22:50:56.277155 ARM64: Done test exception
405 22:50:56.277209 pmic_efuse_setting: Set efuses in 11 msecs
406 22:50:56.277263 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:50:56.277346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:50:56.277417 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:50:56.277662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:50:56.277726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:50:56.277781 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:50:56.277835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:50:56.277890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:50:56.277944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:50:56.278032 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:50:56.278168 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:50:56.278270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:50:56.278355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:50:56.278440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:50:56.278525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:50:56.278612 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:50:56.278697 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:50:56.278782 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:50:56.278868 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:50:56.278953 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:50:56.279038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:50:56.279123 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:50:56.279208 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:50:56.279293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:50:56.279378 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:50:56.279463 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:50:56.279548 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:50:56.279633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:50:56.279718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:50:56.279803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:50:56.279887 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:50:56.279972 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:50:56.280057 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:50:56.280142 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:50:56.280265 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:50:56.280350 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:50:56.280429 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:50:56.280486 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:50:56.280542 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:50:56.280596 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:50:56.280651 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:50:56.280706 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:50:56.280760 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:50:56.280814 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:50:56.280869 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:50:56.280923 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:50:56.280977 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:50:56.281031 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:50:56.281085 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:50:56.281139 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:50:56.281194 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:50:56.281248 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:50:56.281310 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 22:50:56.281402 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:50:56.281458 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:50:56.281512 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:50:56.281567 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:50:56.281621 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:50:56.281675 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:50:56.281729 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:50:56.281783 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 22:50:56.281838 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:50:56.281892 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 22:50:56.281946 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:50:56.282000 [RTC]rtc_get_frequency_meter,154: input=15, output=773
471 22:50:56.282054 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 22:50:56.282109 [RTC]rtc_get_frequency_meter,154: input=19, output=866
473 22:50:56.282163 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 22:50:56.282234 [RTC]rtc_get_frequency_meter,154: input=16, output=795
475 22:50:56.282314 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 22:50:56.282407 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 22:50:56.282493 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 22:50:56.282579 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 22:50:56.282856 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 22:50:56.282947 ADC[4]: Raw value=902876 ID=7
481 22:50:56.283033 ADC[3]: Raw value=213179 ID=1
482 22:50:56.283118 RAM Code: 0x71
483 22:50:56.283204 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 22:50:56.283290 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 22:50:56.283377 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 22:50:56.283464 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 22:50:56.283549 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 22:50:56.283634 in-header: 03 07 00 00 08 00 00 00
489 22:50:56.283719 in-data: aa e4 47 04 13 02 00 00
490 22:50:56.283803 Chrome EC: UHEPI supported
491 22:50:56.283889 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 22:50:56.283974 in-header: 03 a9 00 00 08 00 00 00
493 22:50:56.284059 in-data: 84 60 60 08 00 00 00 00
494 22:50:56.284143 MRC: failed to locate region type 0.
495 22:50:56.284229 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 22:50:56.284314 DRAM-K: Running full calibration
497 22:50:56.284399 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 22:50:56.284484 header.status = 0x0
499 22:50:56.284568 header.version = 0x6 (expected: 0x6)
500 22:50:56.284652 header.size = 0xd00 (expected: 0xd00)
501 22:50:56.284736 header.flags = 0x0
502 22:50:56.284821 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 22:50:56.284906 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
504 22:50:56.284992 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 22:50:56.285076 dram_init: ddr_geometry: 2
506 22:50:56.285160 [EMI] MDL number = 2
507 22:50:56.285244 [EMI] Get MDL freq = 0
508 22:50:56.285352 dram_init: ddr_type: 0
509 22:50:56.285422 is_discrete_lpddr4: 1
510 22:50:56.285477 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 22:50:56.285531
512 22:50:56.285584
513 22:50:56.285638 [Bian_co] ETT version 0.0.0.1
514 22:50:56.285692 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 22:50:56.285746
516 22:50:56.285799 dramc_set_vcore_voltage set vcore to 650000
517 22:50:56.285854 Read voltage for 800, 4
518 22:50:56.285908 Vio18 = 0
519 22:50:56.285962 Vcore = 650000
520 22:50:56.286015 Vdram = 0
521 22:50:56.286069 Vddq = 0
522 22:50:56.286123 Vmddr = 0
523 22:50:56.286195 dram_init: config_dvfs: 1
524 22:50:56.286262 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 22:50:56.286316 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 22:50:56.286370 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 22:50:56.286423 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 22:50:56.286479 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 22:50:56.286532 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 22:50:56.286586 MEM_TYPE=3, freq_sel=18
531 22:50:56.286638 sv_algorithm_assistance_LP4_1600
532 22:50:56.286691 ============ PULL DRAM RESETB DOWN ============
533 22:50:56.286745 ========== PULL DRAM RESETB DOWN end =========
534 22:50:56.286799 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 22:50:56.286852 ===================================
536 22:50:56.286906 LPDDR4 DRAM CONFIGURATION
537 22:50:56.286960 ===================================
538 22:50:56.287014 EX_ROW_EN[0] = 0x0
539 22:50:56.287068 EX_ROW_EN[1] = 0x0
540 22:50:56.287122 LP4Y_EN = 0x0
541 22:50:56.287175 WORK_FSP = 0x0
542 22:50:56.287229 WL = 0x2
543 22:50:56.287283 RL = 0x2
544 22:50:56.287337 BL = 0x2
545 22:50:56.287390 RPST = 0x0
546 22:50:56.287444 RD_PRE = 0x0
547 22:50:56.287497 WR_PRE = 0x1
548 22:50:56.287550 WR_PST = 0x0
549 22:50:56.287604 DBI_WR = 0x0
550 22:50:56.287657 DBI_RD = 0x0
551 22:50:56.287710 OTF = 0x1
552 22:50:56.287765 ===================================
553 22:50:56.287819 ===================================
554 22:50:56.287873 ANA top config
555 22:50:56.287927 ===================================
556 22:50:56.287982 DLL_ASYNC_EN = 0
557 22:50:56.288035 ALL_SLAVE_EN = 1
558 22:50:56.288089 NEW_RANK_MODE = 1
559 22:50:56.288194 DLL_IDLE_MODE = 1
560 22:50:56.288264 LP45_APHY_COMB_EN = 1
561 22:50:56.288318 TX_ODT_DIS = 1
562 22:50:56.288372 NEW_8X_MODE = 1
563 22:50:56.288427 ===================================
564 22:50:56.288481 ===================================
565 22:50:56.288535 data_rate = 1600
566 22:50:56.288589 CKR = 1
567 22:50:56.288642 DQ_P2S_RATIO = 8
568 22:50:56.288696 ===================================
569 22:50:56.288751 CA_P2S_RATIO = 8
570 22:50:56.288804 DQ_CA_OPEN = 0
571 22:50:56.288858 DQ_SEMI_OPEN = 0
572 22:50:56.288911 CA_SEMI_OPEN = 0
573 22:50:56.288967 CA_FULL_RATE = 0
574 22:50:56.289021 DQ_CKDIV4_EN = 1
575 22:50:56.289074 CA_CKDIV4_EN = 1
576 22:50:56.289128 CA_PREDIV_EN = 0
577 22:50:56.289182 PH8_DLY = 0
578 22:50:56.289235 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 22:50:56.289289 DQ_AAMCK_DIV = 4
580 22:50:56.289384 CA_AAMCK_DIV = 4
581 22:50:56.289439 CA_ADMCK_DIV = 4
582 22:50:56.289493 DQ_TRACK_CA_EN = 0
583 22:50:56.289547 CA_PICK = 800
584 22:50:56.289600 CA_MCKIO = 800
585 22:50:56.289654 MCKIO_SEMI = 0
586 22:50:56.289707 PLL_FREQ = 3068
587 22:50:56.289762 DQ_UI_PI_RATIO = 32
588 22:50:56.289815 CA_UI_PI_RATIO = 0
589 22:50:56.289869 ===================================
590 22:50:56.289923 ===================================
591 22:50:56.289977 memory_type:LPDDR4
592 22:50:56.290031 GP_NUM : 10
593 22:50:56.290085 SRAM_EN : 1
594 22:50:56.290139 MD32_EN : 0
595 22:50:56.290242 ===================================
596 22:50:56.290329 [ANA_INIT] >>>>>>>>>>>>>>
597 22:50:56.290396 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 22:50:56.290455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 22:50:56.290509 ===================================
600 22:50:56.290769 data_rate = 1600,PCW = 0X7600
601 22:50:56.290833 ===================================
602 22:50:56.290889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 22:50:56.290944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 22:50:56.290999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 22:50:56.291053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 22:50:56.291107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 22:50:56.291161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 22:50:56.291214 [ANA_INIT] flow start
609 22:50:56.291267 [ANA_INIT] PLL >>>>>>>>
610 22:50:56.291321 [ANA_INIT] PLL <<<<<<<<
611 22:50:56.291374 [ANA_INIT] MIDPI >>>>>>>>
612 22:50:56.291427 [ANA_INIT] MIDPI <<<<<<<<
613 22:50:56.291480 [ANA_INIT] DLL >>>>>>>>
614 22:50:56.291543 [ANA_INIT] flow end
615 22:50:56.291599 ============ LP4 DIFF to SE enter ============
616 22:50:56.291671 ============ LP4 DIFF to SE exit ============
617 22:50:56.291739 [ANA_INIT] <<<<<<<<<<<<<
618 22:50:56.291793 [Flow] Enable top DCM control >>>>>
619 22:50:56.291847 [Flow] Enable top DCM control <<<<<
620 22:50:56.291901 Enable DLL master slave shuffle
621 22:50:56.291954 ==============================================================
622 22:50:56.292009 Gating Mode config
623 22:50:56.292063 ==============================================================
624 22:50:56.292117 Config description:
625 22:50:56.292172 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 22:50:56.292227 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 22:50:56.292282 SELPH_MODE 0: By rank 1: By Phase
628 22:50:56.292337 ==============================================================
629 22:50:56.292391 GAT_TRACK_EN = 1
630 22:50:56.292445 RX_GATING_MODE = 2
631 22:50:56.292498 RX_GATING_TRACK_MODE = 2
632 22:50:56.292553 SELPH_MODE = 1
633 22:50:56.292606 PICG_EARLY_EN = 1
634 22:50:56.292660 VALID_LAT_VALUE = 1
635 22:50:56.292713 ==============================================================
636 22:50:56.292768 Enter into Gating configuration >>>>
637 22:50:56.292822 Exit from Gating configuration <<<<
638 22:50:56.292875 Enter into DVFS_PRE_config >>>>>
639 22:50:56.292929 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 22:50:56.292987 Exit from DVFS_PRE_config <<<<<
641 22:50:56.293041 Enter into PICG configuration >>>>
642 22:50:56.293095 Exit from PICG configuration <<<<
643 22:50:56.293149 [RX_INPUT] configuration >>>>>
644 22:50:56.293202 [RX_INPUT] configuration <<<<<
645 22:50:56.293256 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 22:50:56.293337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 22:50:56.293407 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 22:50:56.293462 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 22:50:56.293516 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 22:50:56.293571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 22:50:56.293625 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 22:50:56.293679 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 22:50:56.293734 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 22:50:56.293788 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 22:50:56.293841 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 22:50:56.293895 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 22:50:56.293950 ===================================
658 22:50:56.294004 LPDDR4 DRAM CONFIGURATION
659 22:50:56.294058 ===================================
660 22:50:56.294112 EX_ROW_EN[0] = 0x0
661 22:50:56.294165 EX_ROW_EN[1] = 0x0
662 22:50:56.294219 LP4Y_EN = 0x0
663 22:50:56.294273 WORK_FSP = 0x0
664 22:50:56.294327 WL = 0x2
665 22:50:56.294380 RL = 0x2
666 22:50:56.294434 BL = 0x2
667 22:50:56.294488 RPST = 0x0
668 22:50:56.294541 RD_PRE = 0x0
669 22:50:56.294594 WR_PRE = 0x1
670 22:50:56.294648 WR_PST = 0x0
671 22:50:56.294701 DBI_WR = 0x0
672 22:50:56.294755 DBI_RD = 0x0
673 22:50:56.294808 OTF = 0x1
674 22:50:56.294862 ===================================
675 22:50:56.294916 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 22:50:56.294971 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 22:50:56.295025 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 22:50:56.295079 ===================================
679 22:50:56.295133 LPDDR4 DRAM CONFIGURATION
680 22:50:56.295186 ===================================
681 22:50:56.295240 EX_ROW_EN[0] = 0x10
682 22:50:56.295294 EX_ROW_EN[1] = 0x0
683 22:50:56.295348 LP4Y_EN = 0x0
684 22:50:56.295402 WORK_FSP = 0x0
685 22:50:56.295455 WL = 0x2
686 22:50:56.295509 RL = 0x2
687 22:50:56.295563 BL = 0x2
688 22:50:56.295617 RPST = 0x0
689 22:50:56.295670 RD_PRE = 0x0
690 22:50:56.295723 WR_PRE = 0x1
691 22:50:56.295777 WR_PST = 0x0
692 22:50:56.295831 DBI_WR = 0x0
693 22:50:56.295884 DBI_RD = 0x0
694 22:50:56.295938 OTF = 0x1
695 22:50:56.295992 ===================================
696 22:50:56.296046 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 22:50:56.296101 nWR fixed to 40
698 22:50:56.296155 [ModeRegInit_LP4] CH0 RK0
699 22:50:56.296209 [ModeRegInit_LP4] CH0 RK1
700 22:50:56.296263 [ModeRegInit_LP4] CH1 RK0
701 22:50:56.296316 [ModeRegInit_LP4] CH1 RK1
702 22:50:56.296370 match AC timing 13
703 22:50:56.296424 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 22:50:56.296478 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 22:50:56.296532 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 22:50:56.296586 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 22:50:56.296833 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 22:50:56.296894 [EMI DOE] emi_dcm 0
709 22:50:56.296951 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 22:50:56.297006 ==
711 22:50:56.297060 Dram Type= 6, Freq= 0, CH_0, rank 0
712 22:50:56.297115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 22:50:56.297171 ==
714 22:50:56.297224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 22:50:56.297278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 22:50:56.297348 [CA 0] Center 38 (7~69) winsize 63
717 22:50:56.297404 [CA 1] Center 38 (7~69) winsize 63
718 22:50:56.297458 [CA 2] Center 35 (5~66) winsize 62
719 22:50:56.297512 [CA 3] Center 35 (5~66) winsize 62
720 22:50:56.297566 [CA 4] Center 35 (4~66) winsize 63
721 22:50:56.297620 [CA 5] Center 33 (3~64) winsize 62
722 22:50:56.297673
723 22:50:56.297727 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 22:50:56.297781
725 22:50:56.297835 [CATrainingPosCal] consider 1 rank data
726 22:50:56.297890 u2DelayCellTimex100 = 270/100 ps
727 22:50:56.297944 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 22:50:56.297998 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 22:50:56.298069 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 22:50:56.298139 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 22:50:56.298192 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
732 22:50:56.298294 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 22:50:56.298362
734 22:50:56.298414 CA PerBit enable=1, Macro0, CA PI delay=33
735 22:50:56.298468
736 22:50:56.298521 [CBTSetCACLKResult] CA Dly = 33
737 22:50:56.298574 CS Dly: 6 (0~37)
738 22:50:56.298627 ==
739 22:50:56.298680 Dram Type= 6, Freq= 0, CH_0, rank 1
740 22:50:56.298734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 22:50:56.298789 ==
742 22:50:56.298843 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 22:50:56.298898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 22:50:56.298952 [CA 0] Center 38 (7~69) winsize 63
745 22:50:56.299006 [CA 1] Center 38 (8~69) winsize 62
746 22:50:56.299060 [CA 2] Center 36 (6~67) winsize 62
747 22:50:56.299114 [CA 3] Center 35 (5~66) winsize 62
748 22:50:56.299168 [CA 4] Center 35 (4~66) winsize 63
749 22:50:56.299222 [CA 5] Center 34 (4~65) winsize 62
750 22:50:56.299275
751 22:50:56.299329 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 22:50:56.299383
753 22:50:56.299436 [CATrainingPosCal] consider 2 rank data
754 22:50:56.299489 u2DelayCellTimex100 = 270/100 ps
755 22:50:56.299542 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 22:50:56.299597 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 22:50:56.299651 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 22:50:56.299704 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 22:50:56.299758 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
760 22:50:56.299811 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 22:50:56.299865
762 22:50:56.299935 CA PerBit enable=1, Macro0, CA PI delay=34
763 22:50:56.300020
764 22:50:56.300087 [CBTSetCACLKResult] CA Dly = 34
765 22:50:56.300141 CS Dly: 6 (0~38)
766 22:50:56.300194
767 22:50:56.300248 ----->DramcWriteLeveling(PI) begin...
768 22:50:56.300304 ==
769 22:50:56.300357 Dram Type= 6, Freq= 0, CH_0, rank 0
770 22:50:56.300411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 22:50:56.300465 ==
772 22:50:56.300519 Write leveling (Byte 0): 32 => 32
773 22:50:56.300573 Write leveling (Byte 1): 31 => 31
774 22:50:56.300627 DramcWriteLeveling(PI) end<-----
775 22:50:56.300681
776 22:50:56.300734 ==
777 22:50:56.300788 Dram Type= 6, Freq= 0, CH_0, rank 0
778 22:50:56.300842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 22:50:56.300896 ==
780 22:50:56.300950 [Gating] SW mode calibration
781 22:50:56.301004 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 22:50:56.301058 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 22:50:56.301112 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 22:50:56.301166 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 22:50:56.301220 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 22:50:56.301291 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 22:50:56.301364 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 22:50:56.301417 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:50:56.301471 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:50:56.301524 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:50:56.301578 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:50:56.301632 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:50:56.301686 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:50:56.301739 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:50:56.301793 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:50:56.301847 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:50:56.301901 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:50:56.301954 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:50:56.302009 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 22:50:56.302097 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
801 22:50:56.302152 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
802 22:50:56.302206 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:50:56.302260 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:50:56.302314 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:50:56.302368 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:50:56.302421 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:50:56.302475 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:50:56.302529 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
809 22:50:56.302583 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 22:50:56.302637 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
811 22:50:56.302690 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 22:50:56.302744 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 22:50:56.302798 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 22:50:56.302852 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:50:56.303096 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 22:50:56.303157 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
817 22:50:56.303213 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
818 22:50:56.303267 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:50:56.303321 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 22:50:56.303375 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:50:56.303429 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 22:50:56.303483 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:50:56.303537 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:50:56.303590 0 11 4 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
825 22:50:56.303644 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
826 22:50:56.303698 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
827 22:50:56.303751 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 22:50:56.303805 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 22:50:56.303859 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 22:50:56.303912 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:50:56.303966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:50:56.304020 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
833 22:50:56.304122 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 22:50:56.304238 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 22:50:56.304306 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 22:50:56.304360 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:50:56.304413 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:50:56.304467 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:50:56.304521 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:50:56.304575 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:50:56.304659 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:50:56.304713 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:50:56.304767 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:50:56.304821 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:50:56.304874 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:50:56.304928 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:50:56.304982 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:50:56.305036 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 22:50:56.305089 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 22:50:56.305143 Total UI for P1: 0, mck2ui 16
851 22:50:56.305197 best dqsien dly found for B0: ( 0, 14, 4)
852 22:50:56.305251 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 22:50:56.305310 Total UI for P1: 0, mck2ui 16
854 22:50:56.305400 best dqsien dly found for B1: ( 0, 14, 8)
855 22:50:56.305454 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
856 22:50:56.305508 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
857 22:50:56.305562
858 22:50:56.305616 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 22:50:56.305670 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
860 22:50:56.305723 [Gating] SW calibration Done
861 22:50:56.305777 ==
862 22:50:56.305831 Dram Type= 6, Freq= 0, CH_0, rank 0
863 22:50:56.305886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 22:50:56.305940 ==
865 22:50:56.305994 RX Vref Scan: 0
866 22:50:56.306049
867 22:50:56.306103 RX Vref 0 -> 0, step: 1
868 22:50:56.306156
869 22:50:56.306209 RX Delay -130 -> 252, step: 16
870 22:50:56.306263 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 22:50:56.306318 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 22:50:56.306372 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 22:50:56.306425 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 22:50:56.306479 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
875 22:50:56.306533 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 22:50:56.306587 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 22:50:56.306640 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 22:50:56.306694 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 22:50:56.306748 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 22:50:56.306801 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 22:50:56.306855 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
882 22:50:56.306909 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
883 22:50:56.306963 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 22:50:56.307017 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 22:50:56.307071 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 22:50:56.307124 ==
887 22:50:56.307177 Dram Type= 6, Freq= 0, CH_0, rank 0
888 22:50:56.307231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 22:50:56.307285 ==
890 22:50:56.307339 DQS Delay:
891 22:50:56.307392 DQS0 = 0, DQS1 = 0
892 22:50:56.307446 DQM Delay:
893 22:50:56.307500 DQM0 = 89, DQM1 = 78
894 22:50:56.307553 DQ Delay:
895 22:50:56.307606 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
896 22:50:56.307660 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
897 22:50:56.307714 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =69
898 22:50:56.307768 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
899 22:50:56.307821
900 22:50:56.307874
901 22:50:56.307928 ==
902 22:50:56.308012 Dram Type= 6, Freq= 0, CH_0, rank 0
903 22:50:56.308066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 22:50:56.308120 ==
905 22:50:56.308174
906 22:50:56.308226
907 22:50:56.308280 TX Vref Scan disable
908 22:50:56.308333 == TX Byte 0 ==
909 22:50:56.308387 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
910 22:50:56.308442 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
911 22:50:56.308497 == TX Byte 1 ==
912 22:50:56.308550 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 22:50:56.308604 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 22:50:56.308659 ==
915 22:50:56.308712 Dram Type= 6, Freq= 0, CH_0, rank 0
916 22:50:56.308766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 22:50:56.308820 ==
918 22:50:56.308874 TX Vref=22, minBit 6, minWin=27, winSum=440
919 22:50:56.308970 TX Vref=24, minBit 6, minWin=27, winSum=445
920 22:50:56.309026 TX Vref=26, minBit 8, minWin=27, winSum=450
921 22:50:56.309081 TX Vref=28, minBit 8, minWin=27, winSum=452
922 22:50:56.309135 TX Vref=30, minBit 5, minWin=28, winSum=460
923 22:50:56.309354 TX Vref=32, minBit 10, minWin=27, winSum=453
924 22:50:56.309419 [TxChooseVref] Worse bit 5, Min win 28, Win sum 460, Final Vref 30
925 22:50:56.309475
926 22:50:56.309530 Final TX Range 1 Vref 30
927 22:50:56.309585
928 22:50:56.309639 ==
929 22:50:56.309693 Dram Type= 6, Freq= 0, CH_0, rank 0
930 22:50:56.309747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 22:50:56.309802 ==
932 22:50:56.309887
933 22:50:56.309941
934 22:50:56.310025 TX Vref Scan disable
935 22:50:56.310079 == TX Byte 0 ==
936 22:50:56.310165 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
937 22:50:56.310252 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
938 22:50:56.310306 == TX Byte 1 ==
939 22:50:56.310392 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 22:50:56.310477 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 22:50:56.310561
942 22:50:56.310614 [DATLAT]
943 22:50:56.310673 Freq=800, CH0 RK0
944 22:50:56.310728
945 22:50:56.310781 DATLAT Default: 0xa
946 22:50:56.310834 0, 0xFFFF, sum = 0
947 22:50:56.310929 1, 0xFFFF, sum = 0
948 22:50:56.310984 2, 0xFFFF, sum = 0
949 22:50:56.311039 3, 0xFFFF, sum = 0
950 22:50:56.311095 4, 0xFFFF, sum = 0
951 22:50:56.311181 5, 0xFFFF, sum = 0
952 22:50:56.311236 6, 0xFFFF, sum = 0
953 22:50:56.311290 7, 0xFFFF, sum = 0
954 22:50:56.311344 8, 0xFFFF, sum = 0
955 22:50:56.311399 9, 0x0, sum = 1
956 22:50:56.311453 10, 0x0, sum = 2
957 22:50:56.311507 11, 0x0, sum = 3
958 22:50:56.311561 12, 0x0, sum = 4
959 22:50:56.311615 best_step = 10
960 22:50:56.311668
961 22:50:56.311721 ==
962 22:50:56.311774 Dram Type= 6, Freq= 0, CH_0, rank 0
963 22:50:56.311828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 22:50:56.311882 ==
965 22:50:56.311951 RX Vref Scan: 1
966 22:50:56.312006
967 22:50:56.312061 Set Vref Range= 32 -> 127
968 22:50:56.312115
969 22:50:56.312169 RX Vref 32 -> 127, step: 1
970 22:50:56.312223
971 22:50:56.312290 RX Delay -95 -> 252, step: 8
972 22:50:56.312343
973 22:50:56.312396 Set Vref, RX VrefLevel [Byte0]: 32
974 22:50:56.312450 [Byte1]: 32
975 22:50:56.312503
976 22:50:56.312556 Set Vref, RX VrefLevel [Byte0]: 33
977 22:50:56.312610 [Byte1]: 33
978 22:50:56.312664
979 22:50:56.312717 Set Vref, RX VrefLevel [Byte0]: 34
980 22:50:56.312770 [Byte1]: 34
981 22:50:56.312823
982 22:50:56.312876 Set Vref, RX VrefLevel [Byte0]: 35
983 22:50:56.312975 [Byte1]: 35
984 22:50:56.313066
985 22:50:56.313158 Set Vref, RX VrefLevel [Byte0]: 36
986 22:50:56.313245 [Byte1]: 36
987 22:50:56.313366
988 22:50:56.313423 Set Vref, RX VrefLevel [Byte0]: 37
989 22:50:56.313478 [Byte1]: 37
990 22:50:56.313533
991 22:50:56.313587 Set Vref, RX VrefLevel [Byte0]: 38
992 22:50:56.313641 [Byte1]: 38
993 22:50:56.313695
994 22:50:56.313749 Set Vref, RX VrefLevel [Byte0]: 39
995 22:50:56.313803 [Byte1]: 39
996 22:50:56.313857
997 22:50:56.313910 Set Vref, RX VrefLevel [Byte0]: 40
998 22:50:56.313963 [Byte1]: 40
999 22:50:56.314017
1000 22:50:56.314070 Set Vref, RX VrefLevel [Byte0]: 41
1001 22:50:56.314125 [Byte1]: 41
1002 22:50:56.314215
1003 22:50:56.314268 Set Vref, RX VrefLevel [Byte0]: 42
1004 22:50:56.314321 [Byte1]: 42
1005 22:50:56.314414
1006 22:50:56.314500 Set Vref, RX VrefLevel [Byte0]: 43
1007 22:50:56.314552 [Byte1]: 43
1008 22:50:56.314604
1009 22:50:56.314657 Set Vref, RX VrefLevel [Byte0]: 44
1010 22:50:56.314710 [Byte1]: 44
1011 22:50:56.314764
1012 22:50:56.314816 Set Vref, RX VrefLevel [Byte0]: 45
1013 22:50:56.314870 [Byte1]: 45
1014 22:50:56.314922
1015 22:50:56.314975 Set Vref, RX VrefLevel [Byte0]: 46
1016 22:50:56.315029 [Byte1]: 46
1017 22:50:56.315124
1018 22:50:56.315178 Set Vref, RX VrefLevel [Byte0]: 47
1019 22:50:56.315248 [Byte1]: 47
1020 22:50:56.315347
1021 22:50:56.315440 Set Vref, RX VrefLevel [Byte0]: 48
1022 22:50:56.315541 [Byte1]: 48
1023 22:50:56.315596
1024 22:50:56.315651 Set Vref, RX VrefLevel [Byte0]: 49
1025 22:50:56.315725 [Byte1]: 49
1026 22:50:56.315796
1027 22:50:56.315868 Set Vref, RX VrefLevel [Byte0]: 50
1028 22:50:56.315923 [Byte1]: 50
1029 22:50:56.315991
1030 22:50:56.316075 Set Vref, RX VrefLevel [Byte0]: 51
1031 22:50:56.316130 [Byte1]: 51
1032 22:50:56.316185
1033 22:50:56.316239 Set Vref, RX VrefLevel [Byte0]: 52
1034 22:50:56.316294 [Byte1]: 52
1035 22:50:56.316349
1036 22:50:56.316403 Set Vref, RX VrefLevel [Byte0]: 53
1037 22:50:56.316458 [Byte1]: 53
1038 22:50:56.316513
1039 22:50:56.316566 Set Vref, RX VrefLevel [Byte0]: 54
1040 22:50:56.316621 [Byte1]: 54
1041 22:50:56.316675
1042 22:50:56.316730 Set Vref, RX VrefLevel [Byte0]: 55
1043 22:50:56.316784 [Byte1]: 55
1044 22:50:56.316839
1045 22:50:56.316893 Set Vref, RX VrefLevel [Byte0]: 56
1046 22:50:56.316948 [Byte1]: 56
1047 22:50:56.317002
1048 22:50:56.317056 Set Vref, RX VrefLevel [Byte0]: 57
1049 22:50:56.317111 [Byte1]: 57
1050 22:50:56.317164
1051 22:50:56.317218 Set Vref, RX VrefLevel [Byte0]: 58
1052 22:50:56.317272 [Byte1]: 58
1053 22:50:56.317349
1054 22:50:56.317402 Set Vref, RX VrefLevel [Byte0]: 59
1055 22:50:56.317456 [Byte1]: 59
1056 22:50:56.317508
1057 22:50:56.317561 Set Vref, RX VrefLevel [Byte0]: 60
1058 22:50:56.317615 [Byte1]: 60
1059 22:50:56.317668
1060 22:50:56.317721 Set Vref, RX VrefLevel [Byte0]: 61
1061 22:50:56.317773 [Byte1]: 61
1062 22:50:56.317827
1063 22:50:56.317879 Set Vref, RX VrefLevel [Byte0]: 62
1064 22:50:56.317932 [Byte1]: 62
1065 22:50:56.317985
1066 22:50:56.318038 Set Vref, RX VrefLevel [Byte0]: 63
1067 22:50:56.318091 [Byte1]: 63
1068 22:50:56.318145
1069 22:50:56.318197 Set Vref, RX VrefLevel [Byte0]: 64
1070 22:50:56.318250 [Byte1]: 64
1071 22:50:56.318303
1072 22:50:56.318356 Set Vref, RX VrefLevel [Byte0]: 65
1073 22:50:56.318409 [Byte1]: 65
1074 22:50:56.318462
1075 22:50:56.318515 Set Vref, RX VrefLevel [Byte0]: 66
1076 22:50:56.318568 [Byte1]: 66
1077 22:50:56.318621
1078 22:50:56.318674 Set Vref, RX VrefLevel [Byte0]: 67
1079 22:50:56.318727 [Byte1]: 67
1080 22:50:56.318780
1081 22:50:56.318833 Set Vref, RX VrefLevel [Byte0]: 68
1082 22:50:56.318886 [Byte1]: 68
1083 22:50:56.318939
1084 22:50:56.318991 Set Vref, RX VrefLevel [Byte0]: 69
1085 22:50:56.319097 [Byte1]: 69
1086 22:50:56.319154
1087 22:50:56.319208 Set Vref, RX VrefLevel [Byte0]: 70
1088 22:50:56.319261 [Byte1]: 70
1089 22:50:56.319314
1090 22:50:56.319366 Set Vref, RX VrefLevel [Byte0]: 71
1091 22:50:56.319420 [Byte1]: 71
1092 22:50:56.319473
1093 22:50:56.319526 Set Vref, RX VrefLevel [Byte0]: 72
1094 22:50:56.319775 [Byte1]: 72
1095 22:50:56.319836
1096 22:50:56.319891 Set Vref, RX VrefLevel [Byte0]: 73
1097 22:50:56.319945 [Byte1]: 73
1098 22:50:56.319998
1099 22:50:56.320052 Set Vref, RX VrefLevel [Byte0]: 74
1100 22:50:56.320106 [Byte1]: 74
1101 22:50:56.320159
1102 22:50:56.320212 Set Vref, RX VrefLevel [Byte0]: 75
1103 22:50:56.320266 [Byte1]: 75
1104 22:50:56.320320
1105 22:50:56.320373 Set Vref, RX VrefLevel [Byte0]: 76
1106 22:50:56.320426 [Byte1]: 76
1107 22:50:56.320479
1108 22:50:56.320531 Set Vref, RX VrefLevel [Byte0]: 77
1109 22:50:56.320585 [Byte1]: 77
1110 22:50:56.320638
1111 22:50:56.320691 Set Vref, RX VrefLevel [Byte0]: 78
1112 22:50:56.320744 [Byte1]: 78
1113 22:50:56.320798
1114 22:50:56.320850 Set Vref, RX VrefLevel [Byte0]: 79
1115 22:50:56.320903 [Byte1]: 79
1116 22:50:56.320956
1117 22:50:56.321009 Final RX Vref Byte 0 = 62 to rank0
1118 22:50:56.321062 Final RX Vref Byte 1 = 60 to rank0
1119 22:50:56.321116 Final RX Vref Byte 0 = 62 to rank1
1120 22:50:56.321169 Final RX Vref Byte 1 = 60 to rank1==
1121 22:50:56.321222 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 22:50:56.321275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 22:50:56.321393 ==
1124 22:50:56.321461 DQS Delay:
1125 22:50:56.321516 DQS0 = 0, DQS1 = 0
1126 22:50:56.321569 DQM Delay:
1127 22:50:56.321620 DQM0 = 93, DQM1 = 82
1128 22:50:56.321673 DQ Delay:
1129 22:50:56.321726 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1130 22:50:56.321780 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1131 22:50:56.321833 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1132 22:50:56.321886 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1133 22:50:56.321940
1134 22:50:56.321993
1135 22:50:56.322046 [DQSOSCAuto] RK0, (LSB)MR18= 0x413c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1136 22:50:56.322101 CH0 RK0: MR19=606, MR18=413C
1137 22:50:56.322154 CH0_RK0: MR19=0x606, MR18=0x413C, DQSOSC=393, MR23=63, INC=95, DEC=63
1138 22:50:56.322208
1139 22:50:56.322261 ----->DramcWriteLeveling(PI) begin...
1140 22:50:56.322315 ==
1141 22:50:56.322369 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 22:50:56.322422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 22:50:56.322476 ==
1144 22:50:56.322529 Write leveling (Byte 0): 33 => 33
1145 22:50:56.322582 Write leveling (Byte 1): 27 => 27
1146 22:50:56.322636 DramcWriteLeveling(PI) end<-----
1147 22:50:56.322689
1148 22:50:56.322742 ==
1149 22:50:56.322794 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 22:50:56.322848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 22:50:56.322902 ==
1152 22:50:56.322983 [Gating] SW mode calibration
1153 22:50:56.323035 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 22:50:56.323089 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 22:50:56.323142 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 22:50:56.323195 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 22:50:56.323249 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:50:56.323302 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:50:56.323356 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:50:56.323409 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:50:56.323462 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:50:56.323515 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:50:56.323568 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:50:56.323621 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:50:56.323674 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:50:56.323728 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:50:56.323781 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:50:56.323834 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:50:56.323887 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:50:56.323940 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:50:56.323993 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:50:56.324047 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1173 22:50:56.324100 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1174 22:50:56.324153 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:50:56.324206 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:50:56.324260 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:50:56.324312 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:50:56.324365 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:50:56.324418 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:50:56.324471 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:50:56.324524 0 9 8 | B1->B0 | 2f2f 3434 | 1 0 | (1 1) (0 0)
1182 22:50:56.324576 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 22:50:56.324629 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 22:50:56.324684 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:50:56.324755 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 22:50:56.324810 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 22:50:56.324863 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 22:50:56.324917 0 10 4 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 0)
1189 22:50:56.324970 0 10 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
1190 22:50:56.325045 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 22:50:56.325099 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:50:56.325154 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:50:56.325208 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:50:56.325263 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:50:56.325339 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:50:56.325393 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1197 22:50:56.325446 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1198 22:50:56.325499 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 22:50:56.325577 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 22:50:56.325682 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:50:56.325936 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:50:56.326067 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 22:50:56.326140 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 22:50:56.326194 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1205 22:50:56.326249 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:50:56.326304 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:50:56.326373 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:50:56.326426 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:50:56.326478 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:50:56.326531 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:50:56.326584 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:50:56.326637 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:50:56.326690 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:50:56.326743 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:50:56.326796 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:50:56.326850 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:50:56.326902 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:50:56.326955 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:50:56.327008 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1220 22:50:56.327062 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1221 22:50:56.327115 Total UI for P1: 0, mck2ui 16
1222 22:50:56.327170 best dqsien dly found for B0: ( 0, 14, 0)
1223 22:50:56.327223 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 22:50:56.327277 Total UI for P1: 0, mck2ui 16
1225 22:50:56.327330 best dqsien dly found for B1: ( 0, 14, 4)
1226 22:50:56.327383 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1227 22:50:56.327436 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1228 22:50:56.327489
1229 22:50:56.327542 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1230 22:50:56.327595 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1231 22:50:56.327648 [Gating] SW calibration Done
1232 22:50:56.327701 ==
1233 22:50:56.327754 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 22:50:56.327807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 22:50:56.327862 ==
1236 22:50:56.327915 RX Vref Scan: 0
1237 22:50:56.327968
1238 22:50:56.328034 RX Vref 0 -> 0, step: 1
1239 22:50:56.328091
1240 22:50:56.328145 RX Delay -130 -> 252, step: 16
1241 22:50:56.328198 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1242 22:50:56.328252 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1243 22:50:56.328306 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1244 22:50:56.328360 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1245 22:50:56.328413 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1246 22:50:56.328466 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1247 22:50:56.328520 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1248 22:50:56.328573 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1249 22:50:56.328626 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1250 22:50:56.328679 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1251 22:50:56.328731 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1252 22:50:56.328783 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1253 22:50:56.328835 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1254 22:50:56.328888 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1255 22:50:56.328941 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1256 22:50:56.328995 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1257 22:50:56.329048 ==
1258 22:50:56.329101 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 22:50:56.329155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 22:50:56.329209 ==
1261 22:50:56.329277 DQS Delay:
1262 22:50:56.329357 DQS0 = 0, DQS1 = 0
1263 22:50:56.329412 DQM Delay:
1264 22:50:56.329465 DQM0 = 90, DQM1 = 80
1265 22:50:56.329519 DQ Delay:
1266 22:50:56.329572 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1267 22:50:56.329625 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1268 22:50:56.329678 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1269 22:50:56.329731 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1270 22:50:56.329785
1271 22:50:56.329837
1272 22:50:56.329905 ==
1273 22:50:56.329960 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 22:50:56.330014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 22:50:56.330068 ==
1276 22:50:56.330122
1277 22:50:56.330175
1278 22:50:56.330228 TX Vref Scan disable
1279 22:50:56.330281 == TX Byte 0 ==
1280 22:50:56.330335 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1281 22:50:56.330389 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1282 22:50:56.330443 == TX Byte 1 ==
1283 22:50:56.330497 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1284 22:50:56.330550 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1285 22:50:56.330604 ==
1286 22:50:56.330657 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 22:50:56.330711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 22:50:56.330765 ==
1289 22:50:56.330819 TX Vref=22, minBit 1, minWin=27, winSum=446
1290 22:50:56.330913 TX Vref=24, minBit 1, minWin=27, winSum=450
1291 22:50:56.330966 TX Vref=26, minBit 8, minWin=27, winSum=455
1292 22:50:56.331020 TX Vref=28, minBit 8, minWin=27, winSum=457
1293 22:50:56.331074 TX Vref=30, minBit 8, minWin=28, winSum=459
1294 22:50:56.331135 TX Vref=32, minBit 4, minWin=28, winSum=460
1295 22:50:56.331198 [TxChooseVref] Worse bit 4, Min win 28, Win sum 460, Final Vref 32
1296 22:50:56.331251
1297 22:50:56.331303 Final TX Range 1 Vref 32
1298 22:50:56.331356
1299 22:50:56.331407 ==
1300 22:50:56.331459 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 22:50:56.331511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 22:50:56.331563 ==
1303 22:50:56.331615
1304 22:50:56.331665
1305 22:50:56.331717 TX Vref Scan disable
1306 22:50:56.331768 == TX Byte 0 ==
1307 22:50:56.331820 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1308 22:50:56.331872 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1309 22:50:56.331923 == TX Byte 1 ==
1310 22:50:56.331974 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1311 22:50:56.332026 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1312 22:50:56.332078
1313 22:50:56.332129 [DATLAT]
1314 22:50:56.332180 Freq=800, CH0 RK1
1315 22:50:56.332231
1316 22:50:56.332282 DATLAT Default: 0xa
1317 22:50:56.332333 0, 0xFFFF, sum = 0
1318 22:50:56.332386 1, 0xFFFF, sum = 0
1319 22:50:56.332439 2, 0xFFFF, sum = 0
1320 22:50:56.332492 3, 0xFFFF, sum = 0
1321 22:50:56.332545 4, 0xFFFF, sum = 0
1322 22:50:56.332597 5, 0xFFFF, sum = 0
1323 22:50:56.332650 6, 0xFFFF, sum = 0
1324 22:50:56.332703 7, 0xFFFF, sum = 0
1325 22:50:56.332755 8, 0xFFFF, sum = 0
1326 22:50:56.332807 9, 0x0, sum = 1
1327 22:50:56.332860 10, 0x0, sum = 2
1328 22:50:56.332912 11, 0x0, sum = 3
1329 22:50:56.333158 12, 0x0, sum = 4
1330 22:50:56.333220 best_step = 10
1331 22:50:56.333273
1332 22:50:56.333363 ==
1333 22:50:56.333417 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 22:50:56.333470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 22:50:56.333524 ==
1336 22:50:56.333577 RX Vref Scan: 0
1337 22:50:56.333630
1338 22:50:56.333697 RX Vref 0 -> 0, step: 1
1339 22:50:56.333749
1340 22:50:56.333800 RX Delay -95 -> 252, step: 8
1341 22:50:56.333851 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1342 22:50:56.333904 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1343 22:50:56.333956 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1344 22:50:56.334008 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1345 22:50:56.334059 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1346 22:50:56.334111 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1347 22:50:56.334162 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1348 22:50:56.334214 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1349 22:50:56.334265 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1350 22:50:56.334317 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1351 22:50:56.334369 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1352 22:50:56.334420 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1353 22:50:56.334471 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1354 22:50:56.334531 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1355 22:50:56.334593 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1356 22:50:56.334645 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1357 22:50:56.334697 ==
1358 22:50:56.334748 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 22:50:56.334801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 22:50:56.334854 ==
1361 22:50:56.334906 DQS Delay:
1362 22:50:56.334957 DQS0 = 0, DQS1 = 0
1363 22:50:56.335009 DQM Delay:
1364 22:50:56.335060 DQM0 = 90, DQM1 = 81
1365 22:50:56.335112 DQ Delay:
1366 22:50:56.335163 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1367 22:50:56.335215 DQ4 =88, DQ5 =80, DQ6 =100, DQ7 =100
1368 22:50:56.335267 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1369 22:50:56.335319 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1370 22:50:56.335370
1371 22:50:56.335421
1372 22:50:56.335473 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a23, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1373 22:50:56.335525 CH0 RK1: MR19=606, MR18=4A23
1374 22:50:56.335576 CH0_RK1: MR19=0x606, MR18=0x4A23, DQSOSC=391, MR23=63, INC=96, DEC=64
1375 22:50:56.335629 [RxdqsGatingPostProcess] freq 800
1376 22:50:56.335680 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 22:50:56.335733 Pre-setting of DQS Precalculation
1378 22:50:56.335785 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 22:50:56.335836 ==
1380 22:50:56.335888 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 22:50:56.335939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 22:50:56.335992 ==
1383 22:50:56.336043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 22:50:56.336096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 22:50:56.336147 [CA 0] Center 36 (6~67) winsize 62
1386 22:50:56.336200 [CA 1] Center 36 (6~67) winsize 62
1387 22:50:56.336251 [CA 2] Center 34 (4~65) winsize 62
1388 22:50:56.336303 [CA 3] Center 34 (3~65) winsize 63
1389 22:50:56.336354 [CA 4] Center 34 (4~65) winsize 62
1390 22:50:56.336406 [CA 5] Center 34 (3~65) winsize 63
1391 22:50:56.336456
1392 22:50:56.336508 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1393 22:50:56.336559
1394 22:50:56.336611 [CATrainingPosCal] consider 1 rank data
1395 22:50:56.336663 u2DelayCellTimex100 = 270/100 ps
1396 22:50:56.336714 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 22:50:56.336766 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 22:50:56.336818 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 22:50:56.336870 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1400 22:50:56.336921 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 22:50:56.336973 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1402 22:50:56.337025
1403 22:50:56.337077 CA PerBit enable=1, Macro0, CA PI delay=34
1404 22:50:56.337128
1405 22:50:56.337180 [CBTSetCACLKResult] CA Dly = 34
1406 22:50:56.337232 CS Dly: 5 (0~36)
1407 22:50:56.337283 ==
1408 22:50:56.337367 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 22:50:56.337419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 22:50:56.337471 ==
1411 22:50:56.337523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 22:50:56.337575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 22:50:56.337628 [CA 0] Center 36 (6~67) winsize 62
1414 22:50:56.337680 [CA 1] Center 37 (6~68) winsize 63
1415 22:50:56.337732 [CA 2] Center 35 (5~66) winsize 62
1416 22:50:56.337784 [CA 3] Center 34 (4~65) winsize 62
1417 22:50:56.337836 [CA 4] Center 34 (4~65) winsize 62
1418 22:50:56.337894 [CA 5] Center 34 (4~65) winsize 62
1419 22:50:56.337958
1420 22:50:56.338011 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1421 22:50:56.338063
1422 22:50:56.338115 [CATrainingPosCal] consider 2 rank data
1423 22:50:56.338167 u2DelayCellTimex100 = 270/100 ps
1424 22:50:56.338219 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 22:50:56.338271 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 22:50:56.338323 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 22:50:56.338375 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 22:50:56.338427 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 22:50:56.338479 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 22:50:56.338530
1431 22:50:56.338581 CA PerBit enable=1, Macro0, CA PI delay=34
1432 22:50:56.338633
1433 22:50:56.338684 [CBTSetCACLKResult] CA Dly = 34
1434 22:50:56.338736 CS Dly: 6 (0~38)
1435 22:50:56.338788
1436 22:50:56.338840 ----->DramcWriteLeveling(PI) begin...
1437 22:50:56.338893 ==
1438 22:50:56.338944 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 22:50:56.338997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 22:50:56.339050 ==
1441 22:50:56.339101 Write leveling (Byte 0): 26 => 26
1442 22:50:56.339153 Write leveling (Byte 1): 27 => 27
1443 22:50:56.339205 DramcWriteLeveling(PI) end<-----
1444 22:50:56.339257
1445 22:50:56.339308 ==
1446 22:50:56.339359 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 22:50:56.339411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 22:50:56.339463 ==
1449 22:50:56.339514 [Gating] SW mode calibration
1450 22:50:56.339566 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 22:50:56.339618 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 22:50:56.339670 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1453 22:50:56.339723 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1454 22:50:56.339972 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 22:50:56.340093 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:50:56.340148 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:50:56.340201 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:50:56.340254 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:50:56.340307 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:50:56.340361 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:50:56.340414 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:50:56.340467 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:50:56.340532 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:50:56.340584 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:50:56.340636 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:50:56.340687 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:50:56.340739 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:50:56.340791 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1469 22:50:56.340842 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1470 22:50:56.340894 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1471 22:50:56.340946 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:50:56.340998 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:50:56.341049 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:50:56.341101 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:50:56.341152 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:50:56.341204 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:50:56.341269 0 9 4 | B1->B0 | 2424 3131 | 0 0 | (1 1) (0 0)
1478 22:50:56.341371 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1479 22:50:56.341423 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 22:50:56.341475 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:50:56.341527 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:50:56.341578 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 22:50:56.341630 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 22:50:56.341682 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1485 22:50:56.341734 0 10 4 | B1->B0 | 2f2f 2626 | 1 1 | (1 0) (1 1)
1486 22:50:56.341785 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1487 22:50:56.341837 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:50:56.341889 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:50:56.341941 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:50:56.341992 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:50:56.342044 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:50:56.342095 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:50:56.342146 0 11 4 | B1->B0 | 3535 3939 | 1 0 | (0 0) (0 0)
1494 22:50:56.342198 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1495 22:50:56.342249 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 22:50:56.342300 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:50:56.342352 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:50:56.342404 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 22:50:56.342455 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 22:50:56.342506 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 22:50:56.342557 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1502 22:50:56.342609 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:50:56.342660 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:50:56.342712 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:50:56.342763 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:50:56.342815 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:50:56.342867 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:50:56.342919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:50:56.342971 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:50:56.343022 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:50:56.343074 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:50:56.343125 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:50:56.343177 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:50:56.343229 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:50:56.343280 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:50:56.343331 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:50:56.343383 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1518 22:50:56.343434 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1519 22:50:56.343486 Total UI for P1: 0, mck2ui 16
1520 22:50:56.343537 best dqsien dly found for B0: ( 0, 14, 4)
1521 22:50:56.343589 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 22:50:56.343642 Total UI for P1: 0, mck2ui 16
1523 22:50:56.343694 best dqsien dly found for B1: ( 0, 14, 8)
1524 22:50:56.343746 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1525 22:50:56.343798 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1526 22:50:56.343849
1527 22:50:56.343901 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 22:50:56.343952 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1529 22:50:56.344004 [Gating] SW calibration Done
1530 22:50:56.344055 ==
1531 22:50:56.344107 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 22:50:56.344159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 22:50:56.344212 ==
1534 22:50:56.344264 RX Vref Scan: 0
1535 22:50:56.344315
1536 22:50:56.344366 RX Vref 0 -> 0, step: 1
1537 22:50:56.344417
1538 22:50:56.344469 RX Delay -130 -> 252, step: 16
1539 22:50:56.344520 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1540 22:50:56.344572 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1541 22:50:56.344643 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1542 22:50:56.344699 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1543 22:50:56.344947 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1544 22:50:56.345005 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1545 22:50:56.345058 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1546 22:50:56.345110 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1547 22:50:56.345162 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1548 22:50:56.345213 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1549 22:50:56.345265 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1550 22:50:56.345365 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1551 22:50:56.345419 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1552 22:50:56.345489 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1553 22:50:56.345556 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1554 22:50:56.345608 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1555 22:50:56.345660 ==
1556 22:50:56.345712 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 22:50:56.345764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 22:50:56.345816 ==
1559 22:50:56.345868 DQS Delay:
1560 22:50:56.345919 DQS0 = 0, DQS1 = 0
1561 22:50:56.345972 DQM Delay:
1562 22:50:56.346024 DQM0 = 87, DQM1 = 82
1563 22:50:56.346075 DQ Delay:
1564 22:50:56.346127 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1565 22:50:56.346179 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85
1566 22:50:56.346231 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1567 22:50:56.346282 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1568 22:50:56.346334
1569 22:50:56.346385
1570 22:50:56.346436 ==
1571 22:50:56.346487 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 22:50:56.346539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 22:50:56.346591 ==
1574 22:50:56.346643
1575 22:50:56.346694
1576 22:50:56.346745 TX Vref Scan disable
1577 22:50:56.346797 == TX Byte 0 ==
1578 22:50:56.346848 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1579 22:50:56.346900 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1580 22:50:56.346952 == TX Byte 1 ==
1581 22:50:56.347004 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1582 22:50:56.347056 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1583 22:50:56.347108 ==
1584 22:50:56.347159 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 22:50:56.347211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 22:50:56.347264 ==
1587 22:50:56.347315 TX Vref=22, minBit 10, minWin=27, winSum=452
1588 22:50:56.347368 TX Vref=24, minBit 10, minWin=27, winSum=453
1589 22:50:56.347419 TX Vref=26, minBit 9, minWin=28, winSum=460
1590 22:50:56.347471 TX Vref=28, minBit 0, minWin=28, winSum=458
1591 22:50:56.347523 TX Vref=30, minBit 9, minWin=28, winSum=462
1592 22:50:56.347575 TX Vref=32, minBit 8, minWin=28, winSum=459
1593 22:50:56.347626 [TxChooseVref] Worse bit 9, Min win 28, Win sum 462, Final Vref 30
1594 22:50:56.347678
1595 22:50:56.347729 Final TX Range 1 Vref 30
1596 22:50:56.347802
1597 22:50:56.347855 ==
1598 22:50:56.347907 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 22:50:56.347959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 22:50:56.348012 ==
1601 22:50:56.348063
1602 22:50:56.348115
1603 22:50:56.348167 TX Vref Scan disable
1604 22:50:56.348218 == TX Byte 0 ==
1605 22:50:56.348271 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1606 22:50:56.348323 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1607 22:50:56.348375 == TX Byte 1 ==
1608 22:50:56.348427 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1609 22:50:56.348479 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1610 22:50:56.348530
1611 22:50:56.348582 [DATLAT]
1612 22:50:56.348633 Freq=800, CH1 RK0
1613 22:50:56.348685
1614 22:50:56.348736 DATLAT Default: 0xa
1615 22:50:56.348788 0, 0xFFFF, sum = 0
1616 22:50:56.348841 1, 0xFFFF, sum = 0
1617 22:50:56.348893 2, 0xFFFF, sum = 0
1618 22:50:56.348946 3, 0xFFFF, sum = 0
1619 22:50:56.348998 4, 0xFFFF, sum = 0
1620 22:50:56.349050 5, 0xFFFF, sum = 0
1621 22:50:56.349102 6, 0xFFFF, sum = 0
1622 22:50:56.349155 7, 0xFFFF, sum = 0
1623 22:50:56.349208 8, 0xFFFF, sum = 0
1624 22:50:56.349260 9, 0x0, sum = 1
1625 22:50:56.349343 10, 0x0, sum = 2
1626 22:50:56.349410 11, 0x0, sum = 3
1627 22:50:56.349463 12, 0x0, sum = 4
1628 22:50:56.349515 best_step = 10
1629 22:50:56.349566
1630 22:50:56.349617 ==
1631 22:50:56.349669 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 22:50:56.349721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 22:50:56.349773 ==
1634 22:50:56.349825 RX Vref Scan: 1
1635 22:50:56.349877
1636 22:50:56.349928 Set Vref Range= 32 -> 127
1637 22:50:56.349980
1638 22:50:56.350031 RX Vref 32 -> 127, step: 1
1639 22:50:56.350082
1640 22:50:56.350134 RX Delay -79 -> 252, step: 8
1641 22:50:56.350185
1642 22:50:56.350237 Set Vref, RX VrefLevel [Byte0]: 32
1643 22:50:56.350288 [Byte1]: 32
1644 22:50:56.350340
1645 22:50:56.350391 Set Vref, RX VrefLevel [Byte0]: 33
1646 22:50:56.350442 [Byte1]: 33
1647 22:50:56.350494
1648 22:50:56.350546 Set Vref, RX VrefLevel [Byte0]: 34
1649 22:50:56.350598 [Byte1]: 34
1650 22:50:56.350649
1651 22:50:56.350701 Set Vref, RX VrefLevel [Byte0]: 35
1652 22:50:56.350752 [Byte1]: 35
1653 22:50:56.350804
1654 22:50:56.350854 Set Vref, RX VrefLevel [Byte0]: 36
1655 22:50:56.350906 [Byte1]: 36
1656 22:50:56.350957
1657 22:50:56.351008 Set Vref, RX VrefLevel [Byte0]: 37
1658 22:50:56.351060 [Byte1]: 37
1659 22:50:56.351111
1660 22:50:56.351162 Set Vref, RX VrefLevel [Byte0]: 38
1661 22:50:56.351213 [Byte1]: 38
1662 22:50:56.351265
1663 22:50:56.351315 Set Vref, RX VrefLevel [Byte0]: 39
1664 22:50:56.351388 [Byte1]: 39
1665 22:50:56.351442
1666 22:50:56.351493 Set Vref, RX VrefLevel [Byte0]: 40
1667 22:50:56.351545 [Byte1]: 40
1668 22:50:56.351597
1669 22:50:56.351648 Set Vref, RX VrefLevel [Byte0]: 41
1670 22:50:56.351700 [Byte1]: 41
1671 22:50:56.351751
1672 22:50:56.351803 Set Vref, RX VrefLevel [Byte0]: 42
1673 22:50:56.351855 [Byte1]: 42
1674 22:50:56.351906
1675 22:50:56.351957 Set Vref, RX VrefLevel [Byte0]: 43
1676 22:50:56.352009 [Byte1]: 43
1677 22:50:56.352061
1678 22:50:56.352111 Set Vref, RX VrefLevel [Byte0]: 44
1679 22:50:56.352163 [Byte1]: 44
1680 22:50:56.352214
1681 22:50:56.352266 Set Vref, RX VrefLevel [Byte0]: 45
1682 22:50:56.352317 [Byte1]: 45
1683 22:50:56.352369
1684 22:50:56.352420 Set Vref, RX VrefLevel [Byte0]: 46
1685 22:50:56.352472 [Byte1]: 46
1686 22:50:56.352523
1687 22:50:56.352574 Set Vref, RX VrefLevel [Byte0]: 47
1688 22:50:56.352625 [Byte1]: 47
1689 22:50:56.352677
1690 22:50:56.352728 Set Vref, RX VrefLevel [Byte0]: 48
1691 22:50:56.352780 [Byte1]: 48
1692 22:50:56.352832
1693 22:50:56.352883 Set Vref, RX VrefLevel [Byte0]: 49
1694 22:50:56.352935 [Byte1]: 49
1695 22:50:56.352986
1696 22:50:56.353037 Set Vref, RX VrefLevel [Byte0]: 50
1697 22:50:56.353089 [Byte1]: 50
1698 22:50:56.353140
1699 22:50:56.353191 Set Vref, RX VrefLevel [Byte0]: 51
1700 22:50:56.353242 [Byte1]: 51
1701 22:50:56.353293
1702 22:50:56.353543 Set Vref, RX VrefLevel [Byte0]: 52
1703 22:50:56.353602 [Byte1]: 52
1704 22:50:56.353655
1705 22:50:56.353707 Set Vref, RX VrefLevel [Byte0]: 53
1706 22:50:56.353776 [Byte1]: 53
1707 22:50:56.353844
1708 22:50:56.353895 Set Vref, RX VrefLevel [Byte0]: 54
1709 22:50:56.353946 [Byte1]: 54
1710 22:50:56.353998
1711 22:50:56.354049 Set Vref, RX VrefLevel [Byte0]: 55
1712 22:50:56.354101 [Byte1]: 55
1713 22:50:56.354152
1714 22:50:56.354204 Set Vref, RX VrefLevel [Byte0]: 56
1715 22:50:56.354255 [Byte1]: 56
1716 22:50:56.354307
1717 22:50:56.354358 Set Vref, RX VrefLevel [Byte0]: 57
1718 22:50:56.354409 [Byte1]: 57
1719 22:50:56.354460
1720 22:50:56.354511 Set Vref, RX VrefLevel [Byte0]: 58
1721 22:50:56.354577 [Byte1]: 58
1722 22:50:56.354633
1723 22:50:56.354685 Set Vref, RX VrefLevel [Byte0]: 59
1724 22:50:56.354737 [Byte1]: 59
1725 22:50:56.354789
1726 22:50:56.354840 Set Vref, RX VrefLevel [Byte0]: 60
1727 22:50:56.354892 [Byte1]: 60
1728 22:50:56.354943
1729 22:50:56.354995 Set Vref, RX VrefLevel [Byte0]: 61
1730 22:50:56.355046 [Byte1]: 61
1731 22:50:56.355098
1732 22:50:56.355149 Set Vref, RX VrefLevel [Byte0]: 62
1733 22:50:56.355201 [Byte1]: 62
1734 22:50:56.355252
1735 22:50:56.355304 Set Vref, RX VrefLevel [Byte0]: 63
1736 22:50:56.355355 [Byte1]: 63
1737 22:50:56.355407
1738 22:50:56.355457 Set Vref, RX VrefLevel [Byte0]: 64
1739 22:50:56.355512 [Byte1]: 64
1740 22:50:56.355564
1741 22:50:56.355615 Set Vref, RX VrefLevel [Byte0]: 65
1742 22:50:56.355667 [Byte1]: 65
1743 22:50:56.355718
1744 22:50:56.355769 Set Vref, RX VrefLevel [Byte0]: 66
1745 22:50:56.355821 [Byte1]: 66
1746 22:50:56.355872
1747 22:50:56.355923 Set Vref, RX VrefLevel [Byte0]: 67
1748 22:50:56.355974 [Byte1]: 67
1749 22:50:56.356026
1750 22:50:56.356077 Set Vref, RX VrefLevel [Byte0]: 68
1751 22:50:56.356129 [Byte1]: 68
1752 22:50:56.356180
1753 22:50:56.356231 Set Vref, RX VrefLevel [Byte0]: 69
1754 22:50:56.356282 [Byte1]: 69
1755 22:50:56.356334
1756 22:50:56.356384 Set Vref, RX VrefLevel [Byte0]: 70
1757 22:50:56.356436 [Byte1]: 70
1758 22:50:56.356487
1759 22:50:56.356538 Set Vref, RX VrefLevel [Byte0]: 71
1760 22:50:56.356589 [Byte1]: 71
1761 22:50:56.356640
1762 22:50:56.356692 Set Vref, RX VrefLevel [Byte0]: 72
1763 22:50:56.356743 [Byte1]: 72
1764 22:50:56.356794
1765 22:50:56.356845 Set Vref, RX VrefLevel [Byte0]: 73
1766 22:50:56.356897 [Byte1]: 73
1767 22:50:56.356949
1768 22:50:56.356999 Set Vref, RX VrefLevel [Byte0]: 74
1769 22:50:56.357050 [Byte1]: 74
1770 22:50:56.357101
1771 22:50:56.357152 Set Vref, RX VrefLevel [Byte0]: 75
1772 22:50:56.357204 [Byte1]: 75
1773 22:50:56.357254
1774 22:50:56.357333 Set Vref, RX VrefLevel [Byte0]: 76
1775 22:50:56.357401 [Byte1]: 76
1776 22:50:56.357453
1777 22:50:56.357504 Set Vref, RX VrefLevel [Byte0]: 77
1778 22:50:56.357555 [Byte1]: 77
1779 22:50:56.357607
1780 22:50:56.357658 Final RX Vref Byte 0 = 51 to rank0
1781 22:50:56.357710 Final RX Vref Byte 1 = 63 to rank0
1782 22:50:56.357762 Final RX Vref Byte 0 = 51 to rank1
1783 22:50:56.357814 Final RX Vref Byte 1 = 63 to rank1==
1784 22:50:56.357866 Dram Type= 6, Freq= 0, CH_1, rank 0
1785 22:50:56.357918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 22:50:56.357971 ==
1787 22:50:56.358022 DQS Delay:
1788 22:50:56.358094 DQS0 = 0, DQS1 = 0
1789 22:50:56.358148 DQM Delay:
1790 22:50:56.358199 DQM0 = 92, DQM1 = 83
1791 22:50:56.358251 DQ Delay:
1792 22:50:56.358303 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1793 22:50:56.358355 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1794 22:50:56.358407 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1795 22:50:56.358459 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1796 22:50:56.358510
1797 22:50:56.358562
1798 22:50:56.358613 [DQSOSCAuto] RK0, (LSB)MR18= 0x304d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1799 22:50:56.358666 CH1 RK0: MR19=606, MR18=304D
1800 22:50:56.358718 CH1_RK0: MR19=0x606, MR18=0x304D, DQSOSC=390, MR23=63, INC=97, DEC=64
1801 22:50:56.358770
1802 22:50:56.358822 ----->DramcWriteLeveling(PI) begin...
1803 22:50:56.358875 ==
1804 22:50:56.358927 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 22:50:56.358979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 22:50:56.359032 ==
1807 22:50:56.359083 Write leveling (Byte 0): 27 => 27
1808 22:50:56.359135 Write leveling (Byte 1): 32 => 32
1809 22:50:56.359187 DramcWriteLeveling(PI) end<-----
1810 22:50:56.359239
1811 22:50:56.359290 ==
1812 22:50:56.359341 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 22:50:56.359394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 22:50:56.359446 ==
1815 22:50:56.359498 [Gating] SW mode calibration
1816 22:50:56.359551 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1817 22:50:56.359603 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1818 22:50:56.359655 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1819 22:50:56.359707 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1820 22:50:56.359759 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:50:56.359811 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:50:56.359863 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:50:56.359915 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:50:56.359966 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:50:56.360018 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:50:56.360070 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:50:56.360121 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:50:56.360173 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:50:56.360224 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:50:56.360276 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:50:56.360328 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:50:56.360379 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:50:56.360431 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:50:56.360483 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:50:56.360535 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1836 22:50:56.360587 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:50:56.360835 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:50:56.360897 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:50:56.360951 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:50:56.361003 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:50:56.361055 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 22:50:56.361107 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 22:50:56.361159 0 9 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1844 22:50:56.361210 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 22:50:56.361262 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 22:50:56.361363 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 22:50:56.361457 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 22:50:56.361515 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 22:50:56.361569 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 22:50:56.361622 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1851 22:50:56.361674 0 10 4 | B1->B0 | 2e2e 2f2f | 1 1 | (1 1) (1 1)
1852 22:50:56.361726 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1853 22:50:56.361778 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:50:56.361831 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:50:56.361882 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:50:56.361934 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:50:56.361985 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 22:50:56.362037 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 22:50:56.362088 0 11 4 | B1->B0 | 3535 2f2f | 0 0 | (0 0) (0 0)
1860 22:50:56.362144 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 22:50:56.362196 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 22:50:56.362248 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 22:50:56.362300 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 22:50:56.362352 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 22:50:56.362404 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 22:50:56.362456 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 22:50:56.362506 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 22:50:56.362558 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:50:56.362618 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:50:56.362712 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:50:56.362777 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:50:56.362830 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:50:56.362883 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:50:56.362935 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:50:56.362986 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:50:56.363038 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:50:56.363090 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:50:56.363141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:50:56.363193 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:50:56.363245 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 22:50:56.363297 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 22:50:56.363350 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 22:50:56.363402 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 22:50:56.363454 Total UI for P1: 0, mck2ui 16
1885 22:50:56.363506 best dqsien dly found for B0: ( 0, 14, 2)
1886 22:50:56.363558 Total UI for P1: 0, mck2ui 16
1887 22:50:56.363609 best dqsien dly found for B1: ( 0, 14, 2)
1888 22:50:56.363661 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1889 22:50:56.363713 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1890 22:50:56.363765
1891 22:50:56.363816 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1892 22:50:56.363868 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1893 22:50:56.363920 [Gating] SW calibration Done
1894 22:50:56.363972 ==
1895 22:50:56.364023 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 22:50:56.364075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 22:50:56.364127 ==
1898 22:50:56.364179 RX Vref Scan: 0
1899 22:50:56.364230
1900 22:50:56.364281 RX Vref 0 -> 0, step: 1
1901 22:50:56.364333
1902 22:50:56.364385 RX Delay -130 -> 252, step: 16
1903 22:50:56.364437 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1904 22:50:56.364489 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1905 22:50:56.364541 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1906 22:50:56.364592 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1907 22:50:56.364644 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1908 22:50:56.364695 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1909 22:50:56.364747 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1910 22:50:56.364798 iDelay=222, Bit 7, Center 85 (-18 ~ 189) 208
1911 22:50:56.364850 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1912 22:50:56.364902 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1913 22:50:56.364953 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1914 22:50:56.365005 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1915 22:50:56.365056 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1916 22:50:56.365108 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1917 22:50:56.365159 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1918 22:50:56.365210 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1919 22:50:56.365261 ==
1920 22:50:56.635953 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 22:50:56.636096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 22:50:56.636161 ==
1923 22:50:56.636220 DQS Delay:
1924 22:50:56.636277 DQS0 = 0, DQS1 = 0
1925 22:50:56.636332 DQM Delay:
1926 22:50:56.636386 DQM0 = 90, DQM1 = 80
1927 22:50:56.636439 DQ Delay:
1928 22:50:56.636492 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1929 22:50:56.636545 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1930 22:50:56.636597 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1931 22:50:56.636649 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1932 22:50:56.636700
1933 22:50:56.636752
1934 22:50:56.636803 ==
1935 22:50:56.636855 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 22:50:56.636906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 22:50:56.636958 ==
1938 22:50:56.637009
1939 22:50:56.637059
1940 22:50:56.637344 TX Vref Scan disable
1941 22:50:56.637471 == TX Byte 0 ==
1942 22:50:56.637551 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1943 22:50:56.637606 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1944 22:50:56.637659 == TX Byte 1 ==
1945 22:50:56.637711 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1946 22:50:56.637764 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1947 22:50:56.637816 ==
1948 22:50:56.637869 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 22:50:56.637921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 22:50:56.637974 ==
1951 22:50:56.638027 TX Vref=22, minBit 8, minWin=27, winSum=450
1952 22:50:56.638080 TX Vref=24, minBit 8, minWin=27, winSum=453
1953 22:50:56.638133 TX Vref=26, minBit 13, minWin=27, winSum=458
1954 22:50:56.638185 TX Vref=28, minBit 8, minWin=27, winSum=458
1955 22:50:56.638238 TX Vref=30, minBit 8, minWin=28, winSum=460
1956 22:50:56.638290 TX Vref=32, minBit 15, minWin=27, winSum=457
1957 22:50:56.638342 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1958 22:50:56.638395
1959 22:50:56.638446 Final TX Range 1 Vref 30
1960 22:50:56.638499
1961 22:50:56.638550 ==
1962 22:50:56.638601 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 22:50:56.638654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 22:50:56.638706 ==
1965 22:50:56.638757
1966 22:50:56.638808
1967 22:50:56.638860 TX Vref Scan disable
1968 22:50:56.638911 == TX Byte 0 ==
1969 22:50:56.638963 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1970 22:50:56.639016 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1971 22:50:56.639068 == TX Byte 1 ==
1972 22:50:56.639119 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1973 22:50:56.639172 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1974 22:50:56.639223
1975 22:50:56.639275 [DATLAT]
1976 22:50:56.639326 Freq=800, CH1 RK1
1977 22:50:56.639378
1978 22:50:56.639428 DATLAT Default: 0xa
1979 22:50:56.639480 0, 0xFFFF, sum = 0
1980 22:50:56.639533 1, 0xFFFF, sum = 0
1981 22:50:56.639586 2, 0xFFFF, sum = 0
1982 22:50:56.639639 3, 0xFFFF, sum = 0
1983 22:50:56.639691 4, 0xFFFF, sum = 0
1984 22:50:56.639744 5, 0xFFFF, sum = 0
1985 22:50:56.639797 6, 0xFFFF, sum = 0
1986 22:50:56.639849 7, 0xFFFF, sum = 0
1987 22:50:56.639901 8, 0xFFFF, sum = 0
1988 22:50:56.639954 9, 0x0, sum = 1
1989 22:50:56.640007 10, 0x0, sum = 2
1990 22:50:56.640059 11, 0x0, sum = 3
1991 22:50:56.640112 12, 0x0, sum = 4
1992 22:50:56.640164 best_step = 10
1993 22:50:56.640216
1994 22:50:56.640267 ==
1995 22:50:56.640318 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 22:50:56.640370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 22:50:56.640422 ==
1998 22:50:56.640474 RX Vref Scan: 0
1999 22:50:56.640525
2000 22:50:56.640576 RX Vref 0 -> 0, step: 1
2001 22:50:56.640627
2002 22:50:56.640679 RX Delay -95 -> 252, step: 8
2003 22:50:56.640730 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2004 22:50:56.640782 iDelay=209, Bit 1, Center 84 (-23 ~ 192) 216
2005 22:50:56.640834 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2006 22:50:56.640887 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2007 22:50:56.640970 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2008 22:50:56.641024 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2009 22:50:56.641075 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2010 22:50:56.641126 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2011 22:50:56.641178 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2012 22:50:56.641229 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2013 22:50:56.641281 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2014 22:50:56.641364 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2015 22:50:56.641416 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2016 22:50:56.641481 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2017 22:50:56.641534 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2018 22:50:56.641586 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2019 22:50:56.641638 ==
2020 22:50:56.641689 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 22:50:56.641742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 22:50:56.641794 ==
2023 22:50:56.641847 DQS Delay:
2024 22:50:56.641898 DQS0 = 0, DQS1 = 0
2025 22:50:56.641950 DQM Delay:
2026 22:50:56.642001 DQM0 = 90, DQM1 = 82
2027 22:50:56.642053 DQ Delay:
2028 22:50:56.642128 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2029 22:50:56.642195 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2030 22:50:56.642247 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =80
2031 22:50:56.642300 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2032 22:50:56.642352
2033 22:50:56.642404
2034 22:50:56.642457 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2035 22:50:56.642511 CH1 RK1: MR19=606, MR18=3C10
2036 22:50:56.642564 CH1_RK1: MR19=0x606, MR18=0x3C10, DQSOSC=394, MR23=63, INC=95, DEC=63
2037 22:50:56.642617 [RxdqsGatingPostProcess] freq 800
2038 22:50:56.642670 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2039 22:50:56.642722 Pre-setting of DQS Precalculation
2040 22:50:56.642775 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2041 22:50:56.642828 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2042 22:50:56.642881 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2043 22:50:56.642934
2044 22:50:56.642986
2045 22:50:56.643038 [Calibration Summary] 1600 Mbps
2046 22:50:56.643091 CH 0, Rank 0
2047 22:50:56.643142 SW Impedance : PASS
2048 22:50:56.643195 DUTY Scan : NO K
2049 22:50:56.643247 ZQ Calibration : PASS
2050 22:50:56.643299 Jitter Meter : NO K
2051 22:50:56.643367 CBT Training : PASS
2052 22:50:56.643420 Write leveling : PASS
2053 22:50:56.643474 RX DQS gating : PASS
2054 22:50:56.643539 RX DQ/DQS(RDDQC) : PASS
2055 22:50:56.643591 TX DQ/DQS : PASS
2056 22:50:56.643644 RX DATLAT : PASS
2057 22:50:56.643696 RX DQ/DQS(Engine): PASS
2058 22:50:56.643748 TX OE : NO K
2059 22:50:56.643801 All Pass.
2060 22:50:56.643853
2061 22:50:56.643905 CH 0, Rank 1
2062 22:50:56.643957 SW Impedance : PASS
2063 22:50:56.644010 DUTY Scan : NO K
2064 22:50:56.644078 ZQ Calibration : PASS
2065 22:50:56.644152 Jitter Meter : NO K
2066 22:50:56.644213 CBT Training : PASS
2067 22:50:56.644266 Write leveling : PASS
2068 22:50:56.644318 RX DQS gating : PASS
2069 22:50:56.644370 RX DQ/DQS(RDDQC) : PASS
2070 22:50:56.644423 TX DQ/DQS : PASS
2071 22:50:56.644475 RX DATLAT : PASS
2072 22:50:56.644527 RX DQ/DQS(Engine): PASS
2073 22:50:56.644580 TX OE : NO K
2074 22:50:56.644633 All Pass.
2075 22:50:56.644685
2076 22:50:56.644736 CH 1, Rank 0
2077 22:50:56.644788 SW Impedance : PASS
2078 22:50:56.644840 DUTY Scan : NO K
2079 22:50:56.644893 ZQ Calibration : PASS
2080 22:50:56.644945 Jitter Meter : NO K
2081 22:50:56.644997 CBT Training : PASS
2082 22:50:56.645049 Write leveling : PASS
2083 22:50:56.645102 RX DQS gating : PASS
2084 22:50:56.645154 RX DQ/DQS(RDDQC) : PASS
2085 22:50:56.645430 TX DQ/DQS : PASS
2086 22:50:56.645550 RX DATLAT : PASS
2087 22:50:56.645651 RX DQ/DQS(Engine): PASS
2088 22:50:56.645706 TX OE : NO K
2089 22:50:56.645759 All Pass.
2090 22:50:56.645813
2091 22:50:56.645866 CH 1, Rank 1
2092 22:50:56.645920 SW Impedance : PASS
2093 22:50:56.645974 DUTY Scan : NO K
2094 22:50:56.646027 ZQ Calibration : PASS
2095 22:50:56.646081 Jitter Meter : NO K
2096 22:50:56.646134 CBT Training : PASS
2097 22:50:56.646187 Write leveling : PASS
2098 22:50:56.646241 RX DQS gating : PASS
2099 22:50:56.646294 RX DQ/DQS(RDDQC) : PASS
2100 22:50:56.646347 TX DQ/DQS : PASS
2101 22:50:56.646400 RX DATLAT : PASS
2102 22:50:56.646453 RX DQ/DQS(Engine): PASS
2103 22:50:56.646506 TX OE : NO K
2104 22:50:56.646560 All Pass.
2105 22:50:56.646612
2106 22:50:56.646665 DramC Write-DBI off
2107 22:50:56.646718 PER_BANK_REFRESH: Hybrid Mode
2108 22:50:56.646771 TX_TRACKING: ON
2109 22:50:56.646824 [GetDramInforAfterCalByMRR] Vendor 6.
2110 22:50:56.646878 [GetDramInforAfterCalByMRR] Revision 606.
2111 22:50:56.646931 [GetDramInforAfterCalByMRR] Revision 2 0.
2112 22:50:56.646985 MR0 0x3b3b
2113 22:50:56.647038 MR8 0x5151
2114 22:50:56.647091 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 22:50:56.647145
2116 22:50:56.647198 MR0 0x3b3b
2117 22:50:56.647251 MR8 0x5151
2118 22:50:56.647304 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 22:50:56.647357
2120 22:50:56.647410 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2121 22:50:56.647465 [FAST_K] Save calibration result to emmc
2122 22:50:56.647550 [FAST_K] Save calibration result to emmc
2123 22:50:56.647604 dram_init: config_dvfs: 1
2124 22:50:56.647657 dramc_set_vcore_voltage set vcore to 662500
2125 22:50:56.647710 Read voltage for 1200, 2
2126 22:50:56.647762 Vio18 = 0
2127 22:50:56.647814 Vcore = 662500
2128 22:50:56.647867 Vdram = 0
2129 22:50:56.647919 Vddq = 0
2130 22:50:56.647971 Vmddr = 0
2131 22:50:56.648024 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2132 22:50:56.648077 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2133 22:50:56.648131 MEM_TYPE=3, freq_sel=15
2134 22:50:56.648183 sv_algorithm_assistance_LP4_1600
2135 22:50:56.648235 ============ PULL DRAM RESETB DOWN ============
2136 22:50:56.648289 ========== PULL DRAM RESETB DOWN end =========
2137 22:50:56.648342 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 22:50:56.648395 ===================================
2139 22:50:56.648447 LPDDR4 DRAM CONFIGURATION
2140 22:50:56.648499 ===================================
2141 22:50:56.648551 EX_ROW_EN[0] = 0x0
2142 22:50:56.648604 EX_ROW_EN[1] = 0x0
2143 22:50:56.648655 LP4Y_EN = 0x0
2144 22:50:56.648707 WORK_FSP = 0x0
2145 22:50:56.648760 WL = 0x4
2146 22:50:56.648812 RL = 0x4
2147 22:50:56.648865 BL = 0x2
2148 22:50:56.648917 RPST = 0x0
2149 22:50:56.648969 RD_PRE = 0x0
2150 22:50:56.649021 WR_PRE = 0x1
2151 22:50:56.649073 WR_PST = 0x0
2152 22:50:56.649125 DBI_WR = 0x0
2153 22:50:56.649177 DBI_RD = 0x0
2154 22:50:56.649229 OTF = 0x1
2155 22:50:56.649281 ===================================
2156 22:50:56.649363 ===================================
2157 22:50:56.649417 ANA top config
2158 22:50:56.649470 ===================================
2159 22:50:56.649525 DLL_ASYNC_EN = 0
2160 22:50:56.649578 ALL_SLAVE_EN = 0
2161 22:50:56.649632 NEW_RANK_MODE = 1
2162 22:50:56.649687 DLL_IDLE_MODE = 1
2163 22:50:56.649741 LP45_APHY_COMB_EN = 1
2164 22:50:56.649794 TX_ODT_DIS = 1
2165 22:50:56.649848 NEW_8X_MODE = 1
2166 22:50:56.649921 ===================================
2167 22:50:56.649991 ===================================
2168 22:50:56.650045 data_rate = 2400
2169 22:50:56.650099 CKR = 1
2170 22:50:56.650153 DQ_P2S_RATIO = 8
2171 22:50:56.650207 ===================================
2172 22:50:56.650261 CA_P2S_RATIO = 8
2173 22:50:56.650314 DQ_CA_OPEN = 0
2174 22:50:56.650367 DQ_SEMI_OPEN = 0
2175 22:50:56.650420 CA_SEMI_OPEN = 0
2176 22:50:56.650473 CA_FULL_RATE = 0
2177 22:50:56.650526 DQ_CKDIV4_EN = 0
2178 22:50:56.650579 CA_CKDIV4_EN = 0
2179 22:50:56.650632 CA_PREDIV_EN = 0
2180 22:50:56.650707 PH8_DLY = 17
2181 22:50:56.650764 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2182 22:50:56.650818 DQ_AAMCK_DIV = 4
2183 22:50:56.650872 CA_AAMCK_DIV = 4
2184 22:50:56.650925 CA_ADMCK_DIV = 4
2185 22:50:56.650978 DQ_TRACK_CA_EN = 0
2186 22:50:56.651031 CA_PICK = 1200
2187 22:50:56.651085 CA_MCKIO = 1200
2188 22:50:56.651138 MCKIO_SEMI = 0
2189 22:50:56.651192 PLL_FREQ = 2366
2190 22:50:56.651245 DQ_UI_PI_RATIO = 32
2191 22:50:56.651298 CA_UI_PI_RATIO = 0
2192 22:50:56.651352 ===================================
2193 22:50:56.651406 ===================================
2194 22:50:56.651459 memory_type:LPDDR4
2195 22:50:56.651512 GP_NUM : 10
2196 22:50:56.651566 SRAM_EN : 1
2197 22:50:56.651619 MD32_EN : 0
2198 22:50:56.651671 ===================================
2199 22:50:56.651725 [ANA_INIT] >>>>>>>>>>>>>>
2200 22:50:56.651778 <<<<<< [CONFIGURE PHASE]: ANA_TX
2201 22:50:56.651832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2202 22:50:56.651885 ===================================
2203 22:50:56.651987 data_rate = 2400,PCW = 0X5b00
2204 22:50:56.652056 ===================================
2205 22:50:56.652109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2206 22:50:56.652163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 22:50:56.652217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 22:50:56.652271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2209 22:50:56.652326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2210 22:50:56.652379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2211 22:50:56.652433 [ANA_INIT] flow start
2212 22:50:56.652486 [ANA_INIT] PLL >>>>>>>>
2213 22:50:56.652540 [ANA_INIT] PLL <<<<<<<<
2214 22:50:56.652593 [ANA_INIT] MIDPI >>>>>>>>
2215 22:50:56.652647 [ANA_INIT] MIDPI <<<<<<<<
2216 22:50:56.652699 [ANA_INIT] DLL >>>>>>>>
2217 22:50:56.652752 [ANA_INIT] DLL <<<<<<<<
2218 22:50:56.652805 [ANA_INIT] flow end
2219 22:50:56.652858 ============ LP4 DIFF to SE enter ============
2220 22:50:56.652912 ============ LP4 DIFF to SE exit ============
2221 22:50:56.652966 [ANA_INIT] <<<<<<<<<<<<<
2222 22:50:56.653224 [Flow] Enable top DCM control >>>>>
2223 22:50:56.653289 [Flow] Enable top DCM control <<<<<
2224 22:50:56.653385 Enable DLL master slave shuffle
2225 22:50:56.653440 ==============================================================
2226 22:50:56.653494 Gating Mode config
2227 22:50:56.653548 ==============================================================
2228 22:50:56.653602 Config description:
2229 22:50:56.653656 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2230 22:50:56.653732 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2231 22:50:56.653801 SELPH_MODE 0: By rank 1: By Phase
2232 22:50:56.653854 ==============================================================
2233 22:50:56.653908 GAT_TRACK_EN = 1
2234 22:50:56.653960 RX_GATING_MODE = 2
2235 22:50:56.654013 RX_GATING_TRACK_MODE = 2
2236 22:50:56.654065 SELPH_MODE = 1
2237 22:50:56.654118 PICG_EARLY_EN = 1
2238 22:50:56.654171 VALID_LAT_VALUE = 1
2239 22:50:56.654223 ==============================================================
2240 22:50:56.654277 Enter into Gating configuration >>>>
2241 22:50:56.654330 Exit from Gating configuration <<<<
2242 22:50:56.654383 Enter into DVFS_PRE_config >>>>>
2243 22:50:56.654435 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2244 22:50:56.654489 Exit from DVFS_PRE_config <<<<<
2245 22:50:56.654542 Enter into PICG configuration >>>>
2246 22:50:56.654595 Exit from PICG configuration <<<<
2247 22:50:56.654648 [RX_INPUT] configuration >>>>>
2248 22:50:56.654700 [RX_INPUT] configuration <<<<<
2249 22:50:56.654752 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2250 22:50:56.654805 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2251 22:50:56.654858 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 22:50:56.654911 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 22:50:56.654964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 22:50:56.655017 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 22:50:56.655070 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2256 22:50:56.655123 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2257 22:50:56.655175 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2258 22:50:56.655228 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2259 22:50:56.655281 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2260 22:50:56.655333 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 22:50:56.655386 ===================================
2262 22:50:56.655439 LPDDR4 DRAM CONFIGURATION
2263 22:50:56.655491 ===================================
2264 22:50:56.655544 EX_ROW_EN[0] = 0x0
2265 22:50:56.655596 EX_ROW_EN[1] = 0x0
2266 22:50:56.655648 LP4Y_EN = 0x0
2267 22:50:56.655701 WORK_FSP = 0x0
2268 22:50:56.655753 WL = 0x4
2269 22:50:56.655804 RL = 0x4
2270 22:50:56.655856 BL = 0x2
2271 22:50:56.655909 RPST = 0x0
2272 22:50:56.655961 RD_PRE = 0x0
2273 22:50:56.656029 WR_PRE = 0x1
2274 22:50:56.656094 WR_PST = 0x0
2275 22:50:56.656146 DBI_WR = 0x0
2276 22:50:56.656198 DBI_RD = 0x0
2277 22:50:56.656249 OTF = 0x1
2278 22:50:56.656301 ===================================
2279 22:50:56.656354 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2280 22:50:56.656406 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2281 22:50:56.656459 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 22:50:56.656512 ===================================
2283 22:50:56.656565 LPDDR4 DRAM CONFIGURATION
2284 22:50:56.656617 ===================================
2285 22:50:56.656669 EX_ROW_EN[0] = 0x10
2286 22:50:56.656721 EX_ROW_EN[1] = 0x0
2287 22:50:56.656773 LP4Y_EN = 0x0
2288 22:50:56.656826 WORK_FSP = 0x0
2289 22:50:56.656878 WL = 0x4
2290 22:50:56.656930 RL = 0x4
2291 22:50:56.656982 BL = 0x2
2292 22:50:56.657034 RPST = 0x0
2293 22:50:56.657086 RD_PRE = 0x0
2294 22:50:56.657137 WR_PRE = 0x1
2295 22:50:56.657203 WR_PST = 0x0
2296 22:50:56.657263 DBI_WR = 0x0
2297 22:50:56.657385 DBI_RD = 0x0
2298 22:50:56.657437 OTF = 0x1
2299 22:50:56.657489 ===================================
2300 22:50:56.657540 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2301 22:50:56.657592 ==
2302 22:50:56.657643 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 22:50:56.657695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2304 22:50:56.657747 ==
2305 22:50:56.657798 [Duty_Offset_Calibration]
2306 22:50:56.657849 B0:2 B1:0 CA:1
2307 22:50:56.657900
2308 22:50:56.657950 [DutyScan_Calibration_Flow] k_type=0
2309 22:50:56.658001
2310 22:50:56.658051 ==CLK 0==
2311 22:50:56.658102 Final CLK duty delay cell = -4
2312 22:50:56.658153 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2313 22:50:56.658205 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2314 22:50:56.658256 [-4] AVG Duty = 4953%(X100)
2315 22:50:56.658307
2316 22:50:56.658357 CH0 CLK Duty spec in!! Max-Min= 156%
2317 22:50:56.658408 [DutyScan_Calibration_Flow] ====Done====
2318 22:50:56.658459
2319 22:50:56.658509 [DutyScan_Calibration_Flow] k_type=1
2320 22:50:56.658560
2321 22:50:56.658610 ==DQS 0 ==
2322 22:50:56.658661 Final DQS duty delay cell = 0
2323 22:50:56.658712 [0] MAX Duty = 5187%(X100), DQS PI = 32
2324 22:50:56.658764 [0] MIN Duty = 4938%(X100), DQS PI = 0
2325 22:50:56.658815 [0] AVG Duty = 5062%(X100)
2326 22:50:56.658865
2327 22:50:56.658916 ==DQS 1 ==
2328 22:50:56.658966 Final DQS duty delay cell = -4
2329 22:50:56.659017 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2330 22:50:56.659067 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2331 22:50:56.659118 [-4] AVG Duty = 5015%(X100)
2332 22:50:56.659169
2333 22:50:56.659219 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2334 22:50:56.659269
2335 22:50:56.659320 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2336 22:50:56.659371 [DutyScan_Calibration_Flow] ====Done====
2337 22:50:56.659422
2338 22:50:56.659473 [DutyScan_Calibration_Flow] k_type=3
2339 22:50:56.659523
2340 22:50:56.659574 ==DQM 0 ==
2341 22:50:56.659625 Final DQM duty delay cell = 0
2342 22:50:56.659675 [0] MAX Duty = 5062%(X100), DQS PI = 24
2343 22:50:56.659939 [0] MIN Duty = 4813%(X100), DQS PI = 0
2344 22:50:56.659998 [0] AVG Duty = 4937%(X100)
2345 22:50:56.660051
2346 22:50:56.660103 ==DQM 1 ==
2347 22:50:56.660155 Final DQM duty delay cell = 0
2348 22:50:56.660207 [0] MAX Duty = 5187%(X100), DQS PI = 48
2349 22:50:56.660259 [0] MIN Duty = 5000%(X100), DQS PI = 12
2350 22:50:56.660310 [0] AVG Duty = 5093%(X100)
2351 22:50:56.660361
2352 22:50:56.660421 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2353 22:50:56.660484
2354 22:50:56.660536 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2355 22:50:56.660588 [DutyScan_Calibration_Flow] ====Done====
2356 22:50:56.660640
2357 22:50:56.660692 [DutyScan_Calibration_Flow] k_type=2
2358 22:50:56.660743
2359 22:50:56.660795 ==DQ 0 ==
2360 22:50:56.660846 Final DQ duty delay cell = -4
2361 22:50:56.660899 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2362 22:50:56.660951 [-4] MIN Duty = 4844%(X100), DQS PI = 14
2363 22:50:56.661002 [-4] AVG Duty = 4937%(X100)
2364 22:50:56.661054
2365 22:50:56.661105 ==DQ 1 ==
2366 22:50:56.661157 Final DQ duty delay cell = 4
2367 22:50:56.661209 [4] MAX Duty = 5093%(X100), DQS PI = 4
2368 22:50:56.661260 [4] MIN Duty = 5031%(X100), DQS PI = 0
2369 22:50:56.661341 [4] AVG Duty = 5062%(X100)
2370 22:50:56.661408
2371 22:50:56.661459 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2372 22:50:56.661511
2373 22:50:56.661562 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2374 22:50:56.661614 [DutyScan_Calibration_Flow] ====Done====
2375 22:50:56.661666 ==
2376 22:50:56.661718 Dram Type= 6, Freq= 0, CH_1, rank 0
2377 22:50:56.661769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 22:50:56.661832 ==
2379 22:50:56.661928 [Duty_Offset_Calibration]
2380 22:50:56.661988 B0:0 B1:-1 CA:2
2381 22:50:56.662042
2382 22:50:56.662095 [DutyScan_Calibration_Flow] k_type=0
2383 22:50:56.662148
2384 22:50:56.662199 ==CLK 0==
2385 22:50:56.662251 Final CLK duty delay cell = 0
2386 22:50:56.662304 [0] MAX Duty = 5156%(X100), DQS PI = 16
2387 22:50:56.662356 [0] MIN Duty = 4938%(X100), DQS PI = 44
2388 22:50:56.662408 [0] AVG Duty = 5047%(X100)
2389 22:50:56.662460
2390 22:50:56.662512 CH1 CLK Duty spec in!! Max-Min= 218%
2391 22:50:56.662564 [DutyScan_Calibration_Flow] ====Done====
2392 22:50:56.662616
2393 22:50:56.662667 [DutyScan_Calibration_Flow] k_type=1
2394 22:50:56.662754
2395 22:50:56.662805 ==DQS 0 ==
2396 22:50:56.662857 Final DQS duty delay cell = 0
2397 22:50:56.662909 [0] MAX Duty = 5093%(X100), DQS PI = 22
2398 22:50:56.662961 [0] MIN Duty = 4969%(X100), DQS PI = 0
2399 22:50:56.663012 [0] AVG Duty = 5031%(X100)
2400 22:50:56.663064
2401 22:50:56.663115 ==DQS 1 ==
2402 22:50:56.663191 Final DQS duty delay cell = 0
2403 22:50:56.663284 [0] MAX Duty = 5156%(X100), DQS PI = 0
2404 22:50:56.663353 [0] MIN Duty = 4813%(X100), DQS PI = 36
2405 22:50:56.663405 [0] AVG Duty = 4984%(X100)
2406 22:50:56.663456
2407 22:50:56.663507 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2408 22:50:56.663559
2409 22:50:56.663609 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2410 22:50:56.663660 [DutyScan_Calibration_Flow] ====Done====
2411 22:50:56.663711
2412 22:50:56.663761 [DutyScan_Calibration_Flow] k_type=3
2413 22:50:56.663812
2414 22:50:56.663863 ==DQM 0 ==
2415 22:50:56.663914 Final DQM duty delay cell = 4
2416 22:50:56.663980 [4] MAX Duty = 5093%(X100), DQS PI = 22
2417 22:50:56.664048 [4] MIN Duty = 4938%(X100), DQS PI = 30
2418 22:50:56.664104 [4] AVG Duty = 5015%(X100)
2419 22:50:56.664169
2420 22:50:56.664220 ==DQM 1 ==
2421 22:50:56.664271 Final DQM duty delay cell = -4
2422 22:50:56.664322 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2423 22:50:56.664374 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2424 22:50:56.664425 [-4] AVG Duty = 4860%(X100)
2425 22:50:56.664476
2426 22:50:56.664526 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2427 22:50:56.664577
2428 22:50:56.664628 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2429 22:50:56.664679 [DutyScan_Calibration_Flow] ====Done====
2430 22:50:56.664729
2431 22:50:56.664779 [DutyScan_Calibration_Flow] k_type=2
2432 22:50:56.664830
2433 22:50:56.664897 ==DQ 0 ==
2434 22:50:56.664961 Final DQ duty delay cell = 0
2435 22:50:56.665012 [0] MAX Duty = 5062%(X100), DQS PI = 20
2436 22:50:56.665062 [0] MIN Duty = 4938%(X100), DQS PI = 30
2437 22:50:56.665113 [0] AVG Duty = 5000%(X100)
2438 22:50:56.665163
2439 22:50:56.665213 ==DQ 1 ==
2440 22:50:56.665263 Final DQ duty delay cell = 0
2441 22:50:56.665348 [0] MAX Duty = 5031%(X100), DQS PI = 2
2442 22:50:56.665428 [0] MIN Duty = 4813%(X100), DQS PI = 34
2443 22:50:56.665479 [0] AVG Duty = 4922%(X100)
2444 22:50:56.665529
2445 22:50:56.665580 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2446 22:50:56.665631
2447 22:50:56.665681 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2448 22:50:56.665732 [DutyScan_Calibration_Flow] ====Done====
2449 22:50:56.665782 nWR fixed to 30
2450 22:50:56.665834 [ModeRegInit_LP4] CH0 RK0
2451 22:50:56.665884 [ModeRegInit_LP4] CH0 RK1
2452 22:50:56.665935 [ModeRegInit_LP4] CH1 RK0
2453 22:50:56.665985 [ModeRegInit_LP4] CH1 RK1
2454 22:50:56.666036 match AC timing 7
2455 22:50:56.666087 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2456 22:50:56.666155 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2457 22:50:56.666219 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2458 22:50:56.666271 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2459 22:50:56.666322 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2460 22:50:56.666373 ==
2461 22:50:56.666423 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 22:50:56.666475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 22:50:56.666542 ==
2464 22:50:56.666607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2465 22:50:56.666659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2466 22:50:56.666710 [CA 0] Center 38 (8~69) winsize 62
2467 22:50:56.666761 [CA 1] Center 38 (8~69) winsize 62
2468 22:50:56.666812 [CA 2] Center 35 (5~66) winsize 62
2469 22:50:56.666863 [CA 3] Center 35 (4~66) winsize 63
2470 22:50:56.666914 [CA 4] Center 34 (4~65) winsize 62
2471 22:50:56.666964 [CA 5] Center 33 (3~64) winsize 62
2472 22:50:56.667015
2473 22:50:56.667065 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2474 22:50:56.667116
2475 22:50:56.667182 [CATrainingPosCal] consider 1 rank data
2476 22:50:56.667261 u2DelayCellTimex100 = 270/100 ps
2477 22:50:56.667316 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2478 22:50:56.667367 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2479 22:50:56.667418 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2480 22:50:56.667498 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2481 22:50:56.667550 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2482 22:50:56.667601 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2483 22:50:56.667651
2484 22:50:56.667702 CA PerBit enable=1, Macro0, CA PI delay=33
2485 22:50:56.667753
2486 22:50:56.667802 [CBTSetCACLKResult] CA Dly = 33
2487 22:50:56.667853 CS Dly: 6 (0~37)
2488 22:50:56.667904 ==
2489 22:50:56.667955 Dram Type= 6, Freq= 0, CH_0, rank 1
2490 22:50:56.668006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 22:50:56.668058 ==
2492 22:50:56.668124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 22:50:56.668384 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2494 22:50:56.668500 [CA 0] Center 39 (8~70) winsize 63
2495 22:50:56.668555 [CA 1] Center 38 (8~69) winsize 62
2496 22:50:56.668607 [CA 2] Center 35 (5~66) winsize 62
2497 22:50:56.668660 [CA 3] Center 35 (5~66) winsize 62
2498 22:50:56.668712 [CA 4] Center 35 (4~66) winsize 63
2499 22:50:56.668763 [CA 5] Center 34 (4~64) winsize 61
2500 22:50:56.668815
2501 22:50:56.668867 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2502 22:50:56.668931
2503 22:50:56.668983 [CATrainingPosCal] consider 2 rank data
2504 22:50:56.669034 u2DelayCellTimex100 = 270/100 ps
2505 22:50:56.669085 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2506 22:50:56.669137 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2507 22:50:56.669188 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2508 22:50:56.669239 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2509 22:50:56.669290 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2510 22:50:56.669397 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2511 22:50:56.669448
2512 22:50:56.669499 CA PerBit enable=1, Macro0, CA PI delay=34
2513 22:50:56.669550
2514 22:50:56.669601 [CBTSetCACLKResult] CA Dly = 34
2515 22:50:56.669652 CS Dly: 7 (0~39)
2516 22:50:56.669703
2517 22:50:56.669753 ----->DramcWriteLeveling(PI) begin...
2518 22:50:56.669806 ==
2519 22:50:56.669857 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 22:50:56.669908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 22:50:56.669960 ==
2522 22:50:56.670010 Write leveling (Byte 0): 35 => 35
2523 22:50:56.670062 Write leveling (Byte 1): 31 => 31
2524 22:50:56.670113 DramcWriteLeveling(PI) end<-----
2525 22:50:56.670164
2526 22:50:56.670214 ==
2527 22:50:56.670265 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 22:50:56.670316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 22:50:56.670368 ==
2530 22:50:56.670419 [Gating] SW mode calibration
2531 22:50:56.670471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2532 22:50:56.670568 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2533 22:50:56.670623 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2534 22:50:56.670676 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2535 22:50:56.670727 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 22:50:56.670778 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 22:50:56.670830 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 22:50:56.670881 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 22:50:56.670933 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2540 22:50:56.670984 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2541 22:50:56.671034 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2542 22:50:56.671086 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 22:50:56.671137 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 22:50:56.671188 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 22:50:56.671239 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 22:50:56.671290 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 22:50:56.671342 1 0 24 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2548 22:50:56.671393 1 0 28 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
2549 22:50:56.671444 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2550 22:50:56.671495 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 22:50:56.671545 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 22:50:56.671596 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 22:50:56.671646 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 22:50:56.671698 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 22:50:56.671748 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 22:50:56.671799 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2557 22:50:56.671849 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2558 22:50:56.671900 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:50:56.671950 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:50:56.672001 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:50:56.672052 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:50:56.672103 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:50:56.672154 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:50:56.672205 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:50:56.672256 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:50:56.672306 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:50:56.672357 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:50:56.672408 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:50:56.672459 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:50:56.672509 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 22:50:56.672560 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 22:50:56.672611 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2573 22:50:56.672662 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 22:50:56.672713 Total UI for P1: 0, mck2ui 16
2575 22:50:56.672764 best dqsien dly found for B0: ( 1, 3, 28)
2576 22:50:56.672815 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 22:50:56.672867 Total UI for P1: 0, mck2ui 16
2578 22:50:56.672918 best dqsien dly found for B1: ( 1, 4, 0)
2579 22:50:56.672969 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2580 22:50:56.673019 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2581 22:50:56.673070
2582 22:50:56.673121 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2583 22:50:56.673172 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2584 22:50:56.673222 [Gating] SW calibration Done
2585 22:50:56.673273 ==
2586 22:50:56.673381 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 22:50:56.673433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 22:50:56.673484 ==
2589 22:50:56.673535 RX Vref Scan: 0
2590 22:50:56.673586
2591 22:50:56.673636 RX Vref 0 -> 0, step: 1
2592 22:50:56.673686
2593 22:50:56.673737 RX Delay -40 -> 252, step: 8
2594 22:50:56.673787 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2595 22:50:56.673838 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2596 22:50:56.673890 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2597 22:50:56.674138 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2598 22:50:56.674252 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2599 22:50:56.674388 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2600 22:50:56.674442 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2601 22:50:56.674495 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2602 22:50:56.674547 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2603 22:50:56.674599 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2604 22:50:56.674652 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2605 22:50:56.674704 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2606 22:50:56.674769 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2607 22:50:56.674820 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2608 22:50:56.674871 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2609 22:50:56.674922 iDelay=208, Bit 15, Center 119 (56 ~ 183) 128
2610 22:50:56.674973 ==
2611 22:50:56.675024 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 22:50:56.675076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 22:50:56.675127 ==
2614 22:50:56.675180 DQS Delay:
2615 22:50:56.675231 DQS0 = 0, DQS1 = 0
2616 22:50:56.675282 DQM Delay:
2617 22:50:56.675332 DQM0 = 122, DQM1 = 111
2618 22:50:56.675383 DQ Delay:
2619 22:50:56.675433 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2620 22:50:56.675484 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2621 22:50:56.675534 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2622 22:50:56.675585 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2623 22:50:56.675636
2624 22:50:56.675686
2625 22:50:56.675737 ==
2626 22:50:56.675787 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 22:50:56.675838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 22:50:56.675889 ==
2629 22:50:56.675939
2630 22:50:56.675990
2631 22:50:56.676040 TX Vref Scan disable
2632 22:50:56.676091 == TX Byte 0 ==
2633 22:50:56.676141 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2634 22:50:56.676193 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2635 22:50:56.676244 == TX Byte 1 ==
2636 22:50:56.676294 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2637 22:50:56.676345 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2638 22:50:56.676396 ==
2639 22:50:56.676447 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 22:50:56.676497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 22:50:56.676549 ==
2642 22:50:56.676600 TX Vref=22, minBit 0, minWin=24, winSum=409
2643 22:50:56.676651 TX Vref=24, minBit 0, minWin=24, winSum=406
2644 22:50:56.676702 TX Vref=26, minBit 7, minWin=24, winSum=415
2645 22:50:56.676754 TX Vref=28, minBit 7, minWin=25, winSum=422
2646 22:50:56.676804 TX Vref=30, minBit 3, minWin=25, winSum=420
2647 22:50:56.676856 TX Vref=32, minBit 0, minWin=25, winSum=416
2648 22:50:56.676906 [TxChooseVref] Worse bit 7, Min win 25, Win sum 422, Final Vref 28
2649 22:50:56.676958
2650 22:50:56.677009 Final TX Range 1 Vref 28
2651 22:50:56.677060
2652 22:50:56.677110 ==
2653 22:50:56.677160 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 22:50:56.677211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 22:50:56.677262 ==
2656 22:50:56.677364
2657 22:50:56.677430
2658 22:50:56.677480 TX Vref Scan disable
2659 22:50:56.677531 == TX Byte 0 ==
2660 22:50:56.677582 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2661 22:50:56.677634 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2662 22:50:56.677730 == TX Byte 1 ==
2663 22:50:56.677784 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2664 22:50:56.677836 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2665 22:50:56.677887
2666 22:50:56.677938 [DATLAT]
2667 22:50:56.677989 Freq=1200, CH0 RK0
2668 22:50:56.678040
2669 22:50:56.678090 DATLAT Default: 0xd
2670 22:50:56.678141 0, 0xFFFF, sum = 0
2671 22:50:56.678194 1, 0xFFFF, sum = 0
2672 22:50:56.678246 2, 0xFFFF, sum = 0
2673 22:50:56.678299 3, 0xFFFF, sum = 0
2674 22:50:56.678351 4, 0xFFFF, sum = 0
2675 22:50:56.678403 5, 0xFFFF, sum = 0
2676 22:50:56.678455 6, 0xFFFF, sum = 0
2677 22:50:56.678507 7, 0xFFFF, sum = 0
2678 22:50:56.678559 8, 0xFFFF, sum = 0
2679 22:50:56.678610 9, 0xFFFF, sum = 0
2680 22:50:56.678662 10, 0xFFFF, sum = 0
2681 22:50:56.678714 11, 0xFFFF, sum = 0
2682 22:50:56.678766 12, 0x0, sum = 1
2683 22:50:56.678818 13, 0x0, sum = 2
2684 22:50:56.678869 14, 0x0, sum = 3
2685 22:50:56.678920 15, 0x0, sum = 4
2686 22:50:56.678972 best_step = 13
2687 22:50:56.679021
2688 22:50:56.679071 ==
2689 22:50:56.679122 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 22:50:56.679173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 22:50:56.679225 ==
2692 22:50:56.679275 RX Vref Scan: 1
2693 22:50:56.679326
2694 22:50:56.679377 Set Vref Range= 32 -> 127
2695 22:50:56.679428
2696 22:50:56.679478 RX Vref 32 -> 127, step: 1
2697 22:50:56.679529
2698 22:50:56.679579 RX Delay -13 -> 252, step: 4
2699 22:50:56.679630
2700 22:50:56.679680 Set Vref, RX VrefLevel [Byte0]: 32
2701 22:50:56.679732 [Byte1]: 32
2702 22:50:56.679783
2703 22:50:56.679833 Set Vref, RX VrefLevel [Byte0]: 33
2704 22:50:56.679884 [Byte1]: 33
2705 22:50:56.679935
2706 22:50:56.679985 Set Vref, RX VrefLevel [Byte0]: 34
2707 22:50:56.680035 [Byte1]: 34
2708 22:50:56.680085
2709 22:50:56.680135 Set Vref, RX VrefLevel [Byte0]: 35
2710 22:50:56.680186 [Byte1]: 35
2711 22:50:56.680236
2712 22:50:56.680286 Set Vref, RX VrefLevel [Byte0]: 36
2713 22:50:56.680337 [Byte1]: 36
2714 22:50:56.680387
2715 22:50:56.680438 Set Vref, RX VrefLevel [Byte0]: 37
2716 22:50:56.680488 [Byte1]: 37
2717 22:50:56.680538
2718 22:50:56.680588 Set Vref, RX VrefLevel [Byte0]: 38
2719 22:50:56.680687 [Byte1]: 38
2720 22:50:56.680741
2721 22:50:56.680791 Set Vref, RX VrefLevel [Byte0]: 39
2722 22:50:56.680842 [Byte1]: 39
2723 22:50:56.680892
2724 22:50:56.680943 Set Vref, RX VrefLevel [Byte0]: 40
2725 22:50:56.680994 [Byte1]: 40
2726 22:50:56.681045
2727 22:50:56.681095 Set Vref, RX VrefLevel [Byte0]: 41
2728 22:50:56.681146 [Byte1]: 41
2729 22:50:56.681197
2730 22:50:56.681247 Set Vref, RX VrefLevel [Byte0]: 42
2731 22:50:56.681306 [Byte1]: 42
2732 22:50:56.681411
2733 22:50:56.681462 Set Vref, RX VrefLevel [Byte0]: 43
2734 22:50:56.681513 [Byte1]: 43
2735 22:50:56.681564
2736 22:50:56.681614 Set Vref, RX VrefLevel [Byte0]: 44
2737 22:50:56.681665 [Byte1]: 44
2738 22:50:56.681715
2739 22:50:56.681765 Set Vref, RX VrefLevel [Byte0]: 45
2740 22:50:56.681816 [Byte1]: 45
2741 22:50:56.681867
2742 22:50:56.681918 Set Vref, RX VrefLevel [Byte0]: 46
2743 22:50:56.681970 [Byte1]: 46
2744 22:50:56.682021
2745 22:50:56.682071 Set Vref, RX VrefLevel [Byte0]: 47
2746 22:50:56.682122 [Byte1]: 47
2747 22:50:56.682173
2748 22:50:56.682223 Set Vref, RX VrefLevel [Byte0]: 48
2749 22:50:56.682273 [Byte1]: 48
2750 22:50:56.682324
2751 22:50:56.682374 Set Vref, RX VrefLevel [Byte0]: 49
2752 22:50:56.682425 [Byte1]: 49
2753 22:50:56.682476
2754 22:50:56.682527 Set Vref, RX VrefLevel [Byte0]: 50
2755 22:50:56.682771 [Byte1]: 50
2756 22:50:56.682882
2757 22:50:56.682935 Set Vref, RX VrefLevel [Byte0]: 51
2758 22:50:56.682988 [Byte1]: 51
2759 22:50:56.683040
2760 22:50:56.683091 Set Vref, RX VrefLevel [Byte0]: 52
2761 22:50:56.683143 [Byte1]: 52
2762 22:50:56.683195
2763 22:50:56.683247 Set Vref, RX VrefLevel [Byte0]: 53
2764 22:50:56.683312 [Byte1]: 53
2765 22:50:56.683363
2766 22:50:56.683413 Set Vref, RX VrefLevel [Byte0]: 54
2767 22:50:56.683464 [Byte1]: 54
2768 22:50:56.683515
2769 22:50:56.683565 Set Vref, RX VrefLevel [Byte0]: 55
2770 22:50:56.683615 [Byte1]: 55
2771 22:50:56.683666
2772 22:50:56.683717 Set Vref, RX VrefLevel [Byte0]: 56
2773 22:50:56.683769 [Byte1]: 56
2774 22:50:56.683819
2775 22:50:56.683886 Set Vref, RX VrefLevel [Byte0]: 57
2776 22:50:56.683971 [Byte1]: 57
2777 22:50:56.684024
2778 22:50:56.684074 Set Vref, RX VrefLevel [Byte0]: 58
2779 22:50:56.684126 [Byte1]: 58
2780 22:50:56.684177
2781 22:50:56.684228 Set Vref, RX VrefLevel [Byte0]: 59
2782 22:50:56.684279 [Byte1]: 59
2783 22:50:56.684330
2784 22:50:56.684381 Set Vref, RX VrefLevel [Byte0]: 60
2785 22:50:56.684433 [Byte1]: 60
2786 22:50:56.684484
2787 22:50:56.684534 Set Vref, RX VrefLevel [Byte0]: 61
2788 22:50:56.684585 [Byte1]: 61
2789 22:50:56.684636
2790 22:50:56.684687 Set Vref, RX VrefLevel [Byte0]: 62
2791 22:50:56.684737 [Byte1]: 62
2792 22:50:56.684789
2793 22:50:56.684839 Set Vref, RX VrefLevel [Byte0]: 63
2794 22:50:56.684890 [Byte1]: 63
2795 22:50:56.684940
2796 22:50:56.684991 Set Vref, RX VrefLevel [Byte0]: 64
2797 22:50:56.685041 [Byte1]: 64
2798 22:50:56.685092
2799 22:50:56.685143 Set Vref, RX VrefLevel [Byte0]: 65
2800 22:50:56.685194 [Byte1]: 65
2801 22:50:56.685244
2802 22:50:56.685294 Set Vref, RX VrefLevel [Byte0]: 66
2803 22:50:56.685405 [Byte1]: 66
2804 22:50:56.685456
2805 22:50:56.685507 Set Vref, RX VrefLevel [Byte0]: 67
2806 22:50:56.685559 [Byte1]: 67
2807 22:50:56.685610
2808 22:50:56.685660 Set Vref, RX VrefLevel [Byte0]: 68
2809 22:50:56.685711 [Byte1]: 68
2810 22:50:56.685761
2811 22:50:56.685811 Set Vref, RX VrefLevel [Byte0]: 69
2812 22:50:56.685863 [Byte1]: 69
2813 22:50:56.685913
2814 22:50:56.685964 Final RX Vref Byte 0 = 57 to rank0
2815 22:50:56.686015 Final RX Vref Byte 1 = 49 to rank0
2816 22:50:56.686067 Final RX Vref Byte 0 = 57 to rank1
2817 22:50:56.686117 Final RX Vref Byte 1 = 49 to rank1==
2818 22:50:56.686169 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 22:50:56.686220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 22:50:56.686272 ==
2821 22:50:56.686322 DQS Delay:
2822 22:50:56.686372 DQS0 = 0, DQS1 = 0
2823 22:50:56.686423 DQM Delay:
2824 22:50:56.686473 DQM0 = 122, DQM1 = 108
2825 22:50:56.686523 DQ Delay:
2826 22:50:56.686574 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2827 22:50:56.686626 DQ4 =124, DQ5 =116, DQ6 =130, DQ7 =128
2828 22:50:56.686677 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2829 22:50:56.686728 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =116
2830 22:50:56.686779
2831 22:50:56.686829
2832 22:50:56.686879 [DQSOSCAuto] RK0, (LSB)MR18= 0xe0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2833 22:50:56.686932 CH0 RK0: MR19=404, MR18=E0A
2834 22:50:56.686983 CH0_RK0: MR19=0x404, MR18=0xE0A, DQSOSC=404, MR23=63, INC=40, DEC=26
2835 22:50:56.687034
2836 22:50:56.687101 ----->DramcWriteLeveling(PI) begin...
2837 22:50:56.687186 ==
2838 22:50:56.687238 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 22:50:56.687290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 22:50:56.687342 ==
2841 22:50:56.687393 Write leveling (Byte 0): 35 => 35
2842 22:50:56.687443 Write leveling (Byte 1): 31 => 31
2843 22:50:56.687494 DramcWriteLeveling(PI) end<-----
2844 22:50:56.687545
2845 22:50:56.687595 ==
2846 22:50:56.687646 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 22:50:56.687696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 22:50:56.687748 ==
2849 22:50:56.687799 [Gating] SW mode calibration
2850 22:50:56.687850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 22:50:56.687901 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 22:50:56.687953 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2853 22:50:56.688004 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 22:50:56.688056 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 22:50:56.688106 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 22:50:56.688157 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 22:50:56.688208 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 22:50:56.688258 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 22:50:56.688309 0 15 28 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (0 1)
2860 22:50:56.688359 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 22:50:56.688410 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 22:50:56.688461 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 22:50:56.688511 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 22:50:56.688563 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 22:50:56.688614 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 22:50:56.688664 1 0 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2867 22:50:56.688715 1 0 28 | B1->B0 | 3534 3e3e | 1 0 | (0 0) (1 1)
2868 22:50:56.688765 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 22:50:56.688815 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 22:50:56.688866 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 22:50:56.688916 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 22:50:56.688966 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 22:50:56.689017 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 22:50:56.689067 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 22:50:56.689118 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2876 22:50:56.689168 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2877 22:50:56.689218 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 22:50:56.689269 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 22:50:56.689378 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 22:50:56.689626 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 22:50:56.689706 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 22:50:56.689759 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 22:50:56.689812 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 22:50:56.689863 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:50:56.689915 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:50:56.689967 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:50:56.690019 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:50:56.690070 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 22:50:56.690135 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 22:50:56.690185 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 22:50:56.690235 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2892 22:50:56.690286 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 22:50:56.690336 Total UI for P1: 0, mck2ui 16
2894 22:50:56.690387 best dqsien dly found for B0: ( 1, 3, 28)
2895 22:50:56.690438 Total UI for P1: 0, mck2ui 16
2896 22:50:56.690489 best dqsien dly found for B1: ( 1, 3, 28)
2897 22:50:56.690539 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2898 22:50:56.690591 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2899 22:50:56.690641
2900 22:50:56.690709 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2901 22:50:56.690790 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2902 22:50:56.690843 [Gating] SW calibration Done
2903 22:50:56.690894 ==
2904 22:50:56.690945 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 22:50:56.690996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 22:50:56.691047 ==
2907 22:50:56.691098 RX Vref Scan: 0
2908 22:50:56.691148
2909 22:50:56.691198 RX Vref 0 -> 0, step: 1
2910 22:50:56.691249
2911 22:50:56.691299 RX Delay -40 -> 252, step: 8
2912 22:50:56.691350 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2913 22:50:56.691402 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2914 22:50:56.691453 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2915 22:50:56.691503 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2916 22:50:56.691554 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2917 22:50:56.691605 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2918 22:50:56.691655 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2919 22:50:56.691706 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2920 22:50:56.691756 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2921 22:50:56.691807 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2922 22:50:56.691858 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2923 22:50:56.691909 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2924 22:50:56.691960 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2925 22:50:56.692011 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2926 22:50:56.692062 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2927 22:50:56.692127 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2928 22:50:56.692179 ==
2929 22:50:56.692230 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 22:50:56.692281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 22:50:56.692332 ==
2932 22:50:56.692383 DQS Delay:
2933 22:50:56.692434 DQS0 = 0, DQS1 = 0
2934 22:50:56.692484 DQM Delay:
2935 22:50:56.692534 DQM0 = 120, DQM1 = 108
2936 22:50:56.692584 DQ Delay:
2937 22:50:56.692635 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2938 22:50:56.822398 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2939 22:50:56.822541 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2940 22:50:56.822607 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2941 22:50:56.822668
2942 22:50:56.822726
2943 22:50:56.822782 ==
2944 22:50:56.822838 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 22:50:56.822894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 22:50:56.822949 ==
2947 22:50:56.823003
2948 22:50:56.823056
2949 22:50:56.823109 TX Vref Scan disable
2950 22:50:56.823162 == TX Byte 0 ==
2951 22:50:56.823215 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2952 22:50:56.823269 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2953 22:50:56.823322 == TX Byte 1 ==
2954 22:50:56.823374 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2955 22:50:56.823426 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2956 22:50:56.823478 ==
2957 22:50:56.823530 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 22:50:56.823583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 22:50:56.823636 ==
2960 22:50:56.823688 TX Vref=22, minBit 0, minWin=25, winSum=415
2961 22:50:56.823741 TX Vref=24, minBit 0, minWin=25, winSum=413
2962 22:50:56.823793 TX Vref=26, minBit 0, minWin=25, winSum=423
2963 22:50:56.823845 TX Vref=28, minBit 1, minWin=25, winSum=420
2964 22:50:56.823897 TX Vref=30, minBit 5, minWin=25, winSum=425
2965 22:50:56.823949 TX Vref=32, minBit 2, minWin=25, winSum=425
2966 22:50:56.824002 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 30
2967 22:50:56.824054
2968 22:50:56.824105 Final TX Range 1 Vref 30
2969 22:50:56.824158
2970 22:50:56.824209 ==
2971 22:50:56.824260 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 22:50:56.824312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 22:50:56.824364 ==
2974 22:50:56.824415
2975 22:50:56.824466
2976 22:50:56.824517 TX Vref Scan disable
2977 22:50:56.824568 == TX Byte 0 ==
2978 22:50:56.824620 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2979 22:50:56.824673 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2980 22:50:56.824725 == TX Byte 1 ==
2981 22:50:56.824776 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2982 22:50:56.824829 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2983 22:50:56.824881
2984 22:50:56.824933 [DATLAT]
2985 22:50:56.824984 Freq=1200, CH0 RK1
2986 22:50:56.825035
2987 22:50:56.825086 DATLAT Default: 0xd
2988 22:50:56.825137 0, 0xFFFF, sum = 0
2989 22:50:56.825190 1, 0xFFFF, sum = 0
2990 22:50:56.825242 2, 0xFFFF, sum = 0
2991 22:50:56.825294 3, 0xFFFF, sum = 0
2992 22:50:56.825353 4, 0xFFFF, sum = 0
2993 22:50:56.825405 5, 0xFFFF, sum = 0
2994 22:50:56.825458 6, 0xFFFF, sum = 0
2995 22:50:56.825510 7, 0xFFFF, sum = 0
2996 22:50:56.825561 8, 0xFFFF, sum = 0
2997 22:50:56.825613 9, 0xFFFF, sum = 0
2998 22:50:56.825665 10, 0xFFFF, sum = 0
2999 22:50:56.825717 11, 0xFFFF, sum = 0
3000 22:50:56.825769 12, 0x0, sum = 1
3001 22:50:56.825821 13, 0x0, sum = 2
3002 22:50:56.825874 14, 0x0, sum = 3
3003 22:50:56.825926 15, 0x0, sum = 4
3004 22:50:56.825978 best_step = 13
3005 22:50:56.826029
3006 22:50:56.826080 ==
3007 22:50:56.826132 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 22:50:56.826184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 22:50:56.826236 ==
3010 22:50:56.826288 RX Vref Scan: 0
3011 22:50:56.826340
3012 22:50:56.826391 RX Vref 0 -> 0, step: 1
3013 22:50:56.826442
3014 22:50:56.826493 RX Delay -21 -> 252, step: 4
3015 22:50:56.826545 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3016 22:50:56.826597 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3017 22:50:56.826863 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3018 22:50:56.826924 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3019 22:50:56.826978 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3020 22:50:56.827048 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3021 22:50:56.827134 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3022 22:50:56.827232 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3023 22:50:56.827284 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3024 22:50:56.827336 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3025 22:50:56.827388 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3026 22:50:56.827440 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3027 22:50:56.827491 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3028 22:50:56.827543 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3029 22:50:56.827594 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3030 22:50:56.827646 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3031 22:50:56.827698 ==
3032 22:50:56.827750 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 22:50:56.827802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 22:50:56.827855 ==
3035 22:50:56.827907 DQS Delay:
3036 22:50:56.827958 DQS0 = 0, DQS1 = 0
3037 22:50:56.828009 DQM Delay:
3038 22:50:56.828060 DQM0 = 119, DQM1 = 107
3039 22:50:56.828112 DQ Delay:
3040 22:50:56.828163 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =114
3041 22:50:56.828214 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3042 22:50:56.828266 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =106
3043 22:50:56.828318 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3044 22:50:56.828369
3045 22:50:56.828421
3046 22:50:56.828473 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3047 22:50:56.828525 CH0 RK1: MR19=403, MR18=11F8
3048 22:50:56.828578 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3049 22:50:56.828630 [RxdqsGatingPostProcess] freq 1200
3050 22:50:56.828682 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3051 22:50:56.828734 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 22:50:56.828786 best DQS1 dly(2T, 0.5T) = (0, 12)
3053 22:50:56.828838 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 22:50:56.828889 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3055 22:50:56.828941 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 22:50:56.828992 best DQS1 dly(2T, 0.5T) = (0, 11)
3057 22:50:56.829069 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 22:50:56.829138 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3059 22:50:56.829189 Pre-setting of DQS Precalculation
3060 22:50:56.829241 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3061 22:50:56.829293 ==
3062 22:50:56.829350 Dram Type= 6, Freq= 0, CH_1, rank 0
3063 22:50:56.829402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 22:50:56.829455 ==
3065 22:50:56.829507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3066 22:50:56.829559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3067 22:50:56.829611 [CA 0] Center 37 (7~68) winsize 62
3068 22:50:56.829663 [CA 1] Center 37 (7~68) winsize 62
3069 22:50:56.829714 [CA 2] Center 35 (5~65) winsize 61
3070 22:50:56.829766 [CA 3] Center 34 (4~65) winsize 62
3071 22:50:56.829819 [CA 4] Center 34 (4~64) winsize 61
3072 22:50:56.829870 [CA 5] Center 33 (3~64) winsize 62
3073 22:50:56.829923
3074 22:50:56.829975 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3075 22:50:56.830028
3076 22:50:56.830079 [CATrainingPosCal] consider 1 rank data
3077 22:50:56.830132 u2DelayCellTimex100 = 270/100 ps
3078 22:50:56.830185 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3079 22:50:56.830238 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3080 22:50:56.830291 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3081 22:50:56.830343 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3082 22:50:56.830412 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3083 22:50:56.830468 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3084 22:50:56.830521
3085 22:50:56.830574 CA PerBit enable=1, Macro0, CA PI delay=33
3086 22:50:56.830628
3087 22:50:56.830681 [CBTSetCACLKResult] CA Dly = 33
3088 22:50:56.830734 CS Dly: 5 (0~36)
3089 22:50:56.830787 ==
3090 22:50:56.830840 Dram Type= 6, Freq= 0, CH_1, rank 1
3091 22:50:56.830898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 22:50:56.830952 ==
3093 22:50:56.831005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 22:50:56.831057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3095 22:50:56.831111 [CA 0] Center 38 (8~68) winsize 61
3096 22:50:56.831163 [CA 1] Center 38 (7~69) winsize 63
3097 22:50:56.831216 [CA 2] Center 35 (5~66) winsize 62
3098 22:50:56.831268 [CA 3] Center 35 (5~65) winsize 61
3099 22:50:56.831321 [CA 4] Center 35 (5~65) winsize 61
3100 22:50:56.831373 [CA 5] Center 34 (4~64) winsize 61
3101 22:50:56.831425
3102 22:50:56.831477 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3103 22:50:56.831530
3104 22:50:56.831584 [CATrainingPosCal] consider 2 rank data
3105 22:50:56.831637 u2DelayCellTimex100 = 270/100 ps
3106 22:50:56.831690 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3107 22:50:56.831744 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3108 22:50:56.831797 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3109 22:50:56.831851 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3110 22:50:56.831903 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3111 22:50:56.831956 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3112 22:50:56.832010
3113 22:50:56.832063 CA PerBit enable=1, Macro0, CA PI delay=34
3114 22:50:56.832117
3115 22:50:56.832170 [CBTSetCACLKResult] CA Dly = 34
3116 22:50:56.832223 CS Dly: 6 (0~39)
3117 22:50:56.832276
3118 22:50:56.832329 ----->DramcWriteLeveling(PI) begin...
3119 22:50:56.832384 ==
3120 22:50:56.832437 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 22:50:56.832491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 22:50:56.832544 ==
3123 22:50:56.832597 Write leveling (Byte 0): 26 => 26
3124 22:50:56.832651 Write leveling (Byte 1): 28 => 28
3125 22:50:56.832704 DramcWriteLeveling(PI) end<-----
3126 22:50:56.832758
3127 22:50:56.832811 ==
3128 22:50:56.832863 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 22:50:56.832917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 22:50:56.832971 ==
3131 22:50:56.833025 [Gating] SW mode calibration
3132 22:50:56.833115 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3133 22:50:56.833169 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3134 22:50:56.833223 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 22:50:56.833278 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 22:50:56.833588 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 22:50:56.833650 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 22:50:56.833706 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 22:50:56.833760 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3140 22:50:56.833814 0 15 24 | B1->B0 | 2b2b 2424 | 1 0 | (0 0) (1 0)
3141 22:50:56.833867 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 22:50:56.833921 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 22:50:56.833975 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 22:50:56.834029 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 22:50:56.834082 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 22:50:56.834136 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 22:50:56.834189 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3148 22:50:56.834243 1 0 24 | B1->B0 | 3d3d 4444 | 1 0 | (1 1) (0 0)
3149 22:50:56.834297 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 22:50:56.834350 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 22:50:56.834404 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 22:50:56.834457 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 22:50:56.834510 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 22:50:56.834564 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 22:50:56.834617 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 22:50:56.834670 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 22:50:56.834724 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 22:50:56.834777 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 22:50:56.834831 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 22:50:56.834884 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 22:50:56.834969 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 22:50:56.835023 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 22:50:56.835077 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 22:50:56.835130 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:50:56.835183 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 22:50:56.835237 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:50:56.835290 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:50:56.835344 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:50:56.835397 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:50:56.835450 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:50:56.835504 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3172 22:50:56.835557 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3173 22:50:56.835610 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 22:50:56.835663 Total UI for P1: 0, mck2ui 16
3175 22:50:56.835717 best dqsien dly found for B0: ( 1, 3, 22)
3176 22:50:56.835771 Total UI for P1: 0, mck2ui 16
3177 22:50:56.835825 best dqsien dly found for B1: ( 1, 3, 24)
3178 22:50:56.835879 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3179 22:50:56.835932 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3180 22:50:56.835986
3181 22:50:56.836038 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3182 22:50:56.836093 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3183 22:50:56.836147 [Gating] SW calibration Done
3184 22:50:56.836201 ==
3185 22:50:56.836253 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 22:50:56.836307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 22:50:56.836362 ==
3188 22:50:56.836415 RX Vref Scan: 0
3189 22:50:56.836468
3190 22:50:56.836521 RX Vref 0 -> 0, step: 1
3191 22:50:56.836574
3192 22:50:56.836628 RX Delay -40 -> 252, step: 8
3193 22:50:56.836681 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3194 22:50:56.836734 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3195 22:50:56.836788 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3196 22:50:56.836842 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3197 22:50:56.836896 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3198 22:50:56.836950 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3199 22:50:56.837003 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3200 22:50:56.837088 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3201 22:50:56.837142 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3202 22:50:56.837195 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3203 22:50:56.837248 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3204 22:50:56.837323 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3205 22:50:56.837404 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3206 22:50:56.837456 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3207 22:50:56.837509 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3208 22:50:56.837562 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3209 22:50:56.837614 ==
3210 22:50:56.837666 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 22:50:56.837719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 22:50:56.837772 ==
3213 22:50:56.837841 DQS Delay:
3214 22:50:56.837912 DQS0 = 0, DQS1 = 0
3215 22:50:56.837979 DQM Delay:
3216 22:50:56.838032 DQM0 = 119, DQM1 = 112
3217 22:50:56.838085 DQ Delay:
3218 22:50:56.838138 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3219 22:50:56.838192 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3220 22:50:56.838246 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3221 22:50:56.838300 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3222 22:50:56.838354
3223 22:50:56.838407
3224 22:50:56.838460 ==
3225 22:50:56.838514 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 22:50:56.838567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 22:50:56.838621 ==
3228 22:50:56.838674
3229 22:50:56.838727
3230 22:50:56.838779 TX Vref Scan disable
3231 22:50:56.838833 == TX Byte 0 ==
3232 22:50:56.838886 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3233 22:50:56.838941 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3234 22:50:56.838994 == TX Byte 1 ==
3235 22:50:56.839048 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3236 22:50:56.839102 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3237 22:50:56.839155 ==
3238 22:50:56.839208 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 22:50:56.839325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 22:50:56.839412 ==
3241 22:50:56.839465 TX Vref=22, minBit 10, minWin=24, winSum=406
3242 22:50:56.839519 TX Vref=24, minBit 11, minWin=24, winSum=409
3243 22:50:56.839767 TX Vref=26, minBit 1, minWin=25, winSum=411
3244 22:50:56.839828 TX Vref=28, minBit 10, minWin=25, winSum=422
3245 22:50:56.839884 TX Vref=30, minBit 11, minWin=25, winSum=424
3246 22:50:56.839939 TX Vref=32, minBit 1, minWin=26, winSum=424
3247 22:50:56.839993 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
3248 22:50:56.840047
3249 22:50:56.840101 Final TX Range 1 Vref 32
3250 22:50:56.840155
3251 22:50:56.840208 ==
3252 22:50:56.840262 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 22:50:56.840315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 22:50:56.840370 ==
3255 22:50:56.840423
3256 22:50:56.840476
3257 22:50:56.840529 TX Vref Scan disable
3258 22:50:56.840583 == TX Byte 0 ==
3259 22:50:56.840636 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3260 22:50:56.840691 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3261 22:50:56.840745 == TX Byte 1 ==
3262 22:50:56.840798 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3263 22:50:56.840852 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3264 22:50:56.840906
3265 22:50:56.840959 [DATLAT]
3266 22:50:56.841012 Freq=1200, CH1 RK0
3267 22:50:56.841096
3268 22:50:56.841149 DATLAT Default: 0xd
3269 22:50:56.841202 0, 0xFFFF, sum = 0
3270 22:50:56.841257 1, 0xFFFF, sum = 0
3271 22:50:56.841341 2, 0xFFFF, sum = 0
3272 22:50:56.841423 3, 0xFFFF, sum = 0
3273 22:50:56.841476 4, 0xFFFF, sum = 0
3274 22:50:56.841530 5, 0xFFFF, sum = 0
3275 22:50:56.841583 6, 0xFFFF, sum = 0
3276 22:50:56.841636 7, 0xFFFF, sum = 0
3277 22:50:56.841690 8, 0xFFFF, sum = 0
3278 22:50:56.841743 9, 0xFFFF, sum = 0
3279 22:50:56.841795 10, 0xFFFF, sum = 0
3280 22:50:56.841848 11, 0xFFFF, sum = 0
3281 22:50:56.841901 12, 0x0, sum = 1
3282 22:50:56.841954 13, 0x0, sum = 2
3283 22:50:56.842007 14, 0x0, sum = 3
3284 22:50:56.842060 15, 0x0, sum = 4
3285 22:50:56.842113 best_step = 13
3286 22:50:56.842165
3287 22:50:56.842217 ==
3288 22:50:56.842270 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 22:50:56.842322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 22:50:56.842376 ==
3291 22:50:56.842445 RX Vref Scan: 1
3292 22:50:56.842509
3293 22:50:56.842561 Set Vref Range= 32 -> 127
3294 22:50:56.842613
3295 22:50:56.842664 RX Vref 32 -> 127, step: 1
3296 22:50:56.842715
3297 22:50:56.842780 RX Delay -13 -> 252, step: 4
3298 22:50:56.842833
3299 22:50:56.842885 Set Vref, RX VrefLevel [Byte0]: 32
3300 22:50:56.842950 [Byte1]: 32
3301 22:50:56.843017
3302 22:50:56.843078 Set Vref, RX VrefLevel [Byte0]: 33
3303 22:50:56.843144 [Byte1]: 33
3304 22:50:56.843195
3305 22:50:56.843246 Set Vref, RX VrefLevel [Byte0]: 34
3306 22:50:56.843297 [Byte1]: 34
3307 22:50:56.843349
3308 22:50:56.843400 Set Vref, RX VrefLevel [Byte0]: 35
3309 22:50:56.843451 [Byte1]: 35
3310 22:50:56.843502
3311 22:50:56.843552 Set Vref, RX VrefLevel [Byte0]: 36
3312 22:50:56.843604 [Byte1]: 36
3313 22:50:56.843655
3314 22:50:56.843706 Set Vref, RX VrefLevel [Byte0]: 37
3315 22:50:56.843757 [Byte1]: 37
3316 22:50:56.843807
3317 22:50:56.843858 Set Vref, RX VrefLevel [Byte0]: 38
3318 22:50:56.843909 [Byte1]: 38
3319 22:50:56.843959
3320 22:50:56.844010 Set Vref, RX VrefLevel [Byte0]: 39
3321 22:50:56.844061 [Byte1]: 39
3322 22:50:56.844113
3323 22:50:56.844163 Set Vref, RX VrefLevel [Byte0]: 40
3324 22:50:56.844214 [Byte1]: 40
3325 22:50:56.844265
3326 22:50:56.844315 Set Vref, RX VrefLevel [Byte0]: 41
3327 22:50:56.844366 [Byte1]: 41
3328 22:50:56.844417
3329 22:50:56.844467 Set Vref, RX VrefLevel [Byte0]: 42
3330 22:50:56.844518 [Byte1]: 42
3331 22:50:56.844569
3332 22:50:56.844620 Set Vref, RX VrefLevel [Byte0]: 43
3333 22:50:56.844671 [Byte1]: 43
3334 22:50:56.844722
3335 22:50:56.844772 Set Vref, RX VrefLevel [Byte0]: 44
3336 22:50:56.844823 [Byte1]: 44
3337 22:50:56.844875
3338 22:50:56.844925 Set Vref, RX VrefLevel [Byte0]: 45
3339 22:50:56.844992 [Byte1]: 45
3340 22:50:56.845071
3341 22:50:56.845136 Set Vref, RX VrefLevel [Byte0]: 46
3342 22:50:56.845187 [Byte1]: 46
3343 22:50:56.845239
3344 22:50:56.845290 Set Vref, RX VrefLevel [Byte0]: 47
3345 22:50:56.845378 [Byte1]: 47
3346 22:50:56.845430
3347 22:50:56.845481 Set Vref, RX VrefLevel [Byte0]: 48
3348 22:50:56.845533 [Byte1]: 48
3349 22:50:56.845584
3350 22:50:56.845636 Set Vref, RX VrefLevel [Byte0]: 49
3351 22:50:56.845687 [Byte1]: 49
3352 22:50:56.845738
3353 22:50:56.845790 Set Vref, RX VrefLevel [Byte0]: 50
3354 22:50:56.845842 [Byte1]: 50
3355 22:50:56.845893
3356 22:50:56.845945 Set Vref, RX VrefLevel [Byte0]: 51
3357 22:50:56.845997 [Byte1]: 51
3358 22:50:56.846048
3359 22:50:56.846099 Set Vref, RX VrefLevel [Byte0]: 52
3360 22:50:56.846152 [Byte1]: 52
3361 22:50:56.846203
3362 22:50:56.846267 Set Vref, RX VrefLevel [Byte0]: 53
3363 22:50:56.846318 [Byte1]: 53
3364 22:50:56.846369
3365 22:50:56.846419 Set Vref, RX VrefLevel [Byte0]: 54
3366 22:50:56.846470 [Byte1]: 54
3367 22:50:56.846520
3368 22:50:56.846571 Set Vref, RX VrefLevel [Byte0]: 55
3369 22:50:56.846622 [Byte1]: 55
3370 22:50:56.846673
3371 22:50:56.846724 Set Vref, RX VrefLevel [Byte0]: 56
3372 22:50:56.846774 [Byte1]: 56
3373 22:50:56.846826
3374 22:50:56.846876 Set Vref, RX VrefLevel [Byte0]: 57
3375 22:50:56.846943 [Byte1]: 57
3376 22:50:56.847026
3377 22:50:56.847078 Set Vref, RX VrefLevel [Byte0]: 58
3378 22:50:56.847157 [Byte1]: 58
3379 22:50:56.847257
3380 22:50:56.847329 Set Vref, RX VrefLevel [Byte0]: 59
3381 22:50:56.847396 [Byte1]: 59
3382 22:50:56.847448
3383 22:50:56.847515 Set Vref, RX VrefLevel [Byte0]: 60
3384 22:50:56.847580 [Byte1]: 60
3385 22:50:56.847632
3386 22:50:56.847700 Set Vref, RX VrefLevel [Byte0]: 61
3387 22:50:56.847764 [Byte1]: 61
3388 22:50:56.847816
3389 22:50:56.847882 Set Vref, RX VrefLevel [Byte0]: 62
3390 22:50:56.847946 [Byte1]: 62
3391 22:50:56.847997
3392 22:50:56.848064 Set Vref, RX VrefLevel [Byte0]: 63
3393 22:50:56.848128 [Byte1]: 63
3394 22:50:56.848179
3395 22:50:56.848245 Set Vref, RX VrefLevel [Byte0]: 64
3396 22:50:56.848309 [Byte1]: 64
3397 22:50:56.848359
3398 22:50:56.848410 Set Vref, RX VrefLevel [Byte0]: 65
3399 22:50:56.848490 [Byte1]: 65
3400 22:50:56.848541
3401 22:50:56.848592 Set Vref, RX VrefLevel [Byte0]: 66
3402 22:50:56.848659 [Byte1]: 66
3403 22:50:56.848711
3404 22:50:56.848763 Set Vref, RX VrefLevel [Byte0]: 67
3405 22:50:56.848814 [Byte1]: 67
3406 22:50:56.848866
3407 22:50:56.848918 Final RX Vref Byte 0 = 51 to rank0
3408 22:50:56.848971 Final RX Vref Byte 1 = 49 to rank0
3409 22:50:56.849023 Final RX Vref Byte 0 = 51 to rank1
3410 22:50:56.849075 Final RX Vref Byte 1 = 49 to rank1==
3411 22:50:56.849343 Dram Type= 6, Freq= 0, CH_1, rank 0
3412 22:50:56.849403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3413 22:50:56.849457 ==
3414 22:50:56.849509 DQS Delay:
3415 22:50:56.849561 DQS0 = 0, DQS1 = 0
3416 22:50:56.849613 DQM Delay:
3417 22:50:56.849664 DQM0 = 119, DQM1 = 111
3418 22:50:56.849716 DQ Delay:
3419 22:50:56.849767 DQ0 =122, DQ1 =114, DQ2 =112, DQ3 =118
3420 22:50:56.849819 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3421 22:50:56.849871 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =104
3422 22:50:56.849923 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3423 22:50:56.849975
3424 22:50:56.850026
3425 22:50:56.850077 [DQSOSCAuto] RK0, (LSB)MR18= 0x71b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 407 ps
3426 22:50:56.850130 CH1 RK0: MR19=404, MR18=71B
3427 22:50:56.850182 CH1_RK0: MR19=0x404, MR18=0x71B, DQSOSC=399, MR23=63, INC=41, DEC=27
3428 22:50:56.850234
3429 22:50:56.850286 ----->DramcWriteLeveling(PI) begin...
3430 22:50:56.850339 ==
3431 22:50:56.850391 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 22:50:56.850443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 22:50:56.850495 ==
3434 22:50:56.850547 Write leveling (Byte 0): 24 => 24
3435 22:50:56.850599 Write leveling (Byte 1): 28 => 28
3436 22:50:56.850651 DramcWriteLeveling(PI) end<-----
3437 22:50:56.850702
3438 22:50:56.850754 ==
3439 22:50:56.850806 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 22:50:56.850857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 22:50:56.850909 ==
3442 22:50:56.850961 [Gating] SW mode calibration
3443 22:50:56.851012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3444 22:50:56.851065 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3445 22:50:56.851117 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 22:50:56.851169 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 22:50:56.851221 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 22:50:56.851273 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 22:50:56.851324 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 22:50:56.851376 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3451 22:50:56.851427 0 15 24 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (0 1)
3452 22:50:56.851479 0 15 28 | B1->B0 | 2323 2a2a | 0 1 | (1 0) (1 0)
3453 22:50:56.851531 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 22:50:56.851582 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 22:50:56.851634 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 22:50:56.851686 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 22:50:56.851754 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 22:50:56.851823 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 22:50:56.851875 1 0 24 | B1->B0 | 3737 2727 | 0 0 | (1 1) (0 0)
3460 22:50:56.851927 1 0 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
3461 22:50:56.851979 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 22:50:56.852031 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 22:50:56.852083 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 22:50:56.852135 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 22:50:56.852186 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 22:50:56.852238 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 22:50:56.852290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3468 22:50:56.852341 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3469 22:50:56.852393 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 22:50:56.852444 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 22:50:56.852496 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 22:50:56.852547 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 22:50:56.852599 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 22:50:56.852650 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 22:50:56.852702 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 22:50:56.852754 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 22:50:56.852805 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 22:50:56.852857 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 22:50:56.852908 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 22:50:56.852959 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 22:50:56.853011 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 22:50:56.853062 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 22:50:56.853113 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3484 22:50:56.853165 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3485 22:50:56.853216 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 22:50:56.853267 Total UI for P1: 0, mck2ui 16
3487 22:50:56.853356 best dqsien dly found for B0: ( 1, 3, 26)
3488 22:50:56.853420 Total UI for P1: 0, mck2ui 16
3489 22:50:56.853471 best dqsien dly found for B1: ( 1, 3, 26)
3490 22:50:56.853522 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3491 22:50:56.853573 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3492 22:50:56.853625
3493 22:50:56.853675 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3494 22:50:56.853727 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3495 22:50:56.853794 [Gating] SW calibration Done
3496 22:50:56.853888 ==
3497 22:50:56.853984 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 22:50:56.854048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 22:50:56.854100 ==
3500 22:50:56.854151 RX Vref Scan: 0
3501 22:50:56.854201
3502 22:50:56.854252 RX Vref 0 -> 0, step: 1
3503 22:50:56.854333
3504 22:50:56.854383 RX Delay -40 -> 252, step: 8
3505 22:50:56.854434 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3506 22:50:56.854485 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3507 22:50:56.854536 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3508 22:50:56.854587 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3509 22:50:56.854638 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3510 22:50:56.854689 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3511 22:50:56.854739 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3512 22:50:56.854790 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3513 22:50:56.854840 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3514 22:50:56.854891 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3515 22:50:56.855138 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3516 22:50:56.855199 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3517 22:50:56.855251 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3518 22:50:56.855303 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3519 22:50:56.855353 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3520 22:50:56.855404 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3521 22:50:56.855456 ==
3522 22:50:56.855507 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 22:50:56.855558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 22:50:56.855610 ==
3525 22:50:56.855661 DQS Delay:
3526 22:50:56.855711 DQS0 = 0, DQS1 = 0
3527 22:50:56.855762 DQM Delay:
3528 22:50:56.855812 DQM0 = 119, DQM1 = 112
3529 22:50:56.855863 DQ Delay:
3530 22:50:56.855914 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3531 22:50:56.855965 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3532 22:50:56.856017 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =103
3533 22:50:56.856069 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3534 22:50:56.856119
3535 22:50:56.856186
3536 22:50:56.856266 ==
3537 22:50:56.856356 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 22:50:56.856421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 22:50:56.856472 ==
3540 22:50:56.856522
3541 22:50:56.856573
3542 22:50:56.856623 TX Vref Scan disable
3543 22:50:56.856673 == TX Byte 0 ==
3544 22:50:56.856723 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3545 22:50:56.856775 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3546 22:50:56.856826 == TX Byte 1 ==
3547 22:50:56.856877 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3548 22:50:56.856927 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3549 22:50:56.856978 ==
3550 22:50:56.857029 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 22:50:56.857080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 22:50:56.857131 ==
3553 22:50:56.857182 TX Vref=22, minBit 1, minWin=25, winSum=414
3554 22:50:56.857234 TX Vref=24, minBit 8, minWin=25, winSum=421
3555 22:50:56.857285 TX Vref=26, minBit 3, minWin=25, winSum=424
3556 22:50:56.857397 TX Vref=28, minBit 0, minWin=26, winSum=430
3557 22:50:56.857449 TX Vref=30, minBit 1, minWin=26, winSum=428
3558 22:50:56.857500 TX Vref=32, minBit 1, minWin=26, winSum=426
3559 22:50:56.857550 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
3560 22:50:56.857601
3561 22:50:56.857652 Final TX Range 1 Vref 28
3562 22:50:56.857704
3563 22:50:56.857754 ==
3564 22:50:56.857805 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 22:50:56.857856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 22:50:56.857907 ==
3567 22:50:56.857958
3568 22:50:56.858008
3569 22:50:56.858073 TX Vref Scan disable
3570 22:50:56.858138 == TX Byte 0 ==
3571 22:50:56.858189 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3572 22:50:56.858257 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3573 22:50:56.858322 == TX Byte 1 ==
3574 22:50:56.858373 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3575 22:50:56.858440 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3576 22:50:56.858521
3577 22:50:56.858599 [DATLAT]
3578 22:50:56.858679 Freq=1200, CH1 RK1
3579 22:50:56.858759
3580 22:50:56.858810 DATLAT Default: 0xd
3581 22:50:56.858862 0, 0xFFFF, sum = 0
3582 22:50:56.858915 1, 0xFFFF, sum = 0
3583 22:50:56.858967 2, 0xFFFF, sum = 0
3584 22:50:56.859020 3, 0xFFFF, sum = 0
3585 22:50:56.859073 4, 0xFFFF, sum = 0
3586 22:50:56.859126 5, 0xFFFF, sum = 0
3587 22:50:56.859178 6, 0xFFFF, sum = 0
3588 22:50:56.859230 7, 0xFFFF, sum = 0
3589 22:50:56.859314 8, 0xFFFF, sum = 0
3590 22:50:56.859384 9, 0xFFFF, sum = 0
3591 22:50:56.859450 10, 0xFFFF, sum = 0
3592 22:50:56.859503 11, 0xFFFF, sum = 0
3593 22:50:56.859556 12, 0x0, sum = 1
3594 22:50:56.859608 13, 0x0, sum = 2
3595 22:50:56.859660 14, 0x0, sum = 3
3596 22:50:56.859712 15, 0x0, sum = 4
3597 22:50:56.859764 best_step = 13
3598 22:50:56.859815
3599 22:50:56.859866 ==
3600 22:50:56.859917 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 22:50:56.859968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 22:50:56.860020 ==
3603 22:50:56.860072 RX Vref Scan: 0
3604 22:50:56.860123
3605 22:50:56.860175 RX Vref 0 -> 0, step: 1
3606 22:50:56.860226
3607 22:50:56.860277 RX Delay -13 -> 252, step: 4
3608 22:50:56.860329 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3609 22:50:56.860381 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3610 22:50:56.860433 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3611 22:50:56.860485 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3612 22:50:56.860536 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3613 22:50:56.860588 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3614 22:50:56.860640 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3615 22:50:56.860692 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3616 22:50:56.860745 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3617 22:50:56.860797 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3618 22:50:56.860848 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3619 22:50:56.860899 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3620 22:50:56.860951 iDelay=195, Bit 12, Center 120 (55 ~ 186) 132
3621 22:50:56.861003 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3622 22:50:56.861055 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3623 22:50:56.861106 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3624 22:50:56.861158 ==
3625 22:50:56.861210 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 22:50:56.861263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 22:50:56.861352 ==
3628 22:50:56.861418 DQS Delay:
3629 22:50:56.861468 DQS0 = 0, DQS1 = 0
3630 22:50:56.861519 DQM Delay:
3631 22:50:56.861569 DQM0 = 119, DQM1 = 112
3632 22:50:56.861620 DQ Delay:
3633 22:50:56.861670 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3634 22:50:56.861721 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3635 22:50:56.861772 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3636 22:50:56.861823 DQ12 =120, DQ13 =118, DQ14 =122, DQ15 =122
3637 22:50:56.861874
3638 22:50:56.861924
3639 22:50:56.861975 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3640 22:50:56.862027 CH1 RK1: MR19=403, MR18=CF1
3641 22:50:56.862078 CH1_RK1: MR19=0x403, MR18=0xCF1, DQSOSC=405, MR23=63, INC=39, DEC=26
3642 22:50:56.862130 [RxdqsGatingPostProcess] freq 1200
3643 22:50:56.862215 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3644 22:50:56.862294 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 22:50:56.862348 best DQS1 dly(2T, 0.5T) = (0, 11)
3646 22:50:56.862401 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 22:50:56.862452 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3648 22:50:56.862504 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 22:50:56.862571 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 22:50:56.862623 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 22:50:56.862675 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 22:50:56.862739 Pre-setting of DQS Precalculation
3653 22:50:56.862999 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3654 22:50:56.863061 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3655 22:50:56.863117 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3656 22:50:56.863183
3657 22:50:56.863234
3658 22:50:56.863285 [Calibration Summary] 2400 Mbps
3659 22:50:56.863336 CH 0, Rank 0
3660 22:50:56.863387 SW Impedance : PASS
3661 22:50:56.863438 DUTY Scan : NO K
3662 22:50:56.863490 ZQ Calibration : PASS
3663 22:50:56.863554 Jitter Meter : NO K
3664 22:50:56.863642 CBT Training : PASS
3665 22:50:56.863737 Write leveling : PASS
3666 22:50:56.863791 RX DQS gating : PASS
3667 22:50:56.863843 RX DQ/DQS(RDDQC) : PASS
3668 22:50:56.863894 TX DQ/DQS : PASS
3669 22:50:56.863945 RX DATLAT : PASS
3670 22:50:56.863996 RX DQ/DQS(Engine): PASS
3671 22:50:56.864047 TX OE : NO K
3672 22:50:56.864098 All Pass.
3673 22:50:56.864149
3674 22:50:56.864200 CH 0, Rank 1
3675 22:50:56.864250 SW Impedance : PASS
3676 22:50:56.864301 DUTY Scan : NO K
3677 22:50:56.864352 ZQ Calibration : PASS
3678 22:50:56.864403 Jitter Meter : NO K
3679 22:50:56.864454 CBT Training : PASS
3680 22:50:56.864505 Write leveling : PASS
3681 22:50:56.864555 RX DQS gating : PASS
3682 22:50:56.864606 RX DQ/DQS(RDDQC) : PASS
3683 22:50:56.864657 TX DQ/DQS : PASS
3684 22:50:56.864708 RX DATLAT : PASS
3685 22:50:56.864758 RX DQ/DQS(Engine): PASS
3686 22:50:56.864809 TX OE : NO K
3687 22:50:56.864860 All Pass.
3688 22:50:56.864910
3689 22:50:56.864961 CH 1, Rank 0
3690 22:50:56.865012 SW Impedance : PASS
3691 22:50:56.865062 DUTY Scan : NO K
3692 22:50:56.865112 ZQ Calibration : PASS
3693 22:50:56.865163 Jitter Meter : NO K
3694 22:50:56.865214 CBT Training : PASS
3695 22:50:56.865264 Write leveling : PASS
3696 22:50:56.865376 RX DQS gating : PASS
3697 22:50:56.865430 RX DQ/DQS(RDDQC) : PASS
3698 22:50:56.865481 TX DQ/DQS : PASS
3699 22:50:56.865532 RX DATLAT : PASS
3700 22:50:56.865583 RX DQ/DQS(Engine): PASS
3701 22:50:56.865634 TX OE : NO K
3702 22:50:56.865685 All Pass.
3703 22:50:56.865736
3704 22:50:56.865786 CH 1, Rank 1
3705 22:50:56.865837 SW Impedance : PASS
3706 22:50:56.865917 DUTY Scan : NO K
3707 22:50:56.865999 ZQ Calibration : PASS
3708 22:50:56.866049 Jitter Meter : NO K
3709 22:50:56.866100 CBT Training : PASS
3710 22:50:56.866150 Write leveling : PASS
3711 22:50:56.866202 RX DQS gating : PASS
3712 22:50:56.866252 RX DQ/DQS(RDDQC) : PASS
3713 22:50:56.866303 TX DQ/DQS : PASS
3714 22:50:56.866354 RX DATLAT : PASS
3715 22:50:56.866404 RX DQ/DQS(Engine): PASS
3716 22:50:56.866455 TX OE : NO K
3717 22:50:56.866506 All Pass.
3718 22:50:56.866556
3719 22:50:56.866606 DramC Write-DBI off
3720 22:50:56.866657 PER_BANK_REFRESH: Hybrid Mode
3721 22:50:56.866708 TX_TRACKING: ON
3722 22:50:56.866760 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3723 22:50:56.866811 [FAST_K] Save calibration result to emmc
3724 22:50:56.866862 dramc_set_vcore_voltage set vcore to 650000
3725 22:50:56.866912 Read voltage for 600, 5
3726 22:50:56.866963 Vio18 = 0
3727 22:50:56.867013 Vcore = 650000
3728 22:50:56.867064 Vdram = 0
3729 22:50:56.867115 Vddq = 0
3730 22:50:56.867165 Vmddr = 0
3731 22:50:56.867216 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3732 22:50:56.867267 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3733 22:50:56.867319 MEM_TYPE=3, freq_sel=19
3734 22:50:56.867370 sv_algorithm_assistance_LP4_1600
3735 22:50:56.867421 ============ PULL DRAM RESETB DOWN ============
3736 22:50:56.867472 ========== PULL DRAM RESETB DOWN end =========
3737 22:50:56.867524 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3738 22:50:56.867576 ===================================
3739 22:50:56.867627 LPDDR4 DRAM CONFIGURATION
3740 22:50:56.867678 ===================================
3741 22:50:56.867729 EX_ROW_EN[0] = 0x0
3742 22:50:56.867780 EX_ROW_EN[1] = 0x0
3743 22:50:56.867831 LP4Y_EN = 0x0
3744 22:50:56.867882 WORK_FSP = 0x0
3745 22:50:56.867932 WL = 0x2
3746 22:50:56.867982 RL = 0x2
3747 22:50:56.868033 BL = 0x2
3748 22:50:56.868083 RPST = 0x0
3749 22:50:56.868133 RD_PRE = 0x0
3750 22:50:56.868183 WR_PRE = 0x1
3751 22:50:56.868233 WR_PST = 0x0
3752 22:50:56.868283 DBI_WR = 0x0
3753 22:50:56.868333 DBI_RD = 0x0
3754 22:50:56.868384 OTF = 0x1
3755 22:50:56.868435 ===================================
3756 22:50:56.868486 ===================================
3757 22:50:56.868536 ANA top config
3758 22:50:56.868586 ===================================
3759 22:50:56.868637 DLL_ASYNC_EN = 0
3760 22:50:56.868688 ALL_SLAVE_EN = 1
3761 22:50:56.868738 NEW_RANK_MODE = 1
3762 22:50:56.868790 DLL_IDLE_MODE = 1
3763 22:50:56.868840 LP45_APHY_COMB_EN = 1
3764 22:50:56.868891 TX_ODT_DIS = 1
3765 22:50:56.868942 NEW_8X_MODE = 1
3766 22:50:56.868993 ===================================
3767 22:50:56.869044 ===================================
3768 22:50:56.869094 data_rate = 1200
3769 22:50:56.869145 CKR = 1
3770 22:50:56.869195 DQ_P2S_RATIO = 8
3771 22:50:56.869246 ===================================
3772 22:50:56.869304 CA_P2S_RATIO = 8
3773 22:50:56.869411 DQ_CA_OPEN = 0
3774 22:50:56.869462 DQ_SEMI_OPEN = 0
3775 22:50:56.869512 CA_SEMI_OPEN = 0
3776 22:50:56.869580 CA_FULL_RATE = 0
3777 22:50:56.869644 DQ_CKDIV4_EN = 1
3778 22:50:56.869723 CA_CKDIV4_EN = 1
3779 22:50:56.869775 CA_PREDIV_EN = 0
3780 22:50:56.869826 PH8_DLY = 0
3781 22:50:56.869876 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3782 22:50:56.869927 DQ_AAMCK_DIV = 4
3783 22:50:56.869978 CA_AAMCK_DIV = 4
3784 22:50:56.870029 CA_ADMCK_DIV = 4
3785 22:50:56.870079 DQ_TRACK_CA_EN = 0
3786 22:50:56.870130 CA_PICK = 600
3787 22:50:56.870180 CA_MCKIO = 600
3788 22:50:56.870231 MCKIO_SEMI = 0
3789 22:50:56.870281 PLL_FREQ = 2288
3790 22:50:56.870331 DQ_UI_PI_RATIO = 32
3791 22:50:56.870382 CA_UI_PI_RATIO = 0
3792 22:50:56.870432 ===================================
3793 22:50:56.870483 ===================================
3794 22:50:56.870534 memory_type:LPDDR4
3795 22:50:56.870585 GP_NUM : 10
3796 22:50:56.870635 SRAM_EN : 1
3797 22:50:56.870685 MD32_EN : 0
3798 22:50:56.870736 ===================================
3799 22:50:56.870786 [ANA_INIT] >>>>>>>>>>>>>>
3800 22:50:56.870837 <<<<<< [CONFIGURE PHASE]: ANA_TX
3801 22:50:56.871080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3802 22:50:56.871139 ===================================
3803 22:50:56.871191 data_rate = 1200,PCW = 0X5800
3804 22:50:56.871242 ===================================
3805 22:50:56.871293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3806 22:50:56.871344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 22:50:56.871395 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 22:50:56.871446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3809 22:50:56.871498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3810 22:50:56.871549 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3811 22:50:56.871600 [ANA_INIT] flow start
3812 22:50:56.871650 [ANA_INIT] PLL >>>>>>>>
3813 22:50:56.871701 [ANA_INIT] PLL <<<<<<<<
3814 22:50:56.871751 [ANA_INIT] MIDPI >>>>>>>>
3815 22:50:56.871802 [ANA_INIT] MIDPI <<<<<<<<
3816 22:50:56.871852 [ANA_INIT] DLL >>>>>>>>
3817 22:50:56.871902 [ANA_INIT] flow end
3818 22:50:56.871953 ============ LP4 DIFF to SE enter ============
3819 22:50:56.872004 ============ LP4 DIFF to SE exit ============
3820 22:50:56.872056 [ANA_INIT] <<<<<<<<<<<<<
3821 22:50:56.872106 [Flow] Enable top DCM control >>>>>
3822 22:50:56.872157 [Flow] Enable top DCM control <<<<<
3823 22:50:56.872208 Enable DLL master slave shuffle
3824 22:50:56.872258 ==============================================================
3825 22:50:56.872309 Gating Mode config
3826 22:50:56.872360 ==============================================================
3827 22:50:56.872410 Config description:
3828 22:50:56.872489 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3829 22:50:56.872558 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3830 22:50:56.872622 SELPH_MODE 0: By rank 1: By Phase
3831 22:50:56.872673 ==============================================================
3832 22:50:56.872725 GAT_TRACK_EN = 1
3833 22:50:56.872775 RX_GATING_MODE = 2
3834 22:50:56.872825 RX_GATING_TRACK_MODE = 2
3835 22:50:56.872876 SELPH_MODE = 1
3836 22:50:56.872926 PICG_EARLY_EN = 1
3837 22:50:56.872988 VALID_LAT_VALUE = 1
3838 22:50:56.879311 ==============================================================
3839 22:50:56.882620 Enter into Gating configuration >>>>
3840 22:50:56.885955 Exit from Gating configuration <<<<
3841 22:50:56.889301 Enter into DVFS_PRE_config >>>>>
3842 22:50:56.899406 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3843 22:50:56.902985 Exit from DVFS_PRE_config <<<<<
3844 22:50:56.906094 Enter into PICG configuration >>>>
3845 22:50:56.909260 Exit from PICG configuration <<<<
3846 22:50:56.912649 [RX_INPUT] configuration >>>>>
3847 22:50:56.916572 [RX_INPUT] configuration <<<<<
3848 22:50:56.919491 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3849 22:50:56.926168 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3850 22:50:56.932830 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 22:50:56.936199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 22:50:56.942557 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 22:50:56.949390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 22:50:56.952736 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3855 22:50:56.959594 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3856 22:50:56.962499 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3857 22:50:56.965727 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3858 22:50:56.969219 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3859 22:50:56.975831 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3860 22:50:56.979406 ===================================
3861 22:50:56.979490 LPDDR4 DRAM CONFIGURATION
3862 22:50:56.982463 ===================================
3863 22:50:56.986087 EX_ROW_EN[0] = 0x0
3864 22:50:56.989151 EX_ROW_EN[1] = 0x0
3865 22:50:56.989233 LP4Y_EN = 0x0
3866 22:50:56.992466 WORK_FSP = 0x0
3867 22:50:56.992576 WL = 0x2
3868 22:50:56.995773 RL = 0x2
3869 22:50:56.995856 BL = 0x2
3870 22:50:56.999368 RPST = 0x0
3871 22:50:56.999450 RD_PRE = 0x0
3872 22:50:57.002539 WR_PRE = 0x1
3873 22:50:57.002621 WR_PST = 0x0
3874 22:50:57.005773 DBI_WR = 0x0
3875 22:50:57.005855 DBI_RD = 0x0
3876 22:50:57.008969 OTF = 0x1
3877 22:50:57.012320 ===================================
3878 22:50:57.015744 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3879 22:50:57.019026 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3880 22:50:57.025473 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3881 22:50:57.028920 ===================================
3882 22:50:57.029001 LPDDR4 DRAM CONFIGURATION
3883 22:50:57.032643 ===================================
3884 22:50:57.035665 EX_ROW_EN[0] = 0x10
3885 22:50:57.038937 EX_ROW_EN[1] = 0x0
3886 22:50:57.039017 LP4Y_EN = 0x0
3887 22:50:57.042190 WORK_FSP = 0x0
3888 22:50:57.042271 WL = 0x2
3889 22:50:57.045575 RL = 0x2
3890 22:50:57.045655 BL = 0x2
3891 22:50:57.048951 RPST = 0x0
3892 22:50:57.049032 RD_PRE = 0x0
3893 22:50:57.052928 WR_PRE = 0x1
3894 22:50:57.053009 WR_PST = 0x0
3895 22:50:57.055779 DBI_WR = 0x0
3896 22:50:57.055859 DBI_RD = 0x0
3897 22:50:57.059085 OTF = 0x1
3898 22:50:57.062164 ===================================
3899 22:50:57.069208 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3900 22:50:57.072262 nWR fixed to 30
3901 22:50:57.072343 [ModeRegInit_LP4] CH0 RK0
3902 22:50:57.075489 [ModeRegInit_LP4] CH0 RK1
3903 22:50:57.078663 [ModeRegInit_LP4] CH1 RK0
3904 22:50:57.082333 [ModeRegInit_LP4] CH1 RK1
3905 22:50:57.082414 match AC timing 17
3906 22:50:57.085415 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3907 22:50:57.092159 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3908 22:50:57.095350 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3909 22:50:57.099136 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3910 22:50:57.105564 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3911 22:50:57.105647 ==
3912 22:50:57.108643 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 22:50:57.112106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3914 22:50:57.112189 ==
3915 22:50:57.118692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3916 22:50:57.125556 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3917 22:50:57.128531 [CA 0] Center 36 (6~67) winsize 62
3918 22:50:57.132054 [CA 1] Center 36 (6~67) winsize 62
3919 22:50:57.135240 [CA 2] Center 34 (4~65) winsize 62
3920 22:50:57.138504 [CA 3] Center 34 (3~65) winsize 63
3921 22:50:57.141889 [CA 4] Center 34 (3~65) winsize 63
3922 22:50:57.145302 [CA 5] Center 33 (2~64) winsize 63
3923 22:50:57.145386
3924 22:50:57.148389 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3925 22:50:57.148472
3926 22:50:57.152121 [CATrainingPosCal] consider 1 rank data
3927 22:50:57.155175 u2DelayCellTimex100 = 270/100 ps
3928 22:50:57.158548 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3929 22:50:57.161979 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3930 22:50:57.165011 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 22:50:57.168887 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3932 22:50:57.171725 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3933 22:50:57.175163 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3934 22:50:57.175247
3935 22:50:57.178364 CA PerBit enable=1, Macro0, CA PI delay=33
3936 22:50:57.181982
3937 22:50:57.182066 [CBTSetCACLKResult] CA Dly = 33
3938 22:50:57.184989 CS Dly: 5 (0~36)
3939 22:50:57.185073 ==
3940 22:50:57.188284 Dram Type= 6, Freq= 0, CH_0, rank 1
3941 22:50:57.192219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 22:50:57.192305 ==
3943 22:50:57.198354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 22:50:57.205259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3945 22:50:57.208343 [CA 0] Center 36 (6~67) winsize 62
3946 22:50:57.211706 [CA 1] Center 36 (6~67) winsize 62
3947 22:50:57.214804 [CA 2] Center 34 (4~65) winsize 62
3948 22:50:57.218167 [CA 3] Center 34 (4~65) winsize 62
3949 22:50:57.221856 [CA 4] Center 34 (3~65) winsize 63
3950 22:50:57.225021 [CA 5] Center 33 (3~64) winsize 62
3951 22:50:57.225105
3952 22:50:57.228094 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3953 22:50:57.228178
3954 22:50:57.231811 [CATrainingPosCal] consider 2 rank data
3955 22:50:57.235010 u2DelayCellTimex100 = 270/100 ps
3956 22:50:57.238707 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3957 22:50:57.241302 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3958 22:50:57.245034 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 22:50:57.248136 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 22:50:57.251424 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3961 22:50:57.254793 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 22:50:57.254877
3963 22:50:57.261604 CA PerBit enable=1, Macro0, CA PI delay=33
3964 22:50:57.261688
3965 22:50:57.261753 [CBTSetCACLKResult] CA Dly = 33
3966 22:50:57.264714 CS Dly: 6 (0~38)
3967 22:50:57.264797
3968 22:50:57.268501 ----->DramcWriteLeveling(PI) begin...
3969 22:50:57.268586 ==
3970 22:50:57.271314 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 22:50:57.275073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 22:50:57.275157 ==
3973 22:50:57.277895 Write leveling (Byte 0): 33 => 33
3974 22:50:57.281306 Write leveling (Byte 1): 32 => 32
3975 22:50:57.284868 DramcWriteLeveling(PI) end<-----
3976 22:50:57.284952
3977 22:50:57.285017 ==
3978 22:50:57.288000 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 22:50:57.291700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 22:50:57.294971 ==
3981 22:50:57.295061 [Gating] SW mode calibration
3982 22:50:57.304594 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3983 22:50:57.308152 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3984 22:50:57.311387 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 22:50:57.317876 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 22:50:57.321286 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3987 22:50:57.324850 0 9 12 | B1->B0 | 3232 2b2b | 1 1 | (1 1) (1 1)
3988 22:50:57.331316 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
3989 22:50:57.334825 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 22:50:57.338047 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 22:50:57.344556 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 22:50:57.347834 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 22:50:57.351071 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 22:50:57.358239 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 22:50:57.361701 0 10 12 | B1->B0 | 2828 3d3d | 1 0 | (0 0) (0 0)
3996 22:50:57.364380 0 10 16 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
3997 22:50:57.367827 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 22:50:57.374686 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 22:50:57.377615 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 22:50:57.381201 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 22:50:57.387712 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 22:50:57.391421 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 22:50:57.394532 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4004 22:50:57.401316 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4005 22:50:57.404389 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 22:50:57.407770 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 22:50:57.414540 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 22:50:57.417847 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 22:50:57.421238 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 22:50:57.427846 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 22:50:57.431236 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 22:50:57.434703 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 22:50:57.441002 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:50:57.444579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:50:57.447703 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:50:57.454290 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:50:57.457938 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:50:57.461222 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:50:57.467389 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4020 22:50:57.471132 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4021 22:50:57.474486 Total UI for P1: 0, mck2ui 16
4022 22:50:57.477414 best dqsien dly found for B0: ( 0, 13, 12)
4023 22:50:57.480762 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 22:50:57.484479 Total UI for P1: 0, mck2ui 16
4025 22:50:57.487467 best dqsien dly found for B1: ( 0, 13, 16)
4026 22:50:57.490912 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4027 22:50:57.494298 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4028 22:50:57.494385
4029 22:50:57.497734 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4030 22:50:57.504001 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4031 22:50:57.504091 [Gating] SW calibration Done
4032 22:50:57.507661 ==
4033 22:50:57.507747 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 22:50:57.514119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 22:50:57.514207 ==
4036 22:50:57.514293 RX Vref Scan: 0
4037 22:50:57.514374
4038 22:50:57.517418 RX Vref 0 -> 0, step: 1
4039 22:50:57.517504
4040 22:50:57.521062 RX Delay -230 -> 252, step: 16
4041 22:50:57.524099 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4042 22:50:57.527342 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4043 22:50:57.534340 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4044 22:50:57.537640 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4045 22:50:57.540711 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4046 22:50:57.544056 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4047 22:50:57.547437 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4048 22:50:57.554065 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4049 22:50:57.557345 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4050 22:50:57.560679 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4051 22:50:57.564179 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4052 22:50:57.570620 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4053 22:50:57.574027 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4054 22:50:57.577503 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4055 22:50:57.580877 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4056 22:50:57.584175 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4057 22:50:57.587518 ==
4058 22:50:57.590883 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 22:50:57.593962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 22:50:57.594086 ==
4061 22:50:57.594173 DQS Delay:
4062 22:50:57.597584 DQS0 = 0, DQS1 = 0
4063 22:50:57.597672 DQM Delay:
4064 22:50:57.600760 DQM0 = 49, DQM1 = 39
4065 22:50:57.600847 DQ Delay:
4066 22:50:57.604137 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4067 22:50:57.607685 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4068 22:50:57.610709 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4069 22:50:57.614136 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4070 22:50:57.614224
4071 22:50:57.614310
4072 22:50:57.614391 ==
4073 22:50:57.617552 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 22:50:57.620905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 22:50:57.621003 ==
4076 22:50:57.621090
4077 22:50:57.621189
4078 22:50:57.624022 TX Vref Scan disable
4079 22:50:57.627606 == TX Byte 0 ==
4080 22:50:57.630772 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4081 22:50:57.633946 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4082 22:50:57.637346 == TX Byte 1 ==
4083 22:50:57.640909 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4084 22:50:57.643887 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4085 22:50:57.643976 ==
4086 22:50:57.647400 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 22:50:57.650503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 22:50:57.654121 ==
4089 22:50:57.654207
4090 22:50:57.654290
4091 22:50:57.654370 TX Vref Scan disable
4092 22:50:57.657672 == TX Byte 0 ==
4093 22:50:57.661270 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4094 22:50:57.664776 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4095 22:50:57.668734 == TX Byte 1 ==
4096 22:50:57.671387 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4097 22:50:57.674807 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4098 22:50:57.678228
4099 22:50:57.678313 [DATLAT]
4100 22:50:57.678398 Freq=600, CH0 RK0
4101 22:50:57.678478
4102 22:50:57.681599 DATLAT Default: 0x9
4103 22:50:57.681684 0, 0xFFFF, sum = 0
4104 22:50:57.684810 1, 0xFFFF, sum = 0
4105 22:50:57.684922 2, 0xFFFF, sum = 0
4106 22:50:57.687859 3, 0xFFFF, sum = 0
4107 22:50:57.687946 4, 0xFFFF, sum = 0
4108 22:50:57.691302 5, 0xFFFF, sum = 0
4109 22:50:57.691388 6, 0xFFFF, sum = 0
4110 22:50:57.694624 7, 0xFFFF, sum = 0
4111 22:50:57.694711 8, 0x0, sum = 1
4112 22:50:57.697953 9, 0x0, sum = 2
4113 22:50:57.698039 10, 0x0, sum = 3
4114 22:50:57.701406 11, 0x0, sum = 4
4115 22:50:57.701493 best_step = 9
4116 22:50:57.701576
4117 22:50:57.701656 ==
4118 22:50:57.704766 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 22:50:57.711504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 22:50:57.711591 ==
4121 22:50:57.711676 RX Vref Scan: 1
4122 22:50:57.711755
4123 22:50:57.714699 RX Vref 0 -> 0, step: 1
4124 22:50:57.714784
4125 22:50:57.717887 RX Delay -179 -> 252, step: 8
4126 22:50:57.717972
4127 22:50:57.721406 Set Vref, RX VrefLevel [Byte0]: 57
4128 22:50:57.724605 [Byte1]: 49
4129 22:50:57.724690
4130 22:50:57.728013 Final RX Vref Byte 0 = 57 to rank0
4131 22:50:57.731350 Final RX Vref Byte 1 = 49 to rank0
4132 22:50:57.735152 Final RX Vref Byte 0 = 57 to rank1
4133 22:50:57.738117 Final RX Vref Byte 1 = 49 to rank1==
4134 22:50:57.741219 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 22:50:57.744709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 22:50:57.744796 ==
4137 22:50:57.748149 DQS Delay:
4138 22:50:57.748234 DQS0 = 0, DQS1 = 0
4139 22:50:57.748318 DQM Delay:
4140 22:50:57.751265 DQM0 = 50, DQM1 = 37
4141 22:50:57.751350 DQ Delay:
4142 22:50:57.754828 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =48
4143 22:50:57.757908 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4144 22:50:57.761436 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4145 22:50:57.764662 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4146 22:50:57.764749
4147 22:50:57.764833
4148 22:50:57.774551 [DQSOSCAuto] RK0, (LSB)MR18= 0x605a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4149 22:50:57.774642 CH0 RK0: MR19=808, MR18=605A
4150 22:50:57.781171 CH0_RK0: MR19=0x808, MR18=0x605A, DQSOSC=391, MR23=63, INC=171, DEC=114
4151 22:50:57.781258
4152 22:50:57.784645 ----->DramcWriteLeveling(PI) begin...
4153 22:50:57.787896 ==
4154 22:50:57.787979 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 22:50:57.794564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 22:50:57.794648 ==
4157 22:50:57.797824 Write leveling (Byte 0): 35 => 35
4158 22:50:57.801115 Write leveling (Byte 1): 30 => 30
4159 22:50:57.804906 DramcWriteLeveling(PI) end<-----
4160 22:50:57.804990
4161 22:50:57.805055 ==
4162 22:50:57.807809 Dram Type= 6, Freq= 0, CH_0, rank 1
4163 22:50:57.810968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 22:50:57.811052 ==
4165 22:50:57.814524 [Gating] SW mode calibration
4166 22:50:57.820959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4167 22:50:57.824497 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4168 22:50:57.830762 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 22:50:57.834114 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 22:50:57.837551 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 22:50:57.844133 0 9 12 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 1)
4172 22:50:57.847795 0 9 16 | B1->B0 | 2828 2424 | 0 0 | (1 1) (0 0)
4173 22:50:57.850904 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 22:50:57.857287 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 22:50:57.860893 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 22:50:57.864410 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 22:50:57.871088 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 22:50:57.874114 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 22:50:57.877651 0 10 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4180 22:50:57.884018 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 22:50:57.887520 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 22:50:57.890958 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 22:50:57.897334 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 22:50:57.900786 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 22:50:57.903770 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 22:50:57.910517 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4187 22:50:57.913592 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 22:50:57.917216 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 22:50:57.923849 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 22:50:57.927267 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 22:50:57.930440 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 22:50:57.937252 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 22:50:57.940444 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 22:50:57.943568 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 22:50:57.950273 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 22:50:57.953691 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 22:50:57.957252 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:50:57.963586 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:50:57.967002 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:50:57.970362 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 22:50:57.973591 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 22:50:57.980303 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 22:50:57.983562 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4204 22:50:57.987115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 22:50:57.990036 Total UI for P1: 0, mck2ui 16
4206 22:50:57.993521 best dqsien dly found for B0: ( 0, 13, 12)
4207 22:50:57.996823 Total UI for P1: 0, mck2ui 16
4208 22:50:58.000254 best dqsien dly found for B1: ( 0, 13, 12)
4209 22:50:58.003558 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4210 22:50:58.010305 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4211 22:50:58.010388
4212 22:50:58.013403 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4213 22:50:58.016616 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 22:50:58.020075 [Gating] SW calibration Done
4215 22:50:58.020157 ==
4216 22:50:58.023378 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 22:50:58.026652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 22:50:58.026740 ==
4219 22:50:58.030082 RX Vref Scan: 0
4220 22:50:58.030165
4221 22:50:58.030231 RX Vref 0 -> 0, step: 1
4222 22:50:58.030293
4223 22:50:58.033184 RX Delay -230 -> 252, step: 16
4224 22:50:58.036619 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4225 22:50:58.043552 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4226 22:50:58.046711 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4227 22:50:58.050004 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4228 22:50:58.053432 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4229 22:50:58.057016 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4230 22:50:58.063164 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4231 22:50:58.066651 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4232 22:50:58.070036 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4233 22:50:58.073267 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4234 22:50:58.079909 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4235 22:50:58.083316 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4236 22:50:58.086771 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4237 22:50:58.089775 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4238 22:50:58.096614 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4239 22:50:58.099798 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4240 22:50:58.099881 ==
4241 22:50:58.103342 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 22:50:58.106476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 22:50:58.106558 ==
4244 22:50:58.106624 DQS Delay:
4245 22:50:58.109853 DQS0 = 0, DQS1 = 0
4246 22:50:58.109936 DQM Delay:
4247 22:50:58.112925 DQM0 = 49, DQM1 = 40
4248 22:50:58.113007 DQ Delay:
4249 22:50:58.116447 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4250 22:50:58.119766 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4251 22:50:58.123156 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4252 22:50:58.126527 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4253 22:50:58.126609
4254 22:50:58.126675
4255 22:50:58.126740 ==
4256 22:50:58.129871 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 22:50:58.133120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 22:50:58.136533 ==
4259 22:50:58.136615
4260 22:50:58.136680
4261 22:50:58.136739 TX Vref Scan disable
4262 22:50:58.140002 == TX Byte 0 ==
4263 22:50:58.143002 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4264 22:50:58.146604 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4265 22:50:58.149722 == TX Byte 1 ==
4266 22:50:58.153049 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4267 22:50:58.156322 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4268 22:50:58.159932 ==
4269 22:50:58.163344 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 22:50:58.166969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 22:50:58.167052 ==
4272 22:50:58.167117
4273 22:50:58.167177
4274 22:50:58.169998 TX Vref Scan disable
4275 22:50:58.170080 == TX Byte 0 ==
4276 22:50:58.176775 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4277 22:50:58.179970 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4278 22:50:58.183129 == TX Byte 1 ==
4279 22:50:58.186323 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4280 22:50:58.189699 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4281 22:50:58.189782
4282 22:50:58.189847 [DATLAT]
4283 22:50:58.193065 Freq=600, CH0 RK1
4284 22:50:58.193147
4285 22:50:58.193212 DATLAT Default: 0x9
4286 22:50:58.196606 0, 0xFFFF, sum = 0
4287 22:50:58.196690 1, 0xFFFF, sum = 0
4288 22:50:58.199628 2, 0xFFFF, sum = 0
4289 22:50:58.203283 3, 0xFFFF, sum = 0
4290 22:50:58.203368 4, 0xFFFF, sum = 0
4291 22:50:58.206221 5, 0xFFFF, sum = 0
4292 22:50:58.206305 6, 0xFFFF, sum = 0
4293 22:50:58.209567 7, 0xFFFF, sum = 0
4294 22:50:58.209650 8, 0x0, sum = 1
4295 22:50:58.209716 9, 0x0, sum = 2
4296 22:50:58.212876 10, 0x0, sum = 3
4297 22:50:58.212960 11, 0x0, sum = 4
4298 22:50:58.216456 best_step = 9
4299 22:50:58.216537
4300 22:50:58.216605 ==
4301 22:50:58.219474 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 22:50:58.223028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 22:50:58.223111 ==
4304 22:50:58.226292 RX Vref Scan: 0
4305 22:50:58.226373
4306 22:50:58.226437 RX Vref 0 -> 0, step: 1
4307 22:50:58.226498
4308 22:50:58.229575 RX Delay -179 -> 252, step: 8
4309 22:50:58.236902 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4310 22:50:58.240324 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4311 22:50:58.243670 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4312 22:50:58.247178 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4313 22:50:58.250368 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4314 22:50:58.257117 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4315 22:50:58.260323 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4316 22:50:58.263296 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4317 22:50:58.266907 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4318 22:50:58.273603 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4319 22:50:58.276974 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4320 22:50:58.280001 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4321 22:50:58.283630 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4322 22:50:58.287032 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4323 22:50:58.293562 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4324 22:50:58.296804 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4325 22:50:58.296886 ==
4326 22:50:58.299993 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 22:50:58.303430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 22:50:58.303512 ==
4329 22:50:58.306740 DQS Delay:
4330 22:50:58.306822 DQS0 = 0, DQS1 = 0
4331 22:50:58.306885 DQM Delay:
4332 22:50:58.310264 DQM0 = 47, DQM1 = 40
4333 22:50:58.310345 DQ Delay:
4334 22:50:58.313413 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4335 22:50:58.316841 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4336 22:50:58.320281 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4337 22:50:58.323497 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =48
4338 22:50:58.323578
4339 22:50:58.323642
4340 22:50:58.333272 [DQSOSCAuto] RK1, (LSB)MR18= 0x6935, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4341 22:50:58.333373 CH0 RK1: MR19=808, MR18=6935
4342 22:50:58.340018 CH0_RK1: MR19=0x808, MR18=0x6935, DQSOSC=390, MR23=63, INC=172, DEC=114
4343 22:50:58.343392 [RxdqsGatingPostProcess] freq 600
4344 22:50:58.349925 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4345 22:50:58.353323 Pre-setting of DQS Precalculation
4346 22:50:58.356778 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4347 22:50:58.356860 ==
4348 22:50:58.360135 Dram Type= 6, Freq= 0, CH_1, rank 0
4349 22:50:58.366694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 22:50:58.366777 ==
4351 22:50:58.370062 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4352 22:50:58.376503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4353 22:50:58.380096 [CA 0] Center 35 (5~66) winsize 62
4354 22:50:58.383363 [CA 1] Center 35 (5~66) winsize 62
4355 22:50:58.386441 [CA 2] Center 34 (3~65) winsize 63
4356 22:50:58.389904 [CA 3] Center 33 (3~64) winsize 62
4357 22:50:58.393253 [CA 4] Center 34 (3~65) winsize 63
4358 22:50:58.396591 [CA 5] Center 33 (3~64) winsize 62
4359 22:50:58.396673
4360 22:50:58.399584 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4361 22:50:58.399667
4362 22:50:58.403260 [CATrainingPosCal] consider 1 rank data
4363 22:50:58.406396 u2DelayCellTimex100 = 270/100 ps
4364 22:50:58.409913 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4365 22:50:58.413113 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 22:50:58.419890 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4367 22:50:58.423174 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 22:50:58.426519 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4369 22:50:58.429801 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4370 22:50:58.429994
4371 22:50:58.433088 CA PerBit enable=1, Macro0, CA PI delay=33
4372 22:50:58.433360
4373 22:50:58.436470 [CBTSetCACLKResult] CA Dly = 33
4374 22:50:58.436754 CS Dly: 3 (0~34)
4375 22:50:58.439693 ==
4376 22:50:58.439893 Dram Type= 6, Freq= 0, CH_1, rank 1
4377 22:50:58.446233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 22:50:58.446548 ==
4379 22:50:58.449712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 22:50:58.456305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4381 22:50:58.460483 [CA 0] Center 35 (5~66) winsize 62
4382 22:50:58.463691 [CA 1] Center 35 (5~66) winsize 62
4383 22:50:58.466964 [CA 2] Center 34 (4~65) winsize 62
4384 22:50:58.469967 [CA 3] Center 34 (4~65) winsize 62
4385 22:50:58.473513 [CA 4] Center 34 (4~65) winsize 62
4386 22:50:58.476388 [CA 5] Center 33 (3~64) winsize 62
4387 22:50:58.476781
4388 22:50:58.480044 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4389 22:50:58.480544
4390 22:50:58.483541 [CATrainingPosCal] consider 2 rank data
4391 22:50:58.486540 u2DelayCellTimex100 = 270/100 ps
4392 22:50:58.489783 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 22:50:58.496621 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 22:50:58.499972 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 22:50:58.503412 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4396 22:50:58.506466 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4397 22:50:58.509478 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 22:50:58.509905
4399 22:50:58.512871 CA PerBit enable=1, Macro0, CA PI delay=33
4400 22:50:58.513315
4401 22:50:58.516112 [CBTSetCACLKResult] CA Dly = 33
4402 22:50:58.516574 CS Dly: 4 (0~36)
4403 22:50:58.519786
4404 22:50:58.523118 ----->DramcWriteLeveling(PI) begin...
4405 22:50:58.523632 ==
4406 22:50:58.526367 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 22:50:58.529414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 22:50:58.529867 ==
4409 22:50:58.532675 Write leveling (Byte 0): 29 => 29
4410 22:50:58.536219 Write leveling (Byte 1): 30 => 30
4411 22:50:58.539455 DramcWriteLeveling(PI) end<-----
4412 22:50:58.539800
4413 22:50:58.540052 ==
4414 22:50:58.542937 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 22:50:58.546157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 22:50:58.546398 ==
4417 22:50:58.549319 [Gating] SW mode calibration
4418 22:50:58.555608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4419 22:50:58.562507 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4420 22:50:58.565628 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 22:50:58.569207 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 22:50:58.575725 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 22:50:58.579055 0 9 12 | B1->B0 | 2d2d 2b2b | 0 1 | (1 0) (1 0)
4424 22:50:58.582387 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 22:50:58.588808 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 22:50:58.592735 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 22:50:58.595571 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 22:50:58.599020 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 22:50:58.605705 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 22:50:58.608895 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 22:50:58.612487 0 10 12 | B1->B0 | 3a3a 3c3c | 1 0 | (0 0) (0 0)
4432 22:50:58.619018 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 22:50:58.622903 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 22:50:58.625549 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 22:50:58.632217 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 22:50:58.635796 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 22:50:58.639048 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 22:50:58.645611 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 22:50:58.649104 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4440 22:50:58.652839 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 22:50:58.659083 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 22:50:58.662435 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 22:50:58.665334 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 22:50:58.672239 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:50:58.675371 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:50:58.678641 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:50:58.685675 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:50:58.688598 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:50:58.692286 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:50:58.698726 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:50:58.702104 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:50:58.705637 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:50:58.708920 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:50:58.715527 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4455 22:50:58.718916 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 22:50:58.721906 Total UI for P1: 0, mck2ui 16
4457 22:50:58.725203 best dqsien dly found for B0: ( 0, 13, 8)
4458 22:50:58.728744 Total UI for P1: 0, mck2ui 16
4459 22:50:58.732078 best dqsien dly found for B1: ( 0, 13, 10)
4460 22:50:58.735130 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4461 22:50:58.738587 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4462 22:50:58.738669
4463 22:50:58.741849 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4464 22:50:58.748508 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4465 22:50:58.748591 [Gating] SW calibration Done
4466 22:50:58.748657 ==
4467 22:50:58.751870 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 22:50:58.758805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 22:50:58.758889 ==
4470 22:50:58.758956 RX Vref Scan: 0
4471 22:50:58.759015
4472 22:50:58.761643 RX Vref 0 -> 0, step: 1
4473 22:50:58.761725
4474 22:50:58.765094 RX Delay -230 -> 252, step: 16
4475 22:50:58.768590 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4476 22:50:58.771792 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4477 22:50:58.775228 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4478 22:50:58.781828 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4479 22:50:58.785165 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4480 22:50:58.788329 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4481 22:50:58.792034 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4482 22:50:58.794968 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4483 22:50:58.801915 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4484 22:50:58.805274 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4485 22:50:58.808332 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4486 22:50:58.811946 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4487 22:50:58.818314 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4488 22:50:58.822009 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4489 22:50:58.825102 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4490 22:50:58.828433 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4491 22:50:58.828517 ==
4492 22:50:58.831837 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 22:50:58.838514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 22:50:58.838601 ==
4495 22:50:58.838666 DQS Delay:
4496 22:50:58.842434 DQS0 = 0, DQS1 = 0
4497 22:50:58.842543 DQM Delay:
4498 22:50:58.842609 DQM0 = 52, DQM1 = 45
4499 22:50:58.845089 DQ Delay:
4500 22:50:58.848638 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4501 22:50:58.851610 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4502 22:50:58.854881 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4503 22:50:58.858506 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4504 22:50:58.858653
4505 22:50:58.858732
4506 22:50:58.858792 ==
4507 22:50:58.861916 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 22:50:58.865062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 22:50:58.865144 ==
4510 22:50:58.865210
4511 22:50:58.865333
4512 22:50:58.868277 TX Vref Scan disable
4513 22:50:58.871466 == TX Byte 0 ==
4514 22:50:58.875026 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4515 22:50:58.878288 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4516 22:50:58.881488 == TX Byte 1 ==
4517 22:50:58.885092 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4518 22:50:58.888109 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4519 22:50:58.888191 ==
4520 22:50:58.891273 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 22:50:58.894672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 22:50:58.897879 ==
4523 22:50:58.897960
4524 22:50:58.898025
4525 22:50:58.898084 TX Vref Scan disable
4526 22:50:58.901809 == TX Byte 0 ==
4527 22:50:58.905242 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4528 22:50:58.908293 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4529 22:50:58.911627 == TX Byte 1 ==
4530 22:50:58.915141 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4531 22:50:58.918484 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4532 22:50:58.922120
4533 22:50:58.922254 [DATLAT]
4534 22:50:58.922321 Freq=600, CH1 RK0
4535 22:50:58.922384
4536 22:50:58.924874 DATLAT Default: 0x9
4537 22:50:58.924962 0, 0xFFFF, sum = 0
4538 22:50:58.928264 1, 0xFFFF, sum = 0
4539 22:50:58.928392 2, 0xFFFF, sum = 0
4540 22:50:58.931767 3, 0xFFFF, sum = 0
4541 22:50:58.931922 4, 0xFFFF, sum = 0
4542 22:50:58.935266 5, 0xFFFF, sum = 0
4543 22:50:58.938432 6, 0xFFFF, sum = 0
4544 22:50:58.938559 7, 0xFFFF, sum = 0
4545 22:50:58.938634 8, 0x0, sum = 1
4546 22:50:58.941481 9, 0x0, sum = 2
4547 22:50:58.941602 10, 0x0, sum = 3
4548 22:50:58.944991 11, 0x0, sum = 4
4549 22:50:58.945083 best_step = 9
4550 22:50:58.945150
4551 22:50:58.945213 ==
4552 22:50:58.948597 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 22:50:58.955410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 22:50:58.955502 ==
4555 22:50:58.955574 RX Vref Scan: 1
4556 22:50:58.955641
4557 22:50:58.958651 RX Vref 0 -> 0, step: 1
4558 22:50:58.958742
4559 22:50:58.961666 RX Delay -163 -> 252, step: 8
4560 22:50:58.961763
4561 22:50:58.965243 Set Vref, RX VrefLevel [Byte0]: 51
4562 22:50:58.968246 [Byte1]: 49
4563 22:50:58.968400
4564 22:50:58.971688 Final RX Vref Byte 0 = 51 to rank0
4565 22:50:58.975005 Final RX Vref Byte 1 = 49 to rank0
4566 22:50:58.978315 Final RX Vref Byte 0 = 51 to rank1
4567 22:50:58.981631 Final RX Vref Byte 1 = 49 to rank1==
4568 22:50:58.985039 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 22:50:58.987874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 22:50:58.988002 ==
4571 22:50:58.991349 DQS Delay:
4572 22:50:58.991473 DQS0 = 0, DQS1 = 0
4573 22:50:58.991572 DQM Delay:
4574 22:50:58.994923 DQM0 = 49, DQM1 = 41
4575 22:50:58.995047 DQ Delay:
4576 22:50:58.997978 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4577 22:50:59.001321 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4578 22:50:59.004563 DQ8 =32, DQ9 =28, DQ10 =44, DQ11 =32
4579 22:50:59.008425 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4580 22:50:59.008527
4581 22:50:59.008605
4582 22:50:59.017954 [DQSOSCAuto] RK0, (LSB)MR18= 0x537b, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 394 ps
4583 22:50:59.021245 CH1 RK0: MR19=808, MR18=537B
4584 22:50:59.024666 CH1_RK0: MR19=0x808, MR18=0x537B, DQSOSC=386, MR23=63, INC=176, DEC=117
4585 22:50:59.024761
4586 22:50:59.027950 ----->DramcWriteLeveling(PI) begin...
4587 22:50:59.031312 ==
4588 22:50:59.034849 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 22:50:59.038170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 22:50:59.038259 ==
4591 22:50:59.041269 Write leveling (Byte 0): 30 => 30
4592 22:50:59.044911 Write leveling (Byte 1): 30 => 30
4593 22:50:59.048208 DramcWriteLeveling(PI) end<-----
4594 22:50:59.048293
4595 22:50:59.048360 ==
4596 22:50:59.051386 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 22:50:59.054646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 22:50:59.054732 ==
4599 22:50:59.057987 [Gating] SW mode calibration
4600 22:50:59.064951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4601 22:50:59.068011 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4602 22:50:59.075337 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 22:50:59.078160 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4604 22:50:59.081645 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 22:50:59.088142 0 9 12 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
4606 22:50:59.091338 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 22:50:59.094813 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 22:50:59.101584 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 22:50:59.104807 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 22:50:59.108138 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 22:50:59.114951 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 22:50:59.118069 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 22:50:59.121220 0 10 12 | B1->B0 | 3c3c 3636 | 0 0 | (1 1) (0 0)
4614 22:50:59.128332 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4615 22:50:59.131758 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 22:50:59.135060 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 22:50:59.141853 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 22:50:59.144730 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 22:50:59.148263 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 22:50:59.154969 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4621 22:50:59.158235 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4622 22:50:59.161641 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 22:50:59.168090 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 22:50:59.171855 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 22:50:59.174907 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 22:50:59.181564 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 22:50:59.184837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 22:50:59.188258 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 22:50:59.191394 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 22:50:59.198086 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 22:50:59.201634 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 22:50:59.204997 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:50:59.211402 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:50:59.214952 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:50:59.217986 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:50:59.224547 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4637 22:50:59.228282 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4638 22:50:59.231269 Total UI for P1: 0, mck2ui 16
4639 22:50:59.234411 best dqsien dly found for B1: ( 0, 13, 10)
4640 22:50:59.237904 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 22:50:59.241567 Total UI for P1: 0, mck2ui 16
4642 22:50:59.244449 best dqsien dly found for B0: ( 0, 13, 10)
4643 22:50:59.248495 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4644 22:50:59.251889 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4645 22:50:59.252326
4646 22:50:59.258671 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4647 22:50:59.261732 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4648 22:50:59.262180 [Gating] SW calibration Done
4649 22:50:59.264745 ==
4650 22:50:59.268329 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 22:50:59.271052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 22:50:59.271299 ==
4653 22:50:59.271482 RX Vref Scan: 0
4654 22:50:59.271652
4655 22:50:59.274546 RX Vref 0 -> 0, step: 1
4656 22:50:59.274735
4657 22:50:59.278082 RX Delay -230 -> 252, step: 16
4658 22:50:59.281077 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4659 22:50:59.284483 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4660 22:50:59.291101 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4661 22:50:59.294111 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4662 22:50:59.297437 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4663 22:50:59.301012 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4664 22:50:59.304221 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4665 22:50:59.310806 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4666 22:50:59.314144 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4667 22:50:59.317268 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4668 22:50:59.320768 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4669 22:50:59.327458 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4670 22:50:59.330796 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4671 22:50:59.333868 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4672 22:50:59.337613 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4673 22:50:59.340643 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4674 22:50:59.344406 ==
4675 22:50:59.347450 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 22:50:59.350633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 22:50:59.350724 ==
4678 22:50:59.350793 DQS Delay:
4679 22:50:59.353866 DQS0 = 0, DQS1 = 0
4680 22:50:59.353952 DQM Delay:
4681 22:50:59.357102 DQM0 = 52, DQM1 = 49
4682 22:50:59.357187 DQ Delay:
4683 22:50:59.360483 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4684 22:50:59.363902 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4685 22:50:59.367299 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4686 22:50:59.370557 DQ12 =65, DQ13 =49, DQ14 =57, DQ15 =65
4687 22:50:59.370651
4688 22:50:59.370720
4689 22:50:59.370780 ==
4690 22:50:59.373753 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 22:50:59.377424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 22:50:59.377510 ==
4693 22:50:59.377577
4694 22:50:59.377637
4695 22:50:59.380383 TX Vref Scan disable
4696 22:50:59.384145 == TX Byte 0 ==
4697 22:50:59.387234 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4698 22:50:59.390629 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4699 22:50:59.393640 == TX Byte 1 ==
4700 22:50:59.397257 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4701 22:50:59.400271 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4702 22:50:59.400356 ==
4703 22:50:59.403715 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 22:50:59.410638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 22:50:59.410737 ==
4706 22:50:59.410804
4707 22:50:59.410865
4708 22:50:59.410923 TX Vref Scan disable
4709 22:50:59.414520 == TX Byte 0 ==
4710 22:50:59.417650 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4711 22:50:59.421558 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4712 22:50:59.424367 == TX Byte 1 ==
4713 22:50:59.427774 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4714 22:50:59.434348 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4715 22:50:59.434466
4716 22:50:59.434534 [DATLAT]
4717 22:50:59.434596 Freq=600, CH1 RK1
4718 22:50:59.434658
4719 22:50:59.437736 DATLAT Default: 0x9
4720 22:50:59.437821 0, 0xFFFF, sum = 0
4721 22:50:59.440914 1, 0xFFFF, sum = 0
4722 22:50:59.441032 2, 0xFFFF, sum = 0
4723 22:50:59.444579 3, 0xFFFF, sum = 0
4724 22:50:59.444668 4, 0xFFFF, sum = 0
4725 22:50:59.447461 5, 0xFFFF, sum = 0
4726 22:50:59.450907 6, 0xFFFF, sum = 0
4727 22:50:59.450996 7, 0xFFFF, sum = 0
4728 22:50:59.451065 8, 0x0, sum = 1
4729 22:50:59.454536 9, 0x0, sum = 2
4730 22:50:59.454624 10, 0x0, sum = 3
4731 22:50:59.457969 11, 0x0, sum = 4
4732 22:50:59.458054 best_step = 9
4733 22:50:59.458120
4734 22:50:59.458180 ==
4735 22:50:59.461255 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 22:50:59.467920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 22:50:59.468005 ==
4738 22:50:59.468072 RX Vref Scan: 0
4739 22:50:59.468137
4740 22:50:59.470817 RX Vref 0 -> 0, step: 1
4741 22:50:59.470901
4742 22:50:59.474207 RX Delay -163 -> 252, step: 8
4743 22:50:59.478124 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4744 22:50:59.484532 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4745 22:50:59.487638 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4746 22:50:59.491229 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4747 22:50:59.494318 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4748 22:50:59.498278 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4749 22:50:59.501456 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4750 22:50:59.507603 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4751 22:50:59.510943 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4752 22:50:59.514615 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4753 22:50:59.517869 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4754 22:50:59.524236 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4755 22:50:59.527819 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4756 22:50:59.531259 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4757 22:50:59.534250 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4758 22:50:59.537770 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4759 22:50:59.537974 ==
4760 22:50:59.541116 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 22:50:59.547594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 22:50:59.547914 ==
4763 22:50:59.548160 DQS Delay:
4764 22:50:59.551291 DQS0 = 0, DQS1 = 0
4765 22:50:59.551679 DQM Delay:
4766 22:50:59.554574 DQM0 = 50, DQM1 = 44
4767 22:50:59.554999 DQ Delay:
4768 22:50:59.558053 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =48
4769 22:50:59.560891 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4770 22:50:59.564611 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4771 22:50:59.568145 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4772 22:50:59.568573
4773 22:50:59.568932
4774 22:50:59.574674 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4775 22:50:59.577685 CH1 RK1: MR19=808, MR18=5E24
4776 22:50:59.584340 CH1_RK1: MR19=0x808, MR18=0x5E24, DQSOSC=392, MR23=63, INC=170, DEC=113
4777 22:50:59.588021 [RxdqsGatingPostProcess] freq 600
4778 22:50:59.591754 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4779 22:50:59.595072 Pre-setting of DQS Precalculation
4780 22:50:59.601100 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4781 22:50:59.607646 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4782 22:50:59.614685 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4783 22:50:59.615123
4784 22:50:59.615467
4785 22:50:59.617743 [Calibration Summary] 1200 Mbps
4786 22:50:59.618175 CH 0, Rank 0
4787 22:50:59.620989 SW Impedance : PASS
4788 22:50:59.624151 DUTY Scan : NO K
4789 22:50:59.624716 ZQ Calibration : PASS
4790 22:50:59.627914 Jitter Meter : NO K
4791 22:50:59.631210 CBT Training : PASS
4792 22:50:59.631735 Write leveling : PASS
4793 22:50:59.634462 RX DQS gating : PASS
4794 22:50:59.637592 RX DQ/DQS(RDDQC) : PASS
4795 22:50:59.638015 TX DQ/DQS : PASS
4796 22:50:59.641119 RX DATLAT : PASS
4797 22:50:59.644555 RX DQ/DQS(Engine): PASS
4798 22:50:59.645000 TX OE : NO K
4799 22:50:59.647710 All Pass.
4800 22:50:59.648207
4801 22:50:59.648657 CH 0, Rank 1
4802 22:50:59.651161 SW Impedance : PASS
4803 22:50:59.651604 DUTY Scan : NO K
4804 22:50:59.654585 ZQ Calibration : PASS
4805 22:50:59.655048 Jitter Meter : NO K
4806 22:50:59.657820 CBT Training : PASS
4807 22:50:59.661115 Write leveling : PASS
4808 22:50:59.661599 RX DQS gating : PASS
4809 22:50:59.664835 RX DQ/DQS(RDDQC) : PASS
4810 22:50:59.667645 TX DQ/DQS : PASS
4811 22:50:59.668091 RX DATLAT : PASS
4812 22:50:59.671558 RX DQ/DQS(Engine): PASS
4813 22:50:59.674786 TX OE : NO K
4814 22:50:59.675327 All Pass.
4815 22:50:59.675778
4816 22:50:59.676198 CH 1, Rank 0
4817 22:50:59.677738 SW Impedance : PASS
4818 22:50:59.681463 DUTY Scan : NO K
4819 22:50:59.681999 ZQ Calibration : PASS
4820 22:50:59.684696 Jitter Meter : NO K
4821 22:50:59.688215 CBT Training : PASS
4822 22:50:59.688757 Write leveling : PASS
4823 22:50:59.691206 RX DQS gating : PASS
4824 22:50:59.694091 RX DQ/DQS(RDDQC) : PASS
4825 22:50:59.694537 TX DQ/DQS : PASS
4826 22:50:59.697586 RX DATLAT : PASS
4827 22:50:59.698126 RX DQ/DQS(Engine): PASS
4828 22:50:59.701205 TX OE : NO K
4829 22:50:59.701798 All Pass.
4830 22:50:59.702251
4831 22:50:59.704265 CH 1, Rank 1
4832 22:50:59.704707 SW Impedance : PASS
4833 22:50:59.707965 DUTY Scan : NO K
4834 22:50:59.711369 ZQ Calibration : PASS
4835 22:50:59.711816 Jitter Meter : NO K
4836 22:50:59.714237 CBT Training : PASS
4837 22:50:59.717635 Write leveling : PASS
4838 22:50:59.718079 RX DQS gating : PASS
4839 22:50:59.720951 RX DQ/DQS(RDDQC) : PASS
4840 22:50:59.724043 TX DQ/DQS : PASS
4841 22:50:59.724467 RX DATLAT : PASS
4842 22:50:59.727786 RX DQ/DQS(Engine): PASS
4843 22:50:59.731178 TX OE : NO K
4844 22:50:59.731701 All Pass.
4845 22:50:59.732045
4846 22:50:59.733846 DramC Write-DBI off
4847 22:50:59.734273 PER_BANK_REFRESH: Hybrid Mode
4848 22:50:59.737871 TX_TRACKING: ON
4849 22:50:59.744370 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4850 22:50:59.751081 [FAST_K] Save calibration result to emmc
4851 22:50:59.753967 dramc_set_vcore_voltage set vcore to 662500
4852 22:50:59.754391 Read voltage for 933, 3
4853 22:50:59.757184 Vio18 = 0
4854 22:50:59.757748 Vcore = 662500
4855 22:50:59.758096 Vdram = 0
4856 22:50:59.760698 Vddq = 0
4857 22:50:59.761327 Vmddr = 0
4858 22:50:59.764094 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4859 22:50:59.770838 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4860 22:50:59.773664 MEM_TYPE=3, freq_sel=17
4861 22:50:59.777796 sv_algorithm_assistance_LP4_1600
4862 22:50:59.780631 ============ PULL DRAM RESETB DOWN ============
4863 22:50:59.783940 ========== PULL DRAM RESETB DOWN end =========
4864 22:50:59.790699 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4865 22:50:59.794002 ===================================
4866 22:50:59.794535 LPDDR4 DRAM CONFIGURATION
4867 22:50:59.797082 ===================================
4868 22:50:59.800403 EX_ROW_EN[0] = 0x0
4869 22:50:59.800938 EX_ROW_EN[1] = 0x0
4870 22:50:59.803735 LP4Y_EN = 0x0
4871 22:50:59.804268 WORK_FSP = 0x0
4872 22:50:59.806821 WL = 0x3
4873 22:50:59.807266 RL = 0x3
4874 22:50:59.810152 BL = 0x2
4875 22:50:59.813907 RPST = 0x0
4876 22:50:59.814449 RD_PRE = 0x0
4877 22:50:59.816949 WR_PRE = 0x1
4878 22:50:59.817578 WR_PST = 0x0
4879 22:50:59.820026 DBI_WR = 0x0
4880 22:50:59.820471 DBI_RD = 0x0
4881 22:50:59.823717 OTF = 0x1
4882 22:50:59.826895 ===================================
4883 22:50:59.830137 ===================================
4884 22:50:59.830681 ANA top config
4885 22:50:59.833789 ===================================
4886 22:50:59.837190 DLL_ASYNC_EN = 0
4887 22:50:59.840427 ALL_SLAVE_EN = 1
4888 22:50:59.840973 NEW_RANK_MODE = 1
4889 22:50:59.843610 DLL_IDLE_MODE = 1
4890 22:50:59.846783 LP45_APHY_COMB_EN = 1
4891 22:50:59.849878 TX_ODT_DIS = 1
4892 22:50:59.853034 NEW_8X_MODE = 1
4893 22:50:59.853521 ===================================
4894 22:50:59.856900 ===================================
4895 22:50:59.860034 data_rate = 1866
4896 22:50:59.863480 CKR = 1
4897 22:50:59.866496 DQ_P2S_RATIO = 8
4898 22:50:59.870007 ===================================
4899 22:50:59.873117 CA_P2S_RATIO = 8
4900 22:50:59.876850 DQ_CA_OPEN = 0
4901 22:50:59.880004 DQ_SEMI_OPEN = 0
4902 22:50:59.880537 CA_SEMI_OPEN = 0
4903 22:50:59.883455 CA_FULL_RATE = 0
4904 22:50:59.886681 DQ_CKDIV4_EN = 1
4905 22:50:59.890238 CA_CKDIV4_EN = 1
4906 22:50:59.893445 CA_PREDIV_EN = 0
4907 22:50:59.896615 PH8_DLY = 0
4908 22:50:59.897168 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4909 22:50:59.900111 DQ_AAMCK_DIV = 4
4910 22:50:59.903482 CA_AAMCK_DIV = 4
4911 22:50:59.906379 CA_ADMCK_DIV = 4
4912 22:50:59.909591 DQ_TRACK_CA_EN = 0
4913 22:50:59.913145 CA_PICK = 933
4914 22:50:59.913712 CA_MCKIO = 933
4915 22:50:59.916890 MCKIO_SEMI = 0
4916 22:50:59.919633 PLL_FREQ = 3732
4917 22:50:59.923198 DQ_UI_PI_RATIO = 32
4918 22:50:59.926201 CA_UI_PI_RATIO = 0
4919 22:50:59.929532 ===================================
4920 22:50:59.933140 ===================================
4921 22:50:59.936579 memory_type:LPDDR4
4922 22:50:59.937100 GP_NUM : 10
4923 22:50:59.939599 SRAM_EN : 1
4924 22:50:59.940125 MD32_EN : 0
4925 22:50:59.942858 ===================================
4926 22:50:59.946129 [ANA_INIT] >>>>>>>>>>>>>>
4927 22:50:59.949784 <<<<<< [CONFIGURE PHASE]: ANA_TX
4928 22:50:59.953083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4929 22:50:59.956125 ===================================
4930 22:50:59.959504 data_rate = 1866,PCW = 0X8f00
4931 22:50:59.963329 ===================================
4932 22:50:59.966351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4933 22:50:59.972927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4934 22:50:59.975908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4935 22:50:59.982892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4936 22:50:59.986242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4937 22:50:59.989673 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4938 22:50:59.990203 [ANA_INIT] flow start
4939 22:50:59.992902 [ANA_INIT] PLL >>>>>>>>
4940 22:50:59.996233 [ANA_INIT] PLL <<<<<<<<
4941 22:50:59.996757 [ANA_INIT] MIDPI >>>>>>>>
4942 22:50:59.999811 [ANA_INIT] MIDPI <<<<<<<<
4943 22:51:00.002866 [ANA_INIT] DLL >>>>>>>>
4944 22:51:00.003434 [ANA_INIT] flow end
4945 22:51:00.009689 ============ LP4 DIFF to SE enter ============
4946 22:51:00.013133 ============ LP4 DIFF to SE exit ============
4947 22:51:00.013689 [ANA_INIT] <<<<<<<<<<<<<
4948 22:51:00.016100 [Flow] Enable top DCM control >>>>>
4949 22:51:00.019107 [Flow] Enable top DCM control <<<<<
4950 22:51:00.022813 Enable DLL master slave shuffle
4951 22:51:00.029507 ==============================================================
4952 22:51:00.032589 Gating Mode config
4953 22:51:00.036369 ==============================================================
4954 22:51:00.039431 Config description:
4955 22:51:00.049525 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4956 22:51:00.055607 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4957 22:51:00.059791 SELPH_MODE 0: By rank 1: By Phase
4958 22:51:00.066068 ==============================================================
4959 22:51:00.069750 GAT_TRACK_EN = 1
4960 22:51:00.072376 RX_GATING_MODE = 2
4961 22:51:00.075520 RX_GATING_TRACK_MODE = 2
4962 22:51:00.075975 SELPH_MODE = 1
4963 22:51:00.079334 PICG_EARLY_EN = 1
4964 22:51:00.082917 VALID_LAT_VALUE = 1
4965 22:51:00.089533 ==============================================================
4966 22:51:00.092958 Enter into Gating configuration >>>>
4967 22:51:00.095860 Exit from Gating configuration <<<<
4968 22:51:00.099297 Enter into DVFS_PRE_config >>>>>
4969 22:51:00.109216 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4970 22:51:00.112723 Exit from DVFS_PRE_config <<<<<
4971 22:51:00.115685 Enter into PICG configuration >>>>
4972 22:51:00.119053 Exit from PICG configuration <<<<
4973 22:51:00.122244 [RX_INPUT] configuration >>>>>
4974 22:51:00.125553 [RX_INPUT] configuration <<<<<
4975 22:51:00.128801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4976 22:51:00.135513 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4977 22:51:00.142720 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 22:51:00.149270 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 22:51:00.152372 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 22:51:00.158708 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 22:51:00.161996 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4982 22:51:00.169460 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4983 22:51:00.172165 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4984 22:51:00.175650 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4985 22:51:00.179336 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4986 22:51:00.185389 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4987 22:51:00.189215 ===================================
4988 22:51:00.189806 LPDDR4 DRAM CONFIGURATION
4989 22:51:00.192357 ===================================
4990 22:51:00.195790 EX_ROW_EN[0] = 0x0
4991 22:51:00.199306 EX_ROW_EN[1] = 0x0
4992 22:51:00.199847 LP4Y_EN = 0x0
4993 22:51:00.201953 WORK_FSP = 0x0
4994 22:51:00.202382 WL = 0x3
4995 22:51:00.205602 RL = 0x3
4996 22:51:00.206133 BL = 0x2
4997 22:51:00.208710 RPST = 0x0
4998 22:51:00.209242 RD_PRE = 0x0
4999 22:51:00.212133 WR_PRE = 0x1
5000 22:51:00.212663 WR_PST = 0x0
5001 22:51:00.215424 DBI_WR = 0x0
5002 22:51:00.215960 DBI_RD = 0x0
5003 22:51:00.218845 OTF = 0x1
5004 22:51:00.221879 ===================================
5005 22:51:00.225393 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5006 22:51:00.228749 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5007 22:51:00.235267 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5008 22:51:00.238840 ===================================
5009 22:51:00.239383 LPDDR4 DRAM CONFIGURATION
5010 22:51:00.242103 ===================================
5011 22:51:00.245401 EX_ROW_EN[0] = 0x10
5012 22:51:00.248890 EX_ROW_EN[1] = 0x0
5013 22:51:00.249457 LP4Y_EN = 0x0
5014 22:51:00.251876 WORK_FSP = 0x0
5015 22:51:00.252410 WL = 0x3
5016 22:51:00.255168 RL = 0x3
5017 22:51:00.255704 BL = 0x2
5018 22:51:00.258353 RPST = 0x0
5019 22:51:00.258800 RD_PRE = 0x0
5020 22:51:00.262032 WR_PRE = 0x1
5021 22:51:00.262623 WR_PST = 0x0
5022 22:51:00.265183 DBI_WR = 0x0
5023 22:51:00.265746 DBI_RD = 0x0
5024 22:51:00.268386 OTF = 0x1
5025 22:51:00.271542 ===================================
5026 22:51:00.278294 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5027 22:51:00.281710 nWR fixed to 30
5028 22:51:00.282263 [ModeRegInit_LP4] CH0 RK0
5029 22:51:00.285121 [ModeRegInit_LP4] CH0 RK1
5030 22:51:00.288381 [ModeRegInit_LP4] CH1 RK0
5031 22:51:00.292020 [ModeRegInit_LP4] CH1 RK1
5032 22:51:00.292556 match AC timing 9
5033 22:51:00.294644 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5034 22:51:00.302140 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5035 22:51:00.305009 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5036 22:51:00.311835 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5037 22:51:00.315098 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5038 22:51:00.315638 ==
5039 22:51:00.318366 Dram Type= 6, Freq= 0, CH_0, rank 0
5040 22:51:00.321597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5041 22:51:00.322032 ==
5042 22:51:00.328354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5043 22:51:00.334811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5044 22:51:00.338209 [CA 0] Center 37 (7~68) winsize 62
5045 22:51:00.341590 [CA 1] Center 38 (8~69) winsize 62
5046 22:51:00.344830 [CA 2] Center 35 (5~66) winsize 62
5047 22:51:00.348443 [CA 3] Center 35 (5~65) winsize 61
5048 22:51:00.351735 [CA 4] Center 34 (4~65) winsize 62
5049 22:51:00.352273 [CA 5] Center 33 (3~64) winsize 62
5050 22:51:00.354796
5051 22:51:00.358264 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5052 22:51:00.358697
5053 22:51:00.361794 [CATrainingPosCal] consider 1 rank data
5054 22:51:00.365083 u2DelayCellTimex100 = 270/100 ps
5055 22:51:00.368130 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5056 22:51:00.371606 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5057 22:51:00.375292 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5058 22:51:00.378106 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5059 22:51:00.381409 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5060 22:51:00.385249 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5061 22:51:00.385832
5062 22:51:00.388038 CA PerBit enable=1, Macro0, CA PI delay=33
5063 22:51:00.392147
5064 22:51:00.392677 [CBTSetCACLKResult] CA Dly = 33
5065 22:51:00.395027 CS Dly: 7 (0~38)
5066 22:51:00.395552 ==
5067 22:51:00.398010 Dram Type= 6, Freq= 0, CH_0, rank 1
5068 22:51:00.401677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 22:51:00.402203 ==
5070 22:51:00.408277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 22:51:00.415038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5072 22:51:00.418280 [CA 0] Center 38 (7~69) winsize 63
5073 22:51:00.421373 [CA 1] Center 38 (8~69) winsize 62
5074 22:51:00.424718 [CA 2] Center 36 (6~67) winsize 62
5075 22:51:00.427946 [CA 3] Center 36 (5~67) winsize 63
5076 22:51:00.431303 [CA 4] Center 34 (4~65) winsize 62
5077 22:51:00.434594 [CA 5] Center 34 (4~65) winsize 62
5078 22:51:00.435122
5079 22:51:00.438189 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5080 22:51:00.438709
5081 22:51:00.441393 [CATrainingPosCal] consider 2 rank data
5082 22:51:00.444807 u2DelayCellTimex100 = 270/100 ps
5083 22:51:00.448194 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5084 22:51:00.451079 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5085 22:51:00.454723 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5086 22:51:00.457873 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5087 22:51:00.461104 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5088 22:51:00.464481 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5089 22:51:00.464913
5090 22:51:00.471112 CA PerBit enable=1, Macro0, CA PI delay=34
5091 22:51:00.471652
5092 22:51:00.471998 [CBTSetCACLKResult] CA Dly = 34
5093 22:51:00.474489 CS Dly: 7 (0~39)
5094 22:51:00.474917
5095 22:51:00.477809 ----->DramcWriteLeveling(PI) begin...
5096 22:51:00.478248 ==
5097 22:51:00.480959 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 22:51:00.484043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 22:51:00.484478 ==
5100 22:51:00.487682 Write leveling (Byte 0): 32 => 32
5101 22:51:00.491003 Write leveling (Byte 1): 29 => 29
5102 22:51:00.494201 DramcWriteLeveling(PI) end<-----
5103 22:51:00.494736
5104 22:51:00.495215 ==
5105 22:51:00.497515 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 22:51:00.504831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 22:51:00.505403 ==
5108 22:51:00.505760 [Gating] SW mode calibration
5109 22:51:00.514463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5110 22:51:00.517659 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5111 22:51:00.520808 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5112 22:51:00.528060 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 22:51:00.531007 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 22:51:00.534341 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 22:51:00.540534 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 22:51:00.544421 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 22:51:00.547717 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5118 22:51:00.553973 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5119 22:51:00.557662 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5120 22:51:00.560768 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 22:51:00.567630 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 22:51:00.571110 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 22:51:00.573824 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 22:51:00.580718 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 22:51:00.584034 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5126 22:51:00.587637 0 15 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
5127 22:51:00.593863 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 22:51:00.597472 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 22:51:00.600613 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 22:51:00.607673 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 22:51:00.610949 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 22:51:00.614185 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 22:51:00.620540 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5134 22:51:00.624096 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5135 22:51:00.627307 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5136 22:51:00.630587 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 22:51:00.637247 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 22:51:00.640689 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 22:51:00.643802 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 22:51:00.650580 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 22:51:00.653482 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 22:51:00.656823 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 22:51:00.663677 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 22:51:00.667131 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:51:00.670202 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:51:00.677176 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:51:00.680133 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:51:00.683948 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:51:00.690326 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5150 22:51:00.690835 Total UI for P1: 0, mck2ui 16
5151 22:51:00.697137 best dqsien dly found for B0: ( 1, 2, 22)
5152 22:51:00.700690 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5153 22:51:00.703925 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5154 22:51:00.710391 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 22:51:00.710916 Total UI for P1: 0, mck2ui 16
5156 22:51:00.717721 best dqsien dly found for B1: ( 1, 2, 28)
5157 22:51:00.720166 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5158 22:51:00.723860 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5159 22:51:00.724390
5160 22:51:00.726892 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5161 22:51:00.730473 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5162 22:51:00.734168 [Gating] SW calibration Done
5163 22:51:00.734690 ==
5164 22:51:00.736966 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 22:51:00.740541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 22:51:00.741075 ==
5167 22:51:00.743789 RX Vref Scan: 0
5168 22:51:00.744313
5169 22:51:00.744650 RX Vref 0 -> 0, step: 1
5170 22:51:00.744966
5171 22:51:00.747527 RX Delay -80 -> 252, step: 8
5172 22:51:00.750319 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5173 22:51:00.757352 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5174 22:51:00.760337 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5175 22:51:00.763355 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5176 22:51:00.766770 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5177 22:51:00.770497 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5178 22:51:00.773281 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5179 22:51:00.780277 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5180 22:51:00.783428 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5181 22:51:00.786861 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5182 22:51:00.789912 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5183 22:51:00.793509 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5184 22:51:00.796421 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5185 22:51:00.803445 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5186 22:51:00.806774 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5187 22:51:00.809930 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5188 22:51:00.810358 ==
5189 22:51:00.813447 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 22:51:00.816673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 22:51:00.817203 ==
5192 22:51:00.819947 DQS Delay:
5193 22:51:00.820374 DQS0 = 0, DQS1 = 0
5194 22:51:00.823469 DQM Delay:
5195 22:51:00.823996 DQM0 = 105, DQM1 = 90
5196 22:51:00.824344 DQ Delay:
5197 22:51:00.826863 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5198 22:51:00.830074 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5199 22:51:00.833469 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5200 22:51:00.836945 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5201 22:51:00.837499
5202 22:51:00.839824
5203 22:51:00.840345 ==
5204 22:51:00.843268 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 22:51:00.846218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 22:51:00.846752 ==
5207 22:51:00.847101
5208 22:51:00.847421
5209 22:51:00.849690 TX Vref Scan disable
5210 22:51:00.850122 == TX Byte 0 ==
5211 22:51:00.856710 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5212 22:51:00.859791 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5213 22:51:00.860311 == TX Byte 1 ==
5214 22:51:00.866746 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5215 22:51:00.869599 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5216 22:51:00.870033 ==
5217 22:51:00.873430 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 22:51:00.876487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 22:51:00.876928 ==
5220 22:51:00.877266
5221 22:51:00.877652
5222 22:51:00.879840 TX Vref Scan disable
5223 22:51:00.883404 == TX Byte 0 ==
5224 22:51:00.886744 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5225 22:51:00.890086 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5226 22:51:00.892968 == TX Byte 1 ==
5227 22:51:00.896613 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5228 22:51:00.900327 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5229 22:51:00.900844
5230 22:51:00.901187 [DATLAT]
5231 22:51:00.903015 Freq=933, CH0 RK0
5232 22:51:00.903439
5233 22:51:00.906398 DATLAT Default: 0xd
5234 22:51:00.906829 0, 0xFFFF, sum = 0
5235 22:51:00.909689 1, 0xFFFF, sum = 0
5236 22:51:00.910119 2, 0xFFFF, sum = 0
5237 22:51:00.913435 3, 0xFFFF, sum = 0
5238 22:51:00.913960 4, 0xFFFF, sum = 0
5239 22:51:00.916195 5, 0xFFFF, sum = 0
5240 22:51:00.916629 6, 0xFFFF, sum = 0
5241 22:51:00.922018 7, 0xFFFF, sum = 0
5242 22:51:00.922541 8, 0xFFFF, sum = 0
5243 22:51:00.923235 9, 0xFFFF, sum = 0
5244 22:51:00.923600 10, 0x0, sum = 1
5245 22:51:00.926503 11, 0x0, sum = 2
5246 22:51:00.926935 12, 0x0, sum = 3
5247 22:51:00.929895 13, 0x0, sum = 4
5248 22:51:00.930326 best_step = 11
5249 22:51:00.930665
5250 22:51:00.930981 ==
5251 22:51:00.933015 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 22:51:00.936507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 22:51:00.939753 ==
5254 22:51:00.940177 RX Vref Scan: 1
5255 22:51:00.940517
5256 22:51:00.943614 RX Vref 0 -> 0, step: 1
5257 22:51:00.944041
5258 22:51:00.944379 RX Delay -53 -> 252, step: 4
5259 22:51:00.946387
5260 22:51:00.946810 Set Vref, RX VrefLevel [Byte0]: 57
5261 22:51:00.949774 [Byte1]: 49
5262 22:51:00.954750
5263 22:51:00.955279 Final RX Vref Byte 0 = 57 to rank0
5264 22:51:00.958107 Final RX Vref Byte 1 = 49 to rank0
5265 22:51:00.961176 Final RX Vref Byte 0 = 57 to rank1
5266 22:51:00.964413 Final RX Vref Byte 1 = 49 to rank1==
5267 22:51:00.968204 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 22:51:00.974905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 22:51:00.975538 ==
5270 22:51:00.975893 DQS Delay:
5271 22:51:00.976254 DQS0 = 0, DQS1 = 0
5272 22:51:00.977973 DQM Delay:
5273 22:51:00.978506 DQM0 = 107, DQM1 = 91
5274 22:51:00.981439 DQ Delay:
5275 22:51:00.984556 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5276 22:51:00.988022 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =114
5277 22:51:00.991279 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5278 22:51:00.994793 DQ12 =94, DQ13 =90, DQ14 =104, DQ15 =100
5279 22:51:00.995322
5280 22:51:00.995661
5281 22:51:01.001446 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5282 22:51:01.004968 CH0 RK0: MR19=505, MR18=2622
5283 22:51:01.011608 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5284 22:51:01.012190
5285 22:51:01.014671 ----->DramcWriteLeveling(PI) begin...
5286 22:51:01.015253 ==
5287 22:51:01.018132 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 22:51:01.021282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 22:51:01.021794 ==
5290 22:51:01.024621 Write leveling (Byte 0): 31 => 31
5291 22:51:01.027853 Write leveling (Byte 1): 29 => 29
5292 22:51:01.031579 DramcWriteLeveling(PI) end<-----
5293 22:51:01.032147
5294 22:51:01.032513 ==
5295 22:51:01.034509 Dram Type= 6, Freq= 0, CH_0, rank 1
5296 22:51:01.037575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 22:51:01.041127 ==
5298 22:51:01.041575 [Gating] SW mode calibration
5299 22:51:01.050658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5300 22:51:01.054071 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5301 22:51:01.058019 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 22:51:01.064128 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 22:51:01.067770 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 22:51:01.070965 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 22:51:01.077398 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 22:51:01.080924 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 22:51:01.084007 0 14 24 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
5308 22:51:01.091075 0 14 28 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
5309 22:51:01.093927 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 22:51:01.097332 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 22:51:01.104382 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 22:51:01.107527 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 22:51:01.110686 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 22:51:01.117582 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 22:51:01.121213 0 15 24 | B1->B0 | 2828 2828 | 0 0 | (0 0) (0 0)
5316 22:51:01.124298 0 15 28 | B1->B0 | 3939 4040 | 0 0 | (0 0) (0 0)
5317 22:51:01.131139 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 22:51:01.134005 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 22:51:01.137884 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 22:51:01.141150 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 22:51:01.147873 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 22:51:01.151376 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 22:51:01.154137 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 22:51:01.161249 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5325 22:51:01.164433 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 22:51:01.167489 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 22:51:01.174264 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 22:51:01.177610 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 22:51:01.181146 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 22:51:01.187605 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 22:51:01.190967 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 22:51:01.193950 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 22:51:01.200742 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 22:51:01.203545 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 22:51:01.207265 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:51:01.213918 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 22:51:01.216730 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 22:51:01.220272 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 22:51:01.226991 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5340 22:51:01.230380 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5341 22:51:01.233360 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 22:51:01.236900 Total UI for P1: 0, mck2ui 16
5343 22:51:01.240208 best dqsien dly found for B0: ( 1, 2, 26)
5344 22:51:01.243596 Total UI for P1: 0, mck2ui 16
5345 22:51:01.246774 best dqsien dly found for B1: ( 1, 2, 26)
5346 22:51:01.250157 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5347 22:51:01.253676 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5348 22:51:01.254245
5349 22:51:01.259885 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5350 22:51:01.263569 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5351 22:51:01.266186 [Gating] SW calibration Done
5352 22:51:01.266653 ==
5353 22:51:01.269808 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 22:51:01.273349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 22:51:01.273916 ==
5356 22:51:01.274293 RX Vref Scan: 0
5357 22:51:01.274637
5358 22:51:01.276336 RX Vref 0 -> 0, step: 1
5359 22:51:01.276810
5360 22:51:01.279824 RX Delay -80 -> 252, step: 8
5361 22:51:01.283154 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5362 22:51:01.286689 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5363 22:51:01.292952 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5364 22:51:01.296236 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5365 22:51:01.299297 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5366 22:51:01.303290 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5367 22:51:01.306600 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5368 22:51:01.309737 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5369 22:51:01.316145 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5370 22:51:01.319422 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5371 22:51:01.322970 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5372 22:51:01.326217 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5373 22:51:01.329533 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5374 22:51:01.335970 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5375 22:51:01.339100 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5376 22:51:01.342281 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5377 22:51:01.342850 ==
5378 22:51:01.345747 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 22:51:01.349143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 22:51:01.349641 ==
5381 22:51:01.352378 DQS Delay:
5382 22:51:01.352944 DQS0 = 0, DQS1 = 0
5383 22:51:01.353364 DQM Delay:
5384 22:51:01.355735 DQM0 = 104, DQM1 = 90
5385 22:51:01.356208 DQ Delay:
5386 22:51:01.359195 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5387 22:51:01.362057 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =111
5388 22:51:01.365348 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5389 22:51:01.368660 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5390 22:51:01.369192
5391 22:51:01.369587
5392 22:51:01.372186 ==
5393 22:51:01.375760 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 22:51:01.378764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 22:51:01.379274 ==
5396 22:51:01.379652
5397 22:51:01.379997
5398 22:51:01.381992 TX Vref Scan disable
5399 22:51:01.382463 == TX Byte 0 ==
5400 22:51:01.385284 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5401 22:51:01.392104 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5402 22:51:01.392679 == TX Byte 1 ==
5403 22:51:01.395378 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5404 22:51:01.401875 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5405 22:51:01.402346 ==
5406 22:51:01.405366 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 22:51:01.408691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 22:51:01.409260 ==
5409 22:51:01.409685
5410 22:51:01.410034
5411 22:51:01.411755 TX Vref Scan disable
5412 22:51:01.415583 == TX Byte 0 ==
5413 22:51:01.418296 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5414 22:51:01.421661 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5415 22:51:01.425088 == TX Byte 1 ==
5416 22:51:01.428289 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5417 22:51:01.431694 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5418 22:51:01.432218
5419 22:51:01.435297 [DATLAT]
5420 22:51:01.435817 Freq=933, CH0 RK1
5421 22:51:01.436153
5422 22:51:01.438469 DATLAT Default: 0xb
5423 22:51:01.438997 0, 0xFFFF, sum = 0
5424 22:51:01.441737 1, 0xFFFF, sum = 0
5425 22:51:01.442283 2, 0xFFFF, sum = 0
5426 22:51:01.445032 3, 0xFFFF, sum = 0
5427 22:51:01.445593 4, 0xFFFF, sum = 0
5428 22:51:01.448837 5, 0xFFFF, sum = 0
5429 22:51:01.449393 6, 0xFFFF, sum = 0
5430 22:51:01.451283 7, 0xFFFF, sum = 0
5431 22:51:01.451710 8, 0xFFFF, sum = 0
5432 22:51:01.454835 9, 0xFFFF, sum = 0
5433 22:51:01.455362 10, 0x0, sum = 1
5434 22:51:01.458318 11, 0x0, sum = 2
5435 22:51:01.458744 12, 0x0, sum = 3
5436 22:51:01.461684 13, 0x0, sum = 4
5437 22:51:01.462211 best_step = 11
5438 22:51:01.462548
5439 22:51:01.462859 ==
5440 22:51:01.464946 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 22:51:01.471885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 22:51:01.472416 ==
5443 22:51:01.472757 RX Vref Scan: 0
5444 22:51:01.473074
5445 22:51:01.474532 RX Vref 0 -> 0, step: 1
5446 22:51:01.474954
5447 22:51:01.477602 RX Delay -53 -> 252, step: 4
5448 22:51:01.481215 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5449 22:51:01.484401 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5450 22:51:01.491446 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5451 22:51:01.494830 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5452 22:51:01.497780 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5453 22:51:01.501127 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5454 22:51:01.505101 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5455 22:51:01.511379 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5456 22:51:01.514206 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5457 22:51:01.517656 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5458 22:51:01.521181 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5459 22:51:01.524318 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5460 22:51:01.527861 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5461 22:51:01.534672 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5462 22:51:01.537672 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5463 22:51:01.541714 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5464 22:51:01.542241 ==
5465 22:51:01.544142 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 22:51:01.547957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 22:51:01.551411 ==
5468 22:51:01.551933 DQS Delay:
5469 22:51:01.552271 DQS0 = 0, DQS1 = 0
5470 22:51:01.554202 DQM Delay:
5471 22:51:01.554675 DQM0 = 104, DQM1 = 92
5472 22:51:01.558220 DQ Delay:
5473 22:51:01.560881 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5474 22:51:01.563925 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =110
5475 22:51:01.567485 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =92
5476 22:51:01.571248 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5477 22:51:01.571791
5478 22:51:01.572132
5479 22:51:01.577440 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5480 22:51:01.580799 CH0 RK1: MR19=505, MR18=2F0F
5481 22:51:01.587266 CH0_RK1: MR19=0x505, MR18=0x2F0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5482 22:51:01.590575 [RxdqsGatingPostProcess] freq 933
5483 22:51:01.596899 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5484 22:51:01.597471 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 22:51:01.600467 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 22:51:01.603848 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 22:51:01.607423 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 22:51:01.610353 best DQS0 dly(2T, 0.5T) = (0, 10)
5489 22:51:01.613846 best DQS1 dly(2T, 0.5T) = (0, 10)
5490 22:51:01.616946 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5491 22:51:01.620394 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5492 22:51:01.623823 Pre-setting of DQS Precalculation
5493 22:51:01.630316 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5494 22:51:01.630839 ==
5495 22:51:01.633963 Dram Type= 6, Freq= 0, CH_1, rank 0
5496 22:51:01.636844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 22:51:01.637394 ==
5498 22:51:01.643919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5499 22:51:01.646663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5500 22:51:01.651302 [CA 0] Center 37 (7~68) winsize 62
5501 22:51:01.654415 [CA 1] Center 37 (7~68) winsize 62
5502 22:51:01.657347 [CA 2] Center 36 (6~66) winsize 61
5503 22:51:01.660814 [CA 3] Center 34 (4~65) winsize 62
5504 22:51:01.664134 [CA 4] Center 35 (5~65) winsize 61
5505 22:51:01.667494 [CA 5] Center 34 (4~65) winsize 62
5506 22:51:01.668028
5507 22:51:01.671089 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5508 22:51:01.671613
5509 22:51:01.674151 [CATrainingPosCal] consider 1 rank data
5510 22:51:01.677745 u2DelayCellTimex100 = 270/100 ps
5511 22:51:01.680492 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5512 22:51:01.684362 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5513 22:51:01.690970 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5514 22:51:01.694244 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5515 22:51:01.697378 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5516 22:51:01.700760 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5517 22:51:01.701183
5518 22:51:01.704312 CA PerBit enable=1, Macro0, CA PI delay=34
5519 22:51:01.704844
5520 22:51:01.707419 [CBTSetCACLKResult] CA Dly = 34
5521 22:51:01.707840 CS Dly: 6 (0~37)
5522 22:51:01.708178 ==
5523 22:51:01.710600 Dram Type= 6, Freq= 0, CH_1, rank 1
5524 22:51:01.717875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 22:51:01.718406 ==
5526 22:51:01.720852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5527 22:51:01.727542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5528 22:51:01.730992 [CA 0] Center 38 (8~68) winsize 61
5529 22:51:01.734269 [CA 1] Center 38 (8~69) winsize 62
5530 22:51:01.737209 [CA 2] Center 36 (6~66) winsize 61
5531 22:51:01.740854 [CA 3] Center 35 (5~65) winsize 61
5532 22:51:01.744230 [CA 4] Center 35 (6~65) winsize 60
5533 22:51:01.747712 [CA 5] Center 35 (5~65) winsize 61
5534 22:51:01.748238
5535 22:51:01.750899 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5536 22:51:01.751427
5537 22:51:01.754128 [CATrainingPosCal] consider 2 rank data
5538 22:51:01.757463 u2DelayCellTimex100 = 270/100 ps
5539 22:51:01.760859 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5540 22:51:01.764685 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5541 22:51:01.771075 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5542 22:51:01.774154 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5543 22:51:01.777576 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5544 22:51:01.780655 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5545 22:51:01.781180
5546 22:51:01.784138 CA PerBit enable=1, Macro0, CA PI delay=35
5547 22:51:01.784660
5548 22:51:01.787636 [CBTSetCACLKResult] CA Dly = 35
5549 22:51:01.788167 CS Dly: 7 (0~39)
5550 22:51:01.788503
5551 22:51:01.790938 ----->DramcWriteLeveling(PI) begin...
5552 22:51:01.794447 ==
5553 22:51:01.797285 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 22:51:01.801211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 22:51:01.801787 ==
5556 22:51:01.804148 Write leveling (Byte 0): 27 => 27
5557 22:51:01.807551 Write leveling (Byte 1): 29 => 29
5558 22:51:01.810765 DramcWriteLeveling(PI) end<-----
5559 22:51:01.811190
5560 22:51:01.811520 ==
5561 22:51:01.813985 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 22:51:01.817284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 22:51:01.817753 ==
5564 22:51:01.820442 [Gating] SW mode calibration
5565 22:51:01.827566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5566 22:51:01.834031 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5567 22:51:01.837460 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 22:51:01.840675 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 22:51:01.844076 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 22:51:01.850615 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 22:51:01.853934 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 22:51:01.856953 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 22:51:01.864437 0 14 24 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 1)
5574 22:51:01.866973 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5575 22:51:01.870861 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 22:51:01.877285 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 22:51:01.880286 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 22:51:01.883748 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 22:51:01.890470 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 22:51:01.893754 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 22:51:01.897460 0 15 24 | B1->B0 | 2929 2929 | 0 1 | (1 1) (0 0)
5582 22:51:01.904079 0 15 28 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
5583 22:51:01.907458 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 22:51:01.910227 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 22:51:01.917238 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 22:51:01.920615 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 22:51:01.923548 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 22:51:01.930288 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5589 22:51:01.933859 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5590 22:51:01.937050 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5591 22:51:01.943931 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 22:51:01.946749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 22:51:01.950330 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 22:51:01.957217 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 22:51:01.960699 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 22:51:01.963875 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 22:51:01.966932 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 22:51:01.973824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 22:51:01.977244 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:51:01.979991 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 22:51:01.986848 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 22:51:01.990203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 22:51:01.993616 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 22:51:02.000611 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 22:51:02.003632 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5606 22:51:02.007053 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 22:51:02.009925 Total UI for P1: 0, mck2ui 16
5608 22:51:02.013344 best dqsien dly found for B0: ( 1, 2, 24)
5609 22:51:02.016685 Total UI for P1: 0, mck2ui 16
5610 22:51:02.020094 best dqsien dly found for B1: ( 1, 2, 24)
5611 22:51:02.023202 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5612 22:51:02.026791 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5613 22:51:02.027359
5614 22:51:02.033588 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5615 22:51:02.037082 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5616 22:51:02.037691 [Gating] SW calibration Done
5617 22:51:02.040474 ==
5618 22:51:02.043617 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 22:51:02.046755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 22:51:02.047229 ==
5621 22:51:02.047597 RX Vref Scan: 0
5622 22:51:02.047942
5623 22:51:02.049901 RX Vref 0 -> 0, step: 1
5624 22:51:02.050367
5625 22:51:02.053415 RX Delay -80 -> 252, step: 8
5626 22:51:02.056671 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5627 22:51:02.060062 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5628 22:51:02.063691 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5629 22:51:02.070111 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5630 22:51:02.073372 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5631 22:51:02.076344 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5632 22:51:02.080105 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5633 22:51:02.083167 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5634 22:51:02.086644 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5635 22:51:02.093473 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5636 22:51:02.096561 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5637 22:51:02.099736 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5638 22:51:02.102980 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5639 22:51:02.106404 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5640 22:51:02.109956 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5641 22:51:02.116915 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5642 22:51:02.117527 ==
5643 22:51:02.119641 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 22:51:02.123158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 22:51:02.123731 ==
5646 22:51:02.124105 DQS Delay:
5647 22:51:02.126719 DQS0 = 0, DQS1 = 0
5648 22:51:02.127284 DQM Delay:
5649 22:51:02.129989 DQM0 = 101, DQM1 = 95
5650 22:51:02.130525 DQ Delay:
5651 22:51:02.133118 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5652 22:51:02.136449 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5653 22:51:02.139549 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5654 22:51:02.143418 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5655 22:51:02.143991
5656 22:51:02.144360
5657 22:51:02.144699 ==
5658 22:51:02.146206 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 22:51:02.153179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 22:51:02.153790 ==
5661 22:51:02.154167
5662 22:51:02.154505
5663 22:51:02.154831 TX Vref Scan disable
5664 22:51:02.155947 == TX Byte 0 ==
5665 22:51:02.159552 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5666 22:51:02.162963 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5667 22:51:02.166611 == TX Byte 1 ==
5668 22:51:02.169331 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5669 22:51:02.172921 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5670 22:51:02.176502 ==
5671 22:51:02.179643 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 22:51:02.182676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 22:51:02.183171 ==
5674 22:51:02.183550
5675 22:51:02.183896
5676 22:51:02.185875 TX Vref Scan disable
5677 22:51:02.186348 == TX Byte 0 ==
5678 22:51:02.193098 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5679 22:51:02.196038 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5680 22:51:02.196617 == TX Byte 1 ==
5681 22:51:02.203035 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5682 22:51:02.206313 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5683 22:51:02.206895
5684 22:51:02.207280 [DATLAT]
5685 22:51:02.209517 Freq=933, CH1 RK0
5686 22:51:02.210022
5687 22:51:02.210437 DATLAT Default: 0xd
5688 22:51:02.212970 0, 0xFFFF, sum = 0
5689 22:51:02.213646 1, 0xFFFF, sum = 0
5690 22:51:02.215972 2, 0xFFFF, sum = 0
5691 22:51:02.216453 3, 0xFFFF, sum = 0
5692 22:51:02.219541 4, 0xFFFF, sum = 0
5693 22:51:02.220038 5, 0xFFFF, sum = 0
5694 22:51:02.222511 6, 0xFFFF, sum = 0
5695 22:51:02.225784 7, 0xFFFF, sum = 0
5696 22:51:02.226266 8, 0xFFFF, sum = 0
5697 22:51:02.229127 9, 0xFFFF, sum = 0
5698 22:51:02.229663 10, 0x0, sum = 1
5699 22:51:02.230048 11, 0x0, sum = 2
5700 22:51:02.232588 12, 0x0, sum = 3
5701 22:51:02.233177 13, 0x0, sum = 4
5702 22:51:02.235761 best_step = 11
5703 22:51:02.236279
5704 22:51:02.236652 ==
5705 22:51:02.239339 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 22:51:02.242984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 22:51:02.243716 ==
5708 22:51:02.245801 RX Vref Scan: 1
5709 22:51:02.246276
5710 22:51:02.246655 RX Vref 0 -> 0, step: 1
5711 22:51:02.247008
5712 22:51:02.249466 RX Delay -53 -> 252, step: 4
5713 22:51:02.250131
5714 22:51:02.252840 Set Vref, RX VrefLevel [Byte0]: 51
5715 22:51:02.256111 [Byte1]: 49
5716 22:51:02.260161
5717 22:51:02.260745 Final RX Vref Byte 0 = 51 to rank0
5718 22:51:02.263110 Final RX Vref Byte 1 = 49 to rank0
5719 22:51:02.266426 Final RX Vref Byte 0 = 51 to rank1
5720 22:51:02.270361 Final RX Vref Byte 1 = 49 to rank1==
5721 22:51:02.273817 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 22:51:02.280107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 22:51:02.280671 ==
5724 22:51:02.281049 DQS Delay:
5725 22:51:02.281427 DQS0 = 0, DQS1 = 0
5726 22:51:02.283150 DQM Delay:
5727 22:51:02.283625 DQM0 = 103, DQM1 = 97
5728 22:51:02.286553 DQ Delay:
5729 22:51:02.290148 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5730 22:51:02.293415 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5731 22:51:02.296631 DQ8 =86, DQ9 =88, DQ10 =100, DQ11 =90
5732 22:51:02.300306 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =104
5733 22:51:02.300782
5734 22:51:02.301155
5735 22:51:02.306685 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e37, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
5736 22:51:02.310254 CH1 RK0: MR19=505, MR18=1E37
5737 22:51:02.316607 CH1_RK0: MR19=0x505, MR18=0x1E37, DQSOSC=404, MR23=63, INC=66, DEC=44
5738 22:51:02.317170
5739 22:51:02.319612 ----->DramcWriteLeveling(PI) begin...
5740 22:51:02.320141 ==
5741 22:51:02.323401 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 22:51:02.326951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 22:51:02.327537 ==
5744 22:51:02.329734 Write leveling (Byte 0): 28 => 28
5745 22:51:02.333552 Write leveling (Byte 1): 28 => 28
5746 22:51:02.336192 DramcWriteLeveling(PI) end<-----
5747 22:51:02.336665
5748 22:51:02.337041 ==
5749 22:51:02.340028 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 22:51:02.346795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 22:51:02.347380 ==
5752 22:51:02.347900 [Gating] SW mode calibration
5753 22:51:02.356661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5754 22:51:02.359772 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5755 22:51:02.362697 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5756 22:51:02.369948 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 22:51:02.372874 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 22:51:02.376026 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 22:51:02.382814 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 22:51:02.386493 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 22:51:02.389294 0 14 24 | B1->B0 | 3030 3333 | 1 1 | (1 0) (1 1)
5762 22:51:02.396315 0 14 28 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
5763 22:51:02.399438 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5764 22:51:02.402550 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 22:51:02.409553 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 22:51:02.412693 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 22:51:02.415768 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 22:51:02.422107 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 22:51:02.425736 0 15 24 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
5770 22:51:02.429273 0 15 28 | B1->B0 | 4141 3837 | 0 1 | (0 0) (0 0)
5771 22:51:02.435797 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 22:51:02.439174 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 22:51:02.442666 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 22:51:02.449343 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 22:51:02.452412 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 22:51:02.455573 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 22:51:02.462098 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 22:51:02.465550 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5779 22:51:02.469093 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 22:51:02.475174 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 22:51:02.479133 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 22:51:02.482234 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 22:51:02.489285 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 22:51:02.492479 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 22:51:02.495349 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 22:51:02.502382 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 22:51:02.505485 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 22:51:02.508967 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 22:51:02.515516 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 22:51:02.519146 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 22:51:02.521925 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 22:51:02.529104 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5793 22:51:02.531851 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5794 22:51:02.535067 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 22:51:02.538701 Total UI for P1: 0, mck2ui 16
5796 22:51:02.541800 best dqsien dly found for B0: ( 1, 2, 22)
5797 22:51:02.545173 Total UI for P1: 0, mck2ui 16
5798 22:51:02.548342 best dqsien dly found for B1: ( 1, 2, 24)
5799 22:51:02.551901 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5800 22:51:02.555266 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5801 22:51:02.555734
5802 22:51:02.558750 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5803 22:51:02.562177 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5804 22:51:02.565061 [Gating] SW calibration Done
5805 22:51:02.565634 ==
5806 22:51:02.568649 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 22:51:02.575301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 22:51:02.575858 ==
5809 22:51:02.576231 RX Vref Scan: 0
5810 22:51:02.576647
5811 22:51:02.578442 RX Vref 0 -> 0, step: 1
5812 22:51:02.578912
5813 22:51:02.581914 RX Delay -80 -> 252, step: 8
5814 22:51:02.585025 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5815 22:51:02.588545 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5816 22:51:02.591802 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5817 22:51:02.595174 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5818 22:51:02.601738 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5819 22:51:02.605437 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5820 22:51:02.608746 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5821 22:51:02.612171 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5822 22:51:02.615461 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5823 22:51:02.621764 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5824 22:51:02.624687 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5825 22:51:02.628348 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5826 22:51:02.631666 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5827 22:51:02.635027 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5828 22:51:02.638076 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5829 22:51:02.644918 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5830 22:51:02.645520 ==
5831 22:51:02.647909 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 22:51:02.651343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 22:51:02.651922 ==
5834 22:51:02.652305 DQS Delay:
5835 22:51:02.654447 DQS0 = 0, DQS1 = 0
5836 22:51:02.655084 DQM Delay:
5837 22:51:02.658693 DQM0 = 102, DQM1 = 95
5838 22:51:02.659232 DQ Delay:
5839 22:51:02.661264 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =103
5840 22:51:02.664706 DQ4 =103, DQ5 =107, DQ6 =107, DQ7 =103
5841 22:51:02.667764 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5842 22:51:02.671131 DQ12 =107, DQ13 =99, DQ14 =99, DQ15 =103
5843 22:51:02.671615
5844 22:51:02.671992
5845 22:51:02.672344 ==
5846 22:51:02.674763 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 22:51:02.681342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 22:51:02.682101 ==
5849 22:51:02.682785
5850 22:51:02.683435
5851 22:51:02.684074 TX Vref Scan disable
5852 22:51:02.684810 == TX Byte 0 ==
5853 22:51:02.687914 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5854 22:51:02.691241 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5855 22:51:02.694589 == TX Byte 1 ==
5856 22:51:02.698389 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 22:51:02.704995 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 22:51:02.705518 ==
5859 22:51:02.708258 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 22:51:02.711365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 22:51:02.712024 ==
5862 22:51:02.712544
5863 22:51:02.712956
5864 22:51:02.715040 TX Vref Scan disable
5865 22:51:02.715531 == TX Byte 0 ==
5866 22:51:02.721746 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5867 22:51:02.724694 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5868 22:51:02.725181 == TX Byte 1 ==
5869 22:51:02.731257 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5870 22:51:02.734506 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5871 22:51:02.734593
5872 22:51:02.734679 [DATLAT]
5873 22:51:02.737567 Freq=933, CH1 RK1
5874 22:51:02.737654
5875 22:51:02.737738 DATLAT Default: 0xb
5876 22:51:02.740863 0, 0xFFFF, sum = 0
5877 22:51:02.740950 1, 0xFFFF, sum = 0
5878 22:51:02.744072 2, 0xFFFF, sum = 0
5879 22:51:02.744159 3, 0xFFFF, sum = 0
5880 22:51:02.747317 4, 0xFFFF, sum = 0
5881 22:51:02.747404 5, 0xFFFF, sum = 0
5882 22:51:02.750697 6, 0xFFFF, sum = 0
5883 22:51:02.750784 7, 0xFFFF, sum = 0
5884 22:51:02.753848 8, 0xFFFF, sum = 0
5885 22:51:02.757449 9, 0xFFFF, sum = 0
5886 22:51:02.757536 10, 0x0, sum = 1
5887 22:51:02.757622 11, 0x0, sum = 2
5888 22:51:02.760892 12, 0x0, sum = 3
5889 22:51:02.761005 13, 0x0, sum = 4
5890 22:51:02.764181 best_step = 11
5891 22:51:02.764267
5892 22:51:02.764350 ==
5893 22:51:02.767495 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 22:51:02.770653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 22:51:02.770739 ==
5896 22:51:02.773899 RX Vref Scan: 0
5897 22:51:02.773985
5898 22:51:02.774069 RX Vref 0 -> 0, step: 1
5899 22:51:02.774149
5900 22:51:02.777142 RX Delay -53 -> 252, step: 4
5901 22:51:02.784666 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5902 22:51:02.787815 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5903 22:51:02.791097 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5904 22:51:02.794547 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5905 22:51:02.797754 iDelay=199, Bit 4, Center 106 (27 ~ 186) 160
5906 22:51:02.804581 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5907 22:51:02.808188 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5908 22:51:02.811521 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5909 22:51:02.814807 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5910 22:51:02.818176 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5911 22:51:02.821179 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5912 22:51:02.828007 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5913 22:51:02.831271 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5914 22:51:02.834606 iDelay=199, Bit 13, Center 102 (19 ~ 186) 168
5915 22:51:02.837833 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5916 22:51:02.841121 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5917 22:51:02.845068 ==
5918 22:51:02.847978 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 22:51:02.851490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 22:51:02.851578 ==
5921 22:51:02.851663 DQS Delay:
5922 22:51:02.854642 DQS0 = 0, DQS1 = 0
5923 22:51:02.854743 DQM Delay:
5924 22:51:02.857909 DQM0 = 105, DQM1 = 97
5925 22:51:02.857998 DQ Delay:
5926 22:51:02.861582 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5927 22:51:02.864414 DQ4 =106, DQ5 =116, DQ6 =114, DQ7 =102
5928 22:51:02.867687 DQ8 =84, DQ9 =88, DQ10 =100, DQ11 =92
5929 22:51:02.871147 DQ12 =104, DQ13 =102, DQ14 =104, DQ15 =106
5930 22:51:02.871246
5931 22:51:02.871315
5932 22:51:02.881003 [DQSOSCAuto] RK1, (LSB)MR18= 0x22ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5933 22:51:02.881120 CH1 RK1: MR19=504, MR18=22FF
5934 22:51:02.887464 CH1_RK1: MR19=0x504, MR18=0x22FF, DQSOSC=411, MR23=63, INC=64, DEC=42
5935 22:51:02.891112 [RxdqsGatingPostProcess] freq 933
5936 22:51:02.897685 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5937 22:51:02.900848 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 22:51:02.904600 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 22:51:02.907672 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 22:51:02.911238 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 22:51:02.914633 best DQS0 dly(2T, 0.5T) = (0, 10)
5942 22:51:02.914709 best DQS1 dly(2T, 0.5T) = (0, 10)
5943 22:51:02.917519 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5944 22:51:02.921014 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5945 22:51:02.924110 Pre-setting of DQS Precalculation
5946 22:51:02.930773 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5947 22:51:02.937606 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5948 22:51:02.944327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5949 22:51:02.944426
5950 22:51:02.944499
5951 22:51:02.947460 [Calibration Summary] 1866 Mbps
5952 22:51:02.950531 CH 0, Rank 0
5953 22:51:02.950606 SW Impedance : PASS
5954 22:51:02.953862 DUTY Scan : NO K
5955 22:51:02.957241 ZQ Calibration : PASS
5956 22:51:02.957373 Jitter Meter : NO K
5957 22:51:02.960707 CBT Training : PASS
5958 22:51:02.960783 Write leveling : PASS
5959 22:51:02.963956 RX DQS gating : PASS
5960 22:51:02.967071 RX DQ/DQS(RDDQC) : PASS
5961 22:51:02.967175 TX DQ/DQS : PASS
5962 22:51:02.970679 RX DATLAT : PASS
5963 22:51:02.973769 RX DQ/DQS(Engine): PASS
5964 22:51:02.973852 TX OE : NO K
5965 22:51:02.977415 All Pass.
5966 22:51:02.977491
5967 22:51:02.977554 CH 0, Rank 1
5968 22:51:02.980736 SW Impedance : PASS
5969 22:51:02.980836 DUTY Scan : NO K
5970 22:51:02.983482 ZQ Calibration : PASS
5971 22:51:02.987167 Jitter Meter : NO K
5972 22:51:02.987281 CBT Training : PASS
5973 22:51:02.990316 Write leveling : PASS
5974 22:51:02.993713 RX DQS gating : PASS
5975 22:51:02.993791 RX DQ/DQS(RDDQC) : PASS
5976 22:51:02.996868 TX DQ/DQS : PASS
5977 22:51:03.000442 RX DATLAT : PASS
5978 22:51:03.000521 RX DQ/DQS(Engine): PASS
5979 22:51:03.003698 TX OE : NO K
5980 22:51:03.003801 All Pass.
5981 22:51:03.003892
5982 22:51:03.007108 CH 1, Rank 0
5983 22:51:03.007207 SW Impedance : PASS
5984 22:51:03.010170 DUTY Scan : NO K
5985 22:51:03.013466 ZQ Calibration : PASS
5986 22:51:03.013540 Jitter Meter : NO K
5987 22:51:03.017288 CBT Training : PASS
5988 22:51:03.017402 Write leveling : PASS
5989 22:51:03.020508 RX DQS gating : PASS
5990 22:51:03.023940 RX DQ/DQS(RDDQC) : PASS
5991 22:51:03.024018 TX DQ/DQS : PASS
5992 22:51:03.026789 RX DATLAT : PASS
5993 22:51:03.030251 RX DQ/DQS(Engine): PASS
5994 22:51:03.030330 TX OE : NO K
5995 22:51:03.033574 All Pass.
5996 22:51:03.033649
5997 22:51:03.033716 CH 1, Rank 1
5998 22:51:03.036748 SW Impedance : PASS
5999 22:51:03.036821 DUTY Scan : NO K
6000 22:51:03.040287 ZQ Calibration : PASS
6001 22:51:03.043667 Jitter Meter : NO K
6002 22:51:03.043744 CBT Training : PASS
6003 22:51:03.046738 Write leveling : PASS
6004 22:51:03.050116 RX DQS gating : PASS
6005 22:51:03.050194 RX DQ/DQS(RDDQC) : PASS
6006 22:51:03.053580 TX DQ/DQS : PASS
6007 22:51:03.056937 RX DATLAT : PASS
6008 22:51:03.057038 RX DQ/DQS(Engine): PASS
6009 22:51:03.060059 TX OE : NO K
6010 22:51:03.060162 All Pass.
6011 22:51:03.060255
6012 22:51:03.063508 DramC Write-DBI off
6013 22:51:03.067166 PER_BANK_REFRESH: Hybrid Mode
6014 22:51:03.067246 TX_TRACKING: ON
6015 22:51:03.076844 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6016 22:51:03.079977 [FAST_K] Save calibration result to emmc
6017 22:51:03.083145 dramc_set_vcore_voltage set vcore to 650000
6018 22:51:03.086467 Read voltage for 400, 6
6019 22:51:03.086554 Vio18 = 0
6020 22:51:03.086620 Vcore = 650000
6021 22:51:03.089991 Vdram = 0
6022 22:51:03.090063 Vddq = 0
6023 22:51:03.090124 Vmddr = 0
6024 22:51:03.096534 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6025 22:51:03.099838 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6026 22:51:03.103344 MEM_TYPE=3, freq_sel=20
6027 22:51:03.106384 sv_algorithm_assistance_LP4_800
6028 22:51:03.110146 ============ PULL DRAM RESETB DOWN ============
6029 22:51:03.113495 ========== PULL DRAM RESETB DOWN end =========
6030 22:51:03.120002 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6031 22:51:03.123353 ===================================
6032 22:51:03.123439 LPDDR4 DRAM CONFIGURATION
6033 22:51:03.126343 ===================================
6034 22:51:03.129704 EX_ROW_EN[0] = 0x0
6035 22:51:03.132995 EX_ROW_EN[1] = 0x0
6036 22:51:03.133069 LP4Y_EN = 0x0
6037 22:51:03.136413 WORK_FSP = 0x0
6038 22:51:03.136497 WL = 0x2
6039 22:51:03.139797 RL = 0x2
6040 22:51:03.139880 BL = 0x2
6041 22:51:03.143138 RPST = 0x0
6042 22:51:03.143225 RD_PRE = 0x0
6043 22:51:03.146427 WR_PRE = 0x1
6044 22:51:03.146502 WR_PST = 0x0
6045 22:51:03.149753 DBI_WR = 0x0
6046 22:51:03.149848 DBI_RD = 0x0
6047 22:51:03.153204 OTF = 0x1
6048 22:51:03.156800 ===================================
6049 22:51:03.159804 ===================================
6050 22:51:03.159908 ANA top config
6051 22:51:03.163267 ===================================
6052 22:51:03.166789 DLL_ASYNC_EN = 0
6053 22:51:03.169750 ALL_SLAVE_EN = 1
6054 22:51:03.169824 NEW_RANK_MODE = 1
6055 22:51:03.173257 DLL_IDLE_MODE = 1
6056 22:51:03.176714 LP45_APHY_COMB_EN = 1
6057 22:51:03.180117 TX_ODT_DIS = 1
6058 22:51:03.180248 NEW_8X_MODE = 1
6059 22:51:03.183168 ===================================
6060 22:51:03.186466 ===================================
6061 22:51:03.189703 data_rate = 800
6062 22:51:03.193129 CKR = 1
6063 22:51:03.196654 DQ_P2S_RATIO = 4
6064 22:51:03.199662 ===================================
6065 22:51:03.203444 CA_P2S_RATIO = 4
6066 22:51:03.206433 DQ_CA_OPEN = 0
6067 22:51:03.209799 DQ_SEMI_OPEN = 1
6068 22:51:03.209882 CA_SEMI_OPEN = 1
6069 22:51:03.212996 CA_FULL_RATE = 0
6070 22:51:03.216524 DQ_CKDIV4_EN = 0
6071 22:51:03.219413 CA_CKDIV4_EN = 1
6072 22:51:03.223193 CA_PREDIV_EN = 0
6073 22:51:03.226088 PH8_DLY = 0
6074 22:51:03.226200 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6075 22:51:03.229632 DQ_AAMCK_DIV = 0
6076 22:51:03.232911 CA_AAMCK_DIV = 0
6077 22:51:03.236052 CA_ADMCK_DIV = 4
6078 22:51:03.239365 DQ_TRACK_CA_EN = 0
6079 22:51:03.242919 CA_PICK = 800
6080 22:51:03.243003 CA_MCKIO = 400
6081 22:51:03.245940 MCKIO_SEMI = 400
6082 22:51:03.249411 PLL_FREQ = 3016
6083 22:51:03.252987 DQ_UI_PI_RATIO = 32
6084 22:51:03.256055 CA_UI_PI_RATIO = 32
6085 22:51:03.259351 ===================================
6086 22:51:03.262518 ===================================
6087 22:51:03.266298 memory_type:LPDDR4
6088 22:51:03.266397 GP_NUM : 10
6089 22:51:03.269486 SRAM_EN : 1
6090 22:51:03.272704 MD32_EN : 0
6091 22:51:03.272787 ===================================
6092 22:51:03.276264 [ANA_INIT] >>>>>>>>>>>>>>
6093 22:51:03.279593 <<<<<< [CONFIGURE PHASE]: ANA_TX
6094 22:51:03.283205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6095 22:51:03.286328 ===================================
6096 22:51:03.289347 data_rate = 800,PCW = 0X7400
6097 22:51:03.292724 ===================================
6098 22:51:03.295910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6099 22:51:03.302879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 22:51:03.312829 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 22:51:03.315839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6102 22:51:03.319565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6103 22:51:03.322796 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6104 22:51:03.325720 [ANA_INIT] flow start
6105 22:51:03.329423 [ANA_INIT] PLL >>>>>>>>
6106 22:51:03.329507 [ANA_INIT] PLL <<<<<<<<
6107 22:51:03.332421 [ANA_INIT] MIDPI >>>>>>>>
6108 22:51:03.335981 [ANA_INIT] MIDPI <<<<<<<<
6109 22:51:03.339270 [ANA_INIT] DLL >>>>>>>>
6110 22:51:03.339354 [ANA_INIT] flow end
6111 22:51:03.342531 ============ LP4 DIFF to SE enter ============
6112 22:51:03.349151 ============ LP4 DIFF to SE exit ============
6113 22:51:03.349236 [ANA_INIT] <<<<<<<<<<<<<
6114 22:51:03.352597 [Flow] Enable top DCM control >>>>>
6115 22:51:03.356036 [Flow] Enable top DCM control <<<<<
6116 22:51:03.359174 Enable DLL master slave shuffle
6117 22:51:03.365618 ==============================================================
6118 22:51:03.365703 Gating Mode config
6119 22:51:03.372481 ==============================================================
6120 22:51:03.375628 Config description:
6121 22:51:03.385961 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6122 22:51:03.392531 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6123 22:51:03.395709 SELPH_MODE 0: By rank 1: By Phase
6124 22:51:03.402594 ==============================================================
6125 22:51:03.405858 GAT_TRACK_EN = 0
6126 22:51:03.405942 RX_GATING_MODE = 2
6127 22:51:03.409242 RX_GATING_TRACK_MODE = 2
6128 22:51:03.412489 SELPH_MODE = 1
6129 22:51:03.415755 PICG_EARLY_EN = 1
6130 22:51:03.419181 VALID_LAT_VALUE = 1
6131 22:51:03.425702 ==============================================================
6132 22:51:03.429290 Enter into Gating configuration >>>>
6133 22:51:03.432480 Exit from Gating configuration <<<<
6134 22:51:03.436005 Enter into DVFS_PRE_config >>>>>
6135 22:51:03.445857 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6136 22:51:03.448856 Exit from DVFS_PRE_config <<<<<
6137 22:51:03.452255 Enter into PICG configuration >>>>
6138 22:51:03.455553 Exit from PICG configuration <<<<
6139 22:51:03.458943 [RX_INPUT] configuration >>>>>
6140 22:51:03.459026 [RX_INPUT] configuration <<<<<
6141 22:51:03.465930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6142 22:51:03.472283 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6143 22:51:03.478843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 22:51:03.482111 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 22:51:03.488794 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 22:51:03.495398 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 22:51:03.498837 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6148 22:51:03.502419 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6149 22:51:03.508957 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6150 22:51:03.512068 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6151 22:51:03.515184 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6152 22:51:03.521833 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6153 22:51:03.525279 ===================================
6154 22:51:03.525384 LPDDR4 DRAM CONFIGURATION
6155 22:51:03.528320 ===================================
6156 22:51:03.531887 EX_ROW_EN[0] = 0x0
6157 22:51:03.535181 EX_ROW_EN[1] = 0x0
6158 22:51:03.535292 LP4Y_EN = 0x0
6159 22:51:03.538272 WORK_FSP = 0x0
6160 22:51:03.538355 WL = 0x2
6161 22:51:03.542064 RL = 0x2
6162 22:51:03.542147 BL = 0x2
6163 22:51:03.544822 RPST = 0x0
6164 22:51:03.544905 RD_PRE = 0x0
6165 22:51:03.548195 WR_PRE = 0x1
6166 22:51:03.548278 WR_PST = 0x0
6167 22:51:03.552067 DBI_WR = 0x0
6168 22:51:03.552150 DBI_RD = 0x0
6169 22:51:03.555003 OTF = 0x1
6170 22:51:03.558392 ===================================
6171 22:51:03.561551 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6172 22:51:03.565079 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6173 22:51:03.571649 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 22:51:03.574938 ===================================
6175 22:51:03.575022 LPDDR4 DRAM CONFIGURATION
6176 22:51:03.578265 ===================================
6177 22:51:03.581464 EX_ROW_EN[0] = 0x10
6178 22:51:03.581552 EX_ROW_EN[1] = 0x0
6179 22:51:03.584815 LP4Y_EN = 0x0
6180 22:51:03.588354 WORK_FSP = 0x0
6181 22:51:03.588437 WL = 0x2
6182 22:51:03.591671 RL = 0x2
6183 22:51:03.591754 BL = 0x2
6184 22:51:03.595066 RPST = 0x0
6185 22:51:03.595180 RD_PRE = 0x0
6186 22:51:03.598347 WR_PRE = 0x1
6187 22:51:03.598431 WR_PST = 0x0
6188 22:51:03.601448 DBI_WR = 0x0
6189 22:51:03.601525 DBI_RD = 0x0
6190 22:51:03.605204 OTF = 0x1
6191 22:51:03.608183 ===================================
6192 22:51:03.611376 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6193 22:51:03.617062 nWR fixed to 30
6194 22:51:03.620643 [ModeRegInit_LP4] CH0 RK0
6195 22:51:03.620726 [ModeRegInit_LP4] CH0 RK1
6196 22:51:03.623970 [ModeRegInit_LP4] CH1 RK0
6197 22:51:03.626814 [ModeRegInit_LP4] CH1 RK1
6198 22:51:03.626908 match AC timing 19
6199 22:51:03.633547 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6200 22:51:03.636975 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6201 22:51:03.640220 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6202 22:51:03.646726 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6203 22:51:03.650053 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6204 22:51:03.650138 ==
6205 22:51:03.653630 Dram Type= 6, Freq= 0, CH_0, rank 0
6206 22:51:03.656807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6207 22:51:03.656911 ==
6208 22:51:03.663674 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6209 22:51:03.670373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6210 22:51:03.673367 [CA 0] Center 36 (8~64) winsize 57
6211 22:51:03.676827 [CA 1] Center 36 (8~64) winsize 57
6212 22:51:03.680252 [CA 2] Center 36 (8~64) winsize 57
6213 22:51:03.680348 [CA 3] Center 36 (8~64) winsize 57
6214 22:51:03.683450 [CA 4] Center 36 (8~64) winsize 57
6215 22:51:03.686966 [CA 5] Center 36 (8~64) winsize 57
6216 22:51:03.687079
6217 22:51:03.693436 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6218 22:51:03.693516
6219 22:51:03.696950 [CATrainingPosCal] consider 1 rank data
6220 22:51:03.700159 u2DelayCellTimex100 = 270/100 ps
6221 22:51:03.703283 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 22:51:03.706625 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 22:51:03.710094 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 22:51:03.713555 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 22:51:03.716776 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 22:51:03.720108 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 22:51:03.720205
6228 22:51:03.723262 CA PerBit enable=1, Macro0, CA PI delay=36
6229 22:51:03.723333
6230 22:51:03.726720 [CBTSetCACLKResult] CA Dly = 36
6231 22:51:03.729812 CS Dly: 1 (0~32)
6232 22:51:03.729884 ==
6233 22:51:03.733186 Dram Type= 6, Freq= 0, CH_0, rank 1
6234 22:51:03.736822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 22:51:03.736920 ==
6236 22:51:03.743036 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 22:51:03.746544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6238 22:51:03.750111 [CA 0] Center 36 (8~64) winsize 57
6239 22:51:03.753184 [CA 1] Center 36 (8~64) winsize 57
6240 22:51:03.756289 [CA 2] Center 36 (8~64) winsize 57
6241 22:51:03.759682 [CA 3] Center 36 (8~64) winsize 57
6242 22:51:03.763436 [CA 4] Center 36 (8~64) winsize 57
6243 22:51:03.766346 [CA 5] Center 36 (8~64) winsize 57
6244 22:51:03.766416
6245 22:51:03.769716 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6246 22:51:03.769789
6247 22:51:03.772957 [CATrainingPosCal] consider 2 rank data
6248 22:51:03.776484 u2DelayCellTimex100 = 270/100 ps
6249 22:51:03.779803 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:51:03.786203 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 22:51:03.789797 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 22:51:03.792829 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 22:51:03.796063 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 22:51:03.799547 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 22:51:03.799644
6256 22:51:03.802580 CA PerBit enable=1, Macro0, CA PI delay=36
6257 22:51:03.802676
6258 22:51:03.806232 [CBTSetCACLKResult] CA Dly = 36
6259 22:51:03.806303 CS Dly: 1 (0~32)
6260 22:51:03.806364
6261 22:51:03.812873 ----->DramcWriteLeveling(PI) begin...
6262 22:51:03.812979 ==
6263 22:51:03.816035 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 22:51:03.819545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 22:51:03.819642 ==
6266 22:51:03.822784 Write leveling (Byte 0): 40 => 8
6267 22:51:03.826385 Write leveling (Byte 1): 32 => 0
6268 22:51:03.829510 DramcWriteLeveling(PI) end<-----
6269 22:51:03.829606
6270 22:51:03.829694 ==
6271 22:51:03.832768 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 22:51:03.835919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 22:51:03.836002 ==
6274 22:51:03.839366 [Gating] SW mode calibration
6275 22:51:03.845914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6276 22:51:03.852431 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6277 22:51:03.856034 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 22:51:03.859267 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 22:51:03.862682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 22:51:03.869074 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 22:51:03.872500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 22:51:03.879151 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 22:51:03.882293 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 22:51:03.885582 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 22:51:03.888857 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 22:51:03.891986 Total UI for P1: 0, mck2ui 16
6287 22:51:03.895432 best dqsien dly found for B0: ( 0, 14, 24)
6288 22:51:03.899227 Total UI for P1: 0, mck2ui 16
6289 22:51:03.902249 best dqsien dly found for B1: ( 0, 14, 24)
6290 22:51:03.905602 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6291 22:51:03.912079 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6292 22:51:03.912187
6293 22:51:03.915443 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 22:51:03.918894 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 22:51:03.922071 [Gating] SW calibration Done
6296 22:51:03.922164 ==
6297 22:51:03.925260 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 22:51:03.928484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 22:51:03.928588 ==
6300 22:51:03.931978 RX Vref Scan: 0
6301 22:51:03.932079
6302 22:51:03.932168 RX Vref 0 -> 0, step: 1
6303 22:51:03.932264
6304 22:51:03.935313 RX Delay -410 -> 252, step: 16
6305 22:51:03.938758 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6306 22:51:03.945387 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6307 22:51:03.948480 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6308 22:51:03.951874 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6309 22:51:03.955191 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6310 22:51:03.961506 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6311 22:51:03.964902 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6312 22:51:03.968048 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6313 22:51:03.971452 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6314 22:51:03.978307 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6315 22:51:03.981348 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6316 22:51:03.985059 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6317 22:51:03.991559 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6318 22:51:03.994666 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6319 22:51:03.997998 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6320 22:51:04.001554 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6321 22:51:04.001658 ==
6322 22:51:04.004955 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 22:51:04.011258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 22:51:04.011335 ==
6325 22:51:04.011398 DQS Delay:
6326 22:51:04.015148 DQS0 = 27, DQS1 = 43
6327 22:51:04.015220 DQM Delay:
6328 22:51:04.018071 DQM0 = 11, DQM1 = 13
6329 22:51:04.018145 DQ Delay:
6330 22:51:04.021333 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6331 22:51:04.024891 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6332 22:51:04.024962 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6333 22:51:04.031259 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6334 22:51:04.031333
6335 22:51:04.031395
6336 22:51:04.031453 ==
6337 22:51:04.034755 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 22:51:04.038016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 22:51:04.038090 ==
6340 22:51:04.038151
6341 22:51:04.038208
6342 22:51:04.041286 TX Vref Scan disable
6343 22:51:04.041385 == TX Byte 0 ==
6344 22:51:04.044640 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 22:51:04.051537 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 22:51:04.051628 == TX Byte 1 ==
6347 22:51:04.054546 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6348 22:51:04.061166 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6349 22:51:04.061242 ==
6350 22:51:04.064746 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 22:51:04.067801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 22:51:04.067874 ==
6353 22:51:04.067935
6354 22:51:04.067995
6355 22:51:04.071215 TX Vref Scan disable
6356 22:51:04.071284 == TX Byte 0 ==
6357 22:51:04.077919 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 22:51:04.081402 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 22:51:04.081474 == TX Byte 1 ==
6360 22:51:04.088209 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6361 22:51:04.091301 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6362 22:51:04.091377
6363 22:51:04.091457 [DATLAT]
6364 22:51:04.094713 Freq=400, CH0 RK0
6365 22:51:04.094790
6366 22:51:04.094869 DATLAT Default: 0xf
6367 22:51:04.097992 0, 0xFFFF, sum = 0
6368 22:51:04.098068 1, 0xFFFF, sum = 0
6369 22:51:04.101195 2, 0xFFFF, sum = 0
6370 22:51:04.101304 3, 0xFFFF, sum = 0
6371 22:51:04.104490 4, 0xFFFF, sum = 0
6372 22:51:04.104569 5, 0xFFFF, sum = 0
6373 22:51:04.108194 6, 0xFFFF, sum = 0
6374 22:51:04.108298 7, 0xFFFF, sum = 0
6375 22:51:04.111524 8, 0xFFFF, sum = 0
6376 22:51:04.111601 9, 0xFFFF, sum = 0
6377 22:51:04.114626 10, 0xFFFF, sum = 0
6378 22:51:04.114725 11, 0xFFFF, sum = 0
6379 22:51:04.118197 12, 0xFFFF, sum = 0
6380 22:51:04.118278 13, 0x0, sum = 1
6381 22:51:04.121229 14, 0x0, sum = 2
6382 22:51:04.121341 15, 0x0, sum = 3
6383 22:51:04.124877 16, 0x0, sum = 4
6384 22:51:04.124956 best_step = 14
6385 22:51:04.125039
6386 22:51:04.125115 ==
6387 22:51:04.127817 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 22:51:04.134728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 22:51:04.134809 ==
6390 22:51:04.134890 RX Vref Scan: 1
6391 22:51:04.134966
6392 22:51:04.138148 RX Vref 0 -> 0, step: 1
6393 22:51:04.138225
6394 22:51:04.141045 RX Delay -327 -> 252, step: 8
6395 22:51:04.141149
6396 22:51:04.144675 Set Vref, RX VrefLevel [Byte0]: 57
6397 22:51:04.148126 [Byte1]: 49
6398 22:51:04.148202
6399 22:51:04.151338 Final RX Vref Byte 0 = 57 to rank0
6400 22:51:04.154633 Final RX Vref Byte 1 = 49 to rank0
6401 22:51:04.157837 Final RX Vref Byte 0 = 57 to rank1
6402 22:51:04.161036 Final RX Vref Byte 1 = 49 to rank1==
6403 22:51:04.164520 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 22:51:04.167879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 22:51:04.171203 ==
6406 22:51:04.171282 DQS Delay:
6407 22:51:04.171360 DQS0 = 28, DQS1 = 48
6408 22:51:04.174649 DQM Delay:
6409 22:51:04.174721 DQM0 = 11, DQM1 = 15
6410 22:51:04.178081 DQ Delay:
6411 22:51:04.178153 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6412 22:51:04.181497 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6413 22:51:04.184942 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6414 22:51:04.188107 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6415 22:51:04.188193
6416 22:51:04.188260
6417 22:51:04.197941 [DQSOSCAuto] RK0, (LSB)MR18= 0xb7ad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6418 22:51:04.201236 CH0 RK0: MR19=C0C, MR18=B7AD
6419 22:51:04.208051 CH0_RK0: MR19=0xC0C, MR18=0xB7AD, DQSOSC=387, MR23=63, INC=394, DEC=262
6420 22:51:04.208135 ==
6421 22:51:04.211311 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 22:51:04.214368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 22:51:04.214459 ==
6424 22:51:04.218144 [Gating] SW mode calibration
6425 22:51:04.224601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6426 22:51:04.227822 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6427 22:51:04.234418 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 22:51:04.237907 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 22:51:04.241100 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 22:51:04.247695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 22:51:04.251029 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 22:51:04.254438 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 22:51:04.260909 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 22:51:04.264505 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 22:51:04.267880 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 22:51:04.271117 Total UI for P1: 0, mck2ui 16
6437 22:51:04.274115 best dqsien dly found for B0: ( 0, 14, 24)
6438 22:51:04.277601 Total UI for P1: 0, mck2ui 16
6439 22:51:04.280912 best dqsien dly found for B1: ( 0, 14, 24)
6440 22:51:04.284263 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6441 22:51:04.287422 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6442 22:51:04.287507
6443 22:51:04.294502 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 22:51:04.297541 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 22:51:04.300792 [Gating] SW calibration Done
6446 22:51:04.300876 ==
6447 22:51:04.304506 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 22:51:04.307625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 22:51:04.307708 ==
6450 22:51:04.307774 RX Vref Scan: 0
6451 22:51:04.307835
6452 22:51:04.311309 RX Vref 0 -> 0, step: 1
6453 22:51:04.311393
6454 22:51:04.314249 RX Delay -410 -> 252, step: 16
6455 22:51:04.317454 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6456 22:51:04.324233 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6457 22:51:04.327559 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6458 22:51:04.331061 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6459 22:51:04.334407 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6460 22:51:04.337495 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6461 22:51:04.344305 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6462 22:51:04.347550 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6463 22:51:04.350988 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6464 22:51:04.354459 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6465 22:51:04.361104 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6466 22:51:04.364474 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6467 22:51:04.367779 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6468 22:51:04.371159 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6469 22:51:04.377643 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6470 22:51:04.380997 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6471 22:51:04.381081 ==
6472 22:51:04.384007 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 22:51:04.387344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 22:51:04.387427 ==
6475 22:51:04.390664 DQS Delay:
6476 22:51:04.390747 DQS0 = 27, DQS1 = 43
6477 22:51:04.393882 DQM Delay:
6478 22:51:04.393965 DQM0 = 10, DQM1 = 15
6479 22:51:04.397168 DQ Delay:
6480 22:51:04.397250 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6481 22:51:04.400759 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6482 22:51:04.403818 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6483 22:51:04.407121 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6484 22:51:04.407205
6485 22:51:04.407271
6486 22:51:04.407331 ==
6487 22:51:04.410645 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 22:51:04.417146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 22:51:04.417230 ==
6490 22:51:04.417303
6491 22:51:04.417399
6492 22:51:04.417458 TX Vref Scan disable
6493 22:51:04.420233 == TX Byte 0 ==
6494 22:51:04.423782 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6495 22:51:04.427179 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6496 22:51:04.430838 == TX Byte 1 ==
6497 22:51:04.433508 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6498 22:51:04.437241 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6499 22:51:04.437319 ==
6500 22:51:04.440178 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 22:51:04.447033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 22:51:04.447116 ==
6503 22:51:04.447186
6504 22:51:04.447248
6505 22:51:04.447306 TX Vref Scan disable
6506 22:51:04.450027 == TX Byte 0 ==
6507 22:51:04.453629 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6508 22:51:04.456935 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6509 22:51:04.460390 == TX Byte 1 ==
6510 22:51:04.463821 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6511 22:51:04.467067 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6512 22:51:04.467140
6513 22:51:04.469947 [DATLAT]
6514 22:51:04.470052 Freq=400, CH0 RK1
6515 22:51:04.470123
6516 22:51:04.473357 DATLAT Default: 0xe
6517 22:51:04.473426 0, 0xFFFF, sum = 0
6518 22:51:04.476671 1, 0xFFFF, sum = 0
6519 22:51:04.476739 2, 0xFFFF, sum = 0
6520 22:51:04.480272 3, 0xFFFF, sum = 0
6521 22:51:04.480341 4, 0xFFFF, sum = 0
6522 22:51:04.483275 5, 0xFFFF, sum = 0
6523 22:51:04.483343 6, 0xFFFF, sum = 0
6524 22:51:04.486620 7, 0xFFFF, sum = 0
6525 22:51:04.486720 8, 0xFFFF, sum = 0
6526 22:51:04.490073 9, 0xFFFF, sum = 0
6527 22:51:04.493237 10, 0xFFFF, sum = 0
6528 22:51:04.493367 11, 0xFFFF, sum = 0
6529 22:51:04.496683 12, 0xFFFF, sum = 0
6530 22:51:04.496751 13, 0x0, sum = 1
6531 22:51:04.500259 14, 0x0, sum = 2
6532 22:51:04.500327 15, 0x0, sum = 3
6533 22:51:04.503371 16, 0x0, sum = 4
6534 22:51:04.503438 best_step = 14
6535 22:51:04.503497
6536 22:51:04.503554 ==
6537 22:51:04.506959 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 22:51:04.509982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 22:51:04.510054 ==
6540 22:51:04.513157 RX Vref Scan: 0
6541 22:51:04.513223
6542 22:51:04.516401 RX Vref 0 -> 0, step: 1
6543 22:51:04.516467
6544 22:51:04.516526 RX Delay -327 -> 252, step: 8
6545 22:51:04.524953 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6546 22:51:04.528268 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6547 22:51:04.531573 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6548 22:51:04.538428 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6549 22:51:04.541820 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6550 22:51:04.544908 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6551 22:51:04.548174 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6552 22:51:04.551714 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6553 22:51:04.558112 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6554 22:51:04.561540 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6555 22:51:04.564998 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6556 22:51:04.571702 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6557 22:51:04.574840 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6558 22:51:04.577993 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6559 22:51:04.581477 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6560 22:51:04.588298 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6561 22:51:04.588380 ==
6562 22:51:04.591767 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 22:51:04.594598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 22:51:04.594670 ==
6565 22:51:04.594731 DQS Delay:
6566 22:51:04.598299 DQS0 = 28, DQS1 = 40
6567 22:51:04.598368 DQM Delay:
6568 22:51:04.601655 DQM0 = 10, DQM1 = 11
6569 22:51:04.601724 DQ Delay:
6570 22:51:04.604756 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6571 22:51:04.608133 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6572 22:51:04.611238 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6573 22:51:04.614524 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6574 22:51:04.614606
6575 22:51:04.614671
6576 22:51:04.621406 [DQSOSCAuto] RK1, (LSB)MR18= 0xc273, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 385 ps
6577 22:51:04.624655 CH0 RK1: MR19=C0C, MR18=C273
6578 22:51:04.630993 CH0_RK1: MR19=0xC0C, MR18=0xC273, DQSOSC=385, MR23=63, INC=398, DEC=265
6579 22:51:04.634510 [RxdqsGatingPostProcess] freq 400
6580 22:51:04.640999 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6581 22:51:04.644554 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 22:51:04.644629 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 22:51:04.647887 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 22:51:04.651726 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 22:51:04.655126 best DQS0 dly(2T, 0.5T) = (0, 10)
6586 22:51:04.658168 best DQS1 dly(2T, 0.5T) = (0, 10)
6587 22:51:04.661180 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6588 22:51:04.664575 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6589 22:51:04.668229 Pre-setting of DQS Precalculation
6590 22:51:04.671468 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6591 22:51:04.674830 ==
6592 22:51:04.678371 Dram Type= 6, Freq= 0, CH_1, rank 0
6593 22:51:04.681464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 22:51:04.681543 ==
6595 22:51:04.684867 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6596 22:51:04.691379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6597 22:51:04.694835 [CA 0] Center 36 (8~64) winsize 57
6598 22:51:04.697952 [CA 1] Center 36 (8~64) winsize 57
6599 22:51:04.701417 [CA 2] Center 36 (8~64) winsize 57
6600 22:51:04.704676 [CA 3] Center 36 (8~64) winsize 57
6601 22:51:04.708161 [CA 4] Center 36 (8~64) winsize 57
6602 22:51:04.711089 [CA 5] Center 36 (8~64) winsize 57
6603 22:51:04.711164
6604 22:51:04.714574 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6605 22:51:04.714648
6606 22:51:04.718071 [CATrainingPosCal] consider 1 rank data
6607 22:51:04.721535 u2DelayCellTimex100 = 270/100 ps
6608 22:51:04.724457 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 22:51:04.727900 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 22:51:04.731206 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 22:51:04.734767 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 22:51:04.741426 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 22:51:04.744734 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 22:51:04.744807
6615 22:51:04.747911 CA PerBit enable=1, Macro0, CA PI delay=36
6616 22:51:04.747983
6617 22:51:04.751377 [CBTSetCACLKResult] CA Dly = 36
6618 22:51:04.751449 CS Dly: 1 (0~32)
6619 22:51:04.751508 ==
6620 22:51:04.754581 Dram Type= 6, Freq= 0, CH_1, rank 1
6621 22:51:04.758029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 22:51:04.761264 ==
6623 22:51:04.764502 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 22:51:04.771307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6625 22:51:04.774919 [CA 0] Center 36 (8~64) winsize 57
6626 22:51:04.777683 [CA 1] Center 36 (8~64) winsize 57
6627 22:51:04.781087 [CA 2] Center 36 (8~64) winsize 57
6628 22:51:04.784323 [CA 3] Center 36 (8~64) winsize 57
6629 22:51:04.788122 [CA 4] Center 36 (8~64) winsize 57
6630 22:51:04.790998 [CA 5] Center 36 (8~64) winsize 57
6631 22:51:04.791072
6632 22:51:04.794378 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6633 22:51:04.794450
6634 22:51:04.797697 [CATrainingPosCal] consider 2 rank data
6635 22:51:04.801397 u2DelayCellTimex100 = 270/100 ps
6636 22:51:04.804452 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:51:04.807878 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 22:51:04.811050 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 22:51:04.814294 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 22:51:04.817777 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 22:51:04.821100 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 22:51:04.821201
6643 22:51:04.824499 CA PerBit enable=1, Macro0, CA PI delay=36
6644 22:51:04.824571
6645 22:51:04.827802 [CBTSetCACLKResult] CA Dly = 36
6646 22:51:04.831274 CS Dly: 1 (0~32)
6647 22:51:04.831381
6648 22:51:04.834492 ----->DramcWriteLeveling(PI) begin...
6649 22:51:04.834566 ==
6650 22:51:04.837925 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 22:51:04.840948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 22:51:04.841021 ==
6653 22:51:04.844123 Write leveling (Byte 0): 40 => 8
6654 22:51:04.847972 Write leveling (Byte 1): 32 => 0
6655 22:51:04.851112 DramcWriteLeveling(PI) end<-----
6656 22:51:04.851183
6657 22:51:04.851244 ==
6658 22:51:04.854729 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 22:51:04.857496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 22:51:04.857570 ==
6661 22:51:04.860952 [Gating] SW mode calibration
6662 22:51:04.867648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6663 22:51:04.874572 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6664 22:51:04.877573 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 22:51:04.884303 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 22:51:04.887547 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 22:51:04.891038 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 22:51:04.894204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 22:51:04.900823 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 22:51:04.904131 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 22:51:04.907370 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 22:51:04.914480 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 22:51:04.917263 Total UI for P1: 0, mck2ui 16
6674 22:51:04.920570 best dqsien dly found for B0: ( 0, 14, 24)
6675 22:51:04.924323 Total UI for P1: 0, mck2ui 16
6676 22:51:04.927296 best dqsien dly found for B1: ( 0, 14, 24)
6677 22:51:04.930914 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6678 22:51:04.934232 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6679 22:51:04.934316
6680 22:51:04.937250 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 22:51:04.940610 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 22:51:04.943874 [Gating] SW calibration Done
6683 22:51:04.943957 ==
6684 22:51:04.947190 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 22:51:04.950465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 22:51:04.950549 ==
6687 22:51:04.954094 RX Vref Scan: 0
6688 22:51:04.954178
6689 22:51:04.957407 RX Vref 0 -> 0, step: 1
6690 22:51:04.957491
6691 22:51:04.957557 RX Delay -410 -> 252, step: 16
6692 22:51:04.964173 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6693 22:51:04.967472 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6694 22:51:04.970573 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6695 22:51:04.974040 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6696 22:51:04.980498 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6697 22:51:04.983986 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6698 22:51:04.987032 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6699 22:51:04.990607 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6700 22:51:04.997439 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6701 22:51:05.000250 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6702 22:51:05.003866 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6703 22:51:05.010500 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6704 22:51:05.013981 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6705 22:51:05.017070 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6706 22:51:05.020526 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6707 22:51:05.027027 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6708 22:51:05.027114 ==
6709 22:51:05.030419 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 22:51:05.033979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 22:51:05.034063 ==
6712 22:51:05.034130 DQS Delay:
6713 22:51:05.037447 DQS0 = 27, DQS1 = 43
6714 22:51:05.037531 DQM Delay:
6715 22:51:05.040287 DQM0 = 7, DQM1 = 17
6716 22:51:05.040371 DQ Delay:
6717 22:51:05.043887 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6718 22:51:05.047083 DQ4 =8, DQ5 =8, DQ6 =16, DQ7 =0
6719 22:51:05.050475 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6720 22:51:05.053612 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6721 22:51:05.053696
6722 22:51:05.053797
6723 22:51:05.053866 ==
6724 22:51:05.056994 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 22:51:05.060735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 22:51:05.060838 ==
6727 22:51:05.060936
6728 22:51:05.061030
6729 22:51:05.063792 TX Vref Scan disable
6730 22:51:05.063876 == TX Byte 0 ==
6731 22:51:05.070571 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 22:51:05.073880 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 22:51:05.073964 == TX Byte 1 ==
6734 22:51:05.080350 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6735 22:51:05.083904 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6736 22:51:05.083989 ==
6737 22:51:05.087056 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 22:51:05.090123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 22:51:05.090207 ==
6740 22:51:05.090274
6741 22:51:05.090335
6742 22:51:05.093698 TX Vref Scan disable
6743 22:51:05.093793 == TX Byte 0 ==
6744 22:51:05.100410 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 22:51:05.103897 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 22:51:05.103981 == TX Byte 1 ==
6747 22:51:05.110503 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6748 22:51:05.113537 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6749 22:51:05.113621
6750 22:51:05.113687 [DATLAT]
6751 22:51:05.116999 Freq=400, CH1 RK0
6752 22:51:05.117083
6753 22:51:05.117149 DATLAT Default: 0xf
6754 22:51:05.120358 0, 0xFFFF, sum = 0
6755 22:51:05.120444 1, 0xFFFF, sum = 0
6756 22:51:05.123511 2, 0xFFFF, sum = 0
6757 22:51:05.123596 3, 0xFFFF, sum = 0
6758 22:51:05.126953 4, 0xFFFF, sum = 0
6759 22:51:05.130000 5, 0xFFFF, sum = 0
6760 22:51:05.130085 6, 0xFFFF, sum = 0
6761 22:51:05.133438 7, 0xFFFF, sum = 0
6762 22:51:05.133524 8, 0xFFFF, sum = 0
6763 22:51:05.136697 9, 0xFFFF, sum = 0
6764 22:51:05.136783 10, 0xFFFF, sum = 0
6765 22:51:05.140234 11, 0xFFFF, sum = 0
6766 22:51:05.140319 12, 0xFFFF, sum = 0
6767 22:51:05.143463 13, 0x0, sum = 1
6768 22:51:05.143549 14, 0x0, sum = 2
6769 22:51:05.146655 15, 0x0, sum = 3
6770 22:51:05.146740 16, 0x0, sum = 4
6771 22:51:05.146807 best_step = 14
6772 22:51:05.150382
6773 22:51:05.150465 ==
6774 22:51:05.153565 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 22:51:05.156725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 22:51:05.156809 ==
6777 22:51:05.156876 RX Vref Scan: 1
6778 22:51:05.156939
6779 22:51:05.160178 RX Vref 0 -> 0, step: 1
6780 22:51:05.160262
6781 22:51:05.163486 RX Delay -327 -> 252, step: 8
6782 22:51:05.163570
6783 22:51:05.166714 Set Vref, RX VrefLevel [Byte0]: 51
6784 22:51:05.170282 [Byte1]: 49
6785 22:51:05.174059
6786 22:51:05.174146 Final RX Vref Byte 0 = 51 to rank0
6787 22:51:05.177399 Final RX Vref Byte 1 = 49 to rank0
6788 22:51:05.180387 Final RX Vref Byte 0 = 51 to rank1
6789 22:51:05.183828 Final RX Vref Byte 1 = 49 to rank1==
6790 22:51:05.186930 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 22:51:05.193785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 22:51:05.193872 ==
6793 22:51:05.193977 DQS Delay:
6794 22:51:05.197198 DQS0 = 32, DQS1 = 40
6795 22:51:05.197281 DQM Delay:
6796 22:51:05.197393 DQM0 = 11, DQM1 = 12
6797 22:51:05.200364 DQ Delay:
6798 22:51:05.203506 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6799 22:51:05.203590 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6800 22:51:05.206980 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6801 22:51:05.210490 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6802 22:51:05.210574
6803 22:51:05.210640
6804 22:51:05.220142 [DQSOSCAuto] RK0, (LSB)MR18= 0xa2dc, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 389 ps
6805 22:51:05.223564 CH1 RK0: MR19=C0C, MR18=A2DC
6806 22:51:05.229827 CH1_RK0: MR19=0xC0C, MR18=0xA2DC, DQSOSC=382, MR23=63, INC=404, DEC=269
6807 22:51:05.229914 ==
6808 22:51:05.233126 Dram Type= 6, Freq= 0, CH_1, rank 1
6809 22:51:05.236826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 22:51:05.236929 ==
6811 22:51:05.239979 [Gating] SW mode calibration
6812 22:51:05.246642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6813 22:51:05.253147 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6814 22:51:05.256524 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 22:51:05.259627 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 22:51:05.266506 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 22:51:05.269838 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 22:51:05.272931 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 22:51:05.276694 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 22:51:05.282998 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 22:51:05.286733 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 22:51:05.289774 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 22:51:05.293103 Total UI for P1: 0, mck2ui 16
6824 22:51:05.296498 best dqsien dly found for B0: ( 0, 14, 24)
6825 22:51:05.299633 Total UI for P1: 0, mck2ui 16
6826 22:51:05.303230 best dqsien dly found for B1: ( 0, 14, 24)
6827 22:51:05.306352 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6828 22:51:05.313214 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6829 22:51:05.313355
6830 22:51:05.316418 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 22:51:05.319503 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 22:51:05.322794 [Gating] SW calibration Done
6833 22:51:05.322893 ==
6834 22:51:05.326377 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 22:51:05.329507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 22:51:05.329580 ==
6837 22:51:05.332945 RX Vref Scan: 0
6838 22:51:05.333039
6839 22:51:05.333130 RX Vref 0 -> 0, step: 1
6840 22:51:05.333216
6841 22:51:05.336117 RX Delay -410 -> 252, step: 16
6842 22:51:05.339443 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6843 22:51:05.346481 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6844 22:51:05.349549 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6845 22:51:05.352835 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6846 22:51:05.356161 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6847 22:51:05.362796 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6848 22:51:05.366384 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6849 22:51:05.369587 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6850 22:51:05.373097 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6851 22:51:05.379569 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6852 22:51:05.382921 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6853 22:51:05.385908 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6854 22:51:05.389649 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6855 22:51:05.395875 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6856 22:51:05.399256 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6857 22:51:05.403070 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6858 22:51:05.403173 ==
6859 22:51:05.406004 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 22:51:05.412836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 22:51:05.412934 ==
6862 22:51:05.413024 DQS Delay:
6863 22:51:05.415922 DQS0 = 35, DQS1 = 35
6864 22:51:05.416015 DQM Delay:
6865 22:51:05.416105 DQM0 = 16, DQM1 = 12
6866 22:51:05.419583 DQ Delay:
6867 22:51:05.422963 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6868 22:51:05.423059 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6869 22:51:05.426219 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6870 22:51:05.429462 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6871 22:51:05.429531
6872 22:51:05.432886
6873 22:51:05.432978 ==
6874 22:51:05.436123 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 22:51:05.439337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 22:51:05.439431 ==
6877 22:51:05.439518
6878 22:51:05.439607
6879 22:51:05.442746 TX Vref Scan disable
6880 22:51:05.442811 == TX Byte 0 ==
6881 22:51:05.445946 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6882 22:51:05.452753 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6883 22:51:05.452850 == TX Byte 1 ==
6884 22:51:05.456213 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6885 22:51:05.463140 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6886 22:51:05.463236 ==
6887 22:51:05.465982 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 22:51:05.469171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 22:51:05.469267 ==
6890 22:51:05.469401
6891 22:51:05.469484
6892 22:51:05.472509 TX Vref Scan disable
6893 22:51:05.472601 == TX Byte 0 ==
6894 22:51:05.476040 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6895 22:51:05.482768 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6896 22:51:05.482838 == TX Byte 1 ==
6897 22:51:05.485986 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6898 22:51:05.492654 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6899 22:51:05.492758
6900 22:51:05.492849 [DATLAT]
6901 22:51:05.492936 Freq=400, CH1 RK1
6902 22:51:05.493027
6903 22:51:05.495844 DATLAT Default: 0xe
6904 22:51:05.498963 0, 0xFFFF, sum = 0
6905 22:51:05.499059 1, 0xFFFF, sum = 0
6906 22:51:05.502606 2, 0xFFFF, sum = 0
6907 22:51:05.502674 3, 0xFFFF, sum = 0
6908 22:51:05.505827 4, 0xFFFF, sum = 0
6909 22:51:05.505924 5, 0xFFFF, sum = 0
6910 22:51:05.509084 6, 0xFFFF, sum = 0
6911 22:51:05.509185 7, 0xFFFF, sum = 0
6912 22:51:05.512370 8, 0xFFFF, sum = 0
6913 22:51:05.512468 9, 0xFFFF, sum = 0
6914 22:51:05.515818 10, 0xFFFF, sum = 0
6915 22:51:05.515913 11, 0xFFFF, sum = 0
6916 22:51:05.519093 12, 0xFFFF, sum = 0
6917 22:51:05.519161 13, 0x0, sum = 1
6918 22:51:05.522626 14, 0x0, sum = 2
6919 22:51:05.522727 15, 0x0, sum = 3
6920 22:51:05.525931 16, 0x0, sum = 4
6921 22:51:05.526030 best_step = 14
6922 22:51:05.526118
6923 22:51:05.526213 ==
6924 22:51:05.529229 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 22:51:05.532756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 22:51:05.535860 ==
6927 22:51:05.535958 RX Vref Scan: 0
6928 22:51:05.536022
6929 22:51:05.539013 RX Vref 0 -> 0, step: 1
6930 22:51:05.539106
6931 22:51:05.542694 RX Delay -311 -> 252, step: 8
6932 22:51:05.545602 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6933 22:51:05.552206 iDelay=217, Bit 1, Center -24 (-239 ~ 192) 432
6934 22:51:05.555686 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6935 22:51:05.558882 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6936 22:51:05.562330 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6937 22:51:05.569196 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6938 22:51:05.572581 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6939 22:51:05.575646 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6940 22:51:05.578972 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6941 22:51:05.585371 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6942 22:51:05.589029 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6943 22:51:05.592121 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6944 22:51:05.595396 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6945 22:51:05.602353 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6946 22:51:05.605550 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6947 22:51:05.608942 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6948 22:51:05.609046 ==
6949 22:51:05.612134 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 22:51:05.618788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 22:51:05.618865 ==
6952 22:51:05.618929 DQS Delay:
6953 22:51:05.622344 DQS0 = 32, DQS1 = 36
6954 22:51:05.622440 DQM Delay:
6955 22:51:05.622539 DQM0 = 12, DQM1 = 11
6956 22:51:05.625689 DQ Delay:
6957 22:51:05.628653 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6958 22:51:05.628731 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =8
6959 22:51:05.631896 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6960 22:51:05.635488 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
6961 22:51:05.635593
6962 22:51:05.635684
6963 22:51:05.645222 [DQSOSCAuto] RK1, (LSB)MR18= 0xac56, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
6964 22:51:05.648719 CH1 RK1: MR19=C0C, MR18=AC56
6965 22:51:05.655490 CH1_RK1: MR19=0xC0C, MR18=0xAC56, DQSOSC=388, MR23=63, INC=392, DEC=261
6966 22:51:05.655599 [RxdqsGatingPostProcess] freq 400
6967 22:51:05.661933 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6968 22:51:05.665597 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 22:51:05.669173 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 22:51:05.672360 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 22:51:05.675717 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 22:51:05.679051 best DQS0 dly(2T, 0.5T) = (0, 10)
6973 22:51:05.682270 best DQS1 dly(2T, 0.5T) = (0, 10)
6974 22:51:05.685260 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6975 22:51:05.688788 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6976 22:51:05.692097 Pre-setting of DQS Precalculation
6977 22:51:05.695554 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6978 22:51:05.702049 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6979 22:51:05.709085 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6980 22:51:05.709183
6981 22:51:05.712316
6982 22:51:05.712410 [Calibration Summary] 800 Mbps
6983 22:51:05.715407 CH 0, Rank 0
6984 22:51:05.715502 SW Impedance : PASS
6985 22:51:05.718930 DUTY Scan : NO K
6986 22:51:05.721970 ZQ Calibration : PASS
6987 22:51:05.722045 Jitter Meter : NO K
6988 22:51:05.725293 CBT Training : PASS
6989 22:51:05.728888 Write leveling : PASS
6990 22:51:05.728984 RX DQS gating : PASS
6991 22:51:05.732097 RX DQ/DQS(RDDQC) : PASS
6992 22:51:05.735162 TX DQ/DQS : PASS
6993 22:51:05.735265 RX DATLAT : PASS
6994 22:51:05.738684 RX DQ/DQS(Engine): PASS
6995 22:51:05.741966 TX OE : NO K
6996 22:51:05.742040 All Pass.
6997 22:51:05.742109
6998 22:51:05.742168 CH 0, Rank 1
6999 22:51:05.745256 SW Impedance : PASS
7000 22:51:05.748609 DUTY Scan : NO K
7001 22:51:05.748683 ZQ Calibration : PASS
7002 22:51:05.752150 Jitter Meter : NO K
7003 22:51:05.752223 CBT Training : PASS
7004 22:51:05.755251 Write leveling : NO K
7005 22:51:05.758443 RX DQS gating : PASS
7006 22:51:05.758516 RX DQ/DQS(RDDQC) : PASS
7007 22:51:05.761632 TX DQ/DQS : PASS
7008 22:51:05.765223 RX DATLAT : PASS
7009 22:51:05.765317 RX DQ/DQS(Engine): PASS
7010 22:51:05.768647 TX OE : NO K
7011 22:51:05.768746 All Pass.
7012 22:51:05.768840
7013 22:51:05.771916 CH 1, Rank 0
7014 22:51:05.772014 SW Impedance : PASS
7015 22:51:05.774982 DUTY Scan : NO K
7016 22:51:05.778532 ZQ Calibration : PASS
7017 22:51:05.778628 Jitter Meter : NO K
7018 22:51:05.781830 CBT Training : PASS
7019 22:51:05.784998 Write leveling : PASS
7020 22:51:05.785106 RX DQS gating : PASS
7021 22:51:05.788392 RX DQ/DQS(RDDQC) : PASS
7022 22:51:05.794011 TX DQ/DQS : PASS
7023 22:51:05.794097 RX DATLAT : PASS
7024 22:51:05.795095 RX DQ/DQS(Engine): PASS
7025 22:51:05.798427 TX OE : NO K
7026 22:51:05.798526 All Pass.
7027 22:51:05.798619
7028 22:51:05.798707 CH 1, Rank 1
7029 22:51:05.801701 SW Impedance : PASS
7030 22:51:05.805007 DUTY Scan : NO K
7031 22:51:05.805109 ZQ Calibration : PASS
7032 22:51:05.808733 Jitter Meter : NO K
7033 22:51:05.808808 CBT Training : PASS
7034 22:51:05.811569 Write leveling : NO K
7035 22:51:05.814848 RX DQS gating : PASS
7036 22:51:05.814949 RX DQ/DQS(RDDQC) : PASS
7037 22:51:05.818392 TX DQ/DQS : PASS
7038 22:51:05.821487 RX DATLAT : PASS
7039 22:51:05.821561 RX DQ/DQS(Engine): PASS
7040 22:51:05.825081 TX OE : NO K
7041 22:51:05.825183 All Pass.
7042 22:51:05.825272
7043 22:51:05.829090 DramC Write-DBI off
7044 22:51:05.831623 PER_BANK_REFRESH: Hybrid Mode
7045 22:51:05.831697 TX_TRACKING: ON
7046 22:51:05.841720 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7047 22:51:05.844931 [FAST_K] Save calibration result to emmc
7048 22:51:05.848115 dramc_set_vcore_voltage set vcore to 725000
7049 22:51:05.851867 Read voltage for 1600, 0
7050 22:51:05.851983 Vio18 = 0
7051 22:51:05.852114 Vcore = 725000
7052 22:51:05.854806 Vdram = 0
7053 22:51:05.854897 Vddq = 0
7054 22:51:05.854983 Vmddr = 0
7055 22:51:05.861591 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7056 22:51:05.864960 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7057 22:51:05.868568 MEM_TYPE=3, freq_sel=13
7058 22:51:05.871410 sv_algorithm_assistance_LP4_3733
7059 22:51:05.874911 ============ PULL DRAM RESETB DOWN ============
7060 22:51:05.878183 ========== PULL DRAM RESETB DOWN end =========
7061 22:51:05.884566 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7062 22:51:05.888461 ===================================
7063 22:51:05.891598 LPDDR4 DRAM CONFIGURATION
7064 22:51:05.894975 ===================================
7065 22:51:05.895062 EX_ROW_EN[0] = 0x0
7066 22:51:05.897962 EX_ROW_EN[1] = 0x0
7067 22:51:05.898085 LP4Y_EN = 0x0
7068 22:51:05.901463 WORK_FSP = 0x1
7069 22:51:05.901596 WL = 0x5
7070 22:51:05.904856 RL = 0x5
7071 22:51:05.904966 BL = 0x2
7072 22:51:05.908066 RPST = 0x0
7073 22:51:05.908207 RD_PRE = 0x0
7074 22:51:05.911311 WR_PRE = 0x1
7075 22:51:05.911458 WR_PST = 0x1
7076 22:51:05.914473 DBI_WR = 0x0
7077 22:51:05.914592 DBI_RD = 0x0
7078 22:51:05.917911 OTF = 0x1
7079 22:51:05.921314 ===================================
7080 22:51:05.924650 ===================================
7081 22:51:05.924755 ANA top config
7082 22:51:05.927900 ===================================
7083 22:51:05.931371 DLL_ASYNC_EN = 0
7084 22:51:05.934661 ALL_SLAVE_EN = 0
7085 22:51:05.937785 NEW_RANK_MODE = 1
7086 22:51:05.937868 DLL_IDLE_MODE = 1
7087 22:51:05.941375 LP45_APHY_COMB_EN = 1
7088 22:51:05.944356 TX_ODT_DIS = 0
7089 22:51:05.947849 NEW_8X_MODE = 1
7090 22:51:05.951374 ===================================
7091 22:51:05.955019 ===================================
7092 22:51:05.958310 data_rate = 3200
7093 22:51:05.958396 CKR = 1
7094 22:51:05.961271 DQ_P2S_RATIO = 8
7095 22:51:05.964808 ===================================
7096 22:51:05.967979 CA_P2S_RATIO = 8
7097 22:51:05.971355 DQ_CA_OPEN = 0
7098 22:51:05.974758 DQ_SEMI_OPEN = 0
7099 22:51:05.977766 CA_SEMI_OPEN = 0
7100 22:51:05.977879 CA_FULL_RATE = 0
7101 22:51:05.981481 DQ_CKDIV4_EN = 0
7102 22:51:05.984487 CA_CKDIV4_EN = 0
7103 22:51:05.988071 CA_PREDIV_EN = 0
7104 22:51:05.991640 PH8_DLY = 12
7105 22:51:05.994775 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7106 22:51:05.994868 DQ_AAMCK_DIV = 4
7107 22:51:05.998243 CA_AAMCK_DIV = 4
7108 22:51:06.001140 CA_ADMCK_DIV = 4
7109 22:51:06.004497 DQ_TRACK_CA_EN = 0
7110 22:51:06.007792 CA_PICK = 1600
7111 22:51:06.011379 CA_MCKIO = 1600
7112 22:51:06.011468 MCKIO_SEMI = 0
7113 22:51:06.014595 PLL_FREQ = 3068
7114 22:51:06.017819 DQ_UI_PI_RATIO = 32
7115 22:51:06.021232 CA_UI_PI_RATIO = 0
7116 22:51:06.024650 ===================================
7117 22:51:06.028014 ===================================
7118 22:51:06.031171 memory_type:LPDDR4
7119 22:51:06.031256 GP_NUM : 10
7120 22:51:06.034849 SRAM_EN : 1
7121 22:51:06.037991 MD32_EN : 0
7122 22:51:06.041226 ===================================
7123 22:51:06.041336 [ANA_INIT] >>>>>>>>>>>>>>
7124 22:51:06.044524 <<<<<< [CONFIGURE PHASE]: ANA_TX
7125 22:51:06.047797 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7126 22:51:06.051429 ===================================
7127 22:51:06.054334 data_rate = 3200,PCW = 0X7600
7128 22:51:06.057854 ===================================
7129 22:51:06.061132 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7130 22:51:06.067568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 22:51:06.071228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 22:51:06.077710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7133 22:51:06.081340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7134 22:51:06.084507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7135 22:51:06.084591 [ANA_INIT] flow start
7136 22:51:06.087948 [ANA_INIT] PLL >>>>>>>>
7137 22:51:06.090795 [ANA_INIT] PLL <<<<<<<<
7138 22:51:06.094174 [ANA_INIT] MIDPI >>>>>>>>
7139 22:51:06.094257 [ANA_INIT] MIDPI <<<<<<<<
7140 22:51:06.097807 [ANA_INIT] DLL >>>>>>>>
7141 22:51:06.100794 [ANA_INIT] DLL <<<<<<<<
7142 22:51:06.100877 [ANA_INIT] flow end
7143 22:51:06.104711 ============ LP4 DIFF to SE enter ============
7144 22:51:06.111188 ============ LP4 DIFF to SE exit ============
7145 22:51:06.111272 [ANA_INIT] <<<<<<<<<<<<<
7146 22:51:06.114135 [Flow] Enable top DCM control >>>>>
7147 22:51:06.117599 [Flow] Enable top DCM control <<<<<
7148 22:51:06.120878 Enable DLL master slave shuffle
7149 22:51:06.127506 ==============================================================
7150 22:51:06.127591 Gating Mode config
7151 22:51:06.134259 ==============================================================
7152 22:51:06.137847 Config description:
7153 22:51:06.147737 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7154 22:51:06.154247 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7155 22:51:06.157611 SELPH_MODE 0: By rank 1: By Phase
7156 22:51:06.164034 ==============================================================
7157 22:51:06.167569 GAT_TRACK_EN = 1
7158 22:51:06.167653 RX_GATING_MODE = 2
7159 22:51:06.170598 RX_GATING_TRACK_MODE = 2
7160 22:51:06.174093 SELPH_MODE = 1
7161 22:51:06.177157 PICG_EARLY_EN = 1
7162 22:51:06.180709 VALID_LAT_VALUE = 1
7163 22:51:06.187345 ==============================================================
7164 22:51:06.190892 Enter into Gating configuration >>>>
7165 22:51:06.193973 Exit from Gating configuration <<<<
7166 22:51:06.197373 Enter into DVFS_PRE_config >>>>>
7167 22:51:06.207348 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7168 22:51:06.210703 Exit from DVFS_PRE_config <<<<<
7169 22:51:06.214057 Enter into PICG configuration >>>>
7170 22:51:06.217366 Exit from PICG configuration <<<<
7171 22:51:06.220510 [RX_INPUT] configuration >>>>>
7172 22:51:06.224129 [RX_INPUT] configuration <<<<<
7173 22:51:06.227500 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7174 22:51:06.234190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7175 22:51:06.240966 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 22:51:06.243845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 22:51:06.250753 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 22:51:06.256989 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 22:51:06.260765 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7180 22:51:06.263876 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7181 22:51:06.270648 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7182 22:51:06.273905 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7183 22:51:06.277439 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7184 22:51:06.284060 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7185 22:51:06.287422 ===================================
7186 22:51:06.287505 LPDDR4 DRAM CONFIGURATION
7187 22:51:06.290304 ===================================
7188 22:51:06.293915 EX_ROW_EN[0] = 0x0
7189 22:51:06.296994 EX_ROW_EN[1] = 0x0
7190 22:51:06.297064 LP4Y_EN = 0x0
7191 22:51:06.300343 WORK_FSP = 0x1
7192 22:51:06.300413 WL = 0x5
7193 22:51:06.303786 RL = 0x5
7194 22:51:06.303855 BL = 0x2
7195 22:51:06.307046 RPST = 0x0
7196 22:51:06.307117 RD_PRE = 0x0
7197 22:51:06.310478 WR_PRE = 0x1
7198 22:51:06.310548 WR_PST = 0x1
7199 22:51:06.313830 DBI_WR = 0x0
7200 22:51:06.313900 DBI_RD = 0x0
7201 22:51:06.317223 OTF = 0x1
7202 22:51:06.320436 ===================================
7203 22:51:06.323762 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7204 22:51:06.326957 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7205 22:51:06.333614 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 22:51:06.337046 ===================================
7207 22:51:06.337122 LPDDR4 DRAM CONFIGURATION
7208 22:51:06.340273 ===================================
7209 22:51:06.343374 EX_ROW_EN[0] = 0x10
7210 22:51:06.343445 EX_ROW_EN[1] = 0x0
7211 22:51:06.346979 LP4Y_EN = 0x0
7212 22:51:06.347049 WORK_FSP = 0x1
7213 22:51:06.350183 WL = 0x5
7214 22:51:06.353420 RL = 0x5
7215 22:51:06.353497 BL = 0x2
7216 22:51:06.356912 RPST = 0x0
7217 22:51:06.357007 RD_PRE = 0x0
7218 22:51:06.360066 WR_PRE = 0x1
7219 22:51:06.360136 WR_PST = 0x1
7220 22:51:06.363449 DBI_WR = 0x0
7221 22:51:06.363551 DBI_RD = 0x0
7222 22:51:06.367139 OTF = 0x1
7223 22:51:06.370483 ===================================
7224 22:51:06.373568 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7225 22:51:06.376830 ==
7226 22:51:06.379931 Dram Type= 6, Freq= 0, CH_0, rank 0
7227 22:51:06.383471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7228 22:51:06.383572 ==
7229 22:51:06.386711 [Duty_Offset_Calibration]
7230 22:51:06.386787 B0:2 B1:0 CA:1
7231 22:51:06.386849
7232 22:51:06.389816 [DutyScan_Calibration_Flow] k_type=0
7233 22:51:06.399174
7234 22:51:06.399284 ==CLK 0==
7235 22:51:06.402467 Final CLK duty delay cell = -4
7236 22:51:06.405917 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7237 22:51:06.409110 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7238 22:51:06.412359 [-4] AVG Duty = 4906%(X100)
7239 22:51:06.412432
7240 22:51:06.415919 CH0 CLK Duty spec in!! Max-Min= 187%
7241 22:51:06.419058 [DutyScan_Calibration_Flow] ====Done====
7242 22:51:06.419127
7243 22:51:06.422342 [DutyScan_Calibration_Flow] k_type=1
7244 22:51:06.439025
7245 22:51:06.439100 ==DQS 0 ==
7246 22:51:06.441893 Final DQS duty delay cell = 0
7247 22:51:06.445255 [0] MAX Duty = 5218%(X100), DQS PI = 32
7248 22:51:06.448688 [0] MIN Duty = 4938%(X100), DQS PI = 0
7249 22:51:06.448761 [0] AVG Duty = 5078%(X100)
7250 22:51:06.452116
7251 22:51:06.452189 ==DQS 1 ==
7252 22:51:06.455385 Final DQS duty delay cell = -4
7253 22:51:06.458812 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7254 22:51:06.462039 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7255 22:51:06.465248 [-4] AVG Duty = 4969%(X100)
7256 22:51:06.465353
7257 22:51:06.468772 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7258 22:51:06.468845
7259 22:51:06.471993 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7260 22:51:06.475547 [DutyScan_Calibration_Flow] ====Done====
7261 22:51:06.475615
7262 22:51:06.478534 [DutyScan_Calibration_Flow] k_type=3
7263 22:51:06.495941
7264 22:51:06.496022 ==DQM 0 ==
7265 22:51:06.499435 Final DQM duty delay cell = 0
7266 22:51:06.502756 [0] MAX Duty = 5062%(X100), DQS PI = 24
7267 22:51:06.506031 [0] MIN Duty = 4813%(X100), DQS PI = 50
7268 22:51:06.509315 [0] AVG Duty = 4937%(X100)
7269 22:51:06.509417
7270 22:51:06.509495 ==DQM 1 ==
7271 22:51:06.512762 Final DQM duty delay cell = 0
7272 22:51:06.515988 [0] MAX Duty = 5249%(X100), DQS PI = 30
7273 22:51:06.519379 [0] MIN Duty = 5000%(X100), DQS PI = 20
7274 22:51:06.522583 [0] AVG Duty = 5124%(X100)
7275 22:51:06.522652
7276 22:51:06.525875 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7277 22:51:06.525946
7278 22:51:06.529412 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7279 22:51:06.532888 [DutyScan_Calibration_Flow] ====Done====
7280 22:51:06.532957
7281 22:51:06.535911 [DutyScan_Calibration_Flow] k_type=2
7282 22:51:06.553139
7283 22:51:06.553240 ==DQ 0 ==
7284 22:51:06.556516 Final DQ duty delay cell = 0
7285 22:51:06.560011 [0] MAX Duty = 5124%(X100), DQS PI = 34
7286 22:51:06.563204 [0] MIN Duty = 5000%(X100), DQS PI = 0
7287 22:51:06.563277 [0] AVG Duty = 5062%(X100)
7288 22:51:06.563340
7289 22:51:06.566770 ==DQ 1 ==
7290 22:51:06.569933 Final DQ duty delay cell = 0
7291 22:51:06.573022 [0] MAX Duty = 4969%(X100), DQS PI = 44
7292 22:51:06.576726 [0] MIN Duty = 4875%(X100), DQS PI = 0
7293 22:51:06.576795 [0] AVG Duty = 4922%(X100)
7294 22:51:06.576855
7295 22:51:06.580012 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7296 22:51:06.580078
7297 22:51:06.583505 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7298 22:51:06.589925 [DutyScan_Calibration_Flow] ====Done====
7299 22:51:06.590000 ==
7300 22:51:06.593200 Dram Type= 6, Freq= 0, CH_1, rank 0
7301 22:51:06.596582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7302 22:51:06.596653 ==
7303 22:51:06.600140 [Duty_Offset_Calibration]
7304 22:51:06.600211 B0:0 B1:-1 CA:2
7305 22:51:06.600275
7306 22:51:06.603313 [DutyScan_Calibration_Flow] k_type=0
7307 22:51:06.613469
7308 22:51:06.613566 ==CLK 0==
7309 22:51:06.616544 Final CLK duty delay cell = 0
7310 22:51:06.620203 [0] MAX Duty = 5156%(X100), DQS PI = 10
7311 22:51:06.623197 [0] MIN Duty = 4906%(X100), DQS PI = 46
7312 22:51:06.623264 [0] AVG Duty = 5031%(X100)
7313 22:51:06.626465
7314 22:51:06.629866 CH1 CLK Duty spec in!! Max-Min= 250%
7315 22:51:06.633316 [DutyScan_Calibration_Flow] ====Done====
7316 22:51:06.633391
7317 22:51:06.636773 [DutyScan_Calibration_Flow] k_type=1
7318 22:51:06.653040
7319 22:51:06.653115 ==DQS 0 ==
7320 22:51:06.656362 Final DQS duty delay cell = 0
7321 22:51:06.659693 [0] MAX Duty = 5093%(X100), DQS PI = 24
7322 22:51:06.663006 [0] MIN Duty = 4969%(X100), DQS PI = 60
7323 22:51:06.663078 [0] AVG Duty = 5031%(X100)
7324 22:51:06.666802
7325 22:51:06.666877 ==DQS 1 ==
7326 22:51:06.669613 Final DQS duty delay cell = 0
7327 22:51:06.673078 [0] MAX Duty = 5187%(X100), DQS PI = 0
7328 22:51:06.676562 [0] MIN Duty = 4844%(X100), DQS PI = 32
7329 22:51:06.676638 [0] AVG Duty = 5015%(X100)
7330 22:51:06.679663
7331 22:51:06.682975 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7332 22:51:06.683047
7333 22:51:06.686430 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7334 22:51:06.689699 [DutyScan_Calibration_Flow] ====Done====
7335 22:51:06.689810
7336 22:51:06.692934 [DutyScan_Calibration_Flow] k_type=3
7337 22:51:06.710656
7338 22:51:06.710736 ==DQM 0 ==
7339 22:51:06.713857 Final DQM duty delay cell = 4
7340 22:51:06.717076 [4] MAX Duty = 5125%(X100), DQS PI = 8
7341 22:51:06.720332 [4] MIN Duty = 4969%(X100), DQS PI = 32
7342 22:51:06.724246 [4] AVG Duty = 5047%(X100)
7343 22:51:06.724326
7344 22:51:06.724389 ==DQM 1 ==
7345 22:51:06.727023 Final DQM duty delay cell = 0
7346 22:51:06.730529 [0] MAX Duty = 5281%(X100), DQS PI = 58
7347 22:51:06.734209 [0] MIN Duty = 4844%(X100), DQS PI = 34
7348 22:51:06.737005 [0] AVG Duty = 5062%(X100)
7349 22:51:06.737086
7350 22:51:06.740339 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7351 22:51:06.740422
7352 22:51:06.743687 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7353 22:51:06.747008 [DutyScan_Calibration_Flow] ====Done====
7354 22:51:06.747091
7355 22:51:06.750293 [DutyScan_Calibration_Flow] k_type=2
7356 22:51:06.767566
7357 22:51:06.767649 ==DQ 0 ==
7358 22:51:06.770935 Final DQ duty delay cell = 0
7359 22:51:06.774082 [0] MAX Duty = 5062%(X100), DQS PI = 22
7360 22:51:06.777486 [0] MIN Duty = 4969%(X100), DQS PI = 2
7361 22:51:06.777569 [0] AVG Duty = 5015%(X100)
7362 22:51:06.780608
7363 22:51:06.780690 ==DQ 1 ==
7364 22:51:06.784195 Final DQ duty delay cell = 0
7365 22:51:06.787634 [0] MAX Duty = 5062%(X100), DQS PI = 2
7366 22:51:06.790905 [0] MIN Duty = 4813%(X100), DQS PI = 34
7367 22:51:06.790987 [0] AVG Duty = 4937%(X100)
7368 22:51:06.791053
7369 22:51:06.794039 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7370 22:51:06.794121
7371 22:51:06.797518 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7372 22:51:06.804318 [DutyScan_Calibration_Flow] ====Done====
7373 22:51:06.807669 nWR fixed to 30
7374 22:51:06.807753 [ModeRegInit_LP4] CH0 RK0
7375 22:51:06.810458 [ModeRegInit_LP4] CH0 RK1
7376 22:51:06.813818 [ModeRegInit_LP4] CH1 RK0
7377 22:51:06.813904 [ModeRegInit_LP4] CH1 RK1
7378 22:51:06.817497 match AC timing 5
7379 22:51:06.820934 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7380 22:51:06.824243 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7381 22:51:06.830587 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7382 22:51:06.834054 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7383 22:51:06.840642 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7384 22:51:06.840726 [MiockJmeterHQA]
7385 22:51:06.840791
7386 22:51:06.844075 [DramcMiockJmeter] u1RxGatingPI = 0
7387 22:51:06.847451 0 : 4252, 4027
7388 22:51:06.847536 4 : 4363, 4137
7389 22:51:06.847603 8 : 4252, 4027
7390 22:51:06.850721 12 : 4252, 4027
7391 22:51:06.850805 16 : 4363, 4137
7392 22:51:06.853971 20 : 4363, 4137
7393 22:51:06.854055 24 : 4255, 4030
7394 22:51:06.857362 28 : 4362, 4137
7395 22:51:06.857446 32 : 4252, 4027
7396 22:51:06.857513 36 : 4362, 4137
7397 22:51:06.860631 40 : 4253, 4026
7398 22:51:06.860715 44 : 4252, 4027
7399 22:51:06.863820 48 : 4255, 4029
7400 22:51:06.863904 52 : 4252, 4027
7401 22:51:06.867217 56 : 4252, 4027
7402 22:51:06.867301 60 : 4252, 4027
7403 22:51:06.870934 64 : 4252, 4027
7404 22:51:06.871018 68 : 4250, 4026
7405 22:51:06.871084 72 : 4363, 4140
7406 22:51:06.874229 76 : 4252, 4030
7407 22:51:06.874322 80 : 4253, 4029
7408 22:51:06.877513 84 : 4250, 4027
7409 22:51:06.877596 88 : 4363, 3794
7410 22:51:06.880619 92 : 4250, 0
7411 22:51:06.880703 96 : 4362, 0
7412 22:51:06.880769 100 : 4361, 0
7413 22:51:06.883800 104 : 4250, 0
7414 22:51:06.883884 108 : 4250, 0
7415 22:51:06.883950 112 : 4250, 0
7416 22:51:06.886996 116 : 4363, 0
7417 22:51:06.887080 120 : 4250, 0
7418 22:51:06.890328 124 : 4360, 0
7419 22:51:06.890413 128 : 4255, 0
7420 22:51:06.890512 132 : 4250, 0
7421 22:51:06.894051 136 : 4250, 0
7422 22:51:06.894136 140 : 4255, 0
7423 22:51:06.896887 144 : 4250, 0
7424 22:51:06.896972 148 : 4250, 0
7425 22:51:06.897039 152 : 4252, 0
7426 22:51:06.900949 156 : 4250, 0
7427 22:51:06.901033 160 : 4250, 0
7428 22:51:06.903806 164 : 4250, 0
7429 22:51:06.903890 168 : 4360, 0
7430 22:51:06.903963 172 : 4250, 0
7431 22:51:06.906976 176 : 4250, 0
7432 22:51:06.907061 180 : 4249, 0
7433 22:51:06.907128 184 : 4250, 0
7434 22:51:06.910682 188 : 4250, 0
7435 22:51:06.910766 192 : 4363, 0
7436 22:51:06.913618 196 : 4250, 0
7437 22:51:06.913701 200 : 4250, 10
7438 22:51:06.917108 204 : 4250, 2835
7439 22:51:06.917220 208 : 4250, 4027
7440 22:51:06.917356 212 : 4253, 4029
7441 22:51:06.920380 216 : 4253, 4029
7442 22:51:06.920463 220 : 4363, 4138
7443 22:51:06.923833 224 : 4250, 4027
7444 22:51:06.923917 228 : 4252, 4029
7445 22:51:06.927094 232 : 4250, 4027
7446 22:51:06.927178 236 : 4250, 4027
7447 22:51:06.930305 240 : 4361, 4137
7448 22:51:06.930389 244 : 4250, 4026
7449 22:51:06.933780 248 : 4361, 4137
7450 22:51:06.933864 252 : 4250, 4027
7451 22:51:06.937215 256 : 4249, 4027
7452 22:51:06.937304 260 : 4250, 4026
7453 22:51:06.937412 264 : 4250, 4026
7454 22:51:06.940614 268 : 4253, 4029
7455 22:51:06.940698 272 : 4360, 4138
7456 22:51:06.943864 276 : 4249, 4027
7457 22:51:06.943949 280 : 4250, 4026
7458 22:51:06.947130 284 : 4255, 4029
7459 22:51:06.947214 288 : 4250, 4027
7460 22:51:06.950634 292 : 4360, 4137
7461 22:51:06.950718 296 : 4250, 4026
7462 22:51:06.953667 300 : 4363, 4137
7463 22:51:06.953751 304 : 4250, 4027
7464 22:51:06.957081 308 : 4250, 4027
7465 22:51:06.957165 312 : 4254, 3918
7466 22:51:06.960692 316 : 4250, 1861
7467 22:51:06.960776
7468 22:51:06.960842 MIOCK jitter meter ch=0
7469 22:51:06.960903
7470 22:51:06.963744 1T = (316-92) = 224 dly cells
7471 22:51:06.970794 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7472 22:51:06.970878 ==
7473 22:51:06.973864 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 22:51:06.977349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7475 22:51:06.977435 ==
7476 22:51:06.983928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7477 22:51:06.987131 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7478 22:51:06.990249 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7479 22:51:06.997220 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7480 22:51:07.006227 [CA 0] Center 42 (12~73) winsize 62
7481 22:51:07.009497 [CA 1] Center 42 (13~72) winsize 60
7482 22:51:07.013078 [CA 2] Center 37 (7~67) winsize 61
7483 22:51:07.016171 [CA 3] Center 37 (7~67) winsize 61
7484 22:51:07.019735 [CA 4] Center 36 (6~66) winsize 61
7485 22:51:07.023056 [CA 5] Center 35 (5~65) winsize 61
7486 22:51:07.023140
7487 22:51:07.026428 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7488 22:51:07.026512
7489 22:51:07.029913 [CATrainingPosCal] consider 1 rank data
7490 22:51:07.033237 u2DelayCellTimex100 = 290/100 ps
7491 22:51:07.036660 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7492 22:51:07.042874 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7493 22:51:07.046920 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7494 22:51:07.049512 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7495 22:51:07.052605 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7496 22:51:07.056186 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7497 22:51:07.056287
7498 22:51:07.059352 CA PerBit enable=1, Macro0, CA PI delay=35
7499 22:51:07.059428
7500 22:51:07.062865 [CBTSetCACLKResult] CA Dly = 35
7501 22:51:07.066038 CS Dly: 9 (0~40)
7502 22:51:07.069621 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7503 22:51:07.072777 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7504 22:51:07.072885 ==
7505 22:51:07.075932 Dram Type= 6, Freq= 0, CH_0, rank 1
7506 22:51:07.079280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 22:51:07.082324 ==
7508 22:51:07.085734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 22:51:07.089423 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 22:51:07.095834 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 22:51:07.099166 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 22:51:07.109300 [CA 0] Center 43 (13~73) winsize 61
7513 22:51:07.112956 [CA 1] Center 43 (13~73) winsize 61
7514 22:51:07.116407 [CA 2] Center 37 (8~67) winsize 60
7515 22:51:07.119277 [CA 3] Center 38 (8~68) winsize 61
7516 22:51:07.122884 [CA 4] Center 36 (6~66) winsize 61
7517 22:51:07.126157 [CA 5] Center 36 (6~66) winsize 61
7518 22:51:07.126263
7519 22:51:07.129749 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 22:51:07.129833
7521 22:51:07.132540 [CATrainingPosCal] consider 2 rank data
7522 22:51:07.136096 u2DelayCellTimex100 = 290/100 ps
7523 22:51:07.139385 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7524 22:51:07.145923 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7525 22:51:07.149082 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7526 22:51:07.152825 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7527 22:51:07.155765 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7528 22:51:07.159209 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7529 22:51:07.159293
7530 22:51:07.162640 CA PerBit enable=1, Macro0, CA PI delay=35
7531 22:51:07.162724
7532 22:51:07.165884 [CBTSetCACLKResult] CA Dly = 35
7533 22:51:07.169447 CS Dly: 10 (0~43)
7534 22:51:07.172957 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 22:51:07.175858 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 22:51:07.175941
7537 22:51:07.179051 ----->DramcWriteLeveling(PI) begin...
7538 22:51:07.179136 ==
7539 22:51:07.182312 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 22:51:07.186344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 22:51:07.189286 ==
7542 22:51:07.192236 Write leveling (Byte 0): 37 => 37
7543 22:51:07.192320 Write leveling (Byte 1): 29 => 29
7544 22:51:07.195938 DramcWriteLeveling(PI) end<-----
7545 22:51:07.196021
7546 22:51:07.196088 ==
7547 22:51:07.199125 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 22:51:07.205717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 22:51:07.205801 ==
7550 22:51:07.209139 [Gating] SW mode calibration
7551 22:51:07.215608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7552 22:51:07.218968 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7553 22:51:07.225450 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 22:51:07.229094 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 22:51:07.232474 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7556 22:51:07.238838 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7557 22:51:07.242381 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7558 22:51:07.245360 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7559 22:51:07.252590 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 22:51:07.255455 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 22:51:07.258777 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 22:51:07.265505 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 22:51:07.268670 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
7564 22:51:07.271875 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7565 22:51:07.275303 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7566 22:51:07.281880 1 5 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
7567 22:51:07.285120 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 22:51:07.288698 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 22:51:07.295563 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 22:51:07.298747 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 22:51:07.302058 1 6 8 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
7572 22:51:07.308501 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7573 22:51:07.311889 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7574 22:51:07.315120 1 6 20 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7575 22:51:07.321760 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 22:51:07.324893 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 22:51:07.328620 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 22:51:07.335070 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 22:51:07.338589 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 22:51:07.341902 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7581 22:51:07.348424 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7582 22:51:07.351885 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7583 22:51:07.355053 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 22:51:07.361951 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 22:51:07.365047 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 22:51:07.368119 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 22:51:07.374784 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 22:51:07.378212 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 22:51:07.381535 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 22:51:07.388025 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 22:51:07.391571 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 22:51:07.395119 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 22:51:07.401458 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 22:51:07.404768 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 22:51:07.408000 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7596 22:51:07.415020 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7597 22:51:07.417839 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7598 22:51:07.421694 Total UI for P1: 0, mck2ui 16
7599 22:51:07.425101 best dqsien dly found for B0: ( 1, 9, 10)
7600 22:51:07.428326 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7601 22:51:07.431274 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 22:51:07.434976 Total UI for P1: 0, mck2ui 16
7603 22:51:07.437938 best dqsien dly found for B1: ( 1, 9, 20)
7604 22:51:07.441222 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7605 22:51:07.444552 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7606 22:51:07.448168
7607 22:51:07.451251 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7608 22:51:07.454838 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7609 22:51:07.458119 [Gating] SW calibration Done
7610 22:51:07.458192 ==
7611 22:51:07.461078 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 22:51:07.464938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 22:51:07.465044 ==
7614 22:51:07.468158 RX Vref Scan: 0
7615 22:51:07.468264
7616 22:51:07.468354 RX Vref 0 -> 0, step: 1
7617 22:51:07.468441
7618 22:51:07.471262 RX Delay 0 -> 252, step: 8
7619 22:51:07.474541 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7620 22:51:07.477898 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7621 22:51:07.484467 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7622 22:51:07.487772 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7623 22:51:07.491157 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7624 22:51:07.494392 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7625 22:51:07.497932 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7626 22:51:07.504390 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7627 22:51:07.507762 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7628 22:51:07.511195 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7629 22:51:07.514783 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7630 22:51:07.517731 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7631 22:51:07.524561 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7632 22:51:07.527731 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7633 22:51:07.531314 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7634 22:51:07.534459 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7635 22:51:07.534559 ==
7636 22:51:07.538165 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 22:51:07.541467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 22:51:07.541540 ==
7639 22:51:07.544467 DQS Delay:
7640 22:51:07.544563 DQS0 = 0, DQS1 = 0
7641 22:51:07.547824 DQM Delay:
7642 22:51:07.547924 DQM0 = 138, DQM1 = 126
7643 22:51:07.551144 DQ Delay:
7644 22:51:07.554735 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7645 22:51:07.557749 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7646 22:51:07.561244 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7647 22:51:07.564780 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7648 22:51:07.564888
7649 22:51:07.564980
7650 22:51:07.565067 ==
7651 22:51:07.567756 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 22:51:07.571116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 22:51:07.571216 ==
7654 22:51:07.571305
7655 22:51:07.571385
7656 22:51:07.574215 TX Vref Scan disable
7657 22:51:07.577627 == TX Byte 0 ==
7658 22:51:07.581175 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7659 22:51:07.584274 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7660 22:51:07.587905 == TX Byte 1 ==
7661 22:51:07.591184 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7662 22:51:07.594472 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7663 22:51:07.594574 ==
7664 22:51:07.597860 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 22:51:07.604377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 22:51:07.604476 ==
7667 22:51:07.617504
7668 22:51:07.621182 TX Vref early break, caculate TX vref
7669 22:51:07.624492 TX Vref=16, minBit 12, minWin=22, winSum=378
7670 22:51:07.627562 TX Vref=18, minBit 12, minWin=22, winSum=387
7671 22:51:07.631056 TX Vref=20, minBit 12, minWin=23, winSum=396
7672 22:51:07.634187 TX Vref=22, minBit 7, minWin=24, winSum=405
7673 22:51:07.637520 TX Vref=24, minBit 0, minWin=25, winSum=412
7674 22:51:07.644365 TX Vref=26, minBit 12, minWin=25, winSum=425
7675 22:51:07.647553 TX Vref=28, minBit 0, minWin=26, winSum=429
7676 22:51:07.650986 TX Vref=30, minBit 1, minWin=25, winSum=425
7677 22:51:07.654451 TX Vref=32, minBit 1, minWin=25, winSum=414
7678 22:51:07.657535 TX Vref=34, minBit 7, minWin=24, winSum=407
7679 22:51:07.664129 TX Vref=36, minBit 2, minWin=24, winSum=397
7680 22:51:07.667297 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
7681 22:51:07.667387
7682 22:51:07.670913 Final TX Range 0 Vref 28
7683 22:51:07.671015
7684 22:51:07.671114 ==
7685 22:51:07.673943 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 22:51:07.677303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 22:51:07.680468 ==
7688 22:51:07.680564
7689 22:51:07.680662
7690 22:51:07.680749 TX Vref Scan disable
7691 22:51:07.687334 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7692 22:51:07.687409 == TX Byte 0 ==
7693 22:51:07.690669 u2DelayCellOfst[0]=10 cells (3 PI)
7694 22:51:07.693962 u2DelayCellOfst[1]=13 cells (4 PI)
7695 22:51:07.697192 u2DelayCellOfst[2]=10 cells (3 PI)
7696 22:51:07.700566 u2DelayCellOfst[3]=10 cells (3 PI)
7697 22:51:07.703987 u2DelayCellOfst[4]=6 cells (2 PI)
7698 22:51:07.707012 u2DelayCellOfst[5]=0 cells (0 PI)
7699 22:51:07.710392 u2DelayCellOfst[6]=16 cells (5 PI)
7700 22:51:07.713887 u2DelayCellOfst[7]=13 cells (4 PI)
7701 22:51:07.716976 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7702 22:51:07.720459 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7703 22:51:07.723861 == TX Byte 1 ==
7704 22:51:07.727106 u2DelayCellOfst[8]=0 cells (0 PI)
7705 22:51:07.730374 u2DelayCellOfst[9]=0 cells (0 PI)
7706 22:51:07.733613 u2DelayCellOfst[10]=6 cells (2 PI)
7707 22:51:07.737150 u2DelayCellOfst[11]=3 cells (1 PI)
7708 22:51:07.737259 u2DelayCellOfst[12]=13 cells (4 PI)
7709 22:51:07.740485 u2DelayCellOfst[13]=13 cells (4 PI)
7710 22:51:07.743588 u2DelayCellOfst[14]=13 cells (4 PI)
7711 22:51:07.747007 u2DelayCellOfst[15]=10 cells (3 PI)
7712 22:51:07.753467 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7713 22:51:07.757112 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7714 22:51:07.757219 DramC Write-DBI on
7715 22:51:07.760470 ==
7716 22:51:07.760571 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 22:51:07.766935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 22:51:07.767055 ==
7719 22:51:07.767147
7720 22:51:07.767243
7721 22:51:07.770359 TX Vref Scan disable
7722 22:51:07.770433 == TX Byte 0 ==
7723 22:51:07.776950 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7724 22:51:07.777053 == TX Byte 1 ==
7725 22:51:07.779969 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7726 22:51:07.783697 DramC Write-DBI off
7727 22:51:07.783795
7728 22:51:07.783894 [DATLAT]
7729 22:51:07.786886 Freq=1600, CH0 RK0
7730 22:51:07.787003
7731 22:51:07.787100 DATLAT Default: 0xf
7732 22:51:07.790297 0, 0xFFFF, sum = 0
7733 22:51:07.790398 1, 0xFFFF, sum = 0
7734 22:51:07.793725 2, 0xFFFF, sum = 0
7735 22:51:07.793801 3, 0xFFFF, sum = 0
7736 22:51:07.796793 4, 0xFFFF, sum = 0
7737 22:51:07.796894 5, 0xFFFF, sum = 0
7738 22:51:07.800255 6, 0xFFFF, sum = 0
7739 22:51:07.800356 7, 0xFFFF, sum = 0
7740 22:51:07.803499 8, 0xFFFF, sum = 0
7741 22:51:07.807045 9, 0xFFFF, sum = 0
7742 22:51:07.807147 10, 0xFFFF, sum = 0
7743 22:51:07.809786 11, 0xFFFF, sum = 0
7744 22:51:07.809860 12, 0xFFFF, sum = 0
7745 22:51:07.813634 13, 0xFFFF, sum = 0
7746 22:51:07.813743 14, 0x0, sum = 1
7747 22:51:07.816618 15, 0x0, sum = 2
7748 22:51:07.816724 16, 0x0, sum = 3
7749 22:51:07.819904 17, 0x0, sum = 4
7750 22:51:07.819989 best_step = 15
7751 22:51:07.820055
7752 22:51:07.820115 ==
7753 22:51:07.823529 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 22:51:07.826485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 22:51:07.826569 ==
7756 22:51:07.829961 RX Vref Scan: 1
7757 22:51:07.830043
7758 22:51:07.833163 Set Vref Range= 24 -> 127
7759 22:51:07.833245
7760 22:51:07.833347 RX Vref 24 -> 127, step: 1
7761 22:51:07.833411
7762 22:51:07.836688 RX Delay 19 -> 252, step: 4
7763 22:51:07.836771
7764 22:51:07.839791 Set Vref, RX VrefLevel [Byte0]: 24
7765 22:51:07.843323 [Byte1]: 24
7766 22:51:07.846318
7767 22:51:07.846401 Set Vref, RX VrefLevel [Byte0]: 25
7768 22:51:07.849994 [Byte1]: 25
7769 22:51:07.854241
7770 22:51:07.854324 Set Vref, RX VrefLevel [Byte0]: 26
7771 22:51:07.857480 [Byte1]: 26
7772 22:51:07.861852
7773 22:51:07.861934 Set Vref, RX VrefLevel [Byte0]: 27
7774 22:51:07.865268 [Byte1]: 27
7775 22:51:07.869036
7776 22:51:07.869119 Set Vref, RX VrefLevel [Byte0]: 28
7777 22:51:07.872363 [Byte1]: 28
7778 22:51:07.876662
7779 22:51:07.876744 Set Vref, RX VrefLevel [Byte0]: 29
7780 22:51:07.880010 [Byte1]: 29
7781 22:51:07.884400
7782 22:51:07.884483 Set Vref, RX VrefLevel [Byte0]: 30
7783 22:51:07.887676 [Byte1]: 30
7784 22:51:07.891962
7785 22:51:07.892045 Set Vref, RX VrefLevel [Byte0]: 31
7786 22:51:07.895096 [Byte1]: 31
7787 22:51:07.899828
7788 22:51:07.899911 Set Vref, RX VrefLevel [Byte0]: 32
7789 22:51:07.902606 [Byte1]: 32
7790 22:51:07.907427
7791 22:51:07.907510 Set Vref, RX VrefLevel [Byte0]: 33
7792 22:51:07.910370 [Byte1]: 33
7793 22:51:07.914803
7794 22:51:07.914886 Set Vref, RX VrefLevel [Byte0]: 34
7795 22:51:07.917777 [Byte1]: 34
7796 22:51:07.922431
7797 22:51:07.922514 Set Vref, RX VrefLevel [Byte0]: 35
7798 22:51:07.925365 [Byte1]: 35
7799 22:51:07.929679
7800 22:51:07.929761 Set Vref, RX VrefLevel [Byte0]: 36
7801 22:51:07.933488 [Byte1]: 36
7802 22:51:07.937362
7803 22:51:07.937445 Set Vref, RX VrefLevel [Byte0]: 37
7804 22:51:07.940680 [Byte1]: 37
7805 22:51:07.944904
7806 22:51:07.944987 Set Vref, RX VrefLevel [Byte0]: 38
7807 22:51:07.948158 [Byte1]: 38
7808 22:51:07.952375
7809 22:51:07.952459 Set Vref, RX VrefLevel [Byte0]: 39
7810 22:51:07.955728 [Byte1]: 39
7811 22:51:07.960459
7812 22:51:07.960543 Set Vref, RX VrefLevel [Byte0]: 40
7813 22:51:07.963601 [Byte1]: 40
7814 22:51:07.967480
7815 22:51:07.967563 Set Vref, RX VrefLevel [Byte0]: 41
7816 22:51:07.974256 [Byte1]: 41
7817 22:51:07.974344
7818 22:51:07.977304 Set Vref, RX VrefLevel [Byte0]: 42
7819 22:51:07.980765 [Byte1]: 42
7820 22:51:07.980875
7821 22:51:07.984047 Set Vref, RX VrefLevel [Byte0]: 43
7822 22:51:07.987447 [Byte1]: 43
7823 22:51:07.987531
7824 22:51:07.990582 Set Vref, RX VrefLevel [Byte0]: 44
7825 22:51:07.993941 [Byte1]: 44
7826 22:51:07.997819
7827 22:51:07.997902 Set Vref, RX VrefLevel [Byte0]: 45
7828 22:51:08.001074 [Byte1]: 45
7829 22:51:08.005683
7830 22:51:08.005766 Set Vref, RX VrefLevel [Byte0]: 46
7831 22:51:08.008794 [Byte1]: 46
7832 22:51:08.012912
7833 22:51:08.012995 Set Vref, RX VrefLevel [Byte0]: 47
7834 22:51:08.016390 [Byte1]: 47
7835 22:51:08.020724
7836 22:51:08.020808 Set Vref, RX VrefLevel [Byte0]: 48
7837 22:51:08.023850 [Byte1]: 48
7838 22:51:08.028193
7839 22:51:08.028277 Set Vref, RX VrefLevel [Byte0]: 49
7840 22:51:08.031772 [Byte1]: 49
7841 22:51:08.036054
7842 22:51:08.036138 Set Vref, RX VrefLevel [Byte0]: 50
7843 22:51:08.039345 [Byte1]: 50
7844 22:51:08.043168
7845 22:51:08.043252 Set Vref, RX VrefLevel [Byte0]: 51
7846 22:51:08.046973 [Byte1]: 51
7847 22:51:08.051128
7848 22:51:08.051212 Set Vref, RX VrefLevel [Byte0]: 52
7849 22:51:08.054546 [Byte1]: 52
7850 22:51:08.058250
7851 22:51:08.058334 Set Vref, RX VrefLevel [Byte0]: 53
7852 22:51:08.061784 [Byte1]: 53
7853 22:51:08.065890
7854 22:51:08.065973 Set Vref, RX VrefLevel [Byte0]: 54
7855 22:51:08.069467 [Byte1]: 54
7856 22:51:08.073699
7857 22:51:08.073782 Set Vref, RX VrefLevel [Byte0]: 55
7858 22:51:08.077247 [Byte1]: 55
7859 22:51:08.081440
7860 22:51:08.081524 Set Vref, RX VrefLevel [Byte0]: 56
7861 22:51:08.084733 [Byte1]: 56
7862 22:51:08.088677
7863 22:51:08.088761 Set Vref, RX VrefLevel [Byte0]: 57
7864 22:51:08.092310 [Byte1]: 57
7865 22:51:08.096487
7866 22:51:08.096571 Set Vref, RX VrefLevel [Byte0]: 58
7867 22:51:08.099686 [Byte1]: 58
7868 22:51:08.103811
7869 22:51:08.103895 Set Vref, RX VrefLevel [Byte0]: 59
7870 22:51:08.107106 [Byte1]: 59
7871 22:51:08.111692
7872 22:51:08.111776 Set Vref, RX VrefLevel [Byte0]: 60
7873 22:51:08.115015 [Byte1]: 60
7874 22:51:08.119179
7875 22:51:08.119262 Set Vref, RX VrefLevel [Byte0]: 61
7876 22:51:08.122425 [Byte1]: 61
7877 22:51:08.126642
7878 22:51:08.126726 Set Vref, RX VrefLevel [Byte0]: 62
7879 22:51:08.129886 [Byte1]: 62
7880 22:51:08.134230
7881 22:51:08.134314 Set Vref, RX VrefLevel [Byte0]: 63
7882 22:51:08.137482 [Byte1]: 63
7883 22:51:08.141587
7884 22:51:08.141671 Set Vref, RX VrefLevel [Byte0]: 64
7885 22:51:08.145012 [Byte1]: 64
7886 22:51:08.149871
7887 22:51:08.149955 Set Vref, RX VrefLevel [Byte0]: 65
7888 22:51:08.152797 [Byte1]: 65
7889 22:51:08.157312
7890 22:51:08.157450 Set Vref, RX VrefLevel [Byte0]: 66
7891 22:51:08.160492 [Byte1]: 66
7892 22:51:08.164646
7893 22:51:08.164730 Set Vref, RX VrefLevel [Byte0]: 67
7894 22:51:08.168192 [Byte1]: 67
7895 22:51:08.171923
7896 22:51:08.172007 Set Vref, RX VrefLevel [Byte0]: 68
7897 22:51:08.175492 [Byte1]: 68
7898 22:51:08.179777
7899 22:51:08.179860 Set Vref, RX VrefLevel [Byte0]: 69
7900 22:51:08.183058 [Byte1]: 69
7901 22:51:08.187374
7902 22:51:08.187458 Set Vref, RX VrefLevel [Byte0]: 70
7903 22:51:08.190608 [Byte1]: 70
7904 22:51:08.194946
7905 22:51:08.195030 Set Vref, RX VrefLevel [Byte0]: 71
7906 22:51:08.197975 [Byte1]: 71
7907 22:51:08.202393
7908 22:51:08.205472 Set Vref, RX VrefLevel [Byte0]: 72
7909 22:51:08.209118 [Byte1]: 72
7910 22:51:08.209202
7911 22:51:08.211892 Set Vref, RX VrefLevel [Byte0]: 73
7912 22:51:08.215269 [Byte1]: 73
7913 22:51:08.215353
7914 22:51:08.218884 Set Vref, RX VrefLevel [Byte0]: 74
7915 22:51:08.222281 [Byte1]: 74
7916 22:51:08.222366
7917 22:51:08.225244 Set Vref, RX VrefLevel [Byte0]: 75
7918 22:51:08.228486 [Byte1]: 75
7919 22:51:08.232961
7920 22:51:08.233046 Set Vref, RX VrefLevel [Byte0]: 76
7921 22:51:08.235911 [Byte1]: 76
7922 22:51:08.240640
7923 22:51:08.240724 Set Vref, RX VrefLevel [Byte0]: 77
7924 22:51:08.243894 [Byte1]: 77
7925 22:51:08.247648
7926 22:51:08.247732 Set Vref, RX VrefLevel [Byte0]: 78
7927 22:51:08.251075 [Byte1]: 78
7928 22:51:08.255262
7929 22:51:08.255345 Set Vref, RX VrefLevel [Byte0]: 79
7930 22:51:08.258576 [Byte1]: 79
7931 22:51:08.263022
7932 22:51:08.263105 Set Vref, RX VrefLevel [Byte0]: 80
7933 22:51:08.266292 [Byte1]: 80
7934 22:51:08.270716
7935 22:51:08.270799 Final RX Vref Byte 0 = 58 to rank0
7936 22:51:08.273914 Final RX Vref Byte 1 = 60 to rank0
7937 22:51:08.277206 Final RX Vref Byte 0 = 58 to rank1
7938 22:51:08.280310 Final RX Vref Byte 1 = 60 to rank1==
7939 22:51:08.283905 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 22:51:08.290676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 22:51:08.290762 ==
7942 22:51:08.290829 DQS Delay:
7943 22:51:08.290888 DQS0 = 0, DQS1 = 0
7944 22:51:08.293904 DQM Delay:
7945 22:51:08.293987 DQM0 = 136, DQM1 = 124
7946 22:51:08.297118 DQ Delay:
7947 22:51:08.300457 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7948 22:51:08.303562 DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144
7949 22:51:08.307127 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7950 22:51:08.310108 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7951 22:51:08.310194
7952 22:51:08.310261
7953 22:51:08.310322
7954 22:51:08.313530 [DramC_TX_OE_Calibration] TA2
7955 22:51:08.317020 Original DQ_B0 (3 6) =30, OEN = 27
7956 22:51:08.320854 Original DQ_B1 (3 6) =30, OEN = 27
7957 22:51:08.323615 24, 0x0, End_B0=24 End_B1=24
7958 22:51:08.323701 25, 0x0, End_B0=25 End_B1=25
7959 22:51:08.326776 26, 0x0, End_B0=26 End_B1=26
7960 22:51:08.330259 27, 0x0, End_B0=27 End_B1=27
7961 22:51:08.333553 28, 0x0, End_B0=28 End_B1=28
7962 22:51:08.333639 29, 0x0, End_B0=29 End_B1=29
7963 22:51:08.336963 30, 0x0, End_B0=30 End_B1=30
7964 22:51:08.340169 31, 0x4141, End_B0=30 End_B1=30
7965 22:51:08.343855 Byte0 end_step=30 best_step=27
7966 22:51:08.347226 Byte1 end_step=30 best_step=27
7967 22:51:08.350269 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 22:51:08.350353 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 22:51:08.353782
7970 22:51:08.353866
7971 22:51:08.360350 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7972 22:51:08.363947 CH0 RK0: MR19=303, MR18=1D1B
7973 22:51:08.370225 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7974 22:51:08.370310
7975 22:51:08.373412 ----->DramcWriteLeveling(PI) begin...
7976 22:51:08.373498 ==
7977 22:51:08.376819 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 22:51:08.380418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 22:51:08.380503 ==
7980 22:51:08.383796 Write leveling (Byte 0): 38 => 38
7981 22:51:08.387356 Write leveling (Byte 1): 29 => 29
7982 22:51:08.390300 DramcWriteLeveling(PI) end<-----
7983 22:51:08.390383
7984 22:51:08.390449 ==
7985 22:51:08.393323 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 22:51:08.396883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 22:51:08.396967 ==
7988 22:51:08.400118 [Gating] SW mode calibration
7989 22:51:08.406517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 22:51:08.413393 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 22:51:08.416431 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 22:51:08.419923 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 22:51:08.426580 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 22:51:08.429915 1 4 12 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
7995 22:51:08.433255 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7996 22:51:08.439907 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 22:51:08.443150 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 22:51:08.446825 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 22:51:08.453451 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 22:51:08.456719 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 22:51:08.459950 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8002 22:51:08.466833 1 5 12 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (0 1)
8003 22:51:08.469746 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8004 22:51:08.473227 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 22:51:08.480218 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 22:51:08.483053 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 22:51:08.486556 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 22:51:08.493509 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 22:51:08.496488 1 6 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8010 22:51:08.499822 1 6 12 | B1->B0 | 2e2e 4444 | 0 0 | (0 0) (0 0)
8011 22:51:08.506511 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 22:51:08.509943 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 22:51:08.513100 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 22:51:08.516749 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 22:51:08.522989 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 22:51:08.526640 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 22:51:08.530216 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8018 22:51:08.536452 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8019 22:51:08.539561 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8020 22:51:08.543000 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 22:51:08.550109 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 22:51:08.553142 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 22:51:08.556167 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 22:51:08.563248 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 22:51:08.566267 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 22:51:08.569584 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 22:51:08.576074 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 22:51:08.579569 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 22:51:08.582796 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 22:51:08.589265 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 22:51:08.592560 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 22:51:08.596111 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 22:51:08.602632 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 22:51:08.605998 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8035 22:51:08.609206 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8036 22:51:08.612766 Total UI for P1: 0, mck2ui 16
8037 22:51:08.615966 best dqsien dly found for B0: ( 1, 9, 10)
8038 22:51:08.622813 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 22:51:08.622891 Total UI for P1: 0, mck2ui 16
8040 22:51:08.625958 best dqsien dly found for B1: ( 1, 9, 14)
8041 22:51:08.632667 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8042 22:51:08.635845 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8043 22:51:08.635918
8044 22:51:08.639403 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8045 22:51:08.642924 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8046 22:51:08.645724 [Gating] SW calibration Done
8047 22:51:08.645795 ==
8048 22:51:08.649366 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 22:51:08.652755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 22:51:08.652829 ==
8051 22:51:08.655794 RX Vref Scan: 0
8052 22:51:08.655870
8053 22:51:08.655932 RX Vref 0 -> 0, step: 1
8054 22:51:08.655994
8055 22:51:08.659168 RX Delay 0 -> 252, step: 8
8056 22:51:08.662574 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8057 22:51:08.669231 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8058 22:51:08.672241 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8059 22:51:08.675809 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8060 22:51:08.678887 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8061 22:51:08.682223 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8062 22:51:08.689332 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8063 22:51:08.692374 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8064 22:51:08.695384 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8065 22:51:08.698878 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8066 22:51:08.702240 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8067 22:51:08.708999 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8068 22:51:08.712332 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8069 22:51:08.715558 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8070 22:51:08.718680 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8071 22:51:08.721937 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8072 22:51:08.725516 ==
8073 22:51:08.728572 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 22:51:08.732254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 22:51:08.732356 ==
8076 22:51:08.732448 DQS Delay:
8077 22:51:08.735107 DQS0 = 0, DQS1 = 0
8078 22:51:08.735187 DQM Delay:
8079 22:51:08.738740 DQM0 = 136, DQM1 = 125
8080 22:51:08.738816 DQ Delay:
8081 22:51:08.741885 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8082 22:51:08.745116 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8083 22:51:08.748892 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8084 22:51:08.751826 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8085 22:51:08.751931
8086 22:51:08.752035
8087 22:51:08.752117 ==
8088 22:51:08.755152 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 22:51:08.762027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 22:51:08.762109 ==
8091 22:51:08.762174
8092 22:51:08.762233
8093 22:51:08.762290 TX Vref Scan disable
8094 22:51:08.765409 == TX Byte 0 ==
8095 22:51:08.768793 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8096 22:51:08.775417 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8097 22:51:08.775492 == TX Byte 1 ==
8098 22:51:08.778774 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8099 22:51:08.785823 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8100 22:51:08.785901 ==
8101 22:51:08.788732 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 22:51:08.792061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 22:51:08.792139 ==
8104 22:51:08.807049
8105 22:51:08.810356 TX Vref early break, caculate TX vref
8106 22:51:08.813477 TX Vref=16, minBit 8, minWin=22, winSum=387
8107 22:51:08.816680 TX Vref=18, minBit 8, minWin=23, winSum=398
8108 22:51:08.820079 TX Vref=20, minBit 0, minWin=25, winSum=407
8109 22:51:08.823613 TX Vref=22, minBit 0, minWin=25, winSum=414
8110 22:51:08.826864 TX Vref=24, minBit 0, minWin=25, winSum=423
8111 22:51:08.833730 TX Vref=26, minBit 0, minWin=26, winSum=427
8112 22:51:08.836741 TX Vref=28, minBit 0, minWin=26, winSum=430
8113 22:51:08.840073 TX Vref=30, minBit 8, minWin=25, winSum=427
8114 22:51:08.843461 TX Vref=32, minBit 0, minWin=25, winSum=418
8115 22:51:08.846910 TX Vref=34, minBit 2, minWin=24, winSum=408
8116 22:51:08.850293 TX Vref=36, minBit 0, minWin=24, winSum=401
8117 22:51:08.856680 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8118 22:51:08.856755
8119 22:51:08.860059 Final TX Range 0 Vref 28
8120 22:51:08.860134
8121 22:51:08.860212 ==
8122 22:51:08.863723 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 22:51:08.867066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 22:51:08.867142 ==
8125 22:51:08.867205
8126 22:51:08.867263
8127 22:51:08.870276 TX Vref Scan disable
8128 22:51:08.876881 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8129 22:51:08.876957 == TX Byte 0 ==
8130 22:51:08.880175 u2DelayCellOfst[0]=13 cells (4 PI)
8131 22:51:08.883459 u2DelayCellOfst[1]=20 cells (6 PI)
8132 22:51:08.886919 u2DelayCellOfst[2]=13 cells (4 PI)
8133 22:51:08.889935 u2DelayCellOfst[3]=13 cells (4 PI)
8134 22:51:08.893188 u2DelayCellOfst[4]=10 cells (3 PI)
8135 22:51:08.896850 u2DelayCellOfst[5]=0 cells (0 PI)
8136 22:51:08.899947 u2DelayCellOfst[6]=20 cells (6 PI)
8137 22:51:08.903317 u2DelayCellOfst[7]=20 cells (6 PI)
8138 22:51:08.906707 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8139 22:51:08.909791 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8140 22:51:08.913145 == TX Byte 1 ==
8141 22:51:08.916847 u2DelayCellOfst[8]=0 cells (0 PI)
8142 22:51:08.916951 u2DelayCellOfst[9]=0 cells (0 PI)
8143 22:51:08.920061 u2DelayCellOfst[10]=3 cells (1 PI)
8144 22:51:08.923110 u2DelayCellOfst[11]=0 cells (0 PI)
8145 22:51:08.926751 u2DelayCellOfst[12]=10 cells (3 PI)
8146 22:51:08.929693 u2DelayCellOfst[13]=10 cells (3 PI)
8147 22:51:08.933205 u2DelayCellOfst[14]=10 cells (3 PI)
8148 22:51:08.936386 u2DelayCellOfst[15]=6 cells (2 PI)
8149 22:51:08.939991 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8150 22:51:08.946744 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8151 22:51:08.946821 DramC Write-DBI on
8152 22:51:08.946883 ==
8153 22:51:08.950188 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 22:51:08.956299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 22:51:08.956374 ==
8156 22:51:08.956435
8157 22:51:08.956496
8158 22:51:08.956551 TX Vref Scan disable
8159 22:51:08.960332 == TX Byte 0 ==
8160 22:51:08.963344 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8161 22:51:08.967272 == TX Byte 1 ==
8162 22:51:08.970244 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8163 22:51:08.970318 DramC Write-DBI off
8164 22:51:08.973377
8165 22:51:08.973448 [DATLAT]
8166 22:51:08.973512 Freq=1600, CH0 RK1
8167 22:51:08.973569
8168 22:51:08.976982 DATLAT Default: 0xf
8169 22:51:08.977077 0, 0xFFFF, sum = 0
8170 22:51:08.980078 1, 0xFFFF, sum = 0
8171 22:51:08.980150 2, 0xFFFF, sum = 0
8172 22:51:08.983484 3, 0xFFFF, sum = 0
8173 22:51:08.986545 4, 0xFFFF, sum = 0
8174 22:51:08.986617 5, 0xFFFF, sum = 0
8175 22:51:08.990193 6, 0xFFFF, sum = 0
8176 22:51:08.990268 7, 0xFFFF, sum = 0
8177 22:51:08.993370 8, 0xFFFF, sum = 0
8178 22:51:08.993480 9, 0xFFFF, sum = 0
8179 22:51:08.996881 10, 0xFFFF, sum = 0
8180 22:51:08.996983 11, 0xFFFF, sum = 0
8181 22:51:09.000282 12, 0xFFFF, sum = 0
8182 22:51:09.000360 13, 0xFFFF, sum = 0
8183 22:51:09.003243 14, 0x0, sum = 1
8184 22:51:09.003318 15, 0x0, sum = 2
8185 22:51:09.006862 16, 0x0, sum = 3
8186 22:51:09.006937 17, 0x0, sum = 4
8187 22:51:09.010080 best_step = 15
8188 22:51:09.010152
8189 22:51:09.010211 ==
8190 22:51:09.013267 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 22:51:09.016885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 22:51:09.016958 ==
8193 22:51:09.017020 RX Vref Scan: 0
8194 22:51:09.019965
8195 22:51:09.020035 RX Vref 0 -> 0, step: 1
8196 22:51:09.020097
8197 22:51:09.023351 RX Delay 11 -> 252, step: 4
8198 22:51:09.026620 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8199 22:51:09.033378 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8200 22:51:09.037132 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8201 22:51:09.040296 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8202 22:51:09.043577 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8203 22:51:09.046773 iDelay=191, Bit 5, Center 122 (71 ~ 174) 104
8204 22:51:09.050204 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8205 22:51:09.056938 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8206 22:51:09.060165 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8207 22:51:09.063544 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8208 22:51:09.066709 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8209 22:51:09.070429 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8210 22:51:09.077108 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8211 22:51:09.079911 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8212 22:51:09.083477 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8213 22:51:09.086930 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8214 22:51:09.087005 ==
8215 22:51:09.090359 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 22:51:09.096490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 22:51:09.096569 ==
8218 22:51:09.096634 DQS Delay:
8219 22:51:09.100086 DQS0 = 0, DQS1 = 0
8220 22:51:09.100158 DQM Delay:
8221 22:51:09.103433 DQM0 = 132, DQM1 = 123
8222 22:51:09.103507 DQ Delay:
8223 22:51:09.106430 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8224 22:51:09.109941 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =138
8225 22:51:09.113042 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8226 22:51:09.116394 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8227 22:51:09.116472
8228 22:51:09.116535
8229 22:51:09.116593
8230 22:51:09.119815 [DramC_TX_OE_Calibration] TA2
8231 22:51:09.123400 Original DQ_B0 (3 6) =30, OEN = 27
8232 22:51:09.126369 Original DQ_B1 (3 6) =30, OEN = 27
8233 22:51:09.129819 24, 0x0, End_B0=24 End_B1=24
8234 22:51:09.132879 25, 0x0, End_B0=25 End_B1=25
8235 22:51:09.132952 26, 0x0, End_B0=26 End_B1=26
8236 22:51:09.136581 27, 0x0, End_B0=27 End_B1=27
8237 22:51:09.139577 28, 0x0, End_B0=28 End_B1=28
8238 22:51:09.142869 29, 0x0, End_B0=29 End_B1=29
8239 22:51:09.142943 30, 0x0, End_B0=30 End_B1=30
8240 22:51:09.146281 31, 0x4141, End_B0=30 End_B1=30
8241 22:51:09.149646 Byte0 end_step=30 best_step=27
8242 22:51:09.153042 Byte1 end_step=30 best_step=27
8243 22:51:09.156309 Byte0 TX OE(2T, 0.5T) = (3, 3)
8244 22:51:09.159702 Byte1 TX OE(2T, 0.5T) = (3, 3)
8245 22:51:09.159777
8246 22:51:09.159839
8247 22:51:09.166412 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8248 22:51:09.169661 CH0 RK1: MR19=303, MR18=200D
8249 22:51:09.175980 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8250 22:51:09.179592 [RxdqsGatingPostProcess] freq 1600
8251 22:51:09.182936 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8252 22:51:09.185972 best DQS0 dly(2T, 0.5T) = (1, 1)
8253 22:51:09.189695 best DQS1 dly(2T, 0.5T) = (1, 1)
8254 22:51:09.192782 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8255 22:51:09.196103 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8256 22:51:09.199584 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 22:51:09.203041 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 22:51:09.206168 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 22:51:09.209283 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 22:51:09.212842 Pre-setting of DQS Precalculation
8261 22:51:09.216210 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8262 22:51:09.216312 ==
8263 22:51:09.219189 Dram Type= 6, Freq= 0, CH_1, rank 0
8264 22:51:09.225814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 22:51:09.225895 ==
8266 22:51:09.229035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8267 22:51:09.235540 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8268 22:51:09.238988 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8269 22:51:09.245441 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8270 22:51:09.253203 [CA 0] Center 42 (12~72) winsize 61
8271 22:51:09.256623 [CA 1] Center 42 (12~72) winsize 61
8272 22:51:09.260067 [CA 2] Center 38 (9~67) winsize 59
8273 22:51:09.263304 [CA 3] Center 37 (8~67) winsize 60
8274 22:51:09.266801 [CA 4] Center 37 (7~67) winsize 61
8275 22:51:09.269863 [CA 5] Center 37 (7~67) winsize 61
8276 22:51:09.269937
8277 22:51:09.273272 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8278 22:51:09.273358
8279 22:51:09.276433 [CATrainingPosCal] consider 1 rank data
8280 22:51:09.279713 u2DelayCellTimex100 = 290/100 ps
8281 22:51:09.283276 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8282 22:51:09.289647 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8283 22:51:09.293283 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8284 22:51:09.296313 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8285 22:51:09.299669 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
8286 22:51:09.302947 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8287 22:51:09.303031
8288 22:51:09.306646 CA PerBit enable=1, Macro0, CA PI delay=37
8289 22:51:09.306729
8290 22:51:09.309717 [CBTSetCACLKResult] CA Dly = 37
8291 22:51:09.313132 CS Dly: 8 (0~39)
8292 22:51:09.316531 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8293 22:51:09.319382 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8294 22:51:09.319464 ==
8295 22:51:09.323208 Dram Type= 6, Freq= 0, CH_1, rank 1
8296 22:51:09.326200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 22:51:09.329339 ==
8298 22:51:09.333055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8299 22:51:09.336043 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8300 22:51:09.342710 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8301 22:51:09.345906 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8302 22:51:09.356284 [CA 0] Center 42 (13~72) winsize 60
8303 22:51:09.359810 [CA 1] Center 42 (12~72) winsize 61
8304 22:51:09.362872 [CA 2] Center 38 (9~67) winsize 59
8305 22:51:09.366270 [CA 3] Center 37 (8~67) winsize 60
8306 22:51:09.369912 [CA 4] Center 37 (8~67) winsize 60
8307 22:51:09.372866 [CA 5] Center 37 (8~67) winsize 60
8308 22:51:09.372948
8309 22:51:09.376130 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8310 22:51:09.376211
8311 22:51:09.379576 [CATrainingPosCal] consider 2 rank data
8312 22:51:09.382887 u2DelayCellTimex100 = 290/100 ps
8313 22:51:09.386446 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8314 22:51:09.392830 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8315 22:51:09.396449 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8316 22:51:09.399932 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8317 22:51:09.402757 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8318 22:51:09.406238 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8319 22:51:09.406320
8320 22:51:09.409483 CA PerBit enable=1, Macro0, CA PI delay=37
8321 22:51:09.409565
8322 22:51:09.412972 [CBTSetCACLKResult] CA Dly = 37
8323 22:51:09.416108 CS Dly: 9 (0~42)
8324 22:51:09.419687 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8325 22:51:09.422821 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8326 22:51:09.422903
8327 22:51:09.426273 ----->DramcWriteLeveling(PI) begin...
8328 22:51:09.426357 ==
8329 22:51:09.429692 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 22:51:09.433021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 22:51:09.433104 ==
8332 22:51:09.436197 Write leveling (Byte 0): 25 => 25
8333 22:51:09.439772 Write leveling (Byte 1): 28 => 28
8334 22:51:09.443138 DramcWriteLeveling(PI) end<-----
8335 22:51:09.443219
8336 22:51:09.443283 ==
8337 22:51:09.446096 Dram Type= 6, Freq= 0, CH_1, rank 0
8338 22:51:09.453065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 22:51:09.453147 ==
8340 22:51:09.453211 [Gating] SW mode calibration
8341 22:51:09.463023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8342 22:51:09.466419 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8343 22:51:09.469594 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 22:51:09.475855 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 22:51:09.479114 1 4 8 | B1->B0 | 2c2c 2f2f | 1 1 | (1 1) (1 1)
8346 22:51:09.482523 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 22:51:09.489478 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 22:51:09.492442 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 22:51:09.495683 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 22:51:09.502969 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 22:51:09.506208 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 22:51:09.509131 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8353 22:51:09.516068 1 5 8 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (0 1)
8354 22:51:09.519464 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8355 22:51:09.522641 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 22:51:09.529277 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 22:51:09.532955 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 22:51:09.536178 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 22:51:09.542738 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 22:51:09.545934 1 6 4 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
8361 22:51:09.549229 1 6 8 | B1->B0 | 3b3b 4545 | 0 0 | (1 1) (0 0)
8362 22:51:09.556151 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 22:51:09.559356 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 22:51:09.562729 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 22:51:09.569341 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 22:51:09.572750 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 22:51:09.576262 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 22:51:09.582465 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8369 22:51:09.585842 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8370 22:51:09.588949 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 22:51:09.592317 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 22:51:09.599246 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 22:51:09.602540 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 22:51:09.605759 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 22:51:09.612393 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 22:51:09.615886 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 22:51:09.619072 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 22:51:09.625743 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 22:51:09.628777 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 22:51:09.632176 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 22:51:09.638864 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 22:51:09.641949 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 22:51:09.645562 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 22:51:09.652174 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8385 22:51:09.655372 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8386 22:51:09.658681 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8387 22:51:09.662045 Total UI for P1: 0, mck2ui 16
8388 22:51:09.665448 best dqsien dly found for B0: ( 1, 9, 6)
8389 22:51:09.671832 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 22:51:09.671917 Total UI for P1: 0, mck2ui 16
8391 22:51:09.678634 best dqsien dly found for B1: ( 1, 9, 10)
8392 22:51:09.682261 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8393 22:51:09.685231 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8394 22:51:09.685343
8395 22:51:09.688786 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8396 22:51:09.692006 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8397 22:51:09.695275 [Gating] SW calibration Done
8398 22:51:09.695385 ==
8399 22:51:09.698696 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 22:51:09.702015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 22:51:09.702100 ==
8402 22:51:09.705212 RX Vref Scan: 0
8403 22:51:09.705358
8404 22:51:09.705427 RX Vref 0 -> 0, step: 1
8405 22:51:09.705491
8406 22:51:09.708593 RX Delay 0 -> 252, step: 8
8407 22:51:09.711824 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8408 22:51:09.718629 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8409 22:51:09.721843 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8410 22:51:09.725486 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8411 22:51:09.728779 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8412 22:51:09.732139 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8413 22:51:09.735159 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8414 22:51:09.742019 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8415 22:51:09.745425 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8416 22:51:09.748610 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8417 22:51:09.751850 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8418 22:51:09.755216 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8419 22:51:09.761737 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8420 22:51:09.765248 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8421 22:51:09.768388 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8422 22:51:09.771676 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8423 22:51:09.771784 ==
8424 22:51:09.775254 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 22:51:09.782065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 22:51:09.782146 ==
8427 22:51:09.782211 DQS Delay:
8428 22:51:09.782272 DQS0 = 0, DQS1 = 0
8429 22:51:09.785012 DQM Delay:
8430 22:51:09.785175 DQM0 = 138, DQM1 = 130
8431 22:51:09.788213 DQ Delay:
8432 22:51:09.791762 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8433 22:51:09.794986 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8434 22:51:09.798582 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8435 22:51:09.801910 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8436 22:51:09.801985
8437 22:51:09.802047
8438 22:51:09.802105 ==
8439 22:51:09.804843 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 22:51:09.808487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 22:51:09.811625 ==
8442 22:51:09.811695
8443 22:51:09.811755
8444 22:51:09.811812 TX Vref Scan disable
8445 22:51:09.814944 == TX Byte 0 ==
8446 22:51:09.818438 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8447 22:51:09.821471 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8448 22:51:09.824793 == TX Byte 1 ==
8449 22:51:09.828584 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8450 22:51:09.831479 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8451 22:51:09.831583 ==
8452 22:51:09.835259 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 22:51:09.841755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 22:51:09.841842 ==
8455 22:51:09.852879
8456 22:51:09.856268 TX Vref early break, caculate TX vref
8457 22:51:09.859649 TX Vref=16, minBit 8, minWin=21, winSum=365
8458 22:51:09.863204 TX Vref=18, minBit 15, minWin=21, winSum=379
8459 22:51:09.866370 TX Vref=20, minBit 10, minWin=23, winSum=388
8460 22:51:09.869707 TX Vref=22, minBit 10, minWin=23, winSum=395
8461 22:51:09.876261 TX Vref=24, minBit 10, minWin=24, winSum=410
8462 22:51:09.879882 TX Vref=26, minBit 10, minWin=24, winSum=413
8463 22:51:09.882772 TX Vref=28, minBit 10, minWin=25, winSum=420
8464 22:51:09.886292 TX Vref=30, minBit 9, minWin=25, winSum=416
8465 22:51:09.889334 TX Vref=32, minBit 10, minWin=23, winSum=402
8466 22:51:09.893013 TX Vref=34, minBit 9, minWin=23, winSum=393
8467 22:51:09.899656 [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 28
8468 22:51:09.899760
8469 22:51:09.902683 Final TX Range 0 Vref 28
8470 22:51:09.902781
8471 22:51:09.902879 ==
8472 22:51:09.906204 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 22:51:09.909445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 22:51:09.909543 ==
8475 22:51:09.909642
8476 22:51:09.913022
8477 22:51:09.913124 TX Vref Scan disable
8478 22:51:09.919382 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8479 22:51:09.919482 == TX Byte 0 ==
8480 22:51:09.922881 u2DelayCellOfst[0]=16 cells (5 PI)
8481 22:51:09.925862 u2DelayCellOfst[1]=10 cells (3 PI)
8482 22:51:09.929743 u2DelayCellOfst[2]=0 cells (0 PI)
8483 22:51:09.932975 u2DelayCellOfst[3]=3 cells (1 PI)
8484 22:51:09.935953 u2DelayCellOfst[4]=6 cells (2 PI)
8485 22:51:09.939258 u2DelayCellOfst[5]=16 cells (5 PI)
8486 22:51:09.942918 u2DelayCellOfst[6]=16 cells (5 PI)
8487 22:51:09.946214 u2DelayCellOfst[7]=3 cells (1 PI)
8488 22:51:09.949633 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8489 22:51:09.952744 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8490 22:51:09.955937 == TX Byte 1 ==
8491 22:51:09.959469 u2DelayCellOfst[8]=0 cells (0 PI)
8492 22:51:09.959569 u2DelayCellOfst[9]=3 cells (1 PI)
8493 22:51:09.962731 u2DelayCellOfst[10]=13 cells (4 PI)
8494 22:51:09.966254 u2DelayCellOfst[11]=3 cells (1 PI)
8495 22:51:09.969171 u2DelayCellOfst[12]=16 cells (5 PI)
8496 22:51:09.972982 u2DelayCellOfst[13]=20 cells (6 PI)
8497 22:51:09.975656 u2DelayCellOfst[14]=20 cells (6 PI)
8498 22:51:09.979471 u2DelayCellOfst[15]=20 cells (6 PI)
8499 22:51:09.985684 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8500 22:51:09.988856 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8501 22:51:09.988960 DramC Write-DBI on
8502 22:51:09.989052 ==
8503 22:51:09.992377 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 22:51:09.998830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 22:51:09.998939 ==
8506 22:51:09.999036
8507 22:51:09.999125
8508 22:51:09.999211 TX Vref Scan disable
8509 22:51:10.003269 == TX Byte 0 ==
8510 22:51:10.006256 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8511 22:51:10.009835 == TX Byte 1 ==
8512 22:51:10.013033 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8513 22:51:10.016542 DramC Write-DBI off
8514 22:51:10.016644
8515 22:51:10.016745 [DATLAT]
8516 22:51:10.016835 Freq=1600, CH1 RK0
8517 22:51:10.016922
8518 22:51:10.019730 DATLAT Default: 0xf
8519 22:51:10.019827 0, 0xFFFF, sum = 0
8520 22:51:10.023110 1, 0xFFFF, sum = 0
8521 22:51:10.026373 2, 0xFFFF, sum = 0
8522 22:51:10.026453 3, 0xFFFF, sum = 0
8523 22:51:10.029468 4, 0xFFFF, sum = 0
8524 22:51:10.029539 5, 0xFFFF, sum = 0
8525 22:51:10.033100 6, 0xFFFF, sum = 0
8526 22:51:10.033204 7, 0xFFFF, sum = 0
8527 22:51:10.036177 8, 0xFFFF, sum = 0
8528 22:51:10.036285 9, 0xFFFF, sum = 0
8529 22:51:10.039898 10, 0xFFFF, sum = 0
8530 22:51:10.040005 11, 0xFFFF, sum = 0
8531 22:51:10.042839 12, 0xFFFF, sum = 0
8532 22:51:10.042911 13, 0xFFFF, sum = 0
8533 22:51:10.046198 14, 0x0, sum = 1
8534 22:51:10.046276 15, 0x0, sum = 2
8535 22:51:10.049610 16, 0x0, sum = 3
8536 22:51:10.049682 17, 0x0, sum = 4
8537 22:51:10.052917 best_step = 15
8538 22:51:10.053019
8539 22:51:10.053107 ==
8540 22:51:10.056226 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 22:51:10.059402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 22:51:10.059511 ==
8543 22:51:10.063061 RX Vref Scan: 1
8544 22:51:10.063157
8545 22:51:10.063254 Set Vref Range= 24 -> 127
8546 22:51:10.063342
8547 22:51:10.066149 RX Vref 24 -> 127, step: 1
8548 22:51:10.066250
8549 22:51:10.069487 RX Delay 19 -> 252, step: 4
8550 22:51:10.069587
8551 22:51:10.072596 Set Vref, RX VrefLevel [Byte0]: 24
8552 22:51:10.075971 [Byte1]: 24
8553 22:51:10.076077
8554 22:51:10.079125 Set Vref, RX VrefLevel [Byte0]: 25
8555 22:51:10.082569 [Byte1]: 25
8556 22:51:10.082670
8557 22:51:10.086035 Set Vref, RX VrefLevel [Byte0]: 26
8558 22:51:10.089081 [Byte1]: 26
8559 22:51:10.093489
8560 22:51:10.093596 Set Vref, RX VrefLevel [Byte0]: 27
8561 22:51:10.096738 [Byte1]: 27
8562 22:51:10.100894
8563 22:51:10.100996 Set Vref, RX VrefLevel [Byte0]: 28
8564 22:51:10.104248 [Byte1]: 28
8565 22:51:10.108332
8566 22:51:10.108411 Set Vref, RX VrefLevel [Byte0]: 29
8567 22:51:10.111919 [Byte1]: 29
8568 22:51:10.116380
8569 22:51:10.116473 Set Vref, RX VrefLevel [Byte0]: 30
8570 22:51:10.119517 [Byte1]: 30
8571 22:51:10.123834
8572 22:51:10.123936 Set Vref, RX VrefLevel [Byte0]: 31
8573 22:51:10.127124 [Byte1]: 31
8574 22:51:10.131312
8575 22:51:10.131418 Set Vref, RX VrefLevel [Byte0]: 32
8576 22:51:10.134330 [Byte1]: 32
8577 22:51:10.138677
8578 22:51:10.138777 Set Vref, RX VrefLevel [Byte0]: 33
8579 22:51:10.141971 [Byte1]: 33
8580 22:51:10.146554
8581 22:51:10.146641 Set Vref, RX VrefLevel [Byte0]: 34
8582 22:51:10.149465 [Byte1]: 34
8583 22:51:10.154073
8584 22:51:10.154175 Set Vref, RX VrefLevel [Byte0]: 35
8585 22:51:10.157330 [Byte1]: 35
8586 22:51:10.161262
8587 22:51:10.161352 Set Vref, RX VrefLevel [Byte0]: 36
8588 22:51:10.164779 [Byte1]: 36
8589 22:51:10.168939
8590 22:51:10.169023 Set Vref, RX VrefLevel [Byte0]: 37
8591 22:51:10.172526 [Byte1]: 37
8592 22:51:10.176878
8593 22:51:10.176960 Set Vref, RX VrefLevel [Byte0]: 38
8594 22:51:10.179930 [Byte1]: 38
8595 22:51:10.184271
8596 22:51:10.184375 Set Vref, RX VrefLevel [Byte0]: 39
8597 22:51:10.187447 [Byte1]: 39
8598 22:51:10.191704
8599 22:51:10.191786 Set Vref, RX VrefLevel [Byte0]: 40
8600 22:51:10.194790 [Byte1]: 40
8601 22:51:10.199140
8602 22:51:10.199223 Set Vref, RX VrefLevel [Byte0]: 41
8603 22:51:10.202659 [Byte1]: 41
8604 22:51:10.206797
8605 22:51:10.206880 Set Vref, RX VrefLevel [Byte0]: 42
8606 22:51:10.210429 [Byte1]: 42
8607 22:51:10.214600
8608 22:51:10.214682 Set Vref, RX VrefLevel [Byte0]: 43
8609 22:51:10.217595 [Byte1]: 43
8610 22:51:10.222171
8611 22:51:10.222253 Set Vref, RX VrefLevel [Byte0]: 44
8612 22:51:10.225274 [Byte1]: 44
8613 22:51:10.229611
8614 22:51:10.229694 Set Vref, RX VrefLevel [Byte0]: 45
8615 22:51:10.232868 [Byte1]: 45
8616 22:51:10.237200
8617 22:51:10.237285 Set Vref, RX VrefLevel [Byte0]: 46
8618 22:51:10.240697 [Byte1]: 46
8619 22:51:10.244605
8620 22:51:10.244686 Set Vref, RX VrefLevel [Byte0]: 47
8621 22:51:10.248073 [Byte1]: 47
8622 22:51:10.252500
8623 22:51:10.252579 Set Vref, RX VrefLevel [Byte0]: 48
8624 22:51:10.255823 [Byte1]: 48
8625 22:51:10.260025
8626 22:51:10.260103 Set Vref, RX VrefLevel [Byte0]: 49
8627 22:51:10.263031 [Byte1]: 49
8628 22:51:10.267560
8629 22:51:10.267632 Set Vref, RX VrefLevel [Byte0]: 50
8630 22:51:10.270683 [Byte1]: 50
8631 22:51:10.274961
8632 22:51:10.275033 Set Vref, RX VrefLevel [Byte0]: 51
8633 22:51:10.278443 [Byte1]: 51
8634 22:51:10.282407
8635 22:51:10.285902 Set Vref, RX VrefLevel [Byte0]: 52
8636 22:51:10.289311 [Byte1]: 52
8637 22:51:10.289382
8638 22:51:10.292292 Set Vref, RX VrefLevel [Byte0]: 53
8639 22:51:10.295816 [Byte1]: 53
8640 22:51:10.295893
8641 22:51:10.299103 Set Vref, RX VrefLevel [Byte0]: 54
8642 22:51:10.302218 [Byte1]: 54
8643 22:51:10.302289
8644 22:51:10.305659 Set Vref, RX VrefLevel [Byte0]: 55
8645 22:51:10.309094 [Byte1]: 55
8646 22:51:10.313118
8647 22:51:10.313189 Set Vref, RX VrefLevel [Byte0]: 56
8648 22:51:10.316050 [Byte1]: 56
8649 22:51:10.320261
8650 22:51:10.320338 Set Vref, RX VrefLevel [Byte0]: 57
8651 22:51:10.323904 [Byte1]: 57
8652 22:51:10.328227
8653 22:51:10.328301 Set Vref, RX VrefLevel [Byte0]: 58
8654 22:51:10.331421 [Byte1]: 58
8655 22:51:10.335675
8656 22:51:10.335749 Set Vref, RX VrefLevel [Byte0]: 59
8657 22:51:10.339157 [Byte1]: 59
8658 22:51:10.343357
8659 22:51:10.343429 Set Vref, RX VrefLevel [Byte0]: 60
8660 22:51:10.346298 [Byte1]: 60
8661 22:51:10.350484
8662 22:51:10.350554 Set Vref, RX VrefLevel [Byte0]: 61
8663 22:51:10.354336 [Byte1]: 61
8664 22:51:10.358427
8665 22:51:10.358497 Set Vref, RX VrefLevel [Byte0]: 62
8666 22:51:10.361722 [Byte1]: 62
8667 22:51:10.366180
8668 22:51:10.366254 Set Vref, RX VrefLevel [Byte0]: 63
8669 22:51:10.368950 [Byte1]: 63
8670 22:51:10.373663
8671 22:51:10.373735 Set Vref, RX VrefLevel [Byte0]: 64
8672 22:51:10.377010 [Byte1]: 64
8673 22:51:10.381044
8674 22:51:10.381122 Set Vref, RX VrefLevel [Byte0]: 65
8675 22:51:10.384321 [Byte1]: 65
8676 22:51:10.388374
8677 22:51:10.388444 Set Vref, RX VrefLevel [Byte0]: 66
8678 22:51:10.391688 [Byte1]: 66
8679 22:51:10.396185
8680 22:51:10.396262 Set Vref, RX VrefLevel [Byte0]: 67
8681 22:51:10.399517 [Byte1]: 67
8682 22:51:10.403945
8683 22:51:10.404016 Set Vref, RX VrefLevel [Byte0]: 68
8684 22:51:10.406874 [Byte1]: 68
8685 22:51:10.411502
8686 22:51:10.411579 Set Vref, RX VrefLevel [Byte0]: 69
8687 22:51:10.414437 [Byte1]: 69
8688 22:51:10.419146
8689 22:51:10.419215 Set Vref, RX VrefLevel [Byte0]: 70
8690 22:51:10.422294 [Byte1]: 70
8691 22:51:10.426255
8692 22:51:10.426333 Set Vref, RX VrefLevel [Byte0]: 71
8693 22:51:10.430021 [Byte1]: 71
8694 22:51:10.433877
8695 22:51:10.433960 Set Vref, RX VrefLevel [Byte0]: 72
8696 22:51:10.437283 [Byte1]: 72
8697 22:51:10.441722
8698 22:51:10.441806 Final RX Vref Byte 0 = 53 to rank0
8699 22:51:10.445175 Final RX Vref Byte 1 = 62 to rank0
8700 22:51:10.448119 Final RX Vref Byte 0 = 53 to rank1
8701 22:51:10.451650 Final RX Vref Byte 1 = 62 to rank1==
8702 22:51:10.455066 Dram Type= 6, Freq= 0, CH_1, rank 0
8703 22:51:10.461675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8704 22:51:10.461759 ==
8705 22:51:10.461844 DQS Delay:
8706 22:51:10.461909 DQS0 = 0, DQS1 = 0
8707 22:51:10.465043 DQM Delay:
8708 22:51:10.465127 DQM0 = 133, DQM1 = 129
8709 22:51:10.468164 DQ Delay:
8710 22:51:10.471518 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8711 22:51:10.474717 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8712 22:51:10.478502 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8713 22:51:10.481449 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8714 22:51:10.481534
8715 22:51:10.481600
8716 22:51:10.481659
8717 22:51:10.484812 [DramC_TX_OE_Calibration] TA2
8718 22:51:10.488229 Original DQ_B0 (3 6) =30, OEN = 27
8719 22:51:10.491676 Original DQ_B1 (3 6) =30, OEN = 27
8720 22:51:10.494638 24, 0x0, End_B0=24 End_B1=24
8721 22:51:10.494723 25, 0x0, End_B0=25 End_B1=25
8722 22:51:10.498204 26, 0x0, End_B0=26 End_B1=26
8723 22:51:10.501194 27, 0x0, End_B0=27 End_B1=27
8724 22:51:10.504499 28, 0x0, End_B0=28 End_B1=28
8725 22:51:10.504584 29, 0x0, End_B0=29 End_B1=29
8726 22:51:10.507798 30, 0x0, End_B0=30 End_B1=30
8727 22:51:10.511239 31, 0x4545, End_B0=30 End_B1=30
8728 22:51:10.514715 Byte0 end_step=30 best_step=27
8729 22:51:10.517984 Byte1 end_step=30 best_step=27
8730 22:51:10.521169 Byte0 TX OE(2T, 0.5T) = (3, 3)
8731 22:51:10.521252 Byte1 TX OE(2T, 0.5T) = (3, 3)
8732 22:51:10.524440
8733 22:51:10.524523
8734 22:51:10.531191 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8735 22:51:10.534820 CH1 RK0: MR19=303, MR18=1A28
8736 22:51:10.541465 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8737 22:51:10.541550
8738 22:51:10.544463 ----->DramcWriteLeveling(PI) begin...
8739 22:51:10.544548 ==
8740 22:51:10.548127 Dram Type= 6, Freq= 0, CH_1, rank 1
8741 22:51:10.551173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8742 22:51:10.551258 ==
8743 22:51:10.554617 Write leveling (Byte 0): 25 => 25
8744 22:51:10.557920 Write leveling (Byte 1): 28 => 28
8745 22:51:10.561232 DramcWriteLeveling(PI) end<-----
8746 22:51:10.561342
8747 22:51:10.561423 ==
8748 22:51:10.564523 Dram Type= 6, Freq= 0, CH_1, rank 1
8749 22:51:10.567570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 22:51:10.567655 ==
8751 22:51:10.571080 [Gating] SW mode calibration
8752 22:51:10.577896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8753 22:51:10.584153 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8754 22:51:10.587485 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 22:51:10.590973 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 22:51:10.597562 1 4 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8757 22:51:10.600851 1 4 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
8758 22:51:10.604284 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 22:51:10.611128 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 22:51:10.614162 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 22:51:10.617553 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 22:51:10.624106 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 22:51:10.627459 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8764 22:51:10.630861 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (0 1) (1 0)
8765 22:51:10.637685 1 5 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
8766 22:51:10.640975 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 22:51:10.644282 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 22:51:10.650768 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 22:51:10.653964 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 22:51:10.657695 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 22:51:10.664382 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8772 22:51:10.667337 1 6 8 | B1->B0 | 4646 2626 | 0 0 | (0 0) (0 0)
8773 22:51:10.670830 1 6 12 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
8774 22:51:10.677340 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 22:51:10.680551 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 22:51:10.683848 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 22:51:10.690750 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 22:51:10.693890 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 22:51:10.697186 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 22:51:10.703976 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8781 22:51:10.707283 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8782 22:51:10.710665 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 22:51:10.714021 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 22:51:10.720457 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 22:51:10.723811 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 22:51:10.727039 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 22:51:10.733923 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 22:51:10.737494 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 22:51:10.740684 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 22:51:10.747445 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 22:51:10.750329 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 22:51:10.753706 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 22:51:10.760419 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 22:51:10.763779 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 22:51:10.767142 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 22:51:10.774002 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8797 22:51:10.777279 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8798 22:51:10.780268 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 22:51:10.783834 Total UI for P1: 0, mck2ui 16
8800 22:51:10.787230 best dqsien dly found for B0: ( 1, 9, 10)
8801 22:51:10.790217 Total UI for P1: 0, mck2ui 16
8802 22:51:10.793737 best dqsien dly found for B1: ( 1, 9, 10)
8803 22:51:10.797171 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8804 22:51:10.800086 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8805 22:51:10.800197
8806 22:51:10.807151 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8807 22:51:10.810158 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8808 22:51:10.814068 [Gating] SW calibration Done
8809 22:51:10.814155 ==
8810 22:51:10.816792 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 22:51:10.820463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 22:51:10.820548 ==
8813 22:51:10.820616 RX Vref Scan: 0
8814 22:51:10.820678
8815 22:51:10.823702 RX Vref 0 -> 0, step: 1
8816 22:51:10.823812
8817 22:51:10.827158 RX Delay 0 -> 252, step: 8
8818 22:51:10.830160 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
8819 22:51:10.833809 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8820 22:51:10.836889 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8821 22:51:10.843515 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8822 22:51:10.847039 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8823 22:51:10.850279 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8824 22:51:10.853712 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8825 22:51:10.856739 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8826 22:51:10.863329 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8827 22:51:10.866914 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8828 22:51:10.870040 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8829 22:51:10.873345 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8830 22:51:10.876735 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8831 22:51:10.883346 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8832 22:51:10.886839 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8833 22:51:10.889868 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8834 22:51:10.889955 ==
8835 22:51:10.893735 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 22:51:10.897083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 22:51:10.897163 ==
8838 22:51:10.900053 DQS Delay:
8839 22:51:10.900139 DQS0 = 0, DQS1 = 0
8840 22:51:10.903480 DQM Delay:
8841 22:51:10.903565 DQM0 = 136, DQM1 = 133
8842 22:51:10.903633 DQ Delay:
8843 22:51:10.909880 DQ0 =135, DQ1 =135, DQ2 =123, DQ3 =135
8844 22:51:10.913324 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =139
8845 22:51:10.916370 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8846 22:51:10.920116 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8847 22:51:10.920221
8848 22:51:10.920318
8849 22:51:10.920413 ==
8850 22:51:10.923477 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 22:51:10.926877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 22:51:10.926954 ==
8853 22:51:10.927018
8854 22:51:10.927091
8855 22:51:10.929918 TX Vref Scan disable
8856 22:51:10.933259 == TX Byte 0 ==
8857 22:51:10.936691 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8858 22:51:10.939898 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8859 22:51:10.943453 == TX Byte 1 ==
8860 22:51:10.946634 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8861 22:51:10.949611 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8862 22:51:10.949686 ==
8863 22:51:10.953072 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 22:51:10.956577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 22:51:10.959846 ==
8866 22:51:10.971128
8867 22:51:10.974574 TX Vref early break, caculate TX vref
8868 22:51:10.977665 TX Vref=16, minBit 9, minWin=22, winSum=385
8869 22:51:10.980780 TX Vref=18, minBit 9, minWin=23, winSum=393
8870 22:51:10.984618 TX Vref=20, minBit 10, minWin=23, winSum=398
8871 22:51:10.987493 TX Vref=22, minBit 8, minWin=24, winSum=407
8872 22:51:10.990885 TX Vref=24, minBit 11, minWin=24, winSum=415
8873 22:51:10.997633 TX Vref=26, minBit 9, minWin=25, winSum=421
8874 22:51:11.000961 TX Vref=28, minBit 10, minWin=25, winSum=425
8875 22:51:11.004152 TX Vref=30, minBit 10, minWin=24, winSum=410
8876 22:51:11.007318 TX Vref=32, minBit 0, minWin=24, winSum=404
8877 22:51:11.010573 TX Vref=34, minBit 10, minWin=23, winSum=399
8878 22:51:11.017198 [TxChooseVref] Worse bit 10, Min win 25, Win sum 425, Final Vref 28
8879 22:51:11.017307
8880 22:51:11.020777 Final TX Range 0 Vref 28
8881 22:51:11.020880
8882 22:51:11.020972 ==
8883 22:51:11.024361 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 22:51:11.027731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 22:51:11.027841 ==
8886 22:51:11.027934
8887 22:51:11.028023
8888 22:51:11.030795 TX Vref Scan disable
8889 22:51:11.037196 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8890 22:51:11.037305 == TX Byte 0 ==
8891 22:51:11.040509 u2DelayCellOfst[0]=13 cells (4 PI)
8892 22:51:11.043930 u2DelayCellOfst[1]=10 cells (3 PI)
8893 22:51:11.047594 u2DelayCellOfst[2]=0 cells (0 PI)
8894 22:51:11.050746 u2DelayCellOfst[3]=3 cells (1 PI)
8895 22:51:11.054153 u2DelayCellOfst[4]=6 cells (2 PI)
8896 22:51:11.057416 u2DelayCellOfst[5]=16 cells (5 PI)
8897 22:51:11.060727 u2DelayCellOfst[6]=16 cells (5 PI)
8898 22:51:11.064141 u2DelayCellOfst[7]=3 cells (1 PI)
8899 22:51:11.067605 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8900 22:51:11.070512 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8901 22:51:11.074138 == TX Byte 1 ==
8902 22:51:11.074224 u2DelayCellOfst[8]=0 cells (0 PI)
8903 22:51:11.077115 u2DelayCellOfst[9]=6 cells (2 PI)
8904 22:51:11.080742 u2DelayCellOfst[10]=13 cells (4 PI)
8905 22:51:11.084192 u2DelayCellOfst[11]=3 cells (1 PI)
8906 22:51:11.087339 u2DelayCellOfst[12]=16 cells (5 PI)
8907 22:51:11.090732 u2DelayCellOfst[13]=20 cells (6 PI)
8908 22:51:11.093827 u2DelayCellOfst[14]=16 cells (5 PI)
8909 22:51:11.097446 u2DelayCellOfst[15]=20 cells (6 PI)
8910 22:51:11.100824 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8911 22:51:11.107389 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8912 22:51:11.107483 DramC Write-DBI on
8913 22:51:11.107550 ==
8914 22:51:11.110557 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 22:51:11.114127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 22:51:11.117471 ==
8917 22:51:11.117554
8918 22:51:11.117620
8919 22:51:11.117682 TX Vref Scan disable
8920 22:51:11.120743 == TX Byte 0 ==
8921 22:51:11.124223 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8922 22:51:11.127235 == TX Byte 1 ==
8923 22:51:11.130591 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8924 22:51:11.133940 DramC Write-DBI off
8925 22:51:11.134023
8926 22:51:11.134089 [DATLAT]
8927 22:51:11.134149 Freq=1600, CH1 RK1
8928 22:51:11.134208
8929 22:51:11.137546 DATLAT Default: 0xf
8930 22:51:11.137628 0, 0xFFFF, sum = 0
8931 22:51:11.140963 1, 0xFFFF, sum = 0
8932 22:51:11.141050 2, 0xFFFF, sum = 0
8933 22:51:11.144129 3, 0xFFFF, sum = 0
8934 22:51:11.147605 4, 0xFFFF, sum = 0
8935 22:51:11.147697 5, 0xFFFF, sum = 0
8936 22:51:11.150888 6, 0xFFFF, sum = 0
8937 22:51:11.150973 7, 0xFFFF, sum = 0
8938 22:51:11.153828 8, 0xFFFF, sum = 0
8939 22:51:11.153912 9, 0xFFFF, sum = 0
8940 22:51:11.157303 10, 0xFFFF, sum = 0
8941 22:51:11.157420 11, 0xFFFF, sum = 0
8942 22:51:11.160714 12, 0xFFFF, sum = 0
8943 22:51:11.160798 13, 0xFFFF, sum = 0
8944 22:51:11.164066 14, 0x0, sum = 1
8945 22:51:11.164150 15, 0x0, sum = 2
8946 22:51:11.167339 16, 0x0, sum = 3
8947 22:51:11.167423 17, 0x0, sum = 4
8948 22:51:11.170768 best_step = 15
8949 22:51:11.170852
8950 22:51:11.170919 ==
8951 22:51:11.173797 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 22:51:11.177549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 22:51:11.177634 ==
8954 22:51:11.177701 RX Vref Scan: 0
8955 22:51:11.180807
8956 22:51:11.180890 RX Vref 0 -> 0, step: 1
8957 22:51:11.180957
8958 22:51:11.184198 RX Delay 19 -> 252, step: 4
8959 22:51:11.187408 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
8960 22:51:11.190883 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
8961 22:51:11.197433 iDelay=195, Bit 2, Center 118 (71 ~ 166) 96
8962 22:51:11.200862 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8963 22:51:11.204081 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8964 22:51:11.207360 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8965 22:51:11.210693 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8966 22:51:11.214135 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8967 22:51:11.220532 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8968 22:51:11.224131 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8969 22:51:11.227518 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8970 22:51:11.230621 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8971 22:51:11.237123 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8972 22:51:11.240577 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
8973 22:51:11.243803 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8974 22:51:11.247279 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8975 22:51:11.247357 ==
8976 22:51:11.250414 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 22:51:11.254049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 22:51:11.257104 ==
8979 22:51:11.257174 DQS Delay:
8980 22:51:11.257242 DQS0 = 0, DQS1 = 0
8981 22:51:11.260563 DQM Delay:
8982 22:51:11.260632 DQM0 = 133, DQM1 = 130
8983 22:51:11.264029 DQ Delay:
8984 22:51:11.267571 DQ0 =136, DQ1 =132, DQ2 =118, DQ3 =130
8985 22:51:11.270473 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
8986 22:51:11.273702 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
8987 22:51:11.277306 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
8988 22:51:11.277375
8989 22:51:11.277441
8990 22:51:11.277500
8991 22:51:11.280637 [DramC_TX_OE_Calibration] TA2
8992 22:51:11.283814 Original DQ_B0 (3 6) =30, OEN = 27
8993 22:51:11.287448 Original DQ_B1 (3 6) =30, OEN = 27
8994 22:51:11.290276 24, 0x0, End_B0=24 End_B1=24
8995 22:51:11.290345 25, 0x0, End_B0=25 End_B1=25
8996 22:51:11.293714 26, 0x0, End_B0=26 End_B1=26
8997 22:51:11.296944 27, 0x0, End_B0=27 End_B1=27
8998 22:51:11.300387 28, 0x0, End_B0=28 End_B1=28
8999 22:51:11.300468 29, 0x0, End_B0=29 End_B1=29
9000 22:51:11.303795 30, 0x0, End_B0=30 End_B1=30
9001 22:51:11.306930 31, 0x4141, End_B0=30 End_B1=30
9002 22:51:11.310413 Byte0 end_step=30 best_step=27
9003 22:51:11.313397 Byte1 end_step=30 best_step=27
9004 22:51:11.316716 Byte0 TX OE(2T, 0.5T) = (3, 3)
9005 22:51:11.316784 Byte1 TX OE(2T, 0.5T) = (3, 3)
9006 22:51:11.316845
9007 22:51:11.320605
9008 22:51:11.326852 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
9009 22:51:11.330006 CH1 RK1: MR19=303, MR18=1F0B
9010 22:51:11.337177 CH1_RK1: MR19=0x303, MR18=0x1F0B, DQSOSC=394, MR23=63, INC=23, DEC=15
9011 22:51:11.339881 [RxdqsGatingPostProcess] freq 1600
9012 22:51:11.343452 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9013 22:51:11.346699 best DQS0 dly(2T, 0.5T) = (1, 1)
9014 22:51:11.349715 best DQS1 dly(2T, 0.5T) = (1, 1)
9015 22:51:11.353190 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9016 22:51:11.356455 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9017 22:51:11.359728 best DQS0 dly(2T, 0.5T) = (1, 1)
9018 22:51:11.363089 best DQS1 dly(2T, 0.5T) = (1, 1)
9019 22:51:11.366875 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9020 22:51:11.370054 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9021 22:51:11.373088 Pre-setting of DQS Precalculation
9022 22:51:11.376337 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9023 22:51:11.382824 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9024 22:51:11.389774 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9025 22:51:11.393214
9026 22:51:11.393283
9027 22:51:11.393356 [Calibration Summary] 3200 Mbps
9028 22:51:11.396653 CH 0, Rank 0
9029 22:51:11.396738 SW Impedance : PASS
9030 22:51:11.399815 DUTY Scan : NO K
9031 22:51:11.403126 ZQ Calibration : PASS
9032 22:51:11.403207 Jitter Meter : NO K
9033 22:51:11.406009 CBT Training : PASS
9034 22:51:11.409209 Write leveling : PASS
9035 22:51:11.409281 RX DQS gating : PASS
9036 22:51:11.412508 RX DQ/DQS(RDDQC) : PASS
9037 22:51:11.416292 TX DQ/DQS : PASS
9038 22:51:11.416366 RX DATLAT : PASS
9039 22:51:11.419501 RX DQ/DQS(Engine): PASS
9040 22:51:11.422993 TX OE : PASS
9041 22:51:11.423066 All Pass.
9042 22:51:11.423127
9043 22:51:11.423192 CH 0, Rank 1
9044 22:51:11.426167 SW Impedance : PASS
9045 22:51:11.429468 DUTY Scan : NO K
9046 22:51:11.429538 ZQ Calibration : PASS
9047 22:51:11.432759 Jitter Meter : NO K
9048 22:51:11.436265 CBT Training : PASS
9049 22:51:11.436338 Write leveling : PASS
9050 22:51:11.439072 RX DQS gating : PASS
9051 22:51:11.442527 RX DQ/DQS(RDDQC) : PASS
9052 22:51:11.442607 TX DQ/DQS : PASS
9053 22:51:11.445806 RX DATLAT : PASS
9054 22:51:11.449093 RX DQ/DQS(Engine): PASS
9055 22:51:11.449162 TX OE : PASS
9056 22:51:11.449222 All Pass.
9057 22:51:11.449279
9058 22:51:11.452577 CH 1, Rank 0
9059 22:51:11.452644 SW Impedance : PASS
9060 22:51:11.455956 DUTY Scan : NO K
9061 22:51:11.459320 ZQ Calibration : PASS
9062 22:51:11.459389 Jitter Meter : NO K
9063 22:51:11.462752 CBT Training : PASS
9064 22:51:11.465711 Write leveling : PASS
9065 22:51:11.465780 RX DQS gating : PASS
9066 22:51:11.469224 RX DQ/DQS(RDDQC) : PASS
9067 22:51:11.472448 TX DQ/DQS : PASS
9068 22:51:11.472522 RX DATLAT : PASS
9069 22:51:11.475776 RX DQ/DQS(Engine): PASS
9070 22:51:11.479201 TX OE : PASS
9071 22:51:11.479273 All Pass.
9072 22:51:11.479341
9073 22:51:11.479400 CH 1, Rank 1
9074 22:51:11.482297 SW Impedance : PASS
9075 22:51:11.485994 DUTY Scan : NO K
9076 22:51:11.486075 ZQ Calibration : PASS
9077 22:51:11.489083 Jitter Meter : NO K
9078 22:51:11.492197 CBT Training : PASS
9079 22:51:11.492269 Write leveling : PASS
9080 22:51:11.495744 RX DQS gating : PASS
9081 22:51:11.495828 RX DQ/DQS(RDDQC) : PASS
9082 22:51:11.499104 TX DQ/DQS : PASS
9083 22:51:11.502473 RX DATLAT : PASS
9084 22:51:11.502547 RX DQ/DQS(Engine): PASS
9085 22:51:11.505627 TX OE : PASS
9086 22:51:11.505699 All Pass.
9087 22:51:11.505759
9088 22:51:11.509227 DramC Write-DBI on
9089 22:51:11.512126 PER_BANK_REFRESH: Hybrid Mode
9090 22:51:11.512198 TX_TRACKING: ON
9091 22:51:11.522299 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9092 22:51:11.528999 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9093 22:51:11.535946 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9094 22:51:11.542164 [FAST_K] Save calibration result to emmc
9095 22:51:11.542245 sync common calibartion params.
9096 22:51:11.545733 sync cbt_mode0:1, 1:1
9097 22:51:11.549215 dram_init: ddr_geometry: 2
9098 22:51:11.549287 dram_init: ddr_geometry: 2
9099 22:51:11.552640 dram_init: ddr_geometry: 2
9100 22:51:11.555587 0:dram_rank_size:100000000
9101 22:51:11.559037 1:dram_rank_size:100000000
9102 22:51:11.562426 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9103 22:51:11.565610 DFS_SHUFFLE_HW_MODE: ON
9104 22:51:11.569106 dramc_set_vcore_voltage set vcore to 725000
9105 22:51:11.572470 Read voltage for 1600, 0
9106 22:51:11.572545 Vio18 = 0
9107 22:51:11.572615 Vcore = 725000
9108 22:51:11.575646 Vdram = 0
9109 22:51:11.575717 Vddq = 0
9110 22:51:11.575776 Vmddr = 0
9111 22:51:11.578973 switch to 3200 Mbps bootup
9112 22:51:11.582408 [DramcRunTimeConfig]
9113 22:51:11.582480 PHYPLL
9114 22:51:11.582540 DPM_CONTROL_AFTERK: ON
9115 22:51:11.585871 PER_BANK_REFRESH: ON
9116 22:51:11.589621 REFRESH_OVERHEAD_REDUCTION: ON
9117 22:51:11.589696 CMD_PICG_NEW_MODE: OFF
9118 22:51:11.592527 XRTWTW_NEW_MODE: ON
9119 22:51:11.592606 XRTRTR_NEW_MODE: ON
9120 22:51:11.595503 TX_TRACKING: ON
9121 22:51:11.595585 RDSEL_TRACKING: OFF
9122 22:51:11.599132 DQS Precalculation for DVFS: ON
9123 22:51:11.602588 RX_TRACKING: OFF
9124 22:51:11.602662 HW_GATING DBG: ON
9125 22:51:11.605786 ZQCS_ENABLE_LP4: ON
9126 22:51:11.605865 RX_PICG_NEW_MODE: ON
9127 22:51:11.608920 TX_PICG_NEW_MODE: ON
9128 22:51:11.612723 ENABLE_RX_DCM_DPHY: ON
9129 22:51:11.615708 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9130 22:51:11.615780 DUMMY_READ_FOR_TRACKING: OFF
9131 22:51:11.619153 !!! SPM_CONTROL_AFTERK: OFF
9132 22:51:11.622352 !!! SPM could not control APHY
9133 22:51:11.625326 IMPEDANCE_TRACKING: ON
9134 22:51:11.625413 TEMP_SENSOR: ON
9135 22:51:11.628696 HW_SAVE_FOR_SR: OFF
9136 22:51:11.628766 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9137 22:51:11.635332 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9138 22:51:11.635409 Read ODT Tracking: ON
9139 22:51:11.638660 Refresh Rate DeBounce: ON
9140 22:51:11.638732 DFS_NO_QUEUE_FLUSH: ON
9141 22:51:11.642015 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9142 22:51:11.645315 ENABLE_DFS_RUNTIME_MRW: OFF
9143 22:51:11.648695 DDR_RESERVE_NEW_MODE: ON
9144 22:51:11.648767 MR_CBT_SWITCH_FREQ: ON
9145 22:51:11.651921 =========================
9146 22:51:11.671409 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9147 22:51:11.674868 dram_init: ddr_geometry: 2
9148 22:51:11.692825 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9149 22:51:11.696272 dram_init: dram init end (result: 0)
9150 22:51:11.703180 DRAM-K: Full calibration passed in 24498 msecs
9151 22:51:11.706499 MRC: failed to locate region type 0.
9152 22:51:11.706581 DRAM rank0 size:0x100000000,
9153 22:51:11.709614 DRAM rank1 size=0x100000000
9154 22:51:11.720075 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9155 22:51:11.726412 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9156 22:51:11.733109 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9157 22:51:11.739783 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9158 22:51:11.743003 DRAM rank0 size:0x100000000,
9159 22:51:11.746217 DRAM rank1 size=0x100000000
9160 22:51:11.746290 CBMEM:
9161 22:51:11.749901 IMD: root @ 0xfffff000 254 entries.
9162 22:51:11.752772 IMD: root @ 0xffffec00 62 entries.
9163 22:51:11.756399 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9164 22:51:11.759234 WARNING: RO_VPD is uninitialized or empty.
9165 22:51:11.766307 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9166 22:51:11.776128 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9167 22:51:11.785952 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9168 22:51:11.796946 BS: romstage times (exec / console): total (unknown) / 23997 ms
9169 22:51:11.797026
9170 22:51:11.797098
9171 22:51:11.807015 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9172 22:51:11.810288 ARM64: Exception handlers installed.
9173 22:51:11.813729 ARM64: Testing exception
9174 22:51:11.816907 ARM64: Done test exception
9175 22:51:11.816979 Enumerating buses...
9176 22:51:11.820641 Show all devs... Before device enumeration.
9177 22:51:11.823740 Root Device: enabled 1
9178 22:51:11.826837 CPU_CLUSTER: 0: enabled 1
9179 22:51:11.826912 CPU: 00: enabled 1
9180 22:51:11.830559 Compare with tree...
9181 22:51:11.830631 Root Device: enabled 1
9182 22:51:11.833640 CPU_CLUSTER: 0: enabled 1
9183 22:51:11.837021 CPU: 00: enabled 1
9184 22:51:11.837149 Root Device scanning...
9185 22:51:11.840136 scan_static_bus for Root Device
9186 22:51:11.843437 CPU_CLUSTER: 0 enabled
9187 22:51:11.847095 scan_static_bus for Root Device done
9188 22:51:11.850202 scan_bus: bus Root Device finished in 8 msecs
9189 22:51:11.850278 done
9190 22:51:11.856753 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9191 22:51:11.860597 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9192 22:51:11.867135 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9193 22:51:11.870487 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9194 22:51:11.873687 Allocating resources...
9195 22:51:11.876920 Reading resources...
9196 22:51:11.880373 Root Device read_resources bus 0 link: 0
9197 22:51:11.880440 DRAM rank0 size:0x100000000,
9198 22:51:11.883441 DRAM rank1 size=0x100000000
9199 22:51:11.886710 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9200 22:51:11.890402 CPU: 00 missing read_resources
9201 22:51:11.893406 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9202 22:51:11.900195 Root Device read_resources bus 0 link: 0 done
9203 22:51:11.900276 Done reading resources.
9204 22:51:11.906802 Show resources in subtree (Root Device)...After reading.
9205 22:51:11.910378 Root Device child on link 0 CPU_CLUSTER: 0
9206 22:51:11.913591 CPU_CLUSTER: 0 child on link 0 CPU: 00
9207 22:51:11.923515 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9208 22:51:11.923616 CPU: 00
9209 22:51:11.926922 Root Device assign_resources, bus 0 link: 0
9210 22:51:11.930245 CPU_CLUSTER: 0 missing set_resources
9211 22:51:11.933536 Root Device assign_resources, bus 0 link: 0 done
9212 22:51:11.936667 Done setting resources.
9213 22:51:11.943599 Show resources in subtree (Root Device)...After assigning values.
9214 22:51:11.946970 Root Device child on link 0 CPU_CLUSTER: 0
9215 22:51:11.949818 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 22:51:11.960023 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 22:51:11.960098 CPU: 00
9218 22:51:11.963143 Done allocating resources.
9219 22:51:11.966332 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9220 22:51:11.969777 Enabling resources...
9221 22:51:11.969848 done.
9222 22:51:11.976562 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9223 22:51:11.976636 Initializing devices...
9224 22:51:11.979631 Root Device init
9225 22:51:11.979699 init hardware done!
9226 22:51:11.983018 0x00000018: ctrlr->caps
9227 22:51:11.986198 52.000 MHz: ctrlr->f_max
9228 22:51:11.986273 0.400 MHz: ctrlr->f_min
9229 22:51:11.989655 0x40ff8080: ctrlr->voltages
9230 22:51:11.989747 sclk: 390625
9231 22:51:11.992968 Bus Width = 1
9232 22:51:11.993036 sclk: 390625
9233 22:51:11.996289 Bus Width = 1
9234 22:51:11.996365 Early init status = 3
9235 22:51:12.002726 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9236 22:51:12.006295 in-header: 03 fc 00 00 01 00 00 00
9237 22:51:12.006393 in-data: 00
9238 22:51:12.012870 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9239 22:51:12.015869 in-header: 03 fd 00 00 00 00 00 00
9240 22:51:12.019642 in-data:
9241 22:51:12.022697 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9242 22:51:12.025840 in-header: 03 fc 00 00 01 00 00 00
9243 22:51:12.029382 in-data: 00
9244 22:51:12.032540 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9245 22:51:12.037002 in-header: 03 fd 00 00 00 00 00 00
9246 22:51:12.040756 in-data:
9247 22:51:12.043913 [SSUSB] Setting up USB HOST controller...
9248 22:51:12.047155 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9249 22:51:12.050702 [SSUSB] phy power-on done.
9250 22:51:12.053883 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9251 22:51:12.060633 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9252 22:51:12.063715 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9253 22:51:12.070795 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9254 22:51:12.077119 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9255 22:51:12.083861 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9256 22:51:12.090532 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9257 22:51:12.097174 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9258 22:51:12.097291 SPM: binary array size = 0x9dc
9259 22:51:12.103671 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9260 22:51:12.110644 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9261 22:51:12.117209 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9262 22:51:12.120278 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9263 22:51:12.123739 configure_display: Starting display init
9264 22:51:12.160305 anx7625_power_on_init: Init interface.
9265 22:51:12.163706 anx7625_disable_pd_protocol: Disabled PD feature.
9266 22:51:12.166971 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9267 22:51:12.194894 anx7625_start_dp_work: Secure OCM version=00
9268 22:51:12.198052 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9269 22:51:12.212842 sp_tx_get_edid_block: EDID Block = 1
9270 22:51:12.315557 Extracted contents:
9271 22:51:12.318770 header: 00 ff ff ff ff ff ff 00
9272 22:51:12.322175 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9273 22:51:12.325506 version: 01 04
9274 22:51:12.328616 basic params: 95 1f 11 78 0a
9275 22:51:12.332005 chroma info: 76 90 94 55 54 90 27 21 50 54
9276 22:51:12.335291 established: 00 00 00
9277 22:51:12.342025 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9278 22:51:12.345615 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9279 22:51:12.352058 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9280 22:51:12.358400 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9281 22:51:12.365278 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9282 22:51:12.368635 extensions: 00
9283 22:51:12.368713 checksum: fb
9284 22:51:12.368795
9285 22:51:12.371913 Manufacturer: IVO Model 57d Serial Number 0
9286 22:51:12.374896 Made week 0 of 2020
9287 22:51:12.378590 EDID version: 1.4
9288 22:51:12.378661 Digital display
9289 22:51:12.381412 6 bits per primary color channel
9290 22:51:12.381486 DisplayPort interface
9291 22:51:12.385224 Maximum image size: 31 cm x 17 cm
9292 22:51:12.388083 Gamma: 220%
9293 22:51:12.388181 Check DPMS levels
9294 22:51:12.391980 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9295 22:51:12.398190 First detailed timing is preferred timing
9296 22:51:12.398267 Established timings supported:
9297 22:51:12.401553 Standard timings supported:
9298 22:51:12.404735 Detailed timings
9299 22:51:12.408053 Hex of detail: 383680a07038204018303c0035ae10000019
9300 22:51:12.411360 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9301 22:51:12.418493 0780 0798 07c8 0820 hborder 0
9302 22:51:12.421686 0438 043b 0447 0458 vborder 0
9303 22:51:12.425199 -hsync -vsync
9304 22:51:12.425302 Did detailed timing
9305 22:51:12.431518 Hex of detail: 000000000000000000000000000000000000
9306 22:51:12.434813 Manufacturer-specified data, tag 0
9307 22:51:12.438056 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9308 22:51:12.441556 ASCII string: InfoVision
9309 22:51:12.444570 Hex of detail: 000000fe00523134304e574635205248200a
9310 22:51:12.448254 ASCII string: R140NWF5 RH
9311 22:51:12.448350 Checksum
9312 22:51:12.451484 Checksum: 0xfb (valid)
9313 22:51:12.454667 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9314 22:51:12.457779 DSI data_rate: 832800000 bps
9315 22:51:12.464679 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9316 22:51:12.467631 anx7625_parse_edid: pixelclock(138800).
9317 22:51:12.471296 hactive(1920), hsync(48), hfp(24), hbp(88)
9318 22:51:12.474662 vactive(1080), vsync(12), vfp(3), vbp(17)
9319 22:51:12.478124 anx7625_dsi_config: config dsi.
9320 22:51:12.484849 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9321 22:51:12.497421 anx7625_dsi_config: success to config DSI
9322 22:51:12.500836 anx7625_dp_start: MIPI phy setup OK.
9323 22:51:12.504036 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9324 22:51:12.507782 mtk_ddp_mode_set invalid vrefresh 60
9325 22:51:12.510837 main_disp_path_setup
9326 22:51:12.510936 ovl_layer_smi_id_en
9327 22:51:12.514392 ovl_layer_smi_id_en
9328 22:51:12.514487 ccorr_config
9329 22:51:12.514583 aal_config
9330 22:51:12.517709 gamma_config
9331 22:51:12.517806 postmask_config
9332 22:51:12.520749 dither_config
9333 22:51:12.524048 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9334 22:51:12.530964 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9335 22:51:12.533996 Root Device init finished in 551 msecs
9336 22:51:12.534066 CPU_CLUSTER: 0 init
9337 22:51:12.543943 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9338 22:51:12.547279 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9339 22:51:12.550819 APU_MBOX 0x190000b0 = 0x10001
9340 22:51:12.554008 APU_MBOX 0x190001b0 = 0x10001
9341 22:51:12.557285 APU_MBOX 0x190005b0 = 0x10001
9342 22:51:12.560819 APU_MBOX 0x190006b0 = 0x10001
9343 22:51:12.564226 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9344 22:51:12.576681 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9345 22:51:12.588701 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9346 22:51:12.595742 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9347 22:51:12.607237 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9348 22:51:12.616212 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9349 22:51:12.619524 CPU_CLUSTER: 0 init finished in 81 msecs
9350 22:51:12.622753 Devices initialized
9351 22:51:12.626398 Show all devs... After init.
9352 22:51:12.626494 Root Device: enabled 1
9353 22:51:12.629590 CPU_CLUSTER: 0: enabled 1
9354 22:51:12.632712 CPU: 00: enabled 1
9355 22:51:12.636038 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9356 22:51:12.639312 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9357 22:51:12.642835 ELOG: NV offset 0x57f000 size 0x1000
9358 22:51:12.649392 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9359 22:51:12.656347 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9360 22:51:12.663485 ELOG: Event(17) added with size 13 at 2024-05-07 22:50:01 UTC
9361 22:51:12.663601 out: cmd=0x121: 03 db 21 01 00 00 00 00
9362 22:51:12.667711 in-header: 03 71 00 00 2c 00 00 00
9363 22:51:12.680744 in-data: ce 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9364 22:51:12.687692 ELOG: Event(A1) added with size 10 at 2024-05-07 22:50:01 UTC
9365 22:51:12.694288 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9366 22:51:12.700930 ELOG: Event(A0) added with size 9 at 2024-05-07 22:50:01 UTC
9367 22:51:12.704248 elog_add_boot_reason: Logged dev mode boot
9368 22:51:12.707717 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9369 22:51:12.710933 Finalize devices...
9370 22:51:12.711077 Devices finalized
9371 22:51:12.717833 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9372 22:51:12.720944 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9373 22:51:12.724076 in-header: 03 07 00 00 08 00 00 00
9374 22:51:12.727736 in-data: aa e4 47 04 13 02 00 00
9375 22:51:12.730915 Chrome EC: UHEPI supported
9376 22:51:12.737739 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9377 22:51:12.740775 in-header: 03 a9 00 00 08 00 00 00
9378 22:51:12.743783 in-data: 84 60 60 08 00 00 00 00
9379 22:51:12.747434 ELOG: Event(91) added with size 10 at 2024-05-07 22:50:01 UTC
9380 22:51:12.753966 Chrome EC: clear events_b mask to 0x0000000020004000
9381 22:51:12.760845 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9382 22:51:12.764339 in-header: 03 fd 00 00 00 00 00 00
9383 22:51:12.764442 in-data:
9384 22:51:12.770928 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9385 22:51:12.774248 Writing coreboot table at 0xffe64000
9386 22:51:12.777630 0. 000000000010a000-0000000000113fff: RAMSTAGE
9387 22:51:12.781121 1. 0000000040000000-00000000400fffff: RAM
9388 22:51:12.784233 2. 0000000040100000-000000004032afff: RAMSTAGE
9389 22:51:12.787817 3. 000000004032b000-00000000545fffff: RAM
9390 22:51:12.794483 4. 0000000054600000-000000005465ffff: BL31
9391 22:51:12.797696 5. 0000000054660000-00000000ffe63fff: RAM
9392 22:51:12.801181 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9393 22:51:12.804096 7. 0000000100000000-000000023fffffff: RAM
9394 22:51:12.807378 Passing 5 GPIOs to payload:
9395 22:51:12.813943 NAME | PORT | POLARITY | VALUE
9396 22:51:12.817479 EC in RW | 0x000000aa | low | undefined
9397 22:51:12.820777 EC interrupt | 0x00000005 | low | undefined
9398 22:51:12.827575 TPM interrupt | 0x000000ab | high | undefined
9399 22:51:12.831005 SD card detect | 0x00000011 | high | undefined
9400 22:51:12.837152 speaker enable | 0x00000093 | high | undefined
9401 22:51:12.840695 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9402 22:51:12.843917 in-header: 03 f9 00 00 02 00 00 00
9403 22:51:12.844001 in-data: 02 00
9404 22:51:12.847488 ADC[4]: Raw value=900663 ID=7
9405 22:51:12.850734 ADC[3]: Raw value=213179 ID=1
9406 22:51:12.854200 RAM Code: 0x71
9407 22:51:12.854287 ADC[6]: Raw value=74502 ID=0
9408 22:51:12.857253 ADC[5]: Raw value=212810 ID=1
9409 22:51:12.860451 SKU Code: 0x1
9410 22:51:12.864164 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 822f
9411 22:51:12.867253 coreboot table: 964 bytes.
9412 22:51:12.870580 IMD ROOT 0. 0xfffff000 0x00001000
9413 22:51:12.874008 IMD SMALL 1. 0xffffe000 0x00001000
9414 22:51:12.877278 RO MCACHE 2. 0xffffc000 0x00001104
9415 22:51:12.880498 CONSOLE 3. 0xfff7c000 0x00080000
9416 22:51:12.883896 FMAP 4. 0xfff7b000 0x00000452
9417 22:51:12.887305 TIME STAMP 5. 0xfff7a000 0x00000910
9418 22:51:12.890667 VBOOT WORK 6. 0xfff66000 0x00014000
9419 22:51:12.893725 RAMOOPS 7. 0xffe66000 0x00100000
9420 22:51:12.897489 COREBOOT 8. 0xffe64000 0x00002000
9421 22:51:12.897569 IMD small region:
9422 22:51:12.900780 IMD ROOT 0. 0xffffec00 0x00000400
9423 22:51:12.904185 VPD 1. 0xffffeb80 0x0000006c
9424 22:51:12.907621 MMC STATUS 2. 0xffffeb60 0x00000004
9425 22:51:12.913815 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9426 22:51:12.920561 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9427 22:51:12.960069 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9428 22:51:12.963561 Checking segment from ROM address 0x40100000
9429 22:51:12.967238 Checking segment from ROM address 0x4010001c
9430 22:51:12.973382 Loading segment from ROM address 0x40100000
9431 22:51:12.973463 code (compression=0)
9432 22:51:12.983310 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9433 22:51:12.989858 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9434 22:51:12.989937 it's not compressed!
9435 22:51:12.996895 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9436 22:51:13.003498 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9437 22:51:13.020694 Loading segment from ROM address 0x4010001c
9438 22:51:13.020774 Entry Point 0x80000000
9439 22:51:13.023981 Loaded segments
9440 22:51:13.027249 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9441 22:51:13.034293 Jumping to boot code at 0x80000000(0xffe64000)
9442 22:51:13.040700 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9443 22:51:13.047292 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9444 22:51:13.055274 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9445 22:51:13.058340 Checking segment from ROM address 0x40100000
9446 22:51:13.061670 Checking segment from ROM address 0x4010001c
9447 22:51:13.068187 Loading segment from ROM address 0x40100000
9448 22:51:13.068266 code (compression=1)
9449 22:51:13.075061 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9450 22:51:13.084965 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9451 22:51:13.085047 using LZMA
9452 22:51:13.093798 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9453 22:51:13.100336 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9454 22:51:13.103734 Loading segment from ROM address 0x4010001c
9455 22:51:13.103810 Entry Point 0x54601000
9456 22:51:13.107024 Loaded segments
9457 22:51:13.110174 NOTICE: MT8192 bl31_setup
9458 22:51:13.116952 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9459 22:51:13.120310 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9460 22:51:13.123384 WARNING: region 0:
9461 22:51:13.126956 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 22:51:13.127031 WARNING: region 1:
9463 22:51:13.133264 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9464 22:51:13.136972 WARNING: region 2:
9465 22:51:13.140120 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9466 22:51:13.143824 WARNING: region 3:
9467 22:51:13.146733 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 22:51:13.150318 WARNING: region 4:
9469 22:51:13.156873 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 22:51:13.156950 WARNING: region 5:
9471 22:51:13.160232 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 22:51:13.163981 WARNING: region 6:
9473 22:51:13.167048 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 22:51:13.170027 WARNING: region 7:
9475 22:51:13.173394 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 22:51:13.180086 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9477 22:51:13.183177 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9478 22:51:13.186717 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9479 22:51:13.193233 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9480 22:51:13.196420 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9481 22:51:13.199845 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9482 22:51:13.206572 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9483 22:51:13.210088 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9484 22:51:13.216583 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9485 22:51:13.220215 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9486 22:51:13.223269 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9487 22:51:13.230007 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9488 22:51:13.233151 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9489 22:51:13.236657 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9490 22:51:13.243048 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9491 22:51:13.246811 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9492 22:51:13.253118 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9493 22:51:13.256469 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9494 22:51:13.259665 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9495 22:51:13.266665 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9496 22:51:13.269927 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9497 22:51:13.276222 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9498 22:51:13.279542 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9499 22:51:13.283170 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9500 22:51:13.289742 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9501 22:51:13.293017 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9502 22:51:13.299751 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9503 22:51:13.303026 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9504 22:51:13.306428 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9505 22:51:13.312611 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9506 22:51:13.316593 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9507 22:51:13.322998 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9508 22:51:13.326116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9509 22:51:13.329554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9510 22:51:13.332893 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9511 22:51:13.339365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9512 22:51:13.343054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9513 22:51:13.346344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9514 22:51:13.349324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9515 22:51:13.352875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9516 22:51:13.359565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9517 22:51:13.362814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9518 22:51:13.366388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9519 22:51:13.369658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9520 22:51:13.376323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9521 22:51:13.379656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9522 22:51:13.382975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9523 22:51:13.389403 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9524 22:51:13.392786 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9525 22:51:13.396015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9526 22:51:13.402756 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9527 22:51:13.406591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9528 22:51:13.412846 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9529 22:51:13.416174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9530 22:51:13.422671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9531 22:51:13.426187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9532 22:51:13.429325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9533 22:51:13.436160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9534 22:51:13.439547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9535 22:51:13.445826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9536 22:51:13.449386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9537 22:51:13.455882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9538 22:51:13.459206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9539 22:51:13.463035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9540 22:51:13.469368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9541 22:51:13.472559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9542 22:51:13.479339 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9543 22:51:13.482744 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9544 22:51:13.489380 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9545 22:51:13.492909 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9546 22:51:13.496205 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9547 22:51:13.502939 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9548 22:51:13.506066 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9549 22:51:13.512712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9550 22:51:13.515921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9551 22:51:13.522855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9552 22:51:13.526152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9553 22:51:13.532819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9554 22:51:13.536073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9555 22:51:13.539462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9556 22:51:13.545977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9557 22:51:13.549418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9558 22:51:13.556099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9559 22:51:13.559139 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9560 22:51:13.566137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9561 22:51:13.569010 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9562 22:51:13.572612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9563 22:51:13.579242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9564 22:51:13.582688 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9565 22:51:13.589199 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9566 22:51:13.592714 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9567 22:51:13.599255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9568 22:51:13.602794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9569 22:51:13.606365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9570 22:51:13.612548 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9571 22:51:13.616296 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9572 22:51:13.622617 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9573 22:51:13.625767 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9574 22:51:13.629495 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9575 22:51:13.632520 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9576 22:51:13.639238 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9577 22:51:13.642542 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9578 22:51:13.646164 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9579 22:51:13.652537 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9580 22:51:13.656214 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9581 22:51:13.662480 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9582 22:51:13.665976 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9583 22:51:13.669204 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9584 22:51:13.676047 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9585 22:51:13.679142 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9586 22:51:13.685935 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9587 22:51:13.689501 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9588 22:51:13.692597 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9589 22:51:13.699365 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9590 22:51:13.702505 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9591 22:51:13.705956 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9592 22:51:13.712636 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9593 22:51:13.716300 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9594 22:51:13.719635 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9595 22:51:13.726227 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9596 22:51:13.729792 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9597 22:51:13.733047 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9598 22:51:13.736038 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9599 22:51:13.742676 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9600 22:51:13.746165 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9601 22:51:13.749488 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9602 22:51:13.756430 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9603 22:51:13.759238 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9604 22:51:13.763013 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9605 22:51:13.769433 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9606 22:51:13.772860 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9607 22:51:13.779635 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9608 22:51:13.782604 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9609 22:51:13.786139 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9610 22:51:13.792883 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9611 22:51:13.796283 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9612 22:51:13.802829 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9613 22:51:13.806045 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9614 22:51:13.809334 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9615 22:51:13.815975 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9616 22:51:13.819253 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9617 22:51:13.826096 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9618 22:51:13.829585 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9619 22:51:13.832817 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9620 22:51:13.839454 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9621 22:51:13.842569 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9622 22:51:13.845995 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9623 22:51:13.852575 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9624 22:51:13.855927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9625 22:51:13.862410 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9626 22:51:13.865956 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9627 22:51:13.869493 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9628 22:51:13.876093 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9629 22:51:13.879125 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9630 22:51:13.886003 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9631 22:51:13.889176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9632 22:51:13.892636 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9633 22:51:13.899157 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9634 22:51:13.902350 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9635 22:51:13.905726 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9636 22:51:13.912780 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9637 22:51:13.915886 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9638 22:51:13.922774 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9639 22:51:13.925743 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9640 22:51:13.929537 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9641 22:51:13.936006 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9642 22:51:13.939365 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9643 22:51:13.945890 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9644 22:51:13.949424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9645 22:51:13.952604 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9646 22:51:13.959263 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9647 22:51:13.962658 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9648 22:51:13.965759 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9649 22:51:13.972459 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9650 22:51:13.975760 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9651 22:51:13.982442 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9652 22:51:13.985991 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9653 22:51:13.988893 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9654 22:51:13.995576 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9655 22:51:13.999266 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9656 22:51:14.005662 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9657 22:51:14.008790 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9658 22:51:14.012391 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9659 22:51:14.019039 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9660 22:51:14.022320 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9661 22:51:14.028551 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9662 22:51:14.032220 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9663 22:51:14.035220 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9664 22:51:14.041898 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9665 22:51:14.045457 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9666 22:51:14.051689 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9667 22:51:14.054996 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9668 22:51:14.061992 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9669 22:51:14.065219 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9670 22:51:14.068386 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9671 22:51:14.075013 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9672 22:51:14.078886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9673 22:51:14.084819 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9674 22:51:14.088371 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9675 22:51:14.091972 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9676 22:51:14.098568 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9677 22:51:14.101908 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9678 22:51:14.108294 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9679 22:51:14.111541 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9680 22:51:14.118257 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9681 22:51:14.121560 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9682 22:51:14.124832 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9683 22:51:14.131454 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9684 22:51:14.135190 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9685 22:51:14.141470 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9686 22:51:14.145193 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9687 22:51:14.148024 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9688 22:51:14.154878 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9689 22:51:14.157998 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9690 22:51:14.164846 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9691 22:51:14.168344 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9692 22:51:14.171577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9693 22:51:14.177958 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9694 22:51:14.181601 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9695 22:51:14.188341 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9696 22:51:14.191462 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9697 22:51:14.198050 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9698 22:51:14.201423 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9699 22:51:14.204654 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9700 22:51:14.211482 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9701 22:51:14.214742 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9702 22:51:14.221359 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9703 22:51:14.224787 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9704 22:51:14.227863 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9705 22:51:14.234570 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9706 22:51:14.238290 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9707 22:51:14.241098 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9708 22:51:14.244735 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9709 22:51:14.251279 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9710 22:51:14.254695 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9711 22:51:14.257990 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9712 22:51:14.264731 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9713 22:51:14.268184 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9714 22:51:14.271373 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9715 22:51:14.278133 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9716 22:51:14.281130 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9717 22:51:14.287749 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9718 22:51:14.291352 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9719 22:51:14.294648 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9720 22:51:14.301287 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9721 22:51:14.304365 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9722 22:51:14.308135 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9723 22:51:14.314636 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9724 22:51:14.317994 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9725 22:51:14.321007 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9726 22:51:14.327534 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9727 22:51:14.331166 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9728 22:51:14.337574 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9729 22:51:14.341025 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9730 22:51:14.344307 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9731 22:51:14.351008 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9732 22:51:14.354568 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9733 22:51:14.357765 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9734 22:51:14.364187 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9735 22:51:14.367474 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9736 22:51:14.370844 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9737 22:51:14.377420 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9738 22:51:14.380692 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9739 22:51:14.384340 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9740 22:51:14.390762 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9741 22:51:14.394130 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9742 22:51:14.400828 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9743 22:51:14.404115 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9744 22:51:14.407581 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9745 22:51:14.414035 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9746 22:51:14.417575 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9747 22:51:14.420853 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9748 22:51:14.424073 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9749 22:51:14.427109 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9750 22:51:14.433916 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9751 22:51:14.437425 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9752 22:51:14.440576 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9753 22:51:14.443663 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9754 22:51:14.450404 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9755 22:51:14.453702 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9756 22:51:14.457123 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9757 22:51:14.460433 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9758 22:51:14.467089 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9759 22:51:14.470486 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9760 22:51:14.477601 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9761 22:51:14.480726 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9762 22:51:14.486887 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9763 22:51:14.490311 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9764 22:51:14.493935 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9765 22:51:14.500751 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9766 22:51:14.503924 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9767 22:51:14.510417 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9768 22:51:14.513896 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9769 22:51:14.517184 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9770 22:51:14.523955 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9771 22:51:14.526896 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9772 22:51:14.533977 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9773 22:51:14.537193 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9774 22:51:14.540142 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9775 22:51:14.546864 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9776 22:51:14.550242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9777 22:51:14.556747 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9778 22:51:14.560654 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9779 22:51:14.566995 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9780 22:51:14.570313 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9781 22:51:14.573753 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9782 22:51:14.580350 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9783 22:51:14.583756 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9784 22:51:14.587196 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9785 22:51:14.593925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9786 22:51:14.596828 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9787 22:51:14.603732 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9788 22:51:14.607016 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9789 22:51:14.610418 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9790 22:51:14.616975 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9791 22:51:14.620274 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9792 22:51:14.627363 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9793 22:51:14.630576 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9794 22:51:14.636855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9795 22:51:14.640436 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9796 22:51:14.643795 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9797 22:51:14.650336 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9798 22:51:14.653697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9799 22:51:14.660346 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9800 22:51:14.663500 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9801 22:51:14.667019 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9802 22:51:14.673632 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9803 22:51:14.676964 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9804 22:51:14.683438 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9805 22:51:14.686828 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9806 22:51:14.690003 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9807 22:51:14.697060 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9808 22:51:14.700150 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9809 22:51:14.706953 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9810 22:51:14.709851 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9811 22:51:14.713331 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9812 22:51:14.719970 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9813 22:51:14.723646 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9814 22:51:14.730267 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9815 22:51:14.733330 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9816 22:51:14.736813 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9817 22:51:14.743586 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9818 22:51:14.746956 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9819 22:51:14.753588 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9820 22:51:14.756759 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9821 22:51:14.760223 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9822 22:51:14.766846 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9823 22:51:14.770305 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9824 22:51:14.776752 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9825 22:51:14.779916 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9826 22:51:14.783749 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9827 22:51:14.790113 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9828 22:51:14.793356 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9829 22:51:14.800082 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9830 22:51:14.803621 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9831 22:51:14.810061 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9832 22:51:14.813604 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9833 22:51:14.816727 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9834 22:51:14.823533 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9835 22:51:14.826898 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9836 22:51:14.833724 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9837 22:51:14.836527 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9838 22:51:14.843375 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9839 22:51:14.846714 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9840 22:51:14.850123 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9841 22:51:14.856449 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9842 22:51:14.860017 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9843 22:51:14.866536 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9844 22:51:14.869759 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9845 22:51:14.876791 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9846 22:51:14.879882 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9847 22:51:14.883226 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9848 22:51:14.889765 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9849 22:51:14.893009 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9850 22:51:14.900052 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9851 22:51:14.903173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9852 22:51:14.909784 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9853 22:51:14.913171 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9854 22:51:14.916372 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9855 22:51:14.923065 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9856 22:51:14.926521 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9857 22:51:14.933059 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9858 22:51:14.936711 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9859 22:51:14.942965 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9860 22:51:14.946142 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9861 22:51:14.949894 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9862 22:51:14.956171 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9863 22:51:14.959884 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9864 22:51:14.966511 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9865 22:51:14.969921 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9866 22:51:14.976244 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9867 22:51:14.980045 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9868 22:51:14.986653 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9869 22:51:14.989594 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9870 22:51:14.993179 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9871 22:51:14.999757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9872 22:51:15.003136 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9873 22:51:15.009574 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9874 22:51:15.012990 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9875 22:51:15.019754 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9876 22:51:15.023285 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9877 22:51:15.026427 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9878 22:51:15.033081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9879 22:51:15.036675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9880 22:51:15.039673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9881 22:51:15.046191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9882 22:51:15.049744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9883 22:51:15.056619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9884 22:51:15.059687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9885 22:51:15.066512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9886 22:51:15.069850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9887 22:51:15.076786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9888 22:51:15.079641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9889 22:51:15.086530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9890 22:51:15.089598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9891 22:51:15.096652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9892 22:51:15.099531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9893 22:51:15.106262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9894 22:51:15.109919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9895 22:51:15.116342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9896 22:51:15.119699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9897 22:51:15.126351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9898 22:51:15.129721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9899 22:51:15.136204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9900 22:51:15.139944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9901 22:51:15.146337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9902 22:51:15.149728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9903 22:51:15.156336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9904 22:51:15.159734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9905 22:51:15.166146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9906 22:51:15.169706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9907 22:51:15.176027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9908 22:51:15.179085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9909 22:51:15.185689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9910 22:51:15.189169 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9911 22:51:15.192383 INFO: [APUAPC] vio 0
9912 22:51:15.195905 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9913 22:51:15.199090 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9914 22:51:15.202339 INFO: [APUAPC] D0_APC_0: 0x400510
9915 22:51:15.205595 INFO: [APUAPC] D0_APC_1: 0x0
9916 22:51:15.208934 INFO: [APUAPC] D0_APC_2: 0x1540
9917 22:51:15.212382 INFO: [APUAPC] D0_APC_3: 0x0
9918 22:51:15.215585 INFO: [APUAPC] D1_APC_0: 0xffffffff
9919 22:51:15.218830 INFO: [APUAPC] D1_APC_1: 0xffffffff
9920 22:51:15.222501 INFO: [APUAPC] D1_APC_2: 0x3fffff
9921 22:51:15.225689 INFO: [APUAPC] D1_APC_3: 0x0
9922 22:51:15.228910 INFO: [APUAPC] D2_APC_0: 0xffffffff
9923 22:51:15.232221 INFO: [APUAPC] D2_APC_1: 0xffffffff
9924 22:51:15.235724 INFO: [APUAPC] D2_APC_2: 0x3fffff
9925 22:51:15.238784 INFO: [APUAPC] D2_APC_3: 0x0
9926 22:51:15.242187 INFO: [APUAPC] D3_APC_0: 0xffffffff
9927 22:51:15.245789 INFO: [APUAPC] D3_APC_1: 0xffffffff
9928 22:51:15.248906 INFO: [APUAPC] D3_APC_2: 0x3fffff
9929 22:51:15.252432 INFO: [APUAPC] D3_APC_3: 0x0
9930 22:51:15.255471 INFO: [APUAPC] D4_APC_0: 0xffffffff
9931 22:51:15.258812 INFO: [APUAPC] D4_APC_1: 0xffffffff
9932 22:51:15.261947 INFO: [APUAPC] D4_APC_2: 0x3fffff
9933 22:51:15.265349 INFO: [APUAPC] D4_APC_3: 0x0
9934 22:51:15.269026 INFO: [APUAPC] D5_APC_0: 0xffffffff
9935 22:51:15.272187 INFO: [APUAPC] D5_APC_1: 0xffffffff
9936 22:51:15.275221 INFO: [APUAPC] D5_APC_2: 0x3fffff
9937 22:51:15.278878 INFO: [APUAPC] D5_APC_3: 0x0
9938 22:51:15.282062 INFO: [APUAPC] D6_APC_0: 0xffffffff
9939 22:51:15.285196 INFO: [APUAPC] D6_APC_1: 0xffffffff
9940 22:51:15.288382 INFO: [APUAPC] D6_APC_2: 0x3fffff
9941 22:51:15.291988 INFO: [APUAPC] D6_APC_3: 0x0
9942 22:51:15.295467 INFO: [APUAPC] D7_APC_0: 0xffffffff
9943 22:51:15.299358 INFO: [APUAPC] D7_APC_1: 0xffffffff
9944 22:51:15.302394 INFO: [APUAPC] D7_APC_2: 0x3fffff
9945 22:51:15.305250 INFO: [APUAPC] D7_APC_3: 0x0
9946 22:51:15.308634 INFO: [APUAPC] D8_APC_0: 0xffffffff
9947 22:51:15.311859 INFO: [APUAPC] D8_APC_1: 0xffffffff
9948 22:51:15.315319 INFO: [APUAPC] D8_APC_2: 0x3fffff
9949 22:51:15.315414 INFO: [APUAPC] D8_APC_3: 0x0
9950 22:51:15.321780 INFO: [APUAPC] D9_APC_0: 0xffffffff
9951 22:51:15.325409 INFO: [APUAPC] D9_APC_1: 0xffffffff
9952 22:51:15.328545 INFO: [APUAPC] D9_APC_2: 0x3fffff
9953 22:51:15.328640 INFO: [APUAPC] D9_APC_3: 0x0
9954 22:51:15.331935 INFO: [APUAPC] D10_APC_0: 0xffffffff
9955 22:51:15.338356 INFO: [APUAPC] D10_APC_1: 0xffffffff
9956 22:51:15.341892 INFO: [APUAPC] D10_APC_2: 0x3fffff
9957 22:51:15.341969 INFO: [APUAPC] D10_APC_3: 0x0
9958 22:51:15.344900 INFO: [APUAPC] D11_APC_0: 0xffffffff
9959 22:51:15.351838 INFO: [APUAPC] D11_APC_1: 0xffffffff
9960 22:51:15.354905 INFO: [APUAPC] D11_APC_2: 0x3fffff
9961 22:51:15.354979 INFO: [APUAPC] D11_APC_3: 0x0
9962 22:51:15.361462 INFO: [APUAPC] D12_APC_0: 0xffffffff
9963 22:51:15.365249 INFO: [APUAPC] D12_APC_1: 0xffffffff
9964 22:51:15.368244 INFO: [APUAPC] D12_APC_2: 0x3fffff
9965 22:51:15.368340 INFO: [APUAPC] D12_APC_3: 0x0
9966 22:51:15.375032 INFO: [APUAPC] D13_APC_0: 0xffffffff
9967 22:51:15.378210 INFO: [APUAPC] D13_APC_1: 0xffffffff
9968 22:51:15.381926 INFO: [APUAPC] D13_APC_2: 0x3fffff
9969 22:51:15.381993 INFO: [APUAPC] D13_APC_3: 0x0
9970 22:51:15.385387 INFO: [APUAPC] D14_APC_0: 0xffffffff
9971 22:51:15.391582 INFO: [APUAPC] D14_APC_1: 0xffffffff
9972 22:51:15.395036 INFO: [APUAPC] D14_APC_2: 0x3fffff
9973 22:51:15.395104 INFO: [APUAPC] D14_APC_3: 0x0
9974 22:51:15.401932 INFO: [APUAPC] D15_APC_0: 0xffffffff
9975 22:51:15.404829 INFO: [APUAPC] D15_APC_1: 0xffffffff
9976 22:51:15.408507 INFO: [APUAPC] D15_APC_2: 0x3fffff
9977 22:51:15.408604 INFO: [APUAPC] D15_APC_3: 0x0
9978 22:51:15.411869 INFO: [APUAPC] APC_CON: 0x4
9979 22:51:15.414795 INFO: [NOCDAPC] D0_APC_0: 0x0
9980 22:51:15.418334 INFO: [NOCDAPC] D0_APC_1: 0x0
9981 22:51:15.421768 INFO: [NOCDAPC] D1_APC_0: 0x0
9982 22:51:15.424785 INFO: [NOCDAPC] D1_APC_1: 0xfff
9983 22:51:15.428161 INFO: [NOCDAPC] D2_APC_0: 0x0
9984 22:51:15.431478 INFO: [NOCDAPC] D2_APC_1: 0xfff
9985 22:51:15.435069 INFO: [NOCDAPC] D3_APC_0: 0x0
9986 22:51:15.438218 INFO: [NOCDAPC] D3_APC_1: 0xfff
9987 22:51:15.438292 INFO: [NOCDAPC] D4_APC_0: 0x0
9988 22:51:15.441727 INFO: [NOCDAPC] D4_APC_1: 0xfff
9989 22:51:15.444955 INFO: [NOCDAPC] D5_APC_0: 0x0
9990 22:51:15.448167 INFO: [NOCDAPC] D5_APC_1: 0xfff
9991 22:51:15.451326 INFO: [NOCDAPC] D6_APC_0: 0x0
9992 22:51:15.455171 INFO: [NOCDAPC] D6_APC_1: 0xfff
9993 22:51:15.458310 INFO: [NOCDAPC] D7_APC_0: 0x0
9994 22:51:15.461290 INFO: [NOCDAPC] D7_APC_1: 0xfff
9995 22:51:15.464696 INFO: [NOCDAPC] D8_APC_0: 0x0
9996 22:51:15.467963 INFO: [NOCDAPC] D8_APC_1: 0xfff
9997 22:51:15.471330 INFO: [NOCDAPC] D9_APC_0: 0x0
9998 22:51:15.471427 INFO: [NOCDAPC] D9_APC_1: 0xfff
9999 22:51:15.474776 INFO: [NOCDAPC] D10_APC_0: 0x0
10000 22:51:15.477746 INFO: [NOCDAPC] D10_APC_1: 0xfff
10001 22:51:15.481457 INFO: [NOCDAPC] D11_APC_0: 0x0
10002 22:51:15.484693 INFO: [NOCDAPC] D11_APC_1: 0xfff
10003 22:51:15.487811 INFO: [NOCDAPC] D12_APC_0: 0x0
10004 22:51:15.491432 INFO: [NOCDAPC] D12_APC_1: 0xfff
10005 22:51:15.494824 INFO: [NOCDAPC] D13_APC_0: 0x0
10006 22:51:15.498220 INFO: [NOCDAPC] D13_APC_1: 0xfff
10007 22:51:15.501376 INFO: [NOCDAPC] D14_APC_0: 0x0
10008 22:51:15.504591 INFO: [NOCDAPC] D14_APC_1: 0xfff
10009 22:51:15.508065 INFO: [NOCDAPC] D15_APC_0: 0x0
10010 22:51:15.511022 INFO: [NOCDAPC] D15_APC_1: 0xfff
10011 22:51:15.514497 INFO: [NOCDAPC] APC_CON: 0x4
10012 22:51:15.517863 INFO: [APUAPC] set_apusys_apc done
10013 22:51:15.517964 INFO: [DEVAPC] devapc_init done
10014 22:51:15.524462 INFO: GICv3 without legacy support detected.
10015 22:51:15.527692 INFO: ARM GICv3 driver initialized in EL3
10016 22:51:15.530917 INFO: Maximum SPI INTID supported: 639
10017 22:51:15.534287 INFO: BL31: Initializing runtime services
10018 22:51:15.541170 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10019 22:51:15.544455 INFO: SPM: enable CPC mode
10020 22:51:15.547976 INFO: mcdi ready for mcusys-off-idle and system suspend
10021 22:51:15.554212 INFO: BL31: Preparing for EL3 exit to normal world
10022 22:51:15.557669 INFO: Entry point address = 0x80000000
10023 22:51:15.557770 INFO: SPSR = 0x8
10024 22:51:15.565287
10025 22:51:15.565428
10026 22:51:15.565518
10027 22:51:15.566243 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10028 22:51:15.566381 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10029 22:51:15.566492 Setting prompt string to ['asurada:']
10030 22:51:15.566609 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10031 22:51:15.568382 Starting depthcharge on Spherion...
10032 22:51:15.568483
10033 22:51:15.568583 Wipe memory regions:
10034 22:51:15.568646
10035 22:51:15.571673 [0x00000040000000, 0x00000054600000)
10036 22:51:15.693732
10037 22:51:15.693824 [0x00000054660000, 0x00000080000000)
10038 22:51:15.954609
10039 22:51:15.954796 [0x000000821a7280, 0x000000ffe64000)
10040 22:51:16.699148
10041 22:51:16.699292 [0x00000100000000, 0x00000240000000)
10042 22:51:18.589093
10043 22:51:18.592508 Initializing XHCI USB controller at 0x11200000.
10044 22:51:19.631950
10045 22:51:19.634791 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10046 22:51:19.634874
10047 22:51:19.634956
10048 22:51:19.635019
10049 22:51:19.635299 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10051 22:51:19.735609 asurada: tftpboot 192.168.201.1 13683698/tftp-deploy-ddvax7wk/kernel/image.itb 13683698/tftp-deploy-ddvax7wk/kernel/cmdline
10052 22:51:19.735743 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 22:51:19.735922 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10054 22:51:19.740185 tftpboot 192.168.201.1 13683698/tftp-deploy-ddvax7wk/kernel/image.itp-deploy-ddvax7wk/kernel/cmdline
10055 22:51:19.740346
10056 22:51:19.740466 Waiting for link
10057 22:51:19.898626
10058 22:51:19.898752 R8152: Initializing
10059 22:51:19.898853
10060 22:51:19.901557 Version 9 (ocp_data = 6010)
10061 22:51:19.901630
10062 22:51:19.904894 R8152: Done initializing
10063 22:51:19.904964
10064 22:51:19.905026 Adding net device
10065 22:51:21.779693
10066 22:51:21.779833 done.
10067 22:51:21.779910
10068 22:51:21.779978 MAC: 00:e0:4c:72:2d:d6
10069 22:51:21.780039
10070 22:51:21.782636 Sending DHCP discover... done.
10071 22:51:21.782736
10072 22:51:21.786152 Waiting for reply... done.
10073 22:51:21.786228
10074 22:51:21.789194 Sending DHCP request... done.
10075 22:51:21.789290
10076 22:51:21.789395 Waiting for reply... done.
10077 22:51:21.789457
10078 22:51:21.792806 My ip is 192.168.201.21
10079 22:51:21.792902
10080 22:51:21.795793 The DHCP server ip is 192.168.201.1
10081 22:51:21.795864
10082 22:51:21.799559 TFTP server IP predefined by user: 192.168.201.1
10083 22:51:21.799630
10084 22:51:21.805979 Bootfile predefined by user: 13683698/tftp-deploy-ddvax7wk/kernel/image.itb
10085 22:51:21.806079
10086 22:51:21.809083 Sending tftp read request... done.
10087 22:51:21.809186
10088 22:51:21.812444 Waiting for the transfer...
10089 22:51:21.812543
10090 22:51:22.071952 00000000 ################################################################
10091 22:51:22.072117
10092 22:51:22.339793 00080000 ################################################################
10093 22:51:22.339972
10094 22:51:22.593096 00100000 ################################################################
10095 22:51:22.593229
10096 22:51:22.847271 00180000 ################################################################
10097 22:51:22.847394
10098 22:51:23.099258 00200000 ################################################################
10099 22:51:23.099376
10100 22:51:23.368799 00280000 ################################################################
10101 22:51:23.368957
10102 22:51:23.620807 00300000 ################################################################
10103 22:51:23.620976
10104 22:51:23.861018 00380000 ################################################################
10105 22:51:23.861184
10106 22:51:24.101891 00400000 ################################################################
10107 22:51:24.102023
10108 22:51:24.341967 00480000 ################################################################
10109 22:51:24.342097
10110 22:51:24.584284 00500000 ################################################################
10111 22:51:24.584418
10112 22:51:24.825534 00580000 ################################################################
10113 22:51:24.825663
10114 22:51:25.065961 00600000 ################################################################
10115 22:51:25.066091
10116 22:51:25.308373 00680000 ################################################################
10117 22:51:25.308508
10118 22:51:25.548744 00700000 ################################################################
10119 22:51:25.548877
10120 22:51:25.789455 00780000 ################################################################
10121 22:51:25.789586
10122 22:51:26.029020 00800000 ################################################################
10123 22:51:26.029188
10124 22:51:26.269046 00880000 ################################################################
10125 22:51:26.269214
10126 22:51:26.511089 00900000 ################################################################
10127 22:51:26.511248
10128 22:51:26.752801 00980000 ################################################################
10129 22:51:26.753000
10130 22:51:26.994499 00a00000 ################################################################
10131 22:51:26.994671
10132 22:51:27.235007 00a80000 ################################################################
10133 22:51:27.235174
10134 22:51:27.476531 00b00000 ################################################################
10135 22:51:27.476710
10136 22:51:27.716861 00b80000 ################################################################
10137 22:51:27.717027
10138 22:51:27.958101 00c00000 ################################################################
10139 22:51:27.958241
10140 22:51:28.198994 00c80000 ################################################################
10141 22:51:28.199135
10142 22:51:28.442746 00d00000 ################################################################
10143 22:51:28.442897
10144 22:51:28.685045 00d80000 ################################################################
10145 22:51:28.685182
10146 22:51:28.928705 00e00000 ################################################################
10147 22:51:28.928849
10148 22:51:29.169628 00e80000 ################################################################
10149 22:51:29.169771
10150 22:51:29.412343 00f00000 ################################################################
10151 22:51:29.412487
10152 22:51:29.653242 00f80000 ################################################################
10153 22:51:29.653415
10154 22:51:29.891751 01000000 ################################################################
10155 22:51:29.891883
10156 22:51:30.133396 01080000 ################################################################
10157 22:51:30.133539
10158 22:51:30.374297 01100000 ################################################################
10159 22:51:30.374427
10160 22:51:30.614003 01180000 ################################################################
10161 22:51:30.614162
10162 22:51:30.855917 01200000 ################################################################
10163 22:51:30.856047
10164 22:51:31.097084 01280000 ################################################################
10165 22:51:31.097223
10166 22:51:31.335614 01300000 ################################################################
10167 22:51:31.335782
10168 22:51:31.576346 01380000 ################################################################
10169 22:51:31.576520
10170 22:51:31.819463 01400000 ################################################################
10171 22:51:31.819605
10172 22:51:32.063500 01480000 ################################################################
10173 22:51:32.063637
10174 22:51:32.304933 01500000 ################################################################
10175 22:51:32.305126
10176 22:51:32.545728 01580000 ################################################################
10177 22:51:32.545883
10178 22:51:32.787890 01600000 ################################################################
10179 22:51:32.788028
10180 22:51:33.027640 01680000 ################################################################
10181 22:51:33.027802
10182 22:51:33.268193 01700000 ################################################################
10183 22:51:33.268359
10184 22:51:33.512229 01780000 ################################################################
10185 22:51:33.512398
10186 22:51:33.759494 01800000 ################################################################
10187 22:51:33.759645
10188 22:51:34.000085 01880000 ################################################################
10189 22:51:34.000254
10190 22:51:34.249323 01900000 ################################################################
10191 22:51:34.249473
10192 22:51:34.490497 01980000 ################################################################
10193 22:51:34.490633
10194 22:51:34.730713 01a00000 ################################################################
10195 22:51:34.730846
10196 22:51:34.972081 01a80000 ################################################################
10197 22:51:34.972212
10198 22:51:35.217831 01b00000 ################################################################
10199 22:51:35.217964
10200 22:51:35.460351 01b80000 ################################################################
10201 22:51:35.460511
10202 22:51:35.703229 01c00000 ################################################################
10203 22:51:35.703364
10204 22:51:35.945500 01c80000 ################################################################
10205 22:51:35.945631
10206 22:51:36.186100 01d00000 ################################################################
10207 22:51:36.186233
10208 22:51:36.426926 01d80000 ################################################################
10209 22:51:36.427051
10210 22:51:36.666703 01e00000 ################################################################
10211 22:51:36.666852
10212 22:51:36.907165 01e80000 ################################################################
10213 22:51:36.907298
10214 22:51:37.148400 01f00000 ################################################################
10215 22:51:37.148559
10216 22:51:37.389059 01f80000 ################################################################
10217 22:51:37.389187
10218 22:51:37.629237 02000000 ################################################################
10219 22:51:37.629415
10220 22:51:37.870409 02080000 ################################################################
10221 22:51:37.870582
10222 22:51:38.110920 02100000 ################################################################
10223 22:51:38.111055
10224 22:51:38.356474 02180000 ################################################################
10225 22:51:38.356607
10226 22:51:38.606114 02200000 ################################################################
10227 22:51:38.606246
10228 22:51:38.855898 02280000 ################################################################
10229 22:51:38.856038
10230 22:51:39.115641 02300000 ################################################################
10231 22:51:39.115780
10232 22:51:39.407406 02380000 ################################################################
10233 22:51:39.407538
10234 22:51:39.702318 02400000 ################################################################
10235 22:51:39.702450
10236 22:51:40.045504 02480000 ################################################################
10237 22:51:40.046104
10238 22:51:40.467585 02500000 ################################################################
10239 22:51:40.468090
10240 22:51:40.847604 02580000 ################################################################
10241 22:51:40.848105
10242 22:51:41.175490 02600000 ################################################################
10243 22:51:41.175645
10244 22:51:41.440380 02680000 ################################################################
10245 22:51:41.440521
10246 22:51:41.709629 02700000 ################################################################
10247 22:51:41.709767
10248 22:51:41.966695 02780000 ################################################################
10249 22:51:41.966852
10250 22:51:42.230673 02800000 ################################################################
10251 22:51:42.230808
10252 22:51:42.483836 02880000 ################################################################
10253 22:51:42.484000
10254 22:51:42.750290 02900000 ################################################################
10255 22:51:42.750430
10256 22:51:43.018227 02980000 ################################################################
10257 22:51:43.018358
10258 22:51:43.271878 02a00000 ################################################################
10259 22:51:43.272022
10260 22:51:43.529546 02a80000 ################################################################
10261 22:51:43.529679
10262 22:51:43.797676 02b00000 ################################################################
10263 22:51:43.797807
10264 22:51:44.074554 02b80000 ################################################################
10265 22:51:44.074685
10266 22:51:44.355789 02c00000 ################################################################
10267 22:51:44.355943
10268 22:51:44.609940 02c80000 ################################################################
10269 22:51:44.610089
10270 22:51:44.864268 02d00000 ################################################################
10271 22:51:44.864396
10272 22:51:45.115889 02d80000 ################################################################
10273 22:51:45.116016
10274 22:51:45.401503 02e00000 ################################################################
10275 22:51:45.401643
10276 22:51:45.677538 02e80000 ################################################################
10277 22:51:45.677686
10278 22:51:45.945955 02f00000 ################################################################
10279 22:51:45.946092
10280 22:51:46.230884 02f80000 ################################################################
10281 22:51:46.231016
10282 22:51:46.488884 03000000 ################################################################
10283 22:51:46.489010
10284 22:51:46.819090 03080000 ################################################################
10285 22:51:46.819230
10286 22:51:47.134885 03100000 ################################################################
10287 22:51:47.135531
10288 22:51:47.530469 03180000 ################################################################
10289 22:51:47.531017
10290 22:51:47.849863 03200000 ################################################################
10291 22:51:47.849990
10292 22:51:48.135689 03280000 ################################################################
10293 22:51:48.135847
10294 22:51:48.425925 03300000 ################################################################
10295 22:51:48.426055
10296 22:51:48.604769 03380000 ####################################### done.
10297 22:51:48.604893
10298 22:51:48.608448 The bootfile was 54317182 bytes long.
10299 22:51:48.608916
10300 22:51:48.611605 Sending tftp read request... done.
10301 22:51:48.612068
10302 22:51:48.615408 Waiting for the transfer...
10303 22:51:48.615896
10304 22:51:48.618172 00000000 # done.
10305 22:51:48.618647
10306 22:51:48.626694 Command line loaded dynamically from TFTP file: 13683698/tftp-deploy-ddvax7wk/kernel/cmdline
10307 22:51:48.627259
10308 22:51:48.638282 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10309 22:51:48.638722
10310 22:51:48.639054 Loading FIT.
10311 22:51:48.641749
10312 22:51:48.642166 Image ramdisk-1 has 41208333 bytes.
10313 22:51:48.642500
10314 22:51:48.644872 Image fdt-1 has 47258 bytes.
10315 22:51:48.645380
10316 22:51:48.648086 Image kernel-1 has 13059555 bytes.
10317 22:51:48.648505
10318 22:51:48.657746 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10319 22:51:48.658180
10320 22:51:48.674898 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10321 22:51:48.675467
10322 22:51:48.681728 Choosing best match conf-1 for compat google,spherion-rev2.
10323 22:51:48.682256
10324 22:51:48.689536 Connected to device vid:did:rid of 1ae0:0028:00
10325 22:51:48.696201
10326 22:51:48.699438 tpm_get_response: command 0x17b, return code 0x0
10327 22:51:48.700024
10328 22:51:48.702894 ec_init: CrosEC protocol v3 supported (256, 248)
10329 22:51:48.706924
10330 22:51:48.709962 tpm_cleanup: add release locality here.
10331 22:51:48.710547
10332 22:51:48.710927 Shutting down all USB controllers.
10333 22:51:48.713247
10334 22:51:48.713752 Removing current net device
10335 22:51:48.714128
10336 22:51:48.720401 Exiting depthcharge with code 4 at timestamp: 62453967
10337 22:51:48.720981
10338 22:51:48.723033 LZMA decompressing kernel-1 to 0x821a6718
10339 22:51:48.723509
10340 22:51:48.726537 LZMA decompressing kernel-1 to 0x40000000
10341 22:51:50.337682
10342 22:51:50.338263 jumping to kernel
10343 22:51:50.340330 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10344 22:51:50.340848 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10345 22:51:50.341256 Setting prompt string to ['Linux version [0-9]']
10346 22:51:50.341658 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10347 22:51:50.342032 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10348 22:51:50.419383
10349 22:51:50.422803 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10350 22:51:50.425867 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10351 22:51:50.425984 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10352 22:51:50.426082 Setting prompt string to []
10353 22:51:50.426191 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10354 22:51:50.426301 Using line separator: #'\n'#
10355 22:51:50.426392 No login prompt set.
10356 22:51:50.426496 Parsing kernel messages
10357 22:51:50.426555 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10358 22:51:50.426770 [login-action] Waiting for messages, (timeout 00:03:52)
10359 22:51:50.426878 Waiting using forced prompt support (timeout 00:01:56)
10360 22:51:50.446106 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10361 22:51:50.449376 [ 0.000000] random: crng init done
10362 22:51:50.455815 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10363 22:51:50.459347 [ 0.000000] efi: UEFI not found.
10364 22:51:50.466085 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10365 22:51:50.472821 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10366 22:51:50.482186 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10367 22:51:50.492433 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10368 22:51:50.499062 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10369 22:51:50.506056 [ 0.000000] printk: bootconsole [mtk8250] enabled
10370 22:51:50.512315 [ 0.000000] NUMA: No NUMA configuration found
10371 22:51:50.519090 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10372 22:51:50.522161 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10373 22:51:50.525582 [ 0.000000] Zone ranges:
10374 22:51:50.531929 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10375 22:51:50.535953 [ 0.000000] DMA32 empty
10376 22:51:50.542382 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10377 22:51:50.545389 [ 0.000000] Movable zone start for each node
10378 22:51:50.548733 [ 0.000000] Early memory node ranges
10379 22:51:50.555276 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10380 22:51:50.561860 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10381 22:51:50.568628 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10382 22:51:50.575201 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10383 22:51:50.582095 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10384 22:51:50.588380 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10385 22:51:50.644897 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10386 22:51:50.651507 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10387 22:51:50.658092 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10388 22:51:50.661012 [ 0.000000] psci: probing for conduit method from DT.
10389 22:51:50.668093 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10390 22:51:50.671138 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10391 22:51:50.677497 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10392 22:51:50.680999 [ 0.000000] psci: SMC Calling Convention v1.2
10393 22:51:50.687660 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10394 22:51:50.691162 [ 0.000000] Detected VIPT I-cache on CPU0
10395 22:51:50.697758 [ 0.000000] CPU features: detected: GIC system register CPU interface
10396 22:51:50.704587 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10397 22:51:50.711069 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10398 22:51:50.717509 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10399 22:51:50.723753 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10400 22:51:50.730579 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10401 22:51:50.737440 [ 0.000000] alternatives: applying boot alternatives
10402 22:51:50.740462 [ 0.000000] Fallback order for Node 0: 0
10403 22:51:50.750713 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10404 22:51:50.751281 [ 0.000000] Policy zone: Normal
10405 22:51:50.766915 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10406 22:51:50.777176 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10407 22:51:50.788530 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10408 22:51:50.798879 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10409 22:51:50.805254 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10410 22:51:50.808567 <6>[ 0.000000] software IO TLB: area num 8.
10411 22:51:50.864783 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10412 22:51:51.014094 <6>[ 0.000000] Memory: 7923948K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 428820K reserved, 32768K cma-reserved)
10413 22:51:51.020670 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10414 22:51:51.027656 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10415 22:51:51.030716 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10416 22:51:51.037382 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10417 22:51:51.043875 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10418 22:51:51.047392 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10419 22:51:51.057176 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10420 22:51:51.063802 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10421 22:51:51.070698 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10422 22:51:51.076792 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10423 22:51:51.080133 <6>[ 0.000000] GICv3: 608 SPIs implemented
10424 22:51:51.083438 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10425 22:51:51.090317 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10426 22:51:51.093268 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10427 22:51:51.100042 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10428 22:51:51.112986 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10429 22:51:51.126327 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10430 22:51:51.132440 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10431 22:51:51.140440 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10432 22:51:51.153700 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10433 22:51:51.160179 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10434 22:51:51.166940 <6>[ 0.009233] Console: colour dummy device 80x25
10435 22:51:51.176975 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10436 22:51:51.183499 <6>[ 0.024395] pid_max: default: 32768 minimum: 301
10437 22:51:51.186998 <6>[ 0.029266] LSM: Security Framework initializing
10438 22:51:51.193427 <6>[ 0.034228] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10439 22:51:51.203578 <6>[ 0.042042] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 22:51:51.210324 <6>[ 0.051469] cblist_init_generic: Setting adjustable number of callback queues.
10441 22:51:51.217207 <6>[ 0.058914] cblist_init_generic: Setting shift to 3 and lim to 1.
10442 22:51:51.226861 <6>[ 0.065292] cblist_init_generic: Setting adjustable number of callback queues.
10443 22:51:51.233671 <6>[ 0.072719] cblist_init_generic: Setting shift to 3 and lim to 1.
10444 22:51:51.236570 <6>[ 0.079119] rcu: Hierarchical SRCU implementation.
10445 22:51:51.243106 <6>[ 0.084166] rcu: Max phase no-delay instances is 1000.
10446 22:51:51.249780 <6>[ 0.091224] EFI services will not be available.
10447 22:51:51.252851 <6>[ 0.096186] smp: Bringing up secondary CPUs ...
10448 22:51:51.261046 <6>[ 0.101264] Detected VIPT I-cache on CPU1
10449 22:51:51.268009 <6>[ 0.101335] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10450 22:51:51.274918 <6>[ 0.101366] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10451 22:51:51.278260 <6>[ 0.101704] Detected VIPT I-cache on CPU2
10452 22:51:51.284530 <6>[ 0.101753] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10453 22:51:51.294800 <6>[ 0.101769] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10454 22:51:51.298038 <6>[ 0.102030] Detected VIPT I-cache on CPU3
10455 22:51:51.304482 <6>[ 0.102077] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10456 22:51:51.311089 <6>[ 0.102091] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10457 22:51:51.314224 <6>[ 0.102393] CPU features: detected: Spectre-v4
10458 22:51:51.321281 <6>[ 0.102399] CPU features: detected: Spectre-BHB
10459 22:51:51.324019 <6>[ 0.102404] Detected PIPT I-cache on CPU4
10460 22:51:51.331043 <6>[ 0.102466] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10461 22:51:51.337692 <6>[ 0.102482] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10462 22:51:51.344293 <6>[ 0.102775] Detected PIPT I-cache on CPU5
10463 22:51:51.350741 <6>[ 0.102838] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10464 22:51:51.357336 <6>[ 0.102854] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10465 22:51:51.360540 <6>[ 0.103137] Detected PIPT I-cache on CPU6
10466 22:51:51.367618 <6>[ 0.103202] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10467 22:51:51.374312 <6>[ 0.103218] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10468 22:51:51.381057 <6>[ 0.103519] Detected PIPT I-cache on CPU7
10469 22:51:51.387274 <6>[ 0.103584] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10470 22:51:51.394451 <6>[ 0.103600] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10471 22:51:51.397554 <6>[ 0.103647] smp: Brought up 1 node, 8 CPUs
10472 22:51:51.404243 <6>[ 0.245106] SMP: Total of 8 processors activated.
10473 22:51:51.407396 <6>[ 0.250057] CPU features: detected: 32-bit EL0 Support
10474 22:51:51.417257 <6>[ 0.255419] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10475 22:51:51.424101 <6>[ 0.264220] CPU features: detected: Common not Private translations
10476 22:51:51.430580 <6>[ 0.270695] CPU features: detected: CRC32 instructions
10477 22:51:51.433918 <6>[ 0.276047] CPU features: detected: RCpc load-acquire (LDAPR)
10478 22:51:51.440556 <6>[ 0.282007] CPU features: detected: LSE atomic instructions
10479 22:51:51.447157 <6>[ 0.287789] CPU features: detected: Privileged Access Never
10480 22:51:51.453970 <6>[ 0.293568] CPU features: detected: RAS Extension Support
10481 22:51:51.460585 <6>[ 0.299177] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10482 22:51:51.463407 <6>[ 0.306436] CPU: All CPU(s) started at EL2
10483 22:51:51.470123 <6>[ 0.310753] alternatives: applying system-wide alternatives
10484 22:51:51.479783 <6>[ 0.321583] devtmpfs: initialized
10485 22:51:51.495253 <6>[ 0.330492] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10486 22:51:51.501501 <6>[ 0.340456] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10487 22:51:51.508708 <6>[ 0.348681] pinctrl core: initialized pinctrl subsystem
10488 22:51:51.512045 <6>[ 0.355323] DMI not present or invalid.
10489 22:51:51.518082 <6>[ 0.359736] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10490 22:51:51.528463 <6>[ 0.366604] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10491 22:51:51.534990 <6>[ 0.374194] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10492 22:51:51.544681 <6>[ 0.382410] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10493 22:51:51.548107 <6>[ 0.390652] audit: initializing netlink subsys (disabled)
10494 22:51:51.558255 <5>[ 0.396343] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10495 22:51:51.564553 <6>[ 0.397042] thermal_sys: Registered thermal governor 'step_wise'
10496 22:51:51.570922 <6>[ 0.404310] thermal_sys: Registered thermal governor 'power_allocator'
10497 22:51:51.573951 <6>[ 0.410564] cpuidle: using governor menu
10498 22:51:51.580615 <6>[ 0.421525] NET: Registered PF_QIPCRTR protocol family
10499 22:51:51.587802 <6>[ 0.427000] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10500 22:51:51.594092 <6>[ 0.434101] ASID allocator initialised with 32768 entries
10501 22:51:51.597141 <6>[ 0.440673] Serial: AMBA PL011 UART driver
10502 22:51:51.607602 <4>[ 0.449394] Trying to register duplicate clock ID: 134
10503 22:51:51.665892 <6>[ 0.510913] KASLR enabled
10504 22:51:51.680303 <6>[ 0.518681] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10505 22:51:51.686719 <6>[ 0.525696] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10506 22:51:51.693501 <6>[ 0.532186] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10507 22:51:51.700361 <6>[ 0.539193] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10508 22:51:51.706835 <6>[ 0.545680] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10509 22:51:51.714132 <6>[ 0.552684] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10510 22:51:51.719982 <6>[ 0.559171] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10511 22:51:51.726829 <6>[ 0.566175] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10512 22:51:51.729987 <6>[ 0.573707] ACPI: Interpreter disabled.
10513 22:51:51.738325 <6>[ 0.580127] iommu: Default domain type: Translated
10514 22:51:51.745373 <6>[ 0.585241] iommu: DMA domain TLB invalidation policy: strict mode
10515 22:51:51.748517 <5>[ 0.591901] SCSI subsystem initialized
10516 22:51:51.755018 <6>[ 0.596071] usbcore: registered new interface driver usbfs
10517 22:51:51.761371 <6>[ 0.601803] usbcore: registered new interface driver hub
10518 22:51:51.764954 <6>[ 0.607353] usbcore: registered new device driver usb
10519 22:51:51.771334 <6>[ 0.613449] pps_core: LinuxPPS API ver. 1 registered
10520 22:51:51.781524 <6>[ 0.618644] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10521 22:51:51.785045 <6>[ 0.627993] PTP clock support registered
10522 22:51:51.788574 <6>[ 0.632235] EDAC MC: Ver: 3.0.0
10523 22:51:51.795441 <6>[ 0.637404] FPGA manager framework
10524 22:51:51.799121 <6>[ 0.641092] Advanced Linux Sound Architecture Driver Initialized.
10525 22:51:51.802740 <6>[ 0.647870] vgaarb: loaded
10526 22:51:51.809444 <6>[ 0.651025] clocksource: Switched to clocksource arch_sys_counter
10527 22:51:51.816079 <5>[ 0.657472] VFS: Disk quotas dquot_6.6.0
10528 22:51:51.822813 <6>[ 0.661659] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10529 22:51:51.825823 <6>[ 0.668847] pnp: PnP ACPI: disabled
10530 22:51:51.833735 <6>[ 0.675543] NET: Registered PF_INET protocol family
10531 22:51:51.843722 <6>[ 0.681138] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10532 22:51:51.854617 <6>[ 0.693461] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10533 22:51:51.865283 <6>[ 0.702275] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10534 22:51:51.871425 <6>[ 0.710243] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10535 22:51:51.878254 <6>[ 0.718944] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10536 22:51:51.890037 <6>[ 0.728701] TCP: Hash tables configured (established 65536 bind 65536)
10537 22:51:51.896405 <6>[ 0.735568] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10538 22:51:51.903088 <6>[ 0.742765] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 22:51:51.910054 <6>[ 0.750470] NET: Registered PF_UNIX/PF_LOCAL protocol family
10540 22:51:51.916738 <6>[ 0.756623] RPC: Registered named UNIX socket transport module.
10541 22:51:51.919705 <6>[ 0.762777] RPC: Registered udp transport module.
10542 22:51:51.926393 <6>[ 0.767710] RPC: Registered tcp transport module.
10543 22:51:51.933238 <6>[ 0.772643] RPC: Registered tcp NFSv4.1 backchannel transport module.
10544 22:51:51.936671 <6>[ 0.779311] PCI: CLS 0 bytes, default 64
10545 22:51:51.939721 <6>[ 0.783634] Unpacking initramfs...
10546 22:51:51.957375 <6>[ 0.795606] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10547 22:51:51.967086 <6>[ 0.804279] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10548 22:51:51.970129 <6>[ 0.813127] kvm [1]: IPA Size Limit: 40 bits
10549 22:51:51.977029 <6>[ 0.817655] kvm [1]: GICv3: no GICV resource entry
10550 22:51:51.980557 <6>[ 0.822677] kvm [1]: disabling GICv2 emulation
10551 22:51:51.987100 <6>[ 0.827366] kvm [1]: GIC system register CPU interface enabled
10552 22:51:51.993475 <6>[ 0.835039] kvm [1]: vgic interrupt IRQ18
10553 22:51:51.996587 <6>[ 0.839417] kvm [1]: VHE mode initialized successfully
10554 22:51:52.003975 <5>[ 0.845895] Initialise system trusted keyrings
10555 22:51:52.010608 <6>[ 0.850689] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10556 22:51:52.018898 <6>[ 0.860757] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10557 22:51:52.025561 <5>[ 0.867169] NFS: Registering the id_resolver key type
10558 22:51:52.029007 <5>[ 0.872472] Key type id_resolver registered
10559 22:51:52.035571 <5>[ 0.876887] Key type id_legacy registered
10560 22:51:52.041881 <6>[ 0.881169] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10561 22:51:52.049165 <6>[ 0.888091] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10562 22:51:52.055156 <6>[ 0.895816] 9p: Installing v9fs 9p2000 file system support
10563 22:51:52.091965 <5>[ 0.933690] Key type asymmetric registered
10564 22:51:52.094826 <5>[ 0.938025] Asymmetric key parser 'x509' registered
10565 22:51:52.105007 <6>[ 0.943173] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10566 22:51:52.108607 <6>[ 0.950787] io scheduler mq-deadline registered
10567 22:51:52.111457 <6>[ 0.955556] io scheduler kyber registered
10568 22:51:52.130645 <6>[ 0.972689] EINJ: ACPI disabled.
10569 22:51:52.164298 <4>[ 0.999233] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 22:51:52.173952 <4>[ 1.009859] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 22:51:52.189487 <6>[ 1.031006] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10572 22:51:52.197108 <6>[ 1.039082] printk: console [ttyS0] disabled
10573 22:51:52.225382 <6>[ 1.063713] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10574 22:51:52.231940 <6>[ 1.073192] printk: console [ttyS0] enabled
10575 22:51:52.235043 <6>[ 1.073192] printk: console [ttyS0] enabled
10576 22:51:52.241641 <6>[ 1.082093] printk: bootconsole [mtk8250] disabled
10577 22:51:52.245137 <6>[ 1.082093] printk: bootconsole [mtk8250] disabled
10578 22:51:52.252335 <6>[ 1.093355] SuperH (H)SCI(F) driver initialized
10579 22:51:52.254682 <6>[ 1.098634] msm_serial: driver initialized
10580 22:51:52.269041 <6>[ 1.107528] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10581 22:51:52.278900 <6>[ 1.116078] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10582 22:51:52.285899 <6>[ 1.124620] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10583 22:51:52.296326 <6>[ 1.133249] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10584 22:51:52.302471 <6>[ 1.141957] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10585 22:51:52.312303 <6>[ 1.150673] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10586 22:51:52.322446 <6>[ 1.159217] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10587 22:51:52.329155 <6>[ 1.168026] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10588 22:51:52.338831 <6>[ 1.176573] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10589 22:51:52.350704 <6>[ 1.192282] loop: module loaded
10590 22:51:52.356678 <6>[ 1.198258] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10591 22:51:52.379351 <4>[ 1.221229] mtk-pmic-keys: Failed to locate of_node [id: -1]
10592 22:51:52.386142 <6>[ 1.228202] megasas: 07.719.03.00-rc1
10593 22:51:52.396009 <6>[ 1.237827] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10594 22:51:52.408902 <6>[ 1.250396] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10595 22:51:52.425593 <6>[ 1.267125] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10596 22:51:52.482028 <6>[ 1.317262] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10597 22:51:53.668240 <6>[ 2.510763] Freeing initrd memory: 40236K
10598 22:51:53.680140 <6>[ 2.522410] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10599 22:51:53.691886 <6>[ 2.533487] tun: Universal TUN/TAP device driver, 1.6
10600 22:51:53.694374 <6>[ 2.539571] thunder_xcv, ver 1.0
10601 22:51:53.697888 <6>[ 2.543078] thunder_bgx, ver 1.0
10602 22:51:53.701422 <6>[ 2.546567] nicpf, ver 1.0
10603 22:51:53.712011 <6>[ 2.550584] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10604 22:51:53.715321 <6>[ 2.558060] hns3: Copyright (c) 2017 Huawei Corporation.
10605 22:51:53.721776 <6>[ 2.563650] hclge is initializing
10606 22:51:53.724658 <6>[ 2.567230] e1000: Intel(R) PRO/1000 Network Driver
10607 22:51:53.731461 <6>[ 2.572360] e1000: Copyright (c) 1999-2006 Intel Corporation.
10608 22:51:53.734927 <6>[ 2.578371] e1000e: Intel(R) PRO/1000 Network Driver
10609 22:51:53.741274 <6>[ 2.583587] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10610 22:51:53.747826 <6>[ 2.589773] igb: Intel(R) Gigabit Ethernet Network Driver
10611 22:51:53.754795 <6>[ 2.595423] igb: Copyright (c) 2007-2014 Intel Corporation.
10612 22:51:53.761399 <6>[ 2.601261] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10613 22:51:53.767837 <6>[ 2.607778] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10614 22:51:53.771168 <6>[ 2.614237] sky2: driver version 1.30
10615 22:51:53.777774 <6>[ 2.619170] usbcore: registered new device driver r8152-cfgselector
10616 22:51:53.784627 <6>[ 2.625703] usbcore: registered new interface driver r8152
10617 22:51:53.790855 <6>[ 2.631520] VFIO - User Level meta-driver version: 0.3
10618 22:51:53.797334 <6>[ 2.639807] usbcore: registered new interface driver usb-storage
10619 22:51:53.803988 <6>[ 2.646250] usbcore: registered new device driver onboard-usb-hub
10620 22:51:53.812554 <6>[ 2.655401] mt6397-rtc mt6359-rtc: registered as rtc0
10621 22:51:53.822865 <6>[ 2.660859] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:50:42 UTC (1715122242)
10622 22:51:53.826008 <6>[ 2.670426] i2c_dev: i2c /dev entries driver
10623 22:51:53.843026 <6>[ 2.682231] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10624 22:51:53.849565 <4>[ 2.690958] cpu cpu0: supply cpu not found, using dummy regulator
10625 22:51:53.856153 <4>[ 2.697385] cpu cpu1: supply cpu not found, using dummy regulator
10626 22:51:53.863379 <4>[ 2.703789] cpu cpu2: supply cpu not found, using dummy regulator
10627 22:51:53.869531 <4>[ 2.710203] cpu cpu3: supply cpu not found, using dummy regulator
10628 22:51:53.875919 <4>[ 2.716616] cpu cpu4: supply cpu not found, using dummy regulator
10629 22:51:53.882767 <4>[ 2.723017] cpu cpu5: supply cpu not found, using dummy regulator
10630 22:51:53.889193 <4>[ 2.729415] cpu cpu6: supply cpu not found, using dummy regulator
10631 22:51:53.896477 <4>[ 2.735811] cpu cpu7: supply cpu not found, using dummy regulator
10632 22:51:53.915138 <6>[ 2.757472] cpu cpu0: EM: created perf domain
10633 22:51:53.918071 <6>[ 2.762305] cpu cpu4: EM: created perf domain
10634 22:51:53.925402 <6>[ 2.767933] sdhci: Secure Digital Host Controller Interface driver
10635 22:51:53.932119 <6>[ 2.774364] sdhci: Copyright(c) Pierre Ossman
10636 22:51:53.939185 <6>[ 2.779320] Synopsys Designware Multimedia Card Interface Driver
10637 22:51:53.945261 <6>[ 2.785953] sdhci-pltfm: SDHCI platform and OF driver helper
10638 22:51:53.948674 <6>[ 2.785980] mmc0: CQHCI version 5.10
10639 22:51:53.955132 <6>[ 2.795898] ledtrig-cpu: registered to indicate activity on CPUs
10640 22:51:53.962080 <6>[ 2.803042] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10641 22:51:53.968536 <6>[ 2.810097] usbcore: registered new interface driver usbhid
10642 22:51:53.971703 <6>[ 2.815919] usbhid: USB HID core driver
10643 22:51:53.978434 <6>[ 2.820118] spi_master spi0: will run message pump with realtime priority
10644 22:51:54.024575 <6>[ 2.860070] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10645 22:51:54.043638 <6>[ 2.875621] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10646 22:51:54.046687 <6>[ 2.889247] mmc0: Command Queue Engine enabled
10647 22:51:54.053120 <6>[ 2.894024] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10648 22:51:54.060016 <6>[ 2.901313] mmcblk0: mmc0:0001 DA4128 116 GiB
10649 22:51:54.063232 <6>[ 2.906278] cros-ec-spi spi0.0: Chrome EC device registered
10650 22:51:54.069655 <6>[ 2.910407] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10651 22:51:54.077328 <6>[ 2.919745] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10652 22:51:54.084128 <6>[ 2.925775] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10653 22:51:54.090641 <6>[ 2.931735] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10654 22:51:54.108403 <6>[ 2.947269] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10655 22:51:54.115569 <6>[ 2.957856] NET: Registered PF_PACKET protocol family
10656 22:51:54.118884 <6>[ 2.963237] 9pnet: Installing 9P2000 support
10657 22:51:54.125678 <5>[ 2.967805] Key type dns_resolver registered
10658 22:51:54.129113 <6>[ 2.972797] registered taskstats version 1
10659 22:51:54.135742 <5>[ 2.977181] Loading compiled-in X.509 certificates
10660 22:51:54.165399 <4>[ 3.000965] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10661 22:51:54.175313 <4>[ 3.011739] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10662 22:51:54.181945 <3>[ 3.022289] debugfs: File 'uA_load' in directory '/' already present!
10663 22:51:54.188369 <3>[ 3.028992] debugfs: File 'min_uV' in directory '/' already present!
10664 22:51:54.195533 <3>[ 3.035600] debugfs: File 'max_uV' in directory '/' already present!
10665 22:51:54.201805 <3>[ 3.042205] debugfs: File 'constraint_flags' in directory '/' already present!
10666 22:51:54.218537 <6>[ 3.060737] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10667 22:51:54.225115 <6>[ 3.067568] xhci-mtk 11200000.usb: xHCI Host Controller
10668 22:51:54.232118 <6>[ 3.073065] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10669 22:51:54.242276 <6>[ 3.080924] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10670 22:51:54.248509 <6>[ 3.090374] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10671 22:51:54.255345 <6>[ 3.096592] xhci-mtk 11200000.usb: xHCI Host Controller
10672 22:51:54.262005 <6>[ 3.102094] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10673 22:51:54.268149 <6>[ 3.109755] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10674 22:51:54.275264 <6>[ 3.117609] hub 1-0:1.0: USB hub found
10675 22:51:54.278699 <6>[ 3.121634] hub 1-0:1.0: 1 port detected
10676 22:51:54.288655 <6>[ 3.125936] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10677 22:51:54.291949 <6>[ 3.134748] hub 2-0:1.0: USB hub found
10678 22:51:54.295183 <6>[ 3.138786] hub 2-0:1.0: 1 port detected
10679 22:51:54.304292 <6>[ 3.146591] mtk-msdc 11f70000.mmc: Got CD GPIO
10680 22:51:54.316841 <6>[ 3.155712] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10681 22:51:54.323478 <6>[ 3.163738] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10682 22:51:54.333155 <4>[ 3.171669] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10683 22:51:54.343438 <6>[ 3.181210] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10684 22:51:54.349978 <6>[ 3.189291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10685 22:51:54.356737 <6>[ 3.197317] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10686 22:51:54.366430 <6>[ 3.205243] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10687 22:51:54.373106 <6>[ 3.213060] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10688 22:51:54.383067 <6>[ 3.220880] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10689 22:51:54.392676 <6>[ 3.231271] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10690 22:51:54.399670 <6>[ 3.239624] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10691 22:51:54.409438 <6>[ 3.247966] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10692 22:51:54.416128 <6>[ 3.256304] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10693 22:51:54.426125 <6>[ 3.264642] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10694 22:51:54.432972 <6>[ 3.272980] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10695 22:51:54.442966 <6>[ 3.281317] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10696 22:51:54.449406 <6>[ 3.289655] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10697 22:51:54.459368 <6>[ 3.297993] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10698 22:51:54.466282 <6>[ 3.306331] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10699 22:51:54.475989 <6>[ 3.314668] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10700 22:51:54.482447 <6>[ 3.323005] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10701 22:51:54.492612 <6>[ 3.331344] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10702 22:51:54.499142 <6>[ 3.339681] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10703 22:51:54.509146 <6>[ 3.348019] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10704 22:51:54.515687 <6>[ 3.356761] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10705 22:51:54.522136 <6>[ 3.363913] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10706 22:51:54.528947 <6>[ 3.370675] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10707 22:51:54.535403 <6>[ 3.377436] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10708 22:51:54.542116 <6>[ 3.384385] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10709 22:51:54.552076 <6>[ 3.391229] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10710 22:51:54.562519 <6>[ 3.400359] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10711 22:51:54.572090 <6>[ 3.409481] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10712 22:51:54.582063 <6>[ 3.418775] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10713 22:51:54.588580 <6>[ 3.428243] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10714 22:51:54.598840 <6>[ 3.437710] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10715 22:51:54.608611 <6>[ 3.446831] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10716 22:51:54.618656 <6>[ 3.456297] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10717 22:51:54.628382 <6>[ 3.465415] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10718 22:51:54.638461 <6>[ 3.474718] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10719 22:51:54.648654 <6>[ 3.484880] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10720 22:51:54.658491 <6>[ 3.496540] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10721 22:51:54.704196 <6>[ 3.543299] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10722 22:51:54.859154 <6>[ 3.701184] hub 1-1:1.0: USB hub found
10723 22:51:54.862174 <6>[ 3.705711] hub 1-1:1.0: 4 ports detected
10724 22:51:54.872192 <6>[ 3.714223] hub 1-1:1.0: USB hub found
10725 22:51:54.875405 <6>[ 3.718600] hub 1-1:1.0: 4 ports detected
10726 22:51:54.984490 <6>[ 3.823648] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10727 22:51:55.010471 <6>[ 3.852927] hub 2-1:1.0: USB hub found
10728 22:51:55.014192 <6>[ 3.857423] hub 2-1:1.0: 3 ports detected
10729 22:51:55.023421 <6>[ 3.865484] hub 2-1:1.0: USB hub found
10730 22:51:55.026290 <6>[ 3.869937] hub 2-1:1.0: 3 ports detected
10731 22:51:55.200437 <6>[ 4.039324] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10732 22:51:55.332589 <6>[ 4.174857] hub 1-1.4:1.0: USB hub found
10733 22:51:55.335893 <6>[ 4.179437] hub 1-1.4:1.0: 2 ports detected
10734 22:51:55.344548 <6>[ 4.186594] hub 1-1.4:1.0: USB hub found
10735 22:51:55.347682 <6>[ 4.191117] hub 1-1.4:1.0: 2 ports detected
10736 22:51:55.412823 <6>[ 4.251434] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10737 22:51:55.521171 <6>[ 4.359979] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10738 22:51:55.556131 <4>[ 4.395418] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10739 22:51:55.566007 <4>[ 4.404507] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10740 22:51:55.606327 <6>[ 4.448806] r8152 2-1.3:1.0 eth0: v1.12.13
10741 22:51:55.644260 <6>[ 4.483343] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10742 22:51:55.836076 <6>[ 4.675356] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10743 22:51:57.191773 <6>[ 6.034046] r8152 2-1.3:1.0 eth0: carrier on
10744 22:51:59.891934 <5>[ 6.063111] Sending DHCP requests .., OK
10745 22:51:59.898518 <6>[ 8.739612] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10746 22:51:59.901879 <6>[ 8.747922] IP-Config: Complete:
10747 22:51:59.914751 <6>[ 8.751425] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10748 22:51:59.921766 <6>[ 8.762134] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10749 22:51:59.928457 <6>[ 8.770753] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10750 22:51:59.935144 <6>[ 8.770763] nameserver0=192.168.201.1
10751 22:51:59.938176 <6>[ 8.782949] clk: Disabling unused clocks
10752 22:51:59.941410 <6>[ 8.788300] ALSA device list:
10753 22:51:59.948153 <6>[ 8.791696] No soundcards found.
10754 22:51:59.956240 <6>[ 8.799517] Freeing unused kernel memory: 8512K
10755 22:51:59.959804 <6>[ 8.804425] Run /init as init process
10756 22:51:59.989939 <6>[ 8.833098] NET: Registered PF_INET6 protocol family
10757 22:51:59.996572 <6>[ 8.839931] Segment Routing with IPv6
10758 22:51:59.999594 <6>[ 8.843913] In-situ OAM (IOAM) with IPv6
10759 22:52:00.040347 <30>[ 8.857580] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10760 22:52:00.047488 <30>[ 8.890699] systemd[1]: Detected architecture arm64.
10761 22:52:00.047573
10762 22:52:00.053931 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10763 22:52:00.054013
10764 22:52:00.054078
10765 22:52:00.067832 <30>[ 8.911326] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10766 22:52:00.208342 <30>[ 9.047912] systemd[1]: Queued start job for default target graphical.target.
10767 22:52:00.249750 <30>[ 9.089296] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10768 22:52:00.255992 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10769 22:52:00.256078
10770 22:52:00.276634 <30>[ 9.116665] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10771 22:52:00.283053 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10772 22:52:00.283134
10773 22:52:00.304689 <30>[ 9.144396] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10774 22:52:00.314334 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10775 22:52:00.314428
10776 22:52:00.333147 <30>[ 9.172881] systemd[1]: Created slice user.slice - User and Session Slice.
10777 22:52:00.339240 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10778 22:52:00.339322
10779 22:52:00.363227 <30>[ 9.200069] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10780 22:52:00.369962 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10781 22:52:00.373292
10782 22:52:00.390708 <30>[ 9.227540] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10783 22:52:00.397440 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10784 22:52:00.397531
10785 22:52:00.425769 <30>[ 9.255898] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10786 22:52:00.435786 <30>[ 9.275787] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10787 22:52:00.442155 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10788 22:52:00.442243
10789 22:52:00.459802 <30>[ 9.299684] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10790 22:52:00.469179 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10791 22:52:00.469261
10792 22:52:00.487935 <30>[ 9.327731] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10793 22:52:00.497829 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10794 22:52:00.498454
10795 22:52:00.512731 <30>[ 9.355848] systemd[1]: Reached target paths.target - Path Units.
10796 22:52:00.519483 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10797 22:52:00.522529
10798 22:52:00.539937 <30>[ 9.379780] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10799 22:52:00.546707 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10800 22:52:00.547125
10801 22:52:00.563551 <30>[ 9.403314] systemd[1]: Reached target slices.target - Slice Units.
10802 22:52:00.570299 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10803 22:52:00.570854
10804 22:52:00.584531 <30>[ 9.427451] systemd[1]: Reached target swap.target - Swaps.
10805 22:52:00.590936 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10806 22:52:00.591398
10807 22:52:00.612159 <30>[ 9.451440] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10808 22:52:00.621483 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10809 22:52:00.621949
10810 22:52:00.640731 <30>[ 9.480300] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10811 22:52:00.650226 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10812 22:52:00.650695
10813 22:52:00.669789 <30>[ 9.509314] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10814 22:52:00.679502 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10815 22:52:00.679971
10816 22:52:00.696074 <30>[ 9.535946] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10817 22:52:00.705996 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10818 22:52:00.706421
10819 22:52:00.725001 <30>[ 9.564659] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10820 22:52:00.731663 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10821 22:52:00.732127
10822 22:52:00.752426 <30>[ 9.592106] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10823 22:52:00.762654 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10824 22:52:00.763207
10825 22:52:00.780870 <30>[ 9.620097] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10826 22:52:00.790717 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10827 22:52:00.791281
10828 22:52:00.808139 <30>[ 9.647891] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10829 22:52:00.817881 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10830 22:52:00.818362
10831 22:52:00.872284 <30>[ 9.711549] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10832 22:52:00.878405 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10833 22:52:00.878859
10834 22:52:00.900107 <30>[ 9.739652] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10835 22:52:00.906466 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10836 22:52:00.907082
10837 22:52:00.955872 <30>[ 9.795490] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10838 22:52:00.962140 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10839 22:52:00.962608
10840 22:52:00.986441 <30>[ 9.819792] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10841 22:52:01.000150 <30>[ 9.840148] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10842 22:52:01.010165 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10843 22:52:01.010621
10844 22:52:01.032940 <30>[ 9.872683] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10845 22:52:01.039536 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10846 22:52:01.039965
10847 22:52:01.064141 <30>[ 9.903785] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10848 22:52:01.077347 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 9.917610] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10849 22:52:01.080780 Module dm_mod...
10850 22:52:01.081381
10851 22:52:01.132211 <30>[ 9.971843] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10852 22:52:01.138476 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10853 22:52:01.138898
10854 22:52:01.158002 <30>[ 9.997849] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10855 22:52:01.164921 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10856 22:52:01.165505
10857 22:52:01.186614 <30>[ 10.026626] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10858 22:52:01.193432 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10859 22:52:01.194049
10860 22:52:01.223991 <30>[ 10.063505] systemd[1]: Starting systemd-journald.service - Journal Service...
10861 22:52:01.230177 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10862 22:52:01.230693
10863 22:52:01.250316 <30>[ 10.090161] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10864 22:52:01.256607 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10865 22:52:01.257127
10866 22:52:01.283346 <30>[ 10.119967] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10867 22:52:01.289834 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10868 22:52:01.290430
10869 22:52:01.314441 <30>[ 10.154143] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10870 22:52:01.324304 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10871 22:52:01.324874
10872 22:52:01.348917 <30>[ 10.188698] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10873 22:52:01.358877 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10874 22:52:01.359472
10875 22:52:01.387506 <30>[ 10.227679] systemd[1]: Started systemd-journald.service - Journal Service.
10876 22:52:01.394527 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10877 22:52:01.395067
10878 22:52:01.416953 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10879 22:52:01.417578
10880 22:52:01.440539 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10881 22:52:01.440998
10882 22:52:01.460410 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10883 22:52:01.460886
10884 22:52:01.480817 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10885 22:52:01.481326
10886 22:52:01.502365 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10887 22:52:01.502960
10888 22:52:01.522397 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10889 22:52:01.522825
10890 22:52:01.547127 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10891 22:52:01.547700
10892 22:52:01.566306 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10893 22:52:01.566730
10894 22:52:01.591751 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10895 22:52:01.591836
10896 22:52:01.609158 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10897 22:52:01.609268
10898 22:52:01.629217 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10899 22:52:01.629370
10900 22:52:01.654024 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10901 22:52:01.654505
10902 22:52:01.668220 See 'systemctl status systemd-remount-fs.service' for details.
10903 22:52:01.668794
10904 22:52:01.692800 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10905 22:52:01.693357
10906 22:52:01.714341 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10907 22:52:01.714875
10908 22:52:01.767502 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10909 22:52:01.767636
10910 22:52:01.792550 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10911 22:52:01.792639
10912 22:52:01.811662 <46>[ 10.651810] systemd-journald[182]: Received client request to flush runtime journal.
10913 22:52:01.871953 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10914 22:52:01.872144
10915 22:52:01.899382 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10916 22:52:01.899492
10917 22:52:01.923098 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10918 22:52:01.923216
10919 22:52:01.954277 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10920 22:52:01.954385
10921 22:52:01.977095 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10922 22:52:01.977275
10923 22:52:02.000865 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10924 22:52:02.001290
10925 22:52:02.024832 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10926 22:52:02.025363
10927 22:52:02.044749 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10928 22:52:02.045474
10929 22:52:02.087825 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10930 22:52:02.088311
10931 22:52:02.111949 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10932 22:52:02.112373
10933 22:52:02.136082 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10934 22:52:02.136505
10935 22:52:02.151441 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10936 22:52:02.151858
10937 22:52:02.200546 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10938 22:52:02.201145
10939 22:52:02.225940 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10940 22:52:02.226368
10941 22:52:02.250632 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10942 22:52:02.251100
10943 22:52:02.272304 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10944 22:52:02.272809
10945 22:52:02.350580 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10946 22:52:02.351085
10947 22:52:02.386729 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10948 22:52:02.387302
10949 22:52:02.411171 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10950 22:52:02.411593
10951 22:52:02.441115 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10952 22:52:02.441802
10953 22:52:02.466474 <5>[ 11.306061] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10954 22:52:02.476021 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10955 22:52:02.476584
10956 22:52:02.496366 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10957 22:52:02.496454
10958 22:52:02.516809 <5>[ 11.356867] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10959 22:52:02.523238 <5>[ 11.364434] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10960 22:52:02.533531 <4>[ 11.373699] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10961 22:52:02.540284 <6>[ 11.382632] cfg80211: failed to load regulatory.db
10962 22:52:02.563919 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10963 22:52:02.564220
10964 22:52:02.622192 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10965 22:52:02.622679
10966 22:52:02.640872 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10967 22:52:02.641461
10968 22:52:02.663952 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Clean<6>[ 11.505847] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10969 22:52:02.667101 up of Temporary Directories.
10970 22:52:02.667561
10971 22:52:02.677407 <6>[ 11.516344] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10972 22:52:02.680374 <6>[ 11.517896] remoteproc remoteproc0: scp is available
10973 22:52:02.690433 <6>[ 11.524007] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10974 22:52:02.693606 <6>[ 11.529255] remoteproc remoteproc0: powering up scp
10975 22:52:02.703615 <6>[ 11.537873] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10976 22:52:02.710432 <6>[ 11.542995] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10977 22:52:02.716896 <6>[ 11.543020] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10978 22:52:02.730034 [[0;32m OK [0m] Reached target [0;1;39mtime<3>[ 11.569388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10979 22:52:02.740251 -set.target[0m <3>[ 11.578540] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10980 22:52:02.750066 - System Time Se<3>[ 11.587953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10981 22:52:02.750502 t.
10982 22:52:02.750828
10983 22:52:02.768367 [[0;32m OK [<3>[ 11.608988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10984 22:52:02.778253 0m] Started [0;<3>[ 11.618110] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10985 22:52:02.788089 1;39mfstrim.time<3>[ 11.627436] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10986 22:52:02.797945 r[0m - Discard <4>[ 11.630271] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10987 22:52:02.808375 unused blocks on<3>[ 11.637069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10988 22:52:02.808459 ce a week.
10989 22:52:02.808524
10990 22:52:02.811648 <6>[ 11.642208] mc: Linux media interface: v0.10
10991 22:52:02.817973 <4>[ 11.653607] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10992 22:52:02.827681 <3>[ 11.655308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10993 22:52:02.838137 [[0;32m OK [<3>[ 11.677652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10994 22:52:02.844570 0m] Reached targ<6>[ 11.682858] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10995 22:52:02.854476 et [0;1;39mtime<6>[ 11.691423] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10996 22:52:02.860850 <6>[ 11.691484] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10997 22:52:02.867409 <6>[ 11.691492] remoteproc remoteproc0: remote processor scp is now up
10998 22:52:02.877816 rs.target[0m - <6>[ 11.694293] pci_bus 0000:00: root bus resource [bus 00-ff]
10999 22:52:02.877898 Timer Units.
11000 22:52:02.877962
11001 22:52:02.884183 <6>[ 11.694303] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11002 22:52:02.894379 <6>[ 11.694307] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11003 22:52:02.900791 <6>[ 11.694356] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11004 22:52:02.907834 <6>[ 11.694373] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11005 22:52:02.914170 <6>[ 11.694459] pci 0000:00:00.0: supports D1 D2
11006 22:52:02.920717 <3>[ 11.697570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11007 22:52:02.930794 <3>[ 11.697582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11008 22:52:02.937648 <3>[ 11.697587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11009 22:52:02.944469 <6>[ 11.697775] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11010 22:52:02.954608 <3>[ 11.704841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11011 22:52:02.961017 <6>[ 11.711283] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11012 22:52:02.970720 <6>[ 11.724031] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11013 22:52:02.980432 <4>[ 11.724805] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11014 22:52:02.984113 <4>[ 11.724805] Fallback method does not support PEC.
11015 22:52:02.993594 <3>[ 11.724892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11016 22:52:03.000347 <6>[ 11.745001] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11017 22:52:03.010145 <3>[ 11.749514] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11018 22:52:03.016803 <3>[ 11.749524] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11019 22:52:03.026980 <3>[ 11.749531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11020 22:52:03.033186 <6>[ 11.750737] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11021 22:52:03.043672 <3>[ 11.754833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11022 22:52:03.050759 <6>[ 11.769347] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11023 22:52:03.056965 <6>[ 11.770002] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11024 22:52:03.067134 <6>[ 11.782197] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11025 22:52:03.073474 <6>[ 11.785954] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11026 22:52:03.077183 <6>[ 11.794737] videodev: Linux video capture interface: v2.00
11027 22:52:03.086877 <6>[ 11.798589] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11028 22:52:03.093860 <6>[ 11.801745] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11029 22:52:03.097072 <6>[ 11.802459] Bluetooth: Core ver 2.22
11030 22:52:03.103732 <6>[ 11.802527] NET: Registered PF_BLUETOOTH protocol family
11031 22:52:03.110682 <6>[ 11.802531] Bluetooth: HCI device and connection manager initialized
11032 22:52:03.114664 <6>[ 11.802547] Bluetooth: HCI socket layer initialized
11033 22:52:03.121260 <6>[ 11.802557] Bluetooth: L2CAP socket layer initialized
11034 22:52:03.124804 <6>[ 11.802573] Bluetooth: SCO socket layer initialized
11035 22:52:03.131806 <6>[ 11.883906] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11036 22:52:03.142223 <4>[ 11.885078] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11037 22:52:03.149401 <3>[ 11.885085] Bluetooth: hci0: Failed to load firmware file (-2)
11038 22:52:03.156649 <3>[ 11.885087] Bluetooth: hci0: Failed to set up firmware (-2)
11039 22:52:03.166426 <4>[ 11.885090] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11040 22:52:03.173669 <6>[ 11.886448] usbcore: registered new interface driver btusb
11041 22:52:03.180208 <6>[ 11.890062] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11042 22:52:03.190395 <6>[ 11.900510] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11043 22:52:03.197015 <6>[ 11.905815] pci 0000:01:00.0: supports D1 D2
11044 22:52:03.203687 <6>[ 11.906561] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11045 22:52:03.207231 <6>[ 11.914090] usbcore: registered new interface driver uvcvideo
11046 22:52:03.217406 <6>[ 11.921449] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11047 22:52:03.223946 <3>[ 11.929541] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11048 22:52:03.230912 <6>[ 11.951158] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11049 22:52:03.241058 <3>[ 11.978000] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11050 22:52:03.247993 <3>[ 11.978595] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11051 22:52:03.257857 <6>[ 11.981649] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11052 22:52:03.264294 <3>[ 11.997122] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11053 22:52:03.275017 <3>[ 11.997902] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
11054 22:52:03.281919 <6>[ 11.998378] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11055 22:52:03.291584 <3>[ 12.026012] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11056 22:52:03.298367 <6>[ 12.027763] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11057 22:52:03.308825 <6>[ 12.027776] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11058 22:52:03.315754 <3>[ 12.061101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11059 22:52:03.322257 <6>[ 12.064074] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11060 22:52:03.329121 <6>[ 12.064086] pci 0000:00:00.0: PCI bridge to [bus 01]
11061 22:52:03.335610 <6>[ 12.064092] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11062 22:52:03.342404 <6>[ 12.064272] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11063 22:52:03.352341 <3>[ 12.095229] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11064 22:52:03.358765 <6>[ 12.097804] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11065 22:52:03.365097 <3>[ 12.124974] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11066 22:52:03.371863 <6>[ 12.130647] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11067 22:52:03.381854 <3>[ 12.161149] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11068 22:52:03.391880 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11069 22:52:03.392302
11070 22:52:03.403076 <6>[ 12.242870] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11071 22:52:03.407002 <6>[ 12.250407] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11072 22:52:03.416780 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11073 22:52:03.417246
11074 22:52:03.436653 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - B<6>[ 12.277413] mt7921e 0000:01:00.0: ASIC revision: 79610010
11075 22:52:03.437132 asic System.
11076 22:52:03.437539
11077 22:52:03.474829 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11078 22:52:03.475258
11079 22:52:03.499777 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11080 22:52:03.500344
11081 22:52:03.535175 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11082 22:52:03.535737
11083 22:52:03.541619 <6>[ 12.382767] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11084 22:52:03.545006 <6>[ 12.382767]
11085 22:52:03.558518 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11086 22:52:03.558979
11087 22:52:03.585840 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11088 22:52:03.586307
11089 22:52:03.638905 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11090 22:52:03.639392
11091 22:52:03.659318 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11092 22:52:03.659898
11093 22:52:03.675736 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11094 22:52:03.675820
11095 22:52:03.696973 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11096 22:52:03.697618
11097 22:52:03.741955 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11098 22:52:03.742497
11099 22:52:03.763389 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11100 22:52:03.764093
11101 22:52:03.781804 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11102 22:52:03.782346
11103 22:52:03.797645 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11104 22:52:03.798184
11105 22:52:03.811829 <6>[ 12.651839] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11106 22:52:03.822008 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11107 22:52:03.822465
11108 22:52:03.859126 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11109 22:52:03.859684
11110 22:52:03.882799 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11111 22:52:03.883341
11112 22:52:03.909652 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11113 22:52:03.910298
11114 22:52:03.980779 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11115 22:52:03.981263
11116 22:52:04.004858 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11117 22:52:04.005527
11118 22:52:04.027743 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11119 22:52:04.028290
11120 22:52:04.081210
11121 22:52:04.081804
11122 22:52:04.084328 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11123 22:52:04.084783
11124 22:52:04.087627 debian-bookworm-arm64 login: root (automatic login)
11125 22:52:04.088085
11126 22:52:04.088447
11127 22:52:04.100879 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
11128 22:52:04.101371
11129 22:52:04.107739 The programs included with the Debian GNU/Linux system are free software;
11130 22:52:04.114224 the exact distribution terms for each program are described in the
11131 22:52:04.117745 individual files in /usr/share/doc/*/copyright.
11132 22:52:04.118366
11133 22:52:04.124242 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11134 22:52:04.127509 permitted by applicable law.
11135 22:52:04.129081 Matched prompt #10: / #
11137 22:52:04.130451 Setting prompt string to ['/ #']
11138 22:52:04.130954 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11140 22:52:04.132014 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11141 22:52:04.132511 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
11142 22:52:04.132899 Setting prompt string to ['/ #']
11143 22:52:04.133230 Forcing a shell prompt, looking for ['/ #']
11145 22:52:04.184121 / #
11146 22:52:04.184790 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11147 22:52:04.185233 Waiting using forced prompt support (timeout 00:02:30)
11148 22:52:04.190549
11149 22:52:04.191482 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11150 22:52:04.192012 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11151 22:52:04.192515 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11152 22:52:04.193004 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11153 22:52:04.193482 end: 2 depthcharge-action (duration 00:01:22) [common]
11154 22:52:04.193949 start: 3 lava-test-retry (timeout 00:08:17) [common]
11155 22:52:04.194405 start: 3.1 lava-test-shell (timeout 00:08:17) [common]
11156 22:52:04.194784 Using namespace: common
11158 22:52:04.295908 / # #
11159 22:52:04.296553 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11160 22:52:04.302298 #
11161 22:52:04.303174 Using /lava-13683698
11163 22:52:04.404354 / # export SHELL=/bin/sh
11164 22:52:04.410804 export SHELL=/bin/sh
11166 22:52:04.512244 / # . /lava-13683698/environment
11167 22:52:04.518377 . /lava-13683698/environment
11169 22:52:04.619828 / # /lava-13683698/bin/lava-test-runner /lava-13683698/0
11170 22:52:04.620476 Test shell timeout: 10s (minimum of the action and connection timeout)
11171 22:52:04.626505 /lava-13683698/bin/lava-test-runner /lava-13683698/0
11172 22:52:04.652581 + export TESTRUN_ID=0_v4l2-compliance-uvc
11173 22:52:04.656110 + cd /lava-13683698/0/tests/0_v4l2-compliance-uvc
11174 22:52:04.656588 + cat uuid
11175 22:52:04.659053 + UUID=13683698_1.5.2.3.1
11176 22:52:04.659688 + set +x
11177 22:52:04.666006 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 13683698_1.5.2.3.1>
11178 22:52:04.666826 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 13683698_1.5.2.3.1
11179 22:52:04.667223 Starting test lava.0_v4l2-compliance-uvc (13683698_1.5.2.3.1)
11180 22:52:04.667661 Skipping test definition patterns.
11181 22:52:04.668985 + /usr/bin/v4l2-parser.sh -d uvcvideo
11182 22:52:04.675718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11183 22:52:04.676297 device: /dev/video0
11184 22:52:04.676967 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11186 22:52:04.695484 <6>[ 13.538824] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11187 22:52:11.196281 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11188 22:52:11.207944 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11189 22:52:11.219669
11190 22:52:11.233010 Compliance test for uvcvideo device /dev/video0:
11191 22:52:11.244783
11192 22:52:11.257948 Driver Info:
11193 22:52:11.269926 Driver name : uvcvideo
11194 22:52:11.288331 Card type : HD User Facing: HD User Facing
11195 22:52:11.298794 Bus info : usb-11200000.usb-1.4.1
11196 22:52:11.305309 Driver version : 6.1.90
11197 22:52:11.315609 Capabilities : 0x84a00001
11198 22:52:11.330948 Metadata Capture
11199 22:52:11.343846 Streaming
11200 22:52:11.354766 Extended Pix Format
11201 22:52:11.364983 Device Capabilities
11202 22:52:11.376578 Device Caps : 0x04200001
11203 22:52:11.392151 Streaming
11204 22:52:11.405780 Extended Pix Format
11205 22:52:11.415491 Media Driver Info:
11206 22:52:11.426545 Driver name : uvcvideo
11207 22:52:11.441594 Model : HD User Facing: HD User Facing
11208 22:52:11.448161 Serial : 200901010001
11209 22:52:11.462323 Bus info : usb-11200000.usb-1.4.1
11210 22:52:11.470257 Media version : 6.1.90
11211 22:52:11.482826 Hardware revision: 0x00009758 (38744)
11212 22:52:11.491163 Driver version : 6.1.90
11213 22:52:11.501953 Interface Info:
11214 22:52:11.516249 <LAVA_SIGNAL_TESTSET START Interface-Info>
11215 22:52:11.516671 ID : 0x03000002
11216 22:52:11.517265 Received signal: <TESTSET> START Interface-Info
11217 22:52:11.517648 Starting test_set Interface-Info
11218 22:52:11.529191 Type : V4L Video
11219 22:52:11.538882 Entity Info:
11220 22:52:11.546261 <LAVA_SIGNAL_TESTSET STOP>
11221 22:52:11.547119 Received signal: <TESTSET> STOP
11222 22:52:11.547541 Closing test_set Interface-Info
11223 22:52:11.555992 <LAVA_SIGNAL_TESTSET START Entity-Info>
11224 22:52:11.556743 Received signal: <TESTSET> START Entity-Info
11225 22:52:11.557158 Starting test_set Entity-Info
11226 22:52:11.558984 ID : 0x00000001 (1)
11227 22:52:11.568196 Name : HD User Facing: HD User Facing
11228 22:52:11.575034 Function : V4L2 I/O
11229 22:52:11.587251 Flags : default
11230 22:52:11.602855 Pad 0x01000007 : 0: Sink
11231 22:52:11.623712 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11232 22:52:11.627688
11233 22:52:11.637490 Required ioctls:
11234 22:52:11.648686 <LAVA_SIGNAL_TESTSET STOP>
11235 22:52:11.649430 Received signal: <TESTSET> STOP
11236 22:52:11.649842 Closing test_set Entity-Info
11237 22:52:11.658386 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11238 22:52:11.659110 Received signal: <TESTSET> START Required-ioctls
11239 22:52:11.659515 Starting test_set Required-ioctls
11240 22:52:11.661568 test MC information (see 'Media Driver Info' above): OK
11241 22:52:11.686313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11242 22:52:11.687050 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11244 22:52:11.689442 test VIDIOC_QUERYCAP: OK
11245 22:52:11.706909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11246 22:52:11.707586 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11248 22:52:11.710227 test invalid ioctls: OK
11249 22:52:11.731434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11250 22:52:11.731868
11251 22:52:11.732447 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11253 22:52:11.744026 Allow for multiple opens:
11254 22:52:11.751391 <LAVA_SIGNAL_TESTSET STOP>
11255 22:52:11.752061 Received signal: <TESTSET> STOP
11256 22:52:11.752411 Closing test_set Required-ioctls
11257 22:52:11.761730 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11258 22:52:11.762401 Received signal: <TESTSET> START Allow-for-multiple-opens
11259 22:52:11.762755 Starting test_set Allow-for-multiple-opens
11260 22:52:11.764429 test second /dev/video0 open: OK
11261 22:52:11.787517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11262 22:52:11.787770 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11264 22:52:11.790854 test VIDIOC_QUERYCAP: OK
11265 22:52:11.813323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11266 22:52:11.813593 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11268 22:52:11.816399 test VIDIOC_G/S_PRIORITY: OK
11269 22:52:11.838170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11270 22:52:11.838435 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11272 22:52:11.841328 test for unlimited opens: OK
11273 22:52:11.863983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11274 22:52:11.864068
11275 22:52:11.864303 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11277 22:52:11.874590 Debug ioctls:
11278 22:52:11.883107 <LAVA_SIGNAL_TESTSET STOP>
11279 22:52:11.883351 Received signal: <TESTSET> STOP
11280 22:52:11.883431 Closing test_set Allow-for-multiple-opens
11281 22:52:11.893194 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11282 22:52:11.893439 Received signal: <TESTSET> START Debug-ioctls
11283 22:52:11.893508 Starting test_set Debug-ioctls
11284 22:52:11.896413 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11285 22:52:11.920580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11286 22:52:11.920837 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11288 22:52:11.926989 test VIDIOC_LOG_STATUS: OK (Not Supported)
11289 22:52:11.948511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11290 22:52:11.948599
11291 22:52:11.948842 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11293 22:52:11.957617 Input ioctls:
11294 22:52:11.965171 <LAVA_SIGNAL_TESTSET STOP>
11295 22:52:11.965457 Received signal: <TESTSET> STOP
11296 22:52:11.965528 Closing test_set Debug-ioctls
11297 22:52:11.974088 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11298 22:52:11.974340 Received signal: <TESTSET> START Input-ioctls
11299 22:52:11.974410 Starting test_set Input-ioctls
11300 22:52:11.977475 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11301 22:52:12.003222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11302 22:52:12.003477 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11304 22:52:12.006792 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11305 22:52:12.025443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11306 22:52:12.025697 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11308 22:52:12.032459 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11309 22:52:12.054859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11310 22:52:12.055227 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11312 22:52:12.061329 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11313 22:52:12.084168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11314 22:52:12.084472 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11316 22:52:12.087311 test VIDIOC_G/S/ENUMINPUT: OK
11317 22:52:12.114039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11318 22:52:12.114291 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11320 22:52:12.117250 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11321 22:52:12.138336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11322 22:52:12.138590 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11324 22:52:12.141700 Inputs: 1 Audio Inputs: 0 Tuners: 0
11325 22:52:12.153643
11326 22:52:12.171052 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11327 22:52:12.195666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11328 22:52:12.195915 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11330 22:52:12.202108 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11331 22:52:12.222013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11332 22:52:12.222259 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11334 22:52:12.228666 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11335 22:52:12.245379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11336 22:52:12.245625 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11338 22:52:12.251810 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11339 22:52:12.271981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11340 22:52:12.272232 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11342 22:52:12.278435 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11343 22:52:12.294622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11344 22:52:12.294723
11345 22:52:12.294983 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11347 22:52:12.313816 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11348 22:52:12.335560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11349 22:52:12.335807 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11351 22:52:12.342082 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11352 22:52:12.363620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11353 22:52:12.363872 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11355 22:52:12.366797 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11356 22:52:12.385682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11357 22:52:12.385930 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11359 22:52:12.389234 test VIDIOC_G/S_EDID: OK (Not Supported)
11360 22:52:12.413693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11361 22:52:12.413773
11362 22:52:12.414005 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11364 22:52:12.427003 Control ioctls (Input 0):
11365 22:52:12.434580 <LAVA_SIGNAL_TESTSET STOP>
11366 22:52:12.434822 Received signal: <TESTSET> STOP
11367 22:52:12.434888 Closing test_set Input-ioctls
11368 22:52:12.443733 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11369 22:52:12.443975 Received signal: <TESTSET> START Control-ioctls-Input-0
11370 22:52:12.444041 Starting test_set Control-ioctls-Input-0
11371 22:52:12.447044 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11372 22:52:12.472306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11373 22:52:12.472414 test VIDIOC_QUERYCTRL: OK
11374 22:52:12.472681 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11376 22:52:12.494152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11377 22:52:12.494402 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11379 22:52:12.497353 test VIDIOC_G/S_CTRL: OK
11380 22:52:12.519490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11381 22:52:12.519750 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11383 22:52:12.522605 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11384 22:52:12.545708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11385 22:52:12.545977 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11387 22:52:12.552402 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11388 22:52:12.581742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11389 22:52:12.582149 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11391 22:52:12.585223 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11392 22:52:12.602785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11393 22:52:12.603517 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11395 22:52:12.606557 Standard Controls: 16 Private Controls: 0
11396 22:52:12.612419
11397 22:52:12.624100 Format ioctls (Input 0):
11398 22:52:12.631648 <LAVA_SIGNAL_TESTSET STOP>
11399 22:52:12.632319 Received signal: <TESTSET> STOP
11400 22:52:12.632672 Closing test_set Control-ioctls-Input-0
11401 22:52:12.641224 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11402 22:52:12.641956 Received signal: <TESTSET> START Format-ioctls-Input-0
11403 22:52:12.642334 Starting test_set Format-ioctls-Input-0
11404 22:52:12.644635 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11405 22:52:12.668960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11406 22:52:12.669674 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11408 22:52:12.672356 test VIDIOC_G/S_PARM: OK
11409 22:52:12.691172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11410 22:52:12.691940 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11412 22:52:12.694430 test VIDIOC_G_FBUF: OK (Not Supported)
11413 22:52:12.719905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11414 22:52:12.720744 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11416 22:52:12.722961 test VIDIOC_G_FMT: OK
11417 22:52:12.744292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11418 22:52:12.745022 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11420 22:52:12.747552 test VIDIOC_TRY_FMT: OK
11421 22:52:12.767957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11422 22:52:12.768716 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11424 22:52:12.774567 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11425 22:52:12.779092 test VIDIOC_S_FMT: OK
11426 22:52:12.807502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11427 22:52:12.808219 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11429 22:52:12.810726 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11430 22:52:12.833275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11431 22:52:12.834030 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11433 22:52:12.836548 test Cropping: OK (Not Supported)
11434 22:52:12.856358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11435 22:52:12.857041 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11437 22:52:12.859853 test Composing: OK (Not Supported)
11438 22:52:12.882604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11439 22:52:12.883284 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11441 22:52:12.885372 test Scaling: OK (Not Supported)
11442 22:52:12.907719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11443 22:52:12.908150
11444 22:52:12.908735 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11446 22:52:12.918529 Codec ioctls (Input 0):
11447 22:52:12.924772 <LAVA_SIGNAL_TESTSET STOP>
11448 22:52:12.925463 Received signal: <TESTSET> STOP
11449 22:52:12.925827 Closing test_set Format-ioctls-Input-0
11450 22:52:12.934385 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11451 22:52:12.935095 Received signal: <TESTSET> START Codec-ioctls-Input-0
11452 22:52:12.935479 Starting test_set Codec-ioctls-Input-0
11453 22:52:12.937713 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11454 22:52:12.957897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11455 22:52:12.958154 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11457 22:52:12.964699 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11458 22:52:12.983116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11459 22:52:12.983915 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11461 22:52:12.990152 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11462 22:52:13.006790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11463 22:52:13.007242
11464 22:52:13.007823 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11466 22:52:13.019113 Buffer ioctls (Input 0):
11467 22:52:13.027272 <LAVA_SIGNAL_TESTSET STOP>
11468 22:52:13.027995 Received signal: <TESTSET> STOP
11469 22:52:13.028378 Closing test_set Codec-ioctls-Input-0
11470 22:52:13.037052 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11471 22:52:13.037830 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11472 22:52:13.038240 Starting test_set Buffer-ioctls-Input-0
11473 22:52:13.040344 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11474 22:52:13.066005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11475 22:52:13.066736 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11477 22:52:13.069573 test CREATE_BUFS maximum buffers: OK
11478 22:52:13.091742 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11480 22:52:13.094824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11481 22:52:13.095250 test VIDIOC_EXPBUF: OK
11482 22:52:13.116197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11483 22:52:13.116942 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11485 22:52:13.119597 test Requests: OK (Not Supported)
11486 22:52:13.141183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11487 22:52:13.141682
11488 22:52:13.142342 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11490 22:52:13.152516 Test input 0:
11491 22:52:13.163167
11492 22:52:13.179553 Streaming ioctls:
11493 22:52:13.185965 <LAVA_SIGNAL_TESTSET STOP>
11494 22:52:13.186629 Received signal: <TESTSET> STOP
11495 22:52:13.186978 Closing test_set Buffer-ioctls-Input-0
11496 22:52:13.196296 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11497 22:52:13.197031 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11498 22:52:13.197464 Starting test_set Streaming-ioctls_Test-input-0
11499 22:52:13.199392 test read/write: OK (Not Supported)
11500 22:52:13.226688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11501 22:52:13.227449 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11503 22:52:13.229832 test blocking wait: OK
11504 22:52:13.251964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11505 22:52:13.252694 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11507 22:52:13.258646 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11508 22:52:13.261787 test MMAP (no poll): FAIL
11509 22:52:13.286495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11510 22:52:13.287165 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11512 22:52:13.293192 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11513 22:52:13.301766 test MMAP (select): FAIL
11514 22:52:13.325782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11515 22:52:13.326515 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11517 22:52:13.331963 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11518 22:52:13.335489 test MMAP (epoll): FAIL
11519 22:52:13.360102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11520 22:52:13.360584
11521 22:52:13.361210 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11523 22:52:13.373799
11524 22:52:13.551873
11525 22:52:13.559796 test USERPTR (no poll): OK
11526 22:52:13.587958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11527 22:52:13.588436
11528 22:52:13.589138 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11530 22:52:13.601599
11531 22:52:13.793705
11532 22:52:13.805748 test USERPTR (select): OK
11533 22:52:13.834264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11534 22:52:13.835054 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11536 22:52:13.840701 test DMABUF: Cannot test, specify --expbuf-device
11537 22:52:13.846135
11538 22:52:13.864338 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11539 22:52:13.872053 <LAVA_TEST_RUNNER EXIT>
11540 22:52:13.872969 ok: lava_test_shell seems to have completed
11541 22:52:13.873456 Marking unfinished test run as failed
11543 22:52:13.879525 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11544 22:52:13.880217 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11545 22:52:13.880761 end: 3 lava-test-retry (duration 00:00:10) [common]
11546 22:52:13.881243 start: 4 finalize (timeout 00:08:07) [common]
11547 22:52:13.881803 start: 4.1 power-off (timeout 00:00:30) [common]
11548 22:52:13.882677 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11549 22:52:14.144538 >> Command sent successfully.
11550 22:52:14.155734 Returned 0 in 0 seconds
11551 22:52:14.257140 end: 4.1 power-off (duration 00:00:00) [common]
11553 22:52:14.259356 start: 4.2 read-feedback (timeout 00:08:07) [common]
11554 22:52:14.260937 Listened to connection for namespace 'common' for up to 1s
11555 22:52:15.261351 Finalising connection for namespace 'common'
11556 22:52:15.261565 Disconnecting from shell: Finalise
11557 22:52:15.261681 / #
11558 22:52:15.362040 end: 4.2 read-feedback (duration 00:00:01) [common]
11559 22:52:15.362216 end: 4 finalize (duration 00:00:01) [common]
11560 22:52:15.362340 Cleaning after the job
11561 22:52:15.362437 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/ramdisk
11562 22:52:15.366981 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/kernel
11563 22:52:15.379939 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/dtb
11564 22:52:15.380164 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683698/tftp-deploy-ddvax7wk/modules
11565 22:52:15.385751 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683698
11566 22:52:15.445087 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683698
11567 22:52:15.445249 Job finished correctly