Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 14:47:12.969037 lava-dispatcher, installed at version: 2024.03
2 14:47:12.969249 start: 0 validate
3 14:47:12.969463 Start time: 2024-06-04 14:47:12.969452+00:00 (UTC)
4 14:47:12.969620 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:47:12.969805 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:47:13.228459 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:47:13.228629 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:47:27.751863 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:47:27.752636 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:47:28.014489 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:47:28.015164 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:47:28.530667 Using caching service: 'http://localhost/cache/?uri=%s'
13 14:47:28.531344 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 14:47:30.035472 validate duration: 17.07
16 14:47:30.035776 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:47:30.035880 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:47:30.035966 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:47:30.036089 Not decompressing ramdisk as can be used compressed.
20 14:47:30.036172 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 14:47:30.036235 saving as /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/ramdisk/initrd.cpio.gz
22 14:47:30.036298 total size: 5628182 (5 MB)
23 14:47:30.294309 progress 0 % (0 MB)
24 14:47:30.295955 progress 5 % (0 MB)
25 14:47:30.297656 progress 10 % (0 MB)
26 14:47:30.299155 progress 15 % (0 MB)
27 14:47:30.300879 progress 20 % (1 MB)
28 14:47:30.302305 progress 25 % (1 MB)
29 14:47:30.303926 progress 30 % (1 MB)
30 14:47:30.305533 progress 35 % (1 MB)
31 14:47:30.306916 progress 40 % (2 MB)
32 14:47:30.308529 progress 45 % (2 MB)
33 14:47:30.309930 progress 50 % (2 MB)
34 14:47:30.311613 progress 55 % (2 MB)
35 14:47:30.313270 progress 60 % (3 MB)
36 14:47:30.314757 progress 65 % (3 MB)
37 14:47:30.316305 progress 70 % (3 MB)
38 14:47:30.317763 progress 75 % (4 MB)
39 14:47:30.319294 progress 80 % (4 MB)
40 14:47:30.320778 progress 85 % (4 MB)
41 14:47:30.322328 progress 90 % (4 MB)
42 14:47:30.323994 progress 95 % (5 MB)
43 14:47:30.325435 progress 100 % (5 MB)
44 14:47:30.325655 5 MB downloaded in 0.29 s (18.55 MB/s)
45 14:47:30.325827 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:47:30.326142 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:47:30.326247 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:47:30.326350 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:47:30.326506 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 14:47:30.326609 saving as /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/kernel/Image
52 14:47:30.326708 total size: 54682112 (52 MB)
53 14:47:30.326809 No compression specified
54 14:47:30.328510 progress 0 % (0 MB)
55 14:47:30.342420 progress 5 % (2 MB)
56 14:47:30.356710 progress 10 % (5 MB)
57 14:47:30.371034 progress 15 % (7 MB)
58 14:47:30.385619 progress 20 % (10 MB)
59 14:47:30.399747 progress 25 % (13 MB)
60 14:47:30.413883 progress 30 % (15 MB)
61 14:47:30.428114 progress 35 % (18 MB)
62 14:47:30.442613 progress 40 % (20 MB)
63 14:47:30.456857 progress 45 % (23 MB)
64 14:47:30.471516 progress 50 % (26 MB)
65 14:47:30.486141 progress 55 % (28 MB)
66 14:47:30.500469 progress 60 % (31 MB)
67 14:47:30.514634 progress 65 % (33 MB)
68 14:47:30.528982 progress 70 % (36 MB)
69 14:47:30.543547 progress 75 % (39 MB)
70 14:47:30.558486 progress 80 % (41 MB)
71 14:47:30.572872 progress 85 % (44 MB)
72 14:47:30.587198 progress 90 % (46 MB)
73 14:47:30.601640 progress 95 % (49 MB)
74 14:47:30.615438 progress 100 % (52 MB)
75 14:47:30.615729 52 MB downloaded in 0.29 s (180.44 MB/s)
76 14:47:30.615908 end: 1.2.1 http-download (duration 00:00:00) [common]
78 14:47:30.616276 end: 1.2 download-retry (duration 00:00:00) [common]
79 14:47:30.616408 start: 1.3 download-retry (timeout 00:09:59) [common]
80 14:47:30.616511 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 14:47:30.616664 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 14:47:30.616744 saving as /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/dtb/mt8192-asurada-spherion-r0.dtb
83 14:47:30.616844 total size: 47258 (0 MB)
84 14:47:30.616944 No compression specified
85 14:47:30.618645 progress 69 % (0 MB)
86 14:47:30.618960 progress 100 % (0 MB)
87 14:47:30.619158 0 MB downloaded in 0.00 s (19.50 MB/s)
88 14:47:30.619328 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:47:30.619585 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:47:30.619689 start: 1.4 download-retry (timeout 00:09:59) [common]
92 14:47:30.619792 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 14:47:30.619957 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 14:47:30.620058 saving as /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/nfsrootfs/full.rootfs.tar
95 14:47:30.620159 total size: 107552908 (102 MB)
96 14:47:30.620262 Using unxz to decompress xz
97 14:47:30.624735 progress 0 % (0 MB)
98 14:47:30.918677 progress 5 % (5 MB)
99 14:47:31.240710 progress 10 % (10 MB)
100 14:47:31.559965 progress 15 % (15 MB)
101 14:47:31.883203 progress 20 % (20 MB)
102 14:47:32.145409 progress 25 % (25 MB)
103 14:47:32.443737 progress 30 % (30 MB)
104 14:47:32.764449 progress 35 % (35 MB)
105 14:47:32.930793 progress 40 % (41 MB)
106 14:47:33.128254 progress 45 % (46 MB)
107 14:47:33.433292 progress 50 % (51 MB)
108 14:47:33.732908 progress 55 % (56 MB)
109 14:47:34.063248 progress 60 % (61 MB)
110 14:47:34.396131 progress 65 % (66 MB)
111 14:47:34.720239 progress 70 % (71 MB)
112 14:47:35.055397 progress 75 % (76 MB)
113 14:47:35.363895 progress 80 % (82 MB)
114 14:47:35.682582 progress 85 % (87 MB)
115 14:47:35.995241 progress 90 % (92 MB)
116 14:47:36.308408 progress 95 % (97 MB)
117 14:47:36.635467 progress 100 % (102 MB)
118 14:47:36.640937 102 MB downloaded in 6.02 s (17.04 MB/s)
119 14:47:36.641264 end: 1.4.1 http-download (duration 00:00:06) [common]
121 14:47:36.641548 end: 1.4 download-retry (duration 00:00:06) [common]
122 14:47:36.641640 start: 1.5 download-retry (timeout 00:09:53) [common]
123 14:47:36.641744 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 14:47:36.641948 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 14:47:36.642019 saving as /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/modules/modules.tar
126 14:47:36.642079 total size: 8608920 (8 MB)
127 14:47:36.642141 Using unxz to decompress xz
128 14:47:36.646557 progress 0 % (0 MB)
129 14:47:36.666364 progress 5 % (0 MB)
130 14:47:36.695254 progress 10 % (0 MB)
131 14:47:36.727343 progress 15 % (1 MB)
132 14:47:36.753498 progress 20 % (1 MB)
133 14:47:36.778486 progress 25 % (2 MB)
134 14:47:36.803182 progress 30 % (2 MB)
135 14:47:36.828426 progress 35 % (2 MB)
136 14:47:36.856337 progress 40 % (3 MB)
137 14:47:36.879887 progress 45 % (3 MB)
138 14:47:36.904706 progress 50 % (4 MB)
139 14:47:36.933662 progress 55 % (4 MB)
140 14:47:36.960253 progress 60 % (4 MB)
141 14:47:36.985852 progress 65 % (5 MB)
142 14:47:37.011939 progress 70 % (5 MB)
143 14:47:37.038803 progress 75 % (6 MB)
144 14:47:37.065616 progress 80 % (6 MB)
145 14:47:37.091733 progress 85 % (7 MB)
146 14:47:37.118496 progress 90 % (7 MB)
147 14:47:37.145527 progress 95 % (7 MB)
148 14:47:37.172330 progress 100 % (8 MB)
149 14:47:37.178227 8 MB downloaded in 0.54 s (15.31 MB/s)
150 14:47:37.178544 end: 1.5.1 http-download (duration 00:00:01) [common]
152 14:47:37.178877 end: 1.5 download-retry (duration 00:00:01) [common]
153 14:47:37.178973 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 14:47:37.179067 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 14:47:39.335693 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14167046/extract-nfsrootfs-pjnyfw_3
156 14:47:39.335904 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 14:47:39.336030 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 14:47:39.336222 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj
159 14:47:39.336521 makedir: /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin
160 14:47:39.336631 makedir: /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/tests
161 14:47:39.336731 makedir: /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/results
162 14:47:39.336834 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-add-keys
163 14:47:39.336985 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-add-sources
164 14:47:39.337127 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-background-process-start
165 14:47:39.337257 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-background-process-stop
166 14:47:39.337382 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-common-functions
167 14:47:39.337506 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-echo-ipv4
168 14:47:39.337630 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-install-packages
169 14:47:39.337753 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-installed-packages
170 14:47:39.337875 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-os-build
171 14:47:39.337998 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-probe-channel
172 14:47:39.338120 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-probe-ip
173 14:47:39.338241 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-target-ip
174 14:47:39.338363 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-target-mac
175 14:47:39.338486 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-target-storage
176 14:47:39.338612 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-test-case
177 14:47:39.338779 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-test-event
178 14:47:39.338901 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-test-feedback
179 14:47:39.339068 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-test-raise
180 14:47:39.339244 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-test-reference
181 14:47:39.339377 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-test-runner
182 14:47:39.339500 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-test-set
183 14:47:39.339625 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-test-shell
184 14:47:39.339748 Updating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-install-packages (oe)
185 14:47:39.339899 Updating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/bin/lava-installed-packages (oe)
186 14:47:39.340019 Creating /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/environment
187 14:47:39.340113 LAVA metadata
188 14:47:39.340178 - LAVA_JOB_ID=14167046
189 14:47:39.340238 - LAVA_DISPATCHER_IP=192.168.201.1
190 14:47:39.340374 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 14:47:39.340455 skipped lava-vland-overlay
192 14:47:39.340530 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 14:47:39.340610 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 14:47:39.340670 skipped lava-multinode-overlay
195 14:47:39.340787 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 14:47:39.340867 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 14:47:39.340943 Loading test definitions
198 14:47:39.341031 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 14:47:39.341102 Using /lava-14167046 at stage 0
200 14:47:39.341404 uuid=14167046_1.6.2.3.1 testdef=None
201 14:47:39.341493 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 14:47:39.341575 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 14:47:39.342083 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 14:47:39.342305 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 14:47:39.342973 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 14:47:39.343199 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 14:47:39.343801 runner path: /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/0/tests/0_dmesg test_uuid 14167046_1.6.2.3.1
210 14:47:39.343958 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 14:47:39.344158 Creating lava-test-runner.conf files
213 14:47:39.344219 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14167046/lava-overlay-4gh1z9cj/lava-14167046/0 for stage 0
214 14:47:39.344306 - 0_dmesg
215 14:47:39.344600 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 14:47:39.344734 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 14:47:39.350654 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 14:47:39.350802 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 14:47:39.350892 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 14:47:39.350977 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 14:47:39.351061 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 14:47:39.517804 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 14:47:39.518195 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 14:47:39.518360 extracting modules file /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167046/extract-nfsrootfs-pjnyfw_3
225 14:47:39.742188 extracting modules file /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167046/extract-overlay-ramdisk-yar3vcsx/ramdisk
226 14:47:39.967395 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 14:47:39.967608 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 14:47:39.967731 [common] Applying overlay to NFS
229 14:47:39.967829 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167046/compress-overlay-wls8gccb/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14167046/extract-nfsrootfs-pjnyfw_3
230 14:47:39.974885 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 14:47:39.975051 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 14:47:39.975144 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 14:47:39.975232 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 14:47:39.975322 Building ramdisk /var/lib/lava/dispatcher/tmp/14167046/extract-overlay-ramdisk-yar3vcsx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14167046/extract-overlay-ramdisk-yar3vcsx/ramdisk
235 14:47:40.313853 >> 130335 blocks
236 14:47:42.409006 rename /var/lib/lava/dispatcher/tmp/14167046/extract-overlay-ramdisk-yar3vcsx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/ramdisk/ramdisk.cpio.gz
237 14:47:42.409519 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 14:47:42.409675 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 14:47:42.409795 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 14:47:42.409912 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/kernel/Image']
241 14:47:56.427926 Returned 0 in 14 seconds
242 14:47:56.528475 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/kernel/image.itb
243 14:47:56.904126 output: FIT description: Kernel Image image with one or more FDT blobs
244 14:47:56.904486 output: Created: Tue Jun 4 15:47:56 2024
245 14:47:56.904567 output: Image 0 (kernel-1)
246 14:47:56.904632 output: Description:
247 14:47:56.904694 output: Created: Tue Jun 4 15:47:56 2024
248 14:47:56.904757 output: Type: Kernel Image
249 14:47:56.904816 output: Compression: lzma compressed
250 14:47:56.904876 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
251 14:47:56.904939 output: Architecture: AArch64
252 14:47:56.905016 output: OS: Linux
253 14:47:56.905079 output: Load Address: 0x00000000
254 14:47:56.905138 output: Entry Point: 0x00000000
255 14:47:56.905195 output: Hash algo: crc32
256 14:47:56.905252 output: Hash value: 88dcd836
257 14:47:56.905306 output: Image 1 (fdt-1)
258 14:47:56.905362 output: Description: mt8192-asurada-spherion-r0
259 14:47:56.905419 output: Created: Tue Jun 4 15:47:56 2024
260 14:47:56.905472 output: Type: Flat Device Tree
261 14:47:56.905528 output: Compression: uncompressed
262 14:47:56.905580 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 14:47:56.905634 output: Architecture: AArch64
264 14:47:56.905687 output: Hash algo: crc32
265 14:47:56.905740 output: Hash value: 0f8e4d2e
266 14:47:56.905793 output: Image 2 (ramdisk-1)
267 14:47:56.905846 output: Description: unavailable
268 14:47:56.905899 output: Created: Tue Jun 4 15:47:56 2024
269 14:47:56.905952 output: Type: RAMDisk Image
270 14:47:56.906006 output: Compression: Unknown Compression
271 14:47:56.906060 output: Data Size: 18730705 Bytes = 18291.70 KiB = 17.86 MiB
272 14:47:56.906113 output: Architecture: AArch64
273 14:47:56.906166 output: OS: Linux
274 14:47:56.906219 output: Load Address: unavailable
275 14:47:56.906272 output: Entry Point: unavailable
276 14:47:56.906326 output: Hash algo: crc32
277 14:47:56.906379 output: Hash value: 6ec78862
278 14:47:56.906432 output: Default Configuration: 'conf-1'
279 14:47:56.906485 output: Configuration 0 (conf-1)
280 14:47:56.906537 output: Description: mt8192-asurada-spherion-r0
281 14:47:56.906590 output: Kernel: kernel-1
282 14:47:56.906642 output: Init Ramdisk: ramdisk-1
283 14:47:56.906695 output: FDT: fdt-1
284 14:47:56.906748 output: Loadables: kernel-1
285 14:47:56.906824 output:
286 14:47:56.907036 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 14:47:56.907134 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 14:47:56.907246 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
289 14:47:56.907340 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
290 14:47:56.907417 No LXC device requested
291 14:47:56.907497 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 14:47:56.907584 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
293 14:47:56.907662 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 14:47:56.907727 Checking files for TFTP limit of 4294967296 bytes.
295 14:47:56.908237 end: 1 tftp-deploy (duration 00:00:27) [common]
296 14:47:56.908356 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 14:47:56.908458 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 14:47:56.908584 substitutions:
299 14:47:56.908649 - {DTB}: 14167046/tftp-deploy-mx7et379/dtb/mt8192-asurada-spherion-r0.dtb
300 14:47:56.908714 - {INITRD}: 14167046/tftp-deploy-mx7et379/ramdisk/ramdisk.cpio.gz
301 14:47:56.908774 - {KERNEL}: 14167046/tftp-deploy-mx7et379/kernel/Image
302 14:47:56.908830 - {LAVA_MAC}: None
303 14:47:56.908886 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14167046/extract-nfsrootfs-pjnyfw_3
304 14:47:56.908941 - {NFS_SERVER_IP}: 192.168.201.1
305 14:47:56.908996 - {PRESEED_CONFIG}: None
306 14:47:56.909050 - {PRESEED_LOCAL}: None
307 14:47:56.909104 - {RAMDISK}: 14167046/tftp-deploy-mx7et379/ramdisk/ramdisk.cpio.gz
308 14:47:56.909158 - {ROOT_PART}: None
309 14:47:56.909212 - {ROOT}: None
310 14:47:56.909266 - {SERVER_IP}: 192.168.201.1
311 14:47:56.909320 - {TEE}: None
312 14:47:56.909373 Parsed boot commands:
313 14:47:56.909428 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 14:47:56.909617 Parsed boot commands: tftpboot 192.168.201.1 14167046/tftp-deploy-mx7et379/kernel/image.itb 14167046/tftp-deploy-mx7et379/kernel/cmdline
315 14:47:56.909707 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 14:47:56.909796 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 14:47:56.909891 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 14:47:56.909979 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 14:47:56.910052 Not connected, no need to disconnect.
320 14:47:56.910126 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 14:47:56.910206 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 14:47:56.910274 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
323 14:47:56.914299 Setting prompt string to ['lava-test: # ']
324 14:47:56.914721 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 14:47:56.914836 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 14:47:56.914937 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 14:47:56.915032 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 14:47:56.915234 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
329 14:48:02.051353 >> Command sent successfully.
330 14:48:02.054280 Returned 0 in 5 seconds
331 14:48:02.154724 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 14:48:02.155183 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 14:48:02.155296 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 14:48:02.155419 Setting prompt string to 'Starting depthcharge on Spherion...'
336 14:48:02.155541 Changing prompt to 'Starting depthcharge on Spherion...'
337 14:48:02.155644 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 14:48:02.156246 [Enter `^Ec?' for help]
339 14:48:02.329834
340 14:48:02.330036
341 14:48:02.330146 F0: 102B 0000
342 14:48:02.330248
343 14:48:02.330352 F3: 1001 0000 [0200]
344 14:48:02.330449
345 14:48:02.333653 F3: 1001 0000
346 14:48:02.333780
347 14:48:02.333876 F7: 102D 0000
348 14:48:02.333970
349 14:48:02.334060 F1: 0000 0000
350 14:48:02.334153
351 14:48:02.337461 V0: 0000 0000 [0001]
352 14:48:02.337593
353 14:48:02.337695 00: 0007 8000
354 14:48:02.337793
355 14:48:02.341078 01: 0000 0000
356 14:48:02.341218
357 14:48:02.341319 BP: 0C00 0209 [0000]
358 14:48:02.341412
359 14:48:02.344854 G0: 1182 0000
360 14:48:02.344960
361 14:48:02.345058 EC: 0000 0021 [4000]
362 14:48:02.345150
363 14:48:02.348054 S7: 0000 0000 [0000]
364 14:48:02.348165
365 14:48:02.348261 CC: 0000 0000 [0001]
366 14:48:02.348372
367 14:48:02.351771 T0: 0000 0040 [010F]
368 14:48:02.351887
369 14:48:02.351979 Jump to BL
370 14:48:02.352071
371 14:48:02.377117
372 14:48:02.377298
373 14:48:02.384059 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 14:48:02.387282 ARM64: Exception handlers installed.
375 14:48:02.391051 ARM64: Testing exception
376 14:48:02.394887 ARM64: Done test exception
377 14:48:02.401897 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 14:48:02.409519 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 14:48:02.416476 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 14:48:02.427109 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 14:48:02.433626 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 14:48:02.444228 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 14:48:02.454850 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 14:48:02.461241 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 14:48:02.479417 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 14:48:02.482529 WDT: Last reset was cold boot
387 14:48:02.485761 SPI1(PAD0) initialized at 2873684 Hz
388 14:48:02.489531 SPI5(PAD0) initialized at 992727 Hz
389 14:48:02.492573 VBOOT: Loading verstage.
390 14:48:02.499603 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 14:48:02.504000 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 14:48:02.507202 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 14:48:02.510387 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 14:48:02.517206 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 14:48:02.523637 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 14:48:02.534656 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
397 14:48:02.534821
398 14:48:02.534919
399 14:48:02.545473 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 14:48:02.548737 ARM64: Exception handlers installed.
401 14:48:02.548849 ARM64: Testing exception
402 14:48:02.551837 ARM64: Done test exception
403 14:48:02.555022 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 14:48:02.562023 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 14:48:02.575263 Probing TPM: . done!
406 14:48:02.575428 TPM ready after 0 ms
407 14:48:02.582233 Connected to device vid:did:rid of 1ae0:0028:00
408 14:48:02.589170 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 14:48:02.648390 Initialized TPM device CR50 revision 0
410 14:48:02.659806 tlcl_send_startup: Startup return code is 0
411 14:48:02.659960 TPM: setup succeeded
412 14:48:02.671786 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 14:48:02.680435 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 14:48:02.694564 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 14:48:02.702435 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 14:48:02.705337 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 14:48:02.709345 in-header: 03 07 00 00 08 00 00 00
418 14:48:02.712894 in-data: aa e4 47 04 13 02 00 00
419 14:48:02.716650 Chrome EC: UHEPI supported
420 14:48:02.724484 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 14:48:02.728343 in-header: 03 95 00 00 08 00 00 00
422 14:48:02.728441 in-data: 18 20 20 08 00 00 00 00
423 14:48:02.731866 Phase 1
424 14:48:02.735344 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 14:48:02.739134 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 14:48:02.746572 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
427 14:48:02.750287 Recovery requested (1009000e)
428 14:48:02.760444 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 14:48:02.763578 tlcl_extend: response is 0
430 14:48:02.772563 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 14:48:02.778167 tlcl_extend: response is 0
432 14:48:02.785501 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 14:48:02.805344 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
434 14:48:02.811749 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 14:48:02.811864
436 14:48:02.811955
437 14:48:02.821834 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 14:48:02.824997 ARM64: Exception handlers installed.
439 14:48:02.828220 ARM64: Testing exception
440 14:48:02.828343 ARM64: Done test exception
441 14:48:02.850355 pmic_efuse_setting: Set efuses in 11 msecs
442 14:48:02.853840 pmwrap_interface_init: Select PMIF_VLD_RDY
443 14:48:02.860714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 14:48:02.863851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 14:48:02.870950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 14:48:02.875041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 14:48:02.879091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 14:48:02.882673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 14:48:02.889604 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 14:48:02.893626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 14:48:02.896638 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 14:48:02.903755 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 14:48:02.907628 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 14:48:02.911447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 14:48:02.914574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 14:48:02.922239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 14:48:02.929488 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 14:48:02.933248 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 14:48:02.940884 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 14:48:02.944223 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 14:48:02.951992 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 14:48:02.955838 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 14:48:02.963382 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 14:48:02.967185 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 14:48:02.973911 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 14:48:02.977929 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 14:48:02.985389 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 14:48:02.988937 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 14:48:02.996359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 14:48:02.999987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 14:48:03.003691 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 14:48:03.011039 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 14:48:03.014572 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 14:48:03.018518 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 14:48:03.025885 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 14:48:03.029148 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 14:48:03.033068 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 14:48:03.040674 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 14:48:03.044478 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 14:48:03.047938 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 14:48:03.055641 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 14:48:03.059296 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 14:48:03.062661 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 14:48:03.066715 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 14:48:03.070361 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 14:48:03.077572 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 14:48:03.081413 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 14:48:03.085013 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 14:48:03.088837 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 14:48:03.092418 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 14:48:03.096195 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 14:48:03.103234 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 14:48:03.107021 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 14:48:03.114400 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
495 14:48:03.121647 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 14:48:03.124846 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 14:48:03.136507 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 14:48:03.143917 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 14:48:03.147764 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 14:48:03.151540 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 14:48:03.155025 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 14:48:03.164471 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
503 14:48:03.167606 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 14:48:03.172709 [RTC]rtc_osc_init,62: osc32con val = 0xde70
505 14:48:03.179492 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 14:48:03.188788 [RTC]rtc_get_frequency_meter,154: input=15, output=759
507 14:48:03.198005 [RTC]rtc_get_frequency_meter,154: input=23, output=940
508 14:48:03.207511 [RTC]rtc_get_frequency_meter,154: input=19, output=850
509 14:48:03.216457 [RTC]rtc_get_frequency_meter,154: input=17, output=804
510 14:48:03.225779 [RTC]rtc_get_frequency_meter,154: input=16, output=782
511 14:48:03.235977 [RTC]rtc_get_frequency_meter,154: input=16, output=782
512 14:48:03.246162 [RTC]rtc_get_frequency_meter,154: input=17, output=804
513 14:48:03.249537 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
514 14:48:03.253369 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
515 14:48:03.256872 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 14:48:03.264257 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
517 14:48:03.267865 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 14:48:03.272074 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
519 14:48:03.275829 ADC[4]: Raw value=906203 ID=7
520 14:48:03.275958 ADC[3]: Raw value=213441 ID=1
521 14:48:03.279995 RAM Code: 0x71
522 14:48:03.283662 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 14:48:03.287018 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 14:48:03.295024 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 14:48:03.301935 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 14:48:03.306193 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 14:48:03.310155 in-header: 03 07 00 00 08 00 00 00
528 14:48:03.313391 in-data: aa e4 47 04 13 02 00 00
529 14:48:03.313518 Chrome EC: UHEPI supported
530 14:48:03.320459 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 14:48:03.324835 in-header: 03 95 00 00 08 00 00 00
532 14:48:03.328668 in-data: 18 20 20 08 00 00 00 00
533 14:48:03.331926 MRC: failed to locate region type 0.
534 14:48:03.339540 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 14:48:03.343485 DRAM-K: Running full calibration
536 14:48:03.347426 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 14:48:03.350855 header.status = 0x0
538 14:48:03.354850 header.version = 0x6 (expected: 0x6)
539 14:48:03.358570 header.size = 0xd00 (expected: 0xd00)
540 14:48:03.358709 header.flags = 0x0
541 14:48:03.365445 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 14:48:03.382753 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
543 14:48:03.390767 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 14:48:03.390927 dram_init: ddr_geometry: 2
545 14:48:03.394244 [EMI] MDL number = 2
546 14:48:03.394367 [EMI] Get MDL freq = 0
547 14:48:03.397669 dram_init: ddr_type: 0
548 14:48:03.401434 is_discrete_lpddr4: 1
549 14:48:03.401571 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 14:48:03.401672
551 14:48:03.405317
552 14:48:03.405412 [Bian_co] ETT version 0.0.0.1
553 14:48:03.408738 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 14:48:03.412509
555 14:48:03.416194 dramc_set_vcore_voltage set vcore to 650000
556 14:48:03.416322 Read voltage for 800, 4
557 14:48:03.416406 Vio18 = 0
558 14:48:03.420025 Vcore = 650000
559 14:48:03.420138 Vdram = 0
560 14:48:03.420234 Vddq = 0
561 14:48:03.420325 Vmddr = 0
562 14:48:03.423723 dram_init: config_dvfs: 1
563 14:48:03.427687 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 14:48:03.435077 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 14:48:03.438875 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
566 14:48:03.442830 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
567 14:48:03.447165 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
568 14:48:03.450264 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
569 14:48:03.450384 MEM_TYPE=3, freq_sel=18
570 14:48:03.453525 sv_algorithm_assistance_LP4_1600
571 14:48:03.460414 ============ PULL DRAM RESETB DOWN ============
572 14:48:03.463475 ========== PULL DRAM RESETB DOWN end =========
573 14:48:03.467040 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 14:48:03.471362 ===================================
575 14:48:03.475053 LPDDR4 DRAM CONFIGURATION
576 14:48:03.478358 ===================================
577 14:48:03.478471 EX_ROW_EN[0] = 0x0
578 14:48:03.482221 EX_ROW_EN[1] = 0x0
579 14:48:03.482357 LP4Y_EN = 0x0
580 14:48:03.486062 WORK_FSP = 0x0
581 14:48:03.486175 WL = 0x2
582 14:48:03.489306 RL = 0x2
583 14:48:03.489429 BL = 0x2
584 14:48:03.493208 RPST = 0x0
585 14:48:03.493347 RD_PRE = 0x0
586 14:48:03.496291 WR_PRE = 0x1
587 14:48:03.496429 WR_PST = 0x0
588 14:48:03.499258 DBI_WR = 0x0
589 14:48:03.499375 DBI_RD = 0x0
590 14:48:03.502830 OTF = 0x1
591 14:48:03.506732 ===================================
592 14:48:03.510071 ===================================
593 14:48:03.510177 ANA top config
594 14:48:03.513745 ===================================
595 14:48:03.517356 DLL_ASYNC_EN = 0
596 14:48:03.517508 ALL_SLAVE_EN = 1
597 14:48:03.520710 NEW_RANK_MODE = 1
598 14:48:03.523854 DLL_IDLE_MODE = 1
599 14:48:03.523979 LP45_APHY_COMB_EN = 1
600 14:48:03.527523 TX_ODT_DIS = 1
601 14:48:03.530853 NEW_8X_MODE = 1
602 14:48:03.534460 ===================================
603 14:48:03.538568 ===================================
604 14:48:03.541382 data_rate = 1600
605 14:48:03.541538 CKR = 1
606 14:48:03.545208 DQ_P2S_RATIO = 8
607 14:48:03.548308 ===================================
608 14:48:03.551482 CA_P2S_RATIO = 8
609 14:48:03.554699 DQ_CA_OPEN = 0
610 14:48:03.558546 DQ_SEMI_OPEN = 0
611 14:48:03.561577 CA_SEMI_OPEN = 0
612 14:48:03.561711 CA_FULL_RATE = 0
613 14:48:03.564724 DQ_CKDIV4_EN = 1
614 14:48:03.568563 CA_CKDIV4_EN = 1
615 14:48:03.571655 CA_PREDIV_EN = 0
616 14:48:03.575300 PH8_DLY = 0
617 14:48:03.575428 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 14:48:03.578710 DQ_AAMCK_DIV = 4
619 14:48:03.582304 CA_AAMCK_DIV = 4
620 14:48:03.585437 CA_ADMCK_DIV = 4
621 14:48:03.588559 DQ_TRACK_CA_EN = 0
622 14:48:03.591741 CA_PICK = 800
623 14:48:03.594992 CA_MCKIO = 800
624 14:48:03.595100 MCKIO_SEMI = 0
625 14:48:03.599363 PLL_FREQ = 3068
626 14:48:03.602545 DQ_UI_PI_RATIO = 32
627 14:48:03.606413 CA_UI_PI_RATIO = 0
628 14:48:03.610234 ===================================
629 14:48:03.610377 ===================================
630 14:48:03.614722 memory_type:LPDDR4
631 14:48:03.614843 GP_NUM : 10
632 14:48:03.618463 SRAM_EN : 1
633 14:48:03.621869 MD32_EN : 0
634 14:48:03.621982 ===================================
635 14:48:03.625558 [ANA_INIT] >>>>>>>>>>>>>>
636 14:48:03.629920 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 14:48:03.633224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 14:48:03.636394 ===================================
639 14:48:03.636480 data_rate = 1600,PCW = 0X7600
640 14:48:03.639518 ===================================
641 14:48:03.646432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 14:48:03.649828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 14:48:03.656743 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 14:48:03.659664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 14:48:03.663353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 14:48:03.666779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 14:48:03.669625 [ANA_INIT] flow start
648 14:48:03.673451 [ANA_INIT] PLL >>>>>>>>
649 14:48:03.673544 [ANA_INIT] PLL <<<<<<<<
650 14:48:03.676556 [ANA_INIT] MIDPI >>>>>>>>
651 14:48:03.679751 [ANA_INIT] MIDPI <<<<<<<<
652 14:48:03.679866 [ANA_INIT] DLL >>>>>>>>
653 14:48:03.683511 [ANA_INIT] flow end
654 14:48:03.686658 ============ LP4 DIFF to SE enter ============
655 14:48:03.690238 ============ LP4 DIFF to SE exit ============
656 14:48:03.693268 [ANA_INIT] <<<<<<<<<<<<<
657 14:48:03.696479 [Flow] Enable top DCM control >>>>>
658 14:48:03.700302 [Flow] Enable top DCM control <<<<<
659 14:48:03.703725 Enable DLL master slave shuffle
660 14:48:03.709861 ==============================================================
661 14:48:03.709967 Gating Mode config
662 14:48:03.716898 ==============================================================
663 14:48:03.717005 Config description:
664 14:48:03.726878 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 14:48:03.733264 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 14:48:03.740206 SELPH_MODE 0: By rank 1: By Phase
667 14:48:03.743490 ==============================================================
668 14:48:03.746489 GAT_TRACK_EN = 1
669 14:48:03.750144 RX_GATING_MODE = 2
670 14:48:03.753295 RX_GATING_TRACK_MODE = 2
671 14:48:03.756419 SELPH_MODE = 1
672 14:48:03.760287 PICG_EARLY_EN = 1
673 14:48:03.763332 VALID_LAT_VALUE = 1
674 14:48:03.766431 ==============================================================
675 14:48:03.770071 Enter into Gating configuration >>>>
676 14:48:03.773581 Exit from Gating configuration <<<<
677 14:48:03.776498 Enter into DVFS_PRE_config >>>>>
678 14:48:03.790315 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 14:48:03.790485 Exit from DVFS_PRE_config <<<<<
680 14:48:03.793418 Enter into PICG configuration >>>>
681 14:48:03.796479 Exit from PICG configuration <<<<
682 14:48:03.800071 [RX_INPUT] configuration >>>>>
683 14:48:03.803363 [RX_INPUT] configuration <<<<<
684 14:48:03.809935 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 14:48:03.813768 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 14:48:03.820089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 14:48:03.827129 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 14:48:03.833423 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 14:48:03.840729 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 14:48:03.843825 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 14:48:03.847140 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 14:48:03.850184 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 14:48:03.857103 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 14:48:03.860256 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 14:48:03.863401 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 14:48:03.867309 ===================================
697 14:48:03.870581 LPDDR4 DRAM CONFIGURATION
698 14:48:03.873793 ===================================
699 14:48:03.873889 EX_ROW_EN[0] = 0x0
700 14:48:03.876787 EX_ROW_EN[1] = 0x0
701 14:48:03.876880 LP4Y_EN = 0x0
702 14:48:03.880741 WORK_FSP = 0x0
703 14:48:03.880829 WL = 0x2
704 14:48:03.883763 RL = 0x2
705 14:48:03.886855 BL = 0x2
706 14:48:03.886947 RPST = 0x0
707 14:48:03.890425 RD_PRE = 0x0
708 14:48:03.890511 WR_PRE = 0x1
709 14:48:03.893876 WR_PST = 0x0
710 14:48:03.893957 DBI_WR = 0x0
711 14:48:03.897221 DBI_RD = 0x0
712 14:48:03.897307 OTF = 0x1
713 14:48:03.900024 ===================================
714 14:48:03.903681 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 14:48:03.906931 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 14:48:03.913725 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 14:48:03.917073 ===================================
718 14:48:03.920245 LPDDR4 DRAM CONFIGURATION
719 14:48:03.923407 ===================================
720 14:48:03.923493 EX_ROW_EN[0] = 0x10
721 14:48:03.926785 EX_ROW_EN[1] = 0x0
722 14:48:03.926871 LP4Y_EN = 0x0
723 14:48:03.930321 WORK_FSP = 0x0
724 14:48:03.930405 WL = 0x2
725 14:48:03.934081 RL = 0x2
726 14:48:03.934177 BL = 0x2
727 14:48:03.936739 RPST = 0x0
728 14:48:03.936819 RD_PRE = 0x0
729 14:48:03.940732 WR_PRE = 0x1
730 14:48:03.940819 WR_PST = 0x0
731 14:48:03.943619 DBI_WR = 0x0
732 14:48:03.943713 DBI_RD = 0x0
733 14:48:03.947028 OTF = 0x1
734 14:48:03.950000 ===================================
735 14:48:03.957139 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 14:48:03.960277 nWR fixed to 40
737 14:48:03.963384 [ModeRegInit_LP4] CH0 RK0
738 14:48:03.963481 [ModeRegInit_LP4] CH0 RK1
739 14:48:03.967303 [ModeRegInit_LP4] CH1 RK0
740 14:48:03.970448 [ModeRegInit_LP4] CH1 RK1
741 14:48:03.970529 match AC timing 13
742 14:48:03.976819 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 14:48:03.980527 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 14:48:03.983854 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 14:48:03.990561 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 14:48:03.993799 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 14:48:03.993894 [EMI DOE] emi_dcm 0
748 14:48:04.000586 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 14:48:04.000682 ==
750 14:48:04.003712 Dram Type= 6, Freq= 0, CH_0, rank 0
751 14:48:04.006822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 14:48:04.006907 ==
753 14:48:04.013975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 14:48:04.017183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 14:48:04.027724 [CA 0] Center 36 (6~67) winsize 62
756 14:48:04.031079 [CA 1] Center 36 (6~67) winsize 62
757 14:48:04.034531 [CA 2] Center 34 (4~65) winsize 62
758 14:48:04.037872 [CA 3] Center 33 (3~64) winsize 62
759 14:48:04.040620 [CA 4] Center 33 (3~64) winsize 62
760 14:48:04.044537 [CA 5] Center 32 (2~62) winsize 61
761 14:48:04.044628
762 14:48:04.048044 [CmdBusTrainingLP45] Vref(ca) range 1: 34
763 14:48:04.048133
764 14:48:04.050911 [CATrainingPosCal] consider 1 rank data
765 14:48:04.054287 u2DelayCellTimex100 = 270/100 ps
766 14:48:04.057542 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
767 14:48:04.061294 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
768 14:48:04.067916 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
769 14:48:04.070982 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
770 14:48:04.074251 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
771 14:48:04.078118 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
772 14:48:04.078221
773 14:48:04.081189 CA PerBit enable=1, Macro0, CA PI delay=32
774 14:48:04.081275
775 14:48:04.084346 [CBTSetCACLKResult] CA Dly = 32
776 14:48:04.084434 CS Dly: 5 (0~36)
777 14:48:04.084502 ==
778 14:48:04.087596 Dram Type= 6, Freq= 0, CH_0, rank 1
779 14:48:04.094465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 14:48:04.094560 ==
781 14:48:04.097736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 14:48:04.104548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 14:48:04.114167 [CA 0] Center 36 (6~67) winsize 62
784 14:48:04.117148 [CA 1] Center 36 (6~67) winsize 62
785 14:48:04.120670 [CA 2] Center 34 (4~65) winsize 62
786 14:48:04.124106 [CA 3] Center 33 (3~64) winsize 62
787 14:48:04.127261 [CA 4] Center 33 (2~64) winsize 63
788 14:48:04.130388 [CA 5] Center 32 (2~63) winsize 62
789 14:48:04.130495
790 14:48:04.134378 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 14:48:04.134467
792 14:48:04.137100 [CATrainingPosCal] consider 2 rank data
793 14:48:04.140238 u2DelayCellTimex100 = 270/100 ps
794 14:48:04.143925 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
795 14:48:04.147081 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
796 14:48:04.153945 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
797 14:48:04.157211 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
798 14:48:04.160257 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
799 14:48:04.164012 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
800 14:48:04.164130
801 14:48:04.167027 CA PerBit enable=1, Macro0, CA PI delay=32
802 14:48:04.167114
803 14:48:04.170281 [CBTSetCACLKResult] CA Dly = 32
804 14:48:04.170369 CS Dly: 5 (0~37)
805 14:48:04.170437
806 14:48:04.173831 ----->DramcWriteLeveling(PI) begin...
807 14:48:04.178051 ==
808 14:48:04.178143 Dram Type= 6, Freq= 0, CH_0, rank 0
809 14:48:04.181216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 14:48:04.185458 ==
811 14:48:04.185600 Write leveling (Byte 0): 35 => 35
812 14:48:04.188665 Write leveling (Byte 1): 30 => 30
813 14:48:04.192750 DramcWriteLeveling(PI) end<-----
814 14:48:04.192852
815 14:48:04.192920 ==
816 14:48:04.196419 Dram Type= 6, Freq= 0, CH_0, rank 0
817 14:48:04.199613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 14:48:04.199708 ==
819 14:48:04.202814 [Gating] SW mode calibration
820 14:48:04.210485 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 14:48:04.216475 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 14:48:04.220270 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 14:48:04.223393 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
824 14:48:04.226524 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
825 14:48:04.233707 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 14:48:04.236791 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 14:48:04.239946 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 14:48:04.247182 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 14:48:04.250288 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 14:48:04.253768 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 14:48:04.260216 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 14:48:04.264001 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 14:48:04.267255 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 14:48:04.273476 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 14:48:04.276968 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 14:48:04.280634 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 14:48:04.287426 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 14:48:04.290265 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 14:48:04.293852 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 14:48:04.297265 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
841 14:48:04.303955 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 14:48:04.307325 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 14:48:04.310674 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 14:48:04.317486 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 14:48:04.320930 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 14:48:04.323984 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 14:48:04.330442 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 14:48:04.334217 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
849 14:48:04.337549 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
850 14:48:04.343926 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 14:48:04.347555 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 14:48:04.350780 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 14:48:04.357688 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 14:48:04.360728 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 14:48:04.363973 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
856 14:48:04.367736 0 10 8 | B1->B0 | 3232 2626 | 1 0 | (1 0) (1 0)
857 14:48:04.374089 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 14:48:04.377304 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 14:48:04.380516 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 14:48:04.387602 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 14:48:04.390829 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 14:48:04.394085 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 14:48:04.400614 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 14:48:04.404278 0 11 8 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (0 0)
865 14:48:04.407405 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 14:48:04.414268 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 14:48:04.417925 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 14:48:04.421027 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 14:48:04.427950 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 14:48:04.431284 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 14:48:04.434083 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
872 14:48:04.441143 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
873 14:48:04.444310 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 14:48:04.447552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 14:48:04.450884 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 14:48:04.457932 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 14:48:04.460722 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 14:48:04.464686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 14:48:04.471029 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 14:48:04.474195 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 14:48:04.477532 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 14:48:04.484225 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 14:48:04.487459 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 14:48:04.491361 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 14:48:04.497884 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 14:48:04.500969 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 14:48:04.504183 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
888 14:48:04.510824 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
889 14:48:04.510920 Total UI for P1: 0, mck2ui 16
890 14:48:04.517798 best dqsien dly found for B0: ( 0, 14, 4)
891 14:48:04.520811 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 14:48:04.524560 Total UI for P1: 0, mck2ui 16
893 14:48:04.527773 best dqsien dly found for B1: ( 0, 14, 8)
894 14:48:04.531543 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
895 14:48:04.535397 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
896 14:48:04.535498
897 14:48:04.538296 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
898 14:48:04.541662 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 14:48:04.545382 [Gating] SW calibration Done
900 14:48:04.545501 ==
901 14:48:04.548402 Dram Type= 6, Freq= 0, CH_0, rank 0
902 14:48:04.551787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 14:48:04.551910 ==
904 14:48:04.555259 RX Vref Scan: 0
905 14:48:04.555370
906 14:48:04.555490 RX Vref 0 -> 0, step: 1
907 14:48:04.555590
908 14:48:04.558264 RX Delay -130 -> 252, step: 16
909 14:48:04.561814 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
910 14:48:04.568290 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
911 14:48:04.571656 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
912 14:48:04.575128 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
913 14:48:04.578311 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
914 14:48:04.582222 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
915 14:48:04.588629 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
916 14:48:04.591713 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
917 14:48:04.595550 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
918 14:48:04.598755 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
919 14:48:04.601909 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
920 14:48:04.608205 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
921 14:48:04.611902 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
922 14:48:04.615168 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
923 14:48:04.618517 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
924 14:48:04.621663 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
925 14:48:04.621746 ==
926 14:48:04.624875 Dram Type= 6, Freq= 0, CH_0, rank 0
927 14:48:04.632215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 14:48:04.632336 ==
929 14:48:04.632443 DQS Delay:
930 14:48:04.635271 DQS0 = 0, DQS1 = 0
931 14:48:04.635347 DQM Delay:
932 14:48:04.638366 DQM0 = 91, DQM1 = 84
933 14:48:04.638449 DQ Delay:
934 14:48:04.642172 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
935 14:48:04.645140 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
936 14:48:04.648362 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
937 14:48:04.652195 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
938 14:48:04.652287
939 14:48:04.652391
940 14:48:04.652475 ==
941 14:48:04.655099 Dram Type= 6, Freq= 0, CH_0, rank 0
942 14:48:04.658581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
943 14:48:04.658671 ==
944 14:48:04.658760
945 14:48:04.658843
946 14:48:04.661782 TX Vref Scan disable
947 14:48:04.665441 == TX Byte 0 ==
948 14:48:04.668542 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
949 14:48:04.671701 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
950 14:48:04.675443 == TX Byte 1 ==
951 14:48:04.678535 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
952 14:48:04.681674 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
953 14:48:04.681765 ==
954 14:48:04.685446 Dram Type= 6, Freq= 0, CH_0, rank 0
955 14:48:04.688574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 14:48:04.688664 ==
957 14:48:04.703296 TX Vref=22, minBit 8, minWin=27, winSum=448
958 14:48:04.707202 TX Vref=24, minBit 8, minWin=27, winSum=450
959 14:48:04.710286 TX Vref=26, minBit 8, minWin=27, winSum=452
960 14:48:04.713554 TX Vref=28, minBit 4, minWin=28, winSum=456
961 14:48:04.716651 TX Vref=30, minBit 5, minWin=28, winSum=458
962 14:48:04.720491 TX Vref=32, minBit 2, minWin=28, winSum=455
963 14:48:04.726856 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
964 14:48:04.726952
965 14:48:04.730541 Final TX Range 1 Vref 30
966 14:48:04.730636
967 14:48:04.730742 ==
968 14:48:04.733526 Dram Type= 6, Freq= 0, CH_0, rank 0
969 14:48:04.736724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 14:48:04.736814 ==
971 14:48:04.736903
972 14:48:04.736985
973 14:48:04.740538 TX Vref Scan disable
974 14:48:04.743792 == TX Byte 0 ==
975 14:48:04.746920 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
976 14:48:04.750592 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
977 14:48:04.753883 == TX Byte 1 ==
978 14:48:04.757055 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
979 14:48:04.760679 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
980 14:48:04.760775
981 14:48:04.763764 [DATLAT]
982 14:48:04.763853 Freq=800, CH0 RK0
983 14:48:04.763942
984 14:48:04.767371 DATLAT Default: 0xa
985 14:48:04.767461 0, 0xFFFF, sum = 0
986 14:48:04.770540 1, 0xFFFF, sum = 0
987 14:48:04.770632 2, 0xFFFF, sum = 0
988 14:48:04.774177 3, 0xFFFF, sum = 0
989 14:48:04.774269 4, 0xFFFF, sum = 0
990 14:48:04.777403 5, 0xFFFF, sum = 0
991 14:48:04.777494 6, 0xFFFF, sum = 0
992 14:48:04.780350 7, 0xFFFF, sum = 0
993 14:48:04.780441 8, 0xFFFF, sum = 0
994 14:48:04.784068 9, 0x0, sum = 1
995 14:48:04.784151 10, 0x0, sum = 2
996 14:48:04.787306 11, 0x0, sum = 3
997 14:48:04.787388 12, 0x0, sum = 4
998 14:48:04.790553 best_step = 10
999 14:48:04.790633
1000 14:48:04.790739 ==
1001 14:48:04.793770 Dram Type= 6, Freq= 0, CH_0, rank 0
1002 14:48:04.797826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1003 14:48:04.797916 ==
1004 14:48:04.798004 RX Vref Scan: 1
1005 14:48:04.800748
1006 14:48:04.800827 Set Vref Range= 32 -> 127
1007 14:48:04.800904
1008 14:48:04.803858 RX Vref 32 -> 127, step: 1
1009 14:48:04.803942
1010 14:48:04.807744 RX Delay -79 -> 252, step: 8
1011 14:48:04.807863
1012 14:48:04.810764 Set Vref, RX VrefLevel [Byte0]: 32
1013 14:48:04.814049 [Byte1]: 32
1014 14:48:04.814140
1015 14:48:04.817478 Set Vref, RX VrefLevel [Byte0]: 33
1016 14:48:04.820677 [Byte1]: 33
1017 14:48:04.820766
1018 14:48:04.823967 Set Vref, RX VrefLevel [Byte0]: 34
1019 14:48:04.827220 [Byte1]: 34
1020 14:48:04.831369
1021 14:48:04.831458 Set Vref, RX VrefLevel [Byte0]: 35
1022 14:48:04.834541 [Byte1]: 35
1023 14:48:04.838998
1024 14:48:04.839088 Set Vref, RX VrefLevel [Byte0]: 36
1025 14:48:04.842074 [Byte1]: 36
1026 14:48:04.846299
1027 14:48:04.846397 Set Vref, RX VrefLevel [Byte0]: 37
1028 14:48:04.850204 [Byte1]: 37
1029 14:48:04.854506
1030 14:48:04.854598 Set Vref, RX VrefLevel [Byte0]: 38
1031 14:48:04.857756 [Byte1]: 38
1032 14:48:04.861568
1033 14:48:04.861657 Set Vref, RX VrefLevel [Byte0]: 39
1034 14:48:04.864796 [Byte1]: 39
1035 14:48:04.869211
1036 14:48:04.869299 Set Vref, RX VrefLevel [Byte0]: 40
1037 14:48:04.872442 [Byte1]: 40
1038 14:48:04.876812
1039 14:48:04.876902 Set Vref, RX VrefLevel [Byte0]: 41
1040 14:48:04.880268 [Byte1]: 41
1041 14:48:04.883709
1042 14:48:04.883797 Set Vref, RX VrefLevel [Byte0]: 42
1043 14:48:04.887346 [Byte1]: 42
1044 14:48:04.891570
1045 14:48:04.891660 Set Vref, RX VrefLevel [Byte0]: 43
1046 14:48:04.894690 [Byte1]: 43
1047 14:48:04.899063
1048 14:48:04.899153 Set Vref, RX VrefLevel [Byte0]: 44
1049 14:48:04.902294 [Byte1]: 44
1050 14:48:04.907050
1051 14:48:04.907139 Set Vref, RX VrefLevel [Byte0]: 45
1052 14:48:04.910284 [Byte1]: 45
1053 14:48:04.914554
1054 14:48:04.914646 Set Vref, RX VrefLevel [Byte0]: 46
1055 14:48:04.917415 [Byte1]: 46
1056 14:48:04.921825
1057 14:48:04.921917 Set Vref, RX VrefLevel [Byte0]: 47
1058 14:48:04.924991 [Byte1]: 47
1059 14:48:04.929470
1060 14:48:04.929562 Set Vref, RX VrefLevel [Byte0]: 48
1061 14:48:04.932678 [Byte1]: 48
1062 14:48:04.936796
1063 14:48:04.936890 Set Vref, RX VrefLevel [Byte0]: 49
1064 14:48:04.940754 [Byte1]: 49
1065 14:48:04.944538
1066 14:48:04.944635 Set Vref, RX VrefLevel [Byte0]: 50
1067 14:48:04.947930 [Byte1]: 50
1068 14:48:04.952168
1069 14:48:04.952259 Set Vref, RX VrefLevel [Byte0]: 51
1070 14:48:04.955158 [Byte1]: 51
1071 14:48:04.959284
1072 14:48:04.959376 Set Vref, RX VrefLevel [Byte0]: 52
1073 14:48:04.963017 [Byte1]: 52
1074 14:48:04.967219
1075 14:48:04.967313 Set Vref, RX VrefLevel [Byte0]: 53
1076 14:48:04.970345 [Byte1]: 53
1077 14:48:04.974747
1078 14:48:04.974845 Set Vref, RX VrefLevel [Byte0]: 54
1079 14:48:04.977874 [Byte1]: 54
1080 14:48:04.982624
1081 14:48:04.982721 Set Vref, RX VrefLevel [Byte0]: 55
1082 14:48:04.985192 [Byte1]: 55
1083 14:48:04.989861
1084 14:48:04.989960 Set Vref, RX VrefLevel [Byte0]: 56
1085 14:48:04.992791 [Byte1]: 56
1086 14:48:04.997129
1087 14:48:04.997221 Set Vref, RX VrefLevel [Byte0]: 57
1088 14:48:05.000610 [Byte1]: 57
1089 14:48:05.005023
1090 14:48:05.005113 Set Vref, RX VrefLevel [Byte0]: 58
1091 14:48:05.008200 [Byte1]: 58
1092 14:48:05.012017
1093 14:48:05.012103 Set Vref, RX VrefLevel [Byte0]: 59
1094 14:48:05.015843 [Byte1]: 59
1095 14:48:05.019610
1096 14:48:05.019720 Set Vref, RX VrefLevel [Byte0]: 60
1097 14:48:05.023386 [Byte1]: 60
1098 14:48:05.027669
1099 14:48:05.027790 Set Vref, RX VrefLevel [Byte0]: 61
1100 14:48:05.030884 [Byte1]: 61
1101 14:48:05.035305
1102 14:48:05.035395 Set Vref, RX VrefLevel [Byte0]: 62
1103 14:48:05.038535 [Byte1]: 62
1104 14:48:05.042492
1105 14:48:05.042602 Set Vref, RX VrefLevel [Byte0]: 63
1106 14:48:05.045500 [Byte1]: 63
1107 14:48:05.050418
1108 14:48:05.050552 Set Vref, RX VrefLevel [Byte0]: 64
1109 14:48:05.053488 [Byte1]: 64
1110 14:48:05.057806
1111 14:48:05.057921 Set Vref, RX VrefLevel [Byte0]: 65
1112 14:48:05.060845 [Byte1]: 65
1113 14:48:05.065249
1114 14:48:05.065358 Set Vref, RX VrefLevel [Byte0]: 66
1115 14:48:05.068507 [Byte1]: 66
1116 14:48:05.072693
1117 14:48:05.072814 Set Vref, RX VrefLevel [Byte0]: 67
1118 14:48:05.076119 [Byte1]: 67
1119 14:48:05.080197
1120 14:48:05.080300 Set Vref, RX VrefLevel [Byte0]: 68
1121 14:48:05.083604 [Byte1]: 68
1122 14:48:05.088111
1123 14:48:05.088221 Set Vref, RX VrefLevel [Byte0]: 69
1124 14:48:05.091293 [Byte1]: 69
1125 14:48:05.095592
1126 14:48:05.095729 Set Vref, RX VrefLevel [Byte0]: 70
1127 14:48:05.098591 [Byte1]: 70
1128 14:48:05.102744
1129 14:48:05.102875 Set Vref, RX VrefLevel [Byte0]: 71
1130 14:48:05.106323 [Byte1]: 71
1131 14:48:05.110344
1132 14:48:05.110472 Set Vref, RX VrefLevel [Byte0]: 72
1133 14:48:05.113455 [Byte1]: 72
1134 14:48:05.117875
1135 14:48:05.118012 Set Vref, RX VrefLevel [Byte0]: 73
1136 14:48:05.121678 [Byte1]: 73
1137 14:48:05.125506
1138 14:48:05.125609 Set Vref, RX VrefLevel [Byte0]: 74
1139 14:48:05.128731 [Byte1]: 74
1140 14:48:05.132956
1141 14:48:05.133070 Set Vref, RX VrefLevel [Byte0]: 75
1142 14:48:05.136719 [Byte1]: 75
1143 14:48:05.140656
1144 14:48:05.140761 Set Vref, RX VrefLevel [Byte0]: 76
1145 14:48:05.143842 [Byte1]: 76
1146 14:48:05.148291
1147 14:48:05.148430 Set Vref, RX VrefLevel [Byte0]: 77
1148 14:48:05.151562 [Byte1]: 77
1149 14:48:05.155876
1150 14:48:05.155982 Set Vref, RX VrefLevel [Byte0]: 78
1151 14:48:05.159090 [Byte1]: 78
1152 14:48:05.163175
1153 14:48:05.163292 Final RX Vref Byte 0 = 53 to rank0
1154 14:48:05.167006 Final RX Vref Byte 1 = 61 to rank0
1155 14:48:05.170146 Final RX Vref Byte 0 = 53 to rank1
1156 14:48:05.173305 Final RX Vref Byte 1 = 61 to rank1==
1157 14:48:05.176365 Dram Type= 6, Freq= 0, CH_0, rank 0
1158 14:48:05.183530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 14:48:05.183683 ==
1160 14:48:05.183782 DQS Delay:
1161 14:48:05.183863 DQS0 = 0, DQS1 = 0
1162 14:48:05.186565 DQM Delay:
1163 14:48:05.186673 DQM0 = 91, DQM1 = 86
1164 14:48:05.189749 DQ Delay:
1165 14:48:05.193253 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1166 14:48:05.196363 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1167 14:48:05.199974 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1168 14:48:05.202990 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1169 14:48:05.203086
1170 14:48:05.203154
1171 14:48:05.209745 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1172 14:48:05.213268 CH0 RK0: MR19=606, MR18=4F45
1173 14:48:05.219746 CH0_RK0: MR19=0x606, MR18=0x4F45, DQSOSC=390, MR23=63, INC=97, DEC=64
1174 14:48:05.219856
1175 14:48:05.223080 ----->DramcWriteLeveling(PI) begin...
1176 14:48:05.223197 ==
1177 14:48:05.226762 Dram Type= 6, Freq= 0, CH_0, rank 1
1178 14:48:05.230017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 14:48:05.230136 ==
1180 14:48:05.233229 Write leveling (Byte 0): 33 => 33
1181 14:48:05.236238 Write leveling (Byte 1): 29 => 29
1182 14:48:05.239960 DramcWriteLeveling(PI) end<-----
1183 14:48:05.240100
1184 14:48:05.240198 ==
1185 14:48:05.243313 Dram Type= 6, Freq= 0, CH_0, rank 1
1186 14:48:05.246370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 14:48:05.246485 ==
1188 14:48:05.290481 [Gating] SW mode calibration
1189 14:48:05.291193 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1190 14:48:05.291517 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1191 14:48:05.291640 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1192 14:48:05.291754 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1193 14:48:05.291850 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1194 14:48:05.291956 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 14:48:05.292064 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 14:48:05.292367 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 14:48:05.334661 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 14:48:05.334851 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 14:48:05.335164 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 14:48:05.335269 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 14:48:05.335366 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 14:48:05.335942 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 14:48:05.336048 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 14:48:05.336335 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 14:48:05.336757 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 14:48:05.337061 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 14:48:05.339802 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 14:48:05.339913 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1209 14:48:05.346473 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1210 14:48:05.349606 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 14:48:05.353588 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 14:48:05.360066 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 14:48:05.363299 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 14:48:05.366424 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 14:48:05.373108 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 14:48:05.376752 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 14:48:05.379939 0 9 8 | B1->B0 | 2c2c 2e2e | 0 0 | (0 0) (0 0)
1218 14:48:05.386202 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 14:48:05.389973 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 14:48:05.393003 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 14:48:05.399809 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 14:48:05.403238 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 14:48:05.407016 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 14:48:05.413246 0 10 4 | B1->B0 | 3333 3333 | 1 1 | (1 1) (0 0)
1225 14:48:05.416520 0 10 8 | B1->B0 | 2626 2424 | 0 0 | (1 0) (0 0)
1226 14:48:05.420363 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 14:48:05.424496 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 14:48:05.428096 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 14:48:05.435323 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 14:48:05.438086 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 14:48:05.441926 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 14:48:05.448702 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1233 14:48:05.452160 0 11 8 | B1->B0 | 3f3f 4141 | 0 0 | (1 1) (0 0)
1234 14:48:05.455804 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 14:48:05.458889 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 14:48:05.465271 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 14:48:05.469178 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 14:48:05.472407 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 14:48:05.478704 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 14:48:05.482366 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 14:48:05.485461 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1242 14:48:05.492608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 14:48:05.495665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 14:48:05.499351 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 14:48:05.505466 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 14:48:05.509352 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 14:48:05.512496 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 14:48:05.515719 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 14:48:05.522189 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 14:48:05.525617 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 14:48:05.529215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 14:48:05.535769 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 14:48:05.538985 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 14:48:05.542798 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 14:48:05.549220 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 14:48:05.552416 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 14:48:05.556235 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1258 14:48:05.559018 Total UI for P1: 0, mck2ui 16
1259 14:48:05.562467 best dqsien dly found for B0: ( 0, 14, 6)
1260 14:48:05.569329 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 14:48:05.569491 Total UI for P1: 0, mck2ui 16
1262 14:48:05.572325 best dqsien dly found for B1: ( 0, 14, 8)
1263 14:48:05.575821 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1264 14:48:05.582923 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1265 14:48:05.583083
1266 14:48:05.586006 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1267 14:48:05.589214 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1268 14:48:05.593530 [Gating] SW calibration Done
1269 14:48:05.593657 ==
1270 14:48:05.595828 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 14:48:05.599719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 14:48:05.599874 ==
1273 14:48:05.599994 RX Vref Scan: 0
1274 14:48:05.600081
1275 14:48:05.602990 RX Vref 0 -> 0, step: 1
1276 14:48:05.603107
1277 14:48:05.606154 RX Delay -130 -> 252, step: 16
1278 14:48:05.609499 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1279 14:48:05.612902 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1280 14:48:05.620022 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1281 14:48:05.622892 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1282 14:48:05.626290 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1283 14:48:05.629245 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1284 14:48:05.633180 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1285 14:48:05.639411 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1286 14:48:05.642579 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1287 14:48:05.645921 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1288 14:48:05.649548 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1289 14:48:05.652701 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1290 14:48:05.659042 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1291 14:48:05.662850 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1292 14:48:05.666344 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1293 14:48:05.669486 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1294 14:48:05.669608 ==
1295 14:48:05.672485 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 14:48:05.679522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 14:48:05.679668 ==
1298 14:48:05.679767 DQS Delay:
1299 14:48:05.679862 DQS0 = 0, DQS1 = 0
1300 14:48:05.682537 DQM Delay:
1301 14:48:05.682650 DQM0 = 91, DQM1 = 80
1302 14:48:05.686366 DQ Delay:
1303 14:48:05.689773 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1304 14:48:05.689895 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1305 14:48:05.692613 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
1306 14:48:05.699468 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =77
1307 14:48:05.699603
1308 14:48:05.699701
1309 14:48:05.699795 ==
1310 14:48:05.702466 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 14:48:05.705791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 14:48:05.705917 ==
1313 14:48:05.706014
1314 14:48:05.706106
1315 14:48:05.709584 TX Vref Scan disable
1316 14:48:05.709703 == TX Byte 0 ==
1317 14:48:05.715969 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1318 14:48:05.719375 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1319 14:48:05.719502 == TX Byte 1 ==
1320 14:48:05.725754 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1321 14:48:05.729202 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1322 14:48:05.729328 ==
1323 14:48:05.732285 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 14:48:05.735948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 14:48:05.736065 ==
1326 14:48:05.750324 TX Vref=22, minBit 8, minWin=27, winSum=447
1327 14:48:05.753447 TX Vref=24, minBit 8, minWin=27, winSum=447
1328 14:48:05.757187 TX Vref=26, minBit 1, minWin=28, winSum=457
1329 14:48:05.760318 TX Vref=28, minBit 1, minWin=28, winSum=458
1330 14:48:05.763464 TX Vref=30, minBit 4, minWin=28, winSum=456
1331 14:48:05.766879 TX Vref=32, minBit 1, minWin=28, winSum=453
1332 14:48:05.773688 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 28
1333 14:48:05.773871
1334 14:48:05.776766 Final TX Range 1 Vref 28
1335 14:48:05.776884
1336 14:48:05.776981 ==
1337 14:48:05.780441 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 14:48:05.783357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 14:48:05.783496 ==
1340 14:48:05.783599
1341 14:48:05.787173
1342 14:48:05.787317 TX Vref Scan disable
1343 14:48:05.790292 == TX Byte 0 ==
1344 14:48:05.793366 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1345 14:48:05.796909 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1346 14:48:05.800545 == TX Byte 1 ==
1347 14:48:05.803685 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1348 14:48:05.806889 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1349 14:48:05.810417
1350 14:48:05.810541 [DATLAT]
1351 14:48:05.810637 Freq=800, CH0 RK1
1352 14:48:05.810731
1353 14:48:05.813999 DATLAT Default: 0xa
1354 14:48:05.814125 0, 0xFFFF, sum = 0
1355 14:48:05.817164 1, 0xFFFF, sum = 0
1356 14:48:05.817300 2, 0xFFFF, sum = 0
1357 14:48:05.820369 3, 0xFFFF, sum = 0
1358 14:48:05.820505 4, 0xFFFF, sum = 0
1359 14:48:05.823439 5, 0xFFFF, sum = 0
1360 14:48:05.823561 6, 0xFFFF, sum = 0
1361 14:48:05.827199 7, 0xFFFF, sum = 0
1362 14:48:05.827340 8, 0xFFFF, sum = 0
1363 14:48:05.830297 9, 0x0, sum = 1
1364 14:48:05.830416 10, 0x0, sum = 2
1365 14:48:05.833791 11, 0x0, sum = 3
1366 14:48:05.833913 12, 0x0, sum = 4
1367 14:48:05.837370 best_step = 10
1368 14:48:05.837493
1369 14:48:05.837588 ==
1370 14:48:05.840441 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 14:48:05.843720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 14:48:05.843836 ==
1373 14:48:05.847196 RX Vref Scan: 0
1374 14:48:05.847317
1375 14:48:05.847413 RX Vref 0 -> 0, step: 1
1376 14:48:05.847506
1377 14:48:05.850516 RX Delay -95 -> 252, step: 8
1378 14:48:05.856900 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1379 14:48:05.860458 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1380 14:48:05.864005 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1381 14:48:05.867088 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1382 14:48:05.870241 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1383 14:48:05.877569 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1384 14:48:05.880478 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1385 14:48:05.883703 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1386 14:48:05.887420 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1387 14:48:05.890497 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1388 14:48:05.893789 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1389 14:48:05.900708 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1390 14:48:05.903721 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1391 14:48:05.907330 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1392 14:48:05.910508 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1393 14:48:05.917476 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1394 14:48:05.917640 ==
1395 14:48:05.920845 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 14:48:05.923829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 14:48:05.923964 ==
1398 14:48:05.924063 DQS Delay:
1399 14:48:05.926919 DQS0 = 0, DQS1 = 0
1400 14:48:05.927039 DQM Delay:
1401 14:48:05.930139 DQM0 = 92, DQM1 = 83
1402 14:48:05.930273 DQ Delay:
1403 14:48:05.934062 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1404 14:48:05.937225 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1405 14:48:05.940456 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1406 14:48:05.943738 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1407 14:48:05.943862
1408 14:48:05.943960
1409 14:48:05.950148 [DQSOSCAuto] RK1, (LSB)MR18= 0x4717, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1410 14:48:05.953403 CH0 RK1: MR19=606, MR18=4717
1411 14:48:05.960211 CH0_RK1: MR19=0x606, MR18=0x4717, DQSOSC=392, MR23=63, INC=96, DEC=64
1412 14:48:05.963755 [RxdqsGatingPostProcess] freq 800
1413 14:48:05.970719 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1414 14:48:05.973680 Pre-setting of DQS Precalculation
1415 14:48:05.977363 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1416 14:48:05.977523 ==
1417 14:48:05.980356 Dram Type= 6, Freq= 0, CH_1, rank 0
1418 14:48:05.983850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 14:48:05.984005 ==
1420 14:48:05.990712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1421 14:48:05.997000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1422 14:48:06.005334 [CA 0] Center 36 (6~67) winsize 62
1423 14:48:06.008916 [CA 1] Center 36 (6~67) winsize 62
1424 14:48:06.011712 [CA 2] Center 35 (4~66) winsize 63
1425 14:48:06.015057 [CA 3] Center 35 (5~65) winsize 61
1426 14:48:06.018543 [CA 4] Center 34 (4~65) winsize 62
1427 14:48:06.021852 [CA 5] Center 34 (4~65) winsize 62
1428 14:48:06.021982
1429 14:48:06.025059 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1430 14:48:06.025176
1431 14:48:06.028235 [CATrainingPosCal] consider 1 rank data
1432 14:48:06.032055 u2DelayCellTimex100 = 270/100 ps
1433 14:48:06.035286 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 14:48:06.038364 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1435 14:48:06.045459 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1436 14:48:06.048560 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1437 14:48:06.051849 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 14:48:06.054941 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1439 14:48:06.055042
1440 14:48:06.058743 CA PerBit enable=1, Macro0, CA PI delay=34
1441 14:48:06.058838
1442 14:48:06.062044 [CBTSetCACLKResult] CA Dly = 34
1443 14:48:06.062159 CS Dly: 6 (0~37)
1444 14:48:06.062241 ==
1445 14:48:06.065142 Dram Type= 6, Freq= 0, CH_1, rank 1
1446 14:48:06.071771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 14:48:06.071912 ==
1448 14:48:06.074889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 14:48:06.081995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 14:48:06.092352 [CA 0] Center 36 (6~67) winsize 62
1451 14:48:06.095930 [CA 1] Center 37 (6~68) winsize 63
1452 14:48:06.099555 [CA 2] Center 35 (4~66) winsize 63
1453 14:48:06.103338 [CA 3] Center 34 (4~65) winsize 62
1454 14:48:06.107179 [CA 4] Center 35 (5~66) winsize 62
1455 14:48:06.107354 [CA 5] Center 34 (4~65) winsize 62
1456 14:48:06.107460
1457 14:48:06.110811 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 14:48:06.114560
1459 14:48:06.114729 [CATrainingPosCal] consider 2 rank data
1460 14:48:06.118359 u2DelayCellTimex100 = 270/100 ps
1461 14:48:06.122002 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 14:48:06.124950 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 14:48:06.128146 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1464 14:48:06.134884 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1465 14:48:06.138405 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1466 14:48:06.141515 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 14:48:06.141620
1468 14:48:06.144727 CA PerBit enable=1, Macro0, CA PI delay=34
1469 14:48:06.144852
1470 14:48:06.148285 [CBTSetCACLKResult] CA Dly = 34
1471 14:48:06.148439 CS Dly: 7 (0~39)
1472 14:48:06.148527
1473 14:48:06.151454 ----->DramcWriteLeveling(PI) begin...
1474 14:48:06.151573 ==
1475 14:48:06.154831 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 14:48:06.161866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 14:48:06.162115 ==
1478 14:48:06.165243 Write leveling (Byte 0): 28 => 28
1479 14:48:06.168321 Write leveling (Byte 1): 28 => 28
1480 14:48:06.168428 DramcWriteLeveling(PI) end<-----
1481 14:48:06.171388
1482 14:48:06.171502 ==
1483 14:48:06.175281 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 14:48:06.178540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 14:48:06.178668 ==
1486 14:48:06.181632 [Gating] SW mode calibration
1487 14:48:06.188128 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1488 14:48:06.191745 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1489 14:48:06.198919 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1490 14:48:06.201918 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1491 14:48:06.205161 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 14:48:06.211581 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 14:48:06.215196 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 14:48:06.218363 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 14:48:06.225049 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 14:48:06.228650 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 14:48:06.231840 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 14:48:06.234983 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 14:48:06.241930 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 14:48:06.245465 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 14:48:06.248841 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 14:48:06.255271 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 14:48:06.258623 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 14:48:06.261875 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 14:48:06.268706 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1506 14:48:06.271975 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1507 14:48:06.275424 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 14:48:06.281784 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 14:48:06.284971 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 14:48:06.288813 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 14:48:06.295308 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 14:48:06.298747 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 14:48:06.301885 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 14:48:06.308265 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
1515 14:48:06.311996 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1516 14:48:06.315187 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 14:48:06.322034 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 14:48:06.325201 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 14:48:06.328376 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 14:48:06.332303 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 14:48:06.338581 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1522 14:48:06.341732 0 10 4 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
1523 14:48:06.345516 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 14:48:06.351936 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 14:48:06.355069 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 14:48:06.358912 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 14:48:06.365041 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 14:48:06.368884 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 14:48:06.372112 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 14:48:06.378662 0 11 4 | B1->B0 | 2c2c 3636 | 0 0 | (0 0) (0 0)
1531 14:48:06.382130 0 11 8 | B1->B0 | 3f3f 4646 | 1 0 | (1 1) (0 0)
1532 14:48:06.385141 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 14:48:06.391731 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 14:48:06.395097 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 14:48:06.398848 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 14:48:06.405456 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 14:48:06.408883 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 14:48:06.412058 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1539 14:48:06.418382 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 14:48:06.421802 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 14:48:06.425420 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 14:48:06.428395 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 14:48:06.435331 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 14:48:06.439064 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 14:48:06.442269 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 14:48:06.449039 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 14:48:06.452193 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 14:48:06.455313 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 14:48:06.461827 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 14:48:06.465817 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 14:48:06.468852 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 14:48:06.475581 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 14:48:06.478617 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 14:48:06.481834 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1555 14:48:06.488835 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 14:48:06.488930 Total UI for P1: 0, mck2ui 16
1557 14:48:06.492013 best dqsien dly found for B0: ( 0, 14, 6)
1558 14:48:06.495177 Total UI for P1: 0, mck2ui 16
1559 14:48:06.498919 best dqsien dly found for B1: ( 0, 14, 4)
1560 14:48:06.505296 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1561 14:48:06.508689 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1562 14:48:06.508792
1563 14:48:06.511796 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1564 14:48:06.515085 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1565 14:48:06.518912 [Gating] SW calibration Done
1566 14:48:06.519007 ==
1567 14:48:06.522791 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 14:48:06.525184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 14:48:06.525284 ==
1570 14:48:06.525351 RX Vref Scan: 0
1571 14:48:06.525416
1572 14:48:06.529069 RX Vref 0 -> 0, step: 1
1573 14:48:06.529171
1574 14:48:06.532104 RX Delay -130 -> 252, step: 16
1575 14:48:06.535381 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1576 14:48:06.538561 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1577 14:48:06.545255 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1578 14:48:06.548569 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1579 14:48:06.552385 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1580 14:48:06.555297 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1581 14:48:06.558970 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1582 14:48:06.565446 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1583 14:48:06.568720 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1584 14:48:06.572421 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1585 14:48:06.575659 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1586 14:48:06.578761 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1587 14:48:06.585541 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1588 14:48:06.588823 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1589 14:48:06.592678 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1590 14:48:06.595846 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1591 14:48:06.595925 ==
1592 14:48:06.598976 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 14:48:06.602212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 14:48:06.605906 ==
1595 14:48:06.605984 DQS Delay:
1596 14:48:06.606048 DQS0 = 0, DQS1 = 0
1597 14:48:06.609066 DQM Delay:
1598 14:48:06.609144 DQM0 = 92, DQM1 = 87
1599 14:48:06.612259 DQ Delay:
1600 14:48:06.612367 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1601 14:48:06.615472 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1602 14:48:06.618621 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1603 14:48:06.622415 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1604 14:48:06.625587
1605 14:48:06.625702
1606 14:48:06.625799 ==
1607 14:48:06.628765 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 14:48:06.632496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 14:48:06.632587 ==
1610 14:48:06.632654
1611 14:48:06.632715
1612 14:48:06.635393 TX Vref Scan disable
1613 14:48:06.635481 == TX Byte 0 ==
1614 14:48:06.642471 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1615 14:48:06.645952 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1616 14:48:06.646052 == TX Byte 1 ==
1617 14:48:06.652053 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1618 14:48:06.655430 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1619 14:48:06.655533 ==
1620 14:48:06.659094 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 14:48:06.661898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 14:48:06.662011 ==
1623 14:48:06.675561 TX Vref=22, minBit 0, minWin=27, winSum=441
1624 14:48:06.679189 TX Vref=24, minBit 2, minWin=27, winSum=446
1625 14:48:06.682254 TX Vref=26, minBit 0, minWin=27, winSum=444
1626 14:48:06.685389 TX Vref=28, minBit 2, minWin=27, winSum=449
1627 14:48:06.688715 TX Vref=30, minBit 1, minWin=27, winSum=451
1628 14:48:06.692726 TX Vref=32, minBit 1, minWin=27, winSum=449
1629 14:48:06.699171 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1630 14:48:06.699282
1631 14:48:06.702465 Final TX Range 1 Vref 30
1632 14:48:06.702553
1633 14:48:06.702656 ==
1634 14:48:06.705539 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 14:48:06.708814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 14:48:06.708901 ==
1637 14:48:06.708990
1638 14:48:06.709075
1639 14:48:06.712494 TX Vref Scan disable
1640 14:48:06.715740 == TX Byte 0 ==
1641 14:48:06.718848 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1642 14:48:06.722125 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1643 14:48:06.725995 == TX Byte 1 ==
1644 14:48:06.729261 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1645 14:48:06.732402 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1646 14:48:06.732493
1647 14:48:06.735546 [DATLAT]
1648 14:48:06.735629 Freq=800, CH1 RK0
1649 14:48:06.735696
1650 14:48:06.738757 DATLAT Default: 0xa
1651 14:48:06.738836 0, 0xFFFF, sum = 0
1652 14:48:06.742592 1, 0xFFFF, sum = 0
1653 14:48:06.742677 2, 0xFFFF, sum = 0
1654 14:48:06.745525 3, 0xFFFF, sum = 0
1655 14:48:06.745614 4, 0xFFFF, sum = 0
1656 14:48:06.749272 5, 0xFFFF, sum = 0
1657 14:48:06.749379 6, 0xFFFF, sum = 0
1658 14:48:06.752571 7, 0xFFFF, sum = 0
1659 14:48:06.752659 8, 0xFFFF, sum = 0
1660 14:48:06.755841 9, 0x0, sum = 1
1661 14:48:06.755928 10, 0x0, sum = 2
1662 14:48:06.759078 11, 0x0, sum = 3
1663 14:48:06.759164 12, 0x0, sum = 4
1664 14:48:06.762285 best_step = 10
1665 14:48:06.762370
1666 14:48:06.762441 ==
1667 14:48:06.765937 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 14:48:06.769663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 14:48:06.769753 ==
1670 14:48:06.772776 RX Vref Scan: 1
1671 14:48:06.772881
1672 14:48:06.772949 Set Vref Range= 32 -> 127
1673 14:48:06.773011
1674 14:48:06.775864 RX Vref 32 -> 127, step: 1
1675 14:48:06.775952
1676 14:48:06.779173 RX Delay -79 -> 252, step: 8
1677 14:48:06.779259
1678 14:48:06.782570 Set Vref, RX VrefLevel [Byte0]: 32
1679 14:48:06.786076 [Byte1]: 32
1680 14:48:06.786160
1681 14:48:06.789034 Set Vref, RX VrefLevel [Byte0]: 33
1682 14:48:06.792706 [Byte1]: 33
1683 14:48:06.796031
1684 14:48:06.796114 Set Vref, RX VrefLevel [Byte0]: 34
1685 14:48:06.798888 [Byte1]: 34
1686 14:48:06.803334
1687 14:48:06.803428 Set Vref, RX VrefLevel [Byte0]: 35
1688 14:48:06.806551 [Byte1]: 35
1689 14:48:06.810897
1690 14:48:06.810991 Set Vref, RX VrefLevel [Byte0]: 36
1691 14:48:06.813920 [Byte1]: 36
1692 14:48:06.818627
1693 14:48:06.818725 Set Vref, RX VrefLevel [Byte0]: 37
1694 14:48:06.821979 [Byte1]: 37
1695 14:48:06.825907
1696 14:48:06.826004 Set Vref, RX VrefLevel [Byte0]: 38
1697 14:48:06.829233 [Byte1]: 38
1698 14:48:06.833737
1699 14:48:06.833818 Set Vref, RX VrefLevel [Byte0]: 39
1700 14:48:06.836873 [Byte1]: 39
1701 14:48:06.840668
1702 14:48:06.840749 Set Vref, RX VrefLevel [Byte0]: 40
1703 14:48:06.844606 [Byte1]: 40
1704 14:48:06.848308
1705 14:48:06.848416 Set Vref, RX VrefLevel [Byte0]: 41
1706 14:48:06.851877 [Byte1]: 41
1707 14:48:06.856317
1708 14:48:06.856442 Set Vref, RX VrefLevel [Byte0]: 42
1709 14:48:06.859479 [Byte1]: 42
1710 14:48:06.863341
1711 14:48:06.863436 Set Vref, RX VrefLevel [Byte0]: 43
1712 14:48:06.867178 [Byte1]: 43
1713 14:48:06.870843
1714 14:48:06.870933 Set Vref, RX VrefLevel [Byte0]: 44
1715 14:48:06.874418 [Byte1]: 44
1716 14:48:06.878964
1717 14:48:06.879059 Set Vref, RX VrefLevel [Byte0]: 45
1718 14:48:06.882109 [Byte1]: 45
1719 14:48:06.886367
1720 14:48:06.886459 Set Vref, RX VrefLevel [Byte0]: 46
1721 14:48:06.889734 [Byte1]: 46
1722 14:48:06.893937
1723 14:48:06.894029 Set Vref, RX VrefLevel [Byte0]: 47
1724 14:48:06.897184 [Byte1]: 47
1725 14:48:06.901641
1726 14:48:06.901726 Set Vref, RX VrefLevel [Byte0]: 48
1727 14:48:06.904592 [Byte1]: 48
1728 14:48:06.908979
1729 14:48:06.909064 Set Vref, RX VrefLevel [Byte0]: 49
1730 14:48:06.912008 [Byte1]: 49
1731 14:48:06.916469
1732 14:48:06.916552 Set Vref, RX VrefLevel [Byte0]: 50
1733 14:48:06.920023 [Byte1]: 50
1734 14:48:06.923961
1735 14:48:06.924084 Set Vref, RX VrefLevel [Byte0]: 51
1736 14:48:06.927091 [Byte1]: 51
1737 14:48:06.931539
1738 14:48:06.931637 Set Vref, RX VrefLevel [Byte0]: 52
1739 14:48:06.934803 [Byte1]: 52
1740 14:48:06.939162
1741 14:48:06.939316 Set Vref, RX VrefLevel [Byte0]: 53
1742 14:48:06.942403 [Byte1]: 53
1743 14:48:06.946590
1744 14:48:06.946682 Set Vref, RX VrefLevel [Byte0]: 54
1745 14:48:06.949984 [Byte1]: 54
1746 14:48:06.954175
1747 14:48:06.954294 Set Vref, RX VrefLevel [Byte0]: 55
1748 14:48:06.957456 [Byte1]: 55
1749 14:48:06.961641
1750 14:48:06.961731 Set Vref, RX VrefLevel [Byte0]: 56
1751 14:48:06.964833 [Byte1]: 56
1752 14:48:06.969285
1753 14:48:06.969376 Set Vref, RX VrefLevel [Byte0]: 57
1754 14:48:06.972416 [Byte1]: 57
1755 14:48:06.976768
1756 14:48:06.976896 Set Vref, RX VrefLevel [Byte0]: 58
1757 14:48:06.980660 [Byte1]: 58
1758 14:48:06.984221
1759 14:48:06.984349 Set Vref, RX VrefLevel [Byte0]: 59
1760 14:48:06.987348 [Byte1]: 59
1761 14:48:06.991993
1762 14:48:06.992077 Set Vref, RX VrefLevel [Byte0]: 60
1763 14:48:06.995168 [Byte1]: 60
1764 14:48:06.999527
1765 14:48:06.999613 Set Vref, RX VrefLevel [Byte0]: 61
1766 14:48:07.002644 [Byte1]: 61
1767 14:48:07.006974
1768 14:48:07.007063 Set Vref, RX VrefLevel [Byte0]: 62
1769 14:48:07.010121 [Byte1]: 62
1770 14:48:07.014747
1771 14:48:07.014837 Set Vref, RX VrefLevel [Byte0]: 63
1772 14:48:07.017812 [Byte1]: 63
1773 14:48:07.022123
1774 14:48:07.022214 Set Vref, RX VrefLevel [Byte0]: 64
1775 14:48:07.025215 [Byte1]: 64
1776 14:48:07.029721
1777 14:48:07.029803 Set Vref, RX VrefLevel [Byte0]: 65
1778 14:48:07.032756 [Byte1]: 65
1779 14:48:07.037084
1780 14:48:07.037174 Set Vref, RX VrefLevel [Byte0]: 66
1781 14:48:07.040944 [Byte1]: 66
1782 14:48:07.045103
1783 14:48:07.045221 Set Vref, RX VrefLevel [Byte0]: 67
1784 14:48:07.048064 [Byte1]: 67
1785 14:48:07.052288
1786 14:48:07.052401 Set Vref, RX VrefLevel [Byte0]: 68
1787 14:48:07.055560 [Byte1]: 68
1788 14:48:07.059874
1789 14:48:07.059963 Set Vref, RX VrefLevel [Byte0]: 69
1790 14:48:07.063387 [Byte1]: 69
1791 14:48:07.067310
1792 14:48:07.067404 Set Vref, RX VrefLevel [Byte0]: 70
1793 14:48:07.070597 [Byte1]: 70
1794 14:48:07.075112
1795 14:48:07.075235 Set Vref, RX VrefLevel [Byte0]: 71
1796 14:48:07.078328 [Byte1]: 71
1797 14:48:07.082617
1798 14:48:07.082715 Set Vref, RX VrefLevel [Byte0]: 72
1799 14:48:07.085641 [Byte1]: 72
1800 14:48:07.090259
1801 14:48:07.090384 Final RX Vref Byte 0 = 54 to rank0
1802 14:48:07.093508 Final RX Vref Byte 1 = 54 to rank0
1803 14:48:07.096765 Final RX Vref Byte 0 = 54 to rank1
1804 14:48:07.100276 Final RX Vref Byte 1 = 54 to rank1==
1805 14:48:07.103704 Dram Type= 6, Freq= 0, CH_1, rank 0
1806 14:48:07.106847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 14:48:07.109984 ==
1808 14:48:07.110068 DQS Delay:
1809 14:48:07.110165 DQS0 = 0, DQS1 = 0
1810 14:48:07.113757 DQM Delay:
1811 14:48:07.113838 DQM0 = 94, DQM1 = 89
1812 14:48:07.117060 DQ Delay:
1813 14:48:07.117147 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1814 14:48:07.120465 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =92
1815 14:48:07.123461 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1816 14:48:07.127133 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1817 14:48:07.130718
1818 14:48:07.130805
1819 14:48:07.136689 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1820 14:48:07.140162 CH1 RK0: MR19=606, MR18=2E4B
1821 14:48:07.146956 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1822 14:48:07.147045
1823 14:48:07.150135 ----->DramcWriteLeveling(PI) begin...
1824 14:48:07.150239 ==
1825 14:48:07.153576 Dram Type= 6, Freq= 0, CH_1, rank 1
1826 14:48:07.156990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 14:48:07.157081 ==
1828 14:48:07.160511 Write leveling (Byte 0): 25 => 25
1829 14:48:07.163459 Write leveling (Byte 1): 28 => 28
1830 14:48:07.166872 DramcWriteLeveling(PI) end<-----
1831 14:48:07.166961
1832 14:48:07.167050 ==
1833 14:48:07.170456 Dram Type= 6, Freq= 0, CH_1, rank 1
1834 14:48:07.173648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 14:48:07.173735 ==
1836 14:48:07.176746 [Gating] SW mode calibration
1837 14:48:07.183849 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1838 14:48:07.190428 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1839 14:48:07.193635 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1840 14:48:07.197699 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 14:48:07.203500 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1842 14:48:07.207071 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 14:48:07.210894 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 14:48:07.216945 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 14:48:07.220874 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 14:48:07.224077 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 14:48:07.227502 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 14:48:07.233653 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 14:48:07.237466 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 14:48:07.240591 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 14:48:07.247175 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 14:48:07.250333 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 14:48:07.254182 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 14:48:07.260475 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 14:48:07.264291 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1856 14:48:07.267559 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1857 14:48:07.273749 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 14:48:07.277034 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 14:48:07.280912 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 14:48:07.287206 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 14:48:07.290416 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 14:48:07.294303 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 14:48:07.300476 0 9 0 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1864 14:48:07.304163 0 9 4 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
1865 14:48:07.307354 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1866 14:48:07.310592 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 14:48:07.317316 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 14:48:07.321050 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 14:48:07.324328 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 14:48:07.330892 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 14:48:07.333887 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 14:48:07.337325 0 10 4 | B1->B0 | 2e2e 2f2f | 1 1 | (1 0) (1 0)
1873 14:48:07.343957 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1874 14:48:07.347785 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 14:48:07.350883 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 14:48:07.357777 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 14:48:07.361002 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 14:48:07.364231 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 14:48:07.367621 0 11 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1880 14:48:07.374468 0 11 4 | B1->B0 | 3d3d 2e2e | 0 0 | (1 1) (0 0)
1881 14:48:07.377997 0 11 8 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
1882 14:48:07.381197 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 14:48:07.387958 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 14:48:07.391053 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 14:48:07.394230 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 14:48:07.401146 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 14:48:07.404387 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 14:48:07.408064 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1889 14:48:07.414464 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1890 14:48:07.418082 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 14:48:07.421138 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 14:48:07.428259 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 14:48:07.431276 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 14:48:07.435091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 14:48:07.438283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 14:48:07.445385 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 14:48:07.448157 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 14:48:07.451777 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 14:48:07.458134 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 14:48:07.461465 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 14:48:07.464992 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 14:48:07.471733 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 14:48:07.474917 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 14:48:07.478190 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1905 14:48:07.485158 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 14:48:07.485243 Total UI for P1: 0, mck2ui 16
1907 14:48:07.491453 best dqsien dly found for B0: ( 0, 14, 4)
1908 14:48:07.491545 Total UI for P1: 0, mck2ui 16
1909 14:48:07.494778 best dqsien dly found for B1: ( 0, 14, 4)
1910 14:48:07.501485 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1911 14:48:07.505179 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1912 14:48:07.505298
1913 14:48:07.508559 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1914 14:48:07.511721 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1915 14:48:07.515314 [Gating] SW calibration Done
1916 14:48:07.515418 ==
1917 14:48:07.518437 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 14:48:07.521599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 14:48:07.521692 ==
1920 14:48:07.521756 RX Vref Scan: 0
1921 14:48:07.521816
1922 14:48:07.525149 RX Vref 0 -> 0, step: 1
1923 14:48:07.525249
1924 14:48:07.528172 RX Delay -130 -> 252, step: 16
1925 14:48:07.531963 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1926 14:48:07.535246 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192
1927 14:48:07.541695 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1928 14:48:07.544784 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1929 14:48:07.548492 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1930 14:48:07.551783 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1931 14:48:07.555406 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1932 14:48:07.558467 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1933 14:48:07.565416 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1934 14:48:07.568634 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1935 14:48:07.571678 iDelay=222, Bit 10, Center 101 (-2 ~ 205) 208
1936 14:48:07.575096 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1937 14:48:07.581251 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1938 14:48:07.584742 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1939 14:48:07.588272 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1940 14:48:07.591393 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1941 14:48:07.591485 ==
1942 14:48:07.594573 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 14:48:07.601552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 14:48:07.601646 ==
1945 14:48:07.601713 DQS Delay:
1946 14:48:07.601782 DQS0 = 0, DQS1 = 0
1947 14:48:07.604640 DQM Delay:
1948 14:48:07.604750 DQM0 = 96, DQM1 = 92
1949 14:48:07.607991 DQ Delay:
1950 14:48:07.611165 DQ0 =101, DQ1 =93, DQ2 =77, DQ3 =93
1951 14:48:07.614949 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101
1952 14:48:07.617958 DQ8 =77, DQ9 =77, DQ10 =101, DQ11 =77
1953 14:48:07.621216 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1954 14:48:07.621308
1955 14:48:07.621376
1956 14:48:07.621437 ==
1957 14:48:07.625005 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 14:48:07.628066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 14:48:07.628152 ==
1960 14:48:07.628219
1961 14:48:07.628280
1962 14:48:07.631581 TX Vref Scan disable
1963 14:48:07.634596 == TX Byte 0 ==
1964 14:48:07.637804 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1965 14:48:07.641548 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1966 14:48:07.644748 == TX Byte 1 ==
1967 14:48:07.647915 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1968 14:48:07.651618 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1969 14:48:07.651710 ==
1970 14:48:07.654965 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 14:48:07.658336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 14:48:07.661545 ==
1973 14:48:07.672811 TX Vref=22, minBit 2, minWin=26, winSum=438
1974 14:48:07.676006 TX Vref=24, minBit 1, minWin=26, winSum=443
1975 14:48:07.679169 TX Vref=26, minBit 0, minWin=27, winSum=447
1976 14:48:07.683063 TX Vref=28, minBit 0, minWin=27, winSum=446
1977 14:48:07.686249 TX Vref=30, minBit 0, minWin=27, winSum=449
1978 14:48:07.689293 TX Vref=32, minBit 0, minWin=27, winSum=447
1979 14:48:07.695990 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 30
1980 14:48:07.696083
1981 14:48:07.699595 Final TX Range 1 Vref 30
1982 14:48:07.699685
1983 14:48:07.699751 ==
1984 14:48:07.702860 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 14:48:07.706040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 14:48:07.706153 ==
1987 14:48:07.706250
1988 14:48:07.706339
1989 14:48:07.709907 TX Vref Scan disable
1990 14:48:07.712795 == TX Byte 0 ==
1991 14:48:07.716324 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1992 14:48:07.719749 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1993 14:48:07.722794 == TX Byte 1 ==
1994 14:48:07.726831 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1995 14:48:07.729338 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1996 14:48:07.729425
1997 14:48:07.733107 [DATLAT]
1998 14:48:07.733193 Freq=800, CH1 RK1
1999 14:48:07.733258
2000 14:48:07.736328 DATLAT Default: 0xa
2001 14:48:07.736421 0, 0xFFFF, sum = 0
2002 14:48:07.739616 1, 0xFFFF, sum = 0
2003 14:48:07.739703 2, 0xFFFF, sum = 0
2004 14:48:07.742798 3, 0xFFFF, sum = 0
2005 14:48:07.742884 4, 0xFFFF, sum = 0
2006 14:48:07.746510 5, 0xFFFF, sum = 0
2007 14:48:07.746600 6, 0xFFFF, sum = 0
2008 14:48:07.749487 7, 0xFFFF, sum = 0
2009 14:48:07.749577 8, 0xFFFF, sum = 0
2010 14:48:07.753358 9, 0x0, sum = 1
2011 14:48:07.753445 10, 0x0, sum = 2
2012 14:48:07.756482 11, 0x0, sum = 3
2013 14:48:07.756569 12, 0x0, sum = 4
2014 14:48:07.759916 best_step = 10
2015 14:48:07.760001
2016 14:48:07.760065 ==
2017 14:48:07.763337 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 14:48:07.766521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 14:48:07.766608 ==
2020 14:48:07.769746 RX Vref Scan: 0
2021 14:48:07.769858
2022 14:48:07.769952 RX Vref 0 -> 0, step: 1
2023 14:48:07.770039
2024 14:48:07.772865 RX Delay -79 -> 252, step: 8
2025 14:48:07.776666 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2026 14:48:07.783210 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2027 14:48:07.786422 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2028 14:48:07.789518 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2029 14:48:07.793351 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2030 14:48:07.796661 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2031 14:48:07.803192 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2032 14:48:07.806620 iDelay=209, Bit 7, Center 92 (-7 ~ 192) 200
2033 14:48:07.809418 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2034 14:48:07.813371 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2035 14:48:07.816458 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2036 14:48:07.819626 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2037 14:48:07.826671 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2038 14:48:07.829848 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2039 14:48:07.833043 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2040 14:48:07.836235 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2041 14:48:07.836349 ==
2042 14:48:07.840015 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 14:48:07.846344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 14:48:07.846458 ==
2045 14:48:07.846552 DQS Delay:
2046 14:48:07.846644 DQS0 = 0, DQS1 = 0
2047 14:48:07.849775 DQM Delay:
2048 14:48:07.849888 DQM0 = 97, DQM1 = 90
2049 14:48:07.853168 DQ Delay:
2050 14:48:07.856517 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2051 14:48:07.859817 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =92
2052 14:48:07.862945 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2053 14:48:07.866167 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2054 14:48:07.866251
2055 14:48:07.866324
2056 14:48:07.873320 [DQSOSCAuto] RK1, (LSB)MR18= 0x4711, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2057 14:48:07.876571 CH1 RK1: MR19=606, MR18=4711
2058 14:48:07.883264 CH1_RK1: MR19=0x606, MR18=0x4711, DQSOSC=392, MR23=63, INC=96, DEC=64
2059 14:48:07.886679 [RxdqsGatingPostProcess] freq 800
2060 14:48:07.890517 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2061 14:48:07.893451 Pre-setting of DQS Precalculation
2062 14:48:07.899843 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2063 14:48:07.906902 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2064 14:48:07.913386 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2065 14:48:07.913479
2066 14:48:07.913547
2067 14:48:07.916903 [Calibration Summary] 1600 Mbps
2068 14:48:07.916991 CH 0, Rank 0
2069 14:48:07.920011 SW Impedance : PASS
2070 14:48:07.923633 DUTY Scan : NO K
2071 14:48:07.923720 ZQ Calibration : PASS
2072 14:48:07.926909 Jitter Meter : NO K
2073 14:48:07.930104 CBT Training : PASS
2074 14:48:07.930191 Write leveling : PASS
2075 14:48:07.933296 RX DQS gating : PASS
2076 14:48:07.933391 RX DQ/DQS(RDDQC) : PASS
2077 14:48:07.937202 TX DQ/DQS : PASS
2078 14:48:07.940426 RX DATLAT : PASS
2079 14:48:07.940507 RX DQ/DQS(Engine): PASS
2080 14:48:07.943557 TX OE : NO K
2081 14:48:07.943662 All Pass.
2082 14:48:07.943753
2083 14:48:07.946935 CH 0, Rank 1
2084 14:48:07.947036 SW Impedance : PASS
2085 14:48:07.950060 DUTY Scan : NO K
2086 14:48:07.953879 ZQ Calibration : PASS
2087 14:48:07.953960 Jitter Meter : NO K
2088 14:48:07.957106 CBT Training : PASS
2089 14:48:07.960235 Write leveling : PASS
2090 14:48:07.960336 RX DQS gating : PASS
2091 14:48:07.963591 RX DQ/DQS(RDDQC) : PASS
2092 14:48:07.963692 TX DQ/DQS : PASS
2093 14:48:07.966756 RX DATLAT : PASS
2094 14:48:07.970403 RX DQ/DQS(Engine): PASS
2095 14:48:07.970512 TX OE : NO K
2096 14:48:07.973450 All Pass.
2097 14:48:07.973525
2098 14:48:07.973625 CH 1, Rank 0
2099 14:48:07.976811 SW Impedance : PASS
2100 14:48:07.976911 DUTY Scan : NO K
2101 14:48:07.980291 ZQ Calibration : PASS
2102 14:48:07.983673 Jitter Meter : NO K
2103 14:48:07.983752 CBT Training : PASS
2104 14:48:07.987164 Write leveling : PASS
2105 14:48:07.990542 RX DQS gating : PASS
2106 14:48:07.990622 RX DQ/DQS(RDDQC) : PASS
2107 14:48:07.993740 TX DQ/DQS : PASS
2108 14:48:07.997269 RX DATLAT : PASS
2109 14:48:07.997355 RX DQ/DQS(Engine): PASS
2110 14:48:08.000621 TX OE : NO K
2111 14:48:08.000707 All Pass.
2112 14:48:08.000793
2113 14:48:08.003971 CH 1, Rank 1
2114 14:48:08.004054 SW Impedance : PASS
2115 14:48:08.006978 DUTY Scan : NO K
2116 14:48:08.007062 ZQ Calibration : PASS
2117 14:48:08.010157 Jitter Meter : NO K
2118 14:48:08.013711 CBT Training : PASS
2119 14:48:08.013796 Write leveling : PASS
2120 14:48:08.016839 RX DQS gating : PASS
2121 14:48:08.020509 RX DQ/DQS(RDDQC) : PASS
2122 14:48:08.020595 TX DQ/DQS : PASS
2123 14:48:08.023824 RX DATLAT : PASS
2124 14:48:08.027407 RX DQ/DQS(Engine): PASS
2125 14:48:08.027493 TX OE : NO K
2126 14:48:08.030155 All Pass.
2127 14:48:08.030239
2128 14:48:08.030304 DramC Write-DBI off
2129 14:48:08.033845 PER_BANK_REFRESH: Hybrid Mode
2130 14:48:08.033932 TX_TRACKING: ON
2131 14:48:08.037029 [GetDramInforAfterCalByMRR] Vendor 6.
2132 14:48:08.044061 [GetDramInforAfterCalByMRR] Revision 606.
2133 14:48:08.047289 [GetDramInforAfterCalByMRR] Revision 2 0.
2134 14:48:08.047375 MR0 0x3b3b
2135 14:48:08.047440 MR8 0x5151
2136 14:48:08.050366 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2137 14:48:08.050454
2138 14:48:08.053572 MR0 0x3b3b
2139 14:48:08.053656 MR8 0x5151
2140 14:48:08.057351 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 14:48:08.057435
2142 14:48:08.067429 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2143 14:48:08.070509 [FAST_K] Save calibration result to emmc
2144 14:48:08.073601 [FAST_K] Save calibration result to emmc
2145 14:48:08.077432 dram_init: config_dvfs: 1
2146 14:48:08.080557 dramc_set_vcore_voltage set vcore to 662500
2147 14:48:08.083793 Read voltage for 1200, 2
2148 14:48:08.083877 Vio18 = 0
2149 14:48:08.083941 Vcore = 662500
2150 14:48:08.087291 Vdram = 0
2151 14:48:08.087374 Vddq = 0
2152 14:48:08.087439 Vmddr = 0
2153 14:48:08.093525 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2154 14:48:08.097399 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2155 14:48:08.100584 MEM_TYPE=3, freq_sel=15
2156 14:48:08.103671 sv_algorithm_assistance_LP4_1600
2157 14:48:08.107163 ============ PULL DRAM RESETB DOWN ============
2158 14:48:08.110385 ========== PULL DRAM RESETB DOWN end =========
2159 14:48:08.117025 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2160 14:48:08.120326 ===================================
2161 14:48:08.120418 LPDDR4 DRAM CONFIGURATION
2162 14:48:08.123824 ===================================
2163 14:48:08.127205 EX_ROW_EN[0] = 0x0
2164 14:48:08.130500 EX_ROW_EN[1] = 0x0
2165 14:48:08.130583 LP4Y_EN = 0x0
2166 14:48:08.133708 WORK_FSP = 0x0
2167 14:48:08.133791 WL = 0x4
2168 14:48:08.137226 RL = 0x4
2169 14:48:08.137315 BL = 0x2
2170 14:48:08.140396 RPST = 0x0
2171 14:48:08.140480 RD_PRE = 0x0
2172 14:48:08.143771 WR_PRE = 0x1
2173 14:48:08.143855 WR_PST = 0x0
2174 14:48:08.146990 DBI_WR = 0x0
2175 14:48:08.147075 DBI_RD = 0x0
2176 14:48:08.150655 OTF = 0x1
2177 14:48:08.153501 ===================================
2178 14:48:08.157161 ===================================
2179 14:48:08.157250 ANA top config
2180 14:48:08.160368 ===================================
2181 14:48:08.163554 DLL_ASYNC_EN = 0
2182 14:48:08.167337 ALL_SLAVE_EN = 0
2183 14:48:08.167423 NEW_RANK_MODE = 1
2184 14:48:08.170531 DLL_IDLE_MODE = 1
2185 14:48:08.173738 LP45_APHY_COMB_EN = 1
2186 14:48:08.177115 TX_ODT_DIS = 1
2187 14:48:08.177227 NEW_8X_MODE = 1
2188 14:48:08.180611 ===================================
2189 14:48:08.183809 ===================================
2190 14:48:08.187599 data_rate = 2400
2191 14:48:08.190742 CKR = 1
2192 14:48:08.193799 DQ_P2S_RATIO = 8
2193 14:48:08.197464 ===================================
2194 14:48:08.200593 CA_P2S_RATIO = 8
2195 14:48:08.204267 DQ_CA_OPEN = 0
2196 14:48:08.204384 DQ_SEMI_OPEN = 0
2197 14:48:08.207352 CA_SEMI_OPEN = 0
2198 14:48:08.211013 CA_FULL_RATE = 0
2199 14:48:08.214084 DQ_CKDIV4_EN = 0
2200 14:48:08.217655 CA_CKDIV4_EN = 0
2201 14:48:08.220785 CA_PREDIV_EN = 0
2202 14:48:08.220873 PH8_DLY = 17
2203 14:48:08.224002 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2204 14:48:08.227645 DQ_AAMCK_DIV = 4
2205 14:48:08.230845 CA_AAMCK_DIV = 4
2206 14:48:08.234041 CA_ADMCK_DIV = 4
2207 14:48:08.234127 DQ_TRACK_CA_EN = 0
2208 14:48:08.237322 CA_PICK = 1200
2209 14:48:08.241269 CA_MCKIO = 1200
2210 14:48:08.244383 MCKIO_SEMI = 0
2211 14:48:08.247438 PLL_FREQ = 2366
2212 14:48:08.251135 DQ_UI_PI_RATIO = 32
2213 14:48:08.254053 CA_UI_PI_RATIO = 0
2214 14:48:08.257325 ===================================
2215 14:48:08.260910 ===================================
2216 14:48:08.260996 memory_type:LPDDR4
2217 14:48:08.264459 GP_NUM : 10
2218 14:48:08.267747 SRAM_EN : 1
2219 14:48:08.267833 MD32_EN : 0
2220 14:48:08.270999 ===================================
2221 14:48:08.274211 [ANA_INIT] >>>>>>>>>>>>>>
2222 14:48:08.277717 <<<<<< [CONFIGURE PHASE]: ANA_TX
2223 14:48:08.280850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2224 14:48:08.284292 ===================================
2225 14:48:08.287788 data_rate = 2400,PCW = 0X5b00
2226 14:48:08.291104 ===================================
2227 14:48:08.294314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2228 14:48:08.297938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2229 14:48:08.304600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2230 14:48:08.307933 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2231 14:48:08.310987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2232 14:48:08.314488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2233 14:48:08.317958 [ANA_INIT] flow start
2234 14:48:08.320955 [ANA_INIT] PLL >>>>>>>>
2235 14:48:08.321043 [ANA_INIT] PLL <<<<<<<<
2236 14:48:08.324264 [ANA_INIT] MIDPI >>>>>>>>
2237 14:48:08.327713 [ANA_INIT] MIDPI <<<<<<<<
2238 14:48:08.327800 [ANA_INIT] DLL >>>>>>>>
2239 14:48:08.331407 [ANA_INIT] DLL <<<<<<<<
2240 14:48:08.334456 [ANA_INIT] flow end
2241 14:48:08.337774 ============ LP4 DIFF to SE enter ============
2242 14:48:08.340845 ============ LP4 DIFF to SE exit ============
2243 14:48:08.344853 [ANA_INIT] <<<<<<<<<<<<<
2244 14:48:08.347843 [Flow] Enable top DCM control >>>>>
2245 14:48:08.351129 [Flow] Enable top DCM control <<<<<
2246 14:48:08.354362 Enable DLL master slave shuffle
2247 14:48:08.357643 ==============================================================
2248 14:48:08.360794 Gating Mode config
2249 14:48:08.367805 ==============================================================
2250 14:48:08.367897 Config description:
2251 14:48:08.377825 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2252 14:48:08.384359 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2253 14:48:08.388020 SELPH_MODE 0: By rank 1: By Phase
2254 14:48:08.394360 ==============================================================
2255 14:48:08.397627 GAT_TRACK_EN = 1
2256 14:48:08.401267 RX_GATING_MODE = 2
2257 14:48:08.404274 RX_GATING_TRACK_MODE = 2
2258 14:48:08.407921 SELPH_MODE = 1
2259 14:48:08.411289 PICG_EARLY_EN = 1
2260 14:48:08.411375 VALID_LAT_VALUE = 1
2261 14:48:08.418181 ==============================================================
2262 14:48:08.421146 Enter into Gating configuration >>>>
2263 14:48:08.424594 Exit from Gating configuration <<<<
2264 14:48:08.428283 Enter into DVFS_PRE_config >>>>>
2265 14:48:08.437920 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2266 14:48:08.441729 Exit from DVFS_PRE_config <<<<<
2267 14:48:08.444840 Enter into PICG configuration >>>>
2268 14:48:08.448015 Exit from PICG configuration <<<<
2269 14:48:08.451133 [RX_INPUT] configuration >>>>>
2270 14:48:08.455052 [RX_INPUT] configuration <<<<<
2271 14:48:08.458188 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2272 14:48:08.464643 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2273 14:48:08.471530 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2274 14:48:08.477919 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2275 14:48:08.484880 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2276 14:48:08.488509 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2277 14:48:08.494829 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2278 14:48:08.498589 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2279 14:48:08.501778 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2280 14:48:08.504873 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2281 14:48:08.508300 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2282 14:48:08.515213 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 14:48:08.518643 ===================================
2284 14:48:08.518773 LPDDR4 DRAM CONFIGURATION
2285 14:48:08.522180 ===================================
2286 14:48:08.525513 EX_ROW_EN[0] = 0x0
2287 14:48:08.528423 EX_ROW_EN[1] = 0x0
2288 14:48:08.528527 LP4Y_EN = 0x0
2289 14:48:08.532225 WORK_FSP = 0x0
2290 14:48:08.532333 WL = 0x4
2291 14:48:08.535563 RL = 0x4
2292 14:48:08.535668 BL = 0x2
2293 14:48:08.538708 RPST = 0x0
2294 14:48:08.538806 RD_PRE = 0x0
2295 14:48:08.541824 WR_PRE = 0x1
2296 14:48:08.541922 WR_PST = 0x0
2297 14:48:08.545460 DBI_WR = 0x0
2298 14:48:08.545576 DBI_RD = 0x0
2299 14:48:08.548787 OTF = 0x1
2300 14:48:08.551665 ===================================
2301 14:48:08.555452 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2302 14:48:08.558433 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2303 14:48:08.565145 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 14:48:08.568234 ===================================
2305 14:48:08.568361 LPDDR4 DRAM CONFIGURATION
2306 14:48:08.572136 ===================================
2307 14:48:08.575306 EX_ROW_EN[0] = 0x10
2308 14:48:08.575394 EX_ROW_EN[1] = 0x0
2309 14:48:08.578582 LP4Y_EN = 0x0
2310 14:48:08.581769 WORK_FSP = 0x0
2311 14:48:08.581859 WL = 0x4
2312 14:48:08.584967 RL = 0x4
2313 14:48:08.585056 BL = 0x2
2314 14:48:08.588791 RPST = 0x0
2315 14:48:08.588885 RD_PRE = 0x0
2316 14:48:08.591975 WR_PRE = 0x1
2317 14:48:08.592061 WR_PST = 0x0
2318 14:48:08.595151 DBI_WR = 0x0
2319 14:48:08.595240 DBI_RD = 0x0
2320 14:48:08.598675 OTF = 0x1
2321 14:48:08.601678 ===================================
2322 14:48:08.605384 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2323 14:48:08.608627 ==
2324 14:48:08.611825 Dram Type= 6, Freq= 0, CH_0, rank 0
2325 14:48:08.615428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2326 14:48:08.615509 ==
2327 14:48:08.618541 [Duty_Offset_Calibration]
2328 14:48:08.618633 B0:2 B1:1 CA:1
2329 14:48:08.618717
2330 14:48:08.621564 [DutyScan_Calibration_Flow] k_type=0
2331 14:48:08.631359
2332 14:48:08.631466 ==CLK 0==
2333 14:48:08.634750 Final CLK duty delay cell = 0
2334 14:48:08.637880 [0] MAX Duty = 5187%(X100), DQS PI = 24
2335 14:48:08.641724 [0] MIN Duty = 4875%(X100), DQS PI = 0
2336 14:48:08.641816 [0] AVG Duty = 5031%(X100)
2337 14:48:08.644829
2338 14:48:08.644913 CH0 CLK Duty spec in!! Max-Min= 312%
2339 14:48:08.651439 [DutyScan_Calibration_Flow] ====Done====
2340 14:48:08.651534
2341 14:48:08.654453 [DutyScan_Calibration_Flow] k_type=1
2342 14:48:08.669748
2343 14:48:08.669867 ==DQS 0 ==
2344 14:48:08.673308 Final DQS duty delay cell = -4
2345 14:48:08.676696 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2346 14:48:08.680188 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2347 14:48:08.683311 [-4] AVG Duty = 4937%(X100)
2348 14:48:08.683402
2349 14:48:08.683464 ==DQS 1 ==
2350 14:48:08.686601 Final DQS duty delay cell = 0
2351 14:48:08.690092 [0] MAX Duty = 5156%(X100), DQS PI = 0
2352 14:48:08.693462 [0] MIN Duty = 5000%(X100), DQS PI = 32
2353 14:48:08.696547 [0] AVG Duty = 5078%(X100)
2354 14:48:08.696726
2355 14:48:08.700267 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2356 14:48:08.700373
2357 14:48:08.703399 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2358 14:48:08.706996 [DutyScan_Calibration_Flow] ====Done====
2359 14:48:08.707070
2360 14:48:08.710183 [DutyScan_Calibration_Flow] k_type=3
2361 14:48:08.726597
2362 14:48:08.726771 ==DQM 0 ==
2363 14:48:08.730531 Final DQM duty delay cell = 0
2364 14:48:08.733741 [0] MAX Duty = 5156%(X100), DQS PI = 32
2365 14:48:08.736897 [0] MIN Duty = 4906%(X100), DQS PI = 50
2366 14:48:08.736983 [0] AVG Duty = 5031%(X100)
2367 14:48:08.740204
2368 14:48:08.740274 ==DQM 1 ==
2369 14:48:08.743438 Final DQM duty delay cell = 0
2370 14:48:08.746714 [0] MAX Duty = 5124%(X100), DQS PI = 6
2371 14:48:08.750468 [0] MIN Duty = 5031%(X100), DQS PI = 16
2372 14:48:08.750574 [0] AVG Duty = 5077%(X100)
2373 14:48:08.753570
2374 14:48:08.756937 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2375 14:48:08.757029
2376 14:48:08.759935 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2377 14:48:08.763527 [DutyScan_Calibration_Flow] ====Done====
2378 14:48:08.763625
2379 14:48:08.766660 [DutyScan_Calibration_Flow] k_type=2
2380 14:48:08.783415
2381 14:48:08.783539 ==DQ 0 ==
2382 14:48:08.787838 Final DQ duty delay cell = 0
2383 14:48:08.789768 [0] MAX Duty = 5062%(X100), DQS PI = 32
2384 14:48:08.792896 [0] MIN Duty = 4844%(X100), DQS PI = 62
2385 14:48:08.792976 [0] AVG Duty = 4953%(X100)
2386 14:48:08.796467
2387 14:48:08.796554 ==DQ 1 ==
2388 14:48:08.799555 Final DQ duty delay cell = 0
2389 14:48:08.802993 [0] MAX Duty = 5093%(X100), DQS PI = 24
2390 14:48:08.806360 [0] MIN Duty = 4907%(X100), DQS PI = 36
2391 14:48:08.806466 [0] AVG Duty = 5000%(X100)
2392 14:48:08.806599
2393 14:48:08.809940 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2394 14:48:08.813009
2395 14:48:08.816654 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2396 14:48:08.820064 [DutyScan_Calibration_Flow] ====Done====
2397 14:48:08.820154 ==
2398 14:48:08.823218 Dram Type= 6, Freq= 0, CH_1, rank 0
2399 14:48:08.826512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2400 14:48:08.826591 ==
2401 14:48:08.829744 [Duty_Offset_Calibration]
2402 14:48:08.829868 B0:1 B1:0 CA:1
2403 14:48:08.829970
2404 14:48:08.833121 [DutyScan_Calibration_Flow] k_type=0
2405 14:48:08.842489
2406 14:48:08.842627 ==CLK 0==
2407 14:48:08.845542 Final CLK duty delay cell = -4
2408 14:48:08.848860 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2409 14:48:08.852237 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2410 14:48:08.855442 [-4] AVG Duty = 4969%(X100)
2411 14:48:08.855522
2412 14:48:08.859445 CH1 CLK Duty spec in!! Max-Min= 124%
2413 14:48:08.862534 [DutyScan_Calibration_Flow] ====Done====
2414 14:48:08.862610
2415 14:48:08.865622 [DutyScan_Calibration_Flow] k_type=1
2416 14:48:08.882446
2417 14:48:08.882565 ==DQS 0 ==
2418 14:48:08.885635 Final DQS duty delay cell = 0
2419 14:48:08.889324 [0] MAX Duty = 5062%(X100), DQS PI = 14
2420 14:48:08.892300 [0] MIN Duty = 4844%(X100), DQS PI = 0
2421 14:48:08.892397 [0] AVG Duty = 4953%(X100)
2422 14:48:08.895681
2423 14:48:08.895769 ==DQS 1 ==
2424 14:48:08.898947 Final DQS duty delay cell = 0
2425 14:48:08.902444 [0] MAX Duty = 5187%(X100), DQS PI = 18
2426 14:48:08.905560 [0] MIN Duty = 4938%(X100), DQS PI = 10
2427 14:48:08.905644 [0] AVG Duty = 5062%(X100)
2428 14:48:08.908761
2429 14:48:08.912561 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2430 14:48:08.912727
2431 14:48:08.915671 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2432 14:48:08.918753 [DutyScan_Calibration_Flow] ====Done====
2433 14:48:08.918838
2434 14:48:08.922274 [DutyScan_Calibration_Flow] k_type=3
2435 14:48:08.939125
2436 14:48:08.939238 ==DQM 0 ==
2437 14:48:08.942484 Final DQM duty delay cell = 0
2438 14:48:08.945806 [0] MAX Duty = 5156%(X100), DQS PI = 8
2439 14:48:08.948626 [0] MIN Duty = 5031%(X100), DQS PI = 0
2440 14:48:08.948747 [0] AVG Duty = 5093%(X100)
2441 14:48:08.952041
2442 14:48:08.952126 ==DQM 1 ==
2443 14:48:08.955641 Final DQM duty delay cell = 0
2444 14:48:08.958830 [0] MAX Duty = 5031%(X100), DQS PI = 16
2445 14:48:08.962167 [0] MIN Duty = 4907%(X100), DQS PI = 36
2446 14:48:08.962253 [0] AVG Duty = 4969%(X100)
2447 14:48:08.962318
2448 14:48:08.968688 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2449 14:48:08.968783
2450 14:48:08.972250 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2451 14:48:08.975773 [DutyScan_Calibration_Flow] ====Done====
2452 14:48:08.975860
2453 14:48:08.979057 [DutyScan_Calibration_Flow] k_type=2
2454 14:48:08.994492
2455 14:48:08.994625 ==DQ 0 ==
2456 14:48:08.997764 Final DQ duty delay cell = -4
2457 14:48:09.001087 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2458 14:48:09.004721 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2459 14:48:09.007903 [-4] AVG Duty = 4984%(X100)
2460 14:48:09.007990
2461 14:48:09.008057 ==DQ 1 ==
2462 14:48:09.011099 Final DQ duty delay cell = 0
2463 14:48:09.014278 [0] MAX Duty = 5125%(X100), DQS PI = 20
2464 14:48:09.017588 [0] MIN Duty = 4969%(X100), DQS PI = 12
2465 14:48:09.017675 [0] AVG Duty = 5047%(X100)
2466 14:48:09.021514
2467 14:48:09.024626 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2468 14:48:09.024712
2469 14:48:09.028267 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2470 14:48:09.031391 [DutyScan_Calibration_Flow] ====Done====
2471 14:48:09.034609 nWR fixed to 30
2472 14:48:09.034700 [ModeRegInit_LP4] CH0 RK0
2473 14:48:09.037902 [ModeRegInit_LP4] CH0 RK1
2474 14:48:09.041194 [ModeRegInit_LP4] CH1 RK0
2475 14:48:09.041283 [ModeRegInit_LP4] CH1 RK1
2476 14:48:09.044484 match AC timing 7
2477 14:48:09.047848 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2478 14:48:09.051622 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2479 14:48:09.057910 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2480 14:48:09.061775 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2481 14:48:09.067941 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2482 14:48:09.068031 ==
2483 14:48:09.071143 Dram Type= 6, Freq= 0, CH_0, rank 0
2484 14:48:09.075015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 14:48:09.075101 ==
2486 14:48:09.081644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 14:48:09.084505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2488 14:48:09.095107 [CA 0] Center 39 (8~70) winsize 63
2489 14:48:09.097920 [CA 1] Center 39 (8~70) winsize 63
2490 14:48:09.101415 [CA 2] Center 35 (5~66) winsize 62
2491 14:48:09.104855 [CA 3] Center 34 (4~65) winsize 62
2492 14:48:09.108444 [CA 4] Center 33 (3~64) winsize 62
2493 14:48:09.111708 [CA 5] Center 32 (3~62) winsize 60
2494 14:48:09.111792
2495 14:48:09.115360 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2496 14:48:09.115445
2497 14:48:09.117940 [CATrainingPosCal] consider 1 rank data
2498 14:48:09.121849 u2DelayCellTimex100 = 270/100 ps
2499 14:48:09.124785 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2500 14:48:09.128309 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2501 14:48:09.135214 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2502 14:48:09.138235 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2503 14:48:09.141508 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2504 14:48:09.144790 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2505 14:48:09.144875
2506 14:48:09.148565 CA PerBit enable=1, Macro0, CA PI delay=32
2507 14:48:09.148649
2508 14:48:09.151791 [CBTSetCACLKResult] CA Dly = 32
2509 14:48:09.151877 CS Dly: 6 (0~37)
2510 14:48:09.151943 ==
2511 14:48:09.155061 Dram Type= 6, Freq= 0, CH_0, rank 1
2512 14:48:09.161957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 14:48:09.162045 ==
2514 14:48:09.165202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2515 14:48:09.172024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2516 14:48:09.180488 [CA 0] Center 38 (8~69) winsize 62
2517 14:48:09.183625 [CA 1] Center 38 (8~69) winsize 62
2518 14:48:09.187309 [CA 2] Center 35 (5~66) winsize 62
2519 14:48:09.190352 [CA 3] Center 34 (4~65) winsize 62
2520 14:48:09.193651 [CA 4] Center 33 (3~64) winsize 62
2521 14:48:09.196921 [CA 5] Center 32 (3~62) winsize 60
2522 14:48:09.197007
2523 14:48:09.200853 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2524 14:48:09.200938
2525 14:48:09.204060 [CATrainingPosCal] consider 2 rank data
2526 14:48:09.207276 u2DelayCellTimex100 = 270/100 ps
2527 14:48:09.210559 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2528 14:48:09.213999 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2529 14:48:09.220602 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2530 14:48:09.224059 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2531 14:48:09.226955 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2532 14:48:09.230410 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2533 14:48:09.230517
2534 14:48:09.233718 CA PerBit enable=1, Macro0, CA PI delay=32
2535 14:48:09.233810
2536 14:48:09.237050 [CBTSetCACLKResult] CA Dly = 32
2537 14:48:09.237144 CS Dly: 6 (0~38)
2538 14:48:09.237235
2539 14:48:09.240715 ----->DramcWriteLeveling(PI) begin...
2540 14:48:09.244139 ==
2541 14:48:09.247221 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 14:48:09.250550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 14:48:09.250632 ==
2544 14:48:09.254051 Write leveling (Byte 0): 33 => 33
2545 14:48:09.257484 Write leveling (Byte 1): 31 => 31
2546 14:48:09.257599 DramcWriteLeveling(PI) end<-----
2547 14:48:09.260524
2548 14:48:09.260600 ==
2549 14:48:09.264302 Dram Type= 6, Freq= 0, CH_0, rank 0
2550 14:48:09.267503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 14:48:09.267603 ==
2552 14:48:09.270729 [Gating] SW mode calibration
2553 14:48:09.277674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2554 14:48:09.280826 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2555 14:48:09.287250 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2556 14:48:09.290433 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2557 14:48:09.294188 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 14:48:09.300565 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 14:48:09.303720 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 14:48:09.307595 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 14:48:09.314020 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2562 14:48:09.317432 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2563 14:48:09.320465 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2564 14:48:09.327342 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 14:48:09.330454 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 14:48:09.333578 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 14:48:09.340589 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 14:48:09.343795 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 14:48:09.347384 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2570 14:48:09.354024 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2571 14:48:09.357329 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2572 14:48:09.360581 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 14:48:09.367174 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 14:48:09.370396 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 14:48:09.373546 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 14:48:09.377203 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 14:48:09.383540 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2578 14:48:09.387344 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2579 14:48:09.390215 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2580 14:48:09.397237 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 14:48:09.400319 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 14:48:09.404230 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 14:48:09.410537 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 14:48:09.413708 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 14:48:09.416954 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 14:48:09.424133 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 14:48:09.427217 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 14:48:09.430352 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 14:48:09.437376 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 14:48:09.440285 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 14:48:09.444009 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 14:48:09.450216 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 14:48:09.454302 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 14:48:09.457192 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2595 14:48:09.463796 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2596 14:48:09.463879 Total UI for P1: 0, mck2ui 16
2597 14:48:09.467020 best dqsien dly found for B0: ( 1, 3, 28)
2598 14:48:09.474051 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 14:48:09.477290 Total UI for P1: 0, mck2ui 16
2600 14:48:09.480439 best dqsien dly found for B1: ( 1, 4, 0)
2601 14:48:09.483673 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2602 14:48:09.486798 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2603 14:48:09.486915
2604 14:48:09.490352 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2605 14:48:09.493866 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2606 14:48:09.497204 [Gating] SW calibration Done
2607 14:48:09.497324 ==
2608 14:48:09.500239 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 14:48:09.503679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 14:48:09.503791 ==
2611 14:48:09.507034 RX Vref Scan: 0
2612 14:48:09.507147
2613 14:48:09.507243 RX Vref 0 -> 0, step: 1
2614 14:48:09.507341
2615 14:48:09.510466 RX Delay -40 -> 252, step: 8
2616 14:48:09.517318 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2617 14:48:09.520258 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2618 14:48:09.523474 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2619 14:48:09.527303 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2620 14:48:09.530282 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2621 14:48:09.534093 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2622 14:48:09.540530 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2623 14:48:09.543779 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2624 14:48:09.546886 iDelay=200, Bit 8, Center 99 (40 ~ 159) 120
2625 14:48:09.550477 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2626 14:48:09.553672 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2627 14:48:09.560614 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2628 14:48:09.563701 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2629 14:48:09.567250 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2630 14:48:09.570149 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2631 14:48:09.573940 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2632 14:48:09.577467 ==
2633 14:48:09.580546 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 14:48:09.583499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 14:48:09.583681 ==
2636 14:48:09.583802 DQS Delay:
2637 14:48:09.587341 DQS0 = 0, DQS1 = 0
2638 14:48:09.587430 DQM Delay:
2639 14:48:09.590577 DQM0 = 121, DQM1 = 113
2640 14:48:09.590656 DQ Delay:
2641 14:48:09.593898 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2642 14:48:09.597060 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2643 14:48:09.600238 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2644 14:48:09.603450 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2645 14:48:09.603561
2646 14:48:09.603645
2647 14:48:09.603721 ==
2648 14:48:09.607247 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 14:48:09.613713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 14:48:09.613824 ==
2651 14:48:09.613925
2652 14:48:09.614002
2653 14:48:09.614106 TX Vref Scan disable
2654 14:48:09.617307 == TX Byte 0 ==
2655 14:48:09.620698 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2656 14:48:09.623718 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2657 14:48:09.627270 == TX Byte 1 ==
2658 14:48:09.630200 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2659 14:48:09.633727 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2660 14:48:09.637161 ==
2661 14:48:09.640308 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 14:48:09.643521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 14:48:09.643607 ==
2664 14:48:09.655177 TX Vref=22, minBit 12, minWin=24, winSum=407
2665 14:48:09.658671 TX Vref=24, minBit 4, minWin=24, winSum=414
2666 14:48:09.661745 TX Vref=26, minBit 3, minWin=25, winSum=416
2667 14:48:09.664870 TX Vref=28, minBit 12, minWin=25, winSum=426
2668 14:48:09.668189 TX Vref=30, minBit 12, minWin=25, winSum=425
2669 14:48:09.675272 TX Vref=32, minBit 0, minWin=26, winSum=421
2670 14:48:09.678174 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 32
2671 14:48:09.678256
2672 14:48:09.681977 Final TX Range 1 Vref 32
2673 14:48:09.682051
2674 14:48:09.682112 ==
2675 14:48:09.685216 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 14:48:09.688386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 14:48:09.688462 ==
2678 14:48:09.691574
2679 14:48:09.691677
2680 14:48:09.691768 TX Vref Scan disable
2681 14:48:09.695026 == TX Byte 0 ==
2682 14:48:09.698699 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2683 14:48:09.701911 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2684 14:48:09.705153 == TX Byte 1 ==
2685 14:48:09.708408 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2686 14:48:09.711608 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2687 14:48:09.711713
2688 14:48:09.715373 [DATLAT]
2689 14:48:09.715449 Freq=1200, CH0 RK0
2690 14:48:09.715517
2691 14:48:09.718434 DATLAT Default: 0xd
2692 14:48:09.718505 0, 0xFFFF, sum = 0
2693 14:48:09.721498 1, 0xFFFF, sum = 0
2694 14:48:09.721572 2, 0xFFFF, sum = 0
2695 14:48:09.725349 3, 0xFFFF, sum = 0
2696 14:48:09.725424 4, 0xFFFF, sum = 0
2697 14:48:09.728749 5, 0xFFFF, sum = 0
2698 14:48:09.728819 6, 0xFFFF, sum = 0
2699 14:48:09.731771 7, 0xFFFF, sum = 0
2700 14:48:09.734880 8, 0xFFFF, sum = 0
2701 14:48:09.734952 9, 0xFFFF, sum = 0
2702 14:48:09.738703 10, 0xFFFF, sum = 0
2703 14:48:09.738810 11, 0xFFFF, sum = 0
2704 14:48:09.741695 12, 0x0, sum = 1
2705 14:48:09.741767 13, 0x0, sum = 2
2706 14:48:09.745238 14, 0x0, sum = 3
2707 14:48:09.745313 15, 0x0, sum = 4
2708 14:48:09.745375 best_step = 13
2709 14:48:09.745432
2710 14:48:09.748125 ==
2711 14:48:09.751909 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 14:48:09.755009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 14:48:09.755091 ==
2714 14:48:09.755154 RX Vref Scan: 1
2715 14:48:09.755214
2716 14:48:09.758332 Set Vref Range= 32 -> 127
2717 14:48:09.758404
2718 14:48:09.761903 RX Vref 32 -> 127, step: 1
2719 14:48:09.761981
2720 14:48:09.764932 RX Delay -5 -> 252, step: 4
2721 14:48:09.765006
2722 14:48:09.768288 Set Vref, RX VrefLevel [Byte0]: 32
2723 14:48:09.771747 [Byte1]: 32
2724 14:48:09.771849
2725 14:48:09.774933 Set Vref, RX VrefLevel [Byte0]: 33
2726 14:48:09.778176 [Byte1]: 33
2727 14:48:09.778255
2728 14:48:09.781465 Set Vref, RX VrefLevel [Byte0]: 34
2729 14:48:09.785022 [Byte1]: 34
2730 14:48:09.789195
2731 14:48:09.789276 Set Vref, RX VrefLevel [Byte0]: 35
2732 14:48:09.792406 [Byte1]: 35
2733 14:48:09.796773
2734 14:48:09.796879 Set Vref, RX VrefLevel [Byte0]: 36
2735 14:48:09.799966 [Byte1]: 36
2736 14:48:09.804600
2737 14:48:09.804677 Set Vref, RX VrefLevel [Byte0]: 37
2738 14:48:09.808437 [Byte1]: 37
2739 14:48:09.812878
2740 14:48:09.812955 Set Vref, RX VrefLevel [Byte0]: 38
2741 14:48:09.816154 [Byte1]: 38
2742 14:48:09.820635
2743 14:48:09.820710 Set Vref, RX VrefLevel [Byte0]: 39
2744 14:48:09.823728 [Byte1]: 39
2745 14:48:09.828037
2746 14:48:09.828112 Set Vref, RX VrefLevel [Byte0]: 40
2747 14:48:09.831912 [Byte1]: 40
2748 14:48:09.836291
2749 14:48:09.836408 Set Vref, RX VrefLevel [Byte0]: 41
2750 14:48:09.839477 [Byte1]: 41
2751 14:48:09.844279
2752 14:48:09.844402 Set Vref, RX VrefLevel [Byte0]: 42
2753 14:48:09.847505 [Byte1]: 42
2754 14:48:09.851985
2755 14:48:09.852103 Set Vref, RX VrefLevel [Byte0]: 43
2756 14:48:09.855184 [Byte1]: 43
2757 14:48:09.859428
2758 14:48:09.859507 Set Vref, RX VrefLevel [Byte0]: 44
2759 14:48:09.863241 [Byte1]: 44
2760 14:48:09.867591
2761 14:48:09.867681 Set Vref, RX VrefLevel [Byte0]: 45
2762 14:48:09.871178 [Byte1]: 45
2763 14:48:09.875417
2764 14:48:09.875498 Set Vref, RX VrefLevel [Byte0]: 46
2765 14:48:09.878923 [Byte1]: 46
2766 14:48:09.883209
2767 14:48:09.883293 Set Vref, RX VrefLevel [Byte0]: 47
2768 14:48:09.886757 [Byte1]: 47
2769 14:48:09.891327
2770 14:48:09.891429 Set Vref, RX VrefLevel [Byte0]: 48
2771 14:48:09.894145 [Byte1]: 48
2772 14:48:09.899197
2773 14:48:09.899271 Set Vref, RX VrefLevel [Byte0]: 49
2774 14:48:09.902133 [Byte1]: 49
2775 14:48:09.907061
2776 14:48:09.907140 Set Vref, RX VrefLevel [Byte0]: 50
2777 14:48:09.910063 [Byte1]: 50
2778 14:48:09.914741
2779 14:48:09.914847 Set Vref, RX VrefLevel [Byte0]: 51
2780 14:48:09.917892 [Byte1]: 51
2781 14:48:09.922577
2782 14:48:09.922668 Set Vref, RX VrefLevel [Byte0]: 52
2783 14:48:09.925623 [Byte1]: 52
2784 14:48:09.930815
2785 14:48:09.930939 Set Vref, RX VrefLevel [Byte0]: 53
2786 14:48:09.933879 [Byte1]: 53
2787 14:48:09.938356
2788 14:48:09.938445 Set Vref, RX VrefLevel [Byte0]: 54
2789 14:48:09.941814 [Byte1]: 54
2790 14:48:09.946025
2791 14:48:09.946112 Set Vref, RX VrefLevel [Byte0]: 55
2792 14:48:09.949223 [Byte1]: 55
2793 14:48:09.953861
2794 14:48:09.953957 Set Vref, RX VrefLevel [Byte0]: 56
2795 14:48:09.957124 [Byte1]: 56
2796 14:48:09.961632
2797 14:48:09.961710 Set Vref, RX VrefLevel [Byte0]: 57
2798 14:48:09.965331 [Byte1]: 57
2799 14:48:09.969791
2800 14:48:09.969869 Set Vref, RX VrefLevel [Byte0]: 58
2801 14:48:09.972996 [Byte1]: 58
2802 14:48:09.977523
2803 14:48:09.977599 Set Vref, RX VrefLevel [Byte0]: 59
2804 14:48:09.980672 [Byte1]: 59
2805 14:48:09.985614
2806 14:48:09.985687 Set Vref, RX VrefLevel [Byte0]: 60
2807 14:48:09.988906 [Byte1]: 60
2808 14:48:09.993429
2809 14:48:09.993532 Set Vref, RX VrefLevel [Byte0]: 61
2810 14:48:09.996986 [Byte1]: 61
2811 14:48:10.000838
2812 14:48:10.000911 Set Vref, RX VrefLevel [Byte0]: 62
2813 14:48:10.004655 [Byte1]: 62
2814 14:48:10.008811
2815 14:48:10.008912 Set Vref, RX VrefLevel [Byte0]: 63
2816 14:48:10.012451 [Byte1]: 63
2817 14:48:10.016819
2818 14:48:10.016893 Set Vref, RX VrefLevel [Byte0]: 64
2819 14:48:10.020519 [Byte1]: 64
2820 14:48:10.024482
2821 14:48:10.024552 Set Vref, RX VrefLevel [Byte0]: 65
2822 14:48:10.027988 [Byte1]: 65
2823 14:48:10.032266
2824 14:48:10.032381 Set Vref, RX VrefLevel [Byte0]: 66
2825 14:48:10.035680 [Byte1]: 66
2826 14:48:10.040510
2827 14:48:10.040583 Set Vref, RX VrefLevel [Byte0]: 67
2828 14:48:10.043551 [Byte1]: 67
2829 14:48:10.048245
2830 14:48:10.048356 Set Vref, RX VrefLevel [Byte0]: 68
2831 14:48:10.051420 [Byte1]: 68
2832 14:48:10.055784
2833 14:48:10.055862 Set Vref, RX VrefLevel [Byte0]: 69
2834 14:48:10.059191 [Byte1]: 69
2835 14:48:10.063774
2836 14:48:10.063848 Set Vref, RX VrefLevel [Byte0]: 70
2837 14:48:10.066857 [Byte1]: 70
2838 14:48:10.071817
2839 14:48:10.071922 Set Vref, RX VrefLevel [Byte0]: 71
2840 14:48:10.075028 [Byte1]: 71
2841 14:48:10.079475
2842 14:48:10.079579 Final RX Vref Byte 0 = 54 to rank0
2843 14:48:10.082904 Final RX Vref Byte 1 = 56 to rank0
2844 14:48:10.086061 Final RX Vref Byte 0 = 54 to rank1
2845 14:48:10.089815 Final RX Vref Byte 1 = 56 to rank1==
2846 14:48:10.092921 Dram Type= 6, Freq= 0, CH_0, rank 0
2847 14:48:10.099332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 14:48:10.099411 ==
2849 14:48:10.099474 DQS Delay:
2850 14:48:10.099532 DQS0 = 0, DQS1 = 0
2851 14:48:10.103363 DQM Delay:
2852 14:48:10.103432 DQM0 = 120, DQM1 = 112
2853 14:48:10.106530 DQ Delay:
2854 14:48:10.109753 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2855 14:48:10.112806 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2856 14:48:10.115826 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2857 14:48:10.119754 DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =120
2858 14:48:10.119840
2859 14:48:10.119902
2860 14:48:10.129391 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2861 14:48:10.129473 CH0 RK0: MR19=404, MR18=1610
2862 14:48:10.136494 CH0_RK0: MR19=0x404, MR18=0x1610, DQSOSC=401, MR23=63, INC=40, DEC=27
2863 14:48:10.136590
2864 14:48:10.139790 ----->DramcWriteLeveling(PI) begin...
2865 14:48:10.139873 ==
2866 14:48:10.142764 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 14:48:10.149540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 14:48:10.149623 ==
2869 14:48:10.153249 Write leveling (Byte 0): 33 => 33
2870 14:48:10.153330 Write leveling (Byte 1): 29 => 29
2871 14:48:10.156126 DramcWriteLeveling(PI) end<-----
2872 14:48:10.156206
2873 14:48:10.156268 ==
2874 14:48:10.159423 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 14:48:10.166159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 14:48:10.166279 ==
2877 14:48:10.169208 [Gating] SW mode calibration
2878 14:48:10.175762 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2879 14:48:10.179516 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2880 14:48:10.185858 0 15 0 | B1->B0 | 3131 2f2f | 1 1 | (0 0) (1 1)
2881 14:48:10.189217 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 14:48:10.192517 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 14:48:10.199414 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 14:48:10.202553 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 14:48:10.205835 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 14:48:10.209105 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 14:48:10.216290 0 15 28 | B1->B0 | 3232 2e2e | 0 1 | (0 1) (1 0)
2888 14:48:10.219342 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2889 14:48:10.222457 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 14:48:10.229166 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 14:48:10.232991 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 14:48:10.236157 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 14:48:10.242595 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 14:48:10.245787 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2895 14:48:10.249239 1 0 28 | B1->B0 | 3535 3838 | 0 1 | (1 1) (0 0)
2896 14:48:10.256127 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 14:48:10.258957 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 14:48:10.262338 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 14:48:10.269188 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 14:48:10.272418 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 14:48:10.275793 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 14:48:10.282181 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2903 14:48:10.285653 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2904 14:48:10.289389 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2905 14:48:10.295628 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 14:48:10.299036 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 14:48:10.302440 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 14:48:10.308969 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 14:48:10.312163 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 14:48:10.316001 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 14:48:10.319559 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 14:48:10.325683 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 14:48:10.329357 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 14:48:10.332302 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 14:48:10.339493 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 14:48:10.342772 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 14:48:10.345991 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 14:48:10.352523 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2919 14:48:10.355693 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2920 14:48:10.359734 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2921 14:48:10.365779 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 14:48:10.365856 Total UI for P1: 0, mck2ui 16
2923 14:48:10.372640 best dqsien dly found for B0: ( 1, 3, 28)
2924 14:48:10.372716 Total UI for P1: 0, mck2ui 16
2925 14:48:10.375742 best dqsien dly found for B1: ( 1, 3, 28)
2926 14:48:10.382660 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2927 14:48:10.385956 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2928 14:48:10.386056
2929 14:48:10.389078 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2930 14:48:10.392772 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2931 14:48:10.395808 [Gating] SW calibration Done
2932 14:48:10.395905 ==
2933 14:48:10.399250 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 14:48:10.402503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 14:48:10.402605 ==
2936 14:48:10.406019 RX Vref Scan: 0
2937 14:48:10.406102
2938 14:48:10.406164 RX Vref 0 -> 0, step: 1
2939 14:48:10.406221
2940 14:48:10.409457 RX Delay -40 -> 252, step: 8
2941 14:48:10.412859 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2942 14:48:10.419345 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2943 14:48:10.422483 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2944 14:48:10.425737 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2945 14:48:10.429609 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2946 14:48:10.432690 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2947 14:48:10.436261 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2948 14:48:10.442459 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2949 14:48:10.446247 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2950 14:48:10.449534 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2951 14:48:10.452704 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2952 14:48:10.455937 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2953 14:48:10.462504 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2954 14:48:10.465840 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2955 14:48:10.469246 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2956 14:48:10.472899 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2957 14:48:10.473001 ==
2958 14:48:10.476102 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 14:48:10.482450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 14:48:10.482526 ==
2961 14:48:10.482602 DQS Delay:
2962 14:48:10.485628 DQS0 = 0, DQS1 = 0
2963 14:48:10.485699 DQM Delay:
2964 14:48:10.485759 DQM0 = 122, DQM1 = 113
2965 14:48:10.489790 DQ Delay:
2966 14:48:10.492863 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2967 14:48:10.496150 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2968 14:48:10.499456 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
2969 14:48:10.502716 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2970 14:48:10.502822
2971 14:48:10.502909
2972 14:48:10.503000 ==
2973 14:48:10.506027 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 14:48:10.509594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 14:48:10.509691 ==
2976 14:48:10.512522
2977 14:48:10.512592
2978 14:48:10.512650 TX Vref Scan disable
2979 14:48:10.515923 == TX Byte 0 ==
2980 14:48:10.519258 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2981 14:48:10.522604 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2982 14:48:10.526054 == TX Byte 1 ==
2983 14:48:10.529465 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2984 14:48:10.532891 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2985 14:48:10.532976 ==
2986 14:48:10.536282 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 14:48:10.542712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 14:48:10.542827 ==
2989 14:48:10.553828 TX Vref=22, minBit 12, minWin=24, winSum=411
2990 14:48:10.557082 TX Vref=24, minBit 3, minWin=25, winSum=416
2991 14:48:10.560191 TX Vref=26, minBit 13, minWin=25, winSum=421
2992 14:48:10.563509 TX Vref=28, minBit 0, minWin=26, winSum=424
2993 14:48:10.566725 TX Vref=30, minBit 12, minWin=25, winSum=423
2994 14:48:10.573675 TX Vref=32, minBit 12, minWin=25, winSum=420
2995 14:48:10.577362 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
2996 14:48:10.577464
2997 14:48:10.580431 Final TX Range 1 Vref 28
2998 14:48:10.580507
2999 14:48:10.580569 ==
3000 14:48:10.583623 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 14:48:10.586907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 14:48:10.590374 ==
3003 14:48:10.590475
3004 14:48:10.590572
3005 14:48:10.590661 TX Vref Scan disable
3006 14:48:10.593552 == TX Byte 0 ==
3007 14:48:10.596807 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3008 14:48:10.600767 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3009 14:48:10.603915 == TX Byte 1 ==
3010 14:48:10.607154 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3011 14:48:10.610380 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3012 14:48:10.613722
3013 14:48:10.613819 [DATLAT]
3014 14:48:10.613909 Freq=1200, CH0 RK1
3015 14:48:10.614005
3016 14:48:10.616939 DATLAT Default: 0xd
3017 14:48:10.617043 0, 0xFFFF, sum = 0
3018 14:48:10.620311 1, 0xFFFF, sum = 0
3019 14:48:10.620424 2, 0xFFFF, sum = 0
3020 14:48:10.624019 3, 0xFFFF, sum = 0
3021 14:48:10.624121 4, 0xFFFF, sum = 0
3022 14:48:10.627079 5, 0xFFFF, sum = 0
3023 14:48:10.630548 6, 0xFFFF, sum = 0
3024 14:48:10.630663 7, 0xFFFF, sum = 0
3025 14:48:10.633612 8, 0xFFFF, sum = 0
3026 14:48:10.633692 9, 0xFFFF, sum = 0
3027 14:48:10.637400 10, 0xFFFF, sum = 0
3028 14:48:10.637486 11, 0xFFFF, sum = 0
3029 14:48:10.640863 12, 0x0, sum = 1
3030 14:48:10.640981 13, 0x0, sum = 2
3031 14:48:10.643696 14, 0x0, sum = 3
3032 14:48:10.643808 15, 0x0, sum = 4
3033 14:48:10.643912 best_step = 13
3034 14:48:10.644001
3035 14:48:10.647509 ==
3036 14:48:10.647608 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 14:48:10.653861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 14:48:10.653947 ==
3039 14:48:10.654013 RX Vref Scan: 0
3040 14:48:10.654075
3041 14:48:10.657436 RX Vref 0 -> 0, step: 1
3042 14:48:10.657510
3043 14:48:10.660619 RX Delay -13 -> 252, step: 4
3044 14:48:10.664272 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3045 14:48:10.670950 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3046 14:48:10.674208 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3047 14:48:10.677523 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3048 14:48:10.680463 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3049 14:48:10.684082 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3050 14:48:10.687054 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3051 14:48:10.694078 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3052 14:48:10.697224 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3053 14:48:10.700911 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3054 14:48:10.704108 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3055 14:48:10.707551 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3056 14:48:10.714005 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3057 14:48:10.717283 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3058 14:48:10.720549 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3059 14:48:10.723834 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3060 14:48:10.723918 ==
3061 14:48:10.727656 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 14:48:10.734105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 14:48:10.734190 ==
3064 14:48:10.734256 DQS Delay:
3065 14:48:10.737232 DQS0 = 0, DQS1 = 0
3066 14:48:10.737317 DQM Delay:
3067 14:48:10.737383 DQM0 = 120, DQM1 = 111
3068 14:48:10.740767 DQ Delay:
3069 14:48:10.744605 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3070 14:48:10.747360 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3071 14:48:10.751014 DQ8 =102, DQ9 =100, DQ10 =112, DQ11 =104
3072 14:48:10.754026 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =118
3073 14:48:10.754123
3074 14:48:10.754203
3075 14:48:10.761211 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3076 14:48:10.764249 CH0 RK1: MR19=403, MR18=11F2
3077 14:48:10.771040 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3078 14:48:10.774544 [RxdqsGatingPostProcess] freq 1200
3079 14:48:10.780685 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3080 14:48:10.784672 best DQS0 dly(2T, 0.5T) = (0, 11)
3081 14:48:10.787679 best DQS1 dly(2T, 0.5T) = (0, 12)
3082 14:48:10.790596 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3083 14:48:10.790673 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3084 14:48:10.793914 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 14:48:10.797241 best DQS1 dly(2T, 0.5T) = (0, 11)
3086 14:48:10.801003 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 14:48:10.803876 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3088 14:48:10.807508 Pre-setting of DQS Precalculation
3089 14:48:10.814212 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3090 14:48:10.814297 ==
3091 14:48:10.817266 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 14:48:10.820581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 14:48:10.820666 ==
3094 14:48:10.827157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 14:48:10.830878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3096 14:48:10.840550 [CA 0] Center 37 (7~68) winsize 62
3097 14:48:10.843747 [CA 1] Center 37 (7~68) winsize 62
3098 14:48:10.847681 [CA 2] Center 35 (5~65) winsize 61
3099 14:48:10.850475 [CA 3] Center 34 (4~64) winsize 61
3100 14:48:10.854389 [CA 4] Center 34 (4~64) winsize 61
3101 14:48:10.857241 [CA 5] Center 33 (3~64) winsize 62
3102 14:48:10.857326
3103 14:48:10.860649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 14:48:10.860733
3105 14:48:10.863777 [CATrainingPosCal] consider 1 rank data
3106 14:48:10.867811 u2DelayCellTimex100 = 270/100 ps
3107 14:48:10.870639 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3108 14:48:10.874278 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 14:48:10.877310 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3110 14:48:10.884215 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3111 14:48:10.887395 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 14:48:10.890481 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3113 14:48:10.890564
3114 14:48:10.894096 CA PerBit enable=1, Macro0, CA PI delay=33
3115 14:48:10.894178
3116 14:48:10.897718 [CBTSetCACLKResult] CA Dly = 33
3117 14:48:10.897800 CS Dly: 7 (0~38)
3118 14:48:10.897864 ==
3119 14:48:10.900482 Dram Type= 6, Freq= 0, CH_1, rank 1
3120 14:48:10.907494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 14:48:10.907579 ==
3122 14:48:10.910745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 14:48:10.917368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3124 14:48:10.926409 [CA 0] Center 37 (7~68) winsize 62
3125 14:48:10.929690 [CA 1] Center 38 (8~68) winsize 61
3126 14:48:10.932848 [CA 2] Center 35 (5~65) winsize 61
3127 14:48:10.936232 [CA 3] Center 34 (4~65) winsize 62
3128 14:48:10.939457 [CA 4] Center 34 (4~65) winsize 62
3129 14:48:10.942724 [CA 5] Center 33 (3~63) winsize 61
3130 14:48:10.942806
3131 14:48:10.945968 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3132 14:48:10.946050
3133 14:48:10.949772 [CATrainingPosCal] consider 2 rank data
3134 14:48:10.952930 u2DelayCellTimex100 = 270/100 ps
3135 14:48:10.956132 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3136 14:48:10.960047 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3137 14:48:10.966505 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3138 14:48:10.969758 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3139 14:48:10.972933 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3140 14:48:10.976598 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3141 14:48:10.976680
3142 14:48:10.979834 CA PerBit enable=1, Macro0, CA PI delay=33
3143 14:48:10.979919
3144 14:48:10.983067 [CBTSetCACLKResult] CA Dly = 33
3145 14:48:10.983149 CS Dly: 8 (0~40)
3146 14:48:10.983217
3147 14:48:10.986256 ----->DramcWriteLeveling(PI) begin...
3148 14:48:10.986341 ==
3149 14:48:10.989898 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 14:48:10.996616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 14:48:10.996700 ==
3152 14:48:10.999671 Write leveling (Byte 0): 27 => 27
3153 14:48:11.003273 Write leveling (Byte 1): 29 => 29
3154 14:48:11.003355 DramcWriteLeveling(PI) end<-----
3155 14:48:11.003419
3156 14:48:11.006266 ==
3157 14:48:11.010098 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 14:48:11.013112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 14:48:11.013211 ==
3160 14:48:11.016659 [Gating] SW mode calibration
3161 14:48:11.023176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3162 14:48:11.026246 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3163 14:48:11.033417 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 14:48:11.036654 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 14:48:11.039987 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 14:48:11.046488 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 14:48:11.049759 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 14:48:11.053549 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 14:48:11.059907 0 15 24 | B1->B0 | 3131 2929 | 1 0 | (1 0) (0 1)
3170 14:48:11.063372 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3171 14:48:11.066400 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 14:48:11.070171 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 14:48:11.076732 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 14:48:11.079732 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 14:48:11.083346 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 14:48:11.090249 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 14:48:11.093411 1 0 24 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
3178 14:48:11.096306 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 14:48:11.103185 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 14:48:11.106465 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 14:48:11.110298 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 14:48:11.116755 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 14:48:11.120086 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 14:48:11.123769 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 14:48:11.129730 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3186 14:48:11.133520 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3187 14:48:11.136793 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 14:48:11.143125 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 14:48:11.146846 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 14:48:11.150120 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 14:48:11.153369 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 14:48:11.160521 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 14:48:11.163662 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 14:48:11.166972 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 14:48:11.173497 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 14:48:11.176865 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 14:48:11.180126 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 14:48:11.186929 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 14:48:11.190375 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 14:48:11.193829 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 14:48:11.200194 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3202 14:48:11.203714 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3203 14:48:11.206685 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 14:48:11.210378 Total UI for P1: 0, mck2ui 16
3205 14:48:11.213614 best dqsien dly found for B0: ( 1, 3, 26)
3206 14:48:11.216815 Total UI for P1: 0, mck2ui 16
3207 14:48:11.220052 best dqsien dly found for B1: ( 1, 3, 26)
3208 14:48:11.223692 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3209 14:48:11.227251 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3210 14:48:11.227398
3211 14:48:11.230545 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3212 14:48:11.236899 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3213 14:48:11.236979 [Gating] SW calibration Done
3214 14:48:11.237048 ==
3215 14:48:11.240447 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 14:48:11.246645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 14:48:11.246728 ==
3218 14:48:11.246793 RX Vref Scan: 0
3219 14:48:11.246853
3220 14:48:11.250485 RX Vref 0 -> 0, step: 1
3221 14:48:11.250559
3222 14:48:11.253374 RX Delay -40 -> 252, step: 8
3223 14:48:11.256987 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3224 14:48:11.260315 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3225 14:48:11.263244 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3226 14:48:11.269755 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3227 14:48:11.273571 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3228 14:48:11.276872 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3229 14:48:11.280249 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3230 14:48:11.283346 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3231 14:48:11.289818 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3232 14:48:11.293534 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3233 14:48:11.296616 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3234 14:48:11.299674 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3235 14:48:11.303143 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3236 14:48:11.310182 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3237 14:48:11.313468 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3238 14:48:11.316573 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3239 14:48:11.316649 ==
3240 14:48:11.320019 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 14:48:11.323256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 14:48:11.323343 ==
3243 14:48:11.326567 DQS Delay:
3244 14:48:11.326644 DQS0 = 0, DQS1 = 0
3245 14:48:11.330305 DQM Delay:
3246 14:48:11.330380 DQM0 = 120, DQM1 = 116
3247 14:48:11.330444 DQ Delay:
3248 14:48:11.336879 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3249 14:48:11.340176 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3250 14:48:11.343568 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3251 14:48:11.346420 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3252 14:48:11.346505
3253 14:48:11.346570
3254 14:48:11.346631 ==
3255 14:48:11.350063 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 14:48:11.353164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 14:48:11.353248 ==
3258 14:48:11.353313
3259 14:48:11.353374
3260 14:48:11.356816 TX Vref Scan disable
3261 14:48:11.360048 == TX Byte 0 ==
3262 14:48:11.363605 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3263 14:48:11.366420 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3264 14:48:11.370071 == TX Byte 1 ==
3265 14:48:11.373563 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3266 14:48:11.376845 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3267 14:48:11.376930 ==
3268 14:48:11.380075 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 14:48:11.383274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 14:48:11.386497 ==
3271 14:48:11.396643 TX Vref=22, minBit 9, minWin=24, winSum=411
3272 14:48:11.399815 TX Vref=24, minBit 9, minWin=24, winSum=414
3273 14:48:11.403020 TX Vref=26, minBit 0, minWin=26, winSum=427
3274 14:48:11.406786 TX Vref=28, minBit 1, minWin=26, winSum=426
3275 14:48:11.409903 TX Vref=30, minBit 1, minWin=26, winSum=430
3276 14:48:11.413293 TX Vref=32, minBit 10, minWin=25, winSum=429
3277 14:48:11.420196 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3278 14:48:11.420282
3279 14:48:11.422985 Final TX Range 1 Vref 30
3280 14:48:11.423069
3281 14:48:11.423134 ==
3282 14:48:11.426469 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 14:48:11.430010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 14:48:11.430094 ==
3285 14:48:11.430160
3286 14:48:11.433146
3287 14:48:11.433230 TX Vref Scan disable
3288 14:48:11.436561 == TX Byte 0 ==
3289 14:48:11.440062 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3290 14:48:11.443305 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3291 14:48:11.446545 == TX Byte 1 ==
3292 14:48:11.449945 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3293 14:48:11.453414 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3294 14:48:11.453498
3295 14:48:11.456890 [DATLAT]
3296 14:48:11.456974 Freq=1200, CH1 RK0
3297 14:48:11.457041
3298 14:48:11.459932 DATLAT Default: 0xd
3299 14:48:11.460015 0, 0xFFFF, sum = 0
3300 14:48:11.463201 1, 0xFFFF, sum = 0
3301 14:48:11.463287 2, 0xFFFF, sum = 0
3302 14:48:11.466603 3, 0xFFFF, sum = 0
3303 14:48:11.466701 4, 0xFFFF, sum = 0
3304 14:48:11.470292 5, 0xFFFF, sum = 0
3305 14:48:11.470376 6, 0xFFFF, sum = 0
3306 14:48:11.473519 7, 0xFFFF, sum = 0
3307 14:48:11.473603 8, 0xFFFF, sum = 0
3308 14:48:11.476499 9, 0xFFFF, sum = 0
3309 14:48:11.476583 10, 0xFFFF, sum = 0
3310 14:48:11.480197 11, 0xFFFF, sum = 0
3311 14:48:11.480280 12, 0x0, sum = 1
3312 14:48:11.483530 13, 0x0, sum = 2
3313 14:48:11.483680 14, 0x0, sum = 3
3314 14:48:11.486595 15, 0x0, sum = 4
3315 14:48:11.486678 best_step = 13
3316 14:48:11.486742
3317 14:48:11.486802 ==
3318 14:48:11.489856 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 14:48:11.496464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 14:48:11.496548 ==
3321 14:48:11.496612 RX Vref Scan: 1
3322 14:48:11.496672
3323 14:48:11.500366 Set Vref Range= 32 -> 127
3324 14:48:11.500463
3325 14:48:11.503582 RX Vref 32 -> 127, step: 1
3326 14:48:11.503695
3327 14:48:11.506876 RX Delay -5 -> 252, step: 4
3328 14:48:11.506959
3329 14:48:11.507024 Set Vref, RX VrefLevel [Byte0]: 32
3330 14:48:11.510168 [Byte1]: 32
3331 14:48:11.514490
3332 14:48:11.514571 Set Vref, RX VrefLevel [Byte0]: 33
3333 14:48:11.517799 [Byte1]: 33
3334 14:48:11.522414
3335 14:48:11.522495 Set Vref, RX VrefLevel [Byte0]: 34
3336 14:48:11.525588 [Byte1]: 34
3337 14:48:11.530342
3338 14:48:11.530422 Set Vref, RX VrefLevel [Byte0]: 35
3339 14:48:11.533552 [Byte1]: 35
3340 14:48:11.538012
3341 14:48:11.538094 Set Vref, RX VrefLevel [Byte0]: 36
3342 14:48:11.541672 [Byte1]: 36
3343 14:48:11.545808
3344 14:48:11.545889 Set Vref, RX VrefLevel [Byte0]: 37
3345 14:48:11.549305 [Byte1]: 37
3346 14:48:11.553816
3347 14:48:11.553898 Set Vref, RX VrefLevel [Byte0]: 38
3348 14:48:11.556958 [Byte1]: 38
3349 14:48:11.561763
3350 14:48:11.561847 Set Vref, RX VrefLevel [Byte0]: 39
3351 14:48:11.565148 [Byte1]: 39
3352 14:48:11.569457
3353 14:48:11.569600 Set Vref, RX VrefLevel [Byte0]: 40
3354 14:48:11.573018 [Byte1]: 40
3355 14:48:11.577545
3356 14:48:11.577627 Set Vref, RX VrefLevel [Byte0]: 41
3357 14:48:11.580946 [Byte1]: 41
3358 14:48:11.585378
3359 14:48:11.585459 Set Vref, RX VrefLevel [Byte0]: 42
3360 14:48:11.588569 [Byte1]: 42
3361 14:48:11.592894
3362 14:48:11.596449 Set Vref, RX VrefLevel [Byte0]: 43
3363 14:48:11.596531 [Byte1]: 43
3364 14:48:11.601360
3365 14:48:11.601446 Set Vref, RX VrefLevel [Byte0]: 44
3366 14:48:11.604616 [Byte1]: 44
3367 14:48:11.609239
3368 14:48:11.609319 Set Vref, RX VrefLevel [Byte0]: 45
3369 14:48:11.612487 [Byte1]: 45
3370 14:48:11.616653
3371 14:48:11.616734 Set Vref, RX VrefLevel [Byte0]: 46
3372 14:48:11.620279 [Byte1]: 46
3373 14:48:11.624849
3374 14:48:11.624929 Set Vref, RX VrefLevel [Byte0]: 47
3375 14:48:11.628102 [Byte1]: 47
3376 14:48:11.632565
3377 14:48:11.632644 Set Vref, RX VrefLevel [Byte0]: 48
3378 14:48:11.635788 [Byte1]: 48
3379 14:48:11.640265
3380 14:48:11.640369 Set Vref, RX VrefLevel [Byte0]: 49
3381 14:48:11.643484 [Byte1]: 49
3382 14:48:11.647900
3383 14:48:11.647980 Set Vref, RX VrefLevel [Byte0]: 50
3384 14:48:11.651281 [Byte1]: 50
3385 14:48:11.656112
3386 14:48:11.656191 Set Vref, RX VrefLevel [Byte0]: 51
3387 14:48:11.662687 [Byte1]: 51
3388 14:48:11.662768
3389 14:48:11.665569 Set Vref, RX VrefLevel [Byte0]: 52
3390 14:48:11.669326 [Byte1]: 52
3391 14:48:11.669407
3392 14:48:11.672659 Set Vref, RX VrefLevel [Byte0]: 53
3393 14:48:11.675852 [Byte1]: 53
3394 14:48:11.679509
3395 14:48:11.679590 Set Vref, RX VrefLevel [Byte0]: 54
3396 14:48:11.683018 [Byte1]: 54
3397 14:48:11.687367
3398 14:48:11.687447 Set Vref, RX VrefLevel [Byte0]: 55
3399 14:48:11.690418 [Byte1]: 55
3400 14:48:11.695297
3401 14:48:11.695387 Set Vref, RX VrefLevel [Byte0]: 56
3402 14:48:11.698382 [Byte1]: 56
3403 14:48:11.702716
3404 14:48:11.702796 Set Vref, RX VrefLevel [Byte0]: 57
3405 14:48:11.706338 [Byte1]: 57
3406 14:48:11.710868
3407 14:48:11.710948 Set Vref, RX VrefLevel [Byte0]: 58
3408 14:48:11.714336 [Byte1]: 58
3409 14:48:11.718667
3410 14:48:11.718747 Set Vref, RX VrefLevel [Byte0]: 59
3411 14:48:11.722158 [Byte1]: 59
3412 14:48:11.726644
3413 14:48:11.726751 Set Vref, RX VrefLevel [Byte0]: 60
3414 14:48:11.729888 [Byte1]: 60
3415 14:48:11.734622
3416 14:48:11.734696 Set Vref, RX VrefLevel [Byte0]: 61
3417 14:48:11.737579 [Byte1]: 61
3418 14:48:11.742349
3419 14:48:11.742421 Set Vref, RX VrefLevel [Byte0]: 62
3420 14:48:11.745490 [Byte1]: 62
3421 14:48:11.749922
3422 14:48:11.749992 Set Vref, RX VrefLevel [Byte0]: 63
3423 14:48:11.753112 [Byte1]: 63
3424 14:48:11.757720
3425 14:48:11.761034 Set Vref, RX VrefLevel [Byte0]: 64
3426 14:48:11.764180 [Byte1]: 64
3427 14:48:11.764260
3428 14:48:11.768043 Set Vref, RX VrefLevel [Byte0]: 65
3429 14:48:11.771016 [Byte1]: 65
3430 14:48:11.771096
3431 14:48:11.774385 Set Vref, RX VrefLevel [Byte0]: 66
3432 14:48:11.777591 [Byte1]: 66
3433 14:48:11.781385
3434 14:48:11.781465 Set Vref, RX VrefLevel [Byte0]: 67
3435 14:48:11.785048 [Byte1]: 67
3436 14:48:11.789921
3437 14:48:11.790001 Final RX Vref Byte 0 = 56 to rank0
3438 14:48:11.792826 Final RX Vref Byte 1 = 55 to rank0
3439 14:48:11.796063 Final RX Vref Byte 0 = 56 to rank1
3440 14:48:11.799261 Final RX Vref Byte 1 = 55 to rank1==
3441 14:48:11.802909 Dram Type= 6, Freq= 0, CH_1, rank 0
3442 14:48:11.809611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 14:48:11.809693 ==
3444 14:48:11.809757 DQS Delay:
3445 14:48:11.809816 DQS0 = 0, DQS1 = 0
3446 14:48:11.813102 DQM Delay:
3447 14:48:11.813170 DQM0 = 120, DQM1 = 117
3448 14:48:11.816099 DQ Delay:
3449 14:48:11.819646 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3450 14:48:11.822792 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3451 14:48:11.826220 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3452 14:48:11.829332 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3453 14:48:11.829404
3454 14:48:11.829463
3455 14:48:11.836351 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3456 14:48:11.839611 CH1 RK0: MR19=404, MR18=114
3457 14:48:11.846345 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3458 14:48:11.846448
3459 14:48:11.849408 ----->DramcWriteLeveling(PI) begin...
3460 14:48:11.849484 ==
3461 14:48:11.853212 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 14:48:11.856524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 14:48:11.856608 ==
3464 14:48:11.859818 Write leveling (Byte 0): 25 => 25
3465 14:48:11.863108 Write leveling (Byte 1): 28 => 28
3466 14:48:11.866436 DramcWriteLeveling(PI) end<-----
3467 14:48:11.866518
3468 14:48:11.866582 ==
3469 14:48:11.869708 Dram Type= 6, Freq= 0, CH_1, rank 1
3470 14:48:11.872955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 14:48:11.876683 ==
3472 14:48:11.876765 [Gating] SW mode calibration
3473 14:48:11.883111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3474 14:48:11.889905 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3475 14:48:11.893138 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3476 14:48:11.899591 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 14:48:11.902923 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 14:48:11.906275 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 14:48:11.913570 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 14:48:11.916494 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3481 14:48:11.919932 0 15 24 | B1->B0 | 2828 3131 | 0 1 | (0 0) (1 0)
3482 14:48:11.945860 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 14:48:11.945995 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 14:48:11.946064 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 14:48:11.946132 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 14:48:11.946191 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 14:48:11.946438 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 14:48:11.949712 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3489 14:48:11.956271 1 0 24 | B1->B0 | 4545 2626 | 0 0 | (0 0) (0 0)
3490 14:48:11.959300 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 14:48:11.962741 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 14:48:11.969364 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 14:48:11.972764 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 14:48:11.976086 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 14:48:11.982695 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 14:48:11.985936 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3497 14:48:11.989153 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3498 14:48:11.996355 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3499 14:48:11.999367 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 14:48:12.002440 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 14:48:12.009916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 14:48:12.012891 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 14:48:12.016125 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 14:48:12.022525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 14:48:12.025875 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 14:48:12.029051 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 14:48:12.036188 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 14:48:12.039462 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 14:48:12.042627 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 14:48:12.049137 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 14:48:12.052687 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 14:48:12.055953 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3513 14:48:12.062305 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3514 14:48:12.065768 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 14:48:12.068877 Total UI for P1: 0, mck2ui 16
3516 14:48:12.072470 best dqsien dly found for B0: ( 1, 3, 24)
3517 14:48:12.076073 Total UI for P1: 0, mck2ui 16
3518 14:48:12.078887 best dqsien dly found for B1: ( 1, 3, 22)
3519 14:48:12.082377 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3520 14:48:12.085831 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3521 14:48:12.085938
3522 14:48:12.089220 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3523 14:48:12.092279 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3524 14:48:12.095787 [Gating] SW calibration Done
3525 14:48:12.095872 ==
3526 14:48:12.099016 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 14:48:12.102047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 14:48:12.102133 ==
3529 14:48:12.105602 RX Vref Scan: 0
3530 14:48:12.105688
3531 14:48:12.108659 RX Vref 0 -> 0, step: 1
3532 14:48:12.108790
3533 14:48:12.108890 RX Delay -40 -> 252, step: 8
3534 14:48:12.115266 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3535 14:48:12.118811 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3536 14:48:12.121791 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3537 14:48:12.125580 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3538 14:48:12.132207 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3539 14:48:12.135479 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3540 14:48:12.138720 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3541 14:48:12.141969 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3542 14:48:12.145085 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3543 14:48:12.148315 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3544 14:48:12.155493 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3545 14:48:12.158481 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3546 14:48:12.161681 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3547 14:48:12.165480 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3548 14:48:12.171966 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3549 14:48:12.175267 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3550 14:48:12.175353 ==
3551 14:48:12.178291 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 14:48:12.182420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 14:48:12.182531 ==
3554 14:48:12.182624 DQS Delay:
3555 14:48:12.185399 DQS0 = 0, DQS1 = 0
3556 14:48:12.185511 DQM Delay:
3557 14:48:12.188785 DQM0 = 120, DQM1 = 117
3558 14:48:12.188869 DQ Delay:
3559 14:48:12.192196 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3560 14:48:12.195009 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3561 14:48:12.198296 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3562 14:48:12.205338 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3563 14:48:12.205449
3564 14:48:12.205517
3565 14:48:12.205578 ==
3566 14:48:12.208393 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 14:48:12.211932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 14:48:12.212044 ==
3569 14:48:12.212146
3570 14:48:12.212247
3571 14:48:12.214949 TX Vref Scan disable
3572 14:48:12.215032 == TX Byte 0 ==
3573 14:48:12.222062 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3574 14:48:12.224918 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3575 14:48:12.225015 == TX Byte 1 ==
3576 14:48:12.232009 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 14:48:12.234614 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 14:48:12.234701 ==
3579 14:48:12.238163 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 14:48:12.241362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 14:48:12.241448 ==
3582 14:48:12.254481 TX Vref=22, minBit 0, minWin=26, winSum=421
3583 14:48:12.257755 TX Vref=24, minBit 10, minWin=25, winSum=422
3584 14:48:12.260977 TX Vref=26, minBit 10, minWin=25, winSum=427
3585 14:48:12.264116 TX Vref=28, minBit 9, minWin=26, winSum=433
3586 14:48:12.267378 TX Vref=30, minBit 9, minWin=26, winSum=435
3587 14:48:12.273856 TX Vref=32, minBit 9, minWin=26, winSum=438
3588 14:48:12.277889 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 32
3589 14:48:12.277973
3590 14:48:12.280881 Final TX Range 1 Vref 32
3591 14:48:12.280964
3592 14:48:12.281028 ==
3593 14:48:12.284183 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 14:48:12.287633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 14:48:12.290678 ==
3596 14:48:12.290760
3597 14:48:12.290825
3598 14:48:12.290883 TX Vref Scan disable
3599 14:48:12.293827 == TX Byte 0 ==
3600 14:48:12.297724 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3601 14:48:12.303989 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3602 14:48:12.304098 == TX Byte 1 ==
3603 14:48:12.307350 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3604 14:48:12.314116 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3605 14:48:12.314241
3606 14:48:12.314367 [DATLAT]
3607 14:48:12.314470 Freq=1200, CH1 RK1
3608 14:48:12.314636
3609 14:48:12.317147 DATLAT Default: 0xd
3610 14:48:12.317228 0, 0xFFFF, sum = 0
3611 14:48:12.320661 1, 0xFFFF, sum = 0
3612 14:48:12.323616 2, 0xFFFF, sum = 0
3613 14:48:12.323709 3, 0xFFFF, sum = 0
3614 14:48:12.326907 4, 0xFFFF, sum = 0
3615 14:48:12.327024 5, 0xFFFF, sum = 0
3616 14:48:12.330818 6, 0xFFFF, sum = 0
3617 14:48:12.330942 7, 0xFFFF, sum = 0
3618 14:48:12.334033 8, 0xFFFF, sum = 0
3619 14:48:12.334166 9, 0xFFFF, sum = 0
3620 14:48:12.337336 10, 0xFFFF, sum = 0
3621 14:48:12.337450 11, 0xFFFF, sum = 0
3622 14:48:12.340550 12, 0x0, sum = 1
3623 14:48:12.340661 13, 0x0, sum = 2
3624 14:48:12.343668 14, 0x0, sum = 3
3625 14:48:12.343779 15, 0x0, sum = 4
3626 14:48:12.347311 best_step = 13
3627 14:48:12.347423
3628 14:48:12.347522 ==
3629 14:48:12.350493 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 14:48:12.353627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 14:48:12.353717 ==
3632 14:48:12.353782 RX Vref Scan: 0
3633 14:48:12.357150
3634 14:48:12.357240 RX Vref 0 -> 0, step: 1
3635 14:48:12.357306
3636 14:48:12.360217 RX Delay -5 -> 252, step: 4
3637 14:48:12.363573 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3638 14:48:12.370324 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3639 14:48:12.373650 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3640 14:48:12.377102 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3641 14:48:12.380087 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3642 14:48:12.383479 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3643 14:48:12.390415 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3644 14:48:12.393691 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3645 14:48:12.396860 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3646 14:48:12.400084 iDelay=195, Bit 9, Center 110 (51 ~ 170) 120
3647 14:48:12.403494 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3648 14:48:12.410500 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3649 14:48:12.413347 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3650 14:48:12.416714 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3651 14:48:12.420305 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3652 14:48:12.423394 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3653 14:48:12.427134 ==
3654 14:48:12.430264 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 14:48:12.433920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 14:48:12.434021 ==
3657 14:48:12.434086 DQS Delay:
3658 14:48:12.437180 DQS0 = 0, DQS1 = 0
3659 14:48:12.437272 DQM Delay:
3660 14:48:12.440457 DQM0 = 120, DQM1 = 118
3661 14:48:12.440560 DQ Delay:
3662 14:48:12.443593 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3663 14:48:12.447068 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3664 14:48:12.450283 DQ8 =106, DQ9 =110, DQ10 =118, DQ11 =112
3665 14:48:12.453260 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3666 14:48:12.453380
3667 14:48:12.453455
3668 14:48:12.463430 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3669 14:48:12.466464 CH1 RK1: MR19=403, MR18=12EE
3670 14:48:12.470096 CH1_RK1: MR19=0x403, MR18=0x12EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3671 14:48:12.473174 [RxdqsGatingPostProcess] freq 1200
3672 14:48:12.479780 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3673 14:48:12.483202 best DQS0 dly(2T, 0.5T) = (0, 11)
3674 14:48:12.486229 best DQS1 dly(2T, 0.5T) = (0, 11)
3675 14:48:12.489777 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3676 14:48:12.493141 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3677 14:48:12.496386 best DQS0 dly(2T, 0.5T) = (0, 11)
3678 14:48:12.499462 best DQS1 dly(2T, 0.5T) = (0, 11)
3679 14:48:12.502943 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3680 14:48:12.505989 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3681 14:48:12.509236 Pre-setting of DQS Precalculation
3682 14:48:12.513164 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3683 14:48:12.519681 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3684 14:48:12.526021 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3685 14:48:12.529606
3686 14:48:12.529742
3687 14:48:12.529813 [Calibration Summary] 2400 Mbps
3688 14:48:12.532679 CH 0, Rank 0
3689 14:48:12.532798 SW Impedance : PASS
3690 14:48:12.536240 DUTY Scan : NO K
3691 14:48:12.539248 ZQ Calibration : PASS
3692 14:48:12.539337 Jitter Meter : NO K
3693 14:48:12.542569 CBT Training : PASS
3694 14:48:12.545736 Write leveling : PASS
3695 14:48:12.545830 RX DQS gating : PASS
3696 14:48:12.549034 RX DQ/DQS(RDDQC) : PASS
3697 14:48:12.552333 TX DQ/DQS : PASS
3698 14:48:12.552430 RX DATLAT : PASS
3699 14:48:12.556243 RX DQ/DQS(Engine): PASS
3700 14:48:12.559486 TX OE : NO K
3701 14:48:12.559570 All Pass.
3702 14:48:12.559636
3703 14:48:12.559703 CH 0, Rank 1
3704 14:48:12.562587 SW Impedance : PASS
3705 14:48:12.565781 DUTY Scan : NO K
3706 14:48:12.565890 ZQ Calibration : PASS
3707 14:48:12.568915 Jitter Meter : NO K
3708 14:48:12.572763 CBT Training : PASS
3709 14:48:12.572939 Write leveling : PASS
3710 14:48:12.575960 RX DQS gating : PASS
3711 14:48:12.579025 RX DQ/DQS(RDDQC) : PASS
3712 14:48:12.579165 TX DQ/DQS : PASS
3713 14:48:12.582814 RX DATLAT : PASS
3714 14:48:12.582951 RX DQ/DQS(Engine): PASS
3715 14:48:12.586057 TX OE : NO K
3716 14:48:12.586173 All Pass.
3717 14:48:12.586267
3718 14:48:12.589382 CH 1, Rank 0
3719 14:48:12.589493 SW Impedance : PASS
3720 14:48:12.592371 DUTY Scan : NO K
3721 14:48:12.595500 ZQ Calibration : PASS
3722 14:48:12.595636 Jitter Meter : NO K
3723 14:48:12.598876 CBT Training : PASS
3724 14:48:12.602198 Write leveling : PASS
3725 14:48:12.602338 RX DQS gating : PASS
3726 14:48:12.605375 RX DQ/DQS(RDDQC) : PASS
3727 14:48:12.608721 TX DQ/DQS : PASS
3728 14:48:12.608837 RX DATLAT : PASS
3729 14:48:12.612074 RX DQ/DQS(Engine): PASS
3730 14:48:12.615607 TX OE : NO K
3731 14:48:12.615772 All Pass.
3732 14:48:12.615899
3733 14:48:12.616022 CH 1, Rank 1
3734 14:48:12.618822 SW Impedance : PASS
3735 14:48:12.622712 DUTY Scan : NO K
3736 14:48:12.622874 ZQ Calibration : PASS
3737 14:48:12.625879 Jitter Meter : NO K
3738 14:48:12.629032 CBT Training : PASS
3739 14:48:12.629169 Write leveling : PASS
3740 14:48:12.631989 RX DQS gating : PASS
3741 14:48:12.632097 RX DQ/DQS(RDDQC) : PASS
3742 14:48:12.635398 TX DQ/DQS : PASS
3743 14:48:12.639000 RX DATLAT : PASS
3744 14:48:12.639115 RX DQ/DQS(Engine): PASS
3745 14:48:12.642008 TX OE : NO K
3746 14:48:12.642113 All Pass.
3747 14:48:12.642210
3748 14:48:12.645358 DramC Write-DBI off
3749 14:48:12.648976 PER_BANK_REFRESH: Hybrid Mode
3750 14:48:12.649098 TX_TRACKING: ON
3751 14:48:12.659053 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3752 14:48:12.662294 [FAST_K] Save calibration result to emmc
3753 14:48:12.665609 dramc_set_vcore_voltage set vcore to 650000
3754 14:48:12.668878 Read voltage for 600, 5
3755 14:48:12.668972 Vio18 = 0
3756 14:48:12.669070 Vcore = 650000
3757 14:48:12.672069 Vdram = 0
3758 14:48:12.672183 Vddq = 0
3759 14:48:12.672280 Vmddr = 0
3760 14:48:12.679140 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3761 14:48:12.682340 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3762 14:48:12.685461 MEM_TYPE=3, freq_sel=19
3763 14:48:12.688685 sv_algorithm_assistance_LP4_1600
3764 14:48:12.691907 ============ PULL DRAM RESETB DOWN ============
3765 14:48:12.699168 ========== PULL DRAM RESETB DOWN end =========
3766 14:48:12.702138 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3767 14:48:12.705542 ===================================
3768 14:48:12.708638 LPDDR4 DRAM CONFIGURATION
3769 14:48:12.711814 ===================================
3770 14:48:12.711922 EX_ROW_EN[0] = 0x0
3771 14:48:12.715120 EX_ROW_EN[1] = 0x0
3772 14:48:12.715222 LP4Y_EN = 0x0
3773 14:48:12.718994 WORK_FSP = 0x0
3774 14:48:12.719098 WL = 0x2
3775 14:48:12.722112 RL = 0x2
3776 14:48:12.722213 BL = 0x2
3777 14:48:12.725765 RPST = 0x0
3778 14:48:12.725870 RD_PRE = 0x0
3779 14:48:12.728646 WR_PRE = 0x1
3780 14:48:12.728725 WR_PST = 0x0
3781 14:48:12.731842 DBI_WR = 0x0
3782 14:48:12.731946 DBI_RD = 0x0
3783 14:48:12.735338 OTF = 0x1
3784 14:48:12.739113 ===================================
3785 14:48:12.741949 ===================================
3786 14:48:12.742057 ANA top config
3787 14:48:12.745366 ===================================
3788 14:48:12.748443 DLL_ASYNC_EN = 0
3789 14:48:12.752184 ALL_SLAVE_EN = 1
3790 14:48:12.755115 NEW_RANK_MODE = 1
3791 14:48:12.755220 DLL_IDLE_MODE = 1
3792 14:48:12.758513 LP45_APHY_COMB_EN = 1
3793 14:48:12.762013 TX_ODT_DIS = 1
3794 14:48:12.765419 NEW_8X_MODE = 1
3795 14:48:12.768488 ===================================
3796 14:48:12.771854 ===================================
3797 14:48:12.775089 data_rate = 1200
3798 14:48:12.775202 CKR = 1
3799 14:48:12.778281 DQ_P2S_RATIO = 8
3800 14:48:12.781496 ===================================
3801 14:48:12.785443 CA_P2S_RATIO = 8
3802 14:48:12.788807 DQ_CA_OPEN = 0
3803 14:48:12.791935 DQ_SEMI_OPEN = 0
3804 14:48:12.794861 CA_SEMI_OPEN = 0
3805 14:48:12.794969 CA_FULL_RATE = 0
3806 14:48:12.798424 DQ_CKDIV4_EN = 1
3807 14:48:12.801526 CA_CKDIV4_EN = 1
3808 14:48:12.805296 CA_PREDIV_EN = 0
3809 14:48:12.808132 PH8_DLY = 0
3810 14:48:12.812170 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3811 14:48:12.812254 DQ_AAMCK_DIV = 4
3812 14:48:12.815242 CA_AAMCK_DIV = 4
3813 14:48:12.818543 CA_ADMCK_DIV = 4
3814 14:48:12.821686 DQ_TRACK_CA_EN = 0
3815 14:48:12.825049 CA_PICK = 600
3816 14:48:12.828183 CA_MCKIO = 600
3817 14:48:12.831446 MCKIO_SEMI = 0
3818 14:48:12.831542 PLL_FREQ = 2288
3819 14:48:12.835247 DQ_UI_PI_RATIO = 32
3820 14:48:12.838316 CA_UI_PI_RATIO = 0
3821 14:48:12.841309 ===================================
3822 14:48:12.844792 ===================================
3823 14:48:12.847973 memory_type:LPDDR4
3824 14:48:12.848102 GP_NUM : 10
3825 14:48:12.851425 SRAM_EN : 1
3826 14:48:12.854797 MD32_EN : 0
3827 14:48:12.857897 ===================================
3828 14:48:12.858024 [ANA_INIT] >>>>>>>>>>>>>>
3829 14:48:12.861514 <<<<<< [CONFIGURE PHASE]: ANA_TX
3830 14:48:12.865033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3831 14:48:12.867946 ===================================
3832 14:48:12.871438 data_rate = 1200,PCW = 0X5800
3833 14:48:12.874891 ===================================
3834 14:48:12.877806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3835 14:48:12.885040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 14:48:12.888191 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3837 14:48:12.894750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3838 14:48:12.897968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3839 14:48:12.901575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3840 14:48:12.905017 [ANA_INIT] flow start
3841 14:48:12.905098 [ANA_INIT] PLL >>>>>>>>
3842 14:48:12.908140 [ANA_INIT] PLL <<<<<<<<
3843 14:48:12.911603 [ANA_INIT] MIDPI >>>>>>>>
3844 14:48:12.911708 [ANA_INIT] MIDPI <<<<<<<<
3845 14:48:12.914487 [ANA_INIT] DLL >>>>>>>>
3846 14:48:12.917743 [ANA_INIT] flow end
3847 14:48:12.920933 ============ LP4 DIFF to SE enter ============
3848 14:48:12.924278 ============ LP4 DIFF to SE exit ============
3849 14:48:12.927488 [ANA_INIT] <<<<<<<<<<<<<
3850 14:48:12.930774 [Flow] Enable top DCM control >>>>>
3851 14:48:12.934120 [Flow] Enable top DCM control <<<<<
3852 14:48:12.937489 Enable DLL master slave shuffle
3853 14:48:12.940760 ==============================================================
3854 14:48:12.944543 Gating Mode config
3855 14:48:12.950620 ==============================================================
3856 14:48:12.950729 Config description:
3857 14:48:12.961029 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3858 14:48:12.967218 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3859 14:48:12.970600 SELPH_MODE 0: By rank 1: By Phase
3860 14:48:12.977449 ==============================================================
3861 14:48:12.980521 GAT_TRACK_EN = 1
3862 14:48:12.983762 RX_GATING_MODE = 2
3863 14:48:12.987527 RX_GATING_TRACK_MODE = 2
3864 14:48:12.990374 SELPH_MODE = 1
3865 14:48:12.993874 PICG_EARLY_EN = 1
3866 14:48:12.997189 VALID_LAT_VALUE = 1
3867 14:48:13.000476 ==============================================================
3868 14:48:13.004016 Enter into Gating configuration >>>>
3869 14:48:13.007060 Exit from Gating configuration <<<<
3870 14:48:13.010758 Enter into DVFS_PRE_config >>>>>
3871 14:48:13.024176 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3872 14:48:13.024289 Exit from DVFS_PRE_config <<<<<
3873 14:48:13.027577 Enter into PICG configuration >>>>
3874 14:48:13.030782 Exit from PICG configuration <<<<
3875 14:48:13.033941 [RX_INPUT] configuration >>>>>
3876 14:48:13.037200 [RX_INPUT] configuration <<<<<
3877 14:48:13.043568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3878 14:48:13.046824 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3879 14:48:13.053915 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 14:48:13.060335 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 14:48:13.067025 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3882 14:48:13.073547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3883 14:48:13.076781 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3884 14:48:13.080592 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3885 14:48:13.083603 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3886 14:48:13.090335 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3887 14:48:13.093967 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3888 14:48:13.097054 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 14:48:13.100029 ===================================
3890 14:48:13.103305 LPDDR4 DRAM CONFIGURATION
3891 14:48:13.106712 ===================================
3892 14:48:13.106801 EX_ROW_EN[0] = 0x0
3893 14:48:13.110219 EX_ROW_EN[1] = 0x0
3894 14:48:13.113454 LP4Y_EN = 0x0
3895 14:48:13.113538 WORK_FSP = 0x0
3896 14:48:13.116943 WL = 0x2
3897 14:48:13.117027 RL = 0x2
3898 14:48:13.120206 BL = 0x2
3899 14:48:13.120291 RPST = 0x0
3900 14:48:13.123556 RD_PRE = 0x0
3901 14:48:13.123640 WR_PRE = 0x1
3902 14:48:13.126923 WR_PST = 0x0
3903 14:48:13.127007 DBI_WR = 0x0
3904 14:48:13.130121 DBI_RD = 0x0
3905 14:48:13.130204 OTF = 0x1
3906 14:48:13.133457 ===================================
3907 14:48:13.136687 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3908 14:48:13.143577 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3909 14:48:13.146679 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3910 14:48:13.149996 ===================================
3911 14:48:13.153023 LPDDR4 DRAM CONFIGURATION
3912 14:48:13.156884 ===================================
3913 14:48:13.156969 EX_ROW_EN[0] = 0x10
3914 14:48:13.160254 EX_ROW_EN[1] = 0x0
3915 14:48:13.163422 LP4Y_EN = 0x0
3916 14:48:13.163516 WORK_FSP = 0x0
3917 14:48:13.166637 WL = 0x2
3918 14:48:13.166745 RL = 0x2
3919 14:48:13.169829 BL = 0x2
3920 14:48:13.169927 RPST = 0x0
3921 14:48:13.173540 RD_PRE = 0x0
3922 14:48:13.173643 WR_PRE = 0x1
3923 14:48:13.176657 WR_PST = 0x0
3924 14:48:13.176757 DBI_WR = 0x0
3925 14:48:13.179921 DBI_RD = 0x0
3926 14:48:13.180020 OTF = 0x1
3927 14:48:13.183142 ===================================
3928 14:48:13.189736 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3929 14:48:13.193788 nWR fixed to 30
3930 14:48:13.197607 [ModeRegInit_LP4] CH0 RK0
3931 14:48:13.197713 [ModeRegInit_LP4] CH0 RK1
3932 14:48:13.200647 [ModeRegInit_LP4] CH1 RK0
3933 14:48:13.204130 [ModeRegInit_LP4] CH1 RK1
3934 14:48:13.204236 match AC timing 17
3935 14:48:13.210476 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3936 14:48:13.213658 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3937 14:48:13.217246 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3938 14:48:13.223558 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3939 14:48:13.227340 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3940 14:48:13.227448 ==
3941 14:48:13.230330 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 14:48:13.234049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 14:48:13.234157 ==
3944 14:48:13.240451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 14:48:13.246855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3946 14:48:13.250290 [CA 0] Center 35 (5~66) winsize 62
3947 14:48:13.253625 [CA 1] Center 35 (5~66) winsize 62
3948 14:48:13.256904 [CA 2] Center 33 (3~64) winsize 62
3949 14:48:13.260126 [CA 3] Center 33 (2~64) winsize 63
3950 14:48:13.263440 [CA 4] Center 33 (2~64) winsize 63
3951 14:48:13.266681 [CA 5] Center 32 (2~63) winsize 62
3952 14:48:13.266789
3953 14:48:13.269979 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3954 14:48:13.270091
3955 14:48:13.273350 [CATrainingPosCal] consider 1 rank data
3956 14:48:13.276539 u2DelayCellTimex100 = 270/100 ps
3957 14:48:13.279893 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3958 14:48:13.283142 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3959 14:48:13.286406 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3960 14:48:13.289642 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3961 14:48:13.296714 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3962 14:48:13.299720 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3963 14:48:13.299826
3964 14:48:13.303323 CA PerBit enable=1, Macro0, CA PI delay=32
3965 14:48:13.303426
3966 14:48:13.306402 [CBTSetCACLKResult] CA Dly = 32
3967 14:48:13.306487 CS Dly: 5 (0~36)
3968 14:48:13.306553 ==
3969 14:48:13.309691 Dram Type= 6, Freq= 0, CH_0, rank 1
3970 14:48:13.312905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 14:48:13.316216 ==
3972 14:48:13.319472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 14:48:13.326451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3974 14:48:13.329674 [CA 0] Center 35 (5~66) winsize 62
3975 14:48:13.333301 [CA 1] Center 35 (5~66) winsize 62
3976 14:48:13.336425 [CA 2] Center 34 (3~65) winsize 63
3977 14:48:13.339773 [CA 3] Center 33 (3~64) winsize 62
3978 14:48:13.342954 [CA 4] Center 32 (2~63) winsize 62
3979 14:48:13.346204 [CA 5] Center 32 (2~63) winsize 62
3980 14:48:13.346289
3981 14:48:13.349659 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3982 14:48:13.349743
3983 14:48:13.352676 [CATrainingPosCal] consider 2 rank data
3984 14:48:13.356315 u2DelayCellTimex100 = 270/100 ps
3985 14:48:13.359586 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3986 14:48:13.363138 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3987 14:48:13.366493 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3988 14:48:13.372918 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3989 14:48:13.376067 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3990 14:48:13.379358 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3991 14:48:13.379441
3992 14:48:13.382831 CA PerBit enable=1, Macro0, CA PI delay=32
3993 14:48:13.382935
3994 14:48:13.386389 [CBTSetCACLKResult] CA Dly = 32
3995 14:48:13.386491 CS Dly: 5 (0~36)
3996 14:48:13.386583
3997 14:48:13.389243 ----->DramcWriteLeveling(PI) begin...
3998 14:48:13.389347 ==
3999 14:48:13.392507 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 14:48:13.399165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 14:48:13.399272 ==
4002 14:48:13.403088 Write leveling (Byte 0): 33 => 33
4003 14:48:13.406133 Write leveling (Byte 1): 30 => 30
4004 14:48:13.409255 DramcWriteLeveling(PI) end<-----
4005 14:48:13.409355
4006 14:48:13.409447 ==
4007 14:48:13.412444 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 14:48:13.416097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 14:48:13.416177 ==
4010 14:48:13.419286 [Gating] SW mode calibration
4011 14:48:13.425761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4012 14:48:13.429066 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4013 14:48:13.436210 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 14:48:13.439460 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 14:48:13.442837 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4016 14:48:13.449402 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4017 14:48:13.452602 0 9 16 | B1->B0 | 3131 2525 | 0 0 | (1 1) (0 0)
4018 14:48:13.456105 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 14:48:13.462432 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 14:48:13.465556 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 14:48:13.469105 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 14:48:13.476023 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 14:48:13.478898 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 14:48:13.482453 0 10 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (1 1)
4025 14:48:13.489361 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4026 14:48:13.492302 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 14:48:13.495901 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 14:48:13.502342 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 14:48:13.505403 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 14:48:13.508639 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 14:48:13.515588 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 14:48:13.518738 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4033 14:48:13.522665 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 14:48:13.529161 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 14:48:13.532442 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 14:48:13.535736 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 14:48:13.542340 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 14:48:13.545537 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 14:48:13.548705 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 14:48:13.552282 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 14:48:13.558879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 14:48:13.562175 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 14:48:13.565346 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 14:48:13.571964 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 14:48:13.575416 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 14:48:13.579084 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 14:48:13.585488 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 14:48:13.588437 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4049 14:48:13.592031 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4050 14:48:13.595174 Total UI for P1: 0, mck2ui 16
4051 14:48:13.598726 best dqsien dly found for B0: ( 0, 13, 12)
4052 14:48:13.605297 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 14:48:13.605410 Total UI for P1: 0, mck2ui 16
4054 14:48:13.611999 best dqsien dly found for B1: ( 0, 13, 16)
4055 14:48:13.615287 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4056 14:48:13.618230 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4057 14:48:13.618336
4058 14:48:13.622033 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4059 14:48:13.625261 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4060 14:48:13.628625 [Gating] SW calibration Done
4061 14:48:13.628732 ==
4062 14:48:13.631595 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 14:48:13.635469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 14:48:13.635577 ==
4065 14:48:13.638775 RX Vref Scan: 0
4066 14:48:13.638875
4067 14:48:13.638976 RX Vref 0 -> 0, step: 1
4068 14:48:13.639066
4069 14:48:13.641976 RX Delay -230 -> 252, step: 16
4070 14:48:13.648526 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4071 14:48:13.651749 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4072 14:48:13.655045 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4073 14:48:13.658745 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4074 14:48:13.661917 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4075 14:48:13.668922 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4076 14:48:13.672180 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4077 14:48:13.675455 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4078 14:48:13.678800 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4079 14:48:13.685244 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4080 14:48:13.688756 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4081 14:48:13.691804 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4082 14:48:13.695569 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4083 14:48:13.698443 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4084 14:48:13.705373 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4085 14:48:13.708524 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4086 14:48:13.708608 ==
4087 14:48:13.711617 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 14:48:13.715238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 14:48:13.715343 ==
4090 14:48:13.718513 DQS Delay:
4091 14:48:13.718616 DQS0 = 0, DQS1 = 0
4092 14:48:13.721525 DQM Delay:
4093 14:48:13.721604 DQM0 = 50, DQM1 = 45
4094 14:48:13.721667 DQ Delay:
4095 14:48:13.725117 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4096 14:48:13.728377 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4097 14:48:13.731413 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4098 14:48:13.734966 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4099 14:48:13.735073
4100 14:48:13.735167
4101 14:48:13.738442 ==
4102 14:48:13.738548 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 14:48:13.745053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 14:48:13.745158 ==
4105 14:48:13.745253
4106 14:48:13.745345
4107 14:48:13.745432 TX Vref Scan disable
4108 14:48:13.748999 == TX Byte 0 ==
4109 14:48:13.752230 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4110 14:48:13.755715 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4111 14:48:13.758830 == TX Byte 1 ==
4112 14:48:13.762766 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4113 14:48:13.765723 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4114 14:48:13.768929 ==
4115 14:48:13.772721 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 14:48:13.775923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 14:48:13.776033 ==
4118 14:48:13.776125
4119 14:48:13.776213
4120 14:48:13.779144 TX Vref Scan disable
4121 14:48:13.779254 == TX Byte 0 ==
4122 14:48:13.785620 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4123 14:48:13.803332 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4124 14:48:13.803447 == TX Byte 1 ==
4125 14:48:13.803543 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4126 14:48:13.803633 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4127 14:48:13.803720
4128 14:48:13.803805 [DATLAT]
4129 14:48:13.803889 Freq=600, CH0 RK0
4130 14:48:13.803973
4131 14:48:13.804055 DATLAT Default: 0x9
4132 14:48:13.805273 0, 0xFFFF, sum = 0
4133 14:48:13.805358 1, 0xFFFF, sum = 0
4134 14:48:13.808781 2, 0xFFFF, sum = 0
4135 14:48:13.811925 3, 0xFFFF, sum = 0
4136 14:48:13.812031 4, 0xFFFF, sum = 0
4137 14:48:13.815580 5, 0xFFFF, sum = 0
4138 14:48:13.815690 6, 0xFFFF, sum = 0
4139 14:48:13.818819 7, 0xFFFF, sum = 0
4140 14:48:13.818926 8, 0x0, sum = 1
4141 14:48:13.819019 9, 0x0, sum = 2
4142 14:48:13.822135 10, 0x0, sum = 3
4143 14:48:13.822244 11, 0x0, sum = 4
4144 14:48:13.825510 best_step = 9
4145 14:48:13.825616
4146 14:48:13.825707 ==
4147 14:48:13.828503 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 14:48:13.832163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 14:48:13.832268 ==
4150 14:48:13.835592 RX Vref Scan: 1
4151 14:48:13.835697
4152 14:48:13.835788 RX Vref 0 -> 0, step: 1
4153 14:48:13.835879
4154 14:48:13.838768 RX Delay -163 -> 252, step: 8
4155 14:48:13.838869
4156 14:48:13.841904 Set Vref, RX VrefLevel [Byte0]: 54
4157 14:48:13.845065 [Byte1]: 56
4158 14:48:13.849320
4159 14:48:13.849426 Final RX Vref Byte 0 = 54 to rank0
4160 14:48:13.852584 Final RX Vref Byte 1 = 56 to rank0
4161 14:48:13.856312 Final RX Vref Byte 0 = 54 to rank1
4162 14:48:13.859418 Final RX Vref Byte 1 = 56 to rank1==
4163 14:48:13.862632 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 14:48:13.869515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 14:48:13.869624 ==
4166 14:48:13.869719 DQS Delay:
4167 14:48:13.872592 DQS0 = 0, DQS1 = 0
4168 14:48:13.872693 DQM Delay:
4169 14:48:13.872786 DQM0 = 54, DQM1 = 46
4170 14:48:13.875717 DQ Delay:
4171 14:48:13.879015 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4172 14:48:13.882347 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4173 14:48:13.885536 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4174 14:48:13.888914 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4175 14:48:13.889016
4176 14:48:13.889109
4177 14:48:13.895916 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4178 14:48:13.898951 CH0 RK0: MR19=808, MR18=6C60
4179 14:48:13.905857 CH0_RK0: MR19=0x808, MR18=0x6C60, DQSOSC=389, MR23=63, INC=173, DEC=115
4180 14:48:13.905975
4181 14:48:13.909229 ----->DramcWriteLeveling(PI) begin...
4182 14:48:13.909334 ==
4183 14:48:13.912440 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 14:48:13.915641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 14:48:13.915748 ==
4186 14:48:13.919114 Write leveling (Byte 0): 34 => 34
4187 14:48:13.922639 Write leveling (Byte 1): 30 => 30
4188 14:48:13.925635 DramcWriteLeveling(PI) end<-----
4189 14:48:13.925737
4190 14:48:13.925828 ==
4191 14:48:13.928814 Dram Type= 6, Freq= 0, CH_0, rank 1
4192 14:48:13.932075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 14:48:13.932178 ==
4194 14:48:13.935447 [Gating] SW mode calibration
4195 14:48:13.942375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4196 14:48:13.948805 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4197 14:48:13.952019 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 14:48:13.958602 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 14:48:13.962392 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 14:48:13.965236 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
4201 14:48:13.972011 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
4202 14:48:13.975321 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 14:48:13.978396 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 14:48:13.985079 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 14:48:13.988430 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 14:48:13.991616 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 14:48:13.998204 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 14:48:14.001447 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4209 14:48:14.004700 0 10 16 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
4210 14:48:14.011278 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 14:48:14.014897 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 14:48:14.017939 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 14:48:14.024502 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 14:48:14.028202 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 14:48:14.031411 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 14:48:14.037982 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 14:48:14.041255 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 14:48:14.044545 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 14:48:14.051216 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 14:48:14.054269 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 14:48:14.057643 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 14:48:14.061267 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 14:48:14.067497 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 14:48:14.070725 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 14:48:14.077416 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 14:48:14.081009 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 14:48:14.084252 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 14:48:14.087661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 14:48:14.094505 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 14:48:14.097231 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 14:48:14.100893 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 14:48:14.107192 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4233 14:48:14.110429 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4234 14:48:14.114016 Total UI for P1: 0, mck2ui 16
4235 14:48:14.117268 best dqsien dly found for B1: ( 0, 13, 12)
4236 14:48:14.120628 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 14:48:14.123700 Total UI for P1: 0, mck2ui 16
4238 14:48:14.127289 best dqsien dly found for B0: ( 0, 13, 14)
4239 14:48:14.130282 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4240 14:48:14.137335 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4241 14:48:14.137444
4242 14:48:14.140473 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4243 14:48:14.143550 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4244 14:48:14.147048 [Gating] SW calibration Done
4245 14:48:14.147152 ==
4246 14:48:14.150223 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 14:48:14.153513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 14:48:14.153593 ==
4249 14:48:14.157366 RX Vref Scan: 0
4250 14:48:14.157470
4251 14:48:14.157560 RX Vref 0 -> 0, step: 1
4252 14:48:14.157649
4253 14:48:14.160630 RX Delay -230 -> 252, step: 16
4254 14:48:14.163891 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4255 14:48:14.170285 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4256 14:48:14.173517 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4257 14:48:14.176856 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4258 14:48:14.180509 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4259 14:48:14.183932 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4260 14:48:14.190114 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4261 14:48:14.194140 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4262 14:48:14.196922 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4263 14:48:14.200682 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4264 14:48:14.207148 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4265 14:48:14.210589 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4266 14:48:14.213600 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4267 14:48:14.216831 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4268 14:48:14.223473 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4269 14:48:14.226646 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4270 14:48:14.226795 ==
4271 14:48:14.230476 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 14:48:14.233764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 14:48:14.233895 ==
4274 14:48:14.233988 DQS Delay:
4275 14:48:14.237037 DQS0 = 0, DQS1 = 0
4276 14:48:14.237167 DQM Delay:
4277 14:48:14.240243 DQM0 = 50, DQM1 = 43
4278 14:48:14.240369 DQ Delay:
4279 14:48:14.243502 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4280 14:48:14.246758 DQ4 =57, DQ5 =41, DQ6 =49, DQ7 =57
4281 14:48:14.250135 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4282 14:48:14.253846 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4283 14:48:14.253949
4284 14:48:14.254060
4285 14:48:14.254165 ==
4286 14:48:14.256932 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 14:48:14.260087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 14:48:14.263395 ==
4289 14:48:14.263524
4290 14:48:14.263626
4291 14:48:14.263715 TX Vref Scan disable
4292 14:48:14.267291 == TX Byte 0 ==
4293 14:48:14.270526 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4294 14:48:14.273755 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4295 14:48:14.277143 == TX Byte 1 ==
4296 14:48:14.280154 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4297 14:48:14.283400 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4298 14:48:14.286978 ==
4299 14:48:14.290020 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 14:48:14.293180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 14:48:14.293294 ==
4302 14:48:14.293394
4303 14:48:14.293484
4304 14:48:14.297215 TX Vref Scan disable
4305 14:48:14.297325 == TX Byte 0 ==
4306 14:48:14.303345 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4307 14:48:14.306952 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4308 14:48:14.310127 == TX Byte 1 ==
4309 14:48:14.313273 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4310 14:48:14.316884 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4311 14:48:14.316998
4312 14:48:14.317097 [DATLAT]
4313 14:48:14.319784 Freq=600, CH0 RK1
4314 14:48:14.319885
4315 14:48:14.319985 DATLAT Default: 0x9
4316 14:48:14.323300 0, 0xFFFF, sum = 0
4317 14:48:14.323408 1, 0xFFFF, sum = 0
4318 14:48:14.326811 2, 0xFFFF, sum = 0
4319 14:48:14.330032 3, 0xFFFF, sum = 0
4320 14:48:14.330110 4, 0xFFFF, sum = 0
4321 14:48:14.333543 5, 0xFFFF, sum = 0
4322 14:48:14.333635 6, 0xFFFF, sum = 0
4323 14:48:14.336777 7, 0xFFFF, sum = 0
4324 14:48:14.336880 8, 0x0, sum = 1
4325 14:48:14.336980 9, 0x0, sum = 2
4326 14:48:14.339988 10, 0x0, sum = 3
4327 14:48:14.340090 11, 0x0, sum = 4
4328 14:48:14.343234 best_step = 9
4329 14:48:14.343342
4330 14:48:14.343433 ==
4331 14:48:14.346531 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 14:48:14.349780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 14:48:14.349883 ==
4334 14:48:14.353083 RX Vref Scan: 0
4335 14:48:14.353160
4336 14:48:14.353221 RX Vref 0 -> 0, step: 1
4337 14:48:14.353279
4338 14:48:14.356326 RX Delay -163 -> 252, step: 8
4339 14:48:14.363865 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4340 14:48:14.367212 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4341 14:48:14.370820 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4342 14:48:14.374095 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4343 14:48:14.377384 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4344 14:48:14.383918 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4345 14:48:14.387093 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4346 14:48:14.390896 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4347 14:48:14.394096 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4348 14:48:14.397336 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4349 14:48:14.404107 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4350 14:48:14.407369 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4351 14:48:14.410436 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4352 14:48:14.413897 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4353 14:48:14.420232 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4354 14:48:14.423780 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4355 14:48:14.423894 ==
4356 14:48:14.426864 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 14:48:14.430586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 14:48:14.430668 ==
4359 14:48:14.433745 DQS Delay:
4360 14:48:14.433849 DQS0 = 0, DQS1 = 0
4361 14:48:14.433915 DQM Delay:
4362 14:48:14.436790 DQM0 = 54, DQM1 = 46
4363 14:48:14.436935 DQ Delay:
4364 14:48:14.440530 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4365 14:48:14.443596 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4366 14:48:14.447052 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4367 14:48:14.450077 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4368 14:48:14.450163
4369 14:48:14.450253
4370 14:48:14.460328 [DQSOSCAuto] RK1, (LSB)MR18= 0x6324, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4371 14:48:14.460458 CH0 RK1: MR19=808, MR18=6324
4372 14:48:14.466848 CH0_RK1: MR19=0x808, MR18=0x6324, DQSOSC=391, MR23=63, INC=171, DEC=114
4373 14:48:14.470070 [RxdqsGatingPostProcess] freq 600
4374 14:48:14.476611 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4375 14:48:14.480205 Pre-setting of DQS Precalculation
4376 14:48:14.483607 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4377 14:48:14.483713 ==
4378 14:48:14.486692 Dram Type= 6, Freq= 0, CH_1, rank 0
4379 14:48:14.493495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 14:48:14.493604 ==
4381 14:48:14.496773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4382 14:48:14.503284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4383 14:48:14.506356 [CA 0] Center 36 (5~67) winsize 63
4384 14:48:14.510004 [CA 1] Center 36 (5~67) winsize 63
4385 14:48:14.513143 [CA 2] Center 34 (4~65) winsize 62
4386 14:48:14.516375 [CA 3] Center 34 (3~65) winsize 63
4387 14:48:14.519995 [CA 4] Center 34 (4~65) winsize 62
4388 14:48:14.523557 [CA 5] Center 34 (3~65) winsize 63
4389 14:48:14.523643
4390 14:48:14.526820 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4391 14:48:14.526921
4392 14:48:14.529963 [CATrainingPosCal] consider 1 rank data
4393 14:48:14.533034 u2DelayCellTimex100 = 270/100 ps
4394 14:48:14.536622 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4395 14:48:14.539978 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4396 14:48:14.543432 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4397 14:48:14.549553 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4398 14:48:14.553075 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4399 14:48:14.556459 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4400 14:48:14.556565
4401 14:48:14.559657 CA PerBit enable=1, Macro0, CA PI delay=34
4402 14:48:14.559762
4403 14:48:14.563149 [CBTSetCACLKResult] CA Dly = 34
4404 14:48:14.563258 CS Dly: 6 (0~37)
4405 14:48:14.563355 ==
4406 14:48:14.566145 Dram Type= 6, Freq= 0, CH_1, rank 1
4407 14:48:14.573307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 14:48:14.573451 ==
4409 14:48:14.576628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4410 14:48:14.583048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4411 14:48:14.586212 [CA 0] Center 36 (6~67) winsize 62
4412 14:48:14.589972 [CA 1] Center 36 (6~67) winsize 62
4413 14:48:14.593485 [CA 2] Center 35 (4~66) winsize 63
4414 14:48:14.596823 [CA 3] Center 35 (4~66) winsize 63
4415 14:48:14.599464 [CA 4] Center 35 (5~65) winsize 61
4416 14:48:14.603148 [CA 5] Center 34 (4~65) winsize 62
4417 14:48:14.603263
4418 14:48:14.606504 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4419 14:48:14.606586
4420 14:48:14.609775 [CATrainingPosCal] consider 2 rank data
4421 14:48:14.613234 u2DelayCellTimex100 = 270/100 ps
4422 14:48:14.616051 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4423 14:48:14.619810 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4424 14:48:14.626122 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4425 14:48:14.629687 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4426 14:48:14.632830 CA4 delay=35 (5~65),Diff = 1 PI (9 cell)
4427 14:48:14.636515 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4428 14:48:14.636588
4429 14:48:14.639664 CA PerBit enable=1, Macro0, CA PI delay=34
4430 14:48:14.639761
4431 14:48:14.643200 [CBTSetCACLKResult] CA Dly = 34
4432 14:48:14.643277 CS Dly: 6 (0~37)
4433 14:48:14.643340
4434 14:48:14.646459 ----->DramcWriteLeveling(PI) begin...
4435 14:48:14.649684 ==
4436 14:48:14.652961 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 14:48:14.656216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 14:48:14.656315 ==
4439 14:48:14.659537 Write leveling (Byte 0): 29 => 29
4440 14:48:14.663261 Write leveling (Byte 1): 32 => 32
4441 14:48:14.666315 DramcWriteLeveling(PI) end<-----
4442 14:48:14.666411
4443 14:48:14.666497 ==
4444 14:48:14.669808 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 14:48:14.673344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 14:48:14.673427 ==
4447 14:48:14.676652 [Gating] SW mode calibration
4448 14:48:14.682776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4449 14:48:14.686120 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4450 14:48:14.692756 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 14:48:14.696536 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4452 14:48:14.699914 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4453 14:48:14.706013 0 9 12 | B1->B0 | 2d2d 2929 | 1 0 | (1 0) (0 0)
4454 14:48:14.709570 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
4455 14:48:14.712762 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 14:48:14.719692 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 14:48:14.722595 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 14:48:14.726378 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 14:48:14.732797 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 14:48:14.736049 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 14:48:14.739635 0 10 12 | B1->B0 | 3636 3939 | 0 0 | (0 0) (0 0)
4462 14:48:14.746122 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 14:48:14.749197 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 14:48:14.752764 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 14:48:14.759950 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 14:48:14.763105 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 14:48:14.766503 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 14:48:14.773217 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 14:48:14.776276 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 14:48:14.779534 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 14:48:14.783213 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 14:48:14.789766 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 14:48:14.792982 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 14:48:14.796263 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 14:48:14.802991 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 14:48:14.806238 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 14:48:14.809457 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 14:48:14.816517 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 14:48:14.819680 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 14:48:14.822945 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 14:48:14.829273 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 14:48:14.832578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 14:48:14.835919 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 14:48:14.842558 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 14:48:14.845875 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4486 14:48:14.849143 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 14:48:14.852471 Total UI for P1: 0, mck2ui 16
4488 14:48:14.855920 best dqsien dly found for B0: ( 0, 13, 12)
4489 14:48:14.858783 Total UI for P1: 0, mck2ui 16
4490 14:48:14.862248 best dqsien dly found for B1: ( 0, 13, 12)
4491 14:48:14.865575 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4492 14:48:14.872068 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4493 14:48:14.872150
4494 14:48:14.875317 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4495 14:48:14.878585 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4496 14:48:14.882540 [Gating] SW calibration Done
4497 14:48:14.882622 ==
4498 14:48:14.885841 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 14:48:14.889210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 14:48:14.889286 ==
4501 14:48:14.889350 RX Vref Scan: 0
4502 14:48:14.892399
4503 14:48:14.892471 RX Vref 0 -> 0, step: 1
4504 14:48:14.892562
4505 14:48:14.895528 RX Delay -230 -> 252, step: 16
4506 14:48:14.898614 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4507 14:48:14.905700 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4508 14:48:14.908713 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4509 14:48:14.911932 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4510 14:48:14.915306 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4511 14:48:14.918470 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4512 14:48:14.924951 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4513 14:48:14.928862 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4514 14:48:14.932491 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4515 14:48:14.935741 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4516 14:48:14.941954 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4517 14:48:14.945607 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4518 14:48:14.948846 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4519 14:48:14.951937 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4520 14:48:14.958353 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4521 14:48:14.961937 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4522 14:48:14.962057 ==
4523 14:48:14.965110 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 14:48:14.968432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 14:48:14.968509 ==
4526 14:48:14.971904 DQS Delay:
4527 14:48:14.971984 DQS0 = 0, DQS1 = 0
4528 14:48:14.972054 DQM Delay:
4529 14:48:14.975410 DQM0 = 50, DQM1 = 47
4530 14:48:14.975485 DQ Delay:
4531 14:48:14.978204 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4532 14:48:14.981624 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4533 14:48:14.985113 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4534 14:48:14.988055 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4535 14:48:14.988161
4536 14:48:14.988290
4537 14:48:14.988404 ==
4538 14:48:14.991934 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 14:48:14.998458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 14:48:14.998576 ==
4541 14:48:14.998667
4542 14:48:14.998773
4543 14:48:14.998861 TX Vref Scan disable
4544 14:48:15.001666 == TX Byte 0 ==
4545 14:48:15.004879 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4546 14:48:15.008178 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4547 14:48:15.012085 == TX Byte 1 ==
4548 14:48:15.015165 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4549 14:48:15.018436 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4550 14:48:15.021439 ==
4551 14:48:15.024829 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 14:48:15.028756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 14:48:15.028878 ==
4554 14:48:15.029005
4555 14:48:15.029133
4556 14:48:15.031411 TX Vref Scan disable
4557 14:48:15.034701 == TX Byte 0 ==
4558 14:48:15.038213 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4559 14:48:15.042042 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4560 14:48:15.044840 == TX Byte 1 ==
4561 14:48:15.048012 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4562 14:48:15.051573 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4563 14:48:15.051737
4564 14:48:15.051859 [DATLAT]
4565 14:48:15.054492 Freq=600, CH1 RK0
4566 14:48:15.054597
4567 14:48:15.054706 DATLAT Default: 0x9
4568 14:48:15.058553 0, 0xFFFF, sum = 0
4569 14:48:15.058690 1, 0xFFFF, sum = 0
4570 14:48:15.061866 2, 0xFFFF, sum = 0
4571 14:48:15.065198 3, 0xFFFF, sum = 0
4572 14:48:15.065323 4, 0xFFFF, sum = 0
4573 14:48:15.068512 5, 0xFFFF, sum = 0
4574 14:48:15.068622 6, 0xFFFF, sum = 0
4575 14:48:15.071594 7, 0xFFFF, sum = 0
4576 14:48:15.071697 8, 0x0, sum = 1
4577 14:48:15.071790 9, 0x0, sum = 2
4578 14:48:15.075169 10, 0x0, sum = 3
4579 14:48:15.075276 11, 0x0, sum = 4
4580 14:48:15.078432 best_step = 9
4581 14:48:15.078538
4582 14:48:15.078629 ==
4583 14:48:15.082349 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 14:48:15.085482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 14:48:15.085588 ==
4586 14:48:15.088216 RX Vref Scan: 1
4587 14:48:15.088318
4588 14:48:15.088397 RX Vref 0 -> 0, step: 1
4589 14:48:15.088464
4590 14:48:15.091533 RX Delay -163 -> 252, step: 8
4591 14:48:15.091609
4592 14:48:15.095053 Set Vref, RX VrefLevel [Byte0]: 56
4593 14:48:15.098219 [Byte1]: 55
4594 14:48:15.102017
4595 14:48:15.102132 Final RX Vref Byte 0 = 56 to rank0
4596 14:48:15.105255 Final RX Vref Byte 1 = 55 to rank0
4597 14:48:15.108460 Final RX Vref Byte 0 = 56 to rank1
4598 14:48:15.112201 Final RX Vref Byte 1 = 55 to rank1==
4599 14:48:15.115518 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 14:48:15.122034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 14:48:15.122139 ==
4602 14:48:15.122252 DQS Delay:
4603 14:48:15.125353 DQS0 = 0, DQS1 = 0
4604 14:48:15.125456 DQM Delay:
4605 14:48:15.125565 DQM0 = 50, DQM1 = 45
4606 14:48:15.128400 DQ Delay:
4607 14:48:15.132001 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4608 14:48:15.135593 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4609 14:48:15.138773 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4610 14:48:15.141693 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4611 14:48:15.141777
4612 14:48:15.141848
4613 14:48:15.148275 [DQSOSCAuto] RK0, (LSB)MR18= 0x456b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4614 14:48:15.151754 CH1 RK0: MR19=808, MR18=456B
4615 14:48:15.158732 CH1_RK0: MR19=0x808, MR18=0x456B, DQSOSC=389, MR23=63, INC=173, DEC=115
4616 14:48:15.158839
4617 14:48:15.162154 ----->DramcWriteLeveling(PI) begin...
4618 14:48:15.162268 ==
4619 14:48:15.165309 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 14:48:15.168430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 14:48:15.168541 ==
4622 14:48:15.171794 Write leveling (Byte 0): 31 => 31
4623 14:48:15.175388 Write leveling (Byte 1): 30 => 30
4624 14:48:15.178737 DramcWriteLeveling(PI) end<-----
4625 14:48:15.178813
4626 14:48:15.178884 ==
4627 14:48:15.182028 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 14:48:15.184983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 14:48:15.185067 ==
4630 14:48:15.188365 [Gating] SW mode calibration
4631 14:48:15.195199 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4632 14:48:15.201866 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4633 14:48:15.204827 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4634 14:48:15.211712 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4635 14:48:15.215261 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4636 14:48:15.217920 0 9 12 | B1->B0 | 2d2d 2f2f | 1 0 | (0 0) (0 0)
4637 14:48:15.221868 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 14:48:15.228366 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 14:48:15.231680 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 14:48:15.234892 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 14:48:15.241281 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 14:48:15.244801 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 14:48:15.247862 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4644 14:48:15.255041 0 10 12 | B1->B0 | 3737 3737 | 0 1 | (0 0) (0 0)
4645 14:48:15.258353 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 14:48:15.261363 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 14:48:15.267922 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 14:48:15.271513 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 14:48:15.274532 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 14:48:15.281276 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 14:48:15.284478 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 14:48:15.288039 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 14:48:15.294745 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 14:48:15.297823 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 14:48:15.301260 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 14:48:15.307871 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 14:48:15.311025 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 14:48:15.314718 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 14:48:15.320788 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 14:48:15.324585 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 14:48:15.327844 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 14:48:15.334298 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 14:48:15.337454 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 14:48:15.341235 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 14:48:15.347834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 14:48:15.351088 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 14:48:15.354476 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 14:48:15.360912 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4669 14:48:15.363952 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 14:48:15.367747 Total UI for P1: 0, mck2ui 16
4671 14:48:15.370593 best dqsien dly found for B0: ( 0, 13, 12)
4672 14:48:15.374250 Total UI for P1: 0, mck2ui 16
4673 14:48:15.377474 best dqsien dly found for B1: ( 0, 13, 12)
4674 14:48:15.380742 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4675 14:48:15.383821 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4676 14:48:15.383931
4677 14:48:15.387424 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4678 14:48:15.390844 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4679 14:48:15.394406 [Gating] SW calibration Done
4680 14:48:15.394520 ==
4681 14:48:15.397854 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 14:48:15.400814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 14:48:15.400922 ==
4684 14:48:15.404134 RX Vref Scan: 0
4685 14:48:15.404241
4686 14:48:15.407009 RX Vref 0 -> 0, step: 1
4687 14:48:15.407110
4688 14:48:15.410274 RX Delay -230 -> 252, step: 16
4689 14:48:15.413842 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4690 14:48:15.417120 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4691 14:48:15.420444 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4692 14:48:15.423581 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4693 14:48:15.430375 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4694 14:48:15.433609 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4695 14:48:15.436982 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4696 14:48:15.440350 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4697 14:48:15.446863 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4698 14:48:15.450177 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4699 14:48:15.453596 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4700 14:48:15.456917 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4701 14:48:15.460364 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4702 14:48:15.466904 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4703 14:48:15.470145 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4704 14:48:15.473944 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4705 14:48:15.474030 ==
4706 14:48:15.476864 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 14:48:15.484057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 14:48:15.484158 ==
4709 14:48:15.484224 DQS Delay:
4710 14:48:15.484285 DQS0 = 0, DQS1 = 0
4711 14:48:15.487193 DQM Delay:
4712 14:48:15.487276 DQM0 = 50, DQM1 = 48
4713 14:48:15.490229 DQ Delay:
4714 14:48:15.493816 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4715 14:48:15.493899 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4716 14:48:15.496992 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4717 14:48:15.500287 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4718 14:48:15.503569
4719 14:48:15.503671
4720 14:48:15.503762 ==
4721 14:48:15.506833 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 14:48:15.510441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 14:48:15.510547 ==
4724 14:48:15.510643
4725 14:48:15.510732
4726 14:48:15.513817 TX Vref Scan disable
4727 14:48:15.513929 == TX Byte 0 ==
4728 14:48:15.520269 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4729 14:48:15.523944 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4730 14:48:15.524046 == TX Byte 1 ==
4731 14:48:15.530716 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4732 14:48:15.533511 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4733 14:48:15.533586 ==
4734 14:48:15.537770 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 14:48:15.540517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 14:48:15.540645 ==
4737 14:48:15.540775
4738 14:48:15.540852
4739 14:48:15.543563 TX Vref Scan disable
4740 14:48:15.546747 == TX Byte 0 ==
4741 14:48:15.550208 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4742 14:48:15.553467 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4743 14:48:15.556790 == TX Byte 1 ==
4744 14:48:15.560130 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4745 14:48:15.563497 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4746 14:48:15.563607
4747 14:48:15.566754 [DATLAT]
4748 14:48:15.566833 Freq=600, CH1 RK1
4749 14:48:15.566924
4750 14:48:15.570286 DATLAT Default: 0x9
4751 14:48:15.570369 0, 0xFFFF, sum = 0
4752 14:48:15.573598 1, 0xFFFF, sum = 0
4753 14:48:15.573682 2, 0xFFFF, sum = 0
4754 14:48:15.576861 3, 0xFFFF, sum = 0
4755 14:48:15.576945 4, 0xFFFF, sum = 0
4756 14:48:15.580193 5, 0xFFFF, sum = 0
4757 14:48:15.580276 6, 0xFFFF, sum = 0
4758 14:48:15.583325 7, 0xFFFF, sum = 0
4759 14:48:15.583409 8, 0x0, sum = 1
4760 14:48:15.586999 9, 0x0, sum = 2
4761 14:48:15.587082 10, 0x0, sum = 3
4762 14:48:15.590027 11, 0x0, sum = 4
4763 14:48:15.590110 best_step = 9
4764 14:48:15.590174
4765 14:48:15.590234 ==
4766 14:48:15.593454 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 14:48:15.599766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 14:48:15.599898 ==
4769 14:48:15.600010 RX Vref Scan: 0
4770 14:48:15.600117
4771 14:48:15.603513 RX Vref 0 -> 0, step: 1
4772 14:48:15.603596
4773 14:48:15.606619 RX Delay -163 -> 252, step: 8
4774 14:48:15.610382 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4775 14:48:15.613558 iDelay=205, Bit 1, Center 48 (-91 ~ 188) 280
4776 14:48:15.619887 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4777 14:48:15.623363 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4778 14:48:15.626541 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4779 14:48:15.630388 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4780 14:48:15.633368 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4781 14:48:15.640197 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4782 14:48:15.643970 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4783 14:48:15.647211 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4784 14:48:15.650342 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4785 14:48:15.657585 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4786 14:48:15.660537 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4787 14:48:15.663556 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4788 14:48:15.667004 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4789 14:48:15.670349 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4790 14:48:15.670775 ==
4791 14:48:15.673598 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 14:48:15.680083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 14:48:15.680555 ==
4794 14:48:15.680896 DQS Delay:
4795 14:48:15.684305 DQS0 = 0, DQS1 = 0
4796 14:48:15.684904 DQM Delay:
4797 14:48:15.687526 DQM0 = 50, DQM1 = 46
4798 14:48:15.688094 DQ Delay:
4799 14:48:15.689911 DQ0 =52, DQ1 =48, DQ2 =36, DQ3 =48
4800 14:48:15.693393 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4801 14:48:15.697087 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4802 14:48:15.700237 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4803 14:48:15.700707
4804 14:48:15.701078
4805 14:48:15.707170 [DQSOSCAuto] RK1, (LSB)MR18= 0x671e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4806 14:48:15.710543 CH1 RK1: MR19=808, MR18=671E
4807 14:48:15.716762 CH1_RK1: MR19=0x808, MR18=0x671E, DQSOSC=390, MR23=63, INC=172, DEC=114
4808 14:48:15.720180 [RxdqsGatingPostProcess] freq 600
4809 14:48:15.723548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4810 14:48:15.727059 Pre-setting of DQS Precalculation
4811 14:48:15.733559 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4812 14:48:15.740081 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4813 14:48:15.746972 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4814 14:48:15.747396
4815 14:48:15.747721
4816 14:48:15.750200 [Calibration Summary] 1200 Mbps
4817 14:48:15.750620 CH 0, Rank 0
4818 14:48:15.753521 SW Impedance : PASS
4819 14:48:15.756792 DUTY Scan : NO K
4820 14:48:15.757214 ZQ Calibration : PASS
4821 14:48:15.760037 Jitter Meter : NO K
4822 14:48:15.764080 CBT Training : PASS
4823 14:48:15.764545 Write leveling : PASS
4824 14:48:15.766798 RX DQS gating : PASS
4825 14:48:15.770028 RX DQ/DQS(RDDQC) : PASS
4826 14:48:15.770447 TX DQ/DQS : PASS
4827 14:48:15.773127 RX DATLAT : PASS
4828 14:48:15.776384 RX DQ/DQS(Engine): PASS
4829 14:48:15.776830 TX OE : NO K
4830 14:48:15.779716 All Pass.
4831 14:48:15.780150
4832 14:48:15.780596 CH 0, Rank 1
4833 14:48:15.783021 SW Impedance : PASS
4834 14:48:15.783599 DUTY Scan : NO K
4835 14:48:15.786357 ZQ Calibration : PASS
4836 14:48:15.789621 Jitter Meter : NO K
4837 14:48:15.790040 CBT Training : PASS
4838 14:48:15.792968 Write leveling : PASS
4839 14:48:15.796273 RX DQS gating : PASS
4840 14:48:15.796739 RX DQ/DQS(RDDQC) : PASS
4841 14:48:15.799815 TX DQ/DQS : PASS
4842 14:48:15.800234 RX DATLAT : PASS
4843 14:48:15.803095 RX DQ/DQS(Engine): PASS
4844 14:48:15.806935 TX OE : NO K
4845 14:48:15.807365 All Pass.
4846 14:48:15.807771
4847 14:48:15.808102 CH 1, Rank 0
4848 14:48:15.809977 SW Impedance : PASS
4849 14:48:15.813114 DUTY Scan : NO K
4850 14:48:15.813670 ZQ Calibration : PASS
4851 14:48:15.816363 Jitter Meter : NO K
4852 14:48:15.819633 CBT Training : PASS
4853 14:48:15.820144 Write leveling : PASS
4854 14:48:15.823030 RX DQS gating : PASS
4855 14:48:15.826419 RX DQ/DQS(RDDQC) : PASS
4856 14:48:15.826923 TX DQ/DQS : PASS
4857 14:48:15.829667 RX DATLAT : PASS
4858 14:48:15.832975 RX DQ/DQS(Engine): PASS
4859 14:48:15.833400 TX OE : NO K
4860 14:48:15.836027 All Pass.
4861 14:48:15.836488
4862 14:48:15.836860 CH 1, Rank 1
4863 14:48:15.839407 SW Impedance : PASS
4864 14:48:15.839831 DUTY Scan : NO K
4865 14:48:15.842764 ZQ Calibration : PASS
4866 14:48:15.846083 Jitter Meter : NO K
4867 14:48:15.846678 CBT Training : PASS
4868 14:48:15.849456 Write leveling : PASS
4869 14:48:15.852936 RX DQS gating : PASS
4870 14:48:15.853401 RX DQ/DQS(RDDQC) : PASS
4871 14:48:15.856521 TX DQ/DQS : PASS
4872 14:48:15.856943 RX DATLAT : PASS
4873 14:48:15.859356 RX DQ/DQS(Engine): PASS
4874 14:48:15.863263 TX OE : NO K
4875 14:48:15.863687 All Pass.
4876 14:48:15.864014
4877 14:48:15.865990 DramC Write-DBI off
4878 14:48:15.866407 PER_BANK_REFRESH: Hybrid Mode
4879 14:48:15.869564 TX_TRACKING: ON
4880 14:48:15.879469 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4881 14:48:15.882810 [FAST_K] Save calibration result to emmc
4882 14:48:15.886354 dramc_set_vcore_voltage set vcore to 662500
4883 14:48:15.886789 Read voltage for 933, 3
4884 14:48:15.889987 Vio18 = 0
4885 14:48:15.890503 Vcore = 662500
4886 14:48:15.890833 Vdram = 0
4887 14:48:15.893179 Vddq = 0
4888 14:48:15.893596 Vmddr = 0
4889 14:48:15.896507 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4890 14:48:15.902687 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4891 14:48:15.906165 MEM_TYPE=3, freq_sel=17
4892 14:48:15.909601 sv_algorithm_assistance_LP4_1600
4893 14:48:15.912523 ============ PULL DRAM RESETB DOWN ============
4894 14:48:15.915965 ========== PULL DRAM RESETB DOWN end =========
4895 14:48:15.922663 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4896 14:48:15.926115 ===================================
4897 14:48:15.926544 LPDDR4 DRAM CONFIGURATION
4898 14:48:15.929336 ===================================
4899 14:48:15.932616 EX_ROW_EN[0] = 0x0
4900 14:48:15.933056 EX_ROW_EN[1] = 0x0
4901 14:48:15.936197 LP4Y_EN = 0x0
4902 14:48:15.936651 WORK_FSP = 0x0
4903 14:48:15.939364 WL = 0x3
4904 14:48:15.939787 RL = 0x3
4905 14:48:15.942522 BL = 0x2
4906 14:48:15.946040 RPST = 0x0
4907 14:48:15.946557 RD_PRE = 0x0
4908 14:48:15.949013 WR_PRE = 0x1
4909 14:48:15.949441 WR_PST = 0x0
4910 14:48:15.952308 DBI_WR = 0x0
4911 14:48:15.952868 DBI_RD = 0x0
4912 14:48:15.955977 OTF = 0x1
4913 14:48:15.959089 ===================================
4914 14:48:15.962551 ===================================
4915 14:48:15.963003 ANA top config
4916 14:48:15.965805 ===================================
4917 14:48:15.968723 DLL_ASYNC_EN = 0
4918 14:48:15.972447 ALL_SLAVE_EN = 1
4919 14:48:15.972869 NEW_RANK_MODE = 1
4920 14:48:15.975667 DLL_IDLE_MODE = 1
4921 14:48:15.978740 LP45_APHY_COMB_EN = 1
4922 14:48:15.981955 TX_ODT_DIS = 1
4923 14:48:15.985524 NEW_8X_MODE = 1
4924 14:48:15.988964 ===================================
4925 14:48:15.992062 ===================================
4926 14:48:15.992665 data_rate = 1866
4927 14:48:15.996017 CKR = 1
4928 14:48:15.998882 DQ_P2S_RATIO = 8
4929 14:48:16.002186 ===================================
4930 14:48:16.005454 CA_P2S_RATIO = 8
4931 14:48:16.008698 DQ_CA_OPEN = 0
4932 14:48:16.012063 DQ_SEMI_OPEN = 0
4933 14:48:16.012646 CA_SEMI_OPEN = 0
4934 14:48:16.015219 CA_FULL_RATE = 0
4935 14:48:16.018916 DQ_CKDIV4_EN = 1
4936 14:48:16.022120 CA_CKDIV4_EN = 1
4937 14:48:16.025360 CA_PREDIV_EN = 0
4938 14:48:16.028428 PH8_DLY = 0
4939 14:48:16.028895 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4940 14:48:16.032017 DQ_AAMCK_DIV = 4
4941 14:48:16.035273 CA_AAMCK_DIV = 4
4942 14:48:16.038673 CA_ADMCK_DIV = 4
4943 14:48:16.041941 DQ_TRACK_CA_EN = 0
4944 14:48:16.044731 CA_PICK = 933
4945 14:48:16.048507 CA_MCKIO = 933
4946 14:48:16.048928 MCKIO_SEMI = 0
4947 14:48:16.051948 PLL_FREQ = 3732
4948 14:48:16.055209 DQ_UI_PI_RATIO = 32
4949 14:48:16.058477 CA_UI_PI_RATIO = 0
4950 14:48:16.061904 ===================================
4951 14:48:16.064674 ===================================
4952 14:48:16.067976 memory_type:LPDDR4
4953 14:48:16.068502 GP_NUM : 10
4954 14:48:16.071552 SRAM_EN : 1
4955 14:48:16.072051 MD32_EN : 0
4956 14:48:16.074937 ===================================
4957 14:48:16.078225 [ANA_INIT] >>>>>>>>>>>>>>
4958 14:48:16.081928 <<<<<< [CONFIGURE PHASE]: ANA_TX
4959 14:48:16.084991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4960 14:48:16.088408 ===================================
4961 14:48:16.091505 data_rate = 1866,PCW = 0X8f00
4962 14:48:16.094676 ===================================
4963 14:48:16.098032 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4964 14:48:16.105914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4965 14:48:16.108430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4966 14:48:16.114622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4967 14:48:16.118226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4968 14:48:16.121115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4969 14:48:16.121538 [ANA_INIT] flow start
4970 14:48:16.124679 [ANA_INIT] PLL >>>>>>>>
4971 14:48:16.128454 [ANA_INIT] PLL <<<<<<<<
4972 14:48:16.128876 [ANA_INIT] MIDPI >>>>>>>>
4973 14:48:16.131546 [ANA_INIT] MIDPI <<<<<<<<
4974 14:48:16.135141 [ANA_INIT] DLL >>>>>>>>
4975 14:48:16.135660 [ANA_INIT] flow end
4976 14:48:16.141336 ============ LP4 DIFF to SE enter ============
4977 14:48:16.144282 ============ LP4 DIFF to SE exit ============
4978 14:48:16.148302 [ANA_INIT] <<<<<<<<<<<<<
4979 14:48:16.152039 [Flow] Enable top DCM control >>>>>
4980 14:48:16.154872 [Flow] Enable top DCM control <<<<<
4981 14:48:16.155293 Enable DLL master slave shuffle
4982 14:48:16.161543 ==============================================================
4983 14:48:16.164687 Gating Mode config
4984 14:48:16.167909 ==============================================================
4985 14:48:16.171183 Config description:
4986 14:48:16.180924 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4987 14:48:16.188074 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4988 14:48:16.191310 SELPH_MODE 0: By rank 1: By Phase
4989 14:48:16.197918 ==============================================================
4990 14:48:16.201216 GAT_TRACK_EN = 1
4991 14:48:16.204545 RX_GATING_MODE = 2
4992 14:48:16.207980 RX_GATING_TRACK_MODE = 2
4993 14:48:16.208432 SELPH_MODE = 1
4994 14:48:16.211286 PICG_EARLY_EN = 1
4995 14:48:16.214643 VALID_LAT_VALUE = 1
4996 14:48:16.220842 ==============================================================
4997 14:48:16.224530 Enter into Gating configuration >>>>
4998 14:48:16.228003 Exit from Gating configuration <<<<
4999 14:48:16.231379 Enter into DVFS_PRE_config >>>>>
5000 14:48:16.241908 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5001 14:48:16.244221 Exit from DVFS_PRE_config <<<<<
5002 14:48:16.247546 Enter into PICG configuration >>>>
5003 14:48:16.251072 Exit from PICG configuration <<<<
5004 14:48:16.254575 [RX_INPUT] configuration >>>>>
5005 14:48:16.257471 [RX_INPUT] configuration <<<<<
5006 14:48:16.261093 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5007 14:48:16.267534 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5008 14:48:16.274240 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 14:48:16.280589 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 14:48:16.287103 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5011 14:48:16.290593 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5012 14:48:16.297256 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5013 14:48:16.300560 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5014 14:48:16.304008 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5015 14:48:16.307143 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5016 14:48:16.310608 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5017 14:48:16.317479 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5018 14:48:16.320641 ===================================
5019 14:48:16.323993 LPDDR4 DRAM CONFIGURATION
5020 14:48:16.327243 ===================================
5021 14:48:16.327529 EX_ROW_EN[0] = 0x0
5022 14:48:16.330457 EX_ROW_EN[1] = 0x0
5023 14:48:16.330686 LP4Y_EN = 0x0
5024 14:48:16.333866 WORK_FSP = 0x0
5025 14:48:16.334094 WL = 0x3
5026 14:48:16.336993 RL = 0x3
5027 14:48:16.337220 BL = 0x2
5028 14:48:16.340394 RPST = 0x0
5029 14:48:16.340645 RD_PRE = 0x0
5030 14:48:16.343962 WR_PRE = 0x1
5031 14:48:16.344410 WR_PST = 0x0
5032 14:48:16.347498 DBI_WR = 0x0
5033 14:48:16.347915 DBI_RD = 0x0
5034 14:48:16.351132 OTF = 0x1
5035 14:48:16.354088 ===================================
5036 14:48:16.357824 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5037 14:48:16.360597 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5038 14:48:16.367410 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5039 14:48:16.370719 ===================================
5040 14:48:16.370802 LPDDR4 DRAM CONFIGURATION
5041 14:48:16.373933 ===================================
5042 14:48:16.376805 EX_ROW_EN[0] = 0x10
5043 14:48:16.380173 EX_ROW_EN[1] = 0x0
5044 14:48:16.380250 LP4Y_EN = 0x0
5045 14:48:16.383833 WORK_FSP = 0x0
5046 14:48:16.383921 WL = 0x3
5047 14:48:16.386997 RL = 0x3
5048 14:48:16.387085 BL = 0x2
5049 14:48:16.390686 RPST = 0x0
5050 14:48:16.390782 RD_PRE = 0x0
5051 14:48:16.393771 WR_PRE = 0x1
5052 14:48:16.393873 WR_PST = 0x0
5053 14:48:16.396937 DBI_WR = 0x0
5054 14:48:16.397039 DBI_RD = 0x0
5055 14:48:16.400159 OTF = 0x1
5056 14:48:16.403542 ===================================
5057 14:48:16.410296 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5058 14:48:16.413477 nWR fixed to 30
5059 14:48:16.413632 [ModeRegInit_LP4] CH0 RK0
5060 14:48:16.416644 [ModeRegInit_LP4] CH0 RK1
5061 14:48:16.420096 [ModeRegInit_LP4] CH1 RK0
5062 14:48:16.423465 [ModeRegInit_LP4] CH1 RK1
5063 14:48:16.423669 match AC timing 9
5064 14:48:16.430190 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5065 14:48:16.433366 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5066 14:48:16.436745 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5067 14:48:16.443477 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5068 14:48:16.446764 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5069 14:48:16.447008 ==
5070 14:48:16.449904 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 14:48:16.453259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 14:48:16.453504 ==
5073 14:48:16.459748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5074 14:48:16.466276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5075 14:48:16.469833 [CA 0] Center 37 (6~68) winsize 63
5076 14:48:16.473645 [CA 1] Center 37 (6~68) winsize 63
5077 14:48:16.476960 [CA 2] Center 34 (4~65) winsize 62
5078 14:48:16.480066 [CA 3] Center 34 (3~65) winsize 63
5079 14:48:16.483165 [CA 4] Center 33 (3~64) winsize 62
5080 14:48:16.486657 [CA 5] Center 32 (2~62) winsize 61
5081 14:48:16.486899
5082 14:48:16.489767 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5083 14:48:16.490010
5084 14:48:16.493244 [CATrainingPosCal] consider 1 rank data
5085 14:48:16.496840 u2DelayCellTimex100 = 270/100 ps
5086 14:48:16.499948 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5087 14:48:16.503284 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5088 14:48:16.506579 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5089 14:48:16.509801 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5090 14:48:16.512931 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5091 14:48:16.516375 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5092 14:48:16.516722
5093 14:48:16.523029 CA PerBit enable=1, Macro0, CA PI delay=32
5094 14:48:16.523366
5095 14:48:16.523631 [CBTSetCACLKResult] CA Dly = 32
5096 14:48:16.526633 CS Dly: 5 (0~36)
5097 14:48:16.526964 ==
5098 14:48:16.529653 Dram Type= 6, Freq= 0, CH_0, rank 1
5099 14:48:16.533363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 14:48:16.533632 ==
5101 14:48:16.540145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5102 14:48:16.546289 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5103 14:48:16.549853 [CA 0] Center 37 (6~68) winsize 63
5104 14:48:16.553188 [CA 1] Center 37 (6~68) winsize 63
5105 14:48:16.556529 [CA 2] Center 34 (4~65) winsize 62
5106 14:48:16.559704 [CA 3] Center 34 (3~65) winsize 63
5107 14:48:16.563033 [CA 4] Center 33 (3~63) winsize 61
5108 14:48:16.566385 [CA 5] Center 32 (2~62) winsize 61
5109 14:48:16.566685
5110 14:48:16.570342 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5111 14:48:16.570642
5112 14:48:16.573485 [CATrainingPosCal] consider 2 rank data
5113 14:48:16.576888 u2DelayCellTimex100 = 270/100 ps
5114 14:48:16.580452 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5115 14:48:16.583015 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5116 14:48:16.586342 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5117 14:48:16.590153 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5118 14:48:16.593364 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5119 14:48:16.596318 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5120 14:48:16.600058
5121 14:48:16.603577 CA PerBit enable=1, Macro0, CA PI delay=32
5122 14:48:16.603891
5123 14:48:16.606617 [CBTSetCACLKResult] CA Dly = 32
5124 14:48:16.606925 CS Dly: 5 (0~37)
5125 14:48:16.607206
5126 14:48:16.609617 ----->DramcWriteLeveling(PI) begin...
5127 14:48:16.609983 ==
5128 14:48:16.613029 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 14:48:16.616493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 14:48:16.619763 ==
5131 14:48:16.620132 Write leveling (Byte 0): 31 => 31
5132 14:48:16.623043 Write leveling (Byte 1): 29 => 29
5133 14:48:16.626147 DramcWriteLeveling(PI) end<-----
5134 14:48:16.626579
5135 14:48:16.626921 ==
5136 14:48:16.629804 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 14:48:16.635960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 14:48:16.636386 ==
5139 14:48:16.636747 [Gating] SW mode calibration
5140 14:48:16.646219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5141 14:48:16.649531 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5142 14:48:16.652822 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
5143 14:48:16.659786 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 14:48:16.662940 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 14:48:16.666089 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 14:48:16.672901 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 14:48:16.676257 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 14:48:16.679220 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5149 14:48:16.686072 0 14 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
5150 14:48:16.689509 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (1 0)
5151 14:48:16.692679 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 14:48:16.699575 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 14:48:16.702844 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 14:48:16.705929 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 14:48:16.712703 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 14:48:16.715892 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5157 14:48:16.718879 0 15 28 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
5158 14:48:16.725384 1 0 0 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5159 14:48:16.728792 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 14:48:16.732072 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 14:48:16.738676 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 14:48:16.742685 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 14:48:16.745265 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 14:48:16.752096 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 14:48:16.755372 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5166 14:48:16.759048 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5167 14:48:16.765791 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 14:48:16.768852 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 14:48:16.772199 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 14:48:16.778921 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 14:48:16.782212 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 14:48:16.785207 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 14:48:16.792084 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 14:48:16.795425 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 14:48:16.798934 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 14:48:16.805400 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 14:48:16.808808 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 14:48:16.812147 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 14:48:16.815499 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 14:48:16.822541 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5181 14:48:16.825665 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5182 14:48:16.828971 Total UI for P1: 0, mck2ui 16
5183 14:48:16.832618 best dqsien dly found for B0: ( 1, 2, 24)
5184 14:48:16.835886 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5185 14:48:16.842477 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 14:48:16.842794 Total UI for P1: 0, mck2ui 16
5187 14:48:16.849169 best dqsien dly found for B1: ( 1, 3, 0)
5188 14:48:16.852467 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5189 14:48:16.855789 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5190 14:48:16.856089
5191 14:48:16.859121 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5192 14:48:16.862621 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5193 14:48:16.865454 [Gating] SW calibration Done
5194 14:48:16.865753 ==
5195 14:48:16.868688 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 14:48:16.871871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 14:48:16.872288 ==
5198 14:48:16.875181 RX Vref Scan: 0
5199 14:48:16.875570
5200 14:48:16.875818 RX Vref 0 -> 0, step: 1
5201 14:48:16.876142
5202 14:48:16.878395 RX Delay -80 -> 252, step: 8
5203 14:48:16.881913 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5204 14:48:16.888431 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5205 14:48:16.892063 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5206 14:48:16.895312 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5207 14:48:16.899071 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5208 14:48:16.902572 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5209 14:48:16.905433 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5210 14:48:16.912401 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5211 14:48:16.915739 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5212 14:48:16.918441 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5213 14:48:16.921805 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5214 14:48:16.925023 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5215 14:48:16.931885 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5216 14:48:16.934907 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5217 14:48:16.938676 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5218 14:48:16.941620 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5219 14:48:16.942051 ==
5220 14:48:16.945025 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 14:48:16.948264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 14:48:16.951609 ==
5223 14:48:16.952031 DQS Delay:
5224 14:48:16.952398 DQS0 = 0, DQS1 = 0
5225 14:48:16.954817 DQM Delay:
5226 14:48:16.955237 DQM0 = 104, DQM1 = 96
5227 14:48:16.958193 DQ Delay:
5228 14:48:16.961413 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5229 14:48:16.965512 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5230 14:48:16.968659 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5231 14:48:16.971689 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5232 14:48:16.972110
5233 14:48:16.972500
5234 14:48:16.972819 ==
5235 14:48:16.975357 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 14:48:16.978126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 14:48:16.978552 ==
5238 14:48:16.978882
5239 14:48:16.979188
5240 14:48:16.981985 TX Vref Scan disable
5241 14:48:16.985114 == TX Byte 0 ==
5242 14:48:16.988756 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5243 14:48:16.991914 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5244 14:48:16.995061 == TX Byte 1 ==
5245 14:48:16.998291 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5246 14:48:17.001813 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5247 14:48:17.002235 ==
5248 14:48:17.004907 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 14:48:17.008218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 14:48:17.011683 ==
5251 14:48:17.012103
5252 14:48:17.012481
5253 14:48:17.012797 TX Vref Scan disable
5254 14:48:17.015364 == TX Byte 0 ==
5255 14:48:17.018417 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5256 14:48:17.025102 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5257 14:48:17.025555 == TX Byte 1 ==
5258 14:48:17.028246 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5259 14:48:17.035375 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5260 14:48:17.035851
5261 14:48:17.036215 [DATLAT]
5262 14:48:17.036611 Freq=933, CH0 RK0
5263 14:48:17.036947
5264 14:48:17.038458 DATLAT Default: 0xd
5265 14:48:17.038874 0, 0xFFFF, sum = 0
5266 14:48:17.042065 1, 0xFFFF, sum = 0
5267 14:48:17.044938 2, 0xFFFF, sum = 0
5268 14:48:17.045525 3, 0xFFFF, sum = 0
5269 14:48:17.048724 4, 0xFFFF, sum = 0
5270 14:48:17.049223 5, 0xFFFF, sum = 0
5271 14:48:17.051800 6, 0xFFFF, sum = 0
5272 14:48:17.052227 7, 0xFFFF, sum = 0
5273 14:48:17.055458 8, 0xFFFF, sum = 0
5274 14:48:17.056044 9, 0xFFFF, sum = 0
5275 14:48:17.058369 10, 0x0, sum = 1
5276 14:48:17.058796 11, 0x0, sum = 2
5277 14:48:17.061299 12, 0x0, sum = 3
5278 14:48:17.061725 13, 0x0, sum = 4
5279 14:48:17.062061 best_step = 11
5280 14:48:17.064595
5281 14:48:17.065149 ==
5282 14:48:17.067735 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 14:48:17.071166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 14:48:17.071600 ==
5285 14:48:17.071930 RX Vref Scan: 1
5286 14:48:17.072236
5287 14:48:17.074711 RX Vref 0 -> 0, step: 1
5288 14:48:17.075134
5289 14:48:17.078025 RX Delay -53 -> 252, step: 4
5290 14:48:17.078550
5291 14:48:17.081088 Set Vref, RX VrefLevel [Byte0]: 54
5292 14:48:17.084635 [Byte1]: 56
5293 14:48:17.085123
5294 14:48:17.087591 Final RX Vref Byte 0 = 54 to rank0
5295 14:48:17.091257 Final RX Vref Byte 1 = 56 to rank0
5296 14:48:17.094423 Final RX Vref Byte 0 = 54 to rank1
5297 14:48:17.097865 Final RX Vref Byte 1 = 56 to rank1==
5298 14:48:17.101272 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 14:48:17.104493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 14:48:17.107988 ==
5301 14:48:17.108462 DQS Delay:
5302 14:48:17.108804 DQS0 = 0, DQS1 = 0
5303 14:48:17.111303 DQM Delay:
5304 14:48:17.111725 DQM0 = 104, DQM1 = 97
5305 14:48:17.114589 DQ Delay:
5306 14:48:17.117866 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =102
5307 14:48:17.121154 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5308 14:48:17.124465 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5309 14:48:17.127935 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5310 14:48:17.128395
5311 14:48:17.128733
5312 14:48:17.134704 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5313 14:48:17.137852 CH0 RK0: MR19=505, MR18=3028
5314 14:48:17.144063 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5315 14:48:17.144522
5316 14:48:17.147674 ----->DramcWriteLeveling(PI) begin...
5317 14:48:17.148101 ==
5318 14:48:17.150965 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 14:48:17.154394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 14:48:17.154816 ==
5321 14:48:17.157595 Write leveling (Byte 0): 35 => 35
5322 14:48:17.160849 Write leveling (Byte 1): 29 => 29
5323 14:48:17.164186 DramcWriteLeveling(PI) end<-----
5324 14:48:17.164636
5325 14:48:17.164964 ==
5326 14:48:17.167443 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 14:48:17.171301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 14:48:17.174081 ==
5329 14:48:17.174502 [Gating] SW mode calibration
5330 14:48:17.181256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5331 14:48:17.187301 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5332 14:48:17.190861 0 14 0 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
5333 14:48:17.197346 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 14:48:17.200714 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 14:48:17.203718 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 14:48:17.211090 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 14:48:17.214067 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 14:48:17.217358 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5339 14:48:17.224259 0 14 28 | B1->B0 | 2e2e 2f2f | 1 1 | (1 1) (1 0)
5340 14:48:17.227384 0 15 0 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
5341 14:48:17.230734 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 14:48:17.237518 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 14:48:17.240806 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 14:48:17.244258 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 14:48:17.250871 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 14:48:17.254045 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5347 14:48:17.257183 0 15 28 | B1->B0 | 3838 3939 | 0 0 | (0 0) (0 0)
5348 14:48:17.263597 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5349 14:48:17.266974 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 14:48:17.270742 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 14:48:17.274113 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 14:48:17.280762 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 14:48:17.284008 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 14:48:17.287960 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5355 14:48:17.294402 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 14:48:17.297671 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 14:48:17.300837 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 14:48:17.307471 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 14:48:17.310683 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 14:48:17.314158 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 14:48:17.320890 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 14:48:17.323609 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 14:48:17.327077 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 14:48:17.333732 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 14:48:17.337304 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 14:48:17.341030 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 14:48:17.347653 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 14:48:17.350585 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 14:48:17.353984 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 14:48:17.361142 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5371 14:48:17.364282 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5372 14:48:17.367449 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 14:48:17.370441 Total UI for P1: 0, mck2ui 16
5374 14:48:17.373802 best dqsien dly found for B0: ( 1, 2, 26)
5375 14:48:17.377358 Total UI for P1: 0, mck2ui 16
5376 14:48:17.380725 best dqsien dly found for B1: ( 1, 2, 28)
5377 14:48:17.383925 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5378 14:48:17.387798 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5379 14:48:17.388502
5380 14:48:17.390474 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5381 14:48:17.397098 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5382 14:48:17.397646 [Gating] SW calibration Done
5383 14:48:17.398012 ==
5384 14:48:17.399960 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 14:48:17.406749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 14:48:17.407175 ==
5387 14:48:17.407505 RX Vref Scan: 0
5388 14:48:17.407809
5389 14:48:17.409946 RX Vref 0 -> 0, step: 1
5390 14:48:17.410368
5391 14:48:17.413701 RX Delay -80 -> 252, step: 8
5392 14:48:17.416898 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5393 14:48:17.419897 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5394 14:48:17.423581 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5395 14:48:17.429756 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5396 14:48:17.433459 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5397 14:48:17.436893 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5398 14:48:17.440029 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5399 14:48:17.443193 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5400 14:48:17.446721 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5401 14:48:17.453904 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5402 14:48:17.456793 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5403 14:48:17.459865 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5404 14:48:17.463072 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5405 14:48:17.466500 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5406 14:48:17.470161 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5407 14:48:17.476584 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5408 14:48:17.477118 ==
5409 14:48:17.479932 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 14:48:17.482948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 14:48:17.483496 ==
5412 14:48:17.484013 DQS Delay:
5413 14:48:17.486460 DQS0 = 0, DQS1 = 0
5414 14:48:17.487064 DQM Delay:
5415 14:48:17.489790 DQM0 = 105, DQM1 = 94
5416 14:48:17.490272 DQ Delay:
5417 14:48:17.493043 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =99
5418 14:48:17.496281 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5419 14:48:17.499780 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5420 14:48:17.503272 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5421 14:48:17.503787
5422 14:48:17.504121
5423 14:48:17.504504 ==
5424 14:48:17.506535 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 14:48:17.513135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 14:48:17.513560 ==
5427 14:48:17.513889
5428 14:48:17.514192
5429 14:48:17.514487 TX Vref Scan disable
5430 14:48:17.516467 == TX Byte 0 ==
5431 14:48:17.519899 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5432 14:48:17.526274 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5433 14:48:17.526697 == TX Byte 1 ==
5434 14:48:17.529950 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5435 14:48:17.536460 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5436 14:48:17.536961 ==
5437 14:48:17.539736 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 14:48:17.542869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 14:48:17.543297 ==
5440 14:48:17.543630
5441 14:48:17.543991
5442 14:48:17.546384 TX Vref Scan disable
5443 14:48:17.546810 == TX Byte 0 ==
5444 14:48:17.553060 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5445 14:48:17.556640 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5446 14:48:17.557165 == TX Byte 1 ==
5447 14:48:17.562984 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5448 14:48:17.566489 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5449 14:48:17.567011
5450 14:48:17.567347 [DATLAT]
5451 14:48:17.569295 Freq=933, CH0 RK1
5452 14:48:17.569813
5453 14:48:17.570147 DATLAT Default: 0xb
5454 14:48:17.573187 0, 0xFFFF, sum = 0
5455 14:48:17.573621 1, 0xFFFF, sum = 0
5456 14:48:17.576413 2, 0xFFFF, sum = 0
5457 14:48:17.576845 3, 0xFFFF, sum = 0
5458 14:48:17.580038 4, 0xFFFF, sum = 0
5459 14:48:17.583194 5, 0xFFFF, sum = 0
5460 14:48:17.583697 6, 0xFFFF, sum = 0
5461 14:48:17.586167 7, 0xFFFF, sum = 0
5462 14:48:17.586598 8, 0xFFFF, sum = 0
5463 14:48:17.589291 9, 0xFFFF, sum = 0
5464 14:48:17.589784 10, 0x0, sum = 1
5465 14:48:17.592767 11, 0x0, sum = 2
5466 14:48:17.593196 12, 0x0, sum = 3
5467 14:48:17.593561 13, 0x0, sum = 4
5468 14:48:17.595799 best_step = 11
5469 14:48:17.596217
5470 14:48:17.596619 ==
5471 14:48:17.599551 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 14:48:17.602487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 14:48:17.603019 ==
5474 14:48:17.606323 RX Vref Scan: 0
5475 14:48:17.606744
5476 14:48:17.607071 RX Vref 0 -> 0, step: 1
5477 14:48:17.609532
5478 14:48:17.609952 RX Delay -45 -> 252, step: 4
5479 14:48:17.616810 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5480 14:48:17.620407 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5481 14:48:17.623808 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5482 14:48:17.626710 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5483 14:48:17.633201 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5484 14:48:17.636785 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5485 14:48:17.639892 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5486 14:48:17.643473 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5487 14:48:17.646743 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5488 14:48:17.649669 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5489 14:48:17.656480 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5490 14:48:17.659729 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5491 14:48:17.663179 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5492 14:48:17.666941 iDelay=199, Bit 13, Center 102 (19 ~ 186) 168
5493 14:48:17.669806 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5494 14:48:17.676509 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5495 14:48:17.676935 ==
5496 14:48:17.679850 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 14:48:17.683059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 14:48:17.683553 ==
5499 14:48:17.683906 DQS Delay:
5500 14:48:17.686258 DQS0 = 0, DQS1 = 0
5501 14:48:17.686691 DQM Delay:
5502 14:48:17.689479 DQM0 = 104, DQM1 = 96
5503 14:48:17.689962 DQ Delay:
5504 14:48:17.692840 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =102
5505 14:48:17.696057 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5506 14:48:17.699342 DQ8 =88, DQ9 =88, DQ10 =96, DQ11 =92
5507 14:48:17.703067 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5508 14:48:17.703586
5509 14:48:17.703916
5510 14:48:17.712820 [DQSOSCAuto] RK1, (LSB)MR18= 0x2901, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5511 14:48:17.716194 CH0 RK1: MR19=505, MR18=2901
5512 14:48:17.719089 CH0_RK1: MR19=0x505, MR18=0x2901, DQSOSC=408, MR23=63, INC=65, DEC=43
5513 14:48:17.723307 [RxdqsGatingPostProcess] freq 933
5514 14:48:17.729738 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5515 14:48:17.733030 best DQS0 dly(2T, 0.5T) = (0, 10)
5516 14:48:17.736196 best DQS1 dly(2T, 0.5T) = (0, 11)
5517 14:48:17.739396 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5518 14:48:17.742652 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5519 14:48:17.745947 best DQS0 dly(2T, 0.5T) = (0, 10)
5520 14:48:17.749575 best DQS1 dly(2T, 0.5T) = (0, 10)
5521 14:48:17.752775 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5522 14:48:17.755681 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5523 14:48:17.758856 Pre-setting of DQS Precalculation
5524 14:48:17.762129 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5525 14:48:17.762593 ==
5526 14:48:17.766134 Dram Type= 6, Freq= 0, CH_1, rank 0
5527 14:48:17.769062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 14:48:17.769535 ==
5529 14:48:17.775733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5530 14:48:17.782282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5531 14:48:17.785456 [CA 0] Center 36 (6~67) winsize 62
5532 14:48:17.788728 [CA 1] Center 36 (6~67) winsize 62
5533 14:48:17.792274 [CA 2] Center 34 (4~65) winsize 62
5534 14:48:17.795760 [CA 3] Center 34 (4~65) winsize 62
5535 14:48:17.798802 [CA 4] Center 34 (4~65) winsize 62
5536 14:48:17.802166 [CA 5] Center 33 (3~64) winsize 62
5537 14:48:17.802628
5538 14:48:17.805642 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5539 14:48:17.806066
5540 14:48:17.808755 [CATrainingPosCal] consider 1 rank data
5541 14:48:17.811926 u2DelayCellTimex100 = 270/100 ps
5542 14:48:17.815118 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 14:48:17.818845 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5544 14:48:17.822388 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5545 14:48:17.825643 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5546 14:48:17.829056 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5547 14:48:17.835691 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5548 14:48:17.836210
5549 14:48:17.838851 CA PerBit enable=1, Macro0, CA PI delay=33
5550 14:48:17.839275
5551 14:48:17.842291 [CBTSetCACLKResult] CA Dly = 33
5552 14:48:17.842837 CS Dly: 6 (0~37)
5553 14:48:17.843323 ==
5554 14:48:17.845177 Dram Type= 6, Freq= 0, CH_1, rank 1
5555 14:48:17.848786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 14:48:17.851631 ==
5557 14:48:17.854981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5558 14:48:17.861730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5559 14:48:17.865343 [CA 0] Center 36 (6~67) winsize 62
5560 14:48:17.868335 [CA 1] Center 37 (7~68) winsize 62
5561 14:48:17.871647 [CA 2] Center 35 (5~65) winsize 61
5562 14:48:17.874930 [CA 3] Center 34 (4~65) winsize 62
5563 14:48:17.878077 [CA 4] Center 34 (4~65) winsize 62
5564 14:48:17.881753 [CA 5] Center 34 (4~64) winsize 61
5565 14:48:17.882265
5566 14:48:17.884861 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5567 14:48:17.885305
5568 14:48:17.888719 [CATrainingPosCal] consider 2 rank data
5569 14:48:17.891956 u2DelayCellTimex100 = 270/100 ps
5570 14:48:17.895120 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5571 14:48:17.898541 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5572 14:48:17.901647 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5573 14:48:17.905175 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5574 14:48:17.911934 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5575 14:48:17.915051 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5576 14:48:17.915477
5577 14:48:17.918256 CA PerBit enable=1, Macro0, CA PI delay=34
5578 14:48:17.918697
5579 14:48:17.921671 [CBTSetCACLKResult] CA Dly = 34
5580 14:48:17.922170 CS Dly: 7 (0~40)
5581 14:48:17.922567
5582 14:48:17.924646 ----->DramcWriteLeveling(PI) begin...
5583 14:48:17.925231 ==
5584 14:48:17.928181 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 14:48:17.934751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 14:48:17.935186 ==
5587 14:48:17.938102 Write leveling (Byte 0): 28 => 28
5588 14:48:17.941376 Write leveling (Byte 1): 27 => 27
5589 14:48:17.941809 DramcWriteLeveling(PI) end<-----
5590 14:48:17.942322
5591 14:48:17.944777 ==
5592 14:48:17.947928 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 14:48:17.951385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 14:48:17.951841 ==
5595 14:48:17.954587 [Gating] SW mode calibration
5596 14:48:17.961295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5597 14:48:17.964557 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5598 14:48:17.971514 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 14:48:17.974769 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 14:48:17.978076 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 14:48:17.984756 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 14:48:17.988048 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 14:48:17.991323 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5604 14:48:17.997975 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 1)
5605 14:48:18.001544 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (1 0)
5606 14:48:18.005199 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 14:48:18.011832 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 14:48:18.014798 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 14:48:18.018161 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 14:48:18.021737 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 14:48:18.028034 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 14:48:18.031241 0 15 24 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5613 14:48:18.034771 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5614 14:48:18.041427 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 14:48:18.044719 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 14:48:18.048083 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 14:48:18.054750 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 14:48:18.057867 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 14:48:18.061184 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 14:48:18.067831 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5621 14:48:18.070991 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 14:48:18.074478 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 14:48:18.080809 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 14:48:18.084139 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 14:48:18.087779 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 14:48:18.094473 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 14:48:18.097829 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 14:48:18.100822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 14:48:18.107956 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 14:48:18.111511 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 14:48:18.114504 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 14:48:18.121246 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 14:48:18.124317 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 14:48:18.127310 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 14:48:18.134031 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 14:48:18.137744 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5637 14:48:18.140789 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 14:48:18.144889 Total UI for P1: 0, mck2ui 16
5639 14:48:18.147741 best dqsien dly found for B0: ( 1, 2, 24)
5640 14:48:18.150793 Total UI for P1: 0, mck2ui 16
5641 14:48:18.154478 best dqsien dly found for B1: ( 1, 2, 24)
5642 14:48:18.157783 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5643 14:48:18.161148 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5644 14:48:18.161746
5645 14:48:18.164751 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5646 14:48:18.171265 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5647 14:48:18.171815 [Gating] SW calibration Done
5648 14:48:18.172312 ==
5649 14:48:18.174237 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 14:48:18.181001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 14:48:18.181269 ==
5652 14:48:18.181472 RX Vref Scan: 0
5653 14:48:18.181664
5654 14:48:18.183890 RX Vref 0 -> 0, step: 1
5655 14:48:18.184080
5656 14:48:18.187552 RX Delay -80 -> 252, step: 8
5657 14:48:18.190461 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5658 14:48:18.193960 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5659 14:48:18.197366 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5660 14:48:18.200801 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5661 14:48:18.207081 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5662 14:48:18.210435 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5663 14:48:18.213684 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5664 14:48:18.216934 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5665 14:48:18.220496 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5666 14:48:18.223625 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5667 14:48:18.230090 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5668 14:48:18.233829 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5669 14:48:18.236952 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5670 14:48:18.240164 iDelay=208, Bit 13, Center 111 (24 ~ 199) 176
5671 14:48:18.243955 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5672 14:48:18.250210 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5673 14:48:18.250432 ==
5674 14:48:18.253522 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 14:48:18.256909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 14:48:18.257076 ==
5677 14:48:18.257197 DQS Delay:
5678 14:48:18.260323 DQS0 = 0, DQS1 = 0
5679 14:48:18.260490 DQM Delay:
5680 14:48:18.263514 DQM0 = 103, DQM1 = 99
5681 14:48:18.263688 DQ Delay:
5682 14:48:18.266725 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5683 14:48:18.270141 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5684 14:48:18.273335 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5685 14:48:18.276616 DQ12 =107, DQ13 =111, DQ14 =103, DQ15 =103
5686 14:48:18.276832
5687 14:48:18.276970
5688 14:48:18.277096 ==
5689 14:48:18.280080 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 14:48:18.286583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 14:48:18.286757 ==
5692 14:48:18.286890
5693 14:48:18.287013
5694 14:48:18.287132 TX Vref Scan disable
5695 14:48:18.290528 == TX Byte 0 ==
5696 14:48:18.293499 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5697 14:48:18.297138 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5698 14:48:18.300275 == TX Byte 1 ==
5699 14:48:18.303406 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5700 14:48:18.307096 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5701 14:48:18.310058 ==
5702 14:48:18.313599 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 14:48:18.316788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 14:48:18.316911 ==
5705 14:48:18.317004
5706 14:48:18.317090
5707 14:48:18.320035 TX Vref Scan disable
5708 14:48:18.320130 == TX Byte 0 ==
5709 14:48:18.326688 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5710 14:48:18.330310 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5711 14:48:18.330393 == TX Byte 1 ==
5712 14:48:18.336784 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5713 14:48:18.339865 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5714 14:48:18.339946
5715 14:48:18.340009 [DATLAT]
5716 14:48:18.343520 Freq=933, CH1 RK0
5717 14:48:18.343602
5718 14:48:18.343665 DATLAT Default: 0xd
5719 14:48:18.346782 0, 0xFFFF, sum = 0
5720 14:48:18.346894 1, 0xFFFF, sum = 0
5721 14:48:18.350147 2, 0xFFFF, sum = 0
5722 14:48:18.350230 3, 0xFFFF, sum = 0
5723 14:48:18.353446 4, 0xFFFF, sum = 0
5724 14:48:18.353555 5, 0xFFFF, sum = 0
5725 14:48:18.356769 6, 0xFFFF, sum = 0
5726 14:48:18.356853 7, 0xFFFF, sum = 0
5727 14:48:18.360107 8, 0xFFFF, sum = 0
5728 14:48:18.360190 9, 0xFFFF, sum = 0
5729 14:48:18.363785 10, 0x0, sum = 1
5730 14:48:18.363895 11, 0x0, sum = 2
5731 14:48:18.366841 12, 0x0, sum = 3
5732 14:48:18.366951 13, 0x0, sum = 4
5733 14:48:18.370586 best_step = 11
5734 14:48:18.370667
5735 14:48:18.370730 ==
5736 14:48:18.373565 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 14:48:18.376816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 14:48:18.376931 ==
5739 14:48:18.380217 RX Vref Scan: 1
5740 14:48:18.380317
5741 14:48:18.380444 RX Vref 0 -> 0, step: 1
5742 14:48:18.380531
5743 14:48:18.383633 RX Delay -45 -> 252, step: 4
5744 14:48:18.383742
5745 14:48:18.386977 Set Vref, RX VrefLevel [Byte0]: 56
5746 14:48:18.390149 [Byte1]: 55
5747 14:48:18.394331
5748 14:48:18.394455 Final RX Vref Byte 0 = 56 to rank0
5749 14:48:18.397475 Final RX Vref Byte 1 = 55 to rank0
5750 14:48:18.400664 Final RX Vref Byte 0 = 56 to rank1
5751 14:48:18.404285 Final RX Vref Byte 1 = 55 to rank1==
5752 14:48:18.407715 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 14:48:18.414220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 14:48:18.414344 ==
5755 14:48:18.414439 DQS Delay:
5756 14:48:18.414527 DQS0 = 0, DQS1 = 0
5757 14:48:18.417322 DQM Delay:
5758 14:48:18.417443 DQM0 = 103, DQM1 = 100
5759 14:48:18.420404 DQ Delay:
5760 14:48:18.423861 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5761 14:48:18.427263 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5762 14:48:18.430520 DQ8 =88, DQ9 =90, DQ10 =102, DQ11 =94
5763 14:48:18.433794 DQ12 =106, DQ13 =106, DQ14 =110, DQ15 =106
5764 14:48:18.433923
5765 14:48:18.434018
5766 14:48:18.440658 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5767 14:48:18.444060 CH1 RK0: MR19=505, MR18=1931
5768 14:48:18.450621 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5769 14:48:18.450846
5770 14:48:18.453934 ----->DramcWriteLeveling(PI) begin...
5771 14:48:18.454146 ==
5772 14:48:18.457057 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 14:48:18.460410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 14:48:18.463796 ==
5775 14:48:18.464096 Write leveling (Byte 0): 26 => 26
5776 14:48:18.467097 Write leveling (Byte 1): 27 => 27
5777 14:48:18.470455 DramcWriteLeveling(PI) end<-----
5778 14:48:18.470767
5779 14:48:18.471074 ==
5780 14:48:18.473731 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 14:48:18.480378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 14:48:18.480779 ==
5783 14:48:18.481135 [Gating] SW mode calibration
5784 14:48:18.490187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5785 14:48:18.493504 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5786 14:48:18.500121 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 14:48:18.503342 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 14:48:18.507198 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 14:48:18.513793 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 14:48:18.516983 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 14:48:18.520176 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 14:48:18.523374 0 14 24 | B1->B0 | 2a2a 2f2f | 0 0 | (0 1) (0 0)
5793 14:48:18.530693 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 14:48:18.533350 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 14:48:18.536721 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 14:48:18.543173 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 14:48:18.546803 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 14:48:18.550422 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 14:48:18.556978 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 14:48:18.559891 0 15 24 | B1->B0 | 3333 2626 | 1 0 | (0 0) (0 0)
5801 14:48:18.563627 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5802 14:48:18.569917 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 14:48:18.573141 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 14:48:18.576537 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 14:48:18.583065 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 14:48:18.586646 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 14:48:18.589683 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5808 14:48:18.596355 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5809 14:48:18.599866 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5810 14:48:18.603328 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 14:48:18.609622 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 14:48:18.612847 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 14:48:18.616604 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 14:48:18.623347 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 14:48:18.626433 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 14:48:18.629688 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 14:48:18.636291 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 14:48:18.639550 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 14:48:18.643435 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 14:48:18.646624 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 14:48:18.652983 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 14:48:18.656886 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 14:48:18.659749 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 14:48:18.666276 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5825 14:48:18.670020 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 14:48:18.673035 Total UI for P1: 0, mck2ui 16
5827 14:48:18.676176 best dqsien dly found for B0: ( 1, 2, 24)
5828 14:48:18.680064 Total UI for P1: 0, mck2ui 16
5829 14:48:18.682823 best dqsien dly found for B1: ( 1, 2, 24)
5830 14:48:18.686130 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5831 14:48:18.689427 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5832 14:48:18.689753
5833 14:48:18.692866 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5834 14:48:18.696015 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5835 14:48:18.699337 [Gating] SW calibration Done
5836 14:48:18.699663 ==
5837 14:48:18.703116 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 14:48:18.709261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 14:48:18.709593 ==
5840 14:48:18.709851 RX Vref Scan: 0
5841 14:48:18.710100
5842 14:48:18.712882 RX Vref 0 -> 0, step: 1
5843 14:48:18.713124
5844 14:48:18.715917 RX Delay -80 -> 252, step: 8
5845 14:48:18.718971 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5846 14:48:18.722133 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5847 14:48:18.725890 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5848 14:48:18.729138 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5849 14:48:18.735761 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5850 14:48:18.738977 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5851 14:48:18.742174 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5852 14:48:18.745336 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5853 14:48:18.748843 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5854 14:48:18.751832 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5855 14:48:18.759030 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5856 14:48:18.762389 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5857 14:48:18.765518 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5858 14:48:18.768682 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5859 14:48:18.771806 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5860 14:48:18.778454 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5861 14:48:18.778591 ==
5862 14:48:18.782077 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 14:48:18.785945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 14:48:18.786139 ==
5865 14:48:18.786292 DQS Delay:
5866 14:48:18.788522 DQS0 = 0, DQS1 = 0
5867 14:48:18.788657 DQM Delay:
5868 14:48:18.791751 DQM0 = 102, DQM1 = 99
5869 14:48:18.791938 DQ Delay:
5870 14:48:18.794997 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5871 14:48:18.798645 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5872 14:48:18.801901 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =95
5873 14:48:18.805599 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5874 14:48:18.806123
5875 14:48:18.806481
5876 14:48:18.806998 ==
5877 14:48:18.808766 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 14:48:18.815420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 14:48:18.815975 ==
5880 14:48:18.816443
5881 14:48:18.816777
5882 14:48:18.817212 TX Vref Scan disable
5883 14:48:18.819261 == TX Byte 0 ==
5884 14:48:18.822267 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5885 14:48:18.828431 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5886 14:48:18.829010 == TX Byte 1 ==
5887 14:48:18.832301 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5888 14:48:18.838778 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5889 14:48:18.839376 ==
5890 14:48:18.841921 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 14:48:18.845164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 14:48:18.845747 ==
5893 14:48:18.846141
5894 14:48:18.846652
5895 14:48:18.848378 TX Vref Scan disable
5896 14:48:18.848909 == TX Byte 0 ==
5897 14:48:18.855841 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5898 14:48:18.858802 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5899 14:48:18.859239 == TX Byte 1 ==
5900 14:48:18.864972 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5901 14:48:18.868377 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5902 14:48:18.868628
5903 14:48:18.868824 [DATLAT]
5904 14:48:18.872256 Freq=933, CH1 RK1
5905 14:48:18.872581
5906 14:48:18.872787 DATLAT Default: 0xb
5907 14:48:18.874718 0, 0xFFFF, sum = 0
5908 14:48:18.874975 1, 0xFFFF, sum = 0
5909 14:48:18.878281 2, 0xFFFF, sum = 0
5910 14:48:18.881490 3, 0xFFFF, sum = 0
5911 14:48:18.881660 4, 0xFFFF, sum = 0
5912 14:48:18.885031 5, 0xFFFF, sum = 0
5913 14:48:18.885167 6, 0xFFFF, sum = 0
5914 14:48:18.888211 7, 0xFFFF, sum = 0
5915 14:48:18.888381 8, 0xFFFF, sum = 0
5916 14:48:18.891355 9, 0xFFFF, sum = 0
5917 14:48:18.891463 10, 0x0, sum = 1
5918 14:48:18.894970 11, 0x0, sum = 2
5919 14:48:18.895091 12, 0x0, sum = 3
5920 14:48:18.895196 13, 0x0, sum = 4
5921 14:48:18.898080 best_step = 11
5922 14:48:18.898404
5923 14:48:18.898656 ==
5924 14:48:18.901792 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 14:48:18.904545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 14:48:18.904787 ==
5927 14:48:18.907997 RX Vref Scan: 0
5928 14:48:18.908237
5929 14:48:18.910962 RX Vref 0 -> 0, step: 1
5930 14:48:18.911148
5931 14:48:18.911292 RX Delay -45 -> 252, step: 4
5932 14:48:18.919018 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5933 14:48:18.922298 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5934 14:48:18.925741 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5935 14:48:18.928942 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5936 14:48:18.932297 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5937 14:48:18.938468 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5938 14:48:18.942172 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5939 14:48:18.945333 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5940 14:48:18.948694 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5941 14:48:18.951866 iDelay=203, Bit 9, Center 86 (-1 ~ 174) 176
5942 14:48:18.958292 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5943 14:48:18.962449 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5944 14:48:18.965684 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5945 14:48:18.968745 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5946 14:48:18.971918 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5947 14:48:18.978744 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5948 14:48:18.978874 ==
5949 14:48:18.981951 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 14:48:18.985177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 14:48:18.985295 ==
5952 14:48:18.985386 DQS Delay:
5953 14:48:18.988889 DQS0 = 0, DQS1 = 0
5954 14:48:18.989047 DQM Delay:
5955 14:48:18.991881 DQM0 = 105, DQM1 = 99
5956 14:48:18.992038 DQ Delay:
5957 14:48:18.995211 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5958 14:48:18.998472 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5959 14:48:19.001837 DQ8 =92, DQ9 =86, DQ10 =102, DQ11 =94
5960 14:48:19.004831 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5961 14:48:19.004948
5962 14:48:19.005038
5963 14:48:19.014715 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5964 14:48:19.018277 CH1 RK1: MR19=505, MR18=2C00
5965 14:48:19.021928 CH1_RK1: MR19=0x505, MR18=0x2C00, DQSOSC=408, MR23=63, INC=65, DEC=43
5966 14:48:19.025023 [RxdqsGatingPostProcess] freq 933
5967 14:48:19.031816 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5968 14:48:19.034991 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 14:48:19.038546 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 14:48:19.041837 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 14:48:19.045049 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 14:48:19.048326 best DQS0 dly(2T, 0.5T) = (0, 10)
5973 14:48:19.052234 best DQS1 dly(2T, 0.5T) = (0, 10)
5974 14:48:19.054877 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5975 14:48:19.058724 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5976 14:48:19.058855 Pre-setting of DQS Precalculation
5977 14:48:19.064860 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5978 14:48:19.071908 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5979 14:48:19.078469 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5980 14:48:19.078603
5981 14:48:19.078703
5982 14:48:19.081634 [Calibration Summary] 1866 Mbps
5983 14:48:19.085214 CH 0, Rank 0
5984 14:48:19.085344 SW Impedance : PASS
5985 14:48:19.088449 DUTY Scan : NO K
5986 14:48:19.091813 ZQ Calibration : PASS
5987 14:48:19.091944 Jitter Meter : NO K
5988 14:48:19.095133 CBT Training : PASS
5989 14:48:19.098125 Write leveling : PASS
5990 14:48:19.098255 RX DQS gating : PASS
5991 14:48:19.101797 RX DQ/DQS(RDDQC) : PASS
5992 14:48:19.105141 TX DQ/DQS : PASS
5993 14:48:19.105272 RX DATLAT : PASS
5994 14:48:19.108334 RX DQ/DQS(Engine): PASS
5995 14:48:19.108479 TX OE : NO K
5996 14:48:19.111630 All Pass.
5997 14:48:19.111758
5998 14:48:19.111859 CH 0, Rank 1
5999 14:48:19.114962 SW Impedance : PASS
6000 14:48:19.115106 DUTY Scan : NO K
6001 14:48:19.118193 ZQ Calibration : PASS
6002 14:48:19.121484 Jitter Meter : NO K
6003 14:48:19.121648 CBT Training : PASS
6004 14:48:19.124769 Write leveling : PASS
6005 14:48:19.128392 RX DQS gating : PASS
6006 14:48:19.128702 RX DQ/DQS(RDDQC) : PASS
6007 14:48:19.131300 TX DQ/DQS : PASS
6008 14:48:19.134999 RX DATLAT : PASS
6009 14:48:19.135358 RX DQ/DQS(Engine): PASS
6010 14:48:19.138036 TX OE : NO K
6011 14:48:19.138346 All Pass.
6012 14:48:19.138588
6013 14:48:19.141988 CH 1, Rank 0
6014 14:48:19.142312 SW Impedance : PASS
6015 14:48:19.144883 DUTY Scan : NO K
6016 14:48:19.147975 ZQ Calibration : PASS
6017 14:48:19.148360 Jitter Meter : NO K
6018 14:48:19.151241 CBT Training : PASS
6019 14:48:19.155081 Write leveling : PASS
6020 14:48:19.155394 RX DQS gating : PASS
6021 14:48:19.158440 RX DQ/DQS(RDDQC) : PASS
6022 14:48:19.158831 TX DQ/DQS : PASS
6023 14:48:19.161506 RX DATLAT : PASS
6024 14:48:19.164784 RX DQ/DQS(Engine): PASS
6025 14:48:19.165154 TX OE : NO K
6026 14:48:19.167952 All Pass.
6027 14:48:19.168241
6028 14:48:19.168526 CH 1, Rank 1
6029 14:48:19.171734 SW Impedance : PASS
6030 14:48:19.172104 DUTY Scan : NO K
6031 14:48:19.174858 ZQ Calibration : PASS
6032 14:48:19.177980 Jitter Meter : NO K
6033 14:48:19.178257 CBT Training : PASS
6034 14:48:19.181506 Write leveling : PASS
6035 14:48:19.185015 RX DQS gating : PASS
6036 14:48:19.185302 RX DQ/DQS(RDDQC) : PASS
6037 14:48:19.188492 TX DQ/DQS : PASS
6038 14:48:19.191637 RX DATLAT : PASS
6039 14:48:19.191908 RX DQ/DQS(Engine): PASS
6040 14:48:19.194924 TX OE : NO K
6041 14:48:19.195197 All Pass.
6042 14:48:19.195455
6043 14:48:19.198146 DramC Write-DBI off
6044 14:48:19.201338 PER_BANK_REFRESH: Hybrid Mode
6045 14:48:19.201621 TX_TRACKING: ON
6046 14:48:19.211571 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6047 14:48:19.214697 [FAST_K] Save calibration result to emmc
6048 14:48:19.218343 dramc_set_vcore_voltage set vcore to 650000
6049 14:48:19.221435 Read voltage for 400, 6
6050 14:48:19.221893 Vio18 = 0
6051 14:48:19.222247 Vcore = 650000
6052 14:48:19.224447 Vdram = 0
6053 14:48:19.224842 Vddq = 0
6054 14:48:19.225131 Vmddr = 0
6055 14:48:19.231765 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6056 14:48:19.234839 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6057 14:48:19.238118 MEM_TYPE=3, freq_sel=20
6058 14:48:19.241703 sv_algorithm_assistance_LP4_800
6059 14:48:19.244521 ============ PULL DRAM RESETB DOWN ============
6060 14:48:19.248057 ========== PULL DRAM RESETB DOWN end =========
6061 14:48:19.254578 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6062 14:48:19.257867 ===================================
6063 14:48:19.258261 LPDDR4 DRAM CONFIGURATION
6064 14:48:19.260703 ===================================
6065 14:48:19.264326 EX_ROW_EN[0] = 0x0
6066 14:48:19.267525 EX_ROW_EN[1] = 0x0
6067 14:48:19.267901 LP4Y_EN = 0x0
6068 14:48:19.270749 WORK_FSP = 0x0
6069 14:48:19.271148 WL = 0x2
6070 14:48:19.274679 RL = 0x2
6071 14:48:19.275048 BL = 0x2
6072 14:48:19.277884 RPST = 0x0
6073 14:48:19.278274 RD_PRE = 0x0
6074 14:48:19.280899 WR_PRE = 0x1
6075 14:48:19.281261 WR_PST = 0x0
6076 14:48:19.284089 DBI_WR = 0x0
6077 14:48:19.284550 DBI_RD = 0x0
6078 14:48:19.288032 OTF = 0x1
6079 14:48:19.290425 ===================================
6080 14:48:19.294135 ===================================
6081 14:48:19.294349 ANA top config
6082 14:48:19.297134 ===================================
6083 14:48:19.300655 DLL_ASYNC_EN = 0
6084 14:48:19.303958 ALL_SLAVE_EN = 1
6085 14:48:19.307062 NEW_RANK_MODE = 1
6086 14:48:19.307287 DLL_IDLE_MODE = 1
6087 14:48:19.311038 LP45_APHY_COMB_EN = 1
6088 14:48:19.314386 TX_ODT_DIS = 1
6089 14:48:19.317421 NEW_8X_MODE = 1
6090 14:48:19.320497 ===================================
6091 14:48:19.323888 ===================================
6092 14:48:19.327395 data_rate = 800
6093 14:48:19.327627 CKR = 1
6094 14:48:19.330527 DQ_P2S_RATIO = 4
6095 14:48:19.333911 ===================================
6096 14:48:19.337187 CA_P2S_RATIO = 4
6097 14:48:19.340323 DQ_CA_OPEN = 0
6098 14:48:19.343678 DQ_SEMI_OPEN = 1
6099 14:48:19.347085 CA_SEMI_OPEN = 1
6100 14:48:19.347317 CA_FULL_RATE = 0
6101 14:48:19.350301 DQ_CKDIV4_EN = 0
6102 14:48:19.354078 CA_CKDIV4_EN = 1
6103 14:48:19.356715 CA_PREDIV_EN = 0
6104 14:48:19.360249 PH8_DLY = 0
6105 14:48:19.363504 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6106 14:48:19.363735 DQ_AAMCK_DIV = 0
6107 14:48:19.367141 CA_AAMCK_DIV = 0
6108 14:48:19.370679 CA_ADMCK_DIV = 4
6109 14:48:19.373493 DQ_TRACK_CA_EN = 0
6110 14:48:19.377305 CA_PICK = 800
6111 14:48:19.380026 CA_MCKIO = 400
6112 14:48:19.383553 MCKIO_SEMI = 400
6113 14:48:19.383731 PLL_FREQ = 3016
6114 14:48:19.387157 DQ_UI_PI_RATIO = 32
6115 14:48:19.390495 CA_UI_PI_RATIO = 32
6116 14:48:19.393564 ===================================
6117 14:48:19.397238 ===================================
6118 14:48:19.400520 memory_type:LPDDR4
6119 14:48:19.400687 GP_NUM : 10
6120 14:48:19.403626 SRAM_EN : 1
6121 14:48:19.407117 MD32_EN : 0
6122 14:48:19.410138 ===================================
6123 14:48:19.410332 [ANA_INIT] >>>>>>>>>>>>>>
6124 14:48:19.413441 <<<<<< [CONFIGURE PHASE]: ANA_TX
6125 14:48:19.416903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6126 14:48:19.420628 ===================================
6127 14:48:19.423951 data_rate = 800,PCW = 0X7400
6128 14:48:19.427206 ===================================
6129 14:48:19.430397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6130 14:48:19.437052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 14:48:19.447176 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 14:48:19.453448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6133 14:48:19.456737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6134 14:48:19.460207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6135 14:48:19.460676 [ANA_INIT] flow start
6136 14:48:19.463422 [ANA_INIT] PLL >>>>>>>>
6137 14:48:19.466995 [ANA_INIT] PLL <<<<<<<<
6138 14:48:19.467419 [ANA_INIT] MIDPI >>>>>>>>
6139 14:48:19.470294 [ANA_INIT] MIDPI <<<<<<<<
6140 14:48:19.473459 [ANA_INIT] DLL >>>>>>>>
6141 14:48:19.473884 [ANA_INIT] flow end
6142 14:48:19.480050 ============ LP4 DIFF to SE enter ============
6143 14:48:19.483223 ============ LP4 DIFF to SE exit ============
6144 14:48:19.487135 [ANA_INIT] <<<<<<<<<<<<<
6145 14:48:19.490123 [Flow] Enable top DCM control >>>>>
6146 14:48:19.493496 [Flow] Enable top DCM control <<<<<
6147 14:48:19.494147 Enable DLL master slave shuffle
6148 14:48:19.500654 ==============================================================
6149 14:48:19.503174 Gating Mode config
6150 14:48:19.506697 ==============================================================
6151 14:48:19.510029 Config description:
6152 14:48:19.519813 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6153 14:48:19.526559 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6154 14:48:19.530117 SELPH_MODE 0: By rank 1: By Phase
6155 14:48:19.537096 ==============================================================
6156 14:48:19.540090 GAT_TRACK_EN = 0
6157 14:48:19.543500 RX_GATING_MODE = 2
6158 14:48:19.546349 RX_GATING_TRACK_MODE = 2
6159 14:48:19.549703 SELPH_MODE = 1
6160 14:48:19.550264 PICG_EARLY_EN = 1
6161 14:48:19.553152 VALID_LAT_VALUE = 1
6162 14:48:19.559987 ==============================================================
6163 14:48:19.563047 Enter into Gating configuration >>>>
6164 14:48:19.566350 Exit from Gating configuration <<<<
6165 14:48:19.569636 Enter into DVFS_PRE_config >>>>>
6166 14:48:19.579802 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6167 14:48:19.582963 Exit from DVFS_PRE_config <<<<<
6168 14:48:19.586225 Enter into PICG configuration >>>>
6169 14:48:19.589590 Exit from PICG configuration <<<<
6170 14:48:19.592661 [RX_INPUT] configuration >>>>>
6171 14:48:19.595717 [RX_INPUT] configuration <<<<<
6172 14:48:19.599126 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6173 14:48:19.606358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6174 14:48:19.612669 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6175 14:48:19.619463 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6176 14:48:19.626085 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6177 14:48:19.629583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6178 14:48:19.635733 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6179 14:48:19.639124 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6180 14:48:19.642454 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6181 14:48:19.645661 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6182 14:48:19.652835 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6183 14:48:19.655858 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 14:48:19.659459 ===================================
6185 14:48:19.662272 LPDDR4 DRAM CONFIGURATION
6186 14:48:19.666002 ===================================
6187 14:48:19.666430 EX_ROW_EN[0] = 0x0
6188 14:48:19.669236 EX_ROW_EN[1] = 0x0
6189 14:48:19.669662 LP4Y_EN = 0x0
6190 14:48:19.672542 WORK_FSP = 0x0
6191 14:48:19.672968 WL = 0x2
6192 14:48:19.675651 RL = 0x2
6193 14:48:19.676076 BL = 0x2
6194 14:48:19.679448 RPST = 0x0
6195 14:48:19.679876 RD_PRE = 0x0
6196 14:48:19.682746 WR_PRE = 0x1
6197 14:48:19.683208 WR_PST = 0x0
6198 14:48:19.685858 DBI_WR = 0x0
6199 14:48:19.689206 DBI_RD = 0x0
6200 14:48:19.689774 OTF = 0x1
6201 14:48:19.692405 ===================================
6202 14:48:19.695881 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6203 14:48:19.699012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6204 14:48:19.706191 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 14:48:19.709045 ===================================
6206 14:48:19.712696 LPDDR4 DRAM CONFIGURATION
6207 14:48:19.715540 ===================================
6208 14:48:19.716134 EX_ROW_EN[0] = 0x10
6209 14:48:19.718967 EX_ROW_EN[1] = 0x0
6210 14:48:19.719613 LP4Y_EN = 0x0
6211 14:48:19.722607 WORK_FSP = 0x0
6212 14:48:19.723030 WL = 0x2
6213 14:48:19.725795 RL = 0x2
6214 14:48:19.726362 BL = 0x2
6215 14:48:19.728852 RPST = 0x0
6216 14:48:19.729446 RD_PRE = 0x0
6217 14:48:19.731958 WR_PRE = 0x1
6218 14:48:19.732597 WR_PST = 0x0
6219 14:48:19.735843 DBI_WR = 0x0
6220 14:48:19.736458 DBI_RD = 0x0
6221 14:48:19.738886 OTF = 0x1
6222 14:48:19.741874 ===================================
6223 14:48:19.749074 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6224 14:48:19.752269 nWR fixed to 30
6225 14:48:19.755345 [ModeRegInit_LP4] CH0 RK0
6226 14:48:19.755915 [ModeRegInit_LP4] CH0 RK1
6227 14:48:19.758438 [ModeRegInit_LP4] CH1 RK0
6228 14:48:19.762045 [ModeRegInit_LP4] CH1 RK1
6229 14:48:19.762576 match AC timing 19
6230 14:48:19.768328 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6231 14:48:19.771911 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6232 14:48:19.775529 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6233 14:48:19.781591 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6234 14:48:19.785002 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6235 14:48:19.785101 ==
6236 14:48:19.788130 Dram Type= 6, Freq= 0, CH_0, rank 0
6237 14:48:19.791429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 14:48:19.791569 ==
6239 14:48:19.797951 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 14:48:19.804659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6241 14:48:19.808007 [CA 0] Center 36 (8~64) winsize 57
6242 14:48:19.811357 [CA 1] Center 36 (8~64) winsize 57
6243 14:48:19.814655 [CA 2] Center 36 (8~64) winsize 57
6244 14:48:19.814760 [CA 3] Center 36 (8~64) winsize 57
6245 14:48:19.817998 [CA 4] Center 36 (8~64) winsize 57
6246 14:48:19.821461 [CA 5] Center 36 (8~64) winsize 57
6247 14:48:19.821539
6248 14:48:19.828360 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6249 14:48:19.828456
6250 14:48:19.831443 [CATrainingPosCal] consider 1 rank data
6251 14:48:19.834521 u2DelayCellTimex100 = 270/100 ps
6252 14:48:19.838420 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 14:48:19.841164 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 14:48:19.845022 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 14:48:19.848126 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 14:48:19.851366 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 14:48:19.854607 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 14:48:19.854691
6259 14:48:19.857911 CA PerBit enable=1, Macro0, CA PI delay=36
6260 14:48:19.858033
6261 14:48:19.861466 [CBTSetCACLKResult] CA Dly = 36
6262 14:48:19.864320 CS Dly: 1 (0~32)
6263 14:48:19.864430 ==
6264 14:48:19.867619 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 14:48:19.870997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 14:48:19.871085 ==
6267 14:48:19.877551 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 14:48:19.881494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6269 14:48:19.884546 [CA 0] Center 36 (8~64) winsize 57
6270 14:48:19.887993 [CA 1] Center 36 (8~64) winsize 57
6271 14:48:19.890827 [CA 2] Center 36 (8~64) winsize 57
6272 14:48:19.894796 [CA 3] Center 36 (8~64) winsize 57
6273 14:48:19.897812 [CA 4] Center 36 (8~64) winsize 57
6274 14:48:19.901307 [CA 5] Center 36 (8~64) winsize 57
6275 14:48:19.901413
6276 14:48:19.904571 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6277 14:48:19.904649
6278 14:48:19.907983 [CATrainingPosCal] consider 2 rank data
6279 14:48:19.911253 u2DelayCellTimex100 = 270/100 ps
6280 14:48:19.914575 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 14:48:19.918150 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 14:48:19.924390 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 14:48:19.927697 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 14:48:19.930821 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 14:48:19.934266 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 14:48:19.934395
6287 14:48:19.937766 CA PerBit enable=1, Macro0, CA PI delay=36
6288 14:48:19.937886
6289 14:48:19.940964 [CBTSetCACLKResult] CA Dly = 36
6290 14:48:19.941106 CS Dly: 1 (0~32)
6291 14:48:19.941216
6292 14:48:19.944381 ----->DramcWriteLeveling(PI) begin...
6293 14:48:19.947636 ==
6294 14:48:19.947796 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 14:48:19.954131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 14:48:19.954218 ==
6297 14:48:19.957341 Write leveling (Byte 0): 40 => 8
6298 14:48:19.960992 Write leveling (Byte 1): 40 => 8
6299 14:48:19.961107 DramcWriteLeveling(PI) end<-----
6300 14:48:19.964443
6301 14:48:19.964527 ==
6302 14:48:19.967588 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 14:48:19.970771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 14:48:19.970886 ==
6305 14:48:19.974255 [Gating] SW mode calibration
6306 14:48:19.980663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6307 14:48:19.984496 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6308 14:48:19.990939 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 14:48:19.994186 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 14:48:19.997878 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 14:48:20.004289 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 14:48:20.007401 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 14:48:20.011055 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 14:48:20.017553 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 14:48:20.021002 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 14:48:20.024385 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 14:48:20.027446 Total UI for P1: 0, mck2ui 16
6318 14:48:20.030611 best dqsien dly found for B0: ( 0, 14, 24)
6319 14:48:20.033866 Total UI for P1: 0, mck2ui 16
6320 14:48:20.037209 best dqsien dly found for B1: ( 0, 14, 24)
6321 14:48:20.041051 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6322 14:48:20.044148 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6323 14:48:20.044282
6324 14:48:20.050392 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 14:48:20.054349 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 14:48:20.054471 [Gating] SW calibration Done
6327 14:48:20.057659 ==
6328 14:48:20.060765 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 14:48:20.064239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 14:48:20.064385 ==
6331 14:48:20.064520 RX Vref Scan: 0
6332 14:48:20.064619
6333 14:48:20.067478 RX Vref 0 -> 0, step: 1
6334 14:48:20.067617
6335 14:48:20.070745 RX Delay -410 -> 252, step: 16
6336 14:48:20.074065 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6337 14:48:20.077572 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6338 14:48:20.083907 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6339 14:48:20.087721 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6340 14:48:20.090306 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6341 14:48:20.093989 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6342 14:48:20.100446 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6343 14:48:20.103766 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6344 14:48:20.107169 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6345 14:48:20.110431 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6346 14:48:20.117265 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6347 14:48:20.120768 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6348 14:48:20.123944 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6349 14:48:20.127238 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6350 14:48:20.133846 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6351 14:48:20.137477 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6352 14:48:20.137588 ==
6353 14:48:20.140551 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 14:48:20.143780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 14:48:20.143891 ==
6356 14:48:20.147344 DQS Delay:
6357 14:48:20.147451 DQS0 = 27, DQS1 = 35
6358 14:48:20.150532 DQM Delay:
6359 14:48:20.150610 DQM0 = 12, DQM1 = 12
6360 14:48:20.150672 DQ Delay:
6361 14:48:20.153933 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6362 14:48:20.157210 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6363 14:48:20.160483 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6364 14:48:20.163676 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6365 14:48:20.163757
6366 14:48:20.163819
6367 14:48:20.163878 ==
6368 14:48:20.167274 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 14:48:20.173915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 14:48:20.174029 ==
6371 14:48:20.174123
6372 14:48:20.174212
6373 14:48:20.174299 TX Vref Scan disable
6374 14:48:20.177021 == TX Byte 0 ==
6375 14:48:20.180446 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 14:48:20.183801 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 14:48:20.187092 == TX Byte 1 ==
6378 14:48:20.190284 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 14:48:20.193491 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 14:48:20.193574 ==
6381 14:48:20.196751 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 14:48:20.203083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 14:48:20.203166 ==
6384 14:48:20.203231
6385 14:48:20.203290
6386 14:48:20.203359 TX Vref Scan disable
6387 14:48:20.206889 == TX Byte 0 ==
6388 14:48:20.210086 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 14:48:20.213267 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 14:48:20.216539 == TX Byte 1 ==
6391 14:48:20.219983 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 14:48:20.223550 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 14:48:20.223633
6394 14:48:20.226731 [DATLAT]
6395 14:48:20.226813 Freq=400, CH0 RK0
6396 14:48:20.226878
6397 14:48:20.230025 DATLAT Default: 0xf
6398 14:48:20.230107 0, 0xFFFF, sum = 0
6399 14:48:20.233056 1, 0xFFFF, sum = 0
6400 14:48:20.233140 2, 0xFFFF, sum = 0
6401 14:48:20.236522 3, 0xFFFF, sum = 0
6402 14:48:20.236605 4, 0xFFFF, sum = 0
6403 14:48:20.239972 5, 0xFFFF, sum = 0
6404 14:48:20.240086 6, 0xFFFF, sum = 0
6405 14:48:20.243267 7, 0xFFFF, sum = 0
6406 14:48:20.243350 8, 0xFFFF, sum = 0
6407 14:48:20.246270 9, 0xFFFF, sum = 0
6408 14:48:20.249955 10, 0xFFFF, sum = 0
6409 14:48:20.250039 11, 0xFFFF, sum = 0
6410 14:48:20.252883 12, 0xFFFF, sum = 0
6411 14:48:20.252967 13, 0x0, sum = 1
6412 14:48:20.256489 14, 0x0, sum = 2
6413 14:48:20.256600 15, 0x0, sum = 3
6414 14:48:20.256698 16, 0x0, sum = 4
6415 14:48:20.259509 best_step = 14
6416 14:48:20.259590
6417 14:48:20.259654 ==
6418 14:48:20.263324 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 14:48:20.266538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 14:48:20.266622 ==
6421 14:48:20.269769 RX Vref Scan: 1
6422 14:48:20.269849
6423 14:48:20.273378 RX Vref 0 -> 0, step: 1
6424 14:48:20.273459
6425 14:48:20.273522 RX Delay -311 -> 252, step: 8
6426 14:48:20.273584
6427 14:48:20.276290 Set Vref, RX VrefLevel [Byte0]: 54
6428 14:48:20.279981 [Byte1]: 56
6429 14:48:20.284633
6430 14:48:20.284714 Final RX Vref Byte 0 = 54 to rank0
6431 14:48:20.288497 Final RX Vref Byte 1 = 56 to rank0
6432 14:48:20.292004 Final RX Vref Byte 0 = 54 to rank1
6433 14:48:20.295148 Final RX Vref Byte 1 = 56 to rank1==
6434 14:48:20.298166 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 14:48:20.304568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 14:48:20.304649 ==
6437 14:48:20.304713 DQS Delay:
6438 14:48:20.308241 DQS0 = 28, DQS1 = 36
6439 14:48:20.308369 DQM Delay:
6440 14:48:20.308448 DQM0 = 11, DQM1 = 13
6441 14:48:20.311224 DQ Delay:
6442 14:48:20.314686 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6443 14:48:20.314768 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6444 14:48:20.318560 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6445 14:48:20.321673 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6446 14:48:20.321755
6447 14:48:20.321819
6448 14:48:20.331720 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdbb, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6449 14:48:20.334845 CH0 RK0: MR19=C0C, MR18=CDBB
6450 14:48:20.341402 CH0_RK0: MR19=0xC0C, MR18=0xCDBB, DQSOSC=384, MR23=63, INC=400, DEC=267
6451 14:48:20.341485 ==
6452 14:48:20.344531 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 14:48:20.348276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 14:48:20.348399 ==
6455 14:48:20.351256 [Gating] SW mode calibration
6456 14:48:20.357916 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6457 14:48:20.361448 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6458 14:48:20.368173 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 14:48:20.371363 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 14:48:20.374341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 14:48:20.381303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 14:48:20.384636 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 14:48:20.387979 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 14:48:20.394385 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 14:48:20.398221 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 14:48:20.400861 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 14:48:20.404810 Total UI for P1: 0, mck2ui 16
6468 14:48:20.407981 best dqsien dly found for B0: ( 0, 14, 24)
6469 14:48:20.411075 Total UI for P1: 0, mck2ui 16
6470 14:48:20.414359 best dqsien dly found for B1: ( 0, 14, 24)
6471 14:48:20.417658 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6472 14:48:20.424054 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6473 14:48:20.424137
6474 14:48:20.427413 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 14:48:20.430861 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 14:48:20.434058 [Gating] SW calibration Done
6477 14:48:20.434141 ==
6478 14:48:20.437322 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 14:48:20.440582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 14:48:20.440665 ==
6481 14:48:20.444279 RX Vref Scan: 0
6482 14:48:20.444399
6483 14:48:20.444465 RX Vref 0 -> 0, step: 1
6484 14:48:20.444525
6485 14:48:20.447568 RX Delay -410 -> 252, step: 16
6486 14:48:20.450849 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6487 14:48:20.457759 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6488 14:48:20.460817 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6489 14:48:20.463954 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6490 14:48:20.467210 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6491 14:48:20.474072 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6492 14:48:20.477138 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6493 14:48:20.480722 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6494 14:48:20.483987 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6495 14:48:20.490446 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6496 14:48:20.494379 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6497 14:48:20.497247 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6498 14:48:20.500839 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6499 14:48:20.507176 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6500 14:48:20.510586 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6501 14:48:20.513814 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6502 14:48:20.513897 ==
6503 14:48:20.516946 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 14:48:20.521133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 14:48:20.524219 ==
6506 14:48:20.524335 DQS Delay:
6507 14:48:20.524444 DQS0 = 27, DQS1 = 35
6508 14:48:20.527017 DQM Delay:
6509 14:48:20.527099 DQM0 = 13, DQM1 = 10
6510 14:48:20.530295 DQ Delay:
6511 14:48:20.533887 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6512 14:48:20.533970 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6513 14:48:20.536811 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6514 14:48:20.540313 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6515 14:48:20.540416
6516 14:48:20.540510
6517 14:48:20.543703 ==
6518 14:48:20.546812 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 14:48:20.550499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 14:48:20.550608 ==
6521 14:48:20.550699
6522 14:48:20.550786
6523 14:48:20.553766 TX Vref Scan disable
6524 14:48:20.553847 == TX Byte 0 ==
6525 14:48:20.556997 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6526 14:48:20.563671 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6527 14:48:20.563753 == TX Byte 1 ==
6528 14:48:20.566589 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6529 14:48:20.573646 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6530 14:48:20.573729 ==
6531 14:48:20.576900 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 14:48:20.580568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 14:48:20.580651 ==
6534 14:48:20.580715
6535 14:48:20.580774
6536 14:48:20.583235 TX Vref Scan disable
6537 14:48:20.583317 == TX Byte 0 ==
6538 14:48:20.586861 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6539 14:48:20.593533 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6540 14:48:20.593615 == TX Byte 1 ==
6541 14:48:20.596525 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6542 14:48:20.603493 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6543 14:48:20.603601
6544 14:48:20.603680 [DATLAT]
6545 14:48:20.603739 Freq=400, CH0 RK1
6546 14:48:20.603796
6547 14:48:20.606615 DATLAT Default: 0xe
6548 14:48:20.606695 0, 0xFFFF, sum = 0
6549 14:48:20.610253 1, 0xFFFF, sum = 0
6550 14:48:20.613403 2, 0xFFFF, sum = 0
6551 14:48:20.613485 3, 0xFFFF, sum = 0
6552 14:48:20.617082 4, 0xFFFF, sum = 0
6553 14:48:20.617165 5, 0xFFFF, sum = 0
6554 14:48:20.620297 6, 0xFFFF, sum = 0
6555 14:48:20.620420 7, 0xFFFF, sum = 0
6556 14:48:20.623556 8, 0xFFFF, sum = 0
6557 14:48:20.623639 9, 0xFFFF, sum = 0
6558 14:48:20.626904 10, 0xFFFF, sum = 0
6559 14:48:20.626986 11, 0xFFFF, sum = 0
6560 14:48:20.630053 12, 0xFFFF, sum = 0
6561 14:48:20.630135 13, 0x0, sum = 1
6562 14:48:20.633524 14, 0x0, sum = 2
6563 14:48:20.633606 15, 0x0, sum = 3
6564 14:48:20.636585 16, 0x0, sum = 4
6565 14:48:20.636668 best_step = 14
6566 14:48:20.636731
6567 14:48:20.636789 ==
6568 14:48:20.640368 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 14:48:20.643125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 14:48:20.643207 ==
6571 14:48:20.646428 RX Vref Scan: 0
6572 14:48:20.646508
6573 14:48:20.650353 RX Vref 0 -> 0, step: 1
6574 14:48:20.650434
6575 14:48:20.653444 RX Delay -311 -> 252, step: 8
6576 14:48:20.656775 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6577 14:48:20.663618 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6578 14:48:20.666680 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6579 14:48:20.669833 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6580 14:48:20.673213 iDelay=217, Bit 4, Center -12 (-239 ~ 216) 456
6581 14:48:20.679978 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6582 14:48:20.683135 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6583 14:48:20.686408 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6584 14:48:20.689619 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6585 14:48:20.696564 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6586 14:48:20.699838 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6587 14:48:20.703178 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6588 14:48:20.706294 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6589 14:48:20.712966 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6590 14:48:20.716351 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6591 14:48:20.719634 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6592 14:48:20.719716 ==
6593 14:48:20.723808 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 14:48:20.729555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 14:48:20.729663 ==
6596 14:48:20.729742 DQS Delay:
6597 14:48:20.729801 DQS0 = 24, DQS1 = 32
6598 14:48:20.732840 DQM Delay:
6599 14:48:20.732939 DQM0 = 8, DQM1 = 10
6600 14:48:20.736133 DQ Delay:
6601 14:48:20.736231 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6602 14:48:20.739485 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6603 14:48:20.742792 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6604 14:48:20.746190 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6605 14:48:20.746301
6606 14:48:20.746377
6607 14:48:20.756211 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6608 14:48:20.759589 CH0 RK1: MR19=C0C, MR18=BE5E
6609 14:48:20.766269 CH0_RK1: MR19=0xC0C, MR18=0xBE5E, DQSOSC=386, MR23=63, INC=396, DEC=264
6610 14:48:20.766353 [RxdqsGatingPostProcess] freq 400
6611 14:48:20.772700 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6612 14:48:20.776505 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 14:48:20.779531 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 14:48:20.782987 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 14:48:20.786456 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 14:48:20.789450 best DQS0 dly(2T, 0.5T) = (0, 10)
6617 14:48:20.792772 best DQS1 dly(2T, 0.5T) = (0, 10)
6618 14:48:20.796126 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6619 14:48:20.799540 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6620 14:48:20.803027 Pre-setting of DQS Precalculation
6621 14:48:20.806081 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6622 14:48:20.806164 ==
6623 14:48:20.809387 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 14:48:20.812613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 14:48:20.812696 ==
6626 14:48:20.819259 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 14:48:20.825920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6628 14:48:20.829815 [CA 0] Center 36 (8~64) winsize 57
6629 14:48:20.833206 [CA 1] Center 36 (8~64) winsize 57
6630 14:48:20.836068 [CA 2] Center 36 (8~64) winsize 57
6631 14:48:20.840071 [CA 3] Center 36 (8~64) winsize 57
6632 14:48:20.843054 [CA 4] Center 36 (8~64) winsize 57
6633 14:48:20.843142 [CA 5] Center 36 (8~64) winsize 57
6634 14:48:20.846219
6635 14:48:20.849540 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6636 14:48:20.849652
6637 14:48:20.852822 [CATrainingPosCal] consider 1 rank data
6638 14:48:20.856119 u2DelayCellTimex100 = 270/100 ps
6639 14:48:20.859393 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 14:48:20.862817 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 14:48:20.866262 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 14:48:20.869771 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 14:48:20.873011 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 14:48:20.876179 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 14:48:20.876284
6646 14:48:20.879477 CA PerBit enable=1, Macro0, CA PI delay=36
6647 14:48:20.879652
6648 14:48:20.882827 [CBTSetCACLKResult] CA Dly = 36
6649 14:48:20.885996 CS Dly: 1 (0~32)
6650 14:48:20.886078 ==
6651 14:48:20.889458 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 14:48:20.892357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 14:48:20.892496 ==
6654 14:48:20.899619 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 14:48:20.905734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6656 14:48:20.908940 [CA 0] Center 36 (8~64) winsize 57
6657 14:48:20.909023 [CA 1] Center 36 (8~64) winsize 57
6658 14:48:20.912489 [CA 2] Center 36 (8~64) winsize 57
6659 14:48:20.915956 [CA 3] Center 36 (8~64) winsize 57
6660 14:48:20.919227 [CA 4] Center 36 (8~64) winsize 57
6661 14:48:20.922286 [CA 5] Center 36 (8~64) winsize 57
6662 14:48:20.922369
6663 14:48:20.925996 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6664 14:48:20.926092
6665 14:48:20.929117 [CATrainingPosCal] consider 2 rank data
6666 14:48:20.932691 u2DelayCellTimex100 = 270/100 ps
6667 14:48:20.935828 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 14:48:20.942509 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 14:48:20.946418 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 14:48:20.949306 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 14:48:20.952358 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 14:48:20.955579 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 14:48:20.955661
6674 14:48:20.959630 CA PerBit enable=1, Macro0, CA PI delay=36
6675 14:48:20.959713
6676 14:48:20.962770 [CBTSetCACLKResult] CA Dly = 36
6677 14:48:20.962852 CS Dly: 1 (0~32)
6678 14:48:20.962916
6679 14:48:20.966091 ----->DramcWriteLeveling(PI) begin...
6680 14:48:20.969378 ==
6681 14:48:20.972910 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 14:48:20.975849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 14:48:20.975934 ==
6684 14:48:20.979182 Write leveling (Byte 0): 40 => 8
6685 14:48:20.982491 Write leveling (Byte 1): 40 => 8
6686 14:48:20.985681 DramcWriteLeveling(PI) end<-----
6687 14:48:20.985764
6688 14:48:20.985827 ==
6689 14:48:20.989544 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 14:48:20.992801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 14:48:20.992884 ==
6692 14:48:20.996073 [Gating] SW mode calibration
6693 14:48:21.002636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6694 14:48:21.005890 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6695 14:48:21.012842 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 14:48:21.015917 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 14:48:21.019480 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 14:48:21.025948 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 14:48:21.029423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 14:48:21.032157 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 14:48:21.039070 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 14:48:21.042628 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 14:48:21.045623 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 14:48:21.048713 Total UI for P1: 0, mck2ui 16
6705 14:48:21.052276 best dqsien dly found for B0: ( 0, 14, 24)
6706 14:48:21.055783 Total UI for P1: 0, mck2ui 16
6707 14:48:21.059059 best dqsien dly found for B1: ( 0, 14, 24)
6708 14:48:21.062236 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6709 14:48:21.065559 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6710 14:48:21.065642
6711 14:48:21.072202 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 14:48:21.075603 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 14:48:21.078843 [Gating] SW calibration Done
6714 14:48:21.078925 ==
6715 14:48:21.082245 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 14:48:21.085590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 14:48:21.085673 ==
6718 14:48:21.085737 RX Vref Scan: 0
6719 14:48:21.085795
6720 14:48:21.088878 RX Vref 0 -> 0, step: 1
6721 14:48:21.088958
6722 14:48:21.092250 RX Delay -410 -> 252, step: 16
6723 14:48:21.095720 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6724 14:48:21.102524 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6725 14:48:21.105734 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6726 14:48:21.108882 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6727 14:48:21.112128 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6728 14:48:21.115509 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6729 14:48:21.122366 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6730 14:48:21.125580 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6731 14:48:21.128878 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6732 14:48:21.132096 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6733 14:48:21.138542 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6734 14:48:21.141877 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6735 14:48:21.145591 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6736 14:48:21.152211 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6737 14:48:21.155227 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6738 14:48:21.158995 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6739 14:48:21.159077 ==
6740 14:48:21.161946 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 14:48:21.164921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 14:48:21.168265 ==
6743 14:48:21.168357 DQS Delay:
6744 14:48:21.168425 DQS0 = 35, DQS1 = 35
6745 14:48:21.172135 DQM Delay:
6746 14:48:21.172218 DQM0 = 18, DQM1 = 13
6747 14:48:21.175093 DQ Delay:
6748 14:48:21.175181 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6749 14:48:21.178616 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6750 14:48:21.181843 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6751 14:48:21.185178 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6752 14:48:21.185262
6753 14:48:21.185326
6754 14:48:21.188439 ==
6755 14:48:21.192259 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 14:48:21.195754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 14:48:21.195837 ==
6758 14:48:21.195903
6759 14:48:21.195962
6760 14:48:21.198302 TX Vref Scan disable
6761 14:48:21.198384 == TX Byte 0 ==
6762 14:48:21.201650 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 14:48:21.208869 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 14:48:21.208957 == TX Byte 1 ==
6765 14:48:21.211603 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 14:48:21.215585 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 14:48:21.218751 ==
6768 14:48:21.222079 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 14:48:21.225281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 14:48:21.225399 ==
6771 14:48:21.225492
6772 14:48:21.225572
6773 14:48:21.228742 TX Vref Scan disable
6774 14:48:21.228828 == TX Byte 0 ==
6775 14:48:21.231808 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 14:48:21.238189 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 14:48:21.238286 == TX Byte 1 ==
6778 14:48:21.241687 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 14:48:21.248310 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 14:48:21.248419
6781 14:48:21.248495 [DATLAT]
6782 14:48:21.248565 Freq=400, CH1 RK0
6783 14:48:21.248632
6784 14:48:21.251595 DATLAT Default: 0xf
6785 14:48:21.251691 0, 0xFFFF, sum = 0
6786 14:48:21.254985 1, 0xFFFF, sum = 0
6787 14:48:21.258375 2, 0xFFFF, sum = 0
6788 14:48:21.258500 3, 0xFFFF, sum = 0
6789 14:48:21.262106 4, 0xFFFF, sum = 0
6790 14:48:21.262221 5, 0xFFFF, sum = 0
6791 14:48:21.265308 6, 0xFFFF, sum = 0
6792 14:48:21.265434 7, 0xFFFF, sum = 0
6793 14:48:21.268567 8, 0xFFFF, sum = 0
6794 14:48:21.268709 9, 0xFFFF, sum = 0
6795 14:48:21.271796 10, 0xFFFF, sum = 0
6796 14:48:21.272022 11, 0xFFFF, sum = 0
6797 14:48:21.275115 12, 0xFFFF, sum = 0
6798 14:48:21.275361 13, 0x0, sum = 1
6799 14:48:21.278721 14, 0x0, sum = 2
6800 14:48:21.278974 15, 0x0, sum = 3
6801 14:48:21.281740 16, 0x0, sum = 4
6802 14:48:21.281998 best_step = 14
6803 14:48:21.282174
6804 14:48:21.282325 ==
6805 14:48:21.285434 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 14:48:21.288562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 14:48:21.291973 ==
6808 14:48:21.292228 RX Vref Scan: 1
6809 14:48:21.292460
6810 14:48:21.295512 RX Vref 0 -> 0, step: 1
6811 14:48:21.295837
6812 14:48:21.298691 RX Delay -311 -> 252, step: 8
6813 14:48:21.299109
6814 14:48:21.299435 Set Vref, RX VrefLevel [Byte0]: 56
6815 14:48:21.302073 [Byte1]: 55
6816 14:48:21.307551
6817 14:48:21.307976 Final RX Vref Byte 0 = 56 to rank0
6818 14:48:21.310805 Final RX Vref Byte 1 = 55 to rank0
6819 14:48:21.314378 Final RX Vref Byte 0 = 56 to rank1
6820 14:48:21.317655 Final RX Vref Byte 1 = 55 to rank1==
6821 14:48:21.320684 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 14:48:21.327786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 14:48:21.328336 ==
6824 14:48:21.328724 DQS Delay:
6825 14:48:21.331164 DQS0 = 28, DQS1 = 32
6826 14:48:21.331721 DQM Delay:
6827 14:48:21.332132 DQM0 = 9, DQM1 = 9
6828 14:48:21.333996 DQ Delay:
6829 14:48:21.337400 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6830 14:48:21.337865 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6831 14:48:21.340985 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6832 14:48:21.343761 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6833 14:48:21.344223
6834 14:48:21.344606
6835 14:48:21.354282 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6836 14:48:21.357238 CH1 RK0: MR19=C0C, MR18=8FC8
6837 14:48:21.363814 CH1_RK0: MR19=0xC0C, MR18=0x8FC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6838 14:48:21.364373 ==
6839 14:48:21.367110 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 14:48:21.370227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 14:48:21.370646 ==
6842 14:48:21.373509 [Gating] SW mode calibration
6843 14:48:21.380448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6844 14:48:21.386802 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6845 14:48:21.389931 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 14:48:21.393173 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 14:48:21.399897 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 14:48:21.402922 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 14:48:21.406588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 14:48:21.413133 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 14:48:21.416392 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 14:48:21.419443 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 14:48:21.426601 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 14:48:21.427072 Total UI for P1: 0, mck2ui 16
6855 14:48:21.429869 best dqsien dly found for B0: ( 0, 14, 24)
6856 14:48:21.433106 Total UI for P1: 0, mck2ui 16
6857 14:48:21.436275 best dqsien dly found for B1: ( 0, 14, 24)
6858 14:48:21.443294 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6859 14:48:21.446258 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6860 14:48:21.446852
6861 14:48:21.449515 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 14:48:21.453317 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 14:48:21.456255 [Gating] SW calibration Done
6864 14:48:21.456781 ==
6865 14:48:21.459995 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 14:48:21.463172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 14:48:21.463681 ==
6868 14:48:21.466376 RX Vref Scan: 0
6869 14:48:21.466940
6870 14:48:21.467451 RX Vref 0 -> 0, step: 1
6871 14:48:21.467882
6872 14:48:21.469576 RX Delay -410 -> 252, step: 16
6873 14:48:21.472778 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6874 14:48:21.479291 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6875 14:48:21.482708 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6876 14:48:21.485835 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6877 14:48:21.489177 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6878 14:48:21.495975 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6879 14:48:21.499270 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6880 14:48:21.502436 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6881 14:48:21.506258 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6882 14:48:21.512275 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6883 14:48:21.515890 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6884 14:48:21.519261 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6885 14:48:21.522246 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6886 14:48:21.529208 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6887 14:48:21.532542 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6888 14:48:21.535564 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6889 14:48:21.535641 ==
6890 14:48:21.539419 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 14:48:21.542763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 14:48:21.546024 ==
6893 14:48:21.546130 DQS Delay:
6894 14:48:21.546227 DQS0 = 35, DQS1 = 35
6895 14:48:21.549107 DQM Delay:
6896 14:48:21.549210 DQM0 = 19, DQM1 = 15
6897 14:48:21.552684 DQ Delay:
6898 14:48:21.555864 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6899 14:48:21.555966 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6900 14:48:21.559027 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6901 14:48:21.562660 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6902 14:48:21.562765
6903 14:48:21.562857
6904 14:48:21.565952 ==
6905 14:48:21.569282 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 14:48:21.572541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 14:48:21.572614 ==
6908 14:48:21.572686
6909 14:48:21.572743
6910 14:48:21.575702 TX Vref Scan disable
6911 14:48:21.575801 == TX Byte 0 ==
6912 14:48:21.579043 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6913 14:48:21.585872 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6914 14:48:21.585986 == TX Byte 1 ==
6915 14:48:21.589182 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6916 14:48:21.595637 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6917 14:48:21.595764 ==
6918 14:48:21.599404 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 14:48:21.602513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 14:48:21.602623 ==
6921 14:48:21.602717
6922 14:48:21.602806
6923 14:48:21.605982 TX Vref Scan disable
6924 14:48:21.606089 == TX Byte 0 ==
6925 14:48:21.609168 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6926 14:48:21.615856 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6927 14:48:21.615960 == TX Byte 1 ==
6928 14:48:21.619047 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6929 14:48:21.622349 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6930 14:48:21.625537
6931 14:48:21.625610 [DATLAT]
6932 14:48:21.625670 Freq=400, CH1 RK1
6933 14:48:21.625734
6934 14:48:21.629265 DATLAT Default: 0xe
6935 14:48:21.629338 0, 0xFFFF, sum = 0
6936 14:48:21.632307 1, 0xFFFF, sum = 0
6937 14:48:21.632406 2, 0xFFFF, sum = 0
6938 14:48:21.636069 3, 0xFFFF, sum = 0
6939 14:48:21.636171 4, 0xFFFF, sum = 0
6940 14:48:21.639151 5, 0xFFFF, sum = 0
6941 14:48:21.642649 6, 0xFFFF, sum = 0
6942 14:48:21.642720 7, 0xFFFF, sum = 0
6943 14:48:21.645562 8, 0xFFFF, sum = 0
6944 14:48:21.645668 9, 0xFFFF, sum = 0
6945 14:48:21.649074 10, 0xFFFF, sum = 0
6946 14:48:21.649185 11, 0xFFFF, sum = 0
6947 14:48:21.652251 12, 0xFFFF, sum = 0
6948 14:48:21.652369 13, 0x0, sum = 1
6949 14:48:21.655886 14, 0x0, sum = 2
6950 14:48:21.655986 15, 0x0, sum = 3
6951 14:48:21.658810 16, 0x0, sum = 4
6952 14:48:21.658887 best_step = 14
6953 14:48:21.658977
6954 14:48:21.659062 ==
6955 14:48:21.662527 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 14:48:21.665784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 14:48:21.665881 ==
6958 14:48:21.668786 RX Vref Scan: 0
6959 14:48:21.668890
6960 14:48:21.672572 RX Vref 0 -> 0, step: 1
6961 14:48:21.672668
6962 14:48:21.672755 RX Delay -311 -> 252, step: 8
6963 14:48:21.681016 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6964 14:48:21.684299 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6965 14:48:21.687588 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6966 14:48:21.691027 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6967 14:48:21.697644 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6968 14:48:21.701542 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6969 14:48:21.704279 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6970 14:48:21.707753 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6971 14:48:21.714205 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6972 14:48:21.717479 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6973 14:48:21.721500 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6974 14:48:21.724617 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6975 14:48:21.731004 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6976 14:48:21.734351 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6977 14:48:21.737889 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6978 14:48:21.741041 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6979 14:48:21.744694 ==
6980 14:48:21.747838 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 14:48:21.751093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 14:48:21.751189 ==
6983 14:48:21.751278 DQS Delay:
6984 14:48:21.754571 DQS0 = 28, DQS1 = 36
6985 14:48:21.754665 DQM Delay:
6986 14:48:21.757512 DQM0 = 10, DQM1 = 14
6987 14:48:21.757584 DQ Delay:
6988 14:48:21.760876 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6989 14:48:21.764264 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6990 14:48:21.767692 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6991 14:48:21.771124 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6992 14:48:21.771220
6993 14:48:21.771309
6994 14:48:21.777474 [DQSOSCAuto] RK1, (LSB)MR18= 0xc354, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6995 14:48:21.780615 CH1 RK1: MR19=C0C, MR18=C354
6996 14:48:21.787163 CH1_RK1: MR19=0xC0C, MR18=0xC354, DQSOSC=385, MR23=63, INC=398, DEC=265
6997 14:48:21.790970 [RxdqsGatingPostProcess] freq 400
6998 14:48:21.794173 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6999 14:48:21.797378 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 14:48:21.800570 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 14:48:21.803793 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 14:48:21.806973 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 14:48:21.810311 best DQS0 dly(2T, 0.5T) = (0, 10)
7004 14:48:21.813495 best DQS1 dly(2T, 0.5T) = (0, 10)
7005 14:48:21.817446 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7006 14:48:21.820250 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7007 14:48:21.823622 Pre-setting of DQS Precalculation
7008 14:48:21.830559 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7009 14:48:21.837140 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7010 14:48:21.843575 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7011 14:48:21.843679
7012 14:48:21.843769
7013 14:48:21.846813 [Calibration Summary] 800 Mbps
7014 14:48:21.846913 CH 0, Rank 0
7015 14:48:21.849915 SW Impedance : PASS
7016 14:48:21.849988 DUTY Scan : NO K
7017 14:48:21.853774 ZQ Calibration : PASS
7018 14:48:21.856911 Jitter Meter : NO K
7019 14:48:21.856996 CBT Training : PASS
7020 14:48:21.860195 Write leveling : PASS
7021 14:48:21.863536 RX DQS gating : PASS
7022 14:48:21.863609 RX DQ/DQS(RDDQC) : PASS
7023 14:48:21.866871 TX DQ/DQS : PASS
7024 14:48:21.870333 RX DATLAT : PASS
7025 14:48:21.870444 RX DQ/DQS(Engine): PASS
7026 14:48:21.873194 TX OE : NO K
7027 14:48:21.873290 All Pass.
7028 14:48:21.873384
7029 14:48:21.876684 CH 0, Rank 1
7030 14:48:21.876757 SW Impedance : PASS
7031 14:48:21.880233 DUTY Scan : NO K
7032 14:48:21.883168 ZQ Calibration : PASS
7033 14:48:21.883267 Jitter Meter : NO K
7034 14:48:21.886740 CBT Training : PASS
7035 14:48:21.889823 Write leveling : NO K
7036 14:48:21.889932 RX DQS gating : PASS
7037 14:48:21.893474 RX DQ/DQS(RDDQC) : PASS
7038 14:48:21.896789 TX DQ/DQS : PASS
7039 14:48:21.896893 RX DATLAT : PASS
7040 14:48:21.900043 RX DQ/DQS(Engine): PASS
7041 14:48:21.900142 TX OE : NO K
7042 14:48:21.903033 All Pass.
7043 14:48:21.903129
7044 14:48:21.903220 CH 1, Rank 0
7045 14:48:21.906864 SW Impedance : PASS
7046 14:48:21.906958 DUTY Scan : NO K
7047 14:48:21.910133 ZQ Calibration : PASS
7048 14:48:21.913380 Jitter Meter : NO K
7049 14:48:21.913480 CBT Training : PASS
7050 14:48:21.916654 Write leveling : PASS
7051 14:48:21.919831 RX DQS gating : PASS
7052 14:48:21.919927 RX DQ/DQS(RDDQC) : PASS
7053 14:48:21.923227 TX DQ/DQS : PASS
7054 14:48:21.926456 RX DATLAT : PASS
7055 14:48:21.926550 RX DQ/DQS(Engine): PASS
7056 14:48:21.930253 TX OE : NO K
7057 14:48:21.930357 All Pass.
7058 14:48:21.930450
7059 14:48:21.933065 CH 1, Rank 1
7060 14:48:21.933154 SW Impedance : PASS
7061 14:48:21.936712 DUTY Scan : NO K
7062 14:48:21.939932 ZQ Calibration : PASS
7063 14:48:21.940036 Jitter Meter : NO K
7064 14:48:21.943050 CBT Training : PASS
7065 14:48:21.946305 Write leveling : NO K
7066 14:48:21.946408 RX DQS gating : PASS
7067 14:48:21.950034 RX DQ/DQS(RDDQC) : PASS
7068 14:48:21.950135 TX DQ/DQS : PASS
7069 14:48:21.953274 RX DATLAT : PASS
7070 14:48:21.956497 RX DQ/DQS(Engine): PASS
7071 14:48:21.956576 TX OE : NO K
7072 14:48:21.959614 All Pass.
7073 14:48:21.959686
7074 14:48:21.959746 DramC Write-DBI off
7075 14:48:21.963493 PER_BANK_REFRESH: Hybrid Mode
7076 14:48:21.966666 TX_TRACKING: ON
7077 14:48:21.973283 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7078 14:48:21.976295 [FAST_K] Save calibration result to emmc
7079 14:48:21.980129 dramc_set_vcore_voltage set vcore to 725000
7080 14:48:21.983281 Read voltage for 1600, 0
7081 14:48:21.983375 Vio18 = 0
7082 14:48:21.986467 Vcore = 725000
7083 14:48:21.986567 Vdram = 0
7084 14:48:21.986654 Vddq = 0
7085 14:48:21.989850 Vmddr = 0
7086 14:48:21.993394 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7087 14:48:21.999902 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7088 14:48:21.999986 MEM_TYPE=3, freq_sel=13
7089 14:48:22.003249 sv_algorithm_assistance_LP4_3733
7090 14:48:22.009501 ============ PULL DRAM RESETB DOWN ============
7091 14:48:22.013110 ========== PULL DRAM RESETB DOWN end =========
7092 14:48:22.016573 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7093 14:48:22.019669 ===================================
7094 14:48:22.022900 LPDDR4 DRAM CONFIGURATION
7095 14:48:22.026328 ===================================
7096 14:48:22.029483 EX_ROW_EN[0] = 0x0
7097 14:48:22.029567 EX_ROW_EN[1] = 0x0
7098 14:48:22.032910 LP4Y_EN = 0x0
7099 14:48:22.032995 WORK_FSP = 0x1
7100 14:48:22.035903 WL = 0x5
7101 14:48:22.035987 RL = 0x5
7102 14:48:22.039226 BL = 0x2
7103 14:48:22.039310 RPST = 0x0
7104 14:48:22.042703 RD_PRE = 0x0
7105 14:48:22.042787 WR_PRE = 0x1
7106 14:48:22.046073 WR_PST = 0x1
7107 14:48:22.046157 DBI_WR = 0x0
7108 14:48:22.049496 DBI_RD = 0x0
7109 14:48:22.049583 OTF = 0x1
7110 14:48:22.052694 ===================================
7111 14:48:22.056162 ===================================
7112 14:48:22.059708 ANA top config
7113 14:48:22.062763 ===================================
7114 14:48:22.065833 DLL_ASYNC_EN = 0
7115 14:48:22.065918 ALL_SLAVE_EN = 0
7116 14:48:22.069625 NEW_RANK_MODE = 1
7117 14:48:22.072821 DLL_IDLE_MODE = 1
7118 14:48:22.076053 LP45_APHY_COMB_EN = 1
7119 14:48:22.076136 TX_ODT_DIS = 0
7120 14:48:22.079278 NEW_8X_MODE = 1
7121 14:48:22.082485 ===================================
7122 14:48:22.085720 ===================================
7123 14:48:22.089502 data_rate = 3200
7124 14:48:22.092764 CKR = 1
7125 14:48:22.095717 DQ_P2S_RATIO = 8
7126 14:48:22.098991 ===================================
7127 14:48:22.102649 CA_P2S_RATIO = 8
7128 14:48:22.102748 DQ_CA_OPEN = 0
7129 14:48:22.105844 DQ_SEMI_OPEN = 0
7130 14:48:22.108893 CA_SEMI_OPEN = 0
7131 14:48:22.112537 CA_FULL_RATE = 0
7132 14:48:22.116189 DQ_CKDIV4_EN = 0
7133 14:48:22.119132 CA_CKDIV4_EN = 0
7134 14:48:22.119212 CA_PREDIV_EN = 0
7135 14:48:22.122566 PH8_DLY = 12
7136 14:48:22.125558 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7137 14:48:22.128680 DQ_AAMCK_DIV = 4
7138 14:48:22.132552 CA_AAMCK_DIV = 4
7139 14:48:22.135765 CA_ADMCK_DIV = 4
7140 14:48:22.135866 DQ_TRACK_CA_EN = 0
7141 14:48:22.139003 CA_PICK = 1600
7142 14:48:22.142302 CA_MCKIO = 1600
7143 14:48:22.145604 MCKIO_SEMI = 0
7144 14:48:22.148795 PLL_FREQ = 3068
7145 14:48:22.152367 DQ_UI_PI_RATIO = 32
7146 14:48:22.155286 CA_UI_PI_RATIO = 0
7147 14:48:22.159047 ===================================
7148 14:48:22.162426 ===================================
7149 14:48:22.162598 memory_type:LPDDR4
7150 14:48:22.165753 GP_NUM : 10
7151 14:48:22.168969 SRAM_EN : 1
7152 14:48:22.169074 MD32_EN : 0
7153 14:48:22.172684 ===================================
7154 14:48:22.175891 [ANA_INIT] >>>>>>>>>>>>>>
7155 14:48:22.179057 <<<<<< [CONFIGURE PHASE]: ANA_TX
7156 14:48:22.182291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7157 14:48:22.185680 ===================================
7158 14:48:22.188743 data_rate = 3200,PCW = 0X7600
7159 14:48:22.192560 ===================================
7160 14:48:22.195744 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7161 14:48:22.198969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 14:48:22.205673 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 14:48:22.209398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7164 14:48:22.212718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7165 14:48:22.215929 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7166 14:48:22.219128 [ANA_INIT] flow start
7167 14:48:22.222370 [ANA_INIT] PLL >>>>>>>>
7168 14:48:22.222915 [ANA_INIT] PLL <<<<<<<<
7169 14:48:22.225749 [ANA_INIT] MIDPI >>>>>>>>
7170 14:48:22.228991 [ANA_INIT] MIDPI <<<<<<<<
7171 14:48:22.229438 [ANA_INIT] DLL >>>>>>>>
7172 14:48:22.232689 [ANA_INIT] DLL <<<<<<<<
7173 14:48:22.236452 [ANA_INIT] flow end
7174 14:48:22.239402 ============ LP4 DIFF to SE enter ============
7175 14:48:22.242824 ============ LP4 DIFF to SE exit ============
7176 14:48:22.246054 [ANA_INIT] <<<<<<<<<<<<<
7177 14:48:22.249070 [Flow] Enable top DCM control >>>>>
7178 14:48:22.252518 [Flow] Enable top DCM control <<<<<
7179 14:48:22.255797 Enable DLL master slave shuffle
7180 14:48:22.259320 ==============================================================
7181 14:48:22.262474 Gating Mode config
7182 14:48:22.269069 ==============================================================
7183 14:48:22.269670 Config description:
7184 14:48:22.279206 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7185 14:48:22.285865 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7186 14:48:22.292090 SELPH_MODE 0: By rank 1: By Phase
7187 14:48:22.295321 ==============================================================
7188 14:48:22.298388 GAT_TRACK_EN = 1
7189 14:48:22.302130 RX_GATING_MODE = 2
7190 14:48:22.305393 RX_GATING_TRACK_MODE = 2
7191 14:48:22.308623 SELPH_MODE = 1
7192 14:48:22.311993 PICG_EARLY_EN = 1
7193 14:48:22.314899 VALID_LAT_VALUE = 1
7194 14:48:22.318569 ==============================================================
7195 14:48:22.322264 Enter into Gating configuration >>>>
7196 14:48:22.325302 Exit from Gating configuration <<<<
7197 14:48:22.328845 Enter into DVFS_PRE_config >>>>>
7198 14:48:22.342014 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7199 14:48:22.344782 Exit from DVFS_PRE_config <<<<<
7200 14:48:22.348657 Enter into PICG configuration >>>>
7201 14:48:22.349255 Exit from PICG configuration <<<<
7202 14:48:22.351992 [RX_INPUT] configuration >>>>>
7203 14:48:22.355208 [RX_INPUT] configuration <<<<<
7204 14:48:22.362291 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7205 14:48:22.364894 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7206 14:48:22.372106 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7207 14:48:22.378652 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7208 14:48:22.384995 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7209 14:48:22.392128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7210 14:48:22.395120 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7211 14:48:22.398214 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7212 14:48:22.401847 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7213 14:48:22.408577 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7214 14:48:22.411901 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7215 14:48:22.414998 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 14:48:22.418281 ===================================
7217 14:48:22.421702 LPDDR4 DRAM CONFIGURATION
7218 14:48:22.425017 ===================================
7219 14:48:22.428474 EX_ROW_EN[0] = 0x0
7220 14:48:22.428898 EX_ROW_EN[1] = 0x0
7221 14:48:22.431441 LP4Y_EN = 0x0
7222 14:48:22.431860 WORK_FSP = 0x1
7223 14:48:22.435122 WL = 0x5
7224 14:48:22.435557 RL = 0x5
7225 14:48:22.438595 BL = 0x2
7226 14:48:22.439199 RPST = 0x0
7227 14:48:22.441486 RD_PRE = 0x0
7228 14:48:22.441906 WR_PRE = 0x1
7229 14:48:22.444854 WR_PST = 0x1
7230 14:48:22.445275 DBI_WR = 0x0
7231 14:48:22.448052 DBI_RD = 0x0
7232 14:48:22.448680 OTF = 0x1
7233 14:48:22.451929 ===================================
7234 14:48:22.458227 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7235 14:48:22.461718 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7236 14:48:22.465197 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 14:48:22.468193 ===================================
7238 14:48:22.471435 LPDDR4 DRAM CONFIGURATION
7239 14:48:22.474584 ===================================
7240 14:48:22.475020 EX_ROW_EN[0] = 0x10
7241 14:48:22.478006 EX_ROW_EN[1] = 0x0
7242 14:48:22.481550 LP4Y_EN = 0x0
7243 14:48:22.481972 WORK_FSP = 0x1
7244 14:48:22.484600 WL = 0x5
7245 14:48:22.485220 RL = 0x5
7246 14:48:22.488174 BL = 0x2
7247 14:48:22.488684 RPST = 0x0
7248 14:48:22.491212 RD_PRE = 0x0
7249 14:48:22.491755 WR_PRE = 0x1
7250 14:48:22.495065 WR_PST = 0x1
7251 14:48:22.495612 DBI_WR = 0x0
7252 14:48:22.498286 DBI_RD = 0x0
7253 14:48:22.498906 OTF = 0x1
7254 14:48:22.501507 ===================================
7255 14:48:22.508406 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7256 14:48:22.508831 ==
7257 14:48:22.511583 Dram Type= 6, Freq= 0, CH_0, rank 0
7258 14:48:22.514822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7259 14:48:22.515238 ==
7260 14:48:22.518538 [Duty_Offset_Calibration]
7261 14:48:22.521744 B0:2 B1:1 CA:1
7262 14:48:22.522264
7263 14:48:22.524582 [DutyScan_Calibration_Flow] k_type=0
7264 14:48:22.533783
7265 14:48:22.534298 ==CLK 0==
7266 14:48:22.536947 Final CLK duty delay cell = 0
7267 14:48:22.540025 [0] MAX Duty = 5156%(X100), DQS PI = 22
7268 14:48:22.543781 [0] MIN Duty = 4907%(X100), DQS PI = 0
7269 14:48:22.544210 [0] AVG Duty = 5031%(X100)
7270 14:48:22.547011
7271 14:48:22.547431 CH0 CLK Duty spec in!! Max-Min= 249%
7272 14:48:22.553230 [DutyScan_Calibration_Flow] ====Done====
7273 14:48:22.553656
7274 14:48:22.556740 [DutyScan_Calibration_Flow] k_type=1
7275 14:48:22.572748
7276 14:48:22.573174 ==DQS 0 ==
7277 14:48:22.576002 Final DQS duty delay cell = -4
7278 14:48:22.579048 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7279 14:48:22.582357 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7280 14:48:22.585477 [-4] AVG Duty = 4891%(X100)
7281 14:48:22.585903
7282 14:48:22.586230 ==DQS 1 ==
7283 14:48:22.589336 Final DQS duty delay cell = 0
7284 14:48:22.592300 [0] MAX Duty = 5187%(X100), DQS PI = 2
7285 14:48:22.595718 [0] MIN Duty = 5031%(X100), DQS PI = 52
7286 14:48:22.599160 [0] AVG Duty = 5109%(X100)
7287 14:48:22.599582
7288 14:48:22.602772 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7289 14:48:22.603199
7290 14:48:22.605961 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7291 14:48:22.609229 [DutyScan_Calibration_Flow] ====Done====
7292 14:48:22.609652
7293 14:48:22.612540 [DutyScan_Calibration_Flow] k_type=3
7294 14:48:22.629532
7295 14:48:22.630059 ==DQM 0 ==
7296 14:48:22.632175 Final DQM duty delay cell = 0
7297 14:48:22.635944 [0] MAX Duty = 5218%(X100), DQS PI = 34
7298 14:48:22.639080 [0] MIN Duty = 4844%(X100), DQS PI = 60
7299 14:48:22.642330 [0] AVG Duty = 5031%(X100)
7300 14:48:22.642752
7301 14:48:22.643081 ==DQM 1 ==
7302 14:48:22.645784 Final DQM duty delay cell = -4
7303 14:48:22.648599 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7304 14:48:22.652661 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7305 14:48:22.655945 [-4] AVG Duty = 4891%(X100)
7306 14:48:22.656406
7307 14:48:22.659354 CH0 DQM 0 Duty spec in!! Max-Min= 374%
7308 14:48:22.659887
7309 14:48:22.662333 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7310 14:48:22.665597 [DutyScan_Calibration_Flow] ====Done====
7311 14:48:22.666020
7312 14:48:22.668562 [DutyScan_Calibration_Flow] k_type=2
7313 14:48:22.687083
7314 14:48:22.687663 ==DQ 0 ==
7315 14:48:22.690519 Final DQ duty delay cell = 0
7316 14:48:22.693206 [0] MAX Duty = 5062%(X100), DQS PI = 26
7317 14:48:22.697027 [0] MIN Duty = 4907%(X100), DQS PI = 0
7318 14:48:22.697485 [0] AVG Duty = 4984%(X100)
7319 14:48:22.700260
7320 14:48:22.700770 ==DQ 1 ==
7321 14:48:22.703395 Final DQ duty delay cell = 0
7322 14:48:22.706486 [0] MAX Duty = 5125%(X100), DQS PI = 6
7323 14:48:22.710066 [0] MIN Duty = 4938%(X100), DQS PI = 34
7324 14:48:22.710710 [0] AVG Duty = 5031%(X100)
7325 14:48:22.711081
7326 14:48:22.713289 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7327 14:48:22.716401
7328 14:48:22.720183 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7329 14:48:22.723127 [DutyScan_Calibration_Flow] ====Done====
7330 14:48:22.723582 ==
7331 14:48:22.726257 Dram Type= 6, Freq= 0, CH_1, rank 0
7332 14:48:22.730179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7333 14:48:22.730591 ==
7334 14:48:22.733346 [Duty_Offset_Calibration]
7335 14:48:22.733768 B0:1 B1:0 CA:1
7336 14:48:22.734210
7337 14:48:22.736397 [DutyScan_Calibration_Flow] k_type=0
7338 14:48:22.746072
7339 14:48:22.746612 ==CLK 0==
7340 14:48:22.749431 Final CLK duty delay cell = -4
7341 14:48:22.752642 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7342 14:48:22.755976 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7343 14:48:22.759364 [-4] AVG Duty = 4938%(X100)
7344 14:48:22.759784
7345 14:48:22.762547 CH1 CLK Duty spec in!! Max-Min= 124%
7346 14:48:22.765782 [DutyScan_Calibration_Flow] ====Done====
7347 14:48:22.766202
7348 14:48:22.768973 [DutyScan_Calibration_Flow] k_type=1
7349 14:48:22.786001
7350 14:48:22.786511 ==DQS 0 ==
7351 14:48:22.789486 Final DQS duty delay cell = 0
7352 14:48:22.792587 [0] MAX Duty = 5094%(X100), DQS PI = 18
7353 14:48:22.795640 [0] MIN Duty = 4844%(X100), DQS PI = 42
7354 14:48:22.799037 [0] AVG Duty = 4969%(X100)
7355 14:48:22.799475
7356 14:48:22.799799 ==DQS 1 ==
7357 14:48:22.802504 Final DQS duty delay cell = 0
7358 14:48:22.806144 [0] MAX Duty = 5249%(X100), DQS PI = 18
7359 14:48:22.809350 [0] MIN Duty = 4938%(X100), DQS PI = 8
7360 14:48:22.812379 [0] AVG Duty = 5093%(X100)
7361 14:48:22.812806
7362 14:48:22.816477 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7363 14:48:22.816923
7364 14:48:22.819363 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7365 14:48:22.822405 [DutyScan_Calibration_Flow] ====Done====
7366 14:48:22.822877
7367 14:48:22.825793 [DutyScan_Calibration_Flow] k_type=3
7368 14:48:22.842747
7369 14:48:22.843218 ==DQM 0 ==
7370 14:48:22.846110 Final DQM duty delay cell = 0
7371 14:48:22.849817 [0] MAX Duty = 5187%(X100), DQS PI = 8
7372 14:48:22.852832 [0] MIN Duty = 4969%(X100), DQS PI = 48
7373 14:48:22.853309 [0] AVG Duty = 5078%(X100)
7374 14:48:22.856317
7375 14:48:22.856814 ==DQM 1 ==
7376 14:48:22.859164 Final DQM duty delay cell = 0
7377 14:48:22.862875 [0] MAX Duty = 5093%(X100), DQS PI = 16
7378 14:48:22.866028 [0] MIN Duty = 4907%(X100), DQS PI = 50
7379 14:48:22.869123 [0] AVG Duty = 5000%(X100)
7380 14:48:22.869563
7381 14:48:22.872946 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7382 14:48:22.873497
7383 14:48:22.876297 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7384 14:48:22.879659 [DutyScan_Calibration_Flow] ====Done====
7385 14:48:22.880235
7386 14:48:22.882605 [DutyScan_Calibration_Flow] k_type=2
7387 14:48:22.898804
7388 14:48:22.899459 ==DQ 0 ==
7389 14:48:22.902428 Final DQ duty delay cell = -4
7390 14:48:22.905479 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7391 14:48:22.908902 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7392 14:48:22.912389 [-4] AVG Duty = 4953%(X100)
7393 14:48:22.912818
7394 14:48:22.913145 ==DQ 1 ==
7395 14:48:22.915413 Final DQ duty delay cell = 0
7396 14:48:22.918795 [0] MAX Duty = 5156%(X100), DQS PI = 18
7397 14:48:22.921691 [0] MIN Duty = 4938%(X100), DQS PI = 8
7398 14:48:22.925458 [0] AVG Duty = 5047%(X100)
7399 14:48:22.926018
7400 14:48:22.928249 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7401 14:48:22.928849
7402 14:48:22.931755 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7403 14:48:22.935098 [DutyScan_Calibration_Flow] ====Done====
7404 14:48:22.938594 nWR fixed to 30
7405 14:48:22.941726 [ModeRegInit_LP4] CH0 RK0
7406 14:48:22.942135 [ModeRegInit_LP4] CH0 RK1
7407 14:48:22.945115 [ModeRegInit_LP4] CH1 RK0
7408 14:48:22.949089 [ModeRegInit_LP4] CH1 RK1
7409 14:48:22.949610 match AC timing 5
7410 14:48:22.954753 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7411 14:48:22.958309 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7412 14:48:22.961610 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7413 14:48:22.968609 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7414 14:48:22.971594 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7415 14:48:22.972127 [MiockJmeterHQA]
7416 14:48:22.972592
7417 14:48:22.974860 [DramcMiockJmeter] u1RxGatingPI = 0
7418 14:48:22.978447 0 : 4363, 4137
7419 14:48:22.978875 4 : 4362, 4137
7420 14:48:22.981987 8 : 4253, 4026
7421 14:48:22.982512 12 : 4252, 4026
7422 14:48:22.984997 16 : 4363, 4140
7423 14:48:22.985430 20 : 4252, 4027
7424 14:48:22.985766 24 : 4252, 4027
7425 14:48:22.988156 28 : 4252, 4027
7426 14:48:22.988648 32 : 4363, 4137
7427 14:48:22.991297 36 : 4366, 4140
7428 14:48:22.991724 40 : 4252, 4026
7429 14:48:22.994591 44 : 4252, 4027
7430 14:48:22.995019 48 : 4252, 4027
7431 14:48:22.998480 52 : 4252, 4026
7432 14:48:22.998909 56 : 4252, 4027
7433 14:48:22.999249 60 : 4362, 4137
7434 14:48:23.001321 64 : 4250, 4026
7435 14:48:23.001751 68 : 4249, 4027
7436 14:48:23.004878 72 : 4250, 4026
7437 14:48:23.005308 76 : 4250, 4027
7438 14:48:23.008372 80 : 4249, 4027
7439 14:48:23.008966 84 : 4361, 4134
7440 14:48:23.009504 88 : 4360, 152
7441 14:48:23.011358 92 : 4249, 0
7442 14:48:23.011925 96 : 4363, 0
7443 14:48:23.014744 100 : 4250, 0
7444 14:48:23.015177 104 : 4250, 0
7445 14:48:23.015549 108 : 4360, 0
7446 14:48:23.017930 112 : 4360, 0
7447 14:48:23.018361 116 : 4360, 0
7448 14:48:23.021186 120 : 4250, 0
7449 14:48:23.021616 124 : 4250, 0
7450 14:48:23.021952 128 : 4249, 0
7451 14:48:23.024318 132 : 4250, 0
7452 14:48:23.024789 136 : 4250, 0
7453 14:48:23.028007 140 : 4250, 0
7454 14:48:23.028590 144 : 4250, 0
7455 14:48:23.028937 148 : 4250, 0
7456 14:48:23.030822 152 : 4250, 0
7457 14:48:23.031251 156 : 4252, 0
7458 14:48:23.031586 160 : 4360, 0
7459 14:48:23.034218 164 : 4361, 0
7460 14:48:23.034650 168 : 4360, 0
7461 14:48:23.037924 172 : 4250, 0
7462 14:48:23.038376 176 : 4250, 0
7463 14:48:23.038709 180 : 4363, 0
7464 14:48:23.041243 184 : 4250, 0
7465 14:48:23.041673 188 : 4250, 0
7466 14:48:23.044633 192 : 4250, 0
7467 14:48:23.045201 196 : 4252, 0
7468 14:48:23.045598 200 : 4250, 0
7469 14:48:23.047613 204 : 4250, 1124
7470 14:48:23.048227 208 : 4250, 3993
7471 14:48:23.050838 212 : 4250, 4026
7472 14:48:23.051262 216 : 4253, 4029
7473 14:48:23.054521 220 : 4250, 4027
7474 14:48:23.054947 224 : 4250, 4027
7475 14:48:23.057716 228 : 4363, 4140
7476 14:48:23.058140 232 : 4250, 4027
7477 14:48:23.060917 236 : 4249, 4027
7478 14:48:23.061338 240 : 4363, 4140
7479 14:48:23.064058 244 : 4250, 4027
7480 14:48:23.064529 248 : 4250, 4026
7481 14:48:23.064872 252 : 4360, 4138
7482 14:48:23.068002 256 : 4249, 4027
7483 14:48:23.068464 260 : 4250, 4027
7484 14:48:23.070611 264 : 4250, 4027
7485 14:48:23.071037 268 : 4250, 4027
7486 14:48:23.073884 272 : 4249, 4027
7487 14:48:23.074383 276 : 4250, 4027
7488 14:48:23.077623 280 : 4361, 4137
7489 14:48:23.078046 284 : 4250, 4027
7490 14:48:23.080638 288 : 4249, 4027
7491 14:48:23.081061 292 : 4360, 4137
7492 14:48:23.084187 296 : 4250, 4027
7493 14:48:23.084724 300 : 4250, 4027
7494 14:48:23.087201 304 : 4360, 4138
7495 14:48:23.087799 308 : 4249, 3984
7496 14:48:23.088416 312 : 4250, 1997
7497 14:48:23.090601
7498 14:48:23.091104 MIOCK jitter meter ch=0
7499 14:48:23.091440
7500 14:48:23.093942 1T = (312-88) = 224 dly cells
7501 14:48:23.100857 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7502 14:48:23.101278 ==
7503 14:48:23.104116 Dram Type= 6, Freq= 0, CH_0, rank 0
7504 14:48:23.107701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 14:48:23.108118 ==
7506 14:48:23.113967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 14:48:23.117304 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 14:48:23.120951 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 14:48:23.127476 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 14:48:23.136769 [CA 0] Center 42 (12~73) winsize 62
7511 14:48:23.139968 [CA 1] Center 42 (12~73) winsize 62
7512 14:48:23.143058 [CA 2] Center 37 (8~67) winsize 60
7513 14:48:23.146567 [CA 3] Center 37 (7~67) winsize 61
7514 14:48:23.149609 [CA 4] Center 36 (6~66) winsize 61
7515 14:48:23.153463 [CA 5] Center 35 (6~64) winsize 59
7516 14:48:23.153882
7517 14:48:23.156403 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 14:48:23.156939
7519 14:48:23.160103 [CATrainingPosCal] consider 1 rank data
7520 14:48:23.163393 u2DelayCellTimex100 = 290/100 ps
7521 14:48:23.166394 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7522 14:48:23.173381 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7523 14:48:23.176626 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 14:48:23.180101 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7525 14:48:23.183104 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7526 14:48:23.186230 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7527 14:48:23.186653
7528 14:48:23.189898 CA PerBit enable=1, Macro0, CA PI delay=35
7529 14:48:23.190331
7530 14:48:23.193086 [CBTSetCACLKResult] CA Dly = 35
7531 14:48:23.193505 CS Dly: 9 (0~40)
7532 14:48:23.199983 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 14:48:23.203404 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 14:48:23.204030 ==
7535 14:48:23.206674 Dram Type= 6, Freq= 0, CH_0, rank 1
7536 14:48:23.209701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 14:48:23.210231 ==
7538 14:48:23.216097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 14:48:23.219938 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 14:48:23.226405 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 14:48:23.229422 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 14:48:23.239694 [CA 0] Center 42 (12~73) winsize 62
7543 14:48:23.242843 [CA 1] Center 42 (12~73) winsize 62
7544 14:48:23.246200 [CA 2] Center 37 (8~67) winsize 60
7545 14:48:23.249893 [CA 3] Center 38 (8~68) winsize 61
7546 14:48:23.253048 [CA 4] Center 35 (5~65) winsize 61
7547 14:48:23.256626 [CA 5] Center 35 (5~65) winsize 61
7548 14:48:23.257080
7549 14:48:23.259687 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7550 14:48:23.260104
7551 14:48:23.262898 [CATrainingPosCal] consider 2 rank data
7552 14:48:23.265877 u2DelayCellTimex100 = 290/100 ps
7553 14:48:23.269233 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7554 14:48:23.275924 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7555 14:48:23.279265 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7556 14:48:23.282748 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7557 14:48:23.285886 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7558 14:48:23.289358 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7559 14:48:23.289782
7560 14:48:23.292540 CA PerBit enable=1, Macro0, CA PI delay=35
7561 14:48:23.292961
7562 14:48:23.296255 [CBTSetCACLKResult] CA Dly = 35
7563 14:48:23.299538 CS Dly: 10 (0~42)
7564 14:48:23.302825 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 14:48:23.306028 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 14:48:23.306447
7567 14:48:23.309207 ----->DramcWriteLeveling(PI) begin...
7568 14:48:23.309633 ==
7569 14:48:23.312887 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 14:48:23.319014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 14:48:23.319435 ==
7572 14:48:23.322671 Write leveling (Byte 0): 36 => 36
7573 14:48:23.323089 Write leveling (Byte 1): 27 => 27
7574 14:48:23.325891 DramcWriteLeveling(PI) end<-----
7575 14:48:23.326308
7576 14:48:23.329123 ==
7577 14:48:23.329542 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 14:48:23.335566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 14:48:23.335985 ==
7580 14:48:23.339443 [Gating] SW mode calibration
7581 14:48:23.346163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7582 14:48:23.349190 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7583 14:48:23.356071 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7584 14:48:23.359168 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7585 14:48:23.362777 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7586 14:48:23.369209 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7587 14:48:23.372566 1 4 16 | B1->B0 | 2626 3535 | 1 1 | (1 1) (1 1)
7588 14:48:23.375464 1 4 20 | B1->B0 | 3232 3636 | 1 1 | (1 1) (1 1)
7589 14:48:23.382784 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7590 14:48:23.385861 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7591 14:48:23.389455 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7592 14:48:23.395745 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7593 14:48:23.398784 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 0)
7594 14:48:23.402055 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
7595 14:48:23.405774 1 5 16 | B1->B0 | 3333 2424 | 1 1 | (1 1) (1 0)
7596 14:48:23.412279 1 5 20 | B1->B0 | 2b2b 2626 | 0 0 | (1 0) (0 0)
7597 14:48:23.415403 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
7598 14:48:23.418698 1 5 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7599 14:48:23.425950 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7600 14:48:23.428993 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7601 14:48:23.432470 1 6 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
7602 14:48:23.438548 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7603 14:48:23.441932 1 6 16 | B1->B0 | 2b2b 4545 | 0 1 | (0 0) (0 0)
7604 14:48:23.445771 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7605 14:48:23.452007 1 6 24 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
7606 14:48:23.455567 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 14:48:23.459328 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 14:48:23.465836 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 14:48:23.469009 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 14:48:23.472199 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 14:48:23.479000 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7612 14:48:23.481945 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 14:48:23.485686 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 14:48:23.491723 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 14:48:23.495689 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 14:48:23.498901 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 14:48:23.505285 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 14:48:23.508705 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 14:48:23.511940 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 14:48:23.518361 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 14:48:23.521473 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 14:48:23.524691 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 14:48:23.531861 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 14:48:23.534831 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 14:48:23.538275 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 14:48:23.544488 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 14:48:23.548295 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7628 14:48:23.551150 Total UI for P1: 0, mck2ui 16
7629 14:48:23.554822 best dqsien dly found for B0: ( 1, 9, 12)
7630 14:48:23.558095 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 14:48:23.561097 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 14:48:23.564609 Total UI for P1: 0, mck2ui 16
7633 14:48:23.568402 best dqsien dly found for B1: ( 1, 9, 20)
7634 14:48:23.571559 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7635 14:48:23.578122 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7636 14:48:23.578543
7637 14:48:23.581386 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7638 14:48:23.584454 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7639 14:48:23.587652 [Gating] SW calibration Done
7640 14:48:23.588111 ==
7641 14:48:23.591469 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 14:48:23.594703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 14:48:23.595127 ==
7644 14:48:23.597585 RX Vref Scan: 0
7645 14:48:23.598002
7646 14:48:23.598324 RX Vref 0 -> 0, step: 1
7647 14:48:23.598623
7648 14:48:23.601690 RX Delay 0 -> 252, step: 8
7649 14:48:23.605014 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7650 14:48:23.608111 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7651 14:48:23.614794 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7652 14:48:23.618203 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7653 14:48:23.621182 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7654 14:48:23.624271 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7655 14:48:23.628057 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7656 14:48:23.634471 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7657 14:48:23.637668 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7658 14:48:23.641423 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7659 14:48:23.644658 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7660 14:48:23.647640 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7661 14:48:23.654481 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7662 14:48:23.658147 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7663 14:48:23.661344 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7664 14:48:23.664328 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7665 14:48:23.664814 ==
7666 14:48:23.667637 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 14:48:23.674675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 14:48:23.675097 ==
7669 14:48:23.675467 DQS Delay:
7670 14:48:23.675801 DQS0 = 0, DQS1 = 0
7671 14:48:23.677692 DQM Delay:
7672 14:48:23.678108 DQM0 = 137, DQM1 = 129
7673 14:48:23.681350 DQ Delay:
7674 14:48:23.684202 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7675 14:48:23.688010 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7676 14:48:23.691194 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7677 14:48:23.694429 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7678 14:48:23.694848
7679 14:48:23.695171
7680 14:48:23.695470 ==
7681 14:48:23.697599 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 14:48:23.700727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 14:48:23.704442 ==
7684 14:48:23.704867
7685 14:48:23.705393
7686 14:48:23.706012 TX Vref Scan disable
7687 14:48:23.707474 == TX Byte 0 ==
7688 14:48:23.710835 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7689 14:48:23.714201 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7690 14:48:23.717484 == TX Byte 1 ==
7691 14:48:23.720894 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7692 14:48:23.724398 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7693 14:48:23.727709 ==
7694 14:48:23.728129 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 14:48:23.733836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 14:48:23.734140 ==
7697 14:48:23.746732
7698 14:48:23.750482 TX Vref early break, caculate TX vref
7699 14:48:23.753754 TX Vref=16, minBit 7, minWin=22, winSum=381
7700 14:48:23.756663 TX Vref=18, minBit 0, minWin=23, winSum=389
7701 14:48:23.759856 TX Vref=20, minBit 7, minWin=23, winSum=397
7702 14:48:23.763457 TX Vref=22, minBit 0, minWin=24, winSum=408
7703 14:48:23.766934 TX Vref=24, minBit 2, minWin=24, winSum=412
7704 14:48:23.773648 TX Vref=26, minBit 2, minWin=25, winSum=422
7705 14:48:23.776725 TX Vref=28, minBit 1, minWin=25, winSum=422
7706 14:48:23.779924 TX Vref=30, minBit 0, minWin=25, winSum=417
7707 14:48:23.783625 TX Vref=32, minBit 6, minWin=23, winSum=400
7708 14:48:23.788882 TX Vref=34, minBit 1, minWin=23, winSum=394
7709 14:48:23.793716 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 26
7710 14:48:23.794158
7711 14:48:23.796806 Final TX Range 0 Vref 26
7712 14:48:23.797333
7713 14:48:23.797664 ==
7714 14:48:23.800094 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 14:48:23.803223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 14:48:23.803883 ==
7717 14:48:23.804236
7718 14:48:23.804591
7719 14:48:23.806783 TX Vref Scan disable
7720 14:48:23.813088 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7721 14:48:23.813509 == TX Byte 0 ==
7722 14:48:23.816243 u2DelayCellOfst[0]=10 cells (3 PI)
7723 14:48:23.820104 u2DelayCellOfst[1]=13 cells (4 PI)
7724 14:48:23.823365 u2DelayCellOfst[2]=10 cells (3 PI)
7725 14:48:23.826497 u2DelayCellOfst[3]=10 cells (3 PI)
7726 14:48:23.829816 u2DelayCellOfst[4]=6 cells (2 PI)
7727 14:48:23.832997 u2DelayCellOfst[5]=0 cells (0 PI)
7728 14:48:23.836178 u2DelayCellOfst[6]=16 cells (5 PI)
7729 14:48:23.839971 u2DelayCellOfst[7]=16 cells (5 PI)
7730 14:48:23.843086 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7731 14:48:23.846451 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7732 14:48:23.849592 == TX Byte 1 ==
7733 14:48:23.849818 u2DelayCellOfst[8]=0 cells (0 PI)
7734 14:48:23.852816 u2DelayCellOfst[9]=3 cells (1 PI)
7735 14:48:23.855961 u2DelayCellOfst[10]=6 cells (2 PI)
7736 14:48:23.859385 u2DelayCellOfst[11]=3 cells (1 PI)
7737 14:48:23.862967 u2DelayCellOfst[12]=10 cells (3 PI)
7738 14:48:23.866298 u2DelayCellOfst[13]=10 cells (3 PI)
7739 14:48:23.869523 u2DelayCellOfst[14]=13 cells (4 PI)
7740 14:48:23.872565 u2DelayCellOfst[15]=13 cells (4 PI)
7741 14:48:23.875711 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7742 14:48:23.882726 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7743 14:48:23.882859 DramC Write-DBI on
7744 14:48:23.882980 ==
7745 14:48:23.886004 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 14:48:23.889143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 14:48:23.892252 ==
7748 14:48:23.892334
7749 14:48:23.892437
7750 14:48:23.892497 TX Vref Scan disable
7751 14:48:23.896319 == TX Byte 0 ==
7752 14:48:23.899340 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7753 14:48:23.902550 == TX Byte 1 ==
7754 14:48:23.906357 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7755 14:48:23.909415 DramC Write-DBI off
7756 14:48:23.909496
7757 14:48:23.909558 [DATLAT]
7758 14:48:23.909616 Freq=1600, CH0 RK0
7759 14:48:23.909671
7760 14:48:23.912932 DATLAT Default: 0xf
7761 14:48:23.913013 0, 0xFFFF, sum = 0
7762 14:48:23.916484 1, 0xFFFF, sum = 0
7763 14:48:23.919617 2, 0xFFFF, sum = 0
7764 14:48:23.919698 3, 0xFFFF, sum = 0
7765 14:48:23.922690 4, 0xFFFF, sum = 0
7766 14:48:23.922854 5, 0xFFFF, sum = 0
7767 14:48:23.926318 6, 0xFFFF, sum = 0
7768 14:48:23.926468 7, 0xFFFF, sum = 0
7769 14:48:23.929686 8, 0xFFFF, sum = 0
7770 14:48:23.929853 9, 0xFFFF, sum = 0
7771 14:48:23.932834 10, 0xFFFF, sum = 0
7772 14:48:23.932917 11, 0xFFFF, sum = 0
7773 14:48:23.936324 12, 0xFFFF, sum = 0
7774 14:48:23.936420 13, 0xFFFF, sum = 0
7775 14:48:23.939589 14, 0x0, sum = 1
7776 14:48:23.939715 15, 0x0, sum = 2
7777 14:48:23.942648 16, 0x0, sum = 3
7778 14:48:23.942774 17, 0x0, sum = 4
7779 14:48:23.946362 best_step = 15
7780 14:48:23.946462
7781 14:48:23.946540 ==
7782 14:48:23.949549 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 14:48:23.952837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 14:48:23.952948 ==
7785 14:48:23.956129 RX Vref Scan: 1
7786 14:48:23.956249
7787 14:48:23.956356 Set Vref Range= 24 -> 127
7788 14:48:23.956448
7789 14:48:23.959546 RX Vref 24 -> 127, step: 1
7790 14:48:23.959680
7791 14:48:23.962700 RX Delay 19 -> 252, step: 4
7792 14:48:23.962833
7793 14:48:23.966333 Set Vref, RX VrefLevel [Byte0]: 24
7794 14:48:23.969160 [Byte1]: 24
7795 14:48:23.969241
7796 14:48:23.972261 Set Vref, RX VrefLevel [Byte0]: 25
7797 14:48:23.976149 [Byte1]: 25
7798 14:48:23.976256
7799 14:48:23.979428 Set Vref, RX VrefLevel [Byte0]: 26
7800 14:48:23.982633 [Byte1]: 26
7801 14:48:23.986590
7802 14:48:23.986671 Set Vref, RX VrefLevel [Byte0]: 27
7803 14:48:23.989523 [Byte1]: 27
7804 14:48:23.993705
7805 14:48:23.993787 Set Vref, RX VrefLevel [Byte0]: 28
7806 14:48:23.997170 [Byte1]: 28
7807 14:48:24.001936
7808 14:48:24.002039 Set Vref, RX VrefLevel [Byte0]: 29
7809 14:48:24.004885 [Byte1]: 29
7810 14:48:24.009512
7811 14:48:24.009617 Set Vref, RX VrefLevel [Byte0]: 30
7812 14:48:24.012670 [Byte1]: 30
7813 14:48:24.016566
7814 14:48:24.016651 Set Vref, RX VrefLevel [Byte0]: 31
7815 14:48:24.019911 [Byte1]: 31
7816 14:48:24.024464
7817 14:48:24.024575 Set Vref, RX VrefLevel [Byte0]: 32
7818 14:48:24.027642 [Byte1]: 32
7819 14:48:24.032312
7820 14:48:24.032432 Set Vref, RX VrefLevel [Byte0]: 33
7821 14:48:24.035374 [Byte1]: 33
7822 14:48:24.039946
7823 14:48:24.040079 Set Vref, RX VrefLevel [Byte0]: 34
7824 14:48:24.043126 [Byte1]: 34
7825 14:48:24.047523
7826 14:48:24.047673 Set Vref, RX VrefLevel [Byte0]: 35
7827 14:48:24.050867 [Byte1]: 35
7828 14:48:24.054997
7829 14:48:24.055233 Set Vref, RX VrefLevel [Byte0]: 36
7830 14:48:24.057954 [Byte1]: 36
7831 14:48:24.062511
7832 14:48:24.062789 Set Vref, RX VrefLevel [Byte0]: 37
7833 14:48:24.065840 [Byte1]: 37
7834 14:48:24.070498
7835 14:48:24.070874 Set Vref, RX VrefLevel [Byte0]: 38
7836 14:48:24.073605 [Byte1]: 38
7837 14:48:24.077824
7838 14:48:24.078248 Set Vref, RX VrefLevel [Byte0]: 39
7839 14:48:24.080975 [Byte1]: 39
7840 14:48:24.085521
7841 14:48:24.085934 Set Vref, RX VrefLevel [Byte0]: 40
7842 14:48:24.088724 [Byte1]: 40
7843 14:48:24.093504
7844 14:48:24.093918 Set Vref, RX VrefLevel [Byte0]: 41
7845 14:48:24.095875 [Byte1]: 41
7846 14:48:24.100491
7847 14:48:24.101137 Set Vref, RX VrefLevel [Byte0]: 42
7848 14:48:24.103738 [Byte1]: 42
7849 14:48:24.107981
7850 14:48:24.108564 Set Vref, RX VrefLevel [Byte0]: 43
7851 14:48:24.111231 [Byte1]: 43
7852 14:48:24.115800
7853 14:48:24.116217 Set Vref, RX VrefLevel [Byte0]: 44
7854 14:48:24.118908 [Byte1]: 44
7855 14:48:24.122858
7856 14:48:24.123499 Set Vref, RX VrefLevel [Byte0]: 45
7857 14:48:24.126074 [Byte1]: 45
7858 14:48:24.130691
7859 14:48:24.131287 Set Vref, RX VrefLevel [Byte0]: 46
7860 14:48:24.134021 [Byte1]: 46
7861 14:48:24.138346
7862 14:48:24.138924 Set Vref, RX VrefLevel [Byte0]: 47
7863 14:48:24.142085 [Byte1]: 47
7864 14:48:24.145938
7865 14:48:24.146377 Set Vref, RX VrefLevel [Byte0]: 48
7866 14:48:24.149133 [Byte1]: 48
7867 14:48:24.153488
7868 14:48:24.153997 Set Vref, RX VrefLevel [Byte0]: 49
7869 14:48:24.156885 [Byte1]: 49
7870 14:48:24.161148
7871 14:48:24.161734 Set Vref, RX VrefLevel [Byte0]: 50
7872 14:48:24.164327 [Byte1]: 50
7873 14:48:24.168975
7874 14:48:24.169390 Set Vref, RX VrefLevel [Byte0]: 51
7875 14:48:24.172060 [Byte1]: 51
7876 14:48:24.176127
7877 14:48:24.176595 Set Vref, RX VrefLevel [Byte0]: 52
7878 14:48:24.179444 [Byte1]: 52
7879 14:48:24.183505
7880 14:48:24.183953 Set Vref, RX VrefLevel [Byte0]: 53
7881 14:48:24.187145 [Byte1]: 53
7882 14:48:24.191341
7883 14:48:24.191764 Set Vref, RX VrefLevel [Byte0]: 54
7884 14:48:24.194951 [Byte1]: 54
7885 14:48:24.198815
7886 14:48:24.199252 Set Vref, RX VrefLevel [Byte0]: 55
7887 14:48:24.202392 [Byte1]: 55
7888 14:48:24.206306
7889 14:48:24.206773 Set Vref, RX VrefLevel [Byte0]: 56
7890 14:48:24.209645 [Byte1]: 56
7891 14:48:24.214315
7892 14:48:24.214731 Set Vref, RX VrefLevel [Byte0]: 57
7893 14:48:24.217446 [Byte1]: 57
7894 14:48:24.221303
7895 14:48:24.221724 Set Vref, RX VrefLevel [Byte0]: 58
7896 14:48:24.225192 [Byte1]: 58
7897 14:48:24.229379
7898 14:48:24.229797 Set Vref, RX VrefLevel [Byte0]: 59
7899 14:48:24.232316 [Byte1]: 59
7900 14:48:24.236959
7901 14:48:24.237513 Set Vref, RX VrefLevel [Byte0]: 60
7902 14:48:24.240330 [Byte1]: 60
7903 14:48:24.244081
7904 14:48:24.244594 Set Vref, RX VrefLevel [Byte0]: 61
7905 14:48:24.247255 [Byte1]: 61
7906 14:48:24.251925
7907 14:48:24.252482 Set Vref, RX VrefLevel [Byte0]: 62
7908 14:48:24.255524 [Byte1]: 62
7909 14:48:24.259967
7910 14:48:24.260604 Set Vref, RX VrefLevel [Byte0]: 63
7911 14:48:24.262898 [Byte1]: 63
7912 14:48:24.266921
7913 14:48:24.267359 Set Vref, RX VrefLevel [Byte0]: 64
7914 14:48:24.270304 [Byte1]: 64
7915 14:48:24.275011
7916 14:48:24.275465 Set Vref, RX VrefLevel [Byte0]: 65
7917 14:48:24.278049 [Byte1]: 65
7918 14:48:24.282191
7919 14:48:24.282610 Set Vref, RX VrefLevel [Byte0]: 66
7920 14:48:24.285300 [Byte1]: 66
7921 14:48:24.289666
7922 14:48:24.290107 Set Vref, RX VrefLevel [Byte0]: 67
7923 14:48:24.292988 [Byte1]: 67
7924 14:48:24.297320
7925 14:48:24.297777 Set Vref, RX VrefLevel [Byte0]: 68
7926 14:48:24.301040 [Byte1]: 68
7927 14:48:24.304953
7928 14:48:24.305400 Set Vref, RX VrefLevel [Byte0]: 69
7929 14:48:24.308398 [Byte1]: 69
7930 14:48:24.312502
7931 14:48:24.313148 Set Vref, RX VrefLevel [Byte0]: 70
7932 14:48:24.315671 [Byte1]: 70
7933 14:48:24.320205
7934 14:48:24.320726 Set Vref, RX VrefLevel [Byte0]: 71
7935 14:48:24.323379 [Byte1]: 71
7936 14:48:24.327894
7937 14:48:24.328330 Set Vref, RX VrefLevel [Byte0]: 72
7938 14:48:24.330977 [Byte1]: 72
7939 14:48:24.335748
7940 14:48:24.336262 Set Vref, RX VrefLevel [Byte0]: 73
7941 14:48:24.338907 [Byte1]: 73
7942 14:48:24.342954
7943 14:48:24.343411 Set Vref, RX VrefLevel [Byte0]: 74
7944 14:48:24.346285 [Byte1]: 74
7945 14:48:24.350390
7946 14:48:24.350835 Set Vref, RX VrefLevel [Byte0]: 75
7947 14:48:24.353551 [Byte1]: 75
7948 14:48:24.358065
7949 14:48:24.358483 Final RX Vref Byte 0 = 53 to rank0
7950 14:48:24.361259 Final RX Vref Byte 1 = 60 to rank0
7951 14:48:24.364569 Final RX Vref Byte 0 = 53 to rank1
7952 14:48:24.367750 Final RX Vref Byte 1 = 60 to rank1==
7953 14:48:24.371577 Dram Type= 6, Freq= 0, CH_0, rank 0
7954 14:48:24.377950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 14:48:24.378420 ==
7956 14:48:24.378748 DQS Delay:
7957 14:48:24.379081 DQS0 = 0, DQS1 = 0
7958 14:48:24.381323 DQM Delay:
7959 14:48:24.381741 DQM0 = 132, DQM1 = 127
7960 14:48:24.384873 DQ Delay:
7961 14:48:24.387781 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
7962 14:48:24.390834 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =138
7963 14:48:24.394229 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7964 14:48:24.397980 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7965 14:48:24.398422
7966 14:48:24.398761
7967 14:48:24.399067
7968 14:48:24.401045 [DramC_TX_OE_Calibration] TA2
7969 14:48:24.404172 Original DQ_B0 (3 6) =30, OEN = 27
7970 14:48:24.407353 Original DQ_B1 (3 6) =30, OEN = 27
7971 14:48:24.410878 24, 0x0, End_B0=24 End_B1=24
7972 14:48:24.411389 25, 0x0, End_B0=25 End_B1=25
7973 14:48:24.414497 26, 0x0, End_B0=26 End_B1=26
7974 14:48:24.417605 27, 0x0, End_B0=27 End_B1=27
7975 14:48:24.421253 28, 0x0, End_B0=28 End_B1=28
7976 14:48:24.424312 29, 0x0, End_B0=29 End_B1=29
7977 14:48:24.424807 30, 0x0, End_B0=30 End_B1=30
7978 14:48:24.427299 31, 0x4141, End_B0=30 End_B1=30
7979 14:48:24.430899 Byte0 end_step=30 best_step=27
7980 14:48:24.434320 Byte1 end_step=30 best_step=27
7981 14:48:24.437332 Byte0 TX OE(2T, 0.5T) = (3, 3)
7982 14:48:24.440644 Byte1 TX OE(2T, 0.5T) = (3, 3)
7983 14:48:24.441085
7984 14:48:24.441409
7985 14:48:24.447744 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7986 14:48:24.450988 CH0 RK0: MR19=303, MR18=2622
7987 14:48:24.457165 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7988 14:48:24.457625
7989 14:48:24.460901 ----->DramcWriteLeveling(PI) begin...
7990 14:48:24.461327 ==
7991 14:48:24.463986 Dram Type= 6, Freq= 0, CH_0, rank 1
7992 14:48:24.467334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7993 14:48:24.467760 ==
7994 14:48:24.470678 Write leveling (Byte 0): 36 => 36
7995 14:48:24.473922 Write leveling (Byte 1): 26 => 26
7996 14:48:24.477175 DramcWriteLeveling(PI) end<-----
7997 14:48:24.477593
7998 14:48:24.477914 ==
7999 14:48:24.480848 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 14:48:24.484373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 14:48:24.484829 ==
8002 14:48:24.487500 [Gating] SW mode calibration
8003 14:48:24.493651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8004 14:48:24.500851 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8005 14:48:24.503951 1 4 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8006 14:48:24.510489 1 4 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8007 14:48:24.513792 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (1 1)
8008 14:48:24.516879 1 4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
8009 14:48:24.520610 1 4 16 | B1->B0 | 3232 3939 | 0 0 | (0 0) (0 0)
8010 14:48:24.526880 1 4 20 | B1->B0 | 3434 3b3b | 1 1 | (1 1) (0 0)
8011 14:48:24.530097 1 4 24 | B1->B0 | 3434 3c3b | 1 1 | (1 1) (0 0)
8012 14:48:24.534247 1 4 28 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
8013 14:48:24.540078 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
8014 14:48:24.543474 1 5 4 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
8015 14:48:24.547068 1 5 8 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
8016 14:48:24.553334 1 5 12 | B1->B0 | 3434 3635 | 1 1 | (1 0) (1 0)
8017 14:48:24.557305 1 5 16 | B1->B0 | 2e2e 2928 | 0 1 | (1 0) (0 0)
8018 14:48:24.560182 1 5 20 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8019 14:48:24.567393 1 5 24 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8020 14:48:24.570599 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
8021 14:48:24.573898 1 6 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8022 14:48:24.580298 1 6 4 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8023 14:48:24.583910 1 6 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8024 14:48:24.587481 1 6 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
8025 14:48:24.593973 1 6 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8026 14:48:24.596870 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8027 14:48:24.600882 1 6 24 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
8028 14:48:24.607118 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (1 1)
8029 14:48:24.610450 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 14:48:24.613492 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 14:48:24.616929 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 14:48:24.624100 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8033 14:48:24.627240 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 14:48:24.630162 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 14:48:24.637357 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 14:48:24.640583 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 14:48:24.643731 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 14:48:24.650448 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 14:48:24.653615 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 14:48:24.656884 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 14:48:24.663745 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 14:48:24.666525 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 14:48:24.670161 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 14:48:24.676401 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 14:48:24.679650 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 14:48:24.683134 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 14:48:24.689656 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 14:48:24.693197 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8049 14:48:24.696155 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 14:48:24.699924 Total UI for P1: 0, mck2ui 16
8051 14:48:24.702983 best dqsien dly found for B0: ( 1, 9, 12)
8052 14:48:24.709614 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 14:48:24.709819 Total UI for P1: 0, mck2ui 16
8054 14:48:24.716479 best dqsien dly found for B1: ( 1, 9, 14)
8055 14:48:24.719860 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8056 14:48:24.723181 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8057 14:48:24.723383
8058 14:48:24.726614 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8059 14:48:24.729655 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8060 14:48:24.732798 [Gating] SW calibration Done
8061 14:48:24.733005 ==
8062 14:48:24.736828 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 14:48:24.739426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 14:48:24.739718 ==
8065 14:48:24.743308 RX Vref Scan: 0
8066 14:48:24.743692
8067 14:48:24.744080 RX Vref 0 -> 0, step: 1
8068 14:48:24.744544
8069 14:48:24.746673 RX Delay 0 -> 252, step: 8
8070 14:48:24.749920 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8071 14:48:24.756945 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8072 14:48:24.760179 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8073 14:48:24.763496 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8074 14:48:24.766268 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8075 14:48:24.769665 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8076 14:48:24.776195 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8077 14:48:24.779569 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8078 14:48:24.782885 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8079 14:48:24.786528 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8080 14:48:24.790005 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8081 14:48:24.796320 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8082 14:48:24.799767 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8083 14:48:24.802697 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8084 14:48:24.806366 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8085 14:48:24.809867 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8086 14:48:24.813140 ==
8087 14:48:24.816326 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 14:48:24.819520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 14:48:24.819941 ==
8090 14:48:24.820365 DQS Delay:
8091 14:48:24.822821 DQS0 = 0, DQS1 = 0
8092 14:48:24.823232 DQM Delay:
8093 14:48:24.826094 DQM0 = 136, DQM1 = 128
8094 14:48:24.826612 DQ Delay:
8095 14:48:24.829856 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8096 14:48:24.832873 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8097 14:48:24.835994 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8098 14:48:24.839721 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8099 14:48:24.840134
8100 14:48:24.840500
8101 14:48:24.840808 ==
8102 14:48:24.842983 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 14:48:24.849337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 14:48:24.849753 ==
8105 14:48:24.850078
8106 14:48:24.850377
8107 14:48:24.850665 TX Vref Scan disable
8108 14:48:24.853226 == TX Byte 0 ==
8109 14:48:24.856452 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8110 14:48:24.863367 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8111 14:48:24.863784 == TX Byte 1 ==
8112 14:48:24.866608 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8113 14:48:24.872851 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8114 14:48:24.873270 ==
8115 14:48:24.876435 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 14:48:24.879703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 14:48:24.880122 ==
8118 14:48:24.894495
8119 14:48:24.897789 TX Vref early break, caculate TX vref
8120 14:48:24.900626 TX Vref=16, minBit 1, minWin=23, winSum=386
8121 14:48:24.904555 TX Vref=18, minBit 1, minWin=23, winSum=398
8122 14:48:24.907641 TX Vref=20, minBit 0, minWin=24, winSum=406
8123 14:48:24.910963 TX Vref=22, minBit 1, minWin=24, winSum=412
8124 14:48:24.914182 TX Vref=24, minBit 3, minWin=24, winSum=417
8125 14:48:24.920997 TX Vref=26, minBit 1, minWin=24, winSum=423
8126 14:48:24.924021 TX Vref=28, minBit 1, minWin=25, winSum=423
8127 14:48:24.927763 TX Vref=30, minBit 0, minWin=25, winSum=418
8128 14:48:24.930626 TX Vref=32, minBit 0, minWin=25, winSum=411
8129 14:48:24.934050 TX Vref=34, minBit 0, minWin=24, winSum=401
8130 14:48:24.937520 TX Vref=36, minBit 0, minWin=23, winSum=391
8131 14:48:24.944004 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 28
8132 14:48:24.944473
8133 14:48:24.947720 Final TX Range 0 Vref 28
8134 14:48:24.948105
8135 14:48:24.948465 ==
8136 14:48:24.951008 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 14:48:24.954176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 14:48:24.954760 ==
8139 14:48:24.955235
8140 14:48:24.955608
8141 14:48:24.957578 TX Vref Scan disable
8142 14:48:24.963985 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8143 14:48:24.964466 == TX Byte 0 ==
8144 14:48:24.967140 u2DelayCellOfst[0]=13 cells (4 PI)
8145 14:48:24.970656 u2DelayCellOfst[1]=13 cells (4 PI)
8146 14:48:24.973936 u2DelayCellOfst[2]=10 cells (3 PI)
8147 14:48:24.977212 u2DelayCellOfst[3]=10 cells (3 PI)
8148 14:48:24.980585 u2DelayCellOfst[4]=6 cells (2 PI)
8149 14:48:24.983426 u2DelayCellOfst[5]=0 cells (0 PI)
8150 14:48:24.987004 u2DelayCellOfst[6]=13 cells (4 PI)
8151 14:48:24.990305 u2DelayCellOfst[7]=13 cells (4 PI)
8152 14:48:24.993810 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8153 14:48:24.996874 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8154 14:48:25.000006 == TX Byte 1 ==
8155 14:48:25.003388 u2DelayCellOfst[8]=0 cells (0 PI)
8156 14:48:25.006685 u2DelayCellOfst[9]=0 cells (0 PI)
8157 14:48:25.009887 u2DelayCellOfst[10]=3 cells (1 PI)
8158 14:48:25.012995 u2DelayCellOfst[11]=3 cells (1 PI)
8159 14:48:25.013082 u2DelayCellOfst[12]=10 cells (3 PI)
8160 14:48:25.016831 u2DelayCellOfst[13]=6 cells (2 PI)
8161 14:48:25.020003 u2DelayCellOfst[14]=10 cells (3 PI)
8162 14:48:25.022648 u2DelayCellOfst[15]=6 cells (2 PI)
8163 14:48:25.029609 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8164 14:48:25.032925 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8165 14:48:25.033024 DramC Write-DBI on
8166 14:48:25.036483 ==
8167 14:48:25.039668 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 14:48:25.042988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 14:48:25.043085 ==
8170 14:48:25.043172
8171 14:48:25.043260
8172 14:48:25.046010 TX Vref Scan disable
8173 14:48:25.046078 == TX Byte 0 ==
8174 14:48:25.053026 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8175 14:48:25.053107 == TX Byte 1 ==
8176 14:48:25.056018 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8177 14:48:25.059385 DramC Write-DBI off
8178 14:48:25.059480
8179 14:48:25.059553 [DATLAT]
8180 14:48:25.062841 Freq=1600, CH0 RK1
8181 14:48:25.062936
8182 14:48:25.063009 DATLAT Default: 0xf
8183 14:48:25.066463 0, 0xFFFF, sum = 0
8184 14:48:25.066568 1, 0xFFFF, sum = 0
8185 14:48:25.069558 2, 0xFFFF, sum = 0
8186 14:48:25.069671 3, 0xFFFF, sum = 0
8187 14:48:25.072936 4, 0xFFFF, sum = 0
8188 14:48:25.073049 5, 0xFFFF, sum = 0
8189 14:48:25.076230 6, 0xFFFF, sum = 0
8190 14:48:25.076397 7, 0xFFFF, sum = 0
8191 14:48:25.079484 8, 0xFFFF, sum = 0
8192 14:48:25.079622 9, 0xFFFF, sum = 0
8193 14:48:25.082698 10, 0xFFFF, sum = 0
8194 14:48:25.085830 11, 0xFFFF, sum = 0
8195 14:48:25.085985 12, 0xFFFF, sum = 0
8196 14:48:25.089637 13, 0xFFFF, sum = 0
8197 14:48:25.089814 14, 0x0, sum = 1
8198 14:48:25.092649 15, 0x0, sum = 2
8199 14:48:25.092825 16, 0x0, sum = 3
8200 14:48:25.096106 17, 0x0, sum = 4
8201 14:48:25.096396 best_step = 15
8202 14:48:25.096561
8203 14:48:25.096709 ==
8204 14:48:25.099199 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 14:48:25.102932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 14:48:25.103177 ==
8207 14:48:25.106179 RX Vref Scan: 0
8208 14:48:25.106480
8209 14:48:25.109627 RX Vref 0 -> 0, step: 1
8210 14:48:25.110018
8211 14:48:25.110322 RX Delay 19 -> 252, step: 4
8212 14:48:25.116698 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
8213 14:48:25.119718 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8214 14:48:25.123531 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8215 14:48:25.126605 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8216 14:48:25.129875 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8217 14:48:25.136791 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8218 14:48:25.139859 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8219 14:48:25.143613 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8220 14:48:25.146358 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8221 14:48:25.149633 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8222 14:48:25.156544 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8223 14:48:25.159905 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8224 14:48:25.163149 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8225 14:48:25.166218 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8226 14:48:25.169805 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8227 14:48:25.176415 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8228 14:48:25.177019 ==
8229 14:48:25.180123 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 14:48:25.183013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 14:48:25.183722 ==
8232 14:48:25.184469 DQS Delay:
8233 14:48:25.186733 DQS0 = 0, DQS1 = 0
8234 14:48:25.187395 DQM Delay:
8235 14:48:25.189854 DQM0 = 134, DQM1 = 127
8236 14:48:25.190469 DQ Delay:
8237 14:48:25.193177 DQ0 =132, DQ1 =138, DQ2 =130, DQ3 =134
8238 14:48:25.196383 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =142
8239 14:48:25.199664 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8240 14:48:25.202890 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8241 14:48:25.203571
8242 14:48:25.204138
8243 14:48:25.206391
8244 14:48:25.206858 [DramC_TX_OE_Calibration] TA2
8245 14:48:25.209872 Original DQ_B0 (3 6) =30, OEN = 27
8246 14:48:25.213067 Original DQ_B1 (3 6) =30, OEN = 27
8247 14:48:25.217112 24, 0x0, End_B0=24 End_B1=24
8248 14:48:25.219639 25, 0x0, End_B0=25 End_B1=25
8249 14:48:25.222918 26, 0x0, End_B0=26 End_B1=26
8250 14:48:25.223505 27, 0x0, End_B0=27 End_B1=27
8251 14:48:25.226357 28, 0x0, End_B0=28 End_B1=28
8252 14:48:25.229542 29, 0x0, End_B0=29 End_B1=29
8253 14:48:25.233329 30, 0x0, End_B0=30 End_B1=30
8254 14:48:25.233760 31, 0x4141, End_B0=30 End_B1=30
8255 14:48:25.236736 Byte0 end_step=30 best_step=27
8256 14:48:25.240006 Byte1 end_step=30 best_step=27
8257 14:48:25.243128 Byte0 TX OE(2T, 0.5T) = (3, 3)
8258 14:48:25.246155 Byte1 TX OE(2T, 0.5T) = (3, 3)
8259 14:48:25.246673
8260 14:48:25.247131
8261 14:48:25.253100 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
8262 14:48:25.256651 CH0 RK1: MR19=303, MR18=1F08
8263 14:48:25.263144 CH0_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15
8264 14:48:25.266367 [RxdqsGatingPostProcess] freq 1600
8265 14:48:25.272790 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8266 14:48:25.276093 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 14:48:25.276535 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 14:48:25.279391 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 14:48:25.283464 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 14:48:25.286456 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 14:48:25.290044 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 14:48:25.292792 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 14:48:25.296023 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 14:48:25.299223 Pre-setting of DQS Precalculation
8275 14:48:25.302884 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8276 14:48:25.303300 ==
8277 14:48:25.305916 Dram Type= 6, Freq= 0, CH_1, rank 0
8278 14:48:25.312991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 14:48:25.313412 ==
8280 14:48:25.316317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 14:48:25.322784 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 14:48:25.326038 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 14:48:25.332489 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 14:48:25.340444 [CA 0] Center 41 (12~71) winsize 60
8285 14:48:25.343918 [CA 1] Center 41 (12~71) winsize 60
8286 14:48:25.346942 [CA 2] Center 39 (10~68) winsize 59
8287 14:48:25.350238 [CA 3] Center 38 (9~67) winsize 59
8288 14:48:25.353928 [CA 4] Center 37 (8~67) winsize 60
8289 14:48:25.357030 [CA 5] Center 37 (8~66) winsize 59
8290 14:48:25.357454
8291 14:48:25.360334 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8292 14:48:25.360827
8293 14:48:25.363698 [CATrainingPosCal] consider 1 rank data
8294 14:48:25.367254 u2DelayCellTimex100 = 290/100 ps
8295 14:48:25.374086 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8296 14:48:25.377636 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8297 14:48:25.380507 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8298 14:48:25.383721 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8299 14:48:25.386925 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8300 14:48:25.390152 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8301 14:48:25.390568
8302 14:48:25.393587 CA PerBit enable=1, Macro0, CA PI delay=37
8303 14:48:25.394108
8304 14:48:25.396590 [CBTSetCACLKResult] CA Dly = 37
8305 14:48:25.399904 CS Dly: 11 (0~42)
8306 14:48:25.403711 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 14:48:25.406844 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 14:48:25.407290 ==
8309 14:48:25.409978 Dram Type= 6, Freq= 0, CH_1, rank 1
8310 14:48:25.413717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 14:48:25.416815 ==
8312 14:48:25.420022 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 14:48:25.423787 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 14:48:25.429978 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 14:48:25.436665 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 14:48:25.444111 [CA 0] Center 42 (13~72) winsize 60
8317 14:48:25.447502 [CA 1] Center 42 (13~72) winsize 60
8318 14:48:25.450591 [CA 2] Center 39 (10~69) winsize 60
8319 14:48:25.454042 [CA 3] Center 38 (9~68) winsize 60
8320 14:48:25.457287 [CA 4] Center 39 (9~69) winsize 61
8321 14:48:25.460427 [CA 5] Center 38 (9~68) winsize 60
8322 14:48:25.460866
8323 14:48:25.463609 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8324 14:48:25.464057
8325 14:48:25.467157 [CATrainingPosCal] consider 2 rank data
8326 14:48:25.470470 u2DelayCellTimex100 = 290/100 ps
8327 14:48:25.474023 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8328 14:48:25.480557 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8329 14:48:25.483734 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8330 14:48:25.486907 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8331 14:48:25.490730 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8332 14:48:25.493980 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8333 14:48:25.494395
8334 14:48:25.497277 CA PerBit enable=1, Macro0, CA PI delay=37
8335 14:48:25.497689
8336 14:48:25.501001 [CBTSetCACLKResult] CA Dly = 37
8337 14:48:25.501448 CS Dly: 12 (0~44)
8338 14:48:25.507439 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 14:48:25.510551 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 14:48:25.510966
8341 14:48:25.513954 ----->DramcWriteLeveling(PI) begin...
8342 14:48:25.514377 ==
8343 14:48:25.517184 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 14:48:25.521099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 14:48:25.521519 ==
8346 14:48:25.524373 Write leveling (Byte 0): 25 => 25
8347 14:48:25.527475 Write leveling (Byte 1): 28 => 28
8348 14:48:25.531081 DramcWriteLeveling(PI) end<-----
8349 14:48:25.531493
8350 14:48:25.531818 ==
8351 14:48:25.533947 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 14:48:25.540741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 14:48:25.541259 ==
8354 14:48:25.541586 [Gating] SW mode calibration
8355 14:48:25.550551 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8356 14:48:25.554219 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8357 14:48:25.557652 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 14:48:25.564281 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 14:48:25.567631 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
8360 14:48:25.571086 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8361 14:48:25.577782 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 14:48:25.580647 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 14:48:25.583999 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 14:48:25.590466 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 14:48:25.594232 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 14:48:25.597493 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 14:48:25.604022 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8368 14:48:25.607236 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8369 14:48:25.610350 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 14:48:25.616936 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 14:48:25.620921 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 14:48:25.623982 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 14:48:25.630478 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 14:48:25.633864 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 14:48:25.637055 1 6 8 | B1->B0 | 2525 4242 | 0 1 | (0 0) (0 0)
8376 14:48:25.644091 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8377 14:48:25.647209 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 14:48:25.650357 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 14:48:25.656757 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 14:48:25.660010 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 14:48:25.663606 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 14:48:25.670031 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 14:48:25.673383 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8384 14:48:25.676860 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8385 14:48:25.683540 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 14:48:25.686727 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 14:48:25.690446 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 14:48:25.693777 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 14:48:25.700027 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 14:48:25.703635 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 14:48:25.706664 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 14:48:25.713296 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 14:48:25.716887 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 14:48:25.720075 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 14:48:25.726863 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 14:48:25.730189 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 14:48:25.733729 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 14:48:25.740315 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 14:48:25.743741 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8400 14:48:25.746650 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 14:48:25.753070 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 14:48:25.753490 Total UI for P1: 0, mck2ui 16
8403 14:48:25.760179 best dqsien dly found for B0: ( 1, 9, 10)
8404 14:48:25.760619 Total UI for P1: 0, mck2ui 16
8405 14:48:25.766931 best dqsien dly found for B1: ( 1, 9, 10)
8406 14:48:25.770227 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8407 14:48:25.773575 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8408 14:48:25.774141
8409 14:48:25.776648 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8410 14:48:25.780127 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8411 14:48:25.783585 [Gating] SW calibration Done
8412 14:48:25.784149 ==
8413 14:48:25.786557 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 14:48:25.789431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 14:48:25.789902 ==
8416 14:48:25.793245 RX Vref Scan: 0
8417 14:48:25.793841
8418 14:48:25.794209 RX Vref 0 -> 0, step: 1
8419 14:48:25.796121
8420 14:48:25.796635 RX Delay 0 -> 252, step: 8
8421 14:48:25.799772 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8422 14:48:25.806274 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8423 14:48:25.809431 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8424 14:48:25.812843 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8425 14:48:25.816715 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8426 14:48:25.819787 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8427 14:48:25.826563 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8428 14:48:25.829684 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8429 14:48:25.832611 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8430 14:48:25.836172 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8431 14:48:25.839186 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8432 14:48:25.846034 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8433 14:48:25.849294 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8434 14:48:25.852623 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8435 14:48:25.856113 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8436 14:48:25.859231 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8437 14:48:25.862473 ==
8438 14:48:25.862821 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 14:48:25.869411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 14:48:25.869514 ==
8441 14:48:25.869613 DQS Delay:
8442 14:48:25.872681 DQS0 = 0, DQS1 = 0
8443 14:48:25.872755 DQM Delay:
8444 14:48:25.875931 DQM0 = 136, DQM1 = 133
8445 14:48:25.876026 DQ Delay:
8446 14:48:25.879133 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8447 14:48:25.882561 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8448 14:48:25.885734 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8449 14:48:25.889152 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8450 14:48:25.889222
8451 14:48:25.889281
8452 14:48:25.889350 ==
8453 14:48:25.892098 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 14:48:25.898470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 14:48:25.898580 ==
8456 14:48:25.898669
8457 14:48:25.898754
8458 14:48:25.898845 TX Vref Scan disable
8459 14:48:25.902645 == TX Byte 0 ==
8460 14:48:25.905800 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8461 14:48:25.909316 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8462 14:48:25.912162 == TX Byte 1 ==
8463 14:48:25.915500 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8464 14:48:25.922209 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8465 14:48:25.922300 ==
8466 14:48:25.925690 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 14:48:25.928840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 14:48:25.928921 ==
8469 14:48:25.942336
8470 14:48:25.945741 TX Vref early break, caculate TX vref
8471 14:48:25.948941 TX Vref=16, minBit 1, minWin=22, winSum=373
8472 14:48:25.952213 TX Vref=18, minBit 0, minWin=23, winSum=384
8473 14:48:25.955669 TX Vref=20, minBit 0, minWin=24, winSum=398
8474 14:48:25.959223 TX Vref=22, minBit 0, minWin=25, winSum=410
8475 14:48:25.962233 TX Vref=24, minBit 0, minWin=25, winSum=416
8476 14:48:25.968750 TX Vref=26, minBit 0, minWin=25, winSum=421
8477 14:48:25.972071 TX Vref=28, minBit 1, minWin=25, winSum=427
8478 14:48:25.975815 TX Vref=30, minBit 2, minWin=25, winSum=419
8479 14:48:25.979393 TX Vref=32, minBit 0, minWin=24, winSum=412
8480 14:48:25.982537 TX Vref=34, minBit 0, minWin=24, winSum=408
8481 14:48:25.985830 TX Vref=36, minBit 0, minWin=23, winSum=389
8482 14:48:25.992311 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 28
8483 14:48:25.992415
8484 14:48:25.995590 Final TX Range 0 Vref 28
8485 14:48:25.995671
8486 14:48:25.995734 ==
8487 14:48:25.998796 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 14:48:26.002584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 14:48:26.002667 ==
8490 14:48:26.002729
8491 14:48:26.002786
8492 14:48:26.005450 TX Vref Scan disable
8493 14:48:26.012126 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8494 14:48:26.012234 == TX Byte 0 ==
8495 14:48:26.016052 u2DelayCellOfst[0]=16 cells (5 PI)
8496 14:48:26.019094 u2DelayCellOfst[1]=10 cells (3 PI)
8497 14:48:26.022224 u2DelayCellOfst[2]=0 cells (0 PI)
8498 14:48:26.025732 u2DelayCellOfst[3]=6 cells (2 PI)
8499 14:48:26.029097 u2DelayCellOfst[4]=10 cells (3 PI)
8500 14:48:26.032312 u2DelayCellOfst[5]=20 cells (6 PI)
8501 14:48:26.035810 u2DelayCellOfst[6]=16 cells (5 PI)
8502 14:48:26.038907 u2DelayCellOfst[7]=6 cells (2 PI)
8503 14:48:26.042602 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8504 14:48:26.045835 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8505 14:48:26.049089 == TX Byte 1 ==
8506 14:48:26.049169 u2DelayCellOfst[8]=0 cells (0 PI)
8507 14:48:26.052243 u2DelayCellOfst[9]=3 cells (1 PI)
8508 14:48:26.056528 u2DelayCellOfst[10]=13 cells (4 PI)
8509 14:48:26.058754 u2DelayCellOfst[11]=6 cells (2 PI)
8510 14:48:26.062605 u2DelayCellOfst[12]=13 cells (4 PI)
8511 14:48:26.065842 u2DelayCellOfst[13]=16 cells (5 PI)
8512 14:48:26.069595 u2DelayCellOfst[14]=20 cells (6 PI)
8513 14:48:26.072236 u2DelayCellOfst[15]=16 cells (5 PI)
8514 14:48:26.075684 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8515 14:48:26.082282 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8516 14:48:26.082374 DramC Write-DBI on
8517 14:48:26.082439 ==
8518 14:48:26.085562 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 14:48:26.088930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 14:48:26.092299 ==
8521 14:48:26.092427
8522 14:48:26.092491
8523 14:48:26.092547 TX Vref Scan disable
8524 14:48:26.095437 == TX Byte 0 ==
8525 14:48:26.099246 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8526 14:48:26.102401 == TX Byte 1 ==
8527 14:48:26.105628 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8528 14:48:26.108850 DramC Write-DBI off
8529 14:48:26.108930
8530 14:48:26.108993 [DATLAT]
8531 14:48:26.109051 Freq=1600, CH1 RK0
8532 14:48:26.109107
8533 14:48:26.111987 DATLAT Default: 0xf
8534 14:48:26.112095 0, 0xFFFF, sum = 0
8535 14:48:26.115643 1, 0xFFFF, sum = 0
8536 14:48:26.118561 2, 0xFFFF, sum = 0
8537 14:48:26.118644 3, 0xFFFF, sum = 0
8538 14:48:26.121906 4, 0xFFFF, sum = 0
8539 14:48:26.121989 5, 0xFFFF, sum = 0
8540 14:48:26.125551 6, 0xFFFF, sum = 0
8541 14:48:26.125633 7, 0xFFFF, sum = 0
8542 14:48:26.128724 8, 0xFFFF, sum = 0
8543 14:48:26.128806 9, 0xFFFF, sum = 0
8544 14:48:26.132057 10, 0xFFFF, sum = 0
8545 14:48:26.132177 11, 0xFFFF, sum = 0
8546 14:48:26.135303 12, 0xFFFF, sum = 0
8547 14:48:26.135385 13, 0xFFFF, sum = 0
8548 14:48:26.138941 14, 0x0, sum = 1
8549 14:48:26.139023 15, 0x0, sum = 2
8550 14:48:26.142043 16, 0x0, sum = 3
8551 14:48:26.142125 17, 0x0, sum = 4
8552 14:48:26.145093 best_step = 15
8553 14:48:26.145173
8554 14:48:26.145235 ==
8555 14:48:26.148568 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 14:48:26.151810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 14:48:26.151891 ==
8558 14:48:26.155461 RX Vref Scan: 1
8559 14:48:26.155541
8560 14:48:26.155639 Set Vref Range= 24 -> 127
8561 14:48:26.155700
8562 14:48:26.158742 RX Vref 24 -> 127, step: 1
8563 14:48:26.158830
8564 14:48:26.161776 RX Delay 27 -> 252, step: 4
8565 14:48:26.161882
8566 14:48:26.165514 Set Vref, RX VrefLevel [Byte0]: 24
8567 14:48:26.168315 [Byte1]: 24
8568 14:48:26.168437
8569 14:48:26.171675 Set Vref, RX VrefLevel [Byte0]: 25
8570 14:48:26.175477 [Byte1]: 25
8571 14:48:26.175558
8572 14:48:26.178690 Set Vref, RX VrefLevel [Byte0]: 26
8573 14:48:26.181982 [Byte1]: 26
8574 14:48:26.185835
8575 14:48:26.188739 Set Vref, RX VrefLevel [Byte0]: 27
8576 14:48:26.188821 [Byte1]: 27
8577 14:48:26.193434
8578 14:48:26.193551 Set Vref, RX VrefLevel [Byte0]: 28
8579 14:48:26.196606 [Byte1]: 28
8580 14:48:26.200567
8581 14:48:26.200653 Set Vref, RX VrefLevel [Byte0]: 29
8582 14:48:26.204451 [Byte1]: 29
8583 14:48:26.208213
8584 14:48:26.208322 Set Vref, RX VrefLevel [Byte0]: 30
8585 14:48:26.211652 [Byte1]: 30
8586 14:48:26.216003
8587 14:48:26.216085 Set Vref, RX VrefLevel [Byte0]: 31
8588 14:48:26.219296 [Byte1]: 31
8589 14:48:26.223165
8590 14:48:26.223314 Set Vref, RX VrefLevel [Byte0]: 32
8591 14:48:26.226848 [Byte1]: 32
8592 14:48:26.230594
8593 14:48:26.230668 Set Vref, RX VrefLevel [Byte0]: 33
8594 14:48:26.234024 [Byte1]: 33
8595 14:48:26.238441
8596 14:48:26.238543 Set Vref, RX VrefLevel [Byte0]: 34
8597 14:48:26.241481 [Byte1]: 34
8598 14:48:26.245977
8599 14:48:26.246059 Set Vref, RX VrefLevel [Byte0]: 35
8600 14:48:26.249264 [Byte1]: 35
8601 14:48:26.253801
8602 14:48:26.253883 Set Vref, RX VrefLevel [Byte0]: 36
8603 14:48:26.256986 [Byte1]: 36
8604 14:48:26.261338
8605 14:48:26.261419 Set Vref, RX VrefLevel [Byte0]: 37
8606 14:48:26.264336 [Byte1]: 37
8607 14:48:26.268545
8608 14:48:26.268626 Set Vref, RX VrefLevel [Byte0]: 38
8609 14:48:26.271612 [Byte1]: 38
8610 14:48:26.275857
8611 14:48:26.275933 Set Vref, RX VrefLevel [Byte0]: 39
8612 14:48:26.279325 [Byte1]: 39
8613 14:48:26.283621
8614 14:48:26.283702 Set Vref, RX VrefLevel [Byte0]: 40
8615 14:48:26.287115 [Byte1]: 40
8616 14:48:26.291420
8617 14:48:26.291502 Set Vref, RX VrefLevel [Byte0]: 41
8618 14:48:26.294601 [Byte1]: 41
8619 14:48:26.298837
8620 14:48:26.298940 Set Vref, RX VrefLevel [Byte0]: 42
8621 14:48:26.302152 [Byte1]: 42
8622 14:48:26.306592
8623 14:48:26.306672 Set Vref, RX VrefLevel [Byte0]: 43
8624 14:48:26.309255 [Byte1]: 43
8625 14:48:26.313898
8626 14:48:26.313978 Set Vref, RX VrefLevel [Byte0]: 44
8627 14:48:26.317096 [Byte1]: 44
8628 14:48:26.321114
8629 14:48:26.321198 Set Vref, RX VrefLevel [Byte0]: 45
8630 14:48:26.324972 [Byte1]: 45
8631 14:48:26.329126
8632 14:48:26.329233 Set Vref, RX VrefLevel [Byte0]: 46
8633 14:48:26.331961 [Byte1]: 46
8634 14:48:26.336667
8635 14:48:26.336738 Set Vref, RX VrefLevel [Byte0]: 47
8636 14:48:26.339663 [Byte1]: 47
8637 14:48:26.343895
8638 14:48:26.343975 Set Vref, RX VrefLevel [Byte0]: 48
8639 14:48:26.347550 [Byte1]: 48
8640 14:48:26.351487
8641 14:48:26.351567 Set Vref, RX VrefLevel [Byte0]: 49
8642 14:48:26.354479 [Byte1]: 49
8643 14:48:26.358968
8644 14:48:26.359048 Set Vref, RX VrefLevel [Byte0]: 50
8645 14:48:26.362248 [Byte1]: 50
8646 14:48:26.366725
8647 14:48:26.366805 Set Vref, RX VrefLevel [Byte0]: 51
8648 14:48:26.369941 [Byte1]: 51
8649 14:48:26.374325
8650 14:48:26.374408 Set Vref, RX VrefLevel [Byte0]: 52
8651 14:48:26.377465 [Byte1]: 52
8652 14:48:26.381580
8653 14:48:26.381660 Set Vref, RX VrefLevel [Byte0]: 53
8654 14:48:26.384789 [Byte1]: 53
8655 14:48:26.388891
8656 14:48:26.388964 Set Vref, RX VrefLevel [Byte0]: 54
8657 14:48:26.392427 [Byte1]: 54
8658 14:48:26.396792
8659 14:48:26.396865 Set Vref, RX VrefLevel [Byte0]: 55
8660 14:48:26.399811 [Byte1]: 55
8661 14:48:26.404015
8662 14:48:26.404095 Set Vref, RX VrefLevel [Byte0]: 56
8663 14:48:26.407636 [Byte1]: 56
8664 14:48:26.411543
8665 14:48:26.411645 Set Vref, RX VrefLevel [Byte0]: 57
8666 14:48:26.415271 [Byte1]: 57
8667 14:48:26.419225
8668 14:48:26.419305 Set Vref, RX VrefLevel [Byte0]: 58
8669 14:48:26.422603 [Byte1]: 58
8670 14:48:26.426889
8671 14:48:26.426970 Set Vref, RX VrefLevel [Byte0]: 59
8672 14:48:26.430183 [Byte1]: 59
8673 14:48:26.433963
8674 14:48:26.434043 Set Vref, RX VrefLevel [Byte0]: 60
8675 14:48:26.437370 [Byte1]: 60
8676 14:48:26.441826
8677 14:48:26.441906 Set Vref, RX VrefLevel [Byte0]: 61
8678 14:48:26.444948 [Byte1]: 61
8679 14:48:26.449678
8680 14:48:26.449759 Set Vref, RX VrefLevel [Byte0]: 62
8681 14:48:26.452706 [Byte1]: 62
8682 14:48:26.457140
8683 14:48:26.457221 Set Vref, RX VrefLevel [Byte0]: 63
8684 14:48:26.460145 [Byte1]: 63
8685 14:48:26.464070
8686 14:48:26.464151 Set Vref, RX VrefLevel [Byte0]: 64
8687 14:48:26.467866 [Byte1]: 64
8688 14:48:26.471726
8689 14:48:26.471808 Set Vref, RX VrefLevel [Byte0]: 65
8690 14:48:26.475022 [Byte1]: 65
8691 14:48:26.479567
8692 14:48:26.479637 Set Vref, RX VrefLevel [Byte0]: 66
8693 14:48:26.482905 [Byte1]: 66
8694 14:48:26.487181
8695 14:48:26.487261 Set Vref, RX VrefLevel [Byte0]: 67
8696 14:48:26.490226 [Byte1]: 67
8697 14:48:26.494604
8698 14:48:26.494684 Set Vref, RX VrefLevel [Byte0]: 68
8699 14:48:26.498110 [Byte1]: 68
8700 14:48:26.501836
8701 14:48:26.501918 Set Vref, RX VrefLevel [Byte0]: 69
8702 14:48:26.505322 [Byte1]: 69
8703 14:48:26.509868
8704 14:48:26.509948 Set Vref, RX VrefLevel [Byte0]: 70
8705 14:48:26.513252 [Byte1]: 70
8706 14:48:26.517108
8707 14:48:26.517189 Set Vref, RX VrefLevel [Byte0]: 71
8708 14:48:26.520166 [Byte1]: 71
8709 14:48:26.524374
8710 14:48:26.524465 Set Vref, RX VrefLevel [Byte0]: 72
8711 14:48:26.527958 [Byte1]: 72
8712 14:48:26.532028
8713 14:48:26.532107 Set Vref, RX VrefLevel [Byte0]: 73
8714 14:48:26.535344 [Byte1]: 73
8715 14:48:26.539875
8716 14:48:26.539954 Set Vref, RX VrefLevel [Byte0]: 74
8717 14:48:26.542724 [Byte1]: 74
8718 14:48:26.547274
8719 14:48:26.547354 Set Vref, RX VrefLevel [Byte0]: 75
8720 14:48:26.550884 [Byte1]: 75
8721 14:48:26.554574
8722 14:48:26.554654 Set Vref, RX VrefLevel [Byte0]: 76
8723 14:48:26.557838 [Byte1]: 76
8724 14:48:26.562464
8725 14:48:26.562544 Set Vref, RX VrefLevel [Byte0]: 77
8726 14:48:26.565675 [Byte1]: 77
8727 14:48:26.569948
8728 14:48:26.570033 Set Vref, RX VrefLevel [Byte0]: 78
8729 14:48:26.573499 [Byte1]: 78
8730 14:48:26.577480
8731 14:48:26.577560 Final RX Vref Byte 0 = 60 to rank0
8732 14:48:26.580521 Final RX Vref Byte 1 = 52 to rank0
8733 14:48:26.584310 Final RX Vref Byte 0 = 60 to rank1
8734 14:48:26.587544 Final RX Vref Byte 1 = 52 to rank1==
8735 14:48:26.590828 Dram Type= 6, Freq= 0, CH_1, rank 0
8736 14:48:26.597027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 14:48:26.597109 ==
8738 14:48:26.597172 DQS Delay:
8739 14:48:26.597230 DQS0 = 0, DQS1 = 0
8740 14:48:26.600524 DQM Delay:
8741 14:48:26.600635 DQM0 = 134, DQM1 = 130
8742 14:48:26.603793 DQ Delay:
8743 14:48:26.607059 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8744 14:48:26.610531 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8745 14:48:26.613494 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8746 14:48:26.616659 DQ12 =136, DQ13 =136, DQ14 =140, DQ15 =140
8747 14:48:26.616741
8748 14:48:26.616803
8749 14:48:26.616860
8750 14:48:26.620253 [DramC_TX_OE_Calibration] TA2
8751 14:48:26.623488 Original DQ_B0 (3 6) =30, OEN = 27
8752 14:48:26.626969 Original DQ_B1 (3 6) =30, OEN = 27
8753 14:48:26.630273 24, 0x0, End_B0=24 End_B1=24
8754 14:48:26.630356 25, 0x0, End_B0=25 End_B1=25
8755 14:48:26.633665 26, 0x0, End_B0=26 End_B1=26
8756 14:48:26.636708 27, 0x0, End_B0=27 End_B1=27
8757 14:48:26.640413 28, 0x0, End_B0=28 End_B1=28
8758 14:48:26.643378 29, 0x0, End_B0=29 End_B1=29
8759 14:48:26.643460 30, 0x0, End_B0=30 End_B1=30
8760 14:48:26.646518 31, 0x5151, End_B0=30 End_B1=30
8761 14:48:26.650379 Byte0 end_step=30 best_step=27
8762 14:48:26.653485 Byte1 end_step=30 best_step=27
8763 14:48:26.656453 Byte0 TX OE(2T, 0.5T) = (3, 3)
8764 14:48:26.660113 Byte1 TX OE(2T, 0.5T) = (3, 3)
8765 14:48:26.660194
8766 14:48:26.660256
8767 14:48:26.666963 [DQSOSCAuto] RK0, (LSB)MR18= 0x1522, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8768 14:48:26.670069 CH1 RK0: MR19=303, MR18=1522
8769 14:48:26.676606 CH1_RK0: MR19=0x303, MR18=0x1522, DQSOSC=392, MR23=63, INC=24, DEC=16
8770 14:48:26.676687
8771 14:48:26.680124 ----->DramcWriteLeveling(PI) begin...
8772 14:48:26.680206 ==
8773 14:48:26.683329 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 14:48:26.686602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 14:48:26.686709 ==
8776 14:48:26.689925 Write leveling (Byte 0): 27 => 27
8777 14:48:26.693349 Write leveling (Byte 1): 27 => 27
8778 14:48:26.696520 DramcWriteLeveling(PI) end<-----
8779 14:48:26.696600
8780 14:48:26.696663 ==
8781 14:48:26.699893 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 14:48:26.703036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 14:48:26.703122 ==
8784 14:48:26.706590 [Gating] SW mode calibration
8785 14:48:26.712985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8786 14:48:26.719587 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8787 14:48:26.723262 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 14:48:26.729903 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 14:48:26.733208 1 4 8 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (0 0)
8790 14:48:26.736517 1 4 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 1)
8791 14:48:26.743170 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 14:48:26.746408 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 14:48:26.749525 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 14:48:26.756230 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 14:48:26.759468 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 14:48:26.762711 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 14:48:26.769404 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8798 14:48:26.773221 1 5 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 1)
8799 14:48:26.776146 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 14:48:26.779847 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 14:48:26.786285 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 14:48:26.789570 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 14:48:26.792646 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 14:48:26.799525 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 14:48:26.802887 1 6 8 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
8806 14:48:26.805993 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
8807 14:48:26.812690 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 14:48:26.815864 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 14:48:26.819698 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 14:48:26.826311 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 14:48:26.829469 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 14:48:26.832690 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 14:48:26.839436 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8814 14:48:26.842673 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8815 14:48:26.846006 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8816 14:48:26.852451 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 14:48:26.855951 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 14:48:26.859079 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 14:48:26.865930 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 14:48:26.869270 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 14:48:26.872467 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 14:48:26.879398 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 14:48:26.882515 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 14:48:26.885785 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 14:48:26.892829 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 14:48:26.896058 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 14:48:26.899316 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 14:48:26.905600 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 14:48:26.908745 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8830 14:48:26.912459 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8831 14:48:26.915739 Total UI for P1: 0, mck2ui 16
8832 14:48:26.918736 best dqsien dly found for B1: ( 1, 9, 8)
8833 14:48:26.922468 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 14:48:26.925400 Total UI for P1: 0, mck2ui 16
8835 14:48:26.928995 best dqsien dly found for B0: ( 1, 9, 12)
8836 14:48:26.932231 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8837 14:48:26.935443 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8838 14:48:26.938896
8839 14:48:26.942524 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8840 14:48:26.945603 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8841 14:48:26.948986 [Gating] SW calibration Done
8842 14:48:26.949103 ==
8843 14:48:26.951895 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 14:48:26.955964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 14:48:26.956046 ==
8846 14:48:26.956109 RX Vref Scan: 0
8847 14:48:26.959059
8848 14:48:26.959139 RX Vref 0 -> 0, step: 1
8849 14:48:26.959202
8850 14:48:26.962224 RX Delay 0 -> 252, step: 8
8851 14:48:26.965459 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8852 14:48:26.968757 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8853 14:48:26.975361 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8854 14:48:26.978547 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8855 14:48:26.981826 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8856 14:48:26.985206 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8857 14:48:26.988521 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8858 14:48:26.995247 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8859 14:48:26.998438 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8860 14:48:27.001541 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8861 14:48:27.005346 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8862 14:48:27.008544 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8863 14:48:27.015045 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8864 14:48:27.018694 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8865 14:48:27.022373 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8866 14:48:27.025345 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8867 14:48:27.025426 ==
8868 14:48:27.028930 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 14:48:27.035181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 14:48:27.035266 ==
8871 14:48:27.035331 DQS Delay:
8872 14:48:27.035390 DQS0 = 0, DQS1 = 0
8873 14:48:27.038343 DQM Delay:
8874 14:48:27.038423 DQM0 = 136, DQM1 = 134
8875 14:48:27.041734 DQ Delay:
8876 14:48:27.045346 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8877 14:48:27.048561 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8878 14:48:27.051651 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8879 14:48:27.054946 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8880 14:48:27.055027
8881 14:48:27.055089
8882 14:48:27.055146 ==
8883 14:48:27.058629 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 14:48:27.062011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 14:48:27.065053 ==
8886 14:48:27.065133
8887 14:48:27.065195
8888 14:48:27.065254 TX Vref Scan disable
8889 14:48:27.068309 == TX Byte 0 ==
8890 14:48:27.072185 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8891 14:48:27.074755 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8892 14:48:27.078559 == TX Byte 1 ==
8893 14:48:27.081783 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8894 14:48:27.085653 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8895 14:48:27.085734 ==
8896 14:48:27.088122 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 14:48:27.094618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 14:48:27.094699 ==
8899 14:48:27.107943
8900 14:48:27.111163 TX Vref early break, caculate TX vref
8901 14:48:27.114420 TX Vref=16, minBit 2, minWin=23, winSum=384
8902 14:48:27.117633 TX Vref=18, minBit 0, minWin=24, winSum=393
8903 14:48:27.120804 TX Vref=20, minBit 0, minWin=24, winSum=401
8904 14:48:27.123919 TX Vref=22, minBit 0, minWin=25, winSum=412
8905 14:48:27.127245 TX Vref=24, minBit 0, minWin=24, winSum=416
8906 14:48:27.134300 TX Vref=26, minBit 0, minWin=25, winSum=427
8907 14:48:27.137713 TX Vref=28, minBit 0, minWin=25, winSum=427
8908 14:48:27.140789 TX Vref=30, minBit 1, minWin=25, winSum=421
8909 14:48:27.144021 TX Vref=32, minBit 0, minWin=25, winSum=416
8910 14:48:27.147278 TX Vref=34, minBit 0, minWin=24, winSum=405
8911 14:48:27.150848 TX Vref=36, minBit 0, minWin=24, winSum=398
8912 14:48:27.157433 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8913 14:48:27.157514
8914 14:48:27.160496 Final TX Range 0 Vref 26
8915 14:48:27.160577
8916 14:48:27.160639 ==
8917 14:48:27.163686 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 14:48:27.166858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 14:48:27.166964 ==
8920 14:48:27.167054
8921 14:48:27.170688
8922 14:48:27.170794 TX Vref Scan disable
8923 14:48:27.177543 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8924 14:48:27.177625 == TX Byte 0 ==
8925 14:48:27.180488 u2DelayCellOfst[0]=16 cells (5 PI)
8926 14:48:27.183802 u2DelayCellOfst[1]=10 cells (3 PI)
8927 14:48:27.186950 u2DelayCellOfst[2]=0 cells (0 PI)
8928 14:48:27.190585 u2DelayCellOfst[3]=6 cells (2 PI)
8929 14:48:27.193618 u2DelayCellOfst[4]=6 cells (2 PI)
8930 14:48:27.197563 u2DelayCellOfst[5]=16 cells (5 PI)
8931 14:48:27.200666 u2DelayCellOfst[6]=16 cells (5 PI)
8932 14:48:27.204028 u2DelayCellOfst[7]=6 cells (2 PI)
8933 14:48:27.207344 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8934 14:48:27.210605 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8935 14:48:27.213882 == TX Byte 1 ==
8936 14:48:27.217077 u2DelayCellOfst[8]=0 cells (0 PI)
8937 14:48:27.217180 u2DelayCellOfst[9]=3 cells (1 PI)
8938 14:48:27.220463 u2DelayCellOfst[10]=10 cells (3 PI)
8939 14:48:27.223585 u2DelayCellOfst[11]=3 cells (1 PI)
8940 14:48:27.227315 u2DelayCellOfst[12]=13 cells (4 PI)
8941 14:48:27.230541 u2DelayCellOfst[13]=13 cells (4 PI)
8942 14:48:27.233830 u2DelayCellOfst[14]=13 cells (4 PI)
8943 14:48:27.237027 u2DelayCellOfst[15]=16 cells (5 PI)
8944 14:48:27.243248 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8945 14:48:27.246550 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8946 14:48:27.246663 DramC Write-DBI on
8947 14:48:27.246742 ==
8948 14:48:27.249839 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 14:48:27.256465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 14:48:27.256541 ==
8951 14:48:27.256604
8952 14:48:27.256661
8953 14:48:27.256753 TX Vref Scan disable
8954 14:48:27.261079 == TX Byte 0 ==
8955 14:48:27.264103 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8956 14:48:27.267699 == TX Byte 1 ==
8957 14:48:27.270694 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8958 14:48:27.274346 DramC Write-DBI off
8959 14:48:27.274458
8960 14:48:27.274555 [DATLAT]
8961 14:48:27.274647 Freq=1600, CH1 RK1
8962 14:48:27.274720
8963 14:48:27.277281 DATLAT Default: 0xf
8964 14:48:27.277398 0, 0xFFFF, sum = 0
8965 14:48:27.280747 1, 0xFFFF, sum = 0
8966 14:48:27.284514 2, 0xFFFF, sum = 0
8967 14:48:27.284597 3, 0xFFFF, sum = 0
8968 14:48:27.287199 4, 0xFFFF, sum = 0
8969 14:48:27.287328 5, 0xFFFF, sum = 0
8970 14:48:27.290858 6, 0xFFFF, sum = 0
8971 14:48:27.291035 7, 0xFFFF, sum = 0
8972 14:48:27.294203 8, 0xFFFF, sum = 0
8973 14:48:27.294298 9, 0xFFFF, sum = 0
8974 14:48:27.297257 10, 0xFFFF, sum = 0
8975 14:48:27.297391 11, 0xFFFF, sum = 0
8976 14:48:27.300601 12, 0xFFFF, sum = 0
8977 14:48:27.300686 13, 0xFFFF, sum = 0
8978 14:48:27.303758 14, 0x0, sum = 1
8979 14:48:27.303858 15, 0x0, sum = 2
8980 14:48:27.307302 16, 0x0, sum = 3
8981 14:48:27.307412 17, 0x0, sum = 4
8982 14:48:27.310776 best_step = 15
8983 14:48:27.310893
8984 14:48:27.310957 ==
8985 14:48:27.313676 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 14:48:27.317334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 14:48:27.317417 ==
8988 14:48:27.320521 RX Vref Scan: 0
8989 14:48:27.320603
8990 14:48:27.320666 RX Vref 0 -> 0, step: 1
8991 14:48:27.320725
8992 14:48:27.323733 RX Delay 19 -> 252, step: 4
8993 14:48:27.327054 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8994 14:48:27.334045 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8995 14:48:27.337431 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8996 14:48:27.340503 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8997 14:48:27.343901 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8998 14:48:27.347394 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8999 14:48:27.350663 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9000 14:48:27.357179 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9001 14:48:27.360449 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9002 14:48:27.363567 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9003 14:48:27.366839 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9004 14:48:27.370756 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9005 14:48:27.376851 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9006 14:48:27.380458 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
9007 14:48:27.383605 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9008 14:48:27.386846 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9009 14:48:27.386927 ==
9010 14:48:27.390245 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 14:48:27.397127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 14:48:27.397209 ==
9013 14:48:27.397273 DQS Delay:
9014 14:48:27.400462 DQS0 = 0, DQS1 = 0
9015 14:48:27.400543 DQM Delay:
9016 14:48:27.404382 DQM0 = 134, DQM1 = 131
9017 14:48:27.404478 DQ Delay:
9018 14:48:27.407487 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
9019 14:48:27.410577 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9020 14:48:27.413844 DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =126
9021 14:48:27.417199 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =140
9022 14:48:27.417282
9023 14:48:27.417346
9024 14:48:27.417404
9025 14:48:27.420607 [DramC_TX_OE_Calibration] TA2
9026 14:48:27.424172 Original DQ_B0 (3 6) =30, OEN = 27
9027 14:48:27.427020 Original DQ_B1 (3 6) =30, OEN = 27
9028 14:48:27.430804 24, 0x0, End_B0=24 End_B1=24
9029 14:48:27.430886 25, 0x0, End_B0=25 End_B1=25
9030 14:48:27.433665 26, 0x0, End_B0=26 End_B1=26
9031 14:48:27.437640 27, 0x0, End_B0=27 End_B1=27
9032 14:48:27.440703 28, 0x0, End_B0=28 End_B1=28
9033 14:48:27.443549 29, 0x0, End_B0=29 End_B1=29
9034 14:48:27.443631 30, 0x0, End_B0=30 End_B1=30
9035 14:48:27.447240 31, 0x4545, End_B0=30 End_B1=30
9036 14:48:27.450431 Byte0 end_step=30 best_step=27
9037 14:48:27.454045 Byte1 end_step=30 best_step=27
9038 14:48:27.457208 Byte0 TX OE(2T, 0.5T) = (3, 3)
9039 14:48:27.460450 Byte1 TX OE(2T, 0.5T) = (3, 3)
9040 14:48:27.460531
9041 14:48:27.460594
9042 14:48:27.466901 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
9043 14:48:27.470330 CH1 RK1: MR19=303, MR18=2207
9044 14:48:27.476761 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
9045 14:48:27.480020 [RxdqsGatingPostProcess] freq 1600
9046 14:48:27.483239 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9047 14:48:27.487012 best DQS0 dly(2T, 0.5T) = (1, 1)
9048 14:48:27.489823 best DQS1 dly(2T, 0.5T) = (1, 1)
9049 14:48:27.493488 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9050 14:48:27.496715 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9051 14:48:27.499815 best DQS0 dly(2T, 0.5T) = (1, 1)
9052 14:48:27.503485 best DQS1 dly(2T, 0.5T) = (1, 1)
9053 14:48:27.506765 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9054 14:48:27.510017 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9055 14:48:27.513451 Pre-setting of DQS Precalculation
9056 14:48:27.516501 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9057 14:48:27.523412 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9058 14:48:27.532861 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9059 14:48:27.532943
9060 14:48:27.533006
9061 14:48:27.536206 [Calibration Summary] 3200 Mbps
9062 14:48:27.536303 CH 0, Rank 0
9063 14:48:27.539776 SW Impedance : PASS
9064 14:48:27.539856 DUTY Scan : NO K
9065 14:48:27.542776 ZQ Calibration : PASS
9066 14:48:27.542856 Jitter Meter : NO K
9067 14:48:27.546272 CBT Training : PASS
9068 14:48:27.549798 Write leveling : PASS
9069 14:48:27.549878 RX DQS gating : PASS
9070 14:48:27.553003 RX DQ/DQS(RDDQC) : PASS
9071 14:48:27.556147 TX DQ/DQS : PASS
9072 14:48:27.556228 RX DATLAT : PASS
9073 14:48:27.559488 RX DQ/DQS(Engine): PASS
9074 14:48:27.562822 TX OE : PASS
9075 14:48:27.562903 All Pass.
9076 14:48:27.562966
9077 14:48:27.563024 CH 0, Rank 1
9078 14:48:27.566491 SW Impedance : PASS
9079 14:48:27.569667 DUTY Scan : NO K
9080 14:48:27.569747 ZQ Calibration : PASS
9081 14:48:27.573331 Jitter Meter : NO K
9082 14:48:27.576331 CBT Training : PASS
9083 14:48:27.576448 Write leveling : PASS
9084 14:48:27.579860 RX DQS gating : PASS
9085 14:48:27.583035 RX DQ/DQS(RDDQC) : PASS
9086 14:48:27.583115 TX DQ/DQS : PASS
9087 14:48:27.586370 RX DATLAT : PASS
9088 14:48:27.589630 RX DQ/DQS(Engine): PASS
9089 14:48:27.589736 TX OE : PASS
9090 14:48:27.589827 All Pass.
9091 14:48:27.592751
9092 14:48:27.592886 CH 1, Rank 0
9093 14:48:27.595858 SW Impedance : PASS
9094 14:48:27.595971 DUTY Scan : NO K
9095 14:48:27.599737 ZQ Calibration : PASS
9096 14:48:27.599832 Jitter Meter : NO K
9097 14:48:27.602774 CBT Training : PASS
9098 14:48:27.605923 Write leveling : PASS
9099 14:48:27.606008 RX DQS gating : PASS
9100 14:48:27.609218 RX DQ/DQS(RDDQC) : PASS
9101 14:48:27.612627 TX DQ/DQS : PASS
9102 14:48:27.612713 RX DATLAT : PASS
9103 14:48:27.616289 RX DQ/DQS(Engine): PASS
9104 14:48:27.619543 TX OE : PASS
9105 14:48:27.619656 All Pass.
9106 14:48:27.619754
9107 14:48:27.619878 CH 1, Rank 1
9108 14:48:27.623025 SW Impedance : PASS
9109 14:48:27.625818 DUTY Scan : NO K
9110 14:48:27.625907 ZQ Calibration : PASS
9111 14:48:27.629732 Jitter Meter : NO K
9112 14:48:27.632962 CBT Training : PASS
9113 14:48:27.633044 Write leveling : PASS
9114 14:48:27.636084 RX DQS gating : PASS
9115 14:48:27.639285 RX DQ/DQS(RDDQC) : PASS
9116 14:48:27.639367 TX DQ/DQS : PASS
9117 14:48:27.642890 RX DATLAT : PASS
9118 14:48:27.642972 RX DQ/DQS(Engine): PASS
9119 14:48:27.646168 TX OE : PASS
9120 14:48:27.646250 All Pass.
9121 14:48:27.646314
9122 14:48:27.649397 DramC Write-DBI on
9123 14:48:27.652638 PER_BANK_REFRESH: Hybrid Mode
9124 14:48:27.652719 TX_TRACKING: ON
9125 14:48:27.662739 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9126 14:48:27.669200 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9127 14:48:27.676222 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9128 14:48:27.682738 [FAST_K] Save calibration result to emmc
9129 14:48:27.682830 sync common calibartion params.
9130 14:48:27.685718 sync cbt_mode0:1, 1:1
9131 14:48:27.689231 dram_init: ddr_geometry: 2
9132 14:48:27.689312 dram_init: ddr_geometry: 2
9133 14:48:27.692590 dram_init: ddr_geometry: 2
9134 14:48:27.696075 0:dram_rank_size:100000000
9135 14:48:27.699192 1:dram_rank_size:100000000
9136 14:48:27.702327 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9137 14:48:27.705842 DFS_SHUFFLE_HW_MODE: ON
9138 14:48:27.709613 dramc_set_vcore_voltage set vcore to 725000
9139 14:48:27.712607 Read voltage for 1600, 0
9140 14:48:27.712688 Vio18 = 0
9141 14:48:27.715660 Vcore = 725000
9142 14:48:27.715741 Vdram = 0
9143 14:48:27.715804 Vddq = 0
9144 14:48:27.715862 Vmddr = 0
9145 14:48:27.718887 switch to 3200 Mbps bootup
9146 14:48:27.722698 [DramcRunTimeConfig]
9147 14:48:27.722779 PHYPLL
9148 14:48:27.725938 DPM_CONTROL_AFTERK: ON
9149 14:48:27.726018 PER_BANK_REFRESH: ON
9150 14:48:27.729058 REFRESH_OVERHEAD_REDUCTION: ON
9151 14:48:27.732314 CMD_PICG_NEW_MODE: OFF
9152 14:48:27.732454 XRTWTW_NEW_MODE: ON
9153 14:48:27.735564 XRTRTR_NEW_MODE: ON
9154 14:48:27.735643 TX_TRACKING: ON
9155 14:48:27.738857 RDSEL_TRACKING: OFF
9156 14:48:27.738937 DQS Precalculation for DVFS: ON
9157 14:48:27.742036 RX_TRACKING: OFF
9158 14:48:27.742116 HW_GATING DBG: ON
9159 14:48:27.745999 ZQCS_ENABLE_LP4: ON
9160 14:48:27.748807 RX_PICG_NEW_MODE: ON
9161 14:48:27.748886 TX_PICG_NEW_MODE: ON
9162 14:48:27.752544 ENABLE_RX_DCM_DPHY: ON
9163 14:48:27.755705 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9164 14:48:27.755786 DUMMY_READ_FOR_TRACKING: OFF
9165 14:48:27.758962 !!! SPM_CONTROL_AFTERK: OFF
9166 14:48:27.762215 !!! SPM could not control APHY
9167 14:48:27.765510 IMPEDANCE_TRACKING: ON
9168 14:48:27.765590 TEMP_SENSOR: ON
9169 14:48:27.769325 HW_SAVE_FOR_SR: OFF
9170 14:48:27.772197 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9171 14:48:27.775265 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9172 14:48:27.775345 Read ODT Tracking: ON
9173 14:48:27.778847 Refresh Rate DeBounce: ON
9174 14:48:27.782145 DFS_NO_QUEUE_FLUSH: ON
9175 14:48:27.785403 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9176 14:48:27.785484 ENABLE_DFS_RUNTIME_MRW: OFF
9177 14:48:27.788702 DDR_RESERVE_NEW_MODE: ON
9178 14:48:27.792032 MR_CBT_SWITCH_FREQ: ON
9179 14:48:27.792112 =========================
9180 14:48:27.812032 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9181 14:48:27.815363 dram_init: ddr_geometry: 2
9182 14:48:27.833268 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9183 14:48:27.837048 dram_init: dram init end (result: 0)
9184 14:48:27.843152 DRAM-K: Full calibration passed in 24489 msecs
9185 14:48:27.846934 MRC: failed to locate region type 0.
9186 14:48:27.847014 DRAM rank0 size:0x100000000,
9187 14:48:27.850185 DRAM rank1 size=0x100000000
9188 14:48:27.860043 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9189 14:48:27.866395 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9190 14:48:27.873372 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9191 14:48:27.880202 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9192 14:48:27.883415 DRAM rank0 size:0x100000000,
9193 14:48:27.886401 DRAM rank1 size=0x100000000
9194 14:48:27.886504 CBMEM:
9195 14:48:27.890182 IMD: root @ 0xfffff000 254 entries.
9196 14:48:27.893484 IMD: root @ 0xffffec00 62 entries.
9197 14:48:27.896666 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9198 14:48:27.899880 WARNING: RO_VPD is uninitialized or empty.
9199 14:48:27.906467 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9200 14:48:27.913565 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9201 14:48:27.926154 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9202 14:48:27.937809 BS: romstage times (exec / console): total (unknown) / 24015 ms
9203 14:48:27.937891
9204 14:48:27.937954
9205 14:48:27.947389 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9206 14:48:27.950966 ARM64: Exception handlers installed.
9207 14:48:27.954226 ARM64: Testing exception
9208 14:48:27.957510 ARM64: Done test exception
9209 14:48:27.957592 Enumerating buses...
9210 14:48:27.961294 Show all devs... Before device enumeration.
9211 14:48:27.964397 Root Device: enabled 1
9212 14:48:27.967888 CPU_CLUSTER: 0: enabled 1
9213 14:48:27.967970 CPU: 00: enabled 1
9214 14:48:27.970930 Compare with tree...
9215 14:48:27.971012 Root Device: enabled 1
9216 14:48:27.974059 CPU_CLUSTER: 0: enabled 1
9217 14:48:27.977197 CPU: 00: enabled 1
9218 14:48:27.977279 Root Device scanning...
9219 14:48:27.980930 scan_static_bus for Root Device
9220 14:48:27.983988 CPU_CLUSTER: 0 enabled
9221 14:48:27.987230 scan_static_bus for Root Device done
9222 14:48:27.990344 scan_bus: bus Root Device finished in 8 msecs
9223 14:48:27.990426 done
9224 14:48:27.997236 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9225 14:48:28.000494 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9226 14:48:28.006995 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9227 14:48:28.010240 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9228 14:48:28.014091 Allocating resources...
9229 14:48:28.017463 Reading resources...
9230 14:48:28.020820 Root Device read_resources bus 0 link: 0
9231 14:48:28.020903 DRAM rank0 size:0x100000000,
9232 14:48:28.023843 DRAM rank1 size=0x100000000
9233 14:48:28.027212 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9234 14:48:28.030241 CPU: 00 missing read_resources
9235 14:48:28.036512 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9236 14:48:28.040493 Root Device read_resources bus 0 link: 0 done
9237 14:48:28.040576 Done reading resources.
9238 14:48:28.046814 Show resources in subtree (Root Device)...After reading.
9239 14:48:28.050303 Root Device child on link 0 CPU_CLUSTER: 0
9240 14:48:28.053811 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 14:48:28.063334 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 14:48:28.063418 CPU: 00
9243 14:48:28.066851 Root Device assign_resources, bus 0 link: 0
9244 14:48:28.070148 CPU_CLUSTER: 0 missing set_resources
9245 14:48:28.076904 Root Device assign_resources, bus 0 link: 0 done
9246 14:48:28.076987 Done setting resources.
9247 14:48:28.083597 Show resources in subtree (Root Device)...After assigning values.
9248 14:48:28.086783 Root Device child on link 0 CPU_CLUSTER: 0
9249 14:48:28.090374 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 14:48:28.099868 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 14:48:28.099952 CPU: 00
9252 14:48:28.103435 Done allocating resources.
9253 14:48:28.106622 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9254 14:48:28.109726 Enabling resources...
9255 14:48:28.109809 done.
9256 14:48:28.116848 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9257 14:48:28.116931 Initializing devices...
9258 14:48:28.120282 Root Device init
9259 14:48:28.120401 init hardware done!
9260 14:48:28.123460 0x00000018: ctrlr->caps
9261 14:48:28.126817 52.000 MHz: ctrlr->f_max
9262 14:48:28.126901 0.400 MHz: ctrlr->f_min
9263 14:48:28.130188 0x40ff8080: ctrlr->voltages
9264 14:48:28.130272 sclk: 390625
9265 14:48:28.133612 Bus Width = 1
9266 14:48:28.133694 sclk: 390625
9267 14:48:28.136860 Bus Width = 1
9268 14:48:28.136942 Early init status = 3
9269 14:48:28.142933 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9270 14:48:28.146242 in-header: 03 fc 00 00 01 00 00 00
9271 14:48:28.146324 in-data: 00
9272 14:48:28.152780 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9273 14:48:28.157290 in-header: 03 fd 00 00 00 00 00 00
9274 14:48:28.160506 in-data:
9275 14:48:28.163528 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9276 14:48:28.168485 in-header: 03 fc 00 00 01 00 00 00
9277 14:48:28.171591 in-data: 00
9278 14:48:28.174947 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9279 14:48:28.180256 in-header: 03 fd 00 00 00 00 00 00
9280 14:48:28.183811 in-data:
9281 14:48:28.187412 [SSUSB] Setting up USB HOST controller...
9282 14:48:28.190209 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9283 14:48:28.193840 [SSUSB] phy power-on done.
9284 14:48:28.197466 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9285 14:48:28.204199 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9286 14:48:28.206972 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9287 14:48:28.214121 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9288 14:48:28.220791 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9289 14:48:28.226948 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9290 14:48:28.234001 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9291 14:48:28.240368 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9292 14:48:28.243761 SPM: binary array size = 0x9dc
9293 14:48:28.246952 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9294 14:48:28.253351 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9295 14:48:28.260236 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9296 14:48:28.266679 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9297 14:48:28.269727 configure_display: Starting display init
9298 14:48:28.303687 anx7625_power_on_init: Init interface.
9299 14:48:28.307227 anx7625_disable_pd_protocol: Disabled PD feature.
9300 14:48:28.310175 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9301 14:48:28.338186 anx7625_start_dp_work: Secure OCM version=00
9302 14:48:28.341975 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9303 14:48:28.355974 sp_tx_get_edid_block: EDID Block = 1
9304 14:48:28.459120 Extracted contents:
9305 14:48:28.461961 header: 00 ff ff ff ff ff ff 00
9306 14:48:28.465665 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9307 14:48:28.468942 version: 01 04
9308 14:48:28.472249 basic params: 95 1f 11 78 0a
9309 14:48:28.475479 chroma info: 76 90 94 55 54 90 27 21 50 54
9310 14:48:28.478565 established: 00 00 00
9311 14:48:28.485296 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9312 14:48:28.488516 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9313 14:48:28.495853 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9314 14:48:28.502344 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9315 14:48:28.508929 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9316 14:48:28.511775 extensions: 00
9317 14:48:28.511857 checksum: fb
9318 14:48:28.511921
9319 14:48:28.515256 Manufacturer: IVO Model 57d Serial Number 0
9320 14:48:28.518875 Made week 0 of 2020
9321 14:48:28.518957 EDID version: 1.4
9322 14:48:28.521779 Digital display
9323 14:48:28.525710 6 bits per primary color channel
9324 14:48:28.525817 DisplayPort interface
9325 14:48:28.528604 Maximum image size: 31 cm x 17 cm
9326 14:48:28.531747 Gamma: 220%
9327 14:48:28.531829 Check DPMS levels
9328 14:48:28.535355 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9329 14:48:28.538618 First detailed timing is preferred timing
9330 14:48:28.541876 Established timings supported:
9331 14:48:28.545397 Standard timings supported:
9332 14:48:28.545479 Detailed timings
9333 14:48:28.552053 Hex of detail: 383680a07038204018303c0035ae10000019
9334 14:48:28.555265 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9335 14:48:28.562232 0780 0798 07c8 0820 hborder 0
9336 14:48:28.565482 0438 043b 0447 0458 vborder 0
9337 14:48:28.568258 -hsync -vsync
9338 14:48:28.568369 Did detailed timing
9339 14:48:28.571632 Hex of detail: 000000000000000000000000000000000000
9340 14:48:28.575073 Manufacturer-specified data, tag 0
9341 14:48:28.581514 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9342 14:48:28.581596 ASCII string: InfoVision
9343 14:48:28.588541 Hex of detail: 000000fe00523134304e574635205248200a
9344 14:48:28.591681 ASCII string: R140NWF5 RH
9345 14:48:28.591787 Checksum
9346 14:48:28.591882 Checksum: 0xfb (valid)
9347 14:48:28.598269 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9348 14:48:28.601609 DSI data_rate: 832800000 bps
9349 14:48:28.604823 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9350 14:48:28.611372 anx7625_parse_edid: pixelclock(138800).
9351 14:48:28.614871 hactive(1920), hsync(48), hfp(24), hbp(88)
9352 14:48:28.617939 vactive(1080), vsync(12), vfp(3), vbp(17)
9353 14:48:28.621384 anx7625_dsi_config: config dsi.
9354 14:48:28.628049 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9355 14:48:28.640773 anx7625_dsi_config: success to config DSI
9356 14:48:28.644266 anx7625_dp_start: MIPI phy setup OK.
9357 14:48:28.647206 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9358 14:48:28.651205 mtk_ddp_mode_set invalid vrefresh 60
9359 14:48:28.654292 main_disp_path_setup
9360 14:48:28.654373 ovl_layer_smi_id_en
9361 14:48:28.657346 ovl_layer_smi_id_en
9362 14:48:28.657427 ccorr_config
9363 14:48:28.657490 aal_config
9364 14:48:28.660513 gamma_config
9365 14:48:28.660595 postmask_config
9366 14:48:28.664512 dither_config
9367 14:48:28.667153 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9368 14:48:28.674208 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9369 14:48:28.677564 Root Device init finished in 554 msecs
9370 14:48:28.677646 CPU_CLUSTER: 0 init
9371 14:48:28.687405 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9372 14:48:28.690610 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9373 14:48:28.694075 APU_MBOX 0x190000b0 = 0x10001
9374 14:48:28.697258 APU_MBOX 0x190001b0 = 0x10001
9375 14:48:28.700847 APU_MBOX 0x190005b0 = 0x10001
9376 14:48:28.704414 APU_MBOX 0x190006b0 = 0x10001
9377 14:48:28.707424 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9378 14:48:28.719865 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9379 14:48:28.732464 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9380 14:48:28.738831 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9381 14:48:28.750357 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9382 14:48:28.759851 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9383 14:48:28.762983 CPU_CLUSTER: 0 init finished in 81 msecs
9384 14:48:28.766576 Devices initialized
9385 14:48:28.769885 Show all devs... After init.
9386 14:48:28.769968 Root Device: enabled 1
9387 14:48:28.773062 CPU_CLUSTER: 0: enabled 1
9388 14:48:28.776317 CPU: 00: enabled 1
9389 14:48:28.779586 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9390 14:48:28.782753 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9391 14:48:28.786433 ELOG: NV offset 0x57f000 size 0x1000
9392 14:48:28.793166 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9393 14:48:28.799651 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9394 14:48:28.803046 ELOG: Event(17) added with size 13 at 2024-06-04 14:43:47 UTC
9395 14:48:28.806083 out: cmd=0x121: 03 db 21 01 00 00 00 00
9396 14:48:28.809987 in-header: 03 ba 00 00 2c 00 00 00
9397 14:48:28.823461 in-data: a5 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9398 14:48:28.829906 ELOG: Event(A1) added with size 10 at 2024-06-04 14:43:47 UTC
9399 14:48:28.836533 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9400 14:48:28.842964 ELOG: Event(A0) added with size 9 at 2024-06-04 14:43:47 UTC
9401 14:48:28.846720 elog_add_boot_reason: Logged dev mode boot
9402 14:48:28.849844 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9403 14:48:28.853072 Finalize devices...
9404 14:48:28.853154 Devices finalized
9405 14:48:28.859862 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9406 14:48:28.863411 Writing coreboot table at 0xffe64000
9407 14:48:28.866493 0. 000000000010a000-0000000000113fff: RAMSTAGE
9408 14:48:28.869548 1. 0000000040000000-00000000400fffff: RAM
9409 14:48:28.873060 2. 0000000040100000-000000004032afff: RAMSTAGE
9410 14:48:28.879362 3. 000000004032b000-00000000545fffff: RAM
9411 14:48:28.882976 4. 0000000054600000-000000005465ffff: BL31
9412 14:48:28.886212 5. 0000000054660000-00000000ffe63fff: RAM
9413 14:48:28.892746 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9414 14:48:28.895863 7. 0000000100000000-000000023fffffff: RAM
9415 14:48:28.895950 Passing 5 GPIOs to payload:
9416 14:48:28.902456 NAME | PORT | POLARITY | VALUE
9417 14:48:28.906260 EC in RW | 0x000000aa | low | undefined
9418 14:48:28.912542 EC interrupt | 0x00000005 | low | undefined
9419 14:48:28.916162 TPM interrupt | 0x000000ab | high | undefined
9420 14:48:28.919166 SD card detect | 0x00000011 | high | undefined
9421 14:48:28.926228 speaker enable | 0x00000093 | high | undefined
9422 14:48:28.929316 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9423 14:48:28.932527 in-header: 03 f9 00 00 02 00 00 00
9424 14:48:28.932612 in-data: 02 00
9425 14:48:28.935884 ADC[4]: Raw value=904726 ID=7
9426 14:48:28.939294 ADC[3]: Raw value=213441 ID=1
9427 14:48:28.939378 RAM Code: 0x71
9428 14:48:28.942365 ADC[6]: Raw value=75701 ID=0
9429 14:48:28.946185 ADC[5]: Raw value=212703 ID=1
9430 14:48:28.946267 SKU Code: 0x1
9431 14:48:28.952619 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b33e
9432 14:48:28.956387 coreboot table: 964 bytes.
9433 14:48:28.959489 IMD ROOT 0. 0xfffff000 0x00001000
9434 14:48:28.962667 IMD SMALL 1. 0xffffe000 0x00001000
9435 14:48:28.965830 RO MCACHE 2. 0xffffc000 0x00001104
9436 14:48:28.969256 CONSOLE 3. 0xfff7c000 0x00080000
9437 14:48:28.972713 FMAP 4. 0xfff7b000 0x00000452
9438 14:48:28.975690 TIME STAMP 5. 0xfff7a000 0x00000910
9439 14:48:28.979058 VBOOT WORK 6. 0xfff66000 0x00014000
9440 14:48:28.982540 RAMOOPS 7. 0xffe66000 0x00100000
9441 14:48:28.985525 COREBOOT 8. 0xffe64000 0x00002000
9442 14:48:28.985607 IMD small region:
9443 14:48:28.988736 IMD ROOT 0. 0xffffec00 0x00000400
9444 14:48:28.992505 VPD 1. 0xffffeb80 0x0000006c
9445 14:48:28.995783 MMC STATUS 2. 0xffffeb60 0x00000004
9446 14:48:29.002094 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9447 14:48:29.005820 Probing TPM: done!
9448 14:48:29.008822 Connected to device vid:did:rid of 1ae0:0028:00
9449 14:48:29.019040 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9450 14:48:29.022321 Initialized TPM device CR50 revision 0
9451 14:48:29.026332 Checking cr50 for pending updates
9452 14:48:29.029369 Reading cr50 TPM mode
9453 14:48:29.038456 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9454 14:48:29.044739 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9455 14:48:29.084665 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9456 14:48:29.087740 Checking segment from ROM address 0x40100000
9457 14:48:29.091429 Checking segment from ROM address 0x4010001c
9458 14:48:29.097950 Loading segment from ROM address 0x40100000
9459 14:48:29.098033 code (compression=0)
9460 14:48:29.107984 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9461 14:48:29.114442 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9462 14:48:29.114525 it's not compressed!
9463 14:48:29.121457 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9464 14:48:29.127742 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9465 14:48:29.145050 Loading segment from ROM address 0x4010001c
9466 14:48:29.145178 Entry Point 0x80000000
9467 14:48:29.148842 Loaded segments
9468 14:48:29.151888 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9469 14:48:29.158591 Jumping to boot code at 0x80000000(0xffe64000)
9470 14:48:29.164939 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9471 14:48:29.171898 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9472 14:48:29.179774 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9473 14:48:29.182734 Checking segment from ROM address 0x40100000
9474 14:48:29.185842 Checking segment from ROM address 0x4010001c
9475 14:48:29.193506 Loading segment from ROM address 0x40100000
9476 14:48:29.193589 code (compression=1)
9477 14:48:29.199230 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9478 14:48:29.209257 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9479 14:48:29.209342 using LZMA
9480 14:48:29.218115 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9481 14:48:29.224477 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9482 14:48:29.228091 Loading segment from ROM address 0x4010001c
9483 14:48:29.228202 Entry Point 0x54601000
9484 14:48:29.231277 Loaded segments
9485 14:48:29.234391 NOTICE: MT8192 bl31_setup
9486 14:48:29.241360 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9487 14:48:29.245197 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9488 14:48:29.248280 WARNING: region 0:
9489 14:48:29.251917 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9490 14:48:29.251993 WARNING: region 1:
9491 14:48:29.258785 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9492 14:48:29.258866 WARNING: region 2:
9493 14:48:29.265228 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9494 14:48:29.268358 WARNING: region 3:
9495 14:48:29.271528 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9496 14:48:29.275231 WARNING: region 4:
9497 14:48:29.278355 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9498 14:48:29.281438 WARNING: region 5:
9499 14:48:29.285412 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 14:48:29.288326 WARNING: region 6:
9501 14:48:29.291554 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 14:48:29.291624 WARNING: region 7:
9503 14:48:29.298194 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 14:48:29.304954 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9505 14:48:29.308130 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9506 14:48:29.311949 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9507 14:48:29.318381 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9508 14:48:29.321412 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9509 14:48:29.324952 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9510 14:48:29.331700 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9511 14:48:29.335038 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9512 14:48:29.338399 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9513 14:48:29.344974 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9514 14:48:29.348166 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9515 14:48:29.354756 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9516 14:48:29.358342 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9517 14:48:29.361476 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9518 14:48:29.368144 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9519 14:48:29.371657 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9520 14:48:29.374907 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9521 14:48:29.381691 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9522 14:48:29.384781 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9523 14:48:29.388533 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9524 14:48:29.394954 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9525 14:48:29.398184 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9526 14:48:29.404680 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9527 14:48:29.408520 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9528 14:48:29.415271 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9529 14:48:29.418565 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9530 14:48:29.421695 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9531 14:48:29.428259 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9532 14:48:29.432017 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9533 14:48:29.435060 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9534 14:48:29.441666 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9535 14:48:29.445350 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9536 14:48:29.448331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9537 14:48:29.455031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9538 14:48:29.458838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9539 14:48:29.462049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9540 14:48:29.465378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9541 14:48:29.471553 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9542 14:48:29.475354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9543 14:48:29.478341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9544 14:48:29.481663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9545 14:48:29.488258 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9546 14:48:29.491903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9547 14:48:29.495150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9548 14:48:29.498336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9549 14:48:29.505434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9550 14:48:29.508510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9551 14:48:29.511999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9552 14:48:29.518490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9553 14:48:29.522105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9554 14:48:29.525291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9555 14:48:29.532290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9556 14:48:29.535516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9557 14:48:29.541862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9558 14:48:29.545541 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9559 14:48:29.551866 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9560 14:48:29.555801 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9561 14:48:29.558907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9562 14:48:29.565516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9563 14:48:29.568698 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9564 14:48:29.575272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9565 14:48:29.579001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9566 14:48:29.585570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9567 14:48:29.588511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9568 14:48:29.592222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9569 14:48:29.598834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9570 14:48:29.602066 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9571 14:48:29.608832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9572 14:48:29.612031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9573 14:48:29.618843 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9574 14:48:29.622329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9575 14:48:29.625589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9576 14:48:29.632184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9577 14:48:29.635367 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9578 14:48:29.641798 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9579 14:48:29.645575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9580 14:48:29.652298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9581 14:48:29.655435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9582 14:48:29.661887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9583 14:48:29.665123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9584 14:48:29.668888 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9585 14:48:29.675400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9586 14:48:29.678690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9587 14:48:29.685373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9588 14:48:29.689074 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9589 14:48:29.692051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9590 14:48:29.698493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9591 14:48:29.702241 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9592 14:48:29.708886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9593 14:48:29.712138 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9594 14:48:29.718921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9595 14:48:29.722113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9596 14:48:29.725326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9597 14:48:29.732073 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9598 14:48:29.735271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9599 14:48:29.741826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9600 14:48:29.745467 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9601 14:48:29.748616 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9602 14:48:29.752562 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9603 14:48:29.759229 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9604 14:48:29.762545 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9605 14:48:29.765619 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9606 14:48:29.772297 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9607 14:48:29.775380 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9608 14:48:29.782353 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9609 14:48:29.785504 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9610 14:48:29.788844 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9611 14:48:29.796047 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9612 14:48:29.799174 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9613 14:48:29.805956 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9614 14:48:29.808864 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9615 14:48:29.812188 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9616 14:48:29.819191 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9617 14:48:29.822256 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9618 14:48:29.828892 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9619 14:48:29.832478 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9620 14:48:29.835662 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9621 14:48:29.838764 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9622 14:48:29.845374 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9623 14:48:29.849295 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9624 14:48:29.852242 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9625 14:48:29.855858 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9626 14:48:29.862261 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9627 14:48:29.865942 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9628 14:48:29.869239 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9629 14:48:29.875728 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9630 14:48:29.879140 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9631 14:48:29.885567 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9632 14:48:29.889473 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9633 14:48:29.892451 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9634 14:48:29.898727 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9635 14:48:29.902594 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9636 14:48:29.905784 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9637 14:48:29.912683 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9638 14:48:29.916118 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9639 14:48:29.922851 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9640 14:48:29.925715 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9641 14:48:29.928921 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9642 14:48:29.936182 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9643 14:48:29.939049 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9644 14:48:29.945952 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9645 14:48:29.949053 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9646 14:48:29.952592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9647 14:48:29.958974 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9648 14:48:29.962742 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9649 14:48:29.965672 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9650 14:48:29.972451 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9651 14:48:29.975594 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9652 14:48:29.982508 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9653 14:48:29.985789 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9654 14:48:29.989534 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9655 14:48:29.995748 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9656 14:48:29.999494 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9657 14:48:30.002489 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9658 14:48:30.009566 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9659 14:48:30.012714 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9660 14:48:30.019559 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9661 14:48:30.022669 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9662 14:48:30.026406 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9663 14:48:30.032897 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9664 14:48:30.036127 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9665 14:48:30.042550 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9666 14:48:30.045845 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9667 14:48:30.049478 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9668 14:48:30.056199 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9669 14:48:30.059565 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9670 14:48:30.062610 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9671 14:48:30.069080 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9672 14:48:30.072378 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9673 14:48:30.078864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9674 14:48:30.082538 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9675 14:48:30.088973 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9676 14:48:30.092113 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9677 14:48:30.095948 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9678 14:48:30.102077 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9679 14:48:30.105824 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9680 14:48:30.112209 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9681 14:48:30.115464 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9682 14:48:30.118730 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9683 14:48:30.125500 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9684 14:48:30.128758 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9685 14:48:30.132115 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9686 14:48:30.138882 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9687 14:48:30.142145 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9688 14:48:30.148515 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9689 14:48:30.151849 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9690 14:48:30.155155 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9691 14:48:30.161580 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9692 14:48:30.165256 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9693 14:48:30.171607 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9694 14:48:30.175381 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9695 14:48:30.178497 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9696 14:48:30.185431 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9697 14:48:30.188458 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9698 14:48:30.195101 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9699 14:48:30.198782 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9700 14:48:30.205016 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9701 14:48:30.208195 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9702 14:48:30.211920 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9703 14:48:30.218424 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9704 14:48:30.221785 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9705 14:48:30.228320 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9706 14:48:30.231524 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9707 14:48:30.235734 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9708 14:48:30.241684 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9709 14:48:30.244834 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9710 14:48:30.251938 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9711 14:48:30.255249 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9712 14:48:30.258565 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9713 14:48:30.265232 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9714 14:48:30.268459 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9715 14:48:30.274924 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9716 14:48:30.278279 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9717 14:48:30.284652 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9718 14:48:30.288434 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9719 14:48:30.291563 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9720 14:48:30.298407 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9721 14:48:30.301836 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9722 14:48:30.308363 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9723 14:48:30.311696 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9724 14:48:30.314656 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9725 14:48:30.321279 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9726 14:48:30.325046 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9727 14:48:30.331491 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9728 14:48:30.335192 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9729 14:48:30.341366 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9730 14:48:30.344582 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9731 14:48:30.347990 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9732 14:48:30.354900 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9733 14:48:30.358121 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9734 14:48:30.361396 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9735 14:48:30.364658 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9736 14:48:30.371648 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9737 14:48:30.374737 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9738 14:48:30.377947 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9739 14:48:30.384908 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9740 14:48:30.387848 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9741 14:48:30.391469 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9742 14:48:30.398269 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9743 14:48:30.401673 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9744 14:48:30.404767 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9745 14:48:30.411956 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9746 14:48:30.414926 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9747 14:48:30.418061 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9748 14:48:30.425106 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9749 14:48:30.427977 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9750 14:48:30.435316 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9751 14:48:30.437887 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9752 14:48:30.441261 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9753 14:48:30.448610 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9754 14:48:30.451572 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9755 14:48:30.455027 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9756 14:48:30.461211 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9757 14:48:30.464472 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9758 14:48:30.468183 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9759 14:48:30.474707 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9760 14:48:30.477902 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9761 14:48:30.484419 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9762 14:48:30.487691 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9763 14:48:30.491064 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9764 14:48:30.498012 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9765 14:48:30.501029 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9766 14:48:30.504737 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9767 14:48:30.511309 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9768 14:48:30.514574 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9769 14:48:30.521173 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9770 14:48:30.524354 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9771 14:48:30.527664 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9772 14:48:30.534456 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9773 14:48:30.537569 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9774 14:48:30.540874 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9775 14:48:30.544445 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9776 14:48:30.547445 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9777 14:48:30.554491 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9778 14:48:30.557276 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9779 14:48:30.560978 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9780 14:48:30.564510 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9781 14:48:30.570696 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9782 14:48:30.574137 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9783 14:48:30.577433 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9784 14:48:30.580962 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9785 14:48:30.587801 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9786 14:48:30.591144 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9787 14:48:30.597667 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9788 14:48:30.600909 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9789 14:48:30.604133 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9790 14:48:30.610729 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9791 14:48:30.614404 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9792 14:48:30.620765 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9793 14:48:30.624003 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9794 14:48:30.627486 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9795 14:48:30.633817 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9796 14:48:30.637166 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9797 14:48:30.643700 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9798 14:48:30.647694 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9799 14:48:30.654309 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9800 14:48:30.657405 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9801 14:48:30.660676 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9802 14:48:30.667552 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9803 14:48:30.670632 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9804 14:48:30.676979 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9805 14:48:30.680375 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9806 14:48:30.683958 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9807 14:48:30.690703 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9808 14:48:30.694119 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9809 14:48:30.700602 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9810 14:48:30.703851 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9811 14:48:30.707186 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9812 14:48:30.713725 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9813 14:48:30.716973 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9814 14:48:30.723531 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9815 14:48:30.727335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9816 14:48:30.730429 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9817 14:48:30.736936 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9818 14:48:30.740317 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9819 14:48:30.747031 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9820 14:48:30.750535 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9821 14:48:30.753436 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9822 14:48:30.760387 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9823 14:48:30.763736 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9824 14:48:30.770039 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9825 14:48:30.773210 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9826 14:48:30.776840 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9827 14:48:30.783844 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9828 14:48:30.787102 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9829 14:48:30.793412 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9830 14:48:30.797026 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9831 14:48:30.803872 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9832 14:48:30.806813 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9833 14:48:30.810049 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9834 14:48:30.816725 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9835 14:48:30.819914 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9836 14:48:30.826541 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9837 14:48:30.830444 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9838 14:48:30.833748 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9839 14:48:30.840273 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9840 14:48:30.843434 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9841 14:48:30.846595 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9842 14:48:30.853212 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9843 14:48:30.857087 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9844 14:48:30.863184 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9845 14:48:30.866729 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9846 14:48:30.873329 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9847 14:48:30.876561 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9848 14:48:30.883391 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9849 14:48:30.886671 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9850 14:48:30.889782 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9851 14:48:30.896248 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9852 14:48:30.899579 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9853 14:48:30.906561 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9854 14:48:30.909661 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9855 14:48:30.912698 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9856 14:48:30.919969 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9857 14:48:30.922898 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9858 14:48:30.929448 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9859 14:48:30.932830 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9860 14:48:30.936200 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9861 14:48:30.942646 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9862 14:48:30.945856 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9863 14:48:30.952482 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9864 14:48:30.956103 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9865 14:48:30.962439 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9866 14:48:30.965720 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9867 14:48:30.972753 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9868 14:48:30.975824 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9869 14:48:30.979101 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9870 14:48:30.986283 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9871 14:48:30.988968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9872 14:48:30.995565 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9873 14:48:30.999020 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9874 14:48:31.005503 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9875 14:48:31.008800 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9876 14:48:31.012083 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9877 14:48:31.018935 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9878 14:48:31.022414 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9879 14:48:31.028818 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9880 14:48:31.031972 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9881 14:48:31.039074 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9882 14:48:31.042063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9883 14:48:31.045275 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9884 14:48:31.052288 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9885 14:48:31.055480 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9886 14:48:31.061714 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9887 14:48:31.065260 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9888 14:48:31.072095 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9889 14:48:31.075402 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9890 14:48:31.081651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9891 14:48:31.085306 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9892 14:48:31.088858 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9893 14:48:31.094980 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9894 14:48:31.098399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9895 14:48:31.105099 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9896 14:48:31.108694 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9897 14:48:31.115173 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9898 14:48:31.118404 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9899 14:48:31.121485 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9900 14:48:31.128173 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9901 14:48:31.131764 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9902 14:48:31.138339 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9903 14:48:31.141884 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9904 14:48:31.148043 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9905 14:48:31.151878 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9906 14:48:31.155082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9907 14:48:31.161510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9908 14:48:31.164827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9909 14:48:31.171750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9910 14:48:31.174803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9911 14:48:31.181424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9912 14:48:31.184585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9913 14:48:31.191197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9914 14:48:31.194986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9915 14:48:31.201321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9916 14:48:31.204463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9917 14:48:31.211244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9918 14:48:31.214481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9919 14:48:31.218106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9920 14:48:31.224721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9921 14:48:31.228181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9922 14:48:31.235089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9923 14:48:31.237904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9924 14:48:31.244795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9925 14:48:31.248490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9926 14:48:31.254815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9927 14:48:31.258039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9928 14:48:31.265006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9929 14:48:31.268176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9930 14:48:31.274427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9931 14:48:31.278203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9932 14:48:31.284738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9933 14:48:31.287790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9934 14:48:31.294714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9935 14:48:31.297853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9936 14:48:31.304304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9937 14:48:31.307983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9938 14:48:31.314672 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9939 14:48:31.314754 INFO: [APUAPC] vio 0
9940 14:48:31.321076 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9941 14:48:31.324654 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9942 14:48:31.327951 INFO: [APUAPC] D0_APC_0: 0x400510
9943 14:48:31.331487 INFO: [APUAPC] D0_APC_1: 0x0
9944 14:48:31.334471 INFO: [APUAPC] D0_APC_2: 0x1540
9945 14:48:31.337974 INFO: [APUAPC] D0_APC_3: 0x0
9946 14:48:31.341437 INFO: [APUAPC] D1_APC_0: 0xffffffff
9947 14:48:31.344827 INFO: [APUAPC] D1_APC_1: 0xffffffff
9948 14:48:31.348337 INFO: [APUAPC] D1_APC_2: 0x3fffff
9949 14:48:31.351039 INFO: [APUAPC] D1_APC_3: 0x0
9950 14:48:31.354445 INFO: [APUAPC] D2_APC_0: 0xffffffff
9951 14:48:31.357948 INFO: [APUAPC] D2_APC_1: 0xffffffff
9952 14:48:31.361072 INFO: [APUAPC] D2_APC_2: 0x3fffff
9953 14:48:31.364286 INFO: [APUAPC] D2_APC_3: 0x0
9954 14:48:31.367416 INFO: [APUAPC] D3_APC_0: 0xffffffff
9955 14:48:31.370737 INFO: [APUAPC] D3_APC_1: 0xffffffff
9956 14:48:31.374168 INFO: [APUAPC] D3_APC_2: 0x3fffff
9957 14:48:31.377873 INFO: [APUAPC] D3_APC_3: 0x0
9958 14:48:31.381239 INFO: [APUAPC] D4_APC_0: 0xffffffff
9959 14:48:31.384498 INFO: [APUAPC] D4_APC_1: 0xffffffff
9960 14:48:31.387639 INFO: [APUAPC] D4_APC_2: 0x3fffff
9961 14:48:31.390512 INFO: [APUAPC] D4_APC_3: 0x0
9962 14:48:31.394177 INFO: [APUAPC] D5_APC_0: 0xffffffff
9963 14:48:31.397503 INFO: [APUAPC] D5_APC_1: 0xffffffff
9964 14:48:31.400917 INFO: [APUAPC] D5_APC_2: 0x3fffff
9965 14:48:31.401022 INFO: [APUAPC] D5_APC_3: 0x0
9966 14:48:31.404430 INFO: [APUAPC] D6_APC_0: 0xffffffff
9967 14:48:31.410756 INFO: [APUAPC] D6_APC_1: 0xffffffff
9968 14:48:31.414128 INFO: [APUAPC] D6_APC_2: 0x3fffff
9969 14:48:31.414232 INFO: [APUAPC] D6_APC_3: 0x0
9970 14:48:31.417158 INFO: [APUAPC] D7_APC_0: 0xffffffff
9971 14:48:31.420366 INFO: [APUAPC] D7_APC_1: 0xffffffff
9972 14:48:31.423566 INFO: [APUAPC] D7_APC_2: 0x3fffff
9973 14:48:31.427303 INFO: [APUAPC] D7_APC_3: 0x0
9974 14:48:31.430221 INFO: [APUAPC] D8_APC_0: 0xffffffff
9975 14:48:31.433584 INFO: [APUAPC] D8_APC_1: 0xffffffff
9976 14:48:31.436614 INFO: [APUAPC] D8_APC_2: 0x3fffff
9977 14:48:31.439911 INFO: [APUAPC] D8_APC_3: 0x0
9978 14:48:31.443176 INFO: [APUAPC] D9_APC_0: 0xffffffff
9979 14:48:31.446819 INFO: [APUAPC] D9_APC_1: 0xffffffff
9980 14:48:31.450034 INFO: [APUAPC] D9_APC_2: 0x3fffff
9981 14:48:31.453436 INFO: [APUAPC] D9_APC_3: 0x0
9982 14:48:31.456572 INFO: [APUAPC] D10_APC_0: 0xffffffff
9983 14:48:31.459903 INFO: [APUAPC] D10_APC_1: 0xffffffff
9984 14:48:31.463165 INFO: [APUAPC] D10_APC_2: 0x3fffff
9985 14:48:31.466733 INFO: [APUAPC] D10_APC_3: 0x0
9986 14:48:31.470223 INFO: [APUAPC] D11_APC_0: 0xffffffff
9987 14:48:31.473455 INFO: [APUAPC] D11_APC_1: 0xffffffff
9988 14:48:31.476484 INFO: [APUAPC] D11_APC_2: 0x3fffff
9989 14:48:31.479786 INFO: [APUAPC] D11_APC_3: 0x0
9990 14:48:31.483223 INFO: [APUAPC] D12_APC_0: 0xffffffff
9991 14:48:31.486421 INFO: [APUAPC] D12_APC_1: 0xffffffff
9992 14:48:31.492868 INFO: [APUAPC] D12_APC_2: 0x3fffff
9993 14:48:31.492995 INFO: [APUAPC] D12_APC_3: 0x0
9994 14:48:31.496256 INFO: [APUAPC] D13_APC_0: 0xffffffff
9995 14:48:31.502890 INFO: [APUAPC] D13_APC_1: 0xffffffff
9996 14:48:31.506004 INFO: [APUAPC] D13_APC_2: 0x3fffff
9997 14:48:31.506112 INFO: [APUAPC] D13_APC_3: 0x0
9998 14:48:31.509819 INFO: [APUAPC] D14_APC_0: 0xffffffff
9999 14:48:31.516582 INFO: [APUAPC] D14_APC_1: 0xffffffff
10000 14:48:31.519786 INFO: [APUAPC] D14_APC_2: 0x3fffff
10001 14:48:31.519867 INFO: [APUAPC] D14_APC_3: 0x0
10002 14:48:31.522850 INFO: [APUAPC] D15_APC_0: 0xffffffff
10003 14:48:31.529436 INFO: [APUAPC] D15_APC_1: 0xffffffff
10004 14:48:31.532982 INFO: [APUAPC] D15_APC_2: 0x3fffff
10005 14:48:31.533058 INFO: [APUAPC] D15_APC_3: 0x0
10006 14:48:31.536145 INFO: [APUAPC] APC_CON: 0x4
10007 14:48:31.539357 INFO: [NOCDAPC] D0_APC_0: 0x0
10008 14:48:31.543146 INFO: [NOCDAPC] D0_APC_1: 0x0
10009 14:48:31.546111 INFO: [NOCDAPC] D1_APC_0: 0x0
10010 14:48:31.549667 INFO: [NOCDAPC] D1_APC_1: 0xfff
10011 14:48:31.552875 INFO: [NOCDAPC] D2_APC_0: 0x0
10012 14:48:31.556213 INFO: [NOCDAPC] D2_APC_1: 0xfff
10013 14:48:31.559301 INFO: [NOCDAPC] D3_APC_0: 0x0
10014 14:48:31.559406 INFO: [NOCDAPC] D3_APC_1: 0xfff
10015 14:48:31.562782 INFO: [NOCDAPC] D4_APC_0: 0x0
10016 14:48:31.565915 INFO: [NOCDAPC] D4_APC_1: 0xfff
10017 14:48:31.569679 INFO: [NOCDAPC] D5_APC_0: 0x0
10018 14:48:31.572758 INFO: [NOCDAPC] D5_APC_1: 0xfff
10019 14:48:31.576300 INFO: [NOCDAPC] D6_APC_0: 0x0
10020 14:48:31.579644 INFO: [NOCDAPC] D6_APC_1: 0xfff
10021 14:48:31.582720 INFO: [NOCDAPC] D7_APC_0: 0x0
10022 14:48:31.585981 INFO: [NOCDAPC] D7_APC_1: 0xfff
10023 14:48:31.589347 INFO: [NOCDAPC] D8_APC_0: 0x0
10024 14:48:31.592516 INFO: [NOCDAPC] D8_APC_1: 0xfff
10025 14:48:31.592595 INFO: [NOCDAPC] D9_APC_0: 0x0
10026 14:48:31.596105 INFO: [NOCDAPC] D9_APC_1: 0xfff
10027 14:48:31.599402 INFO: [NOCDAPC] D10_APC_0: 0x0
10028 14:48:31.602707 INFO: [NOCDAPC] D10_APC_1: 0xfff
10029 14:48:31.606002 INFO: [NOCDAPC] D11_APC_0: 0x0
10030 14:48:31.609339 INFO: [NOCDAPC] D11_APC_1: 0xfff
10031 14:48:31.612466 INFO: [NOCDAPC] D12_APC_0: 0x0
10032 14:48:31.615924 INFO: [NOCDAPC] D12_APC_1: 0xfff
10033 14:48:31.619396 INFO: [NOCDAPC] D13_APC_0: 0x0
10034 14:48:31.622479 INFO: [NOCDAPC] D13_APC_1: 0xfff
10035 14:48:31.625633 INFO: [NOCDAPC] D14_APC_0: 0x0
10036 14:48:31.629061 INFO: [NOCDAPC] D14_APC_1: 0xfff
10037 14:48:31.632281 INFO: [NOCDAPC] D15_APC_0: 0x0
10038 14:48:31.635581 INFO: [NOCDAPC] D15_APC_1: 0xfff
10039 14:48:31.635665 INFO: [NOCDAPC] APC_CON: 0x4
10040 14:48:31.638825 INFO: [APUAPC] set_apusys_apc done
10041 14:48:31.642754 INFO: [DEVAPC] devapc_init done
10042 14:48:31.649179 INFO: GICv3 without legacy support detected.
10043 14:48:31.652618 INFO: ARM GICv3 driver initialized in EL3
10044 14:48:31.655528 INFO: Maximum SPI INTID supported: 639
10045 14:48:31.659484 INFO: BL31: Initializing runtime services
10046 14:48:31.665581 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10047 14:48:31.668818 INFO: SPM: enable CPC mode
10048 14:48:31.672132 INFO: mcdi ready for mcusys-off-idle and system suspend
10049 14:48:31.678863 INFO: BL31: Preparing for EL3 exit to normal world
10050 14:48:31.682204 INFO: Entry point address = 0x80000000
10051 14:48:31.682288 INFO: SPSR = 0x8
10052 14:48:31.689386
10053 14:48:31.689469
10054 14:48:31.689554
10055 14:48:31.692378 Starting depthcharge on Spherion...
10056 14:48:31.692494
10057 14:48:31.692599 Wipe memory regions:
10058 14:48:31.692698
10059 14:48:31.693535 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10060 14:48:31.693678 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10061 14:48:31.693798 Setting prompt string to ['asurada:']
10062 14:48:31.693921 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10063 14:48:31.695889 [0x00000040000000, 0x00000054600000)
10064 14:48:31.818286
10065 14:48:31.818419 [0x00000054660000, 0x00000080000000)
10066 14:48:32.078246
10067 14:48:32.078387 [0x000000821a7280, 0x000000ffe64000)
10068 14:48:32.823139
10069 14:48:32.823297 [0x00000100000000, 0x00000240000000)
10070 14:48:34.710504
10071 14:48:34.714023 Initializing XHCI USB controller at 0x11200000.
10072 14:48:35.751689
10073 14:48:35.754794 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10074 14:48:35.754903
10075 14:48:35.754969
10076 14:48:35.755255 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 14:48:35.855607 asurada: tftpboot 192.168.201.1 14167046/tftp-deploy-mx7et379/kernel/image.itb 14167046/tftp-deploy-mx7et379/kernel/cmdline
10079 14:48:35.856044 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 14:48:35.856133 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10081 14:48:35.860495 tftpboot 192.168.201.1 14167046/tftp-deploy-mx7et379/kernel/image.ittp-deploy-mx7et379/kernel/cmdline
10082 14:48:35.860584
10083 14:48:35.860649 Waiting for link
10084 14:48:36.021181
10085 14:48:36.021322 R8152: Initializing
10086 14:48:36.021394
10087 14:48:36.023916 Version 9 (ocp_data = 6010)
10088 14:48:36.024024
10089 14:48:36.027143 R8152: Done initializing
10090 14:48:36.027275
10091 14:48:36.027385 Adding net device
10092 14:48:37.973523
10093 14:48:37.973664 done.
10094 14:48:37.973731
10095 14:48:37.973791 MAC: 00:e0:4c:78:7a:aa
10096 14:48:37.973848
10097 14:48:37.976631 Sending DHCP discover... done.
10098 14:48:37.976714
10099 14:48:37.979813 Waiting for reply... done.
10100 14:48:37.979895
10101 14:48:37.983698 Sending DHCP request... done.
10102 14:48:37.983783
10103 14:48:38.041485 Waiting for reply... done.
10104 14:48:38.041626
10105 14:48:38.041696 My ip is 192.168.201.12
10106 14:48:38.041757
10107 14:48:38.045348 The DHCP server ip is 192.168.201.1
10108 14:48:38.045431
10109 14:48:38.051672 TFTP server IP predefined by user: 192.168.201.1
10110 14:48:38.051762
10111 14:48:38.058295 Bootfile predefined by user: 14167046/tftp-deploy-mx7et379/kernel/image.itb
10112 14:48:38.058379
10113 14:48:38.061562 Sending tftp read request... done.
10114 14:48:38.061645
10115 14:48:38.064998 Waiting for the transfer...
10116 14:48:38.065159
10117 14:48:38.311121 00000000 ################################################################
10118 14:48:38.311274
10119 14:48:38.553589 00080000 ################################################################
10120 14:48:38.553739
10121 14:48:38.796969 00100000 ################################################################
10122 14:48:38.797114
10123 14:48:39.039935 00180000 ################################################################
10124 14:48:39.040118
10125 14:48:39.284252 00200000 ################################################################
10126 14:48:39.284404
10127 14:48:39.532175 00280000 ################################################################
10128 14:48:39.532361
10129 14:48:39.775852 00300000 ################################################################
10130 14:48:39.776000
10131 14:48:40.027122 00380000 ################################################################
10132 14:48:40.027271
10133 14:48:40.291218 00400000 ################################################################
10134 14:48:40.291397
10135 14:48:40.547343 00480000 ################################################################
10136 14:48:40.547495
10137 14:48:40.790368 00500000 ################################################################
10138 14:48:40.790517
10139 14:48:41.050218 00580000 ################################################################
10140 14:48:41.050367
10141 14:48:41.295923 00600000 ################################################################
10142 14:48:41.296069
10143 14:48:41.566031 00680000 ################################################################
10144 14:48:41.566174
10145 14:48:41.837997 00700000 ################################################################
10146 14:48:41.838134
10147 14:48:42.101065 00780000 ################################################################
10148 14:48:42.101227
10149 14:48:42.366794 00800000 ################################################################
10150 14:48:42.366932
10151 14:48:42.630264 00880000 ################################################################
10152 14:48:42.630404
10153 14:48:42.911099 00900000 ################################################################
10154 14:48:42.911241
10155 14:48:43.192317 00980000 ################################################################
10156 14:48:43.192476
10157 14:48:43.467056 00a00000 ################################################################
10158 14:48:43.467200
10159 14:48:43.733395 00a80000 ################################################################
10160 14:48:43.733569
10161 14:48:43.998682 00b00000 ################################################################
10162 14:48:43.998847
10163 14:48:44.256817 00b80000 ################################################################
10164 14:48:44.256954
10165 14:48:44.500863 00c00000 ################################################################
10166 14:48:44.501001
10167 14:48:44.745470 00c80000 ################################################################
10168 14:48:44.745602
10169 14:48:44.989270 00d00000 ################################################################
10170 14:48:44.989407
10171 14:48:45.233871 00d80000 ################################################################
10172 14:48:45.234013
10173 14:48:45.479043 00e00000 ################################################################
10174 14:48:45.479207
10175 14:48:45.720977 00e80000 ################################################################
10176 14:48:45.721145
10177 14:48:45.964474 00f00000 ################################################################
10178 14:48:45.964615
10179 14:48:46.215057 00f80000 ################################################################
10180 14:48:46.215203
10181 14:48:46.478670 01000000 ################################################################
10182 14:48:46.478836
10183 14:48:46.726581 01080000 ################################################################
10184 14:48:46.726737
10185 14:48:46.974772 01100000 ################################################################
10186 14:48:46.974933
10187 14:48:47.218098 01180000 ################################################################
10188 14:48:47.218261
10189 14:48:47.469170 01200000 ################################################################
10190 14:48:47.469302
10191 14:48:47.741412 01280000 ################################################################
10192 14:48:47.741568
10193 14:48:48.015277 01300000 ################################################################
10194 14:48:48.015424
10195 14:48:48.279960 01380000 ################################################################
10196 14:48:48.280096
10197 14:48:48.529624 01400000 ################################################################
10198 14:48:48.529786
10199 14:48:48.775529 01480000 ################################################################
10200 14:48:48.775701
10201 14:48:49.019981 01500000 ################################################################
10202 14:48:49.020149
10203 14:48:49.267110 01580000 ################################################################
10204 14:48:49.267255
10205 14:48:49.511205 01600000 ################################################################
10206 14:48:49.511355
10207 14:48:49.758048 01680000 ################################################################
10208 14:48:49.758194
10209 14:48:50.001464 01700000 ################################################################
10210 14:48:50.001611
10211 14:48:50.245516 01780000 ################################################################
10212 14:48:50.245668
10213 14:48:50.497734 01800000 ################################################################
10214 14:48:50.497903
10215 14:48:50.743095 01880000 ################################################################
10216 14:48:50.743254
10217 14:48:50.987556 01900000 ################################################################
10218 14:48:50.987701
10219 14:48:51.231849 01980000 ################################################################
10220 14:48:51.231996
10221 14:48:51.487734 01a00000 ################################################################
10222 14:48:51.487901
10223 14:48:51.735047 01a80000 ################################################################
10224 14:48:51.735177
10225 14:48:51.983706 01b00000 ################################################################
10226 14:48:51.983884
10227 14:48:52.232895 01b80000 ################################################################
10228 14:48:52.233031
10229 14:48:52.482592 01c00000 ################################################################
10230 14:48:52.482744
10231 14:48:52.732471 01c80000 ################################################################
10232 14:48:52.732609
10233 14:48:52.984656 01d00000 ################################################################
10234 14:48:52.984783
10235 14:48:53.243868 01d80000 ################################################################
10236 14:48:53.243998
10237 14:48:53.427542 01e00000 ############################################### done.
10238 14:48:53.427669
10239 14:48:53.430638 The bootfile was 31840618 bytes long.
10240 14:48:53.430725
10241 14:48:53.433897 Sending tftp read request... done.
10242 14:48:53.433981
10243 14:48:53.434046 Waiting for the transfer...
10244 14:48:53.434107
10245 14:48:53.437703 00000000 # done.
10246 14:48:53.437788
10247 14:48:53.443786 Command line loaded dynamically from TFTP file: 14167046/tftp-deploy-mx7et379/kernel/cmdline
10248 14:48:53.443869
10249 14:48:53.466946 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14167046/extract-nfsrootfs-pjnyfw_3,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10250 14:48:53.467039
10251 14:48:53.467105 Loading FIT.
10252 14:48:53.467166
10253 14:48:53.470632 Image ramdisk-1 has 18730705 bytes.
10254 14:48:53.470715
10255 14:48:53.473824 Image fdt-1 has 47258 bytes.
10256 14:48:53.473911
10257 14:48:53.477297 Image kernel-1 has 13060619 bytes.
10258 14:48:53.477388
10259 14:48:53.487199 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10260 14:48:53.487317
10261 14:48:53.503501 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10262 14:48:53.503596
10263 14:48:53.507341 Choosing best match conf-1 for compat google,spherion-rev2.
10264 14:48:53.512971
10265 14:48:53.517427 Connected to device vid:did:rid of 1ae0:0028:00
10266 14:48:53.525463
10267 14:48:53.528897 tpm_get_response: command 0x17b, return code 0x0
10268 14:48:53.529009
10269 14:48:53.532667 ec_init: CrosEC protocol v3 supported (256, 248)
10270 14:48:53.536332
10271 14:48:53.540277 tpm_cleanup: add release locality here.
10272 14:48:53.540401
10273 14:48:53.540469 Shutting down all USB controllers.
10274 14:48:53.540529
10275 14:48:53.543245 Removing current net device
10276 14:48:53.543352
10277 14:48:53.549737 Exiting depthcharge with code 4 at timestamp: 51169278
10278 14:48:53.549820
10279 14:48:53.553248 LZMA decompressing kernel-1 to 0x821a6718
10280 14:48:53.553330
10281 14:48:53.556360 LZMA decompressing kernel-1 to 0x40000000
10282 14:48:55.169036
10283 14:48:55.169368 jumping to kernel
10284 14:48:55.170799 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10285 14:48:55.171126 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10286 14:48:55.171385 Setting prompt string to ['Linux version [0-9]']
10287 14:48:55.171655 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10288 14:48:55.171905 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10289 14:48:55.250820
10290 14:48:55.253868 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10291 14:48:55.258154 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10292 14:48:55.258461 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10293 14:48:55.258714 Setting prompt string to []
10294 14:48:55.258966 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10295 14:48:55.259147 Using line separator: #'\n'#
10296 14:48:55.259291 No login prompt set.
10297 14:48:55.259439 Parsing kernel messages
10298 14:48:55.259574 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10299 14:48:55.259817 [login-action] Waiting for messages, (timeout 00:04:02)
10300 14:48:55.259974 Waiting using forced prompt support (timeout 00:02:01)
10301 14:48:55.277105 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10302 14:48:55.281001 [ 0.000000] random: crng init done
10303 14:48:55.287212 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10304 14:48:55.290306 [ 0.000000] efi: UEFI not found.
10305 14:48:55.297249 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10306 14:48:55.303581 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10307 14:48:55.313503 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10308 14:48:55.323476 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10309 14:48:55.330367 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10310 14:48:55.337014 [ 0.000000] printk: bootconsole [mtk8250] enabled
10311 14:48:55.343248 [ 0.000000] NUMA: No NUMA configuration found
10312 14:48:55.350084 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10313 14:48:55.354022 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10314 14:48:55.356642 [ 0.000000] Zone ranges:
10315 14:48:55.363461 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10316 14:48:55.366829 [ 0.000000] DMA32 empty
10317 14:48:55.373649 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10318 14:48:55.377042 [ 0.000000] Movable zone start for each node
10319 14:48:55.380531 [ 0.000000] Early memory node ranges
10320 14:48:55.386844 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10321 14:48:55.393618 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10322 14:48:55.399786 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10323 14:48:55.406964 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10324 14:48:55.410066 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10325 14:48:55.417039 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10326 14:48:55.475044 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10327 14:48:55.481870 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10328 14:48:55.488719 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10329 14:48:55.491969 [ 0.000000] psci: probing for conduit method from DT.
10330 14:48:55.498782 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10331 14:48:55.502006 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10332 14:48:55.508220 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10333 14:48:55.512117 [ 0.000000] psci: SMC Calling Convention v1.2
10334 14:48:55.517946 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10335 14:48:55.521686 [ 0.000000] Detected VIPT I-cache on CPU0
10336 14:48:55.528257 [ 0.000000] CPU features: detected: GIC system register CPU interface
10337 14:48:55.534552 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10338 14:48:55.541651 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10339 14:48:55.548215 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10340 14:48:55.554547 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10341 14:48:55.564723 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10342 14:48:55.567627 [ 0.000000] alternatives: applying boot alternatives
10343 14:48:55.574588 [ 0.000000] Fallback order for Node 0: 0
10344 14:48:55.581019 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10345 14:48:55.584603 [ 0.000000] Policy zone: Normal
10346 14:48:55.607614 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14167046/extract-nfsrootfs-pjnyfw_3,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10347 14:48:55.617603 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10348 14:48:55.628528 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10349 14:48:55.638794 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10350 14:48:55.645391 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10351 14:48:55.648526 <6>[ 0.000000] software IO TLB: area num 8.
10352 14:48:55.705489 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10353 14:48:55.855033 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10354 14:48:55.861881 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10355 14:48:55.868560 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10356 14:48:55.871376 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10357 14:48:55.878633 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10358 14:48:55.884637 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10359 14:48:55.888096 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10360 14:48:55.897878 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10361 14:48:55.904715 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10362 14:48:55.911156 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10363 14:48:55.917955 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10364 14:48:55.920967 <6>[ 0.000000] GICv3: 608 SPIs implemented
10365 14:48:55.924287 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10366 14:48:55.930905 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10367 14:48:55.934580 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10368 14:48:55.941284 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10369 14:48:55.954805 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10370 14:48:55.964232 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10371 14:48:55.974227 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10372 14:48:55.980965 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10373 14:48:55.994791 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10374 14:48:56.001474 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10375 14:48:56.008334 <6>[ 0.009183] Console: colour dummy device 80x25
10376 14:48:56.018185 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10377 14:48:56.021606 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10378 14:48:56.027950 <6>[ 0.029224] LSM: Security Framework initializing
10379 14:48:56.034630 <6>[ 0.034160] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10380 14:48:56.044923 <6>[ 0.041974] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10381 14:48:56.051368 <6>[ 0.051433] cblist_init_generic: Setting adjustable number of callback queues.
10382 14:48:56.058054 <6>[ 0.058877] cblist_init_generic: Setting shift to 3 and lim to 1.
10383 14:48:56.064672 <6>[ 0.065215] cblist_init_generic: Setting adjustable number of callback queues.
10384 14:48:56.071394 <6>[ 0.072642] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 14:48:56.078240 <6>[ 0.079042] rcu: Hierarchical SRCU implementation.
10386 14:48:56.084586 <6>[ 0.084058] rcu: Max phase no-delay instances is 1000.
10387 14:48:56.088168 <6>[ 0.091085] EFI services will not be available.
10388 14:48:56.095136 <6>[ 0.096073] smp: Bringing up secondary CPUs ...
10389 14:48:56.102413 <6>[ 0.101122] Detected VIPT I-cache on CPU1
10390 14:48:56.109044 <6>[ 0.101195] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10391 14:48:56.115236 <6>[ 0.101225] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10392 14:48:56.119127 <6>[ 0.101565] Detected VIPT I-cache on CPU2
10393 14:48:56.128675 <6>[ 0.101618] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10394 14:48:56.135149 <6>[ 0.101636] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10395 14:48:56.139039 <6>[ 0.101893] Detected VIPT I-cache on CPU3
10396 14:48:56.145408 <6>[ 0.101939] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10397 14:48:56.151821 <6>[ 0.101953] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10398 14:48:56.155039 <6>[ 0.102257] CPU features: detected: Spectre-v4
10399 14:48:56.161876 <6>[ 0.102263] CPU features: detected: Spectre-BHB
10400 14:48:56.164876 <6>[ 0.102268] Detected PIPT I-cache on CPU4
10401 14:48:56.171574 <6>[ 0.102325] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10402 14:48:56.178709 <6>[ 0.102340] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10403 14:48:56.185211 <6>[ 0.102631] Detected PIPT I-cache on CPU5
10404 14:48:56.191667 <6>[ 0.102693] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10405 14:48:56.198432 <6>[ 0.102709] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10406 14:48:56.201646 <6>[ 0.102991] Detected PIPT I-cache on CPU6
10407 14:48:56.208000 <6>[ 0.103055] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10408 14:48:56.214681 <6>[ 0.103071] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10409 14:48:56.222047 <6>[ 0.103371] Detected PIPT I-cache on CPU7
10410 14:48:56.228376 <6>[ 0.103435] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10411 14:48:56.235333 <6>[ 0.103451] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10412 14:48:56.238509 <6>[ 0.103498] smp: Brought up 1 node, 8 CPUs
10413 14:48:56.244771 <6>[ 0.244850] SMP: Total of 8 processors activated.
10414 14:48:56.248507 <6>[ 0.249801] CPU features: detected: 32-bit EL0 Support
10415 14:48:56.258133 <6>[ 0.255164] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10416 14:48:56.264798 <6>[ 0.263964] CPU features: detected: Common not Private translations
10417 14:48:56.268062 <6>[ 0.270440] CPU features: detected: CRC32 instructions
10418 14:48:56.274788 <6>[ 0.275825] CPU features: detected: RCpc load-acquire (LDAPR)
10419 14:48:56.281630 <6>[ 0.281785] CPU features: detected: LSE atomic instructions
10420 14:48:56.288023 <6>[ 0.287566] CPU features: detected: Privileged Access Never
10421 14:48:56.291318 <6>[ 0.293346] CPU features: detected: RAS Extension Support
10422 14:48:56.300759 <6>[ 0.298955] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10423 14:48:56.304267 <6>[ 0.306177] CPU: All CPU(s) started at EL2
10424 14:48:56.310550 <6>[ 0.310520] alternatives: applying system-wide alternatives
10425 14:48:56.320115 <6>[ 0.321408] devtmpfs: initialized
10426 14:48:56.332523 <6>[ 0.330352] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10427 14:48:56.342761 <6>[ 0.340316] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10428 14:48:56.348991 <6>[ 0.348332] pinctrl core: initialized pinctrl subsystem
10429 14:48:56.352566 <6>[ 0.354983] DMI not present or invalid.
10430 14:48:56.358792 <6>[ 0.359395] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10431 14:48:56.368382 <6>[ 0.366276] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10432 14:48:56.375297 <6>[ 0.373862] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10433 14:48:56.385397 <6>[ 0.382079] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10434 14:48:56.388645 <6>[ 0.390321] audit: initializing netlink subsys (disabled)
10435 14:48:56.398654 <5>[ 0.396016] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10436 14:48:56.405033 <6>[ 0.396721] thermal_sys: Registered thermal governor 'step_wise'
10437 14:48:56.412185 <6>[ 0.403985] thermal_sys: Registered thermal governor 'power_allocator'
10438 14:48:56.415666 <6>[ 0.410238] cpuidle: using governor menu
10439 14:48:56.418381 <6>[ 0.421200] NET: Registered PF_QIPCRTR protocol family
10440 14:48:56.428321 <6>[ 0.426685] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10441 14:48:56.431892 <6>[ 0.433790] ASID allocator initialised with 32768 entries
10442 14:48:56.439325 <6>[ 0.440365] Serial: AMBA PL011 UART driver
10443 14:48:56.447418 <4>[ 0.449149] Trying to register duplicate clock ID: 134
10444 14:48:56.507919 <6>[ 0.512484] KASLR enabled
10445 14:48:56.522831 <6>[ 0.520386] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10446 14:48:56.528878 <6>[ 0.527395] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10447 14:48:56.535614 <6>[ 0.533887] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10448 14:48:56.542289 <6>[ 0.540888] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10449 14:48:56.548638 <6>[ 0.547372] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10450 14:48:56.555918 <6>[ 0.554377] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10451 14:48:56.562186 <6>[ 0.560861] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10452 14:48:56.568930 <6>[ 0.567866] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10453 14:48:56.572674 <6>[ 0.575370] ACPI: Interpreter disabled.
10454 14:48:56.580855 <6>[ 0.581798] iommu: Default domain type: Translated
10455 14:48:56.587975 <6>[ 0.586912] iommu: DMA domain TLB invalidation policy: strict mode
10456 14:48:56.590787 <5>[ 0.593565] SCSI subsystem initialized
10457 14:48:56.597729 <6>[ 0.597731] usbcore: registered new interface driver usbfs
10458 14:48:56.603980 <6>[ 0.603464] usbcore: registered new interface driver hub
10459 14:48:56.607878 <6>[ 0.609016] usbcore: registered new device driver usb
10460 14:48:56.614440 <6>[ 0.615118] pps_core: LinuxPPS API ver. 1 registered
10461 14:48:56.624275 <6>[ 0.620307] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10462 14:48:56.627542 <6>[ 0.629650] PTP clock support registered
10463 14:48:56.631009 <6>[ 0.633891] EDAC MC: Ver: 3.0.0
10464 14:48:56.638099 <6>[ 0.639057] FPGA manager framework
10465 14:48:56.641529 <6>[ 0.642745] Advanced Linux Sound Architecture Driver Initialized.
10466 14:48:56.644923 <6>[ 0.649526] vgaarb: loaded
10467 14:48:56.651333 <6>[ 0.652696] clocksource: Switched to clocksource arch_sys_counter
10468 14:48:56.658382 <5>[ 0.659117] VFS: Disk quotas dquot_6.6.0
10469 14:48:56.665199 <6>[ 0.663306] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10470 14:48:56.668114 <6>[ 0.670494] pnp: PnP ACPI: disabled
10471 14:48:56.676241 <6>[ 0.677183] NET: Registered PF_INET protocol family
10472 14:48:56.682626 <6>[ 0.682798] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10473 14:48:56.697341 <6>[ 0.695145] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10474 14:48:56.707726 <6>[ 0.703955] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10475 14:48:56.714090 <6>[ 0.711928] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10476 14:48:56.720361 <6>[ 0.720631] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10477 14:48:56.732681 <6>[ 0.730368] TCP: Hash tables configured (established 65536 bind 65536)
10478 14:48:56.738865 <6>[ 0.737230] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10479 14:48:56.745724 <6>[ 0.744430] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10480 14:48:56.752041 <6>[ 0.752142] NET: Registered PF_UNIX/PF_LOCAL protocol family
10481 14:48:56.759051 <6>[ 0.758240] RPC: Registered named UNIX socket transport module.
10482 14:48:56.762158 <6>[ 0.764387] RPC: Registered udp transport module.
10483 14:48:56.768990 <6>[ 0.769318] RPC: Registered tcp transport module.
10484 14:48:56.775552 <6>[ 0.774248] RPC: Registered tcp NFSv4.1 backchannel transport module.
10485 14:48:56.778469 <6>[ 0.780915] PCI: CLS 0 bytes, default 64
10486 14:48:56.781738 <6>[ 0.785254] Unpacking initramfs...
10487 14:48:56.792294 <6>[ 0.789390] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10488 14:48:56.801976 <6>[ 0.798058] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10489 14:48:56.805291 <6>[ 0.806897] kvm [1]: IPA Size Limit: 40 bits
10490 14:48:56.812138 <6>[ 0.811423] kvm [1]: GICv3: no GICV resource entry
10491 14:48:56.814901 <6>[ 0.816442] kvm [1]: disabling GICv2 emulation
10492 14:48:56.821787 <6>[ 0.821125] kvm [1]: GIC system register CPU interface enabled
10493 14:48:56.825063 <6>[ 0.827278] kvm [1]: vgic interrupt IRQ18
10494 14:48:56.831748 <6>[ 0.831628] kvm [1]: VHE mode initialized successfully
10495 14:48:56.834987 <5>[ 0.838003] Initialise system trusted keyrings
10496 14:48:56.841475 <6>[ 0.842770] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10497 14:48:56.851949 <6>[ 0.852769] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10498 14:48:56.858383 <5>[ 0.859139] NFS: Registering the id_resolver key type
10499 14:48:56.861562 <5>[ 0.864433] Key type id_resolver registered
10500 14:48:56.868233 <5>[ 0.868846] Key type id_legacy registered
10501 14:48:56.874647 <6>[ 0.873125] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10502 14:48:56.881299 <6>[ 0.880044] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10503 14:48:56.887581 <6>[ 0.887735] 9p: Installing v9fs 9p2000 file system support
10504 14:48:56.923704 <5>[ 0.925432] Key type asymmetric registered
10505 14:48:56.927501 <5>[ 0.929760] Asymmetric key parser 'x509' registered
10506 14:48:56.937937 <6>[ 0.934896] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10507 14:48:56.940887 <6>[ 0.942513] io scheduler mq-deadline registered
10508 14:48:56.944386 <6>[ 0.947272] io scheduler kyber registered
10509 14:48:56.962675 <6>[ 0.964146] EINJ: ACPI disabled.
10510 14:48:56.995860 <4>[ 0.990652] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 14:48:57.005526 <4>[ 1.001277] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10512 14:48:57.020809 <6>[ 1.022165] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10513 14:48:57.028398 <6>[ 1.030107] printk: console [ttyS0] disabled
10514 14:48:57.056302 <6>[ 1.054734] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10515 14:48:57.063213 <6>[ 1.064207] printk: console [ttyS0] enabled
10516 14:48:57.066476 <6>[ 1.064207] printk: console [ttyS0] enabled
10517 14:48:57.073231 <6>[ 1.073103] printk: bootconsole [mtk8250] disabled
10518 14:48:57.076615 <6>[ 1.073103] printk: bootconsole [mtk8250] disabled
10519 14:48:57.083673 <6>[ 1.084117] SuperH (H)SCI(F) driver initialized
10520 14:48:57.087040 <6>[ 1.089391] msm_serial: driver initialized
10521 14:48:57.100616 <6>[ 1.098276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10522 14:48:57.110988 <6>[ 1.106824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10523 14:48:57.117295 <6>[ 1.115367] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10524 14:48:57.127483 <6>[ 1.123994] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10525 14:48:57.134126 <6>[ 1.132702] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10526 14:48:57.143529 <6>[ 1.141416] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10527 14:48:57.153325 <6>[ 1.149963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10528 14:48:57.160730 <6>[ 1.158757] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10529 14:48:57.169969 <6>[ 1.167300] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10530 14:48:57.181940 <6>[ 1.182764] loop: module loaded
10531 14:48:57.188022 <6>[ 1.188827] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10532 14:48:57.210458 <4>[ 1.212009] mtk-pmic-keys: Failed to locate of_node [id: -1]
10533 14:48:57.217226 <6>[ 1.218806] megasas: 07.719.03.00-rc1
10534 14:48:57.227081 <6>[ 1.228510] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10535 14:48:57.235286 <6>[ 1.236097] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10536 14:48:57.251726 <6>[ 1.252767] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10537 14:48:57.308133 <6>[ 1.302377] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10538 14:48:57.615372 <6>[ 1.616278] Freeing initrd memory: 18288K
10539 14:48:57.627294 <6>[ 1.627683] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10540 14:48:57.637362 <6>[ 1.638639] tun: Universal TUN/TAP device driver, 1.6
10541 14:48:57.640950 <6>[ 1.644704] thunder_xcv, ver 1.0
10542 14:48:57.643898 <6>[ 1.648201] thunder_bgx, ver 1.0
10543 14:48:57.647295 <6>[ 1.651696] nicpf, ver 1.0
10544 14:48:57.658145 <6>[ 1.655708] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10545 14:48:57.660925 <6>[ 1.663184] hns3: Copyright (c) 2017 Huawei Corporation.
10546 14:48:57.668193 <6>[ 1.668774] hclge is initializing
10547 14:48:57.671148 <6>[ 1.672350] e1000: Intel(R) PRO/1000 Network Driver
10548 14:48:57.677681 <6>[ 1.677479] e1000: Copyright (c) 1999-2006 Intel Corporation.
10549 14:48:57.681493 <6>[ 1.683492] e1000e: Intel(R) PRO/1000 Network Driver
10550 14:48:57.687704 <6>[ 1.688707] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10551 14:48:57.693981 <6>[ 1.694892] igb: Intel(R) Gigabit Ethernet Network Driver
10552 14:48:57.700902 <6>[ 1.700542] igb: Copyright (c) 2007-2014 Intel Corporation.
10553 14:48:57.707679 <6>[ 1.706377] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10554 14:48:57.713959 <6>[ 1.712895] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10555 14:48:57.717520 <6>[ 1.719355] sky2: driver version 1.30
10556 14:48:57.724294 <6>[ 1.724286] usbcore: registered new device driver r8152-cfgselector
10557 14:48:57.730754 <6>[ 1.730821] usbcore: registered new interface driver r8152
10558 14:48:57.737656 <6>[ 1.736633] VFIO - User Level meta-driver version: 0.3
10559 14:48:57.743887 <6>[ 1.744865] usbcore: registered new interface driver usb-storage
10560 14:48:57.750978 <6>[ 1.751305] usbcore: registered new device driver onboard-usb-hub
10561 14:48:57.759063 <6>[ 1.760435] mt6397-rtc mt6359-rtc: registered as rtc0
10562 14:48:57.768912 <6>[ 1.765897] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:44:16 UTC (1717512256)
10563 14:48:57.772655 <6>[ 1.775458] i2c_dev: i2c /dev entries driver
10564 14:48:57.789149 <6>[ 1.787328] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10565 14:48:57.795957 <4>[ 1.796060] cpu cpu0: supply cpu not found, using dummy regulator
10566 14:48:57.802506 <4>[ 1.802484] cpu cpu1: supply cpu not found, using dummy regulator
10567 14:48:57.809154 <4>[ 1.808906] cpu cpu2: supply cpu not found, using dummy regulator
10568 14:48:57.815909 <4>[ 1.815307] cpu cpu3: supply cpu not found, using dummy regulator
10569 14:48:57.822471 <4>[ 1.821705] cpu cpu4: supply cpu not found, using dummy regulator
10570 14:48:57.829230 <4>[ 1.828101] cpu cpu5: supply cpu not found, using dummy regulator
10571 14:48:57.835801 <4>[ 1.834498] cpu cpu6: supply cpu not found, using dummy regulator
10572 14:48:57.839359 <4>[ 1.840924] cpu cpu7: supply cpu not found, using dummy regulator
10573 14:48:57.860935 <6>[ 1.861561] cpu cpu0: EM: created perf domain
10574 14:48:57.863318 <6>[ 1.866492] cpu cpu4: EM: created perf domain
10575 14:48:57.870711 <6>[ 1.872080] sdhci: Secure Digital Host Controller Interface driver
10576 14:48:57.877411 <6>[ 1.878514] sdhci: Copyright(c) Pierre Ossman
10577 14:48:57.884086 <6>[ 1.883464] Synopsys Designware Multimedia Card Interface Driver
10578 14:48:57.890777 <6>[ 1.890105] sdhci-pltfm: SDHCI platform and OF driver helper
10579 14:48:57.894014 <6>[ 1.890134] mmc0: CQHCI version 5.10
10580 14:48:57.900771 <6>[ 1.900275] ledtrig-cpu: registered to indicate activity on CPUs
10581 14:48:57.907772 <6>[ 1.907378] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10582 14:48:57.914644 <6>[ 1.914436] usbcore: registered new interface driver usbhid
10583 14:48:57.917687 <6>[ 1.920257] usbhid: USB HID core driver
10584 14:48:57.924139 <6>[ 1.924449] spi_master spi0: will run message pump with realtime priority
10585 14:48:57.967964 <6>[ 1.962308] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10586 14:48:57.983419 <6>[ 1.977544] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10587 14:48:57.991551 <6>[ 1.992488] cros-ec-spi spi0.0: Chrome EC device registered
10588 14:48:57.998297 <6>[ 1.998534] mmc0: Command Queue Engine enabled
10589 14:48:58.004788 <6>[ 2.003305] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10590 14:48:58.007823 <6>[ 2.011157] mmcblk0: mmc0:0001 DA4128 116 GiB
10591 14:48:58.021639 <6>[ 2.022693] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10592 14:48:58.031522 <6>[ 2.027285] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10593 14:48:58.038131 <6>[ 2.030068] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10594 14:48:58.041604 <6>[ 2.039183] NET: Registered PF_PACKET protocol family
10595 14:48:58.048013 <6>[ 2.043893] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10596 14:48:58.051384 <6>[ 2.048533] 9pnet: Installing 9P2000 support
10597 14:48:58.058354 <6>[ 2.054360] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10598 14:48:58.061823 <5>[ 2.058234] Key type dns_resolver registered
10599 14:48:58.068683 <6>[ 2.069699] registered taskstats version 1
10600 14:48:58.071796 <5>[ 2.074084] Loading compiled-in X.509 certificates
10601 14:48:58.103375 <4>[ 2.098484] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 14:48:58.113266 <4>[ 2.109215] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 14:48:58.127999 <6>[ 2.129499] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10604 14:48:58.134576 <6>[ 2.136416] xhci-mtk 11200000.usb: xHCI Host Controller
10605 14:48:58.141264 <6>[ 2.141922] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10606 14:48:58.151779 <6>[ 2.149787] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10607 14:48:58.157969 <6>[ 2.159221] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10608 14:48:58.164681 <6>[ 2.165417] xhci-mtk 11200000.usb: xHCI Host Controller
10609 14:48:58.171274 <6>[ 2.170908] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10610 14:48:58.178228 <6>[ 2.178561] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10611 14:48:58.185254 <6>[ 2.186400] hub 1-0:1.0: USB hub found
10612 14:48:58.188148 <6>[ 2.190430] hub 1-0:1.0: 1 port detected
10613 14:48:58.198071 <6>[ 2.194739] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10614 14:48:58.201930 <6>[ 2.203462] hub 2-0:1.0: USB hub found
10615 14:48:58.205177 <6>[ 2.207482] hub 2-0:1.0: 1 port detected
10616 14:48:58.213945 <6>[ 2.214581] mtk-msdc 11f70000.mmc: Got CD GPIO
10617 14:48:58.231681 <6>[ 2.229199] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10618 14:48:58.238518 <6>[ 2.237224] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10619 14:48:58.248717 <4>[ 2.245132] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10620 14:48:58.257759 <6>[ 2.254665] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10621 14:48:58.264530 <6>[ 2.262744] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10622 14:48:58.271554 <6>[ 2.270755] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10623 14:48:58.281395 <6>[ 2.278672] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10624 14:48:58.288398 <6>[ 2.286490] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10625 14:48:58.297923 <6>[ 2.294308] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10626 14:48:58.307911 <6>[ 2.304741] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10627 14:48:58.314868 <6>[ 2.313099] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10628 14:48:58.324449 <6>[ 2.321437] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10629 14:48:58.331128 <6>[ 2.329778] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10630 14:48:58.340903 <6>[ 2.338116] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10631 14:48:58.347770 <6>[ 2.346454] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10632 14:48:58.357576 <6>[ 2.354793] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10633 14:48:58.364186 <6>[ 2.363130] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10634 14:48:58.373808 <6>[ 2.371468] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10635 14:48:58.380372 <6>[ 2.379806] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10636 14:48:58.390096 <6>[ 2.388145] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10637 14:48:58.397027 <6>[ 2.396483] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10638 14:48:58.406435 <6>[ 2.404822] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10639 14:48:58.413350 <6>[ 2.413160] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10640 14:48:58.423176 <6>[ 2.421498] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10641 14:48:58.429848 <6>[ 2.430259] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10642 14:48:58.436205 <6>[ 2.437438] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10643 14:48:58.442813 <6>[ 2.444226] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10644 14:48:58.449646 <6>[ 2.450999] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10645 14:48:58.459877 <6>[ 2.457927] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10646 14:48:58.467135 <6>[ 2.464822] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10647 14:48:58.476572 <6>[ 2.473954] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10648 14:48:58.486565 <6>[ 2.483076] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10649 14:48:58.496674 <6>[ 2.492370] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10650 14:48:58.506663 <6>[ 2.501858] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10651 14:48:58.513138 <6>[ 2.511325] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10652 14:48:58.522804 <6>[ 2.520445] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10653 14:48:58.533242 <6>[ 2.529911] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10654 14:48:58.543372 <6>[ 2.539031] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10655 14:48:58.553012 <6>[ 2.548331] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10656 14:48:58.562693 <6>[ 2.558491] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10657 14:48:58.573000 <6>[ 2.569983] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10658 14:48:58.579285 <6>[ 2.579682] Trying to probe devices needed for running init ...
10659 14:48:58.595107 <6>[ 2.592987] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10660 14:48:58.622757 <6>[ 2.623686] hub 2-1:1.0: USB hub found
10661 14:48:58.625979 <6>[ 2.628090] hub 2-1:1.0: 3 ports detected
10662 14:48:58.633278 <6>[ 2.634430] hub 2-1:1.0: USB hub found
10663 14:48:58.636407 <6>[ 2.638787] hub 2-1:1.0: 3 ports detected
10664 14:48:58.746873 <6>[ 2.745022] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10665 14:48:58.901719 <6>[ 2.903126] hub 1-1:1.0: USB hub found
10666 14:48:58.905170 <6>[ 2.907614] hub 1-1:1.0: 4 ports detected
10667 14:48:58.915561 <6>[ 2.916371] hub 1-1:1.0: USB hub found
10668 14:48:58.918676 <6>[ 2.920753] hub 1-1:1.0: 4 ports detected
10669 14:48:58.979081 <6>[ 2.976879] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10670 14:48:59.087747 <6>[ 3.085322] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10671 14:48:59.119496 <4>[ 3.117190] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10672 14:48:59.129280 <4>[ 3.126288] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10673 14:48:59.168757 <6>[ 3.169955] r8152 2-1.3:1.0 eth0: v1.12.13
10674 14:48:59.239058 <6>[ 3.237009] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10675 14:48:59.371689 <6>[ 3.372795] hub 1-1.4:1.0: USB hub found
10676 14:48:59.375003 <6>[ 3.377451] hub 1-1.4:1.0: 2 ports detected
10677 14:48:59.384798 <6>[ 3.386211] hub 1-1.4:1.0: USB hub found
10678 14:48:59.388218 <6>[ 3.390809] hub 1-1.4:1.0: 2 ports detected
10679 14:48:59.690774 <6>[ 3.688827] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10680 14:48:59.878455 <6>[ 3.876960] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10681 14:49:00.780881 <6>[ 4.782684] r8152 2-1.3:1.0 eth0: carrier on
10682 14:49:02.902977 <5>[ 4.808810] Sending DHCP requests .., OK
10683 14:49:02.909142 <6>[ 6.909168] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10684 14:49:02.912984 <6>[ 6.917459] IP-Config: Complete:
10685 14:49:02.926488 <6>[ 6.920959] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10686 14:49:02.932801 <6>[ 6.931680] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10687 14:49:02.939424 <6>[ 6.940300] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10688 14:49:02.945703 <6>[ 6.940309] nameserver0=192.168.201.1
10689 14:49:02.949448 <6>[ 6.952501] clk: Disabling unused clocks
10690 14:49:02.952615 <6>[ 6.958210] ALSA device list:
10691 14:49:02.959217 <6>[ 6.961451] No soundcards found.
10692 14:49:02.967414 <6>[ 6.968937] Freeing unused kernel memory: 8512K
10693 14:49:02.970125 <6>[ 6.973870] Run /init as init process
10694 14:49:02.979223 Loading, please wait...
10695 14:49:03.005460 Starting systemd-udevd version 252.22-1~deb12u1
10696 14:49:03.263773 <6>[ 7.262656] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10697 14:49:03.270614 <6>[ 7.270516] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10698 14:49:03.280559 <6>[ 7.279396] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10699 14:49:03.287134 <6>[ 7.284066] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10700 14:49:03.300944 <6>[ 7.303206] remoteproc remoteproc0: scp is available
10701 14:49:03.307839 <4>[ 7.303454] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10702 14:49:03.314030 <6>[ 7.308617] remoteproc remoteproc0: powering up scp
10703 14:49:03.320704 <6>[ 7.308633] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10704 14:49:03.327202 <6>[ 7.308671] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10705 14:49:03.333833 <6>[ 7.322851] mc: Linux media interface: v0.10
10706 14:49:03.344664 <4>[ 7.343943] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10707 14:49:03.352151 <3>[ 7.346008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 14:49:03.362147 <3>[ 7.359496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 14:49:03.368610 <3>[ 7.367591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 14:49:03.378267 <3>[ 7.375974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 14:49:03.384694 <6>[ 7.377102] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10712 14:49:03.391222 <3>[ 7.384086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 14:49:03.401488 <3>[ 7.384091] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 14:49:03.408231 <3>[ 7.384096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 14:49:03.418150 <3>[ 7.384099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 14:49:03.424608 <3>[ 7.384129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 14:49:03.431732 <4>[ 7.409739] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10718 14:49:03.439048 <4>[ 7.409739] Fallback method does not support PEC.
10719 14:49:03.445327 <3>[ 7.416026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 14:49:03.455507 <3>[ 7.440919] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10721 14:49:03.465367 <3>[ 7.445785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 14:49:03.471959 <3>[ 7.445790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 14:49:03.481361 <6>[ 7.445858] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10724 14:49:03.488478 <6>[ 7.445858] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10725 14:49:03.495153 <3>[ 7.454244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 14:49:03.501524 <6>[ 7.456945] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10727 14:49:03.508422 <6>[ 7.456954] pci_bus 0000:00: root bus resource [bus 00-ff]
10728 14:49:03.514639 <6>[ 7.456961] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10729 14:49:03.524760 <6>[ 7.456965] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10730 14:49:03.531796 <6>[ 7.457009] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10731 14:49:03.537939 <6>[ 7.457023] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10732 14:49:03.545912 <6>[ 7.457089] pci 0000:00:00.0: supports D1 D2
10733 14:49:03.551299 <6>[ 7.457091] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10734 14:49:03.554775 <6>[ 7.458461] videodev: Linux video capture interface: v2.00
10735 14:49:03.565231 <6>[ 7.459708] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10736 14:49:03.572032 <6>[ 7.459837] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10737 14:49:03.578241 <6>[ 7.459863] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10738 14:49:03.584862 <6>[ 7.459880] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10739 14:49:03.591077 <6>[ 7.459896] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10740 14:49:03.598285 <6>[ 7.460007] pci 0000:01:00.0: supports D1 D2
10741 14:49:03.604622 <6>[ 7.460009] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10742 14:49:03.614461 <6>[ 7.461049] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10743 14:49:03.621287 <6>[ 7.462801] remoteproc remoteproc0: remote processor scp is now up
10744 14:49:03.627786 <3>[ 7.470872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 14:49:03.638225 <6>[ 7.472751] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10746 14:49:03.644355 <6>[ 7.475344] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10747 14:49:03.654744 <6>[ 7.475394] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10748 14:49:03.661384 <6>[ 7.475397] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10749 14:49:03.667713 <6>[ 7.475406] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10750 14:49:03.677458 <6>[ 7.475419] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10751 14:49:03.684183 <6>[ 7.475432] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10752 14:49:03.691062 <6>[ 7.475444] pci 0000:00:00.0: PCI bridge to [bus 01]
10753 14:49:03.697832 <6>[ 7.475450] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10754 14:49:03.704489 <6>[ 7.479018] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10755 14:49:03.714203 <6>[ 7.482484] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10756 14:49:03.720856 <3>[ 7.487610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 14:49:03.727671 <6>[ 7.501225] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10758 14:49:03.737355 <3>[ 7.503007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 14:49:03.741051 <6>[ 7.510762] Bluetooth: Core ver 2.22
10760 14:49:03.744161 <6>[ 7.510972] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10761 14:49:03.754105 <3>[ 7.515232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 14:49:03.760881 <3>[ 7.515305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 14:49:03.767542 <6>[ 7.522607] NET: Registered PF_BLUETOOTH protocol family
10764 14:49:03.774348 <6>[ 7.534275] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10765 14:49:03.785006 <6>[ 7.534630] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10766 14:49:03.790574 <6>[ 7.536990] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10767 14:49:03.797265 <6>[ 7.538609] Bluetooth: HCI device and connection manager initialized
10768 14:49:03.810394 <6>[ 7.547233] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10769 14:49:03.817183 <5>[ 7.548010] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10770 14:49:03.823900 <6>[ 7.550635] Bluetooth: HCI socket layer initialized
10771 14:49:03.826977 <6>[ 7.550655] Bluetooth: L2CAP socket layer initialized
10772 14:49:03.833644 <6>[ 7.550685] Bluetooth: SCO socket layer initialized
10773 14:49:03.840066 <6>[ 7.557869] usbcore: registered new interface driver uvcvideo
10774 14:49:03.846790 <6>[ 7.564437] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10775 14:49:03.853611 <5>[ 7.567783] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10776 14:49:03.860182 <5>[ 7.568291] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10777 14:49:03.870304 <4>[ 7.568370] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10778 14:49:03.873328 <6>[ 7.568379] cfg80211: failed to load regulatory.db
10779 14:49:03.883002 <3>[ 7.573967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10780 14:49:03.889938 <6>[ 7.621983] usbcore: registered new interface driver btusb
10781 14:49:03.900003 <4>[ 7.622975] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10782 14:49:03.906703 <3>[ 7.622983] Bluetooth: hci0: Failed to load firmware file (-2)
10783 14:49:03.912922 <3>[ 7.622985] Bluetooth: hci0: Failed to set up firmware (-2)
10784 14:49:03.923319 <4>[ 7.622987] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10785 14:49:03.929633 <6>[ 7.672264] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10786 14:49:03.935738 <6>[ 7.937234] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10787 14:49:03.958605 <6>[ 7.961085] mt7921e 0000:01:00.0: ASIC revision: 79610010
10788 14:49:04.061517 <6>[ 8.060292] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10789 14:49:04.065024 <6>[ 8.060292]
10790 14:49:04.067745 Begin: Loading essential drivers ... done.
10791 14:49:04.071134 Begin: Running /scripts/init-premount ... done.
10792 14:49:04.078095 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10793 14:49:04.088139 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10794 14:49:04.091433 Device /sys/class/net/eth0 found
10795 14:49:04.091595 done.
10796 14:49:04.097696 Begin: Waiting up to 180 secs for any network device to become available ... done.
10797 14:49:04.151080 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10798 14:49:04.157745 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10799 14:49:04.164172 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10800 14:49:04.170957 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10801 14:49:04.177362 host : mt8192-asurada-spherion-r0-cbg-0
10802 14:49:04.183947 domain : lava-rack
10803 14:49:04.187833 rootserver: 192.168.201.1 rootpath:
10804 14:49:04.188476 filename :
10805 14:49:04.331834 <6>[ 8.330633] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10806 14:49:04.405559 done.
10807 14:49:04.412335 Begin: Running /scripts/nfs-bottom ... done.
10808 14:49:04.428272 Begin: Running /scripts/init-bottom ... done.
10809 14:49:05.733949 <6>[ 9.736528] NET: Registered PF_INET6 protocol family
10810 14:49:05.741372 <6>[ 9.744006] Segment Routing with IPv6
10811 14:49:05.744828 <6>[ 9.747969] In-situ OAM (IOAM) with IPv6
10812 14:49:05.897279 <30>[ 9.872649] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10813 14:49:05.903249 <30>[ 9.905762] systemd[1]: Detected architecture arm64.
10814 14:49:05.910203
10815 14:49:05.913397 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10816 14:49:05.913478
10817 14:49:05.939412 <30>[ 9.941647] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10818 14:49:06.857247 <30>[ 10.856103] systemd[1]: Queued start job for default target graphical.target.
10819 14:49:06.899435 <30>[ 10.898203] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10820 14:49:06.906114 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10821 14:49:06.928337 <30>[ 10.926737] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10822 14:49:06.938398 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10823 14:49:06.955771 <30>[ 10.954762] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10824 14:49:06.965447 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10825 14:49:06.983430 <30>[ 10.982344] systemd[1]: Created slice user.slice - User and Session Slice.
10826 14:49:06.990104 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10827 14:49:07.014293 <30>[ 11.009861] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10828 14:49:07.023758 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10829 14:49:07.046018 <30>[ 11.041842] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10830 14:49:07.052579 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10831 14:49:07.079634 <30>[ 11.069178] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10832 14:49:07.089574 <30>[ 11.089006] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10833 14:49:07.096075 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10834 14:49:07.114316 <30>[ 11.113400] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10835 14:49:07.123937 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10836 14:49:07.141931 <30>[ 11.141172] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10837 14:49:07.151948 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10838 14:49:07.166640 <30>[ 11.169540] systemd[1]: Reached target paths.target - Path Units.
10839 14:49:07.176967 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10840 14:49:07.194828 <30>[ 11.193445] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10841 14:49:07.200862 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10842 14:49:07.214900 <30>[ 11.216967] systemd[1]: Reached target slices.target - Slice Units.
10843 14:49:07.225000 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10844 14:49:07.239499 <30>[ 11.241492] systemd[1]: Reached target swap.target - Swaps.
10845 14:49:07.245539 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10846 14:49:07.267061 <30>[ 11.265506] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10847 14:49:07.276942 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10848 14:49:07.295078 <30>[ 11.293524] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10849 14:49:07.304979 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10850 14:49:07.324924 <30>[ 11.323866] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10851 14:49:07.334884 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10852 14:49:07.351190 <30>[ 11.350351] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10853 14:49:07.360967 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10854 14:49:07.378684 <30>[ 11.377683] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10855 14:49:07.385059 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10856 14:49:07.402683 <30>[ 11.402250] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10857 14:49:07.412384 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10858 14:49:07.432205 <30>[ 11.431600] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10859 14:49:07.442236 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10860 14:49:07.458472 <30>[ 11.458006] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10861 14:49:07.468436 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10862 14:49:07.526489 <30>[ 11.525240] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10863 14:49:07.533119 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10864 14:49:07.558612 <30>[ 11.557608] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10865 14:49:07.565275 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10866 14:49:07.610056 <30>[ 11.609154] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10867 14:49:07.616438 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10868 14:49:07.640777 <30>[ 11.633483] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10869 14:49:07.656471 <30>[ 11.655523] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10870 14:49:07.666220 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10871 14:49:07.687914 <30>[ 11.686723] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10872 14:49:07.694498 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10873 14:49:07.719485 <30>[ 11.718585] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10874 14:49:07.725674 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10875 14:49:07.751694 <30>[ 11.751001] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10876 14:49:07.762040 Startin<6>[ 11.760194] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10877 14:49:07.768028 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10878 14:49:07.791635 <30>[ 11.791071] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10879 14:49:07.798560 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10880 14:49:07.824026 <30>[ 11.822904] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10881 14:49:07.830144 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10882 14:49:07.855360 <30>[ 11.854821] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10883 14:49:07.862538 Startin<6>[ 11.864232] fuse: init (API version 7.37)
10884 14:49:07.868453 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10885 14:49:07.919354 <30>[ 11.917982] systemd[1]: Starting systemd-journald.service - Journal Service...
10886 14:49:07.925909 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10887 14:49:07.958594 <30>[ 11.957905] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10888 14:49:07.965116 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10889 14:49:07.992276 <30>[ 11.988182] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10890 14:49:07.999206 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10891 14:49:08.050629 <30>[ 12.049885] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10892 14:49:08.061527 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10893 14:49:08.071176 <3>[ 12.068499] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 14:49:08.083002 <30>[ 12.082040] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10895 14:49:08.089198 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10896 14:49:08.112080 <3>[ 12.110966] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 14:49:08.118633 <30>[ 12.113816] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10898 14:49:08.128666 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10899 14:49:08.146195 <3>[ 12.145420] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 14:49:08.156019 <30>[ 12.145528] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10901 14:49:08.162440 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10902 14:49:08.174919 <3>[ 12.174553] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 14:49:08.185169 <30>[ 12.183988] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10904 14:49:08.192009 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10905 14:49:08.204447 <3>[ 12.203671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 14:49:08.214677 <30>[ 12.213964] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10907 14:49:08.225239 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10908 14:49:08.235291 <3>[ 12.233603] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 14:49:08.245154 <30>[ 12.243890] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10910 14:49:08.251646 <30>[ 12.251781] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10911 14:49:08.265633 [[0;32m OK [0m] Finished [0<3>[ 12.262467] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 14:49:08.268473 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10913 14:49:08.283825 <30>[ 12.286019] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10914 14:49:08.293770 <3>[ 12.292533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 14:49:08.303518 <30>[ 12.293640] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10916 14:49:08.310417 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10917 14:49:08.331635 <30>[ 12.330356] systemd[1]: modprobe@drm.service: Deactivated successfully.
10918 14:49:08.338524 <30>[ 12.338160] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10919 14:49:08.345394 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10920 14:49:08.367368 <30>[ 12.366069] systemd[1]: Started systemd-journald.service - Journal Service.
10921 14:49:08.373639 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10922 14:49:08.393174 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10923 14:49:08.412458 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10924 14:49:08.432693 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10925 14:49:08.452991 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10926 14:49:08.471736 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10927 14:49:08.491807 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10928 14:49:08.500436 <4>[ 12.502281] power_supply_show_property: 2 callbacks suppressed
10929 14:49:08.510178 <3>[ 12.502298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 14:49:08.524465 <4>[ 12.517192] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10931 14:49:08.534353 <3>[ 12.531849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 14:49:08.540448 <3>[ 12.532822] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10933 14:49:08.551099 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10934 14:49:08.571523 <3>[ 12.570388] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 14:49:08.602359 Mounting [0;1;39msys-fs-fuse-conne…<3>[ 12.601690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 14:49:08.606013 [0m - FUSE Control File System...
10937 14:49:08.633294 <3>[ 12.632056] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 14:49:08.639829 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10939 14:49:08.663425 <3>[ 12.662299] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 14:49:08.694359 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage..<3>[ 12.691742] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 14:49:08.694912 .
10942 14:49:08.724867 Starting [0;1;39msyste<3>[ 12.721752] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 14:49:08.727963 md-random-se…ice[0m - Load/Save Random Seed...
10944 14:49:08.752830 <3>[ 12.751567] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 14:49:08.762324 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10946 14:49:08.782981 <3>[ 12.781708] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 14:49:08.789382 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10948 14:49:08.820588 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10949 14:49:08.835891 <46>[ 12.835278] systemd-journald[310]: Received client request to flush runtime journal.
10950 14:49:08.846001 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10951 14:49:08.862787 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10952 14:49:08.880355 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10953 14:49:08.903627 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10954 14:49:08.927148 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10955 14:49:08.982529 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10956 14:49:10.263689 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10957 14:49:10.310874 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10958 14:49:10.330674 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10959 14:49:10.349520 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10960 14:49:10.398549 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10961 14:49:10.423372 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10962 14:49:10.649362 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10963 14:49:10.708163 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10964 14:49:10.782188 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10965 14:49:10.813369 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10966 14:49:10.988264 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10967 14:49:11.040659 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10968 14:49:11.118912 <6>[ 15.121589] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10969 14:49:11.128567 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10970 14:49:11.241532 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10971 14:49:11.262242 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10972 14:49:11.318205 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10973 14:49:11.338466 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10974 14:49:11.377401 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10975 14:49:11.404971 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10976 14:49:11.429529 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10977 14:49:11.445871 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10978 14:49:11.463063 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10979 14:49:11.486383 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10980 14:49:11.514031 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10981 14:49:11.536610 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10982 14:49:11.553490 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10983 14:49:11.572964 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10984 14:49:11.592620 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10985 14:49:11.609405 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10986 14:49:11.625247 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10987 14:49:11.652481 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10988 14:49:11.669542 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10989 14:49:11.685373 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10990 14:49:11.726561 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10991 14:49:11.761412 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10992 14:49:11.858393 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10993 14:49:11.883601 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10994 14:49:11.906662 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10995 14:49:12.009994 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10996 14:49:12.033327 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10997 14:49:12.050319 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10998 14:49:12.110251 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10999 14:49:12.131817 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11000 14:49:12.149521 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11001 14:49:12.166682 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11002 14:49:12.247727 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11003 14:49:12.267731 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11004 14:49:12.286455 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11005 14:49:12.339351 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11006 14:49:12.389034 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11007 14:49:12.467084
11008 14:49:12.469668 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11009 14:49:12.469755
11010 14:49:12.473026 debian-bookworm-arm64 login: root (automatic login)
11011 14:49:12.473107
11012 14:49:12.700978 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
11013 14:49:12.701120
11014 14:49:12.707842 The programs included with the Debian GNU/Linux system are free software;
11015 14:49:12.714504 the exact distribution terms for each program are described in the
11016 14:49:12.717646 individual files in /usr/share/doc/*/copyright.
11017 14:49:12.717739
11018 14:49:12.724441 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11019 14:49:12.727560 permitted by applicable law.
11020 14:49:12.800166 Matched prompt #10: / #
11022 14:49:12.800553 Setting prompt string to ['/ #']
11023 14:49:12.800646 end: 2.2.5.1 login-action (duration 00:00:18) [common]
11025 14:49:12.800836 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
11026 14:49:12.800923 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
11027 14:49:12.800990 Setting prompt string to ['/ #']
11028 14:49:12.801049 Forcing a shell prompt, looking for ['/ #']
11030 14:49:12.851288 / #
11031 14:49:12.851457 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11032 14:49:12.851591 Waiting using forced prompt support (timeout 00:02:30)
11033 14:49:12.856582
11034 14:49:12.856869 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11035 14:49:12.856963 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
11037 14:49:12.957325 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14167046/extract-nfsrootfs-pjnyfw_3'
11038 14:49:12.962676 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14167046/extract-nfsrootfs-pjnyfw_3'
11040 14:49:13.063458 / # export NFS_SERVER_IP='192.168.201.1'
11041 14:49:13.070058 export NFS_SERVER_IP='192.168.201.1'
11042 14:49:13.070836 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11043 14:49:13.071354 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
11044 14:49:13.071794 end: 2 depthcharge-action (duration 00:01:16) [common]
11045 14:49:13.072241 start: 3 lava-test-retry (timeout 00:01:00) [common]
11046 14:49:13.072724 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11047 14:49:13.073104 Using namespace: common
11049 14:49:13.174201 / # #
11050 14:49:13.174792 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11051 14:49:13.180875 #
11052 14:49:13.181688 Using /lava-14167046
11054 14:49:13.282685 / # export SHELL=/bin/sh
11055 14:49:13.288542 export SHELL=/bin/sh
11057 14:49:13.389468 / # . /lava-14167046/environment
11058 14:49:13.395484 . /lava-14167046/environment
11060 14:49:13.502294 / # /lava-14167046/bin/lava-test-runner /lava-14167046/0
11061 14:49:13.502428 Test shell timeout: 10s (minimum of the action and connection timeout)
11062 14:49:13.507297 /lava-14167046/bin/lava-test-runner /lava-14167046/0
11063 14:49:13.704777 + export TESTRUN_ID=0_dmesg
11064 14:49:13.708570 + cd /lava-14167046/0/tests/0_dmesg
11065 14:49:13.711491 + cat uuid
11066 14:49:13.722588 + UUID=14167046_<8>[ 17.722462] <LAVA_SIGNAL_STARTRUN 0_dmesg 14167046_1.6.2.3.1>
11067 14:49:13.722672 1.6.2.3.1
11068 14:49:13.722737 + set +x
11069 14:49:13.722979 Received signal: <STARTRUN> 0_dmesg 14167046_1.6.2.3.1
11070 14:49:13.723047 Starting test lava.0_dmesg (14167046_1.6.2.3.1)
11071 14:49:13.723124 Skipping test definition patterns.
11072 14:49:13.729037 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11073 14:49:13.816492 <8>[ 17.816564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11074 14:49:13.816780 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11076 14:49:13.877348 <8>[ 17.877621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11077 14:49:13.877648 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11079 14:49:13.935760 <8>[ 17.935768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11080 14:49:13.936035 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11082 14:49:13.939266 + set +x
11083 14:49:13.945369 <8>[ 17.945875] <LAVA_SIGNAL_ENDRUN 0_dmesg 14167046_1.6.2.3.1>
11084 14:49:13.945623 Received signal: <ENDRUN> 0_dmesg 14167046_1.6.2.3.1
11085 14:49:13.945701 Ending use of test pattern.
11086 14:49:13.945763 Ending test lava.0_dmesg (14167046_1.6.2.3.1), duration 0.22
11088 14:49:13.948831 <LAVA_TEST_RUNNER EXIT>
11089 14:49:13.949082 ok: lava_test_shell seems to have completed
11090 14:49:13.949186 alert: pass
crit: pass
emerg: pass
11091 14:49:13.949271 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11092 14:49:13.949351 end: 3 lava-test-retry (duration 00:00:01) [common]
11093 14:49:13.949437 start: 4 finalize (timeout 00:08:16) [common]
11094 14:49:13.949521 start: 4.1 power-off (timeout 00:00:30) [common]
11095 14:49:13.949667 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11096 14:49:14.025129 >> Command sent successfully.
11097 14:49:14.027513 Returned 0 in 0 seconds
11098 14:49:14.127916 end: 4.1 power-off (duration 00:00:00) [common]
11100 14:49:14.128232 start: 4.2 read-feedback (timeout 00:08:16) [common]
11101 14:49:14.128515 Listened to connection for namespace 'common' for up to 1s
11102 14:49:15.129451 Finalising connection for namespace 'common'
11103 14:49:15.129610 Disconnecting from shell: Finalise
11104 14:49:15.129698 / #
11105 14:49:15.230032 end: 4.2 read-feedback (duration 00:00:01) [common]
11106 14:49:15.230218 end: 4 finalize (duration 00:00:01) [common]
11107 14:49:15.230340 Cleaning after the job
11108 14:49:15.230453 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/ramdisk
11109 14:49:15.232658 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/kernel
11110 14:49:15.243795 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/dtb
11111 14:49:15.244020 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/nfsrootfs
11112 14:49:15.304548 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167046/tftp-deploy-mx7et379/modules
11113 14:49:15.310445 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14167046
11114 14:49:15.639428 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14167046
11115 14:49:15.639641 Job finished correctly