Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 14:46:25.092444 lava-dispatcher, installed at version: 2024.03
2 14:46:25.092677 start: 0 validate
3 14:46:25.092820 Start time: 2024-06-04 14:46:25.092812+00:00 (UTC)
4 14:46:25.092951 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:46:25.093088 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 14:46:25.356210 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:46:25.357214 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:46:25.619960 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:46:25.620147 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:46:25.879795 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:46:25.880434 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 14:46:26.148686 validate duration: 1.06
14 14:46:26.149946 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:46:26.150573 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:46:26.151128 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:46:26.151762 Not decompressing ramdisk as can be used compressed.
18 14:46:26.152197 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 14:46:26.152527 saving as /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/ramdisk/rootfs.cpio.gz
20 14:46:26.152862 total size: 39026414 (37 MB)
21 14:46:26.157686 progress 0 % (0 MB)
22 14:46:26.200060 progress 5 % (1 MB)
23 14:46:26.216900 progress 10 % (3 MB)
24 14:46:26.228567 progress 15 % (5 MB)
25 14:46:26.238518 progress 20 % (7 MB)
26 14:46:26.248260 progress 25 % (9 MB)
27 14:46:26.258178 progress 30 % (11 MB)
28 14:46:26.268020 progress 35 % (13 MB)
29 14:46:26.277961 progress 40 % (14 MB)
30 14:46:26.287765 progress 45 % (16 MB)
31 14:46:26.297742 progress 50 % (18 MB)
32 14:46:26.307626 progress 55 % (20 MB)
33 14:46:26.317321 progress 60 % (22 MB)
34 14:46:26.327225 progress 65 % (24 MB)
35 14:46:26.336893 progress 70 % (26 MB)
36 14:46:26.346772 progress 75 % (27 MB)
37 14:46:26.356452 progress 80 % (29 MB)
38 14:46:26.366537 progress 85 % (31 MB)
39 14:46:26.376293 progress 90 % (33 MB)
40 14:46:26.386000 progress 95 % (35 MB)
41 14:46:26.395596 progress 100 % (37 MB)
42 14:46:26.395844 37 MB downloaded in 0.24 s (153.16 MB/s)
43 14:46:26.396002 end: 1.1.1 http-download (duration 00:00:00) [common]
45 14:46:26.396242 end: 1.1 download-retry (duration 00:00:00) [common]
46 14:46:26.396337 start: 1.2 download-retry (timeout 00:10:00) [common]
47 14:46:26.396422 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 14:46:26.396562 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 14:46:26.396636 saving as /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/kernel/Image
50 14:46:26.396697 total size: 54682112 (52 MB)
51 14:46:26.396759 No compression specified
52 14:46:26.397860 progress 0 % (0 MB)
53 14:46:26.411625 progress 5 % (2 MB)
54 14:46:26.425141 progress 10 % (5 MB)
55 14:46:26.438934 progress 15 % (7 MB)
56 14:46:26.452549 progress 20 % (10 MB)
57 14:46:26.466390 progress 25 % (13 MB)
58 14:46:26.480115 progress 30 % (15 MB)
59 14:46:26.494100 progress 35 % (18 MB)
60 14:46:26.507790 progress 40 % (20 MB)
61 14:46:26.521400 progress 45 % (23 MB)
62 14:46:26.535247 progress 50 % (26 MB)
63 14:46:26.548770 progress 55 % (28 MB)
64 14:46:26.562614 progress 60 % (31 MB)
65 14:46:26.576332 progress 65 % (33 MB)
66 14:46:26.590268 progress 70 % (36 MB)
67 14:46:26.604220 progress 75 % (39 MB)
68 14:46:26.618195 progress 80 % (41 MB)
69 14:46:26.631956 progress 85 % (44 MB)
70 14:46:26.645793 progress 90 % (46 MB)
71 14:46:26.659549 progress 95 % (49 MB)
72 14:46:26.673243 progress 100 % (52 MB)
73 14:46:26.673490 52 MB downloaded in 0.28 s (188.41 MB/s)
74 14:46:26.673654 end: 1.2.1 http-download (duration 00:00:00) [common]
76 14:46:26.673894 end: 1.2 download-retry (duration 00:00:00) [common]
77 14:46:26.673983 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:46:26.674067 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:46:26.674240 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 14:46:26.674309 saving as /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/dtb/mt8192-asurada-spherion-r0.dtb
81 14:46:26.674370 total size: 47258 (0 MB)
82 14:46:26.674430 No compression specified
83 14:46:26.675560 progress 69 % (0 MB)
84 14:46:26.675833 progress 100 % (0 MB)
85 14:46:26.675986 0 MB downloaded in 0.00 s (27.92 MB/s)
86 14:46:26.676106 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:46:26.676333 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:46:26.676418 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:46:26.676501 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:46:26.676619 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 14:46:26.676687 saving as /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/modules/modules.tar
93 14:46:26.676747 total size: 8608920 (8 MB)
94 14:46:26.676808 Using unxz to decompress xz
95 14:46:26.680888 progress 0 % (0 MB)
96 14:46:26.699707 progress 5 % (0 MB)
97 14:46:26.726900 progress 10 % (0 MB)
98 14:46:26.756497 progress 15 % (1 MB)
99 14:46:26.780183 progress 20 % (1 MB)
100 14:46:26.803738 progress 25 % (2 MB)
101 14:46:26.827040 progress 30 % (2 MB)
102 14:46:26.851166 progress 35 % (2 MB)
103 14:46:26.877738 progress 40 % (3 MB)
104 14:46:26.900332 progress 45 % (3 MB)
105 14:46:26.923996 progress 50 % (4 MB)
106 14:46:26.948792 progress 55 % (4 MB)
107 14:46:26.973205 progress 60 % (4 MB)
108 14:46:26.997472 progress 65 % (5 MB)
109 14:46:27.022268 progress 70 % (5 MB)
110 14:46:27.047657 progress 75 % (6 MB)
111 14:46:27.073906 progress 80 % (6 MB)
112 14:46:27.098479 progress 85 % (7 MB)
113 14:46:27.123802 progress 90 % (7 MB)
114 14:46:27.148840 progress 95 % (7 MB)
115 14:46:27.173703 progress 100 % (8 MB)
116 14:46:27.179297 8 MB downloaded in 0.50 s (16.34 MB/s)
117 14:46:27.179535 end: 1.4.1 http-download (duration 00:00:01) [common]
119 14:46:27.179807 end: 1.4 download-retry (duration 00:00:01) [common]
120 14:46:27.179900 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 14:46:27.179993 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 14:46:27.180074 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:46:27.180172 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 14:46:27.180406 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1
125 14:46:27.180544 makedir: /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin
126 14:46:27.180647 makedir: /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/tests
127 14:46:27.180746 makedir: /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/results
128 14:46:27.180861 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-add-keys
129 14:46:27.181005 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-add-sources
130 14:46:27.181140 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-background-process-start
131 14:46:27.181274 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-background-process-stop
132 14:46:27.181400 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-common-functions
133 14:46:27.181532 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-echo-ipv4
134 14:46:27.181671 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-install-packages
135 14:46:27.181807 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-installed-packages
136 14:46:27.181940 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-os-build
137 14:46:27.182081 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-probe-channel
138 14:46:27.182252 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-probe-ip
139 14:46:27.182386 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-target-ip
140 14:46:27.182526 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-target-mac
141 14:46:27.182654 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-target-storage
142 14:46:27.182789 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-test-case
143 14:46:27.182915 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-test-event
144 14:46:27.183046 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-test-feedback
145 14:46:27.183177 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-test-raise
146 14:46:27.183304 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-test-reference
147 14:46:27.183435 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-test-runner
148 14:46:27.183565 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-test-set
149 14:46:27.183692 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-test-shell
150 14:46:27.183823 Updating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-install-packages (oe)
151 14:46:27.183977 Updating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/bin/lava-installed-packages (oe)
152 14:46:27.184103 Creating /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/environment
153 14:46:27.184204 LAVA metadata
154 14:46:27.184276 - LAVA_JOB_ID=14167048
155 14:46:27.184343 - LAVA_DISPATCHER_IP=192.168.201.1
156 14:46:27.184449 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 14:46:27.184517 skipped lava-vland-overlay
158 14:46:27.184590 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 14:46:27.184671 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 14:46:27.184747 skipped lava-multinode-overlay
161 14:46:27.184824 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 14:46:27.184909 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 14:46:27.184985 Loading test definitions
164 14:46:27.185074 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 14:46:27.185150 Using /lava-14167048 at stage 0
166 14:46:27.185479 uuid=14167048_1.5.2.3.1 testdef=None
167 14:46:27.185569 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 14:46:27.185652 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 14:46:27.186215 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 14:46:27.186602 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 14:46:27.187241 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 14:46:27.187473 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 14:46:27.188075 runner path: /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/0/tests/0_cros-ec test_uuid 14167048_1.5.2.3.1
176 14:46:27.188236 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 14:46:27.188453 Creating lava-test-runner.conf files
179 14:46:27.188518 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14167048/lava-overlay-4st6gtg1/lava-14167048/0 for stage 0
180 14:46:27.188613 - 0_cros-ec
181 14:46:27.188711 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 14:46:27.188801 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 14:46:27.196090 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 14:46:27.196200 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 14:46:27.196290 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 14:46:27.196381 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 14:46:27.196466 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 14:46:28.443319 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 14:46:28.443714 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 14:46:28.443831 extracting modules file /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14167048/extract-overlay-ramdisk-3g1v5ecw/ramdisk
191 14:46:28.661974 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 14:46:28.662146 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 14:46:28.662333 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167048/compress-overlay-3o9puu7v/overlay-1.5.2.4.tar.gz to ramdisk
194 14:46:28.662412 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14167048/compress-overlay-3o9puu7v/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14167048/extract-overlay-ramdisk-3g1v5ecw/ramdisk
195 14:46:28.668971 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 14:46:28.669088 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 14:46:28.669179 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 14:46:28.669272 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 14:46:28.669353 Building ramdisk /var/lib/lava/dispatcher/tmp/14167048/extract-overlay-ramdisk-3g1v5ecw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14167048/extract-overlay-ramdisk-3g1v5ecw/ramdisk
200 14:46:29.527762 >> 335872 blocks
201 14:46:34.691338 rename /var/lib/lava/dispatcher/tmp/14167048/extract-overlay-ramdisk-3g1v5ecw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/ramdisk/ramdisk.cpio.gz
202 14:46:34.691826 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 14:46:34.691961 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 14:46:34.692065 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 14:46:34.692177 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/kernel/Image']
206 14:46:47.704462 Returned 0 in 13 seconds
207 14:46:47.805483 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/kernel/image.itb
208 14:46:48.596565 output: FIT description: Kernel Image image with one or more FDT blobs
209 14:46:48.596940 output: Created: Tue Jun 4 15:46:48 2024
210 14:46:48.597016 output: Image 0 (kernel-1)
211 14:46:48.597080 output: Description:
212 14:46:48.597141 output: Created: Tue Jun 4 15:46:48 2024
213 14:46:48.597203 output: Type: Kernel Image
214 14:46:48.597266 output: Compression: lzma compressed
215 14:46:48.597328 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
216 14:46:48.597391 output: Architecture: AArch64
217 14:46:48.597453 output: OS: Linux
218 14:46:48.597515 output: Load Address: 0x00000000
219 14:46:48.597576 output: Entry Point: 0x00000000
220 14:46:48.597635 output: Hash algo: crc32
221 14:46:48.597694 output: Hash value: 88dcd836
222 14:46:48.597751 output: Image 1 (fdt-1)
223 14:46:48.597807 output: Description: mt8192-asurada-spherion-r0
224 14:46:48.597864 output: Created: Tue Jun 4 15:46:48 2024
225 14:46:48.597922 output: Type: Flat Device Tree
226 14:46:48.597978 output: Compression: uncompressed
227 14:46:48.598065 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 14:46:48.598150 output: Architecture: AArch64
229 14:46:48.598247 output: Hash algo: crc32
230 14:46:48.598302 output: Hash value: 0f8e4d2e
231 14:46:48.598356 output: Image 2 (ramdisk-1)
232 14:46:48.598410 output: Description: unavailable
233 14:46:48.598465 output: Created: Tue Jun 4 15:46:48 2024
234 14:46:48.598518 output: Type: RAMDisk Image
235 14:46:48.598572 output: Compression: Unknown Compression
236 14:46:48.598626 output: Data Size: 52133096 Bytes = 50911.23 KiB = 49.72 MiB
237 14:46:48.598679 output: Architecture: AArch64
238 14:46:48.598733 output: OS: Linux
239 14:46:48.598786 output: Load Address: unavailable
240 14:46:48.598840 output: Entry Point: unavailable
241 14:46:48.598893 output: Hash algo: crc32
242 14:46:48.598947 output: Hash value: 59a11a4f
243 14:46:48.599000 output: Default Configuration: 'conf-1'
244 14:46:48.599053 output: Configuration 0 (conf-1)
245 14:46:48.599107 output: Description: mt8192-asurada-spherion-r0
246 14:46:48.599161 output: Kernel: kernel-1
247 14:46:48.599213 output: Init Ramdisk: ramdisk-1
248 14:46:48.599267 output: FDT: fdt-1
249 14:46:48.599319 output: Loadables: kernel-1
250 14:46:48.599373 output:
251 14:46:48.599576 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 14:46:48.599672 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 14:46:48.599774 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 14:46:48.599869 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 14:46:48.599948 No LXC device requested
256 14:46:48.600028 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 14:46:48.600110 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 14:46:48.600187 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 14:46:48.600259 Checking files for TFTP limit of 4294967296 bytes.
260 14:46:48.600751 end: 1 tftp-deploy (duration 00:00:22) [common]
261 14:46:48.600857 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 14:46:48.600949 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 14:46:48.601070 substitutions:
264 14:46:48.601137 - {DTB}: 14167048/tftp-deploy-rvk543o5/dtb/mt8192-asurada-spherion-r0.dtb
265 14:46:48.601202 - {INITRD}: 14167048/tftp-deploy-rvk543o5/ramdisk/ramdisk.cpio.gz
266 14:46:48.601262 - {KERNEL}: 14167048/tftp-deploy-rvk543o5/kernel/Image
267 14:46:48.601322 - {LAVA_MAC}: None
268 14:46:48.601380 - {PRESEED_CONFIG}: None
269 14:46:48.601436 - {PRESEED_LOCAL}: None
270 14:46:48.601491 - {RAMDISK}: 14167048/tftp-deploy-rvk543o5/ramdisk/ramdisk.cpio.gz
271 14:46:48.601547 - {ROOT_PART}: None
272 14:46:48.601602 - {ROOT}: None
273 14:46:48.601656 - {SERVER_IP}: 192.168.201.1
274 14:46:48.601711 - {TEE}: None
275 14:46:48.601765 Parsed boot commands:
276 14:46:48.601820 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 14:46:48.601993 Parsed boot commands: tftpboot 192.168.201.1 14167048/tftp-deploy-rvk543o5/kernel/image.itb 14167048/tftp-deploy-rvk543o5/kernel/cmdline
278 14:46:48.602082 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 14:46:48.602175 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 14:46:48.602310 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 14:46:48.602395 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 14:46:48.602466 Not connected, no need to disconnect.
283 14:46:48.602541 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 14:46:48.602621 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 14:46:48.602690 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 14:46:48.606444 Setting prompt string to ['lava-test: # ']
287 14:46:48.606804 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 14:46:48.606914 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 14:46:48.607018 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 14:46:48.607134 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 14:46:48.607314 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
292 14:47:02.366973 Returned 0 in 13 seconds
293 14:47:02.467602 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 14:47:02.468249 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 14:47:02.468384 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 14:47:02.468505 Setting prompt string to 'Starting depthcharge on Spherion...'
298 14:47:02.468604 Changing prompt to 'Starting depthcharge on Spherion...'
299 14:47:02.468702 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 14:47:02.469289 [Enter `^Ec?' for help]
301 14:47:02.469398
302 14:47:02.469497 F0: 102B 0000
303 14:47:02.469591
304 14:47:02.469684 F3: 1001 0000 [0200]
305 14:47:02.469776
306 14:47:02.469865 F3: 1001 0000
307 14:47:02.469958
308 14:47:02.470051 F7: 102D 0000
309 14:47:02.470139
310 14:47:02.470250 F1: 0000 0000
311 14:47:02.470309
312 14:47:02.470365 V0: 0000 0000 [0001]
313 14:47:02.470422
314 14:47:02.470476 00: 0007 8000
315 14:47:02.470556
316 14:47:02.470647 01: 0000 0000
317 14:47:02.470709
318 14:47:02.470774 BP: 0C00 0209 [0000]
319 14:47:02.470831
320 14:47:02.470886 G0: 1182 0000
321 14:47:02.470942
322 14:47:02.471001 EC: 0000 0021 [4000]
323 14:47:02.471057
324 14:47:02.471111 S7: 0000 0000 [0000]
325 14:47:02.471165
326 14:47:02.471218 CC: 0000 0000 [0001]
327 14:47:02.471279
328 14:47:02.471334 T0: 0000 0040 [010F]
329 14:47:02.471388
330 14:47:02.471450 Jump to BL
331 14:47:02.471516
332 14:47:02.471572
333 14:47:02.471627
334 14:47:02.471681 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
335 14:47:02.471744 ARM64: Exception handlers installed.
336 14:47:02.471801 ARM64: Testing exception
337 14:47:02.471856 ARM64: Done test exception
338 14:47:02.471911 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
339 14:47:02.471966 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
340 14:47:02.472028 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
341 14:47:02.472084 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
342 14:47:02.472140 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
343 14:47:02.472195 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
344 14:47:02.472255 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
345 14:47:02.472312 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
346 14:47:02.472366 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
347 14:47:02.472422 WDT: Last reset was cold boot
348 14:47:02.472479 SPI1(PAD0) initialized at 2873684 Hz
349 14:47:02.472538 SPI5(PAD0) initialized at 992727 Hz
350 14:47:02.472607 VBOOT: Loading verstage.
351 14:47:02.472663 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
352 14:47:02.472718 FMAP: Found "FLASH" version 1.1 at 0x20000.
353 14:47:02.472779 FMAP: base = 0x0 size = 0x800000 #areas = 25
354 14:47:02.472835 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
355 14:47:02.472890 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
356 14:47:02.472945 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
357 14:47:02.473008 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
358 14:47:02.473064
359 14:47:02.473124
360 14:47:02.473179 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
361 14:47:02.473242 ARM64: Exception handlers installed.
362 14:47:02.473297 ARM64: Testing exception
363 14:47:02.473352 ARM64: Done test exception
364 14:47:02.473409 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
365 14:47:02.473469 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
366 14:47:02.473524 Probing TPM: . done!
367 14:47:02.473579 TPM ready after 0 ms
368 14:47:02.473634 Connected to device vid:did:rid of 1ae0:0028:00
369 14:47:02.473688 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
370 14:47:02.473751 Initialized TPM device CR50 revision 0
371 14:47:02.473806 tlcl_send_startup: Startup return code is 0
372 14:47:02.473862 TPM: setup succeeded
373 14:47:02.473917 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
374 14:47:02.473978 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
375 14:47:02.474034 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
376 14:47:02.474089 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 14:47:02.474144 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
378 14:47:02.474249 in-header: 03 07 00 00 08 00 00 00
379 14:47:02.474305 in-data: aa e4 47 04 13 02 00 00
380 14:47:02.474359 Chrome EC: UHEPI supported
381 14:47:02.474414 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
382 14:47:02.474476 in-header: 03 a9 00 00 08 00 00 00
383 14:47:02.474532 in-data: 84 60 60 08 00 00 00 00
384 14:47:02.474587 Phase 1
385 14:47:02.474641 FMAP: area GBB found @ 3f5000 (12032 bytes)
386 14:47:02.474733 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
387 14:47:02.474790 VB2:vb2_check_recovery() Recovery was requested manually
388 14:47:02.474844 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
389 14:47:02.474899 Recovery requested (1009000e)
390 14:47:02.474959 TPM: Extending digest for VBOOT: boot mode into PCR 0
391 14:47:02.475015 tlcl_extend: response is 0
392 14:47:02.475069 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
393 14:47:02.475124 tlcl_extend: response is 0
394 14:47:02.475181 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
395 14:47:02.475238 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
396 14:47:02.475293 BS: bootblock times (exec / console): total (unknown) / 148 ms
397 14:47:02.475348
398 14:47:02.475402
399 14:47:02.475467 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
400 14:47:02.475528 ARM64: Exception handlers installed.
401 14:47:02.475584 ARM64: Testing exception
402 14:47:02.475638 ARM64: Done test exception
403 14:47:02.475697 pmic_efuse_setting: Set efuses in 11 msecs
404 14:47:02.475754 pmwrap_interface_init: Select PMIF_VLD_RDY
405 14:47:02.475808 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
406 14:47:02.476056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
407 14:47:02.476160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
408 14:47:02.476261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
409 14:47:02.476348 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
410 14:47:02.476435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
411 14:47:02.476526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
412 14:47:02.476640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
413 14:47:02.476749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
414 14:47:02.476844 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
415 14:47:02.476925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
416 14:47:02.476982 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
417 14:47:02.477044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
418 14:47:02.477100 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
419 14:47:02.477156 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
420 14:47:02.477211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
421 14:47:02.477266 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
422 14:47:02.477328 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
423 14:47:02.477383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
424 14:47:02.477438 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
425 14:47:02.477492 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
426 14:47:02.477547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
427 14:47:02.477618 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
428 14:47:02.477700 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
429 14:47:02.477758 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
430 14:47:02.477813 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
431 14:47:02.477868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
432 14:47:02.477930 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
433 14:47:02.477985 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
434 14:47:02.478039 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
435 14:47:02.478094 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
436 14:47:02.478148 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
437 14:47:02.478251 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
438 14:47:02.478306 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
439 14:47:02.478361 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
440 14:47:02.478415 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
441 14:47:02.478473 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
442 14:47:02.478530 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
443 14:47:02.478585 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
444 14:47:02.478640 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
445 14:47:02.478693 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
446 14:47:02.478748 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
447 14:47:02.478810 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
448 14:47:02.478865 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
449 14:47:02.478920 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
450 14:47:02.478974 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
451 14:47:02.479029 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
452 14:47:02.479088 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
453 14:47:02.479144 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
454 14:47:02.479198 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
455 14:47:02.479252 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
456 14:47:02.479306 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
457 14:47:02.479362 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
458 14:47:02.479422 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
459 14:47:02.479477 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
460 14:47:02.479532 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
461 14:47:02.479588 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
462 14:47:02.479642 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
463 14:47:02.479703 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 14:47:02.479758 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2c
465 14:47:02.479813 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
466 14:47:02.479868 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
467 14:47:02.479922 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
468 14:47:02.479980 [RTC]rtc_get_frequency_meter,154: input=15, output=834
469 14:47:02.480066 [RTC]rtc_get_frequency_meter,154: input=7, output=709
470 14:47:02.480120 [RTC]rtc_get_frequency_meter,154: input=11, output=772
471 14:47:02.480174 [RTC]rtc_get_frequency_meter,154: input=13, output=803
472 14:47:02.480228 [RTC]rtc_get_frequency_meter,154: input=12, output=786
473 14:47:02.480287 [RTC]rtc_get_frequency_meter,154: input=12, output=787
474 14:47:02.480342 [RTC]rtc_get_frequency_meter,154: input=13, output=802
475 14:47:02.480396 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
476 14:47:02.480640 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
477 14:47:02.480757 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
478 14:47:02.480869 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
479 14:47:02.480982 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
480 14:47:02.481087 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
481 14:47:02.481183 ADC[4]: Raw value=904139 ID=7
482 14:47:02.481259 ADC[3]: Raw value=214021 ID=1
483 14:47:02.481317 RAM Code: 0x71
484 14:47:02.481373 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
485 14:47:02.481428 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
486 14:47:02.481488 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
487 14:47:02.481547 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
488 14:47:02.481603 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
489 14:47:02.481659 in-header: 03 07 00 00 08 00 00 00
490 14:47:02.481713 in-data: aa e4 47 04 13 02 00 00
491 14:47:02.481768 Chrome EC: UHEPI supported
492 14:47:02.481830 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
493 14:47:02.481886 in-header: 03 a9 00 00 08 00 00 00
494 14:47:02.481940 in-data: 84 60 60 08 00 00 00 00
495 14:47:02.481994 MRC: failed to locate region type 0.
496 14:47:02.482048 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
497 14:47:02.482110 DRAM-K: Running full calibration
498 14:47:02.482188 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
499 14:47:02.482258 header.status = 0x0
500 14:47:02.482312 header.version = 0x6 (expected: 0x6)
501 14:47:02.482366 header.size = 0xd00 (expected: 0xd00)
502 14:47:02.482428 header.flags = 0x0
503 14:47:02.482483 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
504 14:47:02.482537 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
505 14:47:02.482592 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
506 14:47:02.482648 dram_init: ddr_geometry: 2
507 14:47:02.482706 [EMI] MDL number = 2
508 14:47:02.482761 [EMI] Get MDL freq = 0
509 14:47:02.482815 dram_init: ddr_type: 0
510 14:47:02.482869 is_discrete_lpddr4: 1
511 14:47:02.482924 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
512 14:47:02.482979
513 14:47:02.483038
514 14:47:02.483092 [Bian_co] ETT version 0.0.0.1
515 14:47:02.483146 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
516 14:47:02.483201
517 14:47:02.483255 dramc_set_vcore_voltage set vcore to 650000
518 14:47:02.483316 Read voltage for 800, 4
519 14:47:02.483377 Vio18 = 0
520 14:47:02.483502 Vcore = 650000
521 14:47:02.483561 Vdram = 0
522 14:47:02.483623 Vddq = 0
523 14:47:02.483678 Vmddr = 0
524 14:47:02.483732 dram_init: config_dvfs: 1
525 14:47:02.483786 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
526 14:47:02.483845 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
527 14:47:02.483902 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
528 14:47:02.483957 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
529 14:47:02.484011 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
530 14:47:02.484066 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
531 14:47:02.484121 MEM_TYPE=3, freq_sel=18
532 14:47:02.484180 sv_algorithm_assistance_LP4_1600
533 14:47:02.484234 ============ PULL DRAM RESETB DOWN ============
534 14:47:02.484289 ========== PULL DRAM RESETB DOWN end =========
535 14:47:02.484343 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
536 14:47:02.484397 ===================================
537 14:47:02.484458 LPDDR4 DRAM CONFIGURATION
538 14:47:02.484513 ===================================
539 14:47:02.484567 EX_ROW_EN[0] = 0x0
540 14:47:02.484622 EX_ROW_EN[1] = 0x0
541 14:47:02.484681 LP4Y_EN = 0x0
542 14:47:02.484740 WORK_FSP = 0x0
543 14:47:02.484796 WL = 0x2
544 14:47:02.484850 RL = 0x2
545 14:47:02.484904 BL = 0x2
546 14:47:02.484958 RPST = 0x0
547 14:47:02.485017 RD_PRE = 0x0
548 14:47:02.485072 WR_PRE = 0x1
549 14:47:02.485126 WR_PST = 0x0
550 14:47:02.485180 DBI_WR = 0x0
551 14:47:02.485234 DBI_RD = 0x0
552 14:47:02.485288 OTF = 0x1
553 14:47:02.485348 ===================================
554 14:47:02.485403 ===================================
555 14:47:02.485457 ANA top config
556 14:47:02.485511 ===================================
557 14:47:02.485566 DLL_ASYNC_EN = 0
558 14:47:02.485627 ALL_SLAVE_EN = 1
559 14:47:02.485682 NEW_RANK_MODE = 1
560 14:47:02.485737 DLL_IDLE_MODE = 1
561 14:47:02.485791 LP45_APHY_COMB_EN = 1
562 14:47:02.485845 TX_ODT_DIS = 1
563 14:47:02.485906 NEW_8X_MODE = 1
564 14:47:02.485960 ===================================
565 14:47:02.486015 ===================================
566 14:47:02.486068 data_rate = 1600
567 14:47:02.486122 CKR = 1
568 14:47:02.486220 DQ_P2S_RATIO = 8
569 14:47:02.486289 ===================================
570 14:47:02.486344 CA_P2S_RATIO = 8
571 14:47:02.486398 DQ_CA_OPEN = 0
572 14:47:02.486465 DQ_SEMI_OPEN = 0
573 14:47:02.486533 CA_SEMI_OPEN = 0
574 14:47:02.486588 CA_FULL_RATE = 0
575 14:47:02.486642 DQ_CKDIV4_EN = 1
576 14:47:02.486696 CA_CKDIV4_EN = 1
577 14:47:02.486774 CA_PREDIV_EN = 0
578 14:47:02.486830 PH8_DLY = 0
579 14:47:02.486884 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
580 14:47:02.486939 DQ_AAMCK_DIV = 4
581 14:47:02.487014 CA_AAMCK_DIV = 4
582 14:47:02.487071 CA_ADMCK_DIV = 4
583 14:47:02.487126 DQ_TRACK_CA_EN = 0
584 14:47:02.487180 CA_PICK = 800
585 14:47:02.487249 CA_MCKIO = 800
586 14:47:02.487307 MCKIO_SEMI = 0
587 14:47:02.487362 PLL_FREQ = 3068
588 14:47:02.487416 DQ_UI_PI_RATIO = 32
589 14:47:02.487471 CA_UI_PI_RATIO = 0
590 14:47:02.487542 ===================================
591 14:47:02.487598 ===================================
592 14:47:02.487653 memory_type:LPDDR4
593 14:47:02.487707 GP_NUM : 10
594 14:47:02.487783 SRAM_EN : 1
595 14:47:02.487839 MD32_EN : 0
596 14:47:02.488102 ===================================
597 14:47:02.488219 [ANA_INIT] >>>>>>>>>>>>>>
598 14:47:02.488333 <<<<<< [CONFIGURE PHASE]: ANA_TX
599 14:47:02.488447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
600 14:47:02.488552 ===================================
601 14:47:02.488648 data_rate = 1600,PCW = 0X7600
602 14:47:02.488721 ===================================
603 14:47:02.488778 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
604 14:47:02.488845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 14:47:02.488904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 14:47:02.488966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
607 14:47:02.489023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
608 14:47:02.489078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
609 14:47:02.489140 [ANA_INIT] flow start
610 14:47:02.489196 [ANA_INIT] PLL >>>>>>>>
611 14:47:02.489251 [ANA_INIT] PLL <<<<<<<<
612 14:47:02.489305 [ANA_INIT] MIDPI >>>>>>>>
613 14:47:02.489360 [ANA_INIT] MIDPI <<<<<<<<
614 14:47:02.489418 [ANA_INIT] DLL >>>>>>>>
615 14:47:02.489474 [ANA_INIT] flow end
616 14:47:02.489528 ============ LP4 DIFF to SE enter ============
617 14:47:02.489584 ============ LP4 DIFF to SE exit ============
618 14:47:02.489639 [ANA_INIT] <<<<<<<<<<<<<
619 14:47:02.489706 [Flow] Enable top DCM control >>>>>
620 14:47:02.489762 [Flow] Enable top DCM control <<<<<
621 14:47:02.489818 Enable DLL master slave shuffle
622 14:47:02.489872 ==============================================================
623 14:47:02.489928 Gating Mode config
624 14:47:02.489989 ==============================================================
625 14:47:02.490044 Config description:
626 14:47:02.490099 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
627 14:47:02.490155 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
628 14:47:02.490259 SELPH_MODE 0: By rank 1: By Phase
629 14:47:02.490317 ==============================================================
630 14:47:02.490372 GAT_TRACK_EN = 1
631 14:47:02.490427 RX_GATING_MODE = 2
632 14:47:02.490482 RX_GATING_TRACK_MODE = 2
633 14:47:02.490537 SELPH_MODE = 1
634 14:47:02.490597 PICG_EARLY_EN = 1
635 14:47:02.490652 VALID_LAT_VALUE = 1
636 14:47:02.490706 ==============================================================
637 14:47:02.490761 Enter into Gating configuration >>>>
638 14:47:02.490816 Exit from Gating configuration <<<<
639 14:47:02.490877 Enter into DVFS_PRE_config >>>>>
640 14:47:02.490931 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
641 14:47:02.490990 Exit from DVFS_PRE_config <<<<<
642 14:47:02.491045 Enter into PICG configuration >>>>
643 14:47:02.491100 Exit from PICG configuration <<<<
644 14:47:02.491161 [RX_INPUT] configuration >>>>>
645 14:47:02.491216 [RX_INPUT] configuration <<<<<
646 14:47:02.491270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
647 14:47:02.491325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
648 14:47:02.491380 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
649 14:47:02.491439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
650 14:47:02.491495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
651 14:47:02.491550 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
652 14:47:02.491604 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
653 14:47:02.491659 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
654 14:47:02.491714 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
655 14:47:02.491774 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
656 14:47:02.491829 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
657 14:47:02.491884 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
658 14:47:02.491939 ===================================
659 14:47:02.491993 LPDDR4 DRAM CONFIGURATION
660 14:47:02.492054 ===================================
661 14:47:02.492109 EX_ROW_EN[0] = 0x0
662 14:47:02.492163 EX_ROW_EN[1] = 0x0
663 14:47:02.492218 LP4Y_EN = 0x0
664 14:47:02.492272 WORK_FSP = 0x0
665 14:47:02.492330 WL = 0x2
666 14:47:02.492386 RL = 0x2
667 14:47:02.492441 BL = 0x2
668 14:47:02.492495 RPST = 0x0
669 14:47:02.492551 RD_PRE = 0x0
670 14:47:02.492606 WR_PRE = 0x1
671 14:47:02.492691 WR_PST = 0x0
672 14:47:02.492775 DBI_WR = 0x0
673 14:47:02.492863 DBI_RD = 0x0
674 14:47:02.492941 OTF = 0x1
675 14:47:02.492997 ===================================
676 14:47:02.493052 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
677 14:47:02.493107 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
678 14:47:02.493163 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
679 14:47:02.493222 ===================================
680 14:47:02.493278 LPDDR4 DRAM CONFIGURATION
681 14:47:02.493333 ===================================
682 14:47:02.493388 EX_ROW_EN[0] = 0x10
683 14:47:02.493442 EX_ROW_EN[1] = 0x0
684 14:47:02.493497 LP4Y_EN = 0x0
685 14:47:02.493555 WORK_FSP = 0x0
686 14:47:02.493609 WL = 0x2
687 14:47:02.493663 RL = 0x2
688 14:47:02.493722 BL = 0x2
689 14:47:02.493779 RPST = 0x0
690 14:47:02.493839 RD_PRE = 0x0
691 14:47:02.493894 WR_PRE = 0x1
692 14:47:02.493949 WR_PST = 0x0
693 14:47:02.494003 DBI_WR = 0x0
694 14:47:02.494056 DBI_RD = 0x0
695 14:47:02.494126 OTF = 0x1
696 14:47:02.494232 ===================================
697 14:47:02.494289 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
698 14:47:02.494345 nWR fixed to 40
699 14:47:02.494404 [ModeRegInit_LP4] CH0 RK0
700 14:47:02.494459 [ModeRegInit_LP4] CH0 RK1
701 14:47:02.494513 [ModeRegInit_LP4] CH1 RK0
702 14:47:02.494568 [ModeRegInit_LP4] CH1 RK1
703 14:47:02.494621 match AC timing 13
704 14:47:02.494873 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
705 14:47:02.494935 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
706 14:47:02.494999 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
707 14:47:02.495056 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
708 14:47:02.495112 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
709 14:47:02.495167 [EMI DOE] emi_dcm 0
710 14:47:02.495222 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
711 14:47:02.495281 ==
712 14:47:02.495338 Dram Type= 6, Freq= 0, CH_0, rank 0
713 14:47:02.495392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
714 14:47:02.495447 ==
715 14:47:02.495501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
716 14:47:02.495559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
717 14:47:02.495616 [CA 0] Center 37 (7~68) winsize 62
718 14:47:02.495670 [CA 1] Center 36 (6~67) winsize 62
719 14:47:02.495724 [CA 2] Center 34 (4~65) winsize 62
720 14:47:02.495778 [CA 3] Center 34 (4~65) winsize 62
721 14:47:02.495832 [CA 4] Center 34 (4~64) winsize 61
722 14:47:02.495892 [CA 5] Center 33 (3~64) winsize 62
723 14:47:02.495947
724 14:47:02.496001 [CmdBusTrainingLP45] Vref(ca) range 1: 30
725 14:47:02.496061
726 14:47:02.496115 [CATrainingPosCal] consider 1 rank data
727 14:47:02.496176 u2DelayCellTimex100 = 270/100 ps
728 14:47:02.496232 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
729 14:47:02.496286 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
730 14:47:02.496341 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
731 14:47:02.496396 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
732 14:47:02.496454 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
733 14:47:02.496510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
734 14:47:02.496564
735 14:47:02.496618 CA PerBit enable=1, Macro0, CA PI delay=33
736 14:47:02.496672
737 14:47:02.496727 [CBTSetCACLKResult] CA Dly = 33
738 14:47:02.496786 CS Dly: 6 (0~37)
739 14:47:02.496840 ==
740 14:47:02.496895 Dram Type= 6, Freq= 0, CH_0, rank 1
741 14:47:02.496949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
742 14:47:02.497004 ==
743 14:47:02.497064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
744 14:47:02.497119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
745 14:47:02.497174 [CA 0] Center 37 (6~68) winsize 63
746 14:47:02.497229 [CA 1] Center 37 (7~68) winsize 62
747 14:47:02.497283 [CA 2] Center 34 (4~65) winsize 62
748 14:47:02.497344 [CA 3] Center 34 (4~65) winsize 62
749 14:47:02.497399 [CA 4] Center 33 (3~64) winsize 62
750 14:47:02.497458 [CA 5] Center 33 (3~64) winsize 62
751 14:47:02.497547
752 14:47:02.497605 [CmdBusTrainingLP45] Vref(ca) range 1: 32
753 14:47:02.497666
754 14:47:02.497720 [CATrainingPosCal] consider 2 rank data
755 14:47:02.497775 u2DelayCellTimex100 = 270/100 ps
756 14:47:02.497830 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
757 14:47:02.497892 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
758 14:47:02.497978 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
759 14:47:02.498063 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
760 14:47:02.498147 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
761 14:47:02.498284 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
762 14:47:02.498341
763 14:47:02.498396 CA PerBit enable=1, Macro0, CA PI delay=33
764 14:47:02.498451
765 14:47:02.498511 [CBTSetCACLKResult] CA Dly = 33
766 14:47:02.498565 CS Dly: 6 (0~38)
767 14:47:02.498620
768 14:47:02.498674 ----->DramcWriteLeveling(PI) begin...
769 14:47:02.498732 ==
770 14:47:02.498793 Dram Type= 6, Freq= 0, CH_0, rank 0
771 14:47:02.498848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
772 14:47:02.498903 ==
773 14:47:02.498957 Write leveling (Byte 0): 34 => 34
774 14:47:02.499012 Write leveling (Byte 1): 31 => 31
775 14:47:02.499070 DramcWriteLeveling(PI) end<-----
776 14:47:02.499125
777 14:47:02.499179 ==
778 14:47:02.499233 Dram Type= 6, Freq= 0, CH_0, rank 0
779 14:47:02.499288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 14:47:02.499341 ==
781 14:47:02.499404 [Gating] SW mode calibration
782 14:47:02.499459 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
783 14:47:02.499514 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
784 14:47:02.499568 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
785 14:47:02.499623 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
786 14:47:02.499685 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
787 14:47:02.499740 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 14:47:02.499794 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 14:47:02.499853 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 14:47:02.499909 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 14:47:02.499970 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 14:47:02.500024 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 14:47:02.500079 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 14:47:02.500133 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 14:47:02.500187 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 14:47:02.500250 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 14:47:02.500336 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 14:47:02.500420 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 14:47:02.500505 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 14:47:02.500593 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 14:47:02.500678 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 14:47:02.500763 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
803 14:47:02.500851 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 14:47:02.500936 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 14:47:02.501021 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 14:47:02.501105 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 14:47:02.501193 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 14:47:02.501278 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 14:47:02.501363 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 14:47:02.501451 0 9 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
811 14:47:02.501536 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
812 14:47:02.501816 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 14:47:02.501932 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 14:47:02.502045 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 14:47:02.502155 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 14:47:02.502272 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 14:47:02.502384 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 14:47:02.502498 0 10 8 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)
819 14:47:02.502601 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
820 14:47:02.502722 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 14:47:02.502810 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 14:47:02.502900 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 14:47:02.502989 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 14:47:02.503076 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 14:47:02.503149 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
826 14:47:02.503205 0 11 8 | B1->B0 | 2626 3939 | 0 0 | (0 0) (0 0)
827 14:47:02.503261 0 11 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
828 14:47:02.503316 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 14:47:02.503370 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 14:47:02.503429 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 14:47:02.503485 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 14:47:02.503540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 14:47:02.503594 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
834 14:47:02.503648 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
835 14:47:02.503703 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 14:47:02.503762 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 14:47:02.503816 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 14:47:02.503870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 14:47:02.503925 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 14:47:02.503979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 14:47:02.504041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 14:47:02.504096 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 14:47:02.504151 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 14:47:02.504205 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 14:47:02.504260 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 14:47:02.504319 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 14:47:02.504376 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 14:47:02.504430 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 14:47:02.504484 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 14:47:02.504538 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 14:47:02.504597 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 14:47:02.504653 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 14:47:02.504707 Total UI for P1: 0, mck2ui 16
854 14:47:02.504762 best dqsien dly found for B0: ( 0, 14, 10)
855 14:47:02.504816 Total UI for P1: 0, mck2ui 16
856 14:47:02.504871 best dqsien dly found for B1: ( 0, 14, 12)
857 14:47:02.504959 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
858 14:47:02.505044 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
859 14:47:02.505128
860 14:47:02.505216 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
861 14:47:02.505301 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
862 14:47:02.505386 [Gating] SW calibration Done
863 14:47:02.505472 ==
864 14:47:02.505558 Dram Type= 6, Freq= 0, CH_0, rank 0
865 14:47:02.505643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 14:47:02.505727 ==
867 14:47:02.505801 RX Vref Scan: 0
868 14:47:02.505857
869 14:47:02.505912 RX Vref 0 -> 0, step: 1
870 14:47:02.505966
871 14:47:02.506021 RX Delay -130 -> 252, step: 16
872 14:47:02.506085 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 14:47:02.506195 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 14:47:02.506294 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
875 14:47:02.506379 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
876 14:47:02.506437 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 14:47:02.506492 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 14:47:02.506547 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
879 14:47:02.506601 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
880 14:47:02.506660 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
881 14:47:02.506716 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
882 14:47:02.506770 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 14:47:02.506824 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
884 14:47:02.506879 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
885 14:47:02.506937 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
886 14:47:02.506993 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
887 14:47:02.507047 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
888 14:47:02.507101 ==
889 14:47:02.507156 Dram Type= 6, Freq= 0, CH_0, rank 0
890 14:47:02.507211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 14:47:02.507273 ==
892 14:47:02.507329 DQS Delay:
893 14:47:02.507383 DQS0 = 0, DQS1 = 0
894 14:47:02.507438 DQM Delay:
895 14:47:02.507492 DQM0 = 83, DQM1 = 69
896 14:47:02.507551 DQ Delay:
897 14:47:02.507606 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
898 14:47:02.507661 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
899 14:47:02.507715 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
900 14:47:02.507769 DQ12 =69, DQ13 =77, DQ14 =77, DQ15 =77
901 14:47:02.507823
902 14:47:02.507882
903 14:47:02.507936 ==
904 14:47:02.507991 Dram Type= 6, Freq= 0, CH_0, rank 0
905 14:47:02.508048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 14:47:02.508104 ==
907 14:47:02.508170
908 14:47:02.508225
909 14:47:02.508280 TX Vref Scan disable
910 14:47:02.508334 == TX Byte 0 ==
911 14:47:02.508388 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
912 14:47:02.508449 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
913 14:47:02.508505 == TX Byte 1 ==
914 14:47:02.508583 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
915 14:47:02.508693 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
916 14:47:02.508753 ==
917 14:47:02.508808 Dram Type= 6, Freq= 0, CH_0, rank 0
918 14:47:02.508863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 14:47:02.508919 ==
920 14:47:02.509173 TX Vref=22, minBit 3, minWin=27, winSum=443
921 14:47:02.509240 TX Vref=24, minBit 3, minWin=27, winSum=445
922 14:47:02.509298 TX Vref=26, minBit 8, minWin=27, winSum=449
923 14:47:02.509388 TX Vref=28, minBit 8, minWin=27, winSum=449
924 14:47:02.509473 TX Vref=30, minBit 10, minWin=27, winSum=450
925 14:47:02.509562 TX Vref=32, minBit 7, minWin=27, winSum=448
926 14:47:02.509652 [TxChooseVref] Worse bit 10, Min win 27, Win sum 450, Final Vref 30
927 14:47:02.509737
928 14:47:02.509822 Final TX Range 1 Vref 30
929 14:47:02.509909
930 14:47:02.509993 ==
931 14:47:02.510078 Dram Type= 6, Freq= 0, CH_0, rank 0
932 14:47:02.510171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 14:47:02.510267 ==
934 14:47:02.510322
935 14:47:02.510377
936 14:47:02.510432 TX Vref Scan disable
937 14:47:02.510493 == TX Byte 0 ==
938 14:47:02.510549 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
939 14:47:02.510604 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
940 14:47:02.510659 == TX Byte 1 ==
941 14:47:02.510713 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
942 14:47:02.510774 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
943 14:47:02.510833
944 14:47:02.510888 [DATLAT]
945 14:47:02.510942 Freq=800, CH0 RK0
946 14:47:02.510996
947 14:47:02.511055 DATLAT Default: 0xa
948 14:47:02.511111 0, 0xFFFF, sum = 0
949 14:47:02.511166 1, 0xFFFF, sum = 0
950 14:47:02.511222 2, 0xFFFF, sum = 0
951 14:47:02.511277 3, 0xFFFF, sum = 0
952 14:47:02.511332 4, 0xFFFF, sum = 0
953 14:47:02.511392 5, 0xFFFF, sum = 0
954 14:47:02.511447 6, 0xFFFF, sum = 0
955 14:47:02.511501 7, 0xFFFF, sum = 0
956 14:47:02.511555 8, 0xFFFF, sum = 0
957 14:47:02.511610 9, 0x0, sum = 1
958 14:47:02.511671 10, 0x0, sum = 2
959 14:47:02.511727 11, 0x0, sum = 3
960 14:47:02.511781 12, 0x0, sum = 4
961 14:47:02.511837 best_step = 10
962 14:47:02.511894
963 14:47:02.511950 ==
964 14:47:02.512004 Dram Type= 6, Freq= 0, CH_0, rank 0
965 14:47:02.512059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 14:47:02.512114 ==
967 14:47:02.512171 RX Vref Scan: 1
968 14:47:02.512229
969 14:47:02.512283 Set Vref Range= 32 -> 127
970 14:47:02.512338
971 14:47:02.512425 RX Vref 32 -> 127, step: 1
972 14:47:02.512515
973 14:47:02.512655 RX Delay -111 -> 252, step: 8
974 14:47:02.512789
975 14:47:02.512873 Set Vref, RX VrefLevel [Byte0]: 32
976 14:47:02.512958 [Byte1]: 32
977 14:47:02.513044
978 14:47:02.513128 Set Vref, RX VrefLevel [Byte0]: 33
979 14:47:02.513212 [Byte1]: 33
980 14:47:02.513296
981 14:47:02.513383 Set Vref, RX VrefLevel [Byte0]: 34
982 14:47:02.513468 [Byte1]: 34
983 14:47:02.513550
984 14:47:02.513637 Set Vref, RX VrefLevel [Byte0]: 35
985 14:47:02.513723 [Byte1]: 35
986 14:47:02.513806
987 14:47:02.513890 Set Vref, RX VrefLevel [Byte0]: 36
988 14:47:02.513977 [Byte1]: 36
989 14:47:02.514061
990 14:47:02.514145 Set Vref, RX VrefLevel [Byte0]: 37
991 14:47:02.514270 [Byte1]: 37
992 14:47:02.514354
993 14:47:02.514443 Set Vref, RX VrefLevel [Byte0]: 38
994 14:47:02.514502 [Byte1]: 38
995 14:47:02.514562
996 14:47:02.514617 Set Vref, RX VrefLevel [Byte0]: 39
997 14:47:02.514672 [Byte1]: 39
998 14:47:02.514726
999 14:47:02.514780 Set Vref, RX VrefLevel [Byte0]: 40
1000 14:47:02.514841 [Byte1]: 40
1001 14:47:02.514896
1002 14:47:02.514950 Set Vref, RX VrefLevel [Byte0]: 41
1003 14:47:02.515005 [Byte1]: 41
1004 14:47:02.515059
1005 14:47:02.515118 Set Vref, RX VrefLevel [Byte0]: 42
1006 14:47:02.515173 [Byte1]: 42
1007 14:47:02.515228
1008 14:47:02.515281 Set Vref, RX VrefLevel [Byte0]: 43
1009 14:47:02.515336 [Byte1]: 43
1010 14:47:02.515390
1011 14:47:02.515450 Set Vref, RX VrefLevel [Byte0]: 44
1012 14:47:02.515505 [Byte1]: 44
1013 14:47:02.515559
1014 14:47:02.515612 Set Vref, RX VrefLevel [Byte0]: 45
1015 14:47:02.515667 [Byte1]: 45
1016 14:47:02.515728
1017 14:47:02.515784 Set Vref, RX VrefLevel [Byte0]: 46
1018 14:47:02.515839 [Byte1]: 46
1019 14:47:02.515894
1020 14:47:02.515952 Set Vref, RX VrefLevel [Byte0]: 47
1021 14:47:02.516015 [Byte1]: 47
1022 14:47:02.516070
1023 14:47:02.516125 Set Vref, RX VrefLevel [Byte0]: 48
1024 14:47:02.516180 [Byte1]: 48
1025 14:47:02.516241
1026 14:47:02.516305 Set Vref, RX VrefLevel [Byte0]: 49
1027 14:47:02.516400 [Byte1]: 49
1028 14:47:02.516459
1029 14:47:02.516515 Set Vref, RX VrefLevel [Byte0]: 50
1030 14:47:02.516578 [Byte1]: 50
1031 14:47:02.516633
1032 14:47:02.516687 Set Vref, RX VrefLevel [Byte0]: 51
1033 14:47:02.516742 [Byte1]: 51
1034 14:47:02.516852
1035 14:47:02.516926 Set Vref, RX VrefLevel [Byte0]: 52
1036 14:47:02.516980 [Byte1]: 52
1037 14:47:02.517033
1038 14:47:02.517087 Set Vref, RX VrefLevel [Byte0]: 53
1039 14:47:02.517145 [Byte1]: 53
1040 14:47:02.517201
1041 14:47:02.517254 Set Vref, RX VrefLevel [Byte0]: 54
1042 14:47:02.517308 [Byte1]: 54
1043 14:47:02.517361
1044 14:47:02.517417 Set Vref, RX VrefLevel [Byte0]: 55
1045 14:47:02.517472 [Byte1]: 55
1046 14:47:02.517526
1047 14:47:02.517579 Set Vref, RX VrefLevel [Byte0]: 56
1048 14:47:02.517632 [Byte1]: 56
1049 14:47:02.517686
1050 14:47:02.517745 Set Vref, RX VrefLevel [Byte0]: 57
1051 14:47:02.517800 [Byte1]: 57
1052 14:47:02.517854
1053 14:47:02.517907 Set Vref, RX VrefLevel [Byte0]: 58
1054 14:47:02.517961 [Byte1]: 58
1055 14:47:02.518021
1056 14:47:02.518105 Set Vref, RX VrefLevel [Byte0]: 59
1057 14:47:02.518225 [Byte1]: 59
1058 14:47:02.518282
1059 14:47:02.518342 Set Vref, RX VrefLevel [Byte0]: 60
1060 14:47:02.518397 [Byte1]: 60
1061 14:47:02.518450
1062 14:47:02.518504 Set Vref, RX VrefLevel [Byte0]: 61
1063 14:47:02.518557 [Byte1]: 61
1064 14:47:02.518615
1065 14:47:02.518670 Set Vref, RX VrefLevel [Byte0]: 62
1066 14:47:02.518724 [Byte1]: 62
1067 14:47:02.518777
1068 14:47:02.518831 Set Vref, RX VrefLevel [Byte0]: 63
1069 14:47:02.518884 [Byte1]: 63
1070 14:47:02.518943
1071 14:47:02.518997 Set Vref, RX VrefLevel [Byte0]: 64
1072 14:47:02.519050 [Byte1]: 64
1073 14:47:02.519104
1074 14:47:02.519157 Set Vref, RX VrefLevel [Byte0]: 65
1075 14:47:02.519217 [Byte1]: 65
1076 14:47:02.519276
1077 14:47:02.519330 Set Vref, RX VrefLevel [Byte0]: 66
1078 14:47:02.519383 [Byte1]: 66
1079 14:47:02.519437
1080 14:47:02.519496 Set Vref, RX VrefLevel [Byte0]: 67
1081 14:47:02.519550 [Byte1]: 67
1082 14:47:02.519603
1083 14:47:02.519656 Set Vref, RX VrefLevel [Byte0]: 68
1084 14:47:02.519710 [Byte1]: 68
1085 14:47:02.519770
1086 14:47:02.519824 Set Vref, RX VrefLevel [Byte0]: 69
1087 14:47:02.520074 [Byte1]: 69
1088 14:47:02.520186
1089 14:47:02.520294 Set Vref, RX VrefLevel [Byte0]: 70
1090 14:47:02.520404 [Byte1]: 70
1091 14:47:02.520511
1092 14:47:02.520619 Set Vref, RX VrefLevel [Byte0]: 71
1093 14:47:02.520728 [Byte1]: 71
1094 14:47:02.520835
1095 14:47:02.520943 Set Vref, RX VrefLevel [Byte0]: 72
1096 14:47:02.521036 [Byte1]: 72
1097 14:47:02.521125
1098 14:47:02.521181 Set Vref, RX VrefLevel [Byte0]: 73
1099 14:47:02.521258 [Byte1]: 73
1100 14:47:02.521341
1101 14:47:02.521424 Set Vref, RX VrefLevel [Byte0]: 74
1102 14:47:02.521508 [Byte1]: 74
1103 14:47:02.521565
1104 14:47:02.521619 Set Vref, RX VrefLevel [Byte0]: 75
1105 14:47:02.521672 [Byte1]: 75
1106 14:47:02.521733
1107 14:47:02.521821 Set Vref, RX VrefLevel [Byte0]: 76
1108 14:47:02.521878 [Byte1]: 76
1109 14:47:02.521980
1110 14:47:02.522048 Set Vref, RX VrefLevel [Byte0]: 77
1111 14:47:02.522139 [Byte1]: 77
1112 14:47:02.522226
1113 14:47:02.522280 Set Vref, RX VrefLevel [Byte0]: 78
1114 14:47:02.522338 [Byte1]: 78
1115 14:47:02.522394
1116 14:47:02.522447 Set Vref, RX VrefLevel [Byte0]: 79
1117 14:47:02.522501 [Byte1]: 79
1118 14:47:02.522555
1119 14:47:02.522609 Set Vref, RX VrefLevel [Byte0]: 80
1120 14:47:02.522670 [Byte1]: 80
1121 14:47:02.522724
1122 14:47:02.522777 Set Vref, RX VrefLevel [Byte0]: 81
1123 14:47:02.522831 [Byte1]: 81
1124 14:47:02.522889
1125 14:47:02.522943 Final RX Vref Byte 0 = 63 to rank0
1126 14:47:02.522997 Final RX Vref Byte 1 = 53 to rank0
1127 14:47:02.523052 Final RX Vref Byte 0 = 63 to rank1
1128 14:47:02.523106 Final RX Vref Byte 1 = 53 to rank1==
1129 14:47:02.523163 Dram Type= 6, Freq= 0, CH_0, rank 0
1130 14:47:02.523219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 14:47:02.523274 ==
1132 14:47:02.523328 DQS Delay:
1133 14:47:02.523382 DQS0 = 0, DQS1 = 0
1134 14:47:02.523435 DQM Delay:
1135 14:47:02.523496 DQM0 = 87, DQM1 = 75
1136 14:47:02.523550 DQ Delay:
1137 14:47:02.523604 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1138 14:47:02.523658 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1139 14:47:02.523712 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1140 14:47:02.523770 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1141 14:47:02.523825
1142 14:47:02.523878
1143 14:47:02.523932 [DQSOSCAuto] RK0, (LSB)MR18= 0x4123, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1144 14:47:02.523987 CH0 RK0: MR19=606, MR18=4123
1145 14:47:02.524040 CH0_RK0: MR19=0x606, MR18=0x4123, DQSOSC=393, MR23=63, INC=95, DEC=63
1146 14:47:02.524100
1147 14:47:02.524153 ----->DramcWriteLeveling(PI) begin...
1148 14:47:02.524209 ==
1149 14:47:02.524262 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 14:47:02.524316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 14:47:02.524374 ==
1152 14:47:02.524429 Write leveling (Byte 0): 33 => 33
1153 14:47:02.524483 Write leveling (Byte 1): 32 => 32
1154 14:47:02.524536 DramcWriteLeveling(PI) end<-----
1155 14:47:02.524589
1156 14:47:02.524642 ==
1157 14:47:02.524701 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 14:47:02.524755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 14:47:02.524808 ==
1160 14:47:02.524862 [Gating] SW mode calibration
1161 14:47:02.524916 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1162 14:47:02.524977 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1163 14:47:02.525031 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1164 14:47:02.525085 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1165 14:47:02.525140 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1166 14:47:02.525194 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 14:47:02.525254 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 14:47:02.525338 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 14:47:02.525422 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 14:47:02.525505 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 14:47:02.525592 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 14:47:02.525675 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 14:47:02.525759 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 14:47:02.525859 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 14:47:02.525957 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 14:47:02.526041 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 14:47:02.526125 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 14:47:02.526248 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 14:47:02.526331 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 14:47:02.526415 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1181 14:47:02.526503 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1182 14:47:02.526587 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 14:47:02.526670 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 14:47:02.526757 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 14:47:02.526841 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 14:47:02.526924 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 14:47:02.527007 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 14:47:02.527096 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 14:47:02.527197 0 9 8 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
1190 14:47:02.527260 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1191 14:47:02.527320 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 14:47:02.527376 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 14:47:02.527431 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 14:47:02.527485 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 14:47:02.527539 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 14:47:02.527592 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1197 14:47:02.527657 0 10 8 | B1->B0 | 2f2f 2b2b | 0 0 | (1 0) (1 0)
1198 14:47:02.527712 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 14:47:02.527766 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 14:47:02.527820 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 14:47:02.528067 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 14:47:02.528157 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 14:47:02.528246 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 14:47:02.528331 0 11 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1205 14:47:02.528414 0 11 8 | B1->B0 | 2929 3b3b | 1 0 | (0 0) (0 0)
1206 14:47:02.528498 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1207 14:47:02.528566 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 14:47:02.528655 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 14:47:02.528739 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 14:47:02.528825 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 14:47:02.528910 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 14:47:02.528994 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 14:47:02.529077 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1214 14:47:02.529164 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 14:47:02.529253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 14:47:02.529348 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 14:47:02.529410 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 14:47:02.529466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 14:47:02.529521 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 14:47:02.529574 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 14:47:02.529628 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 14:47:02.529690 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 14:47:02.529775 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 14:47:02.529859 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 14:47:02.529944 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 14:47:02.530031 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 14:47:02.530115 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 14:47:02.530223 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 14:47:02.530285 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1230 14:47:02.530341 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 14:47:02.530395 Total UI for P1: 0, mck2ui 16
1232 14:47:02.530450 best dqsien dly found for B0: ( 0, 14, 8)
1233 14:47:02.530504 Total UI for P1: 0, mck2ui 16
1234 14:47:02.530562 best dqsien dly found for B1: ( 0, 14, 10)
1235 14:47:02.530618 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1236 14:47:02.530672 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1237 14:47:02.530725
1238 14:47:02.530779 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1239 14:47:02.530833 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1240 14:47:02.530893 [Gating] SW calibration Done
1241 14:47:02.530947 ==
1242 14:47:02.531001 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 14:47:02.531054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1244 14:47:02.531111 ==
1245 14:47:02.531167 RX Vref Scan: 0
1246 14:47:02.531220
1247 14:47:02.531274 RX Vref 0 -> 0, step: 1
1248 14:47:02.531327
1249 14:47:02.531380 RX Delay -130 -> 252, step: 16
1250 14:47:02.531440 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1251 14:47:02.531495 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1252 14:47:02.531548 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1253 14:47:02.531602 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1254 14:47:02.531656 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1255 14:47:02.531713 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1256 14:47:02.531769 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1257 14:47:02.531823 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1258 14:47:02.531876 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1259 14:47:02.531930 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1260 14:47:02.531984 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1261 14:47:02.532042 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1262 14:47:02.532096 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1263 14:47:02.532149 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1264 14:47:02.532202 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1265 14:47:02.532255 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1266 14:47:02.532327 ==
1267 14:47:02.532411 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 14:47:02.532495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 14:47:02.532578 ==
1270 14:47:02.532663 DQS Delay:
1271 14:47:02.532746 DQS0 = 0, DQS1 = 0
1272 14:47:02.532828 DQM Delay:
1273 14:47:02.532914 DQM0 = 87, DQM1 = 77
1274 14:47:02.532997 DQ Delay:
1275 14:47:02.533079 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1276 14:47:02.533163 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1277 14:47:02.533224 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =69
1278 14:47:02.533278 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1279 14:47:02.533332
1280 14:47:02.533385
1281 14:47:02.533438 ==
1282 14:47:02.533499 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 14:47:02.533553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 14:47:02.533607 ==
1285 14:47:02.533660
1286 14:47:02.533714
1287 14:47:02.533773 TX Vref Scan disable
1288 14:47:02.533857 == TX Byte 0 ==
1289 14:47:02.533940 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1290 14:47:02.534024 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1291 14:47:02.534110 == TX Byte 1 ==
1292 14:47:02.534227 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1293 14:47:02.534284 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1294 14:47:02.534341 ==
1295 14:47:02.534398 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 14:47:02.534451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 14:47:02.534505 ==
1298 14:47:02.534558 TX Vref=22, minBit 13, minWin=27, winSum=447
1299 14:47:02.534612 TX Vref=24, minBit 4, minWin=27, winSum=447
1300 14:47:02.534673 TX Vref=26, minBit 9, minWin=27, winSum=447
1301 14:47:02.534728 TX Vref=28, minBit 3, minWin=27, winSum=445
1302 14:47:02.534781 TX Vref=30, minBit 8, minWin=27, winSum=445
1303 14:47:02.534834 TX Vref=32, minBit 8, minWin=27, winSum=443
1304 14:47:02.534887 [TxChooseVref] Worse bit 13, Min win 27, Win sum 447, Final Vref 22
1305 14:47:02.534944
1306 14:47:02.534998 Final TX Range 1 Vref 22
1307 14:47:02.535052
1308 14:47:02.535104 ==
1309 14:47:02.535157 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 14:47:02.535211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 14:47:02.535272 ==
1312 14:47:02.535325
1313 14:47:02.535377
1314 14:47:02.535430 TX Vref Scan disable
1315 14:47:02.535483 == TX Byte 0 ==
1316 14:47:02.535540 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1317 14:47:02.535824 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1318 14:47:02.535930 == TX Byte 1 ==
1319 14:47:02.536016 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1320 14:47:02.536104 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1321 14:47:02.536187
1322 14:47:02.536269 [DATLAT]
1323 14:47:02.536355 Freq=800, CH0 RK1
1324 14:47:02.536439
1325 14:47:02.536521 DATLAT Default: 0xa
1326 14:47:02.536603 0, 0xFFFF, sum = 0
1327 14:47:02.536691 1, 0xFFFF, sum = 0
1328 14:47:02.536776 2, 0xFFFF, sum = 0
1329 14:47:02.536861 3, 0xFFFF, sum = 0
1330 14:47:02.536946 4, 0xFFFF, sum = 0
1331 14:47:02.537035 5, 0xFFFF, sum = 0
1332 14:47:02.537119 6, 0xFFFF, sum = 0
1333 14:47:02.537203 7, 0xFFFF, sum = 0
1334 14:47:02.537278 8, 0xFFFF, sum = 0
1335 14:47:02.537333 9, 0x0, sum = 1
1336 14:47:02.537389 10, 0x0, sum = 2
1337 14:47:02.537443 11, 0x0, sum = 3
1338 14:47:02.537498 12, 0x0, sum = 4
1339 14:47:02.537556 best_step = 10
1340 14:47:02.537610
1341 14:47:02.537663 ==
1342 14:47:02.537716 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 14:47:02.537770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 14:47:02.537825 ==
1345 14:47:02.537910 RX Vref Scan: 0
1346 14:47:02.537991
1347 14:47:02.538073 RX Vref 0 -> 0, step: 1
1348 14:47:02.538158
1349 14:47:02.538259 RX Delay -111 -> 252, step: 8
1350 14:47:02.538314 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1351 14:47:02.538368 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1352 14:47:02.538426 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1353 14:47:02.538481 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1354 14:47:02.538534 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1355 14:47:02.538587 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1356 14:47:02.538641 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1357 14:47:02.538694 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1358 14:47:02.538754 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1359 14:47:02.538811 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1360 14:47:02.538864 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1361 14:47:02.538918 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1362 14:47:02.538972 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1363 14:47:02.539030 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1364 14:47:02.539084 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1365 14:47:02.539138 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1366 14:47:02.539191 ==
1367 14:47:02.539244 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 14:47:02.539298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 14:47:02.539357 ==
1370 14:47:02.539410 DQS Delay:
1371 14:47:02.539462 DQS0 = 0, DQS1 = 0
1372 14:47:02.539515 DQM Delay:
1373 14:47:02.539568 DQM0 = 85, DQM1 = 76
1374 14:47:02.539640 DQ Delay:
1375 14:47:02.539723 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1376 14:47:02.539806 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1377 14:47:02.539892 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1378 14:47:02.539975 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1379 14:47:02.540057
1380 14:47:02.540139
1381 14:47:02.540225 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 395 ps
1382 14:47:02.540309 CH0 RK1: MR19=606, MR18=3A02
1383 14:47:02.540392 CH0_RK1: MR19=0x606, MR18=0x3A02, DQSOSC=395, MR23=63, INC=94, DEC=63
1384 14:47:02.540478 [RxdqsGatingPostProcess] freq 800
1385 14:47:02.540561 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1386 14:47:02.540644 Pre-setting of DQS Precalculation
1387 14:47:02.540728 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1388 14:47:02.540812 ==
1389 14:47:02.540895 Dram Type= 6, Freq= 0, CH_1, rank 0
1390 14:47:02.540977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 14:47:02.541066 ==
1392 14:47:02.541190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1393 14:47:02.541259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1394 14:47:02.541318 [CA 0] Center 36 (6~67) winsize 62
1395 14:47:02.541372 [CA 1] Center 36 (6~67) winsize 62
1396 14:47:02.541426 [CA 2] Center 34 (4~65) winsize 62
1397 14:47:02.541479 [CA 3] Center 34 (3~65) winsize 63
1398 14:47:02.541532 [CA 4] Center 34 (4~65) winsize 62
1399 14:47:02.541585 [CA 5] Center 34 (3~65) winsize 63
1400 14:47:02.541661
1401 14:47:02.541743 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1402 14:47:02.541826
1403 14:47:02.541909 [CATrainingPosCal] consider 1 rank data
1404 14:47:02.541999 u2DelayCellTimex100 = 270/100 ps
1405 14:47:02.542082 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1406 14:47:02.542171 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1407 14:47:02.542264 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1408 14:47:02.542318 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1409 14:47:02.542371 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 14:47:02.542424 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1411 14:47:02.542482
1412 14:47:02.542536 CA PerBit enable=1, Macro0, CA PI delay=34
1413 14:47:02.542589
1414 14:47:02.542642 [CBTSetCACLKResult] CA Dly = 34
1415 14:47:02.542696 CS Dly: 5 (0~36)
1416 14:47:02.542749 ==
1417 14:47:02.542807 Dram Type= 6, Freq= 0, CH_1, rank 1
1418 14:47:02.542860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 14:47:02.542914 ==
1420 14:47:02.542966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1421 14:47:02.543020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1422 14:47:02.543084 [CA 0] Center 36 (6~67) winsize 62
1423 14:47:02.543167 [CA 1] Center 36 (6~67) winsize 62
1424 14:47:02.543249 [CA 2] Center 34 (4~65) winsize 62
1425 14:47:02.543331 [CA 3] Center 34 (3~65) winsize 63
1426 14:47:02.543416 [CA 4] Center 34 (4~65) winsize 62
1427 14:47:02.543498 [CA 5] Center 34 (3~65) winsize 63
1428 14:47:02.543580
1429 14:47:02.543664 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1430 14:47:02.543746
1431 14:47:02.543829 [CATrainingPosCal] consider 2 rank data
1432 14:47:02.543911 u2DelayCellTimex100 = 270/100 ps
1433 14:47:02.543997 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 14:47:02.544080 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1435 14:47:02.544162 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 14:47:02.544248 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1437 14:47:02.544331 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 14:47:02.544414 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1439 14:47:02.544495
1440 14:47:02.544564 CA PerBit enable=1, Macro0, CA PI delay=34
1441 14:47:02.544618
1442 14:47:02.544671 [CBTSetCACLKResult] CA Dly = 34
1443 14:47:02.544724 CS Dly: 6 (0~38)
1444 14:47:02.544777
1445 14:47:02.544838 ----->DramcWriteLeveling(PI) begin...
1446 14:47:02.544923 ==
1447 14:47:02.545005 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 14:47:02.545088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 14:47:02.545173 ==
1450 14:47:02.545457 Write leveling (Byte 0): 28 => 28
1451 14:47:02.545522 Write leveling (Byte 1): 28 => 28
1452 14:47:02.545579 DramcWriteLeveling(PI) end<-----
1453 14:47:02.545633
1454 14:47:02.545687 ==
1455 14:47:02.545747 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 14:47:02.545802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 14:47:02.545856 ==
1458 14:47:02.545909 [Gating] SW mode calibration
1459 14:47:02.545969 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1460 14:47:02.546054 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1461 14:47:02.546137 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1462 14:47:02.546246 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1463 14:47:02.546302 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1464 14:47:02.546356 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 14:47:02.546409 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 14:47:02.546463 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 14:47:02.546516 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 14:47:02.546575 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 14:47:02.546628 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 14:47:02.546681 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 14:47:02.546734 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 14:47:02.546788 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 14:47:02.546846 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 14:47:02.546900 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 14:47:02.546953 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 14:47:02.547006 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 14:47:02.547058 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 14:47:02.547114 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1479 14:47:02.547170 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 14:47:02.547223 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 14:47:02.547275 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 14:47:02.547328 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 14:47:02.547381 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 14:47:02.547440 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 14:47:02.547494 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 14:47:02.547547 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 14:47:02.547600 0 9 8 | B1->B0 | 2a2a 3434 | 1 0 | (1 1) (0 0)
1488 14:47:02.547652 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 14:47:02.547710 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 14:47:02.547765 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 14:47:02.547818 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 14:47:02.547871 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 14:47:02.547924 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1494 14:47:02.547976 0 10 4 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
1495 14:47:02.548035 0 10 8 | B1->B0 | 2e2e 2727 | 1 1 | (1 0) (1 0)
1496 14:47:02.548089 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 14:47:02.548141 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 14:47:02.548195 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 14:47:02.548248 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 14:47:02.548305 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 14:47:02.548359 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 14:47:02.548412 0 11 4 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
1503 14:47:02.548465 0 11 8 | B1->B0 | 3838 4343 | 0 0 | (0 0) (0 0)
1504 14:47:02.548519 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 14:47:02.548571 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 14:47:02.548655 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 14:47:02.548727 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 14:47:02.548784 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 14:47:02.548838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1510 14:47:02.548895 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1511 14:47:02.548949 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 14:47:02.549002 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 14:47:02.549055 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 14:47:02.549108 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 14:47:02.549161 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 14:47:02.549219 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 14:47:02.549272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 14:47:02.549325 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 14:47:02.549378 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 14:47:02.549431 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 14:47:02.549487 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 14:47:02.549542 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 14:47:02.549596 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 14:47:02.549649 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 14:47:02.549701 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 14:47:02.549754 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1527 14:47:02.549813 Total UI for P1: 0, mck2ui 16
1528 14:47:02.549868 best dqsien dly found for B0: ( 0, 14, 2)
1529 14:47:02.549921 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 14:47:02.549974 Total UI for P1: 0, mck2ui 16
1531 14:47:02.550028 best dqsien dly found for B1: ( 0, 14, 4)
1532 14:47:02.550103 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1533 14:47:02.550205 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1534 14:47:02.550262
1535 14:47:02.550315 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1536 14:47:02.550373 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1537 14:47:02.550620 [Gating] SW calibration Done
1538 14:47:02.550685 ==
1539 14:47:02.550740 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 14:47:02.550794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 14:47:02.550848 ==
1542 14:47:02.550903 RX Vref Scan: 0
1543 14:47:02.550962
1544 14:47:02.551014 RX Vref 0 -> 0, step: 1
1545 14:47:02.551068
1546 14:47:02.551120 RX Delay -130 -> 252, step: 16
1547 14:47:02.551173 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1548 14:47:02.551232 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1549 14:47:02.551287 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1550 14:47:02.551340 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1551 14:47:02.551393 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1552 14:47:02.551446 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1553 14:47:02.551502 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1554 14:47:02.551557 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1555 14:47:02.551610 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1556 14:47:02.551663 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1557 14:47:02.551716 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1558 14:47:02.551769 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1559 14:47:02.551840 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1560 14:47:02.551923 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1561 14:47:02.552007 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1562 14:47:02.552091 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1563 14:47:02.552174 ==
1564 14:47:02.552257 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 14:47:02.552339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 14:47:02.552425 ==
1567 14:47:02.552507 DQS Delay:
1568 14:47:02.552588 DQS0 = 0, DQS1 = 0
1569 14:47:02.552672 DQM Delay:
1570 14:47:02.552788 DQM0 = 89, DQM1 = 80
1571 14:47:02.552873 DQ Delay:
1572 14:47:02.552931 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1573 14:47:02.552989 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1574 14:47:02.553044 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1575 14:47:02.553098 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =93
1576 14:47:02.553151
1577 14:47:02.553203
1578 14:47:02.553260 ==
1579 14:47:02.553314 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 14:47:02.553368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 14:47:02.553422 ==
1582 14:47:02.553475
1583 14:47:02.553532
1584 14:47:02.553585 TX Vref Scan disable
1585 14:47:02.553637 == TX Byte 0 ==
1586 14:47:02.553690 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1587 14:47:02.553743 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1588 14:47:02.553802 == TX Byte 1 ==
1589 14:47:02.553855 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1590 14:47:02.553908 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1591 14:47:02.553960 ==
1592 14:47:02.554014 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 14:47:02.554088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 14:47:02.554207 ==
1595 14:47:02.554263 TX Vref=22, minBit 13, minWin=26, winSum=444
1596 14:47:02.554318 TX Vref=24, minBit 8, minWin=27, winSum=451
1597 14:47:02.554377 TX Vref=26, minBit 9, minWin=27, winSum=450
1598 14:47:02.554431 TX Vref=28, minBit 9, minWin=27, winSum=454
1599 14:47:02.554484 TX Vref=30, minBit 11, minWin=27, winSum=450
1600 14:47:02.554537 TX Vref=32, minBit 9, minWin=27, winSum=447
1601 14:47:02.554590 [TxChooseVref] Worse bit 9, Min win 27, Win sum 454, Final Vref 28
1602 14:47:02.554652
1603 14:47:02.554705 Final TX Range 1 Vref 28
1604 14:47:02.554758
1605 14:47:02.554810 ==
1606 14:47:02.554863 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 14:47:02.554922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 14:47:02.554977 ==
1609 14:47:02.555030
1610 14:47:02.555121
1611 14:47:02.555177 TX Vref Scan disable
1612 14:47:02.555238 == TX Byte 0 ==
1613 14:47:02.555292 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1614 14:47:02.555346 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1615 14:47:02.555399 == TX Byte 1 ==
1616 14:47:02.555452 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1617 14:47:02.555512 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1618 14:47:02.555567
1619 14:47:02.555620 [DATLAT]
1620 14:47:02.555673 Freq=800, CH1 RK0
1621 14:47:02.555727
1622 14:47:02.555780 DATLAT Default: 0xa
1623 14:47:02.555838 0, 0xFFFF, sum = 0
1624 14:47:02.555892 1, 0xFFFF, sum = 0
1625 14:47:02.555947 2, 0xFFFF, sum = 0
1626 14:47:02.556000 3, 0xFFFF, sum = 0
1627 14:47:02.556055 4, 0xFFFF, sum = 0
1628 14:47:02.556115 5, 0xFFFF, sum = 0
1629 14:47:02.556169 6, 0xFFFF, sum = 0
1630 14:47:02.556226 7, 0xFFFF, sum = 0
1631 14:47:02.556280 8, 0xFFFF, sum = 0
1632 14:47:02.556333 9, 0x0, sum = 1
1633 14:47:02.556391 10, 0x0, sum = 2
1634 14:47:02.556446 11, 0x0, sum = 3
1635 14:47:02.556499 12, 0x0, sum = 4
1636 14:47:02.556553 best_step = 10
1637 14:47:02.556605
1638 14:47:02.556657 ==
1639 14:47:02.556717 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 14:47:02.556770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 14:47:02.556823 ==
1642 14:47:02.556875 RX Vref Scan: 1
1643 14:47:02.556928
1644 14:47:02.556985 Set Vref Range= 32 -> 127
1645 14:47:02.557038
1646 14:47:02.557090 RX Vref 32 -> 127, step: 1
1647 14:47:02.557144
1648 14:47:02.557196 RX Delay -95 -> 252, step: 8
1649 14:47:02.557249
1650 14:47:02.557307 Set Vref, RX VrefLevel [Byte0]: 32
1651 14:47:02.557360 [Byte1]: 32
1652 14:47:02.557413
1653 14:47:02.557466 Set Vref, RX VrefLevel [Byte0]: 33
1654 14:47:02.557518 [Byte1]: 33
1655 14:47:02.557578
1656 14:47:02.557661 Set Vref, RX VrefLevel [Byte0]: 34
1657 14:47:02.557743 [Byte1]: 34
1658 14:47:02.557825
1659 14:47:02.557910 Set Vref, RX VrefLevel [Byte0]: 35
1660 14:47:02.557993 [Byte1]: 35
1661 14:47:02.558074
1662 14:47:02.558159 Set Vref, RX VrefLevel [Byte0]: 36
1663 14:47:02.558288 [Byte1]: 36
1664 14:47:02.558370
1665 14:47:02.558455 Set Vref, RX VrefLevel [Byte0]: 37
1666 14:47:02.558537 [Byte1]: 37
1667 14:47:02.558618
1668 14:47:02.558699 Set Vref, RX VrefLevel [Byte0]: 38
1669 14:47:02.558754 [Byte1]: 38
1670 14:47:02.558807
1671 14:47:02.558860 Set Vref, RX VrefLevel [Byte0]: 39
1672 14:47:02.558913 [Byte1]: 39
1673 14:47:02.558965
1674 14:47:02.559023 Set Vref, RX VrefLevel [Byte0]: 40
1675 14:47:02.559075 [Byte1]: 40
1676 14:47:02.559128
1677 14:47:02.559180 Set Vref, RX VrefLevel [Byte0]: 41
1678 14:47:02.559234 [Byte1]: 41
1679 14:47:02.559291
1680 14:47:02.559344 Set Vref, RX VrefLevel [Byte0]: 42
1681 14:47:02.559397 [Byte1]: 42
1682 14:47:02.559450
1683 14:47:02.559502 Set Vref, RX VrefLevel [Byte0]: 43
1684 14:47:02.559555 [Byte1]: 43
1685 14:47:02.559612
1686 14:47:02.559665 Set Vref, RX VrefLevel [Byte0]: 44
1687 14:47:02.559718 [Byte1]: 44
1688 14:47:02.559771
1689 14:47:02.559823 Set Vref, RX VrefLevel [Byte0]: 45
1690 14:47:02.559880 [Byte1]: 45
1691 14:47:02.559935
1692 14:47:02.559988 Set Vref, RX VrefLevel [Byte0]: 46
1693 14:47:02.560040 [Byte1]: 46
1694 14:47:02.560093
1695 14:47:02.560341 Set Vref, RX VrefLevel [Byte0]: 47
1696 14:47:02.560429 [Byte1]: 47
1697 14:47:02.560502
1698 14:47:02.560557 Set Vref, RX VrefLevel [Byte0]: 48
1699 14:47:02.560611 [Byte1]: 48
1700 14:47:02.560665
1701 14:47:02.560718 Set Vref, RX VrefLevel [Byte0]: 49
1702 14:47:02.560778 [Byte1]: 49
1703 14:47:02.560833
1704 14:47:02.560908 Set Vref, RX VrefLevel [Byte0]: 50
1705 14:47:02.560978 [Byte1]: 50
1706 14:47:02.561035
1707 14:47:02.561092 Set Vref, RX VrefLevel [Byte0]: 51
1708 14:47:02.561145 [Byte1]: 51
1709 14:47:02.561198
1710 14:47:02.561251 Set Vref, RX VrefLevel [Byte0]: 52
1711 14:47:02.561304 [Byte1]: 52
1712 14:47:02.561364
1713 14:47:02.561417 Set Vref, RX VrefLevel [Byte0]: 53
1714 14:47:02.561470 [Byte1]: 53
1715 14:47:02.561523
1716 14:47:02.561576 Set Vref, RX VrefLevel [Byte0]: 54
1717 14:47:02.561632 [Byte1]: 54
1718 14:47:02.561686
1719 14:47:02.561739 Set Vref, RX VrefLevel [Byte0]: 55
1720 14:47:02.561791 [Byte1]: 55
1721 14:47:02.561844
1722 14:47:02.561896 Set Vref, RX VrefLevel [Byte0]: 56
1723 14:47:02.561956 [Byte1]: 56
1724 14:47:02.562009
1725 14:47:02.562062 Set Vref, RX VrefLevel [Byte0]: 57
1726 14:47:02.562115 [Byte1]: 57
1727 14:47:02.562175
1728 14:47:02.562269 Set Vref, RX VrefLevel [Byte0]: 58
1729 14:47:02.562322 [Byte1]: 58
1730 14:47:02.562376
1731 14:47:02.562428 Set Vref, RX VrefLevel [Byte0]: 59
1732 14:47:02.562486 [Byte1]: 59
1733 14:47:02.562541
1734 14:47:02.562594 Set Vref, RX VrefLevel [Byte0]: 60
1735 14:47:02.562646 [Byte1]: 60
1736 14:47:02.562699
1737 14:47:02.562751 Set Vref, RX VrefLevel [Byte0]: 61
1738 14:47:02.562809 [Byte1]: 61
1739 14:47:02.562862
1740 14:47:02.562915 Set Vref, RX VrefLevel [Byte0]: 62
1741 14:47:02.562967 [Byte1]: 62
1742 14:47:02.563020
1743 14:47:02.563077 Set Vref, RX VrefLevel [Byte0]: 63
1744 14:47:02.563130 [Byte1]: 63
1745 14:47:02.563183
1746 14:47:02.563235 Set Vref, RX VrefLevel [Byte0]: 64
1747 14:47:02.563288 [Byte1]: 64
1748 14:47:02.563341
1749 14:47:02.563398 Set Vref, RX VrefLevel [Byte0]: 65
1750 14:47:02.563452 [Byte1]: 65
1751 14:47:02.563505
1752 14:47:02.563557 Set Vref, RX VrefLevel [Byte0]: 66
1753 14:47:02.563610 [Byte1]: 66
1754 14:47:02.563669
1755 14:47:02.563722 Set Vref, RX VrefLevel [Byte0]: 67
1756 14:47:02.563775 [Byte1]: 67
1757 14:47:02.563829
1758 14:47:02.563881 Set Vref, RX VrefLevel [Byte0]: 68
1759 14:47:02.563938 [Byte1]: 68
1760 14:47:02.563992
1761 14:47:02.564045 Set Vref, RX VrefLevel [Byte0]: 69
1762 14:47:02.564098 [Byte1]: 69
1763 14:47:02.564152
1764 14:47:02.564210 Set Vref, RX VrefLevel [Byte0]: 70
1765 14:47:02.564264 [Byte1]: 70
1766 14:47:02.564317
1767 14:47:02.564369 Set Vref, RX VrefLevel [Byte0]: 71
1768 14:47:02.564422 [Byte1]: 71
1769 14:47:02.564474
1770 14:47:02.564532 Set Vref, RX VrefLevel [Byte0]: 72
1771 14:47:02.564586 [Byte1]: 72
1772 14:47:02.564640
1773 14:47:02.564692 Set Vref, RX VrefLevel [Byte0]: 73
1774 14:47:02.564746 [Byte1]: 73
1775 14:47:02.564819
1776 14:47:02.564902 Set Vref, RX VrefLevel [Byte0]: 74
1777 14:47:02.564984 [Byte1]: 74
1778 14:47:02.565068
1779 14:47:02.565151 Set Vref, RX VrefLevel [Byte0]: 75
1780 14:47:02.565233 [Byte1]: 75
1781 14:47:02.565315
1782 14:47:02.565400 Final RX Vref Byte 0 = 55 to rank0
1783 14:47:02.565483 Final RX Vref Byte 1 = 63 to rank0
1784 14:47:02.565566 Final RX Vref Byte 0 = 55 to rank1
1785 14:47:02.565650 Final RX Vref Byte 1 = 63 to rank1==
1786 14:47:02.565707 Dram Type= 6, Freq= 0, CH_1, rank 0
1787 14:47:02.565761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 14:47:02.565814 ==
1789 14:47:02.565867 DQS Delay:
1790 14:47:02.565935 DQS0 = 0, DQS1 = 0
1791 14:47:02.566018 DQM Delay:
1792 14:47:02.566100 DQM0 = 86, DQM1 = 78
1793 14:47:02.566222 DQ Delay:
1794 14:47:02.566305 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1795 14:47:02.566387 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1796 14:47:02.566473 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1797 14:47:02.566555 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =84
1798 14:47:02.566637
1799 14:47:02.566721
1800 14:47:02.566805 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1801 14:47:02.566888 CH1 RK0: MR19=606, MR18=2D19
1802 14:47:02.566972 CH1_RK0: MR19=0x606, MR18=0x2D19, DQSOSC=398, MR23=63, INC=93, DEC=62
1803 14:47:02.567057
1804 14:47:02.567139 ----->DramcWriteLeveling(PI) begin...
1805 14:47:02.567222 ==
1806 14:47:02.567308 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 14:47:02.567391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 14:47:02.567474 ==
1809 14:47:02.567556 Write leveling (Byte 0): 25 => 25
1810 14:47:02.567642 Write leveling (Byte 1): 29 => 29
1811 14:47:02.567725 DramcWriteLeveling(PI) end<-----
1812 14:47:02.567806
1813 14:47:02.567888 ==
1814 14:47:02.567945 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 14:47:02.568000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 14:47:02.568054 ==
1817 14:47:02.568107 [Gating] SW mode calibration
1818 14:47:02.568160 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1819 14:47:02.568220 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1820 14:47:02.568273 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1821 14:47:02.568327 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1822 14:47:02.568380 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1823 14:47:02.568434 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 14:47:02.568490 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 14:47:02.568544 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 14:47:02.568597 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 14:47:02.568650 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 14:47:02.568703 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 14:47:02.568756 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 14:47:02.568814 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 14:47:02.568867 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 14:47:02.568920 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 14:47:02.568972 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 14:47:02.569220 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 14:47:02.569282 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 14:47:02.569337 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1837 14:47:02.569400 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1838 14:47:02.569454 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1839 14:47:02.569508 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 14:47:02.569561 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 14:47:02.569614 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 14:47:02.569676 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 14:47:02.569760 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 14:47:02.569843 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 14:47:02.569926 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1846 14:47:02.570012 0 9 8 | B1->B0 | 3030 2525 | 0 0 | (0 0) (1 1)
1847 14:47:02.570095 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 14:47:02.570222 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 14:47:02.570310 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 14:47:02.570394 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 14:47:02.570477 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 14:47:02.570563 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 14:47:02.570652 0 10 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1854 14:47:02.570736 0 10 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1855 14:47:02.570818 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 14:47:02.570905 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 14:47:02.570987 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 14:47:02.571070 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 14:47:02.571156 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 14:47:02.571240 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 14:47:02.571323 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 14:47:02.571406 0 11 8 | B1->B0 | 3c3c 3838 | 0 0 | (0 0) (0 0)
1863 14:47:02.571492 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 14:47:02.571575 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 14:47:02.571657 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 14:47:02.571737 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 14:47:02.571792 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 14:47:02.571846 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 14:47:02.571899 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1870 14:47:02.571952 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 14:47:02.572005 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 14:47:02.572063 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 14:47:02.572117 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 14:47:02.572170 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 14:47:02.572223 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 14:47:02.572276 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 14:47:02.572348 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 14:47:02.572431 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 14:47:02.572513 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 14:47:02.572597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 14:47:02.572683 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 14:47:02.572767 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 14:47:02.572850 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 14:47:02.572935 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 14:47:02.573018 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1886 14:47:02.573101 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1887 14:47:02.573184 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 14:47:02.573251 Total UI for P1: 0, mck2ui 16
1889 14:47:02.573305 best dqsien dly found for B0: ( 0, 14, 6)
1890 14:47:02.573359 Total UI for P1: 0, mck2ui 16
1891 14:47:02.573413 best dqsien dly found for B1: ( 0, 14, 6)
1892 14:47:02.573467 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1893 14:47:02.573524 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1894 14:47:02.573579
1895 14:47:02.573631 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1896 14:47:02.573685 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1897 14:47:02.573738 [Gating] SW calibration Done
1898 14:47:02.573791 ==
1899 14:47:02.573872 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 14:47:02.573955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 14:47:02.574037 ==
1902 14:47:02.574123 RX Vref Scan: 0
1903 14:47:02.574198
1904 14:47:02.574252 RX Vref 0 -> 0, step: 1
1905 14:47:02.574306
1906 14:47:02.574359 RX Delay -130 -> 252, step: 16
1907 14:47:02.574417 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1908 14:47:02.574471 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1909 14:47:02.574525 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1910 14:47:02.574578 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1911 14:47:02.574632 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1912 14:47:02.574718 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1913 14:47:02.574799 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1914 14:47:02.574854 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1915 14:47:02.574907 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1916 14:47:02.574960 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1917 14:47:02.575021 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1918 14:47:02.575076 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1919 14:47:02.575129 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1920 14:47:02.722660 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1921 14:47:02.722792 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1922 14:47:02.722872 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1923 14:47:02.722935 ==
1924 14:47:02.722995 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 14:47:02.723273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 14:47:02.723359 ==
1927 14:47:02.723421 DQS Delay:
1928 14:47:02.723478 DQS0 = 0, DQS1 = 0
1929 14:47:02.723536 DQM Delay:
1930 14:47:02.723613 DQM0 = 87, DQM1 = 78
1931 14:47:02.723670 DQ Delay:
1932 14:47:02.723725 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1933 14:47:02.723780 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1934 14:47:02.723855 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1935 14:47:02.723912 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1936 14:47:02.723966
1937 14:47:02.724020
1938 14:47:02.724088 ==
1939 14:47:02.724146 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 14:47:02.724199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 14:47:02.724254 ==
1942 14:47:02.724307
1943 14:47:02.724401
1944 14:47:02.724484 TX Vref Scan disable
1945 14:47:02.724568 == TX Byte 0 ==
1946 14:47:02.724661 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1947 14:47:02.724746 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1948 14:47:02.724846 == TX Byte 1 ==
1949 14:47:02.724957 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1950 14:47:02.725118 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1951 14:47:02.725223 ==
1952 14:47:02.725289 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 14:47:02.725370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 14:47:02.725541 ==
1955 14:47:02.725657 TX Vref=22, minBit 9, minWin=26, winSum=443
1956 14:47:02.725752 TX Vref=24, minBit 1, minWin=27, winSum=447
1957 14:47:02.725849 TX Vref=26, minBit 1, minWin=27, winSum=447
1958 14:47:02.725938 TX Vref=28, minBit 1, minWin=27, winSum=448
1959 14:47:02.726031 TX Vref=30, minBit 0, minWin=28, winSum=449
1960 14:47:02.726127 TX Vref=32, minBit 8, minWin=27, winSum=450
1961 14:47:02.726276 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 30
1962 14:47:02.726363
1963 14:47:02.726447 Final TX Range 1 Vref 30
1964 14:47:02.726546
1965 14:47:02.726632 ==
1966 14:47:02.726717 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 14:47:02.726810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 14:47:02.726894 ==
1969 14:47:02.726983
1970 14:47:02.727107
1971 14:47:02.727189 TX Vref Scan disable
1972 14:47:02.727282 == TX Byte 0 ==
1973 14:47:02.727367 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1974 14:47:02.727460 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1975 14:47:02.727554 == TX Byte 1 ==
1976 14:47:02.727639 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1977 14:47:02.727723 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1978 14:47:02.727809
1979 14:47:02.727891 [DATLAT]
1980 14:47:02.727975 Freq=800, CH1 RK1
1981 14:47:02.728096
1982 14:47:02.728229 DATLAT Default: 0xa
1983 14:47:02.728381 0, 0xFFFF, sum = 0
1984 14:47:02.728489 1, 0xFFFF, sum = 0
1985 14:47:02.728578 2, 0xFFFF, sum = 0
1986 14:47:02.728678 3, 0xFFFF, sum = 0
1987 14:47:02.728767 4, 0xFFFF, sum = 0
1988 14:47:02.728826 5, 0xFFFF, sum = 0
1989 14:47:02.728882 6, 0xFFFF, sum = 0
1990 14:47:02.728937 7, 0xFFFF, sum = 0
1991 14:47:02.728992 8, 0xFFFF, sum = 0
1992 14:47:02.729079 9, 0x0, sum = 1
1993 14:47:02.729184 10, 0x0, sum = 2
1994 14:47:02.729269 11, 0x0, sum = 3
1995 14:47:02.729365 12, 0x0, sum = 4
1996 14:47:02.729452 best_step = 10
1997 14:47:02.729542
1998 14:47:02.729640 ==
1999 14:47:02.729727 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 14:47:02.729811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 14:47:02.729899 ==
2002 14:47:02.729983 RX Vref Scan: 0
2003 14:47:02.730066
2004 14:47:02.730152 RX Vref 0 -> 0, step: 1
2005 14:47:02.730281
2006 14:47:02.730342 RX Delay -95 -> 252, step: 8
2007 14:47:02.730427 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2008 14:47:02.730511 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2009 14:47:02.730597 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2010 14:47:02.730681 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2011 14:47:02.730764 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2012 14:47:02.730850 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2013 14:47:02.730909 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2014 14:47:02.730963 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2015 14:47:02.731017 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2016 14:47:02.731141 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2017 14:47:02.731225 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2018 14:47:02.731309 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2019 14:47:02.731403 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2020 14:47:02.731488 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2021 14:47:02.731579 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2022 14:47:02.731670 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2023 14:47:02.731753 ==
2024 14:47:02.731847 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 14:47:02.731933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 14:47:02.732016 ==
2027 14:47:02.732110 DQS Delay:
2028 14:47:02.732194 DQS0 = 0, DQS1 = 0
2029 14:47:02.732276 DQM Delay:
2030 14:47:02.732369 DQM0 = 87, DQM1 = 78
2031 14:47:02.732452 DQ Delay:
2032 14:47:02.732535 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2033 14:47:02.732630 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2034 14:47:02.732714 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2035 14:47:02.732797 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2036 14:47:02.732890
2037 14:47:02.732973
2038 14:47:02.733060 [DQSOSCAuto] RK1, (LSB)MR18= 0x160e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2039 14:47:02.733151 CH1 RK1: MR19=606, MR18=160E
2040 14:47:02.733236 CH1_RK1: MR19=0x606, MR18=0x160E, DQSOSC=404, MR23=63, INC=90, DEC=60
2041 14:47:02.733328 [RxdqsGatingPostProcess] freq 800
2042 14:47:02.733388 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 14:47:02.733443 Pre-setting of DQS Precalculation
2044 14:47:02.733498 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 14:47:02.733552 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 14:47:02.733647 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 14:47:02.733731
2048 14:47:02.733814
2049 14:47:02.733907 [Calibration Summary] 1600 Mbps
2050 14:47:02.733990 CH 0, Rank 0
2051 14:47:02.734080 SW Impedance : PASS
2052 14:47:02.734194 DUTY Scan : NO K
2053 14:47:02.734267 ZQ Calibration : PASS
2054 14:47:02.734330 Jitter Meter : NO K
2055 14:47:02.734395 CBT Training : PASS
2056 14:47:02.734449 Write leveling : PASS
2057 14:47:02.734503 RX DQS gating : PASS
2058 14:47:02.734557 RX DQ/DQS(RDDQC) : PASS
2059 14:47:02.734632 TX DQ/DQS : PASS
2060 14:47:02.734687 RX DATLAT : PASS
2061 14:47:02.734741 RX DQ/DQS(Engine): PASS
2062 14:47:02.734795 TX OE : NO K
2063 14:47:02.734871 All Pass.
2064 14:47:02.734928
2065 14:47:02.734982 CH 0, Rank 1
2066 14:47:02.735150 SW Impedance : PASS
2067 14:47:02.735263 DUTY Scan : NO K
2068 14:47:02.735360 ZQ Calibration : PASS
2069 14:47:02.735447 Jitter Meter : NO K
2070 14:47:02.735537 CBT Training : PASS
2071 14:47:02.735706 Write leveling : PASS
2072 14:47:02.735815 RX DQS gating : PASS
2073 14:47:02.736110 RX DQ/DQS(RDDQC) : PASS
2074 14:47:02.736203 TX DQ/DQS : PASS
2075 14:47:02.736302 RX DATLAT : PASS
2076 14:47:02.736419 RX DQ/DQS(Engine): PASS
2077 14:47:02.736511 TX OE : NO K
2078 14:47:02.736600 All Pass.
2079 14:47:02.736683
2080 14:47:02.736815 CH 1, Rank 0
2081 14:47:02.736900 SW Impedance : PASS
2082 14:47:02.736983 DUTY Scan : NO K
2083 14:47:02.737109 ZQ Calibration : PASS
2084 14:47:02.737193 Jitter Meter : NO K
2085 14:47:02.737278 CBT Training : PASS
2086 14:47:02.737346 Write leveling : PASS
2087 14:47:02.737401 RX DQS gating : PASS
2088 14:47:02.737455 RX DQ/DQS(RDDQC) : PASS
2089 14:47:02.737509 TX DQ/DQS : PASS
2090 14:47:02.737584 RX DATLAT : PASS
2091 14:47:02.737639 RX DQ/DQS(Engine): PASS
2092 14:47:02.737693 TX OE : NO K
2093 14:47:02.737746 All Pass.
2094 14:47:02.737825
2095 14:47:02.737908 CH 1, Rank 1
2096 14:47:02.737990 SW Impedance : PASS
2097 14:47:02.738085 DUTY Scan : NO K
2098 14:47:02.738192 ZQ Calibration : PASS
2099 14:47:02.738264 Jitter Meter : NO K
2100 14:47:02.738340 CBT Training : PASS
2101 14:47:02.738396 Write leveling : PASS
2102 14:47:02.738450 RX DQS gating : PASS
2103 14:47:02.738503 RX DQ/DQS(RDDQC) : PASS
2104 14:47:02.738575 TX DQ/DQS : PASS
2105 14:47:02.738632 RX DATLAT : PASS
2106 14:47:02.738686 RX DQ/DQS(Engine): PASS
2107 14:47:02.738739 TX OE : NO K
2108 14:47:02.738835 All Pass.
2109 14:47:02.738975
2110 14:47:02.739099 DramC Write-DBI off
2111 14:47:02.739189 PER_BANK_REFRESH: Hybrid Mode
2112 14:47:02.739312 TX_TRACKING: ON
2113 14:47:02.739396 [GetDramInforAfterCalByMRR] Vendor 6.
2114 14:47:02.739479 [GetDramInforAfterCalByMRR] Revision 606.
2115 14:47:02.739566 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 14:47:02.739649 MR0 0x3b3b
2117 14:47:02.739732 MR8 0x5151
2118 14:47:02.739819 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 14:47:02.739902
2120 14:47:02.739984 MR0 0x3b3b
2121 14:47:02.740070 MR8 0x5151
2122 14:47:02.740153 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 14:47:02.740236
2124 14:47:02.740332 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 14:47:02.740417 [FAST_K] Save calibration result to emmc
2126 14:47:02.740501 [FAST_K] Save calibration result to emmc
2127 14:47:02.740595 dram_init: config_dvfs: 1
2128 14:47:02.740679 dramc_set_vcore_voltage set vcore to 662500
2129 14:47:02.740766 Read voltage for 1200, 2
2130 14:47:02.740856 Vio18 = 0
2131 14:47:02.740939 Vcore = 662500
2132 14:47:02.741030 Vdram = 0
2133 14:47:02.741116 Vddq = 0
2134 14:47:02.741198 Vmddr = 0
2135 14:47:02.741290 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 14:47:02.741376 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 14:47:02.741459 MEM_TYPE=3, freq_sel=15
2138 14:47:02.741552 sv_algorithm_assistance_LP4_1600
2139 14:47:02.741638 ============ PULL DRAM RESETB DOWN ============
2140 14:47:02.741722 ========== PULL DRAM RESETB DOWN end =========
2141 14:47:02.741816 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 14:47:02.741901 ===================================
2143 14:47:02.741984 LPDDR4 DRAM CONFIGURATION
2144 14:47:02.742078 ===================================
2145 14:47:02.742171 EX_ROW_EN[0] = 0x0
2146 14:47:02.742267 EX_ROW_EN[1] = 0x0
2147 14:47:02.742341 LP4Y_EN = 0x0
2148 14:47:02.742396 WORK_FSP = 0x0
2149 14:47:02.742450 WL = 0x4
2150 14:47:02.742503 RL = 0x4
2151 14:47:02.742578 BL = 0x2
2152 14:47:02.742634 RPST = 0x0
2153 14:47:02.742687 RD_PRE = 0x0
2154 14:47:02.742741 WR_PRE = 0x1
2155 14:47:02.742809 WR_PST = 0x0
2156 14:47:02.742865 DBI_WR = 0x0
2157 14:47:02.742920 DBI_RD = 0x0
2158 14:47:02.742973 OTF = 0x1
2159 14:47:02.743028 ===================================
2160 14:47:02.743123 ===================================
2161 14:47:02.743207 ANA top config
2162 14:47:02.743292 ===================================
2163 14:47:02.743384 DLL_ASYNC_EN = 0
2164 14:47:02.743467 ALL_SLAVE_EN = 0
2165 14:47:02.743557 NEW_RANK_MODE = 1
2166 14:47:02.743645 DLL_IDLE_MODE = 1
2167 14:47:02.743728 LP45_APHY_COMB_EN = 1
2168 14:47:02.743828 TX_ODT_DIS = 1
2169 14:47:02.743926 NEW_8X_MODE = 1
2170 14:47:02.744096 ===================================
2171 14:47:02.744205 ===================================
2172 14:47:02.744298 data_rate = 2400
2173 14:47:02.744388 CKR = 1
2174 14:47:02.744477 DQ_P2S_RATIO = 8
2175 14:47:02.744563 ===================================
2176 14:47:02.744657 CA_P2S_RATIO = 8
2177 14:47:02.744799 DQ_CA_OPEN = 0
2178 14:47:02.744934 DQ_SEMI_OPEN = 0
2179 14:47:02.745035 CA_SEMI_OPEN = 0
2180 14:47:02.745130 CA_FULL_RATE = 0
2181 14:47:02.745219 DQ_CKDIV4_EN = 0
2182 14:47:02.745304 CA_CKDIV4_EN = 0
2183 14:47:02.745388 CA_PREDIV_EN = 0
2184 14:47:02.745474 PH8_DLY = 17
2185 14:47:02.745563 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 14:47:02.745647 DQ_AAMCK_DIV = 4
2187 14:47:02.745734 CA_AAMCK_DIV = 4
2188 14:47:02.745817 CA_ADMCK_DIV = 4
2189 14:47:02.745900 DQ_TRACK_CA_EN = 0
2190 14:47:02.745986 CA_PICK = 1200
2191 14:47:02.746070 CA_MCKIO = 1200
2192 14:47:02.746153 MCKIO_SEMI = 0
2193 14:47:02.746276 PLL_FREQ = 2366
2194 14:47:02.746359 DQ_UI_PI_RATIO = 32
2195 14:47:02.746442 CA_UI_PI_RATIO = 0
2196 14:47:02.746529 ===================================
2197 14:47:02.746612 ===================================
2198 14:47:02.746696 memory_type:LPDDR4
2199 14:47:02.746782 GP_NUM : 10
2200 14:47:02.746864 SRAM_EN : 1
2201 14:47:02.746947 MD32_EN : 0
2202 14:47:02.747046 ===================================
2203 14:47:02.747141 [ANA_INIT] >>>>>>>>>>>>>>
2204 14:47:02.747237 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 14:47:02.747343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 14:47:02.747438 ===================================
2207 14:47:02.747580 data_rate = 2400,PCW = 0X5b00
2208 14:47:02.747714 ===================================
2209 14:47:02.747821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 14:47:02.747974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 14:47:02.748103 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 14:47:02.748206 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 14:47:02.748295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 14:47:02.748632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 14:47:02.748735 [ANA_INIT] flow start
2216 14:47:02.748823 [ANA_INIT] PLL >>>>>>>>
2217 14:47:02.748908 [ANA_INIT] PLL <<<<<<<<
2218 14:47:02.749004 [ANA_INIT] MIDPI >>>>>>>>
2219 14:47:02.749089 [ANA_INIT] MIDPI <<<<<<<<
2220 14:47:02.749172 [ANA_INIT] DLL >>>>>>>>
2221 14:47:02.749249 [ANA_INIT] DLL <<<<<<<<
2222 14:47:02.749305 [ANA_INIT] flow end
2223 14:47:02.749360 ============ LP4 DIFF to SE enter ============
2224 14:47:02.749415 ============ LP4 DIFF to SE exit ============
2225 14:47:02.749491 [ANA_INIT] <<<<<<<<<<<<<
2226 14:47:02.749548 [Flow] Enable top DCM control >>>>>
2227 14:47:02.749602 [Flow] Enable top DCM control <<<<<
2228 14:47:02.749656 Enable DLL master slave shuffle
2229 14:47:02.749736 ==============================================================
2230 14:47:02.749821 Gating Mode config
2231 14:47:02.749905 ==============================================================
2232 14:47:02.750000 Config description:
2233 14:47:02.750086 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 14:47:02.750196 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 14:47:02.750280 SELPH_MODE 0: By rank 1: By Phase
2236 14:47:02.750335 ==============================================================
2237 14:47:02.750390 GAT_TRACK_EN = 1
2238 14:47:02.750444 RX_GATING_MODE = 2
2239 14:47:02.750520 RX_GATING_TRACK_MODE = 2
2240 14:47:02.750575 SELPH_MODE = 1
2241 14:47:02.750629 PICG_EARLY_EN = 1
2242 14:47:02.750683 VALID_LAT_VALUE = 1
2243 14:47:02.750765 ==============================================================
2244 14:47:02.750850 Enter into Gating configuration >>>>
2245 14:47:02.750933 Exit from Gating configuration <<<<
2246 14:47:02.751028 Enter into DVFS_PRE_config >>>>>
2247 14:47:02.751114 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 14:47:02.751200 Exit from DVFS_PRE_config <<<<<
2249 14:47:02.751294 Enter into PICG configuration >>>>
2250 14:47:02.751394 Exit from PICG configuration <<<<
2251 14:47:02.751490 [RX_INPUT] configuration >>>>>
2252 14:47:02.751633 [RX_INPUT] configuration <<<<<
2253 14:47:02.751753 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 14:47:02.751849 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 14:47:02.751935 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 14:47:02.752020 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 14:47:02.752135 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 14:47:02.752220 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 14:47:02.752334 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 14:47:02.752418 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 14:47:02.752502 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 14:47:02.752597 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 14:47:02.752717 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 14:47:02.752963 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 14:47:02.753071 ===================================
2266 14:47:02.753164 LPDDR4 DRAM CONFIGURATION
2267 14:47:02.753255 ===================================
2268 14:47:02.753375 EX_ROW_EN[0] = 0x0
2269 14:47:02.753460 EX_ROW_EN[1] = 0x0
2270 14:47:02.753542 LP4Y_EN = 0x0
2271 14:47:02.753619 WORK_FSP = 0x0
2272 14:47:02.753674 WL = 0x4
2273 14:47:02.753729 RL = 0x4
2274 14:47:02.753783 BL = 0x2
2275 14:47:02.753889 RPST = 0x0
2276 14:47:02.753972 RD_PRE = 0x0
2277 14:47:02.754070 WR_PRE = 0x1
2278 14:47:02.754158 WR_PST = 0x0
2279 14:47:02.754244 DBI_WR = 0x0
2280 14:47:02.754298 DBI_RD = 0x0
2281 14:47:02.754357 OTF = 0x1
2282 14:47:02.754442 ===================================
2283 14:47:02.754525 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 14:47:02.754611 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 14:47:02.754696 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 14:47:02.754779 ===================================
2287 14:47:02.754864 LPDDR4 DRAM CONFIGURATION
2288 14:47:02.754948 ===================================
2289 14:47:02.755031 EX_ROW_EN[0] = 0x10
2290 14:47:02.755116 EX_ROW_EN[1] = 0x0
2291 14:47:02.755199 LP4Y_EN = 0x0
2292 14:47:02.755282 WORK_FSP = 0x0
2293 14:47:02.755367 WL = 0x4
2294 14:47:02.755449 RL = 0x4
2295 14:47:02.755531 BL = 0x2
2296 14:47:02.755615 RPST = 0x0
2297 14:47:02.755698 RD_PRE = 0x0
2298 14:47:02.755779 WR_PRE = 0x1
2299 14:47:02.755864 WR_PST = 0x0
2300 14:47:02.755946 DBI_WR = 0x0
2301 14:47:02.756028 DBI_RD = 0x0
2302 14:47:02.756112 OTF = 0x1
2303 14:47:02.756195 ===================================
2304 14:47:02.756279 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 14:47:02.756363 ==
2306 14:47:02.756447 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 14:47:02.756529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 14:47:02.756622 ==
2309 14:47:02.756706 [Duty_Offset_Calibration]
2310 14:47:02.756864 B0:1 B1:-1 CA:0
2311 14:47:02.756986
2312 14:47:02.757085 [DutyScan_Calibration_Flow] k_type=0
2313 14:47:02.757175
2314 14:47:02.757239 ==CLK 0==
2315 14:47:02.757298 Final CLK duty delay cell = 0
2316 14:47:02.757353 [0] MAX Duty = 5094%(X100), DQS PI = 16
2317 14:47:02.757407 [0] MIN Duty = 4875%(X100), DQS PI = 8
2318 14:47:02.757461 [0] AVG Duty = 4984%(X100)
2319 14:47:02.757514
2320 14:47:02.757584 CH0 CLK Duty spec in!! Max-Min= 219%
2321 14:47:02.757667 [DutyScan_Calibration_Flow] ====Done====
2322 14:47:02.757749
2323 14:47:02.757835 [DutyScan_Calibration_Flow] k_type=1
2324 14:47:02.757917
2325 14:47:02.757999 ==DQS 0 ==
2326 14:47:02.758085 Final DQS duty delay cell = -4
2327 14:47:02.758174 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2328 14:47:02.758295 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2329 14:47:02.758379 [-4] AVG Duty = 4968%(X100)
2330 14:47:02.758460
2331 14:47:02.758544 ==DQS 1 ==
2332 14:47:02.758628 Final DQS duty delay cell = 0
2333 14:47:02.758711 [0] MAX Duty = 5125%(X100), DQS PI = 54
2334 14:47:02.758996 [0] MIN Duty = 5000%(X100), DQS PI = 20
2335 14:47:02.759087 [0] AVG Duty = 5062%(X100)
2336 14:47:02.759170
2337 14:47:02.759255 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2338 14:47:02.759342
2339 14:47:02.759425 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2340 14:47:02.759508 [DutyScan_Calibration_Flow] ====Done====
2341 14:47:02.759594
2342 14:47:02.759677 [DutyScan_Calibration_Flow] k_type=3
2343 14:47:02.759760
2344 14:47:02.759845 ==DQM 0 ==
2345 14:47:02.759928 Final DQM duty delay cell = 0
2346 14:47:02.760012 [0] MAX Duty = 5062%(X100), DQS PI = 20
2347 14:47:02.760099 [0] MIN Duty = 4907%(X100), DQS PI = 6
2348 14:47:02.760182 [0] AVG Duty = 4984%(X100)
2349 14:47:02.760264
2350 14:47:02.760349 ==DQM 1 ==
2351 14:47:02.760436 Final DQM duty delay cell = 4
2352 14:47:02.760524 [4] MAX Duty = 5187%(X100), DQS PI = 14
2353 14:47:02.760608 [4] MIN Duty = 5000%(X100), DQS PI = 22
2354 14:47:02.760691 [4] AVG Duty = 5093%(X100)
2355 14:47:02.760776
2356 14:47:02.760859 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2357 14:47:02.760941
2358 14:47:02.761027 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2359 14:47:02.761110 [DutyScan_Calibration_Flow] ====Done====
2360 14:47:02.761192
2361 14:47:02.761268 [DutyScan_Calibration_Flow] k_type=2
2362 14:47:02.761323
2363 14:47:02.761376 ==DQ 0 ==
2364 14:47:02.761429 Final DQ duty delay cell = -4
2365 14:47:02.761483 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2366 14:47:02.761541 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2367 14:47:02.761595 [-4] AVG Duty = 4953%(X100)
2368 14:47:02.761647
2369 14:47:02.761700 ==DQ 1 ==
2370 14:47:02.761762 Final DQ duty delay cell = -4
2371 14:47:02.761845 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2372 14:47:02.761928 [-4] MIN Duty = 4876%(X100), DQS PI = 40
2373 14:47:02.762013 [-4] AVG Duty = 4922%(X100)
2374 14:47:02.762095
2375 14:47:02.762200 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2376 14:47:02.762277
2377 14:47:02.762331 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2378 14:47:02.762386 [DutyScan_Calibration_Flow] ====Done====
2379 14:47:02.762439 ==
2380 14:47:02.762493 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 14:47:02.762553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 14:47:02.762607 ==
2383 14:47:02.762660 [Duty_Offset_Calibration]
2384 14:47:02.762714 B0:-1 B1:1 CA:1
2385 14:47:02.762771
2386 14:47:02.762825 [DutyScan_Calibration_Flow] k_type=0
2387 14:47:02.762878
2388 14:47:02.762930 ==CLK 0==
2389 14:47:02.762983 Final CLK duty delay cell = 0
2390 14:47:02.763043 [0] MAX Duty = 5156%(X100), DQS PI = 4
2391 14:47:02.763097 [0] MIN Duty = 5000%(X100), DQS PI = 28
2392 14:47:02.763150 [0] AVG Duty = 5078%(X100)
2393 14:47:02.763202
2394 14:47:02.763259 CH1 CLK Duty spec in!! Max-Min= 156%
2395 14:47:02.763343 [DutyScan_Calibration_Flow] ====Done====
2396 14:47:02.763425
2397 14:47:02.763508 [DutyScan_Calibration_Flow] k_type=1
2398 14:47:02.763592
2399 14:47:02.763674 ==DQS 0 ==
2400 14:47:02.763758 Final DQS duty delay cell = 0
2401 14:47:02.763842 [0] MAX Duty = 5125%(X100), DQS PI = 18
2402 14:47:02.763925 [0] MIN Duty = 4875%(X100), DQS PI = 38
2403 14:47:02.764009 [0] AVG Duty = 5000%(X100)
2404 14:47:02.764092
2405 14:47:02.764173 ==DQS 1 ==
2406 14:47:02.764256 Final DQS duty delay cell = 0
2407 14:47:02.764342 [0] MAX Duty = 5062%(X100), DQS PI = 0
2408 14:47:02.764425 [0] MIN Duty = 4969%(X100), DQS PI = 26
2409 14:47:02.764512 [0] AVG Duty = 5015%(X100)
2410 14:47:02.764659
2411 14:47:02.764782 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2412 14:47:02.764878
2413 14:47:02.765008 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2414 14:47:02.765096 [DutyScan_Calibration_Flow] ====Done====
2415 14:47:02.765180
2416 14:47:02.765266 [DutyScan_Calibration_Flow] k_type=3
2417 14:47:02.765352
2418 14:47:02.765435 ==DQM 0 ==
2419 14:47:02.765518 Final DQM duty delay cell = 0
2420 14:47:02.765605 [0] MAX Duty = 5187%(X100), DQS PI = 2
2421 14:47:02.765689 [0] MIN Duty = 5000%(X100), DQS PI = 40
2422 14:47:02.765842 [0] AVG Duty = 5093%(X100)
2423 14:47:02.765961
2424 14:47:02.766054 ==DQM 1 ==
2425 14:47:02.766143 Final DQM duty delay cell = 0
2426 14:47:02.766269 [0] MAX Duty = 5187%(X100), DQS PI = 36
2427 14:47:02.766357 [0] MIN Duty = 4969%(X100), DQS PI = 4
2428 14:47:02.766441 [0] AVG Duty = 5078%(X100)
2429 14:47:02.766523
2430 14:47:02.766605 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2431 14:47:02.766691
2432 14:47:02.766773 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2433 14:47:02.766856 [DutyScan_Calibration_Flow] ====Done====
2434 14:47:02.766941
2435 14:47:02.767023 [DutyScan_Calibration_Flow] k_type=2
2436 14:47:02.767105
2437 14:47:02.767190 ==DQ 0 ==
2438 14:47:02.767273 Final DQ duty delay cell = 0
2439 14:47:02.767356 [0] MAX Duty = 5156%(X100), DQS PI = 0
2440 14:47:02.767442 [0] MIN Duty = 4875%(X100), DQS PI = 40
2441 14:47:02.767525 [0] AVG Duty = 5015%(X100)
2442 14:47:02.767606
2443 14:47:02.767691 ==DQ 1 ==
2444 14:47:02.767773 Final DQ duty delay cell = 0
2445 14:47:02.767856 [0] MAX Duty = 5124%(X100), DQS PI = 42
2446 14:47:02.767942 [0] MIN Duty = 4969%(X100), DQS PI = 0
2447 14:47:02.768024 [0] AVG Duty = 5046%(X100)
2448 14:47:02.768106
2449 14:47:02.768191 CH1 DQ 0 Duty spec in!! Max-Min= 281%
2450 14:47:02.768273
2451 14:47:02.768357 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2452 14:47:02.768441 [DutyScan_Calibration_Flow] ====Done====
2453 14:47:02.768523 nWR fixed to 30
2454 14:47:02.768608 [ModeRegInit_LP4] CH0 RK0
2455 14:47:02.768691 [ModeRegInit_LP4] CH0 RK1
2456 14:47:02.768773 [ModeRegInit_LP4] CH1 RK0
2457 14:47:02.768857 [ModeRegInit_LP4] CH1 RK1
2458 14:47:02.768947 match AC timing 7
2459 14:47:02.769070 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 14:47:02.769169 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 14:47:02.769254 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 14:47:02.769339 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 14:47:02.769402 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 14:47:02.769458 ==
2465 14:47:02.769512 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 14:47:02.769566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 14:47:02.769620 ==
2468 14:47:02.769688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 14:47:02.769773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2470 14:47:02.769856 [CA 0] Center 39 (9~70) winsize 62
2471 14:47:02.769942 [CA 1] Center 39 (9~70) winsize 62
2472 14:47:02.770025 [CA 2] Center 35 (5~66) winsize 62
2473 14:47:02.770108 [CA 3] Center 35 (5~65) winsize 61
2474 14:47:02.770238 [CA 4] Center 33 (3~64) winsize 62
2475 14:47:02.770294 [CA 5] Center 33 (4~63) winsize 60
2476 14:47:02.770348
2477 14:47:02.770405 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 14:47:02.770462
2479 14:47:02.770515 [CATrainingPosCal] consider 1 rank data
2480 14:47:02.770569 u2DelayCellTimex100 = 270/100 ps
2481 14:47:02.770622 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2482 14:47:02.770676 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2483 14:47:02.770737 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 14:47:02.770988 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2485 14:47:02.771066 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2486 14:47:02.771122 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2487 14:47:02.771177
2488 14:47:02.771231 CA PerBit enable=1, Macro0, CA PI delay=33
2489 14:47:02.771319
2490 14:47:02.771403 [CBTSetCACLKResult] CA Dly = 33
2491 14:47:02.771486 CS Dly: 8 (0~39)
2492 14:47:02.771579 ==
2493 14:47:02.771663 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 14:47:02.771747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 14:47:02.771841 ==
2496 14:47:02.771925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 14:47:02.772010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2498 14:47:02.772104 [CA 0] Center 39 (9~70) winsize 62
2499 14:47:02.772187 [CA 1] Center 39 (9~70) winsize 62
2500 14:47:02.772275 [CA 2] Center 35 (5~66) winsize 62
2501 14:47:02.772364 [CA 3] Center 34 (4~65) winsize 62
2502 14:47:02.772446 [CA 4] Center 33 (3~64) winsize 62
2503 14:47:02.772539 [CA 5] Center 33 (3~63) winsize 61
2504 14:47:02.772623
2505 14:47:02.772706 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2506 14:47:02.772797
2507 14:47:02.772881 [CATrainingPosCal] consider 2 rank data
2508 14:47:02.772964 u2DelayCellTimex100 = 270/100 ps
2509 14:47:02.773057 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2510 14:47:02.773141 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2511 14:47:02.773225 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2512 14:47:02.773355 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2513 14:47:02.773439 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2514 14:47:02.773521 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2515 14:47:02.773614
2516 14:47:02.773697 CA PerBit enable=1, Macro0, CA PI delay=33
2517 14:47:02.773779
2518 14:47:02.773872 [CBTSetCACLKResult] CA Dly = 33
2519 14:47:02.773955 CS Dly: 9 (0~41)
2520 14:47:02.774037
2521 14:47:02.774130 ----->DramcWriteLeveling(PI) begin...
2522 14:47:02.774245 ==
2523 14:47:02.774300 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 14:47:02.774375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 14:47:02.774430 ==
2526 14:47:02.774483 Write leveling (Byte 0): 30 => 30
2527 14:47:02.774537 Write leveling (Byte 1): 29 => 29
2528 14:47:02.774613 DramcWriteLeveling(PI) end<-----
2529 14:47:02.774670
2530 14:47:02.774723 ==
2531 14:47:02.774777 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 14:47:02.774843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 14:47:02.774901 ==
2534 14:47:02.774955 [Gating] SW mode calibration
2535 14:47:02.775009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 14:47:02.775063 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 14:47:02.775138 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2538 14:47:02.775194 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2539 14:47:02.775247 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 14:47:02.775300 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 14:47:02.775377 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 14:47:02.775462 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 14:47:02.775546 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2544 14:47:02.775640 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2545 14:47:02.775724 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2546 14:47:02.775807 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 14:47:02.775901 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 14:47:02.775985 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 14:47:02.776068 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 14:47:02.776162 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 14:47:02.776246 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 14:47:02.776333 1 0 28 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
2553 14:47:02.776422 1 1 0 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
2554 14:47:02.776506 1 1 4 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
2555 14:47:02.776598 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 14:47:02.776683 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 14:47:02.776766 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 14:47:02.776859 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 14:47:02.776944 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 14:47:02.777027 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2561 14:47:02.777120 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2562 14:47:02.777204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 14:47:02.777287 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 14:47:02.777381 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 14:47:02.777464 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 14:47:02.777547 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 14:47:02.777640 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 14:47:02.777724 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 14:47:02.777807 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 14:47:02.777901 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 14:47:02.777984 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 14:47:02.778092 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 14:47:02.778183 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 14:47:02.778253 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 14:47:02.778313 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 14:47:02.778379 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 14:47:02.778434 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2578 14:47:02.778487 Total UI for P1: 0, mck2ui 16
2579 14:47:02.778542 best dqsien dly found for B0: ( 1, 3, 28)
2580 14:47:02.778615 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 14:47:02.778670 Total UI for P1: 0, mck2ui 16
2582 14:47:02.778724 best dqsien dly found for B1: ( 1, 4, 0)
2583 14:47:02.778782 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2584 14:47:02.778856 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2585 14:47:02.778916
2586 14:47:02.779001 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2587 14:47:02.779095 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2588 14:47:02.779377 [Gating] SW calibration Done
2589 14:47:02.779470 ==
2590 14:47:02.779566 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 14:47:02.779651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 14:47:02.779734 ==
2593 14:47:02.779828 RX Vref Scan: 0
2594 14:47:02.779911
2595 14:47:02.779998 RX Vref 0 -> 0, step: 1
2596 14:47:02.780087
2597 14:47:02.780170 RX Delay -40 -> 252, step: 8
2598 14:47:02.780262 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2599 14:47:02.780348 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2600 14:47:02.780432 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2601 14:47:02.780524 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2602 14:47:02.780609 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2603 14:47:02.780692 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2604 14:47:02.780784 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2605 14:47:02.780869 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2606 14:47:02.780952 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2607 14:47:02.781044 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2608 14:47:02.781193 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2609 14:47:02.781271 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2610 14:47:02.781326 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2611 14:47:02.781380 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2612 14:47:02.781433 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2613 14:47:02.781507 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2614 14:47:02.781563 ==
2615 14:47:02.781615 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 14:47:02.781669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 14:47:02.781737 ==
2618 14:47:02.781822 DQS Delay:
2619 14:47:02.781905 DQS0 = 0, DQS1 = 0
2620 14:47:02.781997 DQM Delay:
2621 14:47:02.782081 DQM0 = 119, DQM1 = 106
2622 14:47:02.782170 DQ Delay:
2623 14:47:02.782280 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2624 14:47:02.782336 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2625 14:47:02.782390 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2626 14:47:02.782444 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2627 14:47:02.782518
2628 14:47:02.782573
2629 14:47:02.782626 ==
2630 14:47:02.782679 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 14:47:02.782754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 14:47:02.782809 ==
2633 14:47:02.782862
2634 14:47:02.782915
2635 14:47:02.782997 TX Vref Scan disable
2636 14:47:02.783080 == TX Byte 0 ==
2637 14:47:02.783163 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2638 14:47:02.783258 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2639 14:47:02.783341 == TX Byte 1 ==
2640 14:47:02.783424 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2641 14:47:02.783518 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2642 14:47:02.783601 ==
2643 14:47:02.783685 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 14:47:02.783777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 14:47:02.783860 ==
2646 14:47:02.783948 TX Vref=22, minBit 2, minWin=25, winSum=415
2647 14:47:02.784037 TX Vref=24, minBit 0, minWin=26, winSum=421
2648 14:47:02.784121 TX Vref=26, minBit 13, minWin=25, winSum=427
2649 14:47:02.784213 TX Vref=28, minBit 4, minWin=26, winSum=432
2650 14:47:02.784299 TX Vref=30, minBit 5, minWin=26, winSum=433
2651 14:47:02.784383 TX Vref=32, minBit 5, minWin=26, winSum=431
2652 14:47:02.784476 [TxChooseVref] Worse bit 5, Min win 26, Win sum 433, Final Vref 30
2653 14:47:02.784560
2654 14:47:02.784643 Final TX Range 1 Vref 30
2655 14:47:02.784736
2656 14:47:02.784820 ==
2657 14:47:02.784930 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 14:47:02.785038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 14:47:02.785122 ==
2660 14:47:02.785204
2661 14:47:02.785330
2662 14:47:02.785417 TX Vref Scan disable
2663 14:47:02.785570 == TX Byte 0 ==
2664 14:47:02.785692 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2665 14:47:02.785792 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2666 14:47:02.785885 == TX Byte 1 ==
2667 14:47:02.785974 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2668 14:47:02.786058 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2669 14:47:02.786141
2670 14:47:02.786253 [DATLAT]
2671 14:47:02.786309 Freq=1200, CH0 RK0
2672 14:47:02.786364
2673 14:47:02.786417 DATLAT Default: 0xd
2674 14:47:02.786475 0, 0xFFFF, sum = 0
2675 14:47:02.786531 1, 0xFFFF, sum = 0
2676 14:47:02.786586 2, 0xFFFF, sum = 0
2677 14:47:02.786639 3, 0xFFFF, sum = 0
2678 14:47:02.786694 4, 0xFFFF, sum = 0
2679 14:47:02.786755 5, 0xFFFF, sum = 0
2680 14:47:02.786810 6, 0xFFFF, sum = 0
2681 14:47:02.786864 7, 0xFFFF, sum = 0
2682 14:47:02.786917 8, 0xFFFF, sum = 0
2683 14:47:02.786974 9, 0xFFFF, sum = 0
2684 14:47:02.787030 10, 0xFFFF, sum = 0
2685 14:47:02.787083 11, 0xFFFF, sum = 0
2686 14:47:02.787138 12, 0x0, sum = 1
2687 14:47:02.787191 13, 0x0, sum = 2
2688 14:47:02.787276 14, 0x0, sum = 3
2689 14:47:02.787361 15, 0x0, sum = 4
2690 14:47:02.787445 best_step = 13
2691 14:47:02.787539
2692 14:47:02.787621 ==
2693 14:47:02.787705 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 14:47:02.787798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 14:47:02.787882 ==
2696 14:47:02.787974 RX Vref Scan: 1
2697 14:47:02.788058
2698 14:47:02.788140 Set Vref Range= 32 -> 127
2699 14:47:02.788233
2700 14:47:02.788317 RX Vref 32 -> 127, step: 1
2701 14:47:02.788399
2702 14:47:02.788491 RX Delay -21 -> 252, step: 4
2703 14:47:02.788574
2704 14:47:02.788656 Set Vref, RX VrefLevel [Byte0]: 32
2705 14:47:02.788749 [Byte1]: 32
2706 14:47:02.788832
2707 14:47:02.788915 Set Vref, RX VrefLevel [Byte0]: 33
2708 14:47:02.789010 [Byte1]: 33
2709 14:47:02.789093
2710 14:47:02.789176 Set Vref, RX VrefLevel [Byte0]: 34
2711 14:47:02.789247 [Byte1]: 34
2712 14:47:02.789301
2713 14:47:02.789354 Set Vref, RX VrefLevel [Byte0]: 35
2714 14:47:02.789407 [Byte1]: 35
2715 14:47:02.789482
2716 14:47:02.789535 Set Vref, RX VrefLevel [Byte0]: 36
2717 14:47:02.789589 [Byte1]: 36
2718 14:47:02.789642
2719 14:47:02.789725 Set Vref, RX VrefLevel [Byte0]: 37
2720 14:47:02.789809 [Byte1]: 37
2721 14:47:02.789890
2722 14:47:02.789984 Set Vref, RX VrefLevel [Byte0]: 38
2723 14:47:02.790068 [Byte1]: 38
2724 14:47:02.790149
2725 14:47:02.790264 Set Vref, RX VrefLevel [Byte0]: 39
2726 14:47:02.790320 [Byte1]: 39
2727 14:47:02.790373
2728 14:47:02.790426 Set Vref, RX VrefLevel [Byte0]: 40
2729 14:47:02.790497 [Byte1]: 40
2730 14:47:02.790553
2731 14:47:02.790607 Set Vref, RX VrefLevel [Byte0]: 41
2732 14:47:02.790660 [Byte1]: 41
2733 14:47:02.790720
2734 14:47:02.790783 Set Vref, RX VrefLevel [Byte0]: 42
2735 14:47:02.790836 [Byte1]: 42
2736 14:47:02.790890
2737 14:47:02.790942 Set Vref, RX VrefLevel [Byte0]: 43
2738 14:47:02.791030 [Byte1]: 43
2739 14:47:02.791113
2740 14:47:02.791195 Set Vref, RX VrefLevel [Byte0]: 44
2741 14:47:02.791288 [Byte1]: 44
2742 14:47:02.791371
2743 14:47:02.791454 Set Vref, RX VrefLevel [Byte0]: 45
2744 14:47:02.791548 [Byte1]: 45
2745 14:47:02.791630
2746 14:47:02.791909 Set Vref, RX VrefLevel [Byte0]: 46
2747 14:47:02.792008 [Byte1]: 46
2748 14:47:02.792094
2749 14:47:02.792177 Set Vref, RX VrefLevel [Byte0]: 47
2750 14:47:02.792270 [Byte1]: 47
2751 14:47:02.792391
2752 14:47:02.792499 Set Vref, RX VrefLevel [Byte0]: 48
2753 14:47:02.792605 [Byte1]: 48
2754 14:47:02.792701
2755 14:47:02.792795 Set Vref, RX VrefLevel [Byte0]: 49
2756 14:47:02.792880 [Byte1]: 49
2757 14:47:02.793061
2758 14:47:02.793145 Set Vref, RX VrefLevel [Byte0]: 50
2759 14:47:02.793228 [Byte1]: 50
2760 14:47:02.793315
2761 14:47:02.793371 Set Vref, RX VrefLevel [Byte0]: 51
2762 14:47:02.793425 [Byte1]: 51
2763 14:47:02.793478
2764 14:47:02.793541 Set Vref, RX VrefLevel [Byte0]: 52
2765 14:47:02.793602 [Byte1]: 52
2766 14:47:02.793655
2767 14:47:02.793708 Set Vref, RX VrefLevel [Byte0]: 53
2768 14:47:02.793762 [Byte1]: 53
2769 14:47:02.793850
2770 14:47:02.793933 Set Vref, RX VrefLevel [Byte0]: 54
2771 14:47:02.794015 [Byte1]: 54
2772 14:47:02.794108
2773 14:47:02.794195 Set Vref, RX VrefLevel [Byte0]: 55
2774 14:47:02.794251 [Byte1]: 55
2775 14:47:02.794322
2776 14:47:02.794379 Set Vref, RX VrefLevel [Byte0]: 56
2777 14:47:02.794433 [Byte1]: 56
2778 14:47:02.794486
2779 14:47:02.794544 Set Vref, RX VrefLevel [Byte0]: 57
2780 14:47:02.794610 [Byte1]: 57
2781 14:47:02.794664
2782 14:47:02.794717 Set Vref, RX VrefLevel [Byte0]: 58
2783 14:47:02.794771 [Byte1]: 58
2784 14:47:02.794846
2785 14:47:02.794902 Set Vref, RX VrefLevel [Byte0]: 59
2786 14:47:02.794964 [Byte1]: 59
2787 14:47:02.795019
2788 14:47:02.795101 Set Vref, RX VrefLevel [Byte0]: 60
2789 14:47:02.795185 [Byte1]: 60
2790 14:47:02.795266
2791 14:47:02.795359 Set Vref, RX VrefLevel [Byte0]: 61
2792 14:47:02.795443 [Byte1]: 61
2793 14:47:02.795525
2794 14:47:02.795617 Set Vref, RX VrefLevel [Byte0]: 62
2795 14:47:02.795701 [Byte1]: 62
2796 14:47:02.795783
2797 14:47:02.795875 Set Vref, RX VrefLevel [Byte0]: 63
2798 14:47:02.795959 [Byte1]: 63
2799 14:47:02.796041
2800 14:47:02.796133 Set Vref, RX VrefLevel [Byte0]: 64
2801 14:47:02.796217 [Byte1]: 64
2802 14:47:02.796299
2803 14:47:02.796392 Set Vref, RX VrefLevel [Byte0]: 65
2804 14:47:02.796475 [Byte1]: 65
2805 14:47:02.796559
2806 14:47:02.796649 Set Vref, RX VrefLevel [Byte0]: 66
2807 14:47:02.796732 [Byte1]: 66
2808 14:47:02.796817
2809 14:47:02.796906 Set Vref, RX VrefLevel [Byte0]: 67
2810 14:47:02.796990 [Byte1]: 67
2811 14:47:02.797078
2812 14:47:02.797164 Set Vref, RX VrefLevel [Byte0]: 68
2813 14:47:02.797247 [Byte1]: 68
2814 14:47:02.797337
2815 14:47:02.797421 Set Vref, RX VrefLevel [Byte0]: 69
2816 14:47:02.797504 [Byte1]: 69
2817 14:47:02.797595
2818 14:47:02.797679 Set Vref, RX VrefLevel [Byte0]: 70
2819 14:47:02.797762 [Byte1]: 70
2820 14:47:02.797853
2821 14:47:02.797937 Set Vref, RX VrefLevel [Byte0]: 71
2822 14:47:02.798019 [Byte1]: 71
2823 14:47:02.798111
2824 14:47:02.798242 Set Vref, RX VrefLevel [Byte0]: 72
2825 14:47:02.798312 [Byte1]: 72
2826 14:47:02.798389
2827 14:47:02.798444 Set Vref, RX VrefLevel [Byte0]: 73
2828 14:47:02.798499 [Byte1]: 73
2829 14:47:02.798552
2830 14:47:02.798625 Set Vref, RX VrefLevel [Byte0]: 74
2831 14:47:02.798681 [Byte1]: 74
2832 14:47:02.798735
2833 14:47:02.798787 Set Vref, RX VrefLevel [Byte0]: 75
2834 14:47:02.798854 [Byte1]: 75
2835 14:47:02.798911
2836 14:47:02.798964 Set Vref, RX VrefLevel [Byte0]: 76
2837 14:47:02.799018 [Byte1]: 76
2838 14:47:02.799072
2839 14:47:02.799165 Set Vref, RX VrefLevel [Byte0]: 77
2840 14:47:02.799248 [Byte1]: 77
2841 14:47:02.799332
2842 14:47:02.799422 Final RX Vref Byte 0 = 59 to rank0
2843 14:47:02.799506 Final RX Vref Byte 1 = 50 to rank0
2844 14:47:02.799596 Final RX Vref Byte 0 = 59 to rank1
2845 14:47:02.799684 Final RX Vref Byte 1 = 50 to rank1==
2846 14:47:02.799767 Dram Type= 6, Freq= 0, CH_0, rank 0
2847 14:47:02.799859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 14:47:02.799944 ==
2849 14:47:02.800026 DQS Delay:
2850 14:47:02.800118 DQS0 = 0, DQS1 = 0
2851 14:47:02.800202 DQM Delay:
2852 14:47:02.800284 DQM0 = 118, DQM1 = 107
2853 14:47:02.800376 DQ Delay:
2854 14:47:02.800460 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2855 14:47:02.800543 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2856 14:47:02.800636 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
2857 14:47:02.800720 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2858 14:47:02.800802
2859 14:47:02.800893
2860 14:47:02.800978 [DQSOSCAuto] RK0, (LSB)MR18= 0xcf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2861 14:47:02.801062 CH0 RK0: MR19=403, MR18=CF9
2862 14:47:02.801156 CH0_RK0: MR19=0x403, MR18=0xCF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2863 14:47:02.801240
2864 14:47:02.801322 ----->DramcWriteLeveling(PI) begin...
2865 14:47:02.801417 ==
2866 14:47:02.801501 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 14:47:02.801585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 14:47:02.801678 ==
2869 14:47:02.801762 Write leveling (Byte 0): 34 => 34
2870 14:47:02.801844 Write leveling (Byte 1): 31 => 31
2871 14:47:02.801938 DramcWriteLeveling(PI) end<-----
2872 14:47:02.802021
2873 14:47:02.802103 ==
2874 14:47:02.802222 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 14:47:02.802292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 14:47:02.802346 ==
2877 14:47:02.802433 [Gating] SW mode calibration
2878 14:47:02.802518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2879 14:47:02.802602 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2880 14:47:02.802695 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2881 14:47:02.802779 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2882 14:47:02.802863 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 14:47:02.802949 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 14:47:02.803005 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 14:47:02.803059 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 14:47:02.803119 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2887 14:47:02.803184 0 15 28 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
2888 14:47:02.803238 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2889 14:47:02.803486 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 14:47:02.803548 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 14:47:02.803604 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 14:47:02.803679 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 14:47:02.803735 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 14:47:02.803788 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 14:47:02.803842 1 0 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2896 14:47:02.803921 1 1 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
2897 14:47:02.804006 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 14:47:02.804089 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 14:47:02.804183 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 14:47:02.804267 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 14:47:02.804351 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 14:47:02.804446 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 14:47:02.804530 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2904 14:47:02.804613 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2905 14:47:02.804706 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 14:47:02.804790 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 14:47:02.804873 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 14:47:02.804967 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 14:47:02.805050 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 14:47:02.805134 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 14:47:02.805227 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 14:47:02.805311 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 14:47:02.805398 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 14:47:02.805488 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 14:47:02.805571 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 14:47:02.805662 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 14:47:02.805749 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 14:47:02.805832 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 14:47:02.805924 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2920 14:47:02.806009 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2921 14:47:02.806093 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 14:47:02.806224 Total UI for P1: 0, mck2ui 16
2923 14:47:02.806310 best dqsien dly found for B0: ( 1, 3, 30)
2924 14:47:02.806394 Total UI for P1: 0, mck2ui 16
2925 14:47:02.806488 best dqsien dly found for B1: ( 1, 4, 0)
2926 14:47:02.806572 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2927 14:47:02.806661 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2928 14:47:02.806748
2929 14:47:02.806831 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2930 14:47:02.806923 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2931 14:47:02.807008 [Gating] SW calibration Done
2932 14:47:02.807090 ==
2933 14:47:02.807183 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 14:47:02.807269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 14:47:02.807351 ==
2936 14:47:02.807444 RX Vref Scan: 0
2937 14:47:02.807528
2938 14:47:02.926017 RX Vref 0 -> 0, step: 1
2939 14:47:02.926169
2940 14:47:02.926303 RX Delay -40 -> 252, step: 8
2941 14:47:02.926395 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2942 14:47:02.926484 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2943 14:47:02.926575 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2944 14:47:02.926661 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2945 14:47:02.926747 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2946 14:47:02.926812 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2947 14:47:02.926868 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2948 14:47:02.926936 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2949 14:47:02.927021 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2950 14:47:02.927113 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2951 14:47:02.927205 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2952 14:47:02.927260 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2953 14:47:02.927341 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2954 14:47:02.927426 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2955 14:47:02.927510 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2956 14:47:02.927597 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2957 14:47:02.927680 ==
2958 14:47:02.927785 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 14:47:02.927877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 14:47:02.927961 ==
2961 14:47:02.928047 DQS Delay:
2962 14:47:02.928149 DQS0 = 0, DQS1 = 0
2963 14:47:02.928238 DQM Delay:
2964 14:47:02.928330 DQM0 = 117, DQM1 = 108
2965 14:47:02.928419 DQ Delay:
2966 14:47:02.928507 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
2967 14:47:02.928600 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2968 14:47:02.928689 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2969 14:47:02.928778 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2970 14:47:02.928867
2971 14:47:02.928927
2972 14:47:02.928984 ==
2973 14:47:02.929042 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 14:47:02.929139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 14:47:02.929228 ==
2976 14:47:02.929318
2977 14:47:02.929416
2978 14:47:02.929505 TX Vref Scan disable
2979 14:47:02.929604 == TX Byte 0 ==
2980 14:47:02.929695 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2981 14:47:02.929785 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2982 14:47:02.929886 == TX Byte 1 ==
2983 14:47:02.929986 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2984 14:47:02.930076 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2985 14:47:02.930174 ==
2986 14:47:02.930236 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 14:47:02.930295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 14:47:02.930353 ==
2989 14:47:02.930412 TX Vref=22, minBit 0, minWin=26, winSum=418
2990 14:47:02.930477 TX Vref=24, minBit 0, minWin=26, winSum=427
2991 14:47:02.930536 TX Vref=26, minBit 1, minWin=26, winSum=433
2992 14:47:02.930594 TX Vref=28, minBit 1, minWin=26, winSum=432
2993 14:47:02.930652 TX Vref=30, minBit 1, minWin=27, winSum=434
2994 14:47:02.930709 TX Vref=32, minBit 1, minWin=26, winSum=431
2995 14:47:02.930773 [TxChooseVref] Worse bit 1, Min win 27, Win sum 434, Final Vref 30
2996 14:47:02.930833
2997 14:47:02.930889 Final TX Range 1 Vref 30
2998 14:47:02.930947
2999 14:47:02.931003 ==
3000 14:47:02.931272 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 14:47:02.931338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 14:47:02.931406 ==
3003 14:47:02.931465
3004 14:47:02.931523
3005 14:47:02.931580 TX Vref Scan disable
3006 14:47:02.931637 == TX Byte 0 ==
3007 14:47:02.931701 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3008 14:47:02.931760 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3009 14:47:02.931818 == TX Byte 1 ==
3010 14:47:02.931874 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3011 14:47:02.931931 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3012 14:47:02.931998
3013 14:47:02.932086 [DATLAT]
3014 14:47:02.932174 Freq=1200, CH0 RK1
3015 14:47:02.932262
3016 14:47:02.932354 DATLAT Default: 0xd
3017 14:47:02.932442 0, 0xFFFF, sum = 0
3018 14:47:02.932533 1, 0xFFFF, sum = 0
3019 14:47:02.932627 2, 0xFFFF, sum = 0
3020 14:47:02.932717 3, 0xFFFF, sum = 0
3021 14:47:02.932807 4, 0xFFFF, sum = 0
3022 14:47:02.932901 5, 0xFFFF, sum = 0
3023 14:47:02.932992 6, 0xFFFF, sum = 0
3024 14:47:02.933097 7, 0xFFFF, sum = 0
3025 14:47:02.933198 8, 0xFFFF, sum = 0
3026 14:47:02.933295 9, 0xFFFF, sum = 0
3027 14:47:02.933390 10, 0xFFFF, sum = 0
3028 14:47:02.933456 11, 0xFFFF, sum = 0
3029 14:47:02.933518 12, 0x0, sum = 1
3030 14:47:02.933580 13, 0x0, sum = 2
3031 14:47:02.933642 14, 0x0, sum = 3
3032 14:47:02.933712 15, 0x0, sum = 4
3033 14:47:02.933774 best_step = 13
3034 14:47:02.933835
3035 14:47:02.933896 ==
3036 14:47:02.933958 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 14:47:02.934056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 14:47:02.934151 ==
3039 14:47:02.934228 RX Vref Scan: 0
3040 14:47:02.934295
3041 14:47:02.934357 RX Vref 0 -> 0, step: 1
3042 14:47:02.934418
3043 14:47:02.934479 RX Delay -21 -> 252, step: 4
3044 14:47:02.934541 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3045 14:47:02.934610 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3046 14:47:02.934672 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3047 14:47:02.934733 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3048 14:47:02.934795 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3049 14:47:02.934856 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3050 14:47:02.934923 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3051 14:47:02.934984 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3052 14:47:02.935046 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3053 14:47:02.935107 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3054 14:47:02.935174 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3055 14:47:02.935234 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3056 14:47:02.935295 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3057 14:47:02.935356 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3058 14:47:02.935422 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3059 14:47:02.935485 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3060 14:47:02.935547 ==
3061 14:47:02.935608 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 14:47:02.935669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 14:47:02.935740 ==
3064 14:47:02.935844 DQS Delay:
3065 14:47:02.935939 DQS0 = 0, DQS1 = 0
3066 14:47:02.936047 DQM Delay:
3067 14:47:02.936143 DQM0 = 116, DQM1 = 108
3068 14:47:02.936238 DQ Delay:
3069 14:47:02.936346 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3070 14:47:02.936443 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3071 14:47:02.936550 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3072 14:47:02.936647 DQ12 =114, DQ13 =116, DQ14 =118, DQ15 =116
3073 14:47:02.936742
3074 14:47:02.936848
3075 14:47:02.936946 [DQSOSCAuto] RK1, (LSB)MR18= 0x9e3, (MSB)MR19= 0x403, tDQSOscB0 = 422 ps tDQSOscB1 = 406 ps
3076 14:47:02.937054 CH0 RK1: MR19=403, MR18=9E3
3077 14:47:02.937153 CH0_RK1: MR19=0x403, MR18=0x9E3, DQSOSC=406, MR23=63, INC=39, DEC=26
3078 14:47:02.937249 [RxdqsGatingPostProcess] freq 1200
3079 14:47:02.937358 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3080 14:47:02.937454 best DQS0 dly(2T, 0.5T) = (0, 11)
3081 14:47:02.937560 best DQS1 dly(2T, 0.5T) = (0, 12)
3082 14:47:02.937659 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3083 14:47:02.937755 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3084 14:47:02.937863 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 14:47:02.937959 best DQS1 dly(2T, 0.5T) = (0, 12)
3086 14:47:02.938066 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 14:47:02.938170 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3088 14:47:02.938267 Pre-setting of DQS Precalculation
3089 14:47:02.938358 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3090 14:47:02.938422 ==
3091 14:47:02.938485 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 14:47:02.938563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 14:47:02.938630 ==
3094 14:47:02.938693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 14:47:02.938756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3096 14:47:02.938840 [CA 0] Center 38 (8~68) winsize 61
3097 14:47:02.938906 [CA 1] Center 37 (7~68) winsize 62
3098 14:47:02.938968 [CA 2] Center 34 (4~64) winsize 61
3099 14:47:02.939030 [CA 3] Center 33 (3~64) winsize 62
3100 14:47:02.939116 [CA 4] Center 34 (4~64) winsize 61
3101 14:47:02.939179 [CA 5] Center 33 (3~64) winsize 62
3102 14:47:02.939242
3103 14:47:02.939308 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 14:47:02.939414
3105 14:47:02.939510 [CATrainingPosCal] consider 1 rank data
3106 14:47:02.939619 u2DelayCellTimex100 = 270/100 ps
3107 14:47:02.939717 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3108 14:47:02.939815 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 14:47:02.939922 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3110 14:47:02.940018 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3111 14:47:02.940126 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 14:47:02.940224 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3113 14:47:02.940318
3114 14:47:02.940426 CA PerBit enable=1, Macro0, CA PI delay=33
3115 14:47:02.940522
3116 14:47:02.940629 [CBTSetCACLKResult] CA Dly = 33
3117 14:47:02.940726 CS Dly: 6 (0~37)
3118 14:47:02.940821 ==
3119 14:47:02.940929 Dram Type= 6, Freq= 0, CH_1, rank 1
3120 14:47:02.941038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 14:47:02.941149 ==
3122 14:47:02.941248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 14:47:02.941347 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3124 14:47:02.941432 [CA 0] Center 38 (8~68) winsize 61
3125 14:47:02.941496 [CA 1] Center 38 (8~68) winsize 61
3126 14:47:02.941559 [CA 2] Center 34 (4~65) winsize 62
3127 14:47:02.941634 [CA 3] Center 33 (3~64) winsize 62
3128 14:47:02.941702 [CA 4] Center 34 (3~65) winsize 63
3129 14:47:02.941764 [CA 5] Center 33 (3~64) winsize 62
3130 14:47:02.941826
3131 14:47:02.941908 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3132 14:47:02.942006
3133 14:47:02.942102 [CATrainingPosCal] consider 2 rank data
3134 14:47:02.942429 u2DelayCellTimex100 = 270/100 ps
3135 14:47:02.942504 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3136 14:47:02.942569 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3137 14:47:02.942637 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3138 14:47:02.942717 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3139 14:47:02.942780 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3140 14:47:02.942842 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3141 14:47:02.942919
3142 14:47:02.943019 CA PerBit enable=1, Macro0, CA PI delay=33
3143 14:47:02.943114
3144 14:47:02.943222 [CBTSetCACLKResult] CA Dly = 33
3145 14:47:02.943318 CS Dly: 7 (0~40)
3146 14:47:02.943420
3147 14:47:02.943522 ----->DramcWriteLeveling(PI) begin...
3148 14:47:02.943619 ==
3149 14:47:02.943728 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 14:47:02.943825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 14:47:02.943925 ==
3152 14:47:02.944029 Write leveling (Byte 0): 23 => 23
3153 14:47:02.944125 Write leveling (Byte 1): 28 => 28
3154 14:47:02.944233 DramcWriteLeveling(PI) end<-----
3155 14:47:02.944328
3156 14:47:02.944424 ==
3157 14:47:02.944532 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 14:47:02.944629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 14:47:02.944736 ==
3160 14:47:02.944833 [Gating] SW mode calibration
3161 14:47:02.944931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3162 14:47:02.945038 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3163 14:47:02.945135 0 15 0 | B1->B0 | 2d2d 3434 | 1 0 | (1 1) (0 0)
3164 14:47:02.945243 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 14:47:02.945341 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 14:47:02.945438 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 14:47:02.945545 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 14:47:02.945642 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 14:47:02.945753 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
3170 14:47:02.945855 0 15 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
3171 14:47:02.945954 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3172 14:47:02.946062 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 14:47:02.946159 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 14:47:02.946255 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 14:47:02.946321 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 14:47:02.946384 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 14:47:02.946446 1 0 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
3178 14:47:02.946533 1 0 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3179 14:47:02.946597 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3180 14:47:02.946659 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 14:47:02.946731 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 14:47:02.946814 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 14:47:02.946909 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 14:47:02.946980 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 14:47:02.947086 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3186 14:47:02.947183 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3187 14:47:02.947292 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 14:47:02.947389 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 14:47:02.947489 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 14:47:02.947595 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 14:47:02.947691 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 14:47:02.947800 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 14:47:02.947898 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 14:47:02.947996 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 14:47:02.948102 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 14:47:02.948199 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 14:47:02.948307 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 14:47:02.948405 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 14:47:02.948501 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 14:47:02.948610 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 14:47:02.948706 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3202 14:47:02.948814 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3203 14:47:02.948911 Total UI for P1: 0, mck2ui 16
3204 14:47:02.949009 best dqsien dly found for B0: ( 1, 3, 24)
3205 14:47:02.949117 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 14:47:02.949213 Total UI for P1: 0, mck2ui 16
3207 14:47:02.949321 best dqsien dly found for B1: ( 1, 3, 28)
3208 14:47:02.949418 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3209 14:47:02.949522 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3210 14:47:02.949598
3211 14:47:02.949661 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3212 14:47:02.949724 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3213 14:47:02.949804 [Gating] SW calibration Done
3214 14:47:02.949901 ==
3215 14:47:02.949997 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 14:47:02.950106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 14:47:02.950205 ==
3218 14:47:02.950269 RX Vref Scan: 0
3219 14:47:02.950356
3220 14:47:02.950420 RX Vref 0 -> 0, step: 1
3221 14:47:02.950483
3222 14:47:02.950551 RX Delay -40 -> 252, step: 8
3223 14:47:02.950626 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3224 14:47:02.950689 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3225 14:47:02.950751 iDelay=208, Bit 2, Center 115 (48 ~ 183) 136
3226 14:47:02.950828 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3227 14:47:02.950895 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3228 14:47:02.950957 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3229 14:47:02.951019 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3230 14:47:02.951103 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3231 14:47:02.951168 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3232 14:47:02.951230 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3233 14:47:02.951292 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3234 14:47:02.951396 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3235 14:47:02.951698 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3236 14:47:02.951802 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3237 14:47:02.951913 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3238 14:47:02.952011 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3239 14:47:02.952118 ==
3240 14:47:02.952216 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 14:47:02.952313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 14:47:02.952421 ==
3243 14:47:02.952517 DQS Delay:
3244 14:47:02.952623 DQS0 = 0, DQS1 = 0
3245 14:47:02.952721 DQM Delay:
3246 14:47:02.952816 DQM0 = 120, DQM1 = 110
3247 14:47:02.952923 DQ Delay:
3248 14:47:02.953020 DQ0 =123, DQ1 =115, DQ2 =115, DQ3 =119
3249 14:47:02.953125 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3250 14:47:02.953224 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3251 14:47:02.953320 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3252 14:47:02.953427
3253 14:47:02.953522
3254 14:47:02.953625 ==
3255 14:47:02.953726 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 14:47:02.953821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 14:47:02.953929 ==
3258 14:47:02.954025
3259 14:47:02.954122
3260 14:47:02.954240 TX Vref Scan disable
3261 14:47:02.954336 == TX Byte 0 ==
3262 14:47:02.954439 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3263 14:47:02.954505 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3264 14:47:02.954568 == TX Byte 1 ==
3265 14:47:02.954631 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3266 14:47:02.954713 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3267 14:47:02.954776 ==
3268 14:47:02.954838 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 14:47:02.954914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 14:47:02.955014 ==
3271 14:47:02.955110 TX Vref=22, minBit 11, minWin=24, winSum=413
3272 14:47:02.955220 TX Vref=24, minBit 11, minWin=25, winSum=421
3273 14:47:02.955317 TX Vref=26, minBit 10, minWin=25, winSum=424
3274 14:47:02.955414 TX Vref=28, minBit 0, minWin=26, winSum=425
3275 14:47:02.955486 TX Vref=30, minBit 1, minWin=26, winSum=429
3276 14:47:02.955548 TX Vref=32, minBit 10, minWin=25, winSum=424
3277 14:47:02.955610 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3278 14:47:02.955690
3279 14:47:02.955756 Final TX Range 1 Vref 30
3280 14:47:02.955818
3281 14:47:02.955879 ==
3282 14:47:02.955964 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 14:47:02.956029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 14:47:02.956092 ==
3285 14:47:02.956153
3286 14:47:02.956238
3287 14:47:02.956301 TX Vref Scan disable
3288 14:47:02.956363 == TX Byte 0 ==
3289 14:47:02.956434 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3290 14:47:02.956508 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3291 14:47:02.956572 == TX Byte 1 ==
3292 14:47:02.956634 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3293 14:47:02.956712 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3294 14:47:02.956778
3295 14:47:02.956839 [DATLAT]
3296 14:47:02.956901 Freq=1200, CH1 RK0
3297 14:47:02.956983
3298 14:47:02.957047 DATLAT Default: 0xd
3299 14:47:02.957109 0, 0xFFFF, sum = 0
3300 14:47:02.957172 1, 0xFFFF, sum = 0
3301 14:47:02.957258 2, 0xFFFF, sum = 0
3302 14:47:02.957323 3, 0xFFFF, sum = 0
3303 14:47:02.957385 4, 0xFFFF, sum = 0
3304 14:47:02.957459 5, 0xFFFF, sum = 0
3305 14:47:02.957561 6, 0xFFFF, sum = 0
3306 14:47:02.957658 7, 0xFFFF, sum = 0
3307 14:47:02.957768 8, 0xFFFF, sum = 0
3308 14:47:02.957865 9, 0xFFFF, sum = 0
3309 14:47:02.957972 10, 0xFFFF, sum = 0
3310 14:47:02.958082 11, 0xFFFF, sum = 0
3311 14:47:02.958177 12, 0x0, sum = 1
3312 14:47:02.958263 13, 0x0, sum = 2
3313 14:47:02.958323 14, 0x0, sum = 3
3314 14:47:02.958380 15, 0x0, sum = 4
3315 14:47:02.958436 best_step = 13
3316 14:47:02.958514
3317 14:47:02.958571 ==
3318 14:47:02.958627 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 14:47:02.958683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 14:47:02.958758 ==
3321 14:47:02.958817 RX Vref Scan: 1
3322 14:47:02.958873
3323 14:47:02.958929 Set Vref Range= 32 -> 127
3324 14:47:02.959000
3325 14:47:02.959058 RX Vref 32 -> 127, step: 1
3326 14:47:02.959115
3327 14:47:02.959169 RX Delay -21 -> 252, step: 4
3328 14:47:02.959233
3329 14:47:02.959298 Set Vref, RX VrefLevel [Byte0]: 32
3330 14:47:02.959354 [Byte1]: 32
3331 14:47:02.959416
3332 14:47:02.959477 Set Vref, RX VrefLevel [Byte0]: 33
3333 14:47:02.959547 [Byte1]: 33
3334 14:47:02.959604
3335 14:47:02.959659 Set Vref, RX VrefLevel [Byte0]: 34
3336 14:47:02.959715 [Byte1]: 34
3337 14:47:02.959792
3338 14:47:02.959849 Set Vref, RX VrefLevel [Byte0]: 35
3339 14:47:02.959906 [Byte1]: 35
3340 14:47:02.959962
3341 14:47:02.960041 Set Vref, RX VrefLevel [Byte0]: 36
3342 14:47:02.960098 [Byte1]: 36
3343 14:47:02.960154
3344 14:47:02.960209 Set Vref, RX VrefLevel [Byte0]: 37
3345 14:47:02.960295 [Byte1]: 37
3346 14:47:02.960390
3347 14:47:02.960493 Set Vref, RX VrefLevel [Byte0]: 38
3348 14:47:02.960590 [Byte1]: 38
3349 14:47:02.960677
3350 14:47:02.960773 Set Vref, RX VrefLevel [Byte0]: 39
3351 14:47:02.960863 [Byte1]: 39
3352 14:47:02.960949
3353 14:47:02.961045 Set Vref, RX VrefLevel [Byte0]: 40
3354 14:47:02.961133 [Byte1]: 40
3355 14:47:02.961219
3356 14:47:02.961318 Set Vref, RX VrefLevel [Byte0]: 41
3357 14:47:02.961406 [Byte1]: 41
3358 14:47:02.961492
3359 14:47:02.961589 Set Vref, RX VrefLevel [Byte0]: 42
3360 14:47:02.961676 [Byte1]: 42
3361 14:47:02.961771
3362 14:47:02.961860 Set Vref, RX VrefLevel [Byte0]: 43
3363 14:47:02.961947 [Byte1]: 43
3364 14:47:02.962043
3365 14:47:02.962130 Set Vref, RX VrefLevel [Byte0]: 44
3366 14:47:02.962224 [Byte1]: 44
3367 14:47:02.962321
3368 14:47:02.962408 Set Vref, RX VrefLevel [Byte0]: 45
3369 14:47:02.962495 [Byte1]: 45
3370 14:47:02.962569
3371 14:47:02.962626 Set Vref, RX VrefLevel [Byte0]: 46
3372 14:47:02.962681 [Byte1]: 46
3373 14:47:02.962737
3374 14:47:02.962814 Set Vref, RX VrefLevel [Byte0]: 47
3375 14:47:02.962871 [Byte1]: 47
3376 14:47:02.962926
3377 14:47:02.962982 Set Vref, RX VrefLevel [Byte0]: 48
3378 14:47:02.963080 [Byte1]: 48
3379 14:47:02.963163
3380 14:47:02.963244 Set Vref, RX VrefLevel [Byte0]: 49
3381 14:47:02.963339 [Byte1]: 49
3382 14:47:02.963423
3383 14:47:02.963523 Set Vref, RX VrefLevel [Byte0]: 50
3384 14:47:02.963585 [Byte1]: 50
3385 14:47:02.963639
3386 14:47:02.963692 Set Vref, RX VrefLevel [Byte0]: 51
3387 14:47:02.963745 [Byte1]: 51
3388 14:47:02.963819
3389 14:47:02.963874 Set Vref, RX VrefLevel [Byte0]: 52
3390 14:47:02.963928 [Byte1]: 52
3391 14:47:02.963981
3392 14:47:02.964048 Set Vref, RX VrefLevel [Byte0]: 53
3393 14:47:02.964105 [Byte1]: 53
3394 14:47:02.964159
3395 14:47:02.964211 Set Vref, RX VrefLevel [Byte0]: 54
3396 14:47:02.964264 [Byte1]: 54
3397 14:47:02.964338
3398 14:47:02.964393 Set Vref, RX VrefLevel [Byte0]: 55
3399 14:47:02.964446 [Byte1]: 55
3400 14:47:02.964499
3401 14:47:02.964766 Set Vref, RX VrefLevel [Byte0]: 56
3402 14:47:02.964844 [Byte1]: 56
3403 14:47:02.964901
3404 14:47:02.964954 Set Vref, RX VrefLevel [Byte0]: 57
3405 14:47:02.965011 [Byte1]: 57
3406 14:47:02.965079
3407 14:47:02.965133 Set Vref, RX VrefLevel [Byte0]: 58
3408 14:47:02.965187 [Byte1]: 58
3409 14:47:02.965240
3410 14:47:02.965292 Set Vref, RX VrefLevel [Byte0]: 59
3411 14:47:02.965366 [Byte1]: 59
3412 14:47:02.965421
3413 14:47:02.965475 Set Vref, RX VrefLevel [Byte0]: 60
3414 14:47:02.965528 [Byte1]: 60
3415 14:47:02.965581
3416 14:47:02.965657 Set Vref, RX VrefLevel [Byte0]: 61
3417 14:47:02.965741 [Byte1]: 61
3418 14:47:02.965823
3419 14:47:02.965916 Set Vref, RX VrefLevel [Byte0]: 62
3420 14:47:02.966011 [Byte1]: 62
3421 14:47:02.966127
3422 14:47:02.966223 Set Vref, RX VrefLevel [Byte0]: 63
3423 14:47:02.966280 [Byte1]: 63
3424 14:47:02.966333
3425 14:47:02.966387 Set Vref, RX VrefLevel [Byte0]: 64
3426 14:47:02.966457 [Byte1]: 64
3427 14:47:02.966514
3428 14:47:02.966567 Set Vref, RX VrefLevel [Byte0]: 65
3429 14:47:02.966620 [Byte1]: 65
3430 14:47:02.966673
3431 14:47:02.966726 Set Vref, RX VrefLevel [Byte0]: 66
3432 14:47:02.966797 [Byte1]: 66
3433 14:47:02.966852
3434 14:47:02.966905 Set Vref, RX VrefLevel [Byte0]: 67
3435 14:47:02.966958 [Byte1]: 67
3436 14:47:02.967032
3437 14:47:02.967086 Set Vref, RX VrefLevel [Byte0]: 68
3438 14:47:02.967140 [Byte1]: 68
3439 14:47:02.967193
3440 14:47:02.967263 Final RX Vref Byte 0 = 52 to rank0
3441 14:47:02.967320 Final RX Vref Byte 1 = 54 to rank0
3442 14:47:02.967400 Final RX Vref Byte 0 = 52 to rank1
3443 14:47:02.967519 Final RX Vref Byte 1 = 54 to rank1==
3444 14:47:02.967576 Dram Type= 6, Freq= 0, CH_1, rank 0
3445 14:47:02.967629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 14:47:02.967683 ==
3447 14:47:02.967744 DQS Delay:
3448 14:47:02.967805 DQS0 = 0, DQS1 = 0
3449 14:47:02.967859 DQM Delay:
3450 14:47:02.967912 DQM0 = 117, DQM1 = 111
3451 14:47:02.967966 DQ Delay:
3452 14:47:02.968052 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =116
3453 14:47:02.968135 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =114
3454 14:47:02.968218 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =100
3455 14:47:02.968311 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =120
3456 14:47:02.968394
3457 14:47:02.968475
3458 14:47:02.968569 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3459 14:47:02.968654 CH1 RK0: MR19=403, MR18=F4
3460 14:47:02.968739 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3461 14:47:02.968831
3462 14:47:02.968914 ----->DramcWriteLeveling(PI) begin...
3463 14:47:02.969004 ==
3464 14:47:02.969093 Dram Type= 6, Freq= 0, CH_1, rank 1
3465 14:47:02.969177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 14:47:02.969268 ==
3467 14:47:02.969354 Write leveling (Byte 0): 23 => 23
3468 14:47:02.969437 Write leveling (Byte 1): 29 => 29
3469 14:47:02.969529 DramcWriteLeveling(PI) end<-----
3470 14:47:02.969613
3471 14:47:02.969694 ==
3472 14:47:02.969786 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 14:47:02.969871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 14:47:02.969954 ==
3475 14:47:02.970046 [Gating] SW mode calibration
3476 14:47:02.970132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3477 14:47:02.970224 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3478 14:47:02.970310 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3479 14:47:02.970367 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 14:47:02.970422 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 14:47:02.970475 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 14:47:02.970543 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 14:47:02.970601 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 14:47:02.970654 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3485 14:47:02.970707 0 15 28 | B1->B0 | 2828 2f2f | 0 1 | (1 0) (1 0)
3486 14:47:02.970760 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 14:47:02.970833 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 14:47:02.970888 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 14:47:02.970942 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 14:47:02.970995 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 14:47:02.971070 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 14:47:02.971126 1 0 24 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
3493 14:47:02.971180 1 0 28 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
3494 14:47:02.971232 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 14:47:02.971299 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 14:47:02.971356 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 14:47:02.971410 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 14:47:02.971463 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 14:47:02.971517 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 14:47:02.971591 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3501 14:47:02.971646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3502 14:47:02.971699 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 14:47:02.971753 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 14:47:02.971826 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 14:47:02.971882 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 14:47:02.971935 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 14:47:02.971988 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 14:47:02.972053 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 14:47:02.972112 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 14:47:02.972165 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 14:47:02.972218 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 14:47:02.972271 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 14:47:02.972361 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 14:47:02.972445 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 14:47:02.972527 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 14:47:02.972827 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3517 14:47:02.972916 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3518 14:47:02.973001 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 14:47:02.973095 Total UI for P1: 0, mck2ui 16
3520 14:47:02.973180 best dqsien dly found for B0: ( 1, 3, 26)
3521 14:47:02.973263 Total UI for P1: 0, mck2ui 16
3522 14:47:02.973358 best dqsien dly found for B1: ( 1, 3, 26)
3523 14:47:02.973442 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3524 14:47:02.973525 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3525 14:47:02.973618
3526 14:47:02.973701 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3527 14:47:02.973784 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3528 14:47:02.973877 [Gating] SW calibration Done
3529 14:47:02.973960 ==
3530 14:47:02.974042 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 14:47:02.974136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 14:47:02.974262 ==
3533 14:47:02.974352 RX Vref Scan: 0
3534 14:47:02.974408
3535 14:47:02.974461 RX Vref 0 -> 0, step: 1
3536 14:47:02.974516
3537 14:47:02.974579 RX Delay -40 -> 252, step: 8
3538 14:47:02.974640 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3539 14:47:02.974694 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3540 14:47:02.974748 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3541 14:47:02.974802 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3542 14:47:02.974876 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3543 14:47:02.974932 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3544 14:47:02.974985 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3545 14:47:02.975038 iDelay=208, Bit 7, Center 119 (48 ~ 191) 144
3546 14:47:02.975106 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3547 14:47:02.975163 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3548 14:47:02.975217 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3549 14:47:02.975270 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3550 14:47:02.975325 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3551 14:47:02.975394 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3552 14:47:02.975448 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3553 14:47:02.975502 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3554 14:47:02.975555 ==
3555 14:47:02.975635 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 14:47:02.975720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 14:47:02.975803 ==
3558 14:47:02.975896 DQS Delay:
3559 14:47:02.975979 DQS0 = 0, DQS1 = 0
3560 14:47:02.976062 DQM Delay:
3561 14:47:02.976155 DQM0 = 118, DQM1 = 110
3562 14:47:02.976238 DQ Delay:
3563 14:47:02.976320 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3564 14:47:02.976414 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3565 14:47:02.976497 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3566 14:47:02.976580 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3567 14:47:02.976673
3568 14:47:02.976755
3569 14:47:02.976836 ==
3570 14:47:02.976930 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 14:47:02.977014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 14:47:02.977098 ==
3573 14:47:02.977189
3574 14:47:02.977271
3575 14:47:02.977356 TX Vref Scan disable
3576 14:47:02.977447 == TX Byte 0 ==
3577 14:47:02.977530 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3578 14:47:02.977621 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3579 14:47:02.977708 == TX Byte 1 ==
3580 14:47:02.977790 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3581 14:47:02.977883 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3582 14:47:02.977967 ==
3583 14:47:02.978050 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 14:47:02.978142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 14:47:02.978233 ==
3586 14:47:02.978317 TX Vref=22, minBit 9, minWin=25, winSum=422
3587 14:47:02.978411 TX Vref=24, minBit 0, minWin=26, winSum=428
3588 14:47:02.978496 TX Vref=26, minBit 3, minWin=26, winSum=431
3589 14:47:02.978580 TX Vref=28, minBit 3, minWin=26, winSum=433
3590 14:47:02.978674 TX Vref=30, minBit 9, minWin=26, winSum=434
3591 14:47:02.978759 TX Vref=32, minBit 6, minWin=26, winSum=432
3592 14:47:02.978843 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3593 14:47:02.978936
3594 14:47:02.979019 Final TX Range 1 Vref 30
3595 14:47:02.979101
3596 14:47:02.979194 ==
3597 14:47:02.979277 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 14:47:02.979367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 14:47:02.979454 ==
3600 14:47:02.979535
3601 14:47:02.979627
3602 14:47:02.979711 TX Vref Scan disable
3603 14:47:02.979793 == TX Byte 0 ==
3604 14:47:02.979886 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3605 14:47:02.979970 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3606 14:47:02.980052 == TX Byte 1 ==
3607 14:47:02.980146 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3608 14:47:02.980230 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3609 14:47:02.980312
3610 14:47:02.980404 [DATLAT]
3611 14:47:02.980487 Freq=1200, CH1 RK1
3612 14:47:02.980570
3613 14:47:02.980662 DATLAT Default: 0xd
3614 14:47:02.980745 0, 0xFFFF, sum = 0
3615 14:47:02.980834 1, 0xFFFF, sum = 0
3616 14:47:02.980925 2, 0xFFFF, sum = 0
3617 14:47:02.981011 3, 0xFFFF, sum = 0
3618 14:47:02.981105 4, 0xFFFF, sum = 0
3619 14:47:02.981229 5, 0xFFFF, sum = 0
3620 14:47:02.981314 6, 0xFFFF, sum = 0
3621 14:47:02.981408 7, 0xFFFF, sum = 0
3622 14:47:02.981492 8, 0xFFFF, sum = 0
3623 14:47:02.981584 9, 0xFFFF, sum = 0
3624 14:47:02.981672 10, 0xFFFF, sum = 0
3625 14:47:02.981756 11, 0xFFFF, sum = 0
3626 14:47:02.981849 12, 0x0, sum = 1
3627 14:47:02.981936 13, 0x0, sum = 2
3628 14:47:02.982020 14, 0x0, sum = 3
3629 14:47:02.982134 15, 0x0, sum = 4
3630 14:47:02.982245 best_step = 13
3631 14:47:02.982336
3632 14:47:02.982393 ==
3633 14:47:02.982446 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 14:47:02.982500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 14:47:02.982563 ==
3636 14:47:02.982624 RX Vref Scan: 0
3637 14:47:02.982678
3638 14:47:02.982730 RX Vref 0 -> 0, step: 1
3639 14:47:02.982783
3640 14:47:02.982857 RX Delay -21 -> 252, step: 4
3641 14:47:02.982912 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3642 14:47:02.982966 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3643 14:47:02.983019 iDelay=199, Bit 2, Center 108 (47 ~ 170) 124
3644 14:47:02.983092 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3645 14:47:02.983146 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3646 14:47:02.983208 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3647 14:47:02.983263 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3648 14:47:02.983337 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3649 14:47:02.983392 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3650 14:47:02.983445 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3651 14:47:02.983498 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3652 14:47:02.983572 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3653 14:47:02.983627 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3654 14:47:02.983875 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3655 14:47:02.983936 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3656 14:47:02.983999 iDelay=199, Bit 15, Center 120 (55 ~ 186) 132
3657 14:47:02.984061 ==
3658 14:47:02.984117 Dram Type= 6, Freq= 0, CH_1, rank 1
3659 14:47:02.984171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3660 14:47:02.984232 ==
3661 14:47:02.984295 DQS Delay:
3662 14:47:02.984349 DQS0 = 0, DQS1 = 0
3663 14:47:02.984403 DQM Delay:
3664 14:47:02.984456 DQM0 = 118, DQM1 = 111
3665 14:47:02.984530 DQ Delay:
3666 14:47:02.984584 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =114
3667 14:47:02.984638 DQ4 =116, DQ5 =128, DQ6 =130, DQ7 =116
3668 14:47:02.984691 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3669 14:47:02.984765 DQ12 =120, DQ13 =120, DQ14 =122, DQ15 =120
3670 14:47:02.984821
3671 14:47:02.984875
3672 14:47:02.984927 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3673 14:47:02.984993 CH1 RK1: MR19=303, MR18=F3EE
3674 14:47:02.985051 CH1_RK1: MR19=0x303, MR18=0xF3EE, DQSOSC=415, MR23=63, INC=38, DEC=25
3675 14:47:02.985106 [RxdqsGatingPostProcess] freq 1200
3676 14:47:02.985190 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3677 14:47:02.985284 best DQS0 dly(2T, 0.5T) = (0, 11)
3678 14:47:02.985341 best DQS1 dly(2T, 0.5T) = (0, 11)
3679 14:47:02.985395 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3680 14:47:02.985448 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3681 14:47:02.985522 best DQS0 dly(2T, 0.5T) = (0, 11)
3682 14:47:02.985577 best DQS1 dly(2T, 0.5T) = (0, 11)
3683 14:47:02.985631 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3684 14:47:02.985684 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3685 14:47:02.985753 Pre-setting of DQS Precalculation
3686 14:47:02.985839 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3687 14:47:02.985923 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3688 14:47:02.986018 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3689 14:47:02.986102
3690 14:47:02.986206
3691 14:47:02.986294 [Calibration Summary] 2400 Mbps
3692 14:47:02.986350 CH 0, Rank 0
3693 14:47:02.986403 SW Impedance : PASS
3694 14:47:02.986457 DUTY Scan : NO K
3695 14:47:02.986524 ZQ Calibration : PASS
3696 14:47:02.986582 Jitter Meter : NO K
3697 14:47:02.986636 CBT Training : PASS
3698 14:47:02.986689 Write leveling : PASS
3699 14:47:02.986742 RX DQS gating : PASS
3700 14:47:02.986815 RX DQ/DQS(RDDQC) : PASS
3701 14:47:02.986870 TX DQ/DQS : PASS
3702 14:47:02.986923 RX DATLAT : PASS
3703 14:47:02.986976 RX DQ/DQS(Engine): PASS
3704 14:47:02.987050 TX OE : NO K
3705 14:47:02.987106 All Pass.
3706 14:47:02.987180
3707 14:47:02.987267 CH 0, Rank 1
3708 14:47:02.987345 SW Impedance : PASS
3709 14:47:02.987414 DUTY Scan : NO K
3710 14:47:02.987469 ZQ Calibration : PASS
3711 14:47:02.987531 Jitter Meter : NO K
3712 14:47:02.987614 CBT Training : PASS
3713 14:47:02.987697 Write leveling : PASS
3714 14:47:02.987782 RX DQS gating : PASS
3715 14:47:02.987865 RX DQ/DQS(RDDQC) : PASS
3716 14:47:02.987948 TX DQ/DQS : PASS
3717 14:47:02.988033 RX DATLAT : PASS
3718 14:47:02.988116 RX DQ/DQS(Engine): PASS
3719 14:47:02.988198 TX OE : NO K
3720 14:47:02.988283 All Pass.
3721 14:47:02.988365
3722 14:47:02.988447 CH 1, Rank 0
3723 14:47:02.988532 SW Impedance : PASS
3724 14:47:02.988615 DUTY Scan : NO K
3725 14:47:02.988697 ZQ Calibration : PASS
3726 14:47:02.988783 Jitter Meter : NO K
3727 14:47:02.988865 CBT Training : PASS
3728 14:47:02.988947 Write leveling : PASS
3729 14:47:02.989033 RX DQS gating : PASS
3730 14:47:02.989115 RX DQ/DQS(RDDQC) : PASS
3731 14:47:02.989197 TX DQ/DQS : PASS
3732 14:47:02.989283 RX DATLAT : PASS
3733 14:47:02.989365 RX DQ/DQS(Engine): PASS
3734 14:47:02.989447 TX OE : NO K
3735 14:47:02.989532 All Pass.
3736 14:47:02.989614
3737 14:47:02.989695 CH 1, Rank 1
3738 14:47:02.989780 SW Impedance : PASS
3739 14:47:02.989862 DUTY Scan : NO K
3740 14:47:02.989944 ZQ Calibration : PASS
3741 14:47:02.990030 Jitter Meter : NO K
3742 14:47:02.990113 CBT Training : PASS
3743 14:47:02.990236 Write leveling : PASS
3744 14:47:02.990295 RX DQS gating : PASS
3745 14:47:02.990348 RX DQ/DQS(RDDQC) : PASS
3746 14:47:02.990401 TX DQ/DQS : PASS
3747 14:47:02.990454 RX DATLAT : PASS
3748 14:47:02.990515 RX DQ/DQS(Engine): PASS
3749 14:47:02.990569 TX OE : NO K
3750 14:47:02.990623 All Pass.
3751 14:47:02.990676
3752 14:47:02.990734 DramC Write-DBI off
3753 14:47:02.990788 PER_BANK_REFRESH: Hybrid Mode
3754 14:47:02.990841 TX_TRACKING: ON
3755 14:47:02.990895 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3756 14:47:02.990949 [FAST_K] Save calibration result to emmc
3757 14:47:02.991009 dramc_set_vcore_voltage set vcore to 650000
3758 14:47:02.991063 Read voltage for 600, 5
3759 14:47:02.991116 Vio18 = 0
3760 14:47:02.991169 Vcore = 650000
3761 14:47:02.991222 Vdram = 0
3762 14:47:02.991280 Vddq = 0
3763 14:47:02.991332 Vmddr = 0
3764 14:47:02.991386 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3765 14:47:02.991439 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3766 14:47:02.991498 MEM_TYPE=3, freq_sel=19
3767 14:47:02.991552 sv_algorithm_assistance_LP4_1600
3768 14:47:02.991605 ============ PULL DRAM RESETB DOWN ============
3769 14:47:02.991659 ========== PULL DRAM RESETB DOWN end =========
3770 14:47:02.991713 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3771 14:47:02.991772 ===================================
3772 14:47:02.991825 LPDDR4 DRAM CONFIGURATION
3773 14:47:02.991879 ===================================
3774 14:47:02.991932 EX_ROW_EN[0] = 0x0
3775 14:47:02.991989 EX_ROW_EN[1] = 0x0
3776 14:47:02.992043 LP4Y_EN = 0x0
3777 14:47:02.992096 WORK_FSP = 0x0
3778 14:47:02.992149 WL = 0x2
3779 14:47:02.992202 RL = 0x2
3780 14:47:02.992283 BL = 0x2
3781 14:47:02.992365 RPST = 0x0
3782 14:47:02.992448 RD_PRE = 0x0
3783 14:47:02.992534 WR_PRE = 0x1
3784 14:47:02.992616 WR_PST = 0x0
3785 14:47:02.992698 DBI_WR = 0x0
3786 14:47:02.992782 DBI_RD = 0x0
3787 14:47:02.992864 OTF = 0x1
3788 14:47:02.992947 ===================================
3789 14:47:02.993033 ===================================
3790 14:47:02.993115 ANA top config
3791 14:47:02.993193 ===================================
3792 14:47:02.993251 DLL_ASYNC_EN = 0
3793 14:47:02.993304 ALL_SLAVE_EN = 1
3794 14:47:02.993357 NEW_RANK_MODE = 1
3795 14:47:02.993411 DLL_IDLE_MODE = 1
3796 14:47:02.993471 LP45_APHY_COMB_EN = 1
3797 14:47:02.993524 TX_ODT_DIS = 1
3798 14:47:02.993578 NEW_8X_MODE = 1
3799 14:47:02.993631 ===================================
3800 14:47:02.993880 ===================================
3801 14:47:02.993945 data_rate = 1200
3802 14:47:02.994001 CKR = 1
3803 14:47:02.994055 DQ_P2S_RATIO = 8
3804 14:47:02.994108 ===================================
3805 14:47:02.994172 CA_P2S_RATIO = 8
3806 14:47:02.994263 DQ_CA_OPEN = 0
3807 14:47:02.994316 DQ_SEMI_OPEN = 0
3808 14:47:02.994369 CA_SEMI_OPEN = 0
3809 14:47:02.997220 CA_FULL_RATE = 0
3810 14:47:02.997315 DQ_CKDIV4_EN = 1
3811 14:47:03.000247 CA_CKDIV4_EN = 1
3812 14:47:03.003919 CA_PREDIV_EN = 0
3813 14:47:03.007024 PH8_DLY = 0
3814 14:47:03.010157 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3815 14:47:03.014060 DQ_AAMCK_DIV = 4
3816 14:47:03.014169 CA_AAMCK_DIV = 4
3817 14:47:03.017133 CA_ADMCK_DIV = 4
3818 14:47:03.020491 DQ_TRACK_CA_EN = 0
3819 14:47:03.023517 CA_PICK = 600
3820 14:47:03.026792 CA_MCKIO = 600
3821 14:47:03.030415 MCKIO_SEMI = 0
3822 14:47:03.034106 PLL_FREQ = 2288
3823 14:47:03.034233 DQ_UI_PI_RATIO = 32
3824 14:47:03.036753 CA_UI_PI_RATIO = 0
3825 14:47:03.040109 ===================================
3826 14:47:03.043258 ===================================
3827 14:47:03.046610 memory_type:LPDDR4
3828 14:47:03.050025 GP_NUM : 10
3829 14:47:03.050121 SRAM_EN : 1
3830 14:47:03.053239 MD32_EN : 0
3831 14:47:03.056515 ===================================
3832 14:47:03.059905 [ANA_INIT] >>>>>>>>>>>>>>
3833 14:47:03.060002 <<<<<< [CONFIGURE PHASE]: ANA_TX
3834 14:47:03.066667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3835 14:47:03.070024 ===================================
3836 14:47:03.070122 data_rate = 1200,PCW = 0X5800
3837 14:47:03.073409 ===================================
3838 14:47:03.076410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3839 14:47:03.082962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3840 14:47:03.089957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3841 14:47:03.093274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3842 14:47:03.096006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3843 14:47:03.099228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3844 14:47:03.103288 [ANA_INIT] flow start
3845 14:47:03.105944 [ANA_INIT] PLL >>>>>>>>
3846 14:47:03.106022 [ANA_INIT] PLL <<<<<<<<
3847 14:47:03.109217 [ANA_INIT] MIDPI >>>>>>>>
3848 14:47:03.112863 [ANA_INIT] MIDPI <<<<<<<<
3849 14:47:03.112962 [ANA_INIT] DLL >>>>>>>>
3850 14:47:03.115750 [ANA_INIT] flow end
3851 14:47:03.119004 ============ LP4 DIFF to SE enter ============
3852 14:47:03.122471 ============ LP4 DIFF to SE exit ============
3853 14:47:03.125805 [ANA_INIT] <<<<<<<<<<<<<
3854 14:47:03.128959 [Flow] Enable top DCM control >>>>>
3855 14:47:03.132392 [Flow] Enable top DCM control <<<<<
3856 14:47:03.135752 Enable DLL master slave shuffle
3857 14:47:03.142240 ==============================================================
3858 14:47:03.142375 Gating Mode config
3859 14:47:03.149382 ==============================================================
3860 14:47:03.149509 Config description:
3861 14:47:03.158483 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3862 14:47:03.165381 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3863 14:47:03.171994 SELPH_MODE 0: By rank 1: By Phase
3864 14:47:03.178904 ==============================================================
3865 14:47:03.179007 GAT_TRACK_EN = 1
3866 14:47:03.181856 RX_GATING_MODE = 2
3867 14:47:03.185152 RX_GATING_TRACK_MODE = 2
3868 14:47:03.188561 SELPH_MODE = 1
3869 14:47:03.191829 PICG_EARLY_EN = 1
3870 14:47:03.195314 VALID_LAT_VALUE = 1
3871 14:47:03.201850 ==============================================================
3872 14:47:03.204930 Enter into Gating configuration >>>>
3873 14:47:03.208473 Exit from Gating configuration <<<<
3874 14:47:03.211545 Enter into DVFS_PRE_config >>>>>
3875 14:47:03.221551 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3876 14:47:03.224770 Exit from DVFS_PRE_config <<<<<
3877 14:47:03.227946 Enter into PICG configuration >>>>
3878 14:47:03.231464 Exit from PICG configuration <<<<
3879 14:47:03.234877 [RX_INPUT] configuration >>>>>
3880 14:47:03.237925 [RX_INPUT] configuration <<<<<
3881 14:47:03.241299 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3882 14:47:03.247971 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3883 14:47:03.254746 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3884 14:47:03.257703 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3885 14:47:03.264503 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3886 14:47:03.271299 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3887 14:47:03.274519 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3888 14:47:03.281215 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3889 14:47:03.284015 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3890 14:47:03.287551 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3891 14:47:03.290475 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3892 14:47:03.297253 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3893 14:47:03.300750 ===================================
3894 14:47:03.304071 LPDDR4 DRAM CONFIGURATION
3895 14:47:03.307196 ===================================
3896 14:47:03.307267 EX_ROW_EN[0] = 0x0
3897 14:47:03.310546 EX_ROW_EN[1] = 0x0
3898 14:47:03.310642 LP4Y_EN = 0x0
3899 14:47:03.313805 WORK_FSP = 0x0
3900 14:47:03.313919 WL = 0x2
3901 14:47:03.317324 RL = 0x2
3902 14:47:03.317424 BL = 0x2
3903 14:47:03.320192 RPST = 0x0
3904 14:47:03.320266 RD_PRE = 0x0
3905 14:47:03.323569 WR_PRE = 0x1
3906 14:47:03.323639 WR_PST = 0x0
3907 14:47:03.326965 DBI_WR = 0x0
3908 14:47:03.327063 DBI_RD = 0x0
3909 14:47:03.330334 OTF = 0x1
3910 14:47:03.333323 ===================================
3911 14:47:03.336797 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3912 14:47:03.339925 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3913 14:47:03.346704 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3914 14:47:03.350058 ===================================
3915 14:47:03.353372 LPDDR4 DRAM CONFIGURATION
3916 14:47:03.357155 ===================================
3917 14:47:03.357258 EX_ROW_EN[0] = 0x10
3918 14:47:03.360174 EX_ROW_EN[1] = 0x0
3919 14:47:03.360273 LP4Y_EN = 0x0
3920 14:47:03.362964 WORK_FSP = 0x0
3921 14:47:03.363037 WL = 0x2
3922 14:47:03.366865 RL = 0x2
3923 14:47:03.366937 BL = 0x2
3924 14:47:03.370293 RPST = 0x0
3925 14:47:03.370392 RD_PRE = 0x0
3926 14:47:03.372846 WR_PRE = 0x1
3927 14:47:03.372918 WR_PST = 0x0
3928 14:47:03.376394 DBI_WR = 0x0
3929 14:47:03.376493 DBI_RD = 0x0
3930 14:47:03.379485 OTF = 0x1
3931 14:47:03.382977 ===================================
3932 14:47:03.389762 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3933 14:47:03.393197 nWR fixed to 30
3934 14:47:03.396577 [ModeRegInit_LP4] CH0 RK0
3935 14:47:03.396674 [ModeRegInit_LP4] CH0 RK1
3936 14:47:03.399446 [ModeRegInit_LP4] CH1 RK0
3937 14:47:03.403203 [ModeRegInit_LP4] CH1 RK1
3938 14:47:03.403300 match AC timing 17
3939 14:47:03.409417 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3940 14:47:03.412780 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3941 14:47:03.415919 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3942 14:47:03.422355 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3943 14:47:03.425871 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3944 14:47:03.425975 ==
3945 14:47:03.429428 Dram Type= 6, Freq= 0, CH_0, rank 0
3946 14:47:03.432284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 14:47:03.435460 ==
3948 14:47:03.438857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3949 14:47:03.445769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3950 14:47:03.448782 [CA 0] Center 36 (6~66) winsize 61
3951 14:47:03.452235 [CA 1] Center 36 (6~66) winsize 61
3952 14:47:03.455521 [CA 2] Center 34 (4~65) winsize 62
3953 14:47:03.458651 [CA 3] Center 34 (4~64) winsize 61
3954 14:47:03.462269 [CA 4] Center 33 (3~64) winsize 62
3955 14:47:03.465673 [CA 5] Center 33 (3~64) winsize 62
3956 14:47:03.465745
3957 14:47:03.468875 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3958 14:47:03.468945
3959 14:47:03.471849 [CATrainingPosCal] consider 1 rank data
3960 14:47:03.475624 u2DelayCellTimex100 = 270/100 ps
3961 14:47:03.478543 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3962 14:47:03.481831 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3963 14:47:03.485613 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 14:47:03.491890 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3965 14:47:03.495164 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 14:47:03.498514 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 14:47:03.498588
3968 14:47:03.501829 CA PerBit enable=1, Macro0, CA PI delay=33
3969 14:47:03.501925
3970 14:47:03.505012 [CBTSetCACLKResult] CA Dly = 33
3971 14:47:03.505109 CS Dly: 5 (0~36)
3972 14:47:03.505201 ==
3973 14:47:03.508204 Dram Type= 6, Freq= 0, CH_0, rank 1
3974 14:47:03.514791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 14:47:03.514863 ==
3976 14:47:03.518345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 14:47:03.524991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3978 14:47:03.528558 [CA 0] Center 36 (6~66) winsize 61
3979 14:47:03.531614 [CA 1] Center 36 (6~66) winsize 61
3980 14:47:03.534889 [CA 2] Center 33 (3~64) winsize 62
3981 14:47:03.537997 [CA 3] Center 33 (3~64) winsize 62
3982 14:47:03.541683 [CA 4] Center 33 (2~64) winsize 63
3983 14:47:03.544875 [CA 5] Center 33 (2~64) winsize 63
3984 14:47:03.544973
3985 14:47:03.548051 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3986 14:47:03.548153
3987 14:47:03.551450 [CATrainingPosCal] consider 2 rank data
3988 14:47:03.554812 u2DelayCellTimex100 = 270/100 ps
3989 14:47:03.557818 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3990 14:47:03.564414 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3991 14:47:03.567568 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3992 14:47:03.571003 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3993 14:47:03.574618 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 14:47:03.577908 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3995 14:47:03.578017
3996 14:47:03.581204 CA PerBit enable=1, Macro0, CA PI delay=33
3997 14:47:03.581310
3998 14:47:03.584127 [CBTSetCACLKResult] CA Dly = 33
3999 14:47:03.587731 CS Dly: 5 (0~36)
4000 14:47:03.587829
4001 14:47:03.590949 ----->DramcWriteLeveling(PI) begin...
4002 14:47:03.591047 ==
4003 14:47:03.594169 Dram Type= 6, Freq= 0, CH_0, rank 0
4004 14:47:03.598058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4005 14:47:03.598156 ==
4006 14:47:03.600580 Write leveling (Byte 0): 33 => 33
4007 14:47:03.603735 Write leveling (Byte 1): 30 => 30
4008 14:47:03.607165 DramcWriteLeveling(PI) end<-----
4009 14:47:03.607235
4010 14:47:03.607298 ==
4011 14:47:03.610654 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 14:47:03.613815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 14:47:03.613887 ==
4014 14:47:03.617061 [Gating] SW mode calibration
4015 14:47:03.623840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4016 14:47:03.630467 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4017 14:47:03.633710 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 14:47:03.640241 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 14:47:03.643534 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 14:47:03.647021 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
4021 14:47:03.653314 0 9 16 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
4022 14:47:03.656781 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 14:47:03.660141 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 14:47:03.663364 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 14:47:03.669928 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 14:47:03.673141 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 14:47:03.677176 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 14:47:03.683011 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4029 14:47:03.686244 0 10 16 | B1->B0 | 2e2e 3e3e | 0 0 | (0 0) (0 0)
4030 14:47:03.689739 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 14:47:03.696060 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 14:47:03.699810 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 14:47:03.703007 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 14:47:03.709284 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 14:47:03.712954 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 14:47:03.715897 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 14:47:03.722879 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4038 14:47:03.725904 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 14:47:03.729643 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 14:47:03.736347 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 14:47:03.739264 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 14:47:03.742436 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 14:47:03.748973 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 14:47:03.752583 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 14:47:03.755723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 14:47:03.762072 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 14:47:03.765710 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 14:47:03.769219 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 14:47:03.775438 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 14:47:03.778638 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 14:47:03.781766 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 14:47:03.788682 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4053 14:47:03.791576 Total UI for P1: 0, mck2ui 16
4054 14:47:03.794963 best dqsien dly found for B0: ( 0, 13, 10)
4055 14:47:03.798522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 14:47:03.801914 Total UI for P1: 0, mck2ui 16
4057 14:47:03.804768 best dqsien dly found for B1: ( 0, 13, 12)
4058 14:47:03.808216 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4059 14:47:03.811806 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4060 14:47:03.811876
4061 14:47:03.814692 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4062 14:47:03.821531 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4063 14:47:03.821606 [Gating] SW calibration Done
4064 14:47:03.821670 ==
4065 14:47:03.824845 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 14:47:03.831417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 14:47:03.831499 ==
4068 14:47:03.831566 RX Vref Scan: 0
4069 14:47:03.831632
4070 14:47:03.834827 RX Vref 0 -> 0, step: 1
4071 14:47:03.834903
4072 14:47:03.837862 RX Delay -230 -> 252, step: 16
4073 14:47:03.841221 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4074 14:47:03.844692 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4075 14:47:03.851254 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4076 14:47:03.854598 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4077 14:47:03.857850 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4078 14:47:03.861476 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4079 14:47:03.867581 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4080 14:47:03.871148 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4081 14:47:03.874115 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4082 14:47:03.877291 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4083 14:47:03.880794 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4084 14:47:03.887519 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4085 14:47:03.890942 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4086 14:47:03.893746 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4087 14:47:03.900462 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4088 14:47:03.904010 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4089 14:47:03.904110 ==
4090 14:47:03.907282 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 14:47:03.910279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 14:47:03.910376 ==
4093 14:47:03.914556 DQS Delay:
4094 14:47:03.914655 DQS0 = 0, DQS1 = 0
4095 14:47:03.914745 DQM Delay:
4096 14:47:03.917085 DQM0 = 44, DQM1 = 29
4097 14:47:03.917189 DQ Delay:
4098 14:47:03.920307 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4099 14:47:03.923700 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4100 14:47:03.926825 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4101 14:47:03.930411 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4102 14:47:03.930515
4103 14:47:03.930611
4104 14:47:03.930749 ==
4105 14:47:03.933685 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 14:47:03.940251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 14:47:03.940356 ==
4108 14:47:03.940452
4109 14:47:03.940544
4110 14:47:03.940646 TX Vref Scan disable
4111 14:47:03.943552 == TX Byte 0 ==
4112 14:47:03.946849 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4113 14:47:03.953346 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4114 14:47:03.953427 == TX Byte 1 ==
4115 14:47:03.956990 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4116 14:47:03.963288 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4117 14:47:03.963396 ==
4118 14:47:03.966984 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 14:47:03.970037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 14:47:03.970154 ==
4121 14:47:03.970258
4122 14:47:03.970320
4123 14:47:03.973235 TX Vref Scan disable
4124 14:47:03.976237 == TX Byte 0 ==
4125 14:47:03.979804 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4126 14:47:03.983296 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4127 14:47:03.986256 == TX Byte 1 ==
4128 14:47:03.989493 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4129 14:47:03.993147 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4130 14:47:03.993246
4131 14:47:03.996085 [DATLAT]
4132 14:47:03.996181 Freq=600, CH0 RK0
4133 14:47:03.996274
4134 14:47:03.999830 DATLAT Default: 0x9
4135 14:47:03.999928 0, 0xFFFF, sum = 0
4136 14:47:04.002998 1, 0xFFFF, sum = 0
4137 14:47:04.003099 2, 0xFFFF, sum = 0
4138 14:47:04.006453 3, 0xFFFF, sum = 0
4139 14:47:04.006529 4, 0xFFFF, sum = 0
4140 14:47:04.009503 5, 0xFFFF, sum = 0
4141 14:47:04.009573 6, 0xFFFF, sum = 0
4142 14:47:04.012813 7, 0xFFFF, sum = 0
4143 14:47:04.012885 8, 0x0, sum = 1
4144 14:47:04.015815 9, 0x0, sum = 2
4145 14:47:04.015912 10, 0x0, sum = 3
4146 14:47:04.019190 11, 0x0, sum = 4
4147 14:47:04.019278 best_step = 9
4148 14:47:04.019367
4149 14:47:04.019454 ==
4150 14:47:04.022822 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 14:47:04.025849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 14:47:04.029456 ==
4153 14:47:04.029538 RX Vref Scan: 1
4154 14:47:04.029601
4155 14:47:04.032319 RX Vref 0 -> 0, step: 1
4156 14:47:04.032428
4157 14:47:04.035730 RX Delay -195 -> 252, step: 8
4158 14:47:04.035830
4159 14:47:04.039337 Set Vref, RX VrefLevel [Byte0]: 59
4160 14:47:04.042330 [Byte1]: 50
4161 14:47:04.042430
4162 14:47:04.045849 Final RX Vref Byte 0 = 59 to rank0
4163 14:47:04.049259 Final RX Vref Byte 1 = 50 to rank0
4164 14:47:04.052227 Final RX Vref Byte 0 = 59 to rank1
4165 14:47:04.055510 Final RX Vref Byte 1 = 50 to rank1==
4166 14:47:04.058602 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 14:47:04.061993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 14:47:04.062096 ==
4169 14:47:04.065416 DQS Delay:
4170 14:47:04.065516 DQS0 = 0, DQS1 = 0
4171 14:47:04.065614 DQM Delay:
4172 14:47:04.068850 DQM0 = 43, DQM1 = 32
4173 14:47:04.068948 DQ Delay:
4174 14:47:04.071993 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4175 14:47:04.075318 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4176 14:47:04.078396 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4177 14:47:04.081879 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4178 14:47:04.081980
4179 14:47:04.082072
4180 14:47:04.091950 [DQSOSCAuto] RK0, (LSB)MR18= 0x6941, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4181 14:47:04.095435 CH0 RK0: MR19=808, MR18=6941
4182 14:47:04.098244 CH0_RK0: MR19=0x808, MR18=0x6941, DQSOSC=390, MR23=63, INC=172, DEC=114
4183 14:47:04.098346
4184 14:47:04.102044 ----->DramcWriteLeveling(PI) begin...
4185 14:47:04.104954 ==
4186 14:47:04.108624 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 14:47:04.111736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 14:47:04.111813 ==
4189 14:47:04.114898 Write leveling (Byte 0): 33 => 33
4190 14:47:04.118023 Write leveling (Byte 1): 29 => 29
4191 14:47:04.121263 DramcWriteLeveling(PI) end<-----
4192 14:47:04.121361
4193 14:47:04.121454 ==
4194 14:47:04.124793 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 14:47:04.128128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 14:47:04.128228 ==
4197 14:47:04.131403 [Gating] SW mode calibration
4198 14:47:04.137808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4199 14:47:04.144839 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4200 14:47:04.147632 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 14:47:04.150891 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 14:47:04.157651 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 14:47:04.160835 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4204 14:47:04.164303 0 9 16 | B1->B0 | 2f2f 2525 | 1 1 | (0 0) (0 0)
4205 14:47:04.170698 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 14:47:04.174203 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 14:47:04.177219 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 14:47:04.184059 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 14:47:04.187243 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 14:47:04.190992 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 14:47:04.197237 0 10 12 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (0 0)
4212 14:47:04.200332 0 10 16 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
4213 14:47:04.203660 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 14:47:04.210051 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 14:47:04.213471 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 14:47:04.217051 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 14:47:04.223513 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 14:47:04.227084 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 14:47:04.229923 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4220 14:47:04.236850 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 14:47:04.239843 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 14:47:04.243093 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 14:47:04.250030 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 14:47:04.253016 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 14:47:04.256595 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 14:47:04.262945 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 14:47:04.266440 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 14:47:04.269785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 14:47:04.276143 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 14:47:04.279579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 14:47:04.282647 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 14:47:04.289327 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 14:47:04.292629 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 14:47:04.296055 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 14:47:04.302630 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4236 14:47:04.305757 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4237 14:47:04.308972 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 14:47:04.312736 Total UI for P1: 0, mck2ui 16
4239 14:47:04.316169 best dqsien dly found for B0: ( 0, 13, 14)
4240 14:47:04.318989 Total UI for P1: 0, mck2ui 16
4241 14:47:04.322306 best dqsien dly found for B1: ( 0, 13, 16)
4242 14:47:04.325541 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4243 14:47:04.329022 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4244 14:47:04.332321
4245 14:47:04.335289 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4246 14:47:04.338793 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4247 14:47:04.342319 [Gating] SW calibration Done
4248 14:47:04.342421 ==
4249 14:47:04.345689 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 14:47:04.348645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 14:47:04.348750 ==
4252 14:47:04.348842 RX Vref Scan: 0
4253 14:47:04.351781
4254 14:47:04.351878 RX Vref 0 -> 0, step: 1
4255 14:47:04.351977
4256 14:47:04.355656 RX Delay -230 -> 252, step: 16
4257 14:47:04.358511 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4258 14:47:04.365227 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4259 14:47:04.368564 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4260 14:47:04.371894 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4261 14:47:04.375370 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4262 14:47:04.381395 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4263 14:47:04.384932 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4264 14:47:04.388085 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4265 14:47:04.391335 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4266 14:47:04.394862 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4267 14:47:04.401164 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4268 14:47:04.404627 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4269 14:47:04.408364 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4270 14:47:04.411336 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4271 14:47:04.417658 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4272 14:47:04.421128 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4273 14:47:04.421220 ==
4274 14:47:04.424702 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 14:47:04.427900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 14:47:04.428008 ==
4277 14:47:04.431519 DQS Delay:
4278 14:47:04.431621 DQS0 = 0, DQS1 = 0
4279 14:47:04.434711 DQM Delay:
4280 14:47:04.434810 DQM0 = 47, DQM1 = 39
4281 14:47:04.434901 DQ Delay:
4282 14:47:04.437552 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4283 14:47:04.440877 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4284 14:47:04.444296 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4285 14:47:04.447716 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4286 14:47:04.447819
4287 14:47:04.447917
4288 14:47:04.450712 ==
4289 14:47:04.450782 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 14:47:04.457350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 14:47:04.457458 ==
4292 14:47:04.457552
4293 14:47:04.457639
4294 14:47:04.460658 TX Vref Scan disable
4295 14:47:04.460754 == TX Byte 0 ==
4296 14:47:04.467526 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4297 14:47:04.470951 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4298 14:47:04.471088 == TX Byte 1 ==
4299 14:47:04.477231 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4300 14:47:04.480371 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4301 14:47:04.480481 ==
4302 14:47:04.483811 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 14:47:04.487097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 14:47:04.487203 ==
4305 14:47:04.487314
4306 14:47:04.487409
4307 14:47:04.490168 TX Vref Scan disable
4308 14:47:04.493914 == TX Byte 0 ==
4309 14:47:04.497255 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4310 14:47:04.500397 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4311 14:47:04.503534 == TX Byte 1 ==
4312 14:47:04.506923 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4313 14:47:04.510433 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4314 14:47:04.513536
4315 14:47:04.513633 [DATLAT]
4316 14:47:04.513723 Freq=600, CH0 RK1
4317 14:47:04.513820
4318 14:47:04.516508 DATLAT Default: 0x9
4319 14:47:04.516602 0, 0xFFFF, sum = 0
4320 14:47:04.520152 1, 0xFFFF, sum = 0
4321 14:47:04.520250 2, 0xFFFF, sum = 0
4322 14:47:04.523689 3, 0xFFFF, sum = 0
4323 14:47:04.523797 4, 0xFFFF, sum = 0
4324 14:47:04.526760 5, 0xFFFF, sum = 0
4325 14:47:04.530096 6, 0xFFFF, sum = 0
4326 14:47:04.530243 7, 0xFFFF, sum = 0
4327 14:47:04.530338 8, 0x0, sum = 1
4328 14:47:04.533404 9, 0x0, sum = 2
4329 14:47:04.533506 10, 0x0, sum = 3
4330 14:47:04.536558 11, 0x0, sum = 4
4331 14:47:04.536655 best_step = 9
4332 14:47:04.536744
4333 14:47:04.536840 ==
4334 14:47:04.540255 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 14:47:04.546515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 14:47:04.546594 ==
4337 14:47:04.546669 RX Vref Scan: 0
4338 14:47:04.546734
4339 14:47:04.549920 RX Vref 0 -> 0, step: 1
4340 14:47:04.550024
4341 14:47:04.553124 RX Delay -195 -> 252, step: 8
4342 14:47:04.556355 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4343 14:47:04.563099 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4344 14:47:04.566488 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4345 14:47:04.569611 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4346 14:47:04.572837 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4347 14:47:04.579730 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4348 14:47:04.582478 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4349 14:47:04.586104 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4350 14:47:04.589319 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4351 14:47:04.592408 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4352 14:47:04.599414 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4353 14:47:04.602743 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4354 14:47:04.605610 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4355 14:47:04.612107 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4356 14:47:04.615976 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4357 14:47:04.619028 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4358 14:47:04.619100 ==
4359 14:47:04.622846 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 14:47:04.625533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 14:47:04.625632 ==
4362 14:47:04.628866 DQS Delay:
4363 14:47:04.628956 DQS0 = 0, DQS1 = 0
4364 14:47:04.632458 DQM Delay:
4365 14:47:04.632558 DQM0 = 41, DQM1 = 36
4366 14:47:04.632658 DQ Delay:
4367 14:47:04.635279 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4368 14:47:04.638881 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4369 14:47:04.642455 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4370 14:47:04.645595 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4371 14:47:04.645694
4372 14:47:04.645784
4373 14:47:04.655586 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4374 14:47:04.658758 CH0 RK1: MR19=808, MR18=5E12
4375 14:47:04.665223 CH0_RK1: MR19=0x808, MR18=0x5E12, DQSOSC=392, MR23=63, INC=170, DEC=113
4376 14:47:04.668664 [RxdqsGatingPostProcess] freq 600
4377 14:47:04.671570 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4378 14:47:04.675085 Pre-setting of DQS Precalculation
4379 14:47:04.681466 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4380 14:47:04.681600 ==
4381 14:47:04.684944 Dram Type= 6, Freq= 0, CH_1, rank 0
4382 14:47:04.688056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 14:47:04.688126 ==
4384 14:47:04.694532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 14:47:04.697725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4386 14:47:04.702080 [CA 0] Center 35 (5~66) winsize 62
4387 14:47:04.705432 [CA 1] Center 35 (5~66) winsize 62
4388 14:47:04.708823 [CA 2] Center 34 (4~65) winsize 62
4389 14:47:04.712121 [CA 3] Center 33 (3~64) winsize 62
4390 14:47:04.715730 [CA 4] Center 34 (4~64) winsize 61
4391 14:47:04.718589 [CA 5] Center 33 (3~64) winsize 62
4392 14:47:04.718659
4393 14:47:04.721815 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4394 14:47:04.721913
4395 14:47:04.725826 [CATrainingPosCal] consider 1 rank data
4396 14:47:04.728866 u2DelayCellTimex100 = 270/100 ps
4397 14:47:04.731643 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4398 14:47:04.739235 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4399 14:47:04.742144 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 14:47:04.745034 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4401 14:47:04.748371 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4402 14:47:04.751512 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 14:47:04.751607
4404 14:47:04.754789 CA PerBit enable=1, Macro0, CA PI delay=33
4405 14:47:04.754865
4406 14:47:04.758448 [CBTSetCACLKResult] CA Dly = 33
4407 14:47:04.761300 CS Dly: 5 (0~36)
4408 14:47:04.761373 ==
4409 14:47:04.764834 Dram Type= 6, Freq= 0, CH_1, rank 1
4410 14:47:04.768647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 14:47:04.768716 ==
4412 14:47:04.775202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4413 14:47:04.778055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4414 14:47:04.782586 [CA 0] Center 36 (6~66) winsize 61
4415 14:47:04.785663 [CA 1] Center 36 (6~66) winsize 61
4416 14:47:04.788905 [CA 2] Center 34 (4~65) winsize 62
4417 14:47:04.792176 [CA 3] Center 34 (3~65) winsize 63
4418 14:47:04.795691 [CA 4] Center 34 (4~65) winsize 62
4419 14:47:04.799187 [CA 5] Center 34 (3~65) winsize 63
4420 14:47:04.799287
4421 14:47:04.802158 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4422 14:47:04.802242
4423 14:47:04.805326 [CATrainingPosCal] consider 2 rank data
4424 14:47:04.808713 u2DelayCellTimex100 = 270/100 ps
4425 14:47:04.811877 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4426 14:47:04.818740 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4427 14:47:04.821895 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 14:47:04.825133 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 14:47:04.828654 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4430 14:47:04.831682 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 14:47:04.831783
4432 14:47:04.835311 CA PerBit enable=1, Macro0, CA PI delay=33
4433 14:47:04.835412
4434 14:47:04.838399 [CBTSetCACLKResult] CA Dly = 33
4435 14:47:04.841488 CS Dly: 5 (0~37)
4436 14:47:04.841591
4437 14:47:04.845000 ----->DramcWriteLeveling(PI) begin...
4438 14:47:04.845100 ==
4439 14:47:04.848018 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 14:47:04.851628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4441 14:47:04.851736 ==
4442 14:47:04.854638 Write leveling (Byte 0): 30 => 30
4443 14:47:04.858373 Write leveling (Byte 1): 30 => 30
4444 14:47:04.861287 DramcWriteLeveling(PI) end<-----
4445 14:47:04.861371
4446 14:47:04.861462 ==
4447 14:47:04.864780 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 14:47:04.867881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 14:47:04.867988 ==
4450 14:47:04.871270 [Gating] SW mode calibration
4451 14:47:04.878327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4452 14:47:04.884375 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4453 14:47:04.888088 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4454 14:47:04.891069 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4455 14:47:04.897588 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4456 14:47:04.901120 0 9 12 | B1->B0 | 3333 2d2d | 0 1 | (0 0) (1 1)
4457 14:47:04.904002 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4458 14:47:04.910500 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 14:47:04.914209 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 14:47:04.917436 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 14:47:04.923831 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 14:47:04.927297 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 14:47:04.933757 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4464 14:47:04.937650 0 10 12 | B1->B0 | 2f2f 3838 | 1 1 | (1 1) (0 0)
4465 14:47:04.940404 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 14:47:04.946781 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 14:47:04.949956 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 14:47:04.953387 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 14:47:04.960143 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 14:47:04.963341 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 14:47:04.966783 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 14:47:04.972971 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4473 14:47:04.976217 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 14:47:04.979729 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 14:47:04.986413 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 14:47:04.989271 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 14:47:04.992915 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 14:47:04.999261 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 14:47:05.002467 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 14:47:05.005778 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 14:47:05.012338 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 14:47:05.015513 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 14:47:05.018637 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 14:47:05.025269 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 14:47:05.028673 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 14:47:05.031936 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 14:47:05.039110 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4488 14:47:05.042467 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4489 14:47:05.045152 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 14:47:05.048229 Total UI for P1: 0, mck2ui 16
4491 14:47:05.051826 best dqsien dly found for B0: ( 0, 13, 10)
4492 14:47:05.055408 Total UI for P1: 0, mck2ui 16
4493 14:47:05.058493 best dqsien dly found for B1: ( 0, 13, 12)
4494 14:47:05.061809 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4495 14:47:05.064775 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4496 14:47:05.068698
4497 14:47:05.071992 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4498 14:47:05.075011 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4499 14:47:05.077793 [Gating] SW calibration Done
4500 14:47:05.077893 ==
4501 14:47:05.081536 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 14:47:05.084443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 14:47:05.084550 ==
4504 14:47:05.087704 RX Vref Scan: 0
4505 14:47:05.087826
4506 14:47:05.087965 RX Vref 0 -> 0, step: 1
4507 14:47:05.088053
4508 14:47:05.091205 RX Delay -230 -> 252, step: 16
4509 14:47:05.094531 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4510 14:47:05.101025 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4511 14:47:05.104314 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4512 14:47:05.107690 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4513 14:47:05.110861 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4514 14:47:05.117744 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4515 14:47:05.120655 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4516 14:47:05.124558 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4517 14:47:05.127264 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4518 14:47:05.130706 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4519 14:47:05.137305 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4520 14:47:05.140649 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4521 14:47:05.143705 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4522 14:47:05.150150 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4523 14:47:05.153898 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4524 14:47:05.156914 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4525 14:47:05.157027 ==
4526 14:47:05.160319 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 14:47:05.163818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 14:47:05.163922 ==
4529 14:47:05.166846 DQS Delay:
4530 14:47:05.166923 DQS0 = 0, DQS1 = 0
4531 14:47:05.170091 DQM Delay:
4532 14:47:05.170226 DQM0 = 45, DQM1 = 36
4533 14:47:05.170293 DQ Delay:
4534 14:47:05.173486 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4535 14:47:05.177036 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4536 14:47:05.180020 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4537 14:47:05.183126 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4538 14:47:05.183203
4539 14:47:05.186583
4540 14:47:05.186688 ==
4541 14:47:05.189729 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 14:47:05.193437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 14:47:05.193513 ==
4544 14:47:05.193576
4545 14:47:05.193672
4546 14:47:05.196367 TX Vref Scan disable
4547 14:47:05.196469 == TX Byte 0 ==
4548 14:47:05.202872 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4549 14:47:05.206179 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4550 14:47:05.206281 == TX Byte 1 ==
4551 14:47:05.213035 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4552 14:47:05.216671 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4553 14:47:05.216776 ==
4554 14:47:05.219511 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 14:47:05.222801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 14:47:05.222911 ==
4557 14:47:05.223002
4558 14:47:05.223091
4559 14:47:05.225743 TX Vref Scan disable
4560 14:47:05.229493 == TX Byte 0 ==
4561 14:47:05.233169 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4562 14:47:05.239097 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4563 14:47:05.239177 == TX Byte 1 ==
4564 14:47:05.242524 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4565 14:47:05.249228 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4566 14:47:05.249337
4567 14:47:05.249429 [DATLAT]
4568 14:47:05.249527 Freq=600, CH1 RK0
4569 14:47:05.249617
4570 14:47:05.252683 DATLAT Default: 0x9
4571 14:47:05.252780 0, 0xFFFF, sum = 0
4572 14:47:05.255799 1, 0xFFFF, sum = 0
4573 14:47:05.259006 2, 0xFFFF, sum = 0
4574 14:47:05.259106 3, 0xFFFF, sum = 0
4575 14:47:05.262409 4, 0xFFFF, sum = 0
4576 14:47:05.262529 5, 0xFFFF, sum = 0
4577 14:47:05.265718 6, 0xFFFF, sum = 0
4578 14:47:05.265825 7, 0xFFFF, sum = 0
4579 14:47:05.268840 8, 0x0, sum = 1
4580 14:47:05.268946 9, 0x0, sum = 2
4581 14:47:05.272125 10, 0x0, sum = 3
4582 14:47:05.272228 11, 0x0, sum = 4
4583 14:47:05.272321 best_step = 9
4584 14:47:05.272419
4585 14:47:05.275566 ==
4586 14:47:05.278687 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 14:47:05.281917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 14:47:05.282014 ==
4589 14:47:05.282108 RX Vref Scan: 1
4590 14:47:05.282232
4591 14:47:05.285315 RX Vref 0 -> 0, step: 1
4592 14:47:05.285389
4593 14:47:05.288471 RX Delay -195 -> 252, step: 8
4594 14:47:05.288572
4595 14:47:05.291630 Set Vref, RX VrefLevel [Byte0]: 52
4596 14:47:05.295035 [Byte1]: 54
4597 14:47:05.295104
4598 14:47:05.298357 Final RX Vref Byte 0 = 52 to rank0
4599 14:47:05.301897 Final RX Vref Byte 1 = 54 to rank0
4600 14:47:05.305193 Final RX Vref Byte 0 = 52 to rank1
4601 14:47:05.308345 Final RX Vref Byte 1 = 54 to rank1==
4602 14:47:05.311805 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 14:47:05.315398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 14:47:05.318312 ==
4605 14:47:05.318395 DQS Delay:
4606 14:47:05.318461 DQS0 = 0, DQS1 = 0
4607 14:47:05.321717 DQM Delay:
4608 14:47:05.321799 DQM0 = 47, DQM1 = 37
4609 14:47:05.324984 DQ Delay:
4610 14:47:05.325065 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4611 14:47:05.328500 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4612 14:47:05.331344 DQ8 =24, DQ9 =28, DQ10 =40, DQ11 =28
4613 14:47:05.335267 DQ12 =48, DQ13 =40, DQ14 =44, DQ15 =48
4614 14:47:05.337983
4615 14:47:05.338085
4616 14:47:05.344746 [DQSOSCAuto] RK0, (LSB)MR18= 0x5035, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4617 14:47:05.347921 CH1 RK0: MR19=808, MR18=5035
4618 14:47:05.354503 CH1_RK0: MR19=0x808, MR18=0x5035, DQSOSC=394, MR23=63, INC=168, DEC=112
4619 14:47:05.354587
4620 14:47:05.358067 ----->DramcWriteLeveling(PI) begin...
4621 14:47:05.358180 ==
4622 14:47:05.361110 Dram Type= 6, Freq= 0, CH_1, rank 1
4623 14:47:05.364586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 14:47:05.364664 ==
4625 14:47:05.368035 Write leveling (Byte 0): 29 => 29
4626 14:47:05.371455 Write leveling (Byte 1): 29 => 29
4627 14:47:05.374633 DramcWriteLeveling(PI) end<-----
4628 14:47:05.374715
4629 14:47:05.374780 ==
4630 14:47:05.377641 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 14:47:05.381364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 14:47:05.381435 ==
4633 14:47:05.384085 [Gating] SW mode calibration
4634 14:47:05.390864 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4635 14:47:05.397600 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4636 14:47:05.401007 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4637 14:47:05.407642 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4638 14:47:05.410658 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4639 14:47:05.414438 0 9 12 | B1->B0 | 3131 3434 | 0 0 | (0 1) (0 0)
4640 14:47:05.420975 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4641 14:47:05.423865 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 14:47:05.427406 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 14:47:05.434525 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 14:47:05.437215 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 14:47:05.440717 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 14:47:05.447370 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 14:47:05.450411 0 10 12 | B1->B0 | 3939 2929 | 0 0 | (0 0) (1 1)
4648 14:47:05.453808 0 10 16 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
4649 14:47:05.460375 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 14:47:05.463912 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 14:47:05.467017 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 14:47:05.473955 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 14:47:05.477503 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 14:47:05.480510 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 14:47:05.487134 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 14:47:05.490518 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 14:47:05.493774 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 14:47:05.500646 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 14:47:05.503507 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 14:47:05.507647 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 14:47:05.513650 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 14:47:05.517044 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 14:47:05.520569 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 14:47:05.526779 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 14:47:05.530199 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 14:47:05.533159 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 14:47:05.539858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 14:47:05.543159 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 14:47:05.546735 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 14:47:05.553062 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4671 14:47:05.556783 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4672 14:47:05.559356 Total UI for P1: 0, mck2ui 16
4673 14:47:05.562962 best dqsien dly found for B1: ( 0, 13, 8)
4674 14:47:05.566228 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 14:47:05.569348 Total UI for P1: 0, mck2ui 16
4676 14:47:05.573026 best dqsien dly found for B0: ( 0, 13, 12)
4677 14:47:05.576272 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4678 14:47:05.579613 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4679 14:47:05.580174
4680 14:47:05.582789 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4681 14:47:05.589469 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4682 14:47:05.589938 [Gating] SW calibration Done
4683 14:47:05.590353 ==
4684 14:47:05.592540 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 14:47:05.599528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 14:47:05.600090 ==
4687 14:47:05.600466 RX Vref Scan: 0
4688 14:47:05.600814
4689 14:47:05.603017 RX Vref 0 -> 0, step: 1
4690 14:47:05.603568
4691 14:47:05.606019 RX Delay -230 -> 252, step: 16
4692 14:47:05.609377 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4693 14:47:05.612601 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4694 14:47:05.619283 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4695 14:47:05.622676 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4696 14:47:05.625558 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4697 14:47:05.629077 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4698 14:47:05.632670 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4699 14:47:05.638999 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4700 14:47:05.642252 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4701 14:47:05.645297 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4702 14:47:05.648967 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4703 14:47:05.655313 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4704 14:47:05.658930 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4705 14:47:05.661795 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4706 14:47:05.665181 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4707 14:47:05.672090 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4708 14:47:05.672647 ==
4709 14:47:05.675204 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 14:47:05.678673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 14:47:05.679230 ==
4712 14:47:05.679602 DQS Delay:
4713 14:47:05.681940 DQS0 = 0, DQS1 = 0
4714 14:47:05.682550 DQM Delay:
4715 14:47:05.685043 DQM0 = 44, DQM1 = 38
4716 14:47:05.685548 DQ Delay:
4717 14:47:05.688364 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4718 14:47:05.691699 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4719 14:47:05.694988 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4720 14:47:05.697970 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4721 14:47:05.698485
4722 14:47:05.698860
4723 14:47:05.699207 ==
4724 14:47:05.701505 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 14:47:05.707616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 14:47:05.708175 ==
4727 14:47:05.708547
4728 14:47:05.708891
4729 14:47:05.709222 TX Vref Scan disable
4730 14:47:05.711494 == TX Byte 0 ==
4731 14:47:05.714454 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4732 14:47:05.721078 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4733 14:47:05.721572 == TX Byte 1 ==
4734 14:47:05.724634 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4735 14:47:05.730998 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4736 14:47:05.731467 ==
4737 14:47:05.734990 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 14:47:05.738041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 14:47:05.738562 ==
4740 14:47:05.738933
4741 14:47:05.739279
4742 14:47:05.741395 TX Vref Scan disable
4743 14:47:05.744777 == TX Byte 0 ==
4744 14:47:05.747737 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4745 14:47:05.750741 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4746 14:47:05.754150 == TX Byte 1 ==
4747 14:47:05.757906 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4748 14:47:05.760741 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4749 14:47:05.761177
4750 14:47:05.761513 [DATLAT]
4751 14:47:05.763710 Freq=600, CH1 RK1
4752 14:47:05.764134
4753 14:47:05.767432 DATLAT Default: 0x9
4754 14:47:05.767945 0, 0xFFFF, sum = 0
4755 14:47:05.771102 1, 0xFFFF, sum = 0
4756 14:47:05.771627 2, 0xFFFF, sum = 0
4757 14:47:05.774131 3, 0xFFFF, sum = 0
4758 14:47:05.774684 4, 0xFFFF, sum = 0
4759 14:47:05.777084 5, 0xFFFF, sum = 0
4760 14:47:05.777604 6, 0xFFFF, sum = 0
4761 14:47:05.781055 7, 0xFFFF, sum = 0
4762 14:47:05.781572 8, 0x0, sum = 1
4763 14:47:05.783999 9, 0x0, sum = 2
4764 14:47:05.784427 10, 0x0, sum = 3
4765 14:47:05.787919 11, 0x0, sum = 4
4766 14:47:05.788439 best_step = 9
4767 14:47:05.788780
4768 14:47:05.789093 ==
4769 14:47:05.790349 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 14:47:05.794537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 14:47:05.795058 ==
4772 14:47:05.796999 RX Vref Scan: 0
4773 14:47:05.797421
4774 14:47:05.800894 RX Vref 0 -> 0, step: 1
4775 14:47:05.801409
4776 14:47:05.801755 RX Delay -195 -> 252, step: 8
4777 14:47:05.808672 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4778 14:47:05.811869 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4779 14:47:05.814873 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4780 14:47:05.818252 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4781 14:47:05.824837 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4782 14:47:05.828216 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4783 14:47:05.831484 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4784 14:47:05.834705 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4785 14:47:05.837886 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4786 14:47:05.844387 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4787 14:47:05.847930 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4788 14:47:05.851344 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4789 14:47:05.854561 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4790 14:47:05.861164 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4791 14:47:05.864599 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4792 14:47:05.867791 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4793 14:47:05.868346 ==
4794 14:47:05.870957 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 14:47:05.877736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 14:47:05.878232 ==
4797 14:47:05.878675 DQS Delay:
4798 14:47:05.879142 DQS0 = 0, DQS1 = 0
4799 14:47:05.880839 DQM Delay:
4800 14:47:05.881295 DQM0 = 45, DQM1 = 37
4801 14:47:05.884724 DQ Delay:
4802 14:47:05.888038 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4803 14:47:05.891231 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4804 14:47:05.893915 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4805 14:47:05.897378 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4806 14:47:05.897843
4807 14:47:05.898427
4808 14:47:05.904280 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4809 14:47:05.907644 CH1 RK1: MR19=808, MR18=2C22
4810 14:47:05.914102 CH1_RK1: MR19=0x808, MR18=0x2C22, DQSOSC=401, MR23=63, INC=163, DEC=108
4811 14:47:05.917394 [RxdqsGatingPostProcess] freq 600
4812 14:47:05.921109 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4813 14:47:05.924010 Pre-setting of DQS Precalculation
4814 14:47:05.930279 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4815 14:47:05.937279 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4816 14:47:05.943670 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4817 14:47:05.944137
4818 14:47:05.944503
4819 14:47:05.946909 [Calibration Summary] 1200 Mbps
4820 14:47:05.947388 CH 0, Rank 0
4821 14:47:05.950266 SW Impedance : PASS
4822 14:47:05.953522 DUTY Scan : NO K
4823 14:47:05.953986 ZQ Calibration : PASS
4824 14:47:05.956760 Jitter Meter : NO K
4825 14:47:05.960145 CBT Training : PASS
4826 14:47:05.960563 Write leveling : PASS
4827 14:47:05.963843 RX DQS gating : PASS
4828 14:47:05.967130 RX DQ/DQS(RDDQC) : PASS
4829 14:47:05.967549 TX DQ/DQS : PASS
4830 14:47:05.969989 RX DATLAT : PASS
4831 14:47:05.973462 RX DQ/DQS(Engine): PASS
4832 14:47:05.973883 TX OE : NO K
4833 14:47:05.976762 All Pass.
4834 14:47:05.977178
4835 14:47:05.977510 CH 0, Rank 1
4836 14:47:05.980494 SW Impedance : PASS
4837 14:47:05.981007 DUTY Scan : NO K
4838 14:47:05.983616 ZQ Calibration : PASS
4839 14:47:05.987295 Jitter Meter : NO K
4840 14:47:05.987715 CBT Training : PASS
4841 14:47:05.990258 Write leveling : PASS
4842 14:47:05.993572 RX DQS gating : PASS
4843 14:47:05.994084 RX DQ/DQS(RDDQC) : PASS
4844 14:47:05.996821 TX DQ/DQS : PASS
4845 14:47:05.997244 RX DATLAT : PASS
4846 14:47:06.000111 RX DQ/DQS(Engine): PASS
4847 14:47:06.003051 TX OE : NO K
4848 14:47:06.003471 All Pass.
4849 14:47:06.003803
4850 14:47:06.004109 CH 1, Rank 0
4851 14:47:06.006753 SW Impedance : PASS
4852 14:47:06.009989 DUTY Scan : NO K
4853 14:47:06.010536 ZQ Calibration : PASS
4854 14:47:06.013287 Jitter Meter : NO K
4855 14:47:06.016456 CBT Training : PASS
4856 14:47:06.016965 Write leveling : PASS
4857 14:47:06.019788 RX DQS gating : PASS
4858 14:47:06.023484 RX DQ/DQS(RDDQC) : PASS
4859 14:47:06.023999 TX DQ/DQS : PASS
4860 14:47:06.026609 RX DATLAT : PASS
4861 14:47:06.029400 RX DQ/DQS(Engine): PASS
4862 14:47:06.029820 TX OE : NO K
4863 14:47:06.032706 All Pass.
4864 14:47:06.033144
4865 14:47:06.033478 CH 1, Rank 1
4866 14:47:06.036409 SW Impedance : PASS
4867 14:47:06.036829 DUTY Scan : NO K
4868 14:47:06.040113 ZQ Calibration : PASS
4869 14:47:06.042519 Jitter Meter : NO K
4870 14:47:06.042940 CBT Training : PASS
4871 14:47:06.046224 Write leveling : PASS
4872 14:47:06.049155 RX DQS gating : PASS
4873 14:47:06.049579 RX DQ/DQS(RDDQC) : PASS
4874 14:47:06.053091 TX DQ/DQS : PASS
4875 14:47:06.056048 RX DATLAT : PASS
4876 14:47:06.056559 RX DQ/DQS(Engine): PASS
4877 14:47:06.059028 TX OE : NO K
4878 14:47:06.059505 All Pass.
4879 14:47:06.059856
4880 14:47:06.062204 DramC Write-DBI off
4881 14:47:06.065575 PER_BANK_REFRESH: Hybrid Mode
4882 14:47:06.066043 TX_TRACKING: ON
4883 14:47:06.075534 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4884 14:47:06.079012 [FAST_K] Save calibration result to emmc
4885 14:47:06.082102 dramc_set_vcore_voltage set vcore to 662500
4886 14:47:06.085656 Read voltage for 933, 3
4887 14:47:06.086254 Vio18 = 0
4888 14:47:06.086634 Vcore = 662500
4889 14:47:06.088723 Vdram = 0
4890 14:47:06.089183 Vddq = 0
4891 14:47:06.089551 Vmddr = 0
4892 14:47:06.095467 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4893 14:47:06.098771 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4894 14:47:06.102304 MEM_TYPE=3, freq_sel=17
4895 14:47:06.105916 sv_algorithm_assistance_LP4_1600
4896 14:47:06.108790 ============ PULL DRAM RESETB DOWN ============
4897 14:47:06.112027 ========== PULL DRAM RESETB DOWN end =========
4898 14:47:06.118665 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4899 14:47:06.122133 ===================================
4900 14:47:06.125029 LPDDR4 DRAM CONFIGURATION
4901 14:47:06.128607 ===================================
4902 14:47:06.129075 EX_ROW_EN[0] = 0x0
4903 14:47:06.131982 EX_ROW_EN[1] = 0x0
4904 14:47:06.132445 LP4Y_EN = 0x0
4905 14:47:06.135340 WORK_FSP = 0x0
4906 14:47:06.135816 WL = 0x3
4907 14:47:06.138240 RL = 0x3
4908 14:47:06.138705 BL = 0x2
4909 14:47:06.141781 RPST = 0x0
4910 14:47:06.142382 RD_PRE = 0x0
4911 14:47:06.145291 WR_PRE = 0x1
4912 14:47:06.145752 WR_PST = 0x0
4913 14:47:06.148388 DBI_WR = 0x0
4914 14:47:06.148952 DBI_RD = 0x0
4915 14:47:06.151561 OTF = 0x1
4916 14:47:06.154794 ===================================
4917 14:47:06.158612 ===================================
4918 14:47:06.159076 ANA top config
4919 14:47:06.161452 ===================================
4920 14:47:06.165135 DLL_ASYNC_EN = 0
4921 14:47:06.168385 ALL_SLAVE_EN = 1
4922 14:47:06.171390 NEW_RANK_MODE = 1
4923 14:47:06.171864 DLL_IDLE_MODE = 1
4924 14:47:06.174540 LP45_APHY_COMB_EN = 1
4925 14:47:06.178041 TX_ODT_DIS = 1
4926 14:47:06.181375 NEW_8X_MODE = 1
4927 14:47:06.184620 ===================================
4928 14:47:06.188125 ===================================
4929 14:47:06.191285 data_rate = 1866
4930 14:47:06.194486 CKR = 1
4931 14:47:06.194950 DQ_P2S_RATIO = 8
4932 14:47:06.198118 ===================================
4933 14:47:06.201052 CA_P2S_RATIO = 8
4934 14:47:06.204552 DQ_CA_OPEN = 0
4935 14:47:06.207770 DQ_SEMI_OPEN = 0
4936 14:47:06.210864 CA_SEMI_OPEN = 0
4937 14:47:06.214480 CA_FULL_RATE = 0
4938 14:47:06.215041 DQ_CKDIV4_EN = 1
4939 14:47:06.217138 CA_CKDIV4_EN = 1
4940 14:47:06.220470 CA_PREDIV_EN = 0
4941 14:47:06.223989 PH8_DLY = 0
4942 14:47:06.227630 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4943 14:47:06.231133 DQ_AAMCK_DIV = 4
4944 14:47:06.233997 CA_AAMCK_DIV = 4
4945 14:47:06.234596 CA_ADMCK_DIV = 4
4946 14:47:06.236845 DQ_TRACK_CA_EN = 0
4947 14:47:06.240439 CA_PICK = 933
4948 14:47:06.243641 CA_MCKIO = 933
4949 14:47:06.247546 MCKIO_SEMI = 0
4950 14:47:06.250799 PLL_FREQ = 3732
4951 14:47:06.254141 DQ_UI_PI_RATIO = 32
4952 14:47:06.254751 CA_UI_PI_RATIO = 0
4953 14:47:06.257488 ===================================
4954 14:47:06.260184 ===================================
4955 14:47:06.263322 memory_type:LPDDR4
4956 14:47:06.266957 GP_NUM : 10
4957 14:47:06.267425 SRAM_EN : 1
4958 14:47:06.270573 MD32_EN : 0
4959 14:47:06.273435 ===================================
4960 14:47:06.276621 [ANA_INIT] >>>>>>>>>>>>>>
4961 14:47:06.280152 <<<<<< [CONFIGURE PHASE]: ANA_TX
4962 14:47:06.283524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4963 14:47:06.286511 ===================================
4964 14:47:06.286979 data_rate = 1866,PCW = 0X8f00
4965 14:47:06.289701 ===================================
4966 14:47:06.293777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4967 14:47:06.299750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4968 14:47:06.306802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4969 14:47:06.310639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4970 14:47:06.313074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4971 14:47:06.316508 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4972 14:47:06.319806 [ANA_INIT] flow start
4973 14:47:06.322893 [ANA_INIT] PLL >>>>>>>>
4974 14:47:06.323354 [ANA_INIT] PLL <<<<<<<<
4975 14:47:06.326635 [ANA_INIT] MIDPI >>>>>>>>
4976 14:47:06.329578 [ANA_INIT] MIDPI <<<<<<<<
4977 14:47:06.330042 [ANA_INIT] DLL >>>>>>>>
4978 14:47:06.332919 [ANA_INIT] flow end
4979 14:47:06.335805 ============ LP4 DIFF to SE enter ============
4980 14:47:06.342620 ============ LP4 DIFF to SE exit ============
4981 14:47:06.343050 [ANA_INIT] <<<<<<<<<<<<<
4982 14:47:06.345622 [Flow] Enable top DCM control >>>>>
4983 14:47:06.349033 [Flow] Enable top DCM control <<<<<
4984 14:47:06.352498 Enable DLL master slave shuffle
4985 14:47:06.359188 ==============================================================
4986 14:47:06.359610 Gating Mode config
4987 14:47:06.365917 ==============================================================
4988 14:47:06.369137 Config description:
4989 14:47:06.375633 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4990 14:47:06.382242 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4991 14:47:06.388825 SELPH_MODE 0: By rank 1: By Phase
4992 14:47:06.395264 ==============================================================
4993 14:47:06.398828 GAT_TRACK_EN = 1
4994 14:47:06.399251 RX_GATING_MODE = 2
4995 14:47:06.402042 RX_GATING_TRACK_MODE = 2
4996 14:47:06.405637 SELPH_MODE = 1
4997 14:47:06.408761 PICG_EARLY_EN = 1
4998 14:47:06.411734 VALID_LAT_VALUE = 1
4999 14:47:06.418351 ==============================================================
5000 14:47:06.422123 Enter into Gating configuration >>>>
5001 14:47:06.424994 Exit from Gating configuration <<<<
5002 14:47:06.428447 Enter into DVFS_PRE_config >>>>>
5003 14:47:06.438003 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5004 14:47:06.441529 Exit from DVFS_PRE_config <<<<<
5005 14:47:06.445173 Enter into PICG configuration >>>>
5006 14:47:06.448123 Exit from PICG configuration <<<<
5007 14:47:06.451362 [RX_INPUT] configuration >>>>>
5008 14:47:06.454830 [RX_INPUT] configuration <<<<<
5009 14:47:06.458057 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5010 14:47:06.464566 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5011 14:47:06.471301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5012 14:47:06.477485 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5013 14:47:06.484147 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5014 14:47:06.488106 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5015 14:47:06.494015 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5016 14:47:06.497996 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5017 14:47:06.500590 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5018 14:47:06.504558 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5019 14:47:06.510883 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5020 14:47:06.514325 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5021 14:47:06.517674 ===================================
5022 14:47:06.520569 LPDDR4 DRAM CONFIGURATION
5023 14:47:06.524163 ===================================
5024 14:47:06.524680 EX_ROW_EN[0] = 0x0
5025 14:47:06.527245 EX_ROW_EN[1] = 0x0
5026 14:47:06.527659 LP4Y_EN = 0x0
5027 14:47:06.531086 WORK_FSP = 0x0
5028 14:47:06.531505 WL = 0x3
5029 14:47:06.533888 RL = 0x3
5030 14:47:06.534430 BL = 0x2
5031 14:47:06.537375 RPST = 0x0
5032 14:47:06.537795 RD_PRE = 0x0
5033 14:47:06.540226 WR_PRE = 0x1
5034 14:47:06.543940 WR_PST = 0x0
5035 14:47:06.544358 DBI_WR = 0x0
5036 14:47:06.547052 DBI_RD = 0x0
5037 14:47:06.547469 OTF = 0x1
5038 14:47:06.550038 ===================================
5039 14:47:06.554572 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5040 14:47:06.560262 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5041 14:47:06.563702 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5042 14:47:06.566938 ===================================
5043 14:47:06.570719 LPDDR4 DRAM CONFIGURATION
5044 14:47:06.573572 ===================================
5045 14:47:06.573990 EX_ROW_EN[0] = 0x10
5046 14:47:06.576844 EX_ROW_EN[1] = 0x0
5047 14:47:06.577260 LP4Y_EN = 0x0
5048 14:47:06.579783 WORK_FSP = 0x0
5049 14:47:06.580201 WL = 0x3
5050 14:47:06.583046 RL = 0x3
5051 14:47:06.583465 BL = 0x2
5052 14:47:06.586630 RPST = 0x0
5053 14:47:06.589901 RD_PRE = 0x0
5054 14:47:06.590361 WR_PRE = 0x1
5055 14:47:06.592966 WR_PST = 0x0
5056 14:47:06.593383 DBI_WR = 0x0
5057 14:47:06.597110 DBI_RD = 0x0
5058 14:47:06.597639 OTF = 0x1
5059 14:47:06.599636 ===================================
5060 14:47:06.606889 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5061 14:47:06.610074 nWR fixed to 30
5062 14:47:06.613269 [ModeRegInit_LP4] CH0 RK0
5063 14:47:06.613687 [ModeRegInit_LP4] CH0 RK1
5064 14:47:06.616554 [ModeRegInit_LP4] CH1 RK0
5065 14:47:06.620083 [ModeRegInit_LP4] CH1 RK1
5066 14:47:06.620594 match AC timing 9
5067 14:47:06.626412 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5068 14:47:06.630319 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5069 14:47:06.633131 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5070 14:47:06.639661 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5071 14:47:06.642830 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5072 14:47:06.643250 ==
5073 14:47:06.646765 Dram Type= 6, Freq= 0, CH_0, rank 0
5074 14:47:06.650291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 14:47:06.650893 ==
5076 14:47:06.656715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5077 14:47:06.662790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5078 14:47:06.666531 [CA 0] Center 37 (7~68) winsize 62
5079 14:47:06.669467 [CA 1] Center 37 (7~68) winsize 62
5080 14:47:06.673241 [CA 2] Center 34 (4~65) winsize 62
5081 14:47:06.676352 [CA 3] Center 34 (4~65) winsize 62
5082 14:47:06.679655 [CA 4] Center 33 (3~64) winsize 62
5083 14:47:06.682686 [CA 5] Center 33 (3~63) winsize 61
5084 14:47:06.683152
5085 14:47:06.686132 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5086 14:47:06.686579
5087 14:47:06.689364 [CATrainingPosCal] consider 1 rank data
5088 14:47:06.693004 u2DelayCellTimex100 = 270/100 ps
5089 14:47:06.696443 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5090 14:47:06.699495 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5091 14:47:06.702768 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5092 14:47:06.705885 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5093 14:47:06.712834 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5094 14:47:06.716055 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5095 14:47:06.716520
5096 14:47:06.719178 CA PerBit enable=1, Macro0, CA PI delay=33
5097 14:47:06.719596
5098 14:47:06.722611 [CBTSetCACLKResult] CA Dly = 33
5099 14:47:06.723029 CS Dly: 7 (0~38)
5100 14:47:06.723362 ==
5101 14:47:06.725832 Dram Type= 6, Freq= 0, CH_0, rank 1
5102 14:47:06.732186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 14:47:06.732719 ==
5104 14:47:06.735778 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5105 14:47:06.742144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5106 14:47:06.745427 [CA 0] Center 37 (7~68) winsize 62
5107 14:47:06.748809 [CA 1] Center 37 (7~68) winsize 62
5108 14:47:06.752140 [CA 2] Center 34 (4~65) winsize 62
5109 14:47:06.755704 [CA 3] Center 34 (4~65) winsize 62
5110 14:47:06.758601 [CA 4] Center 33 (3~64) winsize 62
5111 14:47:06.761706 [CA 5] Center 33 (3~63) winsize 61
5112 14:47:06.762125
5113 14:47:06.765462 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5114 14:47:06.765975
5115 14:47:06.768530 [CATrainingPosCal] consider 2 rank data
5116 14:47:06.771744 u2DelayCellTimex100 = 270/100 ps
5117 14:47:06.775524 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5118 14:47:06.781843 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5119 14:47:06.784933 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5120 14:47:06.788422 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5121 14:47:06.791459 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5122 14:47:06.795116 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5123 14:47:06.795626
5124 14:47:06.798292 CA PerBit enable=1, Macro0, CA PI delay=33
5125 14:47:06.798865
5126 14:47:06.801780 [CBTSetCACLKResult] CA Dly = 33
5127 14:47:06.802221 CS Dly: 7 (0~39)
5128 14:47:06.805040
5129 14:47:06.808627 ----->DramcWriteLeveling(PI) begin...
5130 14:47:06.809145 ==
5131 14:47:06.811317 Dram Type= 6, Freq= 0, CH_0, rank 0
5132 14:47:06.815143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 14:47:06.815663 ==
5134 14:47:06.817823 Write leveling (Byte 0): 30 => 30
5135 14:47:06.821238 Write leveling (Byte 1): 28 => 28
5136 14:47:06.824300 DramcWriteLeveling(PI) end<-----
5137 14:47:06.824718
5138 14:47:06.825050 ==
5139 14:47:06.827997 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 14:47:06.831355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 14:47:06.831777 ==
5142 14:47:06.834451 [Gating] SW mode calibration
5143 14:47:06.840864 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5144 14:47:06.847450 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5145 14:47:06.851579 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5146 14:47:06.853858 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5147 14:47:06.860681 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 14:47:06.863887 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 14:47:06.867641 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 14:47:06.874180 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 14:47:06.877382 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 14:47:06.880642 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5153 14:47:06.887215 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5154 14:47:06.890326 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5155 14:47:06.893613 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 14:47:06.900188 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 14:47:06.903548 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 14:47:06.906959 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 14:47:06.913427 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 14:47:06.916591 0 15 28 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
5161 14:47:06.920381 1 0 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5162 14:47:06.926701 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 14:47:06.930013 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 14:47:06.932866 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 14:47:06.939617 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 14:47:06.942786 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 14:47:06.946190 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 14:47:06.952764 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5169 14:47:06.956192 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5170 14:47:06.959490 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 14:47:06.965962 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 14:47:06.969200 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 14:47:06.976184 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 14:47:06.978873 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 14:47:06.982748 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 14:47:06.989277 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 14:47:06.992499 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 14:47:06.995673 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 14:47:06.999123 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 14:47:07.005917 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 14:47:07.009004 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 14:47:07.015811 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 14:47:07.018789 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 14:47:07.021940 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5185 14:47:07.028461 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5186 14:47:07.029003 Total UI for P1: 0, mck2ui 16
5187 14:47:07.031914 best dqsien dly found for B0: ( 1, 2, 28)
5188 14:47:07.038414 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 14:47:07.041646 Total UI for P1: 0, mck2ui 16
5190 14:47:07.045184 best dqsien dly found for B1: ( 1, 3, 0)
5191 14:47:07.048591 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5192 14:47:07.051364 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5193 14:47:07.051828
5194 14:47:07.054757 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5195 14:47:07.058058 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5196 14:47:07.061368 [Gating] SW calibration Done
5197 14:47:07.061828 ==
5198 14:47:07.064909 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 14:47:07.067893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 14:47:07.068392 ==
5201 14:47:07.071313 RX Vref Scan: 0
5202 14:47:07.071775
5203 14:47:07.074788 RX Vref 0 -> 0, step: 1
5204 14:47:07.075253
5205 14:47:07.075619 RX Delay -80 -> 252, step: 8
5206 14:47:07.081276 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5207 14:47:07.084835 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5208 14:47:07.088101 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5209 14:47:07.091149 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5210 14:47:07.094750 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5211 14:47:07.098030 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5212 14:47:07.104581 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5213 14:47:07.108002 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5214 14:47:07.110846 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5215 14:47:07.114988 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5216 14:47:07.117597 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5217 14:47:07.124713 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5218 14:47:07.127575 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5219 14:47:07.130588 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5220 14:47:07.134128 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5221 14:47:07.137062 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5222 14:47:07.140406 ==
5223 14:47:07.143848 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 14:47:07.147106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 14:47:07.147573 ==
5226 14:47:07.147940 DQS Delay:
5227 14:47:07.150625 DQS0 = 0, DQS1 = 0
5228 14:47:07.151085 DQM Delay:
5229 14:47:07.153856 DQM0 = 98, DQM1 = 86
5230 14:47:07.154352 DQ Delay:
5231 14:47:07.157247 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5232 14:47:07.160708 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5233 14:47:07.163461 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5234 14:47:07.167928 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5235 14:47:07.168479
5236 14:47:07.168839
5237 14:47:07.169174 ==
5238 14:47:07.170410 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 14:47:07.173405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 14:47:07.173869 ==
5241 14:47:07.174268
5242 14:47:07.174609
5243 14:47:07.176556 TX Vref Scan disable
5244 14:47:07.179963 == TX Byte 0 ==
5245 14:47:07.183299 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5246 14:47:07.186676 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5247 14:47:07.189888 == TX Byte 1 ==
5248 14:47:07.193551 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5249 14:47:07.196512 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5250 14:47:07.197029 ==
5251 14:47:07.200216 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 14:47:07.206675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 14:47:07.207173 ==
5254 14:47:07.207503
5255 14:47:07.207806
5256 14:47:07.208184 TX Vref Scan disable
5257 14:47:07.210565 == TX Byte 0 ==
5258 14:47:07.214637 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5259 14:47:07.220851 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5260 14:47:07.221359 == TX Byte 1 ==
5261 14:47:07.223551 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5262 14:47:07.230341 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5263 14:47:07.230892
5264 14:47:07.231258 [DATLAT]
5265 14:47:07.231600 Freq=933, CH0 RK0
5266 14:47:07.231931
5267 14:47:07.233723 DATLAT Default: 0xd
5268 14:47:07.237262 0, 0xFFFF, sum = 0
5269 14:47:07.237823 1, 0xFFFF, sum = 0
5270 14:47:07.240143 2, 0xFFFF, sum = 0
5271 14:47:07.240613 3, 0xFFFF, sum = 0
5272 14:47:07.243925 4, 0xFFFF, sum = 0
5273 14:47:07.244395 5, 0xFFFF, sum = 0
5274 14:47:07.246926 6, 0xFFFF, sum = 0
5275 14:47:07.247426 7, 0xFFFF, sum = 0
5276 14:47:07.250314 8, 0xFFFF, sum = 0
5277 14:47:07.250781 9, 0xFFFF, sum = 0
5278 14:47:07.253369 10, 0x0, sum = 1
5279 14:47:07.253875 11, 0x0, sum = 2
5280 14:47:07.256842 12, 0x0, sum = 3
5281 14:47:07.257306 13, 0x0, sum = 4
5282 14:47:07.257674 best_step = 11
5283 14:47:07.259890
5284 14:47:07.260345 ==
5285 14:47:07.263238 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 14:47:07.266629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 14:47:07.267073 ==
5288 14:47:07.267402 RX Vref Scan: 1
5289 14:47:07.267709
5290 14:47:07.270345 RX Vref 0 -> 0, step: 1
5291 14:47:07.270762
5292 14:47:07.273270 RX Delay -61 -> 252, step: 4
5293 14:47:07.273682
5294 14:47:07.276546 Set Vref, RX VrefLevel [Byte0]: 59
5295 14:47:07.279897 [Byte1]: 50
5296 14:47:07.282987
5297 14:47:07.283415 Final RX Vref Byte 0 = 59 to rank0
5298 14:47:07.286600 Final RX Vref Byte 1 = 50 to rank0
5299 14:47:07.289786 Final RX Vref Byte 0 = 59 to rank1
5300 14:47:07.292840 Final RX Vref Byte 1 = 50 to rank1==
5301 14:47:07.296393 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 14:47:07.303513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 14:47:07.303915 ==
5304 14:47:07.304154 DQS Delay:
5305 14:47:07.305869 DQS0 = 0, DQS1 = 0
5306 14:47:07.306176 DQM Delay:
5307 14:47:07.306425 DQM0 = 96, DQM1 = 85
5308 14:47:07.309774 DQ Delay:
5309 14:47:07.312526 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5310 14:47:07.315732 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5311 14:47:07.319370 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5312 14:47:07.322203 DQ12 =90, DQ13 =86, DQ14 =98, DQ15 =90
5313 14:47:07.322497
5314 14:47:07.322726
5315 14:47:07.329595 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5316 14:47:07.332300 CH0 RK0: MR19=505, MR18=2A11
5317 14:47:07.339447 CH0_RK0: MR19=0x505, MR18=0x2A11, DQSOSC=408, MR23=63, INC=65, DEC=43
5318 14:47:07.339904
5319 14:47:07.342095 ----->DramcWriteLeveling(PI) begin...
5320 14:47:07.342796 ==
5321 14:47:07.345648 Dram Type= 6, Freq= 0, CH_0, rank 1
5322 14:47:07.348658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 14:47:07.349071 ==
5324 14:47:07.352280 Write leveling (Byte 0): 34 => 34
5325 14:47:07.355905 Write leveling (Byte 1): 30 => 30
5326 14:47:07.358651 DramcWriteLeveling(PI) end<-----
5327 14:47:07.359068
5328 14:47:07.359400 ==
5329 14:47:07.362405 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 14:47:07.368795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 14:47:07.369349 ==
5332 14:47:07.369709 [Gating] SW mode calibration
5333 14:47:07.378864 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5334 14:47:07.382050 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5335 14:47:07.385624 0 14 0 | B1->B0 | 2a2a 3433 | 0 1 | (0 0) (0 0)
5336 14:47:07.391919 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 14:47:07.395341 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 14:47:07.398769 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 14:47:07.405080 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 14:47:07.408229 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 14:47:07.411360 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 14:47:07.418056 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5343 14:47:07.421515 0 15 0 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (1 0)
5344 14:47:07.424877 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 14:47:07.431216 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 14:47:07.434788 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 14:47:07.438082 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 14:47:07.444432 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 14:47:07.448062 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 14:47:07.454275 0 15 28 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
5351 14:47:07.457583 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5352 14:47:07.460782 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 14:47:07.467608 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 14:47:07.470587 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 14:47:07.474483 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 14:47:07.480838 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 14:47:07.484237 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 14:47:07.487153 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5359 14:47:07.493907 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5360 14:47:07.497647 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 14:47:07.500663 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 14:47:07.506847 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 14:47:07.510546 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 14:47:07.514044 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 14:47:07.517120 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 14:47:07.523893 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 14:47:07.527107 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 14:47:07.533310 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 14:47:07.536759 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 14:47:07.540161 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 14:47:07.546522 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 14:47:07.549661 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 14:47:07.553184 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 14:47:07.559671 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5375 14:47:07.563139 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5376 14:47:07.566308 Total UI for P1: 0, mck2ui 16
5377 14:47:07.569859 best dqsien dly found for B0: ( 1, 2, 28)
5378 14:47:07.572811 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 14:47:07.576125 Total UI for P1: 0, mck2ui 16
5380 14:47:07.579597 best dqsien dly found for B1: ( 1, 2, 30)
5381 14:47:07.582725 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5382 14:47:07.585736 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5383 14:47:07.586155
5384 14:47:07.592446 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5385 14:47:07.596324 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5386 14:47:07.596864 [Gating] SW calibration Done
5387 14:47:07.599510 ==
5388 14:47:07.602803 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 14:47:07.605769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 14:47:07.606221 ==
5391 14:47:07.606563 RX Vref Scan: 0
5392 14:47:07.606873
5393 14:47:07.608825 RX Vref 0 -> 0, step: 1
5394 14:47:07.609273
5395 14:47:07.611937 RX Delay -80 -> 252, step: 8
5396 14:47:07.615168 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5397 14:47:07.618702 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5398 14:47:07.622067 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5399 14:47:07.628623 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5400 14:47:07.631913 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5401 14:47:07.635148 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5402 14:47:07.638542 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5403 14:47:07.641968 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5404 14:47:07.644956 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5405 14:47:07.651642 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5406 14:47:07.655023 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5407 14:47:07.658640 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5408 14:47:07.661625 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5409 14:47:07.668370 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5410 14:47:07.671944 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5411 14:47:07.675030 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5412 14:47:07.675453 ==
5413 14:47:07.678076 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 14:47:07.682034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 14:47:07.682586 ==
5416 14:47:07.684870 DQS Delay:
5417 14:47:07.685289 DQS0 = 0, DQS1 = 0
5418 14:47:07.688046 DQM Delay:
5419 14:47:07.688466 DQM0 = 96, DQM1 = 87
5420 14:47:07.688799 DQ Delay:
5421 14:47:07.690975 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5422 14:47:07.694473 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5423 14:47:07.697571 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5424 14:47:07.701255 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5425 14:47:07.701678
5426 14:47:07.702009
5427 14:47:07.704179 ==
5428 14:47:07.708072 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 14:47:07.710849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 14:47:07.711273 ==
5431 14:47:07.711602
5432 14:47:07.711908
5433 14:47:07.714140 TX Vref Scan disable
5434 14:47:07.714606 == TX Byte 0 ==
5435 14:47:07.720792 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5436 14:47:07.723994 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5437 14:47:07.724416 == TX Byte 1 ==
5438 14:47:07.730282 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5439 14:47:07.733975 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5440 14:47:07.734490 ==
5441 14:47:07.737087 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 14:47:07.740387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 14:47:07.740808 ==
5444 14:47:07.741139
5445 14:47:07.741444
5446 14:47:07.743643 TX Vref Scan disable
5447 14:47:07.747149 == TX Byte 0 ==
5448 14:47:07.750263 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5449 14:47:07.753393 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5450 14:47:07.756838 == TX Byte 1 ==
5451 14:47:07.759973 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5452 14:47:07.763693 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5453 14:47:07.764150
5454 14:47:07.766991 [DATLAT]
5455 14:47:07.767411 Freq=933, CH0 RK1
5456 14:47:07.767745
5457 14:47:07.769944 DATLAT Default: 0xb
5458 14:47:07.770409 0, 0xFFFF, sum = 0
5459 14:47:07.773849 1, 0xFFFF, sum = 0
5460 14:47:07.774314 2, 0xFFFF, sum = 0
5461 14:47:07.776761 3, 0xFFFF, sum = 0
5462 14:47:07.777183 4, 0xFFFF, sum = 0
5463 14:47:07.780003 5, 0xFFFF, sum = 0
5464 14:47:07.780518 6, 0xFFFF, sum = 0
5465 14:47:07.783211 7, 0xFFFF, sum = 0
5466 14:47:07.786606 8, 0xFFFF, sum = 0
5467 14:47:07.787172 9, 0xFFFF, sum = 0
5468 14:47:07.790389 10, 0x0, sum = 1
5469 14:47:07.790834 11, 0x0, sum = 2
5470 14:47:07.791334 12, 0x0, sum = 3
5471 14:47:07.793401 13, 0x0, sum = 4
5472 14:47:07.793701 best_step = 11
5473 14:47:07.793934
5474 14:47:07.796485 ==
5475 14:47:07.796780 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 14:47:07.803262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 14:47:07.803488 ==
5478 14:47:07.803666 RX Vref Scan: 0
5479 14:47:07.803834
5480 14:47:07.806107 RX Vref 0 -> 0, step: 1
5481 14:47:07.806359
5482 14:47:07.809581 RX Delay -61 -> 252, step: 4
5483 14:47:07.812792 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5484 14:47:07.819650 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5485 14:47:07.823186 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5486 14:47:07.826407 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5487 14:47:07.829589 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5488 14:47:07.832565 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5489 14:47:07.836008 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5490 14:47:07.842797 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5491 14:47:07.846357 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5492 14:47:07.849066 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5493 14:47:07.852500 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5494 14:47:07.855832 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5495 14:47:07.862389 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5496 14:47:07.865526 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5497 14:47:07.868946 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5498 14:47:07.872619 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5499 14:47:07.872846 ==
5500 14:47:07.875786 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 14:47:07.882086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 14:47:07.882338 ==
5503 14:47:07.882517 DQS Delay:
5504 14:47:07.885721 DQS0 = 0, DQS1 = 0
5505 14:47:07.885944 DQM Delay:
5506 14:47:07.886120 DQM0 = 95, DQM1 = 86
5507 14:47:07.888879 DQ Delay:
5508 14:47:07.891969 DQ0 =94, DQ1 =96, DQ2 =88, DQ3 =92
5509 14:47:07.895668 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5510 14:47:07.898528 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =78
5511 14:47:07.901748 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5512 14:47:07.901973
5513 14:47:07.902147
5514 14:47:07.908422 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5515 14:47:07.911495 CH0 RK1: MR19=504, MR18=28F9
5516 14:47:07.918365 CH0_RK1: MR19=0x504, MR18=0x28F9, DQSOSC=409, MR23=63, INC=64, DEC=43
5517 14:47:07.921900 [RxdqsGatingPostProcess] freq 933
5518 14:47:07.927922 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5519 14:47:07.928002 best DQS0 dly(2T, 0.5T) = (0, 10)
5520 14:47:07.931351 best DQS1 dly(2T, 0.5T) = (0, 11)
5521 14:47:07.935130 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5522 14:47:07.938167 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5523 14:47:07.941616 best DQS0 dly(2T, 0.5T) = (0, 10)
5524 14:47:07.944893 best DQS1 dly(2T, 0.5T) = (0, 10)
5525 14:47:07.948472 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5526 14:47:07.951161 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5527 14:47:07.954967 Pre-setting of DQS Precalculation
5528 14:47:07.960932 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5529 14:47:07.961043 ==
5530 14:47:07.964491 Dram Type= 6, Freq= 0, CH_1, rank 0
5531 14:47:07.967594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 14:47:07.967705 ==
5533 14:47:07.974249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 14:47:07.977648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5535 14:47:07.982094 [CA 0] Center 36 (6~67) winsize 62
5536 14:47:07.985027 [CA 1] Center 37 (6~68) winsize 63
5537 14:47:07.988440 [CA 2] Center 34 (4~65) winsize 62
5538 14:47:07.991581 [CA 3] Center 33 (3~64) winsize 62
5539 14:47:07.994970 [CA 4] Center 34 (4~64) winsize 61
5540 14:47:07.998145 [CA 5] Center 33 (3~64) winsize 62
5541 14:47:07.998405
5542 14:47:08.001762 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5543 14:47:08.001999
5544 14:47:08.005274 [CATrainingPosCal] consider 1 rank data
5545 14:47:08.008257 u2DelayCellTimex100 = 270/100 ps
5546 14:47:08.011525 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5547 14:47:08.018295 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5548 14:47:08.021526 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5549 14:47:08.024650 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5550 14:47:08.028079 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5551 14:47:08.031776 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5552 14:47:08.032294
5553 14:47:08.034866 CA PerBit enable=1, Macro0, CA PI delay=33
5554 14:47:08.035287
5555 14:47:08.038239 [CBTSetCACLKResult] CA Dly = 33
5556 14:47:08.041624 CS Dly: 5 (0~36)
5557 14:47:08.042035 ==
5558 14:47:08.044840 Dram Type= 6, Freq= 0, CH_1, rank 1
5559 14:47:08.047845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 14:47:08.048259 ==
5561 14:47:08.054453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5562 14:47:08.057963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5563 14:47:08.061804 [CA 0] Center 36 (6~67) winsize 62
5564 14:47:08.065304 [CA 1] Center 37 (7~67) winsize 61
5565 14:47:08.068853 [CA 2] Center 34 (4~65) winsize 62
5566 14:47:08.071681 [CA 3] Center 33 (3~64) winsize 62
5567 14:47:08.075099 [CA 4] Center 34 (3~65) winsize 63
5568 14:47:08.078119 [CA 5] Center 33 (3~64) winsize 62
5569 14:47:08.078666
5570 14:47:08.081497 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5571 14:47:08.081959
5572 14:47:08.084651 [CATrainingPosCal] consider 2 rank data
5573 14:47:08.088245 u2DelayCellTimex100 = 270/100 ps
5574 14:47:08.091559 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5575 14:47:08.098262 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5576 14:47:08.101235 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5577 14:47:08.104957 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5578 14:47:08.108193 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5579 14:47:08.111731 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5580 14:47:08.112227
5581 14:47:08.114841 CA PerBit enable=1, Macro0, CA PI delay=33
5582 14:47:08.115256
5583 14:47:08.118204 [CBTSetCACLKResult] CA Dly = 33
5584 14:47:08.121408 CS Dly: 6 (0~39)
5585 14:47:08.121835
5586 14:47:08.124514 ----->DramcWriteLeveling(PI) begin...
5587 14:47:08.124979 ==
5588 14:47:08.127891 Dram Type= 6, Freq= 0, CH_1, rank 0
5589 14:47:08.131032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 14:47:08.131521 ==
5591 14:47:08.134325 Write leveling (Byte 0): 25 => 25
5592 14:47:08.137754 Write leveling (Byte 1): 26 => 26
5593 14:47:08.140682 DramcWriteLeveling(PI) end<-----
5594 14:47:08.140977
5595 14:47:08.141210 ==
5596 14:47:08.144315 Dram Type= 6, Freq= 0, CH_1, rank 0
5597 14:47:08.147960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5598 14:47:08.148383 ==
5599 14:47:08.151123 [Gating] SW mode calibration
5600 14:47:08.157358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5601 14:47:08.164064 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5602 14:47:08.168186 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 14:47:08.171273 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 14:47:08.177446 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 14:47:08.180606 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 14:47:08.183994 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 14:47:08.191048 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 14:47:08.193774 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5609 14:47:08.197204 0 14 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
5610 14:47:08.204362 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 14:47:08.206869 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 14:47:08.210099 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 14:47:08.217188 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 14:47:08.220125 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 14:47:08.223526 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 14:47:08.230215 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5617 14:47:08.233293 0 15 28 | B1->B0 | 3737 3c3c | 0 1 | (0 0) (0 0)
5618 14:47:08.236338 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5619 14:47:08.242975 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 14:47:08.245925 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 14:47:08.249391 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 14:47:08.255890 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 14:47:08.259325 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 14:47:08.262496 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5625 14:47:08.269068 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5626 14:47:08.272442 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 14:47:08.275590 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 14:47:08.282340 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 14:47:08.285589 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 14:47:08.288818 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 14:47:08.295509 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 14:47:08.298559 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 14:47:08.305508 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 14:47:08.308464 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 14:47:08.312148 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 14:47:08.315086 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 14:47:08.322028 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 14:47:08.324928 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 14:47:08.328612 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 14:47:08.334989 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5641 14:47:08.338391 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5642 14:47:08.341841 Total UI for P1: 0, mck2ui 16
5643 14:47:08.344830 best dqsien dly found for B0: ( 1, 2, 24)
5644 14:47:08.347926 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 14:47:08.351947 Total UI for P1: 0, mck2ui 16
5646 14:47:08.354761 best dqsien dly found for B1: ( 1, 2, 28)
5647 14:47:08.358327 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5648 14:47:08.364748 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5649 14:47:08.364831
5650 14:47:08.368444 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5651 14:47:08.371452 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5652 14:47:08.374755 [Gating] SW calibration Done
5653 14:47:08.374836 ==
5654 14:47:08.378380 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 14:47:08.380981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 14:47:08.381064 ==
5657 14:47:08.384444 RX Vref Scan: 0
5658 14:47:08.384528
5659 14:47:08.384613 RX Vref 0 -> 0, step: 1
5660 14:47:08.384694
5661 14:47:08.388207 RX Delay -80 -> 252, step: 8
5662 14:47:08.391200 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5663 14:47:08.397994 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5664 14:47:08.400706 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5665 14:47:08.403781 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5666 14:47:08.407432 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5667 14:47:08.410648 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5668 14:47:08.413846 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5669 14:47:08.420664 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5670 14:47:08.423707 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5671 14:47:08.427222 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5672 14:47:08.430397 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5673 14:47:08.434071 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5674 14:47:08.440733 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5675 14:47:08.443630 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5676 14:47:08.446997 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5677 14:47:08.450405 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5678 14:47:08.450488 ==
5679 14:47:08.453754 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 14:47:08.456776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 14:47:08.456864 ==
5682 14:47:08.460085 DQS Delay:
5683 14:47:08.460179 DQS0 = 0, DQS1 = 0
5684 14:47:08.463296 DQM Delay:
5685 14:47:08.463397 DQM0 = 99, DQM1 = 91
5686 14:47:08.463478 DQ Delay:
5687 14:47:08.466901 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =95
5688 14:47:08.469846 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =95
5689 14:47:08.473112 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5690 14:47:08.479632 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5691 14:47:08.479769
5692 14:47:08.479875
5693 14:47:08.479974 ==
5694 14:47:08.482893 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 14:47:08.486204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 14:47:08.486358 ==
5697 14:47:08.486478
5698 14:47:08.486590
5699 14:47:08.489958 TX Vref Scan disable
5700 14:47:08.490132 == TX Byte 0 ==
5701 14:47:08.496288 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5702 14:47:08.499527 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5703 14:47:08.499701 == TX Byte 1 ==
5704 14:47:08.506050 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5705 14:47:08.509574 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5706 14:47:08.509748 ==
5707 14:47:08.512996 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 14:47:08.516111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 14:47:08.516287 ==
5710 14:47:08.516425
5711 14:47:08.519517
5712 14:47:08.519696 TX Vref Scan disable
5713 14:47:08.522384 == TX Byte 0 ==
5714 14:47:08.526040 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5715 14:47:08.529215 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5716 14:47:08.532535 == TX Byte 1 ==
5717 14:47:08.535795 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5718 14:47:08.539195 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5719 14:47:08.542435
5720 14:47:08.542614 [DATLAT]
5721 14:47:08.542795 Freq=933, CH1 RK0
5722 14:47:08.542966
5723 14:47:08.545981 DATLAT Default: 0xd
5724 14:47:08.546173 0, 0xFFFF, sum = 0
5725 14:47:08.548955 1, 0xFFFF, sum = 0
5726 14:47:08.549137 2, 0xFFFF, sum = 0
5727 14:47:08.552319 3, 0xFFFF, sum = 0
5728 14:47:08.555746 4, 0xFFFF, sum = 0
5729 14:47:08.555938 5, 0xFFFF, sum = 0
5730 14:47:08.558793 6, 0xFFFF, sum = 0
5731 14:47:08.559005 7, 0xFFFF, sum = 0
5732 14:47:08.562241 8, 0xFFFF, sum = 0
5733 14:47:08.562457 9, 0xFFFF, sum = 0
5734 14:47:08.565614 10, 0x0, sum = 1
5735 14:47:08.565796 11, 0x0, sum = 2
5736 14:47:08.568881 12, 0x0, sum = 3
5737 14:47:08.569062 13, 0x0, sum = 4
5738 14:47:08.569248 best_step = 11
5739 14:47:08.569420
5740 14:47:08.572080 ==
5741 14:47:08.575697 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 14:47:08.578576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 14:47:08.578756 ==
5744 14:47:08.578936 RX Vref Scan: 1
5745 14:47:08.579108
5746 14:47:08.582221 RX Vref 0 -> 0, step: 1
5747 14:47:08.582402
5748 14:47:08.585976 RX Delay -69 -> 252, step: 4
5749 14:47:08.586156
5750 14:47:08.588648 Set Vref, RX VrefLevel [Byte0]: 52
5751 14:47:08.592325 [Byte1]: 54
5752 14:47:08.592545
5753 14:47:08.595709 Final RX Vref Byte 0 = 52 to rank0
5754 14:47:08.598518 Final RX Vref Byte 1 = 54 to rank0
5755 14:47:08.602127 Final RX Vref Byte 0 = 52 to rank1
5756 14:47:08.605347 Final RX Vref Byte 1 = 54 to rank1==
5757 14:47:08.608402 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 14:47:08.615020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 14:47:08.615334 ==
5760 14:47:08.615653 DQS Delay:
5761 14:47:08.615951 DQS0 = 0, DQS1 = 0
5762 14:47:08.618187 DQM Delay:
5763 14:47:08.618590 DQM0 = 100, DQM1 = 93
5764 14:47:08.621459 DQ Delay:
5765 14:47:08.624885 DQ0 =104, DQ1 =96, DQ2 =90, DQ3 =96
5766 14:47:08.628004 DQ4 =96, DQ5 =110, DQ6 =112, DQ7 =96
5767 14:47:08.631526 DQ8 =80, DQ9 =84, DQ10 =96, DQ11 =84
5768 14:47:08.634509 DQ12 =102, DQ13 =98, DQ14 =102, DQ15 =104
5769 14:47:08.634822
5770 14:47:08.635199
5771 14:47:08.641339 [DQSOSCAuto] RK0, (LSB)MR18= 0x1808, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5772 14:47:08.644787 CH1 RK0: MR19=505, MR18=1808
5773 14:47:08.651142 CH1_RK0: MR19=0x505, MR18=0x1808, DQSOSC=414, MR23=63, INC=63, DEC=42
5774 14:47:08.651465
5775 14:47:08.654286 ----->DramcWriteLeveling(PI) begin...
5776 14:47:08.654672 ==
5777 14:47:08.657604 Dram Type= 6, Freq= 0, CH_1, rank 1
5778 14:47:08.660817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 14:47:08.664586 ==
5780 14:47:08.664862 Write leveling (Byte 0): 28 => 28
5781 14:47:08.667662 Write leveling (Byte 1): 30 => 30
5782 14:47:08.671285 DramcWriteLeveling(PI) end<-----
5783 14:47:08.671586
5784 14:47:08.671821 ==
5785 14:47:08.674413 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 14:47:08.680512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 14:47:08.680824 ==
5788 14:47:08.684153 [Gating] SW mode calibration
5789 14:47:08.690921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5790 14:47:08.693646 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5791 14:47:08.700532 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5792 14:47:08.703704 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 14:47:08.707594 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 14:47:08.713426 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 14:47:08.716638 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 14:47:08.720117 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 14:47:08.726832 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
5798 14:47:08.729921 0 14 28 | B1->B0 | 2929 3030 | 0 0 | (0 0) (1 0)
5799 14:47:08.733310 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5800 14:47:08.739615 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 14:47:08.743072 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 14:47:08.746773 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 14:47:08.752911 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 14:47:08.756280 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 14:47:08.759996 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5806 14:47:08.766561 0 15 28 | B1->B0 | 4040 3636 | 1 1 | (0 0) (0 0)
5807 14:47:08.769531 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 14:47:08.772583 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 14:47:08.779388 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 14:47:08.782521 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 14:47:08.785824 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 14:47:08.792398 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 14:47:08.795789 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 14:47:08.799094 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5815 14:47:08.805952 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 14:47:08.808718 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 14:47:08.812456 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 14:47:08.818768 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 14:47:08.822020 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 14:47:08.825220 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 14:47:08.831798 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 14:47:08.835286 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 14:47:08.838842 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 14:47:08.845249 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 14:47:08.848590 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 14:47:08.851853 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 14:47:08.858553 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 14:47:08.862026 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 14:47:08.864981 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 14:47:08.872076 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5831 14:47:08.875408 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5832 14:47:08.878859 Total UI for P1: 0, mck2ui 16
5833 14:47:08.882119 best dqsien dly found for B1: ( 1, 2, 28)
5834 14:47:08.885371 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 14:47:08.888839 Total UI for P1: 0, mck2ui 16
5836 14:47:08.891906 best dqsien dly found for B0: ( 1, 2, 30)
5837 14:47:08.895130 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5838 14:47:08.898361 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5839 14:47:08.898433
5840 14:47:08.901254 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5841 14:47:08.907945 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5842 14:47:08.908048 [Gating] SW calibration Done
5843 14:47:08.911351 ==
5844 14:47:08.911424 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 14:47:08.918037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 14:47:08.918150 ==
5847 14:47:08.918292 RX Vref Scan: 0
5848 14:47:08.918382
5849 14:47:08.921222 RX Vref 0 -> 0, step: 1
5850 14:47:08.921329
5851 14:47:08.924549 RX Delay -80 -> 252, step: 8
5852 14:47:08.927980 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5853 14:47:08.931419 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5854 14:47:08.934337 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5855 14:47:08.940882 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5856 14:47:08.944341 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5857 14:47:08.947534 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5858 14:47:08.950802 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5859 14:47:08.954354 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
5860 14:47:08.957820 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5861 14:47:08.964085 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5862 14:47:08.967953 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5863 14:47:08.970676 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5864 14:47:08.974088 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5865 14:47:08.977240 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5866 14:47:08.984295 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5867 14:47:08.987563 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5868 14:47:08.987698 ==
5869 14:47:08.990817 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 14:47:08.994123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 14:47:08.994316 ==
5872 14:47:08.997166 DQS Delay:
5873 14:47:08.997346 DQS0 = 0, DQS1 = 0
5874 14:47:08.997485 DQM Delay:
5875 14:47:09.000610 DQM0 = 100, DQM1 = 91
5876 14:47:09.000839 DQ Delay:
5877 14:47:09.003723 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5878 14:47:09.007238 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5879 14:47:09.010548 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =87
5880 14:47:09.013776 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5881 14:47:09.013946
5882 14:47:09.014080
5883 14:47:09.014257 ==
5884 14:47:09.016936 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 14:47:09.023669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 14:47:09.023771 ==
5887 14:47:09.023865
5888 14:47:09.023992
5889 14:47:09.024056 TX Vref Scan disable
5890 14:47:09.027290 == TX Byte 0 ==
5891 14:47:09.030848 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5892 14:47:09.037542 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5893 14:47:09.037962 == TX Byte 1 ==
5894 14:47:09.041477 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5895 14:47:09.047591 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5896 14:47:09.048027 ==
5897 14:47:09.050919 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 14:47:09.054283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 14:47:09.054703 ==
5900 14:47:09.055032
5901 14:47:09.055339
5902 14:47:09.057118 TX Vref Scan disable
5903 14:47:09.057535 == TX Byte 0 ==
5904 14:47:09.063974 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5905 14:47:09.067213 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5906 14:47:09.067813 == TX Byte 1 ==
5907 14:47:09.073768 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5908 14:47:09.077134 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5909 14:47:09.077586
5910 14:47:09.078012 [DATLAT]
5911 14:47:09.080560 Freq=933, CH1 RK1
5912 14:47:09.081163
5913 14:47:09.081644 DATLAT Default: 0xb
5914 14:47:09.084160 0, 0xFFFF, sum = 0
5915 14:47:09.084578 1, 0xFFFF, sum = 0
5916 14:47:09.087384 2, 0xFFFF, sum = 0
5917 14:47:09.090128 3, 0xFFFF, sum = 0
5918 14:47:09.090612 4, 0xFFFF, sum = 0
5919 14:47:09.093550 5, 0xFFFF, sum = 0
5920 14:47:09.094020 6, 0xFFFF, sum = 0
5921 14:47:09.097433 7, 0xFFFF, sum = 0
5922 14:47:09.097906 8, 0xFFFF, sum = 0
5923 14:47:09.100045 9, 0xFFFF, sum = 0
5924 14:47:09.100159 10, 0x0, sum = 1
5925 14:47:09.103304 11, 0x0, sum = 2
5926 14:47:09.103385 12, 0x0, sum = 3
5927 14:47:09.106508 13, 0x0, sum = 4
5928 14:47:09.106589 best_step = 11
5929 14:47:09.106653
5930 14:47:09.106711 ==
5931 14:47:09.110444 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 14:47:09.113915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 14:47:09.114558 ==
5934 14:47:09.116562 RX Vref Scan: 0
5935 14:47:09.116996
5936 14:47:09.119969 RX Vref 0 -> 0, step: 1
5937 14:47:09.120402
5938 14:47:09.120731 RX Delay -69 -> 252, step: 4
5939 14:47:09.128011 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5940 14:47:09.131327 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5941 14:47:09.134450 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5942 14:47:09.138002 iDelay=207, Bit 3, Center 98 (11 ~ 186) 176
5943 14:47:09.140885 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5944 14:47:09.147726 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
5945 14:47:09.151409 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5946 14:47:09.154473 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5947 14:47:09.157859 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5948 14:47:09.160717 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5949 14:47:09.164044 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5950 14:47:09.170753 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5951 14:47:09.173930 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5952 14:47:09.177473 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
5953 14:47:09.180771 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
5954 14:47:09.184593 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
5955 14:47:09.187580 ==
5956 14:47:09.190304 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 14:47:09.193697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 14:47:09.194341 ==
5959 14:47:09.194936 DQS Delay:
5960 14:47:09.197245 DQS0 = 0, DQS1 = 0
5961 14:47:09.197665 DQM Delay:
5962 14:47:09.200497 DQM0 = 101, DQM1 = 93
5963 14:47:09.200945 DQ Delay:
5964 14:47:09.204014 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
5965 14:47:09.207192 DQ4 =98, DQ5 =112, DQ6 =114, DQ7 =98
5966 14:47:09.210584 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5967 14:47:09.213820 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =100
5968 14:47:09.214287
5969 14:47:09.214631
5970 14:47:09.223817 [DQSOSCAuto] RK1, (LSB)MR18= 0x903, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5971 14:47:09.224125 CH1 RK1: MR19=505, MR18=903
5972 14:47:09.230412 CH1_RK1: MR19=0x505, MR18=0x903, DQSOSC=419, MR23=63, INC=61, DEC=41
5973 14:47:09.233744 [RxdqsGatingPostProcess] freq 933
5974 14:47:09.240099 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5975 14:47:09.243255 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 14:47:09.246595 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 14:47:09.249883 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 14:47:09.253289 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 14:47:09.253516 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 14:47:09.256443 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 14:47:09.259827 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 14:47:09.263338 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 14:47:09.266088 Pre-setting of DQS Precalculation
5984 14:47:09.272879 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5985 14:47:09.279468 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5986 14:47:09.286601 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5987 14:47:09.286830
5988 14:47:09.287009
5989 14:47:09.289264 [Calibration Summary] 1866 Mbps
5990 14:47:09.292964 CH 0, Rank 0
5991 14:47:09.293190 SW Impedance : PASS
5992 14:47:09.295701 DUTY Scan : NO K
5993 14:47:09.295929 ZQ Calibration : PASS
5994 14:47:09.299102 Jitter Meter : NO K
5995 14:47:09.302339 CBT Training : PASS
5996 14:47:09.302565 Write leveling : PASS
5997 14:47:09.305960 RX DQS gating : PASS
5998 14:47:09.308734 RX DQ/DQS(RDDQC) : PASS
5999 14:47:09.309012 TX DQ/DQS : PASS
6000 14:47:09.312544 RX DATLAT : PASS
6001 14:47:09.315631 RX DQ/DQS(Engine): PASS
6002 14:47:09.315950 TX OE : NO K
6003 14:47:09.319303 All Pass.
6004 14:47:09.319534
6005 14:47:09.319713 CH 0, Rank 1
6006 14:47:09.321972 SW Impedance : PASS
6007 14:47:09.322221 DUTY Scan : NO K
6008 14:47:09.325668 ZQ Calibration : PASS
6009 14:47:09.329114 Jitter Meter : NO K
6010 14:47:09.329433 CBT Training : PASS
6011 14:47:09.332222 Write leveling : PASS
6012 14:47:09.335647 RX DQS gating : PASS
6013 14:47:09.335878 RX DQ/DQS(RDDQC) : PASS
6014 14:47:09.338712 TX DQ/DQS : PASS
6015 14:47:09.342194 RX DATLAT : PASS
6016 14:47:09.342564 RX DQ/DQS(Engine): PASS
6017 14:47:09.345400 TX OE : NO K
6018 14:47:09.345763 All Pass.
6019 14:47:09.346044
6020 14:47:09.348762 CH 1, Rank 0
6021 14:47:09.349489 SW Impedance : PASS
6022 14:47:09.352177 DUTY Scan : NO K
6023 14:47:09.355724 ZQ Calibration : PASS
6024 14:47:09.356281 Jitter Meter : NO K
6025 14:47:09.358548 CBT Training : PASS
6026 14:47:09.361979 Write leveling : PASS
6027 14:47:09.362573 RX DQS gating : PASS
6028 14:47:09.365405 RX DQ/DQS(RDDQC) : PASS
6029 14:47:09.368406 TX DQ/DQS : PASS
6030 14:47:09.368892 RX DATLAT : PASS
6031 14:47:09.372221 RX DQ/DQS(Engine): PASS
6032 14:47:09.372785 TX OE : NO K
6033 14:47:09.375394 All Pass.
6034 14:47:09.375859
6035 14:47:09.376224 CH 1, Rank 1
6036 14:47:09.378638 SW Impedance : PASS
6037 14:47:09.379104 DUTY Scan : NO K
6038 14:47:09.381940 ZQ Calibration : PASS
6039 14:47:09.385092 Jitter Meter : NO K
6040 14:47:09.385648 CBT Training : PASS
6041 14:47:09.388521 Write leveling : PASS
6042 14:47:09.391962 RX DQS gating : PASS
6043 14:47:09.392524 RX DQ/DQS(RDDQC) : PASS
6044 14:47:09.395035 TX DQ/DQS : PASS
6045 14:47:09.398287 RX DATLAT : PASS
6046 14:47:09.398851 RX DQ/DQS(Engine): PASS
6047 14:47:09.401659 TX OE : NO K
6048 14:47:09.402285 All Pass.
6049 14:47:09.402741
6050 14:47:09.404616 DramC Write-DBI off
6051 14:47:09.408599 PER_BANK_REFRESH: Hybrid Mode
6052 14:47:09.409166 TX_TRACKING: ON
6053 14:47:09.418382 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6054 14:47:09.421358 [FAST_K] Save calibration result to emmc
6055 14:47:09.425056 dramc_set_vcore_voltage set vcore to 650000
6056 14:47:09.427599 Read voltage for 400, 6
6057 14:47:09.428081 Vio18 = 0
6058 14:47:09.428455 Vcore = 650000
6059 14:47:09.431340 Vdram = 0
6060 14:47:09.431887 Vddq = 0
6061 14:47:09.432258 Vmddr = 0
6062 14:47:09.437600 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6063 14:47:09.441082 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6064 14:47:09.444675 MEM_TYPE=3, freq_sel=20
6065 14:47:09.447667 sv_algorithm_assistance_LP4_800
6066 14:47:09.450985 ============ PULL DRAM RESETB DOWN ============
6067 14:47:09.457609 ========== PULL DRAM RESETB DOWN end =========
6068 14:47:09.460649 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6069 14:47:09.464052 ===================================
6070 14:47:09.467179 LPDDR4 DRAM CONFIGURATION
6071 14:47:09.470537 ===================================
6072 14:47:09.471005 EX_ROW_EN[0] = 0x0
6073 14:47:09.473937 EX_ROW_EN[1] = 0x0
6074 14:47:09.474434 LP4Y_EN = 0x0
6075 14:47:09.477288 WORK_FSP = 0x0
6076 14:47:09.477751 WL = 0x2
6077 14:47:09.480566 RL = 0x2
6078 14:47:09.481032 BL = 0x2
6079 14:47:09.484185 RPST = 0x0
6080 14:47:09.487061 RD_PRE = 0x0
6081 14:47:09.487529 WR_PRE = 0x1
6082 14:47:09.490723 WR_PST = 0x0
6083 14:47:09.491313 DBI_WR = 0x0
6084 14:47:09.493889 DBI_RD = 0x0
6085 14:47:09.494411 OTF = 0x1
6086 14:47:09.497284 ===================================
6087 14:47:09.500512 ===================================
6088 14:47:09.503903 ANA top config
6089 14:47:09.506845 ===================================
6090 14:47:09.507312 DLL_ASYNC_EN = 0
6091 14:47:09.510425 ALL_SLAVE_EN = 1
6092 14:47:09.513895 NEW_RANK_MODE = 1
6093 14:47:09.517054 DLL_IDLE_MODE = 1
6094 14:47:09.520263 LP45_APHY_COMB_EN = 1
6095 14:47:09.520995 TX_ODT_DIS = 1
6096 14:47:09.523566 NEW_8X_MODE = 1
6097 14:47:09.526336 ===================================
6098 14:47:09.530024 ===================================
6099 14:47:09.533579 data_rate = 800
6100 14:47:09.536366 CKR = 1
6101 14:47:09.539488 DQ_P2S_RATIO = 4
6102 14:47:09.543264 ===================================
6103 14:47:09.547044 CA_P2S_RATIO = 4
6104 14:47:09.547617 DQ_CA_OPEN = 0
6105 14:47:09.549784 DQ_SEMI_OPEN = 1
6106 14:47:09.553098 CA_SEMI_OPEN = 1
6107 14:47:09.556302 CA_FULL_RATE = 0
6108 14:47:09.559885 DQ_CKDIV4_EN = 0
6109 14:47:09.562636 CA_CKDIV4_EN = 1
6110 14:47:09.563127 CA_PREDIV_EN = 0
6111 14:47:09.565901 PH8_DLY = 0
6112 14:47:09.569200 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6113 14:47:09.572503 DQ_AAMCK_DIV = 0
6114 14:47:09.576058 CA_AAMCK_DIV = 0
6115 14:47:09.579140 CA_ADMCK_DIV = 4
6116 14:47:09.579606 DQ_TRACK_CA_EN = 0
6117 14:47:09.582681 CA_PICK = 800
6118 14:47:09.586072 CA_MCKIO = 400
6119 14:47:09.589125 MCKIO_SEMI = 400
6120 14:47:09.592224 PLL_FREQ = 3016
6121 14:47:09.595930 DQ_UI_PI_RATIO = 32
6122 14:47:09.599226 CA_UI_PI_RATIO = 32
6123 14:47:09.602202 ===================================
6124 14:47:09.605506 ===================================
6125 14:47:09.605931 memory_type:LPDDR4
6126 14:47:09.609611 GP_NUM : 10
6127 14:47:09.612181 SRAM_EN : 1
6128 14:47:09.612634 MD32_EN : 0
6129 14:47:09.615563 ===================================
6130 14:47:09.618609 [ANA_INIT] >>>>>>>>>>>>>>
6131 14:47:09.622638 <<<<<< [CONFIGURE PHASE]: ANA_TX
6132 14:47:09.625706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6133 14:47:09.628639 ===================================
6134 14:47:09.631916 data_rate = 800,PCW = 0X7400
6135 14:47:09.635079 ===================================
6136 14:47:09.638411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6137 14:47:09.642477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 14:47:09.654769 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 14:47:09.658089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6140 14:47:09.662130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6141 14:47:09.664720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6142 14:47:09.668161 [ANA_INIT] flow start
6143 14:47:09.671943 [ANA_INIT] PLL >>>>>>>>
6144 14:47:09.672356 [ANA_INIT] PLL <<<<<<<<
6145 14:47:09.674475 [ANA_INIT] MIDPI >>>>>>>>
6146 14:47:09.677829 [ANA_INIT] MIDPI <<<<<<<<
6147 14:47:09.678130 [ANA_INIT] DLL >>>>>>>>
6148 14:47:09.681134 [ANA_INIT] flow end
6149 14:47:09.684108 ============ LP4 DIFF to SE enter ============
6150 14:47:09.691278 ============ LP4 DIFF to SE exit ============
6151 14:47:09.691486 [ANA_INIT] <<<<<<<<<<<<<
6152 14:47:09.694440 [Flow] Enable top DCM control >>>>>
6153 14:47:09.697371 [Flow] Enable top DCM control <<<<<
6154 14:47:09.700671 Enable DLL master slave shuffle
6155 14:47:09.707624 ==============================================================
6156 14:47:09.708048 Gating Mode config
6157 14:47:09.714563 ==============================================================
6158 14:47:09.717554 Config description:
6159 14:47:09.727802 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6160 14:47:09.734388 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6161 14:47:09.737502 SELPH_MODE 0: By rank 1: By Phase
6162 14:47:09.743911 ==============================================================
6163 14:47:09.747165 GAT_TRACK_EN = 0
6164 14:47:09.750292 RX_GATING_MODE = 2
6165 14:47:09.750592 RX_GATING_TRACK_MODE = 2
6166 14:47:09.753665 SELPH_MODE = 1
6167 14:47:09.756923 PICG_EARLY_EN = 1
6168 14:47:09.760524 VALID_LAT_VALUE = 1
6169 14:47:09.766847 ==============================================================
6170 14:47:09.770009 Enter into Gating configuration >>>>
6171 14:47:09.773658 Exit from Gating configuration <<<<
6172 14:47:09.776970 Enter into DVFS_PRE_config >>>>>
6173 14:47:09.786598 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6174 14:47:09.790318 Exit from DVFS_PRE_config <<<<<
6175 14:47:09.793510 Enter into PICG configuration >>>>
6176 14:47:09.796836 Exit from PICG configuration <<<<
6177 14:47:09.799970 [RX_INPUT] configuration >>>>>
6178 14:47:09.803581 [RX_INPUT] configuration <<<<<
6179 14:47:09.806499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6180 14:47:09.813020 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6181 14:47:09.819610 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6182 14:47:09.826518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6183 14:47:09.832876 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6184 14:47:09.839560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6185 14:47:09.843131 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6186 14:47:09.846091 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6187 14:47:09.849682 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6188 14:47:09.852673 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6189 14:47:09.859291 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6190 14:47:09.862992 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 14:47:09.866105 ===================================
6192 14:47:09.868887 LPDDR4 DRAM CONFIGURATION
6193 14:47:09.872579 ===================================
6194 14:47:09.873221 EX_ROW_EN[0] = 0x0
6195 14:47:09.876240 EX_ROW_EN[1] = 0x0
6196 14:47:09.876779 LP4Y_EN = 0x0
6197 14:47:09.878831 WORK_FSP = 0x0
6198 14:47:09.882462 WL = 0x2
6199 14:47:09.882876 RL = 0x2
6200 14:47:09.885289 BL = 0x2
6201 14:47:09.885802 RPST = 0x0
6202 14:47:09.888918 RD_PRE = 0x0
6203 14:47:09.889334 WR_PRE = 0x1
6204 14:47:09.891786 WR_PST = 0x0
6205 14:47:09.892383 DBI_WR = 0x0
6206 14:47:09.895477 DBI_RD = 0x0
6207 14:47:09.895888 OTF = 0x1
6208 14:47:09.899122 ===================================
6209 14:47:09.901973 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6210 14:47:09.908324 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6211 14:47:09.912537 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6212 14:47:09.915344 ===================================
6213 14:47:09.918344 LPDDR4 DRAM CONFIGURATION
6214 14:47:09.921758 ===================================
6215 14:47:09.922421 EX_ROW_EN[0] = 0x10
6216 14:47:09.924733 EX_ROW_EN[1] = 0x0
6217 14:47:09.928469 LP4Y_EN = 0x0
6218 14:47:09.929119 WORK_FSP = 0x0
6219 14:47:09.931449 WL = 0x2
6220 14:47:09.931863 RL = 0x2
6221 14:47:09.934916 BL = 0x2
6222 14:47:09.935253 RPST = 0x0
6223 14:47:09.937961 RD_PRE = 0x0
6224 14:47:09.938266 WR_PRE = 0x1
6225 14:47:09.941372 WR_PST = 0x0
6226 14:47:09.941675 DBI_WR = 0x0
6227 14:47:09.944612 DBI_RD = 0x0
6228 14:47:09.944792 OTF = 0x1
6229 14:47:09.948023 ===================================
6230 14:47:09.954466 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6231 14:47:09.958882 nWR fixed to 30
6232 14:47:09.961696 [ModeRegInit_LP4] CH0 RK0
6233 14:47:09.961850 [ModeRegInit_LP4] CH0 RK1
6234 14:47:09.964994 [ModeRegInit_LP4] CH1 RK0
6235 14:47:09.968166 [ModeRegInit_LP4] CH1 RK1
6236 14:47:09.968322 match AC timing 19
6237 14:47:09.975080 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6238 14:47:09.978907 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6239 14:47:09.982031 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6240 14:47:09.988037 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6241 14:47:09.991496 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6242 14:47:09.991579 ==
6243 14:47:09.994984 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 14:47:09.998120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 14:47:09.998241 ==
6246 14:47:10.004586 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 14:47:10.011345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6248 14:47:10.014636 [CA 0] Center 36 (8~64) winsize 57
6249 14:47:10.017649 [CA 1] Center 36 (8~64) winsize 57
6250 14:47:10.021071 [CA 2] Center 36 (8~64) winsize 57
6251 14:47:10.024389 [CA 3] Center 36 (8~64) winsize 57
6252 14:47:10.028252 [CA 4] Center 36 (8~64) winsize 57
6253 14:47:10.031547 [CA 5] Center 36 (8~64) winsize 57
6254 14:47:10.031643
6255 14:47:10.034450 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6256 14:47:10.034553
6257 14:47:10.038054 [CATrainingPosCal] consider 1 rank data
6258 14:47:10.041471 u2DelayCellTimex100 = 270/100 ps
6259 14:47:10.044464 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 14:47:10.047801 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 14:47:10.051000 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 14:47:10.054291 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 14:47:10.057631 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 14:47:10.060922 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 14:47:10.061100
6266 14:47:10.067296 CA PerBit enable=1, Macro0, CA PI delay=36
6267 14:47:10.067580
6268 14:47:10.067747 [CBTSetCACLKResult] CA Dly = 36
6269 14:47:10.070732 CS Dly: 1 (0~32)
6270 14:47:10.070985 ==
6271 14:47:10.074210 Dram Type= 6, Freq= 0, CH_0, rank 1
6272 14:47:10.077885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 14:47:10.078449 ==
6274 14:47:10.084514 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 14:47:10.091099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6276 14:47:10.094492 [CA 0] Center 36 (8~64) winsize 57
6277 14:47:10.097050 [CA 1] Center 36 (8~64) winsize 57
6278 14:47:10.100591 [CA 2] Center 36 (8~64) winsize 57
6279 14:47:10.103696 [CA 3] Center 36 (8~64) winsize 57
6280 14:47:10.107697 [CA 4] Center 36 (8~64) winsize 57
6281 14:47:10.110378 [CA 5] Center 36 (8~64) winsize 57
6282 14:47:10.110931
6283 14:47:10.113666 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6284 14:47:10.114243
6285 14:47:10.117193 [CATrainingPosCal] consider 2 rank data
6286 14:47:10.120604 u2DelayCellTimex100 = 270/100 ps
6287 14:47:10.123718 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 14:47:10.127232 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 14:47:10.130529 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 14:47:10.134198 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 14:47:10.136960 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 14:47:10.139982 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 14:47:10.140442
6294 14:47:10.143452 CA PerBit enable=1, Macro0, CA PI delay=36
6295 14:47:10.146637
6296 14:47:10.147091 [CBTSetCACLKResult] CA Dly = 36
6297 14:47:10.149847 CS Dly: 1 (0~32)
6298 14:47:10.150446
6299 14:47:10.153144 ----->DramcWriteLeveling(PI) begin...
6300 14:47:10.153771 ==
6301 14:47:10.156768 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 14:47:10.159675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 14:47:10.160131 ==
6304 14:47:10.163383 Write leveling (Byte 0): 40 => 8
6305 14:47:10.166997 Write leveling (Byte 1): 32 => 0
6306 14:47:10.169974 DramcWriteLeveling(PI) end<-----
6307 14:47:10.170335
6308 14:47:10.170568 ==
6309 14:47:10.173056 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 14:47:10.176558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 14:47:10.179751 ==
6312 14:47:10.179970 [Gating] SW mode calibration
6313 14:47:10.189222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6314 14:47:10.192485 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6315 14:47:10.195913 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 14:47:10.202586 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 14:47:10.206319 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 14:47:10.209358 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 14:47:10.215815 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 14:47:10.219167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 14:47:10.222559 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 14:47:10.229048 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 14:47:10.232300 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 14:47:10.235399 Total UI for P1: 0, mck2ui 16
6325 14:47:10.238813 best dqsien dly found for B0: ( 0, 14, 24)
6326 14:47:10.242414 Total UI for P1: 0, mck2ui 16
6327 14:47:10.245956 best dqsien dly found for B1: ( 0, 14, 24)
6328 14:47:10.249098 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6329 14:47:10.251898 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6330 14:47:10.252580
6331 14:47:10.255266 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 14:47:10.261628 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 14:47:10.262114 [Gating] SW calibration Done
6334 14:47:10.262475 ==
6335 14:47:10.265412 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 14:47:10.271797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 14:47:10.272403 ==
6338 14:47:10.272852 RX Vref Scan: 0
6339 14:47:10.273166
6340 14:47:10.274925 RX Vref 0 -> 0, step: 1
6341 14:47:10.275336
6342 14:47:10.278353 RX Delay -410 -> 252, step: 16
6343 14:47:10.281818 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6344 14:47:10.284797 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6345 14:47:10.291189 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6346 14:47:10.294469 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6347 14:47:10.298494 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6348 14:47:10.301024 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6349 14:47:10.308191 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6350 14:47:10.311440 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6351 14:47:10.314525 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6352 14:47:10.317855 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6353 14:47:10.324524 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6354 14:47:10.327707 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6355 14:47:10.331215 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6356 14:47:10.337424 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6357 14:47:10.340889 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6358 14:47:10.344229 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6359 14:47:10.344673 ==
6360 14:47:10.348442 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 14:47:10.350923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 14:47:10.353820 ==
6363 14:47:10.354272 DQS Delay:
6364 14:47:10.354607 DQS0 = 43, DQS1 = 59
6365 14:47:10.357264 DQM Delay:
6366 14:47:10.357675 DQM0 = 8, DQM1 = 11
6367 14:47:10.360723 DQ Delay:
6368 14:47:10.361139 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6369 14:47:10.364179 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6370 14:47:10.367604 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6371 14:47:10.370378 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6372 14:47:10.370813
6373 14:47:10.371139
6374 14:47:10.373758 ==
6375 14:47:10.377491 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 14:47:10.380521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 14:47:10.381034 ==
6378 14:47:10.381368
6379 14:47:10.381672
6380 14:47:10.383805 TX Vref Scan disable
6381 14:47:10.384222 == TX Byte 0 ==
6382 14:47:10.387333 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 14:47:10.393446 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 14:47:10.393962 == TX Byte 1 ==
6385 14:47:10.397245 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6386 14:47:10.404092 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6387 14:47:10.404603 ==
6388 14:47:10.406846 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 14:47:10.410322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 14:47:10.410828 ==
6391 14:47:10.411153
6392 14:47:10.411453
6393 14:47:10.413090 TX Vref Scan disable
6394 14:47:10.413498 == TX Byte 0 ==
6395 14:47:10.419819 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6396 14:47:10.423530 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6397 14:47:10.423986 == TX Byte 1 ==
6398 14:47:10.430024 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6399 14:47:10.432988 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6400 14:47:10.433445
6401 14:47:10.433802 [DATLAT]
6402 14:47:10.436526 Freq=400, CH0 RK0
6403 14:47:10.437048
6404 14:47:10.437416 DATLAT Default: 0xf
6405 14:47:10.439862 0, 0xFFFF, sum = 0
6406 14:47:10.440334 1, 0xFFFF, sum = 0
6407 14:47:10.442851 2, 0xFFFF, sum = 0
6408 14:47:10.443323 3, 0xFFFF, sum = 0
6409 14:47:10.446554 4, 0xFFFF, sum = 0
6410 14:47:10.447112 5, 0xFFFF, sum = 0
6411 14:47:10.449792 6, 0xFFFF, sum = 0
6412 14:47:10.450330 7, 0xFFFF, sum = 0
6413 14:47:10.453260 8, 0xFFFF, sum = 0
6414 14:47:10.453947 9, 0xFFFF, sum = 0
6415 14:47:10.456925 10, 0xFFFF, sum = 0
6416 14:47:10.457499 11, 0xFFFF, sum = 0
6417 14:47:10.459774 12, 0xFFFF, sum = 0
6418 14:47:10.463113 13, 0x0, sum = 1
6419 14:47:10.463586 14, 0x0, sum = 2
6420 14:47:10.463961 15, 0x0, sum = 3
6421 14:47:10.466017 16, 0x0, sum = 4
6422 14:47:10.466570 best_step = 14
6423 14:47:10.467045
6424 14:47:10.469513 ==
6425 14:47:10.470031 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 14:47:10.476034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 14:47:10.476511 ==
6428 14:47:10.476986 RX Vref Scan: 1
6429 14:47:10.477435
6430 14:47:10.479261 RX Vref 0 -> 0, step: 1
6431 14:47:10.479799
6432 14:47:10.482856 RX Delay -359 -> 252, step: 8
6433 14:47:10.483271
6434 14:47:10.486078 Set Vref, RX VrefLevel [Byte0]: 59
6435 14:47:10.489527 [Byte1]: 50
6436 14:47:10.493102
6437 14:47:10.493643 Final RX Vref Byte 0 = 59 to rank0
6438 14:47:10.496315 Final RX Vref Byte 1 = 50 to rank0
6439 14:47:10.499464 Final RX Vref Byte 0 = 59 to rank1
6440 14:47:10.503158 Final RX Vref Byte 1 = 50 to rank1==
6441 14:47:10.505972 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 14:47:10.512584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 14:47:10.513022 ==
6444 14:47:10.513441 DQS Delay:
6445 14:47:10.516021 DQS0 = 48, DQS1 = 60
6446 14:47:10.516467 DQM Delay:
6447 14:47:10.516913 DQM0 = 11, DQM1 = 11
6448 14:47:10.518964 DQ Delay:
6449 14:47:10.522432 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6450 14:47:10.525971 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6451 14:47:10.526522 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6452 14:47:10.532440 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6453 14:47:10.532989
6454 14:47:10.533321
6455 14:47:10.538737 [DQSOSCAuto] RK0, (LSB)MR18= 0xbb7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6456 14:47:10.542407 CH0 RK0: MR19=C0C, MR18=BB7D
6457 14:47:10.548752 CH0_RK0: MR19=0xC0C, MR18=0xBB7D, DQSOSC=386, MR23=63, INC=396, DEC=264
6458 14:47:10.549261 ==
6459 14:47:10.552286 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 14:47:10.555144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 14:47:10.555606 ==
6462 14:47:10.558646 [Gating] SW mode calibration
6463 14:47:10.565641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6464 14:47:10.572015 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6465 14:47:10.575003 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 14:47:10.578157 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 14:47:10.584981 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 14:47:10.588278 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 14:47:10.591516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 14:47:10.598233 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 14:47:10.601365 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 14:47:10.604701 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 14:47:10.611303 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 14:47:10.614948 Total UI for P1: 0, mck2ui 16
6475 14:47:10.617784 best dqsien dly found for B0: ( 0, 14, 24)
6476 14:47:10.617971 Total UI for P1: 0, mck2ui 16
6477 14:47:10.624234 best dqsien dly found for B1: ( 0, 14, 24)
6478 14:47:10.627803 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6479 14:47:10.630602 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6480 14:47:10.630686
6481 14:47:10.633855 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 14:47:10.637344 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 14:47:10.640540 [Gating] SW calibration Done
6484 14:47:10.640624 ==
6485 14:47:10.644143 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 14:47:10.647381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 14:47:10.647466 ==
6488 14:47:10.650504 RX Vref Scan: 0
6489 14:47:10.650587
6490 14:47:10.653826 RX Vref 0 -> 0, step: 1
6491 14:47:10.653935
6492 14:47:10.657083 RX Delay -410 -> 252, step: 16
6493 14:47:10.660481 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6494 14:47:10.663519 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6495 14:47:10.667152 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6496 14:47:10.673370 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6497 14:47:10.676641 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6498 14:47:10.679712 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6499 14:47:10.683354 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6500 14:47:10.689806 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6501 14:47:10.693028 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6502 14:47:10.696324 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6503 14:47:10.700219 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6504 14:47:10.706174 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6505 14:47:10.709632 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6506 14:47:10.713349 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6507 14:47:10.719807 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6508 14:47:10.722873 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6509 14:47:10.722974 ==
6510 14:47:10.726076 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 14:47:10.729630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 14:47:10.729702 ==
6513 14:47:10.732905 DQS Delay:
6514 14:47:10.733002 DQS0 = 43, DQS1 = 59
6515 14:47:10.735817 DQM Delay:
6516 14:47:10.735915 DQM0 = 10, DQM1 = 14
6517 14:47:10.736002 DQ Delay:
6518 14:47:10.739147 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6519 14:47:10.742322 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6520 14:47:10.745876 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6521 14:47:10.749431 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6522 14:47:10.749512
6523 14:47:10.749576
6524 14:47:10.749635 ==
6525 14:47:10.752515 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 14:47:10.758787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 14:47:10.758871 ==
6528 14:47:10.758936
6529 14:47:10.759005
6530 14:47:10.759103 TX Vref Scan disable
6531 14:47:10.762352 == TX Byte 0 ==
6532 14:47:10.765708 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6533 14:47:10.769058 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6534 14:47:10.772705 == TX Byte 1 ==
6535 14:47:10.775670 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6536 14:47:10.779442 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6537 14:47:10.779544 ==
6538 14:47:10.782343 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 14:47:10.788935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 14:47:10.789040 ==
6541 14:47:10.789130
6542 14:47:10.789214
6543 14:47:10.789324 TX Vref Scan disable
6544 14:47:10.792370 == TX Byte 0 ==
6545 14:47:10.795459 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6546 14:47:10.798567 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6547 14:47:10.801734 == TX Byte 1 ==
6548 14:47:10.805120 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6549 14:47:10.808782 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6550 14:47:10.808884
6551 14:47:10.812136 [DATLAT]
6552 14:47:10.812251 Freq=400, CH0 RK1
6553 14:47:10.812341
6554 14:47:10.815749 DATLAT Default: 0xe
6555 14:47:10.815930 0, 0xFFFF, sum = 0
6556 14:47:10.818704 1, 0xFFFF, sum = 0
6557 14:47:10.818890 2, 0xFFFF, sum = 0
6558 14:47:10.821750 3, 0xFFFF, sum = 0
6559 14:47:10.821938 4, 0xFFFF, sum = 0
6560 14:47:10.825442 5, 0xFFFF, sum = 0
6561 14:47:10.825655 6, 0xFFFF, sum = 0
6562 14:47:10.828719 7, 0xFFFF, sum = 0
6563 14:47:10.828876 8, 0xFFFF, sum = 0
6564 14:47:10.832301 9, 0xFFFF, sum = 0
6565 14:47:10.835333 10, 0xFFFF, sum = 0
6566 14:47:10.835587 11, 0xFFFF, sum = 0
6567 14:47:10.838844 12, 0xFFFF, sum = 0
6568 14:47:10.839117 13, 0x0, sum = 1
6569 14:47:10.842006 14, 0x0, sum = 2
6570 14:47:10.842286 15, 0x0, sum = 3
6571 14:47:10.845221 16, 0x0, sum = 4
6572 14:47:10.845462 best_step = 14
6573 14:47:10.845650
6574 14:47:10.845826 ==
6575 14:47:10.848906 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 14:47:10.851937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 14:47:10.852332 ==
6578 14:47:10.855074 RX Vref Scan: 0
6579 14:47:10.855483
6580 14:47:10.858503 RX Vref 0 -> 0, step: 1
6581 14:47:10.858927
6582 14:47:10.859258 RX Delay -359 -> 252, step: 8
6583 14:47:10.867810 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6584 14:47:10.870879 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6585 14:47:10.873925 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6586 14:47:10.880830 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6587 14:47:10.883698 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6588 14:47:10.887279 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6589 14:47:10.890135 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6590 14:47:10.896518 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6591 14:47:10.900081 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6592 14:47:10.903139 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6593 14:47:10.906520 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6594 14:47:10.913018 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6595 14:47:10.916113 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6596 14:47:10.919456 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6597 14:47:10.926050 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6598 14:47:10.929262 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6599 14:47:10.929482 ==
6600 14:47:10.932305 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 14:47:10.936302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 14:47:10.936475 ==
6603 14:47:10.938969 DQS Delay:
6604 14:47:10.939085 DQS0 = 44, DQS1 = 60
6605 14:47:10.939186 DQM Delay:
6606 14:47:10.942283 DQM0 = 7, DQM1 = 13
6607 14:47:10.942399 DQ Delay:
6608 14:47:10.945586 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =8
6609 14:47:10.948820 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6610 14:47:10.952333 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6611 14:47:10.955666 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6612 14:47:10.955775
6613 14:47:10.955862
6614 14:47:10.965355 [DQSOSCAuto] RK1, (LSB)MR18= 0xb743, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6615 14:47:10.965501 CH0 RK1: MR19=C0C, MR18=B743
6616 14:47:10.971799 CH0_RK1: MR19=0xC0C, MR18=0xB743, DQSOSC=387, MR23=63, INC=394, DEC=262
6617 14:47:10.975401 [RxdqsGatingPostProcess] freq 400
6618 14:47:10.981870 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6619 14:47:10.985154 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 14:47:10.988453 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 14:47:10.991821 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 14:47:10.995359 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 14:47:10.998596 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 14:47:10.998711 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 14:47:11.001573 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 14:47:11.004988 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 14:47:11.008719 Pre-setting of DQS Precalculation
6628 14:47:11.015125 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6629 14:47:11.015234 ==
6630 14:47:11.018768 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 14:47:11.021443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 14:47:11.021561 ==
6633 14:47:11.027906 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 14:47:11.034697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6635 14:47:11.037971 [CA 0] Center 36 (8~64) winsize 57
6636 14:47:11.041073 [CA 1] Center 36 (8~64) winsize 57
6637 14:47:11.044532 [CA 2] Center 36 (8~64) winsize 57
6638 14:47:11.048361 [CA 3] Center 36 (8~64) winsize 57
6639 14:47:11.048474 [CA 4] Center 36 (8~64) winsize 57
6640 14:47:11.051414 [CA 5] Center 36 (8~64) winsize 57
6641 14:47:11.051537
6642 14:47:11.057767 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6643 14:47:11.057885
6644 14:47:11.061188 [CATrainingPosCal] consider 1 rank data
6645 14:47:11.064380 u2DelayCellTimex100 = 270/100 ps
6646 14:47:11.067472 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 14:47:11.070875 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 14:47:11.074381 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 14:47:11.077585 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 14:47:11.080876 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 14:47:11.084428 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 14:47:11.084574
6653 14:47:11.087902 CA PerBit enable=1, Macro0, CA PI delay=36
6654 14:47:11.088080
6655 14:47:11.091412 [CBTSetCACLKResult] CA Dly = 36
6656 14:47:11.094426 CS Dly: 1 (0~32)
6657 14:47:11.094595 ==
6658 14:47:11.098191 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 14:47:11.100848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 14:47:11.101055 ==
6661 14:47:11.107705 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 14:47:11.114106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6663 14:47:11.117405 [CA 0] Center 36 (8~64) winsize 57
6664 14:47:11.120629 [CA 1] Center 36 (8~64) winsize 57
6665 14:47:11.120812 [CA 2] Center 36 (8~64) winsize 57
6666 14:47:11.123702 [CA 3] Center 36 (8~64) winsize 57
6667 14:47:11.127025 [CA 4] Center 36 (8~64) winsize 57
6668 14:47:11.131044 [CA 5] Center 36 (8~64) winsize 57
6669 14:47:11.131367
6670 14:47:11.133902 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6671 14:47:11.134145
6672 14:47:11.140627 [CATrainingPosCal] consider 2 rank data
6673 14:47:11.141012 u2DelayCellTimex100 = 270/100 ps
6674 14:47:11.147210 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 14:47:11.150541 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 14:47:11.154033 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 14:47:11.157395 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 14:47:11.160416 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 14:47:11.163622 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 14:47:11.164172
6681 14:47:11.166842 CA PerBit enable=1, Macro0, CA PI delay=36
6682 14:47:11.167260
6683 14:47:11.170680 [CBTSetCACLKResult] CA Dly = 36
6684 14:47:11.173404 CS Dly: 1 (0~32)
6685 14:47:11.173879
6686 14:47:11.177013 ----->DramcWriteLeveling(PI) begin...
6687 14:47:11.177440 ==
6688 14:47:11.180165 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 14:47:11.183676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 14:47:11.184103 ==
6691 14:47:11.186913 Write leveling (Byte 0): 40 => 8
6692 14:47:11.190148 Write leveling (Byte 1): 40 => 8
6693 14:47:11.194157 DramcWriteLeveling(PI) end<-----
6694 14:47:11.194715
6695 14:47:11.195051 ==
6696 14:47:11.197209 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 14:47:11.200354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 14:47:11.200799 ==
6699 14:47:11.203403 [Gating] SW mode calibration
6700 14:47:11.209878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6701 14:47:11.217148 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6702 14:47:11.219770 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6703 14:47:11.223344 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6704 14:47:11.230077 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 14:47:11.233580 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 14:47:11.236765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 14:47:11.243218 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 14:47:11.246366 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 14:47:11.250013 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 14:47:11.256509 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 14:47:11.259839 Total UI for P1: 0, mck2ui 16
6712 14:47:11.262743 best dqsien dly found for B0: ( 0, 14, 24)
6713 14:47:11.263212 Total UI for P1: 0, mck2ui 16
6714 14:47:11.270560 best dqsien dly found for B1: ( 0, 14, 24)
6715 14:47:11.272946 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6716 14:47:11.276524 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6717 14:47:11.277133
6718 14:47:11.279251 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 14:47:11.282538 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 14:47:11.285792 [Gating] SW calibration Done
6721 14:47:11.286253 ==
6722 14:47:11.289164 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 14:47:11.292373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 14:47:11.292798 ==
6725 14:47:11.295678 RX Vref Scan: 0
6726 14:47:11.296096
6727 14:47:11.299033 RX Vref 0 -> 0, step: 1
6728 14:47:11.299458
6729 14:47:11.299792 RX Delay -410 -> 252, step: 16
6730 14:47:11.305613 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6731 14:47:11.309314 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6732 14:47:11.312577 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6733 14:47:11.318958 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6734 14:47:11.322388 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6735 14:47:11.325393 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6736 14:47:11.328917 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6737 14:47:11.335239 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6738 14:47:11.338859 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6739 14:47:11.342308 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6740 14:47:11.345303 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6741 14:47:11.352154 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6742 14:47:11.355425 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6743 14:47:11.358486 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6744 14:47:11.362006 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6745 14:47:11.368929 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6746 14:47:11.369489 ==
6747 14:47:11.371796 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 14:47:11.375323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 14:47:11.375882 ==
6750 14:47:11.376248 DQS Delay:
6751 14:47:11.378384 DQS0 = 43, DQS1 = 51
6752 14:47:11.378844 DQM Delay:
6753 14:47:11.381452 DQM0 = 12, DQM1 = 14
6754 14:47:11.381912 DQ Delay:
6755 14:47:11.385301 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6756 14:47:11.388434 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6757 14:47:11.391477 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6758 14:47:11.395008 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6759 14:47:11.395557
6760 14:47:11.396011
6761 14:47:11.396361 ==
6762 14:47:11.398019 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 14:47:11.401424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 14:47:11.402000 ==
6765 14:47:11.404979
6766 14:47:11.405469
6767 14:47:11.405901 TX Vref Scan disable
6768 14:47:11.407793 == TX Byte 0 ==
6769 14:47:11.411132 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 14:47:11.414453 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 14:47:11.418037 == TX Byte 1 ==
6772 14:47:11.420744 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 14:47:11.424092 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 14:47:11.424175 ==
6775 14:47:11.427433 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 14:47:11.430659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 14:47:11.434303 ==
6778 14:47:11.434385
6779 14:47:11.434450
6780 14:47:11.434509 TX Vref Scan disable
6781 14:47:11.437423 == TX Byte 0 ==
6782 14:47:11.440726 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6783 14:47:11.444448 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6784 14:47:11.447380 == TX Byte 1 ==
6785 14:47:11.450657 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 14:47:11.454093 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 14:47:11.454284
6788 14:47:11.457562 [DATLAT]
6789 14:47:11.458058 Freq=400, CH1 RK0
6790 14:47:11.458490
6791 14:47:11.460656 DATLAT Default: 0xf
6792 14:47:11.461119 0, 0xFFFF, sum = 0
6793 14:47:11.463915 1, 0xFFFF, sum = 0
6794 14:47:11.464344 2, 0xFFFF, sum = 0
6795 14:47:11.467505 3, 0xFFFF, sum = 0
6796 14:47:11.468023 4, 0xFFFF, sum = 0
6797 14:47:11.470506 5, 0xFFFF, sum = 0
6798 14:47:11.470937 6, 0xFFFF, sum = 0
6799 14:47:11.473923 7, 0xFFFF, sum = 0
6800 14:47:11.474407 8, 0xFFFF, sum = 0
6801 14:47:11.477400 9, 0xFFFF, sum = 0
6802 14:47:11.478008 10, 0xFFFF, sum = 0
6803 14:47:11.481023 11, 0xFFFF, sum = 0
6804 14:47:11.483881 12, 0xFFFF, sum = 0
6805 14:47:11.484438 13, 0x0, sum = 1
6806 14:47:11.484813 14, 0x0, sum = 2
6807 14:47:11.487204 15, 0x0, sum = 3
6808 14:47:11.487674 16, 0x0, sum = 4
6809 14:47:11.490330 best_step = 14
6810 14:47:11.490803
6811 14:47:11.491168 ==
6812 14:47:11.493697 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 14:47:11.496898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 14:47:11.497345 ==
6815 14:47:11.500159 RX Vref Scan: 1
6816 14:47:11.500577
6817 14:47:11.503401 RX Vref 0 -> 0, step: 1
6818 14:47:11.503821
6819 14:47:11.504245 RX Delay -343 -> 252, step: 8
6820 14:47:11.504698
6821 14:47:11.506785 Set Vref, RX VrefLevel [Byte0]: 52
6822 14:47:11.509849 [Byte1]: 54
6823 14:47:11.516192
6824 14:47:11.516700 Final RX Vref Byte 0 = 52 to rank0
6825 14:47:11.518884 Final RX Vref Byte 1 = 54 to rank0
6826 14:47:11.521968 Final RX Vref Byte 0 = 52 to rank1
6827 14:47:11.525034 Final RX Vref Byte 1 = 54 to rank1==
6828 14:47:11.528617 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 14:47:11.535036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 14:47:11.535464 ==
6831 14:47:11.535799 DQS Delay:
6832 14:47:11.538186 DQS0 = 48, DQS1 = 56
6833 14:47:11.538609 DQM Delay:
6834 14:47:11.538943 DQM0 = 11, DQM1 = 11
6835 14:47:11.541390 DQ Delay:
6836 14:47:11.544521 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6837 14:47:11.548157 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6838 14:47:11.548673 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6839 14:47:11.554771 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6840 14:47:11.555196
6841 14:47:11.555780
6842 14:47:11.561497 [DQSOSCAuto] RK0, (LSB)MR18= 0x9369, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6843 14:47:11.564525 CH1 RK0: MR19=C0C, MR18=9369
6844 14:47:11.571674 CH1_RK0: MR19=0xC0C, MR18=0x9369, DQSOSC=391, MR23=63, INC=386, DEC=257
6845 14:47:11.572219 ==
6846 14:47:11.574581 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 14:47:11.578230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 14:47:11.578793 ==
6849 14:47:11.581271 [Gating] SW mode calibration
6850 14:47:11.587926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6851 14:47:11.594493 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6852 14:47:11.598128 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6853 14:47:11.601187 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6854 14:47:11.607340 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 14:47:11.610711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 14:47:11.614151 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 14:47:11.620305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 14:47:11.624261 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 14:47:11.626982 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 14:47:11.633856 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 14:47:11.637333 Total UI for P1: 0, mck2ui 16
6862 14:47:11.640511 best dqsien dly found for B0: ( 0, 14, 24)
6863 14:47:11.643310 Total UI for P1: 0, mck2ui 16
6864 14:47:11.646947 best dqsien dly found for B1: ( 0, 14, 24)
6865 14:47:11.650408 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6866 14:47:11.653455 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6867 14:47:11.653932
6868 14:47:11.656874 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 14:47:11.659836 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 14:47:11.663060 [Gating] SW calibration Done
6871 14:47:11.663539 ==
6872 14:47:11.666250 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 14:47:11.669704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 14:47:11.670219 ==
6875 14:47:11.673314 RX Vref Scan: 0
6876 14:47:11.673793
6877 14:47:11.676502 RX Vref 0 -> 0, step: 1
6878 14:47:11.677093
6879 14:47:11.680146 RX Delay -410 -> 252, step: 16
6880 14:47:11.683146 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6881 14:47:11.686246 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6882 14:47:11.689747 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6883 14:47:11.696684 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6884 14:47:11.699517 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6885 14:47:11.703277 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6886 14:47:11.706146 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6887 14:47:11.713143 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6888 14:47:11.716193 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6889 14:47:11.719340 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6890 14:47:11.722780 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6891 14:47:11.729887 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6892 14:47:11.733207 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6893 14:47:11.736200 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6894 14:47:11.742539 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6895 14:47:11.746079 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6896 14:47:11.746678 ==
6897 14:47:11.749260 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 14:47:11.752516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 14:47:11.752981 ==
6900 14:47:11.755731 DQS Delay:
6901 14:47:11.756191 DQS0 = 43, DQS1 = 51
6902 14:47:11.756565 DQM Delay:
6903 14:47:11.759050 DQM0 = 12, DQM1 = 14
6904 14:47:11.759560 DQ Delay:
6905 14:47:11.762500 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6906 14:47:11.765753 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6907 14:47:11.769052 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6908 14:47:11.772488 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6909 14:47:11.772953
6910 14:47:11.773315
6911 14:47:11.773761 ==
6912 14:47:11.775283 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 14:47:11.778888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 14:47:11.781849 ==
6915 14:47:11.782356
6916 14:47:11.782724
6917 14:47:11.783062 TX Vref Scan disable
6918 14:47:11.785631 == TX Byte 0 ==
6919 14:47:11.788422 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6920 14:47:11.791850 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6921 14:47:11.795118 == TX Byte 1 ==
6922 14:47:11.798628 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6923 14:47:11.801868 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6924 14:47:11.802334 ==
6925 14:47:11.805554 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 14:47:11.811639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 14:47:11.812064 ==
6928 14:47:11.812397
6929 14:47:11.812706
6930 14:47:11.813024 TX Vref Scan disable
6931 14:47:11.814706 == TX Byte 0 ==
6932 14:47:11.818611 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6933 14:47:11.821958 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6934 14:47:11.824739 == TX Byte 1 ==
6935 14:47:11.828408 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6936 14:47:11.831921 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6937 14:47:11.832435
6938 14:47:11.834755 [DATLAT]
6939 14:47:11.835351 Freq=400, CH1 RK1
6940 14:47:11.835695
6941 14:47:11.838456 DATLAT Default: 0xe
6942 14:47:11.838967 0, 0xFFFF, sum = 0
6943 14:47:11.841752 1, 0xFFFF, sum = 0
6944 14:47:11.842194 2, 0xFFFF, sum = 0
6945 14:47:11.845016 3, 0xFFFF, sum = 0
6946 14:47:11.845438 4, 0xFFFF, sum = 0
6947 14:47:11.848011 5, 0xFFFF, sum = 0
6948 14:47:11.848436 6, 0xFFFF, sum = 0
6949 14:47:11.851978 7, 0xFFFF, sum = 0
6950 14:47:11.852501 8, 0xFFFF, sum = 0
6951 14:47:11.854647 9, 0xFFFF, sum = 0
6952 14:47:11.855124 10, 0xFFFF, sum = 0
6953 14:47:11.857950 11, 0xFFFF, sum = 0
6954 14:47:11.861156 12, 0xFFFF, sum = 0
6955 14:47:11.861579 13, 0x0, sum = 1
6956 14:47:11.861913 14, 0x0, sum = 2
6957 14:47:11.864977 15, 0x0, sum = 3
6958 14:47:11.865401 16, 0x0, sum = 4
6959 14:47:11.868612 best_step = 14
6960 14:47:11.869119
6961 14:47:11.869451 ==
6962 14:47:11.871135 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 14:47:11.874870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 14:47:11.875382 ==
6965 14:47:11.878351 RX Vref Scan: 0
6966 14:47:11.878880
6967 14:47:11.879217 RX Vref 0 -> 0, step: 1
6968 14:47:11.881237
6969 14:47:11.881746 RX Delay -343 -> 252, step: 8
6970 14:47:11.889842 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6971 14:47:11.892680 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6972 14:47:11.895983 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6973 14:47:11.899829 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6974 14:47:11.905978 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6975 14:47:11.909315 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6976 14:47:11.912540 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6977 14:47:11.915766 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6978 14:47:11.922822 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6979 14:47:11.926210 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6980 14:47:11.930054 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6981 14:47:11.936105 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6982 14:47:11.938961 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6983 14:47:11.942542 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6984 14:47:11.946261 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6985 14:47:11.952705 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6986 14:47:11.953259 ==
6987 14:47:11.955745 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 14:47:11.959036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 14:47:11.959503 ==
6990 14:47:11.959881 DQS Delay:
6991 14:47:11.961947 DQS0 = 44, DQS1 = 56
6992 14:47:11.962506 DQM Delay:
6993 14:47:11.965617 DQM0 = 8, DQM1 = 11
6994 14:47:11.966230 DQ Delay:
6995 14:47:11.968662 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6996 14:47:11.972155 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6997 14:47:11.975254 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6998 14:47:11.978746 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6999 14:47:11.979308
7000 14:47:11.979722
7001 14:47:11.985293 [DQSOSCAuto] RK1, (LSB)MR18= 0x6252, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7002 14:47:11.988450 CH1 RK1: MR19=C0C, MR18=6252
7003 14:47:11.994913 CH1_RK1: MR19=0xC0C, MR18=0x6252, DQSOSC=397, MR23=63, INC=374, DEC=249
7004 14:47:11.998848 [RxdqsGatingPostProcess] freq 400
7005 14:47:12.004758 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7006 14:47:12.008240 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 14:47:12.011359 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 14:47:12.014638 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 14:47:12.018467 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 14:47:12.018990 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 14:47:12.021772 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 14:47:12.024847 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 14:47:12.028606 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 14:47:12.031321 Pre-setting of DQS Precalculation
7015 14:47:12.038414 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7016 14:47:12.044403 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7017 14:47:12.051348 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7018 14:47:12.051768
7019 14:47:12.052091
7020 14:47:12.054213 [Calibration Summary] 800 Mbps
7021 14:47:12.054672 CH 0, Rank 0
7022 14:47:12.057543 SW Impedance : PASS
7023 14:47:12.060864 DUTY Scan : NO K
7024 14:47:12.061310 ZQ Calibration : PASS
7025 14:47:12.064275 Jitter Meter : NO K
7026 14:47:12.067858 CBT Training : PASS
7027 14:47:12.068272 Write leveling : PASS
7028 14:47:12.071063 RX DQS gating : PASS
7029 14:47:12.073944 RX DQ/DQS(RDDQC) : PASS
7030 14:47:12.074391 TX DQ/DQS : PASS
7031 14:47:12.077710 RX DATLAT : PASS
7032 14:47:12.080994 RX DQ/DQS(Engine): PASS
7033 14:47:12.081504 TX OE : NO K
7034 14:47:12.084578 All Pass.
7035 14:47:12.085103
7036 14:47:12.085442 CH 0, Rank 1
7037 14:47:12.087308 SW Impedance : PASS
7038 14:47:12.087797 DUTY Scan : NO K
7039 14:47:12.090604 ZQ Calibration : PASS
7040 14:47:12.093803 Jitter Meter : NO K
7041 14:47:12.094340 CBT Training : PASS
7042 14:47:12.097055 Write leveling : NO K
7043 14:47:12.100462 RX DQS gating : PASS
7044 14:47:12.100874 RX DQ/DQS(RDDQC) : PASS
7045 14:47:12.103489 TX DQ/DQS : PASS
7046 14:47:12.106785 RX DATLAT : PASS
7047 14:47:12.107197 RX DQ/DQS(Engine): PASS
7048 14:47:12.110105 TX OE : NO K
7049 14:47:12.110557 All Pass.
7050 14:47:12.110882
7051 14:47:12.113464 CH 1, Rank 0
7052 14:47:12.113873 SW Impedance : PASS
7053 14:47:12.117281 DUTY Scan : NO K
7054 14:47:12.119740 ZQ Calibration : PASS
7055 14:47:12.120154 Jitter Meter : NO K
7056 14:47:12.123605 CBT Training : PASS
7057 14:47:12.126857 Write leveling : PASS
7058 14:47:12.127273 RX DQS gating : PASS
7059 14:47:12.129809 RX DQ/DQS(RDDQC) : PASS
7060 14:47:12.133426 TX DQ/DQS : PASS
7061 14:47:12.133950 RX DATLAT : PASS
7062 14:47:12.136441 RX DQ/DQS(Engine): PASS
7063 14:47:12.136873 TX OE : NO K
7064 14:47:12.139604 All Pass.
7065 14:47:12.140043
7066 14:47:12.140409 CH 1, Rank 1
7067 14:47:12.142974 SW Impedance : PASS
7068 14:47:12.143389 DUTY Scan : NO K
7069 14:47:12.146585 ZQ Calibration : PASS
7070 14:47:12.149498 Jitter Meter : NO K
7071 14:47:12.149911 CBT Training : PASS
7072 14:47:12.152903 Write leveling : NO K
7073 14:47:12.155990 RX DQS gating : PASS
7074 14:47:12.156404 RX DQ/DQS(RDDQC) : PASS
7075 14:47:12.159373 TX DQ/DQS : PASS
7076 14:47:12.162987 RX DATLAT : PASS
7077 14:47:12.163446 RX DQ/DQS(Engine): PASS
7078 14:47:12.166040 TX OE : NO K
7079 14:47:12.166501 All Pass.
7080 14:47:12.166832
7081 14:47:12.169384 DramC Write-DBI off
7082 14:47:12.172722 PER_BANK_REFRESH: Hybrid Mode
7083 14:47:12.173292 TX_TRACKING: ON
7084 14:47:12.182271 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7085 14:47:12.185607 [FAST_K] Save calibration result to emmc
7086 14:47:12.188916 dramc_set_vcore_voltage set vcore to 725000
7087 14:47:12.192123 Read voltage for 1600, 0
7088 14:47:12.192693 Vio18 = 0
7089 14:47:12.196347 Vcore = 725000
7090 14:47:12.196853 Vdram = 0
7091 14:47:12.197186 Vddq = 0
7092 14:47:12.197492 Vmddr = 0
7093 14:47:12.202258 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7094 14:47:12.209015 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7095 14:47:12.209520 MEM_TYPE=3, freq_sel=13
7096 14:47:12.211805 sv_algorithm_assistance_LP4_3733
7097 14:47:12.215315 ============ PULL DRAM RESETB DOWN ============
7098 14:47:12.222305 ========== PULL DRAM RESETB DOWN end =========
7099 14:47:12.225183 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7100 14:47:12.228648 ===================================
7101 14:47:12.231594 LPDDR4 DRAM CONFIGURATION
7102 14:47:12.235235 ===================================
7103 14:47:12.235652 EX_ROW_EN[0] = 0x0
7104 14:47:12.237991 EX_ROW_EN[1] = 0x0
7105 14:47:12.241703 LP4Y_EN = 0x0
7106 14:47:12.242120 WORK_FSP = 0x1
7107 14:47:12.244886 WL = 0x5
7108 14:47:12.245550 RL = 0x5
7109 14:47:12.248334 BL = 0x2
7110 14:47:12.248797 RPST = 0x0
7111 14:47:12.251417 RD_PRE = 0x0
7112 14:47:12.252006 WR_PRE = 0x1
7113 14:47:12.255103 WR_PST = 0x1
7114 14:47:12.255515 DBI_WR = 0x0
7115 14:47:12.258109 DBI_RD = 0x0
7116 14:47:12.258592 OTF = 0x1
7117 14:47:12.261296 ===================================
7118 14:47:12.264704 ===================================
7119 14:47:12.267652 ANA top config
7120 14:47:12.270898 ===================================
7121 14:47:12.274222 DLL_ASYNC_EN = 0
7122 14:47:12.274587 ALL_SLAVE_EN = 0
7123 14:47:12.277455 NEW_RANK_MODE = 1
7124 14:47:12.281014 DLL_IDLE_MODE = 1
7125 14:47:12.284106 LP45_APHY_COMB_EN = 1
7126 14:47:12.284398 TX_ODT_DIS = 0
7127 14:47:12.287303 NEW_8X_MODE = 1
7128 14:47:12.290486 ===================================
7129 14:47:12.293841 ===================================
7130 14:47:12.297053 data_rate = 3200
7131 14:47:12.300842 CKR = 1
7132 14:47:12.303767 DQ_P2S_RATIO = 8
7133 14:47:12.307351 ===================================
7134 14:47:12.310350 CA_P2S_RATIO = 8
7135 14:47:12.313935 DQ_CA_OPEN = 0
7136 14:47:12.314345 DQ_SEMI_OPEN = 0
7137 14:47:12.316924 CA_SEMI_OPEN = 0
7138 14:47:12.320219 CA_FULL_RATE = 0
7139 14:47:12.323649 DQ_CKDIV4_EN = 0
7140 14:47:12.326980 CA_CKDIV4_EN = 0
7141 14:47:12.329952 CA_PREDIV_EN = 0
7142 14:47:12.330324 PH8_DLY = 12
7143 14:47:12.333415 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7144 14:47:12.336758 DQ_AAMCK_DIV = 4
7145 14:47:12.340770 CA_AAMCK_DIV = 4
7146 14:47:12.343771 CA_ADMCK_DIV = 4
7147 14:47:12.347058 DQ_TRACK_CA_EN = 0
7148 14:47:12.350282 CA_PICK = 1600
7149 14:47:12.350666 CA_MCKIO = 1600
7150 14:47:12.353995 MCKIO_SEMI = 0
7151 14:47:12.356650 PLL_FREQ = 3068
7152 14:47:12.360065 DQ_UI_PI_RATIO = 32
7153 14:47:12.363398 CA_UI_PI_RATIO = 0
7154 14:47:12.367039 ===================================
7155 14:47:12.369827 ===================================
7156 14:47:12.373363 memory_type:LPDDR4
7157 14:47:12.373941 GP_NUM : 10
7158 14:47:12.376330 SRAM_EN : 1
7159 14:47:12.379817 MD32_EN : 0
7160 14:47:12.382954 ===================================
7161 14:47:12.383464 [ANA_INIT] >>>>>>>>>>>>>>
7162 14:47:12.385946 <<<<<< [CONFIGURE PHASE]: ANA_TX
7163 14:47:12.389606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7164 14:47:12.392879 ===================================
7165 14:47:12.395848 data_rate = 3200,PCW = 0X7600
7166 14:47:12.399384 ===================================
7167 14:47:12.402597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7168 14:47:12.408946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 14:47:12.412665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 14:47:12.419058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7171 14:47:12.422504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7172 14:47:12.425977 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7173 14:47:12.426578 [ANA_INIT] flow start
7174 14:47:12.429429 [ANA_INIT] PLL >>>>>>>>
7175 14:47:12.432383 [ANA_INIT] PLL <<<<<<<<
7176 14:47:12.435837 [ANA_INIT] MIDPI >>>>>>>>
7177 14:47:12.436252 [ANA_INIT] MIDPI <<<<<<<<
7178 14:47:12.438682 [ANA_INIT] DLL >>>>>>>>
7179 14:47:12.442791 [ANA_INIT] DLL <<<<<<<<
7180 14:47:12.443216 [ANA_INIT] flow end
7181 14:47:12.445362 ============ LP4 DIFF to SE enter ============
7182 14:47:12.451971 ============ LP4 DIFF to SE exit ============
7183 14:47:12.452487 [ANA_INIT] <<<<<<<<<<<<<
7184 14:47:12.455613 [Flow] Enable top DCM control >>>>>
7185 14:47:12.458844 [Flow] Enable top DCM control <<<<<
7186 14:47:12.462329 Enable DLL master slave shuffle
7187 14:47:12.469236 ==============================================================
7188 14:47:12.471984 Gating Mode config
7189 14:47:12.475262 ==============================================================
7190 14:47:12.478998 Config description:
7191 14:47:12.488619 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7192 14:47:12.495251 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7193 14:47:12.498615 SELPH_MODE 0: By rank 1: By Phase
7194 14:47:12.504719 ==============================================================
7195 14:47:12.507980 GAT_TRACK_EN = 1
7196 14:47:12.510989 RX_GATING_MODE = 2
7197 14:47:12.514545 RX_GATING_TRACK_MODE = 2
7198 14:47:12.517813 SELPH_MODE = 1
7199 14:47:12.521282 PICG_EARLY_EN = 1
7200 14:47:12.521796 VALID_LAT_VALUE = 1
7201 14:47:12.527546 ==============================================================
7202 14:47:12.530882 Enter into Gating configuration >>>>
7203 14:47:12.534456 Exit from Gating configuration <<<<
7204 14:47:12.537486 Enter into DVFS_PRE_config >>>>>
7205 14:47:12.547460 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7206 14:47:12.551396 Exit from DVFS_PRE_config <<<<<
7207 14:47:12.553953 Enter into PICG configuration >>>>
7208 14:47:12.557398 Exit from PICG configuration <<<<
7209 14:47:12.560404 [RX_INPUT] configuration >>>>>
7210 14:47:12.564269 [RX_INPUT] configuration <<<<<
7211 14:47:12.570696 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7212 14:47:12.574088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7213 14:47:12.580523 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7214 14:47:12.587153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7215 14:47:12.594314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7216 14:47:12.600447 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7217 14:47:12.603642 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7218 14:47:12.606860 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7219 14:47:12.610261 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7220 14:47:12.616622 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7221 14:47:12.620094 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7222 14:47:12.623358 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 14:47:12.626592 ===================================
7224 14:47:12.629866 LPDDR4 DRAM CONFIGURATION
7225 14:47:12.633082 ===================================
7226 14:47:12.633635 EX_ROW_EN[0] = 0x0
7227 14:47:12.636292 EX_ROW_EN[1] = 0x0
7228 14:47:12.640230 LP4Y_EN = 0x0
7229 14:47:12.640641 WORK_FSP = 0x1
7230 14:47:12.643112 WL = 0x5
7231 14:47:12.643529 RL = 0x5
7232 14:47:12.646385 BL = 0x2
7233 14:47:12.646829 RPST = 0x0
7234 14:47:12.649935 RD_PRE = 0x0
7235 14:47:12.650469 WR_PRE = 0x1
7236 14:47:12.653180 WR_PST = 0x1
7237 14:47:12.653607 DBI_WR = 0x0
7238 14:47:12.657009 DBI_RD = 0x0
7239 14:47:12.657420 OTF = 0x1
7240 14:47:12.659962 ===================================
7241 14:47:12.662878 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7242 14:47:12.669676 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7243 14:47:12.672961 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7244 14:47:12.676792 ===================================
7245 14:47:12.679898 LPDDR4 DRAM CONFIGURATION
7246 14:47:12.683400 ===================================
7247 14:47:12.683842 EX_ROW_EN[0] = 0x10
7248 14:47:12.685935 EX_ROW_EN[1] = 0x0
7249 14:47:12.689428 LP4Y_EN = 0x0
7250 14:47:12.689841 WORK_FSP = 0x1
7251 14:47:12.692962 WL = 0x5
7252 14:47:12.693405 RL = 0x5
7253 14:47:12.696212 BL = 0x2
7254 14:47:12.696623 RPST = 0x0
7255 14:47:12.699653 RD_PRE = 0x0
7256 14:47:12.700323 WR_PRE = 0x1
7257 14:47:12.702861 WR_PST = 0x1
7258 14:47:12.703273 DBI_WR = 0x0
7259 14:47:12.705850 DBI_RD = 0x0
7260 14:47:12.706303 OTF = 0x1
7261 14:47:12.709533 ===================================
7262 14:47:12.715688 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7263 14:47:12.716134 ==
7264 14:47:12.719504 Dram Type= 6, Freq= 0, CH_0, rank 0
7265 14:47:12.722921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7266 14:47:12.725974 ==
7267 14:47:12.726553 [Duty_Offset_Calibration]
7268 14:47:12.729540 B0:1 B1:-1 CA:0
7269 14:47:12.730049
7270 14:47:12.732652 [DutyScan_Calibration_Flow] k_type=0
7271 14:47:12.741666
7272 14:47:12.742228 ==CLK 0==
7273 14:47:12.744801 Final CLK duty delay cell = 0
7274 14:47:12.747934 [0] MAX Duty = 5124%(X100), DQS PI = 22
7275 14:47:12.751385 [0] MIN Duty = 4907%(X100), DQS PI = 6
7276 14:47:12.754504 [0] AVG Duty = 5015%(X100)
7277 14:47:12.754920
7278 14:47:12.758101 CH0 CLK Duty spec in!! Max-Min= 217%
7279 14:47:12.761361 [DutyScan_Calibration_Flow] ====Done====
7280 14:47:12.761916
7281 14:47:12.764426 [DutyScan_Calibration_Flow] k_type=1
7282 14:47:12.780695
7283 14:47:12.781153 ==DQS 0 ==
7284 14:47:12.784187 Final DQS duty delay cell = -4
7285 14:47:12.787244 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7286 14:47:12.790775 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7287 14:47:12.794326 [-4] AVG Duty = 4906%(X100)
7288 14:47:12.794832
7289 14:47:12.795158 ==DQS 1 ==
7290 14:47:12.797230 Final DQS duty delay cell = 0
7291 14:47:12.800526 [0] MAX Duty = 5156%(X100), DQS PI = 0
7292 14:47:12.803570 [0] MIN Duty = 5000%(X100), DQS PI = 20
7293 14:47:12.806750 [0] AVG Duty = 5078%(X100)
7294 14:47:12.807329
7295 14:47:12.810207 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7296 14:47:12.810752
7297 14:47:12.813266 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7298 14:47:12.816624 [DutyScan_Calibration_Flow] ====Done====
7299 14:47:12.817064
7300 14:47:12.819797 [DutyScan_Calibration_Flow] k_type=3
7301 14:47:12.838114
7302 14:47:12.838855 ==DQM 0 ==
7303 14:47:12.841609 Final DQM duty delay cell = 0
7304 14:47:12.844656 [0] MAX Duty = 5124%(X100), DQS PI = 20
7305 14:47:12.848305 [0] MIN Duty = 4875%(X100), DQS PI = 10
7306 14:47:12.851456 [0] AVG Duty = 4999%(X100)
7307 14:47:12.852092
7308 14:47:12.852609 ==DQM 1 ==
7309 14:47:12.854694 Final DQM duty delay cell = 0
7310 14:47:12.858320 [0] MAX Duty = 5000%(X100), DQS PI = 4
7311 14:47:12.861782 [0] MIN Duty = 4782%(X100), DQS PI = 20
7312 14:47:12.864752 [0] AVG Duty = 4891%(X100)
7313 14:47:12.865381
7314 14:47:12.867490 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7315 14:47:12.868053
7316 14:47:12.870985 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7317 14:47:12.874478 [DutyScan_Calibration_Flow] ====Done====
7318 14:47:12.874900
7319 14:47:12.877624 [DutyScan_Calibration_Flow] k_type=2
7320 14:47:12.894493
7321 14:47:12.895037 ==DQ 0 ==
7322 14:47:12.897453 Final DQ duty delay cell = -4
7323 14:47:12.901459 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7324 14:47:12.904521 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7325 14:47:12.908146 [-4] AVG Duty = 4953%(X100)
7326 14:47:12.908652
7327 14:47:12.908982 ==DQ 1 ==
7328 14:47:12.910830 Final DQ duty delay cell = 0
7329 14:47:12.914282 [0] MAX Duty = 5125%(X100), DQS PI = 2
7330 14:47:12.917840 [0] MIN Duty = 5000%(X100), DQS PI = 36
7331 14:47:12.920757 [0] AVG Duty = 5062%(X100)
7332 14:47:12.921436
7333 14:47:12.924279 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7334 14:47:12.924733
7335 14:47:12.927179 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7336 14:47:12.930837 [DutyScan_Calibration_Flow] ====Done====
7337 14:47:12.931408 ==
7338 14:47:12.934077 Dram Type= 6, Freq= 0, CH_1, rank 0
7339 14:47:12.937223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7340 14:47:12.937691 ==
7341 14:47:12.941296 [Duty_Offset_Calibration]
7342 14:47:12.941848 B0:-1 B1:1 CA:2
7343 14:47:12.944110
7344 14:47:12.944569 [DutyScan_Calibration_Flow] k_type=0
7345 14:47:12.955123
7346 14:47:12.955665 ==CLK 0==
7347 14:47:12.958811 Final CLK duty delay cell = 0
7348 14:47:12.961509 [0] MAX Duty = 5187%(X100), DQS PI = 24
7349 14:47:12.965076 [0] MIN Duty = 4969%(X100), DQS PI = 0
7350 14:47:12.968477 [0] AVG Duty = 5078%(X100)
7351 14:47:12.969029
7352 14:47:12.971266 CH1 CLK Duty spec in!! Max-Min= 218%
7353 14:47:12.975030 [DutyScan_Calibration_Flow] ====Done====
7354 14:47:12.975519
7355 14:47:12.978228 [DutyScan_Calibration_Flow] k_type=1
7356 14:47:12.995153
7357 14:47:12.995742 ==DQS 0 ==
7358 14:47:12.998118 Final DQS duty delay cell = 0
7359 14:47:13.001698 [0] MAX Duty = 5124%(X100), DQS PI = 18
7360 14:47:13.004930 [0] MIN Duty = 4907%(X100), DQS PI = 10
7361 14:47:13.007989 [0] AVG Duty = 5015%(X100)
7362 14:47:13.008543
7363 14:47:13.008907 ==DQS 1 ==
7364 14:47:13.011103 Final DQS duty delay cell = 0
7365 14:47:13.015118 [0] MAX Duty = 5093%(X100), DQS PI = 28
7366 14:47:13.018208 [0] MIN Duty = 4938%(X100), DQS PI = 58
7367 14:47:13.020959 [0] AVG Duty = 5015%(X100)
7368 14:47:13.021613
7369 14:47:13.024861 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7370 14:47:13.025414
7371 14:47:13.027478 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7372 14:47:13.031352 [DutyScan_Calibration_Flow] ====Done====
7373 14:47:13.032003
7374 14:47:13.034647 [DutyScan_Calibration_Flow] k_type=3
7375 14:47:13.052021
7376 14:47:13.052572 ==DQM 0 ==
7377 14:47:13.055025 Final DQM duty delay cell = 0
7378 14:47:13.058141 [0] MAX Duty = 5218%(X100), DQS PI = 18
7379 14:47:13.061948 [0] MIN Duty = 5031%(X100), DQS PI = 8
7380 14:47:13.065174 [0] AVG Duty = 5124%(X100)
7381 14:47:13.065886
7382 14:47:13.066517 ==DQM 1 ==
7383 14:47:13.068374 Final DQM duty delay cell = 0
7384 14:47:13.071594 [0] MAX Duty = 5156%(X100), DQS PI = 6
7385 14:47:13.074812 [0] MIN Duty = 4938%(X100), DQS PI = 34
7386 14:47:13.078277 [0] AVG Duty = 5047%(X100)
7387 14:47:13.078734
7388 14:47:13.081439 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7389 14:47:13.081896
7390 14:47:13.085208 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7391 14:47:13.087789 [DutyScan_Calibration_Flow] ====Done====
7392 14:47:13.088247
7393 14:47:13.091404 [DutyScan_Calibration_Flow] k_type=2
7394 14:47:13.108603
7395 14:47:13.109147 ==DQ 0 ==
7396 14:47:13.111943 Final DQ duty delay cell = 0
7397 14:47:13.115079 [0] MAX Duty = 5156%(X100), DQS PI = 30
7398 14:47:13.118273 [0] MIN Duty = 4906%(X100), DQS PI = 8
7399 14:47:13.118732 [0] AVG Duty = 5031%(X100)
7400 14:47:13.121853
7401 14:47:13.122346 ==DQ 1 ==
7402 14:47:13.125248 Final DQ duty delay cell = 0
7403 14:47:13.128156 [0] MAX Duty = 5156%(X100), DQS PI = 10
7404 14:47:13.131777 [0] MIN Duty = 4969%(X100), DQS PI = 56
7405 14:47:13.134702 [0] AVG Duty = 5062%(X100)
7406 14:47:13.135160
7407 14:47:13.137853 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7408 14:47:13.138344
7409 14:47:13.141472 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7410 14:47:13.144583 [DutyScan_Calibration_Flow] ====Done====
7411 14:47:13.147829 nWR fixed to 30
7412 14:47:13.151363 [ModeRegInit_LP4] CH0 RK0
7413 14:47:13.151888 [ModeRegInit_LP4] CH0 RK1
7414 14:47:13.154632 [ModeRegInit_LP4] CH1 RK0
7415 14:47:13.158235 [ModeRegInit_LP4] CH1 RK1
7416 14:47:13.158764 match AC timing 5
7417 14:47:13.164303 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7418 14:47:13.167659 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7419 14:47:13.170752 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7420 14:47:13.177834 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7421 14:47:13.181064 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7422 14:47:13.181632 [MiockJmeterHQA]
7423 14:47:13.182001
7424 14:47:13.184410 [DramcMiockJmeter] u1RxGatingPI = 0
7425 14:47:13.187136 0 : 4257, 4029
7426 14:47:13.187610 4 : 4253, 4026
7427 14:47:13.190731 8 : 4363, 4137
7428 14:47:13.191202 12 : 4258, 4029
7429 14:47:13.194510 16 : 4252, 4027
7430 14:47:13.195009 20 : 4253, 4026
7431 14:47:13.195382 24 : 4366, 4140
7432 14:47:13.197187 28 : 4252, 4027
7433 14:47:13.197657 32 : 4255, 4029
7434 14:47:13.200899 36 : 4252, 4027
7435 14:47:13.201458 40 : 4363, 4137
7436 14:47:13.203791 44 : 4252, 4027
7437 14:47:13.204261 48 : 4363, 4137
7438 14:47:13.207696 52 : 4252, 4027
7439 14:47:13.208257 56 : 4252, 4027
7440 14:47:13.208633 60 : 4253, 4026
7441 14:47:13.210513 64 : 4255, 4030
7442 14:47:13.211090 68 : 4360, 4137
7443 14:47:13.213720 72 : 4250, 4027
7444 14:47:13.214229 76 : 4360, 4138
7445 14:47:13.217197 80 : 4250, 4027
7446 14:47:13.217666 84 : 4250, 4027
7447 14:47:13.220467 88 : 4249, 4027
7448 14:47:13.221073 92 : 4360, 476
7449 14:47:13.221453 96 : 4250, 0
7450 14:47:13.223631 100 : 4250, 0
7451 14:47:13.224102 104 : 4363, 0
7452 14:47:13.227264 108 : 4363, 0
7453 14:47:13.227732 112 : 4363, 0
7454 14:47:13.228104 116 : 4253, 0
7455 14:47:13.230116 120 : 4361, 0
7456 14:47:13.230625 124 : 4249, 0
7457 14:47:13.231003 128 : 4250, 0
7458 14:47:13.233695 132 : 4249, 0
7459 14:47:13.234123 136 : 4252, 0
7460 14:47:13.236978 140 : 4252, 0
7461 14:47:13.237529 144 : 4360, 0
7462 14:47:13.237889 148 : 4250, 0
7463 14:47:13.240154 152 : 4250, 0
7464 14:47:13.240678 156 : 4250, 0
7465 14:47:13.243714 160 : 4361, 0
7466 14:47:13.244145 164 : 4360, 0
7467 14:47:13.244487 168 : 4250, 0
7468 14:47:13.247026 172 : 4361, 0
7469 14:47:13.247609 176 : 4249, 0
7470 14:47:13.250146 180 : 4250, 0
7471 14:47:13.250630 184 : 4250, 0
7472 14:47:13.250968 188 : 4250, 0
7473 14:47:13.253431 192 : 4252, 0
7474 14:47:13.253948 196 : 4360, 0
7475 14:47:13.256833 200 : 4250, 0
7476 14:47:13.257348 204 : 4250, 0
7477 14:47:13.257709 208 : 4250, 0
7478 14:47:13.259941 212 : 4361, 0
7479 14:47:13.260383 216 : 4361, 0
7480 14:47:13.263296 220 : 4250, 0
7481 14:47:13.263816 224 : 4361, 117
7482 14:47:13.264155 228 : 4250, 2968
7483 14:47:13.266743 232 : 4360, 4138
7484 14:47:13.267395 236 : 4252, 4029
7485 14:47:13.269668 240 : 4250, 4027
7486 14:47:13.270092 244 : 4250, 4027
7487 14:47:13.273023 248 : 4252, 4029
7488 14:47:13.273451 252 : 4250, 4027
7489 14:47:13.276334 256 : 4250, 4027
7490 14:47:13.276761 260 : 4250, 4026
7491 14:47:13.280189 264 : 4253, 4029
7492 14:47:13.280709 268 : 4250, 4027
7493 14:47:13.282953 272 : 4360, 4138
7494 14:47:13.283379 276 : 4360, 4137
7495 14:47:13.286526 280 : 4250, 4027
7496 14:47:13.286955 284 : 4362, 4140
7497 14:47:13.287293 288 : 4360, 4137
7498 14:47:13.289795 292 : 4249, 4027
7499 14:47:13.290259 296 : 4250, 4027
7500 14:47:13.292632 300 : 4253, 4029
7501 14:47:13.293060 304 : 4250, 4027
7502 14:47:13.296315 308 : 4250, 4027
7503 14:47:13.296837 312 : 4250, 4027
7504 14:47:13.299902 316 : 4253, 4029
7505 14:47:13.300330 320 : 4250, 4027
7506 14:47:13.302721 324 : 4362, 4140
7507 14:47:13.303152 328 : 4360, 4138
7508 14:47:13.306324 332 : 4250, 4027
7509 14:47:13.306841 336 : 4363, 3961
7510 14:47:13.309463 340 : 4360, 1784
7511 14:47:13.309983
7512 14:47:13.310365 MIOCK jitter meter ch=0
7513 14:47:13.310679
7514 14:47:13.312672 1T = (340-92) = 248 dly cells
7515 14:47:13.319256 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7516 14:47:13.319796 ==
7517 14:47:13.322475 Dram Type= 6, Freq= 0, CH_0, rank 0
7518 14:47:13.325968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 14:47:13.326580 ==
7520 14:47:13.332335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7521 14:47:13.336016 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7522 14:47:13.339317 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7523 14:47:13.345417 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7524 14:47:13.355359 [CA 0] Center 43 (13~74) winsize 62
7525 14:47:13.358385 [CA 1] Center 42 (12~73) winsize 62
7526 14:47:13.361741 [CA 2] Center 38 (9~68) winsize 60
7527 14:47:13.365261 [CA 3] Center 38 (8~68) winsize 61
7528 14:47:13.368500 [CA 4] Center 36 (7~66) winsize 60
7529 14:47:13.372150 [CA 5] Center 35 (6~65) winsize 60
7530 14:47:13.372571
7531 14:47:13.375503 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7532 14:47:13.375926
7533 14:47:13.382013 [CATrainingPosCal] consider 1 rank data
7534 14:47:13.382541 u2DelayCellTimex100 = 262/100 ps
7535 14:47:13.388148 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7536 14:47:13.392078 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7537 14:47:13.394828 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7538 14:47:13.398275 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7539 14:47:13.401915 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7540 14:47:13.405148 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7541 14:47:13.405561
7542 14:47:13.408495 CA PerBit enable=1, Macro0, CA PI delay=35
7543 14:47:13.408907
7544 14:47:13.411764 [CBTSetCACLKResult] CA Dly = 35
7545 14:47:13.414602 CS Dly: 12 (0~43)
7546 14:47:13.417755 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7547 14:47:13.421252 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7548 14:47:13.421680 ==
7549 14:47:13.425017 Dram Type= 6, Freq= 0, CH_0, rank 1
7550 14:47:13.431175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 14:47:13.431631 ==
7552 14:47:13.434378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7553 14:47:13.441055 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7554 14:47:13.444495 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7555 14:47:13.450978 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7556 14:47:13.458870 [CA 0] Center 42 (12~73) winsize 62
7557 14:47:13.462421 [CA 1] Center 43 (13~73) winsize 61
7558 14:47:13.465739 [CA 2] Center 37 (8~67) winsize 60
7559 14:47:13.468709 [CA 3] Center 37 (7~67) winsize 61
7560 14:47:13.472426 [CA 4] Center 35 (6~65) winsize 60
7561 14:47:13.475478 [CA 5] Center 35 (5~65) winsize 61
7562 14:47:13.475918
7563 14:47:13.478582 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7564 14:47:13.479083
7565 14:47:13.481979 [CATrainingPosCal] consider 2 rank data
7566 14:47:13.486233 u2DelayCellTimex100 = 262/100 ps
7567 14:47:13.492155 CA0 delay=43 (13~73),Diff = 8 PI (29 cell)
7568 14:47:13.495212 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7569 14:47:13.498446 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7570 14:47:13.501852 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7571 14:47:13.505347 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7572 14:47:13.508427 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7573 14:47:13.508845
7574 14:47:13.511754 CA PerBit enable=1, Macro0, CA PI delay=35
7575 14:47:13.512188
7576 14:47:13.515275 [CBTSetCACLKResult] CA Dly = 35
7577 14:47:13.518222 CS Dly: 12 (0~43)
7578 14:47:13.521839 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7579 14:47:13.525053 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7580 14:47:13.525567
7581 14:47:13.528229 ----->DramcWriteLeveling(PI) begin...
7582 14:47:13.528660 ==
7583 14:47:13.531578 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 14:47:13.538016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 14:47:13.538601 ==
7586 14:47:13.541691 Write leveling (Byte 0): 36 => 36
7587 14:47:13.544486 Write leveling (Byte 1): 26 => 26
7588 14:47:13.548591 DramcWriteLeveling(PI) end<-----
7589 14:47:13.549122
7590 14:47:13.549461 ==
7591 14:47:13.551648 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 14:47:13.554853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 14:47:13.555278 ==
7594 14:47:13.558087 [Gating] SW mode calibration
7595 14:47:13.564322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7596 14:47:13.567706 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7597 14:47:13.574505 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 14:47:13.577850 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 14:47:13.581157 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 14:47:13.588020 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7601 14:47:13.591032 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7602 14:47:13.594649 1 4 20 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7603 14:47:13.601030 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7604 14:47:13.604619 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 14:47:13.607290 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 14:47:13.614342 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 14:47:13.617327 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 14:47:13.621288 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7609 14:47:13.627679 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7610 14:47:13.630721 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7611 14:47:13.633852 1 5 24 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
7612 14:47:13.640481 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 14:47:13.644026 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 14:47:13.647021 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 14:47:13.653975 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 14:47:13.656546 1 6 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7617 14:47:13.663744 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7618 14:47:13.666798 1 6 20 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7619 14:47:13.669742 1 6 24 | B1->B0 | 3e3d 4646 | 1 0 | (0 0) (0 0)
7620 14:47:13.676419 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 14:47:13.679860 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 14:47:13.683124 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 14:47:13.689805 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 14:47:13.693274 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7625 14:47:13.696938 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7626 14:47:13.703001 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7627 14:47:13.706300 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7628 14:47:13.709498 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 14:47:13.712859 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 14:47:13.719340 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 14:47:13.722639 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 14:47:13.725962 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 14:47:13.732595 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 14:47:13.736335 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 14:47:13.743082 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 14:47:13.746244 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 14:47:13.748978 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 14:47:13.752567 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 14:47:13.759259 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 14:47:13.762405 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7641 14:47:13.765530 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7642 14:47:13.768981 Total UI for P1: 0, mck2ui 16
7643 14:47:13.772153 best dqsien dly found for B0: ( 1, 9, 12)
7644 14:47:13.778654 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7645 14:47:13.782527 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7646 14:47:13.785171 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 14:47:13.788609 Total UI for P1: 0, mck2ui 16
7648 14:47:13.791731 best dqsien dly found for B1: ( 1, 9, 20)
7649 14:47:13.798352 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7650 14:47:13.802450 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7651 14:47:13.803002
7652 14:47:13.804877 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7653 14:47:13.808379 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7654 14:47:13.811692 [Gating] SW calibration Done
7655 14:47:13.812157 ==
7656 14:47:13.815001 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 14:47:13.818413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 14:47:13.818882 ==
7659 14:47:13.821857 RX Vref Scan: 0
7660 14:47:13.822576
7661 14:47:13.822965 RX Vref 0 -> 0, step: 1
7662 14:47:13.823312
7663 14:47:13.824791 RX Delay 0 -> 252, step: 8
7664 14:47:13.828115 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7665 14:47:13.834702 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7666 14:47:13.837939 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7667 14:47:13.841126 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7668 14:47:13.844468 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7669 14:47:13.847952 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7670 14:47:13.854697 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7671 14:47:13.857779 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7672 14:47:13.860929 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7673 14:47:13.864721 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7674 14:47:13.867987 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7675 14:47:13.874647 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7676 14:47:13.877648 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7677 14:47:13.880704 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7678 14:47:13.884207 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7679 14:47:13.890432 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7680 14:47:13.890877 ==
7681 14:47:13.893586 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 14:47:13.897289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 14:47:13.897713 ==
7684 14:47:13.898047 DQS Delay:
7685 14:47:13.900378 DQS0 = 0, DQS1 = 0
7686 14:47:13.900796 DQM Delay:
7687 14:47:13.903926 DQM0 = 136, DQM1 = 126
7688 14:47:13.904358 DQ Delay:
7689 14:47:13.906995 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7690 14:47:13.910525 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7691 14:47:13.913814 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7692 14:47:13.916972 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7693 14:47:13.920290
7694 14:47:13.920755
7695 14:47:13.921115 ==
7696 14:47:13.923711 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 14:47:13.927069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 14:47:13.927626 ==
7699 14:47:13.927997
7700 14:47:13.928343
7701 14:47:13.930440 TX Vref Scan disable
7702 14:47:13.930903 == TX Byte 0 ==
7703 14:47:13.936798 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7704 14:47:13.939786 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7705 14:47:13.940251 == TX Byte 1 ==
7706 14:47:13.946619 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7707 14:47:13.949937 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7708 14:47:13.950491 ==
7709 14:47:13.953141 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 14:47:13.956716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 14:47:13.957349 ==
7712 14:47:13.971198
7713 14:47:13.974345 TX Vref early break, caculate TX vref
7714 14:47:13.977829 TX Vref=16, minBit 4, minWin=22, winSum=370
7715 14:47:13.980852 TX Vref=18, minBit 4, minWin=22, winSum=373
7716 14:47:13.984302 TX Vref=20, minBit 4, minWin=22, winSum=388
7717 14:47:13.987273 TX Vref=22, minBit 1, minWin=24, winSum=400
7718 14:47:13.991114 TX Vref=24, minBit 0, minWin=25, winSum=410
7719 14:47:13.997321 TX Vref=26, minBit 0, minWin=25, winSum=416
7720 14:47:14.000920 TX Vref=28, minBit 1, minWin=25, winSum=414
7721 14:47:14.003971 TX Vref=30, minBit 0, minWin=24, winSum=407
7722 14:47:14.007569 TX Vref=32, minBit 0, minWin=23, winSum=396
7723 14:47:14.010514 TX Vref=34, minBit 4, minWin=23, winSum=387
7724 14:47:14.017345 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
7725 14:47:14.017898
7726 14:47:14.020473 Final TX Range 0 Vref 26
7727 14:47:14.021111
7728 14:47:14.021490 ==
7729 14:47:14.023796 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 14:47:14.027207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 14:47:14.027786 ==
7732 14:47:14.028151
7733 14:47:14.028482
7734 14:47:14.030375 TX Vref Scan disable
7735 14:47:14.037227 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7736 14:47:14.037786 == TX Byte 0 ==
7737 14:47:14.040033 u2DelayCellOfst[0]=14 cells (4 PI)
7738 14:47:14.043616 u2DelayCellOfst[1]=18 cells (5 PI)
7739 14:47:14.046631 u2DelayCellOfst[2]=14 cells (4 PI)
7740 14:47:14.049980 u2DelayCellOfst[3]=18 cells (5 PI)
7741 14:47:14.053758 u2DelayCellOfst[4]=11 cells (3 PI)
7742 14:47:14.057362 u2DelayCellOfst[5]=0 cells (0 PI)
7743 14:47:14.059856 u2DelayCellOfst[6]=18 cells (5 PI)
7744 14:47:14.063300 u2DelayCellOfst[7]=18 cells (5 PI)
7745 14:47:14.066786 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7746 14:47:14.069740 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7747 14:47:14.073007 == TX Byte 1 ==
7748 14:47:14.076419 u2DelayCellOfst[8]=0 cells (0 PI)
7749 14:47:14.079890 u2DelayCellOfst[9]=3 cells (1 PI)
7750 14:47:14.082866 u2DelayCellOfst[10]=7 cells (2 PI)
7751 14:47:14.086358 u2DelayCellOfst[11]=3 cells (1 PI)
7752 14:47:14.086838 u2DelayCellOfst[12]=14 cells (4 PI)
7753 14:47:14.089921 u2DelayCellOfst[13]=14 cells (4 PI)
7754 14:47:14.092991 u2DelayCellOfst[14]=14 cells (4 PI)
7755 14:47:14.096458 u2DelayCellOfst[15]=11 cells (3 PI)
7756 14:47:14.102686 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7757 14:47:14.106094 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7758 14:47:14.106698 DramC Write-DBI on
7759 14:47:14.109745 ==
7760 14:47:14.113051 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 14:47:14.116066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 14:47:14.116618 ==
7763 14:47:14.116981
7764 14:47:14.117312
7765 14:47:14.119240 TX Vref Scan disable
7766 14:47:14.119695 == TX Byte 0 ==
7767 14:47:14.125977 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7768 14:47:14.126595 == TX Byte 1 ==
7769 14:47:14.129199 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7770 14:47:14.132266 DramC Write-DBI off
7771 14:47:14.132785
7772 14:47:14.133145 [DATLAT]
7773 14:47:14.136244 Freq=1600, CH0 RK0
7774 14:47:14.136895
7775 14:47:14.137422 DATLAT Default: 0xf
7776 14:47:14.139036 0, 0xFFFF, sum = 0
7777 14:47:14.139589 1, 0xFFFF, sum = 0
7778 14:47:14.142301 2, 0xFFFF, sum = 0
7779 14:47:14.142694 3, 0xFFFF, sum = 0
7780 14:47:14.145407 4, 0xFFFF, sum = 0
7781 14:47:14.149352 5, 0xFFFF, sum = 0
7782 14:47:14.149949 6, 0xFFFF, sum = 0
7783 14:47:14.152566 7, 0xFFFF, sum = 0
7784 14:47:14.153029 8, 0xFFFF, sum = 0
7785 14:47:14.155270 9, 0xFFFF, sum = 0
7786 14:47:14.155733 10, 0xFFFF, sum = 0
7787 14:47:14.159199 11, 0xFFFF, sum = 0
7788 14:47:14.159676 12, 0xFFFF, sum = 0
7789 14:47:14.161964 13, 0xFFFF, sum = 0
7790 14:47:14.162489 14, 0x0, sum = 1
7791 14:47:14.166007 15, 0x0, sum = 2
7792 14:47:14.166624 16, 0x0, sum = 3
7793 14:47:14.168581 17, 0x0, sum = 4
7794 14:47:14.169072 best_step = 15
7795 14:47:14.169438
7796 14:47:14.169883 ==
7797 14:47:14.171651 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 14:47:14.178270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 14:47:14.178739 ==
7800 14:47:14.179112 RX Vref Scan: 1
7801 14:47:14.179505
7802 14:47:14.181662 Set Vref Range= 24 -> 127
7803 14:47:14.182080
7804 14:47:14.185164 RX Vref 24 -> 127, step: 1
7805 14:47:14.185714
7806 14:47:14.186191 RX Delay 19 -> 252, step: 4
7807 14:47:14.186583
7808 14:47:14.188664 Set Vref, RX VrefLevel [Byte0]: 24
7809 14:47:14.191634 [Byte1]: 24
7810 14:47:14.195473
7811 14:47:14.195937 Set Vref, RX VrefLevel [Byte0]: 25
7812 14:47:14.198764 [Byte1]: 25
7813 14:47:14.203207
7814 14:47:14.203765 Set Vref, RX VrefLevel [Byte0]: 26
7815 14:47:14.206853 [Byte1]: 26
7816 14:47:14.211354
7817 14:47:14.211909 Set Vref, RX VrefLevel [Byte0]: 27
7818 14:47:14.213954 [Byte1]: 27
7819 14:47:14.218876
7820 14:47:14.219430 Set Vref, RX VrefLevel [Byte0]: 28
7821 14:47:14.221979 [Byte1]: 28
7822 14:47:14.226116
7823 14:47:14.226753 Set Vref, RX VrefLevel [Byte0]: 29
7824 14:47:14.229460 [Byte1]: 29
7825 14:47:14.233739
7826 14:47:14.234235 Set Vref, RX VrefLevel [Byte0]: 30
7827 14:47:14.236927 [Byte1]: 30
7828 14:47:14.241095
7829 14:47:14.241667 Set Vref, RX VrefLevel [Byte0]: 31
7830 14:47:14.244955 [Byte1]: 31
7831 14:47:14.248978
7832 14:47:14.249539 Set Vref, RX VrefLevel [Byte0]: 32
7833 14:47:14.252447 [Byte1]: 32
7834 14:47:14.256716
7835 14:47:14.257273 Set Vref, RX VrefLevel [Byte0]: 33
7836 14:47:14.259571 [Byte1]: 33
7837 14:47:14.264363
7838 14:47:14.264919 Set Vref, RX VrefLevel [Byte0]: 34
7839 14:47:14.267292 [Byte1]: 34
7840 14:47:14.271603
7841 14:47:14.272078 Set Vref, RX VrefLevel [Byte0]: 35
7842 14:47:14.275056 [Byte1]: 35
7843 14:47:14.278720
7844 14:47:14.279176 Set Vref, RX VrefLevel [Byte0]: 36
7845 14:47:14.282591 [Byte1]: 36
7846 14:47:14.286920
7847 14:47:14.287473 Set Vref, RX VrefLevel [Byte0]: 37
7848 14:47:14.290037 [Byte1]: 37
7849 14:47:14.294410
7850 14:47:14.294961 Set Vref, RX VrefLevel [Byte0]: 38
7851 14:47:14.297788 [Byte1]: 38
7852 14:47:14.301898
7853 14:47:14.302505 Set Vref, RX VrefLevel [Byte0]: 39
7854 14:47:14.305057 [Byte1]: 39
7855 14:47:14.309780
7856 14:47:14.310395 Set Vref, RX VrefLevel [Byte0]: 40
7857 14:47:14.312862 [Byte1]: 40
7858 14:47:14.317168
7859 14:47:14.317732 Set Vref, RX VrefLevel [Byte0]: 41
7860 14:47:14.320578 [Byte1]: 41
7861 14:47:14.324392
7862 14:47:14.324903 Set Vref, RX VrefLevel [Byte0]: 42
7863 14:47:14.327875 [Byte1]: 42
7864 14:47:14.332297
7865 14:47:14.332795 Set Vref, RX VrefLevel [Byte0]: 43
7866 14:47:14.335257 [Byte1]: 43
7867 14:47:14.339466
7868 14:47:14.339920 Set Vref, RX VrefLevel [Byte0]: 44
7869 14:47:14.342924 [Byte1]: 44
7870 14:47:14.347153
7871 14:47:14.347623 Set Vref, RX VrefLevel [Byte0]: 45
7872 14:47:14.350327 [Byte1]: 45
7873 14:47:14.354706
7874 14:47:14.355275 Set Vref, RX VrefLevel [Byte0]: 46
7875 14:47:14.358035 [Byte1]: 46
7876 14:47:14.362342
7877 14:47:14.362885 Set Vref, RX VrefLevel [Byte0]: 47
7878 14:47:14.365730 [Byte1]: 47
7879 14:47:14.370286
7880 14:47:14.370842 Set Vref, RX VrefLevel [Byte0]: 48
7881 14:47:14.373578 [Byte1]: 48
7882 14:47:14.378278
7883 14:47:14.378860 Set Vref, RX VrefLevel [Byte0]: 49
7884 14:47:14.381021 [Byte1]: 49
7885 14:47:14.384842
7886 14:47:14.385299 Set Vref, RX VrefLevel [Byte0]: 50
7887 14:47:14.388169 [Byte1]: 50
7888 14:47:14.392612
7889 14:47:14.393161 Set Vref, RX VrefLevel [Byte0]: 51
7890 14:47:14.395869 [Byte1]: 51
7891 14:47:14.400491
7892 14:47:14.401056 Set Vref, RX VrefLevel [Byte0]: 52
7893 14:47:14.403621 [Byte1]: 52
7894 14:47:14.407654
7895 14:47:14.408199 Set Vref, RX VrefLevel [Byte0]: 53
7896 14:47:14.411567 [Byte1]: 53
7897 14:47:14.415613
7898 14:47:14.416164 Set Vref, RX VrefLevel [Byte0]: 54
7899 14:47:14.418967 [Byte1]: 54
7900 14:47:14.423060
7901 14:47:14.423643 Set Vref, RX VrefLevel [Byte0]: 55
7902 14:47:14.426157 [Byte1]: 55
7903 14:47:14.430672
7904 14:47:14.431220 Set Vref, RX VrefLevel [Byte0]: 56
7905 14:47:14.433650 [Byte1]: 56
7906 14:47:14.437933
7907 14:47:14.438439 Set Vref, RX VrefLevel [Byte0]: 57
7908 14:47:14.441166 [Byte1]: 57
7909 14:47:14.445497
7910 14:47:14.445982 Set Vref, RX VrefLevel [Byte0]: 58
7911 14:47:14.448829 [Byte1]: 58
7912 14:47:14.453153
7913 14:47:14.453718 Set Vref, RX VrefLevel [Byte0]: 59
7914 14:47:14.456657 [Byte1]: 59
7915 14:47:14.460741
7916 14:47:14.461207 Set Vref, RX VrefLevel [Byte0]: 60
7917 14:47:14.464439 [Byte1]: 60
7918 14:47:14.468222
7919 14:47:14.468676 Set Vref, RX VrefLevel [Byte0]: 61
7920 14:47:14.471510 [Byte1]: 61
7921 14:47:14.475556
7922 14:47:14.476015 Set Vref, RX VrefLevel [Byte0]: 62
7923 14:47:14.479153 [Byte1]: 62
7924 14:47:14.483297
7925 14:47:14.483750 Set Vref, RX VrefLevel [Byte0]: 63
7926 14:47:14.486735 [Byte1]: 63
7927 14:47:14.490956
7928 14:47:14.491369 Set Vref, RX VrefLevel [Byte0]: 64
7929 14:47:14.494773 [Byte1]: 64
7930 14:47:14.498903
7931 14:47:14.499402 Set Vref, RX VrefLevel [Byte0]: 65
7932 14:47:14.501964 [Byte1]: 65
7933 14:47:14.506733
7934 14:47:14.507284 Set Vref, RX VrefLevel [Byte0]: 66
7935 14:47:14.509655 [Byte1]: 66
7936 14:47:14.513887
7937 14:47:14.514459 Set Vref, RX VrefLevel [Byte0]: 67
7938 14:47:14.517218 [Byte1]: 67
7939 14:47:14.521384
7940 14:47:14.521797 Set Vref, RX VrefLevel [Byte0]: 68
7941 14:47:14.524776 [Byte1]: 68
7942 14:47:14.529293
7943 14:47:14.530113 Set Vref, RX VrefLevel [Byte0]: 69
7944 14:47:14.532058 [Byte1]: 69
7945 14:47:14.536591
7946 14:47:14.537162 Set Vref, RX VrefLevel [Byte0]: 70
7947 14:47:14.539608 [Byte1]: 70
7948 14:47:14.544246
7949 14:47:14.544657 Set Vref, RX VrefLevel [Byte0]: 71
7950 14:47:14.547153 [Byte1]: 71
7951 14:47:14.551885
7952 14:47:14.552297 Set Vref, RX VrefLevel [Byte0]: 72
7953 14:47:14.554846 [Byte1]: 72
7954 14:47:14.559384
7955 14:47:14.559904 Set Vref, RX VrefLevel [Byte0]: 73
7956 14:47:14.562890 [Byte1]: 73
7957 14:47:14.566997
7958 14:47:14.567520 Set Vref, RX VrefLevel [Byte0]: 74
7959 14:47:14.570129 [Byte1]: 74
7960 14:47:14.574002
7961 14:47:14.574548 Set Vref, RX VrefLevel [Byte0]: 75
7962 14:47:14.577555 [Byte1]: 75
7963 14:47:14.581719
7964 14:47:14.582400 Set Vref, RX VrefLevel [Byte0]: 76
7965 14:47:14.584842 [Byte1]: 76
7966 14:47:14.589352
7967 14:47:14.589884 Set Vref, RX VrefLevel [Byte0]: 77
7968 14:47:14.592813 [Byte1]: 77
7969 14:47:14.596934
7970 14:47:14.597527 Set Vref, RX VrefLevel [Byte0]: 78
7971 14:47:14.600496 [Byte1]: 78
7972 14:47:14.604844
7973 14:47:14.605354 Set Vref, RX VrefLevel [Byte0]: 79
7974 14:47:14.608298 [Byte1]: 79
7975 14:47:14.612284
7976 14:47:14.612693 Set Vref, RX VrefLevel [Byte0]: 80
7977 14:47:14.615365 [Byte1]: 80
7978 14:47:14.619923
7979 14:47:14.620359 Final RX Vref Byte 0 = 66 to rank0
7980 14:47:14.622831 Final RX Vref Byte 1 = 59 to rank0
7981 14:47:14.626152 Final RX Vref Byte 0 = 66 to rank1
7982 14:47:14.629534 Final RX Vref Byte 1 = 59 to rank1==
7983 14:47:14.632864 Dram Type= 6, Freq= 0, CH_0, rank 0
7984 14:47:14.639322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 14:47:14.639771 ==
7986 14:47:14.640215 DQS Delay:
7987 14:47:14.642602 DQS0 = 0, DQS1 = 0
7988 14:47:14.643040 DQM Delay:
7989 14:47:14.643484 DQM0 = 133, DQM1 = 122
7990 14:47:14.646136 DQ Delay:
7991 14:47:14.649420 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
7992 14:47:14.652479 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
7993 14:47:14.656084 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
7994 14:47:14.659423 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =128
7995 14:47:14.659863
7996 14:47:14.660305
7997 14:47:14.660723
7998 14:47:14.662209 [DramC_TX_OE_Calibration] TA2
7999 14:47:14.666019 Original DQ_B0 (3 6) =30, OEN = 27
8000 14:47:14.668886 Original DQ_B1 (3 6) =30, OEN = 27
8001 14:47:14.672453 24, 0x0, End_B0=24 End_B1=24
8002 14:47:14.675587 25, 0x0, End_B0=25 End_B1=25
8003 14:47:14.676029 26, 0x0, End_B0=26 End_B1=26
8004 14:47:14.679089 27, 0x0, End_B0=27 End_B1=27
8005 14:47:14.682706 28, 0x0, End_B0=28 End_B1=28
8006 14:47:14.685712 29, 0x0, End_B0=29 End_B1=29
8007 14:47:14.686152 30, 0x0, End_B0=30 End_B1=30
8008 14:47:14.688711 31, 0x4545, End_B0=30 End_B1=30
8009 14:47:14.692117 Byte0 end_step=30 best_step=27
8010 14:47:14.695370 Byte1 end_step=30 best_step=27
8011 14:47:14.698477 Byte0 TX OE(2T, 0.5T) = (3, 3)
8012 14:47:14.701766 Byte1 TX OE(2T, 0.5T) = (3, 3)
8013 14:47:14.702234
8014 14:47:14.702675
8015 14:47:14.708676 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8016 14:47:14.711771 CH0 RK0: MR19=303, MR18=2112
8017 14:47:14.718382 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8018 14:47:14.718897
8019 14:47:14.721380 ----->DramcWriteLeveling(PI) begin...
8020 14:47:14.721824 ==
8021 14:47:14.724668 Dram Type= 6, Freq= 0, CH_0, rank 1
8022 14:47:14.728244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 14:47:14.731833 ==
8024 14:47:14.732385 Write leveling (Byte 0): 33 => 33
8025 14:47:14.734924 Write leveling (Byte 1): 27 => 27
8026 14:47:14.737976 DramcWriteLeveling(PI) end<-----
8027 14:47:14.738435
8028 14:47:14.738768 ==
8029 14:47:14.741491 Dram Type= 6, Freq= 0, CH_0, rank 1
8030 14:47:14.747536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 14:47:14.747963 ==
8032 14:47:14.751015 [Gating] SW mode calibration
8033 14:47:14.757908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8034 14:47:14.760964 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8035 14:47:14.767225 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 14:47:14.771081 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 14:47:14.773757 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 14:47:14.780773 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 14:47:14.784403 1 4 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8040 14:47:14.787394 1 4 20 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
8041 14:47:14.793795 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8042 14:47:14.797660 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 14:47:14.800699 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 14:47:14.806750 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 14:47:14.810408 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8046 14:47:14.813659 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8047 14:47:14.819847 1 5 16 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
8048 14:47:14.823261 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8049 14:47:14.826289 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 14:47:14.833029 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 14:47:14.836271 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 14:47:14.840660 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 14:47:14.846343 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 14:47:14.849730 1 6 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8055 14:47:14.853032 1 6 16 | B1->B0 | 302f 4646 | 1 0 | (0 0) (0 0)
8056 14:47:14.859575 1 6 20 | B1->B0 | 403f 4646 | 1 0 | (0 0) (0 0)
8057 14:47:14.863170 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 14:47:14.866140 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 14:47:14.872836 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 14:47:14.875604 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 14:47:14.879187 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8062 14:47:14.885624 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8063 14:47:14.889018 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8064 14:47:14.892486 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8065 14:47:14.899445 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 14:47:14.902097 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 14:47:14.905697 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 14:47:14.911977 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 14:47:14.915191 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 14:47:14.918634 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 14:47:14.925409 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 14:47:14.928529 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 14:47:14.931917 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 14:47:14.938499 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 14:47:14.941648 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 14:47:14.945358 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 14:47:14.951561 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8078 14:47:14.954786 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8079 14:47:14.958421 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8080 14:47:14.964999 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 14:47:14.968053 Total UI for P1: 0, mck2ui 16
8082 14:47:14.971444 best dqsien dly found for B0: ( 1, 9, 12)
8083 14:47:14.974721 Total UI for P1: 0, mck2ui 16
8084 14:47:14.978030 best dqsien dly found for B1: ( 1, 9, 18)
8085 14:47:14.980968 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8086 14:47:14.984704 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8087 14:47:14.985126
8088 14:47:14.987920 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8089 14:47:14.991005 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8090 14:47:14.994197 [Gating] SW calibration Done
8091 14:47:14.994640 ==
8092 14:47:14.998313 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 14:47:15.001970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 14:47:15.002540 ==
8095 14:47:15.004065 RX Vref Scan: 0
8096 14:47:15.004487
8097 14:47:15.007015 RX Vref 0 -> 0, step: 1
8098 14:47:15.007435
8099 14:47:15.007768 RX Delay 0 -> 252, step: 8
8100 14:47:15.013941 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8101 14:47:15.017358 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8102 14:47:15.020658 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8103 14:47:15.024264 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8104 14:47:15.027442 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8105 14:47:15.034221 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8106 14:47:15.037156 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8107 14:47:15.040522 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8108 14:47:15.043806 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8109 14:47:15.046852 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8110 14:47:15.053916 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8111 14:47:15.056821 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8112 14:47:15.060336 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8113 14:47:15.063324 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8114 14:47:15.070247 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8115 14:47:15.073191 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8116 14:47:15.073655 ==
8117 14:47:15.076640 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 14:47:15.080412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 14:47:15.080879 ==
8120 14:47:15.082923 DQS Delay:
8121 14:47:15.083421 DQS0 = 0, DQS1 = 0
8122 14:47:15.083793 DQM Delay:
8123 14:47:15.086466 DQM0 = 132, DQM1 = 128
8124 14:47:15.086928 DQ Delay:
8125 14:47:15.089612 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8126 14:47:15.094126 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
8127 14:47:15.099520 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8128 14:47:15.103418 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8129 14:47:15.103956
8130 14:47:15.104300
8131 14:47:15.104615 ==
8132 14:47:15.106216 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 14:47:15.110768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 14:47:15.111292 ==
8135 14:47:15.111632
8136 14:47:15.111943
8137 14:47:15.112603 TX Vref Scan disable
8138 14:47:15.116159 == TX Byte 0 ==
8139 14:47:15.119455 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8140 14:47:15.122688 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8141 14:47:15.126019 == TX Byte 1 ==
8142 14:47:15.129764 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8143 14:47:15.132589 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8144 14:47:15.133158 ==
8145 14:47:15.136087 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 14:47:15.142517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 14:47:15.143041 ==
8148 14:47:15.153525
8149 14:47:15.156709 TX Vref early break, caculate TX vref
8150 14:47:15.159700 TX Vref=16, minBit 5, minWin=22, winSum=375
8151 14:47:15.163062 TX Vref=18, minBit 1, minWin=23, winSum=386
8152 14:47:15.167170 TX Vref=20, minBit 6, minWin=23, winSum=394
8153 14:47:15.170288 TX Vref=22, minBit 1, minWin=24, winSum=400
8154 14:47:15.173065 TX Vref=24, minBit 1, minWin=24, winSum=409
8155 14:47:15.179486 TX Vref=26, minBit 1, minWin=24, winSum=409
8156 14:47:15.182816 TX Vref=28, minBit 0, minWin=25, winSum=413
8157 14:47:15.185985 TX Vref=30, minBit 1, minWin=24, winSum=402
8158 14:47:15.190027 TX Vref=32, minBit 2, minWin=23, winSum=391
8159 14:47:15.195915 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8160 14:47:15.196383
8161 14:47:15.199563 Final TX Range 0 Vref 28
8162 14:47:15.200205
8163 14:47:15.200575 ==
8164 14:47:15.202907 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 14:47:15.205690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 14:47:15.206158 ==
8167 14:47:15.206572
8168 14:47:15.206914
8169 14:47:15.209448 TX Vref Scan disable
8170 14:47:15.215918 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8171 14:47:15.216389 == TX Byte 0 ==
8172 14:47:15.219081 u2DelayCellOfst[0]=11 cells (3 PI)
8173 14:47:15.222777 u2DelayCellOfst[1]=18 cells (5 PI)
8174 14:47:15.226029 u2DelayCellOfst[2]=11 cells (3 PI)
8175 14:47:15.229533 u2DelayCellOfst[3]=14 cells (4 PI)
8176 14:47:15.233038 u2DelayCellOfst[4]=7 cells (2 PI)
8177 14:47:15.235913 u2DelayCellOfst[5]=0 cells (0 PI)
8178 14:47:15.239148 u2DelayCellOfst[6]=18 cells (5 PI)
8179 14:47:15.239577 u2DelayCellOfst[7]=18 cells (5 PI)
8180 14:47:15.245888 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8181 14:47:15.248824 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8182 14:47:15.251984 == TX Byte 1 ==
8183 14:47:15.252404 u2DelayCellOfst[8]=0 cells (0 PI)
8184 14:47:15.255651 u2DelayCellOfst[9]=3 cells (1 PI)
8185 14:47:15.258730 u2DelayCellOfst[10]=7 cells (2 PI)
8186 14:47:15.262137 u2DelayCellOfst[11]=3 cells (1 PI)
8187 14:47:15.265821 u2DelayCellOfst[12]=11 cells (3 PI)
8188 14:47:15.268502 u2DelayCellOfst[13]=11 cells (3 PI)
8189 14:47:15.271622 u2DelayCellOfst[14]=14 cells (4 PI)
8190 14:47:15.275284 u2DelayCellOfst[15]=11 cells (3 PI)
8191 14:47:15.278079 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8192 14:47:15.285258 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8193 14:47:15.285816 DramC Write-DBI on
8194 14:47:15.286243 ==
8195 14:47:15.288553 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 14:47:15.294885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 14:47:15.295353 ==
8198 14:47:15.295722
8199 14:47:15.296061
8200 14:47:15.296385 TX Vref Scan disable
8201 14:47:15.298700 == TX Byte 0 ==
8202 14:47:15.302085 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8203 14:47:15.305867 == TX Byte 1 ==
8204 14:47:15.309112 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8205 14:47:15.312193 DramC Write-DBI off
8206 14:47:15.312809
8207 14:47:15.313184 [DATLAT]
8208 14:47:15.313529 Freq=1600, CH0 RK1
8209 14:47:15.313861
8210 14:47:15.315162 DATLAT Default: 0xf
8211 14:47:15.318520 0, 0xFFFF, sum = 0
8212 14:47:15.319154 1, 0xFFFF, sum = 0
8213 14:47:15.321519 2, 0xFFFF, sum = 0
8214 14:47:15.321990 3, 0xFFFF, sum = 0
8215 14:47:15.325311 4, 0xFFFF, sum = 0
8216 14:47:15.325891 5, 0xFFFF, sum = 0
8217 14:47:15.328649 6, 0xFFFF, sum = 0
8218 14:47:15.329212 7, 0xFFFF, sum = 0
8219 14:47:15.331782 8, 0xFFFF, sum = 0
8220 14:47:15.332255 9, 0xFFFF, sum = 0
8221 14:47:15.334689 10, 0xFFFF, sum = 0
8222 14:47:15.335163 11, 0xFFFF, sum = 0
8223 14:47:15.338314 12, 0xFFFF, sum = 0
8224 14:47:15.338883 13, 0xFFFF, sum = 0
8225 14:47:15.341409 14, 0x0, sum = 1
8226 14:47:15.341986 15, 0x0, sum = 2
8227 14:47:15.344571 16, 0x0, sum = 3
8228 14:47:15.345055 17, 0x0, sum = 4
8229 14:47:15.348087 best_step = 15
8230 14:47:15.348566
8231 14:47:15.349043 ==
8232 14:47:15.351248 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 14:47:15.354808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 14:47:15.355384 ==
8235 14:47:15.358031 RX Vref Scan: 0
8236 14:47:15.358636
8237 14:47:15.359130 RX Vref 0 -> 0, step: 1
8238 14:47:15.359592
8239 14:47:15.361574 RX Delay 11 -> 252, step: 4
8240 14:47:15.367621 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8241 14:47:15.370815 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8242 14:47:15.374795 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8243 14:47:15.377811 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8244 14:47:15.381371 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8245 14:47:15.387541 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8246 14:47:15.390876 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8247 14:47:15.394044 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8248 14:47:15.398014 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8249 14:47:15.401199 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8250 14:47:15.407543 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8251 14:47:15.411036 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8252 14:47:15.414092 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8253 14:47:15.417352 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8254 14:47:15.423848 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8255 14:47:15.427517 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8256 14:47:15.428069 ==
8257 14:47:15.430660 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 14:47:15.433773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 14:47:15.434397 ==
8260 14:47:15.437130 DQS Delay:
8261 14:47:15.437684 DQS0 = 0, DQS1 = 0
8262 14:47:15.438055 DQM Delay:
8263 14:47:15.440256 DQM0 = 129, DQM1 = 125
8264 14:47:15.440721 DQ Delay:
8265 14:47:15.443781 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8266 14:47:15.447103 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =140
8267 14:47:15.453285 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8268 14:47:15.456668 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =134
8269 14:47:15.457222
8270 14:47:15.457586
8271 14:47:15.457921
8272 14:47:15.459714 [DramC_TX_OE_Calibration] TA2
8273 14:47:15.463456 Original DQ_B0 (3 6) =30, OEN = 27
8274 14:47:15.466677 Original DQ_B1 (3 6) =30, OEN = 27
8275 14:47:15.467144 24, 0x0, End_B0=24 End_B1=24
8276 14:47:15.470399 25, 0x0, End_B0=25 End_B1=25
8277 14:47:15.473016 26, 0x0, End_B0=26 End_B1=26
8278 14:47:15.476470 27, 0x0, End_B0=27 End_B1=27
8279 14:47:15.476956 28, 0x0, End_B0=28 End_B1=28
8280 14:47:15.479684 29, 0x0, End_B0=29 End_B1=29
8281 14:47:15.483389 30, 0x0, End_B0=30 End_B1=30
8282 14:47:15.486426 31, 0x4141, End_B0=30 End_B1=30
8283 14:47:15.489821 Byte0 end_step=30 best_step=27
8284 14:47:15.493177 Byte1 end_step=30 best_step=27
8285 14:47:15.493756 Byte0 TX OE(2T, 0.5T) = (3, 3)
8286 14:47:15.496657 Byte1 TX OE(2T, 0.5T) = (3, 3)
8287 14:47:15.497169
8288 14:47:15.497501
8289 14:47:15.506420 [DQSOSCAuto] RK1, (LSB)MR18= 0x2003, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8290 14:47:15.509665 CH0 RK1: MR19=303, MR18=2003
8291 14:47:15.513006 CH0_RK1: MR19=0x303, MR18=0x2003, DQSOSC=393, MR23=63, INC=23, DEC=15
8292 14:47:15.516429 [RxdqsGatingPostProcess] freq 1600
8293 14:47:15.522660 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8294 14:47:15.525881 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 14:47:15.528952 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 14:47:15.532415 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 14:47:15.535374 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 14:47:15.538590 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 14:47:15.542310 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 14:47:15.545350 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 14:47:15.548512 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 14:47:15.552150 Pre-setting of DQS Precalculation
8303 14:47:15.555021 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8304 14:47:15.555440 ==
8305 14:47:15.558431 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 14:47:15.561741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 14:47:15.562242 ==
8308 14:47:15.568455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8309 14:47:15.572357 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8310 14:47:15.578559 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8311 14:47:15.581531 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8312 14:47:15.592095 [CA 0] Center 42 (13~72) winsize 60
8313 14:47:15.595236 [CA 1] Center 42 (13~72) winsize 60
8314 14:47:15.598529 [CA 2] Center 38 (9~67) winsize 59
8315 14:47:15.601766 [CA 3] Center 37 (8~66) winsize 59
8316 14:47:15.605240 [CA 4] Center 38 (9~67) winsize 59
8317 14:47:15.608243 [CA 5] Center 37 (8~67) winsize 60
8318 14:47:15.608667
8319 14:47:15.611848 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8320 14:47:15.612373
8321 14:47:15.614918 [CATrainingPosCal] consider 1 rank data
8322 14:47:15.618724 u2DelayCellTimex100 = 262/100 ps
8323 14:47:15.625308 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8324 14:47:15.628455 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8325 14:47:15.631661 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8326 14:47:15.634907 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8327 14:47:15.638545 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8328 14:47:15.641286 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8329 14:47:15.641846
8330 14:47:15.644783 CA PerBit enable=1, Macro0, CA PI delay=37
8331 14:47:15.645332
8332 14:47:15.647860 [CBTSetCACLKResult] CA Dly = 37
8333 14:47:15.651053 CS Dly: 9 (0~40)
8334 14:47:15.654897 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8335 14:47:15.658563 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8336 14:47:15.659128 ==
8337 14:47:15.661030 Dram Type= 6, Freq= 0, CH_1, rank 1
8338 14:47:15.668089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 14:47:15.668646 ==
8340 14:47:15.670709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8341 14:47:15.677624 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8342 14:47:15.680935 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8343 14:47:15.687242 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8344 14:47:15.695280 [CA 0] Center 42 (13~72) winsize 60
8345 14:47:15.698466 [CA 1] Center 42 (12~73) winsize 62
8346 14:47:15.701787 [CA 2] Center 37 (8~67) winsize 60
8347 14:47:15.704777 [CA 3] Center 37 (8~67) winsize 60
8348 14:47:15.708074 [CA 4] Center 37 (8~67) winsize 60
8349 14:47:15.711275 [CA 5] Center 37 (8~67) winsize 60
8350 14:47:15.711688
8351 14:47:15.715040 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8352 14:47:15.715456
8353 14:47:15.721267 [CATrainingPosCal] consider 2 rank data
8354 14:47:15.721811 u2DelayCellTimex100 = 262/100 ps
8355 14:47:15.728049 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8356 14:47:15.731326 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8357 14:47:15.734432 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8358 14:47:15.737570 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8359 14:47:15.741149 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8360 14:47:15.744349 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8361 14:47:15.744764
8362 14:47:15.747906 CA PerBit enable=1, Macro0, CA PI delay=37
8363 14:47:15.748322
8364 14:47:15.751222 [CBTSetCACLKResult] CA Dly = 37
8365 14:47:15.754582 CS Dly: 10 (0~43)
8366 14:47:15.757784 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8367 14:47:15.761014 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8368 14:47:15.761429
8369 14:47:15.764243 ----->DramcWriteLeveling(PI) begin...
8370 14:47:15.764661 ==
8371 14:47:15.767569 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 14:47:15.774782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 14:47:15.775338 ==
8374 14:47:15.777489 Write leveling (Byte 0): 22 => 22
8375 14:47:15.780510 Write leveling (Byte 1): 26 => 26
8376 14:47:15.780922 DramcWriteLeveling(PI) end<-----
8377 14:47:15.783865
8378 14:47:15.784398 ==
8379 14:47:15.787207 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 14:47:15.790757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 14:47:15.791173 ==
8382 14:47:15.793543 [Gating] SW mode calibration
8383 14:47:15.800444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8384 14:47:15.806860 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8385 14:47:15.810497 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 14:47:15.813447 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 14:47:15.819850 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 14:47:15.823101 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8389 14:47:15.826505 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 14:47:15.833552 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 14:47:15.836728 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 14:47:15.839540 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 14:47:15.846785 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 14:47:15.849722 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 14:47:15.853110 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8396 14:47:15.859320 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (1 0)
8397 14:47:15.862770 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8398 14:47:15.865973 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 14:47:15.872517 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 14:47:15.875792 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 14:47:15.879082 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 14:47:15.885646 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 14:47:15.889335 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8404 14:47:15.892458 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8405 14:47:15.898780 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 14:47:15.902112 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 14:47:15.905570 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 14:47:15.912268 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 14:47:15.915465 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 14:47:15.918963 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 14:47:15.925443 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8412 14:47:15.929204 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8413 14:47:15.932943 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8414 14:47:15.938830 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 14:47:15.942095 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 14:47:15.945306 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 14:47:15.951799 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 14:47:15.954856 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 14:47:15.958479 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 14:47:15.964705 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 14:47:15.968426 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 14:47:15.971312 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 14:47:15.977912 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 14:47:15.981350 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 14:47:15.984600 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 14:47:15.991035 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 14:47:15.994942 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8428 14:47:15.997500 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8429 14:47:16.004485 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8430 14:47:16.005056 Total UI for P1: 0, mck2ui 16
8431 14:47:16.010915 best dqsien dly found for B0: ( 1, 9, 10)
8432 14:47:16.014670 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 14:47:16.018221 Total UI for P1: 0, mck2ui 16
8434 14:47:16.021025 best dqsien dly found for B1: ( 1, 9, 12)
8435 14:47:16.023898 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8436 14:47:16.027499 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8437 14:47:16.028070
8438 14:47:16.031238 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8439 14:47:16.033733 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8440 14:47:16.037329 [Gating] SW calibration Done
8441 14:47:16.037792 ==
8442 14:47:16.040438 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 14:47:16.047311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 14:47:16.047923 ==
8445 14:47:16.048311 RX Vref Scan: 0
8446 14:47:16.048654
8447 14:47:16.050249 RX Vref 0 -> 0, step: 1
8448 14:47:16.050718
8449 14:47:16.054012 RX Delay 0 -> 252, step: 8
8450 14:47:16.057465 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8451 14:47:16.060283 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8452 14:47:16.063403 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8453 14:47:16.070202 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8454 14:47:16.073255 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8455 14:47:16.076711 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8456 14:47:16.080157 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8457 14:47:16.083064 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8458 14:47:16.089658 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8459 14:47:16.093165 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8460 14:47:16.096460 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8461 14:47:16.099716 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8462 14:47:16.102683 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8463 14:47:16.109689 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8464 14:47:16.112889 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8465 14:47:16.116292 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8466 14:47:16.116858 ==
8467 14:47:16.119235 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 14:47:16.122834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 14:47:16.126070 ==
8470 14:47:16.126572 DQS Delay:
8471 14:47:16.126941 DQS0 = 0, DQS1 = 0
8472 14:47:16.129461 DQM Delay:
8473 14:47:16.130021 DQM0 = 138, DQM1 = 130
8474 14:47:16.132879 DQ Delay:
8475 14:47:16.135718 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8476 14:47:16.138801 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8477 14:47:16.142508 DQ8 =119, DQ9 =115, DQ10 =135, DQ11 =123
8478 14:47:16.146050 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8479 14:47:16.146660
8480 14:47:16.147053
8481 14:47:16.147396 ==
8482 14:47:16.148772 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 14:47:16.152271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 14:47:16.155397 ==
8485 14:47:16.155862
8486 14:47:16.156227
8487 14:47:16.156568 TX Vref Scan disable
8488 14:47:16.159226 == TX Byte 0 ==
8489 14:47:16.162144 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8490 14:47:16.165246 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8491 14:47:16.169075 == TX Byte 1 ==
8492 14:47:16.171732 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8493 14:47:16.175128 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8494 14:47:16.178505 ==
8495 14:47:16.181811 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 14:47:16.184861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 14:47:16.185321 ==
8498 14:47:16.197240
8499 14:47:16.200398 TX Vref early break, caculate TX vref
8500 14:47:16.203794 TX Vref=16, minBit 5, minWin=21, winSum=370
8501 14:47:16.207401 TX Vref=18, minBit 6, minWin=22, winSum=380
8502 14:47:16.210677 TX Vref=20, minBit 0, minWin=23, winSum=392
8503 14:47:16.214023 TX Vref=22, minBit 0, minWin=23, winSum=397
8504 14:47:16.217290 TX Vref=24, minBit 5, minWin=24, winSum=411
8505 14:47:16.223555 TX Vref=26, minBit 0, minWin=25, winSum=417
8506 14:47:16.227342 TX Vref=28, minBit 0, minWin=25, winSum=420
8507 14:47:16.230297 TX Vref=30, minBit 0, minWin=23, winSum=412
8508 14:47:16.233931 TX Vref=32, minBit 0, minWin=24, winSum=399
8509 14:47:16.236601 TX Vref=34, minBit 5, minWin=22, winSum=395
8510 14:47:16.243439 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8511 14:47:16.243998
8512 14:47:16.246771 Final TX Range 0 Vref 28
8513 14:47:16.247248
8514 14:47:16.247608 ==
8515 14:47:16.249917 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 14:47:16.253233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 14:47:16.253711 ==
8518 14:47:16.254075
8519 14:47:16.254541
8520 14:47:16.256468 TX Vref Scan disable
8521 14:47:16.262823 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8522 14:47:16.263320 == TX Byte 0 ==
8523 14:47:16.266281 u2DelayCellOfst[0]=18 cells (5 PI)
8524 14:47:16.270153 u2DelayCellOfst[1]=14 cells (4 PI)
8525 14:47:16.273188 u2DelayCellOfst[2]=0 cells (0 PI)
8526 14:47:16.276818 u2DelayCellOfst[3]=7 cells (2 PI)
8527 14:47:16.279795 u2DelayCellOfst[4]=11 cells (3 PI)
8528 14:47:16.282961 u2DelayCellOfst[5]=22 cells (6 PI)
8529 14:47:16.286224 u2DelayCellOfst[6]=22 cells (6 PI)
8530 14:47:16.289855 u2DelayCellOfst[7]=7 cells (2 PI)
8531 14:47:16.292882 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8532 14:47:16.296625 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8533 14:47:16.299799 == TX Byte 1 ==
8534 14:47:16.303045 u2DelayCellOfst[8]=0 cells (0 PI)
8535 14:47:16.306147 u2DelayCellOfst[9]=3 cells (1 PI)
8536 14:47:16.309369 u2DelayCellOfst[10]=11 cells (3 PI)
8537 14:47:16.309972 u2DelayCellOfst[11]=3 cells (1 PI)
8538 14:47:16.312868 u2DelayCellOfst[12]=18 cells (5 PI)
8539 14:47:16.315978 u2DelayCellOfst[13]=18 cells (5 PI)
8540 14:47:16.319566 u2DelayCellOfst[14]=18 cells (5 PI)
8541 14:47:16.322623 u2DelayCellOfst[15]=18 cells (5 PI)
8542 14:47:16.328932 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8543 14:47:16.332764 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8544 14:47:16.333329 DramC Write-DBI on
8545 14:47:16.335971 ==
8546 14:47:16.336470 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 14:47:16.342228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 14:47:16.342698 ==
8549 14:47:16.343066
8550 14:47:16.343408
8551 14:47:16.346003 TX Vref Scan disable
8552 14:47:16.346629 == TX Byte 0 ==
8553 14:47:16.352744 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8554 14:47:16.353299 == TX Byte 1 ==
8555 14:47:16.355333 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8556 14:47:16.359017 DramC Write-DBI off
8557 14:47:16.359581
8558 14:47:16.359948 [DATLAT]
8559 14:47:16.362207 Freq=1600, CH1 RK0
8560 14:47:16.362774
8561 14:47:16.363140 DATLAT Default: 0xf
8562 14:47:16.365395 0, 0xFFFF, sum = 0
8563 14:47:16.365866 1, 0xFFFF, sum = 0
8564 14:47:16.368454 2, 0xFFFF, sum = 0
8565 14:47:16.368927 3, 0xFFFF, sum = 0
8566 14:47:16.372392 4, 0xFFFF, sum = 0
8567 14:47:16.373030 5, 0xFFFF, sum = 0
8568 14:47:16.375728 6, 0xFFFF, sum = 0
8569 14:47:16.376304 7, 0xFFFF, sum = 0
8570 14:47:16.378655 8, 0xFFFF, sum = 0
8571 14:47:16.381780 9, 0xFFFF, sum = 0
8572 14:47:16.382298 10, 0xFFFF, sum = 0
8573 14:47:16.385230 11, 0xFFFF, sum = 0
8574 14:47:16.385701 12, 0xFFFF, sum = 0
8575 14:47:16.388576 13, 0xFFFF, sum = 0
8576 14:47:16.389048 14, 0x0, sum = 1
8577 14:47:16.391609 15, 0x0, sum = 2
8578 14:47:16.392084 16, 0x0, sum = 3
8579 14:47:16.395340 17, 0x0, sum = 4
8580 14:47:16.395811 best_step = 15
8581 14:47:16.396225
8582 14:47:16.396581 ==
8583 14:47:16.398354 Dram Type= 6, Freq= 0, CH_1, rank 0
8584 14:47:16.401810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8585 14:47:16.405241 ==
8586 14:47:16.405805 RX Vref Scan: 1
8587 14:47:16.406332
8588 14:47:16.408629 Set Vref Range= 24 -> 127
8589 14:47:16.409190
8590 14:47:16.409557 RX Vref 24 -> 127, step: 1
8591 14:47:16.411679
8592 14:47:16.412144 RX Delay 11 -> 252, step: 4
8593 14:47:16.412511
8594 14:47:16.415020 Set Vref, RX VrefLevel [Byte0]: 24
8595 14:47:16.418335 [Byte1]: 24
8596 14:47:16.422196
8597 14:47:16.422765 Set Vref, RX VrefLevel [Byte0]: 25
8598 14:47:16.425400 [Byte1]: 25
8599 14:47:16.429515
8600 14:47:16.429979 Set Vref, RX VrefLevel [Byte0]: 26
8601 14:47:16.432874 [Byte1]: 26
8602 14:47:16.437384
8603 14:47:16.437940 Set Vref, RX VrefLevel [Byte0]: 27
8604 14:47:16.440359 [Byte1]: 27
8605 14:47:16.445096
8606 14:47:16.445670 Set Vref, RX VrefLevel [Byte0]: 28
8607 14:47:16.448069 [Byte1]: 28
8608 14:47:16.452660
8609 14:47:16.453126 Set Vref, RX VrefLevel [Byte0]: 29
8610 14:47:16.455398 [Byte1]: 29
8611 14:47:16.459970
8612 14:47:16.460530 Set Vref, RX VrefLevel [Byte0]: 30
8613 14:47:16.463462 [Byte1]: 30
8614 14:47:16.468042
8615 14:47:16.468616 Set Vref, RX VrefLevel [Byte0]: 31
8616 14:47:16.470874 [Byte1]: 31
8617 14:47:16.475395
8618 14:47:16.475957 Set Vref, RX VrefLevel [Byte0]: 32
8619 14:47:16.478410 [Byte1]: 32
8620 14:47:16.482866
8621 14:47:16.483331 Set Vref, RX VrefLevel [Byte0]: 33
8622 14:47:16.486216 [Byte1]: 33
8623 14:47:16.490278
8624 14:47:16.490816 Set Vref, RX VrefLevel [Byte0]: 34
8625 14:47:16.493869 [Byte1]: 34
8626 14:47:16.498000
8627 14:47:16.498545 Set Vref, RX VrefLevel [Byte0]: 35
8628 14:47:16.501170 [Byte1]: 35
8629 14:47:16.505550
8630 14:47:16.506108 Set Vref, RX VrefLevel [Byte0]: 36
8631 14:47:16.509230 [Byte1]: 36
8632 14:47:16.512907
8633 14:47:16.513329 Set Vref, RX VrefLevel [Byte0]: 37
8634 14:47:16.516936 [Byte1]: 37
8635 14:47:16.521079
8636 14:47:16.521638 Set Vref, RX VrefLevel [Byte0]: 38
8637 14:47:16.524259 [Byte1]: 38
8638 14:47:16.528593
8639 14:47:16.529229 Set Vref, RX VrefLevel [Byte0]: 39
8640 14:47:16.531680 [Byte1]: 39
8641 14:47:16.536256
8642 14:47:16.536816 Set Vref, RX VrefLevel [Byte0]: 40
8643 14:47:16.539701 [Byte1]: 40
8644 14:47:16.543675
8645 14:47:16.544231 Set Vref, RX VrefLevel [Byte0]: 41
8646 14:47:16.546991 [Byte1]: 41
8647 14:47:16.551311
8648 14:47:16.551767 Set Vref, RX VrefLevel [Byte0]: 42
8649 14:47:16.554513 [Byte1]: 42
8650 14:47:16.559123
8651 14:47:16.559585 Set Vref, RX VrefLevel [Byte0]: 43
8652 14:47:16.562590 [Byte1]: 43
8653 14:47:16.566496
8654 14:47:16.566989 Set Vref, RX VrefLevel [Byte0]: 44
8655 14:47:16.569931 [Byte1]: 44
8656 14:47:16.574069
8657 14:47:16.574569 Set Vref, RX VrefLevel [Byte0]: 45
8658 14:47:16.577107 [Byte1]: 45
8659 14:47:16.581844
8660 14:47:16.582546 Set Vref, RX VrefLevel [Byte0]: 46
8661 14:47:16.584847 [Byte1]: 46
8662 14:47:16.589070
8663 14:47:16.589531 Set Vref, RX VrefLevel [Byte0]: 47
8664 14:47:16.592861 [Byte1]: 47
8665 14:47:16.597193
8666 14:47:16.597756 Set Vref, RX VrefLevel [Byte0]: 48
8667 14:47:16.600472 [Byte1]: 48
8668 14:47:16.604611
8669 14:47:16.605074 Set Vref, RX VrefLevel [Byte0]: 49
8670 14:47:16.607841 [Byte1]: 49
8671 14:47:16.612017
8672 14:47:16.612476 Set Vref, RX VrefLevel [Byte0]: 50
8673 14:47:16.615508 [Byte1]: 50
8674 14:47:16.619825
8675 14:47:16.620289 Set Vref, RX VrefLevel [Byte0]: 51
8676 14:47:16.623117 [Byte1]: 51
8677 14:47:16.627621
8678 14:47:16.628213 Set Vref, RX VrefLevel [Byte0]: 52
8679 14:47:16.630770 [Byte1]: 52
8680 14:47:16.635146
8681 14:47:16.635607 Set Vref, RX VrefLevel [Byte0]: 53
8682 14:47:16.638009 [Byte1]: 53
8683 14:47:16.642888
8684 14:47:16.643351 Set Vref, RX VrefLevel [Byte0]: 54
8685 14:47:16.645942 [Byte1]: 54
8686 14:47:16.650299
8687 14:47:16.650856 Set Vref, RX VrefLevel [Byte0]: 55
8688 14:47:16.653685 [Byte1]: 55
8689 14:47:16.658095
8690 14:47:16.658749 Set Vref, RX VrefLevel [Byte0]: 56
8691 14:47:16.661225 [Byte1]: 56
8692 14:47:16.665441
8693 14:47:16.665903 Set Vref, RX VrefLevel [Byte0]: 57
8694 14:47:16.669040 [Byte1]: 57
8695 14:47:16.673315
8696 14:47:16.673877 Set Vref, RX VrefLevel [Byte0]: 58
8697 14:47:16.676412 [Byte1]: 58
8698 14:47:16.681156
8699 14:47:16.681722 Set Vref, RX VrefLevel [Byte0]: 59
8700 14:47:16.683825 [Byte1]: 59
8701 14:47:16.688564
8702 14:47:16.689125 Set Vref, RX VrefLevel [Byte0]: 60
8703 14:47:16.691489 [Byte1]: 60
8704 14:47:16.695868
8705 14:47:16.696417 Set Vref, RX VrefLevel [Byte0]: 61
8706 14:47:16.699343 [Byte1]: 61
8707 14:47:16.703364
8708 14:47:16.703825 Set Vref, RX VrefLevel [Byte0]: 62
8709 14:47:16.707153 [Byte1]: 62
8710 14:47:16.711087
8711 14:47:16.711647 Set Vref, RX VrefLevel [Byte0]: 63
8712 14:47:16.714733 [Byte1]: 63
8713 14:47:16.719136
8714 14:47:16.719693 Set Vref, RX VrefLevel [Byte0]: 64
8715 14:47:16.721866 [Byte1]: 64
8716 14:47:16.726557
8717 14:47:16.727123 Set Vref, RX VrefLevel [Byte0]: 65
8718 14:47:16.729990 [Byte1]: 65
8719 14:47:16.734035
8720 14:47:16.734711 Set Vref, RX VrefLevel [Byte0]: 66
8721 14:47:16.737720 [Byte1]: 66
8722 14:47:16.741633
8723 14:47:16.742143 Set Vref, RX VrefLevel [Byte0]: 67
8724 14:47:16.744680 [Byte1]: 67
8725 14:47:16.749083
8726 14:47:16.749546 Set Vref, RX VrefLevel [Byte0]: 68
8727 14:47:16.752338 [Byte1]: 68
8728 14:47:16.756714
8729 14:47:16.757177 Set Vref, RX VrefLevel [Byte0]: 69
8730 14:47:16.760096 [Byte1]: 69
8731 14:47:16.764450
8732 14:47:16.764911 Set Vref, RX VrefLevel [Byte0]: 70
8733 14:47:16.767860 [Byte1]: 70
8734 14:47:16.772082
8735 14:47:16.772632 Set Vref, RX VrefLevel [Byte0]: 71
8736 14:47:16.775573 [Byte1]: 71
8737 14:47:16.779668
8738 14:47:16.780131 Set Vref, RX VrefLevel [Byte0]: 72
8739 14:47:16.783258 [Byte1]: 72
8740 14:47:16.787714
8741 14:47:16.788294 Set Vref, RX VrefLevel [Byte0]: 73
8742 14:47:16.790350 [Byte1]: 73
8743 14:47:16.795140
8744 14:47:16.795696 Final RX Vref Byte 0 = 53 to rank0
8745 14:47:16.798057 Final RX Vref Byte 1 = 58 to rank0
8746 14:47:16.801274 Final RX Vref Byte 0 = 53 to rank1
8747 14:47:16.804875 Final RX Vref Byte 1 = 58 to rank1==
8748 14:47:16.808095 Dram Type= 6, Freq= 0, CH_1, rank 0
8749 14:47:16.814646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 14:47:16.815115 ==
8751 14:47:16.815479 DQS Delay:
8752 14:47:16.817775 DQS0 = 0, DQS1 = 0
8753 14:47:16.818308 DQM Delay:
8754 14:47:16.818688 DQM0 = 135, DQM1 = 129
8755 14:47:16.821227 DQ Delay:
8756 14:47:16.824575 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8757 14:47:16.828440 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8758 14:47:16.831401 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =118
8759 14:47:16.834420 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8760 14:47:16.834889
8761 14:47:16.835335
8762 14:47:16.835691
8763 14:47:16.837657 [DramC_TX_OE_Calibration] TA2
8764 14:47:16.840890 Original DQ_B0 (3 6) =30, OEN = 27
8765 14:47:16.844300 Original DQ_B1 (3 6) =30, OEN = 27
8766 14:47:16.847511 24, 0x0, End_B0=24 End_B1=24
8767 14:47:16.850984 25, 0x0, End_B0=25 End_B1=25
8768 14:47:16.851573 26, 0x0, End_B0=26 End_B1=26
8769 14:47:16.854088 27, 0x0, End_B0=27 End_B1=27
8770 14:47:16.857133 28, 0x0, End_B0=28 End_B1=28
8771 14:47:16.860288 29, 0x0, End_B0=29 End_B1=29
8772 14:47:16.863730 30, 0x0, End_B0=30 End_B1=30
8773 14:47:16.864205 31, 0x4141, End_B0=30 End_B1=30
8774 14:47:16.867004 Byte0 end_step=30 best_step=27
8775 14:47:16.870084 Byte1 end_step=30 best_step=27
8776 14:47:16.873402 Byte0 TX OE(2T, 0.5T) = (3, 3)
8777 14:47:16.876966 Byte1 TX OE(2T, 0.5T) = (3, 3)
8778 14:47:16.877620
8779 14:47:16.878113
8780 14:47:16.883497 [DQSOSCAuto] RK0, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8781 14:47:16.886605 CH1 RK0: MR19=303, MR18=170C
8782 14:47:16.893730 CH1_RK0: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8783 14:47:16.894214
8784 14:47:16.896583 ----->DramcWriteLeveling(PI) begin...
8785 14:47:16.897024 ==
8786 14:47:16.900212 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 14:47:16.903059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 14:47:16.906435 ==
8789 14:47:16.906958 Write leveling (Byte 0): 24 => 24
8790 14:47:16.909544 Write leveling (Byte 1): 27 => 27
8791 14:47:16.913218 DramcWriteLeveling(PI) end<-----
8792 14:47:16.913887
8793 14:47:16.914420 ==
8794 14:47:16.916607 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 14:47:16.923324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 14:47:16.923764 ==
8797 14:47:16.926012 [Gating] SW mode calibration
8798 14:47:16.932980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8799 14:47:16.935820 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8800 14:47:16.942976 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 14:47:16.945870 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 14:47:16.949827 1 4 8 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
8803 14:47:16.955674 1 4 12 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8804 14:47:16.959119 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 14:47:16.962277 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 14:47:16.969094 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 14:47:16.972452 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 14:47:16.975501 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 14:47:16.982304 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 14:47:16.985465 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8811 14:47:16.989417 1 5 12 | B1->B0 | 2525 3434 | 1 1 | (1 0) (1 0)
8812 14:47:16.995505 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8813 14:47:16.998671 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 14:47:17.001785 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 14:47:17.008826 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 14:47:17.012173 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 14:47:17.015232 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 14:47:17.021785 1 6 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8819 14:47:17.025077 1 6 12 | B1->B0 | 4646 2b2b | 0 0 | (0 0) (1 1)
8820 14:47:17.028401 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 14:47:17.034850 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 14:47:17.038347 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 14:47:17.041314 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 14:47:17.048214 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 14:47:17.051442 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 14:47:17.054685 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8827 14:47:17.061745 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8828 14:47:17.064903 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8829 14:47:17.067999 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 14:47:17.074422 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 14:47:17.078059 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 14:47:17.080871 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 14:47:17.087563 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 14:47:17.090878 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 14:47:17.094443 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 14:47:17.100844 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 14:47:17.104180 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 14:47:17.107711 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 14:47:17.114460 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 14:47:17.117815 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 14:47:17.121089 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 14:47:17.127452 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 14:47:17.130565 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8844 14:47:17.134116 Total UI for P1: 0, mck2ui 16
8845 14:47:17.137316 best dqsien dly found for B1: ( 1, 9, 10)
8846 14:47:17.140683 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8847 14:47:17.143908 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 14:47:17.147395 Total UI for P1: 0, mck2ui 16
8849 14:47:17.150319 best dqsien dly found for B0: ( 1, 9, 14)
8850 14:47:17.157334 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8851 14:47:17.160355 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8852 14:47:17.160819
8853 14:47:17.163339 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8854 14:47:17.166954 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8855 14:47:17.170015 [Gating] SW calibration Done
8856 14:47:17.170563 ==
8857 14:47:17.173611 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 14:47:17.177045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 14:47:17.177462 ==
8860 14:47:17.180367 RX Vref Scan: 0
8861 14:47:17.181188
8862 14:47:17.181638 RX Vref 0 -> 0, step: 1
8863 14:47:17.181964
8864 14:47:17.183820 RX Delay 0 -> 252, step: 8
8865 14:47:17.186729 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8866 14:47:17.193359 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8867 14:47:17.196811 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8868 14:47:17.200340 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8869 14:47:17.203042 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8870 14:47:17.206439 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8871 14:47:17.213153 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8872 14:47:17.216009 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8873 14:47:17.219674 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8874 14:47:17.222731 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8875 14:47:17.226087 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8876 14:47:17.233161 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8877 14:47:17.236128 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8878 14:47:17.239480 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8879 14:47:17.242392 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8880 14:47:17.249263 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8881 14:47:17.249695 ==
8882 14:47:17.252712 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 14:47:17.255844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 14:47:17.256411 ==
8885 14:47:17.256934 DQS Delay:
8886 14:47:17.259070 DQS0 = 0, DQS1 = 0
8887 14:47:17.259640 DQM Delay:
8888 14:47:17.262285 DQM0 = 136, DQM1 = 129
8889 14:47:17.262823 DQ Delay:
8890 14:47:17.265708 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8891 14:47:17.268788 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8892 14:47:17.272834 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8893 14:47:17.275917 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8894 14:47:17.278958
8895 14:47:17.279431
8896 14:47:17.279809 ==
8897 14:47:17.282545 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 14:47:17.285313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 14:47:17.285801 ==
8900 14:47:17.286284
8901 14:47:17.286760
8902 14:47:17.288880 TX Vref Scan disable
8903 14:47:17.289439 == TX Byte 0 ==
8904 14:47:17.295910 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8905 14:47:17.298687 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8906 14:47:17.299097 == TX Byte 1 ==
8907 14:47:17.305478 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8908 14:47:17.308805 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8909 14:47:17.309313 ==
8910 14:47:17.311605 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 14:47:17.315339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 14:47:17.315763 ==
8913 14:47:17.328922
8914 14:47:17.332032 TX Vref early break, caculate TX vref
8915 14:47:17.335399 TX Vref=16, minBit 1, minWin=22, winSum=388
8916 14:47:17.338876 TX Vref=18, minBit 0, minWin=23, winSum=390
8917 14:47:17.342318 TX Vref=20, minBit 0, minWin=23, winSum=402
8918 14:47:17.345624 TX Vref=22, minBit 1, minWin=24, winSum=412
8919 14:47:17.348884 TX Vref=24, minBit 0, minWin=25, winSum=416
8920 14:47:17.355582 TX Vref=26, minBit 1, minWin=25, winSum=422
8921 14:47:17.358984 TX Vref=28, minBit 0, minWin=25, winSum=424
8922 14:47:17.362028 TX Vref=30, minBit 0, minWin=24, winSum=415
8923 14:47:17.365321 TX Vref=32, minBit 1, minWin=23, winSum=406
8924 14:47:17.368287 TX Vref=34, minBit 0, minWin=23, winSum=397
8925 14:47:17.374928 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8926 14:47:17.375435
8927 14:47:17.378536 Final TX Range 0 Vref 28
8928 14:47:17.378974
8929 14:47:17.379415 ==
8930 14:47:17.381413 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 14:47:17.384449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 14:47:17.384887 ==
8933 14:47:17.385331
8934 14:47:17.385751
8935 14:47:17.387983 TX Vref Scan disable
8936 14:47:17.395229 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8937 14:47:17.395651 == TX Byte 0 ==
8938 14:47:17.397996 u2DelayCellOfst[0]=18 cells (5 PI)
8939 14:47:17.401379 u2DelayCellOfst[1]=14 cells (4 PI)
8940 14:47:17.404948 u2DelayCellOfst[2]=0 cells (0 PI)
8941 14:47:17.408057 u2DelayCellOfst[3]=7 cells (2 PI)
8942 14:47:17.411044 u2DelayCellOfst[4]=7 cells (2 PI)
8943 14:47:17.414393 u2DelayCellOfst[5]=22 cells (6 PI)
8944 14:47:17.417679 u2DelayCellOfst[6]=22 cells (6 PI)
8945 14:47:17.421098 u2DelayCellOfst[7]=7 cells (2 PI)
8946 14:47:17.424621 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8947 14:47:17.427854 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8948 14:47:17.431077 == TX Byte 1 ==
8949 14:47:17.434501 u2DelayCellOfst[8]=0 cells (0 PI)
8950 14:47:17.437495 u2DelayCellOfst[9]=7 cells (2 PI)
8951 14:47:17.437961 u2DelayCellOfst[10]=14 cells (4 PI)
8952 14:47:17.441386 u2DelayCellOfst[11]=7 cells (2 PI)
8953 14:47:17.444046 u2DelayCellOfst[12]=18 cells (5 PI)
8954 14:47:17.448085 u2DelayCellOfst[13]=18 cells (5 PI)
8955 14:47:17.450766 u2DelayCellOfst[14]=22 cells (6 PI)
8956 14:47:17.454064 u2DelayCellOfst[15]=18 cells (5 PI)
8957 14:47:17.461066 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8958 14:47:17.464504 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8959 14:47:17.465060 DramC Write-DBI on
8960 14:47:17.465434 ==
8961 14:47:17.467443 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 14:47:17.473719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 14:47:17.474330 ==
8964 14:47:17.474703
8965 14:47:17.475045
8966 14:47:17.477269 TX Vref Scan disable
8967 14:47:17.477823 == TX Byte 0 ==
8968 14:47:17.483886 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8969 14:47:17.484440 == TX Byte 1 ==
8970 14:47:17.487065 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8971 14:47:17.490270 DramC Write-DBI off
8972 14:47:17.490737
8973 14:47:17.491108 [DATLAT]
8974 14:47:17.493674 Freq=1600, CH1 RK1
8975 14:47:17.494140
8976 14:47:17.494560 DATLAT Default: 0xf
8977 14:47:17.496718 0, 0xFFFF, sum = 0
8978 14:47:17.497203 1, 0xFFFF, sum = 0
8979 14:47:17.500606 2, 0xFFFF, sum = 0
8980 14:47:17.501139 3, 0xFFFF, sum = 0
8981 14:47:17.503486 4, 0xFFFF, sum = 0
8982 14:47:17.503958 5, 0xFFFF, sum = 0
8983 14:47:17.507121 6, 0xFFFF, sum = 0
8984 14:47:17.507591 7, 0xFFFF, sum = 0
8985 14:47:17.510243 8, 0xFFFF, sum = 0
8986 14:47:17.510816 9, 0xFFFF, sum = 0
8987 14:47:17.513175 10, 0xFFFF, sum = 0
8988 14:47:17.516823 11, 0xFFFF, sum = 0
8989 14:47:17.517397 12, 0xFFFF, sum = 0
8990 14:47:17.519948 13, 0xFFFF, sum = 0
8991 14:47:17.520421 14, 0x0, sum = 1
8992 14:47:17.523648 15, 0x0, sum = 2
8993 14:47:17.524237 16, 0x0, sum = 3
8994 14:47:17.526286 17, 0x0, sum = 4
8995 14:47:17.526761 best_step = 15
8996 14:47:17.527128
8997 14:47:17.527470 ==
8998 14:47:17.529711 Dram Type= 6, Freq= 0, CH_1, rank 1
8999 14:47:17.533639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9000 14:47:17.534255 ==
9001 14:47:17.536672 RX Vref Scan: 0
9002 14:47:17.537131
9003 14:47:17.539737 RX Vref 0 -> 0, step: 1
9004 14:47:17.540238
9005 14:47:17.540599 RX Delay 11 -> 252, step: 4
9006 14:47:17.547444 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9007 14:47:17.550159 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9008 14:47:17.553457 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9009 14:47:17.556796 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9010 14:47:17.563490 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9011 14:47:17.566711 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9012 14:47:17.569966 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9013 14:47:17.573450 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9014 14:47:17.576937 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9015 14:47:17.583639 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9016 14:47:17.586419 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9017 14:47:17.589654 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9018 14:47:17.593242 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9019 14:47:17.596424 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9020 14:47:17.603488 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9021 14:47:17.606377 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9022 14:47:17.607017 ==
9023 14:47:17.609754 Dram Type= 6, Freq= 0, CH_1, rank 1
9024 14:47:17.612619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9025 14:47:17.613085 ==
9026 14:47:17.616464 DQS Delay:
9027 14:47:17.617007 DQS0 = 0, DQS1 = 0
9028 14:47:17.617379 DQM Delay:
9029 14:47:17.619480 DQM0 = 134, DQM1 = 126
9030 14:47:17.620028 DQ Delay:
9031 14:47:17.622727 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9032 14:47:17.626343 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9033 14:47:17.632859 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9034 14:47:17.636278 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =138
9035 14:47:17.636853
9036 14:47:17.637220
9037 14:47:17.637561
9038 14:47:17.639254 [DramC_TX_OE_Calibration] TA2
9039 14:47:17.642336 Original DQ_B0 (3 6) =30, OEN = 27
9040 14:47:17.645723 Original DQ_B1 (3 6) =30, OEN = 27
9041 14:47:17.646373 24, 0x0, End_B0=24 End_B1=24
9042 14:47:17.649157 25, 0x0, End_B0=25 End_B1=25
9043 14:47:17.652035 26, 0x0, End_B0=26 End_B1=26
9044 14:47:17.655619 27, 0x0, End_B0=27 End_B1=27
9045 14:47:17.658723 28, 0x0, End_B0=28 End_B1=28
9046 14:47:17.659198 29, 0x0, End_B0=29 End_B1=29
9047 14:47:17.662748 30, 0x0, End_B0=30 End_B1=30
9048 14:47:17.665523 31, 0x4141, End_B0=30 End_B1=30
9049 14:47:17.668800 Byte0 end_step=30 best_step=27
9050 14:47:17.672412 Byte1 end_step=30 best_step=27
9051 14:47:17.675284 Byte0 TX OE(2T, 0.5T) = (3, 3)
9052 14:47:17.675755 Byte1 TX OE(2T, 0.5T) = (3, 3)
9053 14:47:17.676122
9054 14:47:17.676466
9055 14:47:17.685451 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
9056 14:47:17.688641 CH1 RK1: MR19=303, MR18=D0A
9057 14:47:17.695400 CH1_RK1: MR19=0x303, MR18=0xD0A, DQSOSC=403, MR23=63, INC=22, DEC=15
9058 14:47:17.695947 [RxdqsGatingPostProcess] freq 1600
9059 14:47:17.702158 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9060 14:47:17.705157 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 14:47:17.709037 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 14:47:17.711691 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 14:47:17.714770 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 14:47:17.718087 best DQS0 dly(2T, 0.5T) = (1, 1)
9065 14:47:17.721657 best DQS1 dly(2T, 0.5T) = (1, 1)
9066 14:47:17.724812 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9067 14:47:17.728082 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9068 14:47:17.731483 Pre-setting of DQS Precalculation
9069 14:47:17.734248 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9070 14:47:17.741006 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9071 14:47:17.748101 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9072 14:47:17.748560
9073 14:47:17.751075
9074 14:47:17.751533 [Calibration Summary] 3200 Mbps
9075 14:47:17.754370 CH 0, Rank 0
9076 14:47:17.754828 SW Impedance : PASS
9077 14:47:17.757312 DUTY Scan : NO K
9078 14:47:17.760986 ZQ Calibration : PASS
9079 14:47:17.761444 Jitter Meter : NO K
9080 14:47:17.764090 CBT Training : PASS
9081 14:47:17.767328 Write leveling : PASS
9082 14:47:17.767684 RX DQS gating : PASS
9083 14:47:17.770903 RX DQ/DQS(RDDQC) : PASS
9084 14:47:17.773749 TX DQ/DQS : PASS
9085 14:47:17.773983 RX DATLAT : PASS
9086 14:47:17.776768 RX DQ/DQS(Engine): PASS
9087 14:47:17.780040 TX OE : PASS
9088 14:47:17.780193 All Pass.
9089 14:47:17.780391
9090 14:47:17.780559 CH 0, Rank 1
9091 14:47:17.783337 SW Impedance : PASS
9092 14:47:17.786634 DUTY Scan : NO K
9093 14:47:17.786786 ZQ Calibration : PASS
9094 14:47:17.790036 Jitter Meter : NO K
9095 14:47:17.793316 CBT Training : PASS
9096 14:47:17.793470 Write leveling : PASS
9097 14:47:17.796517 RX DQS gating : PASS
9098 14:47:17.800289 RX DQ/DQS(RDDQC) : PASS
9099 14:47:17.800482 TX DQ/DQS : PASS
9100 14:47:17.803654 RX DATLAT : PASS
9101 14:47:17.806485 RX DQ/DQS(Engine): PASS
9102 14:47:17.806637 TX OE : PASS
9103 14:47:17.806758 All Pass.
9104 14:47:17.809707
9105 14:47:17.809871 CH 1, Rank 0
9106 14:47:17.813632 SW Impedance : PASS
9107 14:47:17.813806 DUTY Scan : NO K
9108 14:47:17.816337 ZQ Calibration : PASS
9109 14:47:17.816490 Jitter Meter : NO K
9110 14:47:17.819990 CBT Training : PASS
9111 14:47:17.823252 Write leveling : PASS
9112 14:47:17.823404 RX DQS gating : PASS
9113 14:47:17.826430 RX DQ/DQS(RDDQC) : PASS
9114 14:47:17.829811 TX DQ/DQS : PASS
9115 14:47:17.830046 RX DATLAT : PASS
9116 14:47:17.833175 RX DQ/DQS(Engine): PASS
9117 14:47:17.836453 TX OE : PASS
9118 14:47:17.836649 All Pass.
9119 14:47:17.836805
9120 14:47:17.836953 CH 1, Rank 1
9121 14:47:17.839889 SW Impedance : PASS
9122 14:47:17.842786 DUTY Scan : NO K
9123 14:47:17.842960 ZQ Calibration : PASS
9124 14:47:17.846293 Jitter Meter : NO K
9125 14:47:17.849776 CBT Training : PASS
9126 14:47:17.849999 Write leveling : PASS
9127 14:47:17.853241 RX DQS gating : PASS
9128 14:47:17.855844 RX DQ/DQS(RDDQC) : PASS
9129 14:47:17.856109 TX DQ/DQS : PASS
9130 14:47:17.859217 RX DATLAT : PASS
9131 14:47:17.862505 RX DQ/DQS(Engine): PASS
9132 14:47:17.862777 TX OE : PASS
9133 14:47:17.865891 All Pass.
9134 14:47:17.866148
9135 14:47:17.866373 DramC Write-DBI on
9136 14:47:17.869156 PER_BANK_REFRESH: Hybrid Mode
9137 14:47:17.869399 TX_TRACKING: ON
9138 14:47:17.879078 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9139 14:47:17.889150 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9140 14:47:17.895772 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9141 14:47:17.899334 [FAST_K] Save calibration result to emmc
9142 14:47:17.902196 sync common calibartion params.
9143 14:47:17.902664 sync cbt_mode0:1, 1:1
9144 14:47:17.905486 dram_init: ddr_geometry: 2
9145 14:47:17.909036 dram_init: ddr_geometry: 2
9146 14:47:17.912142 dram_init: ddr_geometry: 2
9147 14:47:17.912622 0:dram_rank_size:100000000
9148 14:47:17.915389 1:dram_rank_size:100000000
9149 14:47:17.922210 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9150 14:47:17.922694 DFS_SHUFFLE_HW_MODE: ON
9151 14:47:17.928589 dramc_set_vcore_voltage set vcore to 725000
9152 14:47:17.929063 Read voltage for 1600, 0
9153 14:47:17.932021 Vio18 = 0
9154 14:47:17.932551 Vcore = 725000
9155 14:47:17.932891 Vdram = 0
9156 14:47:17.935280 Vddq = 0
9157 14:47:17.935700 Vmddr = 0
9158 14:47:17.938491 switch to 3200 Mbps bootup
9159 14:47:17.938914 [DramcRunTimeConfig]
9160 14:47:17.939252 PHYPLL
9161 14:47:17.941531 DPM_CONTROL_AFTERK: ON
9162 14:47:17.945105 PER_BANK_REFRESH: ON
9163 14:47:17.945530 REFRESH_OVERHEAD_REDUCTION: ON
9164 14:47:17.948114 CMD_PICG_NEW_MODE: OFF
9165 14:47:17.951587 XRTWTW_NEW_MODE: ON
9166 14:47:17.952008 XRTRTR_NEW_MODE: ON
9167 14:47:17.955212 TX_TRACKING: ON
9168 14:47:17.955636 RDSEL_TRACKING: OFF
9169 14:47:17.958089 DQS Precalculation for DVFS: ON
9170 14:47:17.958548 RX_TRACKING: OFF
9171 14:47:17.961270 HW_GATING DBG: ON
9172 14:47:17.961689 ZQCS_ENABLE_LP4: ON
9173 14:47:17.964864 RX_PICG_NEW_MODE: ON
9174 14:47:17.968082 TX_PICG_NEW_MODE: ON
9175 14:47:17.968505 ENABLE_RX_DCM_DPHY: ON
9176 14:47:17.971576 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9177 14:47:17.974377 DUMMY_READ_FOR_TRACKING: OFF
9178 14:47:17.978015 !!! SPM_CONTROL_AFTERK: OFF
9179 14:47:17.981291 !!! SPM could not control APHY
9180 14:47:17.981818 IMPEDANCE_TRACKING: ON
9181 14:47:17.984870 TEMP_SENSOR: ON
9182 14:47:17.985396 HW_SAVE_FOR_SR: OFF
9183 14:47:17.987941 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9184 14:47:17.990916 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9185 14:47:17.994424 Read ODT Tracking: ON
9186 14:47:17.997736 Refresh Rate DeBounce: ON
9187 14:47:17.998199 DFS_NO_QUEUE_FLUSH: ON
9188 14:47:18.001657 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9189 14:47:18.004809 ENABLE_DFS_RUNTIME_MRW: OFF
9190 14:47:18.007809 DDR_RESERVE_NEW_MODE: ON
9191 14:47:18.008247 MR_CBT_SWITCH_FREQ: ON
9192 14:47:18.010860 =========================
9193 14:47:18.028887 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9194 14:47:18.032010 dram_init: ddr_geometry: 2
9195 14:47:18.050425 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9196 14:47:18.054034 dram_init: dram init end (result: 0)
9197 14:47:18.060441 DRAM-K: Full calibration passed in 24632 msecs
9198 14:47:18.063499 MRC: failed to locate region type 0.
9199 14:47:18.063585 DRAM rank0 size:0x100000000,
9200 14:47:18.067217 DRAM rank1 size=0x100000000
9201 14:47:18.076877 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9202 14:47:18.083274 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9203 14:47:18.089678 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9204 14:47:18.100077 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9205 14:47:18.100168 DRAM rank0 size:0x100000000,
9206 14:47:18.102965 DRAM rank1 size=0x100000000
9207 14:47:18.103051 CBMEM:
9208 14:47:18.106201 IMD: root @ 0xfffff000 254 entries.
9209 14:47:18.109799 IMD: root @ 0xffffec00 62 entries.
9210 14:47:18.112974 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9211 14:47:18.119706 WARNING: RO_VPD is uninitialized or empty.
9212 14:47:18.123117 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9213 14:47:18.130862 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9214 14:47:18.143218 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9215 14:47:18.155031 BS: romstage times (exec / console): total (unknown) / 24124 ms
9216 14:47:18.155258
9217 14:47:18.155434
9218 14:47:18.164861 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9219 14:47:18.168046 ARM64: Exception handlers installed.
9220 14:47:18.171273 ARM64: Testing exception
9221 14:47:18.174696 ARM64: Done test exception
9222 14:47:18.174919 Enumerating buses...
9223 14:47:18.178231 Show all devs... Before device enumeration.
9224 14:47:18.181567 Root Device: enabled 1
9225 14:47:18.184480 CPU_CLUSTER: 0: enabled 1
9226 14:47:18.184763 CPU: 00: enabled 1
9227 14:47:18.187928 Compare with tree...
9228 14:47:18.188342 Root Device: enabled 1
9229 14:47:18.191071 CPU_CLUSTER: 0: enabled 1
9230 14:47:18.194759 CPU: 00: enabled 1
9231 14:47:18.195221 Root Device scanning...
9232 14:47:18.197751 scan_static_bus for Root Device
9233 14:47:18.201100 CPU_CLUSTER: 0 enabled
9234 14:47:18.204407 scan_static_bus for Root Device done
9235 14:47:18.207734 scan_bus: bus Root Device finished in 8 msecs
9236 14:47:18.208363 done
9237 14:47:18.214541 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9238 14:47:18.218146 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9239 14:47:18.224160 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9240 14:47:18.231794 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9241 14:47:18.232309 Allocating resources...
9242 14:47:18.234349 Reading resources...
9243 14:47:18.237509 Root Device read_resources bus 0 link: 0
9244 14:47:18.240647 DRAM rank0 size:0x100000000,
9245 14:47:18.241108 DRAM rank1 size=0x100000000
9246 14:47:18.246886 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9247 14:47:18.247308 CPU: 00 missing read_resources
9248 14:47:18.254326 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9249 14:47:18.257116 Root Device read_resources bus 0 link: 0 done
9250 14:47:18.260438 Done reading resources.
9251 14:47:18.264081 Show resources in subtree (Root Device)...After reading.
9252 14:47:18.266828 Root Device child on link 0 CPU_CLUSTER: 0
9253 14:47:18.270266 CPU_CLUSTER: 0 child on link 0 CPU: 00
9254 14:47:18.280181 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9255 14:47:18.280613 CPU: 00
9256 14:47:18.286659 Root Device assign_resources, bus 0 link: 0
9257 14:47:18.289956 CPU_CLUSTER: 0 missing set_resources
9258 14:47:18.293406 Root Device assign_resources, bus 0 link: 0 done
9259 14:47:18.296740 Done setting resources.
9260 14:47:18.300360 Show resources in subtree (Root Device)...After assigning values.
9261 14:47:18.302856 Root Device child on link 0 CPU_CLUSTER: 0
9262 14:47:18.309606 CPU_CLUSTER: 0 child on link 0 CPU: 00
9263 14:47:18.316126 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9264 14:47:18.319374 CPU: 00
9265 14:47:18.319795 Done allocating resources.
9266 14:47:18.326236 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9267 14:47:18.326693 Enabling resources...
9268 14:47:18.329217 done.
9269 14:47:18.332953 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9270 14:47:18.335962 Initializing devices...
9271 14:47:18.336522 Root Device init
9272 14:47:18.339229 init hardware done!
9273 14:47:18.339649 0x00000018: ctrlr->caps
9274 14:47:18.343085 52.000 MHz: ctrlr->f_max
9275 14:47:18.345954 0.400 MHz: ctrlr->f_min
9276 14:47:18.350134 0x40ff8080: ctrlr->voltages
9277 14:47:18.350691 sclk: 390625
9278 14:47:18.351027 Bus Width = 1
9279 14:47:18.352366 sclk: 390625
9280 14:47:18.352733 Bus Width = 1
9281 14:47:18.356217 Early init status = 3
9282 14:47:18.359215 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9283 14:47:18.362991 in-header: 03 fc 00 00 01 00 00 00
9284 14:47:18.365974 in-data: 00
9285 14:47:18.369161 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9286 14:47:18.373788 in-header: 03 fd 00 00 00 00 00 00
9287 14:47:18.377370 in-data:
9288 14:47:18.380604 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9289 14:47:18.384010 in-header: 03 fc 00 00 01 00 00 00
9290 14:47:18.387459 in-data: 00
9291 14:47:18.390758 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9292 14:47:18.395326 in-header: 03 fd 00 00 00 00 00 00
9293 14:47:18.398144 in-data:
9294 14:47:18.401666 [SSUSB] Setting up USB HOST controller...
9295 14:47:18.404957 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9296 14:47:18.408147 [SSUSB] phy power-on done.
9297 14:47:18.411515 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9298 14:47:18.418229 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9299 14:47:18.421559 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9300 14:47:18.428123 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9301 14:47:18.434529 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9302 14:47:18.440995 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9303 14:47:18.448064 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9304 14:47:18.454119 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9305 14:47:18.457557 SPM: binary array size = 0x9dc
9306 14:47:18.464691 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9307 14:47:18.467316 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9308 14:47:18.474002 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9309 14:47:18.480637 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9310 14:47:18.483661 configure_display: Starting display init
9311 14:47:18.518879 anx7625_power_on_init: Init interface.
9312 14:47:18.521907 anx7625_disable_pd_protocol: Disabled PD feature.
9313 14:47:18.525176 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9314 14:47:18.553134 anx7625_start_dp_work: Secure OCM version=00
9315 14:47:18.555930 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9316 14:47:18.571082 sp_tx_get_edid_block: EDID Block = 1
9317 14:47:18.673754 Extracted contents:
9318 14:47:18.677198 header: 00 ff ff ff ff ff ff 00
9319 14:47:18.680271 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9320 14:47:18.683788 version: 01 04
9321 14:47:18.686623 basic params: 95 1f 11 78 0a
9322 14:47:18.689796 chroma info: 76 90 94 55 54 90 27 21 50 54
9323 14:47:18.693178 established: 00 00 00
9324 14:47:18.700176 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9325 14:47:18.706638 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9326 14:47:18.710020 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9327 14:47:18.716657 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9328 14:47:18.722997 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9329 14:47:18.726590 extensions: 00
9330 14:47:18.727087 checksum: fb
9331 14:47:18.727457
9332 14:47:18.729589 Manufacturer: IVO Model 57d Serial Number 0
9333 14:47:18.733044 Made week 0 of 2020
9334 14:47:18.736393 EDID version: 1.4
9335 14:47:18.736942 Digital display
9336 14:47:18.739548 6 bits per primary color channel
9337 14:47:18.740021 DisplayPort interface
9338 14:47:18.742830 Maximum image size: 31 cm x 17 cm
9339 14:47:18.746330 Gamma: 220%
9340 14:47:18.746882 Check DPMS levels
9341 14:47:18.749661 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9342 14:47:18.755801 First detailed timing is preferred timing
9343 14:47:18.756345 Established timings supported:
9344 14:47:18.759394 Standard timings supported:
9345 14:47:18.762770 Detailed timings
9346 14:47:18.766411 Hex of detail: 383680a07038204018303c0035ae10000019
9347 14:47:18.773252 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9348 14:47:18.775888 0780 0798 07c8 0820 hborder 0
9349 14:47:18.779201 0438 043b 0447 0458 vborder 0
9350 14:47:18.783017 -hsync -vsync
9351 14:47:18.783575 Did detailed timing
9352 14:47:18.789745 Hex of detail: 000000000000000000000000000000000000
9353 14:47:18.792367 Manufacturer-specified data, tag 0
9354 14:47:18.796252 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9355 14:47:18.799096 ASCII string: InfoVision
9356 14:47:18.802430 Hex of detail: 000000fe00523134304e574635205248200a
9357 14:47:18.805945 ASCII string: R140NWF5 RH
9358 14:47:18.806438 Checksum
9359 14:47:18.809435 Checksum: 0xfb (valid)
9360 14:47:18.812366 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9361 14:47:18.815971 DSI data_rate: 832800000 bps
9362 14:47:18.822463 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9363 14:47:18.825751 anx7625_parse_edid: pixelclock(138800).
9364 14:47:18.828973 hactive(1920), hsync(48), hfp(24), hbp(88)
9365 14:47:18.832504 vactive(1080), vsync(12), vfp(3), vbp(17)
9366 14:47:18.835673 anx7625_dsi_config: config dsi.
9367 14:47:18.842030 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9368 14:47:18.855830 anx7625_dsi_config: success to config DSI
9369 14:47:18.859038 anx7625_dp_start: MIPI phy setup OK.
9370 14:47:18.862553 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9371 14:47:18.865629 mtk_ddp_mode_set invalid vrefresh 60
9372 14:47:18.869277 main_disp_path_setup
9373 14:47:18.869742 ovl_layer_smi_id_en
9374 14:47:18.872144 ovl_layer_smi_id_en
9375 14:47:18.872627 ccorr_config
9376 14:47:18.872989 aal_config
9377 14:47:18.875281 gamma_config
9378 14:47:18.875744 postmask_config
9379 14:47:18.878835 dither_config
9380 14:47:18.882256 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9381 14:47:18.888691 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9382 14:47:18.891838 Root Device init finished in 551 msecs
9383 14:47:18.895251 CPU_CLUSTER: 0 init
9384 14:47:18.902270 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9385 14:47:18.908950 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9386 14:47:18.909417 APU_MBOX 0x190000b0 = 0x10001
9387 14:47:18.912106 APU_MBOX 0x190001b0 = 0x10001
9388 14:47:18.914899 APU_MBOX 0x190005b0 = 0x10001
9389 14:47:18.918729 APU_MBOX 0x190006b0 = 0x10001
9390 14:47:18.925595 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9391 14:47:18.934410 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9392 14:47:18.947232 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9393 14:47:18.953511 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9394 14:47:18.965588 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9395 14:47:18.974640 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9396 14:47:18.977388 CPU_CLUSTER: 0 init finished in 81 msecs
9397 14:47:18.981483 Devices initialized
9398 14:47:18.984030 Show all devs... After init.
9399 14:47:18.984490 Root Device: enabled 1
9400 14:47:18.987412 CPU_CLUSTER: 0: enabled 1
9401 14:47:18.991088 CPU: 00: enabled 1
9402 14:47:18.994382 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9403 14:47:18.997996 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9404 14:47:19.000576 ELOG: NV offset 0x57f000 size 0x1000
9405 14:47:19.007888 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9406 14:47:19.014604 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9407 14:47:19.017696 ELOG: Event(17) added with size 13 at 2024-06-04 14:47:19 UTC
9408 14:47:19.020859 out: cmd=0x121: 03 db 21 01 00 00 00 00
9409 14:47:19.025199 in-header: 03 69 00 00 2c 00 00 00
9410 14:47:19.038064 in-data: d5 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9411 14:47:19.045082 ELOG: Event(A1) added with size 10 at 2024-06-04 14:47:19 UTC
9412 14:47:19.051593 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9413 14:47:19.057909 ELOG: Event(A0) added with size 9 at 2024-06-04 14:47:19 UTC
9414 14:47:19.061343 elog_add_boot_reason: Logged dev mode boot
9415 14:47:19.065138 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9416 14:47:19.068142 Finalize devices...
9417 14:47:19.068788 Devices finalized
9418 14:47:19.074805 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9419 14:47:19.077917 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9420 14:47:19.081510 in-header: 03 07 00 00 08 00 00 00
9421 14:47:19.084507 in-data: aa e4 47 04 13 02 00 00
9422 14:47:19.088116 Chrome EC: UHEPI supported
9423 14:47:19.094988 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9424 14:47:19.097866 in-header: 03 a9 00 00 08 00 00 00
9425 14:47:19.100898 in-data: 84 60 60 08 00 00 00 00
9426 14:47:19.104293 ELOG: Event(91) added with size 10 at 2024-06-04 14:47:19 UTC
9427 14:47:19.110908 Chrome EC: clear events_b mask to 0x0000000020004000
9428 14:47:19.117948 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9429 14:47:19.121155 in-header: 03 fd 00 00 00 00 00 00
9430 14:47:19.121704 in-data:
9431 14:47:19.127634 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9432 14:47:19.131367 Writing coreboot table at 0xffe64000
9433 14:47:19.134520 0. 000000000010a000-0000000000113fff: RAMSTAGE
9434 14:47:19.138098 1. 0000000040000000-00000000400fffff: RAM
9435 14:47:19.144123 2. 0000000040100000-000000004032afff: RAMSTAGE
9436 14:47:19.147780 3. 000000004032b000-00000000545fffff: RAM
9437 14:47:19.151079 4. 0000000054600000-000000005465ffff: BL31
9438 14:47:19.154585 5. 0000000054660000-00000000ffe63fff: RAM
9439 14:47:19.161130 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9440 14:47:19.164317 7. 0000000100000000-000000023fffffff: RAM
9441 14:47:19.167405 Passing 5 GPIOs to payload:
9442 14:47:19.170660 NAME | PORT | POLARITY | VALUE
9443 14:47:19.173672 EC in RW | 0x000000aa | low | undefined
9444 14:47:19.180190 EC interrupt | 0x00000005 | low | undefined
9445 14:47:19.183667 TPM interrupt | 0x000000ab | high | undefined
9446 14:47:19.190780 SD card detect | 0x00000011 | high | undefined
9447 14:47:19.194089 speaker enable | 0x00000093 | high | undefined
9448 14:47:19.196885 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9449 14:47:19.200336 in-header: 03 f9 00 00 02 00 00 00
9450 14:47:19.203707 in-data: 02 00
9451 14:47:19.206737 ADC[4]: Raw value=903031 ID=7
9452 14:47:19.207199 ADC[3]: Raw value=214021 ID=1
9453 14:47:19.210049 RAM Code: 0x71
9454 14:47:19.213434 ADC[6]: Raw value=75036 ID=0
9455 14:47:19.217247 ADC[5]: Raw value=213282 ID=1
9456 14:47:19.217797 SKU Code: 0x1
9457 14:47:19.223896 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 573b
9458 14:47:19.224448 coreboot table: 964 bytes.
9459 14:47:19.226584 IMD ROOT 0. 0xfffff000 0x00001000
9460 14:47:19.229719 IMD SMALL 1. 0xffffe000 0x00001000
9461 14:47:19.233330 RO MCACHE 2. 0xffffc000 0x00001104
9462 14:47:19.236869 CONSOLE 3. 0xfff7c000 0x00080000
9463 14:47:19.239688 FMAP 4. 0xfff7b000 0x00000452
9464 14:47:19.242871 TIME STAMP 5. 0xfff7a000 0x00000910
9465 14:47:19.246437 VBOOT WORK 6. 0xfff66000 0x00014000
9466 14:47:19.249617 RAMOOPS 7. 0xffe66000 0x00100000
9467 14:47:19.252790 COREBOOT 8. 0xffe64000 0x00002000
9468 14:47:19.256505 IMD small region:
9469 14:47:19.259411 IMD ROOT 0. 0xffffec00 0x00000400
9470 14:47:19.262681 VPD 1. 0xffffeb80 0x0000006c
9471 14:47:19.266081 MMC STATUS 2. 0xffffeb60 0x00000004
9472 14:47:19.269234 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9473 14:47:19.276802 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9474 14:47:19.317762 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9475 14:47:19.321054 Checking segment from ROM address 0x40100000
9476 14:47:19.327469 Checking segment from ROM address 0x4010001c
9477 14:47:19.331183 Loading segment from ROM address 0x40100000
9478 14:47:19.331744 code (compression=0)
9479 14:47:19.340699 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9480 14:47:19.347528 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9481 14:47:19.348085 it's not compressed!
9482 14:47:19.354135 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9483 14:47:19.360615 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9484 14:47:19.377952 Loading segment from ROM address 0x4010001c
9485 14:47:19.378536 Entry Point 0x80000000
9486 14:47:19.381138 Loaded segments
9487 14:47:19.384381 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9488 14:47:19.391293 Jumping to boot code at 0x80000000(0xffe64000)
9489 14:47:19.397716 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9490 14:47:19.404778 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9491 14:47:19.412724 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9492 14:47:19.415439 Checking segment from ROM address 0x40100000
9493 14:47:19.418629 Checking segment from ROM address 0x4010001c
9494 14:47:19.425616 Loading segment from ROM address 0x40100000
9495 14:47:19.426155 code (compression=1)
9496 14:47:19.432071 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9497 14:47:19.441744 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9498 14:47:19.442256 using LZMA
9499 14:47:19.450799 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9500 14:47:19.457088 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9501 14:47:19.460608 Loading segment from ROM address 0x4010001c
9502 14:47:19.461026 Entry Point 0x54601000
9503 14:47:19.463768 Loaded segments
9504 14:47:19.467332 NOTICE: MT8192 bl31_setup
9505 14:47:19.474571 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9506 14:47:19.477546 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9507 14:47:19.481089 WARNING: region 0:
9508 14:47:19.484297 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 14:47:19.484718 WARNING: region 1:
9510 14:47:19.490761 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9511 14:47:19.494188 WARNING: region 2:
9512 14:47:19.497397 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9513 14:47:19.500961 WARNING: region 3:
9514 14:47:19.507131 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9515 14:47:19.507583 WARNING: region 4:
9516 14:47:19.513775 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9517 14:47:19.514233 WARNING: region 5:
9518 14:47:19.516775 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 14:47:19.520171 WARNING: region 6:
9520 14:47:19.523537 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 14:47:19.526721 WARNING: region 7:
9522 14:47:19.529785 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 14:47:19.536968 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9524 14:47:19.540269 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9525 14:47:19.546672 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9526 14:47:19.550054 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9527 14:47:19.553590 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9528 14:47:19.560074 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9529 14:47:19.563566 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9530 14:47:19.566510 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9531 14:47:19.573253 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9532 14:47:19.576430 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9533 14:47:19.582836 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9534 14:47:19.586247 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9535 14:47:19.589954 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9536 14:47:19.596036 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9537 14:47:19.599734 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9538 14:47:19.606898 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9539 14:47:19.609595 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9540 14:47:19.613035 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9541 14:47:19.619465 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9542 14:47:19.622487 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9543 14:47:19.629037 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9544 14:47:19.632554 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9545 14:47:19.635654 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9546 14:47:19.642770 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9547 14:47:19.645829 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9548 14:47:19.652532 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9549 14:47:19.655861 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9550 14:47:19.659102 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9551 14:47:19.665976 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9552 14:47:19.668939 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9553 14:47:19.675762 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9554 14:47:19.679470 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9555 14:47:19.682039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9556 14:47:19.685243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9557 14:47:19.692210 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9558 14:47:19.695432 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9559 14:47:19.698566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9560 14:47:19.701569 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9561 14:47:19.708984 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9562 14:47:19.712262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9563 14:47:19.715137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9564 14:47:19.718509 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9565 14:47:19.725109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9566 14:47:19.728097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9567 14:47:19.731701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9568 14:47:19.738427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9569 14:47:19.741774 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9570 14:47:19.744735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9571 14:47:19.751181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9572 14:47:19.754755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9573 14:47:19.761321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9574 14:47:19.764827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9575 14:47:19.767590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9576 14:47:19.774471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9577 14:47:19.777733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9578 14:47:19.783982 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9579 14:47:19.787507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9580 14:47:19.794141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9581 14:47:19.797396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9582 14:47:19.800626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9583 14:47:19.807568 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9584 14:47:19.810673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9585 14:47:19.817589 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9586 14:47:19.820831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9587 14:47:19.827431 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9588 14:47:19.830780 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9589 14:47:19.837390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9590 14:47:19.840453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9591 14:47:19.844248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9592 14:47:19.850361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9593 14:47:19.854559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9594 14:47:19.860481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9595 14:47:19.863849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9596 14:47:19.870306 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9597 14:47:19.873886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9598 14:47:19.880152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9599 14:47:19.883341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9600 14:47:19.889698 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9601 14:47:19.893873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9602 14:47:19.896519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9603 14:47:19.903139 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9604 14:47:19.906088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9605 14:47:19.913546 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9606 14:47:19.916444 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9607 14:47:19.922961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9608 14:47:19.926202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9609 14:47:19.932992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9610 14:47:19.936077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9611 14:47:19.940123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9612 14:47:19.945865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9613 14:47:19.949461 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9614 14:47:19.955956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9615 14:47:19.959082 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9616 14:47:19.966394 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9617 14:47:19.969220 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9618 14:47:19.975509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9619 14:47:19.979166 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9620 14:47:19.982030 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9621 14:47:19.986219 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9622 14:47:19.992694 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9623 14:47:19.995423 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9624 14:47:19.998605 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9625 14:47:20.005378 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9626 14:47:20.008445 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9627 14:47:20.015301 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9628 14:47:20.018613 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9629 14:47:20.022104 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9630 14:47:20.029133 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9631 14:47:20.031788 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9632 14:47:20.038611 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9633 14:47:20.041591 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9634 14:47:20.044986 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9635 14:47:20.051681 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9636 14:47:20.054740 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9637 14:47:20.061595 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9638 14:47:20.064689 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9639 14:47:20.067771 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9640 14:47:20.074695 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9641 14:47:20.077996 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9642 14:47:20.081208 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9643 14:47:20.084791 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9644 14:47:20.090963 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9645 14:47:20.094329 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9646 14:47:20.097917 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9647 14:47:20.104312 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9648 14:47:20.107671 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9649 14:47:20.111518 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9650 14:47:20.117425 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9651 14:47:20.120882 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9652 14:47:20.127100 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9653 14:47:20.130704 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9654 14:47:20.134129 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9655 14:47:20.140592 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9656 14:47:20.143762 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9657 14:47:20.151090 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9658 14:47:20.154091 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9659 14:47:20.157351 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9660 14:47:20.163877 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9661 14:47:20.167375 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9662 14:47:20.174362 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9663 14:47:20.176861 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9664 14:47:20.180328 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9665 14:47:20.187040 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9666 14:47:20.190260 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9667 14:47:20.196466 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9668 14:47:20.199899 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9669 14:47:20.203360 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9670 14:47:20.210059 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9671 14:47:20.213230 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9672 14:47:20.219721 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9673 14:47:20.223191 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9674 14:47:20.226655 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9675 14:47:20.233825 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9676 14:47:20.236544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9677 14:47:20.243068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9678 14:47:20.246433 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9679 14:47:20.249983 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9680 14:47:20.256526 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9681 14:47:20.259531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9682 14:47:20.266226 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9683 14:47:20.269277 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9684 14:47:20.272350 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9685 14:47:20.279050 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9686 14:47:20.282281 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9687 14:47:20.289014 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9688 14:47:20.292496 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9689 14:47:20.295870 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9690 14:47:20.302448 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9691 14:47:20.305974 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9692 14:47:20.312185 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9693 14:47:20.315339 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9694 14:47:20.318658 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9695 14:47:20.325660 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9696 14:47:20.328779 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9697 14:47:20.332182 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9698 14:47:20.338787 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9699 14:47:20.341868 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9700 14:47:20.348847 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9701 14:47:20.351929 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9702 14:47:20.355318 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9703 14:47:20.362130 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9704 14:47:20.365187 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9705 14:47:20.371781 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9706 14:47:20.374881 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9707 14:47:20.378094 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9708 14:47:20.385041 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9709 14:47:20.387930 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9710 14:47:20.394564 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9711 14:47:20.398134 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9712 14:47:20.404571 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9713 14:47:20.407903 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9714 14:47:20.411691 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9715 14:47:20.418107 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9716 14:47:20.421438 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9717 14:47:20.428291 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9718 14:47:20.431454 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9719 14:47:20.437984 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9720 14:47:20.441212 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9721 14:47:20.444492 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9722 14:47:20.451417 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9723 14:47:20.454776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9724 14:47:20.460919 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9725 14:47:20.464804 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9726 14:47:20.467772 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9727 14:47:20.474579 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9728 14:47:20.477737 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9729 14:47:20.484249 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9730 14:47:20.487365 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9731 14:47:20.494499 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9732 14:47:20.497545 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9733 14:47:20.500789 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9734 14:47:20.507470 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9735 14:47:20.510394 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9736 14:47:20.517043 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9737 14:47:20.520762 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9738 14:47:20.527015 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9739 14:47:20.531041 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9740 14:47:20.533984 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9741 14:47:20.540065 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9742 14:47:20.543848 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9743 14:47:20.549961 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9744 14:47:20.553136 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9745 14:47:20.559916 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9746 14:47:20.563530 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9747 14:47:20.566662 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9748 14:47:20.572959 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9749 14:47:20.576118 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9750 14:47:20.582809 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9751 14:47:20.586614 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9752 14:47:20.589876 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9753 14:47:20.596544 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9754 14:47:20.600047 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9755 14:47:20.602775 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9756 14:47:20.606241 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9757 14:47:20.612634 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9758 14:47:20.616235 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9759 14:47:20.619287 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9760 14:47:20.626097 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9761 14:47:20.629253 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9762 14:47:20.636075 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9763 14:47:20.638986 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9764 14:47:20.642812 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9765 14:47:20.648862 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9766 14:47:20.652179 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9767 14:47:20.655241 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9768 14:47:20.662381 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9769 14:47:20.665684 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9770 14:47:20.672631 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9771 14:47:20.675218 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9772 14:47:20.678719 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9773 14:47:20.685133 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9774 14:47:20.688523 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9775 14:47:20.695408 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9776 14:47:20.698518 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9777 14:47:20.701629 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9778 14:47:20.708528 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9779 14:47:20.711968 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9780 14:47:20.715376 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9781 14:47:20.722003 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9782 14:47:20.725344 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9783 14:47:20.728121 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9784 14:47:20.735041 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9785 14:47:20.738417 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9786 14:47:20.741655 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9787 14:47:20.748316 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9788 14:47:20.751549 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9789 14:47:20.758915 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9790 14:47:20.761612 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9791 14:47:20.764486 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9792 14:47:20.771484 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9793 14:47:20.774603 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9794 14:47:20.777684 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9795 14:47:20.781190 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9796 14:47:20.784368 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9797 14:47:20.790866 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9798 14:47:20.794216 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9799 14:47:20.797650 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9800 14:47:20.800941 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9801 14:47:20.807366 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9802 14:47:20.810772 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9803 14:47:20.813891 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9804 14:47:20.820312 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9805 14:47:20.823645 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9806 14:47:20.830549 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9807 14:47:20.833979 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9808 14:47:20.837300 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9809 14:47:20.843592 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9810 14:47:20.847074 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9811 14:47:20.853301 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9812 14:47:20.856767 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9813 14:47:20.859851 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9814 14:47:20.866675 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9815 14:47:20.869952 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9816 14:47:20.876778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9817 14:47:20.879854 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9818 14:47:20.887009 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9819 14:47:20.889861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9820 14:47:20.893081 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9821 14:47:20.899800 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9822 14:47:20.903240 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9823 14:47:20.909530 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9824 14:47:20.913220 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9825 14:47:20.916387 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9826 14:47:20.923113 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9827 14:47:20.926842 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9828 14:47:20.933024 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9829 14:47:20.936554 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9830 14:47:20.939493 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9831 14:47:20.946009 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9832 14:47:20.949328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9833 14:47:20.956053 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9834 14:47:20.959432 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9835 14:47:20.965989 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9836 14:47:20.969137 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9837 14:47:20.972503 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9838 14:47:20.979040 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9839 14:47:20.982031 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9840 14:47:20.989299 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9841 14:47:20.992150 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9842 14:47:20.998681 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9843 14:47:21.001862 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9844 14:47:21.005611 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9845 14:47:21.011830 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9846 14:47:21.015073 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9847 14:47:21.021775 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9848 14:47:21.024886 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9849 14:47:21.031568 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9850 14:47:21.034906 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9851 14:47:21.038626 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9852 14:47:21.045043 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9853 14:47:21.048175 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9854 14:47:21.051451 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9855 14:47:21.058633 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9856 14:47:21.061515 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9857 14:47:21.068162 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9858 14:47:21.071848 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9859 14:47:21.078632 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9860 14:47:21.081635 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9861 14:47:21.084818 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9862 14:47:21.091083 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9863 14:47:21.094685 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9864 14:47:21.101018 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9865 14:47:21.104319 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9866 14:47:21.111006 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9867 14:47:21.114727 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9868 14:47:21.117312 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9869 14:47:21.124335 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9870 14:47:21.127563 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9871 14:47:21.134111 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9872 14:47:21.137245 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9873 14:47:21.140720 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9874 14:47:21.147729 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9875 14:47:21.150515 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9876 14:47:21.157283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9877 14:47:21.160390 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9878 14:47:21.167499 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9879 14:47:21.170441 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9880 14:47:21.173665 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9881 14:47:21.181425 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9882 14:47:21.183641 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9883 14:47:21.190219 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9884 14:47:21.193686 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9885 14:47:21.200342 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9886 14:47:21.203240 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9887 14:47:21.210147 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9888 14:47:21.213562 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9889 14:47:21.219524 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9890 14:47:21.223205 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9891 14:47:21.226843 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9892 14:47:21.233337 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9893 14:47:21.236296 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9894 14:47:21.242889 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9895 14:47:21.246654 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9896 14:47:21.252781 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9897 14:47:21.256381 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9898 14:47:21.259607 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9899 14:47:21.266267 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9900 14:47:21.269875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9901 14:47:21.276332 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9902 14:47:21.279488 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9903 14:47:21.285924 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9904 14:47:21.289168 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9905 14:47:21.292571 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9906 14:47:21.299124 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9907 14:47:21.302881 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9908 14:47:21.309470 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9909 14:47:21.312599 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9910 14:47:21.319150 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9911 14:47:21.322425 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9912 14:47:21.329142 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9913 14:47:21.332086 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9914 14:47:21.338914 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9915 14:47:21.342078 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9916 14:47:21.345443 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9917 14:47:21.352569 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9918 14:47:21.355655 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9919 14:47:21.362141 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9920 14:47:21.365210 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9921 14:47:21.372360 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9922 14:47:21.375572 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9923 14:47:21.378582 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9924 14:47:21.385156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9925 14:47:21.388530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9926 14:47:21.396073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9927 14:47:21.398599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9928 14:47:21.405360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9929 14:47:21.408240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9930 14:47:21.411741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9931 14:47:21.418250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9932 14:47:21.421616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9933 14:47:21.428050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9934 14:47:21.431352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9935 14:47:21.438041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9936 14:47:21.441286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9937 14:47:21.447874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9938 14:47:21.451061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9939 14:47:21.458093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9940 14:47:21.460901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9941 14:47:21.467563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9942 14:47:21.471363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9943 14:47:21.477532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9944 14:47:21.481190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9945 14:47:21.487720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9946 14:47:21.490687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9947 14:47:21.497283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9948 14:47:21.500988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9949 14:47:21.507820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9950 14:47:21.510710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9951 14:47:21.517134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9952 14:47:21.520574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9953 14:47:21.527160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9954 14:47:21.530513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9955 14:47:21.537004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9956 14:47:21.540126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9957 14:47:21.546832 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9958 14:47:21.547304 INFO: [APUAPC] vio 0
9959 14:47:21.554483 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9960 14:47:21.557657 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9961 14:47:21.560541 INFO: [APUAPC] D0_APC_0: 0x400510
9962 14:47:21.563853 INFO: [APUAPC] D0_APC_1: 0x0
9963 14:47:21.567335 INFO: [APUAPC] D0_APC_2: 0x1540
9964 14:47:21.570800 INFO: [APUAPC] D0_APC_3: 0x0
9965 14:47:21.573730 INFO: [APUAPC] D1_APC_0: 0xffffffff
9966 14:47:21.577204 INFO: [APUAPC] D1_APC_1: 0xffffffff
9967 14:47:21.580805 INFO: [APUAPC] D1_APC_2: 0x3fffff
9968 14:47:21.583651 INFO: [APUAPC] D1_APC_3: 0x0
9969 14:47:21.587061 INFO: [APUAPC] D2_APC_0: 0xffffffff
9970 14:47:21.590252 INFO: [APUAPC] D2_APC_1: 0xffffffff
9971 14:47:21.593485 INFO: [APUAPC] D2_APC_2: 0x3fffff
9972 14:47:21.597014 INFO: [APUAPC] D2_APC_3: 0x0
9973 14:47:21.600716 INFO: [APUAPC] D3_APC_0: 0xffffffff
9974 14:47:21.603662 INFO: [APUAPC] D3_APC_1: 0xffffffff
9975 14:47:21.606856 INFO: [APUAPC] D3_APC_2: 0x3fffff
9976 14:47:21.610473 INFO: [APUAPC] D3_APC_3: 0x0
9977 14:47:21.613316 INFO: [APUAPC] D4_APC_0: 0xffffffff
9978 14:47:21.616497 INFO: [APUAPC] D4_APC_1: 0xffffffff
9979 14:47:21.620041 INFO: [APUAPC] D4_APC_2: 0x3fffff
9980 14:47:21.623408 INFO: [APUAPC] D4_APC_3: 0x0
9981 14:47:21.626648 INFO: [APUAPC] D5_APC_0: 0xffffffff
9982 14:47:21.630143 INFO: [APUAPC] D5_APC_1: 0xffffffff
9983 14:47:21.633054 INFO: [APUAPC] D5_APC_2: 0x3fffff
9984 14:47:21.637118 INFO: [APUAPC] D5_APC_3: 0x0
9985 14:47:21.640152 INFO: [APUAPC] D6_APC_0: 0xffffffff
9986 14:47:21.643483 INFO: [APUAPC] D6_APC_1: 0xffffffff
9987 14:47:21.646612 INFO: [APUAPC] D6_APC_2: 0x3fffff
9988 14:47:21.647035 INFO: [APUAPC] D6_APC_3: 0x0
9989 14:47:21.652852 INFO: [APUAPC] D7_APC_0: 0xffffffff
9990 14:47:21.656129 INFO: [APUAPC] D7_APC_1: 0xffffffff
9991 14:47:21.660006 INFO: [APUAPC] D7_APC_2: 0x3fffff
9992 14:47:21.660429 INFO: [APUAPC] D7_APC_3: 0x0
9993 14:47:21.662925 INFO: [APUAPC] D8_APC_0: 0xffffffff
9994 14:47:21.666407 INFO: [APUAPC] D8_APC_1: 0xffffffff
9995 14:47:21.669882 INFO: [APUAPC] D8_APC_2: 0x3fffff
9996 14:47:21.672636 INFO: [APUAPC] D8_APC_3: 0x0
9997 14:47:21.676104 INFO: [APUAPC] D9_APC_0: 0xffffffff
9998 14:47:21.679806 INFO: [APUAPC] D9_APC_1: 0xffffffff
9999 14:47:21.682709 INFO: [APUAPC] D9_APC_2: 0x3fffff
10000 14:47:21.686123 INFO: [APUAPC] D9_APC_3: 0x0
10001 14:47:21.689390 INFO: [APUAPC] D10_APC_0: 0xffffffff
10002 14:47:21.692490 INFO: [APUAPC] D10_APC_1: 0xffffffff
10003 14:47:21.695846 INFO: [APUAPC] D10_APC_2: 0x3fffff
10004 14:47:21.699183 INFO: [APUAPC] D10_APC_3: 0x0
10005 14:47:21.702210 INFO: [APUAPC] D11_APC_0: 0xffffffff
10006 14:47:21.709039 INFO: [APUAPC] D11_APC_1: 0xffffffff
10007 14:47:21.712508 INFO: [APUAPC] D11_APC_2: 0x3fffff
10008 14:47:21.712931 INFO: [APUAPC] D11_APC_3: 0x0
10009 14:47:21.715649 INFO: [APUAPC] D12_APC_0: 0xffffffff
10010 14:47:21.722228 INFO: [APUAPC] D12_APC_1: 0xffffffff
10011 14:47:21.725804 INFO: [APUAPC] D12_APC_2: 0x3fffff
10012 14:47:21.726266 INFO: [APUAPC] D12_APC_3: 0x0
10013 14:47:21.728987 INFO: [APUAPC] D13_APC_0: 0xffffffff
10014 14:47:21.735951 INFO: [APUAPC] D13_APC_1: 0xffffffff
10015 14:47:21.739005 INFO: [APUAPC] D13_APC_2: 0x3fffff
10016 14:47:21.739425 INFO: [APUAPC] D13_APC_3: 0x0
10017 14:47:21.745695 INFO: [APUAPC] D14_APC_0: 0xffffffff
10018 14:47:21.748711 INFO: [APUAPC] D14_APC_1: 0xffffffff
10019 14:47:21.752086 INFO: [APUAPC] D14_APC_2: 0x3fffff
10020 14:47:21.755115 INFO: [APUAPC] D14_APC_3: 0x0
10021 14:47:21.758388 INFO: [APUAPC] D15_APC_0: 0xffffffff
10022 14:47:21.761753 INFO: [APUAPC] D15_APC_1: 0xffffffff
10023 14:47:21.765230 INFO: [APUAPC] D15_APC_2: 0x3fffff
10024 14:47:21.768458 INFO: [APUAPC] D15_APC_3: 0x0
10025 14:47:21.768916 INFO: [APUAPC] APC_CON: 0x4
10026 14:47:21.771517 INFO: [NOCDAPC] D0_APC_0: 0x0
10027 14:47:21.774978 INFO: [NOCDAPC] D0_APC_1: 0x0
10028 14:47:21.778084 INFO: [NOCDAPC] D1_APC_0: 0x0
10029 14:47:21.781844 INFO: [NOCDAPC] D1_APC_1: 0xfff
10030 14:47:21.784716 INFO: [NOCDAPC] D2_APC_0: 0x0
10031 14:47:21.788098 INFO: [NOCDAPC] D2_APC_1: 0xfff
10032 14:47:21.791923 INFO: [NOCDAPC] D3_APC_0: 0x0
10033 14:47:21.794944 INFO: [NOCDAPC] D3_APC_1: 0xfff
10034 14:47:21.798011 INFO: [NOCDAPC] D4_APC_0: 0x0
10035 14:47:21.801233 INFO: [NOCDAPC] D4_APC_1: 0xfff
10036 14:47:21.801655 INFO: [NOCDAPC] D5_APC_0: 0x0
10037 14:47:21.804609 INFO: [NOCDAPC] D5_APC_1: 0xfff
10038 14:47:21.808190 INFO: [NOCDAPC] D6_APC_0: 0x0
10039 14:47:21.811379 INFO: [NOCDAPC] D6_APC_1: 0xfff
10040 14:47:21.814588 INFO: [NOCDAPC] D7_APC_0: 0x0
10041 14:47:21.818538 INFO: [NOCDAPC] D7_APC_1: 0xfff
10042 14:47:21.821380 INFO: [NOCDAPC] D8_APC_0: 0x0
10043 14:47:21.824830 INFO: [NOCDAPC] D8_APC_1: 0xfff
10044 14:47:21.827755 INFO: [NOCDAPC] D9_APC_0: 0x0
10045 14:47:21.831209 INFO: [NOCDAPC] D9_APC_1: 0xfff
10046 14:47:21.834283 INFO: [NOCDAPC] D10_APC_0: 0x0
10047 14:47:21.837501 INFO: [NOCDAPC] D10_APC_1: 0xfff
10048 14:47:21.837922 INFO: [NOCDAPC] D11_APC_0: 0x0
10049 14:47:21.841227 INFO: [NOCDAPC] D11_APC_1: 0xfff
10050 14:47:21.844782 INFO: [NOCDAPC] D12_APC_0: 0x0
10051 14:47:21.847591 INFO: [NOCDAPC] D12_APC_1: 0xfff
10052 14:47:21.851072 INFO: [NOCDAPC] D13_APC_0: 0x0
10053 14:47:21.854376 INFO: [NOCDAPC] D13_APC_1: 0xfff
10054 14:47:21.858234 INFO: [NOCDAPC] D14_APC_0: 0x0
10055 14:47:21.860936 INFO: [NOCDAPC] D14_APC_1: 0xfff
10056 14:47:21.864407 INFO: [NOCDAPC] D15_APC_0: 0x0
10057 14:47:21.867385 INFO: [NOCDAPC] D15_APC_1: 0xfff
10058 14:47:21.870977 INFO: [NOCDAPC] APC_CON: 0x4
10059 14:47:21.874487 INFO: [APUAPC] set_apusys_apc done
10060 14:47:21.877377 INFO: [DEVAPC] devapc_init done
10061 14:47:21.880743 INFO: GICv3 without legacy support detected.
10062 14:47:21.884259 INFO: ARM GICv3 driver initialized in EL3
10063 14:47:21.887250 INFO: Maximum SPI INTID supported: 639
10064 14:47:21.893958 INFO: BL31: Initializing runtime services
10065 14:47:21.897346 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10066 14:47:21.900608 INFO: SPM: enable CPC mode
10067 14:47:21.907214 INFO: mcdi ready for mcusys-off-idle and system suspend
10068 14:47:21.910435 INFO: BL31: Preparing for EL3 exit to normal world
10069 14:47:21.914223 INFO: Entry point address = 0x80000000
10070 14:47:21.917235 INFO: SPSR = 0x8
10071 14:47:21.922410
10072 14:47:21.922827
10073 14:47:21.923159
10074 14:47:21.925558 Starting depthcharge on Spherion...
10075 14:47:21.925977
10076 14:47:21.926361 Wipe memory regions:
10077 14:47:21.926679
10078 14:47:21.928948 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10079 14:47:21.929438 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10080 14:47:21.929845 Setting prompt string to ['asurada:']
10081 14:47:21.930272 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10082 14:47:21.930944 [0x00000040000000, 0x00000054600000)
10083 14:47:22.051472
10084 14:47:22.052036 [0x00000054660000, 0x00000080000000)
10085 14:47:22.311936
10086 14:47:22.312455 [0x000000821a7280, 0x000000ffe64000)
10087 14:47:23.056572
10088 14:47:23.057082 [0x00000100000000, 0x00000240000000)
10089 14:47:24.946690
10090 14:47:24.949577 Initializing XHCI USB controller at 0x11200000.
10091 14:47:25.988815
10092 14:47:25.991872 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10093 14:47:25.991955
10094 14:47:25.992021
10095 14:47:25.992305 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10097 14:47:26.092627 asurada: tftpboot 192.168.201.1 14167048/tftp-deploy-rvk543o5/kernel/image.itb 14167048/tftp-deploy-rvk543o5/kernel/cmdline
10098 14:47:26.092814 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 14:47:26.092931 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10100 14:47:26.097154 tftpboot 192.168.201.1 14167048/tftp-deploy-rvk543o5/kernel/image.ittp-deploy-rvk543o5/kernel/cmdline
10101 14:47:26.097256
10102 14:47:26.097323 Waiting for link
10103 14:47:26.255706
10104 14:47:26.255884 R8152: Initializing
10105 14:47:26.255984
10106 14:47:26.258539 Version 6 (ocp_data = 5c30)
10107 14:47:26.258613
10108 14:47:26.261981 R8152: Done initializing
10109 14:47:26.262084
10110 14:47:26.262207 Adding net device
10111 14:47:28.168095
10112 14:47:28.168812 done.
10113 14:47:28.169352
10114 14:47:28.169884 MAC: 00:e0:4c:68:02:81
10115 14:47:28.170407
10116 14:47:28.171283 Sending DHCP discover... done.
10117 14:47:28.171769
10118 14:47:28.174585 Waiting for reply... done.
10119 14:47:28.175220
10120 14:47:28.177709 Sending DHCP request... done.
10121 14:47:28.178317
10122 14:47:28.180969 Waiting for reply... done.
10123 14:47:28.181525
10124 14:47:28.182032 My ip is 192.168.201.14
10125 14:47:28.182588
10126 14:47:28.184712 The DHCP server ip is 192.168.201.1
10127 14:47:28.185316
10128 14:47:28.190912 TFTP server IP predefined by user: 192.168.201.1
10129 14:47:28.191466
10130 14:47:28.197739 Bootfile predefined by user: 14167048/tftp-deploy-rvk543o5/kernel/image.itb
10131 14:47:28.198231
10132 14:47:28.198576 Sending tftp read request... done.
10133 14:47:28.200785
10134 14:47:28.204532 Waiting for the transfer...
10135 14:47:28.204960
10136 14:47:28.796648 00000000 ################################################################
10137 14:47:28.796789
10138 14:47:29.372144 00080000 ################################################################
10139 14:47:29.372286
10140 14:47:29.941685 00100000 ################################################################
10141 14:47:29.941834
10142 14:47:30.501833 00180000 ################################################################
10143 14:47:30.501974
10144 14:47:31.074575 00200000 ################################################################
10145 14:47:31.074716
10146 14:47:31.649832 00280000 ################################################################
10147 14:47:31.650010
10148 14:47:32.207724 00300000 ################################################################
10149 14:47:32.207871
10150 14:47:32.780705 00380000 ################################################################
10151 14:47:32.780856
10152 14:47:33.349882 00400000 ################################################################
10153 14:47:33.350027
10154 14:47:33.920158 00480000 ################################################################
10155 14:47:33.920309
10156 14:47:34.485299 00500000 ################################################################
10157 14:47:34.485446
10158 14:47:35.040905 00580000 ################################################################
10159 14:47:35.041054
10160 14:47:35.592939 00600000 ################################################################
10161 14:47:35.593084
10162 14:47:36.140070 00680000 ################################################################
10163 14:47:36.140200
10164 14:47:36.693866 00700000 ################################################################
10165 14:47:36.694013
10166 14:47:37.254386 00780000 ################################################################
10167 14:47:37.254539
10168 14:47:37.813010 00800000 ################################################################
10169 14:47:37.813165
10170 14:47:38.363072 00880000 ################################################################
10171 14:47:38.363220
10172 14:47:38.916611 00900000 ################################################################
10173 14:47:38.916761
10174 14:47:39.471509 00980000 ################################################################
10175 14:47:39.471658
10176 14:47:40.051292 00a00000 ################################################################
10177 14:47:40.051442
10178 14:47:40.643129 00a80000 ################################################################
10179 14:47:40.643282
10180 14:47:41.235237 00b00000 ################################################################
10181 14:47:41.235401
10182 14:47:41.823684 00b80000 ################################################################
10183 14:47:41.823853
10184 14:47:42.408451 00c00000 ################################################################
10185 14:47:42.408611
10186 14:47:43.002572 00c80000 ################################################################
10187 14:47:43.002733
10188 14:47:43.591911 00d00000 ################################################################
10189 14:47:43.592070
10190 14:47:44.177269 00d80000 ################################################################
10191 14:47:44.177426
10192 14:47:44.762029 00e00000 ################################################################
10193 14:47:44.762242
10194 14:47:45.362414 00e80000 ################################################################
10195 14:47:45.362615
10196 14:47:45.949696 00f00000 ################################################################
10197 14:47:45.949859
10198 14:47:46.530911 00f80000 ################################################################
10199 14:47:46.531061
10200 14:47:47.137219 01000000 ################################################################
10201 14:47:47.137365
10202 14:47:47.739218 01080000 ################################################################
10203 14:47:47.739362
10204 14:47:48.440139 01100000 ################################################################
10205 14:47:48.440650
10206 14:47:49.151680 01180000 ################################################################
10207 14:47:49.152235
10208 14:47:49.851985 01200000 ################################################################
10209 14:47:49.852594
10210 14:47:50.569090 01280000 ################################################################
10211 14:47:50.569612
10212 14:47:51.288173 01300000 ################################################################
10213 14:47:51.288689
10214 14:47:51.984632 01380000 ################################################################
10215 14:47:51.985135
10216 14:47:52.688574 01400000 ################################################################
10217 14:47:52.689106
10218 14:47:53.383624 01480000 ################################################################
10219 14:47:53.384141
10220 14:47:54.079539 01500000 ################################################################
10221 14:47:54.080234
10222 14:47:54.788456 01580000 ################################################################
10223 14:47:54.789047
10224 14:47:55.506194 01600000 ################################################################
10225 14:47:55.506730
10226 14:47:56.181954 01680000 ################################################################
10227 14:47:56.182524
10228 14:47:56.880104 01700000 ################################################################
10229 14:47:56.880691
10230 14:47:57.586182 01780000 ################################################################
10231 14:47:57.586742
10232 14:47:58.279025 01800000 ################################################################
10233 14:47:58.279617
10234 14:47:58.976208 01880000 ################################################################
10235 14:47:58.976717
10236 14:47:59.683389 01900000 ################################################################
10237 14:47:59.683928
10238 14:48:00.392120 01980000 ################################################################
10239 14:48:00.392968
10240 14:48:00.992661 01a00000 ################################################################
10241 14:48:00.992817
10242 14:48:01.678560 01a80000 ################################################################
10243 14:48:01.679072
10244 14:48:02.292626 01b00000 ################################################################
10245 14:48:02.292760
10246 14:48:02.833510 01b80000 ################################################################
10247 14:48:02.833654
10248 14:48:03.362066 01c00000 ################################################################
10249 14:48:03.362274
10250 14:48:03.898169 01c80000 ################################################################
10251 14:48:03.898314
10252 14:48:04.431966 01d00000 ################################################################
10253 14:48:04.432112
10254 14:48:04.989482 01d80000 ################################################################
10255 14:48:04.989625
10256 14:48:05.528740 01e00000 ################################################################
10257 14:48:05.528886
10258 14:48:06.087412 01e80000 ################################################################
10259 14:48:06.087547
10260 14:48:06.635644 01f00000 ################################################################
10261 14:48:06.635795
10262 14:48:07.185041 01f80000 ################################################################
10263 14:48:07.185206
10264 14:48:07.720137 02000000 ################################################################
10265 14:48:07.720311
10266 14:48:08.247895 02080000 ################################################################
10267 14:48:08.248032
10268 14:48:08.783883 02100000 ################################################################
10269 14:48:08.784070
10270 14:48:09.314569 02180000 ################################################################
10271 14:48:09.314755
10272 14:48:09.848151 02200000 ################################################################
10273 14:48:09.848338
10274 14:48:10.419604 02280000 ################################################################
10275 14:48:10.419753
10276 14:48:11.022724 02300000 ################################################################
10277 14:48:11.022875
10278 14:48:11.597448 02380000 ################################################################
10279 14:48:11.597657
10280 14:48:12.163119 02400000 ################################################################
10281 14:48:12.163270
10282 14:48:12.736350 02480000 ################################################################
10283 14:48:12.736486
10284 14:48:13.301025 02500000 ################################################################
10285 14:48:13.301195
10286 14:48:13.870926 02580000 ################################################################
10287 14:48:13.871061
10288 14:48:14.456149 02600000 ################################################################
10289 14:48:14.456281
10290 14:48:15.036715 02680000 ################################################################
10291 14:48:15.036872
10292 14:48:15.625448 02700000 ################################################################
10293 14:48:15.625581
10294 14:48:16.219970 02780000 ################################################################
10295 14:48:16.220112
10296 14:48:16.812583 02800000 ################################################################
10297 14:48:16.812756
10298 14:48:17.396454 02880000 ################################################################
10299 14:48:17.396643
10300 14:48:17.990356 02900000 ################################################################
10301 14:48:17.990509
10302 14:48:18.579337 02980000 ################################################################
10303 14:48:18.579527
10304 14:48:19.170816 02a00000 ################################################################
10305 14:48:19.171003
10306 14:48:19.759984 02a80000 ################################################################
10307 14:48:19.760171
10308 14:48:20.327764 02b00000 ################################################################
10309 14:48:20.327950
10310 14:48:20.890064 02b80000 ################################################################
10311 14:48:20.890277
10312 14:48:21.440856 02c00000 ################################################################
10313 14:48:21.440987
10314 14:48:22.000845 02c80000 ################################################################
10315 14:48:22.000997
10316 14:48:22.573056 02d00000 ################################################################
10317 14:48:22.573183
10318 14:48:23.138718 02d80000 ################################################################
10319 14:48:23.138863
10320 14:48:23.709782 02e00000 ################################################################
10321 14:48:23.709995
10322 14:48:24.278541 02e80000 ################################################################
10323 14:48:24.278690
10324 14:48:24.824228 02f00000 ################################################################
10325 14:48:24.824370
10326 14:48:25.373548 02f80000 ################################################################
10327 14:48:25.373705
10328 14:48:25.926540 03000000 ################################################################
10329 14:48:25.926691
10330 14:48:26.494376 03080000 ################################################################
10331 14:48:26.494545
10332 14:48:27.041169 03100000 ################################################################
10333 14:48:27.041322
10334 14:48:27.590214 03180000 ################################################################
10335 14:48:27.590370
10336 14:48:28.143409 03200000 ################################################################
10337 14:48:28.143561
10338 14:48:28.699486 03280000 ################################################################
10339 14:48:28.699640
10340 14:48:29.266191 03300000 ################################################################
10341 14:48:29.266341
10342 14:48:29.840676 03380000 ################################################################
10343 14:48:29.840817
10344 14:48:30.409847 03400000 ################################################################
10345 14:48:30.410028
10346 14:48:30.990062 03480000 ################################################################
10347 14:48:30.990258
10348 14:48:31.561614 03500000 ################################################################
10349 14:48:31.561772
10350 14:48:32.139973 03580000 ################################################################
10351 14:48:32.140125
10352 14:48:32.719465 03600000 ################################################################
10353 14:48:32.719623
10354 14:48:33.321724 03680000 ################################################################
10355 14:48:33.321877
10356 14:48:33.917562 03700000 ################################################################
10357 14:48:33.917709
10358 14:48:34.518083 03780000 ################################################################
10359 14:48:34.518286
10360 14:48:35.109554 03800000 ################################################################
10361 14:48:35.109706
10362 14:48:35.675318 03880000 ################################################################
10363 14:48:35.675467
10364 14:48:36.238137 03900000 ################################################################
10365 14:48:36.238365
10366 14:48:36.818854 03980000 ################################################################
10367 14:48:36.819010
10368 14:48:37.409591 03a00000 ################################################################
10369 14:48:37.409743
10370 14:48:37.987959 03a80000 ################################################################
10371 14:48:37.988114
10372 14:48:38.577735 03b00000 ################################################################
10373 14:48:38.577895
10374 14:48:39.158147 03b80000 ################################################################
10375 14:48:39.158380
10376 14:48:39.749347 03c00000 ################################################################
10377 14:48:39.749502
10378 14:48:40.323924 03c80000 ################################################################
10379 14:48:40.324085
10380 14:48:40.910222 03d00000 ################################################################
10381 14:48:40.910371
10382 14:48:41.485450 03d80000 ################################################################
10383 14:48:41.485604
10384 14:48:41.743494 03e00000 ############################# done.
10385 14:48:41.743642
10386 14:48:41.746328 The bootfile was 65243006 bytes long.
10387 14:48:41.746413
10388 14:48:41.749613 Sending tftp read request... done.
10389 14:48:41.749701
10390 14:48:41.752822 Waiting for the transfer...
10391 14:48:41.752907
10392 14:48:41.752971 00000000 # done.
10393 14:48:41.756346
10394 14:48:41.762990 Command line loaded dynamically from TFTP file: 14167048/tftp-deploy-rvk543o5/kernel/cmdline
10395 14:48:41.763087
10396 14:48:41.776267 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10397 14:48:41.776388
10398 14:48:41.776455 Loading FIT.
10399 14:48:41.776515
10400 14:48:41.779248 Image ramdisk-1 has 52133096 bytes.
10401 14:48:41.779332
10402 14:48:41.782994 Image fdt-1 has 47258 bytes.
10403 14:48:41.783097
10404 14:48:41.786430 Image kernel-1 has 13060619 bytes.
10405 14:48:41.786516
10406 14:48:41.795517 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10407 14:48:41.795612
10408 14:48:41.812291 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10409 14:48:41.812428
10410 14:48:41.819520 Choosing best match conf-1 for compat google,spherion-rev2.
10411 14:48:41.819701
10412 14:48:41.826371 Connected to device vid:did:rid of 1ae0:0028:00
10413 14:48:41.833432
10414 14:48:41.836453 tpm_get_response: command 0x17b, return code 0x0
10415 14:48:41.836549
10416 14:48:41.839979 ec_init: CrosEC protocol v3 supported (256, 248)
10417 14:48:41.844029
10418 14:48:41.847347 tpm_cleanup: add release locality here.
10419 14:48:41.847434
10420 14:48:41.847500 Shutting down all USB controllers.
10421 14:48:41.850597
10422 14:48:41.850679 Removing current net device
10423 14:48:41.850745
10424 14:48:41.857712 Exiting depthcharge with code 4 at timestamp: 109383520
10425 14:48:41.857804
10426 14:48:41.861259 LZMA decompressing kernel-1 to 0x821a6718
10427 14:48:41.861345
10428 14:48:41.863857 LZMA decompressing kernel-1 to 0x40000000
10429 14:48:43.475583
10430 14:48:43.475736 jumping to kernel
10431 14:48:43.476260 end: 2.2.4 bootloader-commands (duration 00:01:22) [common]
10432 14:48:43.476356 start: 2.2.5 auto-login-action (timeout 00:03:05) [common]
10433 14:48:43.476431 Setting prompt string to ['Linux version [0-9]']
10434 14:48:43.476499 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10435 14:48:43.476565 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10436 14:48:43.557927
10437 14:48:43.561371 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10438 14:48:43.564609 start: 2.2.5.1 login-action (timeout 00:03:05) [common]
10439 14:48:43.564729 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10440 14:48:43.564829 Setting prompt string to []
10441 14:48:43.564937 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10442 14:48:43.565041 Using line separator: #'\n'#
10443 14:48:43.565128 No login prompt set.
10444 14:48:43.565203 Parsing kernel messages
10445 14:48:43.565274 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10446 14:48:43.565377 [login-action] Waiting for messages, (timeout 00:03:05)
10447 14:48:43.565442 Waiting using forced prompt support (timeout 00:01:33)
10448 14:48:43.584163 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10449 14:48:43.587252 [ 0.000000] random: crng init done
10450 14:48:43.593841 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10451 14:48:43.597135 [ 0.000000] efi: UEFI not found.
10452 14:48:43.603969 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10453 14:48:43.613572 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10454 14:48:43.623504 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10455 14:48:43.630015 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10456 14:48:43.636342 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10457 14:48:43.642912 [ 0.000000] printk: bootconsole [mtk8250] enabled
10458 14:48:43.649568 [ 0.000000] NUMA: No NUMA configuration found
10459 14:48:43.656478 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10460 14:48:43.663252 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10461 14:48:43.663355 [ 0.000000] Zone ranges:
10462 14:48:43.669943 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10463 14:48:43.672966 [ 0.000000] DMA32 empty
10464 14:48:43.679737 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10465 14:48:43.682761 [ 0.000000] Movable zone start for each node
10466 14:48:43.686327 [ 0.000000] Early memory node ranges
10467 14:48:43.692869 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10468 14:48:43.699282 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10469 14:48:43.705906 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10470 14:48:43.712872 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10471 14:48:43.719223 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10472 14:48:43.726060 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10473 14:48:43.782879 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10474 14:48:43.788862 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10475 14:48:43.795629 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10476 14:48:43.799050 [ 0.000000] psci: probing for conduit method from DT.
10477 14:48:43.805626 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10478 14:48:43.808898 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10479 14:48:43.815506 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10480 14:48:43.818995 [ 0.000000] psci: SMC Calling Convention v1.2
10481 14:48:43.825290 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10482 14:48:43.828415 [ 0.000000] Detected VIPT I-cache on CPU0
10483 14:48:43.835473 [ 0.000000] CPU features: detected: GIC system register CPU interface
10484 14:48:43.841948 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10485 14:48:43.848524 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10486 14:48:43.854895 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10487 14:48:43.864776 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10488 14:48:43.871838 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10489 14:48:43.874768 [ 0.000000] alternatives: applying boot alternatives
10490 14:48:43.881247 [ 0.000000] Fallback order for Node 0: 0
10491 14:48:43.888125 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10492 14:48:43.891605 [ 0.000000] Policy zone: Normal
10493 14:48:43.904860 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10494 14:48:43.914695 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10495 14:48:43.927054 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10496 14:48:43.936925 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10497 14:48:43.943829 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10498 14:48:43.947211 <6>[ 0.000000] software IO TLB: area num 8.
10499 14:48:44.003280 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10500 14:48:44.152791 <6>[ 0.000000] Memory: 7913272K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 439496K reserved, 32768K cma-reserved)
10501 14:48:44.159576 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10502 14:48:44.166139 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10503 14:48:44.169128 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10504 14:48:44.175856 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10505 14:48:44.182123 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10506 14:48:44.185745 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10507 14:48:44.195627 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10508 14:48:44.202655 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10509 14:48:44.208771 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10510 14:48:44.215184 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10511 14:48:44.218207 <6>[ 0.000000] GICv3: 608 SPIs implemented
10512 14:48:44.221850 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10513 14:48:44.228346 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10514 14:48:44.231756 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10515 14:48:44.238710 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10516 14:48:44.251513 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10517 14:48:44.264699 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10518 14:48:44.271041 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10519 14:48:44.279253 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10520 14:48:44.292334 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10521 14:48:44.299019 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10522 14:48:44.306153 <6>[ 0.009208] Console: colour dummy device 80x25
10523 14:48:44.315757 <6>[ 0.013938] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10524 14:48:44.322328 <6>[ 0.024445] pid_max: default: 32768 minimum: 301
10525 14:48:44.325732 <6>[ 0.029317] LSM: Security Framework initializing
10526 14:48:44.332305 <6>[ 0.034246] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10527 14:48:44.342390 <6>[ 0.042059] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10528 14:48:44.351887 <6>[ 0.051459] cblist_init_generic: Setting adjustable number of callback queues.
10529 14:48:44.358447 <6>[ 0.058902] cblist_init_generic: Setting shift to 3 and lim to 1.
10530 14:48:44.364994 <6>[ 0.065241] cblist_init_generic: Setting adjustable number of callback queues.
10531 14:48:44.371442 <6>[ 0.072668] cblist_init_generic: Setting shift to 3 and lim to 1.
10532 14:48:44.374930 <6>[ 0.079068] rcu: Hierarchical SRCU implementation.
10533 14:48:44.381787 <6>[ 0.084114] rcu: Max phase no-delay instances is 1000.
10534 14:48:44.388045 <6>[ 0.091171] EFI services will not be available.
10535 14:48:44.391777 <6>[ 0.096123] smp: Bringing up secondary CPUs ...
10536 14:48:44.399869 <6>[ 0.101151] Detected VIPT I-cache on CPU1
10537 14:48:44.406509 <6>[ 0.101209] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10538 14:48:44.413303 <6>[ 0.101234] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10539 14:48:44.416759 <6>[ 0.101547] Detected VIPT I-cache on CPU2
10540 14:48:44.426634 <6>[ 0.101600] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10541 14:48:44.433345 <6>[ 0.101616] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10542 14:48:44.436243 <6>[ 0.101875] Detected VIPT I-cache on CPU3
10543 14:48:44.442752 <6>[ 0.101921] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10544 14:48:44.450001 <6>[ 0.101934] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10545 14:48:44.452791 <6>[ 0.102238] CPU features: detected: Spectre-v4
10546 14:48:44.459428 <6>[ 0.102245] CPU features: detected: Spectre-BHB
10547 14:48:44.462944 <6>[ 0.102250] Detected PIPT I-cache on CPU4
10548 14:48:44.469669 <6>[ 0.102307] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10549 14:48:44.476092 <6>[ 0.102323] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10550 14:48:44.482281 <6>[ 0.102619] Detected PIPT I-cache on CPU5
10551 14:48:44.489483 <6>[ 0.102680] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10552 14:48:44.495629 <6>[ 0.102696] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10553 14:48:44.498948 <6>[ 0.102975] Detected PIPT I-cache on CPU6
10554 14:48:44.505709 <6>[ 0.103039] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10555 14:48:44.515249 <6>[ 0.103055] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10556 14:48:44.519261 <6>[ 0.103352] Detected PIPT I-cache on CPU7
10557 14:48:44.525343 <6>[ 0.103417] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10558 14:48:44.532108 <6>[ 0.103433] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10559 14:48:44.535338 <6>[ 0.103480] smp: Brought up 1 node, 8 CPUs
10560 14:48:44.541994 <6>[ 0.244698] SMP: Total of 8 processors activated.
10561 14:48:44.545116 <6>[ 0.249619] CPU features: detected: 32-bit EL0 Support
10562 14:48:44.555015 <6>[ 0.255016] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10563 14:48:44.561481 <6>[ 0.263816] CPU features: detected: Common not Private translations
10564 14:48:44.568403 <6>[ 0.270293] CPU features: detected: CRC32 instructions
10565 14:48:44.574874 <6>[ 0.275677] CPU features: detected: RCpc load-acquire (LDAPR)
10566 14:48:44.577882 <6>[ 0.281637] CPU features: detected: LSE atomic instructions
10567 14:48:44.584405 <6>[ 0.287454] CPU features: detected: Privileged Access Never
10568 14:48:44.591393 <6>[ 0.293237] CPU features: detected: RAS Extension Support
10569 14:48:44.597916 <6>[ 0.298846] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10570 14:48:44.601191 <6>[ 0.306065] CPU: All CPU(s) started at EL2
10571 14:48:44.607793 <6>[ 0.310381] alternatives: applying system-wide alternatives
10572 14:48:44.617519 <6>[ 0.321182] devtmpfs: initialized
10573 14:48:44.633290 <6>[ 0.330029] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10574 14:48:44.639950 <6>[ 0.339986] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10575 14:48:44.646122 <6>[ 0.348001] pinctrl core: initialized pinctrl subsystem
10576 14:48:44.649808 <6>[ 0.354674] DMI not present or invalid.
10577 14:48:44.656247 <6>[ 0.359087] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10578 14:48:44.665924 <6>[ 0.365940] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10579 14:48:44.672767 <6>[ 0.373520] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10580 14:48:44.682263 <6>[ 0.381738] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10581 14:48:44.685621 <6>[ 0.389980] audit: initializing netlink subsys (disabled)
10582 14:48:44.695467 <5>[ 0.395676] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10583 14:48:44.702188 <6>[ 0.396392] thermal_sys: Registered thermal governor 'step_wise'
10584 14:48:44.708974 <6>[ 0.403645] thermal_sys: Registered thermal governor 'power_allocator'
10585 14:48:44.711820 <6>[ 0.409900] cpuidle: using governor menu
10586 14:48:44.718409 <6>[ 0.420862] NET: Registered PF_QIPCRTR protocol family
10587 14:48:44.725275 <6>[ 0.426335] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10588 14:48:44.732003 <6>[ 0.433439] ASID allocator initialised with 32768 entries
10589 14:48:44.734951 <6>[ 0.440025] Serial: AMBA PL011 UART driver
10590 14:48:44.745591 <4>[ 0.448789] Trying to register duplicate clock ID: 134
10591 14:48:44.803809 <6>[ 0.510341] KASLR enabled
10592 14:48:44.818042 <6>[ 0.518195] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10593 14:48:44.824529 <6>[ 0.525209] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10594 14:48:44.831330 <6>[ 0.531700] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10595 14:48:44.837934 <6>[ 0.538705] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10596 14:48:44.844120 <6>[ 0.545191] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10597 14:48:44.851274 <6>[ 0.552196] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10598 14:48:44.857515 <6>[ 0.558682] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10599 14:48:44.864291 <6>[ 0.565689] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10600 14:48:44.867355 <6>[ 0.573205] ACPI: Interpreter disabled.
10601 14:48:44.876226 <6>[ 0.579632] iommu: Default domain type: Translated
10602 14:48:44.882572 <6>[ 0.584745] iommu: DMA domain TLB invalidation policy: strict mode
10603 14:48:44.886105 <5>[ 0.591399] SCSI subsystem initialized
10604 14:48:44.892768 <6>[ 0.595566] usbcore: registered new interface driver usbfs
10605 14:48:44.899266 <6>[ 0.601296] usbcore: registered new interface driver hub
10606 14:48:44.902615 <6>[ 0.606849] usbcore: registered new device driver usb
10607 14:48:44.909603 <6>[ 0.612944] pps_core: LinuxPPS API ver. 1 registered
10608 14:48:44.919254 <6>[ 0.618138] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10609 14:48:44.922635 <6>[ 0.627486] PTP clock support registered
10610 14:48:44.926024 <6>[ 0.631726] EDAC MC: Ver: 3.0.0
10611 14:48:44.933669 <6>[ 0.636871] FPGA manager framework
10612 14:48:44.940158 <6>[ 0.640558] Advanced Linux Sound Architecture Driver Initialized.
10613 14:48:44.943370 <6>[ 0.647331] vgaarb: loaded
10614 14:48:44.949958 <6>[ 0.650494] clocksource: Switched to clocksource arch_sys_counter
10615 14:48:44.953099 <5>[ 0.656938] VFS: Disk quotas dquot_6.6.0
10616 14:48:44.959710 <6>[ 0.661127] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10617 14:48:44.963212 <6>[ 0.668315] pnp: PnP ACPI: disabled
10618 14:48:44.971374 <6>[ 0.675004] NET: Registered PF_INET protocol family
10619 14:48:44.981534 <6>[ 0.680612] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10620 14:48:44.992855 <6>[ 0.692946] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10621 14:48:45.002672 <6>[ 0.701759] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10622 14:48:45.009056 <6>[ 0.709732] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10623 14:48:45.016148 <6>[ 0.718433] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10624 14:48:45.027972 <6>[ 0.728187] TCP: Hash tables configured (established 65536 bind 65536)
10625 14:48:45.034620 <6>[ 0.735056] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10626 14:48:45.041449 <6>[ 0.742253] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10627 14:48:45.047849 <6>[ 0.749958] NET: Registered PF_UNIX/PF_LOCAL protocol family
10628 14:48:45.054434 <6>[ 0.756040] RPC: Registered named UNIX socket transport module.
10629 14:48:45.057718 <6>[ 0.762186] RPC: Registered udp transport module.
10630 14:48:45.064327 <6>[ 0.767118] RPC: Registered tcp transport module.
10631 14:48:45.071132 <6>[ 0.772051] RPC: Registered tcp NFSv4.1 backchannel transport module.
10632 14:48:45.074337 <6>[ 0.778716] PCI: CLS 0 bytes, default 64
10633 14:48:45.077547 <6>[ 0.783063] Unpacking initramfs...
10634 14:48:45.102502 <6>[ 0.802607] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10635 14:48:45.112375 <6>[ 0.811258] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10636 14:48:45.115861 <6>[ 0.820092] kvm [1]: IPA Size Limit: 40 bits
10637 14:48:45.121991 <6>[ 0.824621] kvm [1]: GICv3: no GICV resource entry
10638 14:48:45.125592 <6>[ 0.829639] kvm [1]: disabling GICv2 emulation
10639 14:48:45.132305 <6>[ 0.834325] kvm [1]: GIC system register CPU interface enabled
10640 14:48:45.136329 <6>[ 0.840491] kvm [1]: vgic interrupt IRQ18
10641 14:48:45.142396 <6>[ 0.844846] kvm [1]: VHE mode initialized successfully
10642 14:48:45.149027 <5>[ 0.851402] Initialise system trusted keyrings
10643 14:48:45.155442 <6>[ 0.856266] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10644 14:48:45.162721 <6>[ 0.866252] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10645 14:48:45.169996 <5>[ 0.872621] NFS: Registering the id_resolver key type
10646 14:48:45.173424 <5>[ 0.877920] Key type id_resolver registered
10647 14:48:45.179470 <5>[ 0.882331] Key type id_legacy registered
10648 14:48:45.186025 <6>[ 0.886608] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10649 14:48:45.192708 <6>[ 0.893532] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10650 14:48:45.198909 <6>[ 0.901259] 9p: Installing v9fs 9p2000 file system support
10651 14:48:45.235766 <5>[ 0.939243] Key type asymmetric registered
10652 14:48:45.239088 <5>[ 0.943575] Asymmetric key parser 'x509' registered
10653 14:48:45.249009 <6>[ 0.948714] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10654 14:48:45.251958 <6>[ 0.956331] io scheduler mq-deadline registered
10655 14:48:45.255142 <6>[ 0.961090] io scheduler kyber registered
10656 14:48:45.274592 <6>[ 0.978198] EINJ: ACPI disabled.
10657 14:48:45.307303 <4>[ 1.004237] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10658 14:48:45.317441 <4>[ 1.014889] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10659 14:48:45.332001 <6>[ 1.035720] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10660 14:48:45.340475 <6>[ 1.043827] printk: console [ttyS0] disabled
10661 14:48:45.367961 <6>[ 1.068454] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10662 14:48:45.375017 <6>[ 1.077930] printk: console [ttyS0] enabled
10663 14:48:45.377911 <6>[ 1.077930] printk: console [ttyS0] enabled
10664 14:48:45.384988 <6>[ 1.086825] printk: bootconsole [mtk8250] disabled
10665 14:48:45.387851 <6>[ 1.086825] printk: bootconsole [mtk8250] disabled
10666 14:48:45.394285 <6>[ 1.098073] SuperH (H)SCI(F) driver initialized
10667 14:48:45.397796 <6>[ 1.103341] msm_serial: driver initialized
10668 14:48:45.412565 <6>[ 1.112253] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10669 14:48:45.422189 <6>[ 1.120801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10670 14:48:45.429139 <6>[ 1.129344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10671 14:48:45.438645 <6>[ 1.137973] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10672 14:48:45.448598 <6>[ 1.146681] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10673 14:48:45.454722 <6>[ 1.155397] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10674 14:48:45.464390 <6>[ 1.163946] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10675 14:48:45.471344 <6>[ 1.172750] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10676 14:48:45.480913 <6>[ 1.181293] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10677 14:48:45.493156 <6>[ 1.196946] loop: module loaded
10678 14:48:45.500183 <6>[ 1.203001] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10679 14:48:45.522599 <4>[ 1.226384] mtk-pmic-keys: Failed to locate of_node [id: -1]
10680 14:48:45.529609 <6>[ 1.233306] megasas: 07.719.03.00-rc1
10681 14:48:45.539069 <6>[ 1.242892] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10682 14:48:45.546287 <6>[ 1.249863] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10683 14:48:45.562916 <6>[ 1.266206] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10684 14:48:45.622058 <6>[ 1.318753] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10685 14:48:47.301869 <6>[ 3.005080] Freeing initrd memory: 50908K
10686 14:48:47.313528 <6>[ 3.016879] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10687 14:48:47.324539 <6>[ 3.027823] tun: Universal TUN/TAP device driver, 1.6
10688 14:48:47.327839 <6>[ 3.033869] thunder_xcv, ver 1.0
10689 14:48:47.331309 <6>[ 3.037375] thunder_bgx, ver 1.0
10690 14:48:47.334489 <6>[ 3.040869] nicpf, ver 1.0
10691 14:48:47.345164 <6>[ 3.044885] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10692 14:48:47.348175 <6>[ 3.052361] hns3: Copyright (c) 2017 Huawei Corporation.
10693 14:48:47.355141 <6>[ 3.057949] hclge is initializing
10694 14:48:47.357888 <6>[ 3.061528] e1000: Intel(R) PRO/1000 Network Driver
10695 14:48:47.364613 <6>[ 3.066657] e1000: Copyright (c) 1999-2006 Intel Corporation.
10696 14:48:47.368131 <6>[ 3.072670] e1000e: Intel(R) PRO/1000 Network Driver
10697 14:48:47.374996 <6>[ 3.077885] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10698 14:48:47.380933 <6>[ 3.084068] igb: Intel(R) Gigabit Ethernet Network Driver
10699 14:48:47.387599 <6>[ 3.089718] igb: Copyright (c) 2007-2014 Intel Corporation.
10700 14:48:47.394196 <6>[ 3.095556] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10701 14:48:47.401289 <6>[ 3.102074] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10702 14:48:47.404398 <6>[ 3.108529] sky2: driver version 1.30
10703 14:48:47.411265 <6>[ 3.113445] usbcore: registered new device driver r8152-cfgselector
10704 14:48:47.417232 <6>[ 3.119980] usbcore: registered new interface driver r8152
10705 14:48:47.424557 <6>[ 3.125796] VFIO - User Level meta-driver version: 0.3
10706 14:48:47.430834 <6>[ 3.133984] usbcore: registered new interface driver usb-storage
10707 14:48:47.437324 <6>[ 3.140430] usbcore: registered new device driver onboard-usb-hub
10708 14:48:47.445935 <6>[ 3.149531] mt6397-rtc mt6359-rtc: registered as rtc0
10709 14:48:47.455906 <6>[ 3.154993] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:48:47 UTC (1717512527)
10710 14:48:47.459115 <6>[ 3.164549] i2c_dev: i2c /dev entries driver
10711 14:48:47.476766 <6>[ 3.176256] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10712 14:48:47.482760 <4>[ 3.184972] cpu cpu0: supply cpu not found, using dummy regulator
10713 14:48:47.489749 <4>[ 3.191398] cpu cpu1: supply cpu not found, using dummy regulator
10714 14:48:47.496395 <4>[ 3.197806] cpu cpu2: supply cpu not found, using dummy regulator
10715 14:48:47.502984 <4>[ 3.204209] cpu cpu3: supply cpu not found, using dummy regulator
10716 14:48:47.509272 <4>[ 3.210623] cpu cpu4: supply cpu not found, using dummy regulator
10717 14:48:47.515796 <4>[ 3.217019] cpu cpu5: supply cpu not found, using dummy regulator
10718 14:48:47.522576 <4>[ 3.223415] cpu cpu6: supply cpu not found, using dummy regulator
10719 14:48:47.528844 <4>[ 3.229813] cpu cpu7: supply cpu not found, using dummy regulator
10720 14:48:47.547753 <6>[ 3.251460] cpu cpu0: EM: created perf domain
10721 14:48:47.551491 <6>[ 3.256399] cpu cpu4: EM: created perf domain
10722 14:48:47.558835 <6>[ 3.261987] sdhci: Secure Digital Host Controller Interface driver
10723 14:48:47.565943 <6>[ 3.268420] sdhci: Copyright(c) Pierre Ossman
10724 14:48:47.571658 <6>[ 3.273377] Synopsys Designware Multimedia Card Interface Driver
10725 14:48:47.578751 <6>[ 3.280023] sdhci-pltfm: SDHCI platform and OF driver helper
10726 14:48:47.581754 <6>[ 3.280067] mmc0: CQHCI version 5.10
10727 14:48:47.588476 <6>[ 3.290104] ledtrig-cpu: registered to indicate activity on CPUs
10728 14:48:47.595277 <6>[ 3.297109] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10729 14:48:47.601358 <6>[ 3.304156] usbcore: registered new interface driver usbhid
10730 14:48:47.604833 <6>[ 3.309977] usbhid: USB HID core driver
10731 14:48:47.611395 <6>[ 3.314182] spi_master spi0: will run message pump with realtime priority
10732 14:48:47.661630 <6>[ 3.358044] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10733 14:48:47.681174 <6>[ 3.374191] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10734 14:48:47.684520 <6>[ 3.387823] mmc0: Command Queue Engine enabled
10735 14:48:47.691761 <6>[ 3.389142] cros-ec-spi spi0.0: Chrome EC device registered
10736 14:48:47.697992 <6>[ 3.392572] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10737 14:48:47.701233 <6>[ 3.405597] mmcblk0: mmc0:0001 DA4128 116 GiB
10738 14:48:47.711125 <6>[ 3.411049] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10739 14:48:47.718257 <6>[ 3.421422] NET: Registered PF_PACKET protocol family
10740 14:48:47.724669 <6>[ 3.422022] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10741 14:48:47.727984 <6>[ 3.426838] 9pnet: Installing 9P2000 support
10742 14:48:47.734636 <6>[ 3.434090] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10743 14:48:47.737962 <5>[ 3.437214] Key type dns_resolver registered
10744 14:48:47.744199 <6>[ 3.443015] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10745 14:48:47.747610 <6>[ 3.447460] registered taskstats version 1
10746 14:48:47.754339 <6>[ 3.452774] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10747 14:48:47.760991 <5>[ 3.456517] Loading compiled-in X.509 certificates
10748 14:48:47.792485 <4>[ 3.489517] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10749 14:48:47.803130 <4>[ 3.500225] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10750 14:48:47.816997 <6>[ 3.520565] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10751 14:48:47.824020 <6>[ 3.527389] xhci-mtk 11200000.usb: xHCI Host Controller
10752 14:48:47.833297 <6>[ 3.532894] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10753 14:48:47.840550 <6>[ 3.540756] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10754 14:48:47.846698 <6>[ 3.550184] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10755 14:48:47.853113 <6>[ 3.556385] xhci-mtk 11200000.usb: xHCI Host Controller
10756 14:48:47.860181 <6>[ 3.561890] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10757 14:48:47.869778 <6>[ 3.569551] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10758 14:48:47.873372 <6>[ 3.577397] hub 1-0:1.0: USB hub found
10759 14:48:47.876125 <6>[ 3.581420] hub 1-0:1.0: 1 port detected
10760 14:48:47.886280 <6>[ 3.585719] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10761 14:48:47.889767 <6>[ 3.594463] hub 2-0:1.0: USB hub found
10762 14:48:47.893750 <6>[ 3.598488] hub 2-0:1.0: 1 port detected
10763 14:48:47.903366 <6>[ 3.606593] mtk-msdc 11f70000.mmc: Got CD GPIO
10764 14:48:47.915456 <6>[ 3.615776] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10765 14:48:47.922546 <6>[ 3.623816] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10766 14:48:47.932120 <4>[ 3.631731] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10767 14:48:47.942487 <6>[ 3.641271] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10768 14:48:47.948577 <6>[ 3.649348] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10769 14:48:47.955955 <6>[ 3.657368] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10770 14:48:47.965448 <6>[ 3.665292] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10771 14:48:47.972091 <6>[ 3.673114] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10772 14:48:47.982377 <6>[ 3.680931] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10773 14:48:47.991565 <6>[ 3.691382] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10774 14:48:47.998521 <6>[ 3.699750] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10775 14:48:48.008368 <6>[ 3.708096] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10776 14:48:48.014980 <6>[ 3.716433] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10777 14:48:48.024918 <6>[ 3.724771] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10778 14:48:48.034869 <6>[ 3.733108] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10779 14:48:48.041348 <6>[ 3.741453] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10780 14:48:48.050806 <6>[ 3.749790] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10781 14:48:48.057323 <6>[ 3.758128] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10782 14:48:48.067163 <6>[ 3.766466] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10783 14:48:48.073779 <6>[ 3.774804] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10784 14:48:48.084318 <6>[ 3.783142] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10785 14:48:48.090889 <6>[ 3.791479] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10786 14:48:48.100367 <6>[ 3.799817] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10787 14:48:48.107576 <6>[ 3.808155] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10788 14:48:48.113678 <6>[ 3.816884] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10789 14:48:48.120982 <6>[ 3.824036] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10790 14:48:48.127364 <6>[ 3.830794] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10791 14:48:48.137535 <6>[ 3.837549] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10792 14:48:48.144397 <6>[ 3.844480] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10793 14:48:48.151043 <6>[ 3.851334] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10794 14:48:48.160645 <6>[ 3.860472] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10795 14:48:48.170268 <6>[ 3.869591] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10796 14:48:48.180105 <6>[ 3.878885] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10797 14:48:48.189919 <6>[ 3.888354] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10798 14:48:48.200033 <6>[ 3.897821] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10799 14:48:48.206995 <6>[ 3.906941] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10800 14:48:48.216668 <6>[ 3.916411] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10801 14:48:48.226586 <6>[ 3.925530] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10802 14:48:48.236068 <6>[ 3.934824] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10803 14:48:48.246236 <6>[ 3.944984] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10804 14:48:48.256776 <6>[ 3.956541] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10805 14:48:48.306902 <6>[ 4.006761] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10806 14:48:48.461375 <6>[ 4.164880] hub 1-1:1.0: USB hub found
10807 14:48:48.464950 <6>[ 4.169395] hub 1-1:1.0: 4 ports detected
10808 14:48:48.474307 <6>[ 4.177642] hub 1-1:1.0: USB hub found
10809 14:48:48.477419 <6>[ 4.181967] hub 1-1:1.0: 4 ports detected
10810 14:48:48.587340 <6>[ 4.287124] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10811 14:48:48.612917 <6>[ 4.316601] hub 2-1:1.0: USB hub found
10812 14:48:48.616266 <6>[ 4.321104] hub 2-1:1.0: 3 ports detected
10813 14:48:48.625916 <6>[ 4.329543] hub 2-1:1.0: USB hub found
10814 14:48:48.629706 <6>[ 4.333997] hub 2-1:1.0: 3 ports detected
10815 14:48:48.802763 <6>[ 4.502813] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10816 14:48:48.934825 <6>[ 4.638542] hub 1-1.4:1.0: USB hub found
10817 14:48:48.938618 <6>[ 4.643193] hub 1-1.4:1.0: 2 ports detected
10818 14:48:48.947655 <6>[ 4.651137] hub 1-1.4:1.0: USB hub found
10819 14:48:48.950873 <6>[ 4.655666] hub 1-1.4:1.0: 2 ports detected
10820 14:48:49.018932 <6>[ 4.718900] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10821 14:48:49.127236 <6>[ 4.827426] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10822 14:48:49.164296 <4>[ 4.864306] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10823 14:48:49.173936 <4>[ 4.873471] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10824 14:48:49.212486 <6>[ 4.915525] r8152 2-1.3:1.0 eth0: v1.12.13
10825 14:48:49.246462 <6>[ 4.946784] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10826 14:48:49.438291 <6>[ 5.138649] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10827 14:48:50.963512 <6>[ 6.667409] r8152 2-1.3:1.0 eth0: carrier on
10828 14:48:53.311420 <5>[ 6.694545] Sending DHCP requests .., OK
10829 14:48:53.317251 <6>[ 9.018912] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10830 14:48:53.320340 <6>[ 9.027200] IP-Config: Complete:
10831 14:48:53.333311 <6>[ 9.030697] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10832 14:48:53.340217 <6>[ 9.041414] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10833 14:48:53.350219 <6>[ 9.050033] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10834 14:48:53.353269 <6>[ 9.050042] nameserver0=192.168.201.1
10835 14:48:53.356720 <6>[ 9.062178] clk: Disabling unused clocks
10836 14:48:53.360181 <6>[ 9.067599] ALSA device list:
10837 14:48:53.366701 <6>[ 9.070876] No soundcards found.
10838 14:48:53.374349 <6>[ 9.078442] Freeing unused kernel memory: 8512K
10839 14:48:53.377573 <6>[ 9.083494] Run /init as init process
10840 14:48:53.407802 <6>[ 9.111618] NET: Registered PF_INET6 protocol family
10841 14:48:53.414983 <6>[ 9.118552] Segment Routing with IPv6
10842 14:48:53.418067 <6>[ 9.122489] In-situ OAM (IOAM) with IPv6
10843 14:48:53.461573 <30>[ 9.139422] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10844 14:48:53.468272 <30>[ 9.172464] systemd[1]: Detected architecture arm64.
10845 14:48:53.468771
10846 14:48:53.474850 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10847 14:48:53.475352
10848 14:48:53.486779 <30>[ 9.190872] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10849 14:48:53.600025 <30>[ 9.300873] systemd[1]: Queued start job for default target graphical.target.
10850 14:48:53.651179 <30>[ 9.352048] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10851 14:48:53.658148 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10852 14:48:53.678915 <30>[ 9.379522] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10853 14:48:53.688376 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10854 14:48:53.708141 <30>[ 9.408553] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10855 14:48:53.717725 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10856 14:48:53.735715 <30>[ 9.435965] systemd[1]: Created slice user.slice - User and Session Slice.
10857 14:48:53.741640 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10858 14:48:53.761780 <30>[ 9.458813] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10859 14:48:53.768046 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10860 14:48:53.790236 <30>[ 9.487341] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10861 14:48:53.797070 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10862 14:48:53.824274 <30>[ 9.515097] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10863 14:48:53.834301 <30>[ 9.534966] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10864 14:48:53.840702 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10865 14:48:53.858349 <30>[ 9.559115] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10866 14:48:53.868310 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10867 14:48:53.882055 <30>[ 9.582799] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10868 14:48:53.891871 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10869 14:48:53.907237 <30>[ 9.611190] systemd[1]: Reached target paths.target - Path Units.
10870 14:48:53.916872 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10871 14:48:53.934600 <30>[ 9.635185] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10872 14:48:53.941064 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10873 14:48:53.954481 <30>[ 9.658730] systemd[1]: Reached target slices.target - Slice Units.
10874 14:48:53.964463 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10875 14:48:53.979584 <30>[ 9.683219] systemd[1]: Reached target swap.target - Swaps.
10876 14:48:53.986319 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10877 14:48:54.007061 <30>[ 9.707165] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10878 14:48:54.016529 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10879 14:48:54.034871 <30>[ 9.735215] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10880 14:48:54.044816 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10881 14:48:54.063270 <30>[ 9.764220] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10882 14:48:54.073522 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10883 14:48:54.090829 <30>[ 9.791444] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10884 14:48:54.100445 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10885 14:48:54.122513 <30>[ 9.823385] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10886 14:48:54.128976 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10887 14:48:54.147161 <30>[ 9.847467] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10888 14:48:54.156881 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10889 14:48:54.175476 <30>[ 9.876192] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10890 14:48:54.185104 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10891 14:48:54.202726 <30>[ 9.903894] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10892 14:48:54.212766 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10893 14:48:54.262321 <30>[ 9.962990] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10894 14:48:54.269381 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10895 14:48:54.281891 <30>[ 9.982526] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10896 14:48:54.288689 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10897 14:48:54.310478 <30>[ 10.011278] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10898 14:48:54.317132 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10899 14:48:54.344632 <30>[ 10.038913] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10900 14:48:54.378696 <30>[ 10.079097] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10901 14:48:54.388329 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10902 14:48:54.411297 <30>[ 10.111934] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10903 14:48:54.417452 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10904 14:48:54.443737 <30>[ 10.143987] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10905 14:48:54.456718 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 10.157468] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10906 14:48:54.459677 Module dm_mod...
10907 14:48:54.483115 <30>[ 10.183848] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10908 14:48:54.489843 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10909 14:48:54.515397 <30>[ 10.215995] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10910 14:48:54.525331 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10911 14:48:54.582392 <30>[ 10.283042] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10912 14:48:54.589221 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10913 14:48:54.614292 <30>[ 10.315349] systemd[1]: Starting systemd-journald.service - Journal Service...
10914 14:48:54.621756 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10915 14:48:54.641418 <30>[ 10.341866] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10916 14:48:54.647683 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10917 14:48:54.689178 <30>[ 10.387151] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10918 14:48:54.695880 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10919 14:48:54.718544 <30>[ 10.419704] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10920 14:48:54.728551 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10921 14:48:54.748589 <30>[ 10.449612] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10922 14:48:54.758638 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10923 14:48:54.779668 <30>[ 10.480429] systemd[1]: Started systemd-journald.service - Journal Service.
10924 14:48:54.786689 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10925 14:48:54.808873 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10926 14:48:54.827775 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10927 14:48:54.846263 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10928 14:48:54.866838 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10929 14:48:54.891201 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10930 14:48:54.916044 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10931 14:48:54.935902 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10932 14:48:54.957289 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10933 14:48:54.980287 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10934 14:48:55.004349 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10935 14:48:55.027680 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10936 14:48:55.052444 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10937 14:48:55.059049 See 'systemctl status systemd-remount-fs.service' for details.
10938 14:48:55.068806 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10939 14:48:55.092656 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10940 14:48:55.154845 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10941 14:48:55.179122 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10942 14:48:55.200578 <46>[ 10.901184] systemd-journald[182]: Received client request to flush runtime journal.
10943 14:48:55.213135 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10944 14:48:55.239458 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10945 14:48:55.262354 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10946 14:48:55.292840 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10947 14:48:55.315324 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10948 14:48:55.335830 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10949 14:48:55.359360 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10950 14:48:55.379265 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10951 14:48:55.418780 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10952 14:48:55.448666 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10953 14:48:55.466369 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10954 14:48:55.485987 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10955 14:48:55.530735 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10956 14:48:55.551173 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10957 14:48:55.574686 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10958 14:48:55.592924 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10959 14:48:55.670242 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10960 14:48:55.707955 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10961 14:48:55.737250 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10962 14:48:55.776270 <5>[ 11.476481] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10963 14:48:55.790800 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10964 14:48:55.810540 <5>[ 11.511226] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10965 14:48:55.816802 <5>[ 11.518556] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10966 14:48:55.826882 [[0;32m OK [<4>[ 11.527371] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10967 14:48:55.833802 0m] Finished [0<6>[ 11.537650] cfg80211: failed to load regulatory.db
10968 14:48:55.840376 ;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10969 14:48:55.861233 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10970 14:48:55.884846 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10971 14:48:55.976516 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10972 14:48:55.994798 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10973 14:48:56.011016 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10974 14:48:56.021700 <3>[ 11.722875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10975 14:48:56.028589 <6>[ 11.723672] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10976 14:48:56.038528 <6>[ 11.723700] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10977 14:48:56.045037 <3>[ 11.731552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10978 14:48:56.054794 <6>[ 11.739369] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10979 14:48:56.058464 <6>[ 11.741974] remoteproc remoteproc0: scp is available
10980 14:48:56.068356 <6>[ 11.742030] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10981 14:48:56.071416 <6>[ 11.742195] remoteproc remoteproc0: powering up scp
10982 14:48:56.081572 <6>[ 11.742207] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10983 14:48:56.084854 <6>[ 11.742275] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10984 14:48:56.094778 <3>[ 11.746124] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10985 14:48:56.102334 <3>[ 11.752922] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10986 14:48:56.111542 <6>[ 11.754437] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10987 14:48:56.118249 <3>[ 11.763068] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10988 14:48:56.128181 <4>[ 11.778048] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10989 14:48:56.131423 <4>[ 11.778048] Fallback method does not support PEC.
10990 14:48:56.141330 <3>[ 11.780978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10991 14:48:56.147942 <3>[ 11.780986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10992 14:48:56.158209 <3>[ 11.780994] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10993 14:48:56.164599 <4>[ 11.783876] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10994 14:48:56.174734 <3>[ 11.804649] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 14:48:56.182281 <3>[ 11.811870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10996 14:48:56.188531 <4>[ 11.822633] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10997 14:48:56.191833 <6>[ 11.828839] mc: Linux media interface: v0.10
10998 14:48:56.202052 <3>[ 11.837942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10999 14:48:56.208412 <3>[ 11.837978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11000 14:48:56.218151 <3>[ 11.837984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11001 14:48:56.225360 <3>[ 11.849412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11002 14:48:56.234864 <6>[ 11.868221] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11003 14:48:56.241671 <6>[ 11.868225] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11004 14:48:56.247575 <6>[ 11.868248] remoteproc remoteproc0: remote processor scp is now up
11005 14:48:56.254114 <3>[ 11.873567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11006 14:48:56.264278 <3>[ 11.873584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11007 14:48:56.270894 <3>[ 11.873594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11008 14:48:56.280776 <3>[ 11.888560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 14:48:56.287644 <3>[ 11.890503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11010 14:48:56.297511 <6>[ 11.897576] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11011 14:48:56.300370 <6>[ 11.897586] pci_bus 0000:00: root bus resource [bus 00-ff]
11012 14:48:56.307191 <6>[ 11.897593] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11013 14:48:56.317607 <6>[ 11.897599] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11014 14:48:56.323715 <6>[ 11.897637] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11015 14:48:56.333847 <6>[ 11.897664] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11016 14:48:56.337113 <6>[ 11.897748] pci 0000:00:00.0: supports D1 D2
11017 14:48:56.343687 <6>[ 11.897752] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11018 14:48:56.350589 <3>[ 11.898715] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11019 14:48:56.360316 <6>[ 11.899754] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11020 14:48:56.370765 <6>[ 11.899757] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11021 14:48:56.376805 <6>[ 11.899946] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11022 14:48:56.383232 <6>[ 11.899982] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11023 14:48:56.389781 <6>[ 11.900004] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11024 14:48:56.400065 <6>[ 11.900025] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11025 14:48:56.406274 <6>[ 11.900103] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11026 14:48:56.412921 <6>[ 11.900164] pci 0000:01:00.0: supports D1 D2
11027 14:48:56.419232 <6>[ 11.900169] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11028 14:48:56.425953 <3>[ 11.902316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11029 14:48:56.433121 <6>[ 11.912445] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11030 14:48:56.443085 <6>[ 12.011096] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11031 14:48:56.452902 <6>[ 12.018157] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11032 14:48:56.455933 <6>[ 12.048385] Bluetooth: Core ver 2.22
11033 14:48:56.459032 <6>[ 12.048490] videodev: Linux video capture interface: v2.00
11034 14:48:56.469571 <6>[ 12.053493] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11035 14:48:56.475390 <6>[ 12.054555] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11036 14:48:56.486357 <6>[ 12.056847] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11037 14:48:56.492314 <6>[ 12.060830] NET: Registered PF_BLUETOOTH protocol family
11038 14:48:56.498764 <6>[ 12.069015] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11039 14:48:56.505881 <6>[ 12.079047] Bluetooth: HCI device and connection manager initialized
11040 14:48:56.511816 <6>[ 12.079065] Bluetooth: HCI socket layer initialized
11041 14:48:56.518661 <6>[ 12.085366] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11042 14:48:56.525697 <6>[ 12.092780] Bluetooth: L2CAP socket layer initialized
11043 14:48:56.531974 <6>[ 12.100271] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11044 14:48:56.538881 <6>[ 12.107728] Bluetooth: SCO socket layer initialized
11045 14:48:56.544944 <6>[ 12.111373] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11046 14:48:56.555020 <6>[ 12.112911] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11047 14:48:56.561917 <6>[ 12.113116] usbcore: registered new interface driver uvcvideo
11048 14:48:56.568054 <6>[ 12.116792] pci 0000:00:00.0: PCI bridge to [bus 01]
11049 14:48:56.574356 <6>[ 12.144160] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11050 14:48:56.581714 <6>[ 12.152421] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11051 14:48:56.587956 <6>[ 12.161304] usbcore: registered new interface driver btusb
11052 14:48:56.597646 <4>[ 12.161793] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11053 14:48:56.604581 <3>[ 12.161800] Bluetooth: hci0: Failed to load firmware file (-2)
11054 14:48:56.610927 <3>[ 12.161802] Bluetooth: hci0: Failed to set up firmware (-2)
11055 14:48:56.620923 <4>[ 12.161804] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11056 14:48:56.627449 <6>[ 12.164508] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11057 14:48:56.634355 [[0;32m OK [<6>[ 12.337065] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11058 14:48:56.640774 0m] Reached targ<6>[ 12.344870] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11059 14:48:56.647292 et [0;1;39mtime-set.target[0m - System Time Set.
11060 14:48:56.668098 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11061 14:48:56.690992 [[0;32m OK [<3>[ 12.389654] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11062 14:48:56.698391 0m] Reached targ<3>[ 12.390233] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11063 14:48:56.707926 et [0;1;39mtime<6>[ 12.392732] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11064 14:48:56.714859 <6>[ 12.392842] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11065 14:48:56.721311 rs.target[0m - <6>[ 12.413409] mt7921e 0000:01:00.0: ASIC revision: 79610010
11066 14:48:56.721787 Timer Units.
11067 14:48:56.731208 <3>[ 12.426210] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11068 14:48:56.741894 <3>[ 12.441222] power_supply sbs-5-000b: driver failed to report `status' property: -6
11069 14:48:56.747707 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11070 14:48:56.763553 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11071 14:48:56.777446 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11072 14:48:56.793218 <3>[ 12.494333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11073 14:48:56.827019 <6>[ 12.527398] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11074 14:48:56.827528 <6>[ 12.527398]
11075 14:48:56.837003 <3>[ 12.534985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11076 14:48:56.843736 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11077 14:48:56.870412 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11078 14:48:56.882804 <3>[ 12.583694] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11079 14:48:56.918544 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11080 14:48:56.932334 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11081 14:48:56.963843 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11082 14:48:57.020639 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11083 14:48:57.046024 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11084 14:48:57.062643 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11085 14:48:57.093729 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/r<6>[ 12.794036] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11086 14:48:57.096555 fkill Watch.
11087 14:48:57.139849 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11088 14:48:57.158988 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11089 14:48:57.179485 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11090 14:48:57.195157 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11091 14:48:57.215314 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11092 14:48:57.256847 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11093 14:48:57.281746 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11094 14:48:57.306953 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11095 14:48:57.366455 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11096 14:48:57.386411 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11097 14:48:57.414907 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11098 14:48:57.458782
11099 14:48:57.461897 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11100 14:48:57.462523
11101 14:48:57.464840 debian-bookworm-arm64 login: root (automatic login)
11102 14:48:57.465315
11103 14:48:57.480486 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
11104 14:48:57.481048
11105 14:48:57.487448 The programs included with the Debian GNU/Linux system are free software;
11106 14:48:57.494044 the exact distribution terms for each program are described in the
11107 14:48:57.497005 individual files in /usr/share/doc/*/copyright.
11108 14:48:57.497482
11109 14:48:57.503829 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11110 14:48:57.507102 permitted by applicable law.
11111 14:48:57.508645 Matched prompt #10: / #
11113 14:48:57.509889 Setting prompt string to ['/ #']
11114 14:48:57.510639 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11116 14:48:57.511938 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11117 14:48:57.512519 start: 2.2.6 expect-shell-connection (timeout 00:02:51) [common]
11118 14:48:57.512963 Setting prompt string to ['/ #']
11119 14:48:57.513385 Forcing a shell prompt, looking for ['/ #']
11121 14:48:57.564447 / #
11122 14:48:57.565104 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11123 14:48:57.565592 Waiting using forced prompt support (timeout 00:02:30)
11124 14:48:57.571023
11125 14:48:57.571971 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11126 14:48:57.572555 start: 2.2.7 export-device-env (timeout 00:02:51) [common]
11127 14:48:57.573135 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11128 14:48:57.573711 end: 2.2 depthcharge-retry (duration 00:02:09) [common]
11129 14:48:57.574271 end: 2 depthcharge-action (duration 00:02:09) [common]
11130 14:48:57.574948 start: 3 lava-test-retry (timeout 00:05:00) [common]
11131 14:48:57.575456 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11132 14:48:57.575875 Using namespace: common
11134 14:48:57.677068 / # #
11135 14:48:57.677891 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11136 14:48:57.684020 #
11137 14:48:57.684918 Using /lava-14167048
11139 14:48:57.786297 / # export SHELL=/bin/sh
11140 14:48:57.792705 export SHELL=/bin/sh
11142 14:48:57.894325 / # . /lava-14167048/environment
11143 14:48:57.901064 . /lava-14167048/environment
11145 14:48:58.002678 / # /lava-14167048/bin/lava-test-runner /lava-14167048/0
11146 14:48:58.003248 Test shell timeout: 10s (minimum of the action and connection timeout)
11147 14:48:58.004747 /lava-14167048/bin/lava-test-runner /lava-14167048/0<6>[ 13.680563] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11148 14:48:58.008547
11149 14:48:58.050649 + export TESTRUN_ID=0_cros-ec
11150 14:48:58.051210 + cd /lava-141670<8>[ 13.745478] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14167048_1.5.2.3.1>
11151 14:48:58.051589 48/0/tests/0_cros-ec
11152 14:48:58.052261 Received signal: <STARTRUN> 0_cros-ec 14167048_1.5.2.3.1
11153 14:48:58.052646 Starting test lava.0_cros-ec (14167048_1.5.2.3.1)
11154 14:48:58.053063 Skipping test definition patterns.
11155 14:48:58.053688 + cat uuid
11156 14:48:58.054069 + UUID=14167048_1.5.2.3.1
11157 14:48:58.054468 + set +x
11158 14:48:58.054862 + python3 -m cros.runners.lava_runner -v
11159 14:48:58.474043 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11160 14:48:58.481244 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11161 14:48:58.481682
11162 14:48:58.487445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11163 14:48:58.488264 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11165 14:48:58.497372 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11166 14:48:58.506968 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11167 14:48:58.507526
11168 14:48:58.514085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11169 14:48:58.514916 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11171 14:48:58.523345 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11172 14:48:58.530183 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11173 14:48:58.530601
11174 14:48:58.536860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11175 14:48:58.537731 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11177 14:48:58.543533 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11178 14:48:58.549681 Checks the standard ABI for the main Embedded Controller. ... ok
11179 14:48:58.550222
11180 14:48:58.553051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11181 14:48:58.553746 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11183 14:48:58.559917 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11184 14:48:58.566581 Checks the main Embedded controller character device. ... ok
11185 14:48:58.567151
11186 14:48:58.572758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11187 14:48:58.573460 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11189 14:48:58.579763 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11190 14:48:58.586103 Checks basic comunication with the main Embedded controller. ... ok
11191 14:48:58.586608
11192 14:48:58.592906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11193 14:48:58.593574 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11195 14:48:58.599620 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11196 14:48:58.606553 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11197 14:48:58.606975
11198 14:48:58.612524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11199 14:48:58.613207 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11201 14:48:58.619050 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11202 14:48:58.625521 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11203 14:48:58.626003
11204 14:48:58.632341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11205 14:48:58.633110 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11207 14:48:58.639237 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11208 14:48:58.645337 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11209 14:48:58.645779
11210 14:48:58.651925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11211 14:48:58.652710 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11213 14:48:58.658693 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11214 14:48:58.668791 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11215 14:48:58.669393
11216 14:48:58.671989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11217 14:48:58.672679 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11219 14:48:58.678599 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11220 14:48:58.688939 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11221 14:48:58.689384
11222 14:48:58.695115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11223 14:48:58.695793 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11225 14:48:58.701690 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11226 14:48:58.708452 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11227 14:48:58.709028
11228 14:48:58.715120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11229 14:48:58.715837 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11231 14:48:58.721513 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11232 14:48:58.727886 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11233 14:48:58.728462
11234 14:48:58.734418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11235 14:48:58.735220 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11237 14:48:58.744375 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11238 14:48:58.751175 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11239 14:48:58.751671
11240 14:48:58.757760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11241 14:48:58.758546 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11243 14:48:58.767503 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11244 14:48:58.771028 Check the cros battery ABI. ... skipped 'No BAT found'
11245 14:48:58.771440
11246 14:48:58.777465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11247 14:48:58.778129 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11249 14:48:58.787451 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11250 14:48:58.794068 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11251 14:48:58.794509
11252 14:48:58.800336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11253 14:48:58.801013 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11255 14:48:58.810387 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11256 14:48:58.816770 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11257 14:48:58.817189
11258 14:48:58.820457 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11260 14:48:58.823564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11261 14:48:58.830127 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11262 14:48:58.836830 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11263 14:48:58.837250
11264 14:48:58.843110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11265 14:48:58.843529
11266 14:48:58.844109 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11268 14:48:58.853400 --------------------------<8>[ 14.554907] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14167048_1.5.2.3.1>
11269 14:48:58.854082 Received signal: <ENDRUN> 0_cros-ec 14167048_1.5.2.3.1
11270 14:48:58.854540 Ending use of test pattern.
11271 14:48:58.854869 Ending test lava.0_cros-ec (14167048_1.5.2.3.1), duration 0.80
11273 14:48:58.856850 --------------------------------------------
11274 14:48:58.860326 Ran 18 tests in 0.338s
11275 14:48:58.860809
11276 14:48:58.861144 OK (skipped=15)
11277 14:48:58.861457 + set +x
11278 14:48:58.863302 <LAVA_TEST_RUNNER EXIT>
11279 14:48:58.863967 ok: lava_test_shell seems to have completed
11280 14:48:58.865048 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11281 14:48:58.865533 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11282 14:48:58.865951 end: 3 lava-test-retry (duration 00:00:01) [common]
11283 14:48:58.866435 start: 4 finalize (timeout 00:07:27) [common]
11284 14:48:58.866904 start: 4.1 power-off (timeout 00:00:30) [common]
11285 14:48:58.867626 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11286 14:48:59.119766 >> Command sent successfully.
11287 14:48:59.130827 Returned 0 in 0 seconds
11288 14:48:59.232243 end: 4.1 power-off (duration 00:00:00) [common]
11290 14:48:59.233804 start: 4.2 read-feedback (timeout 00:07:27) [common]
11291 14:48:59.235134 Listened to connection for namespace 'common' for up to 1s
11292 14:49:00.235759 Finalising connection for namespace 'common'
11293 14:49:00.236412 Disconnecting from shell: Finalise
11294 14:49:00.236796 / #
11295 14:49:00.337840 end: 4.2 read-feedback (duration 00:00:01) [common]
11296 14:49:00.338626 end: 4 finalize (duration 00:00:01) [common]
11297 14:49:00.339251 Cleaning after the job
11298 14:49:00.339764 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/ramdisk
11299 14:49:00.366438 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/kernel
11300 14:49:00.394152 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/dtb
11301 14:49:00.394449 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14167048/tftp-deploy-rvk543o5/modules
11302 14:49:00.401573 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14167048
11303 14:49:00.489008 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14167048
11304 14:49:00.489187 Job finished correctly