Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 14:42:29.808517 lava-dispatcher, installed at version: 2024.03
2 14:42:29.808777 start: 0 validate
3 14:42:29.808919 Start time: 2024-06-04 14:42:29.808911+00:00 (UTC)
4 14:42:29.809045 Using caching service: 'http://localhost/cache/?uri=%s'
5 14:42:29.809178 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 14:42:30.069212 Using caching service: 'http://localhost/cache/?uri=%s'
7 14:42:30.069462 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 14:43:02.082008 Using caching service: 'http://localhost/cache/?uri=%s'
9 14:43:02.082240 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 14:43:02.339555 Using caching service: 'http://localhost/cache/?uri=%s'
11 14:43:02.339714 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 14:43:02.851231 Using caching service: 'http://localhost/cache/?uri=%s'
13 14:43:02.851415 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21-33-g2e011af54960c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 14:43:08.852031 validate duration: 39.04
16 14:43:08.852345 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 14:43:08.852479 start: 1.1 download-retry (timeout 00:10:00) [common]
18 14:43:08.852576 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 14:43:08.852711 Not decompressing ramdisk as can be used compressed.
20 14:43:08.852797 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 14:43:08.852863 saving as /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/ramdisk/initrd.cpio.gz
22 14:43:08.852929 total size: 5628169 (5 MB)
23 14:43:09.110695 progress 0 % (0 MB)
24 14:43:09.113165 progress 5 % (0 MB)
25 14:43:09.115561 progress 10 % (0 MB)
26 14:43:09.117888 progress 15 % (0 MB)
27 14:43:09.120333 progress 20 % (1 MB)
28 14:43:09.122666 progress 25 % (1 MB)
29 14:43:09.125099 progress 30 % (1 MB)
30 14:43:09.127637 progress 35 % (1 MB)
31 14:43:09.129769 progress 40 % (2 MB)
32 14:43:09.132355 progress 45 % (2 MB)
33 14:43:09.134599 progress 50 % (2 MB)
34 14:43:09.137147 progress 55 % (2 MB)
35 14:43:09.139508 progress 60 % (3 MB)
36 14:43:09.141688 progress 65 % (3 MB)
37 14:43:09.144656 progress 70 % (3 MB)
38 14:43:09.146809 progress 75 % (4 MB)
39 14:43:09.149210 progress 80 % (4 MB)
40 14:43:09.151433 progress 85 % (4 MB)
41 14:43:09.153834 progress 90 % (4 MB)
42 14:43:09.156373 progress 95 % (5 MB)
43 14:43:09.157927 progress 100 % (5 MB)
44 14:43:09.158171 5 MB downloaded in 0.31 s (17.58 MB/s)
45 14:43:09.158354 end: 1.1.1 http-download (duration 00:00:00) [common]
47 14:43:09.158626 end: 1.1 download-retry (duration 00:00:00) [common]
48 14:43:09.158728 start: 1.2 download-retry (timeout 00:10:00) [common]
49 14:43:09.158830 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 14:43:09.159041 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 14:43:09.159142 saving as /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/kernel/Image
52 14:43:09.159241 total size: 54682112 (52 MB)
53 14:43:09.159342 No compression specified
54 14:43:09.160981 progress 0 % (0 MB)
55 14:43:09.175353 progress 5 % (2 MB)
56 14:43:09.189622 progress 10 % (5 MB)
57 14:43:09.204684 progress 15 % (7 MB)
58 14:43:09.219147 progress 20 % (10 MB)
59 14:43:09.234688 progress 25 % (13 MB)
60 14:43:09.249565 progress 30 % (15 MB)
61 14:43:09.267675 progress 35 % (18 MB)
62 14:43:09.285218 progress 40 % (20 MB)
63 14:43:09.299786 progress 45 % (23 MB)
64 14:43:09.315431 progress 50 % (26 MB)
65 14:43:09.330698 progress 55 % (28 MB)
66 14:43:09.346250 progress 60 % (31 MB)
67 14:43:09.361692 progress 65 % (33 MB)
68 14:43:09.377168 progress 70 % (36 MB)
69 14:43:09.392365 progress 75 % (39 MB)
70 14:43:09.409068 progress 80 % (41 MB)
71 14:43:09.424626 progress 85 % (44 MB)
72 14:43:09.440102 progress 90 % (46 MB)
73 14:43:09.455001 progress 95 % (49 MB)
74 14:43:09.470122 progress 100 % (52 MB)
75 14:43:09.470488 52 MB downloaded in 0.31 s (167.55 MB/s)
76 14:43:09.470722 end: 1.2.1 http-download (duration 00:00:00) [common]
78 14:43:09.471014 end: 1.2 download-retry (duration 00:00:00) [common]
79 14:43:09.471134 start: 1.3 download-retry (timeout 00:09:59) [common]
80 14:43:09.471302 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 14:43:09.471478 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 14:43:09.471551 saving as /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/dtb/mt8192-asurada-spherion-r0.dtb
83 14:43:09.471616 total size: 47258 (0 MB)
84 14:43:09.471680 No compression specified
85 14:43:09.472898 progress 69 % (0 MB)
86 14:43:09.473181 progress 100 % (0 MB)
87 14:43:09.473349 0 MB downloaded in 0.00 s (26.05 MB/s)
88 14:43:09.473485 end: 1.3.1 http-download (duration 00:00:00) [common]
90 14:43:09.473734 end: 1.3 download-retry (duration 00:00:00) [common]
91 14:43:09.473826 start: 1.4 download-retry (timeout 00:09:59) [common]
92 14:43:09.473920 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 14:43:09.474042 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 14:43:09.474115 saving as /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/nfsrootfs/full.rootfs.tar
95 14:43:09.474183 total size: 120894716 (115 MB)
96 14:43:09.474287 Using unxz to decompress xz
97 14:43:09.479330 progress 0 % (0 MB)
98 14:43:09.865075 progress 5 % (5 MB)
99 14:43:10.300339 progress 10 % (11 MB)
100 14:43:10.739454 progress 15 % (17 MB)
101 14:43:11.118102 progress 20 % (23 MB)
102 14:43:11.463152 progress 25 % (28 MB)
103 14:43:11.903379 progress 30 % (34 MB)
104 14:43:12.318334 progress 35 % (40 MB)
105 14:43:12.502320 progress 40 % (46 MB)
106 14:43:12.696967 progress 45 % (51 MB)
107 14:43:13.056572 progress 50 % (57 MB)
108 14:43:13.473663 progress 55 % (63 MB)
109 14:43:13.897684 progress 60 % (69 MB)
110 14:43:14.289596 progress 65 % (74 MB)
111 14:43:14.662629 progress 70 % (80 MB)
112 14:43:15.050179 progress 75 % (86 MB)
113 14:43:15.426531 progress 80 % (92 MB)
114 14:43:15.849165 progress 85 % (98 MB)
115 14:43:16.220736 progress 90 % (103 MB)
116 14:43:16.570212 progress 95 % (109 MB)
117 14:43:16.947723 progress 100 % (115 MB)
118 14:43:16.955008 115 MB downloaded in 7.48 s (15.41 MB/s)
119 14:43:16.955380 end: 1.4.1 http-download (duration 00:00:07) [common]
121 14:43:16.955802 end: 1.4 download-retry (duration 00:00:07) [common]
122 14:43:16.955945 start: 1.5 download-retry (timeout 00:09:52) [common]
123 14:43:16.956088 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 14:43:16.956301 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 14:43:16.956412 saving as /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/modules/modules.tar
126 14:43:16.956510 total size: 8608920 (8 MB)
127 14:43:16.956627 Using unxz to decompress xz
128 14:43:16.961878 progress 0 % (0 MB)
129 14:43:16.982613 progress 5 % (0 MB)
130 14:43:17.012133 progress 10 % (0 MB)
131 14:43:17.045680 progress 15 % (1 MB)
132 14:43:17.070613 progress 20 % (1 MB)
133 14:43:17.095941 progress 25 % (2 MB)
134 14:43:17.120949 progress 30 % (2 MB)
135 14:43:17.147329 progress 35 % (2 MB)
136 14:43:17.181548 progress 40 % (3 MB)
137 14:43:17.209571 progress 45 % (3 MB)
138 14:43:17.238100 progress 50 % (4 MB)
139 14:43:17.264038 progress 55 % (4 MB)
140 14:43:17.289220 progress 60 % (4 MB)
141 14:43:17.314291 progress 65 % (5 MB)
142 14:43:17.341854 progress 70 % (5 MB)
143 14:43:17.371396 progress 75 % (6 MB)
144 14:43:17.399650 progress 80 % (6 MB)
145 14:43:17.425480 progress 85 % (7 MB)
146 14:43:17.451566 progress 90 % (7 MB)
147 14:43:17.477423 progress 95 % (7 MB)
148 14:43:17.507143 progress 100 % (8 MB)
149 14:43:17.514651 8 MB downloaded in 0.56 s (14.71 MB/s)
150 14:43:17.515004 end: 1.5.1 http-download (duration 00:00:01) [common]
152 14:43:17.515440 end: 1.5 download-retry (duration 00:00:01) [common]
153 14:43:17.515604 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 14:43:17.515806 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 14:43:21.692819 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14166992/extract-nfsrootfs-r1s09h8d
156 14:43:21.693029 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 14:43:21.693132 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 14:43:21.693309 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337
159 14:43:21.693452 makedir: /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin
160 14:43:21.693556 makedir: /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/tests
161 14:43:21.693655 makedir: /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/results
162 14:43:21.693756 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-add-keys
163 14:43:21.693898 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-add-sources
164 14:43:21.694030 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-background-process-start
165 14:43:21.694157 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-background-process-stop
166 14:43:21.694283 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-common-functions
167 14:43:21.694407 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-echo-ipv4
168 14:43:21.694533 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-install-packages
169 14:43:21.694659 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-installed-packages
170 14:43:21.694788 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-os-build
171 14:43:21.694912 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-probe-channel
172 14:43:21.695037 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-probe-ip
173 14:43:21.695160 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-target-ip
174 14:43:21.695283 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-target-mac
175 14:43:21.695406 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-target-storage
176 14:43:21.695535 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-test-case
177 14:43:21.695658 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-test-event
178 14:43:21.695784 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-test-feedback
179 14:43:21.695907 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-test-raise
180 14:43:21.696030 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-test-reference
181 14:43:21.696154 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-test-runner
182 14:43:21.696278 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-test-set
183 14:43:21.696403 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-test-shell
184 14:43:21.696528 Updating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-add-keys (debian)
185 14:43:21.696833 Updating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-add-sources (debian)
186 14:43:21.696983 Updating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-install-packages (debian)
187 14:43:21.697124 Updating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-installed-packages (debian)
188 14:43:21.697262 Updating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/bin/lava-os-build (debian)
189 14:43:21.697382 Creating /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/environment
190 14:43:21.697478 LAVA metadata
191 14:43:21.697544 - LAVA_JOB_ID=14166992
192 14:43:21.697607 - LAVA_DISPATCHER_IP=192.168.201.1
193 14:43:21.697721 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 14:43:21.697787 skipped lava-vland-overlay
195 14:43:21.697860 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 14:43:21.697940 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 14:43:21.698001 skipped lava-multinode-overlay
198 14:43:21.698084 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 14:43:21.698163 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 14:43:21.698237 Loading test definitions
201 14:43:21.698324 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 14:43:21.698395 Using /lava-14166992 at stage 0
203 14:43:21.698699 uuid=14166992_1.6.2.3.1 testdef=None
204 14:43:21.698786 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 14:43:21.698869 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 14:43:21.699317 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 14:43:21.699538 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 14:43:21.700081 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 14:43:21.700309 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 14:43:21.700877 runner path: /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/0/tests/0_timesync-off test_uuid 14166992_1.6.2.3.1
213 14:43:21.701034 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 14:43:21.701257 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 14:43:21.701328 Using /lava-14166992 at stage 0
217 14:43:21.701422 Fetching tests from https://github.com/kernelci/test-definitions.git
218 14:43:21.701506 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/0/tests/1_kselftest-rtc'
219 14:43:26.433911 Running '/usr/bin/git checkout kernelci.org
220 14:43:26.607802 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 14:43:26.608735 uuid=14166992_1.6.2.3.5 testdef=None
222 14:43:26.608930 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 14:43:26.609194 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 14:43:26.609985 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 14:43:26.610233 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 14:43:26.611338 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 14:43:26.611594 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 14:43:26.612535 runner path: /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/0/tests/1_kselftest-rtc test_uuid 14166992_1.6.2.3.5
232 14:43:26.612670 BOARD='mt8192-asurada-spherion-r0'
233 14:43:26.612765 BRANCH='cip'
234 14:43:26.612838 SKIPFILE='/dev/null'
235 14:43:26.612914 SKIP_INSTALL='True'
236 14:43:26.613012 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 14:43:26.613084 TST_CASENAME=''
238 14:43:26.613141 TST_CMDFILES='rtc'
239 14:43:26.613293 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 14:43:26.613508 Creating lava-test-runner.conf files
242 14:43:26.613575 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14166992/lava-overlay-qcrxm337/lava-14166992/0 for stage 0
243 14:43:26.613672 - 0_timesync-off
244 14:43:26.613743 - 1_kselftest-rtc
245 14:43:26.613840 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 14:43:26.613935 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 14:43:34.991855 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 14:43:34.992022 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 14:43:34.992121 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 14:43:34.992252 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 14:43:34.992357 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 14:43:35.168716 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 14:43:35.169216 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 14:43:35.169374 extracting modules file /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166992/extract-nfsrootfs-r1s09h8d
255 14:43:35.418954 extracting modules file /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14166992/extract-overlay-ramdisk-fbgqiyea/ramdisk
256 14:43:35.762994 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 14:43:35.763284 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 14:43:35.763473 [common] Applying overlay to NFS
259 14:43:35.763595 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14166992/compress-overlay-z28o0jaa/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14166992/extract-nfsrootfs-r1s09h8d
260 14:43:36.847129 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 14:43:36.847323 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 14:43:36.847423 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 14:43:36.847515 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 14:43:36.847599 Building ramdisk /var/lib/lava/dispatcher/tmp/14166992/extract-overlay-ramdisk-fbgqiyea/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14166992/extract-overlay-ramdisk-fbgqiyea/ramdisk
265 14:43:37.184377 >> 130335 blocks
266 14:43:39.279017 rename /var/lib/lava/dispatcher/tmp/14166992/extract-overlay-ramdisk-fbgqiyea/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/ramdisk/ramdisk.cpio.gz
267 14:43:39.279468 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 14:43:39.279594 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 14:43:39.279697 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 14:43:39.279803 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/kernel/Image']
271 14:43:54.078562 Returned 0 in 14 seconds
272 14:43:54.179334 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/kernel/image.itb
273 14:43:54.538438 output: FIT description: Kernel Image image with one or more FDT blobs
274 14:43:54.538938 output: Created: Tue Jun 4 15:43:54 2024
275 14:43:54.539076 output: Image 0 (kernel-1)
276 14:43:54.539201 output: Description:
277 14:43:54.539319 output: Created: Tue Jun 4 15:43:54 2024
278 14:43:54.539436 output: Type: Kernel Image
279 14:43:54.539558 output: Compression: lzma compressed
280 14:43:54.539678 output: Data Size: 13060619 Bytes = 12754.51 KiB = 12.46 MiB
281 14:43:54.539796 output: Architecture: AArch64
282 14:43:54.539912 output: OS: Linux
283 14:43:54.540027 output: Load Address: 0x00000000
284 14:43:54.540138 output: Entry Point: 0x00000000
285 14:43:54.540251 output: Hash algo: crc32
286 14:43:54.540367 output: Hash value: 88dcd836
287 14:43:54.540480 output: Image 1 (fdt-1)
288 14:43:54.540604 output: Description: mt8192-asurada-spherion-r0
289 14:43:54.540718 output: Created: Tue Jun 4 15:43:54 2024
290 14:43:54.540835 output: Type: Flat Device Tree
291 14:43:54.540948 output: Compression: uncompressed
292 14:43:54.541059 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 14:43:54.541170 output: Architecture: AArch64
294 14:43:54.541279 output: Hash algo: crc32
295 14:43:54.541391 output: Hash value: 0f8e4d2e
296 14:43:54.541502 output: Image 2 (ramdisk-1)
297 14:43:54.541611 output: Description: unavailable
298 14:43:54.541721 output: Created: Tue Jun 4 15:43:54 2024
299 14:43:54.541834 output: Type: RAMDisk Image
300 14:43:54.541942 output: Compression: Unknown Compression
301 14:43:54.542054 output: Data Size: 18728827 Bytes = 18289.87 KiB = 17.86 MiB
302 14:43:54.542162 output: Architecture: AArch64
303 14:43:54.542273 output: OS: Linux
304 14:43:54.542382 output: Load Address: unavailable
305 14:43:54.542491 output: Entry Point: unavailable
306 14:43:54.542601 output: Hash algo: crc32
307 14:43:54.542709 output: Hash value: e27e6c39
308 14:43:54.542817 output: Default Configuration: 'conf-1'
309 14:43:54.542924 output: Configuration 0 (conf-1)
310 14:43:54.543036 output: Description: mt8192-asurada-spherion-r0
311 14:43:54.543146 output: Kernel: kernel-1
312 14:43:54.543254 output: Init Ramdisk: ramdisk-1
313 14:43:54.543362 output: FDT: fdt-1
314 14:43:54.543471 output: Loadables: kernel-1
315 14:43:54.543583 output:
316 14:43:54.543897 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 14:43:54.544071 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 14:43:54.544252 end: 1.6 prepare-tftp-overlay (duration 00:00:37) [common]
319 14:43:54.544416 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
320 14:43:54.544561 No LXC device requested
321 14:43:54.544712 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 14:43:54.544871 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
323 14:43:54.545018 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 14:43:54.545151 Checking files for TFTP limit of 4294967296 bytes.
325 14:43:54.545984 end: 1 tftp-deploy (duration 00:00:46) [common]
326 14:43:54.546157 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 14:43:54.546317 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 14:43:54.546523 substitutions:
329 14:43:54.546644 - {DTB}: 14166992/tftp-deploy-2kidynw7/dtb/mt8192-asurada-spherion-r0.dtb
330 14:43:54.546760 - {INITRD}: 14166992/tftp-deploy-2kidynw7/ramdisk/ramdisk.cpio.gz
331 14:43:54.546874 - {KERNEL}: 14166992/tftp-deploy-2kidynw7/kernel/Image
332 14:43:54.546987 - {LAVA_MAC}: None
333 14:43:54.547101 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14166992/extract-nfsrootfs-r1s09h8d
334 14:43:54.547211 - {NFS_SERVER_IP}: 192.168.201.1
335 14:43:54.547321 - {PRESEED_CONFIG}: None
336 14:43:54.547432 - {PRESEED_LOCAL}: None
337 14:43:54.547541 - {RAMDISK}: 14166992/tftp-deploy-2kidynw7/ramdisk/ramdisk.cpio.gz
338 14:43:54.547653 - {ROOT_PART}: None
339 14:43:54.547761 - {ROOT}: None
340 14:43:54.547867 - {SERVER_IP}: 192.168.201.1
341 14:43:54.547978 - {TEE}: None
342 14:43:54.548086 Parsed boot commands:
343 14:43:54.548194 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 14:43:54.548485 Parsed boot commands: tftpboot 192.168.201.1 14166992/tftp-deploy-2kidynw7/kernel/image.itb 14166992/tftp-deploy-2kidynw7/kernel/cmdline
345 14:43:54.548642 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 14:43:54.548796 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 14:43:54.548955 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 14:43:54.549109 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 14:43:54.549243 Not connected, no need to disconnect.
350 14:43:54.549387 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 14:43:54.549538 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 14:43:54.549667 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 14:43:54.554202 Setting prompt string to ['lava-test: # ']
354 14:43:54.554727 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 14:43:54.554911 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 14:43:54.555060 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 14:43:54.555197 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 14:43:54.555535 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
359 14:43:59.692927 >> Command sent successfully.
360 14:43:59.695879 Returned 0 in 5 seconds
361 14:43:59.796263 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 14:43:59.796613 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 14:43:59.796726 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 14:43:59.796824 Setting prompt string to 'Starting depthcharge on Spherion...'
366 14:43:59.796895 Changing prompt to 'Starting depthcharge on Spherion...'
367 14:43:59.796982 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 14:43:59.797399 [Enter `^Ec?' for help]
369 14:43:59.967882
370 14:43:59.968055
371 14:43:59.968166 F0: 102B 0000
372 14:43:59.968266
373 14:43:59.968368 F3: 1001 0000 [0200]
374 14:43:59.971092
375 14:43:59.971209 F3: 1001 0000
376 14:43:59.971308
377 14:43:59.971400 F7: 102D 0000
378 14:43:59.971495
379 14:43:59.974425 F1: 0000 0000
380 14:43:59.974533
381 14:43:59.974634 V0: 0000 0000 [0001]
382 14:43:59.974725
383 14:43:59.977723 00: 0007 8000
384 14:43:59.977852
385 14:43:59.977952 01: 0000 0000
386 14:43:59.978049
387 14:43:59.981083 BP: 0C00 0209 [0000]
388 14:43:59.981162
389 14:43:59.981257 G0: 1182 0000
390 14:43:59.981349
391 14:43:59.984679 EC: 0000 0021 [4000]
392 14:43:59.984761
393 14:43:59.984827 S7: 0000 0000 [0000]
394 14:43:59.984887
395 14:43:59.988830 CC: 0000 0000 [0001]
396 14:43:59.988914
397 14:43:59.988987 T0: 0000 0040 [010F]
398 14:43:59.989053
399 14:43:59.989113 Jump to BL
400 14:43:59.989204
401 14:44:00.015142
402 14:44:00.015279
403 14:44:00.022137 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 14:44:00.025333 ARM64: Exception handlers installed.
405 14:44:00.028692 ARM64: Testing exception
406 14:44:00.032626 ARM64: Done test exception
407 14:44:00.038950 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 14:44:00.048759 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 14:44:00.055865 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 14:44:00.065608 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 14:44:00.072333 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 14:44:00.082501 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 14:44:00.092816 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 14:44:00.099507 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 14:44:00.117972 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 14:44:00.120724 WDT: Last reset was cold boot
417 14:44:00.124226 SPI1(PAD0) initialized at 2873684 Hz
418 14:44:00.127633 SPI5(PAD0) initialized at 992727 Hz
419 14:44:00.131192 VBOOT: Loading verstage.
420 14:44:00.138083 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 14:44:00.140914 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 14:44:00.144292 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 14:44:00.147602 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 14:44:00.155007 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 14:44:00.161792 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 14:44:00.172449 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
427 14:44:00.172582
428 14:44:00.172678
429 14:44:00.182723 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 14:44:00.185947 ARM64: Exception handlers installed.
431 14:44:00.189231 ARM64: Testing exception
432 14:44:00.189346 ARM64: Done test exception
433 14:44:00.196649 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 14:44:00.200249 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 14:44:00.213476 Probing TPM: . done!
436 14:44:00.213602 TPM ready after 0 ms
437 14:44:00.220573 Connected to device vid:did:rid of 1ae0:0028:00
438 14:44:00.227498 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 14:44:00.268629 Initialized TPM device CR50 revision 0
440 14:44:00.280596 tlcl_send_startup: Startup return code is 0
441 14:44:00.280693 TPM: setup succeeded
442 14:44:00.291979 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 14:44:00.300450 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 14:44:00.313356 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 14:44:00.321543 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 14:44:00.325306 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 14:44:00.328350 in-header: 03 07 00 00 08 00 00 00
448 14:44:00.332455 in-data: aa e4 47 04 13 02 00 00
449 14:44:00.335294 Chrome EC: UHEPI supported
450 14:44:00.342788 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 14:44:00.346236 in-header: 03 9d 00 00 08 00 00 00
452 14:44:00.350258 in-data: 10 20 20 08 00 00 00 00
453 14:44:00.350346 Phase 1
454 14:44:00.353706 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 14:44:00.360943 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 14:44:00.368760 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 14:44:00.368854 Recovery requested (1009000e)
458 14:44:00.376555 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 14:44:00.382074 tlcl_extend: response is 0
460 14:44:00.390238 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 14:44:00.395416 tlcl_extend: response is 0
462 14:44:00.402593 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 14:44:00.423280 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
464 14:44:00.430714 BS: bootblock times (exec / console): total (unknown) / 149 ms
465 14:44:00.430810
466 14:44:00.430882
467 14:44:00.438475 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 14:44:00.441982 ARM64: Exception handlers installed.
469 14:44:00.445928 ARM64: Testing exception
470 14:44:00.448677 ARM64: Done test exception
471 14:44:00.468768 pmic_efuse_setting: Set efuses in 11 msecs
472 14:44:00.472555 pmwrap_interface_init: Select PMIF_VLD_RDY
473 14:44:00.475973 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 14:44:00.483956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 14:44:00.487233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 14:44:00.491304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 14:44:00.498703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 14:44:00.501918 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 14:44:00.505460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 14:44:00.512630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 14:44:00.516743 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 14:44:00.519512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 14:44:00.526178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 14:44:00.529622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 14:44:00.532517 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 14:44:00.539898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 14:44:00.546259 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 14:44:00.553316 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 14:44:00.556663 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 14:44:00.563174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 14:44:00.569989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 14:44:00.573780 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 14:44:00.581117 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 14:44:00.584670 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 14:44:00.591637 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 14:44:00.598530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 14:44:00.602189 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 14:44:00.609065 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 14:44:00.612355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 14:44:00.616214 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 14:44:00.622944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 14:44:00.626292 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 14:44:00.633845 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 14:44:00.637368 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 14:44:00.641141 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 14:44:00.648276 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 14:44:00.652368 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 14:44:00.655672 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 14:44:00.662167 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 14:44:00.665621 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 14:44:00.672346 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 14:44:00.675445 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 14:44:00.679103 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 14:44:00.685587 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 14:44:00.689314 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 14:44:00.692873 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 14:44:00.699372 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 14:44:00.702076 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 14:44:00.705696 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 14:44:00.712784 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 14:44:00.715559 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 14:44:00.718913 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 14:44:00.722652 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 14:44:00.732377 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 14:44:00.738796 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 14:44:00.745753 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 14:44:00.752498 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 14:44:00.762027 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 14:44:00.765941 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 14:44:00.769121 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 14:44:00.775445 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 14:44:00.782305 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x7
533 14:44:00.785566 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 14:44:00.792590 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
535 14:44:00.795834 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 14:44:00.805421 [RTC]rtc_get_frequency_meter,154: input=15, output=793
537 14:44:00.809005 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
538 14:44:00.815356 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
539 14:44:00.818744 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
540 14:44:00.822585 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
541 14:44:00.825364 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
542 14:44:00.828855 ADC[4]: Raw value=896670 ID=7
543 14:44:00.832633 ADC[3]: Raw value=212700 ID=1
544 14:44:00.832714 RAM Code: 0x71
545 14:44:00.838907 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
546 14:44:00.842471 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
547 14:44:00.852523 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
548 14:44:00.859184 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
549 14:44:00.862739 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
550 14:44:00.865557 in-header: 03 07 00 00 08 00 00 00
551 14:44:00.869235 in-data: aa e4 47 04 13 02 00 00
552 14:44:00.872570 Chrome EC: UHEPI supported
553 14:44:00.879492 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
554 14:44:00.883010 in-header: 03 95 00 00 08 00 00 00
555 14:44:00.883118 in-data: 18 20 20 08 00 00 00 00
556 14:44:00.886883 MRC: failed to locate region type 0.
557 14:44:00.894455 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
558 14:44:00.898349 DRAM-K: Running full calibration
559 14:44:00.905011 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
560 14:44:00.905103 header.status = 0x0
561 14:44:00.908387 header.version = 0x6 (expected: 0x6)
562 14:44:00.911852 header.size = 0xd00 (expected: 0xd00)
563 14:44:00.915183 header.flags = 0x0
564 14:44:00.918598 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
565 14:44:00.937530 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
566 14:44:00.943954 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
567 14:44:00.947412 dram_init: ddr_geometry: 2
568 14:44:00.950705 [EMI] MDL number = 2
569 14:44:00.950812 [EMI] Get MDL freq = 0
570 14:44:00.954208 dram_init: ddr_type: 0
571 14:44:00.954340 is_discrete_lpddr4: 1
572 14:44:00.957384 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
573 14:44:00.957513
574 14:44:00.957637
575 14:44:00.960641 [Bian_co] ETT version 0.0.0.1
576 14:44:00.967545 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
577 14:44:00.967677
578 14:44:00.970784 dramc_set_vcore_voltage set vcore to 650000
579 14:44:00.970911 Read voltage for 800, 4
580 14:44:00.974228 Vio18 = 0
581 14:44:00.974353 Vcore = 650000
582 14:44:00.974473 Vdram = 0
583 14:44:00.977367 Vddq = 0
584 14:44:00.977495 Vmddr = 0
585 14:44:00.980671 dram_init: config_dvfs: 1
586 14:44:00.984136 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
587 14:44:00.990992 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
588 14:44:00.993926 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
589 14:44:00.997609 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
590 14:44:01.000740 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
591 14:44:01.004512 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
592 14:44:01.007728 MEM_TYPE=3, freq_sel=18
593 14:44:01.010820 sv_algorithm_assistance_LP4_1600
594 14:44:01.014581 ============ PULL DRAM RESETB DOWN ============
595 14:44:01.017611 ========== PULL DRAM RESETB DOWN end =========
596 14:44:01.024476 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
597 14:44:01.027600 ===================================
598 14:44:01.027728 LPDDR4 DRAM CONFIGURATION
599 14:44:01.031310 ===================================
600 14:44:01.034338 EX_ROW_EN[0] = 0x0
601 14:44:01.037938 EX_ROW_EN[1] = 0x0
602 14:44:01.038066 LP4Y_EN = 0x0
603 14:44:01.041908 WORK_FSP = 0x0
604 14:44:01.042015 WL = 0x2
605 14:44:01.044975 RL = 0x2
606 14:44:01.045082 BL = 0x2
607 14:44:01.045185 RPST = 0x0
608 14:44:01.049003 RD_PRE = 0x0
609 14:44:01.049082 WR_PRE = 0x1
610 14:44:01.052715 WR_PST = 0x0
611 14:44:01.052797 DBI_WR = 0x0
612 14:44:01.056631 DBI_RD = 0x0
613 14:44:01.056719 OTF = 0x1
614 14:44:01.060195 ===================================
615 14:44:01.064519 ===================================
616 14:44:01.064620 ANA top config
617 14:44:01.067976 ===================================
618 14:44:01.071973 DLL_ASYNC_EN = 0
619 14:44:01.072079 ALL_SLAVE_EN = 1
620 14:44:01.075326 NEW_RANK_MODE = 1
621 14:44:01.079364 DLL_IDLE_MODE = 1
622 14:44:01.083298 LP45_APHY_COMB_EN = 1
623 14:44:01.083382 TX_ODT_DIS = 1
624 14:44:01.086883 NEW_8X_MODE = 1
625 14:44:01.090383 ===================================
626 14:44:01.094357 ===================================
627 14:44:01.098437 data_rate = 1600
628 14:44:01.098551 CKR = 1
629 14:44:01.101881 DQ_P2S_RATIO = 8
630 14:44:01.105868 ===================================
631 14:44:01.109191 CA_P2S_RATIO = 8
632 14:44:01.109276 DQ_CA_OPEN = 0
633 14:44:01.113010 DQ_SEMI_OPEN = 0
634 14:44:01.116463 CA_SEMI_OPEN = 0
635 14:44:01.119902 CA_FULL_RATE = 0
636 14:44:01.119981 DQ_CKDIV4_EN = 1
637 14:44:01.123383 CA_CKDIV4_EN = 1
638 14:44:01.127475 CA_PREDIV_EN = 0
639 14:44:01.130797 PH8_DLY = 0
640 14:44:01.133774 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
641 14:44:01.133879 DQ_AAMCK_DIV = 4
642 14:44:01.137226 CA_AAMCK_DIV = 4
643 14:44:01.140431 CA_ADMCK_DIV = 4
644 14:44:01.143801 DQ_TRACK_CA_EN = 0
645 14:44:01.147093 CA_PICK = 800
646 14:44:01.150563 CA_MCKIO = 800
647 14:44:01.150639 MCKIO_SEMI = 0
648 14:44:01.153720 PLL_FREQ = 3068
649 14:44:01.157102 DQ_UI_PI_RATIO = 32
650 14:44:01.160630 CA_UI_PI_RATIO = 0
651 14:44:01.164136 ===================================
652 14:44:01.166987 ===================================
653 14:44:01.170306 memory_type:LPDDR4
654 14:44:01.170391 GP_NUM : 10
655 14:44:01.173965 SRAM_EN : 1
656 14:44:01.177496 MD32_EN : 0
657 14:44:01.180595 ===================================
658 14:44:01.180681 [ANA_INIT] >>>>>>>>>>>>>>
659 14:44:01.183949 <<<<<< [CONFIGURE PHASE]: ANA_TX
660 14:44:01.187219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
661 14:44:01.190412 ===================================
662 14:44:01.193936 data_rate = 1600,PCW = 0X7600
663 14:44:01.196791 ===================================
664 14:44:01.200688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
665 14:44:01.206783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
666 14:44:01.210143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 14:44:01.216740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
668 14:44:01.220824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
669 14:44:01.224805 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
670 14:44:01.224886 [ANA_INIT] flow start
671 14:44:01.228263 [ANA_INIT] PLL >>>>>>>>
672 14:44:01.228370 [ANA_INIT] PLL <<<<<<<<
673 14:44:01.231848 [ANA_INIT] MIDPI >>>>>>>>
674 14:44:01.235823 [ANA_INIT] MIDPI <<<<<<<<
675 14:44:01.235908 [ANA_INIT] DLL >>>>>>>>
676 14:44:01.239183 [ANA_INIT] flow end
677 14:44:01.242489 ============ LP4 DIFF to SE enter ============
678 14:44:01.246429 ============ LP4 DIFF to SE exit ============
679 14:44:01.250291 [ANA_INIT] <<<<<<<<<<<<<
680 14:44:01.253734 [Flow] Enable top DCM control >>>>>
681 14:44:01.253821 [Flow] Enable top DCM control <<<<<
682 14:44:01.257877 Enable DLL master slave shuffle
683 14:44:01.264884 ==============================================================
684 14:44:01.264971 Gating Mode config
685 14:44:01.272063 ==============================================================
686 14:44:01.272200 Config description:
687 14:44:01.281836 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
688 14:44:01.288278 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
689 14:44:01.295264 SELPH_MODE 0: By rank 1: By Phase
690 14:44:01.298304 ==============================================================
691 14:44:01.301567 GAT_TRACK_EN = 1
692 14:44:01.305129 RX_GATING_MODE = 2
693 14:44:01.308311 RX_GATING_TRACK_MODE = 2
694 14:44:01.312154 SELPH_MODE = 1
695 14:44:01.314944 PICG_EARLY_EN = 1
696 14:44:01.318323 VALID_LAT_VALUE = 1
697 14:44:01.321603 ==============================================================
698 14:44:01.328603 Enter into Gating configuration >>>>
699 14:44:01.328684 Exit from Gating configuration <<<<
700 14:44:01.331646 Enter into DVFS_PRE_config >>>>>
701 14:44:01.345216 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
702 14:44:01.348800 Exit from DVFS_PRE_config <<<<<
703 14:44:01.351593 Enter into PICG configuration >>>>
704 14:44:01.355609 Exit from PICG configuration <<<<
705 14:44:01.355690 [RX_INPUT] configuration >>>>>
706 14:44:01.358464 [RX_INPUT] configuration <<<<<
707 14:44:01.365059 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
708 14:44:01.368627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
709 14:44:01.375572 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
710 14:44:01.382245 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
711 14:44:01.388409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
712 14:44:01.395187 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
713 14:44:01.398528 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
714 14:44:01.401759 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
715 14:44:01.405396 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
716 14:44:01.411927 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
717 14:44:01.415310 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
718 14:44:01.418553 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
719 14:44:01.421704 ===================================
720 14:44:01.425235 LPDDR4 DRAM CONFIGURATION
721 14:44:01.428349 ===================================
722 14:44:01.431698 EX_ROW_EN[0] = 0x0
723 14:44:01.431785 EX_ROW_EN[1] = 0x0
724 14:44:01.435157 LP4Y_EN = 0x0
725 14:44:01.435269 WORK_FSP = 0x0
726 14:44:01.438619 WL = 0x2
727 14:44:01.438721 RL = 0x2
728 14:44:01.442156 BL = 0x2
729 14:44:01.442242 RPST = 0x0
730 14:44:01.444909 RD_PRE = 0x0
731 14:44:01.444998 WR_PRE = 0x1
732 14:44:01.448337 WR_PST = 0x0
733 14:44:01.448413 DBI_WR = 0x0
734 14:44:01.451842 DBI_RD = 0x0
735 14:44:01.451920 OTF = 0x1
736 14:44:01.455149 ===================================
737 14:44:01.458452 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
738 14:44:01.465460 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
739 14:44:01.468650 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
740 14:44:01.471929 ===================================
741 14:44:01.475376 LPDDR4 DRAM CONFIGURATION
742 14:44:01.478402 ===================================
743 14:44:01.478513 EX_ROW_EN[0] = 0x10
744 14:44:01.481512 EX_ROW_EN[1] = 0x0
745 14:44:01.485274 LP4Y_EN = 0x0
746 14:44:01.485380 WORK_FSP = 0x0
747 14:44:01.488327 WL = 0x2
748 14:44:01.488406 RL = 0x2
749 14:44:01.492306 BL = 0x2
750 14:44:01.492416 RPST = 0x0
751 14:44:01.495094 RD_PRE = 0x0
752 14:44:01.495172 WR_PRE = 0x1
753 14:44:01.498528 WR_PST = 0x0
754 14:44:01.498606 DBI_WR = 0x0
755 14:44:01.501935 DBI_RD = 0x0
756 14:44:01.502012 OTF = 0x1
757 14:44:01.505344 ===================================
758 14:44:01.511613 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
759 14:44:01.515557 nWR fixed to 40
760 14:44:01.518870 [ModeRegInit_LP4] CH0 RK0
761 14:44:01.518979 [ModeRegInit_LP4] CH0 RK1
762 14:44:01.522131 [ModeRegInit_LP4] CH1 RK0
763 14:44:01.525644 [ModeRegInit_LP4] CH1 RK1
764 14:44:01.525749 match AC timing 13
765 14:44:01.532152 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
766 14:44:01.535594 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
767 14:44:01.539290 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
768 14:44:01.546002 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
769 14:44:01.549429 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
770 14:44:01.549507 [EMI DOE] emi_dcm 0
771 14:44:01.555825 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
772 14:44:01.555906 ==
773 14:44:01.559118 Dram Type= 6, Freq= 0, CH_0, rank 0
774 14:44:01.562338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 14:44:01.562417 ==
776 14:44:01.569110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
777 14:44:01.575849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
778 14:44:01.583108 [CA 0] Center 38 (7~69) winsize 63
779 14:44:01.586829 [CA 1] Center 37 (7~68) winsize 62
780 14:44:01.589961 [CA 2] Center 35 (5~66) winsize 62
781 14:44:01.593354 [CA 3] Center 35 (5~66) winsize 62
782 14:44:01.596750 [CA 4] Center 34 (4~65) winsize 62
783 14:44:01.600313 [CA 5] Center 34 (4~64) winsize 61
784 14:44:01.600390
785 14:44:01.603571 [CmdBusTrainingLP45] Vref(ca) range 1: 32
786 14:44:01.603650
787 14:44:01.607773 [CATrainingPosCal] consider 1 rank data
788 14:44:01.610967 u2DelayCellTimex100 = 270/100 ps
789 14:44:01.614502 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
790 14:44:01.617959 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
791 14:44:01.621926 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
792 14:44:01.625369 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
793 14:44:01.628801 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
794 14:44:01.633318 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
795 14:44:01.633405
796 14:44:01.636546 CA PerBit enable=1, Macro0, CA PI delay=34
797 14:44:01.636649
798 14:44:01.640354 [CBTSetCACLKResult] CA Dly = 34
799 14:44:01.640466 CS Dly: 6 (0~37)
800 14:44:01.640571 ==
801 14:44:01.644093 Dram Type= 6, Freq= 0, CH_0, rank 1
802 14:44:01.647233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
803 14:44:01.651108 ==
804 14:44:01.654734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
805 14:44:01.661741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
806 14:44:01.669948 [CA 0] Center 38 (7~69) winsize 63
807 14:44:01.673513 [CA 1] Center 37 (7~68) winsize 62
808 14:44:01.677272 [CA 2] Center 35 (5~66) winsize 62
809 14:44:01.681224 [CA 3] Center 35 (5~66) winsize 62
810 14:44:01.685297 [CA 4] Center 34 (4~65) winsize 62
811 14:44:01.685385 [CA 5] Center 34 (4~65) winsize 62
812 14:44:01.685454
813 14:44:01.688703 [CmdBusTrainingLP45] Vref(ca) range 1: 30
814 14:44:01.693042
815 14:44:01.693129 [CATrainingPosCal] consider 2 rank data
816 14:44:01.696596 u2DelayCellTimex100 = 270/100 ps
817 14:44:01.699949 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
818 14:44:01.703992 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
819 14:44:01.707461 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
820 14:44:01.711491 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
821 14:44:01.715390 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
822 14:44:01.718803 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
823 14:44:01.718932
824 14:44:01.722766 CA PerBit enable=1, Macro0, CA PI delay=34
825 14:44:01.722886
826 14:44:01.727339 [CBTSetCACLKResult] CA Dly = 34
827 14:44:01.727469 CS Dly: 6 (0~38)
828 14:44:01.727583
829 14:44:01.730859 ----->DramcWriteLeveling(PI) begin...
830 14:44:01.730987 ==
831 14:44:01.734876 Dram Type= 6, Freq= 0, CH_0, rank 0
832 14:44:01.738491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
833 14:44:01.738601 ==
834 14:44:01.742200 Write leveling (Byte 0): 33 => 33
835 14:44:01.745982 Write leveling (Byte 1): 29 => 29
836 14:44:01.749887 DramcWriteLeveling(PI) end<-----
837 14:44:01.750013
838 14:44:01.750131 ==
839 14:44:01.753534 Dram Type= 6, Freq= 0, CH_0, rank 0
840 14:44:01.757102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 14:44:01.757232 ==
842 14:44:01.760204 [Gating] SW mode calibration
843 14:44:01.767504 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
844 14:44:01.771292 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
845 14:44:01.775173 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
846 14:44:01.779133 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 14:44:01.782835 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
848 14:44:01.789682 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
849 14:44:01.793712 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 14:44:01.797751 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 14:44:01.800980 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 14:44:01.805230 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 14:44:01.812549 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 14:44:01.816197 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 14:44:01.819829 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 14:44:01.823347 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 14:44:01.827217 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 14:44:01.834135 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 14:44:01.838063 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 14:44:01.841524 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 14:44:01.845566 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 14:44:01.849172 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 14:44:01.852599 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 14:44:01.860835 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
865 14:44:01.864067 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 14:44:01.867594 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 14:44:01.871224 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 14:44:01.874709 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 14:44:01.882589 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 14:44:01.886375 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 14:44:01.889728 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
872 14:44:01.894136 0 9 12 | B1->B0 | 2626 2f2f | 1 1 | (0 0) (1 1)
873 14:44:01.898149 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
874 14:44:01.901516 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 14:44:01.909107 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 14:44:01.912384 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 14:44:01.916402 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 14:44:01.919735 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 14:44:01.924126 0 10 8 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 1)
880 14:44:01.930465 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
881 14:44:01.934014 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
882 14:44:01.937389 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 14:44:01.944277 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 14:44:01.947219 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 14:44:01.950559 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 14:44:01.953776 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 14:44:01.960472 0 11 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
888 14:44:01.963920 0 11 12 | B1->B0 | 3333 4444 | 0 0 | (0 0) (0 0)
889 14:44:01.967563 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
890 14:44:01.973855 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 14:44:01.977722 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 14:44:01.980635 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 14:44:01.987145 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 14:44:01.990867 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 14:44:01.993818 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 14:44:02.000564 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
897 14:44:02.003999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 14:44:02.007530 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 14:44:02.013897 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 14:44:02.017038 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 14:44:02.020789 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 14:44:02.027491 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 14:44:02.030827 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 14:44:02.034137 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 14:44:02.040937 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 14:44:02.044264 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 14:44:02.047275 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 14:44:02.050697 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 14:44:02.057469 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 14:44:02.060821 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 14:44:02.063866 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
912 14:44:02.070577 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
913 14:44:02.073939 Total UI for P1: 0, mck2ui 16
914 14:44:02.077110 best dqsien dly found for B0: ( 0, 14, 8)
915 14:44:02.077238 Total UI for P1: 0, mck2ui 16
916 14:44:02.083719 best dqsien dly found for B1: ( 0, 14, 10)
917 14:44:02.087495 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
918 14:44:02.090528 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
919 14:44:02.090636
920 14:44:02.093850 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
921 14:44:02.097437 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
922 14:44:02.100825 [Gating] SW calibration Done
923 14:44:02.100909 ==
924 14:44:02.104266 Dram Type= 6, Freq= 0, CH_0, rank 0
925 14:44:02.107114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 14:44:02.107222 ==
927 14:44:02.110517 RX Vref Scan: 0
928 14:44:02.110620
929 14:44:02.110720 RX Vref 0 -> 0, step: 1
930 14:44:02.110811
931 14:44:02.113873 RX Delay -130 -> 252, step: 16
932 14:44:02.117159 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
933 14:44:02.123871 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
934 14:44:02.127389 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
935 14:44:02.130775 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
936 14:44:02.134120 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
937 14:44:02.137472 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
938 14:44:02.144152 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
939 14:44:02.147766 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
940 14:44:02.151036 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
941 14:44:02.154610 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
942 14:44:02.157346 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
943 14:44:02.164300 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
944 14:44:02.167657 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
945 14:44:02.171007 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
946 14:44:02.174049 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
947 14:44:02.177597 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
948 14:44:02.180799 ==
949 14:44:02.180888 Dram Type= 6, Freq= 0, CH_0, rank 0
950 14:44:02.187428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 14:44:02.187515 ==
952 14:44:02.187583 DQS Delay:
953 14:44:02.191006 DQS0 = 0, DQS1 = 0
954 14:44:02.191092 DQM Delay:
955 14:44:02.194259 DQM0 = 82, DQM1 = 70
956 14:44:02.194344 DQ Delay:
957 14:44:02.197562 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
958 14:44:02.200864 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
959 14:44:02.204125 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
960 14:44:02.207257 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
961 14:44:02.207366
962 14:44:02.207461
963 14:44:02.207555 ==
964 14:44:02.210834 Dram Type= 6, Freq= 0, CH_0, rank 0
965 14:44:02.214292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 14:44:02.214403 ==
967 14:44:02.214501
968 14:44:02.214595
969 14:44:02.218193 TX Vref Scan disable
970 14:44:02.218328 == TX Byte 0 ==
971 14:44:02.225121 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
972 14:44:02.228092 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
973 14:44:02.228202 == TX Byte 1 ==
974 14:44:02.235117 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
975 14:44:02.238295 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
976 14:44:02.238432 ==
977 14:44:02.241575 Dram Type= 6, Freq= 0, CH_0, rank 0
978 14:44:02.244535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
979 14:44:02.244680 ==
980 14:44:02.258782 TX Vref=22, minBit 7, minWin=26, winSum=435
981 14:44:02.262105 TX Vref=24, minBit 5, minWin=27, winSum=440
982 14:44:02.265574 TX Vref=26, minBit 4, minWin=27, winSum=442
983 14:44:02.268956 TX Vref=28, minBit 5, minWin=27, winSum=443
984 14:44:02.272459 TX Vref=30, minBit 9, minWin=27, winSum=443
985 14:44:02.275407 TX Vref=32, minBit 10, minWin=26, winSum=440
986 14:44:02.281971 [TxChooseVref] Worse bit 5, Min win 27, Win sum 443, Final Vref 28
987 14:44:02.282060
988 14:44:02.285622 Final TX Range 1 Vref 28
989 14:44:02.285709
990 14:44:02.285779 ==
991 14:44:02.289480 Dram Type= 6, Freq= 0, CH_0, rank 0
992 14:44:02.292132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
993 14:44:02.292218 ==
994 14:44:02.292285
995 14:44:02.295343
996 14:44:02.295430 TX Vref Scan disable
997 14:44:02.299000 == TX Byte 0 ==
998 14:44:02.302167 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
999 14:44:02.308968 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1000 14:44:02.309056 == TX Byte 1 ==
1001 14:44:02.312137 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1002 14:44:02.319059 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1003 14:44:02.319149
1004 14:44:02.319217 [DATLAT]
1005 14:44:02.319282 Freq=800, CH0 RK0
1006 14:44:02.319344
1007 14:44:02.321906 DATLAT Default: 0xa
1008 14:44:02.321992 0, 0xFFFF, sum = 0
1009 14:44:02.325201 1, 0xFFFF, sum = 0
1010 14:44:02.325289 2, 0xFFFF, sum = 0
1011 14:44:02.328447 3, 0xFFFF, sum = 0
1012 14:44:02.331911 4, 0xFFFF, sum = 0
1013 14:44:02.332040 5, 0xFFFF, sum = 0
1014 14:44:02.335169 6, 0xFFFF, sum = 0
1015 14:44:02.335296 7, 0xFFFF, sum = 0
1016 14:44:02.338760 8, 0xFFFF, sum = 0
1017 14:44:02.338887 9, 0x0, sum = 1
1018 14:44:02.339009 10, 0x0, sum = 2
1019 14:44:02.341984 11, 0x0, sum = 3
1020 14:44:02.342112 12, 0x0, sum = 4
1021 14:44:02.345442 best_step = 10
1022 14:44:02.345567
1023 14:44:02.345683 ==
1024 14:44:02.348605 Dram Type= 6, Freq= 0, CH_0, rank 0
1025 14:44:02.351689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1026 14:44:02.351817 ==
1027 14:44:02.355136 RX Vref Scan: 1
1028 14:44:02.355259
1029 14:44:02.358650 Set Vref Range= 32 -> 127
1030 14:44:02.358774
1031 14:44:02.358891 RX Vref 32 -> 127, step: 1
1032 14:44:02.359004
1033 14:44:02.361925 RX Delay -111 -> 252, step: 8
1034 14:44:02.362051
1035 14:44:02.365402 Set Vref, RX VrefLevel [Byte0]: 32
1036 14:44:02.368726 [Byte1]: 32
1037 14:44:02.368852
1038 14:44:02.371727 Set Vref, RX VrefLevel [Byte0]: 33
1039 14:44:02.375027 [Byte1]: 33
1040 14:44:02.379131
1041 14:44:02.379238 Set Vref, RX VrefLevel [Byte0]: 34
1042 14:44:02.382647 [Byte1]: 34
1043 14:44:02.387215
1044 14:44:02.387298 Set Vref, RX VrefLevel [Byte0]: 35
1045 14:44:02.390643 [Byte1]: 35
1046 14:44:02.395152
1047 14:44:02.395235 Set Vref, RX VrefLevel [Byte0]: 36
1048 14:44:02.398139 [Byte1]: 36
1049 14:44:02.402177
1050 14:44:02.402260 Set Vref, RX VrefLevel [Byte0]: 37
1051 14:44:02.405796 [Byte1]: 37
1052 14:44:02.409977
1053 14:44:02.410060 Set Vref, RX VrefLevel [Byte0]: 38
1054 14:44:02.413221 [Byte1]: 38
1055 14:44:02.417827
1056 14:44:02.417912 Set Vref, RX VrefLevel [Byte0]: 39
1057 14:44:02.420654 [Byte1]: 39
1058 14:44:02.425402
1059 14:44:02.425487 Set Vref, RX VrefLevel [Byte0]: 40
1060 14:44:02.428574 [Byte1]: 40
1061 14:44:02.432631
1062 14:44:02.432720 Set Vref, RX VrefLevel [Byte0]: 41
1063 14:44:02.436427 [Byte1]: 41
1064 14:44:02.440382
1065 14:44:02.440460 Set Vref, RX VrefLevel [Byte0]: 42
1066 14:44:02.443673 [Byte1]: 42
1067 14:44:02.448049
1068 14:44:02.448125 Set Vref, RX VrefLevel [Byte0]: 43
1069 14:44:02.451613 [Byte1]: 43
1070 14:44:02.455634
1071 14:44:02.455709 Set Vref, RX VrefLevel [Byte0]: 44
1072 14:44:02.459199 [Byte1]: 44
1073 14:44:02.463188
1074 14:44:02.463272 Set Vref, RX VrefLevel [Byte0]: 45
1075 14:44:02.466609 [Byte1]: 45
1076 14:44:02.471302
1077 14:44:02.471387 Set Vref, RX VrefLevel [Byte0]: 46
1078 14:44:02.474632 [Byte1]: 46
1079 14:44:02.479166
1080 14:44:02.479251 Set Vref, RX VrefLevel [Byte0]: 47
1081 14:44:02.482551 [Byte1]: 47
1082 14:44:02.486596
1083 14:44:02.486675 Set Vref, RX VrefLevel [Byte0]: 48
1084 14:44:02.490166 [Byte1]: 48
1085 14:44:02.494420
1086 14:44:02.494519 Set Vref, RX VrefLevel [Byte0]: 49
1087 14:44:02.497860 [Byte1]: 49
1088 14:44:02.501920
1089 14:44:02.502003 Set Vref, RX VrefLevel [Byte0]: 50
1090 14:44:02.505232 [Byte1]: 50
1091 14:44:02.509425
1092 14:44:02.509511 Set Vref, RX VrefLevel [Byte0]: 51
1093 14:44:02.512926 [Byte1]: 51
1094 14:44:02.516979
1095 14:44:02.517064 Set Vref, RX VrefLevel [Byte0]: 52
1096 14:44:02.520270 [Byte1]: 52
1097 14:44:02.524678
1098 14:44:02.524761 Set Vref, RX VrefLevel [Byte0]: 53
1099 14:44:02.528010 [Byte1]: 53
1100 14:44:02.532484
1101 14:44:02.532576 Set Vref, RX VrefLevel [Byte0]: 54
1102 14:44:02.535455 [Byte1]: 54
1103 14:44:02.539991
1104 14:44:02.540075 Set Vref, RX VrefLevel [Byte0]: 55
1105 14:44:02.543173 [Byte1]: 55
1106 14:44:02.547501
1107 14:44:02.547598 Set Vref, RX VrefLevel [Byte0]: 56
1108 14:44:02.551045 [Byte1]: 56
1109 14:44:02.555115
1110 14:44:02.555258 Set Vref, RX VrefLevel [Byte0]: 57
1111 14:44:02.558741 [Byte1]: 57
1112 14:44:02.562816
1113 14:44:02.562921 Set Vref, RX VrefLevel [Byte0]: 58
1114 14:44:02.566304 [Byte1]: 58
1115 14:44:02.570787
1116 14:44:02.570912 Set Vref, RX VrefLevel [Byte0]: 59
1117 14:44:02.574158 [Byte1]: 59
1118 14:44:02.578244
1119 14:44:02.578350 Set Vref, RX VrefLevel [Byte0]: 60
1120 14:44:02.581556 [Byte1]: 60
1121 14:44:02.585771
1122 14:44:02.585862 Set Vref, RX VrefLevel [Byte0]: 61
1123 14:44:02.589040 [Byte1]: 61
1124 14:44:02.593744
1125 14:44:02.593847 Set Vref, RX VrefLevel [Byte0]: 62
1126 14:44:02.596970 [Byte1]: 62
1127 14:44:02.600949
1128 14:44:02.601027 Set Vref, RX VrefLevel [Byte0]: 63
1129 14:44:02.604295 [Byte1]: 63
1130 14:44:02.608780
1131 14:44:02.608886 Set Vref, RX VrefLevel [Byte0]: 64
1132 14:44:02.612219 [Byte1]: 64
1133 14:44:02.616422
1134 14:44:02.616539 Set Vref, RX VrefLevel [Byte0]: 65
1135 14:44:02.619522 [Byte1]: 65
1136 14:44:02.624008
1137 14:44:02.624092 Set Vref, RX VrefLevel [Byte0]: 66
1138 14:44:02.627198 [Byte1]: 66
1139 14:44:02.631639
1140 14:44:02.631724 Set Vref, RX VrefLevel [Byte0]: 67
1141 14:44:02.635265 [Byte1]: 67
1142 14:44:02.639048
1143 14:44:02.639132 Set Vref, RX VrefLevel [Byte0]: 68
1144 14:44:02.642335 [Byte1]: 68
1145 14:44:02.647030
1146 14:44:02.647115 Set Vref, RX VrefLevel [Byte0]: 69
1147 14:44:02.650312 [Byte1]: 69
1148 14:44:02.654368
1149 14:44:02.654452 Set Vref, RX VrefLevel [Byte0]: 70
1150 14:44:02.657744 [Byte1]: 70
1151 14:44:02.662202
1152 14:44:02.662287 Set Vref, RX VrefLevel [Byte0]: 71
1153 14:44:02.665499 [Byte1]: 71
1154 14:44:02.670008
1155 14:44:02.670093 Set Vref, RX VrefLevel [Byte0]: 72
1156 14:44:02.673170 [Byte1]: 72
1157 14:44:02.677722
1158 14:44:02.677806 Set Vref, RX VrefLevel [Byte0]: 73
1159 14:44:02.680608 [Byte1]: 73
1160 14:44:02.685268
1161 14:44:02.685352 Set Vref, RX VrefLevel [Byte0]: 74
1162 14:44:02.688848 [Byte1]: 74
1163 14:44:02.692504
1164 14:44:02.692597 Set Vref, RX VrefLevel [Byte0]: 75
1165 14:44:02.696099 [Byte1]: 75
1166 14:44:02.700457
1167 14:44:02.700541 Set Vref, RX VrefLevel [Byte0]: 76
1168 14:44:02.703766 [Byte1]: 76
1169 14:44:02.708480
1170 14:44:02.708570 Set Vref, RX VrefLevel [Byte0]: 77
1171 14:44:02.711248 [Byte1]: 77
1172 14:44:02.715661
1173 14:44:02.715751 Set Vref, RX VrefLevel [Byte0]: 78
1174 14:44:02.718934 [Byte1]: 78
1175 14:44:02.723407
1176 14:44:02.723512 Set Vref, RX VrefLevel [Byte0]: 79
1177 14:44:02.726648 [Byte1]: 79
1178 14:44:02.730796
1179 14:44:02.730907 Set Vref, RX VrefLevel [Byte0]: 80
1180 14:44:02.734078 [Byte1]: 80
1181 14:44:02.738698
1182 14:44:02.738776 Final RX Vref Byte 0 = 59 to rank0
1183 14:44:02.742157 Final RX Vref Byte 1 = 55 to rank0
1184 14:44:02.745502 Final RX Vref Byte 0 = 59 to rank1
1185 14:44:02.748837 Final RX Vref Byte 1 = 55 to rank1==
1186 14:44:02.751630 Dram Type= 6, Freq= 0, CH_0, rank 0
1187 14:44:02.758307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 14:44:02.758410 ==
1189 14:44:02.758511 DQS Delay:
1190 14:44:02.758604 DQS0 = 0, DQS1 = 0
1191 14:44:02.761902 DQM Delay:
1192 14:44:02.761978 DQM0 = 82, DQM1 = 67
1193 14:44:02.764970 DQ Delay:
1194 14:44:02.768291 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1195 14:44:02.771950 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1196 14:44:02.772026 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1197 14:44:02.778659 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1198 14:44:02.778747
1199 14:44:02.778816
1200 14:44:02.785131 [DQSOSCAuto] RK0, (LSB)MR18= 0x2423, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1201 14:44:02.788448 CH0 RK0: MR19=606, MR18=2423
1202 14:44:02.795152 CH0_RK0: MR19=0x606, MR18=0x2423, DQSOSC=400, MR23=63, INC=92, DEC=61
1203 14:44:02.795238
1204 14:44:02.798714 ----->DramcWriteLeveling(PI) begin...
1205 14:44:02.798799 ==
1206 14:44:02.802162 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 14:44:02.805504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 14:44:02.805589 ==
1209 14:44:02.808811 Write leveling (Byte 0): 33 => 33
1210 14:44:02.812172 Write leveling (Byte 1): 30 => 30
1211 14:44:02.815616 DramcWriteLeveling(PI) end<-----
1212 14:44:02.815702
1213 14:44:02.815769 ==
1214 14:44:02.818964 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 14:44:02.822159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 14:44:02.822245 ==
1217 14:44:02.825338 [Gating] SW mode calibration
1218 14:44:02.831962 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1219 14:44:02.838375 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1220 14:44:02.841877 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 14:44:02.845462 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 14:44:02.852212 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1223 14:44:02.855743 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 14:44:02.859055 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 14:44:02.865678 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 14:44:02.868453 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 14:44:02.872012 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 14:44:02.878876 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 14:44:02.882021 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 14:44:02.885701 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 14:44:02.888670 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 14:44:02.936221 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 14:44:02.936359 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 14:44:02.936878 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 14:44:02.937524 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 14:44:02.937821 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 14:44:02.938579 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1238 14:44:02.938681 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1239 14:44:02.939225 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 14:44:02.939517 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 14:44:02.939634 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 14:44:02.972199 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 14:44:02.972299 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 14:44:02.972740 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 14:44:02.973343 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 14:44:02.973613 0 9 8 | B1->B0 | 2323 2b2b | 1 1 | (1 1) (1 1)
1247 14:44:02.973684 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1248 14:44:02.973749 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 14:44:02.973822 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 14:44:02.977273 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 14:44:02.980715 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 14:44:02.983596 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 14:44:02.987203 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1254 14:44:02.990610 0 10 8 | B1->B0 | 3232 2525 | 1 1 | (1 1) (1 0)
1255 14:44:02.996837 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1256 14:44:03.000176 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 14:44:03.003654 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 14:44:03.010398 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 14:44:03.014040 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 14:44:03.016967 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 14:44:03.023876 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1262 14:44:03.027171 0 11 8 | B1->B0 | 3232 4242 | 0 0 | (1 1) (0 0)
1263 14:44:03.030476 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
1264 14:44:03.036705 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 14:44:03.040032 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 14:44:03.043478 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 14:44:03.046878 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 14:44:03.054157 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 14:44:03.057840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 14:44:03.061499 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1271 14:44:03.065187 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1272 14:44:03.071557 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 14:44:03.075204 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 14:44:03.079521 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 14:44:03.082010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 14:44:03.089364 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 14:44:03.092146 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 14:44:03.095616 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 14:44:03.102611 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 14:44:03.105433 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 14:44:03.108827 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 14:44:03.115822 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 14:44:03.118966 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 14:44:03.122298 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 14:44:03.128995 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 14:44:03.132401 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1287 14:44:03.135862 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1288 14:44:03.138806 Total UI for P1: 0, mck2ui 16
1289 14:44:03.142476 best dqsien dly found for B0: ( 0, 14, 8)
1290 14:44:03.145664 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 14:44:03.149194 Total UI for P1: 0, mck2ui 16
1292 14:44:03.152285 best dqsien dly found for B1: ( 0, 14, 10)
1293 14:44:03.155894 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1294 14:44:03.162235 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1295 14:44:03.162339
1296 14:44:03.165720 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1297 14:44:03.168944 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1298 14:44:03.172306 [Gating] SW calibration Done
1299 14:44:03.172413 ==
1300 14:44:03.175451 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 14:44:03.179016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 14:44:03.179117 ==
1303 14:44:03.179211 RX Vref Scan: 0
1304 14:44:03.182201
1305 14:44:03.182286 RX Vref 0 -> 0, step: 1
1306 14:44:03.182349
1307 14:44:03.185703 RX Delay -130 -> 252, step: 16
1308 14:44:03.189151 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1309 14:44:03.192091 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1310 14:44:03.199022 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1311 14:44:03.202228 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1312 14:44:03.205626 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1313 14:44:03.209149 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1314 14:44:03.212514 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1315 14:44:03.219088 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1316 14:44:03.222475 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1317 14:44:03.225247 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1318 14:44:03.229265 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1319 14:44:03.231921 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1320 14:44:03.238816 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1321 14:44:03.242252 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1322 14:44:03.245527 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1323 14:44:03.249017 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1324 14:44:03.249097 ==
1325 14:44:03.251932 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 14:44:03.258760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 14:44:03.258840 ==
1328 14:44:03.258925 DQS Delay:
1329 14:44:03.261919 DQS0 = 0, DQS1 = 0
1330 14:44:03.261997 DQM Delay:
1331 14:44:03.262077 DQM0 = 76, DQM1 = 69
1332 14:44:03.265466 DQ Delay:
1333 14:44:03.268798 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1334 14:44:03.272221 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1335 14:44:03.275583 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1336 14:44:03.278799 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1337 14:44:03.278878
1338 14:44:03.278942
1339 14:44:03.279002 ==
1340 14:44:03.282343 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 14:44:03.285756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 14:44:03.285833 ==
1343 14:44:03.285934
1344 14:44:03.286036
1345 14:44:03.288798 TX Vref Scan disable
1346 14:44:03.288875 == TX Byte 0 ==
1347 14:44:03.295398 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1348 14:44:03.298751 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1349 14:44:03.298829 == TX Byte 1 ==
1350 14:44:03.305236 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1351 14:44:03.308496 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1352 14:44:03.308605 ==
1353 14:44:03.312005 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 14:44:03.315297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 14:44:03.315405 ==
1356 14:44:03.329795 TX Vref=22, minBit 12, minWin=26, winSum=433
1357 14:44:03.332632 TX Vref=24, minBit 1, minWin=27, winSum=440
1358 14:44:03.336220 TX Vref=26, minBit 11, minWin=26, winSum=439
1359 14:44:03.339897 TX Vref=28, minBit 1, minWin=27, winSum=439
1360 14:44:03.342784 TX Vref=30, minBit 1, minWin=27, winSum=441
1361 14:44:03.349486 TX Vref=32, minBit 3, minWin=27, winSum=441
1362 14:44:03.352885 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 30
1363 14:44:03.352972
1364 14:44:03.356258 Final TX Range 1 Vref 30
1365 14:44:03.356367
1366 14:44:03.356469 ==
1367 14:44:03.359621 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 14:44:03.363180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 14:44:03.363258 ==
1370 14:44:03.365925
1371 14:44:03.366010
1372 14:44:03.366076 TX Vref Scan disable
1373 14:44:03.369776 == TX Byte 0 ==
1374 14:44:03.372771 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1375 14:44:03.376216 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1376 14:44:03.379647 == TX Byte 1 ==
1377 14:44:03.383043 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1378 14:44:03.386294 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1379 14:44:03.389861
1380 14:44:03.389970 [DATLAT]
1381 14:44:03.390064 Freq=800, CH0 RK1
1382 14:44:03.390154
1383 14:44:03.392874 DATLAT Default: 0xa
1384 14:44:03.392955 0, 0xFFFF, sum = 0
1385 14:44:03.396279 1, 0xFFFF, sum = 0
1386 14:44:03.396389 2, 0xFFFF, sum = 0
1387 14:44:03.399579 3, 0xFFFF, sum = 0
1388 14:44:03.399685 4, 0xFFFF, sum = 0
1389 14:44:03.403254 5, 0xFFFF, sum = 0
1390 14:44:03.406245 6, 0xFFFF, sum = 0
1391 14:44:03.406356 7, 0xFFFF, sum = 0
1392 14:44:03.409774 8, 0xFFFF, sum = 0
1393 14:44:03.409879 9, 0x0, sum = 1
1394 14:44:03.409974 10, 0x0, sum = 2
1395 14:44:03.413171 11, 0x0, sum = 3
1396 14:44:03.413261 12, 0x0, sum = 4
1397 14:44:03.416398 best_step = 10
1398 14:44:03.416510
1399 14:44:03.416603 ==
1400 14:44:03.419376 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 14:44:03.422707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 14:44:03.422811 ==
1403 14:44:03.426530 RX Vref Scan: 0
1404 14:44:03.426614
1405 14:44:03.426679 RX Vref 0 -> 0, step: 1
1406 14:44:03.426742
1407 14:44:03.429497 RX Delay -111 -> 252, step: 8
1408 14:44:03.436240 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1409 14:44:03.439576 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1410 14:44:03.442904 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1411 14:44:03.446279 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1412 14:44:03.449782 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1413 14:44:03.456721 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1414 14:44:03.459656 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1415 14:44:03.463289 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1416 14:44:03.466425 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1417 14:44:03.469762 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1418 14:44:03.476633 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1419 14:44:03.479996 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1420 14:44:03.482960 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1421 14:44:03.486659 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1422 14:44:03.489616 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1423 14:44:03.496385 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1424 14:44:03.496467 ==
1425 14:44:03.499873 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 14:44:03.503300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 14:44:03.503391 ==
1428 14:44:03.503458 DQS Delay:
1429 14:44:03.506565 DQS0 = 0, DQS1 = 0
1430 14:44:03.506647 DQM Delay:
1431 14:44:03.510101 DQM0 = 79, DQM1 = 70
1432 14:44:03.510186 DQ Delay:
1433 14:44:03.513396 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1434 14:44:03.516583 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1435 14:44:03.519709 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1436 14:44:03.523064 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
1437 14:44:03.523147
1438 14:44:03.523212
1439 14:44:03.529667 [DQSOSCAuto] RK1, (LSB)MR18= 0x4823, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1440 14:44:03.533548 CH0 RK1: MR19=606, MR18=4823
1441 14:44:03.540282 CH0_RK1: MR19=0x606, MR18=0x4823, DQSOSC=391, MR23=63, INC=96, DEC=64
1442 14:44:03.543666 [RxdqsGatingPostProcess] freq 800
1443 14:44:03.549900 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 14:44:03.549983 Pre-setting of DQS Precalculation
1445 14:44:03.556578 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 14:44:03.556661 ==
1447 14:44:03.559904 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 14:44:03.563361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 14:44:03.563444 ==
1450 14:44:03.569731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 14:44:03.576428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 14:44:03.585137 [CA 0] Center 36 (6~66) winsize 61
1453 14:44:03.588015 [CA 1] Center 36 (6~67) winsize 62
1454 14:44:03.591778 [CA 2] Center 34 (5~64) winsize 60
1455 14:44:03.595152 [CA 3] Center 34 (4~64) winsize 61
1456 14:44:03.597960 [CA 4] Center 34 (4~64) winsize 61
1457 14:44:03.601568 [CA 5] Center 34 (4~64) winsize 61
1458 14:44:03.601649
1459 14:44:03.605064 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1460 14:44:03.605145
1461 14:44:03.608302 [CATrainingPosCal] consider 1 rank data
1462 14:44:03.611450 u2DelayCellTimex100 = 270/100 ps
1463 14:44:03.614999 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1464 14:44:03.618222 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 14:44:03.624722 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1466 14:44:03.628013 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 14:44:03.631131 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 14:44:03.634696 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1469 14:44:03.634776
1470 14:44:03.638224 CA PerBit enable=1, Macro0, CA PI delay=34
1471 14:44:03.638304
1472 14:44:03.641276 [CBTSetCACLKResult] CA Dly = 34
1473 14:44:03.641356 CS Dly: 5 (0~36)
1474 14:44:03.644261 ==
1475 14:44:03.647719 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 14:44:03.650893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 14:44:03.650989 ==
1478 14:44:03.654366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 14:44:03.661042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 14:44:03.670992 [CA 0] Center 36 (6~67) winsize 62
1481 14:44:03.674303 [CA 1] Center 36 (6~67) winsize 62
1482 14:44:03.677923 [CA 2] Center 35 (5~65) winsize 61
1483 14:44:03.680993 [CA 3] Center 34 (4~64) winsize 61
1484 14:44:03.684147 [CA 4] Center 34 (4~65) winsize 62
1485 14:44:03.687535 [CA 5] Center 33 (3~64) winsize 62
1486 14:44:03.687617
1487 14:44:03.691220 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1488 14:44:03.691302
1489 14:44:03.694209 [CATrainingPosCal] consider 2 rank data
1490 14:44:03.697576 u2DelayCellTimex100 = 270/100 ps
1491 14:44:03.700909 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1492 14:44:03.704410 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 14:44:03.711609 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1494 14:44:03.711692 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 14:44:03.714907 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 14:44:03.719038 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1497 14:44:03.719122
1498 14:44:03.725846 CA PerBit enable=1, Macro0, CA PI delay=34
1499 14:44:03.725945
1500 14:44:03.726072 [CBTSetCACLKResult] CA Dly = 34
1501 14:44:03.729811 CS Dly: 6 (0~38)
1502 14:44:03.729893
1503 14:44:03.733229 ----->DramcWriteLeveling(PI) begin...
1504 14:44:03.733312 ==
1505 14:44:03.737233 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 14:44:03.740815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 14:44:03.740897 ==
1508 14:44:03.744187 Write leveling (Byte 0): 26 => 26
1509 14:44:03.748015 Write leveling (Byte 1): 32 => 32
1510 14:44:03.750876 DramcWriteLeveling(PI) end<-----
1511 14:44:03.750958
1512 14:44:03.751023 ==
1513 14:44:03.754164 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 14:44:03.757468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 14:44:03.757551 ==
1516 14:44:03.761002 [Gating] SW mode calibration
1517 14:44:03.767486 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 14:44:03.770813 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 14:44:03.777748 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 14:44:03.781299 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1521 14:44:03.784567 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1522 14:44:03.791284 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 14:44:03.794358 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 14:44:03.797673 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 14:44:03.804437 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 14:44:03.807377 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 14:44:03.811279 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 14:44:03.817806 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 14:44:03.821381 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 14:44:03.824148 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 14:44:03.830844 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 14:44:03.834239 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 14:44:03.837691 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 14:44:03.844494 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 14:44:03.847835 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 14:44:03.850709 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1537 14:44:03.857386 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1538 14:44:03.860792 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 14:44:03.863681 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 14:44:03.870741 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 14:44:03.873976 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 14:44:03.877209 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 14:44:03.880281 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 14:44:03.887337 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 14:44:03.890488 0 9 8 | B1->B0 | 2929 2d2d | 1 0 | (1 1) (0 0)
1546 14:44:03.893714 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1547 14:44:03.900431 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 14:44:03.904015 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 14:44:03.907314 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 14:44:03.913696 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 14:44:03.917069 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 14:44:03.920327 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1553 14:44:03.927134 0 10 8 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (0 0)
1554 14:44:03.930410 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 14:44:03.933785 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 14:44:03.940701 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 14:44:03.943623 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 14:44:03.946945 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 14:44:03.953791 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 14:44:03.957277 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1561 14:44:03.960579 0 11 8 | B1->B0 | 3939 3737 | 0 0 | (0 0) (0 0)
1562 14:44:03.967483 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 14:44:03.970776 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 14:44:03.973938 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 14:44:03.977241 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 14:44:03.983607 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 14:44:03.986984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 14:44:03.990506 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 14:44:03.997043 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 14:44:04.000255 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 14:44:04.003691 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 14:44:04.010585 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 14:44:04.013939 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 14:44:04.017084 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 14:44:04.023828 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 14:44:04.027140 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 14:44:04.030529 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 14:44:04.036915 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 14:44:04.040414 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 14:44:04.043790 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 14:44:04.050007 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 14:44:04.053440 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 14:44:04.056939 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 14:44:04.063615 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1585 14:44:04.066694 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1586 14:44:04.070044 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 14:44:04.073387 Total UI for P1: 0, mck2ui 16
1588 14:44:04.077311 best dqsien dly found for B0: ( 0, 14, 6)
1589 14:44:04.080489 Total UI for P1: 0, mck2ui 16
1590 14:44:04.083421 best dqsien dly found for B1: ( 0, 14, 6)
1591 14:44:04.086771 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1592 14:44:04.090232 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1593 14:44:04.090315
1594 14:44:04.093458 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1595 14:44:04.100194 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1596 14:44:04.100278 [Gating] SW calibration Done
1597 14:44:04.100362 ==
1598 14:44:04.103373 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 14:44:04.110232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 14:44:04.110316 ==
1601 14:44:04.110401 RX Vref Scan: 0
1602 14:44:04.110480
1603 14:44:04.113682 RX Vref 0 -> 0, step: 1
1604 14:44:04.113782
1605 14:44:04.116941 RX Delay -130 -> 252, step: 16
1606 14:44:04.120255 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1607 14:44:04.123467 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1608 14:44:04.126545 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1609 14:44:04.133502 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1610 14:44:04.136819 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1611 14:44:04.140036 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1612 14:44:04.143159 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1613 14:44:04.146682 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1614 14:44:04.153175 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1615 14:44:04.156670 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1616 14:44:04.159898 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1617 14:44:04.163483 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1618 14:44:04.166902 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1619 14:44:04.173156 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1620 14:44:04.176484 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1621 14:44:04.179828 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1622 14:44:04.179908 ==
1623 14:44:04.183128 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 14:44:04.186321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 14:44:04.186402 ==
1626 14:44:04.189849 DQS Delay:
1627 14:44:04.189930 DQS0 = 0, DQS1 = 0
1628 14:44:04.193380 DQM Delay:
1629 14:44:04.193460 DQM0 = 80, DQM1 = 70
1630 14:44:04.193524 DQ Delay:
1631 14:44:04.196764 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1632 14:44:04.199810 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1633 14:44:04.203118 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1634 14:44:04.207008 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1635 14:44:04.207090
1636 14:44:04.207154
1637 14:44:04.209795 ==
1638 14:44:04.209875 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 14:44:04.216618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 14:44:04.216702 ==
1641 14:44:04.216767
1642 14:44:04.216826
1643 14:44:04.219955 TX Vref Scan disable
1644 14:44:04.220036 == TX Byte 0 ==
1645 14:44:04.223255 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1646 14:44:04.229871 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1647 14:44:04.229952 == TX Byte 1 ==
1648 14:44:04.233319 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1649 14:44:04.240059 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1650 14:44:04.240140 ==
1651 14:44:04.243459 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 14:44:04.246793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 14:44:04.246874 ==
1654 14:44:04.260002 TX Vref=22, minBit 1, minWin=27, winSum=445
1655 14:44:04.263239 TX Vref=24, minBit 1, minWin=27, winSum=446
1656 14:44:04.266952 TX Vref=26, minBit 1, minWin=27, winSum=449
1657 14:44:04.270301 TX Vref=28, minBit 5, minWin=27, winSum=452
1658 14:44:04.273218 TX Vref=30, minBit 1, minWin=28, winSum=455
1659 14:44:04.279932 TX Vref=32, minBit 5, minWin=27, winSum=450
1660 14:44:04.283403 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 30
1661 14:44:04.283484
1662 14:44:04.287196 Final TX Range 1 Vref 30
1663 14:44:04.287277
1664 14:44:04.287341 ==
1665 14:44:04.290687 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 14:44:04.294172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 14:44:04.294249 ==
1668 14:44:04.294314
1669 14:44:04.294375
1670 14:44:04.297623 TX Vref Scan disable
1671 14:44:04.301192 == TX Byte 0 ==
1672 14:44:04.304276 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1673 14:44:04.307586 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1674 14:44:04.311007 == TX Byte 1 ==
1675 14:44:04.314527 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1676 14:44:04.317667 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1677 14:44:04.317763
1678 14:44:04.320789 [DATLAT]
1679 14:44:04.320869 Freq=800, CH1 RK0
1680 14:44:04.320934
1681 14:44:04.324324 DATLAT Default: 0xa
1682 14:44:04.324404 0, 0xFFFF, sum = 0
1683 14:44:04.327779 1, 0xFFFF, sum = 0
1684 14:44:04.327861 2, 0xFFFF, sum = 0
1685 14:44:04.330789 3, 0xFFFF, sum = 0
1686 14:44:04.330870 4, 0xFFFF, sum = 0
1687 14:44:04.334157 5, 0xFFFF, sum = 0
1688 14:44:04.334240 6, 0xFFFF, sum = 0
1689 14:44:04.337492 7, 0xFFFF, sum = 0
1690 14:44:04.337574 8, 0xFFFF, sum = 0
1691 14:44:04.340738 9, 0x0, sum = 1
1692 14:44:04.340846 10, 0x0, sum = 2
1693 14:44:04.344052 11, 0x0, sum = 3
1694 14:44:04.344134 12, 0x0, sum = 4
1695 14:44:04.347637 best_step = 10
1696 14:44:04.347718
1697 14:44:04.347781 ==
1698 14:44:04.350903 Dram Type= 6, Freq= 0, CH_1, rank 0
1699 14:44:04.354367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1700 14:44:04.354448 ==
1701 14:44:04.354512 RX Vref Scan: 1
1702 14:44:04.357335
1703 14:44:04.357415 Set Vref Range= 32 -> 127
1704 14:44:04.357479
1705 14:44:04.360747 RX Vref 32 -> 127, step: 1
1706 14:44:04.360874
1707 14:44:04.364323 RX Delay -111 -> 252, step: 8
1708 14:44:04.364404
1709 14:44:04.367424 Set Vref, RX VrefLevel [Byte0]: 32
1710 14:44:04.370830 [Byte1]: 32
1711 14:44:04.370910
1712 14:44:04.374032 Set Vref, RX VrefLevel [Byte0]: 33
1713 14:44:04.377322 [Byte1]: 33
1714 14:44:04.380872
1715 14:44:04.381036 Set Vref, RX VrefLevel [Byte0]: 34
1716 14:44:04.384220 [Byte1]: 34
1717 14:44:04.388270
1718 14:44:04.388349 Set Vref, RX VrefLevel [Byte0]: 35
1719 14:44:04.391522 [Byte1]: 35
1720 14:44:04.395962
1721 14:44:04.396044 Set Vref, RX VrefLevel [Byte0]: 36
1722 14:44:04.399153 [Byte1]: 36
1723 14:44:04.403704
1724 14:44:04.403786 Set Vref, RX VrefLevel [Byte0]: 37
1725 14:44:04.407025 [Byte1]: 37
1726 14:44:04.411555
1727 14:44:04.411635 Set Vref, RX VrefLevel [Byte0]: 38
1728 14:44:04.414313 [Byte1]: 38
1729 14:44:04.418747
1730 14:44:04.418828 Set Vref, RX VrefLevel [Byte0]: 39
1731 14:44:04.422144 [Byte1]: 39
1732 14:44:04.426647
1733 14:44:04.426727 Set Vref, RX VrefLevel [Byte0]: 40
1734 14:44:04.429810 [Byte1]: 40
1735 14:44:04.434258
1736 14:44:04.434339 Set Vref, RX VrefLevel [Byte0]: 41
1737 14:44:04.437673 [Byte1]: 41
1738 14:44:04.441688
1739 14:44:04.441772 Set Vref, RX VrefLevel [Byte0]: 42
1740 14:44:04.444896 [Byte1]: 42
1741 14:44:04.449361
1742 14:44:04.449446 Set Vref, RX VrefLevel [Byte0]: 43
1743 14:44:04.452840 [Byte1]: 43
1744 14:44:04.456880
1745 14:44:04.456956 Set Vref, RX VrefLevel [Byte0]: 44
1746 14:44:04.460207 [Byte1]: 44
1747 14:44:04.464776
1748 14:44:04.464850 Set Vref, RX VrefLevel [Byte0]: 45
1749 14:44:04.468182 [Byte1]: 45
1750 14:44:04.472179
1751 14:44:04.472249 Set Vref, RX VrefLevel [Byte0]: 46
1752 14:44:04.475653 [Byte1]: 46
1753 14:44:04.480066
1754 14:44:04.480171 Set Vref, RX VrefLevel [Byte0]: 47
1755 14:44:04.483336 [Byte1]: 47
1756 14:44:04.487576
1757 14:44:04.487649 Set Vref, RX VrefLevel [Byte0]: 48
1758 14:44:04.490972 [Byte1]: 48
1759 14:44:04.495476
1760 14:44:04.495575 Set Vref, RX VrefLevel [Byte0]: 49
1761 14:44:04.498740 [Byte1]: 49
1762 14:44:04.502821
1763 14:44:04.502896 Set Vref, RX VrefLevel [Byte0]: 50
1764 14:44:04.506082 [Byte1]: 50
1765 14:44:04.510459
1766 14:44:04.510546 Set Vref, RX VrefLevel [Byte0]: 51
1767 14:44:04.514151 [Byte1]: 51
1768 14:44:04.518078
1769 14:44:04.518153 Set Vref, RX VrefLevel [Byte0]: 52
1770 14:44:04.521519 [Byte1]: 52
1771 14:44:04.525944
1772 14:44:04.526078 Set Vref, RX VrefLevel [Byte0]: 53
1773 14:44:04.528925 [Byte1]: 53
1774 14:44:04.533277
1775 14:44:04.533376 Set Vref, RX VrefLevel [Byte0]: 54
1776 14:44:04.536707 [Byte1]: 54
1777 14:44:04.541407
1778 14:44:04.541496 Set Vref, RX VrefLevel [Byte0]: 55
1779 14:44:04.544570 [Byte1]: 55
1780 14:44:04.548858
1781 14:44:04.549005 Set Vref, RX VrefLevel [Byte0]: 56
1782 14:44:04.552367 [Byte1]: 56
1783 14:44:04.556547
1784 14:44:04.556679 Set Vref, RX VrefLevel [Byte0]: 57
1785 14:44:04.560121 [Byte1]: 57
1786 14:44:04.563860
1787 14:44:04.563963 Set Vref, RX VrefLevel [Byte0]: 58
1788 14:44:04.567329 [Byte1]: 58
1789 14:44:04.572095
1790 14:44:04.572167 Set Vref, RX VrefLevel [Byte0]: 59
1791 14:44:04.575447 [Byte1]: 59
1792 14:44:04.579307
1793 14:44:04.579393 Set Vref, RX VrefLevel [Byte0]: 60
1794 14:44:04.582807 [Byte1]: 60
1795 14:44:04.587292
1796 14:44:04.587402 Set Vref, RX VrefLevel [Byte0]: 61
1797 14:44:04.590208 [Byte1]: 61
1798 14:44:04.594645
1799 14:44:04.594726 Set Vref, RX VrefLevel [Byte0]: 62
1800 14:44:04.598129 [Byte1]: 62
1801 14:44:04.602387
1802 14:44:04.602471 Set Vref, RX VrefLevel [Byte0]: 63
1803 14:44:04.605483 [Byte1]: 63
1804 14:44:04.609904
1805 14:44:04.609989 Set Vref, RX VrefLevel [Byte0]: 64
1806 14:44:04.613175 [Byte1]: 64
1807 14:44:04.617791
1808 14:44:04.617874 Set Vref, RX VrefLevel [Byte0]: 65
1809 14:44:04.621078 [Byte1]: 65
1810 14:44:04.625155
1811 14:44:04.625237 Set Vref, RX VrefLevel [Byte0]: 66
1812 14:44:04.628448 [Byte1]: 66
1813 14:44:04.633257
1814 14:44:04.633339 Set Vref, RX VrefLevel [Byte0]: 67
1815 14:44:04.636175 [Byte1]: 67
1816 14:44:04.640648
1817 14:44:04.640730 Set Vref, RX VrefLevel [Byte0]: 68
1818 14:44:04.643788 [Byte1]: 68
1819 14:44:04.648419
1820 14:44:04.648527 Set Vref, RX VrefLevel [Byte0]: 69
1821 14:44:04.651469 [Byte1]: 69
1822 14:44:04.655888
1823 14:44:04.659298 Set Vref, RX VrefLevel [Byte0]: 70
1824 14:44:04.659381 [Byte1]: 70
1825 14:44:04.663734
1826 14:44:04.663842 Set Vref, RX VrefLevel [Byte0]: 71
1827 14:44:04.666754 [Byte1]: 71
1828 14:44:04.671038
1829 14:44:04.671119 Set Vref, RX VrefLevel [Byte0]: 72
1830 14:44:04.674554 [Byte1]: 72
1831 14:44:04.678587
1832 14:44:04.678670 Set Vref, RX VrefLevel [Byte0]: 73
1833 14:44:04.681909 [Byte1]: 73
1834 14:44:04.686545
1835 14:44:04.686653 Final RX Vref Byte 0 = 59 to rank0
1836 14:44:04.689770 Final RX Vref Byte 1 = 55 to rank0
1837 14:44:04.693624 Final RX Vref Byte 0 = 59 to rank1
1838 14:44:04.696605 Final RX Vref Byte 1 = 55 to rank1==
1839 14:44:04.699559 Dram Type= 6, Freq= 0, CH_1, rank 0
1840 14:44:04.706296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 14:44:04.706380 ==
1842 14:44:04.706445 DQS Delay:
1843 14:44:04.706506 DQS0 = 0, DQS1 = 0
1844 14:44:04.709669 DQM Delay:
1845 14:44:04.709770 DQM0 = 81, DQM1 = 72
1846 14:44:04.713245 DQ Delay:
1847 14:44:04.716446 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1848 14:44:04.716579 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1849 14:44:04.720095 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1850 14:44:04.723161 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =80
1851 14:44:04.726370
1852 14:44:04.726451
1853 14:44:04.732922 [DQSOSCAuto] RK0, (LSB)MR18= 0xf18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1854 14:44:04.736506 CH1 RK0: MR19=606, MR18=F18
1855 14:44:04.743428 CH1_RK0: MR19=0x606, MR18=0xF18, DQSOSC=403, MR23=63, INC=90, DEC=60
1856 14:44:04.743513
1857 14:44:04.746207 ----->DramcWriteLeveling(PI) begin...
1858 14:44:04.746337 ==
1859 14:44:04.750060 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 14:44:04.752963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 14:44:04.753054 ==
1862 14:44:04.756247 Write leveling (Byte 0): 28 => 28
1863 14:44:04.759752 Write leveling (Byte 1): 30 => 30
1864 14:44:04.763272 DramcWriteLeveling(PI) end<-----
1865 14:44:04.763372
1866 14:44:04.763462 ==
1867 14:44:04.766504 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 14:44:04.769904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 14:44:04.769976 ==
1870 14:44:04.773234 [Gating] SW mode calibration
1871 14:44:04.779858 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1872 14:44:04.786465 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1873 14:44:04.789814 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1874 14:44:04.793261 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1875 14:44:04.799673 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 14:44:04.803152 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 14:44:04.806752 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 14:44:04.812950 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 14:44:04.816537 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 14:44:04.819746 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 14:44:04.822965 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 14:44:04.829599 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 14:44:04.833157 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 14:44:04.836458 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 14:44:04.842829 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 14:44:04.846571 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 14:44:04.849638 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 14:44:04.856870 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 14:44:04.860022 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1890 14:44:04.862901 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1891 14:44:04.869679 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 14:44:04.873512 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 14:44:04.876419 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 14:44:04.883150 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 14:44:04.886597 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 14:44:04.889762 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 14:44:04.896716 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 14:44:04.899480 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1899 14:44:04.902959 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (1 1) (1 1)
1900 14:44:04.909747 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 14:44:04.913093 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 14:44:04.916586 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 14:44:04.919898 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 14:44:04.926885 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 14:44:04.929922 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1906 14:44:04.933040 0 10 4 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (1 0)
1907 14:44:04.939709 0 10 8 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
1908 14:44:04.942932 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 14:44:04.946268 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 14:44:04.952848 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 14:44:04.955957 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 14:44:04.959244 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 14:44:04.966014 0 11 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
1914 14:44:04.969151 0 11 4 | B1->B0 | 2e2e 3535 | 0 0 | (1 1) (0 0)
1915 14:44:04.972852 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1916 14:44:04.979599 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 14:44:04.982890 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 14:44:04.985757 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 14:44:04.992197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 14:44:04.995836 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 14:44:04.999379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 14:44:05.006052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 14:44:05.008843 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1924 14:44:05.012232 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 14:44:05.019161 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 14:44:05.022669 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 14:44:05.025875 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 14:44:05.032185 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 14:44:05.035521 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 14:44:05.038761 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 14:44:05.045858 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 14:44:05.049069 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 14:44:05.052179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 14:44:05.059273 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 14:44:05.062340 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 14:44:05.065423 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 14:44:05.072111 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 14:44:05.075882 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 14:44:05.078894 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1940 14:44:05.082358 Total UI for P1: 0, mck2ui 16
1941 14:44:05.085512 best dqsien dly found for B0: ( 0, 14, 6)
1942 14:44:05.088909 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 14:44:05.092447 Total UI for P1: 0, mck2ui 16
1944 14:44:05.095851 best dqsien dly found for B1: ( 0, 14, 8)
1945 14:44:05.098663 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1946 14:44:05.105788 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1947 14:44:05.105864
1948 14:44:05.108786 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1949 14:44:05.112173 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1950 14:44:05.115423 [Gating] SW calibration Done
1951 14:44:05.115495 ==
1952 14:44:05.118857 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 14:44:05.122290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 14:44:05.122365 ==
1955 14:44:05.122433 RX Vref Scan: 0
1956 14:44:05.122496
1957 14:44:05.125723 RX Vref 0 -> 0, step: 1
1958 14:44:05.125795
1959 14:44:05.129172 RX Delay -130 -> 252, step: 16
1960 14:44:05.132455 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1961 14:44:05.135430 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1962 14:44:05.142214 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1963 14:44:05.146022 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1964 14:44:05.148894 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1965 14:44:05.152188 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1966 14:44:05.155441 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1967 14:44:05.162058 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1968 14:44:05.165272 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1969 14:44:05.168702 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1970 14:44:05.172252 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1971 14:44:05.175641 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1972 14:44:05.181809 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1973 14:44:05.185563 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1974 14:44:05.188814 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1975 14:44:05.192410 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1976 14:44:05.192492 ==
1977 14:44:05.195810 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 14:44:05.202298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 14:44:05.202399 ==
1980 14:44:05.202490 DQS Delay:
1981 14:44:05.202577 DQS0 = 0, DQS1 = 0
1982 14:44:05.205503 DQM Delay:
1983 14:44:05.205584 DQM0 = 78, DQM1 = 72
1984 14:44:05.208881 DQ Delay:
1985 14:44:05.212059 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1986 14:44:05.212140 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1987 14:44:05.215526 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1988 14:44:05.218834 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1989 14:44:05.222331
1990 14:44:05.222412
1991 14:44:05.222476 ==
1992 14:44:05.225376 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 14:44:05.228671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 14:44:05.228753 ==
1995 14:44:05.228818
1996 14:44:05.228878
1997 14:44:05.232041 TX Vref Scan disable
1998 14:44:05.232122 == TX Byte 0 ==
1999 14:44:05.238620 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2000 14:44:05.242219 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2001 14:44:05.242300 == TX Byte 1 ==
2002 14:44:05.248737 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2003 14:44:05.251917 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2004 14:44:05.251999 ==
2005 14:44:05.255423 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 14:44:05.258856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 14:44:05.258938 ==
2008 14:44:05.272473 TX Vref=22, minBit 6, minWin=27, winSum=447
2009 14:44:05.275747 TX Vref=24, minBit 1, minWin=28, winSum=454
2010 14:44:05.278960 TX Vref=26, minBit 1, minWin=28, winSum=457
2011 14:44:05.282504 TX Vref=28, minBit 0, minWin=28, winSum=457
2012 14:44:05.285903 TX Vref=30, minBit 1, minWin=27, winSum=460
2013 14:44:05.289527 TX Vref=32, minBit 5, minWin=27, winSum=460
2014 14:44:05.295620 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 26
2015 14:44:05.295703
2016 14:44:05.299376 Final TX Range 1 Vref 26
2017 14:44:05.299495
2018 14:44:05.299560 ==
2019 14:44:05.302829 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 14:44:05.305734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 14:44:05.305815 ==
2022 14:44:05.305880
2023 14:44:05.305939
2024 14:44:05.309165 TX Vref Scan disable
2025 14:44:05.312404 == TX Byte 0 ==
2026 14:44:05.316125 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2027 14:44:05.319290 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2028 14:44:05.322185 == TX Byte 1 ==
2029 14:44:05.325649 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2030 14:44:05.329024 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2031 14:44:05.332508
2032 14:44:05.332626 [DATLAT]
2033 14:44:05.332691 Freq=800, CH1 RK1
2034 14:44:05.332753
2035 14:44:05.335438 DATLAT Default: 0xa
2036 14:44:05.335520 0, 0xFFFF, sum = 0
2037 14:44:05.339206 1, 0xFFFF, sum = 0
2038 14:44:05.339289 2, 0xFFFF, sum = 0
2039 14:44:05.342114 3, 0xFFFF, sum = 0
2040 14:44:05.342197 4, 0xFFFF, sum = 0
2041 14:44:05.345400 5, 0xFFFF, sum = 0
2042 14:44:05.348771 6, 0xFFFF, sum = 0
2043 14:44:05.348853 7, 0xFFFF, sum = 0
2044 14:44:05.352180 8, 0xFFFF, sum = 0
2045 14:44:05.352263 9, 0x0, sum = 1
2046 14:44:05.352329 10, 0x0, sum = 2
2047 14:44:05.355594 11, 0x0, sum = 3
2048 14:44:05.355677 12, 0x0, sum = 4
2049 14:44:05.358920 best_step = 10
2050 14:44:05.359001
2051 14:44:05.359065 ==
2052 14:44:05.362300 Dram Type= 6, Freq= 0, CH_1, rank 1
2053 14:44:05.365622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2054 14:44:05.365704 ==
2055 14:44:05.369000 RX Vref Scan: 0
2056 14:44:05.369081
2057 14:44:05.369146 RX Vref 0 -> 0, step: 1
2058 14:44:05.369208
2059 14:44:05.372090 RX Delay -111 -> 252, step: 8
2060 14:44:05.379036 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2061 14:44:05.382159 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2062 14:44:05.385530 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2063 14:44:05.388828 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2064 14:44:05.392355 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2065 14:44:05.398960 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2066 14:44:05.402557 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2067 14:44:05.405617 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2068 14:44:05.409315 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2069 14:44:05.412519 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2070 14:44:05.419225 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2071 14:44:05.422463 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2072 14:44:05.425471 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2073 14:44:05.429303 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2074 14:44:05.432342 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2075 14:44:05.438991 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2076 14:44:05.439073 ==
2077 14:44:05.442514 Dram Type= 6, Freq= 0, CH_1, rank 1
2078 14:44:05.445785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2079 14:44:05.445868 ==
2080 14:44:05.445932 DQS Delay:
2081 14:44:05.449103 DQS0 = 0, DQS1 = 0
2082 14:44:05.449184 DQM Delay:
2083 14:44:05.452555 DQM0 = 77, DQM1 = 74
2084 14:44:05.452656 DQ Delay:
2085 14:44:05.455457 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2086 14:44:05.459249 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2087 14:44:05.462505 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2088 14:44:05.465839 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2089 14:44:05.465920
2090 14:44:05.466021
2091 14:44:05.475976 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2092 14:44:05.476059 CH1 RK1: MR19=606, MR18=1F37
2093 14:44:05.482716 CH1_RK1: MR19=0x606, MR18=0x1F37, DQSOSC=395, MR23=63, INC=94, DEC=63
2094 14:44:05.485711 [RxdqsGatingPostProcess] freq 800
2095 14:44:05.492180 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2096 14:44:05.495437 Pre-setting of DQS Precalculation
2097 14:44:05.498862 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2098 14:44:05.505666 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2099 14:44:05.512410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2100 14:44:05.512505
2101 14:44:05.515485
2102 14:44:05.515566 [Calibration Summary] 1600 Mbps
2103 14:44:05.519063 CH 0, Rank 0
2104 14:44:05.519145 SW Impedance : PASS
2105 14:44:05.522831 DUTY Scan : NO K
2106 14:44:05.525514 ZQ Calibration : PASS
2107 14:44:05.525596 Jitter Meter : NO K
2108 14:44:05.528948 CBT Training : PASS
2109 14:44:05.532490 Write leveling : PASS
2110 14:44:05.532633 RX DQS gating : PASS
2111 14:44:05.535684 RX DQ/DQS(RDDQC) : PASS
2112 14:44:05.539193 TX DQ/DQS : PASS
2113 14:44:05.539270 RX DATLAT : PASS
2114 14:44:05.542545 RX DQ/DQS(Engine): PASS
2115 14:44:05.542618 TX OE : NO K
2116 14:44:05.545909 All Pass.
2117 14:44:05.545980
2118 14:44:05.546042 CH 0, Rank 1
2119 14:44:05.549252 SW Impedance : PASS
2120 14:44:05.549323 DUTY Scan : NO K
2121 14:44:05.552160 ZQ Calibration : PASS
2122 14:44:05.555619 Jitter Meter : NO K
2123 14:44:05.555693 CBT Training : PASS
2124 14:44:05.559105 Write leveling : PASS
2125 14:44:05.562436 RX DQS gating : PASS
2126 14:44:05.562506 RX DQ/DQS(RDDQC) : PASS
2127 14:44:05.565750 TX DQ/DQS : PASS
2128 14:44:05.568934 RX DATLAT : PASS
2129 14:44:05.569004 RX DQ/DQS(Engine): PASS
2130 14:44:05.572370 TX OE : NO K
2131 14:44:05.572442 All Pass.
2132 14:44:05.572503
2133 14:44:05.575712 CH 1, Rank 0
2134 14:44:05.575784 SW Impedance : PASS
2135 14:44:05.579225 DUTY Scan : NO K
2136 14:44:05.582506 ZQ Calibration : PASS
2137 14:44:05.582606 Jitter Meter : NO K
2138 14:44:05.585768 CBT Training : PASS
2139 14:44:05.589404 Write leveling : PASS
2140 14:44:05.589485 RX DQS gating : PASS
2141 14:44:05.592431 RX DQ/DQS(RDDQC) : PASS
2142 14:44:05.592511 TX DQ/DQS : PASS
2143 14:44:05.595472 RX DATLAT : PASS
2144 14:44:05.598738 RX DQ/DQS(Engine): PASS
2145 14:44:05.598820 TX OE : NO K
2146 14:44:05.602048 All Pass.
2147 14:44:05.602129
2148 14:44:05.602194 CH 1, Rank 1
2149 14:44:05.605416 SW Impedance : PASS
2150 14:44:05.605497 DUTY Scan : NO K
2151 14:44:05.608730 ZQ Calibration : PASS
2152 14:44:05.612102 Jitter Meter : NO K
2153 14:44:05.612230 CBT Training : PASS
2154 14:44:05.615312 Write leveling : PASS
2155 14:44:05.618780 RX DQS gating : PASS
2156 14:44:05.618895 RX DQ/DQS(RDDQC) : PASS
2157 14:44:05.622211 TX DQ/DQS : PASS
2158 14:44:05.625610 RX DATLAT : PASS
2159 14:44:05.625738 RX DQ/DQS(Engine): PASS
2160 14:44:05.628612 TX OE : NO K
2161 14:44:05.628737 All Pass.
2162 14:44:05.628851
2163 14:44:05.632714 DramC Write-DBI off
2164 14:44:05.635467 PER_BANK_REFRESH: Hybrid Mode
2165 14:44:05.635592 TX_TRACKING: ON
2166 14:44:05.638635 [GetDramInforAfterCalByMRR] Vendor 6.
2167 14:44:05.642097 [GetDramInforAfterCalByMRR] Revision 606.
2168 14:44:05.645622 [GetDramInforAfterCalByMRR] Revision 2 0.
2169 14:44:05.648946 MR0 0x3b3b
2170 14:44:05.649070 MR8 0x5151
2171 14:44:05.652289 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2172 14:44:05.652413
2173 14:44:05.652529 MR0 0x3b3b
2174 14:44:05.655844 MR8 0x5151
2175 14:44:05.659024 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 14:44:05.659130
2177 14:44:05.665971 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2178 14:44:05.671995 [FAST_K] Save calibration result to emmc
2179 14:44:05.675394 [FAST_K] Save calibration result to emmc
2180 14:44:05.675520 dram_init: config_dvfs: 1
2181 14:44:05.679204 dramc_set_vcore_voltage set vcore to 662500
2182 14:44:05.682551 Read voltage for 1200, 2
2183 14:44:05.682632 Vio18 = 0
2184 14:44:05.685755 Vcore = 662500
2185 14:44:05.685831 Vdram = 0
2186 14:44:05.685895 Vddq = 0
2187 14:44:05.689308 Vmddr = 0
2188 14:44:05.692112 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2189 14:44:05.698821 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2190 14:44:05.698914 MEM_TYPE=3, freq_sel=15
2191 14:44:05.702067 sv_algorithm_assistance_LP4_1600
2192 14:44:05.709089 ============ PULL DRAM RESETB DOWN ============
2193 14:44:05.712223 ========== PULL DRAM RESETB DOWN end =========
2194 14:44:05.715646 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2195 14:44:05.719013 ===================================
2196 14:44:05.722472 LPDDR4 DRAM CONFIGURATION
2197 14:44:05.725601 ===================================
2198 14:44:05.725682 EX_ROW_EN[0] = 0x0
2199 14:44:05.728967 EX_ROW_EN[1] = 0x0
2200 14:44:05.732278 LP4Y_EN = 0x0
2201 14:44:05.732360 WORK_FSP = 0x0
2202 14:44:05.735424 WL = 0x4
2203 14:44:05.735532 RL = 0x4
2204 14:44:05.738887 BL = 0x2
2205 14:44:05.739001 RPST = 0x0
2206 14:44:05.742420 RD_PRE = 0x0
2207 14:44:05.742520 WR_PRE = 0x1
2208 14:44:05.746099 WR_PST = 0x0
2209 14:44:05.746180 DBI_WR = 0x0
2210 14:44:05.749135 DBI_RD = 0x0
2211 14:44:05.749218 OTF = 0x1
2212 14:44:05.752271 ===================================
2213 14:44:05.755589 ===================================
2214 14:44:05.759167 ANA top config
2215 14:44:05.762650 ===================================
2216 14:44:05.762736 DLL_ASYNC_EN = 0
2217 14:44:05.765459 ALL_SLAVE_EN = 0
2218 14:44:05.768961 NEW_RANK_MODE = 1
2219 14:44:05.772321 DLL_IDLE_MODE = 1
2220 14:44:05.775614 LP45_APHY_COMB_EN = 1
2221 14:44:05.775697 TX_ODT_DIS = 1
2222 14:44:05.779220 NEW_8X_MODE = 1
2223 14:44:05.782360 ===================================
2224 14:44:05.785545 ===================================
2225 14:44:05.789078 data_rate = 2400
2226 14:44:05.792390 CKR = 1
2227 14:44:05.795869 DQ_P2S_RATIO = 8
2228 14:44:05.798808 ===================================
2229 14:44:05.798894 CA_P2S_RATIO = 8
2230 14:44:05.802332 DQ_CA_OPEN = 0
2231 14:44:05.805675 DQ_SEMI_OPEN = 0
2232 14:44:05.809085 CA_SEMI_OPEN = 0
2233 14:44:05.812207 CA_FULL_RATE = 0
2234 14:44:05.815912 DQ_CKDIV4_EN = 0
2235 14:44:05.816008 CA_CKDIV4_EN = 0
2236 14:44:05.819100 CA_PREDIV_EN = 0
2237 14:44:05.822631 PH8_DLY = 17
2238 14:44:05.826035 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2239 14:44:05.829056 DQ_AAMCK_DIV = 4
2240 14:44:05.832422 CA_AAMCK_DIV = 4
2241 14:44:05.832505 CA_ADMCK_DIV = 4
2242 14:44:05.835685 DQ_TRACK_CA_EN = 0
2243 14:44:05.839058 CA_PICK = 1200
2244 14:44:05.842277 CA_MCKIO = 1200
2245 14:44:05.846034 MCKIO_SEMI = 0
2246 14:44:05.849435 PLL_FREQ = 2366
2247 14:44:05.852436 DQ_UI_PI_RATIO = 32
2248 14:44:05.852547 CA_UI_PI_RATIO = 0
2249 14:44:05.855711 ===================================
2250 14:44:05.859272 ===================================
2251 14:44:05.862501 memory_type:LPDDR4
2252 14:44:05.865574 GP_NUM : 10
2253 14:44:05.865698 SRAM_EN : 1
2254 14:44:05.868880 MD32_EN : 0
2255 14:44:05.872196 ===================================
2256 14:44:05.875832 [ANA_INIT] >>>>>>>>>>>>>>
2257 14:44:05.875922 <<<<<< [CONFIGURE PHASE]: ANA_TX
2258 14:44:05.882868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2259 14:44:05.885744 ===================================
2260 14:44:05.885850 data_rate = 2400,PCW = 0X5b00
2261 14:44:05.889350 ===================================
2262 14:44:05.892367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2263 14:44:05.898905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2264 14:44:05.905700 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 14:44:05.909006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2266 14:44:05.912475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2267 14:44:05.915967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2268 14:44:05.919070 [ANA_INIT] flow start
2269 14:44:05.919176 [ANA_INIT] PLL >>>>>>>>
2270 14:44:05.922611 [ANA_INIT] PLL <<<<<<<<
2271 14:44:05.925985 [ANA_INIT] MIDPI >>>>>>>>
2272 14:44:05.926089 [ANA_INIT] MIDPI <<<<<<<<
2273 14:44:05.928880 [ANA_INIT] DLL >>>>>>>>
2274 14:44:05.932200 [ANA_INIT] DLL <<<<<<<<
2275 14:44:05.932302 [ANA_INIT] flow end
2276 14:44:05.938845 ============ LP4 DIFF to SE enter ============
2277 14:44:05.942227 ============ LP4 DIFF to SE exit ============
2278 14:44:05.945687 [ANA_INIT] <<<<<<<<<<<<<
2279 14:44:05.948962 [Flow] Enable top DCM control >>>>>
2280 14:44:05.952160 [Flow] Enable top DCM control <<<<<
2281 14:44:05.952239 Enable DLL master slave shuffle
2282 14:44:05.959064 ==============================================================
2283 14:44:05.962698 Gating Mode config
2284 14:44:05.966051 ==============================================================
2285 14:44:05.969323 Config description:
2286 14:44:05.978896 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2287 14:44:05.985946 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2288 14:44:05.989369 SELPH_MODE 0: By rank 1: By Phase
2289 14:44:05.995671 ==============================================================
2290 14:44:05.999431 GAT_TRACK_EN = 1
2291 14:44:06.002524 RX_GATING_MODE = 2
2292 14:44:06.002628 RX_GATING_TRACK_MODE = 2
2293 14:44:06.006096 SELPH_MODE = 1
2294 14:44:06.008995 PICG_EARLY_EN = 1
2295 14:44:06.012436 VALID_LAT_VALUE = 1
2296 14:44:06.019374 ==============================================================
2297 14:44:06.022715 Enter into Gating configuration >>>>
2298 14:44:06.025592 Exit from Gating configuration <<<<
2299 14:44:06.029110 Enter into DVFS_PRE_config >>>>>
2300 14:44:06.039399 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2301 14:44:06.042558 Exit from DVFS_PRE_config <<<<<
2302 14:44:06.046016 Enter into PICG configuration >>>>
2303 14:44:06.049390 Exit from PICG configuration <<<<
2304 14:44:06.052650 [RX_INPUT] configuration >>>>>
2305 14:44:06.055926 [RX_INPUT] configuration <<<<<
2306 14:44:06.059154 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2307 14:44:06.065955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2308 14:44:06.072794 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 14:44:06.079201 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 14:44:06.082519 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 14:44:06.089221 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 14:44:06.092469 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2313 14:44:06.099003 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2314 14:44:06.102530 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2315 14:44:06.105752 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2316 14:44:06.108971 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2317 14:44:06.115852 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 14:44:06.119165 ===================================
2319 14:44:06.119274 LPDDR4 DRAM CONFIGURATION
2320 14:44:06.122122 ===================================
2321 14:44:06.126152 EX_ROW_EN[0] = 0x0
2322 14:44:06.129334 EX_ROW_EN[1] = 0x0
2323 14:44:06.129436 LP4Y_EN = 0x0
2324 14:44:06.132385 WORK_FSP = 0x0
2325 14:44:06.132492 WL = 0x4
2326 14:44:06.135865 RL = 0x4
2327 14:44:06.135976 BL = 0x2
2328 14:44:06.138870 RPST = 0x0
2329 14:44:06.138969 RD_PRE = 0x0
2330 14:44:06.142437 WR_PRE = 0x1
2331 14:44:06.142543 WR_PST = 0x0
2332 14:44:06.145682 DBI_WR = 0x0
2333 14:44:06.145786 DBI_RD = 0x0
2334 14:44:06.148858 OTF = 0x1
2335 14:44:06.152498 ===================================
2336 14:44:06.155842 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2337 14:44:06.158764 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2338 14:44:06.165919 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2339 14:44:06.168928 ===================================
2340 14:44:06.169011 LPDDR4 DRAM CONFIGURATION
2341 14:44:06.172277 ===================================
2342 14:44:06.176013 EX_ROW_EN[0] = 0x10
2343 14:44:06.176119 EX_ROW_EN[1] = 0x0
2344 14:44:06.179091 LP4Y_EN = 0x0
2345 14:44:06.179210 WORK_FSP = 0x0
2346 14:44:06.182312 WL = 0x4
2347 14:44:06.182421 RL = 0x4
2348 14:44:06.186125 BL = 0x2
2349 14:44:06.188850 RPST = 0x0
2350 14:44:06.188940 RD_PRE = 0x0
2351 14:44:06.192287 WR_PRE = 0x1
2352 14:44:06.192406 WR_PST = 0x0
2353 14:44:06.195446 DBI_WR = 0x0
2354 14:44:06.195551 DBI_RD = 0x0
2355 14:44:06.199106 OTF = 0x1
2356 14:44:06.202131 ===================================
2357 14:44:06.206033 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2358 14:44:06.209061 ==
2359 14:44:06.212518 Dram Type= 6, Freq= 0, CH_0, rank 0
2360 14:44:06.215779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 14:44:06.215893 ==
2362 14:44:06.218854 [Duty_Offset_Calibration]
2363 14:44:06.218962 B0:2 B1:0 CA:3
2364 14:44:06.219122
2365 14:44:06.222622 [DutyScan_Calibration_Flow] k_type=0
2366 14:44:06.231694
2367 14:44:06.231775 ==CLK 0==
2368 14:44:06.235135 Final CLK duty delay cell = 0
2369 14:44:06.238564 [0] MAX Duty = 5062%(X100), DQS PI = 20
2370 14:44:06.241922 [0] MIN Duty = 4875%(X100), DQS PI = 58
2371 14:44:06.242025 [0] AVG Duty = 4968%(X100)
2372 14:44:06.245279
2373 14:44:06.248332 CH0 CLK Duty spec in!! Max-Min= 187%
2374 14:44:06.251689 [DutyScan_Calibration_Flow] ====Done====
2375 14:44:06.251788
2376 14:44:06.254872 [DutyScan_Calibration_Flow] k_type=1
2377 14:44:06.270364
2378 14:44:06.270462 ==DQS 0 ==
2379 14:44:06.273469 Final DQS duty delay cell = 0
2380 14:44:06.276827 [0] MAX Duty = 5062%(X100), DQS PI = 12
2381 14:44:06.280419 [0] MIN Duty = 4907%(X100), DQS PI = 2
2382 14:44:06.280518 [0] AVG Duty = 4984%(X100)
2383 14:44:06.283727
2384 14:44:06.283825 ==DQS 1 ==
2385 14:44:06.286758 Final DQS duty delay cell = -4
2386 14:44:06.290246 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2387 14:44:06.293593 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2388 14:44:06.297086 [-4] AVG Duty = 4937%(X100)
2389 14:44:06.297166
2390 14:44:06.300005 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2391 14:44:06.300104
2392 14:44:06.303934 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2393 14:44:06.306851 [DutyScan_Calibration_Flow] ====Done====
2394 14:44:06.306926
2395 14:44:06.310352 [DutyScan_Calibration_Flow] k_type=3
2396 14:44:06.327743
2397 14:44:06.327857 ==DQM 0 ==
2398 14:44:06.331417 Final DQM duty delay cell = 0
2399 14:44:06.334369 [0] MAX Duty = 5124%(X100), DQS PI = 28
2400 14:44:06.337984 [0] MIN Duty = 4876%(X100), DQS PI = 48
2401 14:44:06.341735 [0] AVG Duty = 5000%(X100)
2402 14:44:06.341818
2403 14:44:06.341884 ==DQM 1 ==
2404 14:44:06.344465 Final DQM duty delay cell = 4
2405 14:44:06.347908 [4] MAX Duty = 5124%(X100), DQS PI = 52
2406 14:44:06.351562 [4] MIN Duty = 5000%(X100), DQS PI = 10
2407 14:44:06.354765 [4] AVG Duty = 5062%(X100)
2408 14:44:06.354852
2409 14:44:06.358226 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2410 14:44:06.358312
2411 14:44:06.361346 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2412 14:44:06.364726 [DutyScan_Calibration_Flow] ====Done====
2413 14:44:06.364843
2414 14:44:06.367700 [DutyScan_Calibration_Flow] k_type=2
2415 14:44:06.382922
2416 14:44:06.383010 ==DQ 0 ==
2417 14:44:06.386318 Final DQ duty delay cell = -4
2418 14:44:06.389764 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2419 14:44:06.393060 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2420 14:44:06.396071 [-4] AVG Duty = 4969%(X100)
2421 14:44:06.396155
2422 14:44:06.396220 ==DQ 1 ==
2423 14:44:06.399632 Final DQ duty delay cell = -4
2424 14:44:06.402925 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2425 14:44:06.406301 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2426 14:44:06.409213 [-4] AVG Duty = 4938%(X100)
2427 14:44:06.409296
2428 14:44:06.412566 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2429 14:44:06.412656
2430 14:44:06.416290 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2431 14:44:06.419368 [DutyScan_Calibration_Flow] ====Done====
2432 14:44:06.419476 ==
2433 14:44:06.422562 Dram Type= 6, Freq= 0, CH_1, rank 0
2434 14:44:06.426055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2435 14:44:06.426134 ==
2436 14:44:06.429433 [Duty_Offset_Calibration]
2437 14:44:06.429510 B0:1 B1:-2 CA:0
2438 14:44:06.429574
2439 14:44:06.432543 [DutyScan_Calibration_Flow] k_type=0
2440 14:44:06.443416
2441 14:44:06.443500 ==CLK 0==
2442 14:44:06.446837 Final CLK duty delay cell = 0
2443 14:44:06.450492 [0] MAX Duty = 5031%(X100), DQS PI = 18
2444 14:44:06.453382 [0] MIN Duty = 4844%(X100), DQS PI = 58
2445 14:44:06.453467 [0] AVG Duty = 4937%(X100)
2446 14:44:06.456771
2447 14:44:06.460109 CH1 CLK Duty spec in!! Max-Min= 187%
2448 14:44:06.463333 [DutyScan_Calibration_Flow] ====Done====
2449 14:44:06.463417
2450 14:44:06.466658 [DutyScan_Calibration_Flow] k_type=1
2451 14:44:06.481840
2452 14:44:06.481944 ==DQS 0 ==
2453 14:44:06.485729 Final DQS duty delay cell = -4
2454 14:44:06.488987 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2455 14:44:06.492040 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2456 14:44:06.495257 [-4] AVG Duty = 4953%(X100)
2457 14:44:06.495360
2458 14:44:06.495453 ==DQS 1 ==
2459 14:44:06.498826 Final DQS duty delay cell = 0
2460 14:44:06.501870 [0] MAX Duty = 5062%(X100), DQS PI = 0
2461 14:44:06.505156 [0] MIN Duty = 4844%(X100), DQS PI = 26
2462 14:44:06.508760 [0] AVG Duty = 4953%(X100)
2463 14:44:06.508859
2464 14:44:06.511921 CH1 DQS 0 Duty spec in!! Max-Min= 155%
2465 14:44:06.512034
2466 14:44:06.515335 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2467 14:44:06.518789 [DutyScan_Calibration_Flow] ====Done====
2468 14:44:06.518890
2469 14:44:06.522345 [DutyScan_Calibration_Flow] k_type=3
2470 14:44:06.538945
2471 14:44:06.539044 ==DQM 0 ==
2472 14:44:06.542121 Final DQM duty delay cell = 0
2473 14:44:06.546046 [0] MAX Duty = 5000%(X100), DQS PI = 20
2474 14:44:06.548987 [0] MIN Duty = 4844%(X100), DQS PI = 54
2475 14:44:06.549068 [0] AVG Duty = 4922%(X100)
2476 14:44:06.551977
2477 14:44:06.552083 ==DQM 1 ==
2478 14:44:06.555345 Final DQM duty delay cell = 0
2479 14:44:06.558892 [0] MAX Duty = 5031%(X100), DQS PI = 36
2480 14:44:06.562033 [0] MIN Duty = 4907%(X100), DQS PI = 2
2481 14:44:06.562116 [0] AVG Duty = 4969%(X100)
2482 14:44:06.565349
2483 14:44:06.568777 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2484 14:44:06.568859
2485 14:44:06.571862 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2486 14:44:06.575136 [DutyScan_Calibration_Flow] ====Done====
2487 14:44:06.575212
2488 14:44:06.578463 [DutyScan_Calibration_Flow] k_type=2
2489 14:44:06.595566
2490 14:44:06.595653 ==DQ 0 ==
2491 14:44:06.598409 Final DQ duty delay cell = 0
2492 14:44:06.601909 [0] MAX Duty = 5093%(X100), DQS PI = 20
2493 14:44:06.605249 [0] MIN Duty = 4938%(X100), DQS PI = 54
2494 14:44:06.605345 [0] AVG Duty = 5015%(X100)
2495 14:44:06.605413
2496 14:44:06.609002 ==DQ 1 ==
2497 14:44:06.612524 Final DQ duty delay cell = 0
2498 14:44:06.615146 [0] MAX Duty = 5125%(X100), DQS PI = 36
2499 14:44:06.618509 [0] MIN Duty = 4969%(X100), DQS PI = 26
2500 14:44:06.618588 [0] AVG Duty = 5047%(X100)
2501 14:44:06.618688
2502 14:44:06.622521 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2503 14:44:06.622625
2504 14:44:06.625428 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2505 14:44:06.631735 [DutyScan_Calibration_Flow] ====Done====
2506 14:44:06.635274 nWR fixed to 30
2507 14:44:06.635379 [ModeRegInit_LP4] CH0 RK0
2508 14:44:06.638664 [ModeRegInit_LP4] CH0 RK1
2509 14:44:06.641574 [ModeRegInit_LP4] CH1 RK0
2510 14:44:06.641674 [ModeRegInit_LP4] CH1 RK1
2511 14:44:06.644990 match AC timing 7
2512 14:44:06.648848 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2513 14:44:06.651995 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2514 14:44:06.658434 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2515 14:44:06.661790 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2516 14:44:06.668484 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2517 14:44:06.668626 ==
2518 14:44:06.672074 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 14:44:06.675251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 14:44:06.675328 ==
2521 14:44:06.681769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 14:44:06.685256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2523 14:44:06.695025 [CA 0] Center 40 (10~71) winsize 62
2524 14:44:06.698811 [CA 1] Center 39 (9~70) winsize 62
2525 14:44:06.701811 [CA 2] Center 36 (6~66) winsize 61
2526 14:44:06.705593 [CA 3] Center 35 (5~66) winsize 62
2527 14:44:06.708511 [CA 4] Center 34 (4~65) winsize 62
2528 14:44:06.712276 [CA 5] Center 33 (3~64) winsize 62
2529 14:44:06.712403
2530 14:44:06.715260 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2531 14:44:06.715367
2532 14:44:06.718785 [CATrainingPosCal] consider 1 rank data
2533 14:44:06.722147 u2DelayCellTimex100 = 270/100 ps
2534 14:44:06.725230 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2535 14:44:06.728638 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2536 14:44:06.735297 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2537 14:44:06.738993 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 14:44:06.742308 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2539 14:44:06.745204 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2540 14:44:06.745286
2541 14:44:06.748445 CA PerBit enable=1, Macro0, CA PI delay=33
2542 14:44:06.748554
2543 14:44:06.751828 [CBTSetCACLKResult] CA Dly = 33
2544 14:44:06.751910 CS Dly: 7 (0~38)
2545 14:44:06.755191 ==
2546 14:44:06.755288 Dram Type= 6, Freq= 0, CH_0, rank 1
2547 14:44:06.762114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 14:44:06.762197 ==
2549 14:44:06.765464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2550 14:44:06.772340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2551 14:44:06.781370 [CA 0] Center 40 (10~70) winsize 61
2552 14:44:06.784913 [CA 1] Center 40 (10~70) winsize 61
2553 14:44:06.788314 [CA 2] Center 35 (5~66) winsize 62
2554 14:44:06.791460 [CA 3] Center 35 (5~66) winsize 62
2555 14:44:06.794762 [CA 4] Center 34 (4~65) winsize 62
2556 14:44:06.797983 [CA 5] Center 33 (3~63) winsize 61
2557 14:44:06.798098
2558 14:44:06.801193 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2559 14:44:06.801292
2560 14:44:06.805078 [CATrainingPosCal] consider 2 rank data
2561 14:44:06.808376 u2DelayCellTimex100 = 270/100 ps
2562 14:44:06.811314 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2563 14:44:06.818104 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2564 14:44:06.821579 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2565 14:44:06.824944 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2566 14:44:06.827866 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2567 14:44:06.831413 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2568 14:44:06.831495
2569 14:44:06.834343 CA PerBit enable=1, Macro0, CA PI delay=33
2570 14:44:06.834467
2571 14:44:06.837719 [CBTSetCACLKResult] CA Dly = 33
2572 14:44:06.841486 CS Dly: 8 (0~40)
2573 14:44:06.841593
2574 14:44:06.844451 ----->DramcWriteLeveling(PI) begin...
2575 14:44:06.844568 ==
2576 14:44:06.848285 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 14:44:06.851517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 14:44:06.851600 ==
2579 14:44:06.854406 Write leveling (Byte 0): 32 => 32
2580 14:44:06.857801 Write leveling (Byte 1): 30 => 30
2581 14:44:06.861193 DramcWriteLeveling(PI) end<-----
2582 14:44:06.861347
2583 14:44:06.861470 ==
2584 14:44:06.864483 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 14:44:06.867974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 14:44:06.868081 ==
2587 14:44:06.871168 [Gating] SW mode calibration
2588 14:44:06.878009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2589 14:44:06.884397 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2590 14:44:06.887840 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 14:44:06.890960 0 15 4 | B1->B0 | 2828 3333 | 0 1 | (0 0) (1 1)
2592 14:44:06.897758 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 14:44:06.900873 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 14:44:06.904303 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 14:44:06.911048 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 14:44:06.914594 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 14:44:06.917786 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
2598 14:44:06.924701 1 0 0 | B1->B0 | 3333 2727 | 1 1 | (0 0) (1 0)
2599 14:44:06.927419 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2600 14:44:06.931440 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 14:44:06.934388 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 14:44:06.941393 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 14:44:06.944415 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 14:44:06.947941 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 14:44:06.954612 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2606 14:44:06.957840 1 1 0 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
2607 14:44:06.961349 1 1 4 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
2608 14:44:06.967938 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 14:44:06.971369 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 14:44:06.974730 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 14:44:06.980808 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 14:44:06.984397 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 14:44:06.987622 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 14:44:06.994161 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2615 14:44:06.997629 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 14:44:07.001203 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 14:44:07.007956 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 14:44:07.010992 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 14:44:07.014544 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 14:44:07.017926 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 14:44:07.024749 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 14:44:07.028032 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 14:44:07.031195 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 14:44:07.037607 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 14:44:07.041204 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 14:44:07.044808 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 14:44:07.051322 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 14:44:07.054715 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 14:44:07.057518 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2630 14:44:07.064461 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2631 14:44:07.067732 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2632 14:44:07.070761 Total UI for P1: 0, mck2ui 16
2633 14:44:07.073953 best dqsien dly found for B0: ( 1, 3, 30)
2634 14:44:07.077783 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 14:44:07.080640 Total UI for P1: 0, mck2ui 16
2636 14:44:07.084436 best dqsien dly found for B1: ( 1, 4, 4)
2637 14:44:07.087304 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2638 14:44:07.090869 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2639 14:44:07.090953
2640 14:44:07.097567 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2641 14:44:07.100712 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2642 14:44:07.100823 [Gating] SW calibration Done
2643 14:44:07.104338 ==
2644 14:44:07.104422 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 14:44:07.110732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 14:44:07.110817 ==
2647 14:44:07.110884 RX Vref Scan: 0
2648 14:44:07.110945
2649 14:44:07.114575 RX Vref 0 -> 0, step: 1
2650 14:44:07.114658
2651 14:44:07.117826 RX Delay -40 -> 252, step: 8
2652 14:44:07.120916 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2653 14:44:07.124474 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2654 14:44:07.127549 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2655 14:44:07.134630 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2656 14:44:07.137752 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2657 14:44:07.141299 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2658 14:44:07.144509 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2659 14:44:07.147960 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2660 14:44:07.150887 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2661 14:44:07.157715 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2662 14:44:07.160716 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2663 14:44:07.164209 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2664 14:44:07.167444 iDelay=200, Bit 12, Center 103 (32 ~ 175) 144
2665 14:44:07.171166 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2666 14:44:07.177773 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2667 14:44:07.181056 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2668 14:44:07.181152 ==
2669 14:44:07.184490 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 14:44:07.187699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 14:44:07.187783 ==
2672 14:44:07.190878 DQS Delay:
2673 14:44:07.190994 DQS0 = 0, DQS1 = 0
2674 14:44:07.191059 DQM Delay:
2675 14:44:07.194787 DQM0 = 112, DQM1 = 101
2676 14:44:07.194869 DQ Delay:
2677 14:44:07.197522 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2678 14:44:07.201310 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2679 14:44:07.204636 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2680 14:44:07.210968 DQ12 =103, DQ13 =111, DQ14 =115, DQ15 =111
2681 14:44:07.211050
2682 14:44:07.211140
2683 14:44:07.211272 ==
2684 14:44:07.214456 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 14:44:07.217350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 14:44:07.217439 ==
2687 14:44:07.217503
2688 14:44:07.217564
2689 14:44:07.221249 TX Vref Scan disable
2690 14:44:07.221331 == TX Byte 0 ==
2691 14:44:07.227420 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2692 14:44:07.231188 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2693 14:44:07.231290 == TX Byte 1 ==
2694 14:44:07.237391 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2695 14:44:07.240722 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2696 14:44:07.240804 ==
2697 14:44:07.244119 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 14:44:07.247810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 14:44:07.247892 ==
2700 14:44:07.260151 TX Vref=22, minBit 4, minWin=25, winSum=414
2701 14:44:07.263620 TX Vref=24, minBit 1, minWin=26, winSum=423
2702 14:44:07.267005 TX Vref=26, minBit 7, minWin=26, winSum=430
2703 14:44:07.269847 TX Vref=28, minBit 4, minWin=26, winSum=433
2704 14:44:07.273302 TX Vref=30, minBit 1, minWin=27, winSum=437
2705 14:44:07.276549 TX Vref=32, minBit 8, minWin=26, winSum=428
2706 14:44:07.283456 [TxChooseVref] Worse bit 1, Min win 27, Win sum 437, Final Vref 30
2707 14:44:07.283539
2708 14:44:07.286652 Final TX Range 1 Vref 30
2709 14:44:07.286733
2710 14:44:07.286805 ==
2711 14:44:07.289997 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 14:44:07.293332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 14:44:07.293427 ==
2714 14:44:07.293493
2715 14:44:07.296628
2716 14:44:07.296708 TX Vref Scan disable
2717 14:44:07.300006 == TX Byte 0 ==
2718 14:44:07.303383 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2719 14:44:07.306546 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2720 14:44:07.309866 == TX Byte 1 ==
2721 14:44:07.313412 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2722 14:44:07.316851 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2723 14:44:07.317001
2724 14:44:07.319767 [DATLAT]
2725 14:44:07.319848 Freq=1200, CH0 RK0
2726 14:44:07.319913
2727 14:44:07.323381 DATLAT Default: 0xd
2728 14:44:07.323556 0, 0xFFFF, sum = 0
2729 14:44:07.326757 1, 0xFFFF, sum = 0
2730 14:44:07.326840 2, 0xFFFF, sum = 0
2731 14:44:07.330063 3, 0xFFFF, sum = 0
2732 14:44:07.330158 4, 0xFFFF, sum = 0
2733 14:44:07.333542 5, 0xFFFF, sum = 0
2734 14:44:07.333639 6, 0xFFFF, sum = 0
2735 14:44:07.337046 7, 0xFFFF, sum = 0
2736 14:44:07.337129 8, 0xFFFF, sum = 0
2737 14:44:07.340228 9, 0xFFFF, sum = 0
2738 14:44:07.343471 10, 0xFFFF, sum = 0
2739 14:44:07.343580 11, 0xFFFF, sum = 0
2740 14:44:07.346845 12, 0x0, sum = 1
2741 14:44:07.346921 13, 0x0, sum = 2
2742 14:44:07.350281 14, 0x0, sum = 3
2743 14:44:07.350356 15, 0x0, sum = 4
2744 14:44:07.350419 best_step = 13
2745 14:44:07.350495
2746 14:44:07.353504 ==
2747 14:44:07.353573 Dram Type= 6, Freq= 0, CH_0, rank 0
2748 14:44:07.359788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2749 14:44:07.359867 ==
2750 14:44:07.359953 RX Vref Scan: 1
2751 14:44:07.360014
2752 14:44:07.363529 Set Vref Range= 32 -> 127
2753 14:44:07.363602
2754 14:44:07.366514 RX Vref 32 -> 127, step: 1
2755 14:44:07.366587
2756 14:44:07.370492 RX Delay -37 -> 252, step: 4
2757 14:44:07.370565
2758 14:44:07.373418 Set Vref, RX VrefLevel [Byte0]: 32
2759 14:44:07.376854 [Byte1]: 32
2760 14:44:07.376972
2761 14:44:07.379735 Set Vref, RX VrefLevel [Byte0]: 33
2762 14:44:07.383261 [Byte1]: 33
2763 14:44:07.383343
2764 14:44:07.386483 Set Vref, RX VrefLevel [Byte0]: 34
2765 14:44:07.390078 [Byte1]: 34
2766 14:44:07.394406
2767 14:44:07.397951 Set Vref, RX VrefLevel [Byte0]: 35
2768 14:44:07.401042 [Byte1]: 35
2769 14:44:07.401126
2770 14:44:07.404569 Set Vref, RX VrefLevel [Byte0]: 36
2771 14:44:07.407873 [Byte1]: 36
2772 14:44:07.407957
2773 14:44:07.411037 Set Vref, RX VrefLevel [Byte0]: 37
2774 14:44:07.414492 [Byte1]: 37
2775 14:44:07.418394
2776 14:44:07.418477 Set Vref, RX VrefLevel [Byte0]: 38
2777 14:44:07.421865 [Byte1]: 38
2778 14:44:07.426510
2779 14:44:07.426593 Set Vref, RX VrefLevel [Byte0]: 39
2780 14:44:07.429884 [Byte1]: 39
2781 14:44:07.434339
2782 14:44:07.434422 Set Vref, RX VrefLevel [Byte0]: 40
2783 14:44:07.437521 [Byte1]: 40
2784 14:44:07.442596
2785 14:44:07.442680 Set Vref, RX VrefLevel [Byte0]: 41
2786 14:44:07.445587 [Byte1]: 41
2787 14:44:07.450617
2788 14:44:07.450704 Set Vref, RX VrefLevel [Byte0]: 42
2789 14:44:07.453913 [Byte1]: 42
2790 14:44:07.458248
2791 14:44:07.458334 Set Vref, RX VrefLevel [Byte0]: 43
2792 14:44:07.461541 [Byte1]: 43
2793 14:44:07.466452
2794 14:44:07.466535 Set Vref, RX VrefLevel [Byte0]: 44
2795 14:44:07.469942 [Byte1]: 44
2796 14:44:07.474543
2797 14:44:07.474626 Set Vref, RX VrefLevel [Byte0]: 45
2798 14:44:07.478031 [Byte1]: 45
2799 14:44:07.482716
2800 14:44:07.482800 Set Vref, RX VrefLevel [Byte0]: 46
2801 14:44:07.486151 [Byte1]: 46
2802 14:44:07.490271
2803 14:44:07.490352 Set Vref, RX VrefLevel [Byte0]: 47
2804 14:44:07.493473 [Byte1]: 47
2805 14:44:07.498308
2806 14:44:07.498418 Set Vref, RX VrefLevel [Byte0]: 48
2807 14:44:07.501734 [Byte1]: 48
2808 14:44:07.506602
2809 14:44:07.506705 Set Vref, RX VrefLevel [Byte0]: 49
2810 14:44:07.509818 [Byte1]: 49
2811 14:44:07.514495
2812 14:44:07.514591 Set Vref, RX VrefLevel [Byte0]: 50
2813 14:44:07.517897 [Byte1]: 50
2814 14:44:07.522599
2815 14:44:07.522683 Set Vref, RX VrefLevel [Byte0]: 51
2816 14:44:07.525849 [Byte1]: 51
2817 14:44:07.530381
2818 14:44:07.530462 Set Vref, RX VrefLevel [Byte0]: 52
2819 14:44:07.533634 [Byte1]: 52
2820 14:44:07.538638
2821 14:44:07.538719 Set Vref, RX VrefLevel [Byte0]: 53
2822 14:44:07.541485 [Byte1]: 53
2823 14:44:07.546204
2824 14:44:07.546315 Set Vref, RX VrefLevel [Byte0]: 54
2825 14:44:07.549532 [Byte1]: 54
2826 14:44:07.554616
2827 14:44:07.554724 Set Vref, RX VrefLevel [Byte0]: 55
2828 14:44:07.557690 [Byte1]: 55
2829 14:44:07.562292
2830 14:44:07.562373 Set Vref, RX VrefLevel [Byte0]: 56
2831 14:44:07.565621 [Byte1]: 56
2832 14:44:07.570641
2833 14:44:07.570723 Set Vref, RX VrefLevel [Byte0]: 57
2834 14:44:07.573914 [Byte1]: 57
2835 14:44:07.578761
2836 14:44:07.578843 Set Vref, RX VrefLevel [Byte0]: 58
2837 14:44:07.581588 [Byte1]: 58
2838 14:44:07.586288
2839 14:44:07.586370 Set Vref, RX VrefLevel [Byte0]: 59
2840 14:44:07.589740 [Byte1]: 59
2841 14:44:07.594866
2842 14:44:07.594947 Set Vref, RX VrefLevel [Byte0]: 60
2843 14:44:07.597566 [Byte1]: 60
2844 14:44:07.602408
2845 14:44:07.602490 Set Vref, RX VrefLevel [Byte0]: 61
2846 14:44:07.605880 [Byte1]: 61
2847 14:44:07.610340
2848 14:44:07.610421 Set Vref, RX VrefLevel [Byte0]: 62
2849 14:44:07.613640 [Byte1]: 62
2850 14:44:07.618566
2851 14:44:07.618651 Set Vref, RX VrefLevel [Byte0]: 63
2852 14:44:07.622114 [Byte1]: 63
2853 14:44:07.626501
2854 14:44:07.626583 Set Vref, RX VrefLevel [Byte0]: 64
2855 14:44:07.629905 [Byte1]: 64
2856 14:44:07.634357
2857 14:44:07.634438 Set Vref, RX VrefLevel [Byte0]: 65
2858 14:44:07.637840 [Byte1]: 65
2859 14:44:07.642640
2860 14:44:07.642722 Set Vref, RX VrefLevel [Byte0]: 66
2861 14:44:07.645935 [Byte1]: 66
2862 14:44:07.650493
2863 14:44:07.650603 Set Vref, RX VrefLevel [Byte0]: 67
2864 14:44:07.653665 [Byte1]: 67
2865 14:44:07.658226
2866 14:44:07.658339 Set Vref, RX VrefLevel [Byte0]: 68
2867 14:44:07.661639 [Byte1]: 68
2868 14:44:07.666546
2869 14:44:07.666684 Set Vref, RX VrefLevel [Byte0]: 69
2870 14:44:07.669617 [Byte1]: 69
2871 14:44:07.674740
2872 14:44:07.674849 Set Vref, RX VrefLevel [Byte0]: 70
2873 14:44:07.677839 [Byte1]: 70
2874 14:44:07.682604
2875 14:44:07.682753 Set Vref, RX VrefLevel [Byte0]: 71
2876 14:44:07.685860 [Byte1]: 71
2877 14:44:07.690666
2878 14:44:07.690780 Set Vref, RX VrefLevel [Byte0]: 72
2879 14:44:07.693654 [Byte1]: 72
2880 14:44:07.698278
2881 14:44:07.698364 Set Vref, RX VrefLevel [Byte0]: 73
2882 14:44:07.701708 [Byte1]: 73
2883 14:44:07.706847
2884 14:44:07.706932 Set Vref, RX VrefLevel [Byte0]: 74
2885 14:44:07.709626 [Byte1]: 74
2886 14:44:07.714832
2887 14:44:07.714915 Set Vref, RX VrefLevel [Byte0]: 75
2888 14:44:07.717624 [Byte1]: 75
2889 14:44:07.722212
2890 14:44:07.722348 Set Vref, RX VrefLevel [Byte0]: 76
2891 14:44:07.725843 [Byte1]: 76
2892 14:44:07.730197
2893 14:44:07.730298 Final RX Vref Byte 0 = 62 to rank0
2894 14:44:07.733744 Final RX Vref Byte 1 = 46 to rank0
2895 14:44:07.737381 Final RX Vref Byte 0 = 62 to rank1
2896 14:44:07.740360 Final RX Vref Byte 1 = 46 to rank1==
2897 14:44:07.743834 Dram Type= 6, Freq= 0, CH_0, rank 0
2898 14:44:07.750626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 14:44:07.750712 ==
2900 14:44:07.750779 DQS Delay:
2901 14:44:07.750841 DQS0 = 0, DQS1 = 0
2902 14:44:07.753510 DQM Delay:
2903 14:44:07.753587 DQM0 = 112, DQM1 = 98
2904 14:44:07.756924 DQ Delay:
2905 14:44:07.760295 DQ0 =110, DQ1 =114, DQ2 =110, DQ3 =108
2906 14:44:07.763855 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2907 14:44:07.766794 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2908 14:44:07.770204 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2909 14:44:07.770290
2910 14:44:07.770369
2911 14:44:07.777141 [DQSOSCAuto] RK0, (LSB)MR18= 0xfafa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2912 14:44:07.780254 CH0 RK0: MR19=303, MR18=FAFA
2913 14:44:07.787046 CH0_RK0: MR19=0x303, MR18=0xFAFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2914 14:44:07.787132
2915 14:44:07.790352 ----->DramcWriteLeveling(PI) begin...
2916 14:44:07.790458 ==
2917 14:44:07.793756 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 14:44:07.796674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 14:44:07.799993 ==
2920 14:44:07.800092 Write leveling (Byte 0): 33 => 33
2921 14:44:07.803470 Write leveling (Byte 1): 30 => 30
2922 14:44:07.806923 DramcWriteLeveling(PI) end<-----
2923 14:44:07.807000
2924 14:44:07.807065 ==
2925 14:44:07.810326 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 14:44:07.817109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 14:44:07.817199 ==
2928 14:44:07.817286 [Gating] SW mode calibration
2929 14:44:07.827214 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2930 14:44:07.830177 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2931 14:44:07.833602 0 15 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2932 14:44:07.840112 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 14:44:07.843498 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 14:44:07.846560 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 14:44:07.853368 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 14:44:07.856777 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2937 14:44:07.860298 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2938 14:44:07.867143 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
2939 14:44:07.870477 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2940 14:44:07.873355 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 14:44:07.879869 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 14:44:07.883246 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 14:44:07.886695 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 14:44:07.893309 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2945 14:44:07.896726 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2946 14:44:07.899942 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
2947 14:44:07.906725 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
2948 14:44:07.910108 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 14:44:07.913293 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 14:44:07.920388 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 14:44:07.923208 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 14:44:07.926709 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 14:44:07.930080 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 14:44:07.936857 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2955 14:44:07.940577 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2956 14:44:07.943762 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 14:44:07.950116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 14:44:07.953643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 14:44:07.956616 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 14:44:07.963533 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 14:44:07.967103 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 14:44:07.970136 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 14:44:07.977051 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 14:44:07.980044 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 14:44:07.983429 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 14:44:07.989923 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 14:44:07.993631 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 14:44:07.996828 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 14:44:08.003311 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 14:44:08.006708 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2971 14:44:08.010257 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2972 14:44:08.013698 Total UI for P1: 0, mck2ui 16
2973 14:44:08.016889 best dqsien dly found for B0: ( 1, 3, 28)
2974 14:44:08.020253 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 14:44:08.023635 Total UI for P1: 0, mck2ui 16
2976 14:44:08.026782 best dqsien dly found for B1: ( 1, 4, 0)
2977 14:44:08.030232 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2978 14:44:08.033652 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2979 14:44:08.033784
2980 14:44:08.040294 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2981 14:44:08.043420 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2982 14:44:08.046881 [Gating] SW calibration Done
2983 14:44:08.047008 ==
2984 14:44:08.050128 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 14:44:08.053774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 14:44:08.053862 ==
2987 14:44:08.053948 RX Vref Scan: 0
2988 14:44:08.054030
2989 14:44:08.057099 RX Vref 0 -> 0, step: 1
2990 14:44:08.057185
2991 14:44:08.060365 RX Delay -40 -> 252, step: 8
2992 14:44:08.063606 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2993 14:44:08.066945 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2994 14:44:08.070382 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2995 14:44:08.077189 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2996 14:44:08.080511 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2997 14:44:08.083409 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2998 14:44:08.086993 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2999 14:44:08.089978 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3000 14:44:08.096943 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3001 14:44:08.099994 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
3002 14:44:08.103432 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3003 14:44:08.106603 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3004 14:44:08.110220 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
3005 14:44:08.116842 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
3006 14:44:08.119938 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3007 14:44:08.123149 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3008 14:44:08.123271 ==
3009 14:44:08.127178 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 14:44:08.130231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 14:44:08.130357 ==
3012 14:44:08.133132 DQS Delay:
3013 14:44:08.133249 DQS0 = 0, DQS1 = 0
3014 14:44:08.136692 DQM Delay:
3015 14:44:08.136809 DQM0 = 111, DQM1 = 101
3016 14:44:08.140107 DQ Delay:
3017 14:44:08.143559 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
3018 14:44:08.146862 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3019 14:44:08.149919 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3020 14:44:08.153411 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
3021 14:44:08.153494
3022 14:44:08.153558
3023 14:44:08.153618 ==
3024 14:44:08.156903 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 14:44:08.160218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 14:44:08.160327 ==
3027 14:44:08.160420
3028 14:44:08.160509
3029 14:44:08.163857 TX Vref Scan disable
3030 14:44:08.166771 == TX Byte 0 ==
3031 14:44:08.170032 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3032 14:44:08.173172 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3033 14:44:08.176842 == TX Byte 1 ==
3034 14:44:08.179809 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3035 14:44:08.183316 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3036 14:44:08.183423 ==
3037 14:44:08.186961 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 14:44:08.189769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 14:44:08.189852 ==
3040 14:44:08.203547 TX Vref=22, minBit 0, minWin=26, winSum=427
3041 14:44:08.206660 TX Vref=24, minBit 1, minWin=26, winSum=427
3042 14:44:08.209862 TX Vref=26, minBit 8, minWin=26, winSum=435
3043 14:44:08.213408 TX Vref=28, minBit 2, minWin=26, winSum=437
3044 14:44:08.216381 TX Vref=30, minBit 1, minWin=26, winSum=440
3045 14:44:08.219948 TX Vref=32, minBit 8, minWin=26, winSum=436
3046 14:44:08.226526 [TxChooseVref] Worse bit 1, Min win 26, Win sum 440, Final Vref 30
3047 14:44:08.226640
3048 14:44:08.230010 Final TX Range 1 Vref 30
3049 14:44:08.230089
3050 14:44:08.230152 ==
3051 14:44:08.233243 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 14:44:08.236397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 14:44:08.236511 ==
3054 14:44:08.236604
3055 14:44:08.239890
3056 14:44:08.239963 TX Vref Scan disable
3057 14:44:08.243517 == TX Byte 0 ==
3058 14:44:08.246881 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3059 14:44:08.249679 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3060 14:44:08.253109 == TX Byte 1 ==
3061 14:44:08.256750 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3062 14:44:08.259773 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3063 14:44:08.259849
3064 14:44:08.263418 [DATLAT]
3065 14:44:08.263492 Freq=1200, CH0 RK1
3066 14:44:08.263555
3067 14:44:08.266356 DATLAT Default: 0xd
3068 14:44:08.266426 0, 0xFFFF, sum = 0
3069 14:44:08.269843 1, 0xFFFF, sum = 0
3070 14:44:08.269951 2, 0xFFFF, sum = 0
3071 14:44:08.273290 3, 0xFFFF, sum = 0
3072 14:44:08.273400 4, 0xFFFF, sum = 0
3073 14:44:08.276767 5, 0xFFFF, sum = 0
3074 14:44:08.276893 6, 0xFFFF, sum = 0
3075 14:44:08.279628 7, 0xFFFF, sum = 0
3076 14:44:08.283485 8, 0xFFFF, sum = 0
3077 14:44:08.283568 9, 0xFFFF, sum = 0
3078 14:44:08.286798 10, 0xFFFF, sum = 0
3079 14:44:08.286880 11, 0xFFFF, sum = 0
3080 14:44:08.289780 12, 0x0, sum = 1
3081 14:44:08.289866 13, 0x0, sum = 2
3082 14:44:08.293531 14, 0x0, sum = 3
3083 14:44:08.293616 15, 0x0, sum = 4
3084 14:44:08.293683 best_step = 13
3085 14:44:08.293744
3086 14:44:08.296437 ==
3087 14:44:08.299801 Dram Type= 6, Freq= 0, CH_0, rank 1
3088 14:44:08.303367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 14:44:08.303489 ==
3090 14:44:08.303591 RX Vref Scan: 0
3091 14:44:08.303697
3092 14:44:08.306139 RX Vref 0 -> 0, step: 1
3093 14:44:08.306262
3094 14:44:08.309769 RX Delay -37 -> 252, step: 4
3095 14:44:08.312968 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3096 14:44:08.319906 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3097 14:44:08.323203 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3098 14:44:08.326577 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3099 14:44:08.330184 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3100 14:44:08.333221 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3101 14:44:08.339597 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3102 14:44:08.343248 iDelay=195, Bit 7, Center 118 (47 ~ 190) 144
3103 14:44:08.346549 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3104 14:44:08.349509 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3105 14:44:08.352958 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3106 14:44:08.356469 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3107 14:44:08.363308 iDelay=195, Bit 12, Center 106 (35 ~ 178) 144
3108 14:44:08.366629 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3109 14:44:08.369810 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3110 14:44:08.373107 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3111 14:44:08.373215 ==
3112 14:44:08.376381 Dram Type= 6, Freq= 0, CH_0, rank 1
3113 14:44:08.383231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 14:44:08.383341 ==
3115 14:44:08.383409 DQS Delay:
3116 14:44:08.386169 DQS0 = 0, DQS1 = 0
3117 14:44:08.386250 DQM Delay:
3118 14:44:08.386315 DQM0 = 111, DQM1 = 98
3119 14:44:08.389610 DQ Delay:
3120 14:44:08.392876 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3121 14:44:08.396438 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3122 14:44:08.399512 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3123 14:44:08.403091 DQ12 =106, DQ13 =106, DQ14 =112, DQ15 =108
3124 14:44:08.403199
3125 14:44:08.403265
3126 14:44:08.409737 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3127 14:44:08.413043 CH0 RK1: MR19=403, MR18=10F7
3128 14:44:08.420063 CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26
3129 14:44:08.423365 [RxdqsGatingPostProcess] freq 1200
3130 14:44:08.429524 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3131 14:44:08.433035 best DQS0 dly(2T, 0.5T) = (0, 11)
3132 14:44:08.433112 best DQS1 dly(2T, 0.5T) = (0, 12)
3133 14:44:08.436431 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3134 14:44:08.439786 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3135 14:44:08.442728 best DQS0 dly(2T, 0.5T) = (0, 11)
3136 14:44:08.446533 best DQS1 dly(2T, 0.5T) = (0, 12)
3137 14:44:08.449457 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3138 14:44:08.453203 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3139 14:44:08.456572 Pre-setting of DQS Precalculation
3140 14:44:08.463458 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3141 14:44:08.463541 ==
3142 14:44:08.466386 Dram Type= 6, Freq= 0, CH_1, rank 0
3143 14:44:08.469981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 14:44:08.470088 ==
3145 14:44:08.476195 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 14:44:08.479610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3147 14:44:08.489230 [CA 0] Center 37 (8~67) winsize 60
3148 14:44:08.492372 [CA 1] Center 37 (7~68) winsize 62
3149 14:44:08.495791 [CA 2] Center 34 (4~64) winsize 61
3150 14:44:08.499250 [CA 3] Center 33 (3~64) winsize 62
3151 14:44:08.502541 [CA 4] Center 34 (4~64) winsize 61
3152 14:44:08.505875 [CA 5] Center 33 (3~63) winsize 61
3153 14:44:08.505958
3154 14:44:08.508919 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3155 14:44:08.509002
3156 14:44:08.512135 [CATrainingPosCal] consider 1 rank data
3157 14:44:08.515502 u2DelayCellTimex100 = 270/100 ps
3158 14:44:08.519141 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3159 14:44:08.525393 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3160 14:44:08.528813 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 14:44:08.532064 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3162 14:44:08.535557 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 14:44:08.538811 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3164 14:44:08.538932
3165 14:44:08.542619 CA PerBit enable=1, Macro0, CA PI delay=33
3166 14:44:08.542733
3167 14:44:08.545633 [CBTSetCACLKResult] CA Dly = 33
3168 14:44:08.545745 CS Dly: 6 (0~37)
3169 14:44:08.548961 ==
3170 14:44:08.552082 Dram Type= 6, Freq= 0, CH_1, rank 1
3171 14:44:08.555629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 14:44:08.555729 ==
3173 14:44:08.558704 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3174 14:44:08.565417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3175 14:44:08.574799 [CA 0] Center 38 (8~68) winsize 61
3176 14:44:08.578081 [CA 1] Center 37 (7~68) winsize 62
3177 14:44:08.581173 [CA 2] Center 34 (4~65) winsize 62
3178 14:44:08.584573 [CA 3] Center 33 (3~64) winsize 62
3179 14:44:08.587939 [CA 4] Center 34 (4~65) winsize 62
3180 14:44:08.591134 [CA 5] Center 33 (3~63) winsize 61
3181 14:44:08.591248
3182 14:44:08.594643 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3183 14:44:08.594777
3184 14:44:08.597995 [CATrainingPosCal] consider 2 rank data
3185 14:44:08.601322 u2DelayCellTimex100 = 270/100 ps
3186 14:44:08.604590 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3187 14:44:08.607928 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3188 14:44:08.614683 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3189 14:44:08.618036 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3190 14:44:08.621433 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3191 14:44:08.624331 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3192 14:44:08.624442
3193 14:44:08.627866 CA PerBit enable=1, Macro0, CA PI delay=33
3194 14:44:08.627970
3195 14:44:08.631133 [CBTSetCACLKResult] CA Dly = 33
3196 14:44:08.631242 CS Dly: 7 (0~40)
3197 14:44:08.631335
3198 14:44:08.634586 ----->DramcWriteLeveling(PI) begin...
3199 14:44:08.638097 ==
3200 14:44:08.641127 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 14:44:08.644583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 14:44:08.644727 ==
3203 14:44:08.647457 Write leveling (Byte 0): 24 => 24
3204 14:44:08.651344 Write leveling (Byte 1): 28 => 28
3205 14:44:08.654642 DramcWriteLeveling(PI) end<-----
3206 14:44:08.654764
3207 14:44:08.654863 ==
3208 14:44:08.658102 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 14:44:08.660916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 14:44:08.661008 ==
3211 14:44:08.664268 [Gating] SW mode calibration
3212 14:44:08.671139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3213 14:44:08.677888 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3214 14:44:08.680772 0 15 0 | B1->B0 | 2d2d 2727 | 0 1 | (0 0) (1 1)
3215 14:44:08.684383 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 14:44:08.690762 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 14:44:08.694297 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 14:44:08.697565 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3219 14:44:08.700912 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3220 14:44:08.707447 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3221 14:44:08.710672 0 15 28 | B1->B0 | 2a2a 2e2e | 0 0 | (0 0) (0 0)
3222 14:44:08.714000 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 14:44:08.720632 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 14:44:08.724053 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 14:44:08.727532 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 14:44:08.733911 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3227 14:44:08.737380 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3228 14:44:08.740719 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3229 14:44:08.747375 1 0 28 | B1->B0 | 4343 3f3f | 0 0 | (0 0) (0 0)
3230 14:44:08.750532 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 14:44:08.754123 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 14:44:08.760679 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 14:44:08.763933 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 14:44:08.767221 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 14:44:08.774303 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 14:44:08.777871 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 14:44:08.780736 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3238 14:44:08.787586 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3239 14:44:08.791070 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 14:44:08.794070 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 14:44:08.800734 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 14:44:08.804346 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 14:44:08.807276 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 14:44:08.814194 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 14:44:08.817491 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 14:44:08.820843 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 14:44:08.824196 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 14:44:08.830481 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 14:44:08.834008 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 14:44:08.837298 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 14:44:08.843710 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 14:44:08.847170 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 14:44:08.850784 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3254 14:44:08.857029 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 14:44:08.860306 Total UI for P1: 0, mck2ui 16
3256 14:44:08.863889 best dqsien dly found for B0: ( 1, 3, 28)
3257 14:44:08.867297 Total UI for P1: 0, mck2ui 16
3258 14:44:08.870700 best dqsien dly found for B1: ( 1, 3, 28)
3259 14:44:08.873744 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3260 14:44:08.877427 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3261 14:44:08.877541
3262 14:44:08.880472 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3263 14:44:08.884163 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3264 14:44:08.887269 [Gating] SW calibration Done
3265 14:44:08.887353 ==
3266 14:44:08.890588 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 14:44:08.894154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 14:44:08.894238 ==
3269 14:44:08.897090 RX Vref Scan: 0
3270 14:44:08.897172
3271 14:44:08.897237 RX Vref 0 -> 0, step: 1
3272 14:44:08.897298
3273 14:44:08.900508 RX Delay -40 -> 252, step: 8
3274 14:44:08.903803 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3275 14:44:08.910910 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3276 14:44:08.913656 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3277 14:44:08.917161 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3278 14:44:08.920388 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3279 14:44:08.923894 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3280 14:44:08.930342 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3281 14:44:08.933788 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3282 14:44:08.937123 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3283 14:44:08.940289 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3284 14:44:08.943896 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3285 14:44:08.950656 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3286 14:44:08.953803 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3287 14:44:08.957132 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3288 14:44:08.960581 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3289 14:44:08.963780 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3290 14:44:08.967044 ==
3291 14:44:08.967139 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 14:44:08.973600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 14:44:08.973691 ==
3294 14:44:08.973759 DQS Delay:
3295 14:44:08.976794 DQS0 = 0, DQS1 = 0
3296 14:44:08.976911 DQM Delay:
3297 14:44:08.980225 DQM0 = 113, DQM1 = 105
3298 14:44:08.980331 DQ Delay:
3299 14:44:08.983708 DQ0 =115, DQ1 =107, DQ2 =103, DQ3 =115
3300 14:44:08.986967 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3301 14:44:08.990213 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3302 14:44:08.993609 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3303 14:44:08.993698
3304 14:44:08.993782
3305 14:44:08.993862 ==
3306 14:44:08.996728 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 14:44:09.000306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 14:44:09.003819 ==
3309 14:44:09.003926
3310 14:44:09.004037
3311 14:44:09.004140 TX Vref Scan disable
3312 14:44:09.007336 == TX Byte 0 ==
3313 14:44:09.010321 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3314 14:44:09.014065 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3315 14:44:09.017063 == TX Byte 1 ==
3316 14:44:09.020631 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3317 14:44:09.023535 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3318 14:44:09.026976 ==
3319 14:44:09.027061 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 14:44:09.033867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 14:44:09.033954 ==
3322 14:44:09.044829 TX Vref=22, minBit 11, minWin=24, winSum=409
3323 14:44:09.048207 TX Vref=24, minBit 10, minWin=24, winSum=411
3324 14:44:09.051350 TX Vref=26, minBit 8, minWin=25, winSum=416
3325 14:44:09.054453 TX Vref=28, minBit 9, minWin=25, winSum=419
3326 14:44:09.058291 TX Vref=30, minBit 9, minWin=24, winSum=420
3327 14:44:09.064551 TX Vref=32, minBit 9, minWin=25, winSum=418
3328 14:44:09.068165 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
3329 14:44:09.068247
3330 14:44:09.071652 Final TX Range 1 Vref 28
3331 14:44:09.071732
3332 14:44:09.071795 ==
3333 14:44:09.074617 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 14:44:09.078061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 14:44:09.078168 ==
3336 14:44:09.081301
3337 14:44:09.081409
3338 14:44:09.081506 TX Vref Scan disable
3339 14:44:09.084570 == TX Byte 0 ==
3340 14:44:09.088205 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3341 14:44:09.091345 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3342 14:44:09.094393 == TX Byte 1 ==
3343 14:44:09.098222 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3344 14:44:09.104357 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3345 14:44:09.104483
3346 14:44:09.104605 [DATLAT]
3347 14:44:09.104786 Freq=1200, CH1 RK0
3348 14:44:09.104896
3349 14:44:09.107922 DATLAT Default: 0xd
3350 14:44:09.108038 0, 0xFFFF, sum = 0
3351 14:44:09.111555 1, 0xFFFF, sum = 0
3352 14:44:09.111674 2, 0xFFFF, sum = 0
3353 14:44:09.114407 3, 0xFFFF, sum = 0
3354 14:44:09.117970 4, 0xFFFF, sum = 0
3355 14:44:09.118071 5, 0xFFFF, sum = 0
3356 14:44:09.121632 6, 0xFFFF, sum = 0
3357 14:44:09.121742 7, 0xFFFF, sum = 0
3358 14:44:09.124422 8, 0xFFFF, sum = 0
3359 14:44:09.124534 9, 0xFFFF, sum = 0
3360 14:44:09.127957 10, 0xFFFF, sum = 0
3361 14:44:09.128072 11, 0xFFFF, sum = 0
3362 14:44:09.131350 12, 0x0, sum = 1
3363 14:44:09.131464 13, 0x0, sum = 2
3364 14:44:09.134778 14, 0x0, sum = 3
3365 14:44:09.134892 15, 0x0, sum = 4
3366 14:44:09.134989 best_step = 13
3367 14:44:09.137800
3368 14:44:09.137902 ==
3369 14:44:09.141231 Dram Type= 6, Freq= 0, CH_1, rank 0
3370 14:44:09.144323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3371 14:44:09.144433 ==
3372 14:44:09.144529 RX Vref Scan: 1
3373 14:44:09.144633
3374 14:44:09.148096 Set Vref Range= 32 -> 127
3375 14:44:09.148196
3376 14:44:09.151523 RX Vref 32 -> 127, step: 1
3377 14:44:09.151624
3378 14:44:09.154427 RX Delay -21 -> 252, step: 4
3379 14:44:09.154572
3380 14:44:09.158069 Set Vref, RX VrefLevel [Byte0]: 32
3381 14:44:09.161386 [Byte1]: 32
3382 14:44:09.161494
3383 14:44:09.164744 Set Vref, RX VrefLevel [Byte0]: 33
3384 14:44:09.167647 [Byte1]: 33
3385 14:44:09.172512
3386 14:44:09.172618 Set Vref, RX VrefLevel [Byte0]: 34
3387 14:44:09.174429 [Byte1]: 34
3388 14:44:09.178948
3389 14:44:09.179032 Set Vref, RX VrefLevel [Byte0]: 35
3390 14:44:09.182290 [Byte1]: 35
3391 14:44:09.187229
3392 14:44:09.187337 Set Vref, RX VrefLevel [Byte0]: 36
3393 14:44:09.190248 [Byte1]: 36
3394 14:44:09.195192
3395 14:44:09.195274 Set Vref, RX VrefLevel [Byte0]: 37
3396 14:44:09.198286 [Byte1]: 37
3397 14:44:09.202519
3398 14:44:09.202629 Set Vref, RX VrefLevel [Byte0]: 38
3399 14:44:09.206122 [Byte1]: 38
3400 14:44:09.210717
3401 14:44:09.210826 Set Vref, RX VrefLevel [Byte0]: 39
3402 14:44:09.214113 [Byte1]: 39
3403 14:44:09.218812
3404 14:44:09.218891 Set Vref, RX VrefLevel [Byte0]: 40
3405 14:44:09.222331 [Byte1]: 40
3406 14:44:09.226322
3407 14:44:09.226430 Set Vref, RX VrefLevel [Byte0]: 41
3408 14:44:09.229808 [Byte1]: 41
3409 14:44:09.234261
3410 14:44:09.234339 Set Vref, RX VrefLevel [Byte0]: 42
3411 14:44:09.237755 [Byte1]: 42
3412 14:44:09.242293
3413 14:44:09.242401 Set Vref, RX VrefLevel [Byte0]: 43
3414 14:44:09.245857 [Byte1]: 43
3415 14:44:09.250382
3416 14:44:09.250506 Set Vref, RX VrefLevel [Byte0]: 44
3417 14:44:09.253510 [Byte1]: 44
3418 14:44:09.258242
3419 14:44:09.258348 Set Vref, RX VrefLevel [Byte0]: 45
3420 14:44:09.261798 [Byte1]: 45
3421 14:44:09.266038
3422 14:44:09.266119 Set Vref, RX VrefLevel [Byte0]: 46
3423 14:44:09.269218 [Byte1]: 46
3424 14:44:09.274423
3425 14:44:09.274508 Set Vref, RX VrefLevel [Byte0]: 47
3426 14:44:09.277609 [Byte1]: 47
3427 14:44:09.281860
3428 14:44:09.281942 Set Vref, RX VrefLevel [Byte0]: 48
3429 14:44:09.285193 [Byte1]: 48
3430 14:44:09.289734
3431 14:44:09.289816 Set Vref, RX VrefLevel [Byte0]: 49
3432 14:44:09.293154 [Byte1]: 49
3433 14:44:09.298098
3434 14:44:09.298181 Set Vref, RX VrefLevel [Byte0]: 50
3435 14:44:09.301279 [Byte1]: 50
3436 14:44:09.305805
3437 14:44:09.305912 Set Vref, RX VrefLevel [Byte0]: 51
3438 14:44:09.308871 [Byte1]: 51
3439 14:44:09.313786
3440 14:44:09.313867 Set Vref, RX VrefLevel [Byte0]: 52
3441 14:44:09.316893 [Byte1]: 52
3442 14:44:09.321591
3443 14:44:09.321697 Set Vref, RX VrefLevel [Byte0]: 53
3444 14:44:09.324553 [Byte1]: 53
3445 14:44:09.329399
3446 14:44:09.329483 Set Vref, RX VrefLevel [Byte0]: 54
3447 14:44:09.332795 [Byte1]: 54
3448 14:44:09.337429
3449 14:44:09.337511 Set Vref, RX VrefLevel [Byte0]: 55
3450 14:44:09.340752 [Byte1]: 55
3451 14:44:09.345707
3452 14:44:09.345796 Set Vref, RX VrefLevel [Byte0]: 56
3453 14:44:09.348491 [Byte1]: 56
3454 14:44:09.353160
3455 14:44:09.353242 Set Vref, RX VrefLevel [Byte0]: 57
3456 14:44:09.356530 [Byte1]: 57
3457 14:44:09.361358
3458 14:44:09.361469 Set Vref, RX VrefLevel [Byte0]: 58
3459 14:44:09.364766 [Byte1]: 58
3460 14:44:09.369480
3461 14:44:09.369561 Set Vref, RX VrefLevel [Byte0]: 59
3462 14:44:09.372790 [Byte1]: 59
3463 14:44:09.376990
3464 14:44:09.377076 Set Vref, RX VrefLevel [Byte0]: 60
3465 14:44:09.380152 [Byte1]: 60
3466 14:44:09.384786
3467 14:44:09.384867 Set Vref, RX VrefLevel [Byte0]: 61
3468 14:44:09.388445 [Byte1]: 61
3469 14:44:09.392682
3470 14:44:09.392764 Set Vref, RX VrefLevel [Byte0]: 62
3471 14:44:09.396156 [Byte1]: 62
3472 14:44:09.400586
3473 14:44:09.400667 Set Vref, RX VrefLevel [Byte0]: 63
3474 14:44:09.404137 [Byte1]: 63
3475 14:44:09.408543
3476 14:44:09.408633 Set Vref, RX VrefLevel [Byte0]: 64
3477 14:44:09.411835 [Byte1]: 64
3478 14:44:09.416493
3479 14:44:09.416582 Set Vref, RX VrefLevel [Byte0]: 65
3480 14:44:09.420192 [Byte1]: 65
3481 14:44:09.424397
3482 14:44:09.424516 Set Vref, RX VrefLevel [Byte0]: 66
3483 14:44:09.428229 [Byte1]: 66
3484 14:44:09.432663
3485 14:44:09.432784 Set Vref, RX VrefLevel [Byte0]: 67
3486 14:44:09.435550 [Byte1]: 67
3487 14:44:09.440563
3488 14:44:09.440647 Final RX Vref Byte 0 = 59 to rank0
3489 14:44:09.443582 Final RX Vref Byte 1 = 48 to rank0
3490 14:44:09.447363 Final RX Vref Byte 0 = 59 to rank1
3491 14:44:09.450295 Final RX Vref Byte 1 = 48 to rank1==
3492 14:44:09.453711 Dram Type= 6, Freq= 0, CH_1, rank 0
3493 14:44:09.460389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 14:44:09.460474 ==
3495 14:44:09.460539 DQS Delay:
3496 14:44:09.460612 DQS0 = 0, DQS1 = 0
3497 14:44:09.463832 DQM Delay:
3498 14:44:09.463915 DQM0 = 114, DQM1 = 105
3499 14:44:09.467355 DQ Delay:
3500 14:44:09.470619 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3501 14:44:09.473648 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3502 14:44:09.476860 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3503 14:44:09.480276 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3504 14:44:09.480358
3505 14:44:09.480422
3506 14:44:09.487318 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3507 14:44:09.490523 CH1 RK0: MR19=303, MR18=F2F9
3508 14:44:09.497252 CH1_RK0: MR19=0x303, MR18=0xF2F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3509 14:44:09.497339
3510 14:44:09.500533 ----->DramcWriteLeveling(PI) begin...
3511 14:44:09.500665 ==
3512 14:44:09.503558 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 14:44:09.507073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 14:44:09.510325 ==
3515 14:44:09.510409 Write leveling (Byte 0): 22 => 22
3516 14:44:09.513335 Write leveling (Byte 1): 28 => 28
3517 14:44:09.517222 DramcWriteLeveling(PI) end<-----
3518 14:44:09.517323
3519 14:44:09.517413 ==
3520 14:44:09.519994 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 14:44:09.527139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 14:44:09.527255 ==
3523 14:44:09.527351 [Gating] SW mode calibration
3524 14:44:09.536686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3525 14:44:09.540367 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3526 14:44:09.546885 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 14:44:09.550151 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 14:44:09.553562 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 14:44:09.556937 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 14:44:09.563400 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 14:44:09.566911 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3532 14:44:09.570414 0 15 24 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
3533 14:44:09.576574 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
3534 14:44:09.580581 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 14:44:09.583614 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 14:44:09.590362 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 14:44:09.593599 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 14:44:09.596514 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 14:44:09.603173 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3540 14:44:09.606862 1 0 24 | B1->B0 | 2d2d 4545 | 1 0 | (0 0) (0 0)
3541 14:44:09.609798 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3542 14:44:09.616636 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 14:44:09.619898 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 14:44:09.623282 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 14:44:09.629645 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 14:44:09.633268 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 14:44:09.636390 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 14:44:09.643042 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3549 14:44:09.646196 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3550 14:44:09.649802 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 14:44:09.656376 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 14:44:09.659401 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 14:44:09.662918 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 14:44:09.669304 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 14:44:09.672952 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 14:44:09.676342 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 14:44:09.682797 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 14:44:09.686214 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 14:44:09.689545 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 14:44:09.695883 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 14:44:09.699696 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 14:44:09.702807 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 14:44:09.709274 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 14:44:09.712395 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3565 14:44:09.715884 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 14:44:09.719281 Total UI for P1: 0, mck2ui 16
3567 14:44:09.722718 best dqsien dly found for B0: ( 1, 3, 24)
3568 14:44:09.726033 Total UI for P1: 0, mck2ui 16
3569 14:44:09.729484 best dqsien dly found for B1: ( 1, 3, 24)
3570 14:44:09.732325 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3571 14:44:09.735618 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3572 14:44:09.735698
3573 14:44:09.739494 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3574 14:44:09.745576 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3575 14:44:09.745658 [Gating] SW calibration Done
3576 14:44:09.745722 ==
3577 14:44:09.749194 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 14:44:09.755943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 14:44:09.756025 ==
3580 14:44:09.756090 RX Vref Scan: 0
3581 14:44:09.756149
3582 14:44:09.758816 RX Vref 0 -> 0, step: 1
3583 14:44:09.758897
3584 14:44:09.762443 RX Delay -40 -> 252, step: 8
3585 14:44:09.765807 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
3586 14:44:09.769272 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3587 14:44:09.772415 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3588 14:44:09.779339 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3589 14:44:09.782171 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3590 14:44:09.785675 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3591 14:44:09.789194 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3592 14:44:09.792533 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3593 14:44:09.795486 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3594 14:44:09.802249 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3595 14:44:09.805640 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3596 14:44:09.808833 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3597 14:44:09.811955 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3598 14:44:09.818461 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3599 14:44:09.822098 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3600 14:44:09.825133 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3601 14:44:09.825215 ==
3602 14:44:09.828735 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 14:44:09.831922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 14:44:09.832003 ==
3605 14:44:09.835331 DQS Delay:
3606 14:44:09.835412 DQS0 = 0, DQS1 = 0
3607 14:44:09.838702 DQM Delay:
3608 14:44:09.838783 DQM0 = 110, DQM1 = 106
3609 14:44:09.841784 DQ Delay:
3610 14:44:09.845222 DQ0 =111, DQ1 =107, DQ2 =99, DQ3 =107
3611 14:44:09.848643 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3612 14:44:09.851948 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3613 14:44:09.855196 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3614 14:44:09.855293
3615 14:44:09.855405
3616 14:44:09.855464 ==
3617 14:44:09.858418 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 14:44:09.861700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 14:44:09.861786 ==
3620 14:44:09.861872
3621 14:44:09.861951
3622 14:44:09.864896 TX Vref Scan disable
3623 14:44:09.868484 == TX Byte 0 ==
3624 14:44:09.871317 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3625 14:44:09.874957 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3626 14:44:09.878181 == TX Byte 1 ==
3627 14:44:09.881442 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3628 14:44:09.884846 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3629 14:44:09.884926 ==
3630 14:44:09.888105 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 14:44:09.891417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 14:44:09.894875 ==
3633 14:44:09.905262 TX Vref=22, minBit 3, minWin=25, winSum=423
3634 14:44:09.908542 TX Vref=24, minBit 0, minWin=26, winSum=430
3635 14:44:09.912080 TX Vref=26, minBit 8, minWin=26, winSum=432
3636 14:44:09.915613 TX Vref=28, minBit 1, minWin=26, winSum=431
3637 14:44:09.918538 TX Vref=30, minBit 0, minWin=26, winSum=431
3638 14:44:09.924988 TX Vref=32, minBit 8, minWin=25, winSum=426
3639 14:44:09.928186 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 26
3640 14:44:09.928305
3641 14:44:09.931718 Final TX Range 1 Vref 26
3642 14:44:09.931801
3643 14:44:09.931866 ==
3644 14:44:09.935272 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 14:44:09.938540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 14:44:09.938632 ==
3647 14:44:09.941981
3648 14:44:09.942076
3649 14:44:09.942147 TX Vref Scan disable
3650 14:44:09.944649 == TX Byte 0 ==
3651 14:44:09.948613 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3652 14:44:09.955088 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3653 14:44:09.955210 == TX Byte 1 ==
3654 14:44:09.957980 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3655 14:44:09.964947 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3656 14:44:09.965070
3657 14:44:09.965180 [DATLAT]
3658 14:44:09.965288 Freq=1200, CH1 RK1
3659 14:44:09.965394
3660 14:44:09.967874 DATLAT Default: 0xd
3661 14:44:09.971248 0, 0xFFFF, sum = 0
3662 14:44:09.971365 1, 0xFFFF, sum = 0
3663 14:44:09.974722 2, 0xFFFF, sum = 0
3664 14:44:09.974838 3, 0xFFFF, sum = 0
3665 14:44:09.977647 4, 0xFFFF, sum = 0
3666 14:44:09.977824 5, 0xFFFF, sum = 0
3667 14:44:09.981095 6, 0xFFFF, sum = 0
3668 14:44:09.981260 7, 0xFFFF, sum = 0
3669 14:44:09.984519 8, 0xFFFF, sum = 0
3670 14:44:09.984628 9, 0xFFFF, sum = 0
3671 14:44:09.987569 10, 0xFFFF, sum = 0
3672 14:44:09.987686 11, 0xFFFF, sum = 0
3673 14:44:09.991038 12, 0x0, sum = 1
3674 14:44:09.991121 13, 0x0, sum = 2
3675 14:44:09.994617 14, 0x0, sum = 3
3676 14:44:09.994701 15, 0x0, sum = 4
3677 14:44:09.997453 best_step = 13
3678 14:44:09.997534
3679 14:44:09.997599 ==
3680 14:44:10.000986 Dram Type= 6, Freq= 0, CH_1, rank 1
3681 14:44:10.004070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3682 14:44:10.004184 ==
3683 14:44:10.007515 RX Vref Scan: 0
3684 14:44:10.007628
3685 14:44:10.007726 RX Vref 0 -> 0, step: 1
3686 14:44:10.007794
3687 14:44:10.011025 RX Delay -21 -> 252, step: 4
3688 14:44:10.017450 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3689 14:44:10.021115 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3690 14:44:10.024390 iDelay=195, Bit 2, Center 102 (31 ~ 174) 144
3691 14:44:10.027423 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3692 14:44:10.030773 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3693 14:44:10.037405 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3694 14:44:10.041006 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3695 14:44:10.044471 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3696 14:44:10.047264 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3697 14:44:10.050497 iDelay=195, Bit 9, Center 102 (35 ~ 170) 136
3698 14:44:10.057489 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3699 14:44:10.060690 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3700 14:44:10.063741 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3701 14:44:10.067118 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3702 14:44:10.070896 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3703 14:44:10.077337 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3704 14:44:10.077421 ==
3705 14:44:10.080774 Dram Type= 6, Freq= 0, CH_1, rank 1
3706 14:44:10.083786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3707 14:44:10.083890 ==
3708 14:44:10.083983 DQS Delay:
3709 14:44:10.087046 DQS0 = 0, DQS1 = 0
3710 14:44:10.087148 DQM Delay:
3711 14:44:10.090373 DQM0 = 111, DQM1 = 109
3712 14:44:10.090453 DQ Delay:
3713 14:44:10.094028 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =108
3714 14:44:10.097119 DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =110
3715 14:44:10.100444 DQ8 =94, DQ9 =102, DQ10 =110, DQ11 =102
3716 14:44:10.103953 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =118
3717 14:44:10.104112
3718 14:44:10.106693
3719 14:44:10.113891 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa09, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3720 14:44:10.116812 CH1 RK1: MR19=304, MR18=FA09
3721 14:44:10.123753 CH1_RK1: MR19=0x304, MR18=0xFA09, DQSOSC=406, MR23=63, INC=39, DEC=26
3722 14:44:10.126750 [RxdqsGatingPostProcess] freq 1200
3723 14:44:10.129995 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3724 14:44:10.133365 best DQS0 dly(2T, 0.5T) = (0, 11)
3725 14:44:10.136912 best DQS1 dly(2T, 0.5T) = (0, 11)
3726 14:44:10.140290 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3727 14:44:10.143557 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3728 14:44:10.146696 best DQS0 dly(2T, 0.5T) = (0, 11)
3729 14:44:10.150011 best DQS1 dly(2T, 0.5T) = (0, 11)
3730 14:44:10.153525 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3731 14:44:10.156747 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3732 14:44:10.159705 Pre-setting of DQS Precalculation
3733 14:44:10.163209 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3734 14:44:10.170198 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3735 14:44:10.179763 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3736 14:44:10.179860
3737 14:44:10.179925
3738 14:44:10.183362 [Calibration Summary] 2400 Mbps
3739 14:44:10.183463 CH 0, Rank 0
3740 14:44:10.186447 SW Impedance : PASS
3741 14:44:10.186539 DUTY Scan : NO K
3742 14:44:10.189841 ZQ Calibration : PASS
3743 14:44:10.192625 Jitter Meter : NO K
3744 14:44:10.192716 CBT Training : PASS
3745 14:44:10.196183 Write leveling : PASS
3746 14:44:10.199670 RX DQS gating : PASS
3747 14:44:10.199756 RX DQ/DQS(RDDQC) : PASS
3748 14:44:10.202845 TX DQ/DQS : PASS
3749 14:44:10.202956 RX DATLAT : PASS
3750 14:44:10.205928 RX DQ/DQS(Engine): PASS
3751 14:44:10.209794 TX OE : NO K
3752 14:44:10.209908 All Pass.
3753 14:44:10.210005
3754 14:44:10.210106 CH 0, Rank 1
3755 14:44:10.212885 SW Impedance : PASS
3756 14:44:10.216438 DUTY Scan : NO K
3757 14:44:10.216548 ZQ Calibration : PASS
3758 14:44:10.219347 Jitter Meter : NO K
3759 14:44:10.222748 CBT Training : PASS
3760 14:44:10.222861 Write leveling : PASS
3761 14:44:10.226236 RX DQS gating : PASS
3762 14:44:10.229300 RX DQ/DQS(RDDQC) : PASS
3763 14:44:10.229413 TX DQ/DQS : PASS
3764 14:44:10.232628 RX DATLAT : PASS
3765 14:44:10.235889 RX DQ/DQS(Engine): PASS
3766 14:44:10.236002 TX OE : NO K
3767 14:44:10.239098 All Pass.
3768 14:44:10.239201
3769 14:44:10.239294 CH 1, Rank 0
3770 14:44:10.242951 SW Impedance : PASS
3771 14:44:10.243034 DUTY Scan : NO K
3772 14:44:10.246014 ZQ Calibration : PASS
3773 14:44:10.249471 Jitter Meter : NO K
3774 14:44:10.249556 CBT Training : PASS
3775 14:44:10.252511 Write leveling : PASS
3776 14:44:10.256202 RX DQS gating : PASS
3777 14:44:10.256293 RX DQ/DQS(RDDQC) : PASS
3778 14:44:10.259170 TX DQ/DQS : PASS
3779 14:44:10.259249 RX DATLAT : PASS
3780 14:44:10.262628 RX DQ/DQS(Engine): PASS
3781 14:44:10.265991 TX OE : NO K
3782 14:44:10.266074 All Pass.
3783 14:44:10.266140
3784 14:44:10.266202 CH 1, Rank 1
3785 14:44:10.269489 SW Impedance : PASS
3786 14:44:10.272782 DUTY Scan : NO K
3787 14:44:10.272866 ZQ Calibration : PASS
3788 14:44:10.275735 Jitter Meter : NO K
3789 14:44:10.279610 CBT Training : PASS
3790 14:44:10.279692 Write leveling : PASS
3791 14:44:10.282805 RX DQS gating : PASS
3792 14:44:10.285572 RX DQ/DQS(RDDQC) : PASS
3793 14:44:10.285651 TX DQ/DQS : PASS
3794 14:44:10.289051 RX DATLAT : PASS
3795 14:44:10.292486 RX DQ/DQS(Engine): PASS
3796 14:44:10.292597 TX OE : NO K
3797 14:44:10.296072 All Pass.
3798 14:44:10.296155
3799 14:44:10.296220 DramC Write-DBI off
3800 14:44:10.299280 PER_BANK_REFRESH: Hybrid Mode
3801 14:44:10.299364 TX_TRACKING: ON
3802 14:44:10.309285 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3803 14:44:10.312177 [FAST_K] Save calibration result to emmc
3804 14:44:10.315641 dramc_set_vcore_voltage set vcore to 650000
3805 14:44:10.318938 Read voltage for 600, 5
3806 14:44:10.319049 Vio18 = 0
3807 14:44:10.321948 Vcore = 650000
3808 14:44:10.322035 Vdram = 0
3809 14:44:10.322123 Vddq = 0
3810 14:44:10.325693 Vmddr = 0
3811 14:44:10.328963 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3812 14:44:10.335764 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3813 14:44:10.335858 MEM_TYPE=3, freq_sel=19
3814 14:44:10.338720 sv_algorithm_assistance_LP4_1600
3815 14:44:10.345660 ============ PULL DRAM RESETB DOWN ============
3816 14:44:10.348904 ========== PULL DRAM RESETB DOWN end =========
3817 14:44:10.351909 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3818 14:44:10.355417 ===================================
3819 14:44:10.358712 LPDDR4 DRAM CONFIGURATION
3820 14:44:10.361766 ===================================
3821 14:44:10.361849 EX_ROW_EN[0] = 0x0
3822 14:44:10.365345 EX_ROW_EN[1] = 0x0
3823 14:44:10.368301 LP4Y_EN = 0x0
3824 14:44:10.368384 WORK_FSP = 0x0
3825 14:44:10.371895 WL = 0x2
3826 14:44:10.371978 RL = 0x2
3827 14:44:10.375454 BL = 0x2
3828 14:44:10.375569 RPST = 0x0
3829 14:44:10.378364 RD_PRE = 0x0
3830 14:44:10.378476 WR_PRE = 0x1
3831 14:44:10.381781 WR_PST = 0x0
3832 14:44:10.381861 DBI_WR = 0x0
3833 14:44:10.385232 DBI_RD = 0x0
3834 14:44:10.385317 OTF = 0x1
3835 14:44:10.388861 ===================================
3836 14:44:10.391945 ===================================
3837 14:44:10.395259 ANA top config
3838 14:44:10.398638 ===================================
3839 14:44:10.398745 DLL_ASYNC_EN = 0
3840 14:44:10.401833 ALL_SLAVE_EN = 1
3841 14:44:10.405215 NEW_RANK_MODE = 1
3842 14:44:10.408630 DLL_IDLE_MODE = 1
3843 14:44:10.412023 LP45_APHY_COMB_EN = 1
3844 14:44:10.412101 TX_ODT_DIS = 1
3845 14:44:10.415302 NEW_8X_MODE = 1
3846 14:44:10.418114 ===================================
3847 14:44:10.421666 ===================================
3848 14:44:10.425180 data_rate = 1200
3849 14:44:10.428380 CKR = 1
3850 14:44:10.431518 DQ_P2S_RATIO = 8
3851 14:44:10.434916 ===================================
3852 14:44:10.434996 CA_P2S_RATIO = 8
3853 14:44:10.438550 DQ_CA_OPEN = 0
3854 14:44:10.441604 DQ_SEMI_OPEN = 0
3855 14:44:10.444941 CA_SEMI_OPEN = 0
3856 14:44:10.448108 CA_FULL_RATE = 0
3857 14:44:10.451740 DQ_CKDIV4_EN = 1
3858 14:44:10.451828 CA_CKDIV4_EN = 1
3859 14:44:10.454842 CA_PREDIV_EN = 0
3860 14:44:10.458364 PH8_DLY = 0
3861 14:44:10.461474 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3862 14:44:10.464845 DQ_AAMCK_DIV = 4
3863 14:44:10.468423 CA_AAMCK_DIV = 4
3864 14:44:10.468534 CA_ADMCK_DIV = 4
3865 14:44:10.471525 DQ_TRACK_CA_EN = 0
3866 14:44:10.474645 CA_PICK = 600
3867 14:44:10.477983 CA_MCKIO = 600
3868 14:44:10.481434 MCKIO_SEMI = 0
3869 14:44:10.484394 PLL_FREQ = 2288
3870 14:44:10.487694 DQ_UI_PI_RATIO = 32
3871 14:44:10.491383 CA_UI_PI_RATIO = 0
3872 14:44:10.494380 ===================================
3873 14:44:10.497575 ===================================
3874 14:44:10.497655 memory_type:LPDDR4
3875 14:44:10.501167 GP_NUM : 10
3876 14:44:10.504097 SRAM_EN : 1
3877 14:44:10.504184 MD32_EN : 0
3878 14:44:10.507560 ===================================
3879 14:44:10.511182 [ANA_INIT] >>>>>>>>>>>>>>
3880 14:44:10.514331 <<<<<< [CONFIGURE PHASE]: ANA_TX
3881 14:44:10.517137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3882 14:44:10.520617 ===================================
3883 14:44:10.524071 data_rate = 1200,PCW = 0X5800
3884 14:44:10.527684 ===================================
3885 14:44:10.530620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3886 14:44:10.533864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3887 14:44:10.540538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3888 14:44:10.543969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3889 14:44:10.547267 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3890 14:44:10.550611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3891 14:44:10.553735 [ANA_INIT] flow start
3892 14:44:10.556887 [ANA_INIT] PLL >>>>>>>>
3893 14:44:10.556970 [ANA_INIT] PLL <<<<<<<<
3894 14:44:10.560438 [ANA_INIT] MIDPI >>>>>>>>
3895 14:44:10.563654 [ANA_INIT] MIDPI <<<<<<<<
3896 14:44:10.567253 [ANA_INIT] DLL >>>>>>>>
3897 14:44:10.567364 [ANA_INIT] flow end
3898 14:44:10.570108 ============ LP4 DIFF to SE enter ============
3899 14:44:10.577228 ============ LP4 DIFF to SE exit ============
3900 14:44:10.577312 [ANA_INIT] <<<<<<<<<<<<<
3901 14:44:10.580120 [Flow] Enable top DCM control >>>>>
3902 14:44:10.583356 [Flow] Enable top DCM control <<<<<
3903 14:44:10.586899 Enable DLL master slave shuffle
3904 14:44:10.593544 ==============================================================
3905 14:44:10.593631 Gating Mode config
3906 14:44:10.600018 ==============================================================
3907 14:44:10.603588 Config description:
3908 14:44:10.613234 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3909 14:44:10.619942 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3910 14:44:10.623300 SELPH_MODE 0: By rank 1: By Phase
3911 14:44:10.629841 ==============================================================
3912 14:44:10.633216 GAT_TRACK_EN = 1
3913 14:44:10.633301 RX_GATING_MODE = 2
3914 14:44:10.636814 RX_GATING_TRACK_MODE = 2
3915 14:44:10.639800 SELPH_MODE = 1
3916 14:44:10.643187 PICG_EARLY_EN = 1
3917 14:44:10.646711 VALID_LAT_VALUE = 1
3918 14:44:10.652948 ==============================================================
3919 14:44:10.656233 Enter into Gating configuration >>>>
3920 14:44:10.659544 Exit from Gating configuration <<<<
3921 14:44:10.663017 Enter into DVFS_PRE_config >>>>>
3922 14:44:10.672934 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3923 14:44:10.676565 Exit from DVFS_PRE_config <<<<<
3924 14:44:10.679487 Enter into PICG configuration >>>>
3925 14:44:10.682689 Exit from PICG configuration <<<<
3926 14:44:10.686534 [RX_INPUT] configuration >>>>>
3927 14:44:10.689362 [RX_INPUT] configuration <<<<<
3928 14:44:10.692578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3929 14:44:10.699620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3930 14:44:10.705915 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3931 14:44:10.712451 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3932 14:44:10.716198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3933 14:44:10.722350 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3934 14:44:10.725723 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3935 14:44:10.732419 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3936 14:44:10.735942 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3937 14:44:10.739420 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3938 14:44:10.742461 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3939 14:44:10.749190 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3940 14:44:10.752688 ===================================
3941 14:44:10.752773 LPDDR4 DRAM CONFIGURATION
3942 14:44:10.755530 ===================================
3943 14:44:10.759224 EX_ROW_EN[0] = 0x0
3944 14:44:10.762548 EX_ROW_EN[1] = 0x0
3945 14:44:10.762633 LP4Y_EN = 0x0
3946 14:44:10.765725 WORK_FSP = 0x0
3947 14:44:10.765808 WL = 0x2
3948 14:44:10.769390 RL = 0x2
3949 14:44:10.769477 BL = 0x2
3950 14:44:10.772172 RPST = 0x0
3951 14:44:10.772256 RD_PRE = 0x0
3952 14:44:10.775657 WR_PRE = 0x1
3953 14:44:10.775742 WR_PST = 0x0
3954 14:44:10.778918 DBI_WR = 0x0
3955 14:44:10.779001 DBI_RD = 0x0
3956 14:44:10.782151 OTF = 0x1
3957 14:44:10.785299 ===================================
3958 14:44:10.789030 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3959 14:44:10.792288 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3960 14:44:10.799336 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3961 14:44:10.802301 ===================================
3962 14:44:10.802385 LPDDR4 DRAM CONFIGURATION
3963 14:44:10.805395 ===================================
3964 14:44:10.808899 EX_ROW_EN[0] = 0x10
3965 14:44:10.812156 EX_ROW_EN[1] = 0x0
3966 14:44:10.812239 LP4Y_EN = 0x0
3967 14:44:10.815440 WORK_FSP = 0x0
3968 14:44:10.815549 WL = 0x2
3969 14:44:10.818714 RL = 0x2
3970 14:44:10.818798 BL = 0x2
3971 14:44:10.822148 RPST = 0x0
3972 14:44:10.822230 RD_PRE = 0x0
3973 14:44:10.825055 WR_PRE = 0x1
3974 14:44:10.825168 WR_PST = 0x0
3975 14:44:10.828423 DBI_WR = 0x0
3976 14:44:10.828533 DBI_RD = 0x0
3977 14:44:10.831990 OTF = 0x1
3978 14:44:10.835387 ===================================
3979 14:44:10.841819 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3980 14:44:10.845322 nWR fixed to 30
3981 14:44:10.848741 [ModeRegInit_LP4] CH0 RK0
3982 14:44:10.848852 [ModeRegInit_LP4] CH0 RK1
3983 14:44:10.852193 [ModeRegInit_LP4] CH1 RK0
3984 14:44:10.855167 [ModeRegInit_LP4] CH1 RK1
3985 14:44:10.855250 match AC timing 17
3986 14:44:10.861580 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3987 14:44:10.865040 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3988 14:44:10.868383 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3989 14:44:10.875106 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3990 14:44:10.878044 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3991 14:44:10.878129 ==
3992 14:44:10.881542 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 14:44:10.884896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 14:44:10.884985 ==
3995 14:44:10.891597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3996 14:44:10.898085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3997 14:44:10.901337 [CA 0] Center 37 (7~67) winsize 61
3998 14:44:10.904965 [CA 1] Center 36 (6~67) winsize 62
3999 14:44:10.908425 [CA 2] Center 35 (5~65) winsize 61
4000 14:44:10.911322 [CA 3] Center 35 (5~65) winsize 61
4001 14:44:10.914868 [CA 4] Center 34 (4~65) winsize 62
4002 14:44:10.918230 [CA 5] Center 34 (4~64) winsize 61
4003 14:44:10.918315
4004 14:44:10.921334 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4005 14:44:10.921418
4006 14:44:10.924596 [CATrainingPosCal] consider 1 rank data
4007 14:44:10.928140 u2DelayCellTimex100 = 270/100 ps
4008 14:44:10.931099 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4009 14:44:10.934765 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4010 14:44:10.937824 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4011 14:44:10.941648 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4012 14:44:10.944572 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4013 14:44:10.948038 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4014 14:44:10.948122
4015 14:44:10.954448 CA PerBit enable=1, Macro0, CA PI delay=34
4016 14:44:10.954553
4017 14:44:10.957724 [CBTSetCACLKResult] CA Dly = 34
4018 14:44:10.957809 CS Dly: 5 (0~36)
4019 14:44:10.957875 ==
4020 14:44:10.961249 Dram Type= 6, Freq= 0, CH_0, rank 1
4021 14:44:10.964524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 14:44:10.964624 ==
4023 14:44:10.970972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4024 14:44:10.977425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4025 14:44:10.981070 [CA 0] Center 37 (7~67) winsize 61
4026 14:44:10.984063 [CA 1] Center 37 (7~67) winsize 61
4027 14:44:10.987377 [CA 2] Center 35 (5~65) winsize 61
4028 14:44:10.990773 [CA 3] Center 35 (5~65) winsize 61
4029 14:44:10.994063 [CA 4] Center 34 (4~65) winsize 62
4030 14:44:10.997306 [CA 5] Center 33 (3~64) winsize 62
4031 14:44:10.997390
4032 14:44:11.000527 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4033 14:44:11.000616
4034 14:44:11.003850 [CATrainingPosCal] consider 2 rank data
4035 14:44:11.007578 u2DelayCellTimex100 = 270/100 ps
4036 14:44:11.010544 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4037 14:44:11.014156 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4038 14:44:11.017526 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4039 14:44:11.023663 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4040 14:44:11.027053 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4041 14:44:11.030607 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4042 14:44:11.030684
4043 14:44:11.033930 CA PerBit enable=1, Macro0, CA PI delay=34
4044 14:44:11.034003
4045 14:44:11.037048 [CBTSetCACLKResult] CA Dly = 34
4046 14:44:11.037124 CS Dly: 6 (0~38)
4047 14:44:11.037187
4048 14:44:11.040405 ----->DramcWriteLeveling(PI) begin...
4049 14:44:11.040478 ==
4050 14:44:11.043631 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 14:44:11.050207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 14:44:11.050286 ==
4053 14:44:11.053863 Write leveling (Byte 0): 33 => 33
4054 14:44:11.057089 Write leveling (Byte 1): 30 => 30
4055 14:44:11.060310 DramcWriteLeveling(PI) end<-----
4056 14:44:11.060382
4057 14:44:11.060443 ==
4058 14:44:11.063910 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 14:44:11.066620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 14:44:11.066694 ==
4061 14:44:11.070143 [Gating] SW mode calibration
4062 14:44:11.076638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4063 14:44:11.079993 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4064 14:44:11.086613 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4065 14:44:11.089989 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4066 14:44:11.093142 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 14:44:11.099872 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4068 14:44:11.103436 0 9 16 | B1->B0 | 3131 2a2a | 1 0 | (0 0) (0 0)
4069 14:44:11.106906 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 14:44:11.113032 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 14:44:11.116736 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 14:44:11.119755 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 14:44:11.126640 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 14:44:11.129997 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 14:44:11.133409 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4076 14:44:11.139619 0 10 16 | B1->B0 | 3131 3a3a | 1 0 | (0 0) (0 0)
4077 14:44:11.142951 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 14:44:11.146447 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 14:44:11.153104 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 14:44:11.156448 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 14:44:11.159493 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 14:44:11.166428 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 14:44:11.169877 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4084 14:44:11.172913 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4085 14:44:11.179507 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 14:44:11.182911 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 14:44:11.186334 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 14:44:11.193014 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 14:44:11.196414 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 14:44:11.199422 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 14:44:11.206274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 14:44:11.209463 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 14:44:11.212792 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 14:44:11.219686 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 14:44:11.223045 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 14:44:11.226136 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 14:44:11.232627 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 14:44:11.235986 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 14:44:11.239332 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4100 14:44:11.245715 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4101 14:44:11.245842 Total UI for P1: 0, mck2ui 16
4102 14:44:11.249001 best dqsien dly found for B0: ( 0, 13, 12)
4103 14:44:11.256097 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 14:44:11.259504 Total UI for P1: 0, mck2ui 16
4105 14:44:11.262184 best dqsien dly found for B1: ( 0, 13, 16)
4106 14:44:11.265701 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4107 14:44:11.268887 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4108 14:44:11.269014
4109 14:44:11.272471 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4110 14:44:11.275351 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4111 14:44:11.278873 [Gating] SW calibration Done
4112 14:44:11.279032 ==
4113 14:44:11.282115 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 14:44:11.285252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 14:44:11.288688 ==
4116 14:44:11.288812 RX Vref Scan: 0
4117 14:44:11.288923
4118 14:44:11.292713 RX Vref 0 -> 0, step: 1
4119 14:44:11.292834
4120 14:44:11.295320 RX Delay -230 -> 252, step: 16
4121 14:44:11.298855 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4122 14:44:11.302115 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4123 14:44:11.305557 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4124 14:44:11.311998 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4125 14:44:11.315153 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4126 14:44:11.318609 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4127 14:44:11.322387 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4128 14:44:11.324825 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4129 14:44:11.331577 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4130 14:44:11.335009 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4131 14:44:11.338434 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4132 14:44:11.341686 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4133 14:44:11.347974 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4134 14:44:11.351893 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4135 14:44:11.354814 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4136 14:44:11.358215 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4137 14:44:11.358297 ==
4138 14:44:11.361630 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 14:44:11.367923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 14:44:11.368005 ==
4141 14:44:11.368070 DQS Delay:
4142 14:44:11.371260 DQS0 = 0, DQS1 = 0
4143 14:44:11.371341 DQM Delay:
4144 14:44:11.371440 DQM0 = 38, DQM1 = 30
4145 14:44:11.374684 DQ Delay:
4146 14:44:11.378242 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4147 14:44:11.381609 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4148 14:44:11.384936 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4149 14:44:11.387650 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4150 14:44:11.387777
4151 14:44:11.387887
4152 14:44:11.387996 ==
4153 14:44:11.391350 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 14:44:11.394654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 14:44:11.394785 ==
4156 14:44:11.394896
4157 14:44:11.395002
4158 14:44:11.397792 TX Vref Scan disable
4159 14:44:11.401236 == TX Byte 0 ==
4160 14:44:11.404243 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4161 14:44:11.407772 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4162 14:44:11.411167 == TX Byte 1 ==
4163 14:44:11.414236 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4164 14:44:11.417669 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4165 14:44:11.417775 ==
4166 14:44:11.420780 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 14:44:11.424161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 14:44:11.427728 ==
4169 14:44:11.427833
4170 14:44:11.427925
4171 14:44:11.428012 TX Vref Scan disable
4172 14:44:11.431686 == TX Byte 0 ==
4173 14:44:11.435076 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4174 14:44:11.441597 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4175 14:44:11.441678 == TX Byte 1 ==
4176 14:44:11.444856 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4177 14:44:11.451619 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4178 14:44:11.451701
4179 14:44:11.451764 [DATLAT]
4180 14:44:11.451823 Freq=600, CH0 RK0
4181 14:44:11.451890
4182 14:44:11.455167 DATLAT Default: 0x9
4183 14:44:11.455247 0, 0xFFFF, sum = 0
4184 14:44:11.458430 1, 0xFFFF, sum = 0
4185 14:44:11.458512 2, 0xFFFF, sum = 0
4186 14:44:11.461256 3, 0xFFFF, sum = 0
4187 14:44:11.464811 4, 0xFFFF, sum = 0
4188 14:44:11.464892 5, 0xFFFF, sum = 0
4189 14:44:11.468236 6, 0xFFFF, sum = 0
4190 14:44:11.468318 7, 0xFFFF, sum = 0
4191 14:44:11.471548 8, 0x0, sum = 1
4192 14:44:11.471629 9, 0x0, sum = 2
4193 14:44:11.471694 10, 0x0, sum = 3
4194 14:44:11.474889 11, 0x0, sum = 4
4195 14:44:11.474971 best_step = 9
4196 14:44:11.475036
4197 14:44:11.475095 ==
4198 14:44:11.478453 Dram Type= 6, Freq= 0, CH_0, rank 0
4199 14:44:11.484551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 14:44:11.484654 ==
4201 14:44:11.484718 RX Vref Scan: 1
4202 14:44:11.484778
4203 14:44:11.488091 RX Vref 0 -> 0, step: 1
4204 14:44:11.488172
4205 14:44:11.491320 RX Delay -195 -> 252, step: 8
4206 14:44:11.491401
4207 14:44:11.494706 Set Vref, RX VrefLevel [Byte0]: 62
4208 14:44:11.498170 [Byte1]: 46
4209 14:44:11.498251
4210 14:44:11.501090 Final RX Vref Byte 0 = 62 to rank0
4211 14:44:11.504422 Final RX Vref Byte 1 = 46 to rank0
4212 14:44:11.507836 Final RX Vref Byte 0 = 62 to rank1
4213 14:44:11.511145 Final RX Vref Byte 1 = 46 to rank1==
4214 14:44:11.514478 Dram Type= 6, Freq= 0, CH_0, rank 0
4215 14:44:11.517979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 14:44:11.518096 ==
4217 14:44:11.521413 DQS Delay:
4218 14:44:11.521493 DQS0 = 0, DQS1 = 0
4219 14:44:11.524373 DQM Delay:
4220 14:44:11.524452 DQM0 = 34, DQM1 = 29
4221 14:44:11.524516 DQ Delay:
4222 14:44:11.527932 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4223 14:44:11.531351 DQ4 =36, DQ5 =20, DQ6 =40, DQ7 =44
4224 14:44:11.534253 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =24
4225 14:44:11.537459 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4226 14:44:11.537540
4227 14:44:11.537603
4228 14:44:11.547570 [DQSOSCAuto] RK0, (LSB)MR18= 0x403f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4229 14:44:11.550660 CH0 RK0: MR19=808, MR18=403F
4230 14:44:11.557631 CH0_RK0: MR19=0x808, MR18=0x403F, DQSOSC=397, MR23=63, INC=166, DEC=110
4231 14:44:11.557712
4232 14:44:11.561041 ----->DramcWriteLeveling(PI) begin...
4233 14:44:11.561116 ==
4234 14:44:11.563860 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 14:44:11.567757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 14:44:11.567830 ==
4237 14:44:11.570580 Write leveling (Byte 0): 32 => 32
4238 14:44:11.573933 Write leveling (Byte 1): 32 => 32
4239 14:44:11.577396 DramcWriteLeveling(PI) end<-----
4240 14:44:11.577468
4241 14:44:11.577529 ==
4242 14:44:11.580910 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 14:44:11.584159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 14:44:11.584256 ==
4245 14:44:11.587169 [Gating] SW mode calibration
4246 14:44:11.594200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4247 14:44:11.600584 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4248 14:44:11.603921 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4249 14:44:11.606811 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 14:44:11.613414 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4251 14:44:11.616788 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4252 14:44:11.619966 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4253 14:44:11.626959 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 14:44:11.630100 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 14:44:11.633392 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 14:44:11.640297 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 14:44:11.643466 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 14:44:11.646400 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 14:44:11.653366 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
4260 14:44:11.656377 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4261 14:44:11.659617 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 14:44:11.666147 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 14:44:11.669515 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 14:44:11.672632 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 14:44:11.679631 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 14:44:11.682935 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 14:44:11.685844 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 14:44:11.692660 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4269 14:44:11.696194 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 14:44:11.699438 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 14:44:11.706195 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 14:44:11.708973 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 14:44:11.712407 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 14:44:11.719075 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 14:44:11.722349 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 14:44:11.726157 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 14:44:11.732453 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 14:44:11.735722 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 14:44:11.738981 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 14:44:11.745691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 14:44:11.748977 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 14:44:11.752178 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 14:44:11.758831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4284 14:44:11.761897 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 14:44:11.765443 Total UI for P1: 0, mck2ui 16
4286 14:44:11.768413 best dqsien dly found for B0: ( 0, 13, 12)
4287 14:44:11.771555 Total UI for P1: 0, mck2ui 16
4288 14:44:11.774802 best dqsien dly found for B1: ( 0, 13, 14)
4289 14:44:11.778165 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4290 14:44:11.781677 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4291 14:44:11.781757
4292 14:44:11.785037 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4293 14:44:11.791443 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4294 14:44:11.791524 [Gating] SW calibration Done
4295 14:44:11.791588 ==
4296 14:44:11.794965 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 14:44:11.801585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 14:44:11.801666 ==
4299 14:44:11.801736 RX Vref Scan: 0
4300 14:44:11.801869
4301 14:44:11.804778 RX Vref 0 -> 0, step: 1
4302 14:44:11.804857
4303 14:44:11.808212 RX Delay -230 -> 252, step: 16
4304 14:44:11.811571 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4305 14:44:11.814439 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4306 14:44:11.821203 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4307 14:44:11.824450 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4308 14:44:11.827703 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4309 14:44:11.831153 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4310 14:44:11.834469 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4311 14:44:11.841175 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4312 14:44:11.844432 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4313 14:44:11.847718 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4314 14:44:11.851218 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4315 14:44:11.857631 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4316 14:44:11.860954 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4317 14:44:11.864163 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4318 14:44:11.867547 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4319 14:44:11.874463 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4320 14:44:11.874585 ==
4321 14:44:11.877866 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 14:44:11.880541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 14:44:11.880669 ==
4324 14:44:11.880790 DQS Delay:
4325 14:44:11.884377 DQS0 = 0, DQS1 = 0
4326 14:44:11.884497 DQM Delay:
4327 14:44:11.887460 DQM0 = 37, DQM1 = 31
4328 14:44:11.887579 DQ Delay:
4329 14:44:11.890896 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4330 14:44:11.893832 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4331 14:44:11.897372 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4332 14:44:11.900888 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4333 14:44:11.900969
4334 14:44:11.901032
4335 14:44:11.901092 ==
4336 14:44:11.904103 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 14:44:11.907248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 14:44:11.907330 ==
4339 14:44:11.907395
4340 14:44:11.910653
4341 14:44:11.910733 TX Vref Scan disable
4342 14:44:11.914070 == TX Byte 0 ==
4343 14:44:11.917019 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4344 14:44:11.920464 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4345 14:44:11.923917 == TX Byte 1 ==
4346 14:44:11.927296 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4347 14:44:11.930356 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4348 14:44:11.930439 ==
4349 14:44:11.933681 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 14:44:11.940450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 14:44:11.940531 ==
4352 14:44:11.940634
4353 14:44:11.940694
4354 14:44:11.943228 TX Vref Scan disable
4355 14:44:11.943309 == TX Byte 0 ==
4356 14:44:11.950257 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4357 14:44:11.953610 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4358 14:44:11.953691 == TX Byte 1 ==
4359 14:44:11.960081 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4360 14:44:11.963392 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4361 14:44:11.963466
4362 14:44:11.963527 [DATLAT]
4363 14:44:11.966464 Freq=600, CH0 RK1
4364 14:44:11.966535
4365 14:44:11.966594 DATLAT Default: 0x9
4366 14:44:11.969894 0, 0xFFFF, sum = 0
4367 14:44:11.969970 1, 0xFFFF, sum = 0
4368 14:44:11.972999 2, 0xFFFF, sum = 0
4369 14:44:11.973123 3, 0xFFFF, sum = 0
4370 14:44:11.976755 4, 0xFFFF, sum = 0
4371 14:44:11.976875 5, 0xFFFF, sum = 0
4372 14:44:11.979671 6, 0xFFFF, sum = 0
4373 14:44:11.983149 7, 0xFFFF, sum = 0
4374 14:44:11.983264 8, 0x0, sum = 1
4375 14:44:11.983378 9, 0x0, sum = 2
4376 14:44:11.986671 10, 0x0, sum = 3
4377 14:44:11.986795 11, 0x0, sum = 4
4378 14:44:11.989736 best_step = 9
4379 14:44:11.989853
4380 14:44:11.989955 ==
4381 14:44:11.993181 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 14:44:11.996417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 14:44:11.996537 ==
4384 14:44:11.999580 RX Vref Scan: 0
4385 14:44:11.999662
4386 14:44:11.999725 RX Vref 0 -> 0, step: 1
4387 14:44:11.999784
4388 14:44:12.003020 RX Delay -195 -> 252, step: 8
4389 14:44:12.010279 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4390 14:44:12.013693 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4391 14:44:12.017138 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4392 14:44:12.020587 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4393 14:44:12.026837 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4394 14:44:12.030160 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4395 14:44:12.033457 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4396 14:44:12.036627 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4397 14:44:12.043641 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4398 14:44:12.046519 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4399 14:44:12.049840 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4400 14:44:12.053293 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4401 14:44:12.056740 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4402 14:44:12.063324 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4403 14:44:12.066712 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4404 14:44:12.070091 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4405 14:44:12.070219 ==
4406 14:44:12.073612 Dram Type= 6, Freq= 0, CH_0, rank 1
4407 14:44:12.076940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 14:44:12.079850 ==
4409 14:44:12.079929 DQS Delay:
4410 14:44:12.079992 DQS0 = 0, DQS1 = 0
4411 14:44:12.083143 DQM Delay:
4412 14:44:12.083245 DQM0 = 33, DQM1 = 27
4413 14:44:12.086721 DQ Delay:
4414 14:44:12.089887 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4415 14:44:12.089968 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4416 14:44:12.093222 DQ8 =16, DQ9 =12, DQ10 =28, DQ11 =16
4417 14:44:12.099807 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4418 14:44:12.099888
4419 14:44:12.099951
4420 14:44:12.106264 [DQSOSCAuto] RK1, (LSB)MR18= 0x6838, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4421 14:44:12.110097 CH0 RK1: MR19=808, MR18=6838
4422 14:44:12.116554 CH0_RK1: MR19=0x808, MR18=0x6838, DQSOSC=390, MR23=63, INC=172, DEC=114
4423 14:44:12.119513 [RxdqsGatingPostProcess] freq 600
4424 14:44:12.122942 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4425 14:44:12.126363 Pre-setting of DQS Precalculation
4426 14:44:12.133049 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4427 14:44:12.133171 ==
4428 14:44:12.136454 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 14:44:12.139750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 14:44:12.139872 ==
4431 14:44:12.146398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 14:44:12.149726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4433 14:44:12.154221 [CA 0] Center 36 (6~66) winsize 61
4434 14:44:12.157373 [CA 1] Center 36 (6~66) winsize 61
4435 14:44:12.160630 [CA 2] Center 34 (4~65) winsize 62
4436 14:44:12.163925 [CA 3] Center 34 (4~65) winsize 62
4437 14:44:12.167167 [CA 4] Center 34 (4~65) winsize 62
4438 14:44:12.170425 [CA 5] Center 33 (3~64) winsize 62
4439 14:44:12.170545
4440 14:44:12.173812 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4441 14:44:12.173915
4442 14:44:12.177110 [CATrainingPosCal] consider 1 rank data
4443 14:44:12.180597 u2DelayCellTimex100 = 270/100 ps
4444 14:44:12.183872 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4445 14:44:12.190611 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4446 14:44:12.193699 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 14:44:12.197281 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4448 14:44:12.200678 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 14:44:12.203857 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 14:44:12.203959
4451 14:44:12.207216 CA PerBit enable=1, Macro0, CA PI delay=33
4452 14:44:12.207301
4453 14:44:12.210584 [CBTSetCACLKResult] CA Dly = 33
4454 14:44:12.210665 CS Dly: 4 (0~35)
4455 14:44:12.210731 ==
4456 14:44:12.213739 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 14:44:12.220400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 14:44:12.220482 ==
4459 14:44:12.223781 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4460 14:44:12.230709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4461 14:44:12.234054 [CA 0] Center 36 (6~66) winsize 61
4462 14:44:12.237399 [CA 1] Center 36 (6~66) winsize 61
4463 14:44:12.240755 [CA 2] Center 34 (4~65) winsize 62
4464 14:44:12.243723 [CA 3] Center 34 (3~65) winsize 63
4465 14:44:12.247234 [CA 4] Center 34 (4~65) winsize 62
4466 14:44:12.250719 [CA 5] Center 33 (3~64) winsize 62
4467 14:44:12.250846
4468 14:44:12.253614 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4469 14:44:12.253741
4470 14:44:12.257440 [CATrainingPosCal] consider 2 rank data
4471 14:44:12.260900 u2DelayCellTimex100 = 270/100 ps
4472 14:44:12.263807 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4473 14:44:12.270348 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4474 14:44:12.273836 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4475 14:44:12.277029 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4476 14:44:12.280595 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4477 14:44:12.283793 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4478 14:44:12.283913
4479 14:44:12.287408 CA PerBit enable=1, Macro0, CA PI delay=33
4480 14:44:12.287505
4481 14:44:12.290150 [CBTSetCACLKResult] CA Dly = 33
4482 14:44:12.290269 CS Dly: 5 (0~37)
4483 14:44:12.294023
4484 14:44:12.296821 ----->DramcWriteLeveling(PI) begin...
4485 14:44:12.296958 ==
4486 14:44:12.300202 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 14:44:12.303755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 14:44:12.303870 ==
4489 14:44:12.307110 Write leveling (Byte 0): 26 => 26
4490 14:44:12.310327 Write leveling (Byte 1): 30 => 30
4491 14:44:12.313462 DramcWriteLeveling(PI) end<-----
4492 14:44:12.313544
4493 14:44:12.313607 ==
4494 14:44:12.316880 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 14:44:12.319984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 14:44:12.320065 ==
4497 14:44:12.323305 [Gating] SW mode calibration
4498 14:44:12.330308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4499 14:44:12.336949 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4500 14:44:12.340316 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4501 14:44:12.343296 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4502 14:44:12.350203 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4503 14:44:12.353795 0 9 12 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 0)
4504 14:44:12.357086 0 9 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4505 14:44:12.363865 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 14:44:12.366602 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 14:44:12.370221 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 14:44:12.373476 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 14:44:12.380094 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 14:44:12.383464 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 14:44:12.386692 0 10 12 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
4512 14:44:12.393280 0 10 16 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
4513 14:44:12.396488 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 14:44:12.399741 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 14:44:12.406706 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 14:44:12.409972 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 14:44:12.413032 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 14:44:12.419413 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 14:44:12.422824 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 14:44:12.426434 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 14:44:12.433047 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 14:44:12.435957 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 14:44:12.439365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 14:44:12.446335 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 14:44:12.449486 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 14:44:12.452916 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 14:44:12.459194 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 14:44:12.462515 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 14:44:12.465995 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 14:44:12.472515 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 14:44:12.475598 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 14:44:12.478974 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 14:44:12.485624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 14:44:12.489000 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 14:44:12.492121 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4536 14:44:12.498944 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 14:44:12.499040 Total UI for P1: 0, mck2ui 16
4538 14:44:12.505469 best dqsien dly found for B0: ( 0, 13, 12)
4539 14:44:12.505582 Total UI for P1: 0, mck2ui 16
4540 14:44:12.512281 best dqsien dly found for B1: ( 0, 13, 12)
4541 14:44:12.515692 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4542 14:44:12.519120 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4543 14:44:12.519202
4544 14:44:12.522297 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4545 14:44:12.525357 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4546 14:44:12.528959 [Gating] SW calibration Done
4547 14:44:12.529040 ==
4548 14:44:12.532041 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 14:44:12.535565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 14:44:12.535648 ==
4551 14:44:12.538812 RX Vref Scan: 0
4552 14:44:12.538893
4553 14:44:12.538958 RX Vref 0 -> 0, step: 1
4554 14:44:12.542316
4555 14:44:12.542398 RX Delay -230 -> 252, step: 16
4556 14:44:12.548745 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4557 14:44:12.552256 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4558 14:44:12.555255 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4559 14:44:12.558623 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4560 14:44:12.565347 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4561 14:44:12.568208 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4562 14:44:12.571692 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4563 14:44:12.575435 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4564 14:44:12.578437 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4565 14:44:12.584961 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4566 14:44:12.588705 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4567 14:44:12.591844 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4568 14:44:12.595397 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4569 14:44:12.601536 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4570 14:44:12.605396 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4571 14:44:12.608500 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4572 14:44:12.608616 ==
4573 14:44:12.611925 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 14:44:12.615250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 14:44:12.618222 ==
4576 14:44:12.618304 DQS Delay:
4577 14:44:12.618369 DQS0 = 0, DQS1 = 0
4578 14:44:12.621491 DQM Delay:
4579 14:44:12.621573 DQM0 = 38, DQM1 = 28
4580 14:44:12.624857 DQ Delay:
4581 14:44:12.624939 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4582 14:44:12.628358 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4583 14:44:12.631583 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4584 14:44:12.635041 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4585 14:44:12.635124
4586 14:44:12.638326
4587 14:44:12.638406 ==
4588 14:44:12.641448 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 14:44:12.644818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 14:44:12.644940 ==
4591 14:44:12.645005
4592 14:44:12.645064
4593 14:44:12.648430 TX Vref Scan disable
4594 14:44:12.648511 == TX Byte 0 ==
4595 14:44:12.654616 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4596 14:44:12.657942 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4597 14:44:12.658024 == TX Byte 1 ==
4598 14:44:12.664869 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4599 14:44:12.667740 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4600 14:44:12.667821 ==
4601 14:44:12.671083 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 14:44:12.674477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 14:44:12.674559 ==
4604 14:44:12.674623
4605 14:44:12.674683
4606 14:44:12.677813 TX Vref Scan disable
4607 14:44:12.681290 == TX Byte 0 ==
4608 14:44:12.684329 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4609 14:44:12.687792 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4610 14:44:12.691331 == TX Byte 1 ==
4611 14:44:12.694304 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4612 14:44:12.700843 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4613 14:44:12.700925
4614 14:44:12.700990 [DATLAT]
4615 14:44:12.701051 Freq=600, CH1 RK0
4616 14:44:12.701111
4617 14:44:12.704262 DATLAT Default: 0x9
4618 14:44:12.704343 0, 0xFFFF, sum = 0
4619 14:44:12.707417 1, 0xFFFF, sum = 0
4620 14:44:12.707500 2, 0xFFFF, sum = 0
4621 14:44:12.710833 3, 0xFFFF, sum = 0
4622 14:44:12.714223 4, 0xFFFF, sum = 0
4623 14:44:12.714305 5, 0xFFFF, sum = 0
4624 14:44:12.717438 6, 0xFFFF, sum = 0
4625 14:44:12.717525 7, 0xFFFF, sum = 0
4626 14:44:12.721146 8, 0x0, sum = 1
4627 14:44:12.721229 9, 0x0, sum = 2
4628 14:44:12.721295 10, 0x0, sum = 3
4629 14:44:12.724078 11, 0x0, sum = 4
4630 14:44:12.724160 best_step = 9
4631 14:44:12.724224
4632 14:44:12.724284 ==
4633 14:44:12.727498 Dram Type= 6, Freq= 0, CH_1, rank 0
4634 14:44:12.734237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 14:44:12.734321 ==
4636 14:44:12.734386 RX Vref Scan: 1
4637 14:44:12.734447
4638 14:44:12.737571 RX Vref 0 -> 0, step: 1
4639 14:44:12.737652
4640 14:44:12.740490 RX Delay -195 -> 252, step: 8
4641 14:44:12.740612
4642 14:44:12.744154 Set Vref, RX VrefLevel [Byte0]: 59
4643 14:44:12.747407 [Byte1]: 48
4644 14:44:12.747489
4645 14:44:12.750827 Final RX Vref Byte 0 = 59 to rank0
4646 14:44:12.753934 Final RX Vref Byte 1 = 48 to rank0
4647 14:44:12.757222 Final RX Vref Byte 0 = 59 to rank1
4648 14:44:12.760845 Final RX Vref Byte 1 = 48 to rank1==
4649 14:44:12.763945 Dram Type= 6, Freq= 0, CH_1, rank 0
4650 14:44:12.766807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 14:44:12.766888 ==
4652 14:44:12.770206 DQS Delay:
4653 14:44:12.770313 DQS0 = 0, DQS1 = 0
4654 14:44:12.773773 DQM Delay:
4655 14:44:12.773855 DQM0 = 38, DQM1 = 29
4656 14:44:12.773920 DQ Delay:
4657 14:44:12.776970 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4658 14:44:12.780387 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4659 14:44:12.783879 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =24
4660 14:44:12.786705 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4661 14:44:12.786786
4662 14:44:12.786850
4663 14:44:12.796720 [DQSOSCAuto] RK0, (LSB)MR18= 0x202d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4664 14:44:12.800209 CH1 RK0: MR19=808, MR18=202D
4665 14:44:12.807027 CH1_RK0: MR19=0x808, MR18=0x202D, DQSOSC=401, MR23=63, INC=163, DEC=108
4666 14:44:12.807109
4667 14:44:12.810064 ----->DramcWriteLeveling(PI) begin...
4668 14:44:12.810147 ==
4669 14:44:12.813936 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 14:44:12.816821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 14:44:12.816903 ==
4672 14:44:12.820103 Write leveling (Byte 0): 30 => 30
4673 14:44:12.823333 Write leveling (Byte 1): 30 => 30
4674 14:44:12.826925 DramcWriteLeveling(PI) end<-----
4675 14:44:12.827006
4676 14:44:12.827070 ==
4677 14:44:12.829836 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 14:44:12.833608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 14:44:12.833690 ==
4680 14:44:12.836498 [Gating] SW mode calibration
4681 14:44:12.843156 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4682 14:44:12.850247 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4683 14:44:12.853213 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4684 14:44:12.856774 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4685 14:44:12.863046 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4686 14:44:12.866375 0 9 12 | B1->B0 | 3232 2e2e | 0 1 | (0 1) (1 0)
4687 14:44:12.870000 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 14:44:12.876449 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 14:44:12.879941 0 9 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4690 14:44:12.883266 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 14:44:12.889623 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 14:44:12.892958 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 14:44:12.896317 0 10 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4694 14:44:12.902986 0 10 12 | B1->B0 | 2424 3e3e | 1 0 | (0 0) (0 0)
4695 14:44:12.906290 0 10 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
4696 14:44:12.909800 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 14:44:12.916230 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 14:44:12.920166 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 14:44:12.923051 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 14:44:12.929427 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 14:44:12.932743 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4702 14:44:12.936277 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4703 14:44:12.942726 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 14:44:12.946237 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 14:44:12.949680 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 14:44:12.955624 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 14:44:12.959325 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 14:44:12.962458 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 14:44:12.969035 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 14:44:12.972415 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 14:44:12.975690 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 14:44:12.982540 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 14:44:12.985335 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 14:44:12.988744 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 14:44:12.995626 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 14:44:12.998948 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 14:44:13.002223 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 14:44:13.008766 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4719 14:44:13.011683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 14:44:13.015439 Total UI for P1: 0, mck2ui 16
4721 14:44:13.018605 best dqsien dly found for B0: ( 0, 13, 12)
4722 14:44:13.021655 Total UI for P1: 0, mck2ui 16
4723 14:44:13.025453 best dqsien dly found for B1: ( 0, 13, 14)
4724 14:44:13.028889 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4725 14:44:13.032038 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4726 14:44:13.032120
4727 14:44:13.035224 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4728 14:44:13.038396 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4729 14:44:13.041763 [Gating] SW calibration Done
4730 14:44:13.041844 ==
4731 14:44:13.045237 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 14:44:13.048469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 14:44:13.051880 ==
4734 14:44:13.051962 RX Vref Scan: 0
4735 14:44:13.052027
4736 14:44:13.055277 RX Vref 0 -> 0, step: 1
4737 14:44:13.055359
4738 14:44:13.058678 RX Delay -230 -> 252, step: 16
4739 14:44:13.061439 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4740 14:44:13.064953 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4741 14:44:13.068151 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4742 14:44:13.075006 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4743 14:44:13.078481 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4744 14:44:13.081214 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4745 14:44:13.085027 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4746 14:44:13.087857 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4747 14:44:13.094811 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4748 14:44:13.098119 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4749 14:44:13.101094 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4750 14:44:13.104452 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4751 14:44:13.111494 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4752 14:44:13.114854 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4753 14:44:13.117851 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4754 14:44:13.121256 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4755 14:44:13.121338 ==
4756 14:44:13.124379 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 14:44:13.131116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 14:44:13.131200 ==
4759 14:44:13.131264 DQS Delay:
4760 14:44:13.134371 DQS0 = 0, DQS1 = 0
4761 14:44:13.134495 DQM Delay:
4762 14:44:13.134604 DQM0 = 36, DQM1 = 29
4763 14:44:13.137718 DQ Delay:
4764 14:44:13.140983 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4765 14:44:13.145019 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4766 14:44:13.147586 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4767 14:44:13.151000 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4768 14:44:13.151081
4769 14:44:13.151145
4770 14:44:13.151204 ==
4771 14:44:13.154412 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 14:44:13.157832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 14:44:13.157914 ==
4774 14:44:13.157979
4775 14:44:13.158039
4776 14:44:13.161269 TX Vref Scan disable
4777 14:44:13.164109 == TX Byte 0 ==
4778 14:44:13.167755 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4779 14:44:13.171095 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4780 14:44:13.174546 == TX Byte 1 ==
4781 14:44:13.177795 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4782 14:44:13.180933 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4783 14:44:13.181015 ==
4784 14:44:13.184247 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 14:44:13.187577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 14:44:13.190813 ==
4787 14:44:13.190894
4788 14:44:13.190959
4789 14:44:13.191018 TX Vref Scan disable
4790 14:44:13.194278 == TX Byte 0 ==
4791 14:44:13.197620 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4792 14:44:13.204354 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4793 14:44:13.204448 == TX Byte 1 ==
4794 14:44:13.207914 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4795 14:44:13.214455 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4796 14:44:13.214537
4797 14:44:13.214601 [DATLAT]
4798 14:44:13.214661 Freq=600, CH1 RK1
4799 14:44:13.214720
4800 14:44:13.217731 DATLAT Default: 0x9
4801 14:44:13.217812 0, 0xFFFF, sum = 0
4802 14:44:13.221127 1, 0xFFFF, sum = 0
4803 14:44:13.224709 2, 0xFFFF, sum = 0
4804 14:44:13.224791 3, 0xFFFF, sum = 0
4805 14:44:13.227508 4, 0xFFFF, sum = 0
4806 14:44:13.227590 5, 0xFFFF, sum = 0
4807 14:44:13.230792 6, 0xFFFF, sum = 0
4808 14:44:13.230875 7, 0xFFFF, sum = 0
4809 14:44:13.234147 8, 0x0, sum = 1
4810 14:44:13.234229 9, 0x0, sum = 2
4811 14:44:13.234294 10, 0x0, sum = 3
4812 14:44:13.237746 11, 0x0, sum = 4
4813 14:44:13.237828 best_step = 9
4814 14:44:13.237893
4815 14:44:13.237953 ==
4816 14:44:13.240630 Dram Type= 6, Freq= 0, CH_1, rank 1
4817 14:44:13.248074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4818 14:44:13.248156 ==
4819 14:44:13.248220 RX Vref Scan: 0
4820 14:44:13.248280
4821 14:44:13.250835 RX Vref 0 -> 0, step: 1
4822 14:44:13.250916
4823 14:44:13.254017 RX Delay -195 -> 252, step: 8
4824 14:44:13.257291 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4825 14:44:13.264032 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4826 14:44:13.267348 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4827 14:44:13.270577 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4828 14:44:13.274239 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4829 14:44:13.280885 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4830 14:44:13.283978 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4831 14:44:13.287086 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4832 14:44:13.290484 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4833 14:44:13.294035 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4834 14:44:13.300303 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4835 14:44:13.303604 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4836 14:44:13.307178 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4837 14:44:13.313788 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4838 14:44:13.317232 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4839 14:44:13.320079 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4840 14:44:13.320161 ==
4841 14:44:13.323808 Dram Type= 6, Freq= 0, CH_1, rank 1
4842 14:44:13.326873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4843 14:44:13.326956 ==
4844 14:44:13.330370 DQS Delay:
4845 14:44:13.330452 DQS0 = 0, DQS1 = 0
4846 14:44:13.333706 DQM Delay:
4847 14:44:13.333787 DQM0 = 36, DQM1 = 30
4848 14:44:13.333852 DQ Delay:
4849 14:44:13.336758 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4850 14:44:13.340088 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4851 14:44:13.343478 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4852 14:44:13.346631 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4853 14:44:13.346712
4854 14:44:13.346776
4855 14:44:13.356369 [DQSOSCAuto] RK1, (LSB)MR18= 0x3959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4856 14:44:13.359855 CH1 RK1: MR19=808, MR18=3959
4857 14:44:13.366812 CH1_RK1: MR19=0x808, MR18=0x3959, DQSOSC=393, MR23=63, INC=169, DEC=113
4858 14:44:13.370184 [RxdqsGatingPostProcess] freq 600
4859 14:44:13.373108 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4860 14:44:13.376152 Pre-setting of DQS Precalculation
4861 14:44:13.379812 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4862 14:44:13.389410 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4863 14:44:13.396459 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4864 14:44:13.396542
4865 14:44:13.396703
4866 14:44:13.399716 [Calibration Summary] 1200 Mbps
4867 14:44:13.399798 CH 0, Rank 0
4868 14:44:13.402766 SW Impedance : PASS
4869 14:44:13.402847 DUTY Scan : NO K
4870 14:44:13.406178 ZQ Calibration : PASS
4871 14:44:13.409546 Jitter Meter : NO K
4872 14:44:13.409627 CBT Training : PASS
4873 14:44:13.412986 Write leveling : PASS
4874 14:44:13.415843 RX DQS gating : PASS
4875 14:44:13.415924 RX DQ/DQS(RDDQC) : PASS
4876 14:44:13.419255 TX DQ/DQS : PASS
4877 14:44:13.422413 RX DATLAT : PASS
4878 14:44:13.422494 RX DQ/DQS(Engine): PASS
4879 14:44:13.426287 TX OE : NO K
4880 14:44:13.426367 All Pass.
4881 14:44:13.426432
4882 14:44:13.429039 CH 0, Rank 1
4883 14:44:13.429110 SW Impedance : PASS
4884 14:44:13.432553 DUTY Scan : NO K
4885 14:44:13.436062 ZQ Calibration : PASS
4886 14:44:13.436144 Jitter Meter : NO K
4887 14:44:13.439443 CBT Training : PASS
4888 14:44:13.442329 Write leveling : PASS
4889 14:44:13.442399 RX DQS gating : PASS
4890 14:44:13.445795 RX DQ/DQS(RDDQC) : PASS
4891 14:44:13.449165 TX DQ/DQS : PASS
4892 14:44:13.449235 RX DATLAT : PASS
4893 14:44:13.452528 RX DQ/DQS(Engine): PASS
4894 14:44:13.455938 TX OE : NO K
4895 14:44:13.456017 All Pass.
4896 14:44:13.456082
4897 14:44:13.456139 CH 1, Rank 0
4898 14:44:13.459152 SW Impedance : PASS
4899 14:44:13.462621 DUTY Scan : NO K
4900 14:44:13.462692 ZQ Calibration : PASS
4901 14:44:13.465523 Jitter Meter : NO K
4902 14:44:13.465592 CBT Training : PASS
4903 14:44:13.469209 Write leveling : PASS
4904 14:44:13.472105 RX DQS gating : PASS
4905 14:44:13.472177 RX DQ/DQS(RDDQC) : PASS
4906 14:44:13.475406 TX DQ/DQS : PASS
4907 14:44:13.479161 RX DATLAT : PASS
4908 14:44:13.479232 RX DQ/DQS(Engine): PASS
4909 14:44:13.482293 TX OE : NO K
4910 14:44:13.482362 All Pass.
4911 14:44:13.482421
4912 14:44:13.485690 CH 1, Rank 1
4913 14:44:13.485759 SW Impedance : PASS
4914 14:44:13.488909 DUTY Scan : NO K
4915 14:44:13.492112 ZQ Calibration : PASS
4916 14:44:13.492183 Jitter Meter : NO K
4917 14:44:13.495894 CBT Training : PASS
4918 14:44:13.498756 Write leveling : PASS
4919 14:44:13.498842 RX DQS gating : PASS
4920 14:44:13.502216 RX DQ/DQS(RDDQC) : PASS
4921 14:44:13.505506 TX DQ/DQS : PASS
4922 14:44:13.505627 RX DATLAT : PASS
4923 14:44:13.508805 RX DQ/DQS(Engine): PASS
4924 14:44:13.512095 TX OE : NO K
4925 14:44:13.512212 All Pass.
4926 14:44:13.512328
4927 14:44:13.512434 DramC Write-DBI off
4928 14:44:13.515104 PER_BANK_REFRESH: Hybrid Mode
4929 14:44:13.518430 TX_TRACKING: ON
4930 14:44:13.525119 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4931 14:44:13.528814 [FAST_K] Save calibration result to emmc
4932 14:44:13.535108 dramc_set_vcore_voltage set vcore to 662500
4933 14:44:13.535189 Read voltage for 933, 3
4934 14:44:13.538452 Vio18 = 0
4935 14:44:13.538532 Vcore = 662500
4936 14:44:13.538596 Vdram = 0
4937 14:44:13.538656 Vddq = 0
4938 14:44:13.541898 Vmddr = 0
4939 14:44:13.545382 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4940 14:44:13.552122 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4941 14:44:13.555378 MEM_TYPE=3, freq_sel=17
4942 14:44:13.555458 sv_algorithm_assistance_LP4_1600
4943 14:44:13.562355 ============ PULL DRAM RESETB DOWN ============
4944 14:44:13.565296 ========== PULL DRAM RESETB DOWN end =========
4945 14:44:13.568501 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4946 14:44:13.572236 ===================================
4947 14:44:13.575221 LPDDR4 DRAM CONFIGURATION
4948 14:44:13.578481 ===================================
4949 14:44:13.581773 EX_ROW_EN[0] = 0x0
4950 14:44:13.581853 EX_ROW_EN[1] = 0x0
4951 14:44:13.584984 LP4Y_EN = 0x0
4952 14:44:13.585085 WORK_FSP = 0x0
4953 14:44:13.588469 WL = 0x3
4954 14:44:13.588575 RL = 0x3
4955 14:44:13.591894 BL = 0x2
4956 14:44:13.591974 RPST = 0x0
4957 14:44:13.595203 RD_PRE = 0x0
4958 14:44:13.595283 WR_PRE = 0x1
4959 14:44:13.598290 WR_PST = 0x0
4960 14:44:13.598370 DBI_WR = 0x0
4961 14:44:13.601794 DBI_RD = 0x0
4962 14:44:13.601879 OTF = 0x1
4963 14:44:13.604844 ===================================
4964 14:44:13.608270 ===================================
4965 14:44:13.611695 ANA top config
4966 14:44:13.614792 ===================================
4967 14:44:13.618098 DLL_ASYNC_EN = 0
4968 14:44:13.618180 ALL_SLAVE_EN = 1
4969 14:44:13.621855 NEW_RANK_MODE = 1
4970 14:44:13.624879 DLL_IDLE_MODE = 1
4971 14:44:13.627943 LP45_APHY_COMB_EN = 1
4972 14:44:13.631379 TX_ODT_DIS = 1
4973 14:44:13.631484 NEW_8X_MODE = 1
4974 14:44:13.634651 ===================================
4975 14:44:13.638085 ===================================
4976 14:44:13.641540 data_rate = 1866
4977 14:44:13.645077 CKR = 1
4978 14:44:13.648282 DQ_P2S_RATIO = 8
4979 14:44:13.651714 ===================================
4980 14:44:13.654660 CA_P2S_RATIO = 8
4981 14:44:13.654730 DQ_CA_OPEN = 0
4982 14:44:13.658018 DQ_SEMI_OPEN = 0
4983 14:44:13.662086 CA_SEMI_OPEN = 0
4984 14:44:13.664830 CA_FULL_RATE = 0
4985 14:44:13.668224 DQ_CKDIV4_EN = 1
4986 14:44:13.671470 CA_CKDIV4_EN = 1
4987 14:44:13.671580 CA_PREDIV_EN = 0
4988 14:44:13.674855 PH8_DLY = 0
4989 14:44:13.677712 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4990 14:44:13.681813 DQ_AAMCK_DIV = 4
4991 14:44:13.684693 CA_AAMCK_DIV = 4
4992 14:44:13.687765 CA_ADMCK_DIV = 4
4993 14:44:13.687846 DQ_TRACK_CA_EN = 0
4994 14:44:13.691106 CA_PICK = 933
4995 14:44:13.694436 CA_MCKIO = 933
4996 14:44:13.697921 MCKIO_SEMI = 0
4997 14:44:13.701506 PLL_FREQ = 3732
4998 14:44:13.704838 DQ_UI_PI_RATIO = 32
4999 14:44:13.708021 CA_UI_PI_RATIO = 0
5000 14:44:13.711093 ===================================
5001 14:44:13.714989 ===================================
5002 14:44:13.715071 memory_type:LPDDR4
5003 14:44:13.718291 GP_NUM : 10
5004 14:44:13.721197 SRAM_EN : 1
5005 14:44:13.721304 MD32_EN : 0
5006 14:44:13.724549 ===================================
5007 14:44:13.727832 [ANA_INIT] >>>>>>>>>>>>>>
5008 14:44:13.730878 <<<<<< [CONFIGURE PHASE]: ANA_TX
5009 14:44:13.734051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5010 14:44:13.737670 ===================================
5011 14:44:13.741036 data_rate = 1866,PCW = 0X8f00
5012 14:44:13.743999 ===================================
5013 14:44:13.747344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5014 14:44:13.750642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5015 14:44:13.757428 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5016 14:44:13.760905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5017 14:44:13.767137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5018 14:44:13.770600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5019 14:44:13.770673 [ANA_INIT] flow start
5020 14:44:13.774058 [ANA_INIT] PLL >>>>>>>>
5021 14:44:13.776857 [ANA_INIT] PLL <<<<<<<<
5022 14:44:13.776958 [ANA_INIT] MIDPI >>>>>>>>
5023 14:44:13.780191 [ANA_INIT] MIDPI <<<<<<<<
5024 14:44:13.783617 [ANA_INIT] DLL >>>>>>>>
5025 14:44:13.783688 [ANA_INIT] flow end
5026 14:44:13.790446 ============ LP4 DIFF to SE enter ============
5027 14:44:13.793564 ============ LP4 DIFF to SE exit ============
5028 14:44:13.793637 [ANA_INIT] <<<<<<<<<<<<<
5029 14:44:13.796734 [Flow] Enable top DCM control >>>>>
5030 14:44:13.800199 [Flow] Enable top DCM control <<<<<
5031 14:44:13.803192 Enable DLL master slave shuffle
5032 14:44:13.809763 ==============================================================
5033 14:44:13.813050 Gating Mode config
5034 14:44:13.816997 ==============================================================
5035 14:44:13.820329 Config description:
5036 14:44:13.830175 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5037 14:44:13.836458 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5038 14:44:13.839457 SELPH_MODE 0: By rank 1: By Phase
5039 14:44:13.846153 ==============================================================
5040 14:44:13.849617 GAT_TRACK_EN = 1
5041 14:44:13.852708 RX_GATING_MODE = 2
5042 14:44:13.856026 RX_GATING_TRACK_MODE = 2
5043 14:44:13.859362 SELPH_MODE = 1
5044 14:44:13.859437 PICG_EARLY_EN = 1
5045 14:44:13.862710 VALID_LAT_VALUE = 1
5046 14:44:13.869761 ==============================================================
5047 14:44:13.873105 Enter into Gating configuration >>>>
5048 14:44:13.875876 Exit from Gating configuration <<<<
5049 14:44:13.879336 Enter into DVFS_PRE_config >>>>>
5050 14:44:13.889507 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5051 14:44:13.892426 Exit from DVFS_PRE_config <<<<<
5052 14:44:13.895928 Enter into PICG configuration >>>>
5053 14:44:13.899536 Exit from PICG configuration <<<<
5054 14:44:13.902280 [RX_INPUT] configuration >>>>>
5055 14:44:13.905796 [RX_INPUT] configuration <<<<<
5056 14:44:13.909368 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5057 14:44:13.915898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5058 14:44:13.922576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5059 14:44:13.928534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5060 14:44:13.935268 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5061 14:44:13.941712 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5062 14:44:13.945411 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5063 14:44:13.948503 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5064 14:44:13.951805 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5065 14:44:13.958561 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5066 14:44:13.961937 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5067 14:44:13.965923 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5068 14:44:13.968697 ===================================
5069 14:44:13.972111 LPDDR4 DRAM CONFIGURATION
5070 14:44:13.974858 ===================================
5071 14:44:13.974940 EX_ROW_EN[0] = 0x0
5072 14:44:13.978584 EX_ROW_EN[1] = 0x0
5073 14:44:13.978660 LP4Y_EN = 0x0
5074 14:44:13.981794 WORK_FSP = 0x0
5075 14:44:13.985150 WL = 0x3
5076 14:44:13.985239 RL = 0x3
5077 14:44:13.988080 BL = 0x2
5078 14:44:13.988196 RPST = 0x0
5079 14:44:13.991520 RD_PRE = 0x0
5080 14:44:13.991590 WR_PRE = 0x1
5081 14:44:13.995155 WR_PST = 0x0
5082 14:44:13.995249 DBI_WR = 0x0
5083 14:44:13.998088 DBI_RD = 0x0
5084 14:44:13.998171 OTF = 0x1
5085 14:44:14.001642 ===================================
5086 14:44:14.004891 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5087 14:44:14.011214 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5088 14:44:14.014595 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5089 14:44:14.018056 ===================================
5090 14:44:14.021350 LPDDR4 DRAM CONFIGURATION
5091 14:44:14.024540 ===================================
5092 14:44:14.024643 EX_ROW_EN[0] = 0x10
5093 14:44:14.028128 EX_ROW_EN[1] = 0x0
5094 14:44:14.028207 LP4Y_EN = 0x0
5095 14:44:14.031313 WORK_FSP = 0x0
5096 14:44:14.034726 WL = 0x3
5097 14:44:14.034842 RL = 0x3
5098 14:44:14.037743 BL = 0x2
5099 14:44:14.037826 RPST = 0x0
5100 14:44:14.041149 RD_PRE = 0x0
5101 14:44:14.041261 WR_PRE = 0x1
5102 14:44:14.044424 WR_PST = 0x0
5103 14:44:14.044505 DBI_WR = 0x0
5104 14:44:14.048102 DBI_RD = 0x0
5105 14:44:14.048183 OTF = 0x1
5106 14:44:14.051528 ===================================
5107 14:44:14.057667 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5108 14:44:14.061767 nWR fixed to 30
5109 14:44:14.065214 [ModeRegInit_LP4] CH0 RK0
5110 14:44:14.065295 [ModeRegInit_LP4] CH0 RK1
5111 14:44:14.068539 [ModeRegInit_LP4] CH1 RK0
5112 14:44:14.071764 [ModeRegInit_LP4] CH1 RK1
5113 14:44:14.071845 match AC timing 9
5114 14:44:14.078574 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5115 14:44:14.081848 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5116 14:44:14.084989 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5117 14:44:14.091771 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5118 14:44:14.095091 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5119 14:44:14.095173 ==
5120 14:44:14.098380 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 14:44:14.101286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 14:44:14.101370 ==
5123 14:44:14.107918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 14:44:14.114811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5125 14:44:14.118228 [CA 0] Center 38 (8~69) winsize 62
5126 14:44:14.121370 [CA 1] Center 38 (8~69) winsize 62
5127 14:44:14.124972 [CA 2] Center 35 (5~65) winsize 61
5128 14:44:14.128296 [CA 3] Center 35 (5~65) winsize 61
5129 14:44:14.131558 [CA 4] Center 34 (4~65) winsize 62
5130 14:44:14.134681 [CA 5] Center 33 (3~64) winsize 62
5131 14:44:14.134764
5132 14:44:14.138113 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5133 14:44:14.138196
5134 14:44:14.141278 [CATrainingPosCal] consider 1 rank data
5135 14:44:14.144658 u2DelayCellTimex100 = 270/100 ps
5136 14:44:14.148204 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5137 14:44:14.151267 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5138 14:44:14.154454 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5139 14:44:14.157912 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5140 14:44:14.164455 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5141 14:44:14.167792 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5142 14:44:14.167876
5143 14:44:14.171261 CA PerBit enable=1, Macro0, CA PI delay=33
5144 14:44:14.171345
5145 14:44:14.174091 [CBTSetCACLKResult] CA Dly = 33
5146 14:44:14.174175 CS Dly: 7 (0~38)
5147 14:44:14.174243 ==
5148 14:44:14.177375 Dram Type= 6, Freq= 0, CH_0, rank 1
5149 14:44:14.184399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 14:44:14.184484 ==
5151 14:44:14.187826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5152 14:44:14.194075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5153 14:44:14.197254 [CA 0] Center 38 (8~69) winsize 62
5154 14:44:14.200761 [CA 1] Center 38 (8~69) winsize 62
5155 14:44:14.204293 [CA 2] Center 35 (5~66) winsize 62
5156 14:44:14.207234 [CA 3] Center 35 (5~66) winsize 62
5157 14:44:14.210668 [CA 4] Center 34 (3~65) winsize 63
5158 14:44:14.214197 [CA 5] Center 33 (3~64) winsize 62
5159 14:44:14.214278
5160 14:44:14.217318 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5161 14:44:14.217400
5162 14:44:14.220893 [CATrainingPosCal] consider 2 rank data
5163 14:44:14.224227 u2DelayCellTimex100 = 270/100 ps
5164 14:44:14.227519 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5165 14:44:14.231032 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5166 14:44:14.237590 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5167 14:44:14.240870 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5168 14:44:14.244125 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5169 14:44:14.247320 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5170 14:44:14.247402
5171 14:44:14.250611 CA PerBit enable=1, Macro0, CA PI delay=33
5172 14:44:14.250693
5173 14:44:14.253868 [CBTSetCACLKResult] CA Dly = 33
5174 14:44:14.253949 CS Dly: 7 (0~39)
5175 14:44:14.254015
5176 14:44:14.260546 ----->DramcWriteLeveling(PI) begin...
5177 14:44:14.260637 ==
5178 14:44:14.263610 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 14:44:14.266854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 14:44:14.266936 ==
5181 14:44:14.270504 Write leveling (Byte 0): 31 => 31
5182 14:44:14.273401 Write leveling (Byte 1): 30 => 30
5183 14:44:14.276750 DramcWriteLeveling(PI) end<-----
5184 14:44:14.276832
5185 14:44:14.276896 ==
5186 14:44:14.279978 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 14:44:14.283405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 14:44:14.283487 ==
5189 14:44:14.286813 [Gating] SW mode calibration
5190 14:44:14.293721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5191 14:44:14.299830 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5192 14:44:14.303277 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5193 14:44:14.306661 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5194 14:44:14.313190 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 14:44:14.316531 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 14:44:14.319953 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 14:44:14.327063 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 14:44:14.329753 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 14:44:14.333565 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5200 14:44:14.339992 0 15 0 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (1 1)
5201 14:44:14.343379 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5202 14:44:14.346405 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 14:44:14.353409 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 14:44:14.356525 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 14:44:14.360042 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 14:44:14.363002 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 14:44:14.369565 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5208 14:44:14.373018 1 0 0 | B1->B0 | 2424 3a3a | 1 0 | (0 0) (0 0)
5209 14:44:14.376402 1 0 4 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
5210 14:44:14.382920 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 14:44:14.386296 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 14:44:14.389622 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 14:44:14.396458 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 14:44:14.399757 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 14:44:14.402671 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5216 14:44:14.409477 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5217 14:44:14.412690 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5218 14:44:14.416298 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 14:44:14.423066 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 14:44:14.425877 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 14:44:14.429115 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 14:44:14.435800 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 14:44:14.439090 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 14:44:14.442477 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 14:44:14.449311 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 14:44:14.452482 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 14:44:14.455874 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 14:44:14.462657 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 14:44:14.465821 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 14:44:14.469080 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 14:44:14.475794 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5232 14:44:14.479121 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5233 14:44:14.482243 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 14:44:14.485305 Total UI for P1: 0, mck2ui 16
5235 14:44:14.488525 best dqsien dly found for B0: ( 1, 2, 30)
5236 14:44:14.492168 Total UI for P1: 0, mck2ui 16
5237 14:44:14.495515 best dqsien dly found for B1: ( 1, 3, 2)
5238 14:44:14.498839 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5239 14:44:14.502248 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5240 14:44:14.502356
5241 14:44:14.508627 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5242 14:44:14.512005 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5243 14:44:14.512088 [Gating] SW calibration Done
5244 14:44:14.515480 ==
5245 14:44:14.518657 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 14:44:14.521751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 14:44:14.521833 ==
5248 14:44:14.521898 RX Vref Scan: 0
5249 14:44:14.521958
5250 14:44:14.525088 RX Vref 0 -> 0, step: 1
5251 14:44:14.525170
5252 14:44:14.528516 RX Delay -80 -> 252, step: 8
5253 14:44:14.532024 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5254 14:44:14.534898 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5255 14:44:14.538233 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5256 14:44:14.544812 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5257 14:44:14.548247 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5258 14:44:14.551687 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5259 14:44:14.555188 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5260 14:44:14.558481 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5261 14:44:14.561655 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5262 14:44:14.568404 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5263 14:44:14.571618 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5264 14:44:14.574934 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5265 14:44:14.578349 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5266 14:44:14.585212 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5267 14:44:14.587953 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5268 14:44:14.591618 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5269 14:44:14.591725 ==
5270 14:44:14.594594 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 14:44:14.598189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 14:44:14.598270 ==
5273 14:44:14.602033 DQS Delay:
5274 14:44:14.602115 DQS0 = 0, DQS1 = 0
5275 14:44:14.602179 DQM Delay:
5276 14:44:14.604858 DQM0 = 93, DQM1 = 83
5277 14:44:14.604939 DQ Delay:
5278 14:44:14.608031 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5279 14:44:14.611684 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =103
5280 14:44:14.614949 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5281 14:44:14.617845 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5282 14:44:14.617926
5283 14:44:14.617990
5284 14:44:14.618049 ==
5285 14:44:14.621268 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 14:44:14.628065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 14:44:14.628147 ==
5288 14:44:14.628212
5289 14:44:14.628271
5290 14:44:14.628328 TX Vref Scan disable
5291 14:44:14.631959 == TX Byte 0 ==
5292 14:44:14.635362 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5293 14:44:14.641715 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5294 14:44:14.641796 == TX Byte 1 ==
5295 14:44:14.644949 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5296 14:44:14.651730 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5297 14:44:14.651811 ==
5298 14:44:14.654695 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 14:44:14.658117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 14:44:14.658198 ==
5301 14:44:14.658263
5302 14:44:14.658322
5303 14:44:14.661480 TX Vref Scan disable
5304 14:44:14.661561 == TX Byte 0 ==
5305 14:44:14.668051 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5306 14:44:14.671423 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5307 14:44:14.671504 == TX Byte 1 ==
5308 14:44:14.677803 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5309 14:44:14.681443 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5310 14:44:14.681524
5311 14:44:14.681587 [DATLAT]
5312 14:44:14.684678 Freq=933, CH0 RK0
5313 14:44:14.684759
5314 14:44:14.684823 DATLAT Default: 0xd
5315 14:44:14.687899 0, 0xFFFF, sum = 0
5316 14:44:14.687982 1, 0xFFFF, sum = 0
5317 14:44:14.691117 2, 0xFFFF, sum = 0
5318 14:44:14.691200 3, 0xFFFF, sum = 0
5319 14:44:14.694972 4, 0xFFFF, sum = 0
5320 14:44:14.697771 5, 0xFFFF, sum = 0
5321 14:44:14.697853 6, 0xFFFF, sum = 0
5322 14:44:14.701508 7, 0xFFFF, sum = 0
5323 14:44:14.701590 8, 0xFFFF, sum = 0
5324 14:44:14.704442 9, 0xFFFF, sum = 0
5325 14:44:14.704552 10, 0x0, sum = 1
5326 14:44:14.708156 11, 0x0, sum = 2
5327 14:44:14.708238 12, 0x0, sum = 3
5328 14:44:14.708365 13, 0x0, sum = 4
5329 14:44:14.711503 best_step = 11
5330 14:44:14.711584
5331 14:44:14.711648 ==
5332 14:44:14.714377 Dram Type= 6, Freq= 0, CH_0, rank 0
5333 14:44:14.717670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 14:44:14.717752 ==
5335 14:44:14.721446 RX Vref Scan: 1
5336 14:44:14.721527
5337 14:44:14.721592 RX Vref 0 -> 0, step: 1
5338 14:44:14.724394
5339 14:44:14.724475 RX Delay -69 -> 252, step: 4
5340 14:44:14.724555
5341 14:44:14.727709 Set Vref, RX VrefLevel [Byte0]: 62
5342 14:44:14.731044 [Byte1]: 46
5343 14:44:14.735664
5344 14:44:14.735746 Final RX Vref Byte 0 = 62 to rank0
5345 14:44:14.739150 Final RX Vref Byte 1 = 46 to rank0
5346 14:44:14.742529 Final RX Vref Byte 0 = 62 to rank1
5347 14:44:14.745540 Final RX Vref Byte 1 = 46 to rank1==
5348 14:44:14.748702 Dram Type= 6, Freq= 0, CH_0, rank 0
5349 14:44:14.755513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 14:44:14.755627 ==
5351 14:44:14.755725 DQS Delay:
5352 14:44:14.755883 DQS0 = 0, DQS1 = 0
5353 14:44:14.758726 DQM Delay:
5354 14:44:14.758848 DQM0 = 95, DQM1 = 82
5355 14:44:14.762190 DQ Delay:
5356 14:44:14.765218 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5357 14:44:14.768683 DQ4 =94, DQ5 =84, DQ6 =102, DQ7 =108
5358 14:44:14.772228 DQ8 =74, DQ9 =68, DQ10 =84, DQ11 =76
5359 14:44:14.775109 DQ12 =86, DQ13 =88, DQ14 =92, DQ15 =88
5360 14:44:14.775243
5361 14:44:14.775374
5362 14:44:14.781847 [DQSOSCAuto] RK0, (LSB)MR18= 0x1110, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5363 14:44:14.785298 CH0 RK0: MR19=505, MR18=1110
5364 14:44:14.791760 CH0_RK0: MR19=0x505, MR18=0x1110, DQSOSC=416, MR23=63, INC=62, DEC=41
5365 14:44:14.791842
5366 14:44:14.795179 ----->DramcWriteLeveling(PI) begin...
5367 14:44:14.795280 ==
5368 14:44:14.798616 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 14:44:14.802133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 14:44:14.802247 ==
5371 14:44:14.805045 Write leveling (Byte 0): 33 => 33
5372 14:44:14.808759 Write leveling (Byte 1): 32 => 32
5373 14:44:14.811947 DramcWriteLeveling(PI) end<-----
5374 14:44:14.812055
5375 14:44:14.812147 ==
5376 14:44:14.815087 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 14:44:14.818558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 14:44:14.818669 ==
5379 14:44:14.822064 [Gating] SW mode calibration
5380 14:44:14.828657 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5381 14:44:14.835206 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5382 14:44:14.838318 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5383 14:44:14.845096 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 14:44:14.848517 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 14:44:14.851843 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 14:44:14.858237 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 14:44:14.861803 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 14:44:14.864809 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5389 14:44:14.871572 0 14 28 | B1->B0 | 3131 2626 | 1 0 | (1 0) (0 0)
5390 14:44:14.874902 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5391 14:44:14.878007 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 14:44:14.881403 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 14:44:14.888285 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 14:44:14.891774 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 14:44:14.895207 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 14:44:14.901514 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 14:44:14.904582 0 15 28 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
5398 14:44:14.907930 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5399 14:44:14.914934 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 14:44:14.918178 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 14:44:14.921498 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 14:44:14.928075 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 14:44:14.931351 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 14:44:14.934579 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5405 14:44:14.940905 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5406 14:44:14.944316 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5407 14:44:14.947523 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 14:44:14.954290 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 14:44:14.957536 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 14:44:14.960883 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 14:44:14.967434 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 14:44:14.970750 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 14:44:14.974350 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 14:44:14.980699 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 14:44:14.983996 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 14:44:14.987455 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 14:44:14.993665 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 14:44:14.997007 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 14:44:15.000575 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 14:44:15.007012 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 14:44:15.010421 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5422 14:44:15.013800 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 14:44:15.017313 Total UI for P1: 0, mck2ui 16
5424 14:44:15.020493 best dqsien dly found for B0: ( 1, 2, 28)
5425 14:44:15.023303 Total UI for P1: 0, mck2ui 16
5426 14:44:15.027130 best dqsien dly found for B1: ( 1, 2, 30)
5427 14:44:15.030122 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5428 14:44:15.033661 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5429 14:44:15.033747
5430 14:44:15.040222 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5431 14:44:15.043439 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5432 14:44:15.046432 [Gating] SW calibration Done
5433 14:44:15.046552 ==
5434 14:44:15.050046 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 14:44:15.053304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 14:44:15.053410 ==
5437 14:44:15.053503 RX Vref Scan: 0
5438 14:44:15.056794
5439 14:44:15.056866 RX Vref 0 -> 0, step: 1
5440 14:44:15.056927
5441 14:44:15.060258 RX Delay -80 -> 252, step: 8
5442 14:44:15.063041 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5443 14:44:15.066294 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5444 14:44:15.073140 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5445 14:44:15.076456 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5446 14:44:15.079785 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5447 14:44:15.082827 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5448 14:44:15.086389 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5449 14:44:15.089443 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5450 14:44:15.096324 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5451 14:44:15.099733 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5452 14:44:15.102834 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5453 14:44:15.106283 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5454 14:44:15.112690 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5455 14:44:15.116177 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5456 14:44:15.119155 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5457 14:44:15.122432 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5458 14:44:15.122539 ==
5459 14:44:15.126077 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 14:44:15.129329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 14:44:15.132188 ==
5462 14:44:15.132270 DQS Delay:
5463 14:44:15.132336 DQS0 = 0, DQS1 = 0
5464 14:44:15.135717 DQM Delay:
5465 14:44:15.135802 DQM0 = 93, DQM1 = 82
5466 14:44:15.139046 DQ Delay:
5467 14:44:15.139155 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5468 14:44:15.142713 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =107
5469 14:44:15.145561 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =75
5470 14:44:15.152251 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =87
5471 14:44:15.152360
5472 14:44:15.152453
5473 14:44:15.152542 ==
5474 14:44:15.155625 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 14:44:15.158951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 14:44:15.159026 ==
5477 14:44:15.159087
5478 14:44:15.159145
5479 14:44:15.162190 TX Vref Scan disable
5480 14:44:15.162277 == TX Byte 0 ==
5481 14:44:15.169126 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5482 14:44:15.171960 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5483 14:44:15.172042 == TX Byte 1 ==
5484 14:44:15.178892 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5485 14:44:15.181785 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5486 14:44:15.181893 ==
5487 14:44:15.185208 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 14:44:15.188800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 14:44:15.188886 ==
5490 14:44:15.188951
5491 14:44:15.189022
5492 14:44:15.191773 TX Vref Scan disable
5493 14:44:15.195256 == TX Byte 0 ==
5494 14:44:15.198405 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5495 14:44:15.201875 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5496 14:44:15.205417 == TX Byte 1 ==
5497 14:44:15.208298 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5498 14:44:15.211498 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5499 14:44:15.214965
5500 14:44:15.215048 [DATLAT]
5501 14:44:15.215120 Freq=933, CH0 RK1
5502 14:44:15.215184
5503 14:44:15.218344 DATLAT Default: 0xb
5504 14:44:15.218429 0, 0xFFFF, sum = 0
5505 14:44:15.221762 1, 0xFFFF, sum = 0
5506 14:44:15.221847 2, 0xFFFF, sum = 0
5507 14:44:15.224769 3, 0xFFFF, sum = 0
5508 14:44:15.224854 4, 0xFFFF, sum = 0
5509 14:44:15.228177 5, 0xFFFF, sum = 0
5510 14:44:15.231340 6, 0xFFFF, sum = 0
5511 14:44:15.231423 7, 0xFFFF, sum = 0
5512 14:44:15.234545 8, 0xFFFF, sum = 0
5513 14:44:15.234630 9, 0xFFFF, sum = 0
5514 14:44:15.238681 10, 0x0, sum = 1
5515 14:44:15.238766 11, 0x0, sum = 2
5516 14:44:15.241389 12, 0x0, sum = 3
5517 14:44:15.241473 13, 0x0, sum = 4
5518 14:44:15.241541 best_step = 11
5519 14:44:15.241601
5520 14:44:15.244797 ==
5521 14:44:15.248191 Dram Type= 6, Freq= 0, CH_0, rank 1
5522 14:44:15.251450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 14:44:15.251534 ==
5524 14:44:15.251600 RX Vref Scan: 0
5525 14:44:15.251661
5526 14:44:15.255008 RX Vref 0 -> 0, step: 1
5527 14:44:15.255090
5528 14:44:15.257718 RX Delay -77 -> 252, step: 4
5529 14:44:15.264436 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5530 14:44:15.268004 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5531 14:44:15.271307 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5532 14:44:15.274530 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5533 14:44:15.277927 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5534 14:44:15.281669 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5535 14:44:15.284791 iDelay=199, Bit 6, Center 102 (7 ~ 198) 192
5536 14:44:15.291058 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5537 14:44:15.294294 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5538 14:44:15.297595 iDelay=199, Bit 9, Center 68 (-17 ~ 154) 172
5539 14:44:15.301151 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5540 14:44:15.304681 iDelay=199, Bit 11, Center 74 (-13 ~ 162) 176
5541 14:44:15.310820 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5542 14:44:15.314017 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5543 14:44:15.317794 iDelay=199, Bit 14, Center 92 (3 ~ 182) 180
5544 14:44:15.320738 iDelay=199, Bit 15, Center 90 (3 ~ 178) 176
5545 14:44:15.320845 ==
5546 14:44:15.324148 Dram Type= 6, Freq= 0, CH_0, rank 1
5547 14:44:15.330752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 14:44:15.330864 ==
5549 14:44:15.330957 DQS Delay:
5550 14:44:15.333757 DQS0 = 0, DQS1 = 0
5551 14:44:15.333870 DQM Delay:
5552 14:44:15.333979 DQM0 = 92, DQM1 = 83
5553 14:44:15.337074 DQ Delay:
5554 14:44:15.340727 DQ0 =92, DQ1 =94, DQ2 =90, DQ3 =88
5555 14:44:15.343736 DQ4 =92, DQ5 =82, DQ6 =102, DQ7 =102
5556 14:44:15.346970 DQ8 =74, DQ9 =68, DQ10 =86, DQ11 =74
5557 14:44:15.350218 DQ12 =90, DQ13 =90, DQ14 =92, DQ15 =90
5558 14:44:15.350298
5559 14:44:15.350361
5560 14:44:15.356913 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5561 14:44:15.360499 CH0 RK1: MR19=505, MR18=2C0F
5562 14:44:15.367318 CH0_RK1: MR19=0x505, MR18=0x2C0F, DQSOSC=408, MR23=63, INC=65, DEC=43
5563 14:44:15.370624 [RxdqsGatingPostProcess] freq 933
5564 14:44:15.373650 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5565 14:44:15.376796 best DQS0 dly(2T, 0.5T) = (0, 10)
5566 14:44:15.380094 best DQS1 dly(2T, 0.5T) = (0, 11)
5567 14:44:15.383422 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5568 14:44:15.387070 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5569 14:44:15.390616 best DQS0 dly(2T, 0.5T) = (0, 10)
5570 14:44:15.393313 best DQS1 dly(2T, 0.5T) = (0, 10)
5571 14:44:15.396848 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5572 14:44:15.400221 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5573 14:44:15.403262 Pre-setting of DQS Precalculation
5574 14:44:15.407083 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5575 14:44:15.410033 ==
5576 14:44:15.413455 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 14:44:15.416923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 14:44:15.417035 ==
5579 14:44:15.419761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5580 14:44:15.426622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5581 14:44:15.430508 [CA 0] Center 37 (7~67) winsize 61
5582 14:44:15.433856 [CA 1] Center 37 (7~68) winsize 62
5583 14:44:15.437145 [CA 2] Center 34 (5~64) winsize 60
5584 14:44:15.440342 [CA 3] Center 34 (5~64) winsize 60
5585 14:44:15.443247 [CA 4] Center 34 (5~64) winsize 60
5586 14:44:15.446615 [CA 5] Center 34 (4~64) winsize 61
5587 14:44:15.446699
5588 14:44:15.449825 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5589 14:44:15.449908
5590 14:44:15.453110 [CATrainingPosCal] consider 1 rank data
5591 14:44:15.456564 u2DelayCellTimex100 = 270/100 ps
5592 14:44:15.459887 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5593 14:44:15.466388 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5594 14:44:15.469883 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5595 14:44:15.473213 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5596 14:44:15.476423 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5597 14:44:15.479755 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5598 14:44:15.479849
5599 14:44:15.483202 CA PerBit enable=1, Macro0, CA PI delay=34
5600 14:44:15.483309
5601 14:44:15.486282 [CBTSetCACLKResult] CA Dly = 34
5602 14:44:15.486367 CS Dly: 6 (0~37)
5603 14:44:15.489720 ==
5604 14:44:15.493265 Dram Type= 6, Freq= 0, CH_1, rank 1
5605 14:44:15.496505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 14:44:15.496600 ==
5607 14:44:15.502738 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5608 14:44:15.506141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5609 14:44:15.510102 [CA 0] Center 38 (8~68) winsize 61
5610 14:44:15.513437 [CA 1] Center 37 (7~68) winsize 62
5611 14:44:15.517150 [CA 2] Center 35 (6~65) winsize 60
5612 14:44:15.520114 [CA 3] Center 34 (4~65) winsize 62
5613 14:44:15.523582 [CA 4] Center 35 (5~65) winsize 61
5614 14:44:15.526767 [CA 5] Center 34 (4~64) winsize 61
5615 14:44:15.526845
5616 14:44:15.530133 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5617 14:44:15.530261
5618 14:44:15.533006 [CATrainingPosCal] consider 2 rank data
5619 14:44:15.536603 u2DelayCellTimex100 = 270/100 ps
5620 14:44:15.540073 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5621 14:44:15.546272 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5622 14:44:15.549804 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5623 14:44:15.552931 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5624 14:44:15.556434 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5625 14:44:15.559531 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5626 14:44:15.559637
5627 14:44:15.563066 CA PerBit enable=1, Macro0, CA PI delay=34
5628 14:44:15.563158
5629 14:44:15.566218 [CBTSetCACLKResult] CA Dly = 34
5630 14:44:15.569731 CS Dly: 7 (0~39)
5631 14:44:15.569815
5632 14:44:15.573177 ----->DramcWriteLeveling(PI) begin...
5633 14:44:15.573257 ==
5634 14:44:15.576425 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 14:44:15.579354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 14:44:15.579434 ==
5637 14:44:15.582951 Write leveling (Byte 0): 26 => 26
5638 14:44:15.586239 Write leveling (Byte 1): 28 => 28
5639 14:44:15.589701 DramcWriteLeveling(PI) end<-----
5640 14:44:15.589812
5641 14:44:15.589905 ==
5642 14:44:15.593389 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 14:44:15.596294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 14:44:15.596380 ==
5645 14:44:15.599479 [Gating] SW mode calibration
5646 14:44:15.606617 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5647 14:44:15.613102 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5648 14:44:15.616207 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 14:44:15.619807 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 14:44:15.626338 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 14:44:15.629324 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 14:44:15.632818 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 14:44:15.639754 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5654 14:44:15.642803 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5655 14:44:15.646257 0 14 28 | B1->B0 | 3131 3030 | 1 1 | (1 0) (1 0)
5656 14:44:15.652526 0 15 0 | B1->B0 | 2727 2424 | 0 0 | (1 1) (0 0)
5657 14:44:15.655924 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 14:44:15.659235 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 14:44:15.666022 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 14:44:15.669378 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 14:44:15.672500 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 14:44:15.679316 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 14:44:15.682153 0 15 28 | B1->B0 | 3939 3838 | 1 1 | (0 0) (0 0)
5664 14:44:15.686092 1 0 0 | B1->B0 | 4545 4545 | 1 0 | (0 0) (0 0)
5665 14:44:15.692323 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 14:44:15.695644 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 14:44:15.699236 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 14:44:15.702422 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 14:44:15.708892 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 14:44:15.712719 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 14:44:15.715375 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 14:44:15.722053 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 14:44:15.725318 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 14:44:15.728984 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 14:44:15.735506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 14:44:15.739070 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 14:44:15.742119 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 14:44:15.748588 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 14:44:15.752170 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 14:44:15.755136 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 14:44:15.762064 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 14:44:15.765341 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 14:44:15.768603 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 14:44:15.775179 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 14:44:15.778556 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 14:44:15.781979 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 14:44:15.788802 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5688 14:44:15.788912 Total UI for P1: 0, mck2ui 16
5689 14:44:15.795334 best dqsien dly found for B0: ( 1, 2, 26)
5690 14:44:15.798568 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5691 14:44:15.801869 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 14:44:15.804931 Total UI for P1: 0, mck2ui 16
5693 14:44:15.808523 best dqsien dly found for B1: ( 1, 2, 30)
5694 14:44:15.811823 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5695 14:44:15.815304 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5696 14:44:15.815430
5697 14:44:15.821567 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5698 14:44:15.825087 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5699 14:44:15.825212 [Gating] SW calibration Done
5700 14:44:15.828212 ==
5701 14:44:15.831928 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 14:44:15.834886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 14:44:15.835013 ==
5704 14:44:15.835127 RX Vref Scan: 0
5705 14:44:15.835237
5706 14:44:15.838312 RX Vref 0 -> 0, step: 1
5707 14:44:15.838435
5708 14:44:15.841684 RX Delay -80 -> 252, step: 8
5709 14:44:15.845039 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5710 14:44:15.848212 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5711 14:44:15.851807 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5712 14:44:15.858106 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5713 14:44:15.861405 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5714 14:44:15.864827 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5715 14:44:15.868446 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5716 14:44:15.871222 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5717 14:44:15.877985 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5718 14:44:15.881267 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5719 14:44:15.884578 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5720 14:44:15.888047 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5721 14:44:15.890924 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5722 14:44:15.897686 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5723 14:44:15.901210 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5724 14:44:15.904623 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5725 14:44:15.904744 ==
5726 14:44:15.908276 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 14:44:15.911150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 14:44:15.911274 ==
5729 14:44:15.914687 DQS Delay:
5730 14:44:15.914808 DQS0 = 0, DQS1 = 0
5731 14:44:15.914921 DQM Delay:
5732 14:44:15.917637 DQM0 = 95, DQM1 = 86
5733 14:44:15.917757 DQ Delay:
5734 14:44:15.921261 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5735 14:44:15.924258 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5736 14:44:15.928189 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5737 14:44:15.931035 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5738 14:44:15.931158
5739 14:44:15.931270
5740 14:44:15.931378 ==
5741 14:44:15.934529 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 14:44:15.940868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 14:44:15.941000 ==
5744 14:44:15.941115
5745 14:44:15.941225
5746 14:44:15.941336 TX Vref Scan disable
5747 14:44:15.944967 == TX Byte 0 ==
5748 14:44:15.947929 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5749 14:44:15.954609 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5750 14:44:15.954693 == TX Byte 1 ==
5751 14:44:15.957830 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5752 14:44:15.964751 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5753 14:44:15.964864 ==
5754 14:44:15.968237 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 14:44:15.971258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 14:44:15.971388 ==
5757 14:44:15.971503
5758 14:44:15.971616
5759 14:44:15.974649 TX Vref Scan disable
5760 14:44:15.974771 == TX Byte 0 ==
5761 14:44:15.981221 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5762 14:44:15.984710 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5763 14:44:15.984833 == TX Byte 1 ==
5764 14:44:15.991223 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5765 14:44:15.994011 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5766 14:44:15.994089
5767 14:44:15.994154 [DATLAT]
5768 14:44:15.997519 Freq=933, CH1 RK0
5769 14:44:15.997615
5770 14:44:15.997704 DATLAT Default: 0xd
5771 14:44:16.001486 0, 0xFFFF, sum = 0
5772 14:44:16.001618 1, 0xFFFF, sum = 0
5773 14:44:16.004226 2, 0xFFFF, sum = 0
5774 14:44:16.007847 3, 0xFFFF, sum = 0
5775 14:44:16.007974 4, 0xFFFF, sum = 0
5776 14:44:16.011222 5, 0xFFFF, sum = 0
5777 14:44:16.011346 6, 0xFFFF, sum = 0
5778 14:44:16.014526 7, 0xFFFF, sum = 0
5779 14:44:16.014651 8, 0xFFFF, sum = 0
5780 14:44:16.017297 9, 0xFFFF, sum = 0
5781 14:44:16.017422 10, 0x0, sum = 1
5782 14:44:16.020802 11, 0x0, sum = 2
5783 14:44:16.020926 12, 0x0, sum = 3
5784 14:44:16.024445 13, 0x0, sum = 4
5785 14:44:16.024573 best_step = 11
5786 14:44:16.024685
5787 14:44:16.024796 ==
5788 14:44:16.027370 Dram Type= 6, Freq= 0, CH_1, rank 0
5789 14:44:16.030872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 14:44:16.030995 ==
5791 14:44:16.033992 RX Vref Scan: 1
5792 14:44:16.034102
5793 14:44:16.037417 RX Vref 0 -> 0, step: 1
5794 14:44:16.037500
5795 14:44:16.037565 RX Delay -69 -> 252, step: 4
5796 14:44:16.037626
5797 14:44:16.040698 Set Vref, RX VrefLevel [Byte0]: 59
5798 14:44:16.044135 [Byte1]: 48
5799 14:44:16.049072
5800 14:44:16.049153 Final RX Vref Byte 0 = 59 to rank0
5801 14:44:16.052248 Final RX Vref Byte 1 = 48 to rank0
5802 14:44:16.055167 Final RX Vref Byte 0 = 59 to rank1
5803 14:44:16.058478 Final RX Vref Byte 1 = 48 to rank1==
5804 14:44:16.061839 Dram Type= 6, Freq= 0, CH_1, rank 0
5805 14:44:16.068676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 14:44:16.068805 ==
5807 14:44:16.068919 DQS Delay:
5808 14:44:16.069034 DQS0 = 0, DQS1 = 0
5809 14:44:16.072193 DQM Delay:
5810 14:44:16.072284 DQM0 = 96, DQM1 = 88
5811 14:44:16.075207 DQ Delay:
5812 14:44:16.078648 DQ0 =102, DQ1 =90, DQ2 =86, DQ3 =92
5813 14:44:16.082307 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5814 14:44:16.085481 DQ8 =74, DQ9 =80, DQ10 =88, DQ11 =80
5815 14:44:16.088835 DQ12 =98, DQ13 =92, DQ14 =98, DQ15 =96
5816 14:44:16.088918
5817 14:44:16.088983
5818 14:44:16.095066 [DQSOSCAuto] RK0, (LSB)MR18= 0x109, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 421 ps
5819 14:44:16.098416 CH1 RK0: MR19=505, MR18=109
5820 14:44:16.105184 CH1_RK0: MR19=0x505, MR18=0x109, DQSOSC=419, MR23=63, INC=61, DEC=41
5821 14:44:16.105269
5822 14:44:16.108533 ----->DramcWriteLeveling(PI) begin...
5823 14:44:16.108626 ==
5824 14:44:16.111513 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 14:44:16.114913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 14:44:16.114997 ==
5827 14:44:16.118403 Write leveling (Byte 0): 26 => 26
5828 14:44:16.121943 Write leveling (Byte 1): 28 => 28
5829 14:44:16.125267 DramcWriteLeveling(PI) end<-----
5830 14:44:16.125348
5831 14:44:16.125412 ==
5832 14:44:16.128662 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 14:44:16.131810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 14:44:16.131893 ==
5835 14:44:16.134819 [Gating] SW mode calibration
5836 14:44:16.141694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5837 14:44:16.147907 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5838 14:44:16.151558 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5839 14:44:16.158118 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 14:44:16.161248 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5841 14:44:16.164566 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5842 14:44:16.171517 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5843 14:44:16.174359 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5844 14:44:16.178015 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5845 14:44:16.184745 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5846 14:44:16.188042 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5847 14:44:16.190962 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 14:44:16.197456 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 14:44:16.200765 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 14:44:16.204104 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 14:44:16.210796 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 14:44:16.214129 0 15 24 | B1->B0 | 2424 2e2e | 1 0 | (0 0) (0 0)
5853 14:44:16.217461 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5854 14:44:16.223854 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 14:44:16.227386 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 14:44:16.230770 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 14:44:16.234044 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 14:44:16.240801 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 14:44:16.244071 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5860 14:44:16.247351 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5861 14:44:16.253879 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5862 14:44:16.257528 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5863 14:44:16.260761 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 14:44:16.267488 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 14:44:16.270736 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 14:44:16.273700 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 14:44:16.280646 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 14:44:16.283912 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 14:44:16.287203 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 14:44:16.293596 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 14:44:16.297091 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 14:44:16.300680 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 14:44:16.306868 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 14:44:16.310258 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 14:44:16.313707 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5876 14:44:16.319941 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5877 14:44:16.323313 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5878 14:44:16.326849 Total UI for P1: 0, mck2ui 16
5879 14:44:16.330239 best dqsien dly found for B0: ( 1, 2, 22)
5880 14:44:16.333761 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 14:44:16.336482 Total UI for P1: 0, mck2ui 16
5882 14:44:16.339637 best dqsien dly found for B1: ( 1, 2, 28)
5883 14:44:16.343343 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5884 14:44:16.346498 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5885 14:44:16.346582
5886 14:44:16.353299 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5887 14:44:16.356309 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5888 14:44:16.359553 [Gating] SW calibration Done
5889 14:44:16.359635 ==
5890 14:44:16.362927 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 14:44:16.366457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 14:44:16.366540 ==
5893 14:44:16.366606 RX Vref Scan: 0
5894 14:44:16.366667
5895 14:44:16.369718 RX Vref 0 -> 0, step: 1
5896 14:44:16.369800
5897 14:44:16.373030 RX Delay -80 -> 252, step: 8
5898 14:44:16.376255 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5899 14:44:16.379470 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5900 14:44:16.386130 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5901 14:44:16.389262 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5902 14:44:16.392773 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5903 14:44:16.395970 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5904 14:44:16.399638 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5905 14:44:16.402642 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5906 14:44:16.409833 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5907 14:44:16.412705 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5908 14:44:16.416357 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5909 14:44:16.419296 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5910 14:44:16.422787 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5911 14:44:16.429440 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5912 14:44:16.432346 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5913 14:44:16.435712 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5914 14:44:16.435835 ==
5915 14:44:16.439242 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 14:44:16.442711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 14:44:16.442793 ==
5918 14:44:16.445829 DQS Delay:
5919 14:44:16.445910 DQS0 = 0, DQS1 = 0
5920 14:44:16.445974 DQM Delay:
5921 14:44:16.449126 DQM0 = 93, DQM1 = 88
5922 14:44:16.449207 DQ Delay:
5923 14:44:16.452418 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5924 14:44:16.455717 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5925 14:44:16.459025 DQ8 =75, DQ9 =75, DQ10 =95, DQ11 =79
5926 14:44:16.462399 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5927 14:44:16.462480
5928 14:44:16.462544
5929 14:44:16.462602 ==
5930 14:44:16.465504 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 14:44:16.472149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 14:44:16.472231 ==
5933 14:44:16.472295
5934 14:44:16.472355
5935 14:44:16.475469 TX Vref Scan disable
5936 14:44:16.475550 == TX Byte 0 ==
5937 14:44:16.478834 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5938 14:44:16.485711 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5939 14:44:16.485792 == TX Byte 1 ==
5940 14:44:16.491785 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5941 14:44:16.494940 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5942 14:44:16.495021 ==
5943 14:44:16.498437 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 14:44:16.501659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 14:44:16.501739 ==
5946 14:44:16.501803
5947 14:44:16.501862
5948 14:44:16.504823 TX Vref Scan disable
5949 14:44:16.507806 == TX Byte 0 ==
5950 14:44:16.511389 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5951 14:44:16.514564 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5952 14:44:16.517936 == TX Byte 1 ==
5953 14:44:16.521332 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5954 14:44:16.524995 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5955 14:44:16.525118
5956 14:44:16.527935 [DATLAT]
5957 14:44:16.528056 Freq=933, CH1 RK1
5958 14:44:16.528167
5959 14:44:16.530978 DATLAT Default: 0xb
5960 14:44:16.531097 0, 0xFFFF, sum = 0
5961 14:44:16.534566 1, 0xFFFF, sum = 0
5962 14:44:16.534689 2, 0xFFFF, sum = 0
5963 14:44:16.537910 3, 0xFFFF, sum = 0
5964 14:44:16.538035 4, 0xFFFF, sum = 0
5965 14:44:16.541163 5, 0xFFFF, sum = 0
5966 14:44:16.541285 6, 0xFFFF, sum = 0
5967 14:44:16.544096 7, 0xFFFF, sum = 0
5968 14:44:16.544219 8, 0xFFFF, sum = 0
5969 14:44:16.548081 9, 0xFFFF, sum = 0
5970 14:44:16.548203 10, 0x0, sum = 1
5971 14:44:16.550865 11, 0x0, sum = 2
5972 14:44:16.550986 12, 0x0, sum = 3
5973 14:44:16.554340 13, 0x0, sum = 4
5974 14:44:16.554444 best_step = 11
5975 14:44:16.554535
5976 14:44:16.554622 ==
5977 14:44:16.557674 Dram Type= 6, Freq= 0, CH_1, rank 1
5978 14:44:16.563966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5979 14:44:16.564048 ==
5980 14:44:16.564111 RX Vref Scan: 0
5981 14:44:16.564171
5982 14:44:16.567332 RX Vref 0 -> 0, step: 1
5983 14:44:16.567413
5984 14:44:16.570544 RX Delay -69 -> 252, step: 4
5985 14:44:16.574190 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5986 14:44:16.580800 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5987 14:44:16.584190 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5988 14:44:16.587507 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5989 14:44:16.590585 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5990 14:44:16.594406 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5991 14:44:16.597116 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5992 14:44:16.603878 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5993 14:44:16.607598 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5994 14:44:16.610413 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5995 14:44:16.614047 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5996 14:44:16.617259 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5997 14:44:16.624014 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5998 14:44:16.627168 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5999 14:44:16.630504 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
6000 14:44:16.634076 iDelay=203, Bit 15, Center 100 (11 ~ 190) 180
6001 14:44:16.634168 ==
6002 14:44:16.636764 Dram Type= 6, Freq= 0, CH_1, rank 1
6003 14:44:16.643513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6004 14:44:16.643653 ==
6005 14:44:16.643767 DQS Delay:
6006 14:44:16.646911 DQS0 = 0, DQS1 = 0
6007 14:44:16.647031 DQM Delay:
6008 14:44:16.647143 DQM0 = 92, DQM1 = 91
6009 14:44:16.650276 DQ Delay:
6010 14:44:16.653668 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
6011 14:44:16.656989 DQ4 =88, DQ5 =102, DQ6 =106, DQ7 =88
6012 14:44:16.660315 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =84
6013 14:44:16.663773 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
6014 14:44:16.663854
6015 14:44:16.663919
6016 14:44:16.670111 [DQSOSCAuto] RK1, (LSB)MR18= 0x1023, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
6017 14:44:16.673376 CH1 RK1: MR19=505, MR18=1023
6018 14:44:16.680004 CH1_RK1: MR19=0x505, MR18=0x1023, DQSOSC=410, MR23=63, INC=64, DEC=42
6019 14:44:16.683464 [RxdqsGatingPostProcess] freq 933
6020 14:44:16.686868 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6021 14:44:16.690314 best DQS0 dly(2T, 0.5T) = (0, 10)
6022 14:44:16.693591 best DQS1 dly(2T, 0.5T) = (0, 10)
6023 14:44:16.696547 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6024 14:44:16.700177 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6025 14:44:16.703288 best DQS0 dly(2T, 0.5T) = (0, 10)
6026 14:44:16.706684 best DQS1 dly(2T, 0.5T) = (0, 10)
6027 14:44:16.709920 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6028 14:44:16.713574 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6029 14:44:16.716824 Pre-setting of DQS Precalculation
6030 14:44:16.719857 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6031 14:44:16.729755 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6032 14:44:16.736404 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6033 14:44:16.736532
6034 14:44:16.736666
6035 14:44:16.739587 [Calibration Summary] 1866 Mbps
6036 14:44:16.739707 CH 0, Rank 0
6037 14:44:16.743136 SW Impedance : PASS
6038 14:44:16.743255 DUTY Scan : NO K
6039 14:44:16.746515 ZQ Calibration : PASS
6040 14:44:16.749494 Jitter Meter : NO K
6041 14:44:16.749614 CBT Training : PASS
6042 14:44:16.753150 Write leveling : PASS
6043 14:44:16.756447 RX DQS gating : PASS
6044 14:44:16.756583 RX DQ/DQS(RDDQC) : PASS
6045 14:44:16.759500 TX DQ/DQS : PASS
6046 14:44:16.762871 RX DATLAT : PASS
6047 14:44:16.762991 RX DQ/DQS(Engine): PASS
6048 14:44:16.766122 TX OE : NO K
6049 14:44:16.766243 All Pass.
6050 14:44:16.766353
6051 14:44:16.769761 CH 0, Rank 1
6052 14:44:16.769893 SW Impedance : PASS
6053 14:44:16.772983 DUTY Scan : NO K
6054 14:44:16.776374 ZQ Calibration : PASS
6055 14:44:16.776507 Jitter Meter : NO K
6056 14:44:16.779784 CBT Training : PASS
6057 14:44:16.782631 Write leveling : PASS
6058 14:44:16.782748 RX DQS gating : PASS
6059 14:44:16.786001 RX DQ/DQS(RDDQC) : PASS
6060 14:44:16.789496 TX DQ/DQS : PASS
6061 14:44:16.789617 RX DATLAT : PASS
6062 14:44:16.792713 RX DQ/DQS(Engine): PASS
6063 14:44:16.796110 TX OE : NO K
6064 14:44:16.796229 All Pass.
6065 14:44:16.796337
6066 14:44:16.796448 CH 1, Rank 0
6067 14:44:16.799375 SW Impedance : PASS
6068 14:44:16.802863 DUTY Scan : NO K
6069 14:44:16.802979 ZQ Calibration : PASS
6070 14:44:16.805799 Jitter Meter : NO K
6071 14:44:16.805920 CBT Training : PASS
6072 14:44:16.809187 Write leveling : PASS
6073 14:44:16.812413 RX DQS gating : PASS
6074 14:44:16.812531 RX DQ/DQS(RDDQC) : PASS
6075 14:44:16.815981 TX DQ/DQS : PASS
6076 14:44:16.818960 RX DATLAT : PASS
6077 14:44:16.819082 RX DQ/DQS(Engine): PASS
6078 14:44:16.822441 TX OE : NO K
6079 14:44:16.822561 All Pass.
6080 14:44:16.822671
6081 14:44:16.825589 CH 1, Rank 1
6082 14:44:16.825707 SW Impedance : PASS
6083 14:44:16.828820 DUTY Scan : NO K
6084 14:44:16.832290 ZQ Calibration : PASS
6085 14:44:16.832411 Jitter Meter : NO K
6086 14:44:16.835651 CBT Training : PASS
6087 14:44:16.839236 Write leveling : PASS
6088 14:44:16.839358 RX DQS gating : PASS
6089 14:44:16.842482 RX DQ/DQS(RDDQC) : PASS
6090 14:44:16.845788 TX DQ/DQS : PASS
6091 14:44:16.845906 RX DATLAT : PASS
6092 14:44:16.848660 RX DQ/DQS(Engine): PASS
6093 14:44:16.852160 TX OE : NO K
6094 14:44:16.852280 All Pass.
6095 14:44:16.852390
6096 14:44:16.852499 DramC Write-DBI off
6097 14:44:16.855499 PER_BANK_REFRESH: Hybrid Mode
6098 14:44:16.858954 TX_TRACKING: ON
6099 14:44:16.865592 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6100 14:44:16.868742 [FAST_K] Save calibration result to emmc
6101 14:44:16.875350 dramc_set_vcore_voltage set vcore to 650000
6102 14:44:16.875471 Read voltage for 400, 6
6103 14:44:16.878758 Vio18 = 0
6104 14:44:16.878893 Vcore = 650000
6105 14:44:16.879007 Vdram = 0
6106 14:44:16.882118 Vddq = 0
6107 14:44:16.882237 Vmddr = 0
6108 14:44:16.885424 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6109 14:44:16.891795 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6110 14:44:16.895144 MEM_TYPE=3, freq_sel=20
6111 14:44:16.898644 sv_algorithm_assistance_LP4_800
6112 14:44:16.902078 ============ PULL DRAM RESETB DOWN ============
6113 14:44:16.905366 ========== PULL DRAM RESETB DOWN end =========
6114 14:44:16.908763 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6115 14:44:16.911544 ===================================
6116 14:44:16.915103 LPDDR4 DRAM CONFIGURATION
6117 14:44:16.918552 ===================================
6118 14:44:16.921913 EX_ROW_EN[0] = 0x0
6119 14:44:16.922033 EX_ROW_EN[1] = 0x0
6120 14:44:16.925236 LP4Y_EN = 0x0
6121 14:44:16.925338 WORK_FSP = 0x0
6122 14:44:16.928759 WL = 0x2
6123 14:44:16.928855 RL = 0x2
6124 14:44:16.931769 BL = 0x2
6125 14:44:16.931877 RPST = 0x0
6126 14:44:16.935133 RD_PRE = 0x0
6127 14:44:16.935213 WR_PRE = 0x1
6128 14:44:16.938416 WR_PST = 0x0
6129 14:44:16.938496 DBI_WR = 0x0
6130 14:44:16.941633 DBI_RD = 0x0
6131 14:44:16.945075 OTF = 0x1
6132 14:44:16.948311 ===================================
6133 14:44:16.948391 ===================================
6134 14:44:16.951983 ANA top config
6135 14:44:16.954825 ===================================
6136 14:44:16.958454 DLL_ASYNC_EN = 0
6137 14:44:16.958534 ALL_SLAVE_EN = 1
6138 14:44:16.961600 NEW_RANK_MODE = 1
6139 14:44:16.965258 DLL_IDLE_MODE = 1
6140 14:44:16.968452 LP45_APHY_COMB_EN = 1
6141 14:44:16.971355 TX_ODT_DIS = 1
6142 14:44:16.971475 NEW_8X_MODE = 1
6143 14:44:16.974620 ===================================
6144 14:44:16.977932 ===================================
6145 14:44:16.981238 data_rate = 800
6146 14:44:16.984994 CKR = 1
6147 14:44:16.987972 DQ_P2S_RATIO = 4
6148 14:44:16.991309 ===================================
6149 14:44:16.994787 CA_P2S_RATIO = 4
6150 14:44:16.998100 DQ_CA_OPEN = 0
6151 14:44:16.998180 DQ_SEMI_OPEN = 1
6152 14:44:17.001502 CA_SEMI_OPEN = 1
6153 14:44:17.004777 CA_FULL_RATE = 0
6154 14:44:17.007735 DQ_CKDIV4_EN = 0
6155 14:44:17.011192 CA_CKDIV4_EN = 1
6156 14:44:17.014772 CA_PREDIV_EN = 0
6157 14:44:17.014856 PH8_DLY = 0
6158 14:44:17.017677 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6159 14:44:17.020941 DQ_AAMCK_DIV = 0
6160 14:44:17.024383 CA_AAMCK_DIV = 0
6161 14:44:17.027856 CA_ADMCK_DIV = 4
6162 14:44:17.031387 DQ_TRACK_CA_EN = 0
6163 14:44:17.031468 CA_PICK = 800
6164 14:44:17.034434 CA_MCKIO = 400
6165 14:44:17.037560 MCKIO_SEMI = 400
6166 14:44:17.040920 PLL_FREQ = 3016
6167 14:44:17.044149 DQ_UI_PI_RATIO = 32
6168 14:44:17.047520 CA_UI_PI_RATIO = 32
6169 14:44:17.051215 ===================================
6170 14:44:17.054313 ===================================
6171 14:44:17.057481 memory_type:LPDDR4
6172 14:44:17.057562 GP_NUM : 10
6173 14:44:17.060804 SRAM_EN : 1
6174 14:44:17.060911 MD32_EN : 0
6175 14:44:17.064124 ===================================
6176 14:44:17.067549 [ANA_INIT] >>>>>>>>>>>>>>
6177 14:44:17.071179 <<<<<< [CONFIGURE PHASE]: ANA_TX
6178 14:44:17.073837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6179 14:44:17.077150 ===================================
6180 14:44:17.080561 data_rate = 800,PCW = 0X7400
6181 14:44:17.083983 ===================================
6182 14:44:17.087332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6183 14:44:17.094314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6184 14:44:17.104012 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6185 14:44:17.106972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6186 14:44:17.110321 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6187 14:44:17.113694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6188 14:44:17.116833 [ANA_INIT] flow start
6189 14:44:17.120389 [ANA_INIT] PLL >>>>>>>>
6190 14:44:17.120511 [ANA_INIT] PLL <<<<<<<<
6191 14:44:17.123836 [ANA_INIT] MIDPI >>>>>>>>
6192 14:44:17.127270 [ANA_INIT] MIDPI <<<<<<<<
6193 14:44:17.130136 [ANA_INIT] DLL >>>>>>>>
6194 14:44:17.130239 [ANA_INIT] flow end
6195 14:44:17.133575 ============ LP4 DIFF to SE enter ============
6196 14:44:17.140104 ============ LP4 DIFF to SE exit ============
6197 14:44:17.140188 [ANA_INIT] <<<<<<<<<<<<<
6198 14:44:17.143523 [Flow] Enable top DCM control >>>>>
6199 14:44:17.146911 [Flow] Enable top DCM control <<<<<
6200 14:44:17.150443 Enable DLL master slave shuffle
6201 14:44:17.156874 ==============================================================
6202 14:44:17.156956 Gating Mode config
6203 14:44:17.163488 ==============================================================
6204 14:44:17.166624 Config description:
6205 14:44:17.176517 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6206 14:44:17.183252 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6207 14:44:17.186613 SELPH_MODE 0: By rank 1: By Phase
6208 14:44:17.193085 ==============================================================
6209 14:44:17.196360 GAT_TRACK_EN = 0
6210 14:44:17.199995 RX_GATING_MODE = 2
6211 14:44:17.202858 RX_GATING_TRACK_MODE = 2
6212 14:44:17.202939 SELPH_MODE = 1
6213 14:44:17.206196 PICG_EARLY_EN = 1
6214 14:44:17.209781 VALID_LAT_VALUE = 1
6215 14:44:17.216227 ==============================================================
6216 14:44:17.219399 Enter into Gating configuration >>>>
6217 14:44:17.222981 Exit from Gating configuration <<<<
6218 14:44:17.226079 Enter into DVFS_PRE_config >>>>>
6219 14:44:17.235969 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6220 14:44:17.239322 Exit from DVFS_PRE_config <<<<<
6221 14:44:17.242727 Enter into PICG configuration >>>>
6222 14:44:17.246002 Exit from PICG configuration <<<<
6223 14:44:17.249050 [RX_INPUT] configuration >>>>>
6224 14:44:17.252711 [RX_INPUT] configuration <<<<<
6225 14:44:17.256129 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6226 14:44:17.262749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6227 14:44:17.269235 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6228 14:44:17.276177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6229 14:44:17.279146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6230 14:44:17.286134 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6231 14:44:17.292321 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6232 14:44:17.295827 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6233 14:44:17.299207 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6234 14:44:17.302631 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6235 14:44:17.305989 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6236 14:44:17.312332 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6237 14:44:17.315760 ===================================
6238 14:44:17.318948 LPDDR4 DRAM CONFIGURATION
6239 14:44:17.322227 ===================================
6240 14:44:17.322324 EX_ROW_EN[0] = 0x0
6241 14:44:17.325626 EX_ROW_EN[1] = 0x0
6242 14:44:17.325738 LP4Y_EN = 0x0
6243 14:44:17.328880 WORK_FSP = 0x0
6244 14:44:17.328962 WL = 0x2
6245 14:44:17.332458 RL = 0x2
6246 14:44:17.332603 BL = 0x2
6247 14:44:17.335564 RPST = 0x0
6248 14:44:17.335645 RD_PRE = 0x0
6249 14:44:17.338856 WR_PRE = 0x1
6250 14:44:17.338953 WR_PST = 0x0
6251 14:44:17.342275 DBI_WR = 0x0
6252 14:44:17.342357 DBI_RD = 0x0
6253 14:44:17.345493 OTF = 0x1
6254 14:44:17.348965 ===================================
6255 14:44:17.352338 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6256 14:44:17.355412 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6257 14:44:17.362193 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6258 14:44:17.365128 ===================================
6259 14:44:17.368890 LPDDR4 DRAM CONFIGURATION
6260 14:44:17.371866 ===================================
6261 14:44:17.371951 EX_ROW_EN[0] = 0x10
6262 14:44:17.375159 EX_ROW_EN[1] = 0x0
6263 14:44:17.375240 LP4Y_EN = 0x0
6264 14:44:17.378566 WORK_FSP = 0x0
6265 14:44:17.378647 WL = 0x2
6266 14:44:17.381740 RL = 0x2
6267 14:44:17.381820 BL = 0x2
6268 14:44:17.384881 RPST = 0x0
6269 14:44:17.384961 RD_PRE = 0x0
6270 14:44:17.388919 WR_PRE = 0x1
6271 14:44:17.388999 WR_PST = 0x0
6272 14:44:17.391964 DBI_WR = 0x0
6273 14:44:17.395111 DBI_RD = 0x0
6274 14:44:17.395191 OTF = 0x1
6275 14:44:17.397960 ===================================
6276 14:44:17.404872 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6277 14:44:17.408206 nWR fixed to 30
6278 14:44:17.411644 [ModeRegInit_LP4] CH0 RK0
6279 14:44:17.411724 [ModeRegInit_LP4] CH0 RK1
6280 14:44:17.415129 [ModeRegInit_LP4] CH1 RK0
6281 14:44:17.418426 [ModeRegInit_LP4] CH1 RK1
6282 14:44:17.418507 match AC timing 19
6283 14:44:17.424742 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6284 14:44:17.428408 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6285 14:44:17.431588 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6286 14:44:17.438409 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6287 14:44:17.441687 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6288 14:44:17.441784 ==
6289 14:44:17.444830 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 14:44:17.448372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 14:44:17.448452 ==
6292 14:44:17.454729 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6293 14:44:17.461693 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6294 14:44:17.464761 [CA 0] Center 36 (8~64) winsize 57
6295 14:44:17.468176 [CA 1] Center 36 (8~64) winsize 57
6296 14:44:17.471619 [CA 2] Center 36 (8~64) winsize 57
6297 14:44:17.474841 [CA 3] Center 36 (8~64) winsize 57
6298 14:44:17.474939 [CA 4] Center 36 (8~64) winsize 57
6299 14:44:17.478126 [CA 5] Center 36 (8~64) winsize 57
6300 14:44:17.478206
6301 14:44:17.484587 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6302 14:44:17.484699
6303 14:44:17.488139 [CATrainingPosCal] consider 1 rank data
6304 14:44:17.491263 u2DelayCellTimex100 = 270/100 ps
6305 14:44:17.494478 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 14:44:17.498230 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 14:44:17.501501 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 14:44:17.504533 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 14:44:17.507971 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 14:44:17.511389 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 14:44:17.511470
6312 14:44:17.514815 CA PerBit enable=1, Macro0, CA PI delay=36
6313 14:44:17.514896
6314 14:44:17.518178 [CBTSetCACLKResult] CA Dly = 36
6315 14:44:17.521435 CS Dly: 1 (0~32)
6316 14:44:17.521516 ==
6317 14:44:17.524387 Dram Type= 6, Freq= 0, CH_0, rank 1
6318 14:44:17.527786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 14:44:17.527885 ==
6320 14:44:17.534472 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6321 14:44:17.537723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6322 14:44:17.540898 [CA 0] Center 36 (8~64) winsize 57
6323 14:44:17.544054 [CA 1] Center 36 (8~64) winsize 57
6324 14:44:17.547550 [CA 2] Center 36 (8~64) winsize 57
6325 14:44:17.551095 [CA 3] Center 36 (8~64) winsize 57
6326 14:44:17.554308 [CA 4] Center 36 (8~64) winsize 57
6327 14:44:17.557526 [CA 5] Center 36 (8~64) winsize 57
6328 14:44:17.557608
6329 14:44:17.560908 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6330 14:44:17.560990
6331 14:44:17.564116 [CATrainingPosCal] consider 2 rank data
6332 14:44:17.567555 u2DelayCellTimex100 = 270/100 ps
6333 14:44:17.570915 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 14:44:17.577460 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 14:44:17.580874 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 14:44:17.584134 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 14:44:17.587375 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 14:44:17.590624 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 14:44:17.590704
6340 14:44:17.593830 CA PerBit enable=1, Macro0, CA PI delay=36
6341 14:44:17.593910
6342 14:44:17.597159 [CBTSetCACLKResult] CA Dly = 36
6343 14:44:17.597239 CS Dly: 1 (0~32)
6344 14:44:17.600688
6345 14:44:17.603783 ----->DramcWriteLeveling(PI) begin...
6346 14:44:17.603865 ==
6347 14:44:17.607054 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 14:44:17.610292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 14:44:17.610374 ==
6350 14:44:17.613709 Write leveling (Byte 0): 40 => 8
6351 14:44:17.617238 Write leveling (Byte 1): 40 => 8
6352 14:44:17.620636 DramcWriteLeveling(PI) end<-----
6353 14:44:17.620717
6354 14:44:17.620782 ==
6355 14:44:17.623407 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 14:44:17.626768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 14:44:17.626849 ==
6358 14:44:17.630112 [Gating] SW mode calibration
6359 14:44:17.636652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6360 14:44:17.643770 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6361 14:44:17.646928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6362 14:44:17.650192 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6363 14:44:17.656991 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6364 14:44:17.659894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6365 14:44:17.663800 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6366 14:44:17.670306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6367 14:44:17.673547 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6368 14:44:17.676816 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6369 14:44:17.683419 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6370 14:44:17.683526 Total UI for P1: 0, mck2ui 16
6371 14:44:17.686630 best dqsien dly found for B0: ( 0, 14, 24)
6372 14:44:17.690276 Total UI for P1: 0, mck2ui 16
6373 14:44:17.693652 best dqsien dly found for B1: ( 0, 14, 24)
6374 14:44:17.696660 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6375 14:44:17.703069 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6376 14:44:17.703193
6377 14:44:17.706785 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6378 14:44:17.709621 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6379 14:44:17.713128 [Gating] SW calibration Done
6380 14:44:17.713248 ==
6381 14:44:17.716534 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 14:44:17.719991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 14:44:17.720112 ==
6384 14:44:17.722877 RX Vref Scan: 0
6385 14:44:17.722998
6386 14:44:17.723108 RX Vref 0 -> 0, step: 1
6387 14:44:17.723214
6388 14:44:17.726124 RX Delay -410 -> 252, step: 16
6389 14:44:17.729591 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6390 14:44:17.736285 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6391 14:44:17.739705 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6392 14:44:17.743083 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6393 14:44:17.749336 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6394 14:44:17.753065 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6395 14:44:17.756421 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6396 14:44:17.759620 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6397 14:44:17.763224 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6398 14:44:17.769461 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6399 14:44:17.772751 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6400 14:44:17.776160 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6401 14:44:17.783026 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6402 14:44:17.785791 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6403 14:44:17.788987 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6404 14:44:17.792534 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6405 14:44:17.795714 ==
6406 14:44:17.798960 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 14:44:17.802170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 14:44:17.802270 ==
6409 14:44:17.802369 DQS Delay:
6410 14:44:17.805561 DQS0 = 59, DQS1 = 59
6411 14:44:17.805642 DQM Delay:
6412 14:44:17.809081 DQM0 = 18, DQM1 = 10
6413 14:44:17.809163 DQ Delay:
6414 14:44:17.812517 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6415 14:44:17.815927 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6416 14:44:17.818850 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6417 14:44:17.822285 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6418 14:44:17.822368
6419 14:44:17.822432
6420 14:44:17.822492 ==
6421 14:44:17.825612 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 14:44:17.828788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 14:44:17.828871 ==
6424 14:44:17.828935
6425 14:44:17.828996
6426 14:44:17.832235 TX Vref Scan disable
6427 14:44:17.832316 == TX Byte 0 ==
6428 14:44:17.839094 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 14:44:17.841887 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 14:44:17.841969 == TX Byte 1 ==
6431 14:44:17.848704 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6432 14:44:17.852130 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6433 14:44:17.852216 ==
6434 14:44:17.855309 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 14:44:17.858426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 14:44:17.858526 ==
6437 14:44:17.858623
6438 14:44:17.858716
6439 14:44:17.861823 TX Vref Scan disable
6440 14:44:17.865186 == TX Byte 0 ==
6441 14:44:17.868645 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6442 14:44:17.872107 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6443 14:44:17.872190 == TX Byte 1 ==
6444 14:44:17.878431 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6445 14:44:17.881729 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6446 14:44:17.881825
6447 14:44:17.881891 [DATLAT]
6448 14:44:17.885098 Freq=400, CH0 RK0
6449 14:44:17.885208
6450 14:44:17.885306 DATLAT Default: 0xf
6451 14:44:17.888098 0, 0xFFFF, sum = 0
6452 14:44:17.888210 1, 0xFFFF, sum = 0
6453 14:44:17.891372 2, 0xFFFF, sum = 0
6454 14:44:17.894801 3, 0xFFFF, sum = 0
6455 14:44:17.894917 4, 0xFFFF, sum = 0
6456 14:44:17.898311 5, 0xFFFF, sum = 0
6457 14:44:17.898418 6, 0xFFFF, sum = 0
6458 14:44:17.901537 7, 0xFFFF, sum = 0
6459 14:44:17.901612 8, 0xFFFF, sum = 0
6460 14:44:17.904744 9, 0xFFFF, sum = 0
6461 14:44:17.904819 10, 0xFFFF, sum = 0
6462 14:44:17.908397 11, 0xFFFF, sum = 0
6463 14:44:17.908502 12, 0xFFFF, sum = 0
6464 14:44:17.911393 13, 0x0, sum = 1
6465 14:44:17.911493 14, 0x0, sum = 2
6466 14:44:17.914761 15, 0x0, sum = 3
6467 14:44:17.914861 16, 0x0, sum = 4
6468 14:44:17.917995 best_step = 14
6469 14:44:17.918100
6470 14:44:17.918191 ==
6471 14:44:17.921640 Dram Type= 6, Freq= 0, CH_0, rank 0
6472 14:44:17.924392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 14:44:17.924492 ==
6474 14:44:17.924615 RX Vref Scan: 1
6475 14:44:17.927852
6476 14:44:17.927925 RX Vref 0 -> 0, step: 1
6477 14:44:17.928031
6478 14:44:17.931470 RX Delay -359 -> 252, step: 8
6479 14:44:17.931556
6480 14:44:17.934640 Set Vref, RX VrefLevel [Byte0]: 62
6481 14:44:17.938068 [Byte1]: 46
6482 14:44:17.942324
6483 14:44:17.942427 Final RX Vref Byte 0 = 62 to rank0
6484 14:44:17.945396 Final RX Vref Byte 1 = 46 to rank0
6485 14:44:17.948488 Final RX Vref Byte 0 = 62 to rank1
6486 14:44:17.951903 Final RX Vref Byte 1 = 46 to rank1==
6487 14:44:17.955319 Dram Type= 6, Freq= 0, CH_0, rank 0
6488 14:44:17.961916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 14:44:17.962006 ==
6490 14:44:17.962106 DQS Delay:
6491 14:44:17.965040 DQS0 = 60, DQS1 = 68
6492 14:44:17.965122 DQM Delay:
6493 14:44:17.965203 DQM0 = 15, DQM1 = 14
6494 14:44:17.968312 DQ Delay:
6495 14:44:17.971741 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =12
6496 14:44:17.975232 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6497 14:44:17.978522 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6498 14:44:17.982021 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6499 14:44:17.982135
6500 14:44:17.982228
6501 14:44:17.988212 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6502 14:44:17.991624 CH0 RK0: MR19=C0C, MR18=7F7D
6503 14:44:17.998448 CH0_RK0: MR19=0xC0C, MR18=0x7F7D, DQSOSC=393, MR23=63, INC=382, DEC=254
6504 14:44:17.998552 ==
6505 14:44:18.001876 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 14:44:18.005006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 14:44:18.005103 ==
6508 14:44:18.008369 [Gating] SW mode calibration
6509 14:44:18.015145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6510 14:44:18.021557 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6511 14:44:18.025337 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6512 14:44:18.028215 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6513 14:44:18.034834 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6514 14:44:18.038231 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6515 14:44:18.041539 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6516 14:44:18.048079 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6517 14:44:18.051409 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6518 14:44:18.055021 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6519 14:44:18.061288 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6520 14:44:18.061395 Total UI for P1: 0, mck2ui 16
6521 14:44:18.067944 best dqsien dly found for B0: ( 0, 14, 24)
6522 14:44:18.068050 Total UI for P1: 0, mck2ui 16
6523 14:44:18.074261 best dqsien dly found for B1: ( 0, 14, 24)
6524 14:44:18.077877 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6525 14:44:18.081202 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6526 14:44:18.081277
6527 14:44:18.084145 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6528 14:44:18.088090 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6529 14:44:18.091092 [Gating] SW calibration Done
6530 14:44:18.091164 ==
6531 14:44:18.094411 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 14:44:18.097402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 14:44:18.097478 ==
6534 14:44:18.100958 RX Vref Scan: 0
6535 14:44:18.101059
6536 14:44:18.101153 RX Vref 0 -> 0, step: 1
6537 14:44:18.101216
6538 14:44:18.103915 RX Delay -410 -> 252, step: 16
6539 14:44:18.110745 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6540 14:44:18.114113 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6541 14:44:18.117690 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6542 14:44:18.120484 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6543 14:44:18.127239 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6544 14:44:18.130635 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6545 14:44:18.134025 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6546 14:44:18.137703 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6547 14:44:18.143940 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6548 14:44:18.147197 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6549 14:44:18.150844 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6550 14:44:18.154171 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6551 14:44:18.160342 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6552 14:44:18.163665 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6553 14:44:18.167384 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6554 14:44:18.173851 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6555 14:44:18.173934 ==
6556 14:44:18.176937 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 14:44:18.180160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 14:44:18.180287 ==
6559 14:44:18.180402 DQS Delay:
6560 14:44:18.184021 DQS0 = 59, DQS1 = 59
6561 14:44:18.184143 DQM Delay:
6562 14:44:18.186691 DQM0 = 16, DQM1 = 10
6563 14:44:18.186812 DQ Delay:
6564 14:44:18.190251 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6565 14:44:18.193693 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6566 14:44:18.197201 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6567 14:44:18.200404 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6568 14:44:18.200534
6569 14:44:18.200657
6570 14:44:18.200768 ==
6571 14:44:18.203748 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 14:44:18.207106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 14:44:18.207234 ==
6574 14:44:18.207350
6575 14:44:18.207461
6576 14:44:18.210324 TX Vref Scan disable
6577 14:44:18.213566 == TX Byte 0 ==
6578 14:44:18.216664 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6579 14:44:18.220121 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6580 14:44:18.223557 == TX Byte 1 ==
6581 14:44:18.226529 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6582 14:44:18.229781 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6583 14:44:18.229906 ==
6584 14:44:18.233203 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 14:44:18.236667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 14:44:18.236792 ==
6587 14:44:18.236900
6588 14:44:18.239602
6589 14:44:18.239727 TX Vref Scan disable
6590 14:44:18.243089 == TX Byte 0 ==
6591 14:44:18.246454 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6592 14:44:18.249714 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6593 14:44:18.253409 == TX Byte 1 ==
6594 14:44:18.256514 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6595 14:44:18.259936 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6596 14:44:18.260062
6597 14:44:18.260175 [DATLAT]
6598 14:44:18.263481 Freq=400, CH0 RK1
6599 14:44:18.263590
6600 14:44:18.263699 DATLAT Default: 0xe
6601 14:44:18.266784 0, 0xFFFF, sum = 0
6602 14:44:18.266908 1, 0xFFFF, sum = 0
6603 14:44:18.270180 2, 0xFFFF, sum = 0
6604 14:44:18.273271 3, 0xFFFF, sum = 0
6605 14:44:18.273413 4, 0xFFFF, sum = 0
6606 14:44:18.276439 5, 0xFFFF, sum = 0
6607 14:44:18.276625 6, 0xFFFF, sum = 0
6608 14:44:18.279524 7, 0xFFFF, sum = 0
6609 14:44:18.279695 8, 0xFFFF, sum = 0
6610 14:44:18.283292 9, 0xFFFF, sum = 0
6611 14:44:18.283378 10, 0xFFFF, sum = 0
6612 14:44:18.286546 11, 0xFFFF, sum = 0
6613 14:44:18.286631 12, 0xFFFF, sum = 0
6614 14:44:18.289554 13, 0x0, sum = 1
6615 14:44:18.289638 14, 0x0, sum = 2
6616 14:44:18.293248 15, 0x0, sum = 3
6617 14:44:18.293333 16, 0x0, sum = 4
6618 14:44:18.296436 best_step = 14
6619 14:44:18.296518
6620 14:44:18.296593 ==
6621 14:44:18.299290 Dram Type= 6, Freq= 0, CH_0, rank 1
6622 14:44:18.302791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 14:44:18.302918 ==
6624 14:44:18.303030 RX Vref Scan: 0
6625 14:44:18.306091
6626 14:44:18.306214 RX Vref 0 -> 0, step: 1
6627 14:44:18.306324
6628 14:44:18.309491 RX Delay -359 -> 252, step: 8
6629 14:44:18.316896 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6630 14:44:18.320463 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6631 14:44:18.323667 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6632 14:44:18.330372 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6633 14:44:18.333711 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6634 14:44:18.336852 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6635 14:44:18.340286 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6636 14:44:18.343813 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6637 14:44:18.349970 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6638 14:44:18.353406 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6639 14:44:18.356902 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6640 14:44:18.363088 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6641 14:44:18.366647 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6642 14:44:18.370146 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6643 14:44:18.373303 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6644 14:44:18.379923 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6645 14:44:18.380092 ==
6646 14:44:18.383132 Dram Type= 6, Freq= 0, CH_0, rank 1
6647 14:44:18.386352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 14:44:18.386438 ==
6649 14:44:18.386503 DQS Delay:
6650 14:44:18.389836 DQS0 = 60, DQS1 = 72
6651 14:44:18.389919 DQM Delay:
6652 14:44:18.393298 DQM0 = 11, DQM1 = 16
6653 14:44:18.393412 DQ Delay:
6654 14:44:18.396287 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6655 14:44:18.399730 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6656 14:44:18.402998 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6657 14:44:18.406255 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6658 14:44:18.406339
6659 14:44:18.406404
6660 14:44:18.412925 [DQSOSCAuto] RK1, (LSB)MR18= 0xc77c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6661 14:44:18.416209 CH0 RK1: MR19=C0C, MR18=C77C
6662 14:44:18.422881 CH0_RK1: MR19=0xC0C, MR18=0xC77C, DQSOSC=385, MR23=63, INC=398, DEC=265
6663 14:44:18.426148 [RxdqsGatingPostProcess] freq 400
6664 14:44:18.432546 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6665 14:44:18.435966 best DQS0 dly(2T, 0.5T) = (0, 10)
6666 14:44:18.439195 best DQS1 dly(2T, 0.5T) = (0, 10)
6667 14:44:18.439303 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6668 14:44:18.442786 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6669 14:44:18.445998 best DQS0 dly(2T, 0.5T) = (0, 10)
6670 14:44:18.449373 best DQS1 dly(2T, 0.5T) = (0, 10)
6671 14:44:18.452664 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6672 14:44:18.456325 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6673 14:44:18.459691 Pre-setting of DQS Precalculation
6674 14:44:18.465712 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6675 14:44:18.465794 ==
6676 14:44:18.469257 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 14:44:18.472709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 14:44:18.472815 ==
6679 14:44:18.479182 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6680 14:44:18.485469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6681 14:44:18.485551 [CA 0] Center 36 (8~64) winsize 57
6682 14:44:18.488867 [CA 1] Center 36 (8~64) winsize 57
6683 14:44:18.492331 [CA 2] Center 36 (8~64) winsize 57
6684 14:44:18.495785 [CA 3] Center 36 (8~64) winsize 57
6685 14:44:18.499084 [CA 4] Center 36 (8~64) winsize 57
6686 14:44:18.502426 [CA 5] Center 36 (8~64) winsize 57
6687 14:44:18.502547
6688 14:44:18.505388 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6689 14:44:18.505504
6690 14:44:18.508966 [CATrainingPosCal] consider 1 rank data
6691 14:44:18.511977 u2DelayCellTimex100 = 270/100 ps
6692 14:44:18.515558 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 14:44:18.522079 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 14:44:18.525211 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 14:44:18.528562 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 14:44:18.532301 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 14:44:18.535432 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 14:44:18.535513
6699 14:44:18.538598 CA PerBit enable=1, Macro0, CA PI delay=36
6700 14:44:18.538678
6701 14:44:18.541904 [CBTSetCACLKResult] CA Dly = 36
6702 14:44:18.541987 CS Dly: 1 (0~32)
6703 14:44:18.545288 ==
6704 14:44:18.548617 Dram Type= 6, Freq= 0, CH_1, rank 1
6705 14:44:18.552030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 14:44:18.552112 ==
6707 14:44:18.554983 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6708 14:44:18.561863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6709 14:44:18.565238 [CA 0] Center 36 (8~64) winsize 57
6710 14:44:18.568594 [CA 1] Center 36 (8~64) winsize 57
6711 14:44:18.571459 [CA 2] Center 36 (8~64) winsize 57
6712 14:44:18.574848 [CA 3] Center 36 (8~64) winsize 57
6713 14:44:18.578201 [CA 4] Center 36 (8~64) winsize 57
6714 14:44:18.581557 [CA 5] Center 36 (8~64) winsize 57
6715 14:44:18.581655
6716 14:44:18.585017 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6717 14:44:18.585098
6718 14:44:18.588550 [CATrainingPosCal] consider 2 rank data
6719 14:44:18.591721 u2DelayCellTimex100 = 270/100 ps
6720 14:44:18.594802 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 14:44:18.598699 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 14:44:18.601836 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 14:44:18.604897 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 14:44:18.611470 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 14:44:18.614751 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 14:44:18.614846
6727 14:44:18.618504 CA PerBit enable=1, Macro0, CA PI delay=36
6728 14:44:18.618585
6729 14:44:18.621444 [CBTSetCACLKResult] CA Dly = 36
6730 14:44:18.621524 CS Dly: 1 (0~32)
6731 14:44:18.621641
6732 14:44:18.624810 ----->DramcWriteLeveling(PI) begin...
6733 14:44:18.624935 ==
6734 14:44:18.627838 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 14:44:18.634760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 14:44:18.634873 ==
6737 14:44:18.637913 Write leveling (Byte 0): 40 => 8
6738 14:44:18.641159 Write leveling (Byte 1): 40 => 8
6739 14:44:18.641241 DramcWriteLeveling(PI) end<-----
6740 14:44:18.641305
6741 14:44:18.644547 ==
6742 14:44:18.647683 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 14:44:18.651455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 14:44:18.651536 ==
6745 14:44:18.654222 [Gating] SW mode calibration
6746 14:44:18.661052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6747 14:44:18.664425 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6748 14:44:18.670677 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6749 14:44:18.674112 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6750 14:44:18.677712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6751 14:44:18.683951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6752 14:44:18.687363 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6753 14:44:18.690857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6754 14:44:18.697563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6755 14:44:18.700575 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6756 14:44:18.704159 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6757 14:44:18.707487 Total UI for P1: 0, mck2ui 16
6758 14:44:18.710764 best dqsien dly found for B0: ( 0, 14, 24)
6759 14:44:18.714210 Total UI for P1: 0, mck2ui 16
6760 14:44:18.717237 best dqsien dly found for B1: ( 0, 14, 24)
6761 14:44:18.720225 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6762 14:44:18.724168 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6763 14:44:18.726817
6764 14:44:18.730487 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6765 14:44:18.733708 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6766 14:44:18.737085 [Gating] SW calibration Done
6767 14:44:18.737163 ==
6768 14:44:18.740199 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 14:44:18.743499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 14:44:18.743601 ==
6771 14:44:18.743693 RX Vref Scan: 0
6772 14:44:18.746905
6773 14:44:18.747006 RX Vref 0 -> 0, step: 1
6774 14:44:18.747101
6775 14:44:18.750312 RX Delay -410 -> 252, step: 16
6776 14:44:18.753926 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6777 14:44:18.760123 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6778 14:44:18.763650 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6779 14:44:18.767003 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6780 14:44:18.770311 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6781 14:44:18.777313 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6782 14:44:18.780194 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6783 14:44:18.783658 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6784 14:44:18.786879 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6785 14:44:18.793697 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6786 14:44:18.797127 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6787 14:44:18.800418 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6788 14:44:18.803186 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6789 14:44:18.810086 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6790 14:44:18.813223 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6791 14:44:18.816969 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6792 14:44:18.817069 ==
6793 14:44:18.819991 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 14:44:18.826545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 14:44:18.826650 ==
6796 14:44:18.826742 DQS Delay:
6797 14:44:18.830041 DQS0 = 51, DQS1 = 67
6798 14:44:18.830122 DQM Delay:
6799 14:44:18.830185 DQM0 = 12, DQM1 = 19
6800 14:44:18.833277 DQ Delay:
6801 14:44:18.836434 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6802 14:44:18.836534 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6803 14:44:18.839737 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6804 14:44:18.843284 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6805 14:44:18.846048
6806 14:44:18.846180
6807 14:44:18.846245 ==
6808 14:44:18.849763 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 14:44:18.852837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 14:44:18.852918 ==
6811 14:44:18.852982
6812 14:44:18.853041
6813 14:44:18.856128 TX Vref Scan disable
6814 14:44:18.856223 == TX Byte 0 ==
6815 14:44:18.859376 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 14:44:18.866189 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 14:44:18.866271 == TX Byte 1 ==
6818 14:44:18.869714 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 14:44:18.876448 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 14:44:18.876549 ==
6821 14:44:18.879279 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 14:44:18.882667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 14:44:18.882768 ==
6824 14:44:18.882897
6825 14:44:18.883021
6826 14:44:18.885997 TX Vref Scan disable
6827 14:44:18.886092 == TX Byte 0 ==
6828 14:44:18.892595 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6829 14:44:18.895958 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6830 14:44:18.896041 == TX Byte 1 ==
6831 14:44:18.902809 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6832 14:44:18.905579 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6833 14:44:18.905659
6834 14:44:18.905723 [DATLAT]
6835 14:44:18.909122 Freq=400, CH1 RK0
6836 14:44:18.909204
6837 14:44:18.909267 DATLAT Default: 0xf
6838 14:44:18.912598 0, 0xFFFF, sum = 0
6839 14:44:18.912694 1, 0xFFFF, sum = 0
6840 14:44:18.915794 2, 0xFFFF, sum = 0
6841 14:44:18.915885 3, 0xFFFF, sum = 0
6842 14:44:18.919157 4, 0xFFFF, sum = 0
6843 14:44:18.919239 5, 0xFFFF, sum = 0
6844 14:44:18.922520 6, 0xFFFF, sum = 0
6845 14:44:18.922602 7, 0xFFFF, sum = 0
6846 14:44:18.925982 8, 0xFFFF, sum = 0
6847 14:44:18.926074 9, 0xFFFF, sum = 0
6848 14:44:18.928738 10, 0xFFFF, sum = 0
6849 14:44:18.928820 11, 0xFFFF, sum = 0
6850 14:44:18.932298 12, 0xFFFF, sum = 0
6851 14:44:18.932385 13, 0x0, sum = 1
6852 14:44:18.935602 14, 0x0, sum = 2
6853 14:44:18.935720 15, 0x0, sum = 3
6854 14:44:18.938697 16, 0x0, sum = 4
6855 14:44:18.938806 best_step = 14
6856 14:44:18.938897
6857 14:44:18.938984 ==
6858 14:44:18.942426 Dram Type= 6, Freq= 0, CH_1, rank 0
6859 14:44:18.949252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 14:44:18.949334 ==
6861 14:44:18.949398 RX Vref Scan: 1
6862 14:44:18.949478
6863 14:44:18.952082 RX Vref 0 -> 0, step: 1
6864 14:44:18.952163
6865 14:44:18.955346 RX Delay -375 -> 252, step: 8
6866 14:44:18.955441
6867 14:44:18.959069 Set Vref, RX VrefLevel [Byte0]: 59
6868 14:44:18.962292 [Byte1]: 48
6869 14:44:18.965400
6870 14:44:18.965480 Final RX Vref Byte 0 = 59 to rank0
6871 14:44:18.968786 Final RX Vref Byte 1 = 48 to rank0
6872 14:44:18.972245 Final RX Vref Byte 0 = 59 to rank1
6873 14:44:18.975407 Final RX Vref Byte 1 = 48 to rank1==
6874 14:44:18.978911 Dram Type= 6, Freq= 0, CH_1, rank 0
6875 14:44:18.985243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 14:44:18.985325 ==
6877 14:44:18.985389 DQS Delay:
6878 14:44:18.988658 DQS0 = 56, DQS1 = 68
6879 14:44:18.988737 DQM Delay:
6880 14:44:18.988801 DQM0 = 13, DQM1 = 14
6881 14:44:18.992069 DQ Delay:
6882 14:44:18.995296 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6883 14:44:18.995376 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6884 14:44:18.998631 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6885 14:44:19.002175 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6886 14:44:19.005067
6887 14:44:19.005147
6888 14:44:19.011730 [DQSOSCAuto] RK0, (LSB)MR18= 0x5467, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6889 14:44:19.015232 CH1 RK0: MR19=C0C, MR18=5467
6890 14:44:19.022154 CH1_RK0: MR19=0xC0C, MR18=0x5467, DQSOSC=396, MR23=63, INC=376, DEC=251
6891 14:44:19.022236 ==
6892 14:44:19.025210 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 14:44:19.028357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 14:44:19.028437 ==
6895 14:44:19.031955 [Gating] SW mode calibration
6896 14:44:19.038380 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6897 14:44:19.045128 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6898 14:44:19.048133 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6899 14:44:19.051648 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6900 14:44:19.058434 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6901 14:44:19.061325 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6902 14:44:19.064531 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6903 14:44:19.071391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6904 14:44:19.074897 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6905 14:44:19.077686 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6906 14:44:19.084700 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6907 14:44:19.084805 Total UI for P1: 0, mck2ui 16
6908 14:44:19.091441 best dqsien dly found for B0: ( 0, 14, 24)
6909 14:44:19.091543 Total UI for P1: 0, mck2ui 16
6910 14:44:19.097957 best dqsien dly found for B1: ( 0, 14, 24)
6911 14:44:19.101430 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6912 14:44:19.104786 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6913 14:44:19.104888
6914 14:44:19.107585 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6915 14:44:19.110948 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6916 14:44:19.114543 [Gating] SW calibration Done
6917 14:44:19.114645 ==
6918 14:44:19.117305 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 14:44:19.121225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 14:44:19.121300 ==
6921 14:44:19.124161 RX Vref Scan: 0
6922 14:44:19.124285
6923 14:44:19.124395 RX Vref 0 -> 0, step: 1
6924 14:44:19.124483
6925 14:44:19.127731 RX Delay -410 -> 252, step: 16
6926 14:44:19.134241 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6927 14:44:19.137316 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6928 14:44:19.140757 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6929 14:44:19.144208 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6930 14:44:19.150890 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6931 14:44:19.154202 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6932 14:44:19.157492 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6933 14:44:19.160699 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6934 14:44:19.167507 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6935 14:44:19.170706 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6936 14:44:19.173966 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6937 14:44:19.177284 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6938 14:44:19.183658 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6939 14:44:19.187017 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6940 14:44:19.190556 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6941 14:44:19.193897 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6942 14:44:19.197331 ==
6943 14:44:19.200563 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 14:44:19.203733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 14:44:19.203826 ==
6946 14:44:19.203960 DQS Delay:
6947 14:44:19.207051 DQS0 = 59, DQS1 = 59
6948 14:44:19.207153 DQM Delay:
6949 14:44:19.210521 DQM0 = 19, DQM1 = 12
6950 14:44:19.210622 DQ Delay:
6951 14:44:19.213630 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6952 14:44:19.217238 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6953 14:44:19.220513 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6954 14:44:19.223811 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6955 14:44:19.223892
6956 14:44:19.223956
6957 14:44:19.224015 ==
6958 14:44:19.226696 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 14:44:19.230089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 14:44:19.230170 ==
6961 14:44:19.230234
6962 14:44:19.230293
6963 14:44:19.233632 TX Vref Scan disable
6964 14:44:19.233713 == TX Byte 0 ==
6965 14:44:19.240341 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6966 14:44:19.243455 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6967 14:44:19.243580 == TX Byte 1 ==
6968 14:44:19.250125 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6969 14:44:19.253147 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6970 14:44:19.253269 ==
6971 14:44:19.256330 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 14:44:19.260136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 14:44:19.260245 ==
6974 14:44:19.260342
6975 14:44:19.260432
6976 14:44:19.262938 TX Vref Scan disable
6977 14:44:19.266385 == TX Byte 0 ==
6978 14:44:19.269886 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6979 14:44:19.273210 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6980 14:44:19.276489 == TX Byte 1 ==
6981 14:44:19.279621 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6982 14:44:19.283048 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6983 14:44:19.283147
6984 14:44:19.283241 [DATLAT]
6985 14:44:19.286299 Freq=400, CH1 RK1
6986 14:44:19.286380
6987 14:44:19.286470 DATLAT Default: 0xe
6988 14:44:19.289752 0, 0xFFFF, sum = 0
6989 14:44:19.289825 1, 0xFFFF, sum = 0
6990 14:44:19.293020 2, 0xFFFF, sum = 0
6991 14:44:19.293120 3, 0xFFFF, sum = 0
6992 14:44:19.296191 4, 0xFFFF, sum = 0
6993 14:44:19.299348 5, 0xFFFF, sum = 0
6994 14:44:19.299452 6, 0xFFFF, sum = 0
6995 14:44:19.302668 7, 0xFFFF, sum = 0
6996 14:44:19.302787 8, 0xFFFF, sum = 0
6997 14:44:19.306098 9, 0xFFFF, sum = 0
6998 14:44:19.306200 10, 0xFFFF, sum = 0
6999 14:44:19.309463 11, 0xFFFF, sum = 0
7000 14:44:19.309561 12, 0xFFFF, sum = 0
7001 14:44:19.312740 13, 0x0, sum = 1
7002 14:44:19.312840 14, 0x0, sum = 2
7003 14:44:19.315965 15, 0x0, sum = 3
7004 14:44:19.316082 16, 0x0, sum = 4
7005 14:44:19.319361 best_step = 14
7006 14:44:19.319460
7007 14:44:19.319548 ==
7008 14:44:19.322791 Dram Type= 6, Freq= 0, CH_1, rank 1
7009 14:44:19.326102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7010 14:44:19.326200 ==
7011 14:44:19.329190 RX Vref Scan: 0
7012 14:44:19.329292
7013 14:44:19.329381 RX Vref 0 -> 0, step: 1
7014 14:44:19.329468
7015 14:44:19.332588 RX Delay -359 -> 252, step: 8
7016 14:44:19.339933 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7017 14:44:19.343315 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7018 14:44:19.346677 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7019 14:44:19.349952 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7020 14:44:19.356919 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7021 14:44:19.360254 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7022 14:44:19.363617 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7023 14:44:19.366772 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
7024 14:44:19.372981 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7025 14:44:19.376408 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7026 14:44:19.379780 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7027 14:44:19.386464 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7028 14:44:19.389943 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7029 14:44:19.393499 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7030 14:44:19.396208 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7031 14:44:19.403221 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7032 14:44:19.403326 ==
7033 14:44:19.406561 Dram Type= 6, Freq= 0, CH_1, rank 1
7034 14:44:19.409672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7035 14:44:19.409794 ==
7036 14:44:19.409905 DQS Delay:
7037 14:44:19.412911 DQS0 = 60, DQS1 = 64
7038 14:44:19.413033 DQM Delay:
7039 14:44:19.416396 DQM0 = 13, DQM1 = 10
7040 14:44:19.416494 DQ Delay:
7041 14:44:19.419238 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7042 14:44:19.422790 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7043 14:44:19.426066 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7044 14:44:19.429355 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7045 14:44:19.429478
7046 14:44:19.429587
7047 14:44:19.436077 [DQSOSCAuto] RK1, (LSB)MR18= 0x75a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7048 14:44:19.439508 CH1 RK1: MR19=C0C, MR18=75A5
7049 14:44:19.446340 CH1_RK1: MR19=0xC0C, MR18=0x75A5, DQSOSC=389, MR23=63, INC=390, DEC=260
7050 14:44:19.449314 [RxdqsGatingPostProcess] freq 400
7051 14:44:19.456089 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7052 14:44:19.459135 best DQS0 dly(2T, 0.5T) = (0, 10)
7053 14:44:19.462539 best DQS1 dly(2T, 0.5T) = (0, 10)
7054 14:44:19.465773 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7055 14:44:19.469214 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7056 14:44:19.469316 best DQS0 dly(2T, 0.5T) = (0, 10)
7057 14:44:19.472482 best DQS1 dly(2T, 0.5T) = (0, 10)
7058 14:44:19.476041 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7059 14:44:19.479433 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7060 14:44:19.482347 Pre-setting of DQS Precalculation
7061 14:44:19.489339 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7062 14:44:19.495883 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7063 14:44:19.502464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7064 14:44:19.502548
7065 14:44:19.502613
7066 14:44:19.505841 [Calibration Summary] 800 Mbps
7067 14:44:19.505924 CH 0, Rank 0
7068 14:44:19.508777 SW Impedance : PASS
7069 14:44:19.512468 DUTY Scan : NO K
7070 14:44:19.512596 ZQ Calibration : PASS
7071 14:44:19.515616 Jitter Meter : NO K
7072 14:44:19.518902 CBT Training : PASS
7073 14:44:19.519025 Write leveling : PASS
7074 14:44:19.522149 RX DQS gating : PASS
7075 14:44:19.525577 RX DQ/DQS(RDDQC) : PASS
7076 14:44:19.525701 TX DQ/DQS : PASS
7077 14:44:19.529074 RX DATLAT : PASS
7078 14:44:19.529196 RX DQ/DQS(Engine): PASS
7079 14:44:19.532289 TX OE : NO K
7080 14:44:19.532415 All Pass.
7081 14:44:19.532535
7082 14:44:19.535288 CH 0, Rank 1
7083 14:44:19.535408 SW Impedance : PASS
7084 14:44:19.538650 DUTY Scan : NO K
7085 14:44:19.541940 ZQ Calibration : PASS
7086 14:44:19.542026 Jitter Meter : NO K
7087 14:44:19.545551 CBT Training : PASS
7088 14:44:19.549247 Write leveling : NO K
7089 14:44:19.549342 RX DQS gating : PASS
7090 14:44:19.552283 RX DQ/DQS(RDDQC) : PASS
7091 14:44:19.555765 TX DQ/DQS : PASS
7092 14:44:19.555874 RX DATLAT : PASS
7093 14:44:19.558701 RX DQ/DQS(Engine): PASS
7094 14:44:19.562138 TX OE : NO K
7095 14:44:19.562221 All Pass.
7096 14:44:19.562286
7097 14:44:19.562355 CH 1, Rank 0
7098 14:44:19.565443 SW Impedance : PASS
7099 14:44:19.568970 DUTY Scan : NO K
7100 14:44:19.569051 ZQ Calibration : PASS
7101 14:44:19.572390 Jitter Meter : NO K
7102 14:44:19.575484 CBT Training : PASS
7103 14:44:19.575566 Write leveling : PASS
7104 14:44:19.578858 RX DQS gating : PASS
7105 14:44:19.581796 RX DQ/DQS(RDDQC) : PASS
7106 14:44:19.581879 TX DQ/DQS : PASS
7107 14:44:19.585439 RX DATLAT : PASS
7108 14:44:19.588272 RX DQ/DQS(Engine): PASS
7109 14:44:19.588353 TX OE : NO K
7110 14:44:19.588419 All Pass.
7111 14:44:19.591875
7112 14:44:19.591957 CH 1, Rank 1
7113 14:44:19.594982 SW Impedance : PASS
7114 14:44:19.595064 DUTY Scan : NO K
7115 14:44:19.598274 ZQ Calibration : PASS
7116 14:44:19.598356 Jitter Meter : NO K
7117 14:44:19.601602 CBT Training : PASS
7118 14:44:19.604929 Write leveling : NO K
7119 14:44:19.605013 RX DQS gating : PASS
7120 14:44:19.608536 RX DQ/DQS(RDDQC) : PASS
7121 14:44:19.611499 TX DQ/DQS : PASS
7122 14:44:19.611581 RX DATLAT : PASS
7123 14:44:19.614740 RX DQ/DQS(Engine): PASS
7124 14:44:19.618112 TX OE : NO K
7125 14:44:19.618208 All Pass.
7126 14:44:19.618274
7127 14:44:19.621632 DramC Write-DBI off
7128 14:44:19.621714 PER_BANK_REFRESH: Hybrid Mode
7129 14:44:19.624864 TX_TRACKING: ON
7130 14:44:19.634898 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7131 14:44:19.638790 [FAST_K] Save calibration result to emmc
7132 14:44:19.641689 dramc_set_vcore_voltage set vcore to 725000
7133 14:44:19.641773 Read voltage for 1600, 0
7134 14:44:19.644990 Vio18 = 0
7135 14:44:19.645074 Vcore = 725000
7136 14:44:19.645139 Vdram = 0
7137 14:44:19.648335 Vddq = 0
7138 14:44:19.648417 Vmddr = 0
7139 14:44:19.651252 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7140 14:44:19.658116 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7141 14:44:19.661569 MEM_TYPE=3, freq_sel=13
7142 14:44:19.664660 sv_algorithm_assistance_LP4_3733
7143 14:44:19.668007 ============ PULL DRAM RESETB DOWN ============
7144 14:44:19.671116 ========== PULL DRAM RESETB DOWN end =========
7145 14:44:19.678116 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7146 14:44:19.680907 ===================================
7147 14:44:19.681034 LPDDR4 DRAM CONFIGURATION
7148 14:44:19.684172 ===================================
7149 14:44:19.687552 EX_ROW_EN[0] = 0x0
7150 14:44:19.690981 EX_ROW_EN[1] = 0x0
7151 14:44:19.691105 LP4Y_EN = 0x0
7152 14:44:19.694465 WORK_FSP = 0x1
7153 14:44:19.694588 WL = 0x5
7154 14:44:19.697377 RL = 0x5
7155 14:44:19.697499 BL = 0x2
7156 14:44:19.700974 RPST = 0x0
7157 14:44:19.701096 RD_PRE = 0x0
7158 14:44:19.704407 WR_PRE = 0x1
7159 14:44:19.704526 WR_PST = 0x1
7160 14:44:19.707588 DBI_WR = 0x0
7161 14:44:19.707708 DBI_RD = 0x0
7162 14:44:19.710898 OTF = 0x1
7163 14:44:19.713932 ===================================
7164 14:44:19.717254 ===================================
7165 14:44:19.717379 ANA top config
7166 14:44:19.720896 ===================================
7167 14:44:19.724193 DLL_ASYNC_EN = 0
7168 14:44:19.727536 ALL_SLAVE_EN = 0
7169 14:44:19.730806 NEW_RANK_MODE = 1
7170 14:44:19.730930 DLL_IDLE_MODE = 1
7171 14:44:19.733871 LP45_APHY_COMB_EN = 1
7172 14:44:19.737160 TX_ODT_DIS = 0
7173 14:44:19.740583 NEW_8X_MODE = 1
7174 14:44:19.744056 ===================================
7175 14:44:19.747328 ===================================
7176 14:44:19.750386 data_rate = 3200
7177 14:44:19.750478 CKR = 1
7178 14:44:19.753851 DQ_P2S_RATIO = 8
7179 14:44:19.757117 ===================================
7180 14:44:19.760368 CA_P2S_RATIO = 8
7181 14:44:19.763725 DQ_CA_OPEN = 0
7182 14:44:19.767553 DQ_SEMI_OPEN = 0
7183 14:44:19.767638 CA_SEMI_OPEN = 0
7184 14:44:19.770640 CA_FULL_RATE = 0
7185 14:44:19.774006 DQ_CKDIV4_EN = 0
7186 14:44:19.777155 CA_CKDIV4_EN = 0
7187 14:44:19.780458 CA_PREDIV_EN = 0
7188 14:44:19.783971 PH8_DLY = 12
7189 14:44:19.784053 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7190 14:44:19.787088 DQ_AAMCK_DIV = 4
7191 14:44:19.790280 CA_AAMCK_DIV = 4
7192 14:44:19.793720 CA_ADMCK_DIV = 4
7193 14:44:19.797120 DQ_TRACK_CA_EN = 0
7194 14:44:19.800627 CA_PICK = 1600
7195 14:44:19.804149 CA_MCKIO = 1600
7196 14:44:19.804230 MCKIO_SEMI = 0
7197 14:44:19.807191 PLL_FREQ = 3068
7198 14:44:19.810329 DQ_UI_PI_RATIO = 32
7199 14:44:19.813727 CA_UI_PI_RATIO = 0
7200 14:44:19.816956 ===================================
7201 14:44:19.820169 ===================================
7202 14:44:19.823858 memory_type:LPDDR4
7203 14:44:19.823937 GP_NUM : 10
7204 14:44:19.827174 SRAM_EN : 1
7205 14:44:19.830189 MD32_EN : 0
7206 14:44:19.833596 ===================================
7207 14:44:19.833679 [ANA_INIT] >>>>>>>>>>>>>>
7208 14:44:19.836939 <<<<<< [CONFIGURE PHASE]: ANA_TX
7209 14:44:19.839739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7210 14:44:19.843295 ===================================
7211 14:44:19.846716 data_rate = 3200,PCW = 0X7600
7212 14:44:19.850263 ===================================
7213 14:44:19.853652 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7214 14:44:19.859754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7215 14:44:19.863236 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7216 14:44:19.869679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7217 14:44:19.873442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7218 14:44:19.876820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7219 14:44:19.879532 [ANA_INIT] flow start
7220 14:44:19.879614 [ANA_INIT] PLL >>>>>>>>
7221 14:44:19.883065 [ANA_INIT] PLL <<<<<<<<
7222 14:44:19.886115 [ANA_INIT] MIDPI >>>>>>>>
7223 14:44:19.886224 [ANA_INIT] MIDPI <<<<<<<<
7224 14:44:19.889479 [ANA_INIT] DLL >>>>>>>>
7225 14:44:19.893075 [ANA_INIT] DLL <<<<<<<<
7226 14:44:19.893186 [ANA_INIT] flow end
7227 14:44:19.899187 ============ LP4 DIFF to SE enter ============
7228 14:44:19.902824 ============ LP4 DIFF to SE exit ============
7229 14:44:19.906158 [ANA_INIT] <<<<<<<<<<<<<
7230 14:44:19.909181 [Flow] Enable top DCM control >>>>>
7231 14:44:19.912715 [Flow] Enable top DCM control <<<<<
7232 14:44:19.912857 Enable DLL master slave shuffle
7233 14:44:19.919470 ==============================================================
7234 14:44:19.922304 Gating Mode config
7235 14:44:19.925611 ==============================================================
7236 14:44:19.929382 Config description:
7237 14:44:19.938857 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7238 14:44:19.945797 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7239 14:44:19.949132 SELPH_MODE 0: By rank 1: By Phase
7240 14:44:19.955907 ==============================================================
7241 14:44:19.958912 GAT_TRACK_EN = 1
7242 14:44:19.962123 RX_GATING_MODE = 2
7243 14:44:19.965272 RX_GATING_TRACK_MODE = 2
7244 14:44:19.968724 SELPH_MODE = 1
7245 14:44:19.972310 PICG_EARLY_EN = 1
7246 14:44:19.972457 VALID_LAT_VALUE = 1
7247 14:44:19.979180 ==============================================================
7248 14:44:19.981922 Enter into Gating configuration >>>>
7249 14:44:19.985216 Exit from Gating configuration <<<<
7250 14:44:19.988876 Enter into DVFS_PRE_config >>>>>
7251 14:44:19.998611 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7252 14:44:20.002094 Exit from DVFS_PRE_config <<<<<
7253 14:44:20.005327 Enter into PICG configuration >>>>
7254 14:44:20.008238 Exit from PICG configuration <<<<
7255 14:44:20.011547 [RX_INPUT] configuration >>>>>
7256 14:44:20.014860 [RX_INPUT] configuration <<<<<
7257 14:44:20.021611 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7258 14:44:20.024544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7259 14:44:20.031318 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7260 14:44:20.037791 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7261 14:44:20.044655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7262 14:44:20.051345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7263 14:44:20.054459 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7264 14:44:20.057948 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7265 14:44:20.060820 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7266 14:44:20.067789 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7267 14:44:20.071375 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7268 14:44:20.074791 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7269 14:44:20.077567 ===================================
7270 14:44:20.081193 LPDDR4 DRAM CONFIGURATION
7271 14:44:20.084578 ===================================
7272 14:44:20.084689 EX_ROW_EN[0] = 0x0
7273 14:44:20.087372 EX_ROW_EN[1] = 0x0
7274 14:44:20.090640 LP4Y_EN = 0x0
7275 14:44:20.090724 WORK_FSP = 0x1
7276 14:44:20.094000 WL = 0x5
7277 14:44:20.094083 RL = 0x5
7278 14:44:20.097350 BL = 0x2
7279 14:44:20.097463 RPST = 0x0
7280 14:44:20.100762 RD_PRE = 0x0
7281 14:44:20.100842 WR_PRE = 0x1
7282 14:44:20.104034 WR_PST = 0x1
7283 14:44:20.104105 DBI_WR = 0x0
7284 14:44:20.107072 DBI_RD = 0x0
7285 14:44:20.107146 OTF = 0x1
7286 14:44:20.110630 ===================================
7287 14:44:20.117437 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7288 14:44:20.120200 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7289 14:44:20.124034 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7290 14:44:20.127075 ===================================
7291 14:44:20.130367 LPDDR4 DRAM CONFIGURATION
7292 14:44:20.133934 ===================================
7293 14:44:20.136745 EX_ROW_EN[0] = 0x10
7294 14:44:20.136818 EX_ROW_EN[1] = 0x0
7295 14:44:20.140243 LP4Y_EN = 0x0
7296 14:44:20.140311 WORK_FSP = 0x1
7297 14:44:20.143827 WL = 0x5
7298 14:44:20.143909 RL = 0x5
7299 14:44:20.147067 BL = 0x2
7300 14:44:20.147146 RPST = 0x0
7301 14:44:20.150205 RD_PRE = 0x0
7302 14:44:20.150279 WR_PRE = 0x1
7303 14:44:20.153487 WR_PST = 0x1
7304 14:44:20.153572 DBI_WR = 0x0
7305 14:44:20.156497 DBI_RD = 0x0
7306 14:44:20.156606 OTF = 0x1
7307 14:44:20.160292 ===================================
7308 14:44:20.166564 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7309 14:44:20.166649 ==
7310 14:44:20.169921 Dram Type= 6, Freq= 0, CH_0, rank 0
7311 14:44:20.176787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7312 14:44:20.176871 ==
7313 14:44:20.176938 [Duty_Offset_Calibration]
7314 14:44:20.180076 B0:2 B1:0 CA:3
7315 14:44:20.180160
7316 14:44:20.183121 [DutyScan_Calibration_Flow] k_type=0
7317 14:44:20.192705
7318 14:44:20.192789 ==CLK 0==
7319 14:44:20.195532 Final CLK duty delay cell = 0
7320 14:44:20.199014 [0] MAX Duty = 5031%(X100), DQS PI = 12
7321 14:44:20.202153 [0] MIN Duty = 4907%(X100), DQS PI = 4
7322 14:44:20.202236 [0] AVG Duty = 4969%(X100)
7323 14:44:20.205518
7324 14:44:20.208721 CH0 CLK Duty spec in!! Max-Min= 124%
7325 14:44:20.212062 [DutyScan_Calibration_Flow] ====Done====
7326 14:44:20.212147
7327 14:44:20.215063 [DutyScan_Calibration_Flow] k_type=1
7328 14:44:20.232094
7329 14:44:20.232178 ==DQS 0 ==
7330 14:44:20.235429 Final DQS duty delay cell = 0
7331 14:44:20.238732 [0] MAX Duty = 5094%(X100), DQS PI = 28
7332 14:44:20.242164 [0] MIN Duty = 4875%(X100), DQS PI = 48
7333 14:44:20.245136 [0] AVG Duty = 4984%(X100)
7334 14:44:20.245222
7335 14:44:20.245309 ==DQS 1 ==
7336 14:44:20.248432 Final DQS duty delay cell = 0
7337 14:44:20.251867 [0] MAX Duty = 5156%(X100), DQS PI = 30
7338 14:44:20.255128 [0] MIN Duty = 5031%(X100), DQS PI = 12
7339 14:44:20.258778 [0] AVG Duty = 5093%(X100)
7340 14:44:20.258864
7341 14:44:20.261981 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7342 14:44:20.262091
7343 14:44:20.265233 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7344 14:44:20.268417 [DutyScan_Calibration_Flow] ====Done====
7345 14:44:20.268531
7346 14:44:20.271903 [DutyScan_Calibration_Flow] k_type=3
7347 14:44:20.290058
7348 14:44:20.290143 ==DQM 0 ==
7349 14:44:20.293647 Final DQM duty delay cell = 0
7350 14:44:20.296349 [0] MAX Duty = 5156%(X100), DQS PI = 30
7351 14:44:20.299715 [0] MIN Duty = 4844%(X100), DQS PI = 48
7352 14:44:20.303222 [0] AVG Duty = 5000%(X100)
7353 14:44:20.303309
7354 14:44:20.303393 ==DQM 1 ==
7355 14:44:20.306676 Final DQM duty delay cell = 4
7356 14:44:20.309589 [4] MAX Duty = 5187%(X100), DQS PI = 62
7357 14:44:20.313025 [4] MIN Duty = 5000%(X100), DQS PI = 12
7358 14:44:20.316840 [4] AVG Duty = 5093%(X100)
7359 14:44:20.316920
7360 14:44:20.319521 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7361 14:44:20.319635
7362 14:44:20.323304 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7363 14:44:20.326337 [DutyScan_Calibration_Flow] ====Done====
7364 14:44:20.326419
7365 14:44:20.329717 [DutyScan_Calibration_Flow] k_type=2
7366 14:44:20.345930
7367 14:44:20.346035 ==DQ 0 ==
7368 14:44:20.349351 Final DQ duty delay cell = -4
7369 14:44:20.352728 [-4] MAX Duty = 5000%(X100), DQS PI = 12
7370 14:44:20.356056 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7371 14:44:20.359401 [-4] AVG Duty = 4938%(X100)
7372 14:44:20.359479
7373 14:44:20.359544 ==DQ 1 ==
7374 14:44:20.363044 Final DQ duty delay cell = 0
7375 14:44:20.365932 [0] MAX Duty = 5156%(X100), DQS PI = 58
7376 14:44:20.369127 [0] MIN Duty = 5000%(X100), DQS PI = 16
7377 14:44:20.372691 [0] AVG Duty = 5078%(X100)
7378 14:44:20.372790
7379 14:44:20.375885 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7380 14:44:20.375965
7381 14:44:20.379183 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7382 14:44:20.382568 [DutyScan_Calibration_Flow] ====Done====
7383 14:44:20.382649 ==
7384 14:44:20.386152 Dram Type= 6, Freq= 0, CH_1, rank 0
7385 14:44:20.389398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7386 14:44:20.389507 ==
7387 14:44:20.392644 [Duty_Offset_Calibration]
7388 14:44:20.392752 B0:1 B1:-2 CA:1
7389 14:44:20.392845
7390 14:44:20.396074 [DutyScan_Calibration_Flow] k_type=0
7391 14:44:20.406537
7392 14:44:20.406646 ==CLK 0==
7393 14:44:20.409961 Final CLK duty delay cell = 0
7394 14:44:20.413385 [0] MAX Duty = 5031%(X100), DQS PI = 52
7395 14:44:20.416346 [0] MIN Duty = 4906%(X100), DQS PI = 22
7396 14:44:20.419697 [0] AVG Duty = 4968%(X100)
7397 14:44:20.419806
7398 14:44:20.423138 CH1 CLK Duty spec in!! Max-Min= 125%
7399 14:44:20.426274 [DutyScan_Calibration_Flow] ====Done====
7400 14:44:20.426356
7401 14:44:20.429970 [DutyScan_Calibration_Flow] k_type=1
7402 14:44:20.445702
7403 14:44:20.445822 ==DQS 0 ==
7404 14:44:20.448695 Final DQS duty delay cell = -4
7405 14:44:20.451882 [-4] MAX Duty = 4938%(X100), DQS PI = 56
7406 14:44:20.455222 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7407 14:44:20.458882 [-4] AVG Duty = 4891%(X100)
7408 14:44:20.458985
7409 14:44:20.459078 ==DQS 1 ==
7410 14:44:20.461739 Final DQS duty delay cell = 0
7411 14:44:20.465486 [0] MAX Duty = 5156%(X100), DQS PI = 30
7412 14:44:20.468658 [0] MIN Duty = 4844%(X100), DQS PI = 56
7413 14:44:20.472208 [0] AVG Duty = 5000%(X100)
7414 14:44:20.472311
7415 14:44:20.475459 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7416 14:44:20.475569
7417 14:44:20.478657 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7418 14:44:20.481804 [DutyScan_Calibration_Flow] ====Done====
7419 14:44:20.481887
7420 14:44:20.485152 [DutyScan_Calibration_Flow] k_type=3
7421 14:44:20.502406
7422 14:44:20.502506 ==DQM 0 ==
7423 14:44:20.506200 Final DQM duty delay cell = 0
7424 14:44:20.509013 [0] MAX Duty = 5031%(X100), DQS PI = 60
7425 14:44:20.512821 [0] MIN Duty = 4844%(X100), DQS PI = 22
7426 14:44:20.515597 [0] AVG Duty = 4937%(X100)
7427 14:44:20.515679
7428 14:44:20.515743 ==DQM 1 ==
7429 14:44:20.519213 Final DQM duty delay cell = 0
7430 14:44:20.522690 [0] MAX Duty = 5062%(X100), DQS PI = 4
7431 14:44:20.525677 [0] MIN Duty = 4875%(X100), DQS PI = 36
7432 14:44:20.528916 [0] AVG Duty = 4968%(X100)
7433 14:44:20.528998
7434 14:44:20.532849 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7435 14:44:20.532931
7436 14:44:20.536157 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7437 14:44:20.538882 [DutyScan_Calibration_Flow] ====Done====
7438 14:44:20.538965
7439 14:44:20.542541 [DutyScan_Calibration_Flow] k_type=2
7440 14:44:20.559598
7441 14:44:20.559713 ==DQ 0 ==
7442 14:44:20.562612 Final DQ duty delay cell = 0
7443 14:44:20.566113 [0] MAX Duty = 5093%(X100), DQS PI = 62
7444 14:44:20.569372 [0] MIN Duty = 4938%(X100), DQS PI = 14
7445 14:44:20.569455 [0] AVG Duty = 5015%(X100)
7446 14:44:20.572768
7447 14:44:20.572850 ==DQ 1 ==
7448 14:44:20.576027 Final DQ duty delay cell = 0
7449 14:44:20.579076 [0] MAX Duty = 5156%(X100), DQS PI = 26
7450 14:44:20.582556 [0] MIN Duty = 4907%(X100), DQS PI = 56
7451 14:44:20.582639 [0] AVG Duty = 5031%(X100)
7452 14:44:20.585930
7453 14:44:20.589000 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7454 14:44:20.589081
7455 14:44:20.592568 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7456 14:44:20.595883 [DutyScan_Calibration_Flow] ====Done====
7457 14:44:20.599219 nWR fixed to 30
7458 14:44:20.599300 [ModeRegInit_LP4] CH0 RK0
7459 14:44:20.602264 [ModeRegInit_LP4] CH0 RK1
7460 14:44:20.605559 [ModeRegInit_LP4] CH1 RK0
7461 14:44:20.608977 [ModeRegInit_LP4] CH1 RK1
7462 14:44:20.609059 match AC timing 5
7463 14:44:20.615806 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7464 14:44:20.619159 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7465 14:44:20.622170 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7466 14:44:20.629060 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7467 14:44:20.632331 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7468 14:44:20.632413 [MiockJmeterHQA]
7469 14:44:20.632477
7470 14:44:20.635738 [DramcMiockJmeter] u1RxGatingPI = 0
7471 14:44:20.638929 0 : 4368, 4140
7472 14:44:20.639007 4 : 4366, 4140
7473 14:44:20.642610 8 : 4257, 4030
7474 14:44:20.642722 12 : 4366, 4140
7475 14:44:20.642828 16 : 4258, 4029
7476 14:44:20.645547 20 : 4257, 4029
7477 14:44:20.645687 24 : 4260, 4031
7478 14:44:20.648777 28 : 4257, 4029
7479 14:44:20.648942 32 : 4252, 4027
7480 14:44:20.652158 36 : 4259, 4032
7481 14:44:20.652283 40 : 4257, 4029
7482 14:44:20.655261 44 : 4258, 4029
7483 14:44:20.655387 48 : 4258, 4030
7484 14:44:20.655503 52 : 4257, 4029
7485 14:44:20.658671 56 : 4370, 4142
7486 14:44:20.658758 60 : 4254, 4029
7487 14:44:20.662182 64 : 4255, 4029
7488 14:44:20.662310 68 : 4258, 4029
7489 14:44:20.665710 72 : 4255, 4029
7490 14:44:20.665834 76 : 4258, 4031
7491 14:44:20.668525 80 : 4255, 4029
7492 14:44:20.668704 84 : 4252, 4030
7493 14:44:20.668824 88 : 4255, 4029
7494 14:44:20.672100 92 : 4250, 4027
7495 14:44:20.672242 96 : 4255, 4030
7496 14:44:20.675026 100 : 4252, 4030
7497 14:44:20.675163 104 : 4250, 3394
7498 14:44:20.678275 108 : 4255, 0
7499 14:44:20.678400 112 : 4252, 0
7500 14:44:20.678504 116 : 4255, 0
7501 14:44:20.681699 120 : 4253, 0
7502 14:44:20.681781 124 : 4253, 0
7503 14:44:20.685319 128 : 4252, 0
7504 14:44:20.685402 132 : 4252, 0
7505 14:44:20.685468 136 : 4252, 0
7506 14:44:20.688293 140 : 4252, 0
7507 14:44:20.688376 144 : 4257, 0
7508 14:44:20.691896 148 : 4252, 0
7509 14:44:20.692006 152 : 4255, 0
7510 14:44:20.692100 156 : 4257, 0
7511 14:44:20.695138 160 : 4252, 0
7512 14:44:20.695221 164 : 4252, 0
7513 14:44:20.695286 168 : 4255, 0
7514 14:44:20.698490 172 : 4253, 0
7515 14:44:20.698597 176 : 4255, 0
7516 14:44:20.701870 180 : 4365, 0
7517 14:44:20.701990 184 : 4252, 0
7518 14:44:20.702078 188 : 4363, 0
7519 14:44:20.704886 192 : 4255, 0
7520 14:44:20.704972 196 : 4255, 0
7521 14:44:20.708180 200 : 4363, 0
7522 14:44:20.708281 204 : 4250, 0
7523 14:44:20.708382 208 : 4252, 0
7524 14:44:20.711682 212 : 4363, 0
7525 14:44:20.711768 216 : 4255, 0
7526 14:44:20.714975 220 : 4363, 0
7527 14:44:20.715060 224 : 4255, 0
7528 14:44:20.715148 228 : 4253, 0
7529 14:44:20.718317 232 : 4368, 0
7530 14:44:20.718402 236 : 4252, 952
7531 14:44:20.721714 240 : 4255, 4029
7532 14:44:20.721800 244 : 4366, 4140
7533 14:44:20.725241 248 : 4253, 4029
7534 14:44:20.725327 252 : 4255, 4029
7535 14:44:20.725414 256 : 4252, 4030
7536 14:44:20.728547 260 : 4366, 4140
7537 14:44:20.728680 264 : 4254, 4029
7538 14:44:20.731523 268 : 4252, 4029
7539 14:44:20.731615 272 : 4255, 4029
7540 14:44:20.735068 276 : 4363, 4140
7541 14:44:20.735233 280 : 4363, 4140
7542 14:44:20.737956 284 : 4365, 4139
7543 14:44:20.738080 288 : 4247, 4025
7544 14:44:20.741338 292 : 4252, 4030
7545 14:44:20.741459 296 : 4366, 4140
7546 14:44:20.744829 300 : 4364, 4140
7547 14:44:20.744962 304 : 4253, 4027
7548 14:44:20.748159 308 : 4368, 4142
7549 14:44:20.748276 312 : 4253, 4029
7550 14:44:20.751518 316 : 4365, 4140
7551 14:44:20.751642 320 : 4253, 4029
7552 14:44:20.751749 324 : 4252, 4030
7553 14:44:20.754852 328 : 4255, 4030
7554 14:44:20.755043 332 : 4254, 4029
7555 14:44:20.757844 336 : 4254, 4030
7556 14:44:20.757968 340 : 4255, 4029
7557 14:44:20.761261 344 : 4255, 4030
7558 14:44:20.761386 348 : 4255, 4029
7559 14:44:20.764732 352 : 4252, 4016
7560 14:44:20.764863 356 : 4258, 2818
7561 14:44:20.767853 360 : 4252, 1
7562 14:44:20.767979
7563 14:44:20.768090 MIOCK jitter meter ch=0
7564 14:44:20.768200
7565 14:44:20.771243 1T = (360-108) = 252 dly cells
7566 14:44:20.777884 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7567 14:44:20.778018 ==
7568 14:44:20.780980 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 14:44:20.784436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 14:44:20.784551 ==
7571 14:44:20.790966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7572 14:44:20.793934 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7573 14:44:20.801088 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7574 14:44:20.804036 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7575 14:44:20.814072 [CA 0] Center 44 (14~75) winsize 62
7576 14:44:20.817270 [CA 1] Center 43 (13~74) winsize 62
7577 14:44:20.821281 [CA 2] Center 40 (11~69) winsize 59
7578 14:44:20.824512 [CA 3] Center 39 (10~68) winsize 59
7579 14:44:20.827397 [CA 4] Center 37 (8~67) winsize 60
7580 14:44:20.830798 [CA 5] Center 37 (7~67) winsize 61
7581 14:44:20.830921
7582 14:44:20.834274 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7583 14:44:20.834397
7584 14:44:20.837508 [CATrainingPosCal] consider 1 rank data
7585 14:44:20.840847 u2DelayCellTimex100 = 258/100 ps
7586 14:44:20.847546 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7587 14:44:20.850528 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7588 14:44:20.854546 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7589 14:44:20.857317 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7590 14:44:20.860722 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7591 14:44:20.863769 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7592 14:44:20.863851
7593 14:44:20.867114 CA PerBit enable=1, Macro0, CA PI delay=37
7594 14:44:20.867197
7595 14:44:20.870499 [CBTSetCACLKResult] CA Dly = 37
7596 14:44:20.873950 CS Dly: 11 (0~42)
7597 14:44:20.877310 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7598 14:44:20.880700 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7599 14:44:20.880811 ==
7600 14:44:20.883525 Dram Type= 6, Freq= 0, CH_0, rank 1
7601 14:44:20.890227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 14:44:20.890340 ==
7603 14:44:20.893706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7604 14:44:20.900468 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7605 14:44:20.903554 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7606 14:44:20.909929 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7607 14:44:20.918339 [CA 0] Center 44 (14~74) winsize 61
7608 14:44:20.921608 [CA 1] Center 43 (13~74) winsize 62
7609 14:44:20.924760 [CA 2] Center 39 (10~68) winsize 59
7610 14:44:20.928053 [CA 3] Center 39 (10~68) winsize 59
7611 14:44:20.931457 [CA 4] Center 37 (8~66) winsize 59
7612 14:44:20.934781 [CA 5] Center 36 (7~66) winsize 60
7613 14:44:20.934863
7614 14:44:20.937987 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7615 14:44:20.938071
7616 14:44:20.944400 [CATrainingPosCal] consider 2 rank data
7617 14:44:20.944489 u2DelayCellTimex100 = 258/100 ps
7618 14:44:20.951172 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7619 14:44:20.954549 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7620 14:44:20.958186 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7621 14:44:20.960964 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7622 14:44:20.964330 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7623 14:44:20.967317 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7624 14:44:20.967395
7625 14:44:20.970798 CA PerBit enable=1, Macro0, CA PI delay=36
7626 14:44:20.970896
7627 14:44:20.974341 [CBTSetCACLKResult] CA Dly = 36
7628 14:44:20.977609 CS Dly: 11 (0~43)
7629 14:44:20.981085 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7630 14:44:20.983869 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7631 14:44:20.983946
7632 14:44:20.987303 ----->DramcWriteLeveling(PI) begin...
7633 14:44:20.991089 ==
7634 14:44:20.991164 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 14:44:20.997503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 14:44:20.997591 ==
7637 14:44:21.001132 Write leveling (Byte 0): 36 => 36
7638 14:44:21.004374 Write leveling (Byte 1): 29 => 29
7639 14:44:21.007205 DramcWriteLeveling(PI) end<-----
7640 14:44:21.007307
7641 14:44:21.007399 ==
7642 14:44:21.010643 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 14:44:21.014073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 14:44:21.014149 ==
7645 14:44:21.017016 [Gating] SW mode calibration
7646 14:44:21.023867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7647 14:44:21.030631 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7648 14:44:21.034137 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 14:44:21.037330 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 14:44:21.044036 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 14:44:21.047055 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 14:44:21.050175 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7653 14:44:21.056727 1 4 20 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
7654 14:44:21.060144 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7655 14:44:21.063613 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7656 14:44:21.070121 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7657 14:44:21.073525 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 14:44:21.076849 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 14:44:21.083496 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 14:44:21.086818 1 5 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7661 14:44:21.090268 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7662 14:44:21.096348 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7663 14:44:21.099599 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 14:44:21.103255 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 14:44:21.109534 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 14:44:21.112968 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 14:44:21.116368 1 6 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7668 14:44:21.122741 1 6 16 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7669 14:44:21.126291 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
7670 14:44:21.129478 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7671 14:44:21.133114 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 14:44:21.139667 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 14:44:21.142679 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 14:44:21.146083 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 14:44:21.152784 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 14:44:21.155944 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7677 14:44:21.158951 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7678 14:44:21.165725 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7679 14:44:21.168939 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 14:44:21.172856 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 14:44:21.179186 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 14:44:21.182559 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 14:44:21.185706 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 14:44:21.192694 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 14:44:21.195404 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 14:44:21.198723 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 14:44:21.205459 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 14:44:21.209000 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 14:44:21.212333 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 14:44:21.218389 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 14:44:21.222425 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7692 14:44:21.225052 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7693 14:44:21.231872 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7694 14:44:21.235411 Total UI for P1: 0, mck2ui 16
7695 14:44:21.238904 best dqsien dly found for B0: ( 1, 9, 14)
7696 14:44:21.242007 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7697 14:44:21.245392 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7698 14:44:21.248418 Total UI for P1: 0, mck2ui 16
7699 14:44:21.251627 best dqsien dly found for B1: ( 1, 9, 24)
7700 14:44:21.255289 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7701 14:44:21.258601 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7702 14:44:21.258678
7703 14:44:21.265026 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7704 14:44:21.268236 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7705 14:44:21.271853 [Gating] SW calibration Done
7706 14:44:21.271927 ==
7707 14:44:21.274881 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 14:44:21.278387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 14:44:21.278463 ==
7710 14:44:21.278526 RX Vref Scan: 0
7711 14:44:21.281656
7712 14:44:21.281768 RX Vref 0 -> 0, step: 1
7713 14:44:21.281864
7714 14:44:21.285111 RX Delay 0 -> 252, step: 8
7715 14:44:21.288141 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7716 14:44:21.291623 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7717 14:44:21.298147 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7718 14:44:21.301505 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7719 14:44:21.305046 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7720 14:44:21.308095 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7721 14:44:21.311791 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7722 14:44:21.318170 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7723 14:44:21.321572 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7724 14:44:21.324815 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7725 14:44:21.328197 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7726 14:44:21.331671 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7727 14:44:21.337828 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7728 14:44:21.341255 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7729 14:44:21.344648 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7730 14:44:21.348059 iDelay=192, Bit 15, Center 127 (72 ~ 183) 112
7731 14:44:21.348167 ==
7732 14:44:21.351505 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 14:44:21.358172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 14:44:21.358257 ==
7735 14:44:21.358321 DQS Delay:
7736 14:44:21.361296 DQS0 = 0, DQS1 = 0
7737 14:44:21.361376 DQM Delay:
7738 14:44:21.361440 DQM0 = 128, DQM1 = 123
7739 14:44:21.364269 DQ Delay:
7740 14:44:21.367916 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7741 14:44:21.371143 DQ4 =127, DQ5 =115, DQ6 =135, DQ7 =139
7742 14:44:21.374746 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7743 14:44:21.378101 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7744 14:44:21.378178
7745 14:44:21.378249
7746 14:44:21.378310 ==
7747 14:44:21.380867 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 14:44:21.384652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 14:44:21.387814 ==
7750 14:44:21.387886
7751 14:44:21.387961
7752 14:44:21.388052 TX Vref Scan disable
7753 14:44:21.390965 == TX Byte 0 ==
7754 14:44:21.394187 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7755 14:44:21.397734 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7756 14:44:21.400934 == TX Byte 1 ==
7757 14:44:21.404341 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7758 14:44:21.407398 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7759 14:44:21.410673 ==
7760 14:44:21.414124 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 14:44:21.417426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 14:44:21.417509 ==
7763 14:44:21.430539
7764 14:44:21.434128 TX Vref early break, caculate TX vref
7765 14:44:21.436975 TX Vref=16, minBit 8, minWin=21, winSum=358
7766 14:44:21.440388 TX Vref=18, minBit 8, minWin=22, winSum=374
7767 14:44:21.443657 TX Vref=20, minBit 8, minWin=23, winSum=385
7768 14:44:21.446992 TX Vref=22, minBit 4, minWin=24, winSum=392
7769 14:44:21.450276 TX Vref=24, minBit 8, minWin=24, winSum=405
7770 14:44:21.456719 TX Vref=26, minBit 3, minWin=25, winSum=408
7771 14:44:21.460085 TX Vref=28, minBit 10, minWin=24, winSum=406
7772 14:44:21.463586 TX Vref=30, minBit 8, minWin=24, winSum=402
7773 14:44:21.466855 TX Vref=32, minBit 8, minWin=23, winSum=397
7774 14:44:21.470159 TX Vref=34, minBit 8, minWin=21, winSum=386
7775 14:44:21.476867 [TxChooseVref] Worse bit 3, Min win 25, Win sum 408, Final Vref 26
7776 14:44:21.476952
7777 14:44:21.480150 Final TX Range 0 Vref 26
7778 14:44:21.480235
7779 14:44:21.480301 ==
7780 14:44:21.483749 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 14:44:21.487222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 14:44:21.487309 ==
7783 14:44:21.487376
7784 14:44:21.487437
7785 14:44:21.490281 TX Vref Scan disable
7786 14:44:21.496931 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7787 14:44:21.497066 == TX Byte 0 ==
7788 14:44:21.500363 u2DelayCellOfst[0]=15 cells (4 PI)
7789 14:44:21.503553 u2DelayCellOfst[1]=18 cells (5 PI)
7790 14:44:21.506441 u2DelayCellOfst[2]=15 cells (4 PI)
7791 14:44:21.509968 u2DelayCellOfst[3]=15 cells (4 PI)
7792 14:44:21.513342 u2DelayCellOfst[4]=11 cells (3 PI)
7793 14:44:21.516387 u2DelayCellOfst[5]=0 cells (0 PI)
7794 14:44:21.520131 u2DelayCellOfst[6]=18 cells (5 PI)
7795 14:44:21.523661 u2DelayCellOfst[7]=18 cells (5 PI)
7796 14:44:21.526530 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7797 14:44:21.529853 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7798 14:44:21.533314 == TX Byte 1 ==
7799 14:44:21.533398 u2DelayCellOfst[8]=0 cells (0 PI)
7800 14:44:21.536892 u2DelayCellOfst[9]=3 cells (1 PI)
7801 14:44:21.539776 u2DelayCellOfst[10]=7 cells (2 PI)
7802 14:44:21.543264 u2DelayCellOfst[11]=3 cells (1 PI)
7803 14:44:21.546585 u2DelayCellOfst[12]=11 cells (3 PI)
7804 14:44:21.550252 u2DelayCellOfst[13]=11 cells (3 PI)
7805 14:44:21.552973 u2DelayCellOfst[14]=15 cells (4 PI)
7806 14:44:21.556319 u2DelayCellOfst[15]=11 cells (3 PI)
7807 14:44:21.559927 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7808 14:44:21.566347 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7809 14:44:21.566458 DramC Write-DBI on
7810 14:44:21.566559 ==
7811 14:44:21.569658 Dram Type= 6, Freq= 0, CH_0, rank 0
7812 14:44:21.576596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7813 14:44:21.576684 ==
7814 14:44:21.576752
7815 14:44:21.576814
7816 14:44:21.576873 TX Vref Scan disable
7817 14:44:21.579825 == TX Byte 0 ==
7818 14:44:21.583305 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7819 14:44:21.586552 == TX Byte 1 ==
7820 14:44:21.590159 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7821 14:44:21.593387 DramC Write-DBI off
7822 14:44:21.593470
7823 14:44:21.593535 [DATLAT]
7824 14:44:21.593597 Freq=1600, CH0 RK0
7825 14:44:21.593657
7826 14:44:21.597002 DATLAT Default: 0xf
7827 14:44:21.599814 0, 0xFFFF, sum = 0
7828 14:44:21.599929 1, 0xFFFF, sum = 0
7829 14:44:21.603128 2, 0xFFFF, sum = 0
7830 14:44:21.603239 3, 0xFFFF, sum = 0
7831 14:44:21.606538 4, 0xFFFF, sum = 0
7832 14:44:21.606651 5, 0xFFFF, sum = 0
7833 14:44:21.609769 6, 0xFFFF, sum = 0
7834 14:44:21.609855 7, 0xFFFF, sum = 0
7835 14:44:21.612938 8, 0xFFFF, sum = 0
7836 14:44:21.613019 9, 0xFFFF, sum = 0
7837 14:44:21.616350 10, 0xFFFF, sum = 0
7838 14:44:21.616451 11, 0xFFFF, sum = 0
7839 14:44:21.619664 12, 0xFFFF, sum = 0
7840 14:44:21.619769 13, 0xEFFF, sum = 0
7841 14:44:21.623198 14, 0x0, sum = 1
7842 14:44:21.623269 15, 0x0, sum = 2
7843 14:44:21.626138 16, 0x0, sum = 3
7844 14:44:21.626220 17, 0x0, sum = 4
7845 14:44:21.629633 best_step = 15
7846 14:44:21.629740
7847 14:44:21.629852 ==
7848 14:44:21.632800 Dram Type= 6, Freq= 0, CH_0, rank 0
7849 14:44:21.636208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7850 14:44:21.636296 ==
7851 14:44:21.639588 RX Vref Scan: 1
7852 14:44:21.639671
7853 14:44:21.639736 Set Vref Range= 24 -> 127
7854 14:44:21.639797
7855 14:44:21.642517 RX Vref 24 -> 127, step: 1
7856 14:44:21.642630
7857 14:44:21.646492 RX Delay 11 -> 252, step: 4
7858 14:44:21.646575
7859 14:44:21.649337 Set Vref, RX VrefLevel [Byte0]: 24
7860 14:44:21.652839 [Byte1]: 24
7861 14:44:21.652974
7862 14:44:21.655807 Set Vref, RX VrefLevel [Byte0]: 25
7863 14:44:21.659377 [Byte1]: 25
7864 14:44:21.662713
7865 14:44:21.662847 Set Vref, RX VrefLevel [Byte0]: 26
7866 14:44:21.666221 [Byte1]: 26
7867 14:44:21.670521
7868 14:44:21.670645 Set Vref, RX VrefLevel [Byte0]: 27
7869 14:44:21.673870 [Byte1]: 27
7870 14:44:21.678334
7871 14:44:21.678457 Set Vref, RX VrefLevel [Byte0]: 28
7872 14:44:21.681280 [Byte1]: 28
7873 14:44:21.685868
7874 14:44:21.685989 Set Vref, RX VrefLevel [Byte0]: 29
7875 14:44:21.689178 [Byte1]: 29
7876 14:44:21.693513
7877 14:44:21.693644 Set Vref, RX VrefLevel [Byte0]: 30
7878 14:44:21.696667 [Byte1]: 30
7879 14:44:21.700898
7880 14:44:21.701006 Set Vref, RX VrefLevel [Byte0]: 31
7881 14:44:21.704326 [Byte1]: 31
7882 14:44:21.708524
7883 14:44:21.708616 Set Vref, RX VrefLevel [Byte0]: 32
7884 14:44:21.712239 [Byte1]: 32
7885 14:44:21.715936
7886 14:44:21.716046 Set Vref, RX VrefLevel [Byte0]: 33
7887 14:44:21.719255 [Byte1]: 33
7888 14:44:21.723794
7889 14:44:21.723921 Set Vref, RX VrefLevel [Byte0]: 34
7890 14:44:21.727434 [Byte1]: 34
7891 14:44:21.731516
7892 14:44:21.731634 Set Vref, RX VrefLevel [Byte0]: 35
7893 14:44:21.734592 [Byte1]: 35
7894 14:44:21.738735
7895 14:44:21.738855 Set Vref, RX VrefLevel [Byte0]: 36
7896 14:44:21.742334 [Byte1]: 36
7897 14:44:21.746516
7898 14:44:21.746623 Set Vref, RX VrefLevel [Byte0]: 37
7899 14:44:21.749960 [Byte1]: 37
7900 14:44:21.754081
7901 14:44:21.754163 Set Vref, RX VrefLevel [Byte0]: 38
7902 14:44:21.757342 [Byte1]: 38
7903 14:44:21.762095
7904 14:44:21.762204 Set Vref, RX VrefLevel [Byte0]: 39
7905 14:44:21.764875 [Byte1]: 39
7906 14:44:21.769360
7907 14:44:21.769443 Set Vref, RX VrefLevel [Byte0]: 40
7908 14:44:21.773044 [Byte1]: 40
7909 14:44:21.777157
7910 14:44:21.777241 Set Vref, RX VrefLevel [Byte0]: 41
7911 14:44:21.780215 [Byte1]: 41
7912 14:44:21.784827
7913 14:44:21.784902 Set Vref, RX VrefLevel [Byte0]: 42
7914 14:44:21.787873 [Byte1]: 42
7915 14:44:21.792232
7916 14:44:21.792346 Set Vref, RX VrefLevel [Byte0]: 43
7917 14:44:21.795669 [Byte1]: 43
7918 14:44:21.800017
7919 14:44:21.800101 Set Vref, RX VrefLevel [Byte0]: 44
7920 14:44:21.803163 [Byte1]: 44
7921 14:44:21.807551
7922 14:44:21.807634 Set Vref, RX VrefLevel [Byte0]: 45
7923 14:44:21.810728 [Byte1]: 45
7924 14:44:21.815162
7925 14:44:21.815271 Set Vref, RX VrefLevel [Byte0]: 46
7926 14:44:21.818959 [Byte1]: 46
7927 14:44:21.822719
7928 14:44:21.822832 Set Vref, RX VrefLevel [Byte0]: 47
7929 14:44:21.825998 [Byte1]: 47
7930 14:44:21.830463
7931 14:44:21.830545 Set Vref, RX VrefLevel [Byte0]: 48
7932 14:44:21.833392 [Byte1]: 48
7933 14:44:21.837980
7934 14:44:21.838062 Set Vref, RX VrefLevel [Byte0]: 49
7935 14:44:21.841196 [Byte1]: 49
7936 14:44:21.845609
7937 14:44:21.845695 Set Vref, RX VrefLevel [Byte0]: 50
7938 14:44:21.848534 [Byte1]: 50
7939 14:44:21.853211
7940 14:44:21.853302 Set Vref, RX VrefLevel [Byte0]: 51
7941 14:44:21.856510 [Byte1]: 51
7942 14:44:21.860464
7943 14:44:21.860579 Set Vref, RX VrefLevel [Byte0]: 52
7944 14:44:21.864237 [Byte1]: 52
7945 14:44:21.868520
7946 14:44:21.868619 Set Vref, RX VrefLevel [Byte0]: 53
7947 14:44:21.871579 [Byte1]: 53
7948 14:44:21.876065
7949 14:44:21.876147 Set Vref, RX VrefLevel [Byte0]: 54
7950 14:44:21.879443 [Byte1]: 54
7951 14:44:21.883452
7952 14:44:21.883534 Set Vref, RX VrefLevel [Byte0]: 55
7953 14:44:21.887261 [Byte1]: 55
7954 14:44:21.891495
7955 14:44:21.891621 Set Vref, RX VrefLevel [Byte0]: 56
7956 14:44:21.894340 [Byte1]: 56
7957 14:44:21.899024
7958 14:44:21.899107 Set Vref, RX VrefLevel [Byte0]: 57
7959 14:44:21.901936 [Byte1]: 57
7960 14:44:21.906376
7961 14:44:21.906459 Set Vref, RX VrefLevel [Byte0]: 58
7962 14:44:21.909507 [Byte1]: 58
7963 14:44:21.913831
7964 14:44:21.913911 Set Vref, RX VrefLevel [Byte0]: 59
7965 14:44:21.917112 [Byte1]: 59
7966 14:44:21.921876
7967 14:44:21.922002 Set Vref, RX VrefLevel [Byte0]: 60
7968 14:44:21.924764 [Byte1]: 60
7969 14:44:21.929167
7970 14:44:21.929293 Set Vref, RX VrefLevel [Byte0]: 61
7971 14:44:21.932669 [Byte1]: 61
7972 14:44:21.936673
7973 14:44:21.936796 Set Vref, RX VrefLevel [Byte0]: 62
7974 14:44:21.940255 [Byte1]: 62
7975 14:44:21.944680
7976 14:44:21.944802 Set Vref, RX VrefLevel [Byte0]: 63
7977 14:44:21.947549 [Byte1]: 63
7978 14:44:21.951824
7979 14:44:21.951949 Set Vref, RX VrefLevel [Byte0]: 64
7980 14:44:21.955278 [Byte1]: 64
7981 14:44:21.959584
7982 14:44:21.959710 Set Vref, RX VrefLevel [Byte0]: 65
7983 14:44:21.963007 [Byte1]: 65
7984 14:44:21.967200
7985 14:44:21.967286 Set Vref, RX VrefLevel [Byte0]: 66
7986 14:44:21.970632 [Byte1]: 66
7987 14:44:21.975119
7988 14:44:21.975202 Set Vref, RX VrefLevel [Byte0]: 67
7989 14:44:21.978555 [Byte1]: 67
7990 14:44:21.982517
7991 14:44:21.982599 Set Vref, RX VrefLevel [Byte0]: 68
7992 14:44:21.985742 [Byte1]: 68
7993 14:44:21.990328
7994 14:44:21.990438 Set Vref, RX VrefLevel [Byte0]: 69
7995 14:44:21.993152 [Byte1]: 69
7996 14:44:21.997558
7997 14:44:21.997667 Set Vref, RX VrefLevel [Byte0]: 70
7998 14:44:22.001196 [Byte1]: 70
7999 14:44:22.005349
8000 14:44:22.005479 Set Vref, RX VrefLevel [Byte0]: 71
8001 14:44:22.008782 [Byte1]: 71
8002 14:44:22.013414
8003 14:44:22.013540 Set Vref, RX VrefLevel [Byte0]: 72
8004 14:44:22.016165 [Byte1]: 72
8005 14:44:22.020724
8006 14:44:22.020852 Set Vref, RX VrefLevel [Byte0]: 73
8007 14:44:22.023884 [Byte1]: 73
8008 14:44:22.028199
8009 14:44:22.028324 Set Vref, RX VrefLevel [Byte0]: 74
8010 14:44:22.031765 [Byte1]: 74
8011 14:44:22.035711
8012 14:44:22.035838 Set Vref, RX VrefLevel [Byte0]: 75
8013 14:44:22.039112 [Byte1]: 75
8014 14:44:22.043249
8015 14:44:22.043375 Set Vref, RX VrefLevel [Byte0]: 76
8016 14:44:22.046741 [Byte1]: 76
8017 14:44:22.050862
8018 14:44:22.050991 Set Vref, RX VrefLevel [Byte0]: 77
8019 14:44:22.054179 [Byte1]: 77
8020 14:44:22.058765
8021 14:44:22.058888 Set Vref, RX VrefLevel [Byte0]: 78
8022 14:44:22.062236 [Byte1]: 78
8023 14:44:22.066278
8024 14:44:22.066403 Final RX Vref Byte 0 = 64 to rank0
8025 14:44:22.069496 Final RX Vref Byte 1 = 62 to rank0
8026 14:44:22.072822 Final RX Vref Byte 0 = 64 to rank1
8027 14:44:22.076255 Final RX Vref Byte 1 = 62 to rank1==
8028 14:44:22.079410 Dram Type= 6, Freq= 0, CH_0, rank 0
8029 14:44:22.086309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 14:44:22.086437 ==
8031 14:44:22.086552 DQS Delay:
8032 14:44:22.086664 DQS0 = 0, DQS1 = 0
8033 14:44:22.089174 DQM Delay:
8034 14:44:22.089297 DQM0 = 126, DQM1 = 119
8035 14:44:22.092742 DQ Delay:
8036 14:44:22.096052 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8037 14:44:22.099429 DQ4 =126, DQ5 =112, DQ6 =134, DQ7 =138
8038 14:44:22.102776 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8039 14:44:22.105892 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8040 14:44:22.106014
8041 14:44:22.106128
8042 14:44:22.106238
8043 14:44:22.109059 [DramC_TX_OE_Calibration] TA2
8044 14:44:22.112537 Original DQ_B0 (3 6) =30, OEN = 27
8045 14:44:22.115915 Original DQ_B1 (3 6) =30, OEN = 27
8046 14:44:22.119220 24, 0x0, End_B0=24 End_B1=24
8047 14:44:22.119347 25, 0x0, End_B0=25 End_B1=25
8048 14:44:22.122312 26, 0x0, End_B0=26 End_B1=26
8049 14:44:22.125570 27, 0x0, End_B0=27 End_B1=27
8050 14:44:22.129306 28, 0x0, End_B0=28 End_B1=28
8051 14:44:22.132645 29, 0x0, End_B0=29 End_B1=29
8052 14:44:22.132764 30, 0x0, End_B0=30 End_B1=30
8053 14:44:22.135977 31, 0x4141, End_B0=30 End_B1=30
8054 14:44:22.138920 Byte0 end_step=30 best_step=27
8055 14:44:22.142136 Byte1 end_step=30 best_step=27
8056 14:44:22.145905 Byte0 TX OE(2T, 0.5T) = (3, 3)
8057 14:44:22.148816 Byte1 TX OE(2T, 0.5T) = (3, 3)
8058 14:44:22.148901
8059 14:44:22.148967
8060 14:44:22.155723 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8061 14:44:22.159081 CH0 RK0: MR19=303, MR18=1313
8062 14:44:22.165423 CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=23, DEC=15
8063 14:44:22.165510
8064 14:44:22.168595 ----->DramcWriteLeveling(PI) begin...
8065 14:44:22.168681 ==
8066 14:44:22.172117 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 14:44:22.175277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 14:44:22.175369 ==
8069 14:44:22.178457 Write leveling (Byte 0): 35 => 35
8070 14:44:22.181907 Write leveling (Byte 1): 27 => 27
8071 14:44:22.185241 DramcWriteLeveling(PI) end<-----
8072 14:44:22.185326
8073 14:44:22.185392 ==
8074 14:44:22.188581 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 14:44:22.192049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 14:44:22.192134 ==
8077 14:44:22.194965 [Gating] SW mode calibration
8078 14:44:22.201819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8079 14:44:22.208124 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8080 14:44:22.211458 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 14:44:22.218299 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 14:44:22.221856 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 14:44:22.224971 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8084 14:44:22.231870 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8085 14:44:22.234982 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8086 14:44:22.238346 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8087 14:44:22.244851 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 14:44:22.248163 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 14:44:22.251558 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8090 14:44:22.258033 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8091 14:44:22.261777 1 5 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8092 14:44:22.264335 1 5 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8093 14:44:22.270939 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8094 14:44:22.274591 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 14:44:22.277717 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 14:44:22.284439 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 14:44:22.287695 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 14:44:22.291084 1 6 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8099 14:44:22.297842 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8100 14:44:22.301238 1 6 16 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
8101 14:44:22.303958 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 14:44:22.310453 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 14:44:22.314354 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 14:44:22.317247 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 14:44:22.323978 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 14:44:22.327289 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8107 14:44:22.330766 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8108 14:44:22.337372 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8109 14:44:22.340787 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8110 14:44:22.344130 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 14:44:22.350352 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 14:44:22.354184 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 14:44:22.357106 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 14:44:22.363743 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 14:44:22.367074 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 14:44:22.370416 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 14:44:22.373839 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 14:44:22.380486 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 14:44:22.383656 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 14:44:22.386912 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 14:44:22.393509 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 14:44:22.396800 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8123 14:44:22.399887 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8124 14:44:22.403709 Total UI for P1: 0, mck2ui 16
8125 14:44:22.406613 best dqsien dly found for B0: ( 1, 9, 8)
8126 14:44:22.413493 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8127 14:44:22.416971 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8128 14:44:22.419809 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8129 14:44:22.426481 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 14:44:22.430176 Total UI for P1: 0, mck2ui 16
8131 14:44:22.433314 best dqsien dly found for B1: ( 1, 9, 18)
8132 14:44:22.436737 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8133 14:44:22.440004 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8134 14:44:22.440129
8135 14:44:22.442953 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8136 14:44:22.446274 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8137 14:44:22.449638 [Gating] SW calibration Done
8138 14:44:22.449722 ==
8139 14:44:22.453221 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 14:44:22.456502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 14:44:22.456605 ==
8142 14:44:22.459825 RX Vref Scan: 0
8143 14:44:22.459943
8144 14:44:22.462897 RX Vref 0 -> 0, step: 1
8145 14:44:22.463015
8146 14:44:22.463116 RX Delay 0 -> 252, step: 8
8147 14:44:22.469301 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8148 14:44:22.472868 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8149 14:44:22.476413 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8150 14:44:22.479637 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8151 14:44:22.482641 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8152 14:44:22.489556 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8153 14:44:22.492502 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8154 14:44:22.495811 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8155 14:44:22.499305 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8156 14:44:22.502479 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8157 14:44:22.509417 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8158 14:44:22.512698 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8159 14:44:22.516300 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8160 14:44:22.519197 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8161 14:44:22.522544 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8162 14:44:22.529307 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8163 14:44:22.529433 ==
8164 14:44:22.532648 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 14:44:22.535570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 14:44:22.535695 ==
8167 14:44:22.535806 DQS Delay:
8168 14:44:22.539170 DQS0 = 0, DQS1 = 0
8169 14:44:22.539275 DQM Delay:
8170 14:44:22.542268 DQM0 = 127, DQM1 = 121
8171 14:44:22.542376 DQ Delay:
8172 14:44:22.545823 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8173 14:44:22.549260 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8174 14:44:22.552084 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8175 14:44:22.555594 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8176 14:44:22.559053
8177 14:44:22.559155
8178 14:44:22.559247 ==
8179 14:44:22.562258 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 14:44:22.565716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 14:44:22.565829 ==
8182 14:44:22.565922
8183 14:44:22.566014
8184 14:44:22.568881 TX Vref Scan disable
8185 14:44:22.568956 == TX Byte 0 ==
8186 14:44:22.575529 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8187 14:44:22.578616 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8188 14:44:22.578700 == TX Byte 1 ==
8189 14:44:22.585540 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8190 14:44:22.588948 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8191 14:44:22.589035 ==
8192 14:44:22.592252 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 14:44:22.595143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 14:44:22.595246 ==
8195 14:44:22.610888
8196 14:44:22.614495 TX Vref early break, caculate TX vref
8197 14:44:22.617610 TX Vref=16, minBit 8, minWin=21, winSum=366
8198 14:44:22.620814 TX Vref=18, minBit 8, minWin=22, winSum=372
8199 14:44:22.624529 TX Vref=20, minBit 9, minWin=22, winSum=384
8200 14:44:22.627553 TX Vref=22, minBit 0, minWin=24, winSum=391
8201 14:44:22.631094 TX Vref=24, minBit 8, minWin=23, winSum=399
8202 14:44:22.637510 TX Vref=26, minBit 8, minWin=24, winSum=406
8203 14:44:22.640807 TX Vref=28, minBit 8, minWin=24, winSum=407
8204 14:44:22.644035 TX Vref=30, minBit 8, minWin=24, winSum=405
8205 14:44:22.647069 TX Vref=32, minBit 8, minWin=23, winSum=398
8206 14:44:22.650817 TX Vref=34, minBit 8, minWin=22, winSum=387
8207 14:44:22.657217 TX Vref=36, minBit 8, minWin=22, winSum=378
8208 14:44:22.660597 [TxChooseVref] Worse bit 8, Min win 24, Win sum 407, Final Vref 28
8209 14:44:22.660681
8210 14:44:22.664110 Final TX Range 0 Vref 28
8211 14:44:22.664193
8212 14:44:22.664258 ==
8213 14:44:22.667283 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 14:44:22.670209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 14:44:22.673653 ==
8216 14:44:22.673740
8217 14:44:22.673806
8218 14:44:22.673868 TX Vref Scan disable
8219 14:44:22.680390 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8220 14:44:22.680474 == TX Byte 0 ==
8221 14:44:22.683876 u2DelayCellOfst[0]=11 cells (3 PI)
8222 14:44:22.687017 u2DelayCellOfst[1]=18 cells (5 PI)
8223 14:44:22.690618 u2DelayCellOfst[2]=11 cells (3 PI)
8224 14:44:22.693444 u2DelayCellOfst[3]=11 cells (3 PI)
8225 14:44:22.696820 u2DelayCellOfst[4]=7 cells (2 PI)
8226 14:44:22.700394 u2DelayCellOfst[5]=0 cells (0 PI)
8227 14:44:22.703612 u2DelayCellOfst[6]=18 cells (5 PI)
8228 14:44:22.706988 u2DelayCellOfst[7]=18 cells (5 PI)
8229 14:44:22.710256 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8230 14:44:22.713686 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8231 14:44:22.716887 == TX Byte 1 ==
8232 14:44:22.720171 u2DelayCellOfst[8]=0 cells (0 PI)
8233 14:44:22.723451 u2DelayCellOfst[9]=0 cells (0 PI)
8234 14:44:22.727330 u2DelayCellOfst[10]=7 cells (2 PI)
8235 14:44:22.730060 u2DelayCellOfst[11]=7 cells (2 PI)
8236 14:44:22.730190 u2DelayCellOfst[12]=15 cells (4 PI)
8237 14:44:22.733399 u2DelayCellOfst[13]=11 cells (3 PI)
8238 14:44:22.736911 u2DelayCellOfst[14]=15 cells (4 PI)
8239 14:44:22.740345 u2DelayCellOfst[15]=11 cells (3 PI)
8240 14:44:22.746521 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8241 14:44:22.749952 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8242 14:44:22.750047 DramC Write-DBI on
8243 14:44:22.753039 ==
8244 14:44:22.756603 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 14:44:22.759951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 14:44:22.760063 ==
8247 14:44:22.760155
8248 14:44:22.760242
8249 14:44:22.763346 TX Vref Scan disable
8250 14:44:22.763428 == TX Byte 0 ==
8251 14:44:22.769931 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8252 14:44:22.770025 == TX Byte 1 ==
8253 14:44:22.773251 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8254 14:44:22.776232 DramC Write-DBI off
8255 14:44:22.776342
8256 14:44:22.776435 [DATLAT]
8257 14:44:22.779581 Freq=1600, CH0 RK1
8258 14:44:22.779709
8259 14:44:22.779772 DATLAT Default: 0xf
8260 14:44:22.783179 0, 0xFFFF, sum = 0
8261 14:44:22.783291 1, 0xFFFF, sum = 0
8262 14:44:22.786706 2, 0xFFFF, sum = 0
8263 14:44:22.786813 3, 0xFFFF, sum = 0
8264 14:44:22.789989 4, 0xFFFF, sum = 0
8265 14:44:22.790101 5, 0xFFFF, sum = 0
8266 14:44:22.793060 6, 0xFFFF, sum = 0
8267 14:44:22.796422 7, 0xFFFF, sum = 0
8268 14:44:22.796525 8, 0xFFFF, sum = 0
8269 14:44:22.799639 9, 0xFFFF, sum = 0
8270 14:44:22.799721 10, 0xFFFF, sum = 0
8271 14:44:22.802906 11, 0xFFFF, sum = 0
8272 14:44:22.802989 12, 0xFFFF, sum = 0
8273 14:44:22.806010 13, 0xCFFF, sum = 0
8274 14:44:22.806095 14, 0x0, sum = 1
8275 14:44:22.809534 15, 0x0, sum = 2
8276 14:44:22.809618 16, 0x0, sum = 3
8277 14:44:22.812877 17, 0x0, sum = 4
8278 14:44:22.812961 best_step = 15
8279 14:44:22.813026
8280 14:44:22.813086 ==
8281 14:44:22.816013 Dram Type= 6, Freq= 0, CH_0, rank 1
8282 14:44:22.819769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 14:44:22.822789 ==
8284 14:44:22.822872 RX Vref Scan: 0
8285 14:44:22.822938
8286 14:44:22.825815 RX Vref 0 -> 0, step: 1
8287 14:44:22.825899
8288 14:44:22.825966 RX Delay 3 -> 252, step: 4
8289 14:44:22.833172 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8290 14:44:22.836577 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8291 14:44:22.839847 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8292 14:44:22.843366 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8293 14:44:22.846584 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8294 14:44:22.853496 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8295 14:44:22.856340 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8296 14:44:22.859597 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8297 14:44:22.863098 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8298 14:44:22.866244 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8299 14:44:22.873159 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8300 14:44:22.876523 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8301 14:44:22.879579 iDelay=191, Bit 12, Center 122 (67 ~ 178) 112
8302 14:44:22.883415 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8303 14:44:22.889660 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8304 14:44:22.892910 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8305 14:44:22.892998 ==
8306 14:44:22.896454 Dram Type= 6, Freq= 0, CH_0, rank 1
8307 14:44:22.899425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 14:44:22.899558 ==
8309 14:44:22.902814 DQS Delay:
8310 14:44:22.902941 DQS0 = 0, DQS1 = 0
8311 14:44:22.903057 DQM Delay:
8312 14:44:22.906146 DQM0 = 124, DQM1 = 117
8313 14:44:22.906273 DQ Delay:
8314 14:44:22.909674 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8315 14:44:22.913120 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8316 14:44:22.916366 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8317 14:44:22.922649 DQ12 =122, DQ13 =122, DQ14 =128, DQ15 =124
8318 14:44:22.922777
8319 14:44:22.922890
8320 14:44:22.923004
8321 14:44:22.926230 [DramC_TX_OE_Calibration] TA2
8322 14:44:22.926356 Original DQ_B0 (3 6) =30, OEN = 27
8323 14:44:22.929568 Original DQ_B1 (3 6) =30, OEN = 27
8324 14:44:22.932746 24, 0x0, End_B0=24 End_B1=24
8325 14:44:22.936140 25, 0x0, End_B0=25 End_B1=25
8326 14:44:22.939308 26, 0x0, End_B0=26 End_B1=26
8327 14:44:22.942442 27, 0x0, End_B0=27 End_B1=27
8328 14:44:22.942551 28, 0x0, End_B0=28 End_B1=28
8329 14:44:22.946193 29, 0x0, End_B0=29 End_B1=29
8330 14:44:22.949972 30, 0x0, End_B0=30 End_B1=30
8331 14:44:22.952894 31, 0x5151, End_B0=30 End_B1=30
8332 14:44:22.955906 Byte0 end_step=30 best_step=27
8333 14:44:22.955982 Byte1 end_step=30 best_step=27
8334 14:44:22.959261 Byte0 TX OE(2T, 0.5T) = (3, 3)
8335 14:44:22.962686 Byte1 TX OE(2T, 0.5T) = (3, 3)
8336 14:44:22.962803
8337 14:44:22.962906
8338 14:44:22.972514 [DQSOSCAuto] RK1, (LSB)MR18= 0x2612, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8339 14:44:22.972655 CH0 RK1: MR19=303, MR18=2612
8340 14:44:22.979195 CH0_RK1: MR19=0x303, MR18=0x2612, DQSOSC=390, MR23=63, INC=24, DEC=16
8341 14:44:22.982681 [RxdqsGatingPostProcess] freq 1600
8342 14:44:22.989019 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8343 14:44:22.992909 best DQS0 dly(2T, 0.5T) = (1, 1)
8344 14:44:22.995836 best DQS1 dly(2T, 0.5T) = (1, 1)
8345 14:44:22.999101 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8346 14:44:23.002648 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8347 14:44:23.002757 best DQS0 dly(2T, 0.5T) = (1, 1)
8348 14:44:23.006073 best DQS1 dly(2T, 0.5T) = (1, 1)
8349 14:44:23.009417 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8350 14:44:23.012866 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8351 14:44:23.015711 Pre-setting of DQS Precalculation
8352 14:44:23.022576 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8353 14:44:23.022660 ==
8354 14:44:23.025712 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 14:44:23.029317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 14:44:23.029432 ==
8357 14:44:23.035953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8358 14:44:23.039123 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8359 14:44:23.042250 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8360 14:44:23.048905 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8361 14:44:23.057323 [CA 0] Center 41 (12~70) winsize 59
8362 14:44:23.061101 [CA 1] Center 42 (12~72) winsize 61
8363 14:44:23.063928 [CA 2] Center 37 (9~66) winsize 58
8364 14:44:23.067516 [CA 3] Center 37 (8~66) winsize 59
8365 14:44:23.070583 [CA 4] Center 37 (8~67) winsize 60
8366 14:44:23.073915 [CA 5] Center 36 (7~66) winsize 60
8367 14:44:23.074038
8368 14:44:23.077650 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8369 14:44:23.077773
8370 14:44:23.080841 [CATrainingPosCal] consider 1 rank data
8371 14:44:23.084194 u2DelayCellTimex100 = 258/100 ps
8372 14:44:23.087486 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8373 14:44:23.093799 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8374 14:44:23.097161 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8375 14:44:23.100524 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8376 14:44:23.104188 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8377 14:44:23.107640 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8378 14:44:23.107723
8379 14:44:23.110774 CA PerBit enable=1, Macro0, CA PI delay=36
8380 14:44:23.110857
8381 14:44:23.114033 [CBTSetCACLKResult] CA Dly = 36
8382 14:44:23.117035 CS Dly: 9 (0~40)
8383 14:44:23.120184 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8384 14:44:23.123794 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8385 14:44:23.123878 ==
8386 14:44:23.127251 Dram Type= 6, Freq= 0, CH_1, rank 1
8387 14:44:23.130528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 14:44:23.133917 ==
8389 14:44:23.137213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8390 14:44:23.140537 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8391 14:44:23.146914 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8392 14:44:23.150422 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8393 14:44:23.160855 [CA 0] Center 42 (13~72) winsize 60
8394 14:44:23.163867 [CA 1] Center 42 (12~73) winsize 62
8395 14:44:23.167361 [CA 2] Center 38 (9~67) winsize 59
8396 14:44:23.170743 [CA 3] Center 36 (7~66) winsize 60
8397 14:44:23.174055 [CA 4] Center 38 (8~68) winsize 61
8398 14:44:23.177126 [CA 5] Center 36 (7~66) winsize 60
8399 14:44:23.177209
8400 14:44:23.180959 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8401 14:44:23.181041
8402 14:44:23.184021 [CATrainingPosCal] consider 2 rank data
8403 14:44:23.187240 u2DelayCellTimex100 = 258/100 ps
8404 14:44:23.190423 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8405 14:44:23.197370 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8406 14:44:23.200736 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8407 14:44:23.203674 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8408 14:44:23.207280 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8409 14:44:23.210201 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8410 14:44:23.210310
8411 14:44:23.213626 CA PerBit enable=1, Macro0, CA PI delay=36
8412 14:44:23.213710
8413 14:44:23.217367 [CBTSetCACLKResult] CA Dly = 36
8414 14:44:23.220202 CS Dly: 11 (0~44)
8415 14:44:23.225042 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8416 14:44:23.226858 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8417 14:44:23.226957
8418 14:44:23.230512 ----->DramcWriteLeveling(PI) begin...
8419 14:44:23.230641 ==
8420 14:44:23.233795 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 14:44:23.237301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 14:44:23.240177 ==
8423 14:44:23.240300 Write leveling (Byte 0): 24 => 24
8424 14:44:23.243589 Write leveling (Byte 1): 28 => 28
8425 14:44:23.246882 DramcWriteLeveling(PI) end<-----
8426 14:44:23.247005
8427 14:44:23.247113 ==
8428 14:44:23.250349 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 14:44:23.256721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 14:44:23.256806 ==
8431 14:44:23.260452 [Gating] SW mode calibration
8432 14:44:23.266935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8433 14:44:23.270084 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8434 14:44:23.276589 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 14:44:23.279984 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 14:44:23.283392 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 14:44:23.289905 1 4 12 | B1->B0 | 2727 2423 | 1 1 | (1 1) (0 0)
8438 14:44:23.293396 1 4 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
8439 14:44:23.296501 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 14:44:23.303220 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 14:44:23.306659 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 14:44:23.309986 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 14:44:23.316270 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 14:44:23.319604 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 14:44:23.322854 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8446 14:44:23.326442 1 5 16 | B1->B0 | 2828 2929 | 0 0 | (0 0) (0 1)
8447 14:44:23.333033 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 14:44:23.336437 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 14:44:23.339583 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 14:44:23.346504 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 14:44:23.349831 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 14:44:23.355897 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 14:44:23.359582 1 6 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8454 14:44:23.362631 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 14:44:23.366330 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 14:44:23.372607 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 14:44:23.375893 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 14:44:23.379554 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 14:44:23.385892 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 14:44:23.389423 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 14:44:23.392300 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 14:44:23.399260 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8463 14:44:23.402674 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 14:44:23.405800 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 14:44:23.412496 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 14:44:23.415384 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 14:44:23.418862 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 14:44:23.425469 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 14:44:23.428643 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 14:44:23.432236 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 14:44:23.439061 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 14:44:23.442386 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 14:44:23.445401 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 14:44:23.452113 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 14:44:23.455193 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 14:44:23.458591 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 14:44:23.465046 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8478 14:44:23.468378 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8479 14:44:23.471758 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 14:44:23.475144 Total UI for P1: 0, mck2ui 16
8481 14:44:23.478124 best dqsien dly found for B0: ( 1, 9, 14)
8482 14:44:23.481406 Total UI for P1: 0, mck2ui 16
8483 14:44:23.485007 best dqsien dly found for B1: ( 1, 9, 16)
8484 14:44:23.488240 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8485 14:44:23.491780 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8486 14:44:23.494652
8487 14:44:23.498129 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8488 14:44:23.501573 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8489 14:44:23.504796 [Gating] SW calibration Done
8490 14:44:23.504892 ==
8491 14:44:23.508201 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 14:44:23.511680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 14:44:23.511770 ==
8494 14:44:23.514611 RX Vref Scan: 0
8495 14:44:23.514694
8496 14:44:23.514761 RX Vref 0 -> 0, step: 1
8497 14:44:23.514823
8498 14:44:23.518022 RX Delay 0 -> 252, step: 8
8499 14:44:23.521123 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8500 14:44:23.524517 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8501 14:44:23.530947 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8502 14:44:23.534339 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8503 14:44:23.537796 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8504 14:44:23.541408 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8505 14:44:23.544585 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8506 14:44:23.550850 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8507 14:44:23.554216 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8508 14:44:23.557833 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8509 14:44:23.561008 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8510 14:44:23.564322 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8511 14:44:23.571037 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8512 14:44:23.574455 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8513 14:44:23.577808 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8514 14:44:23.581186 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8515 14:44:23.581270 ==
8516 14:44:23.584248 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 14:44:23.590802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 14:44:23.590942 ==
8519 14:44:23.591028 DQS Delay:
8520 14:44:23.593938 DQS0 = 0, DQS1 = 0
8521 14:44:23.594024 DQM Delay:
8522 14:44:23.597367 DQM0 = 132, DQM1 = 126
8523 14:44:23.597457 DQ Delay:
8524 14:44:23.600726 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8525 14:44:23.604018 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8526 14:44:23.607299 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8527 14:44:23.610811 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8528 14:44:23.610896
8529 14:44:23.610981
8530 14:44:23.611060 ==
8531 14:44:23.614171 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 14:44:23.620880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 14:44:23.621018 ==
8534 14:44:23.621123
8535 14:44:23.621206
8536 14:44:23.621287 TX Vref Scan disable
8537 14:44:23.624065 == TX Byte 0 ==
8538 14:44:23.627966 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8539 14:44:23.630808 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8540 14:44:23.634196 == TX Byte 1 ==
8541 14:44:23.637088 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8542 14:44:23.640798 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8543 14:44:23.644014 ==
8544 14:44:23.647425 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 14:44:23.650520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 14:44:23.650649 ==
8547 14:44:23.662939
8548 14:44:23.665903 TX Vref early break, caculate TX vref
8549 14:44:23.669254 TX Vref=16, minBit 10, minWin=21, winSum=363
8550 14:44:23.672540 TX Vref=18, minBit 11, minWin=21, winSum=368
8551 14:44:23.676001 TX Vref=20, minBit 5, minWin=23, winSum=383
8552 14:44:23.679496 TX Vref=22, minBit 11, minWin=23, winSum=393
8553 14:44:23.682974 TX Vref=24, minBit 5, minWin=24, winSum=402
8554 14:44:23.689098 TX Vref=26, minBit 1, minWin=24, winSum=412
8555 14:44:23.692748 TX Vref=28, minBit 0, minWin=25, winSum=417
8556 14:44:23.696276 TX Vref=30, minBit 0, minWin=24, winSum=413
8557 14:44:23.699445 TX Vref=32, minBit 9, minWin=23, winSum=401
8558 14:44:23.702404 TX Vref=34, minBit 0, minWin=23, winSum=392
8559 14:44:23.709219 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8560 14:44:23.709310
8561 14:44:23.712896 Final TX Range 0 Vref 28
8562 14:44:23.712984
8563 14:44:23.713072 ==
8564 14:44:23.715718 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 14:44:23.719173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 14:44:23.719252 ==
8567 14:44:23.719317
8568 14:44:23.719376
8569 14:44:23.722594 TX Vref Scan disable
8570 14:44:23.728736 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8571 14:44:23.728822 == TX Byte 0 ==
8572 14:44:23.732110 u2DelayCellOfst[0]=22 cells (6 PI)
8573 14:44:23.735465 u2DelayCellOfst[1]=15 cells (4 PI)
8574 14:44:23.738823 u2DelayCellOfst[2]=0 cells (0 PI)
8575 14:44:23.742295 u2DelayCellOfst[3]=7 cells (2 PI)
8576 14:44:23.745696 u2DelayCellOfst[4]=11 cells (3 PI)
8577 14:44:23.748765 u2DelayCellOfst[5]=22 cells (6 PI)
8578 14:44:23.752025 u2DelayCellOfst[6]=26 cells (7 PI)
8579 14:44:23.755454 u2DelayCellOfst[7]=11 cells (3 PI)
8580 14:44:23.758951 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8581 14:44:23.762072 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8582 14:44:23.765462 == TX Byte 1 ==
8583 14:44:23.768426 u2DelayCellOfst[8]=0 cells (0 PI)
8584 14:44:23.771628 u2DelayCellOfst[9]=7 cells (2 PI)
8585 14:44:23.775060 u2DelayCellOfst[10]=15 cells (4 PI)
8586 14:44:23.775188 u2DelayCellOfst[11]=7 cells (2 PI)
8587 14:44:23.778442 u2DelayCellOfst[12]=18 cells (5 PI)
8588 14:44:23.781602 u2DelayCellOfst[13]=26 cells (7 PI)
8589 14:44:23.785515 u2DelayCellOfst[14]=22 cells (6 PI)
8590 14:44:23.788338 u2DelayCellOfst[15]=26 cells (7 PI)
8591 14:44:23.795244 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8592 14:44:23.798395 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8593 14:44:23.798480 DramC Write-DBI on
8594 14:44:23.798546 ==
8595 14:44:23.801525 Dram Type= 6, Freq= 0, CH_1, rank 0
8596 14:44:23.808362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8597 14:44:23.808446 ==
8598 14:44:23.808511
8599 14:44:23.808581
8600 14:44:23.808642 TX Vref Scan disable
8601 14:44:23.812551 == TX Byte 0 ==
8602 14:44:23.815677 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8603 14:44:23.818866 == TX Byte 1 ==
8604 14:44:23.822262 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8605 14:44:23.825616 DramC Write-DBI off
8606 14:44:23.825703
8607 14:44:23.825790 [DATLAT]
8608 14:44:23.825873 Freq=1600, CH1 RK0
8609 14:44:23.825954
8610 14:44:23.829098 DATLAT Default: 0xf
8611 14:44:23.829184 0, 0xFFFF, sum = 0
8612 14:44:23.832444 1, 0xFFFF, sum = 0
8613 14:44:23.836063 2, 0xFFFF, sum = 0
8614 14:44:23.836172 3, 0xFFFF, sum = 0
8615 14:44:23.839266 4, 0xFFFF, sum = 0
8616 14:44:23.839358 5, 0xFFFF, sum = 0
8617 14:44:23.842466 6, 0xFFFF, sum = 0
8618 14:44:23.842555 7, 0xFFFF, sum = 0
8619 14:44:23.845415 8, 0xFFFF, sum = 0
8620 14:44:23.845501 9, 0xFFFF, sum = 0
8621 14:44:23.848760 10, 0xFFFF, sum = 0
8622 14:44:23.848847 11, 0xFFFF, sum = 0
8623 14:44:23.852141 12, 0xFFFF, sum = 0
8624 14:44:23.852224 13, 0x8FFF, sum = 0
8625 14:44:23.855574 14, 0x0, sum = 1
8626 14:44:23.855658 15, 0x0, sum = 2
8627 14:44:23.859120 16, 0x0, sum = 3
8628 14:44:23.859210 17, 0x0, sum = 4
8629 14:44:23.862009 best_step = 15
8630 14:44:23.862096
8631 14:44:23.862183 ==
8632 14:44:23.865717 Dram Type= 6, Freq= 0, CH_1, rank 0
8633 14:44:23.868830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8634 14:44:23.868918 ==
8635 14:44:23.872304 RX Vref Scan: 1
8636 14:44:23.872391
8637 14:44:23.872495 Set Vref Range= 24 -> 127
8638 14:44:23.872606
8639 14:44:23.875882 RX Vref 24 -> 127, step: 1
8640 14:44:23.875982
8641 14:44:23.878701 RX Delay 11 -> 252, step: 4
8642 14:44:23.878787
8643 14:44:23.882385 Set Vref, RX VrefLevel [Byte0]: 24
8644 14:44:23.885420 [Byte1]: 24
8645 14:44:23.885507
8646 14:44:23.888662 Set Vref, RX VrefLevel [Byte0]: 25
8647 14:44:23.892234 [Byte1]: 25
8648 14:44:23.895325
8649 14:44:23.895412 Set Vref, RX VrefLevel [Byte0]: 26
8650 14:44:23.898439 [Byte1]: 26
8651 14:44:23.902628
8652 14:44:23.902712 Set Vref, RX VrefLevel [Byte0]: 27
8653 14:44:23.905936 [Byte1]: 27
8654 14:44:23.910587
8655 14:44:23.910670 Set Vref, RX VrefLevel [Byte0]: 28
8656 14:44:23.913832 [Byte1]: 28
8657 14:44:23.917947
8658 14:44:23.918067 Set Vref, RX VrefLevel [Byte0]: 29
8659 14:44:23.921335 [Byte1]: 29
8660 14:44:23.925792
8661 14:44:23.925874 Set Vref, RX VrefLevel [Byte0]: 30
8662 14:44:23.929270 [Byte1]: 30
8663 14:44:23.933221
8664 14:44:23.933305 Set Vref, RX VrefLevel [Byte0]: 31
8665 14:44:23.936661 [Byte1]: 31
8666 14:44:23.940713
8667 14:44:23.940797 Set Vref, RX VrefLevel [Byte0]: 32
8668 14:44:23.944065 [Byte1]: 32
8669 14:44:23.948424
8670 14:44:23.948540 Set Vref, RX VrefLevel [Byte0]: 33
8671 14:44:23.951965 [Byte1]: 33
8672 14:44:23.956327
8673 14:44:23.956481 Set Vref, RX VrefLevel [Byte0]: 34
8674 14:44:23.959577 [Byte1]: 34
8675 14:44:23.964299
8676 14:44:23.964422 Set Vref, RX VrefLevel [Byte0]: 35
8677 14:44:23.967071 [Byte1]: 35
8678 14:44:23.971489
8679 14:44:23.971617 Set Vref, RX VrefLevel [Byte0]: 36
8680 14:44:23.974675 [Byte1]: 36
8681 14:44:23.978800
8682 14:44:23.978929 Set Vref, RX VrefLevel [Byte0]: 37
8683 14:44:23.982235 [Byte1]: 37
8684 14:44:23.986812
8685 14:44:23.986952 Set Vref, RX VrefLevel [Byte0]: 38
8686 14:44:23.990267 [Byte1]: 38
8687 14:44:23.994270
8688 14:44:23.994394 Set Vref, RX VrefLevel [Byte0]: 39
8689 14:44:23.997487 [Byte1]: 39
8690 14:44:24.001974
8691 14:44:24.002108 Set Vref, RX VrefLevel [Byte0]: 40
8692 14:44:24.005087 [Byte1]: 40
8693 14:44:24.009422
8694 14:44:24.009557 Set Vref, RX VrefLevel [Byte0]: 41
8695 14:44:24.012881 [Byte1]: 41
8696 14:44:24.016975
8697 14:44:24.017103 Set Vref, RX VrefLevel [Byte0]: 42
8698 14:44:24.020297 [Byte1]: 42
8699 14:44:24.024631
8700 14:44:24.024763 Set Vref, RX VrefLevel [Byte0]: 43
8701 14:44:24.028119 [Byte1]: 43
8702 14:44:24.032417
8703 14:44:24.032527 Set Vref, RX VrefLevel [Byte0]: 44
8704 14:44:24.035556 [Byte1]: 44
8705 14:44:24.039992
8706 14:44:24.040070 Set Vref, RX VrefLevel [Byte0]: 45
8707 14:44:24.043497 [Byte1]: 45
8708 14:44:24.047400
8709 14:44:24.047505 Set Vref, RX VrefLevel [Byte0]: 46
8710 14:44:24.050789 [Byte1]: 46
8711 14:44:24.055303
8712 14:44:24.055408 Set Vref, RX VrefLevel [Byte0]: 47
8713 14:44:24.058521 [Byte1]: 47
8714 14:44:24.063082
8715 14:44:24.063202 Set Vref, RX VrefLevel [Byte0]: 48
8716 14:44:24.065935 [Byte1]: 48
8717 14:44:24.070456
8718 14:44:24.070534 Set Vref, RX VrefLevel [Byte0]: 49
8719 14:44:24.073954 [Byte1]: 49
8720 14:44:24.077892
8721 14:44:24.077968 Set Vref, RX VrefLevel [Byte0]: 50
8722 14:44:24.081274 [Byte1]: 50
8723 14:44:24.085868
8724 14:44:24.088703 Set Vref, RX VrefLevel [Byte0]: 51
8725 14:44:24.092202 [Byte1]: 51
8726 14:44:24.092286
8727 14:44:24.095946 Set Vref, RX VrefLevel [Byte0]: 52
8728 14:44:24.098391 [Byte1]: 52
8729 14:44:24.098474
8730 14:44:24.101977 Set Vref, RX VrefLevel [Byte0]: 53
8731 14:44:24.105118 [Byte1]: 53
8732 14:44:24.105201
8733 14:44:24.108444 Set Vref, RX VrefLevel [Byte0]: 54
8734 14:44:24.111757 [Byte1]: 54
8735 14:44:24.116247
8736 14:44:24.116335 Set Vref, RX VrefLevel [Byte0]: 55
8737 14:44:24.119386 [Byte1]: 55
8738 14:44:24.123594
8739 14:44:24.123678 Set Vref, RX VrefLevel [Byte0]: 56
8740 14:44:24.126939 [Byte1]: 56
8741 14:44:24.130996
8742 14:44:24.131085 Set Vref, RX VrefLevel [Byte0]: 57
8743 14:44:24.134371 [Byte1]: 57
8744 14:44:24.138878
8745 14:44:24.138961 Set Vref, RX VrefLevel [Byte0]: 58
8746 14:44:24.141902 [Byte1]: 58
8747 14:44:24.146239
8748 14:44:24.146320 Set Vref, RX VrefLevel [Byte0]: 59
8749 14:44:24.149548 [Byte1]: 59
8750 14:44:24.154007
8751 14:44:24.154137 Set Vref, RX VrefLevel [Byte0]: 60
8752 14:44:24.157077 [Byte1]: 60
8753 14:44:24.161891
8754 14:44:24.162020 Set Vref, RX VrefLevel [Byte0]: 61
8755 14:44:24.165027 [Byte1]: 61
8756 14:44:24.169715
8757 14:44:24.169840 Set Vref, RX VrefLevel [Byte0]: 62
8758 14:44:24.172459 [Byte1]: 62
8759 14:44:24.177167
8760 14:44:24.177291 Set Vref, RX VrefLevel [Byte0]: 63
8761 14:44:24.180257 [Byte1]: 63
8762 14:44:24.184825
8763 14:44:24.184948 Set Vref, RX VrefLevel [Byte0]: 64
8764 14:44:24.187688 [Byte1]: 64
8765 14:44:24.192336
8766 14:44:24.192460 Set Vref, RX VrefLevel [Byte0]: 65
8767 14:44:24.195248 [Byte1]: 65
8768 14:44:24.199928
8769 14:44:24.200048 Set Vref, RX VrefLevel [Byte0]: 66
8770 14:44:24.203316 [Byte1]: 66
8771 14:44:24.207390
8772 14:44:24.207508 Set Vref, RX VrefLevel [Byte0]: 67
8773 14:44:24.210618 [Byte1]: 67
8774 14:44:24.214890
8775 14:44:24.215010 Set Vref, RX VrefLevel [Byte0]: 68
8776 14:44:24.218215 [Byte1]: 68
8777 14:44:24.222788
8778 14:44:24.222908 Set Vref, RX VrefLevel [Byte0]: 69
8779 14:44:24.225737 [Byte1]: 69
8780 14:44:24.230616
8781 14:44:24.230737 Set Vref, RX VrefLevel [Byte0]: 70
8782 14:44:24.233518 [Byte1]: 70
8783 14:44:24.238120
8784 14:44:24.238235 Set Vref, RX VrefLevel [Byte0]: 71
8785 14:44:24.241345 [Byte1]: 71
8786 14:44:24.245495
8787 14:44:24.245617 Final RX Vref Byte 0 = 62 to rank0
8788 14:44:24.248442 Final RX Vref Byte 1 = 52 to rank0
8789 14:44:24.252107 Final RX Vref Byte 0 = 62 to rank1
8790 14:44:24.255223 Final RX Vref Byte 1 = 52 to rank1==
8791 14:44:24.258702 Dram Type= 6, Freq= 0, CH_1, rank 0
8792 14:44:24.265097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 14:44:24.265221 ==
8794 14:44:24.265335 DQS Delay:
8795 14:44:24.268477 DQS0 = 0, DQS1 = 0
8796 14:44:24.268607 DQM Delay:
8797 14:44:24.268721 DQM0 = 131, DQM1 = 123
8798 14:44:24.271609 DQ Delay:
8799 14:44:24.275591 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8800 14:44:24.278338 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =126
8801 14:44:24.281978 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8802 14:44:24.285133 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =132
8803 14:44:24.285218
8804 14:44:24.285283
8805 14:44:24.285344
8806 14:44:24.288486 [DramC_TX_OE_Calibration] TA2
8807 14:44:24.291882 Original DQ_B0 (3 6) =30, OEN = 27
8808 14:44:24.295135 Original DQ_B1 (3 6) =30, OEN = 27
8809 14:44:24.298576 24, 0x0, End_B0=24 End_B1=24
8810 14:44:24.298679 25, 0x0, End_B0=25 End_B1=25
8811 14:44:24.301529 26, 0x0, End_B0=26 End_B1=26
8812 14:44:24.304764 27, 0x0, End_B0=27 End_B1=27
8813 14:44:24.308318 28, 0x0, End_B0=28 End_B1=28
8814 14:44:24.311512 29, 0x0, End_B0=29 End_B1=29
8815 14:44:24.311610 30, 0x0, End_B0=30 End_B1=30
8816 14:44:24.314724 31, 0x4141, End_B0=30 End_B1=30
8817 14:44:24.318369 Byte0 end_step=30 best_step=27
8818 14:44:24.321659 Byte1 end_step=30 best_step=27
8819 14:44:24.325058 Byte0 TX OE(2T, 0.5T) = (3, 3)
8820 14:44:24.328464 Byte1 TX OE(2T, 0.5T) = (3, 3)
8821 14:44:24.328548
8822 14:44:24.328627
8823 14:44:24.334618 [DQSOSCAuto] RK0, (LSB)MR18= 0x60b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8824 14:44:24.338212 CH1 RK0: MR19=303, MR18=60B
8825 14:44:24.345111 CH1_RK0: MR19=0x303, MR18=0x60B, DQSOSC=404, MR23=63, INC=22, DEC=15
8826 14:44:24.345195
8827 14:44:24.347731 ----->DramcWriteLeveling(PI) begin...
8828 14:44:24.347813 ==
8829 14:44:24.351415 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 14:44:24.354436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 14:44:24.354608 ==
8832 14:44:24.358132 Write leveling (Byte 0): 24 => 24
8833 14:44:24.361012 Write leveling (Byte 1): 29 => 29
8834 14:44:24.364643 DramcWriteLeveling(PI) end<-----
8835 14:44:24.364765
8836 14:44:24.364877 ==
8837 14:44:24.367779 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 14:44:24.371002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 14:44:24.371104 ==
8840 14:44:24.374318 [Gating] SW mode calibration
8841 14:44:24.380882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8842 14:44:24.387726 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8843 14:44:24.390776 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 14:44:24.397378 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 14:44:24.401105 1 4 8 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
8846 14:44:24.404215 1 4 12 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
8847 14:44:24.411051 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 14:44:24.413896 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 14:44:24.417328 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 14:44:24.424129 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 14:44:24.427596 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 14:44:24.430515 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8853 14:44:24.433800 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
8854 14:44:24.440367 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
8855 14:44:24.443688 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 14:44:24.447158 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 14:44:24.454119 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 14:44:24.457332 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 14:44:24.460545 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 14:44:24.467462 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 14:44:24.470211 1 6 8 | B1->B0 | 2626 4241 | 0 1 | (0 0) (0 0)
8862 14:44:24.473610 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8863 14:44:24.480269 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 14:44:24.483604 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 14:44:24.487081 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 14:44:24.494039 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 14:44:24.497362 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 14:44:24.500052 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 14:44:24.506699 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8870 14:44:24.510424 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8871 14:44:24.513521 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 14:44:24.520202 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 14:44:24.523698 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 14:44:24.526959 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 14:44:24.533435 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 14:44:24.536808 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 14:44:24.540288 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 14:44:24.546835 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 14:44:24.550377 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 14:44:24.553128 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 14:44:24.559886 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 14:44:24.563475 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 14:44:24.566736 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 14:44:24.573084 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 14:44:24.576420 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8886 14:44:24.579673 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8887 14:44:24.583258 Total UI for P1: 0, mck2ui 16
8888 14:44:24.586446 best dqsien dly found for B0: ( 1, 9, 8)
8889 14:44:24.592990 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 14:44:24.593068 Total UI for P1: 0, mck2ui 16
8891 14:44:24.599535 best dqsien dly found for B1: ( 1, 9, 10)
8892 14:44:24.603264 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8893 14:44:24.606501 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8894 14:44:24.606619
8895 14:44:24.609402 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8896 14:44:24.612735 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8897 14:44:24.615975 [Gating] SW calibration Done
8898 14:44:24.616107 ==
8899 14:44:24.619496 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 14:44:24.622594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 14:44:24.622720 ==
8902 14:44:24.626324 RX Vref Scan: 0
8903 14:44:24.626447
8904 14:44:24.626557 RX Vref 0 -> 0, step: 1
8905 14:44:24.626666
8906 14:44:24.629089 RX Delay 0 -> 252, step: 8
8907 14:44:24.632744 iDelay=200, Bit 0, Center 135 (72 ~ 199) 128
8908 14:44:24.639233 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8909 14:44:24.642712 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8910 14:44:24.646173 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8911 14:44:24.649283 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8912 14:44:24.652741 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8913 14:44:24.659150 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8914 14:44:24.662475 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8915 14:44:24.665836 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8916 14:44:24.668692 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8917 14:44:24.672103 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8918 14:44:24.678909 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8919 14:44:24.682135 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8920 14:44:24.685561 iDelay=200, Bit 13, Center 135 (72 ~ 199) 128
8921 14:44:24.688941 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8922 14:44:24.692232 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8923 14:44:24.695286 ==
8924 14:44:24.698607 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 14:44:24.701885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 14:44:24.701991 ==
8927 14:44:24.702085 DQS Delay:
8928 14:44:24.705253 DQS0 = 0, DQS1 = 0
8929 14:44:24.705352 DQM Delay:
8930 14:44:24.708643 DQM0 = 129, DQM1 = 126
8931 14:44:24.708745 DQ Delay:
8932 14:44:24.711632 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =127
8933 14:44:24.715022 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8934 14:44:24.718815 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8935 14:44:24.721698 DQ12 =131, DQ13 =135, DQ14 =131, DQ15 =135
8936 14:44:24.721808
8937 14:44:24.721901
8938 14:44:24.725515 ==
8939 14:44:24.725624 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 14:44:24.732059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 14:44:24.732170 ==
8942 14:44:24.732267
8943 14:44:24.732357
8944 14:44:24.735356 TX Vref Scan disable
8945 14:44:24.735464 == TX Byte 0 ==
8946 14:44:24.738260 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8947 14:44:24.744879 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8948 14:44:24.744970 == TX Byte 1 ==
8949 14:44:24.748188 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8950 14:44:24.755095 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8951 14:44:24.755207 ==
8952 14:44:24.758468 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 14:44:24.761383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 14:44:24.761492 ==
8955 14:44:24.775100
8956 14:44:24.777857 TX Vref early break, caculate TX vref
8957 14:44:24.781504 TX Vref=16, minBit 8, minWin=22, winSum=380
8958 14:44:24.784956 TX Vref=18, minBit 9, minWin=22, winSum=386
8959 14:44:24.788271 TX Vref=20, minBit 8, minWin=23, winSum=395
8960 14:44:24.791481 TX Vref=22, minBit 0, minWin=24, winSum=407
8961 14:44:24.794800 TX Vref=24, minBit 11, minWin=24, winSum=411
8962 14:44:24.801119 TX Vref=26, minBit 0, minWin=25, winSum=418
8963 14:44:24.804435 TX Vref=28, minBit 5, minWin=25, winSum=423
8964 14:44:24.808039 TX Vref=30, minBit 0, minWin=24, winSum=415
8965 14:44:24.811337 TX Vref=32, minBit 8, minWin=23, winSum=405
8966 14:44:24.814255 TX Vref=34, minBit 1, minWin=23, winSum=397
8967 14:44:24.821046 [TxChooseVref] Worse bit 5, Min win 25, Win sum 423, Final Vref 28
8968 14:44:24.821131
8969 14:44:24.824535 Final TX Range 0 Vref 28
8970 14:44:24.824622
8971 14:44:24.824686 ==
8972 14:44:24.827701 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 14:44:24.830744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 14:44:24.830845 ==
8975 14:44:24.830937
8976 14:44:24.831025
8977 14:44:24.834586 TX Vref Scan disable
8978 14:44:24.841063 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8979 14:44:24.841153 == TX Byte 0 ==
8980 14:44:24.844354 u2DelayCellOfst[0]=22 cells (6 PI)
8981 14:44:24.847266 u2DelayCellOfst[1]=15 cells (4 PI)
8982 14:44:24.850718 u2DelayCellOfst[2]=0 cells (0 PI)
8983 14:44:24.853966 u2DelayCellOfst[3]=7 cells (2 PI)
8984 14:44:24.857612 u2DelayCellOfst[4]=11 cells (3 PI)
8985 14:44:24.860971 u2DelayCellOfst[5]=26 cells (7 PI)
8986 14:44:24.864338 u2DelayCellOfst[6]=22 cells (6 PI)
8987 14:44:24.867313 u2DelayCellOfst[7]=7 cells (2 PI)
8988 14:44:24.870796 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8989 14:44:24.874311 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8990 14:44:24.877056 == TX Byte 1 ==
8991 14:44:24.880697 u2DelayCellOfst[8]=0 cells (0 PI)
8992 14:44:24.883681 u2DelayCellOfst[9]=7 cells (2 PI)
8993 14:44:24.887155 u2DelayCellOfst[10]=15 cells (4 PI)
8994 14:44:24.887238 u2DelayCellOfst[11]=7 cells (2 PI)
8995 14:44:24.890602 u2DelayCellOfst[12]=18 cells (5 PI)
8996 14:44:24.893923 u2DelayCellOfst[13]=18 cells (5 PI)
8997 14:44:24.897354 u2DelayCellOfst[14]=22 cells (6 PI)
8998 14:44:24.900399 u2DelayCellOfst[15]=22 cells (6 PI)
8999 14:44:24.907160 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
9000 14:44:24.910062 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
9001 14:44:24.910151 DramC Write-DBI on
9002 14:44:24.913417 ==
9003 14:44:24.913522 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 14:44:24.920184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 14:44:24.920266 ==
9006 14:44:24.920333
9007 14:44:24.920401
9008 14:44:24.923429 TX Vref Scan disable
9009 14:44:24.923529 == TX Byte 0 ==
9010 14:44:24.930310 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9011 14:44:24.930389 == TX Byte 1 ==
9012 14:44:24.933408 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9013 14:44:24.936433 DramC Write-DBI off
9014 14:44:24.936530
9015 14:44:24.936629 [DATLAT]
9016 14:44:24.939959 Freq=1600, CH1 RK1
9017 14:44:24.940065
9018 14:44:24.940157 DATLAT Default: 0xf
9019 14:44:24.943145 0, 0xFFFF, sum = 0
9020 14:44:24.943248 1, 0xFFFF, sum = 0
9021 14:44:24.946758 2, 0xFFFF, sum = 0
9022 14:44:24.946835 3, 0xFFFF, sum = 0
9023 14:44:24.950022 4, 0xFFFF, sum = 0
9024 14:44:24.950103 5, 0xFFFF, sum = 0
9025 14:44:24.953410 6, 0xFFFF, sum = 0
9026 14:44:24.953529 7, 0xFFFF, sum = 0
9027 14:44:24.956230 8, 0xFFFF, sum = 0
9028 14:44:24.956343 9, 0xFFFF, sum = 0
9029 14:44:24.959870 10, 0xFFFF, sum = 0
9030 14:44:24.962987 11, 0xFFFF, sum = 0
9031 14:44:24.963093 12, 0xFFFF, sum = 0
9032 14:44:24.966414 13, 0x8FFF, sum = 0
9033 14:44:24.966531 14, 0x0, sum = 1
9034 14:44:24.969791 15, 0x0, sum = 2
9035 14:44:24.969906 16, 0x0, sum = 3
9036 14:44:24.973157 17, 0x0, sum = 4
9037 14:44:24.973260 best_step = 15
9038 14:44:24.973359
9039 14:44:24.973448 ==
9040 14:44:24.976567 Dram Type= 6, Freq= 0, CH_1, rank 1
9041 14:44:24.980076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9042 14:44:24.980181 ==
9043 14:44:24.982822 RX Vref Scan: 0
9044 14:44:24.982928
9045 14:44:24.986254 RX Vref 0 -> 0, step: 1
9046 14:44:24.986360
9047 14:44:24.986453 RX Delay 3 -> 252, step: 4
9048 14:44:24.993151 iDelay=195, Bit 0, Center 134 (79 ~ 190) 112
9049 14:44:24.996550 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9050 14:44:25.000020 iDelay=195, Bit 2, Center 116 (59 ~ 174) 116
9051 14:44:25.003465 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9052 14:44:25.006358 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
9053 14:44:25.013203 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9054 14:44:25.016526 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9055 14:44:25.020298 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9056 14:44:25.023388 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9057 14:44:25.026723 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9058 14:44:25.033745 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9059 14:44:25.036647 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9060 14:44:25.040012 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9061 14:44:25.043235 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9062 14:44:25.050038 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9063 14:44:25.053161 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9064 14:44:25.053263 ==
9065 14:44:25.056913 Dram Type= 6, Freq= 0, CH_1, rank 1
9066 14:44:25.059948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9067 14:44:25.060040 ==
9068 14:44:25.060107 DQS Delay:
9069 14:44:25.063305 DQS0 = 0, DQS1 = 0
9070 14:44:25.063410 DQM Delay:
9071 14:44:25.066471 DQM0 = 128, DQM1 = 125
9072 14:44:25.066560 DQ Delay:
9073 14:44:25.069905 DQ0 =134, DQ1 =126, DQ2 =116, DQ3 =124
9074 14:44:25.073164 DQ4 =122, DQ5 =138, DQ6 =140, DQ7 =126
9075 14:44:25.076075 DQ8 =108, DQ9 =114, DQ10 =128, DQ11 =120
9076 14:44:25.082756 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =134
9077 14:44:25.082872
9078 14:44:25.082969
9079 14:44:25.083059
9080 14:44:25.086330 [DramC_TX_OE_Calibration] TA2
9081 14:44:25.086412 Original DQ_B0 (3 6) =30, OEN = 27
9082 14:44:25.089245 Original DQ_B1 (3 6) =30, OEN = 27
9083 14:44:25.092709 24, 0x0, End_B0=24 End_B1=24
9084 14:44:25.096138 25, 0x0, End_B0=25 End_B1=25
9085 14:44:25.099508 26, 0x0, End_B0=26 End_B1=26
9086 14:44:25.099592 27, 0x0, End_B0=27 End_B1=27
9087 14:44:25.102887 28, 0x0, End_B0=28 End_B1=28
9088 14:44:25.106336 29, 0x0, End_B0=29 End_B1=29
9089 14:44:25.109828 30, 0x0, End_B0=30 End_B1=30
9090 14:44:25.113238 31, 0x4141, End_B0=30 End_B1=30
9091 14:44:25.116071 Byte0 end_step=30 best_step=27
9092 14:44:25.116154 Byte1 end_step=30 best_step=27
9093 14:44:25.119334 Byte0 TX OE(2T, 0.5T) = (3, 3)
9094 14:44:25.122751 Byte1 TX OE(2T, 0.5T) = (3, 3)
9095 14:44:25.122833
9096 14:44:25.122898
9097 14:44:25.132644 [DQSOSCAuto] RK1, (LSB)MR18= 0xe19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
9098 14:44:25.132757 CH1 RK1: MR19=303, MR18=E19
9099 14:44:25.139118 CH1_RK1: MR19=0x303, MR18=0xE19, DQSOSC=397, MR23=63, INC=23, DEC=15
9100 14:44:25.142622 [RxdqsGatingPostProcess] freq 1600
9101 14:44:25.149328 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9102 14:44:25.152576 best DQS0 dly(2T, 0.5T) = (1, 1)
9103 14:44:25.155592 best DQS1 dly(2T, 0.5T) = (1, 1)
9104 14:44:25.158898 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9105 14:44:25.158984 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9106 14:44:25.162539 best DQS0 dly(2T, 0.5T) = (1, 1)
9107 14:44:25.165547 best DQS1 dly(2T, 0.5T) = (1, 1)
9108 14:44:25.168775 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9109 14:44:25.172610 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9110 14:44:25.175484 Pre-setting of DQS Precalculation
9111 14:44:25.182688 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9112 14:44:25.188928 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9113 14:44:25.195523 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9114 14:44:25.195609
9115 14:44:25.195675
9116 14:44:25.198948 [Calibration Summary] 3200 Mbps
9117 14:44:25.199031 CH 0, Rank 0
9118 14:44:25.202069 SW Impedance : PASS
9119 14:44:25.205554 DUTY Scan : NO K
9120 14:44:25.205636 ZQ Calibration : PASS
9121 14:44:25.208679 Jitter Meter : NO K
9122 14:44:25.212077 CBT Training : PASS
9123 14:44:25.212160 Write leveling : PASS
9124 14:44:25.215607 RX DQS gating : PASS
9125 14:44:25.215690 RX DQ/DQS(RDDQC) : PASS
9126 14:44:25.219180 TX DQ/DQS : PASS
9127 14:44:25.222032 RX DATLAT : PASS
9128 14:44:25.222115 RX DQ/DQS(Engine): PASS
9129 14:44:25.225383 TX OE : PASS
9130 14:44:25.225489 All Pass.
9131 14:44:25.225577
9132 14:44:25.229018 CH 0, Rank 1
9133 14:44:25.229128 SW Impedance : PASS
9134 14:44:25.231860 DUTY Scan : NO K
9135 14:44:25.235331 ZQ Calibration : PASS
9136 14:44:25.235413 Jitter Meter : NO K
9137 14:44:25.238650 CBT Training : PASS
9138 14:44:25.241730 Write leveling : PASS
9139 14:44:25.241812 RX DQS gating : PASS
9140 14:44:25.245386 RX DQ/DQS(RDDQC) : PASS
9141 14:44:25.248455 TX DQ/DQS : PASS
9142 14:44:25.248537 RX DATLAT : PASS
9143 14:44:25.252029 RX DQ/DQS(Engine): PASS
9144 14:44:25.254998 TX OE : PASS
9145 14:44:25.255129 All Pass.
9146 14:44:25.255248
9147 14:44:25.255363 CH 1, Rank 0
9148 14:44:25.258195 SW Impedance : PASS
9149 14:44:25.261623 DUTY Scan : NO K
9150 14:44:25.261746 ZQ Calibration : PASS
9151 14:44:25.265280 Jitter Meter : NO K
9152 14:44:25.268620 CBT Training : PASS
9153 14:44:25.268741 Write leveling : PASS
9154 14:44:25.271732 RX DQS gating : PASS
9155 14:44:25.271858 RX DQ/DQS(RDDQC) : PASS
9156 14:44:25.274938 TX DQ/DQS : PASS
9157 14:44:25.278665 RX DATLAT : PASS
9158 14:44:25.278789 RX DQ/DQS(Engine): PASS
9159 14:44:25.281866 TX OE : PASS
9160 14:44:25.281986 All Pass.
9161 14:44:25.282097
9162 14:44:25.285271 CH 1, Rank 1
9163 14:44:25.285394 SW Impedance : PASS
9164 14:44:25.288574 DUTY Scan : NO K
9165 14:44:25.291626 ZQ Calibration : PASS
9166 14:44:25.291752 Jitter Meter : NO K
9167 14:44:25.295018 CBT Training : PASS
9168 14:44:25.298507 Write leveling : PASS
9169 14:44:25.298592 RX DQS gating : PASS
9170 14:44:25.301702 RX DQ/DQS(RDDQC) : PASS
9171 14:44:25.305265 TX DQ/DQS : PASS
9172 14:44:25.305348 RX DATLAT : PASS
9173 14:44:25.308539 RX DQ/DQS(Engine): PASS
9174 14:44:25.311522 TX OE : PASS
9175 14:44:25.311605 All Pass.
9176 14:44:25.311670
9177 14:44:25.311731 DramC Write-DBI on
9178 14:44:25.314755 PER_BANK_REFRESH: Hybrid Mode
9179 14:44:25.318278 TX_TRACKING: ON
9180 14:44:25.325242 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9181 14:44:25.334795 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9182 14:44:25.341718 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9183 14:44:25.344923 [FAST_K] Save calibration result to emmc
9184 14:44:25.347768 sync common calibartion params.
9185 14:44:25.351548 sync cbt_mode0:1, 1:1
9186 14:44:25.351635 dram_init: ddr_geometry: 2
9187 14:44:25.354971 dram_init: ddr_geometry: 2
9188 14:44:25.357990 dram_init: ddr_geometry: 2
9189 14:44:25.358072 0:dram_rank_size:100000000
9190 14:44:25.361164 1:dram_rank_size:100000000
9191 14:44:25.367923 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9192 14:44:25.371367 DFS_SHUFFLE_HW_MODE: ON
9193 14:44:25.374635 dramc_set_vcore_voltage set vcore to 725000
9194 14:44:25.374720 Read voltage for 1600, 0
9195 14:44:25.377935 Vio18 = 0
9196 14:44:25.378018 Vcore = 725000
9197 14:44:25.378084 Vdram = 0
9198 14:44:25.381769 Vddq = 0
9199 14:44:25.381851 Vmddr = 0
9200 14:44:25.384820 switch to 3200 Mbps bootup
9201 14:44:25.384903 [DramcRunTimeConfig]
9202 14:44:25.384967 PHYPLL
9203 14:44:25.387967 DPM_CONTROL_AFTERK: ON
9204 14:44:25.391261 PER_BANK_REFRESH: ON
9205 14:44:25.391344 REFRESH_OVERHEAD_REDUCTION: ON
9206 14:44:25.395003 CMD_PICG_NEW_MODE: OFF
9207 14:44:25.398142 XRTWTW_NEW_MODE: ON
9208 14:44:25.398225 XRTRTR_NEW_MODE: ON
9209 14:44:25.401188 TX_TRACKING: ON
9210 14:44:25.401296 RDSEL_TRACKING: OFF
9211 14:44:25.404660 DQS Precalculation for DVFS: ON
9212 14:44:25.404744 RX_TRACKING: OFF
9213 14:44:25.407678 HW_GATING DBG: ON
9214 14:44:25.407761 ZQCS_ENABLE_LP4: ON
9215 14:44:25.411008 RX_PICG_NEW_MODE: ON
9216 14:44:25.414516 TX_PICG_NEW_MODE: ON
9217 14:44:25.414602 ENABLE_RX_DCM_DPHY: ON
9218 14:44:25.417475 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9219 14:44:25.420957 DUMMY_READ_FOR_TRACKING: OFF
9220 14:44:25.424341 !!! SPM_CONTROL_AFTERK: OFF
9221 14:44:25.427708 !!! SPM could not control APHY
9222 14:44:25.427835 IMPEDANCE_TRACKING: ON
9223 14:44:25.430744 TEMP_SENSOR: ON
9224 14:44:25.430869 HW_SAVE_FOR_SR: OFF
9225 14:44:25.434294 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9226 14:44:25.437717 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9227 14:44:25.440950 Read ODT Tracking: ON
9228 14:44:25.443829 Refresh Rate DeBounce: ON
9229 14:44:25.443950 DFS_NO_QUEUE_FLUSH: ON
9230 14:44:25.447345 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9231 14:44:25.450619 ENABLE_DFS_RUNTIME_MRW: OFF
9232 14:44:25.454124 DDR_RESERVE_NEW_MODE: ON
9233 14:44:25.454247 MR_CBT_SWITCH_FREQ: ON
9234 14:44:25.457032 =========================
9235 14:44:25.475812 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9236 14:44:25.479027 dram_init: ddr_geometry: 2
9237 14:44:25.497232 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9238 14:44:25.500594 dram_init: dram init end (result: 0)
9239 14:44:25.507342 DRAM-K: Full calibration passed in 24598 msecs
9240 14:44:25.510382 MRC: failed to locate region type 0.
9241 14:44:25.510464 DRAM rank0 size:0x100000000,
9242 14:44:25.513539 DRAM rank1 size=0x100000000
9243 14:44:25.523651 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9244 14:44:25.530459 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9245 14:44:25.537371 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9246 14:44:25.543551 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9247 14:44:25.547106 DRAM rank0 size:0x100000000,
9248 14:44:25.550529 DRAM rank1 size=0x100000000
9249 14:44:25.550613 CBMEM:
9250 14:44:25.553700 IMD: root @ 0xfffff000 254 entries.
9251 14:44:25.557153 IMD: root @ 0xffffec00 62 entries.
9252 14:44:25.560496 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9253 14:44:25.566533 WARNING: RO_VPD is uninitialized or empty.
9254 14:44:25.570099 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9255 14:44:25.577183 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9256 14:44:25.589946 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9257 14:44:25.601550 BS: romstage times (exec / console): total (unknown) / 24056 ms
9258 14:44:25.601689
9259 14:44:25.601803
9260 14:44:25.611540 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9261 14:44:25.614824 ARM64: Exception handlers installed.
9262 14:44:25.617896 ARM64: Testing exception
9263 14:44:25.621116 ARM64: Done test exception
9264 14:44:25.621239 Enumerating buses...
9265 14:44:25.624751 Show all devs... Before device enumeration.
9266 14:44:25.627923 Root Device: enabled 1
9267 14:44:25.631386 CPU_CLUSTER: 0: enabled 1
9268 14:44:25.631470 CPU: 00: enabled 1
9269 14:44:25.634309 Compare with tree...
9270 14:44:25.634440 Root Device: enabled 1
9271 14:44:25.637863 CPU_CLUSTER: 0: enabled 1
9272 14:44:25.641450 CPU: 00: enabled 1
9273 14:44:25.641532 Root Device scanning...
9274 14:44:25.644698 scan_static_bus for Root Device
9275 14:44:25.647665 CPU_CLUSTER: 0 enabled
9276 14:44:25.651128 scan_static_bus for Root Device done
9277 14:44:25.654510 scan_bus: bus Root Device finished in 8 msecs
9278 14:44:25.654601 done
9279 14:44:25.661396 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9280 14:44:25.664305 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9281 14:44:25.671061 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9282 14:44:25.674506 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9283 14:44:25.677717 Allocating resources...
9284 14:44:25.681033 Reading resources...
9285 14:44:25.684185 Root Device read_resources bus 0 link: 0
9286 14:44:25.684267 DRAM rank0 size:0x100000000,
9287 14:44:25.687822 DRAM rank1 size=0x100000000
9288 14:44:25.691203 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9289 14:44:25.694037 CPU: 00 missing read_resources
9290 14:44:25.700805 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9291 14:44:25.703931 Root Device read_resources bus 0 link: 0 done
9292 14:44:25.704090 Done reading resources.
9293 14:44:25.710740 Show resources in subtree (Root Device)...After reading.
9294 14:44:25.714193 Root Device child on link 0 CPU_CLUSTER: 0
9295 14:44:25.717696 CPU_CLUSTER: 0 child on link 0 CPU: 00
9296 14:44:25.727358 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9297 14:44:25.727499 CPU: 00
9298 14:44:25.730685 Root Device assign_resources, bus 0 link: 0
9299 14:44:25.733655 CPU_CLUSTER: 0 missing set_resources
9300 14:44:25.740287 Root Device assign_resources, bus 0 link: 0 done
9301 14:44:25.740423 Done setting resources.
9302 14:44:25.747115 Show resources in subtree (Root Device)...After assigning values.
9303 14:44:25.750597 Root Device child on link 0 CPU_CLUSTER: 0
9304 14:44:25.753941 CPU_CLUSTER: 0 child on link 0 CPU: 00
9305 14:44:25.763807 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9306 14:44:25.763945 CPU: 00
9307 14:44:25.766733 Done allocating resources.
9308 14:44:25.773621 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9309 14:44:25.773754 Enabling resources...
9310 14:44:25.773875 done.
9311 14:44:25.780439 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9312 14:44:25.780572 Initializing devices...
9313 14:44:25.783321 Root Device init
9314 14:44:25.783442 init hardware done!
9315 14:44:25.786743 0x00000018: ctrlr->caps
9316 14:44:25.790456 52.000 MHz: ctrlr->f_max
9317 14:44:25.790592 0.400 MHz: ctrlr->f_min
9318 14:44:25.793251 0x40ff8080: ctrlr->voltages
9319 14:44:25.796510 sclk: 390625
9320 14:44:25.796657 Bus Width = 1
9321 14:44:25.796784 sclk: 390625
9322 14:44:25.800180 Bus Width = 1
9323 14:44:25.800309 Early init status = 3
9324 14:44:25.806698 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9325 14:44:25.809873 in-header: 03 fc 00 00 01 00 00 00
9326 14:44:25.813071 in-data: 00
9327 14:44:25.816506 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9328 14:44:25.821185 in-header: 03 fd 00 00 00 00 00 00
9329 14:44:25.823848 in-data:
9330 14:44:25.827440 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9331 14:44:25.831328 in-header: 03 fc 00 00 01 00 00 00
9332 14:44:25.835229 in-data: 00
9333 14:44:25.838417 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9334 14:44:25.844091 in-header: 03 fd 00 00 00 00 00 00
9335 14:44:25.847018 in-data:
9336 14:44:25.850427 [SSUSB] Setting up USB HOST controller...
9337 14:44:25.853802 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9338 14:44:25.857275 [SSUSB] phy power-on done.
9339 14:44:25.860240 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9340 14:44:25.867256 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9341 14:44:25.870074 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9342 14:44:25.876918 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9343 14:44:25.883695 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9344 14:44:25.890014 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9345 14:44:25.896745 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9346 14:44:25.903446 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9347 14:44:25.906697 SPM: binary array size = 0x9dc
9348 14:44:25.909885 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9349 14:44:25.916425 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9350 14:44:25.923293 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9351 14:44:25.929625 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9352 14:44:25.933101 configure_display: Starting display init
9353 14:44:25.966924 anx7625_power_on_init: Init interface.
9354 14:44:25.970429 anx7625_disable_pd_protocol: Disabled PD feature.
9355 14:44:25.973656 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9356 14:44:26.001329 anx7625_start_dp_work: Secure OCM version=00
9357 14:44:26.004648 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9358 14:44:26.019454 sp_tx_get_edid_block: EDID Block = 1
9359 14:44:26.121998 Extracted contents:
9360 14:44:26.125499 header: 00 ff ff ff ff ff ff 00
9361 14:44:26.128592 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9362 14:44:26.131994 version: 01 04
9363 14:44:26.135057 basic params: 95 1f 11 78 0a
9364 14:44:26.138510 chroma info: 76 90 94 55 54 90 27 21 50 54
9365 14:44:26.141835 established: 00 00 00
9366 14:44:26.148789 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9367 14:44:26.152088 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9368 14:44:26.158384 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9369 14:44:26.165103 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9370 14:44:26.171397 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9371 14:44:26.175228 extensions: 00
9372 14:44:26.175333 checksum: fb
9373 14:44:26.175432
9374 14:44:26.178407 Manufacturer: IVO Model 57d Serial Number 0
9375 14:44:26.181374 Made week 0 of 2020
9376 14:44:26.184872 EDID version: 1.4
9377 14:44:26.184965 Digital display
9378 14:44:26.187939 6 bits per primary color channel
9379 14:44:26.188041 DisplayPort interface
9380 14:44:26.191097 Maximum image size: 31 cm x 17 cm
9381 14:44:26.194572 Gamma: 220%
9382 14:44:26.194673 Check DPMS levels
9383 14:44:26.198306 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9384 14:44:26.204690 First detailed timing is preferred timing
9385 14:44:26.204824 Established timings supported:
9386 14:44:26.208083 Standard timings supported:
9387 14:44:26.211507 Detailed timings
9388 14:44:26.214962 Hex of detail: 383680a07038204018303c0035ae10000019
9389 14:44:26.221148 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9390 14:44:26.224447 0780 0798 07c8 0820 hborder 0
9391 14:44:26.227670 0438 043b 0447 0458 vborder 0
9392 14:44:26.231051 -hsync -vsync
9393 14:44:26.231154 Did detailed timing
9394 14:44:26.237822 Hex of detail: 000000000000000000000000000000000000
9395 14:44:26.240811 Manufacturer-specified data, tag 0
9396 14:44:26.244641 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9397 14:44:26.247490 ASCII string: InfoVision
9398 14:44:26.251144 Hex of detail: 000000fe00523134304e574635205248200a
9399 14:44:26.254633 ASCII string: R140NWF5 RH
9400 14:44:26.254748 Checksum
9401 14:44:26.257527 Checksum: 0xfb (valid)
9402 14:44:26.261002 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9403 14:44:26.264364 DSI data_rate: 832800000 bps
9404 14:44:26.270540 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9405 14:44:26.274048 anx7625_parse_edid: pixelclock(138800).
9406 14:44:26.277420 hactive(1920), hsync(48), hfp(24), hbp(88)
9407 14:44:26.280888 vactive(1080), vsync(12), vfp(3), vbp(17)
9408 14:44:26.283735 anx7625_dsi_config: config dsi.
9409 14:44:26.290616 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9410 14:44:26.304437 anx7625_dsi_config: success to config DSI
9411 14:44:26.307321 anx7625_dp_start: MIPI phy setup OK.
9412 14:44:26.311057 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9413 14:44:26.313793 mtk_ddp_mode_set invalid vrefresh 60
9414 14:44:26.317293 main_disp_path_setup
9415 14:44:26.317370 ovl_layer_smi_id_en
9416 14:44:26.320615 ovl_layer_smi_id_en
9417 14:44:26.320695 ccorr_config
9418 14:44:26.320759 aal_config
9419 14:44:26.323872 gamma_config
9420 14:44:26.323983 postmask_config
9421 14:44:26.327317 dither_config
9422 14:44:26.330733 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9423 14:44:26.337457 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9424 14:44:26.340265 Root Device init finished in 553 msecs
9425 14:44:26.343765 CPU_CLUSTER: 0 init
9426 14:44:26.350675 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9427 14:44:26.353666 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9428 14:44:26.356942 APU_MBOX 0x190000b0 = 0x10001
9429 14:44:26.360769 APU_MBOX 0x190001b0 = 0x10001
9430 14:44:26.364134 APU_MBOX 0x190005b0 = 0x10001
9431 14:44:26.367246 APU_MBOX 0x190006b0 = 0x10001
9432 14:44:26.370333 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9433 14:44:26.383263 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9434 14:44:26.395420 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9435 14:44:26.401950 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9436 14:44:26.414085 read SPI 0x61c74 0xe8ef: 6414 us, 9297 KB/s, 74.376 Mbps
9437 14:44:26.423110 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9438 14:44:26.426376 CPU_CLUSTER: 0 init finished in 81 msecs
9439 14:44:26.429822 Devices initialized
9440 14:44:26.432677 Show all devs... After init.
9441 14:44:26.432763 Root Device: enabled 1
9442 14:44:26.436166 CPU_CLUSTER: 0: enabled 1
9443 14:44:26.439439 CPU: 00: enabled 1
9444 14:44:26.443290 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9445 14:44:26.446026 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9446 14:44:26.449292 ELOG: NV offset 0x57f000 size 0x1000
9447 14:44:26.456105 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9448 14:44:26.462823 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9449 14:44:26.466133 ELOG: Event(17) added with size 13 at 2024-06-04 14:44:25 UTC
9450 14:44:26.469475 out: cmd=0x121: 03 db 21 01 00 00 00 00
9451 14:44:26.473556 in-header: 03 44 00 00 2c 00 00 00
9452 14:44:26.486648 in-data: 1a 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9453 14:44:26.493026 ELOG: Event(A1) added with size 10 at 2024-06-04 14:44:25 UTC
9454 14:44:26.499861 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9455 14:44:26.506844 ELOG: Event(A0) added with size 9 at 2024-06-04 14:44:25 UTC
9456 14:44:26.509593 elog_add_boot_reason: Logged dev mode boot
9457 14:44:26.513122 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9458 14:44:26.516663 Finalize devices...
9459 14:44:26.516783 Devices finalized
9460 14:44:26.523252 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9461 14:44:26.526503 Writing coreboot table at 0xffe64000
9462 14:44:26.529869 0. 000000000010a000-0000000000113fff: RAMSTAGE
9463 14:44:26.532847 1. 0000000040000000-00000000400fffff: RAM
9464 14:44:26.539340 2. 0000000040100000-000000004032afff: RAMSTAGE
9465 14:44:26.542599 3. 000000004032b000-00000000545fffff: RAM
9466 14:44:26.546110 4. 0000000054600000-000000005465ffff: BL31
9467 14:44:26.549226 5. 0000000054660000-00000000ffe63fff: RAM
9468 14:44:26.555870 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9469 14:44:26.559202 7. 0000000100000000-000000023fffffff: RAM
9470 14:44:26.559327 Passing 5 GPIOs to payload:
9471 14:44:26.566316 NAME | PORT | POLARITY | VALUE
9472 14:44:26.569275 EC in RW | 0x000000aa | low | undefined
9473 14:44:26.576150 EC interrupt | 0x00000005 | low | undefined
9474 14:44:26.579047 TPM interrupt | 0x000000ab | high | undefined
9475 14:44:26.582458 SD card detect | 0x00000011 | high | undefined
9476 14:44:26.589206 speaker enable | 0x00000093 | high | undefined
9477 14:44:26.592641 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9478 14:44:26.595994 in-header: 03 f9 00 00 02 00 00 00
9479 14:44:26.596115 in-data: 02 00
9480 14:44:26.598855 ADC[4]: Raw value=895191 ID=7
9481 14:44:26.602261 ADC[3]: Raw value=213070 ID=1
9482 14:44:26.605561 RAM Code: 0x71
9483 14:44:26.605684 ADC[6]: Raw value=74722 ID=0
9484 14:44:26.608834 ADC[5]: Raw value=211960 ID=1
9485 14:44:26.611900 SKU Code: 0x1
9486 14:44:26.615383 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 236
9487 14:44:26.618727 coreboot table: 964 bytes.
9488 14:44:26.622005 IMD ROOT 0. 0xfffff000 0x00001000
9489 14:44:26.625323 IMD SMALL 1. 0xffffe000 0x00001000
9490 14:44:26.628448 RO MCACHE 2. 0xffffc000 0x00001104
9491 14:44:26.632252 CONSOLE 3. 0xfff7c000 0x00080000
9492 14:44:26.635220 FMAP 4. 0xfff7b000 0x00000452
9493 14:44:26.638503 TIME STAMP 5. 0xfff7a000 0x00000910
9494 14:44:26.642010 VBOOT WORK 6. 0xfff66000 0x00014000
9495 14:44:26.645250 RAMOOPS 7. 0xffe66000 0x00100000
9496 14:44:26.648670 COREBOOT 8. 0xffe64000 0x00002000
9497 14:44:26.648742 IMD small region:
9498 14:44:26.651471 IMD ROOT 0. 0xffffec00 0x00000400
9499 14:44:26.658143 VPD 1. 0xffffeb80 0x0000006c
9500 14:44:26.661588 MMC STATUS 2. 0xffffeb60 0x00000004
9501 14:44:26.665213 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9502 14:44:26.668551 Probing TPM: done!
9503 14:44:26.671980 Connected to device vid:did:rid of 1ae0:0028:00
9504 14:44:26.681508 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9505 14:44:26.685072 Initialized TPM device CR50 revision 0
9506 14:44:26.688417 Checking cr50 for pending updates
9507 14:44:26.693481 Reading cr50 TPM mode
9508 14:44:26.701439 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9509 14:44:26.707538 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9510 14:44:26.748226 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9511 14:44:26.751438 Checking segment from ROM address 0x40100000
9512 14:44:26.754794 Checking segment from ROM address 0x4010001c
9513 14:44:26.761091 Loading segment from ROM address 0x40100000
9514 14:44:26.761179 code (compression=0)
9515 14:44:26.771340 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9516 14:44:26.777944 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9517 14:44:26.778034 it's not compressed!
9518 14:44:26.784789 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9519 14:44:26.787933 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9520 14:44:26.808241 Loading segment from ROM address 0x4010001c
9521 14:44:26.808333 Entry Point 0x80000000
9522 14:44:26.811859 Loaded segments
9523 14:44:26.815053 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9524 14:44:26.821495 Jumping to boot code at 0x80000000(0xffe64000)
9525 14:44:26.828148 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9526 14:44:26.834976 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9527 14:44:26.842640 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9528 14:44:26.846217 Checking segment from ROM address 0x40100000
9529 14:44:26.849304 Checking segment from ROM address 0x4010001c
9530 14:44:26.855905 Loading segment from ROM address 0x40100000
9531 14:44:26.855996 code (compression=1)
9532 14:44:26.862563 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9533 14:44:26.872527 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9534 14:44:26.872626 using LZMA
9535 14:44:26.881144 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9536 14:44:26.887710 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9537 14:44:26.891074 Loading segment from ROM address 0x4010001c
9538 14:44:26.891152 Entry Point 0x54601000
9539 14:44:26.894391 Loaded segments
9540 14:44:26.897569 NOTICE: MT8192 bl31_setup
9541 14:44:26.904965 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9542 14:44:26.908274 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9543 14:44:26.911216 WARNING: region 0:
9544 14:44:26.914653 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 14:44:26.914736 WARNING: region 1:
9546 14:44:26.921616 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9547 14:44:26.924808 WARNING: region 2:
9548 14:44:26.927953 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9549 14:44:26.931414 WARNING: region 3:
9550 14:44:26.934772 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9551 14:44:26.938214 WARNING: region 4:
9552 14:44:26.945084 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9553 14:44:26.945163 WARNING: region 5:
9554 14:44:26.947868 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9555 14:44:26.951700 WARNING: region 6:
9556 14:44:26.954874 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9557 14:44:26.954955 WARNING: region 7:
9558 14:44:26.961766 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9559 14:44:26.968113 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9560 14:44:26.971582 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9561 14:44:26.974917 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9562 14:44:26.981850 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9563 14:44:26.985204 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9564 14:44:26.988372 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9565 14:44:26.994966 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9566 14:44:26.998366 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9567 14:44:27.001741 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9568 14:44:27.008534 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9569 14:44:27.011646 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9570 14:44:27.018546 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9571 14:44:27.021715 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9572 14:44:27.025373 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9573 14:44:27.031585 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9574 14:44:27.035155 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9575 14:44:27.038622 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9576 14:44:27.045406 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9577 14:44:27.048227 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9578 14:44:27.051819 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9579 14:44:27.058229 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9580 14:44:27.061766 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9581 14:44:27.068401 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9582 14:44:27.071768 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9583 14:44:27.078529 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9584 14:44:27.081876 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9585 14:44:27.085366 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9586 14:44:27.091611 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9587 14:44:27.095351 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9588 14:44:27.098019 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9589 14:44:27.104899 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9590 14:44:27.108303 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9591 14:44:27.111807 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9592 14:44:27.118709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9593 14:44:27.121891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9594 14:44:27.125111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9595 14:44:27.128569 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9596 14:44:27.135396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9597 14:44:27.138635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9598 14:44:27.141816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9599 14:44:27.145120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9600 14:44:27.151735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9601 14:44:27.155127 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9602 14:44:27.158205 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9603 14:44:27.161986 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9604 14:44:27.168154 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9605 14:44:27.171675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9606 14:44:27.174653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9607 14:44:27.181625 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9608 14:44:27.185134 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9609 14:44:27.191297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9610 14:44:27.194770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9611 14:44:27.198241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9612 14:44:27.205087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9613 14:44:27.207871 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9614 14:44:27.214683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9615 14:44:27.218306 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9616 14:44:27.225040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9617 14:44:27.228129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9618 14:44:27.231642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9619 14:44:27.238413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9620 14:44:27.241489 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9621 14:44:27.248064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9622 14:44:27.251432 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9623 14:44:27.258250 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9624 14:44:27.261659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9625 14:44:27.265031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9626 14:44:27.271103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9627 14:44:27.274519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9628 14:44:27.281302 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9629 14:44:27.285104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9630 14:44:27.291548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9631 14:44:27.294878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9632 14:44:27.298220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9633 14:44:27.304675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9634 14:44:27.308122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9635 14:44:27.314950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9636 14:44:27.318337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9637 14:44:27.324541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9638 14:44:27.328061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9639 14:44:27.334915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9640 14:44:27.338162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9641 14:44:27.341463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9642 14:44:27.348095 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9643 14:44:27.351788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9644 14:44:27.358447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9645 14:44:27.361546 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9646 14:44:27.364829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9647 14:44:27.371446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9648 14:44:27.374751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9649 14:44:27.381416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9650 14:44:27.384987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9651 14:44:27.391703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9652 14:44:27.395117 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9653 14:44:27.401217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9654 14:44:27.405194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9655 14:44:27.407895 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9656 14:44:27.411332 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9657 14:44:27.418160 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9658 14:44:27.421595 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9659 14:44:27.425098 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9660 14:44:27.431867 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9661 14:44:27.435229 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9662 14:44:27.438460 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9663 14:44:27.444684 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9664 14:44:27.448263 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9665 14:44:27.454878 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9666 14:44:27.458330 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9667 14:44:27.461544 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9668 14:44:27.467976 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9669 14:44:27.471579 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9670 14:44:27.478395 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9671 14:44:27.481587 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9672 14:44:27.484850 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9673 14:44:27.491186 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9674 14:44:27.494707 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9675 14:44:27.498110 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9676 14:44:27.504933 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9677 14:44:27.508045 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9678 14:44:27.511178 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9679 14:44:27.518095 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9680 14:44:27.521325 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9681 14:44:27.524809 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9682 14:44:27.527734 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9683 14:44:27.534534 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9684 14:44:27.538123 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9685 14:44:27.544836 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9686 14:44:27.548009 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9687 14:44:27.551149 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9688 14:44:27.557627 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9689 14:44:27.560973 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9690 14:44:27.564593 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9691 14:44:27.571016 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9692 14:44:27.574518 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9693 14:44:27.581248 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9694 14:44:27.584478 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9695 14:44:27.587772 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9696 14:44:27.594268 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9697 14:44:27.597602 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9698 14:44:27.604471 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9699 14:44:27.607564 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9700 14:44:27.610973 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9701 14:44:27.617850 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9702 14:44:27.621244 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9703 14:44:27.624288 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9704 14:44:27.630815 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9705 14:44:27.634314 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9706 14:44:27.641246 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9707 14:44:27.644492 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9708 14:44:27.647964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9709 14:44:27.654968 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9710 14:44:27.657713 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9711 14:44:27.664182 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9712 14:44:27.667928 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9713 14:44:27.671016 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9714 14:44:27.677567 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9715 14:44:27.680906 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9716 14:44:27.687479 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9717 14:44:27.691012 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9718 14:44:27.694434 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9719 14:44:27.700868 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9720 14:44:27.704136 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9721 14:44:27.707526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9722 14:44:27.714225 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9723 14:44:27.717630 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9724 14:44:27.724322 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9725 14:44:27.727730 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9726 14:44:27.730732 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9727 14:44:27.737433 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9728 14:44:27.740880 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9729 14:44:27.747658 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9730 14:44:27.750839 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9731 14:44:27.754264 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9732 14:44:27.760427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9733 14:44:27.764210 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9734 14:44:27.770424 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9735 14:44:27.773783 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9736 14:44:27.777251 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9737 14:44:27.783813 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9738 14:44:27.787219 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9739 14:44:27.790481 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9740 14:44:27.797062 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9741 14:44:27.800287 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9742 14:44:27.806939 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9743 14:44:27.810464 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9744 14:44:27.816828 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9745 14:44:27.820084 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9746 14:44:27.823583 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9747 14:44:27.830103 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9748 14:44:27.833315 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9749 14:44:27.840447 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9750 14:44:27.843675 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9751 14:44:27.846578 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9752 14:44:27.853432 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9753 14:44:27.856441 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9754 14:44:27.863206 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9755 14:44:27.866617 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9756 14:44:27.873246 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9757 14:44:27.876609 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9758 14:44:27.879822 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9759 14:44:27.886284 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9760 14:44:27.890094 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9761 14:44:27.896326 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9762 14:44:27.899765 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9763 14:44:27.903425 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9764 14:44:27.909426 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9765 14:44:27.912722 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9766 14:44:27.919902 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9767 14:44:27.923275 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9768 14:44:27.929614 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9769 14:44:27.933047 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9770 14:44:27.936311 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9771 14:44:27.942765 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9772 14:44:27.946125 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9773 14:44:27.952487 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9774 14:44:27.955654 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9775 14:44:27.962243 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9776 14:44:27.965810 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9777 14:44:27.969181 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9778 14:44:27.975688 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9779 14:44:27.978727 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9780 14:44:27.985406 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9781 14:44:27.989168 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9782 14:44:27.995621 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9783 14:44:27.998911 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9784 14:44:28.002251 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9785 14:44:28.008548 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9786 14:44:28.011840 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9787 14:44:28.018587 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9788 14:44:28.022372 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9789 14:44:28.025273 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9790 14:44:28.028491 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9791 14:44:28.032223 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9792 14:44:28.039046 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9793 14:44:28.041942 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9794 14:44:28.045340 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9795 14:44:28.051674 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9796 14:44:28.055177 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9797 14:44:28.062113 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9798 14:44:28.064855 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9799 14:44:28.068118 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9800 14:44:28.074963 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9801 14:44:28.078245 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9802 14:44:28.081394 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9803 14:44:28.088302 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9804 14:44:28.091961 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9805 14:44:28.098467 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9806 14:44:28.101570 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9807 14:44:28.104892 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9808 14:44:28.111352 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9809 14:44:28.114636 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9810 14:44:28.118431 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9811 14:44:28.124746 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9812 14:44:28.128134 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9813 14:44:28.131332 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9814 14:44:28.138186 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9815 14:44:28.141223 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9816 14:44:28.147723 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9817 14:44:28.151119 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9818 14:44:28.154396 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9819 14:44:28.161272 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9820 14:44:28.164737 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9821 14:44:28.170849 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9822 14:44:28.174260 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9823 14:44:28.177443 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9824 14:44:28.184254 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9825 14:44:28.187321 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9826 14:44:28.190810 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9827 14:44:28.197276 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9828 14:44:28.200536 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9829 14:44:28.203890 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9830 14:44:28.207405 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9831 14:44:28.213948 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9832 14:44:28.217349 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9833 14:44:28.220771 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9834 14:44:28.223578 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9835 14:44:28.230534 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9836 14:44:28.233988 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9837 14:44:28.237078 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9838 14:44:28.240496 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9839 14:44:28.247206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9840 14:44:28.250596 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9841 14:44:28.253792 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9842 14:44:28.260722 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9843 14:44:28.263464 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9844 14:44:28.269976 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9845 14:44:28.273256 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9846 14:44:28.280128 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9847 14:44:28.283670 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9848 14:44:28.287135 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9849 14:44:28.293287 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9850 14:44:28.296503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9851 14:44:28.300284 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9852 14:44:28.306492 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9853 14:44:28.309846 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9854 14:44:28.316769 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9855 14:44:28.319951 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9856 14:44:28.323187 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9857 14:44:28.329967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9858 14:44:28.333192 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9859 14:44:28.339676 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9860 14:44:28.343150 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9861 14:44:28.349887 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9862 14:44:28.353129 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9863 14:44:28.356782 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9864 14:44:28.363367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9865 14:44:28.366599 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9866 14:44:28.373133 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9867 14:44:28.376491 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9868 14:44:28.379878 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9869 14:44:28.386200 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9870 14:44:28.389735 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9871 14:44:28.395951 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9872 14:44:28.399400 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9873 14:44:28.402702 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9874 14:44:28.409445 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9875 14:44:28.412534 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9876 14:44:28.419498 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9877 14:44:28.422368 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9878 14:44:28.429172 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9879 14:44:28.432657 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9880 14:44:28.435848 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9881 14:44:28.442634 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9882 14:44:28.445713 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9883 14:44:28.452201 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9884 14:44:28.455485 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9885 14:44:28.462153 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9886 14:44:28.465610 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9887 14:44:28.469075 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9888 14:44:28.475292 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9889 14:44:28.478883 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9890 14:44:28.485283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9891 14:44:28.488757 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9892 14:44:28.492068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9893 14:44:28.499121 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9894 14:44:28.501868 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9895 14:44:28.508762 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9896 14:44:28.511637 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9897 14:44:28.515166 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9898 14:44:28.522008 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9899 14:44:28.525218 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9900 14:44:28.531901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9901 14:44:28.535291 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9902 14:44:28.541618 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9903 14:44:28.544884 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9904 14:44:28.548584 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9905 14:44:28.555262 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9906 14:44:28.558141 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9907 14:44:28.564948 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9908 14:44:28.568261 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9909 14:44:28.571402 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9910 14:44:28.578224 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9911 14:44:28.581563 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9912 14:44:28.588266 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9913 14:44:28.591227 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9914 14:44:28.594566 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9915 14:44:28.601424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9916 14:44:28.604764 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9917 14:44:28.611073 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9918 14:44:28.614340 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9919 14:44:28.621132 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9920 14:44:28.624546 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9921 14:44:28.631264 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9922 14:44:28.634306 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9923 14:44:28.637727 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9924 14:44:28.644034 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9925 14:44:28.647377 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9926 14:44:28.653947 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9927 14:44:28.657312 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9928 14:44:28.664156 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9929 14:44:28.667434 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9930 14:44:28.673910 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9931 14:44:28.677215 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9932 14:44:28.680661 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9933 14:44:28.687345 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9934 14:44:28.690689 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9935 14:44:28.697223 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9936 14:44:28.700450 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9937 14:44:28.707225 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9938 14:44:28.710921 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9939 14:44:28.713618 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9940 14:44:28.720357 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9941 14:44:28.723781 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9942 14:44:28.730442 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9943 14:44:28.733828 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9944 14:44:28.740584 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9945 14:44:28.743694 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9946 14:44:28.746918 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9947 14:44:28.753686 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9948 14:44:28.756865 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9949 14:44:28.763600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9950 14:44:28.766947 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9951 14:44:28.773864 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9952 14:44:28.777096 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9953 14:44:28.783073 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9954 14:44:28.786638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9955 14:44:28.789960 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9956 14:44:28.796591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9957 14:44:28.799897 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9958 14:44:28.806484 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9959 14:44:28.810144 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9960 14:44:28.816307 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9961 14:44:28.819635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9962 14:44:28.822865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9963 14:44:28.829625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9964 14:44:28.832992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9965 14:44:28.839761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9966 14:44:28.843205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9967 14:44:28.849661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9968 14:44:28.853210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9969 14:44:28.859633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9970 14:44:28.862837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9971 14:44:28.869467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9972 14:44:28.872764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9973 14:44:28.879244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9974 14:44:28.882532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9975 14:44:28.889545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9976 14:44:28.892332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9977 14:44:28.899012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9978 14:44:28.902529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9979 14:44:28.909066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9980 14:44:28.912466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9981 14:44:28.918848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9982 14:44:28.922496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9983 14:44:28.928914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9984 14:44:28.932245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9985 14:44:28.939273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9986 14:44:28.942227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9987 14:44:28.948813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9988 14:44:28.952191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9989 14:44:28.958629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9990 14:44:28.961869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9991 14:44:28.968564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9992 14:44:28.971822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9993 14:44:28.975585 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9994 14:44:28.978329 INFO: [APUAPC] vio 0
9995 14:44:28.985142 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9996 14:44:28.988444 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9997 14:44:28.991889 INFO: [APUAPC] D0_APC_0: 0x400510
9998 14:44:28.995338 INFO: [APUAPC] D0_APC_1: 0x0
9999 14:44:28.998133 INFO: [APUAPC] D0_APC_2: 0x1540
10000 14:44:29.001740 INFO: [APUAPC] D0_APC_3: 0x0
10001 14:44:29.005029 INFO: [APUAPC] D1_APC_0: 0xffffffff
10002 14:44:29.008242 INFO: [APUAPC] D1_APC_1: 0xffffffff
10003 14:44:29.011406 INFO: [APUAPC] D1_APC_2: 0x3fffff
10004 14:44:29.015150 INFO: [APUAPC] D1_APC_3: 0x0
10005 14:44:29.017969 INFO: [APUAPC] D2_APC_0: 0xffffffff
10006 14:44:29.021673 INFO: [APUAPC] D2_APC_1: 0xffffffff
10007 14:44:29.024796 INFO: [APUAPC] D2_APC_2: 0x3fffff
10008 14:44:29.028095 INFO: [APUAPC] D2_APC_3: 0x0
10009 14:44:29.031358 INFO: [APUAPC] D3_APC_0: 0xffffffff
10010 14:44:29.034851 INFO: [APUAPC] D3_APC_1: 0xffffffff
10011 14:44:29.038371 INFO: [APUAPC] D3_APC_2: 0x3fffff
10012 14:44:29.038500 INFO: [APUAPC] D3_APC_3: 0x0
10013 14:44:29.041737 INFO: [APUAPC] D4_APC_0: 0xffffffff
10014 14:44:29.044555 INFO: [APUAPC] D4_APC_1: 0xffffffff
10015 14:44:29.048585 INFO: [APUAPC] D4_APC_2: 0x3fffff
10016 14:44:29.051538 INFO: [APUAPC] D4_APC_3: 0x0
10017 14:44:29.054781 INFO: [APUAPC] D5_APC_0: 0xffffffff
10018 14:44:29.058168 INFO: [APUAPC] D5_APC_1: 0xffffffff
10019 14:44:29.061345 INFO: [APUAPC] D5_APC_2: 0x3fffff
10020 14:44:29.065177 INFO: [APUAPC] D5_APC_3: 0x0
10021 14:44:29.068056 INFO: [APUAPC] D6_APC_0: 0xffffffff
10022 14:44:29.071150 INFO: [APUAPC] D6_APC_1: 0xffffffff
10023 14:44:29.074721 INFO: [APUAPC] D6_APC_2: 0x3fffff
10024 14:44:29.077713 INFO: [APUAPC] D6_APC_3: 0x0
10025 14:44:29.081635 INFO: [APUAPC] D7_APC_0: 0xffffffff
10026 14:44:29.084592 INFO: [APUAPC] D7_APC_1: 0xffffffff
10027 14:44:29.087954 INFO: [APUAPC] D7_APC_2: 0x3fffff
10028 14:44:29.091409 INFO: [APUAPC] D7_APC_3: 0x0
10029 14:44:29.094695 INFO: [APUAPC] D8_APC_0: 0xffffffff
10030 14:44:29.098251 INFO: [APUAPC] D8_APC_1: 0xffffffff
10031 14:44:29.101405 INFO: [APUAPC] D8_APC_2: 0x3fffff
10032 14:44:29.104216 INFO: [APUAPC] D8_APC_3: 0x0
10033 14:44:29.107624 INFO: [APUAPC] D9_APC_0: 0xffffffff
10034 14:44:29.110958 INFO: [APUAPC] D9_APC_1: 0xffffffff
10035 14:44:29.114590 INFO: [APUAPC] D9_APC_2: 0x3fffff
10036 14:44:29.117661 INFO: [APUAPC] D9_APC_3: 0x0
10037 14:44:29.121012 INFO: [APUAPC] D10_APC_0: 0xffffffff
10038 14:44:29.124117 INFO: [APUAPC] D10_APC_1: 0xffffffff
10039 14:44:29.127723 INFO: [APUAPC] D10_APC_2: 0x3fffff
10040 14:44:29.130603 INFO: [APUAPC] D10_APC_3: 0x0
10041 14:44:29.133881 INFO: [APUAPC] D11_APC_0: 0xffffffff
10042 14:44:29.137289 INFO: [APUAPC] D11_APC_1: 0xffffffff
10043 14:44:29.140794 INFO: [APUAPC] D11_APC_2: 0x3fffff
10044 14:44:29.144116 INFO: [APUAPC] D11_APC_3: 0x0
10045 14:44:29.147288 INFO: [APUAPC] D12_APC_0: 0xffffffff
10046 14:44:29.150706 INFO: [APUAPC] D12_APC_1: 0xffffffff
10047 14:44:29.154292 INFO: [APUAPC] D12_APC_2: 0x3fffff
10048 14:44:29.157425 INFO: [APUAPC] D12_APC_3: 0x0
10049 14:44:29.160569 INFO: [APUAPC] D13_APC_0: 0xffffffff
10050 14:44:29.163981 INFO: [APUAPC] D13_APC_1: 0xffffffff
10051 14:44:29.167247 INFO: [APUAPC] D13_APC_2: 0x3fffff
10052 14:44:29.170481 INFO: [APUAPC] D13_APC_3: 0x0
10053 14:44:29.173916 INFO: [APUAPC] D14_APC_0: 0xffffffff
10054 14:44:29.177178 INFO: [APUAPC] D14_APC_1: 0xffffffff
10055 14:44:29.180114 INFO: [APUAPC] D14_APC_2: 0x3fffff
10056 14:44:29.183824 INFO: [APUAPC] D14_APC_3: 0x0
10057 14:44:29.187059 INFO: [APUAPC] D15_APC_0: 0xffffffff
10058 14:44:29.190073 INFO: [APUAPC] D15_APC_1: 0xffffffff
10059 14:44:29.193710 INFO: [APUAPC] D15_APC_2: 0x3fffff
10060 14:44:29.197024 INFO: [APUAPC] D15_APC_3: 0x0
10061 14:44:29.200507 INFO: [APUAPC] APC_CON: 0x4
10062 14:44:29.203727 INFO: [NOCDAPC] D0_APC_0: 0x0
10063 14:44:29.207328 INFO: [NOCDAPC] D0_APC_1: 0x0
10064 14:44:29.210603 INFO: [NOCDAPC] D1_APC_0: 0x0
10065 14:44:29.213228 INFO: [NOCDAPC] D1_APC_1: 0xfff
10066 14:44:29.216508 INFO: [NOCDAPC] D2_APC_0: 0x0
10067 14:44:29.219965 INFO: [NOCDAPC] D2_APC_1: 0xfff
10068 14:44:29.220090 INFO: [NOCDAPC] D3_APC_0: 0x0
10069 14:44:29.223299 INFO: [NOCDAPC] D3_APC_1: 0xfff
10070 14:44:29.226472 INFO: [NOCDAPC] D4_APC_0: 0x0
10071 14:44:29.229857 INFO: [NOCDAPC] D4_APC_1: 0xfff
10072 14:44:29.233076 INFO: [NOCDAPC] D5_APC_0: 0x0
10073 14:44:29.237006 INFO: [NOCDAPC] D5_APC_1: 0xfff
10074 14:44:29.239946 INFO: [NOCDAPC] D6_APC_0: 0x0
10075 14:44:29.243133 INFO: [NOCDAPC] D6_APC_1: 0xfff
10076 14:44:29.246618 INFO: [NOCDAPC] D7_APC_0: 0x0
10077 14:44:29.250109 INFO: [NOCDAPC] D7_APC_1: 0xfff
10078 14:44:29.253007 INFO: [NOCDAPC] D8_APC_0: 0x0
10079 14:44:29.253132 INFO: [NOCDAPC] D8_APC_1: 0xfff
10080 14:44:29.256427 INFO: [NOCDAPC] D9_APC_0: 0x0
10081 14:44:29.259537 INFO: [NOCDAPC] D9_APC_1: 0xfff
10082 14:44:29.262894 INFO: [NOCDAPC] D10_APC_0: 0x0
10083 14:44:29.266796 INFO: [NOCDAPC] D10_APC_1: 0xfff
10084 14:44:29.269646 INFO: [NOCDAPC] D11_APC_0: 0x0
10085 14:44:29.272856 INFO: [NOCDAPC] D11_APC_1: 0xfff
10086 14:44:29.276452 INFO: [NOCDAPC] D12_APC_0: 0x0
10087 14:44:29.279423 INFO: [NOCDAPC] D12_APC_1: 0xfff
10088 14:44:29.282729 INFO: [NOCDAPC] D13_APC_0: 0x0
10089 14:44:29.286203 INFO: [NOCDAPC] D13_APC_1: 0xfff
10090 14:44:29.289823 INFO: [NOCDAPC] D14_APC_0: 0x0
10091 14:44:29.293268 INFO: [NOCDAPC] D14_APC_1: 0xfff
10092 14:44:29.296434 INFO: [NOCDAPC] D15_APC_0: 0x0
10093 14:44:29.299796 INFO: [NOCDAPC] D15_APC_1: 0xfff
10094 14:44:29.299918 INFO: [NOCDAPC] APC_CON: 0x4
10095 14:44:29.303285 INFO: [APUAPC] set_apusys_apc done
10096 14:44:29.306175 INFO: [DEVAPC] devapc_init done
10097 14:44:29.312810 INFO: GICv3 without legacy support detected.
10098 14:44:29.316218 INFO: ARM GICv3 driver initialized in EL3
10099 14:44:29.319523 INFO: Maximum SPI INTID supported: 639
10100 14:44:29.322928 INFO: BL31: Initializing runtime services
10101 14:44:29.329791 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10102 14:44:29.332980 INFO: SPM: enable CPC mode
10103 14:44:29.336009 INFO: mcdi ready for mcusys-off-idle and system suspend
10104 14:44:29.342999 INFO: BL31: Preparing for EL3 exit to normal world
10105 14:44:29.346351 INFO: Entry point address = 0x80000000
10106 14:44:29.346483 INFO: SPSR = 0x8
10107 14:44:29.352914
10108 14:44:29.353160
10109 14:44:29.353285
10110 14:44:29.356073 Starting depthcharge on Spherion...
10111 14:44:29.356231
10112 14:44:29.356347 Wipe memory regions:
10113 14:44:29.356475
10114 14:44:29.357421 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10115 14:44:29.357592 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10116 14:44:29.357726 Setting prompt string to ['asurada:']
10117 14:44:29.357865 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10118 14:44:29.359736 [0x00000040000000, 0x00000054600000)
10119 14:44:29.481684
10120 14:44:29.481888 [0x00000054660000, 0x00000080000000)
10121 14:44:29.742501
10122 14:44:29.742694 [0x000000821a7280, 0x000000ffe64000)
10123 14:44:30.487001
10124 14:44:30.487213 [0x00000100000000, 0x00000240000000)
10125 14:44:32.376428
10126 14:44:32.380026 Initializing XHCI USB controller at 0x11200000.
10127 14:44:33.417790
10128 14:44:33.421301 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10129 14:44:33.421387
10130 14:44:33.421452
10131 14:44:33.421750 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10133 14:44:33.522067 asurada: tftpboot 192.168.201.1 14166992/tftp-deploy-2kidynw7/kernel/image.itb 14166992/tftp-deploy-2kidynw7/kernel/cmdline
10134 14:44:33.522259 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10135 14:44:33.522391 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10136 14:44:33.526702 tftpboot 192.168.201.1 14166992/tftp-deploy-2kidynw7/kernel/image.itp-deploy-2kidynw7/kernel/cmdline
10137 14:44:33.526830
10138 14:44:33.526943 Waiting for link
10139 14:44:33.686776
10140 14:44:33.686957 R8152: Initializing
10141 14:44:33.687071
10142 14:44:33.690354 Version 6 (ocp_data = 5c30)
10143 14:44:33.690476
10144 14:44:33.693531 R8152: Done initializing
10145 14:44:33.693650
10146 14:44:33.693759 Adding net device
10147 14:44:35.597405
10148 14:44:35.597555 done.
10149 14:44:35.597621
10150 14:44:35.597681 MAC: 00:24:32:30:78:ff
10151 14:44:35.597738
10152 14:44:35.600138 Sending DHCP discover... done.
10153 14:44:35.600220
10154 14:44:35.603748 Waiting for reply... done.
10155 14:44:35.603879
10156 14:44:35.607201 Sending DHCP request... done.
10157 14:44:35.607325
10158 14:44:35.611783 Waiting for reply... done.
10159 14:44:35.611906
10160 14:44:35.612020 My ip is 192.168.201.21
10161 14:44:35.612128
10162 14:44:35.615674 The DHCP server ip is 192.168.201.1
10163 14:44:35.615797
10164 14:44:35.621744 TFTP server IP predefined by user: 192.168.201.1
10165 14:44:35.621869
10166 14:44:35.628796 Bootfile predefined by user: 14166992/tftp-deploy-2kidynw7/kernel/image.itb
10167 14:44:35.628920
10168 14:44:35.629033 Sending tftp read request... done.
10169 14:44:35.631543
10170 14:44:35.635255 Waiting for the transfer...
10171 14:44:35.635377
10172 14:44:36.203068 00000000 ################################################################
10173 14:44:36.203266
10174 14:44:36.750290 00080000 ################################################################
10175 14:44:36.750454
10176 14:44:37.306802 00100000 ################################################################
10177 14:44:37.306955
10178 14:44:37.862651 00180000 ################################################################
10179 14:44:37.862786
10180 14:44:38.417327 00200000 ################################################################
10181 14:44:38.417481
10182 14:44:38.972070 00280000 ################################################################
10183 14:44:38.972242
10184 14:44:39.539297 00300000 ################################################################
10185 14:44:39.539445
10186 14:44:40.113606 00380000 ################################################################
10187 14:44:40.113753
10188 14:44:40.690763 00400000 ################################################################
10189 14:44:40.690911
10190 14:44:41.270043 00480000 ################################################################
10191 14:44:41.270186
10192 14:44:41.850038 00500000 ################################################################
10193 14:44:41.850225
10194 14:44:42.431439 00580000 ################################################################
10195 14:44:42.431574
10196 14:44:42.998987 00600000 ################################################################
10197 14:44:42.999120
10198 14:44:43.562537 00680000 ################################################################
10199 14:44:43.562673
10200 14:44:44.130081 00700000 ################################################################
10201 14:44:44.130221
10202 14:44:44.691953 00780000 ################################################################
10203 14:44:44.692085
10204 14:44:45.251246 00800000 ################################################################
10205 14:44:45.251438
10206 14:44:45.815017 00880000 ################################################################
10207 14:44:45.815159
10208 14:44:46.369875 00900000 ################################################################
10209 14:44:46.370023
10210 14:44:46.931285 00980000 ################################################################
10211 14:44:46.931461
10212 14:44:47.494801 00a00000 ################################################################
10213 14:44:47.494973
10214 14:44:48.079494 00a80000 ################################################################
10215 14:44:48.079644
10216 14:44:48.654900 00b00000 ################################################################
10217 14:44:48.655047
10218 14:44:49.240606 00b80000 ################################################################
10219 14:44:49.240751
10220 14:44:49.804340 00c00000 ################################################################
10221 14:44:49.804506
10222 14:44:50.378925 00c80000 ################################################################
10223 14:44:50.379060
10224 14:44:50.947372 00d00000 ################################################################
10225 14:44:50.947503
10226 14:44:51.503298 00d80000 ################################################################
10227 14:44:51.503481
10228 14:44:52.064125 00e00000 ################################################################
10229 14:44:52.064283
10230 14:44:52.628771 00e80000 ################################################################
10231 14:44:52.628908
10232 14:44:53.175812 00f00000 ################################################################
10233 14:44:53.175979
10234 14:44:53.746152 00f80000 ################################################################
10235 14:44:53.746330
10236 14:44:54.310138 01000000 ################################################################
10237 14:44:54.310282
10238 14:44:54.866926 01080000 ################################################################
10239 14:44:54.867076
10240 14:44:55.413979 01100000 ################################################################
10241 14:44:55.414119
10242 14:44:55.962708 01180000 ################################################################
10243 14:44:55.962913
10244 14:44:56.503065 01200000 ################################################################
10245 14:44:56.503267
10246 14:44:57.038215 01280000 ################################################################
10247 14:44:57.038439
10248 14:44:57.571473 01300000 ################################################################
10249 14:44:57.571624
10250 14:44:58.103449 01380000 ################################################################
10251 14:44:58.103612
10252 14:44:58.642489 01400000 ################################################################
10253 14:44:58.642624
10254 14:44:59.184810 01480000 ################################################################
10255 14:44:59.185005
10256 14:44:59.729208 01500000 ################################################################
10257 14:44:59.729387
10258 14:45:00.261937 01580000 ################################################################
10259 14:45:00.262167
10260 14:45:00.803609 01600000 ################################################################
10261 14:45:00.803762
10262 14:45:01.350538 01680000 ################################################################
10263 14:45:01.350688
10264 14:45:01.933759 01700000 ################################################################
10265 14:45:01.933915
10266 14:45:02.544344 01780000 ################################################################
10267 14:45:02.544514
10268 14:45:03.134307 01800000 ################################################################
10269 14:45:03.134525
10270 14:45:03.683579 01880000 ################################################################
10271 14:45:03.683773
10272 14:45:04.221115 01900000 ################################################################
10273 14:45:04.221308
10274 14:45:04.751714 01980000 ################################################################
10275 14:45:04.751859
10276 14:45:05.292830 01a00000 ################################################################
10277 14:45:05.292980
10278 14:45:05.854765 01a80000 ################################################################
10279 14:45:05.854905
10280 14:45:06.397660 01b00000 ################################################################
10281 14:45:06.397803
10282 14:45:06.955066 01b80000 ################################################################
10283 14:45:06.955242
10284 14:45:07.496543 01c00000 ################################################################
10285 14:45:07.496781
10286 14:45:08.057489 01c80000 ################################################################
10287 14:45:08.057632
10288 14:45:08.599494 01d00000 ################################################################
10289 14:45:08.599663
10290 14:45:09.156868 01d80000 ################################################################
10291 14:45:09.157015
10292 14:45:09.550620 01e00000 ############################################### done.
10293 14:45:09.550775
10294 14:45:09.553940 The bootfile was 31838738 bytes long.
10295 14:45:09.554054
10296 14:45:09.557216 Sending tftp read request... done.
10297 14:45:09.557317
10298 14:45:09.557396 Waiting for the transfer...
10299 14:45:09.557488
10300 14:45:09.560521 00000000 # done.
10301 14:45:09.560674
10302 14:45:09.566906 Command line loaded dynamically from TFTP file: 14166992/tftp-deploy-2kidynw7/kernel/cmdline
10303 14:45:09.567006
10304 14:45:09.590246 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14166992/extract-nfsrootfs-r1s09h8d,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10305 14:45:09.590367
10306 14:45:09.590464 Loading FIT.
10307 14:45:09.590526
10308 14:45:09.593551 Image ramdisk-1 has 18728827 bytes.
10309 14:45:09.593649
10310 14:45:09.597101 Image fdt-1 has 47258 bytes.
10311 14:45:09.597200
10312 14:45:09.600316 Image kernel-1 has 13060619 bytes.
10313 14:45:09.600398
10314 14:45:09.610057 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10315 14:45:09.610143
10316 14:45:09.626966 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10317 14:45:09.627076
10318 14:45:09.633572 Choosing best match conf-1 for compat google,spherion-rev2.
10319 14:45:09.633656
10320 14:45:09.640978 Connected to device vid:did:rid of 1ae0:0028:00
10321 14:45:09.649313
10322 14:45:09.652437 tpm_get_response: command 0x17b, return code 0x0
10323 14:45:09.652546
10324 14:45:09.656028 ec_init: CrosEC protocol v3 supported (256, 248)
10325 14:45:09.659949
10326 14:45:09.663220 tpm_cleanup: add release locality here.
10327 14:45:09.663303
10328 14:45:09.663368 Shutting down all USB controllers.
10329 14:45:09.666494
10330 14:45:09.666577 Removing current net device
10331 14:45:09.666642
10332 14:45:09.673017 Exiting depthcharge with code 4 at timestamp: 69654553
10333 14:45:09.673100
10334 14:45:09.676555 LZMA decompressing kernel-1 to 0x821a6718
10335 14:45:09.676660
10336 14:45:09.679983 LZMA decompressing kernel-1 to 0x40000000
10337 14:45:11.292634
10338 14:45:11.292788 jumping to kernel
10339 14:45:11.293242 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10340 14:45:11.293345 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10341 14:45:11.293423 Setting prompt string to ['Linux version [0-9]']
10342 14:45:11.293491 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10343 14:45:11.293558 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10344 14:45:11.374902
10345 14:45:11.377801 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10346 14:45:11.381655 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10347 14:45:11.381756 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10348 14:45:11.381830 Setting prompt string to []
10349 14:45:11.381907 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10350 14:45:11.381979 Using line separator: #'\n'#
10351 14:45:11.382038 No login prompt set.
10352 14:45:11.382171 Parsing kernel messages
10353 14:45:11.382232 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10354 14:45:11.382337 [login-action] Waiting for messages, (timeout 00:03:43)
10355 14:45:11.382406 Waiting using forced prompt support (timeout 00:01:52)
10356 14:45:11.400898 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j216541-arm64-gcc-10-defconfig-arm64-chromebook-f7c97) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024
10357 14:45:11.404535 [ 0.000000] random: crng init done
10358 14:45:11.411117 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10359 14:45:11.414522 [ 0.000000] efi: UEFI not found.
10360 14:45:11.420869 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10361 14:45:11.427849 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10362 14:45:11.437309 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10363 14:45:11.447304 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10364 14:45:11.453829 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10365 14:45:11.460445 [ 0.000000] printk: bootconsole [mtk8250] enabled
10366 14:45:11.467558 [ 0.000000] NUMA: No NUMA configuration found
10367 14:45:11.473945 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10368 14:45:11.477284 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10369 14:45:11.480488 [ 0.000000] Zone ranges:
10370 14:45:11.487545 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10371 14:45:11.490561 [ 0.000000] DMA32 empty
10372 14:45:11.497038 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10373 14:45:11.500450 [ 0.000000] Movable zone start for each node
10374 14:45:11.503527 [ 0.000000] Early memory node ranges
10375 14:45:11.510222 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10376 14:45:11.516917 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10377 14:45:11.523882 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10378 14:45:11.530066 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10379 14:45:11.536420 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10380 14:45:11.543366 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10381 14:45:11.599647 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10382 14:45:11.606082 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10383 14:45:11.612513 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10384 14:45:11.616015 [ 0.000000] psci: probing for conduit method from DT.
10385 14:45:11.622480 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10386 14:45:11.626085 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10387 14:45:11.632258 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10388 14:45:11.635774 [ 0.000000] psci: SMC Calling Convention v1.2
10389 14:45:11.642213 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10390 14:45:11.645522 [ 0.000000] Detected VIPT I-cache on CPU0
10391 14:45:11.652265 [ 0.000000] CPU features: detected: GIC system register CPU interface
10392 14:45:11.659281 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10393 14:45:11.665668 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10394 14:45:11.672053 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10395 14:45:11.682525 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10396 14:45:11.688385 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10397 14:45:11.691920 [ 0.000000] alternatives: applying boot alternatives
10398 14:45:11.698484 [ 0.000000] Fallback order for Node 0: 0
10399 14:45:11.705623 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10400 14:45:11.708350 [ 0.000000] Policy zone: Normal
10401 14:45:11.731401 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14166992/extract-nfsrootfs-r1s09h8d,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10402 14:45:11.741429 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10403 14:45:11.751388 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10404 14:45:11.761653 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10405 14:45:11.768329 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10406 14:45:11.771050 <6>[ 0.000000] software IO TLB: area num 8.
10407 14:45:11.827815 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10408 14:45:11.976789 <6>[ 0.000000] Memory: 7945896K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406872K reserved, 32768K cma-reserved)
10409 14:45:11.983423 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10410 14:45:11.989877 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10411 14:45:11.993568 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10412 14:45:11.999766 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10413 14:45:12.006758 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10414 14:45:12.010133 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10415 14:45:12.020005 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10416 14:45:12.026799 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10417 14:45:12.032956 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10418 14:45:12.039665 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10419 14:45:12.043077 <6>[ 0.000000] GICv3: 608 SPIs implemented
10420 14:45:12.046289 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10421 14:45:12.052795 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10422 14:45:12.056287 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10423 14:45:12.063062 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10424 14:45:12.076057 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10425 14:45:12.089099 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10426 14:45:12.095914 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10427 14:45:12.103486 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10428 14:45:12.116783 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10429 14:45:12.123024 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10430 14:45:12.129881 <6>[ 0.009181] Console: colour dummy device 80x25
10431 14:45:12.139813 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10432 14:45:12.146316 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10433 14:45:12.149463 <6>[ 0.029222] LSM: Security Framework initializing
10434 14:45:12.155959 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10435 14:45:12.166049 <6>[ 0.042053] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10436 14:45:12.175779 <6>[ 0.051480] cblist_init_generic: Setting adjustable number of callback queues.
10437 14:45:12.179315 <6>[ 0.058970] cblist_init_generic: Setting shift to 3 and lim to 1.
10438 14:45:12.189269 <6>[ 0.065348] cblist_init_generic: Setting adjustable number of callback queues.
10439 14:45:12.195747 <6>[ 0.072821] cblist_init_generic: Setting shift to 3 and lim to 1.
10440 14:45:12.199189 <6>[ 0.079223] rcu: Hierarchical SRCU implementation.
10441 14:45:12.205980 <6>[ 0.084269] rcu: Max phase no-delay instances is 1000.
10442 14:45:12.212436 <6>[ 0.091342] EFI services will not be available.
10443 14:45:12.215687 <6>[ 0.096296] smp: Bringing up secondary CPUs ...
10444 14:45:12.224314 <6>[ 0.101371] Detected VIPT I-cache on CPU1
10445 14:45:12.231266 <6>[ 0.101443] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10446 14:45:12.237532 <6>[ 0.101476] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10447 14:45:12.241168 <6>[ 0.101808] Detected VIPT I-cache on CPU2
10448 14:45:12.247278 <6>[ 0.101859] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10449 14:45:12.257258 <6>[ 0.101877] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10450 14:45:12.260531 <6>[ 0.102137] Detected VIPT I-cache on CPU3
10451 14:45:12.267120 <6>[ 0.102183] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10452 14:45:12.274126 <6>[ 0.102197] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10453 14:45:12.277210 <6>[ 0.102500] CPU features: detected: Spectre-v4
10454 14:45:12.283988 <6>[ 0.102506] CPU features: detected: Spectre-BHB
10455 14:45:12.287335 <6>[ 0.102511] Detected PIPT I-cache on CPU4
10456 14:45:12.293933 <6>[ 0.102568] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10457 14:45:12.300811 <6>[ 0.102584] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10458 14:45:12.306913 <6>[ 0.102877] Detected PIPT I-cache on CPU5
10459 14:45:12.313761 <6>[ 0.102938] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10460 14:45:12.320231 <6>[ 0.102954] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10461 14:45:12.323902 <6>[ 0.103238] Detected PIPT I-cache on CPU6
10462 14:45:12.329791 <6>[ 0.103304] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10463 14:45:12.336410 <6>[ 0.103320] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10464 14:45:12.343163 <6>[ 0.103615] Detected PIPT I-cache on CPU7
10465 14:45:12.349807 <6>[ 0.103679] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10466 14:45:12.356668 <6>[ 0.103697] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10467 14:45:12.360162 <6>[ 0.103744] smp: Brought up 1 node, 8 CPUs
10468 14:45:12.366607 <6>[ 0.245065] SMP: Total of 8 processors activated.
10469 14:45:12.369923 <6>[ 0.249986] CPU features: detected: 32-bit EL0 Support
10470 14:45:12.379883 <6>[ 0.255382] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10471 14:45:12.386442 <6>[ 0.264182] CPU features: detected: Common not Private translations
10472 14:45:12.392747 <6>[ 0.270698] CPU features: detected: CRC32 instructions
10473 14:45:12.396390 <6>[ 0.276050] CPU features: detected: RCpc load-acquire (LDAPR)
10474 14:45:12.402938 <6>[ 0.282010] CPU features: detected: LSE atomic instructions
10475 14:45:12.409233 <6>[ 0.287792] CPU features: detected: Privileged Access Never
10476 14:45:12.415862 <6>[ 0.293607] CPU features: detected: RAS Extension Support
10477 14:45:12.422426 <6>[ 0.299216] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10478 14:45:12.426166 <6>[ 0.306436] CPU: All CPU(s) started at EL2
10479 14:45:12.432809 <6>[ 0.310753] alternatives: applying system-wide alternatives
10480 14:45:12.442204 <6>[ 0.321640] devtmpfs: initialized
10481 14:45:12.454507 <6>[ 0.330507] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10482 14:45:12.464198 <6>[ 0.340465] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10483 14:45:12.467515 <6>[ 0.348137] pinctrl core: initialized pinctrl subsystem
10484 14:45:12.475584 <6>[ 0.354778] DMI not present or invalid.
10485 14:45:12.482229 <6>[ 0.359187] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10486 14:45:12.488470 <6>[ 0.366062] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10487 14:45:12.498365 <6>[ 0.373648] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10488 14:45:12.505045 <6>[ 0.381866] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10489 14:45:12.511510 <6>[ 0.390110] audit: initializing netlink subsys (disabled)
10490 14:45:12.518351 <5>[ 0.395803] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10491 14:45:12.524972 <6>[ 0.396501] thermal_sys: Registered thermal governor 'step_wise'
10492 14:45:12.531478 <6>[ 0.403769] thermal_sys: Registered thermal governor 'power_allocator'
10493 14:45:12.534646 <6>[ 0.410024] cpuidle: using governor menu
10494 14:45:12.541399 <6>[ 0.420984] NET: Registered PF_QIPCRTR protocol family
10495 14:45:12.548211 <6>[ 0.426472] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10496 14:45:12.554779 <6>[ 0.433576] ASID allocator initialised with 32768 entries
10497 14:45:12.561236 <6>[ 0.440143] Serial: AMBA PL011 UART driver
10498 14:45:12.569434 <4>[ 0.448881] Trying to register duplicate clock ID: 134
10499 14:45:12.627284 <6>[ 0.510219] KASLR enabled
10500 14:45:12.641860 <6>[ 0.517933] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10501 14:45:12.648130 <6>[ 0.524946] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10502 14:45:12.654767 <6>[ 0.531436] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10503 14:45:12.661682 <6>[ 0.538439] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10504 14:45:12.668255 <6>[ 0.544924] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10505 14:45:12.674854 <6>[ 0.551931] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10506 14:45:12.681714 <6>[ 0.558416] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10507 14:45:12.688310 <6>[ 0.565419] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10508 14:45:12.691096 <6>[ 0.572882] ACPI: Interpreter disabled.
10509 14:45:12.699641 <6>[ 0.579324] iommu: Default domain type: Translated
10510 14:45:12.706414 <6>[ 0.584435] iommu: DMA domain TLB invalidation policy: strict mode
10511 14:45:12.709920 <5>[ 0.591098] SCSI subsystem initialized
10512 14:45:12.716364 <6>[ 0.595345] usbcore: registered new interface driver usbfs
10513 14:45:12.722975 <6>[ 0.601075] usbcore: registered new interface driver hub
10514 14:45:12.726390 <6>[ 0.606623] usbcore: registered new device driver usb
10515 14:45:12.733439 <6>[ 0.612736] pps_core: LinuxPPS API ver. 1 registered
10516 14:45:12.743053 <6>[ 0.617930] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10517 14:45:12.746221 <6>[ 0.627270] PTP clock support registered
10518 14:45:12.749932 <6>[ 0.631512] EDAC MC: Ver: 3.0.0
10519 14:45:12.757263 <6>[ 0.636693] FPGA manager framework
10520 14:45:12.763778 <6>[ 0.640370] Advanced Linux Sound Architecture Driver Initialized.
10521 14:45:12.767016 <6>[ 0.647140] vgaarb: loaded
10522 14:45:12.773900 <6>[ 0.650307] clocksource: Switched to clocksource arch_sys_counter
10523 14:45:12.777062 <5>[ 0.656756] VFS: Disk quotas dquot_6.6.0
10524 14:45:12.783797 <6>[ 0.660941] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10525 14:45:12.787086 <6>[ 0.668129] pnp: PnP ACPI: disabled
10526 14:45:12.795180 <6>[ 0.674760] NET: Registered PF_INET protocol family
10527 14:45:12.805271 <6>[ 0.680350] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10528 14:45:12.816734 <6>[ 0.692686] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10529 14:45:12.826405 <6>[ 0.701505] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10530 14:45:12.833097 <6>[ 0.709475] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10531 14:45:12.842974 <6>[ 0.718172] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10532 14:45:12.849390 <6>[ 0.727925] TCP: Hash tables configured (established 65536 bind 65536)
10533 14:45:12.855977 <6>[ 0.734793] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10534 14:45:12.866191 <6>[ 0.741989] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10535 14:45:12.872952 <6>[ 0.749693] NET: Registered PF_UNIX/PF_LOCAL protocol family
10536 14:45:12.879315 <6>[ 0.755842] RPC: Registered named UNIX socket transport module.
10537 14:45:12.882413 <6>[ 0.761993] RPC: Registered udp transport module.
10538 14:45:12.888805 <6>[ 0.766924] RPC: Registered tcp transport module.
10539 14:45:12.895657 <6>[ 0.771856] RPC: Registered tcp NFSv4.1 backchannel transport module.
10540 14:45:12.899002 <6>[ 0.778523] PCI: CLS 0 bytes, default 64
10541 14:45:12.902257 <6>[ 0.782876] Unpacking initramfs...
10542 14:45:12.926130 <6>[ 0.802413] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10543 14:45:12.936142 <6>[ 0.811049] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10544 14:45:12.939856 <6>[ 0.819875] kvm [1]: IPA Size Limit: 40 bits
10545 14:45:12.946134 <6>[ 0.824400] kvm [1]: GICv3: no GICV resource entry
10546 14:45:12.949150 <6>[ 0.829421] kvm [1]: disabling GICv2 emulation
10547 14:45:12.956290 <6>[ 0.834103] kvm [1]: GIC system register CPU interface enabled
10548 14:45:12.959383 <6>[ 0.840258] kvm [1]: vgic interrupt IRQ18
10549 14:45:12.966095 <6>[ 0.844628] kvm [1]: VHE mode initialized successfully
10550 14:45:12.972991 <5>[ 0.850932] Initialise system trusted keyrings
10551 14:45:12.979012 <6>[ 0.855800] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10552 14:45:12.986357 <6>[ 0.865804] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10553 14:45:12.992853 <5>[ 0.872177] NFS: Registering the id_resolver key type
10554 14:45:12.996177 <5>[ 0.877482] Key type id_resolver registered
10555 14:45:13.003013 <5>[ 0.881898] Key type id_legacy registered
10556 14:45:13.009384 <6>[ 0.886191] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10557 14:45:13.015969 <6>[ 0.893110] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10558 14:45:13.022881 <6>[ 0.900793] 9p: Installing v9fs 9p2000 file system support
10559 14:45:13.058797 <5>[ 0.937962] Key type asymmetric registered
10560 14:45:13.061893 <5>[ 0.942293] Asymmetric key parser 'x509' registered
10561 14:45:13.071525 <6>[ 0.947424] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10562 14:45:13.075139 <6>[ 0.955036] io scheduler mq-deadline registered
10563 14:45:13.078264 <6>[ 0.959796] io scheduler kyber registered
10564 14:45:13.097275 <6>[ 0.976649] EINJ: ACPI disabled.
10565 14:45:13.129537 <4>[ 1.002209] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 14:45:13.139282 <4>[ 1.012839] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 14:45:13.154013 <6>[ 1.033602] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10568 14:45:13.161838 <6>[ 1.041517] printk: console [ttyS0] disabled
10569 14:45:13.189836 <6>[ 1.066167] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10570 14:45:13.196921 <6>[ 1.075638] printk: console [ttyS0] enabled
10571 14:45:13.200144 <6>[ 1.075638] printk: console [ttyS0] enabled
10572 14:45:13.206724 <6>[ 1.084533] printk: bootconsole [mtk8250] disabled
10573 14:45:13.209918 <6>[ 1.084533] printk: bootconsole [mtk8250] disabled
10574 14:45:13.216467 <6>[ 1.095535] SuperH (H)SCI(F) driver initialized
10575 14:45:13.219941 <6>[ 1.100797] msm_serial: driver initialized
10576 14:45:13.233373 <6>[ 1.109676] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10577 14:45:13.243160 <6>[ 1.118224] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10578 14:45:13.249906 <6>[ 1.126765] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10579 14:45:13.260006 <6>[ 1.135392] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10580 14:45:13.269850 <6>[ 1.144097] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10581 14:45:13.276239 <6>[ 1.152816] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10582 14:45:13.286321 <6>[ 1.161356] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10583 14:45:13.292929 <6>[ 1.170151] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10584 14:45:13.302953 <6>[ 1.178692] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10585 14:45:13.314983 <6>[ 1.194091] loop: module loaded
10586 14:45:13.320890 <6>[ 1.200145] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10587 14:45:13.343870 <4>[ 1.223461] mtk-pmic-keys: Failed to locate of_node [id: -1]
10588 14:45:13.350843 <6>[ 1.230261] megasas: 07.719.03.00-rc1
10589 14:45:13.360229 <6>[ 1.239987] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10590 14:45:13.370372 <6>[ 1.249694] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10591 14:45:13.386781 <6>[ 1.266237] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10592 14:45:13.443048 <6>[ 1.316240] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10593 14:45:13.693392 <6>[ 1.572987] Freeing initrd memory: 18284K
10594 14:45:13.705079 <6>[ 1.584724] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10595 14:45:13.716943 <6>[ 1.595880] tun: Universal TUN/TAP device driver, 1.6
10596 14:45:13.719561 <6>[ 1.601965] thunder_xcv, ver 1.0
10597 14:45:13.723295 <6>[ 1.605471] thunder_bgx, ver 1.0
10598 14:45:13.726331 <6>[ 1.608966] nicpf, ver 1.0
10599 14:45:13.736843 <6>[ 1.612998] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10600 14:45:13.740177 <6>[ 1.620473] hns3: Copyright (c) 2017 Huawei Corporation.
10601 14:45:13.743880 <6>[ 1.626061] hclge is initializing
10602 14:45:13.750045 <6>[ 1.629644] e1000: Intel(R) PRO/1000 Network Driver
10603 14:45:13.757093 <6>[ 1.634773] e1000: Copyright (c) 1999-2006 Intel Corporation.
10604 14:45:13.760462 <6>[ 1.640785] e1000e: Intel(R) PRO/1000 Network Driver
10605 14:45:13.766935 <6>[ 1.646000] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10606 14:45:13.773558 <6>[ 1.652188] igb: Intel(R) Gigabit Ethernet Network Driver
10607 14:45:13.780153 <6>[ 1.657838] igb: Copyright (c) 2007-2014 Intel Corporation.
10608 14:45:13.786560 <6>[ 1.663675] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10609 14:45:13.793106 <6>[ 1.670192] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10610 14:45:13.796631 <6>[ 1.676652] sky2: driver version 1.30
10611 14:45:13.803313 <6>[ 1.681577] usbcore: registered new device driver r8152-cfgselector
10612 14:45:13.809909 <6>[ 1.688113] usbcore: registered new interface driver r8152
10613 14:45:13.813234 <6>[ 1.693933] VFIO - User Level meta-driver version: 0.3
10614 14:45:13.822848 <6>[ 1.702197] usbcore: registered new interface driver usb-storage
10615 14:45:13.829523 <6>[ 1.708645] usbcore: registered new device driver onboard-usb-hub
10616 14:45:13.838155 <6>[ 1.717805] mt6397-rtc mt6359-rtc: registered as rtc0
10617 14:45:13.848175 <6>[ 1.723269] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T14:45:13 UTC (1717512313)
10618 14:45:13.851375 <6>[ 1.732837] i2c_dev: i2c /dev entries driver
10619 14:45:13.868329 <6>[ 1.744623] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10620 14:45:13.874783 <4>[ 1.753355] cpu cpu0: supply cpu not found, using dummy regulator
10621 14:45:13.881411 <4>[ 1.759784] cpu cpu1: supply cpu not found, using dummy regulator
10622 14:45:13.888465 <4>[ 1.766205] cpu cpu2: supply cpu not found, using dummy regulator
10623 14:45:13.894884 <4>[ 1.772598] cpu cpu3: supply cpu not found, using dummy regulator
10624 14:45:13.901344 <4>[ 1.778991] cpu cpu4: supply cpu not found, using dummy regulator
10625 14:45:13.908111 <4>[ 1.785393] cpu cpu5: supply cpu not found, using dummy regulator
10626 14:45:13.914976 <4>[ 1.791793] cpu cpu6: supply cpu not found, using dummy regulator
10627 14:45:13.921218 <4>[ 1.798206] cpu cpu7: supply cpu not found, using dummy regulator
10628 14:45:13.939479 <6>[ 1.818838] cpu cpu0: EM: created perf domain
10629 14:45:13.942685 <6>[ 1.823769] cpu cpu4: EM: created perf domain
10630 14:45:13.949732 <6>[ 1.829398] sdhci: Secure Digital Host Controller Interface driver
10631 14:45:13.956307 <6>[ 1.835831] sdhci: Copyright(c) Pierre Ossman
10632 14:45:13.963446 <6>[ 1.840792] Synopsys Designware Multimedia Card Interface Driver
10633 14:45:13.970058 <6>[ 1.847425] sdhci-pltfm: SDHCI platform and OF driver helper
10634 14:45:13.973340 <6>[ 1.847479] mmc0: CQHCI version 5.10
10635 14:45:13.980411 <6>[ 1.857793] ledtrig-cpu: registered to indicate activity on CPUs
10636 14:45:13.986344 <6>[ 1.864932] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10637 14:45:13.993442 <6>[ 1.871985] usbcore: registered new interface driver usbhid
10638 14:45:13.996505 <6>[ 1.877807] usbhid: USB HID core driver
10639 14:45:14.003151 <6>[ 1.882000] spi_master spi0: will run message pump with realtime priority
10640 14:45:14.047333 <6>[ 1.920197] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10641 14:45:14.066434 <6>[ 1.936160] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10642 14:45:14.070119 <6>[ 1.949761] mmc0: Command Queue Engine enabled
10643 14:45:14.076980 <6>[ 1.954525] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10644 14:45:14.083427 <6>[ 1.961501] cros-ec-spi spi0.0: Chrome EC device registered
10645 14:45:14.087241 <6>[ 1.961977] mmcblk0: mmc0:0001 DA4128 116 GiB
10646 14:45:14.097518 <6>[ 1.977080] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10647 14:45:14.105169 <6>[ 1.984435] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10648 14:45:14.111542 <6>[ 1.990259] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10649 14:45:14.121367 <6>[ 1.995630] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10650 14:45:14.127889 <6>[ 1.996163] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10651 14:45:14.131314 <6>[ 2.006268] NET: Registered PF_PACKET protocol family
10652 14:45:14.138060 <6>[ 2.016863] 9pnet: Installing 9P2000 support
10653 14:45:14.141098 <5>[ 2.021428] Key type dns_resolver registered
10654 14:45:14.144663 <6>[ 2.026409] registered taskstats version 1
10655 14:45:14.151023 <5>[ 2.030796] Loading compiled-in X.509 certificates
10656 14:45:14.181527 <4>[ 2.054512] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10657 14:45:14.191528 <4>[ 2.065264] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10658 14:45:14.206023 <6>[ 2.085805] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10659 14:45:14.213065 <6>[ 2.092728] xhci-mtk 11200000.usb: xHCI Host Controller
10660 14:45:14.219980 <6>[ 2.098274] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10661 14:45:14.229833 <6>[ 2.106130] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10662 14:45:14.236449 <6>[ 2.115567] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10663 14:45:14.243290 <6>[ 2.121760] xhci-mtk 11200000.usb: xHCI Host Controller
10664 14:45:14.249822 <6>[ 2.127271] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10665 14:45:14.256878 <6>[ 2.134925] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10666 14:45:14.263195 <6>[ 2.142779] hub 1-0:1.0: USB hub found
10667 14:45:14.266358 <6>[ 2.146806] hub 1-0:1.0: 1 port detected
10668 14:45:14.273611 <6>[ 2.151099] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10669 14:45:14.280429 <6>[ 2.159867] hub 2-0:1.0: USB hub found
10670 14:45:14.283317 <6>[ 2.163893] hub 2-0:1.0: 1 port detected
10671 14:45:14.291246 <6>[ 2.171096] mtk-msdc 11f70000.mmc: Got CD GPIO
10672 14:45:14.304908 <6>[ 2.181098] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10673 14:45:14.311484 <6>[ 2.189136] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10674 14:45:14.321577 <4>[ 2.197043] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10675 14:45:14.331001 <6>[ 2.206580] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10676 14:45:14.338161 <6>[ 2.214658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10677 14:45:14.344542 <6>[ 2.222673] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10678 14:45:14.354423 <6>[ 2.230595] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10679 14:45:14.361394 <6>[ 2.238412] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10680 14:45:14.370867 <6>[ 2.246232] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10681 14:45:14.380932 <6>[ 2.256644] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10682 14:45:14.387417 <6>[ 2.265007] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10683 14:45:14.397190 <6>[ 2.273353] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10684 14:45:14.404308 <6>[ 2.281692] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10685 14:45:14.413520 <6>[ 2.290030] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10686 14:45:14.420308 <6>[ 2.298368] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10687 14:45:14.430752 <6>[ 2.306705] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10688 14:45:14.440601 <6>[ 2.315043] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10689 14:45:14.446993 <6>[ 2.323381] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10690 14:45:14.456865 <6>[ 2.331719] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10691 14:45:14.463388 <6>[ 2.340057] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10692 14:45:14.473093 <6>[ 2.348395] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10693 14:45:14.479864 <6>[ 2.356734] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10694 14:45:14.489746 <6>[ 2.365073] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10695 14:45:14.496364 <6>[ 2.373411] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10696 14:45:14.502928 <6>[ 2.382157] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10697 14:45:14.509453 <6>[ 2.389318] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10698 14:45:14.516439 <6>[ 2.396093] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10699 14:45:14.526219 <6>[ 2.402869] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10700 14:45:14.533165 <6>[ 2.409804] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10701 14:45:14.539752 <6>[ 2.416663] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10702 14:45:14.549547 <6>[ 2.425792] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10703 14:45:14.559516 <6>[ 2.434912] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10704 14:45:14.569508 <6>[ 2.444208] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10705 14:45:14.579671 <6>[ 2.453676] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10706 14:45:14.585884 <6>[ 2.463143] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10707 14:45:14.595942 <6>[ 2.472263] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10708 14:45:14.605898 <6>[ 2.481729] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10709 14:45:14.615548 <6>[ 2.490848] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10710 14:45:14.626000 <6>[ 2.500151] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10711 14:45:14.635681 <6>[ 2.510312] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10712 14:45:14.645211 <6>[ 2.521794] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10713 14:45:14.651992 <6>[ 2.531181] Trying to probe devices needed for running init ...
10714 14:45:14.698246 <6>[ 2.574602] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10715 14:45:14.853163 <6>[ 2.732449] hub 1-1:1.0: USB hub found
10716 14:45:14.855850 <6>[ 2.736946] hub 1-1:1.0: 4 ports detected
10717 14:45:14.866193 <6>[ 2.745587] hub 1-1:1.0: USB hub found
10718 14:45:14.868896 <6>[ 2.749932] hub 1-1:1.0: 4 ports detected
10719 14:45:14.978383 <6>[ 2.854939] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10720 14:45:15.004518 <6>[ 2.884434] hub 2-1:1.0: USB hub found
10721 14:45:15.008397 <6>[ 2.888921] hub 2-1:1.0: 3 ports detected
10722 14:45:15.017460 <6>[ 2.896754] hub 2-1:1.0: USB hub found
10723 14:45:15.020386 <6>[ 2.901240] hub 2-1:1.0: 3 ports detected
10724 14:45:15.193853 <6>[ 3.070628] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10725 14:45:15.326772 <6>[ 3.206495] hub 1-1.4:1.0: USB hub found
10726 14:45:15.329960 <6>[ 3.211156] hub 1-1.4:1.0: 2 ports detected
10727 14:45:15.338876 <6>[ 3.218759] hub 1-1.4:1.0: USB hub found
10728 14:45:15.342167 <6>[ 3.223359] hub 1-1.4:1.0: 2 ports detected
10729 14:45:15.406422 <6>[ 3.282825] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10730 14:45:15.514632 <6>[ 3.391253] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10731 14:45:15.551622 <4>[ 3.427857] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10732 14:45:15.561090 <4>[ 3.436948] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10733 14:45:15.600470 <6>[ 3.480259] r8152 2-1.3:1.0 eth0: v1.12.13
10734 14:45:15.638101 <6>[ 3.514626] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10735 14:45:15.829970 <6>[ 3.706638] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10736 14:45:17.192960 <6>[ 5.073014] r8152 2-1.3:1.0 eth0: carrier on
10737 14:45:17.230372 <5>[ 5.094424] Sending DHCP requests ., OK
10738 14:45:17.236863 <6>[ 5.114660] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10739 14:45:17.240686 <6>[ 5.122966] IP-Config: Complete:
10740 14:45:17.254164 <6>[ 5.126459] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10741 14:45:17.260265 <6>[ 5.137166] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10742 14:45:17.266977 <6>[ 5.145785] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10743 14:45:17.273703 <6>[ 5.145794] nameserver0=192.168.201.1
10744 14:45:17.276963 <6>[ 5.157921] clk: Disabling unused clocks
10745 14:45:17.280441 <6>[ 5.163422] ALSA device list:
10746 14:45:17.283716 <6>[ 5.166679] No soundcards found.
10747 14:45:17.294349 <6>[ 5.174193] Freeing unused kernel memory: 8512K
10748 14:45:17.297408 <6>[ 5.179198] Run /init as init process
10749 14:45:17.307798 Loading, please wait...
10750 14:45:17.333998 Starting systemd-udevd version 252.22-1~deb12u1
10751 14:45:17.629623 <6>[ 5.506398] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10752 14:45:17.642646 <6>[ 5.522347] remoteproc remoteproc0: scp is available
10753 14:45:17.649401 <6>[ 5.527809] remoteproc remoteproc0: powering up scp
10754 14:45:17.655787 <6>[ 5.533163] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10755 14:45:17.662550 <6>[ 5.541641] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10756 14:45:17.672218 <3>[ 5.548778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 14:45:17.678821 <6>[ 5.556401] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10758 14:45:17.689138 <3>[ 5.558872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 14:45:17.695474 <6>[ 5.571145] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10760 14:45:17.701902 <3>[ 5.573285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 14:45:17.712130 <4>[ 5.573483] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10762 14:45:17.719247 <4>[ 5.573620] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10763 14:45:17.729169 <6>[ 5.580518] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10764 14:45:17.732334 <6>[ 5.580866] mc: Linux media interface: v0.10
10765 14:45:17.739367 <3>[ 5.588701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 14:45:17.749173 <3>[ 5.588721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 14:45:17.756418 <3>[ 5.588728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10768 14:45:17.765647 <3>[ 5.588753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 14:45:17.772424 <3>[ 5.588757] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 14:45:17.782190 <3>[ 5.588906] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 14:45:17.789261 <3>[ 5.589005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 14:45:17.798844 <3>[ 5.589010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 14:45:17.805828 <3>[ 5.589014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 14:45:17.816034 <3>[ 5.589061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 14:45:17.822085 <6>[ 5.597207] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10776 14:45:17.832325 <3>[ 5.603668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 14:45:17.838625 <3>[ 5.603674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 14:45:17.845541 <3>[ 5.603682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 14:45:17.855476 <3>[ 5.603685] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 14:45:17.862054 <3>[ 5.603727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 14:45:17.871858 <4>[ 5.605029] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10782 14:45:17.878676 <4>[ 5.605029] Fallback method does not support PEC.
10783 14:45:17.884912 <3>[ 5.622006] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10784 14:45:17.891828 <6>[ 5.731886] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10785 14:45:17.898655 <6>[ 5.732154] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10786 14:45:17.908660 <6>[ 5.732233] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10787 14:45:17.914741 <6>[ 5.732246] remoteproc remoteproc0: remote processor scp is now up
10788 14:45:17.922127 <6>[ 5.740156] pci_bus 0000:00: root bus resource [bus 00-ff]
10789 14:45:17.928693 <6>[ 5.740162] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10790 14:45:17.938556 <6>[ 5.740168] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10791 14:45:17.944963 <6>[ 5.740203] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10792 14:45:17.951709 <6>[ 5.749751] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10793 14:45:17.965082 <6>[ 5.751794] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10794 14:45:17.971694 <6>[ 5.752291] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10795 14:45:17.981138 <6>[ 5.762061] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10796 14:45:17.988105 <6>[ 5.776708] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10797 14:45:17.991207 <6>[ 5.777768] pci 0000:00:00.0: supports D1 D2
10798 14:45:17.998040 <6>[ 5.785602] videodev: Linux video capture interface: v2.00
10799 14:45:18.007800 <6>[ 5.790054] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10800 14:45:18.014199 <6>[ 5.793236] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10801 14:45:18.021013 <3>[ 5.804056] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10802 14:45:18.030916 <6>[ 5.807069] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10803 14:45:18.034219 <6>[ 5.813547] Bluetooth: Core ver 2.22
10804 14:45:18.040546 <6>[ 5.822912] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10805 14:45:18.047107 <6>[ 5.829090] NET: Registered PF_BLUETOOTH protocol family
10806 14:45:18.053884 <6>[ 5.838332] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10807 14:45:18.060722 <6>[ 5.848378] Bluetooth: HCI device and connection manager initialized
10808 14:45:18.067289 <6>[ 5.857425] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10809 14:45:18.073839 <6>[ 5.858101] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10810 14:45:18.086937 <6>[ 5.859222] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10811 14:45:18.093680 <6>[ 5.859368] usbcore: registered new interface driver uvcvideo
10812 14:45:18.097209 <6>[ 5.864895] Bluetooth: HCI socket layer initialized
10813 14:45:18.106939 <6>[ 5.873145] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10814 14:45:18.110352 <6>[ 5.877654] Bluetooth: L2CAP socket layer initialized
10815 14:45:18.116718 <6>[ 5.883506] pci 0000:01:00.0: supports D1 D2
10816 14:45:18.120138 <6>[ 5.891654] Bluetooth: SCO socket layer initialized
10817 14:45:18.126940 <6>[ 5.898503] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10818 14:45:18.133282 <6>[ 5.908319] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10819 14:45:18.139980 <6>[ 5.953115] usbcore: registered new interface driver btusb
10820 14:45:18.149783 <4>[ 5.953845] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10821 14:45:18.156338 <3>[ 5.953856] Bluetooth: hci0: Failed to load firmware file (-2)
10822 14:45:18.163054 <3>[ 5.953860] Bluetooth: hci0: Failed to set up firmware (-2)
10823 14:45:18.172980 <4>[ 5.953865] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10824 14:45:18.179544 <6>[ 5.974498] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10825 14:45:18.186078 <6>[ 6.064559] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10826 14:45:18.196489 <6>[ 6.072637] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10827 14:45:18.202875 <6>[ 6.080636] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10828 14:45:18.212595 <6>[ 6.088639] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10829 14:45:18.219711 <6>[ 6.096642] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10830 14:45:18.226203 <6>[ 6.104643] pci 0000:00:00.0: PCI bridge to [bus 01]
10831 14:45:18.232538 <6>[ 6.109859] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10832 14:45:18.239131 <6>[ 6.117964] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10833 14:45:18.246281 <6>[ 6.124788] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10834 14:45:18.252284 <6>[ 6.131502] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10835 14:45:18.268706 <5>[ 6.145230] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10836 14:45:18.293261 <5>[ 6.169670] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10837 14:45:18.299276 <5>[ 6.177099] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10838 14:45:18.309350 <4>[ 6.185542] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10839 14:45:18.315938 <6>[ 6.194446] cfg80211: failed to load regulatory.db
10840 14:45:18.362384 <6>[ 6.238858] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10841 14:45:18.368435 <6>[ 6.246386] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10842 14:45:18.392974 <6>[ 6.273067] mt7921e 0000:01:00.0: ASIC revision: 79610010
10843 14:45:18.498429 <6>[ 6.375089] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10844 14:45:18.501510 <6>[ 6.375089]
10845 14:45:18.505268 Begin: Loading essential drivers ... done.
10846 14:45:18.511263 Begin: Running /scripts/init-premount ... done.
10847 14:45:18.517991 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10848 14:45:18.524421 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10849 14:45:18.527712 Device /sys/class/net/eth0 found
10850 14:45:18.530996 done.
10851 14:45:18.546717 Begin: Waiting up to 180 secs for any network device to become available ... done.
10852 14:45:18.598498 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10853 14:45:18.604920 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10854 14:45:18.611649 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10855 14:45:18.618350 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10856 14:45:18.624678 host : mt8192-asurada-spherion-r0-cbg-8
10857 14:45:18.631170 domain : lava-rack
10858 14:45:18.634565 rootserver: 192.168.201.1 rootpath:
10859 14:45:18.637622 filename :
10860 14:45:18.766547 <6>[ 6.643120] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10861 14:45:18.787847 done.
10862 14:45:18.795015 Begin: Running /scripts/nfs-bottom ... done.
10863 14:45:18.810164 Begin: Running /scripts/init-bottom ... done.
10864 14:45:20.111040 <6>[ 7.991274] NET: Registered PF_INET6 protocol family
10865 14:45:20.118208 <6>[ 7.998381] Segment Routing with IPv6
10866 14:45:20.121469 <6>[ 8.002321] In-situ OAM (IOAM) with IPv6
10867 14:45:20.291462 <30>[ 8.145241] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10868 14:45:20.297874 <30>[ 8.178366] systemd[1]: Detected architecture arm64.
10869 14:45:20.307704
10870 14:45:20.310997 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10871 14:45:20.311103
10872 14:45:20.339894 <30>[ 8.220133] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10873 14:45:21.446540 <30>[ 9.323665] systemd[1]: Queued start job for default target graphical.target.
10874 14:45:21.490617 <30>[ 9.367909] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10875 14:45:21.497382 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10876 14:45:21.519049 <30>[ 9.396342] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10877 14:45:21.528899 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10878 14:45:21.547312 <30>[ 9.424373] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10879 14:45:21.557013 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10880 14:45:21.574723 <30>[ 9.452031] systemd[1]: Created slice user.slice - User and Session Slice.
10881 14:45:21.581498 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10882 14:45:21.605031 <30>[ 9.478911] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10883 14:45:21.612018 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10884 14:45:21.632789 <30>[ 9.506859] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10885 14:45:21.639920 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10886 14:45:21.668346 <30>[ 9.535280] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10887 14:45:21.678294 <30>[ 9.555192] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10888 14:45:21.684502 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10889 14:45:21.701563 <30>[ 9.578597] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10890 14:45:21.708218 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10891 14:45:21.725608 <30>[ 9.602662] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10892 14:45:21.735825 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10893 14:45:21.750023 <30>[ 9.630712] systemd[1]: Reached target paths.target - Path Units.
10894 14:45:21.760389 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10895 14:45:21.777809 <30>[ 9.655049] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10896 14:45:21.784823 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10897 14:45:21.798027 <30>[ 9.678592] systemd[1]: Reached target slices.target - Slice Units.
10898 14:45:21.808440 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10899 14:45:21.822503 <30>[ 9.703079] systemd[1]: Reached target swap.target - Swaps.
10900 14:45:21.829466 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10901 14:45:21.849662 <30>[ 9.727095] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10902 14:45:21.860124 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10903 14:45:21.877716 <30>[ 9.755102] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10904 14:45:21.887886 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10905 14:45:21.908770 <30>[ 9.786037] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10906 14:45:21.918736 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10907 14:45:21.935015 <30>[ 9.812093] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10908 14:45:21.944805 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10909 14:45:21.961918 <30>[ 9.839266] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10910 14:45:21.968763 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10911 14:45:21.986817 <30>[ 9.864164] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10912 14:45:21.996858 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10913 14:45:22.016376 <30>[ 9.893641] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10914 14:45:22.026152 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10915 14:45:22.041863 <30>[ 9.919079] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10916 14:45:22.051599 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10917 14:45:22.093774 <30>[ 9.971119] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10918 14:45:22.100362 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10919 14:45:22.120542 <30>[ 9.998007] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10920 14:45:22.127240 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10921 14:45:22.148689 <30>[ 10.025793] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10922 14:45:22.154835 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10923 14:45:22.180657 <30>[ 10.051094] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10924 14:45:22.218319 <30>[ 10.095411] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10925 14:45:22.228187 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10926 14:45:22.251156 <30>[ 10.128516] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10927 14:45:22.258321 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10928 14:45:22.283725 <30>[ 10.160685] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10929 14:45:22.290311 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10930 14:45:22.315127 <30>[ 10.192441] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10931 14:45:22.328521 Starting [0;1;39mmodprobe@drm.service<6>[ 10.204225] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10932 14:45:22.331824 [0m - Load Kernel Module drm...
10933 14:45:22.370739 <30>[ 10.247595] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10934 14:45:22.379978 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10935 14:45:22.403459 <30>[ 10.280693] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10936 14:45:22.410020 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10937 14:45:22.435132 <30>[ 10.312326] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10938 14:45:22.441423 Starting [0;1;39mmodpr<6>[ 10.322377] fuse: init (API version 7.37)
10939 14:45:22.448342 obe@loop.ser…e[0m - Load Kernel Module loop...
10940 14:45:22.490345 <30>[ 10.367491] systemd[1]: Starting systemd-journald.service - Journal Service...
10941 14:45:22.497015 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10942 14:45:22.529590 <30>[ 10.407007] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10943 14:45:22.536096 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10944 14:45:22.565076 <30>[ 10.439059] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10945 14:45:22.571532 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10946 14:45:22.606439 <30>[ 10.483846] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10947 14:45:22.616325 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10948 14:45:22.639539 <30>[ 10.516851] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10949 14:45:22.645993 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10950 14:45:22.660100 <3>[ 10.537268] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 14:45:22.673420 <30>[ 10.551006] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10952 14:45:22.679950 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10953 14:45:22.695644 <3>[ 10.572984] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 14:45:22.705471 <30>[ 10.582695] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10955 14:45:22.712449 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10956 14:45:22.730336 <30>[ 10.607325] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10957 14:45:22.740479 [[0;32m OK [<3>[ 10.616162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 14:45:22.746947 0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10959 14:45:22.766940 <30>[ 10.643978] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10960 14:45:22.780721 [[0;32m OK [0m] Finished [0;1;39mkmod-stati<3>[ 10.657006] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 14:45:22.784423 c-nodes…reate List of Static Device Nodes.
10962 14:45:22.805565 <30>[ 10.682322] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10963 14:45:22.812514 <30>[ 10.690488] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10964 14:45:22.825511 [[0;32m OK [0m] Finished [0<3>[ 10.701679] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 14:45:22.832092 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10966 14:45:22.855215 <30>[ 10.732010] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10967 14:45:22.861420 <3>[ 10.733003] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 14:45:22.871494 <30>[ 10.740210] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10969 14:45:22.878575 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10970 14:45:22.893722 <3>[ 10.771104] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 14:45:22.904601 <30>[ 10.781978] systemd[1]: modprobe@drm.service: Deactivated successfully.
10972 14:45:22.911224 <30>[ 10.789839] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10973 14:45:22.928091 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m -<3>[ 10.803209] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 14:45:22.928207 Load Kernel Module drm.
10975 14:45:22.947471 <30>[ 10.824378] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10976 14:45:22.954205 <30>[ 10.832520] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10977 14:45:22.964082 <3>[ 10.833163] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 14:45:22.974313 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10979 14:45:22.991528 <30>[ 10.868550] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10980 14:45:22.998443 <3>[ 10.871844] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 14:45:23.008299 <30>[ 10.876626] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10982 14:45:23.014810 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10983 14:45:23.030379 <3>[ 10.907708] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 14:45:23.041359 <30>[ 10.918753] systemd[1]: modprobe@loop.service: Deactivated successfully.
10985 14:45:23.047937 <30>[ 10.926430] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10986 14:45:23.057937 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10987 14:45:23.072164 <3>[ 10.949011] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 14:45:23.082003 <3>[ 10.951504] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10989 14:45:23.095864 <4>[ 10.966066] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10990 14:45:23.105539 <30>[ 10.967573] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10991 14:45:23.113233 <3>[ 10.981699] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10992 14:45:23.119869 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10993 14:45:23.142898 <30>[ 11.016207] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10994 14:45:23.149415 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10995 14:45:23.165566 <30>[ 11.042869] systemd[1]: Started systemd-journald.service - Journal Service.
10996 14:45:23.172553 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10997 14:45:23.193084 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10998 14:45:23.210684 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10999 14:45:23.232232 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11000 14:45:23.281973 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11001 14:45:23.306757 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11002 14:45:23.354380 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11003 14:45:23.377919 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11004 14:45:23.402157 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11005 14:45:23.434407 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users..<46>[ 11.310822] systemd-journald[309]: Received client request to flush runtime journal.
11006 14:45:23.434585 .
11007 14:45:23.467864 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11008 14:45:23.486922 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11009 14:45:23.506644 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11010 14:45:23.526293 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11011 14:45:24.226296 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11012 14:45:24.298632 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11013 14:45:24.887649 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11014 14:45:24.944976 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11015 14:45:24.961752 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11016 14:45:24.977363 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11017 14:45:25.026235 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11018 14:45:25.049940 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11019 14:45:25.268230 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11020 14:45:25.342713 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11021 14:45:25.413042 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11022 14:45:25.707575 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11023 14:45:25.741516 <6>[ 13.622541] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11024 14:45:25.763094 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11025 14:45:25.785244 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11026 14:45:25.809509 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11027 14:45:25.922056 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11028 14:45:25.946171 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11029 14:45:25.976507 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11030 14:45:26.032445 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11031 14:45:26.057083 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11032 14:45:26.080525 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11033 14:45:26.131268 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11034 14:45:26.152451 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11035 14:45:26.176678 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11036 14:45:26.193977 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11037 14:45:26.215925 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11038 14:45:26.233932 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11039 14:45:26.254291 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11040 14:45:26.304629 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11041 14:45:26.325177 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11042 14:45:26.342149 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11043 14:45:26.364677 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11044 14:45:26.384103 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11045 14:45:26.403233 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11046 14:45:26.421105 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11047 14:45:26.438190 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11048 14:45:26.444736 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11049 14:45:26.497976 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11050 14:45:26.535560 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11051 14:45:26.639308 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11052 14:45:26.664489 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11053 14:45:26.701736 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11054 14:45:26.749554 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11055 14:45:26.768766 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11056 14:45:26.787231 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11057 14:45:26.807009 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11058 14:45:26.942905 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11059 14:45:26.995104 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11060 14:45:27.020381 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11061 14:45:27.038466 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11062 14:45:27.078163 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11063 14:45:27.132330 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11064 14:45:27.223986
11065 14:45:27.227058 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11066 14:45:27.227233
11067 14:45:27.230278 debian-bookworm-arm64 login: root (automatic login)
11068 14:45:27.230362
11069 14:45:27.562637 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue Jun 4 14:26:14 UTC 2024 aarch64
11070 14:45:27.562775
11071 14:45:27.569201 The programs included with the Debian GNU/Linux system are free software;
11072 14:45:27.575987 the exact distribution terms for each program are described in the
11073 14:45:27.579345 individual files in /usr/share/doc/*/copyright.
11074 14:45:27.579433
11075 14:45:27.585868 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11076 14:45:27.589198 permitted by applicable law.
11077 14:45:28.677970 Matched prompt #10: / #
11079 14:45:28.678295 Setting prompt string to ['/ #']
11080 14:45:28.678394 end: 2.2.5.1 login-action (duration 00:00:17) [common]
11082 14:45:28.678607 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
11083 14:45:28.678701 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
11084 14:45:28.678773 Setting prompt string to ['/ #']
11085 14:45:28.678835 Forcing a shell prompt, looking for ['/ #']
11087 14:45:28.729066 / #
11088 14:45:28.729274 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11089 14:45:28.729376 Waiting using forced prompt support (timeout 00:02:30)
11090 14:45:28.734416
11091 14:45:28.734698 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11092 14:45:28.734791 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
11094 14:45:28.835154 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14166992/extract-nfsrootfs-r1s09h8d'
11095 14:45:28.840154 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14166992/extract-nfsrootfs-r1s09h8d'
11097 14:45:28.940691 / # export NFS_SERVER_IP='192.168.201.1'
11098 14:45:28.945845 export NFS_SERVER_IP='192.168.201.1'
11099 14:45:28.946159 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11100 14:45:28.946272 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
11101 14:45:28.946379 end: 2 depthcharge-action (duration 00:01:34) [common]
11102 14:45:28.946485 start: 3 lava-test-retry (timeout 00:07:40) [common]
11103 14:45:28.946588 start: 3.1 lava-test-shell (timeout 00:07:40) [common]
11104 14:45:28.946677 Using namespace: common
11106 14:45:29.047043 / # #
11107 14:45:29.047203 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11108 14:45:29.052335 #
11109 14:45:29.052609 Using /lava-14166992
11111 14:45:29.152999 / # export SHELL=/bin/bash
11112 14:45:29.158398 export SHELL=/bin/bash
11114 14:45:29.259043 / # . /lava-14166992/environment
11115 14:45:29.264464 . /lava-14166992/environment
11117 14:45:29.370662 / # /lava-14166992/bin/lava-test-runner /lava-14166992/0
11118 14:45:29.370903 Test shell timeout: 10s (minimum of the action and connection timeout)
11119 14:45:29.376460 /lava-14166992/bin/lava-test-runner /lava-14166992/0
11120 14:45:29.661513 + export TESTRUN_ID=0_timesync-off
11121 14:45:29.664810 + TESTRUN_ID=0_timesync-off
11122 14:45:29.668198 + cd /lava-14166992/0/tests/0_timesync-off
11123 14:45:29.670981 ++ cat uuid
11124 14:45:29.676819 + UUID=14166992_1.6.2.3.1
11125 14:45:29.676902 + set +x
11126 14:45:29.683454 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14166992_1.6.2.3.1>
11127 14:45:29.683740 Received signal: <STARTRUN> 0_timesync-off 14166992_1.6.2.3.1
11128 14:45:29.683816 Starting test lava.0_timesync-off (14166992_1.6.2.3.1)
11129 14:45:29.683900 Skipping test definition patterns.
11130 14:45:29.686802 + systemctl stop systemd-timesyncd
11131 14:45:29.763583 + set +x
11132 14:45:29.766562 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14166992_1.6.2.3.1>
11133 14:45:29.766848 Received signal: <ENDRUN> 0_timesync-off 14166992_1.6.2.3.1
11134 14:45:29.766934 Ending use of test pattern.
11135 14:45:29.767027 Ending test lava.0_timesync-off (14166992_1.6.2.3.1), duration 0.08
11137 14:45:29.845123 + export TESTRUN_ID=1_kselftest-rtc
11138 14:45:29.848475 + TESTRUN_ID=1_kselftest-rtc
11139 14:45:29.851574 + cd /lava-14166992/0/tests/1_kselftest-rtc
11140 14:45:29.854842 ++ cat uuid
11141 14:45:29.858547 + UUID=14166992_1.6.2.3.5
11142 14:45:29.858662 + set +x
11143 14:45:29.865384 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14166992_1.6.2.3.5>
11144 14:45:29.865691 Received signal: <STARTRUN> 1_kselftest-rtc 14166992_1.6.2.3.5
11145 14:45:29.865797 Starting test lava.1_kselftest-rtc (14166992_1.6.2.3.5)
11146 14:45:29.865913 Skipping test definition patterns.
11147 14:45:29.868415 + cd ./automated/linux/kselftest/
11148 14:45:29.894785 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11149 14:45:29.936934 INFO: install_deps skipped
11150 14:45:30.446087 --2024-06-04 14:45:30-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21-33-g2e011af54960c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11151 14:45:30.459486 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11152 14:45:30.591046 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11153 14:45:30.720525 HTTP request sent, awaiting response... 200 OK
11154 14:45:30.723872 Length: 1647736 (1.6M) [application/octet-stream]
11155 14:45:30.726900 Saving to: 'kselftest_armhf.tar.gz'
11156 14:45:30.726975
11157 14:45:30.727041
11158 14:45:30.980421 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11159 14:45:31.237954 kselftest_armhf.tar 2%[ ] 47.81K 180KB/s
11160 14:45:31.529375 kselftest_armhf.tar 13%[=> ] 217.50K 411KB/s
11161 14:45:31.757455 kselftest_armhf.tar 38%[======> ] 624.26K 755KB/s
11162 14:45:31.763882 kselftest_armhf.tar 89%[================> ] 1.40M 1.32MB/s
11163 14:45:31.770539 kselftest_armhf.tar 100%[===================>] 1.57M 1.48MB/s in 1.1s
11164 14:45:31.770678
11165 14:45:31.913137 2024-06-04 14:45:31 (1.48 MB/s) - 'kselftest_armhf.tar.gz' saved [1647736/1647736]
11166 14:45:31.913290
11167 14:45:37.021039 skiplist:
11168 14:45:37.024444 ========================================
11169 14:45:37.027830 ========================================
11170 14:45:37.083773 rtc:rtctest
11171 14:45:37.105820 ============== Tests to run ===============
11172 14:45:37.105956 rtc:rtctest
11173 14:45:37.111937 ===========End Tests to run ===============
11174 14:45:37.116020 shardfile-rtc pass
11175 14:45:37.226629 <12>[ 25.108917] kselftest: Running tests in rtc
11176 14:45:37.236116 TAP version 13
11177 14:45:37.250946 1..1
11178 14:45:37.283150 # selftests: rtc: rtctest
11179 14:45:37.754566 # TAP version 13
11180 14:45:37.754699 # 1..8
11181 14:45:37.757787 # # Starting 8 tests from 2 test cases.
11182 14:45:37.761111 # # RUN rtc.date_read ...
11183 14:45:37.767618 # # rtctest.c:49:date_read:Current RTC date/time is 04/06/2024 14:45:37.
11184 14:45:37.771079 # # OK rtc.date_read
11185 14:45:37.774490 # ok 1 rtc.date_read
11186 14:45:37.777956 # # RUN rtc.date_read_loop ...
11187 14:45:37.787494 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11188 14:45:47.722705 <6>[ 35.609169] vpu: disabling
11189 14:45:47.725896 <6>[ 35.612273] vproc2: disabling
11190 14:45:47.729168 <6>[ 35.615598] vproc1: disabling
11191 14:45:47.732471 <6>[ 35.618930] vaud18: disabling
11192 14:45:47.738854 <6>[ 35.622438] vsram_others: disabling
11193 14:45:47.742061 <6>[ 35.626431] va09: disabling
11194 14:45:47.745450 <6>[ 35.629599] vsram_md: disabling
11195 14:45:47.748541 <6>[ 35.633164] Vgpu: disabling
11196 14:46:08.309474 # # rtctest.c:115:date_read_loop:Performed 2685 RTC time reads.
11197 14:46:08.312805 # # OK rtc.date_read_loop
11198 14:46:08.316240 # ok 2 rtc.date_read_loop
11199 14:46:08.319759 # # RUN rtc.uie_read ...
11200 14:46:11.292019 # # OK rtc.uie_read
11201 14:46:11.294952 # ok 3 rtc.uie_read
11202 14:46:11.298064 # # RUN rtc.uie_select ...
11203 14:46:14.291598 # # OK rtc.uie_select
11204 14:46:14.294945 # ok 4 rtc.uie_select
11205 14:46:14.297853 # # RUN rtc.alarm_alm_set ...
11206 14:46:14.304709 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 14:46:17.
11207 14:46:14.308054 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11208 14:46:14.314931 # # alarm_alm_set: Test terminated by assertion
11209 14:46:14.317709 # # FAIL rtc.alarm_alm_set
11210 14:46:14.321558 # not ok 5 rtc.alarm_alm_set
11211 14:46:14.324596 # # RUN rtc.alarm_wkalm_set ...
11212 14:46:14.330857 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 04/06/2024 14:46:17.
11213 14:46:17.293926 # # OK rtc.alarm_wkalm_set
11214 14:46:17.294086 # ok 6 rtc.alarm_wkalm_set
11215 14:46:17.300341 # # RUN rtc.alarm_alm_set_minute ...
11216 14:46:17.303924 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 14:47:00.
11217 14:46:17.310421 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11218 14:46:17.316935 # # alarm_alm_set_minute: Test terminated by assertion
11219 14:46:17.320308 # # FAIL rtc.alarm_alm_set_minute
11220 14:46:17.323377 # not ok 7 rtc.alarm_alm_set_minute
11221 14:46:17.326703 # # RUN rtc.alarm_wkalm_set_minute ...
11222 14:46:17.333656 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 04/06/2024 14:47:00.
11223 14:47:00.289784 # # OK rtc.alarm_wkalm_set_minute
11224 14:47:00.292190 # ok 8 rtc.alarm_wkalm_set_minute
11225 14:47:00.295720 # # FAILED: 6 / 8 tests passed.
11226 14:47:00.299390 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11227 14:47:00.302626 not ok 1 selftests: rtc: rtctest # exit=1
11228 14:47:01.820628 rtc_rtctest_rtc_date_read pass
11229 14:47:01.823886 rtc_rtctest_rtc_date_read_loop pass
11230 14:47:01.827550 rtc_rtctest_rtc_uie_read pass
11231 14:47:01.830785 rtc_rtctest_rtc_uie_select pass
11232 14:47:01.833933 rtc_rtctest_rtc_alarm_alm_set fail
11233 14:47:01.837565 rtc_rtctest_rtc_alarm_wkalm_set pass
11234 14:47:01.840657 rtc_rtctest_rtc_alarm_alm_set_minute fail
11235 14:47:01.844136 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11236 14:47:01.847098 rtc_rtctest fail
11237 14:47:01.897087 + ../../utils/send-to-lava.sh ./output/result.txt
11238 14:47:01.984520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11239 14:47:01.984872 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11241 14:47:02.041088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11242 14:47:02.041408 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11244 14:47:02.100450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11245 14:47:02.100882 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11247 14:47:02.152568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11248 14:47:02.153023 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11250 14:47:02.216833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11251 14:47:02.217188 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11253 14:47:02.278212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11254 14:47:02.278542 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11256 14:47:02.335294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11257 14:47:02.335619 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11259 14:47:02.392671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11260 14:47:02.392984 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11262 14:47:02.448375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11263 14:47:02.448789 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11265 14:47:02.498878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11266 14:47:02.499082 + set +x
11267 14:47:02.499383 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11269 14:47:02.504799 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14166992_1.6.2.3.5>
11270 14:47:02.505101 Received signal: <ENDRUN> 1_kselftest-rtc 14166992_1.6.2.3.5
11271 14:47:02.505222 Ending use of test pattern.
11272 14:47:02.505335 Ending test lava.1_kselftest-rtc (14166992_1.6.2.3.5), duration 92.64
11274 14:47:02.505731 ok: lava_test_shell seems to have completed
11275 14:47:02.505980 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11276 14:47:02.506139 end: 3.1 lava-test-shell (duration 00:01:34) [common]
11277 14:47:02.506297 end: 3 lava-test-retry (duration 00:01:34) [common]
11278 14:47:02.506458 start: 4 finalize (timeout 00:06:06) [common]
11279 14:47:02.506606 start: 4.1 power-off (timeout 00:00:30) [common]
11280 14:47:02.506885 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11281 14:47:02.583727 >> Command sent successfully.
11282 14:47:02.586143 Returned 0 in 0 seconds
11283 14:47:02.686496 end: 4.1 power-off (duration 00:00:00) [common]
11285 14:47:02.686863 start: 4.2 read-feedback (timeout 00:06:06) [common]
11287 14:47:02.687404 Listened to connection for namespace 'common' for up to 1s
11288 14:47:03.688080 Finalising connection for namespace 'common'
11289 14:47:03.688259 Disconnecting from shell: Finalise
11290 14:47:03.688335 / #
11291 14:47:03.788659 end: 4.2 read-feedback (duration 00:00:01) [common]
11292 14:47:03.788861 end: 4 finalize (duration 00:00:01) [common]
11293 14:47:03.789012 Cleaning after the job
11294 14:47:03.789147 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/ramdisk
11295 14:47:03.791956 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/kernel
11296 14:47:03.805899 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/dtb
11297 14:47:03.806149 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/nfsrootfs
11298 14:47:03.882659 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14166992/tftp-deploy-2kidynw7/modules
11299 14:47:03.888518 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14166992
11300 14:47:04.463924 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14166992
11301 14:47:04.464107 Job finished correctly